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//======================================================================
//
// aes.v
// --------
// Top level wrapper for the AES block cipher core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, 2014 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module aes(
// Clock and reset.
input wire clk,
input wire reset_n,
// Control.
input wire cs,
input wire we,
// Data ports.
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam STATUS_VALID_BIT = 1;
localparam ADDR_CONFIG = 8'h0a;
localparam CTRL_ENCDEC_BIT = 0;
localparam CTRL_KEYLEN_BIT = 1;
localparam ADDR_KEY0 = 8'h10;
localparam ADDR_KEY7 = 8'h17;
localparam ADDR_BLOCK0 = 8'h20;
localparam ADDR_BLOCK3 = 8'h23;
localparam ADDR_RESULT0 = 8'h30;
localparam ADDR_RESULT3 = 8'h33;
localparam CORE_NAME0 = 32'h61657320; // "aes "
localparam CORE_NAME1 = 32'h20202020; // " "
localparam CORE_VERSION = 32'h302e3630; // "0.60"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg init_reg;
reg init_new;
reg next_reg;
reg next_new;
reg encdec_reg;
reg keylen_reg;
reg config_we;
reg [31 : 0] block_reg [0 : 3];
reg block_we;
reg [31 : 0] key_reg [0 : 7];
reg key_we;
reg [127 : 0] result_reg;
reg valid_reg;
reg ready_reg;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_read_data;
wire core_encdec;
wire core_init;
wire core_next;
wire core_ready;
wire [255 : 0] core_key;
wire core_keylen;
wire [127 : 0] core_block;
wire [127 : 0] core_result;
wire core_valid;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
assign core_key = {key_reg[0], key_reg[1], key_reg[2], key_reg[3],
key_reg[4], key_reg[5], key_reg[6], key_reg[7]};
assign core_block = {block_reg[0], block_reg[1],
block_reg[2], block_reg[3]};
assign core_init = init_reg;
assign core_next = next_reg;
assign core_encdec = encdec_reg;
assign core_keylen = keylen_reg;
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
aes_core core(
.clk(clk),
.reset_n(reset_n),
.encdec(core_encdec),
.init(core_init),
.next(core_next),
.ready(core_ready),
.key(core_key),
.keylen(core_keylen),
.block(core_block),
.result(core_result),
.result_valid(core_valid)
);
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
integer i;
if (!reset_n)
begin
for (i = 0 ; i < 4 ; i = i + 1)
block_reg[i] <= 32'h0;
for (i = 0 ; i < 8 ; i = i + 1)
key_reg[i] <= 32'h0;
init_reg <= 1'b0;
next_reg <= 1'b0;
encdec_reg <= 1'b0;
keylen_reg <= 1'b0;
result_reg <= 128'h0;
valid_reg <= 1'b0;
ready_reg <= 1'b0;
end
else
begin
ready_reg <= core_ready;
valid_reg <= core_valid;
result_reg <= core_result;
init_reg <= init_new;
next_reg <= next_new;
if (config_we)
begin
encdec_reg <= write_data[CTRL_ENCDEC_BIT];
keylen_reg <= write_data[CTRL_KEYLEN_BIT];
end
if (key_we)
key_reg[address[2 : 0]] <= write_data;
if (block_we)
block_reg[address[1 : 0]] <= write_data;
end
end // reg_update
//----------------------------------------------------------------
// api
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
init_new = 1'b0;
next_new = 1'b0;
config_we = 1'b0;
key_we = 1'b0;
block_we = 1'b0;
tmp_read_data = 32'h0;
if (cs)
begin
if (we)
begin
if (address == ADDR_CTRL)
begin
init_new = write_data[CTRL_INIT_BIT];
next_new = write_data[CTRL_NEXT_BIT];
end
if (address == ADDR_CONFIG)
config_we = 1'b1;
if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
key_we = 1'b1;
if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3))
block_we = 1'b1;
end // if (we)
else
begin
case (address)
ADDR_NAME0: tmp_read_data = CORE_NAME0;
ADDR_NAME1: tmp_read_data = CORE_NAME1;
ADDR_VERSION: tmp_read_data = CORE_VERSION;
ADDR_CTRL: tmp_read_data = {28'h0, keylen_reg, encdec_reg, next_reg, init_reg};
ADDR_STATUS: tmp_read_data = {30'h0, valid_reg, ready_reg};
default:
begin
end
endcase // case (address)
if ((address >= ADDR_RESULT0) && (address <= ADDR_RESULT3))
tmp_read_data = result_reg[(3 - (address - ADDR_RESULT0)) * 32 +: 32];
end
end
end // addr_decoder
endmodule // aes
//======================================================================
// EOF aes.v
//======================================================================
//======================================================================
//
// aes.core.v
// ----------
// The AES core. This core supports key size of 128, and 256 bits.
// Most of the functionality is within the submodules.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module aes_core(
input wire clk,
input wire reset_n,
input wire encdec,
input wire init,
input wire next,
output wire ready,
input wire [255 : 0] key,
input wire keylen,
input wire [127 : 0] block,
output wire [127 : 0] result,
output wire result_valid
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam CTRL_IDLE = 2'h0;
localparam CTRL_INIT = 2'h1;
localparam CTRL_NEXT = 2'h2;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [1 : 0] aes_core_ctrl_reg;
reg [1 : 0] aes_core_ctrl_new;
reg aes_core_ctrl_we;
reg result_valid_reg;
reg result_valid_new;
reg result_valid_we;
reg ready_reg;
reg ready_new;
reg ready_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg init_state;
wire [127 : 0] round_key;
wire key_ready;
reg enc_next;
wire [3 : 0] enc_round_nr;
wire [127 : 0] enc_new_block;
wire enc_ready;
wire [31 : 0] enc_sboxw;
reg dec_next;
wire [3 : 0] dec_round_nr;
wire [127 : 0] dec_new_block;
wire dec_ready;
reg [127 : 0] muxed_new_block;
reg [3 : 0] muxed_round_nr;
reg muxed_ready;
wire [31 : 0] keymem_sboxw;
reg [31 : 0] muxed_sboxw;
wire [31 : 0] new_sboxw;
//----------------------------------------------------------------
// Instantiations.
//----------------------------------------------------------------
aes_encipher_block enc_block(
.clk(clk),
.reset_n(reset_n),
.next(enc_next),
.keylen(keylen),
.round(enc_round_nr),
.round_key(round_key),
.sboxw(enc_sboxw),
.new_sboxw(new_sboxw),
.block(block),
.new_block(enc_new_block),
.ready(enc_ready)
);
aes_decipher_block dec_block(
.clk(clk),
.reset_n(reset_n),
.next(dec_next),
.keylen(keylen),
.round(dec_round_nr),
.round_key(round_key),
.block(block),
.new_block(dec_new_block),
.ready(dec_ready)
);
aes_key_mem keymem(
.clk(clk),
.reset_n(reset_n),
.key(key),
.keylen(keylen),
.init(init),
.round(muxed_round_nr),
.round_key(round_key),
.ready(key_ready),
.sboxw(keymem_sboxw),
.new_sboxw(new_sboxw)
);
aes_sbox sbox_inst(.sboxw(muxed_sboxw), .new_sboxw(new_sboxw));
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign ready = ready_reg;
assign result = muxed_new_block;
assign result_valid = result_valid_reg;
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin: reg_update
if (!reset_n)
begin
result_valid_reg <= 1'b0;
ready_reg <= 1'b1;
aes_core_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (result_valid_we)
result_valid_reg <= result_valid_new;
if (ready_we)
ready_reg <= ready_new;
if (aes_core_ctrl_we)
aes_core_ctrl_reg <= aes_core_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// sbox_mux
//
// Controls which of the encipher datapath or the key memory
// that gets access to the sbox.
//----------------------------------------------------------------
always @*
begin : sbox_mux
if (init_state)
begin
muxed_sboxw = keymem_sboxw;
end
else
begin
muxed_sboxw = enc_sboxw;
end
end // sbox_mux
//----------------------------------------------------------------
// encdex_mux
//
// Controls which of the datapaths that get the next signal, have
// access to the memory as well as the block processing result.
//----------------------------------------------------------------
always @*
begin : encdec_mux
enc_next = 1'b0;
dec_next = 1'b0;
if (encdec)
begin
// Encipher operations
enc_next = next;
muxed_round_nr = enc_round_nr;
muxed_new_block = enc_new_block;
muxed_ready = enc_ready;
end
else
begin
// Decipher operations
dec_next = next;
muxed_round_nr = dec_round_nr;
muxed_new_block = dec_new_block;
muxed_ready = dec_ready;
end
end // encdec_mux
//----------------------------------------------------------------
// aes_core_ctrl
//
// Control FSM for aes core. Basically tracks if we are in
// key init, encipher or decipher modes and connects the
// different submodules to shared resources and interface ports.
//----------------------------------------------------------------
always @*
begin : aes_core_ctrl
init_state = 1'b0;
ready_new = 1'b0;
ready_we = 1'b0;
result_valid_new = 1'b0;
result_valid_we = 1'b0;
aes_core_ctrl_new = CTRL_IDLE;
aes_core_ctrl_we = 1'b0;
case (aes_core_ctrl_reg)
CTRL_IDLE:
begin
if (init)
begin
init_state = 1'b1;
ready_new = 1'b0;
ready_we = 1'b1;
result_valid_new = 1'b0;
result_valid_we = 1'b1;
aes_core_ctrl_new = CTRL_INIT;
aes_core_ctrl_we = 1'b1;
end
else if (next)
begin
init_state = 1'b0;
ready_new = 1'b0;
ready_we = 1'b1;
result_valid_new = 1'b0;
result_valid_we = 1'b1;
aes_core_ctrl_new = CTRL_NEXT;
aes_core_ctrl_we = 1'b1;
end
end
CTRL_INIT:
begin
init_state = 1'b1;
if (key_ready)
begin
ready_new = 1'b1;
ready_we = 1'b1;
aes_core_ctrl_new = CTRL_IDLE;
aes_core_ctrl_we = 1'b1;
end
end
CTRL_NEXT:
begin
init_state = 1'b0;
if (muxed_ready)
begin
ready_new = 1'b1;
ready_we = 1'b1;
result_valid_new = 1'b1;
result_valid_we = 1'b1;
aes_core_ctrl_new = CTRL_IDLE;
aes_core_ctrl_we = 1'b1;
end
end
default:
begin
end
endcase // case (aes_core_ctrl_reg)
end // aes_core_ctrl
endmodule // aes_core
//======================================================================
// EOF aes_core.v
//======================================================================
//======================================================================
//
// aes_decipher_block.v
// --------------------
// The AES decipher round. A pure combinational module that implements
// the initial round, main round and final round logic for
// decciper operations.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module aes_decipher_block(
input wire clk,
input wire reset_n,
input wire next,
input wire keylen,
output wire [3 : 0] round,
input wire [127 : 0] round_key,
input wire [127 : 0] block,
output wire [127 : 0] new_block,
output wire ready
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam AES_128_BIT_KEY = 1'h0;
localparam AES_256_BIT_KEY = 1'h1;
localparam AES128_ROUNDS = 4'ha;
localparam AES256_ROUNDS = 4'he;
localparam NO_UPDATE = 3'h0;
localparam INIT_UPDATE = 3'h1;
localparam SBOX_UPDATE = 3'h2;
localparam MAIN_UPDATE = 3'h3;
localparam FINAL_UPDATE = 3'h4;
localparam CTRL_IDLE = 3'h0;
localparam CTRL_INIT = 3'h1;
localparam CTRL_SBOX = 3'h2;
localparam CTRL_MAIN = 3'h3;
localparam CTRL_FINAL = 3'h4;
//----------------------------------------------------------------
// Gaolis multiplication functions for Inverse MixColumn.
//----------------------------------------------------------------
function [7 : 0] gm2(input [7 : 0] op);
begin
gm2 = {op[6 : 0], 1'b0} ^ (8'h1b & {8{op[7]}});
end
endfunction // gm2
function [7 : 0] gm3(input [7 : 0] op);
begin
gm3 = gm2(op) ^ op;
end
endfunction // gm3
function [7 : 0] gm4(input [7 : 0] op);
begin
gm4 = gm2(gm2(op));
end
endfunction // gm4
function [7 : 0] gm8(input [7 : 0] op);
begin
gm8 = gm2(gm4(op));
end
endfunction // gm8
function [7 : 0] gm09(input [7 : 0] op);
begin
gm09 = gm8(op) ^ op;
end
endfunction // gm09
function [7 : 0] gm11(input [7 : 0] op);
begin
gm11 = gm8(op) ^ gm2(op) ^ op;
end
endfunction // gm11
function [7 : 0] gm13(input [7 : 0] op);
begin
gm13 = gm8(op) ^ gm4(op) ^ op;
end
endfunction // gm13
function [7 : 0] gm14(input [7 : 0] op);
begin
gm14 = gm8(op) ^ gm4(op) ^ gm2(op);
end
endfunction // gm14
function [31 : 0] inv_mixw(input [31 : 0] w);
reg [7 : 0] b0, b1, b2, b3;
reg [7 : 0] mb0, mb1, mb2, mb3;
begin
b0 = w[31 : 24];
b1 = w[23 : 16];
b2 = w[15 : 08];
b3 = w[07 : 00];
mb0 = gm14(b0) ^ gm11(b1) ^ gm13(b2) ^ gm09(b3);
mb1 = gm09(b0) ^ gm14(b1) ^ gm11(b2) ^ gm13(b3);
mb2 = gm13(b0) ^ gm09(b1) ^ gm14(b2) ^ gm11(b3);
mb3 = gm11(b0) ^ gm13(b1) ^ gm09(b2) ^ gm14(b3);
inv_mixw = {mb0, mb1, mb2, mb3};
end
endfunction // mixw
function [127 : 0] inv_mixcolumns(input [127 : 0] data);
reg [31 : 0] w0, w1, w2, w3;
reg [31 : 0] ws0, ws1, ws2, ws3;
begin
w0 = data[127 : 096];
w1 = data[095 : 064];
w2 = data[063 : 032];
w3 = data[031 : 000];
ws0 = inv_mixw(w0);
ws1 = inv_mixw(w1);
ws2 = inv_mixw(w2);
ws3 = inv_mixw(w3);
inv_mixcolumns = {ws0, ws1, ws2, ws3};
end
endfunction // inv_mixcolumns
function [127 : 0] inv_shiftrows(input [127 : 0] data);
reg [31 : 0] w0, w1, w2, w3;
reg [31 : 0] ws0, ws1, ws2, ws3;
begin
w0 = data[127 : 096];
w1 = data[095 : 064];
w2 = data[063 : 032];
w3 = data[031 : 000];
ws0 = {w0[31 : 24], w3[23 : 16], w2[15 : 08], w1[07 : 00]};
ws1 = {w1[31 : 24], w0[23 : 16], w3[15 : 08], w2[07 : 00]};
ws2 = {w2[31 : 24], w1[23 : 16], w0[15 : 08], w3[07 : 00]};
ws3 = {w3[31 : 24], w2[23 : 16], w1[15 : 08], w0[07 : 00]};
inv_shiftrows = {ws0, ws1, ws2, ws3};
end
endfunction // inv_shiftrows
function [127 : 0] addroundkey(input [127 : 0] data, input [127 : 0] rkey);
begin
addroundkey = data ^ rkey;
end
endfunction // addroundkey
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [1 : 0] sword_ctr_reg;
reg [1 : 0] sword_ctr_new;
reg sword_ctr_we;
reg sword_ctr_inc;
reg sword_ctr_rst;
reg [3 : 0] round_ctr_reg;
reg [3 : 0] round_ctr_new;
reg round_ctr_we;
reg round_ctr_set;
reg round_ctr_dec;
reg [127 : 0] block_new;
reg [31 : 0] block_w0_reg;
reg [31 : 0] block_w1_reg;
reg [31 : 0] block_w2_reg;
reg [31 : 0] block_w3_reg;
reg block_w0_we;
reg block_w1_we;
reg block_w2_we;
reg block_w3_we;
reg ready_reg;
reg ready_new;
reg ready_we;
reg [2 : 0] dec_ctrl_reg;
reg [2 : 0] dec_ctrl_new;
reg dec_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_sboxw;
wire [31 : 0] new_sboxw;
reg [2 : 0] update_type;
//----------------------------------------------------------------
// Instantiations.
//----------------------------------------------------------------
aes_inv_sbox inv_sbox_inst(.sword(tmp_sboxw), .new_sword(new_sboxw));
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign round = round_ctr_reg;
assign new_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
assign ready = ready_reg;
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin: reg_update
if (!reset_n)
begin
block_w0_reg <= 32'h0;
block_w1_reg <= 32'h0;
block_w2_reg <= 32'h0;
block_w3_reg <= 32'h0;
sword_ctr_reg <= 2'h0;
round_ctr_reg <= 4'h0;
ready_reg <= 1'b1;
dec_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (block_w0_we)
block_w0_reg <= block_new[127 : 096];
if (block_w1_we)
block_w1_reg <= block_new[095 : 064];
if (block_w2_we)
block_w2_reg <= block_new[063 : 032];
if (block_w3_we)
block_w3_reg <= block_new[031 : 000];
if (sword_ctr_we)
sword_ctr_reg <= sword_ctr_new;
if (round_ctr_we)
round_ctr_reg <= round_ctr_new;
if (ready_we)
ready_reg <= ready_new;
if (dec_ctrl_we)
dec_ctrl_reg <= dec_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// round_logic
//
// The logic needed to implement init, main and final rounds.
//----------------------------------------------------------------
always @*
begin : round_logic
reg [127 : 0] old_block, inv_shiftrows_block, inv_mixcolumns_block;
reg [127 : 0] addkey_block;
inv_shiftrows_block = 128'h0;
inv_mixcolumns_block = 128'h0;
addkey_block = 128'h0;
block_new = 128'h0;
tmp_sboxw = 32'h0;
block_w0_we = 1'b0;
block_w1_we = 1'b0;
block_w2_we = 1'b0;
block_w3_we = 1'b0;
old_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
// Update based on update type.
case (update_type)
// InitRound
INIT_UPDATE:
begin
old_block = block;
addkey_block = addroundkey(old_block, round_key);
inv_shiftrows_block = inv_shiftrows(addkey_block);
block_new = inv_shiftrows_block;
block_w0_we = 1'b1;
block_w1_we = 1'b1;
block_w2_we = 1'b1;
block_w3_we = 1'b1;
end
SBOX_UPDATE:
begin
block_new = {new_sboxw, new_sboxw, new_sboxw, new_sboxw};
case (sword_ctr_reg)
2'h0:
begin
tmp_sboxw = block_w0_reg;
block_w0_we = 1'b1;
end
2'h1:
begin
tmp_sboxw = block_w1_reg;
block_w1_we = 1'b1;
end
2'h2:
begin
tmp_sboxw = block_w2_reg;
block_w2_we = 1'b1;
end
2'h3:
begin
tmp_sboxw = block_w3_reg;
block_w3_we = 1'b1;
end
endcase // case (sbox_mux_ctrl_reg)
end
MAIN_UPDATE:
begin
addkey_block = addroundkey(old_block, round_key);
inv_mixcolumns_block = inv_mixcolumns(addkey_block);
inv_shiftrows_block = inv_shiftrows(inv_mixcolumns_block);
block_new = inv_shiftrows_block;
block_w0_we = 1'b1;
block_w1_we = 1'b1;
block_w2_we = 1'b1;
block_w3_we = 1'b1;
end
FINAL_UPDATE:
begin
block_new = addroundkey(old_block, round_key);
block_w0_we = 1'b1;
block_w1_we = 1'b1;
block_w2_we = 1'b1;
block_w3_we = 1'b1;
end
default:
begin
end
endcase // case (update_type)
end // round_logic
//----------------------------------------------------------------
// sword_ctr
//
// The subbytes word counter with reset and increase logic.
//----------------------------------------------------------------
always @*
begin : sword_ctr
sword_ctr_new = 2'h0;
sword_ctr_we = 1'b0;
if (sword_ctr_rst)
begin
sword_ctr_new = 2'h0;
sword_ctr_we = 1'b1;
end
else if (sword_ctr_inc)
begin
sword_ctr_new = sword_ctr_reg + 1'b1;
sword_ctr_we = 1'b1;
end
end // sword_ctr
//----------------------------------------------------------------
// round_ctr
//
// The round counter with reset and increase logic.
//----------------------------------------------------------------
always @*
begin : round_ctr
round_ctr_new = 4'h0;
round_ctr_we = 1'b0;
if (round_ctr_set)
begin
if (keylen == AES_256_BIT_KEY)
begin
round_ctr_new = AES256_ROUNDS;
end
else
begin
round_ctr_new = AES128_ROUNDS;
end
round_ctr_we = 1'b1;
end
else if (round_ctr_dec)
begin
round_ctr_new = round_ctr_reg - 1'b1;
round_ctr_we = 1'b1;
end
end // round_ctr
//----------------------------------------------------------------
// decipher_ctrl
//
// The FSM that controls the decipher operations.
//----------------------------------------------------------------
always @*
begin: decipher_ctrl
sword_ctr_inc = 1'b0;
sword_ctr_rst = 1'b0;
round_ctr_dec = 1'b0;
round_ctr_set = 1'b0;
ready_new = 1'b0;
ready_we = 1'b0;
update_type = NO_UPDATE;
dec_ctrl_new = CTRL_IDLE;
dec_ctrl_we = 1'b0;
case(dec_ctrl_reg)
CTRL_IDLE:
begin
if (next)
begin
round_ctr_set = 1'b1;
ready_new = 1'b0;
ready_we = 1'b1;
dec_ctrl_new = CTRL_INIT;
dec_ctrl_we = 1'b1;
end
end
CTRL_INIT:
begin
sword_ctr_rst = 1'b1;
update_type = INIT_UPDATE;
dec_ctrl_new = CTRL_SBOX;
dec_ctrl_we = 1'b1;
end
CTRL_SBOX:
begin
sword_ctr_inc = 1'b1;
update_type = SBOX_UPDATE;
if (sword_ctr_reg == 2'h3)
begin
round_ctr_dec = 1'b1;
dec_ctrl_new = CTRL_MAIN;
dec_ctrl_we = 1'b1;
end
end
CTRL_MAIN:
begin
sword_ctr_rst = 1'b1;
if (round_ctr_reg > 0)
begin
update_type = MAIN_UPDATE;
dec_ctrl_new = CTRL_SBOX;
dec_ctrl_we = 1'b1;
end
else
begin
update_type = FINAL_UPDATE;
ready_new = 1'b1;
ready_we = 1'b1;
dec_ctrl_new = CTRL_IDLE;
dec_ctrl_we = 1'b1;
end
end
default:
begin
// Empty. Just here to make the synthesis tool happy.
end
endcase // case (dec_ctrl_reg)
end // decipher_ctrl
endmodule // aes_decipher_block
//======================================================================
// EOF aes_decipher_block.v
//======================================================================
//======================================================================
//
// aes_inv_sbox.v
// --------------
// The inverse AES S-box. Basically a 256 Byte ROM.
//
//
// Copyright (c) 2013 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module aes_inv_sbox(
input wire [31 : 0] sword,
output wire [31 : 0] new_sword
);
//----------------------------------------------------------------
// The inverse sbox array.
//----------------------------------------------------------------
wire [7 : 0] inv_sbox [0 : 255];
//----------------------------------------------------------------
// Four parallel muxes.
//----------------------------------------------------------------
assign new_sword[31 : 24] = inv_sbox[sword[31 : 24]];
assign new_sword[23 : 16] = inv_sbox[sword[23 : 16]];
assign new_sword[15 : 08] = inv_sbox[sword[15 : 08]];
assign new_sword[07 : 00] = inv_sbox[sword[07 : 00]];
//----------------------------------------------------------------
// Creating the contents of the array.
//----------------------------------------------------------------
assign inv_sbox[8'h00] = 8'h52;
assign inv_sbox[8'h01] = 8'h09;
assign inv_sbox[8'h02] = 8'h6a;
assign inv_sbox[8'h03] = 8'hd5;
assign inv_sbox[8'h04] = 8'h30;
assign inv_sbox[8'h05] = 8'h36;
assign inv_sbox[8'h06] = 8'ha5;
assign inv_sbox[8'h07] = 8'h38;
assign inv_sbox[8'h08] = 8'hbf;
assign inv_sbox[8'h09] = 8'h40;
assign inv_sbox[8'h0a] = 8'ha3;
assign inv_sbox[8'h0b] = 8'h9e;
assign inv_sbox[8'h0c] = 8'h81;
assign inv_sbox[8'h0d] = 8'hf3;
assign inv_sbox[8'h0e] = 8'hd7;
assign inv_sbox[8'h0f] = 8'hfb;
assign inv_sbox[8'h10] = 8'h7c;
assign inv_sbox[8'h11] = 8'he3;
assign inv_sbox[8'h12] = 8'h39;
assign inv_sbox[8'h13] = 8'h82;
assign inv_sbox[8'h14] = 8'h9b;
assign inv_sbox[8'h15] = 8'h2f;
assign inv_sbox[8'h16] = 8'hff;
assign inv_sbox[8'h17] = 8'h87;
assign inv_sbox[8'h18] = 8'h34;
assign inv_sbox[8'h19] = 8'h8e;
assign inv_sbox[8'h1a] = 8'h43;
assign inv_sbox[8'h1b] = 8'h44;
assign inv_sbox[8'h1c] = 8'hc4;
assign inv_sbox[8'h1d] = 8'hde;
assign inv_sbox[8'h1e] = 8'he9;
assign inv_sbox[8'h1f] = 8'hcb;
assign inv_sbox[8'h20] = 8'h54;
assign inv_sbox[8'h21] = 8'h7b;
assign inv_sbox[8'h22] = 8'h94;
assign inv_sbox[8'h23] = 8'h32;
assign inv_sbox[8'h24] = 8'ha6;
assign inv_sbox[8'h25] = 8'hc2;
assign inv_sbox[8'h26] = 8'h23;
assign inv_sbox[8'h27] = 8'h3d;
assign inv_sbox[8'h28] = 8'hee;
assign inv_sbox[8'h29] = 8'h4c;
assign inv_sbox[8'h2a] = 8'h95;
assign inv_sbox[8'h2b] = 8'h0b;
assign inv_sbox[8'h2c] = 8'h42;
assign inv_sbox[8'h2d] = 8'hfa;
assign inv_sbox[8'h2e] = 8'hc3;
assign inv_sbox[8'h2f] = 8'h4e;
assign inv_sbox[8'h30] = 8'h08;
assign inv_sbox[8'h31] = 8'h2e;
assign inv_sbox[8'h32] = 8'ha1;
assign inv_sbox[8'h33] = 8'h66;
assign inv_sbox[8'h34] = 8'h28;
assign inv_sbox[8'h35] = 8'hd9;
assign inv_sbox[8'h36] = 8'h24;
assign inv_sbox[8'h37] = 8'hb2;
assign inv_sbox[8'h38] = 8'h76;
assign inv_sbox[8'h39] = 8'h5b;
assign inv_sbox[8'h3a] = 8'ha2;
assign inv_sbox[8'h3b] = 8'h49;
assign inv_sbox[8'h3c] = 8'h6d;
assign inv_sbox[8'h3d] = 8'h8b;
assign inv_sbox[8'h3e] = 8'hd1;
assign inv_sbox[8'h3f] = 8'h25;
assign inv_sbox[8'h40] = 8'h72;
assign inv_sbox[8'h41] = 8'hf8;
assign inv_sbox[8'h42] = 8'hf6;
assign inv_sbox[8'h43] = 8'h64;
assign inv_sbox[8'h44] = 8'h86;
assign inv_sbox[8'h45] = 8'h68;
assign inv_sbox[8'h46] = 8'h98;
assign inv_sbox[8'h47] = 8'h16;
assign inv_sbox[8'h48] = 8'hd4;
assign inv_sbox[8'h49] = 8'ha4;
assign inv_sbox[8'h4a] = 8'h5c;
assign inv_sbox[8'h4b] = 8'hcc;
assign inv_sbox[8'h4c] = 8'h5d;
assign inv_sbox[8'h4d] = 8'h65;
assign inv_sbox[8'h4e] = 8'hb6;
assign inv_sbox[8'h4f] = 8'h92;
assign inv_sbox[8'h50] = 8'h6c;
assign inv_sbox[8'h51] = 8'h70;
assign inv_sbox[8'h52] = 8'h48;
assign inv_sbox[8'h53] = 8'h50;
assign inv_sbox[8'h54] = 8'hfd;
assign inv_sbox[8'h55] = 8'hed;
assign inv_sbox[8'h56] = 8'hb9;
assign inv_sbox[8'h57] = 8'hda;
assign inv_sbox[8'h58] = 8'h5e;
assign inv_sbox[8'h59] = 8'h15;
assign inv_sbox[8'h5a] = 8'h46;
assign inv_sbox[8'h5b] = 8'h57;
assign inv_sbox[8'h5c] = 8'ha7;
assign inv_sbox[8'h5d] = 8'h8d;
assign inv_sbox[8'h5e] = 8'h9d;
assign inv_sbox[8'h5f] = 8'h84;
assign inv_sbox[8'h60] = 8'h90;
assign inv_sbox[8'h61] = 8'hd8;
assign inv_sbox[8'h62] = 8'hab;
assign inv_sbox[8'h63] = 8'h00;
assign inv_sbox[8'h64] = 8'h8c;
assign inv_sbox[8'h65] = 8'hbc;
assign inv_sbox[8'h66] = 8'hd3;
assign inv_sbox[8'h67] = 8'h0a;
assign inv_sbox[8'h68] = 8'hf7;
assign inv_sbox[8'h69] = 8'he4;
assign inv_sbox[8'h6a] = 8'h58;
assign inv_sbox[8'h6b] = 8'h05;
assign inv_sbox[8'h6c] = 8'hb8;
assign inv_sbox[8'h6d] = 8'hb3;
assign inv_sbox[8'h6e] = 8'h45;
assign inv_sbox[8'h6f] = 8'h06;
assign inv_sbox[8'h70] = 8'hd0;
assign inv_sbox[8'h71] = 8'h2c;
assign inv_sbox[8'h72] = 8'h1e;
assign inv_sbox[8'h73] = 8'h8f;
assign inv_sbox[8'h74] = 8'hca;
assign inv_sbox[8'h75] = 8'h3f;
assign inv_sbox[8'h76] = 8'h0f;
assign inv_sbox[8'h77] = 8'h02;
assign inv_sbox[8'h78] = 8'hc1;
assign inv_sbox[8'h79] = 8'haf;
assign inv_sbox[8'h7a] = 8'hbd;
assign inv_sbox[8'h7b] = 8'h03;
assign inv_sbox[8'h7c] = 8'h01;
assign inv_sbox[8'h7d] = 8'h13;
assign inv_sbox[8'h7e] = 8'h8a;
assign inv_sbox[8'h7f] = 8'h6b;
assign inv_sbox[8'h80] = 8'h3a;
assign inv_sbox[8'h81] = 8'h91;
assign inv_sbox[8'h82] = 8'h11;
assign inv_sbox[8'h83] = 8'h41;
assign inv_sbox[8'h84] = 8'h4f;
assign inv_sbox[8'h85] = 8'h67;
assign inv_sbox[8'h86] = 8'hdc;
assign inv_sbox[8'h87] = 8'hea;
assign inv_sbox[8'h88] = 8'h97;
assign inv_sbox[8'h89] = 8'hf2;
assign inv_sbox[8'h8a] = 8'hcf;
assign inv_sbox[8'h8b] = 8'hce;
assign inv_sbox[8'h8c] = 8'hf0;
assign inv_sbox[8'h8d] = 8'hb4;
assign inv_sbox[8'h8e] = 8'he6;
assign inv_sbox[8'h8f] = 8'h73;
assign inv_sbox[8'h90] = 8'h96;
assign inv_sbox[8'h91] = 8'hac;
assign inv_sbox[8'h92] = 8'h74;
assign inv_sbox[8'h93] = 8'h22;
assign inv_sbox[8'h94] = 8'he7;
assign inv_sbox[8'h95] = 8'had;
assign inv_sbox[8'h96] = 8'h35;
assign inv_sbox[8'h97] = 8'h85;
assign inv_sbox[8'h98] = 8'he2;
assign inv_sbox[8'h99] = 8'hf9;
assign inv_sbox[8'h9a] = 8'h37;
assign inv_sbox[8'h9b] = 8'he8;
assign inv_sbox[8'h9c] = 8'h1c;
assign inv_sbox[8'h9d] = 8'h75;
assign inv_sbox[8'h9e] = 8'hdf;
assign inv_sbox[8'h9f] = 8'h6e;
assign inv_sbox[8'ha0] = 8'h47;
assign inv_sbox[8'ha1] = 8'hf1;
assign inv_sbox[8'ha2] = 8'h1a;
assign inv_sbox[8'ha3] = 8'h71;
assign inv_sbox[8'ha4] = 8'h1d;
assign inv_sbox[8'ha5] = 8'h29;
assign inv_sbox[8'ha6] = 8'hc5;
assign inv_sbox[8'ha7] = 8'h89;
assign inv_sbox[8'ha8] = 8'h6f;
assign inv_sbox[8'ha9] = 8'hb7;
assign inv_sbox[8'haa] = 8'h62;
assign inv_sbox[8'hab] = 8'h0e;
assign inv_sbox[8'hac] = 8'haa;
assign inv_sbox[8'had] = 8'h18;
assign inv_sbox[8'hae] = 8'hbe;
assign inv_sbox[8'haf] = 8'h1b;
assign inv_sbox[8'hb0] = 8'hfc;
assign inv_sbox[8'hb1] = 8'h56;
assign inv_sbox[8'hb2] = 8'h3e;
assign inv_sbox[8'hb3] = 8'h4b;
assign inv_sbox[8'hb4] = 8'hc6;
assign inv_sbox[8'hb5] = 8'hd2;
assign inv_sbox[8'hb6] = 8'h79;
assign inv_sbox[8'hb7] = 8'h20;
assign inv_sbox[8'hb8] = 8'h9a;
assign inv_sbox[8'hb9] = 8'hdb;
assign inv_sbox[8'hba] = 8'hc0;
assign inv_sbox[8'hbb] = 8'hfe;
assign inv_sbox[8'hbc] = 8'h78;
assign inv_sbox[8'hbd] = 8'hcd;
assign inv_sbox[8'hbe] = 8'h5a;
assign inv_sbox[8'hbf] = 8'hf4;
assign inv_sbox[8'hc0] = 8'h1f;
assign inv_sbox[8'hc1] = 8'hdd;
assign inv_sbox[8'hc2] = 8'ha8;
assign inv_sbox[8'hc3] = 8'h33;
assign inv_sbox[8'hc4] = 8'h88;
assign inv_sbox[8'hc5] = 8'h07;
assign inv_sbox[8'hc6] = 8'hc7;
assign inv_sbox[8'hc7] = 8'h31;
assign inv_sbox[8'hc8] = 8'hb1;
assign inv_sbox[8'hc9] = 8'h12;
assign inv_sbox[8'hca] = 8'h10;
assign inv_sbox[8'hcb] = 8'h59;
assign inv_sbox[8'hcc] = 8'h27;
assign inv_sbox[8'hcd] = 8'h80;
assign inv_sbox[8'hce] = 8'hec;
assign inv_sbox[8'hcf] = 8'h5f;
assign inv_sbox[8'hd0] = 8'h60;
assign inv_sbox[8'hd1] = 8'h51;
assign inv_sbox[8'hd2] = 8'h7f;
assign inv_sbox[8'hd3] = 8'ha9;
assign inv_sbox[8'hd4] = 8'h19;
assign inv_sbox[8'hd5] = 8'hb5;
assign inv_sbox[8'hd6] = 8'h4a;
assign inv_sbox[8'hd7] = 8'h0d;
assign inv_sbox[8'hd8] = 8'h2d;
assign inv_sbox[8'hd9] = 8'he5;
assign inv_sbox[8'hda] = 8'h7a;
assign inv_sbox[8'hdb] = 8'h9f;
assign inv_sbox[8'hdc] = 8'h93;
assign inv_sbox[8'hdd] = 8'hc9;
assign inv_sbox[8'hde] = 8'h9c;
assign inv_sbox[8'hdf] = 8'hef;
assign inv_sbox[8'he0] = 8'ha0;
assign inv_sbox[8'he1] = 8'he0;
assign inv_sbox[8'he2] = 8'h3b;
assign inv_sbox[8'he3] = 8'h4d;
assign inv_sbox[8'he4] = 8'hae;
assign inv_sbox[8'he5] = 8'h2a;
assign inv_sbox[8'he6] = 8'hf5;
assign inv_sbox[8'he7] = 8'hb0;
assign inv_sbox[8'he8] = 8'hc8;
assign inv_sbox[8'he9] = 8'heb;
assign inv_sbox[8'hea] = 8'hbb;
assign inv_sbox[8'heb] = 8'h3c;
assign inv_sbox[8'hec] = 8'h83;
assign inv_sbox[8'hed] = 8'h53;
assign inv_sbox[8'hee] = 8'h99;
assign inv_sbox[8'hef] = 8'h61;
assign inv_sbox[8'hf0] = 8'h17;
assign inv_sbox[8'hf1] = 8'h2b;
assign inv_sbox[8'hf2] = 8'h04;
assign inv_sbox[8'hf3] = 8'h7e;
assign inv_sbox[8'hf4] = 8'hba;
assign inv_sbox[8'hf5] = 8'h77;
assign inv_sbox[8'hf6] = 8'hd6;
assign inv_sbox[8'hf7] = 8'h26;
assign inv_sbox[8'hf8] = 8'he1;
assign inv_sbox[8'hf9] = 8'h69;
assign inv_sbox[8'hfa] = 8'h14;
assign inv_sbox[8'hfb] = 8'h63;
assign inv_sbox[8'hfc] = 8'h55;
assign inv_sbox[8'hfd] = 8'h21;
assign inv_sbox[8'hfe] = 8'h0c;
assign inv_sbox[8'hff] = 8'h7d;
endmodule // aes_inv_sbox
//======================================================================
// EOF aes_inv_sbox.v
//======================================================================
//======================================================================
//
// aes_key_mem.v
// -------------
// The AES key memory including round key generator.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module aes_key_mem(
input wire clk,
input wire reset_n,
input wire [255 : 0] key,
input wire keylen,
input wire init,
input wire [3 : 0] round,
output wire [127 : 0] round_key,
output wire ready,
output wire [31 : 0] sboxw,
input wire [31 : 0] new_sboxw
);
//----------------------------------------------------------------
// Parameters.
//----------------------------------------------------------------
localparam AES_128_BIT_KEY = 1'h0;
localparam AES_256_BIT_KEY = 1'h1;
localparam AES_128_NUM_ROUNDS = 10;
localparam AES_256_NUM_ROUNDS = 14;
localparam CTRL_IDLE = 3'h0;
localparam CTRL_INIT = 3'h1;
localparam CTRL_GENERATE = 3'h2;
localparam CTRL_DONE = 3'h3;
//----------------------------------------------------------------
// Registers.
//----------------------------------------------------------------
reg [127 : 0] key_mem [0 : 14];
reg [127 : 0] key_mem_new;
reg key_mem_we;
reg [127 : 0] prev_key0_reg;
reg [127 : 0] prev_key0_new;
reg prev_key0_we;
reg [127 : 0] prev_key1_reg;
reg [127 : 0] prev_key1_new;
reg prev_key1_we;
reg [3 : 0] round_ctr_reg;
reg [3 : 0] round_ctr_new;
reg round_ctr_rst;
reg round_ctr_inc;
reg round_ctr_we;
reg [2 : 0] key_mem_ctrl_reg;
reg [2 : 0] key_mem_ctrl_new;
reg key_mem_ctrl_we;
reg ready_reg;
reg ready_new;
reg ready_we;
reg [7 : 0] rcon_reg;
reg [7 : 0] rcon_new;
reg rcon_we;
reg rcon_set;
reg rcon_next;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_sboxw;
reg round_key_update;
reg [127 : 0] tmp_round_key;
//----------------------------------------------------------------
// Concurrent assignments for ports.
//----------------------------------------------------------------
assign round_key = tmp_round_key;
assign ready = ready_reg;
assign sboxw = tmp_sboxw;
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin: reg_update
integer i;
if (!reset_n)
begin
for (i = 0 ; i <= AES_256_NUM_ROUNDS ; i = i + 1)
key_mem [i] <= 128'h0;
rcon_reg <= 8'h0;
ready_reg <= 1'b0;
round_ctr_reg <= 4'h0;
key_mem_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (round_ctr_we)
round_ctr_reg <= round_ctr_new;
if (ready_we)
ready_reg <= ready_new;
if (rcon_we)
rcon_reg <= rcon_new;
if (key_mem_we)
key_mem[round_ctr_reg] <= key_mem_new;
if (prev_key0_we)
prev_key0_reg <= prev_key0_new;
if (prev_key1_we)
prev_key1_reg <= prev_key1_new;
if (key_mem_ctrl_we)
key_mem_ctrl_reg <= key_mem_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// key_mem_read
//
// Combinational read port for the key memory.
//----------------------------------------------------------------
always @*
begin : key_mem_read
tmp_round_key = key_mem[round];
end // key_mem_read
//----------------------------------------------------------------
// round_key_gen
//
// The round key generator logic for AES-128 and AES-256.
//----------------------------------------------------------------
always @*
begin: round_key_gen
reg [31 : 0] w0, w1, w2, w3, w4, w5, w6, w7;
reg [31 : 0] k0, k1, k2, k3;
reg [31 : 0] rconw, rotstw, tw, trw;
// Default assignments.
key_mem_new = 128'h0;
key_mem_we = 1'b0;
prev_key0_new = 128'h0;
prev_key0_we = 1'b0;
prev_key1_new = 128'h0;
prev_key1_we = 1'b0;
k0 = 32'h0;
k1 = 32'h0;
k2 = 32'h0;
k3 = 32'h0;
rcon_set = 1'b1;
rcon_next = 1'b0;
// Extract words and calculate intermediate values.
// Perform rotation of sbox word etc.
w0 = prev_key0_reg[127 : 096];
w1 = prev_key0_reg[095 : 064];
w2 = prev_key0_reg[063 : 032];
w3 = prev_key0_reg[031 : 000];
w4 = prev_key1_reg[127 : 096];
w5 = prev_key1_reg[095 : 064];
w6 = prev_key1_reg[063 : 032];
w7 = prev_key1_reg[031 : 000];
rconw = {rcon_reg, 24'h0};
tmp_sboxw = w7;
rotstw = {new_sboxw[23 : 00], new_sboxw[31 : 24]};
trw = rotstw ^ rconw;
tw = new_sboxw;
// Generate the specific round keys.
if (round_key_update)
begin
rcon_set = 1'b0;
key_mem_we = 1'b1;
case (keylen)
AES_128_BIT_KEY:
begin
if (round_ctr_reg == 0)
begin
key_mem_new = key[255 : 128];
prev_key1_new = key[255 : 128];
prev_key1_we = 1'b1;
rcon_next = 1'b1;
end
else
begin
k0 = w4 ^ trw;
k1 = w5 ^ w4 ^ trw;
k2 = w6 ^ w5 ^ w4 ^ trw;
k3 = w7 ^ w6 ^ w5 ^ w4 ^ trw;
key_mem_new = {k0, k1, k2, k3};
prev_key1_new = {k0, k1, k2, k3};
prev_key1_we = 1'b1;
rcon_next = 1'b1;
end
end
AES_256_BIT_KEY:
begin
if (round_ctr_reg == 0)
begin
key_mem_new = key[255 : 128];
prev_key0_new = key[255 : 128];
prev_key0_we = 1'b1;
end
else if (round_ctr_reg == 1)
begin
key_mem_new = key[127 : 0];
prev_key1_new = key[127 : 0];
prev_key1_we = 1'b1;
rcon_next = 1'b1;
end
else
begin
if (round_ctr_reg[0] == 0)
begin
k0 = w0 ^ trw;
k1 = w1 ^ w0 ^ trw;
k2 = w2 ^ w1 ^ w0 ^ trw;
k3 = w3 ^ w2 ^ w1 ^ w0 ^ trw;
end
else
begin
k0 = w0 ^ tw;
k1 = w1 ^ w0 ^ tw;
k2 = w2 ^ w1 ^ w0 ^ tw;
k3 = w3 ^ w2 ^ w1 ^ w0 ^ tw;
rcon_next = 1'b1;
end
// Store the generated round keys.
key_mem_new = {k0, k1, k2, k3};
prev_key1_new = {k0, k1, k2, k3};
prev_key1_we = 1'b1;
prev_key0_new = prev_key1_reg;
prev_key0_we = 1'b1;
end
end
default:
begin
end
endcase // case (keylen)
end
end // round_key_gen
//----------------------------------------------------------------
// rcon_logic
//
// Caclulates the rcon value for the different key expansion
// iterations.
//----------------------------------------------------------------
always @*
begin : rcon_logic
reg [7 : 0] tmp_rcon;
rcon_new = 8'h00;
rcon_we = 1'b0;
tmp_rcon = {rcon_reg[6 : 0], 1'b0} ^ (8'h1b & {8{rcon_reg[7]}});
if (rcon_set)
begin
rcon_new = 8'h8d;
rcon_we = 1'b1;
end
if (rcon_next)
begin
rcon_new = tmp_rcon[7 : 0];
rcon_we = 1'b1;
end
end
//----------------------------------------------------------------
// round_ctr
//
// The round counter logic with increase and reset.
//----------------------------------------------------------------
always @*
begin : round_ctr
round_ctr_new = 4'h0;
round_ctr_we = 1'b0;
if (round_ctr_rst)
begin
round_ctr_new = 4'h0;
round_ctr_we = 1'b1;
end
else if (round_ctr_inc)
begin
round_ctr_new = round_ctr_reg + 1'b1;
round_ctr_we = 1'b1;
end
end
//----------------------------------------------------------------
// key_mem_ctrl
//
//
// The FSM that controls the round key generation.
//----------------------------------------------------------------
always @*
begin: key_mem_ctrl
reg [3 : 0] num_rounds;
// Default assignments.
ready_new = 1'b0;
ready_we = 1'b0;
round_key_update = 1'b0;
round_ctr_rst = 1'b0;
round_ctr_inc = 1'b0;
key_mem_ctrl_new = CTRL_IDLE;
key_mem_ctrl_we = 1'b0;
if (keylen == AES_128_BIT_KEY)
num_rounds = AES_128_NUM_ROUNDS;
else
num_rounds = AES_256_NUM_ROUNDS;
case(key_mem_ctrl_reg)
CTRL_IDLE:
begin
if (init)
begin
ready_new = 1'b0;
ready_we = 1'b1;
key_mem_ctrl_new = CTRL_INIT;
key_mem_ctrl_we = 1'b1;
end
end
CTRL_INIT:
begin
round_ctr_rst = 1'b1;
key_mem_ctrl_new = CTRL_GENERATE;
key_mem_ctrl_we = 1'b1;
end
CTRL_GENERATE:
begin
round_ctr_inc = 1'b1;
round_key_update = 1'b1;
if (round_ctr_reg == num_rounds)
begin
key_mem_ctrl_new = CTRL_DONE;
key_mem_ctrl_we = 1'b1;
end
end
CTRL_DONE:
begin
ready_new = 1'b1;
ready_we = 1'b1;
key_mem_ctrl_new = CTRL_IDLE;
key_mem_ctrl_we = 1'b1;
end
default:
begin
end
endcase // case (key_mem_ctrl_reg)
end // key_mem_ctrl
endmodule // aes_key_mem
//======================================================================
// EOF aes_key_mem.v
//======================================================================
//======================================================================
//
// aes_sbox.v
// ----------
// The AES S-box. Basically a 256 Byte ROM. This implementation
// contains four parallel S-boxes to handle a 32 bit word.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module aes_sbox(
input wire [31 : 0] sboxw,
output wire [31 : 0] new_sboxw
);
//----------------------------------------------------------------
// The sbox array.
//----------------------------------------------------------------
wire [7 : 0] sbox [0 : 255];
//----------------------------------------------------------------
// Four parallel muxes.
//----------------------------------------------------------------
assign new_sboxw[31 : 24] = sbox[sboxw[31 : 24]];
assign new_sboxw[23 : 16] = sbox[sboxw[23 : 16]];
assign new_sboxw[15 : 08] = sbox[sboxw[15 : 08]];
assign new_sboxw[07 : 00] = sbox[sboxw[07 : 00]];
//----------------------------------------------------------------
// Creating the sbox array contents.
//----------------------------------------------------------------
assign sbox[8'h00] = 8'h63;
assign sbox[8'h01] = 8'h7c;
assign sbox[8'h02] = 8'h77;
assign sbox[8'h03] = 8'h7b;
assign sbox[8'h04] = 8'hf2;
assign sbox[8'h05] = 8'h6b;
assign sbox[8'h06] = 8'h6f;
assign sbox[8'h07] = 8'hc5;
assign sbox[8'h08] = 8'h30;
assign sbox[8'h09] = 8'h01;
assign sbox[8'h0a] = 8'h67;
assign sbox[8'h0b] = 8'h2b;
assign sbox[8'h0c] = 8'hfe;
assign sbox[8'h0d] = 8'hd7;
assign sbox[8'h0e] = 8'hab;
assign sbox[8'h0f] = 8'h76;
assign sbox[8'h10] = 8'hca;
assign sbox[8'h11] = 8'h82;
assign sbox[8'h12] = 8'hc9;
assign sbox[8'h13] = 8'h7d;
assign sbox[8'h14] = 8'hfa;
assign sbox[8'h15] = 8'h59;
assign sbox[8'h16] = 8'h47;
assign sbox[8'h17] = 8'hf0;
assign sbox[8'h18] = 8'had;
assign sbox[8'h19] = 8'hd4;
assign sbox[8'h1a] = 8'ha2;
assign sbox[8'h1b] = 8'haf;
assign sbox[8'h1c] = 8'h9c;
assign sbox[8'h1d] = 8'ha4;
assign sbox[8'h1e] = 8'h72;
assign sbox[8'h1f] = 8'hc0;
assign sbox[8'h20] = 8'hb7;
assign sbox[8'h21] = 8'hfd;
assign sbox[8'h22] = 8'h93;
assign sbox[8'h23] = 8'h26;
assign sbox[8'h24] = 8'h36;
assign sbox[8'h25] = 8'h3f;
assign sbox[8'h26] = 8'hf7;
assign sbox[8'h27] = 8'hcc;
assign sbox[8'h28] = 8'h34;
assign sbox[8'h29] = 8'ha5;
assign sbox[8'h2a] = 8'he5;
assign sbox[8'h2b] = 8'hf1;
assign sbox[8'h2c] = 8'h71;
assign sbox[8'h2d] = 8'hd8;
assign sbox[8'h2e] = 8'h31;
assign sbox[8'h2f] = 8'h15;
assign sbox[8'h30] = 8'h04;
assign sbox[8'h31] = 8'hc7;
assign sbox[8'h32] = 8'h23;
assign sbox[8'h33] = 8'hc3;
assign sbox[8'h34] = 8'h18;
assign sbox[8'h35] = 8'h96;
assign sbox[8'h36] = 8'h05;
assign sbox[8'h37] = 8'h9a;
assign sbox[8'h38] = 8'h07;
assign sbox[8'h39] = 8'h12;
assign sbox[8'h3a] = 8'h80;
assign sbox[8'h3b] = 8'he2;
assign sbox[8'h3c] = 8'heb;
assign sbox[8'h3d] = 8'h27;
assign sbox[8'h3e] = 8'hb2;
assign sbox[8'h3f] = 8'h75;
assign sbox[8'h40] = 8'h09;
assign sbox[8'h41] = 8'h83;
assign sbox[8'h42] = 8'h2c;
assign sbox[8'h43] = 8'h1a;
assign sbox[8'h44] = 8'h1b;
assign sbox[8'h45] = 8'h6e;
assign sbox[8'h46] = 8'h5a;
assign sbox[8'h47] = 8'ha0;
assign sbox[8'h48] = 8'h52;
assign sbox[8'h49] = 8'h3b;
assign sbox[8'h4a] = 8'hd6;
assign sbox[8'h4b] = 8'hb3;
assign sbox[8'h4c] = 8'h29;
assign sbox[8'h4d] = 8'he3;
assign sbox[8'h4e] = 8'h2f;
assign sbox[8'h4f] = 8'h84;
assign sbox[8'h50] = 8'h53;
assign sbox[8'h51] = 8'hd1;
assign sbox[8'h52] = 8'h00;
assign sbox[8'h53] = 8'hed;
assign sbox[8'h54] = 8'h20;
assign sbox[8'h55] = 8'hfc;
assign sbox[8'h56] = 8'hb1;
assign sbox[8'h57] = 8'h5b;
assign sbox[8'h58] = 8'h6a;
assign sbox[8'h59] = 8'hcb;
assign sbox[8'h5a] = 8'hbe;
assign sbox[8'h5b] = 8'h39;
assign sbox[8'h5c] = 8'h4a;
assign sbox[8'h5d] = 8'h4c;
assign sbox[8'h5e] = 8'h58;
assign sbox[8'h5f] = 8'hcf;
assign sbox[8'h60] = 8'hd0;
assign sbox[8'h61] = 8'hef;
assign sbox[8'h62] = 8'haa;
assign sbox[8'h63] = 8'hfb;
assign sbox[8'h64] = 8'h43;
assign sbox[8'h65] = 8'h4d;
assign sbox[8'h66] = 8'h33;
assign sbox[8'h67] = 8'h85;
assign sbox[8'h68] = 8'h45;
assign sbox[8'h69] = 8'hf9;
assign sbox[8'h6a] = 8'h02;
assign sbox[8'h6b] = 8'h7f;
assign sbox[8'h6c] = 8'h50;
assign sbox[8'h6d] = 8'h3c;
assign sbox[8'h6e] = 8'h9f;
assign sbox[8'h6f] = 8'ha8;
assign sbox[8'h70] = 8'h51;
assign sbox[8'h71] = 8'ha3;
assign sbox[8'h72] = 8'h40;
assign sbox[8'h73] = 8'h8f;
assign sbox[8'h74] = 8'h92;
assign sbox[8'h75] = 8'h9d;
assign sbox[8'h76] = 8'h38;
assign sbox[8'h77] = 8'hf5;
assign sbox[8'h78] = 8'hbc;
assign sbox[8'h79] = 8'hb6;
assign sbox[8'h7a] = 8'hda;
assign sbox[8'h7b] = 8'h21;
assign sbox[8'h7c] = 8'h10;
assign sbox[8'h7d] = 8'hff;
assign sbox[8'h7e] = 8'hf3;
assign sbox[8'h7f] = 8'hd2;
assign sbox[8'h80] = 8'hcd;
assign sbox[8'h81] = 8'h0c;
assign sbox[8'h82] = 8'h13;
assign sbox[8'h83] = 8'hec;
assign sbox[8'h84] = 8'h5f;
assign sbox[8'h85] = 8'h97;
assign sbox[8'h86] = 8'h44;
assign sbox[8'h87] = 8'h17;
assign sbox[8'h88] = 8'hc4;
assign sbox[8'h89] = 8'ha7;
assign sbox[8'h8a] = 8'h7e;
assign sbox[8'h8b] = 8'h3d;
assign sbox[8'h8c] = 8'h64;
assign sbox[8'h8d] = 8'h5d;
assign sbox[8'h8e] = 8'h19;
assign sbox[8'h8f] = 8'h73;
assign sbox[8'h90] = 8'h60;
assign sbox[8'h91] = 8'h81;
assign sbox[8'h92] = 8'h4f;
assign sbox[8'h93] = 8'hdc;
assign sbox[8'h94] = 8'h22;
assign sbox[8'h95] = 8'h2a;
assign sbox[8'h96] = 8'h90;
assign sbox[8'h97] = 8'h88;
assign sbox[8'h98] = 8'h46;
assign sbox[8'h99] = 8'hee;
assign sbox[8'h9a] = 8'hb8;
assign sbox[8'h9b] = 8'h14;
assign sbox[8'h9c] = 8'hde;
assign sbox[8'h9d] = 8'h5e;
assign sbox[8'h9e] = 8'h0b;
assign sbox[8'h9f] = 8'hdb;
assign sbox[8'ha0] = 8'he0;
assign sbox[8'ha1] = 8'h32;
assign sbox[8'ha2] = 8'h3a;
assign sbox[8'ha3] = 8'h0a;
assign sbox[8'ha4] = 8'h49;
assign sbox[8'ha5] = 8'h06;
assign sbox[8'ha6] = 8'h24;
assign sbox[8'ha7] = 8'h5c;
assign sbox[8'ha8] = 8'hc2;
assign sbox[8'ha9] = 8'hd3;
assign sbox[8'haa] = 8'hac;
assign sbox[8'hab] = 8'h62;
assign sbox[8'hac] = 8'h91;
assign sbox[8'had] = 8'h95;
assign sbox[8'hae] = 8'he4;
assign sbox[8'haf] = 8'h79;
assign sbox[8'hb0] = 8'he7;
assign sbox[8'hb1] = 8'hc8;
assign sbox[8'hb2] = 8'h37;
assign sbox[8'hb3] = 8'h6d;
assign sbox[8'hb4] = 8'h8d;
assign sbox[8'hb5] = 8'hd5;
assign sbox[8'hb6] = 8'h4e;
assign sbox[8'hb7] = 8'ha9;
assign sbox[8'hb8] = 8'h6c;
assign sbox[8'hb9] = 8'h56;
assign sbox[8'hba] = 8'hf4;
assign sbox[8'hbb] = 8'hea;
assign sbox[8'hbc] = 8'h65;
assign sbox[8'hbd] = 8'h7a;
assign sbox[8'hbe] = 8'hae;
assign sbox[8'hbf] = 8'h08;
assign sbox[8'hc0] = 8'hba;
assign sbox[8'hc1] = 8'h78;
assign sbox[8'hc2] = 8'h25;
assign sbox[8'hc3] = 8'h2e;
assign sbox[8'hc4] = 8'h1c;
assign sbox[8'hc5] = 8'ha6;
assign sbox[8'hc6] = 8'hb4;
assign sbox[8'hc7] = 8'hc6;
assign sbox[8'hc8] = 8'he8;
assign sbox[8'hc9] = 8'hdd;
assign sbox[8'hca] = 8'h74;
assign sbox[8'hcb] = 8'h1f;
assign sbox[8'hcc] = 8'h4b;
assign sbox[8'hcd] = 8'hbd;
assign sbox[8'hce] = 8'h8b;
assign sbox[8'hcf] = 8'h8a;
assign sbox[8'hd0] = 8'h70;
assign sbox[8'hd1] = 8'h3e;
assign sbox[8'hd2] = 8'hb5;
assign sbox[8'hd3] = 8'h66;
assign sbox[8'hd4] = 8'h48;
assign sbox[8'hd5] = 8'h03;
assign sbox[8'hd6] = 8'hf6;
assign sbox[8'hd7] = 8'h0e;
assign sbox[8'hd8] = 8'h61;
assign sbox[8'hd9] = 8'h35;
assign sbox[8'hda] = 8'h57;
assign sbox[8'hdb] = 8'hb9;
assign sbox[8'hdc] = 8'h86;
assign sbox[8'hdd] = 8'hc1;
assign sbox[8'hde] = 8'h1d;
assign sbox[8'hdf] = 8'h9e;
assign sbox[8'he0] = 8'he1;
assign sbox[8'he1] = 8'hf8;
assign sbox[8'he2] = 8'h98;
assign sbox[8'he3] = 8'h11;
assign sbox[8'he4] = 8'h69;
assign sbox[8'he5] = 8'hd9;
assign sbox[8'he6] = 8'h8e;
assign sbox[8'he7] = 8'h94;
assign sbox[8'he8] = 8'h9b;
assign sbox[8'he9] = 8'h1e;
assign sbox[8'hea] = 8'h87;
assign sbox[8'heb] = 8'he9;
assign sbox[8'hec] = 8'hce;
assign sbox[8'hed] = 8'h55;
assign sbox[8'hee] = 8'h28;
assign sbox[8'hef] = 8'hdf;
assign sbox[8'hf0] = 8'h8c;
assign sbox[8'hf1] = 8'ha1;
assign sbox[8'hf2] = 8'h89;
assign sbox[8'hf3] = 8'h0d;
assign sbox[8'hf4] = 8'hbf;
assign sbox[8'hf5] = 8'he6;
assign sbox[8'hf6] = 8'h42;
assign sbox[8'hf7] = 8'h68;
assign sbox[8'hf8] = 8'h41;
assign sbox[8'hf9] = 8'h99;
assign sbox[8'hfa] = 8'h2d;
assign sbox[8'hfb] = 8'h0f;
assign sbox[8'hfc] = 8'hb0;
assign sbox[8'hfd] = 8'h54;
assign sbox[8'hfe] = 8'hbb;
assign sbox[8'hff] = 8'h16;
endmodule // aes_sbox
//======================================================================
// EOF aes_sbox.v
//======================================================================
//======================================================================
//
// aes_encipher_block.v
// --------------------
// The AES encipher round. A pure combinational module that implements
// the initial round, main round and final round logic for
// enciper operations.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module aes_encipher_block(
input wire clk,
input wire reset_n,
input wire next,
input wire keylen,
output wire [3 : 0] round,
input wire [127 : 0] round_key,
output wire [31 : 0] sboxw,
input wire [31 : 0] new_sboxw,
input wire [127 : 0] block,
output wire [127 : 0] new_block,
output wire ready
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam AES_128_BIT_KEY = 1'h0;
localparam AES_256_BIT_KEY = 1'h1;
localparam AES128_ROUNDS = 4'ha;
localparam AES256_ROUNDS = 4'he;
localparam NO_UPDATE = 3'h0;
localparam INIT_UPDATE = 3'h1;
localparam SBOX_UPDATE = 3'h2;
localparam MAIN_UPDATE = 3'h3;
localparam FINAL_UPDATE = 3'h4;
localparam CTRL_IDLE = 3'h0;
localparam CTRL_INIT = 3'h1;
localparam CTRL_SBOX = 3'h2;
localparam CTRL_MAIN = 3'h3;
localparam CTRL_FINAL = 3'h4;
//----------------------------------------------------------------
// Round functions with sub functions.
//----------------------------------------------------------------
function [7 : 0] gm2(input [7 : 0] op);
begin
gm2 = {op[6 : 0], 1'b0} ^ (8'h1b & {8{op[7]}});
end
endfunction // gm2
function [7 : 0] gm3(input [7 : 0] op);
begin
gm3 = gm2(op) ^ op;
end
endfunction // gm3
function [31 : 0] mixw(input [31 : 0] w);
reg [7 : 0] b0, b1, b2, b3;
reg [7 : 0] mb0, mb1, mb2, mb3;
begin
b0 = w[31 : 24];
b1 = w[23 : 16];
b2 = w[15 : 08];
b3 = w[07 : 00];
mb0 = gm2(b0) ^ gm3(b1) ^ b2 ^ b3;
mb1 = b0 ^ gm2(b1) ^ gm3(b2) ^ b3;
mb2 = b0 ^ b1 ^ gm2(b2) ^ gm3(b3);
mb3 = gm3(b0) ^ b1 ^ b2 ^ gm2(b3);
mixw = {mb0, mb1, mb2, mb3};
end
endfunction // mixw
function [127 : 0] mixcolumns(input [127 : 0] data);
reg [31 : 0] w0, w1, w2, w3;
reg [31 : 0] ws0, ws1, ws2, ws3;
begin
w0 = data[127 : 096];
w1 = data[095 : 064];
w2 = data[063 : 032];
w3 = data[031 : 000];
ws0 = mixw(w0);
ws1 = mixw(w1);
ws2 = mixw(w2);
ws3 = mixw(w3);
mixcolumns = {ws0, ws1, ws2, ws3};
end
endfunction // mixcolumns
function [127 : 0] shiftrows(input [127 : 0] data);
reg [31 : 0] w0, w1, w2, w3;
reg [31 : 0] ws0, ws1, ws2, ws3;
begin
w0 = data[127 : 096];
w1 = data[095 : 064];
w2 = data[063 : 032];
w3 = data[031 : 000];
ws0 = {w0[31 : 24], w1[23 : 16], w2[15 : 08], w3[07 : 00]};
ws1 = {w1[31 : 24], w2[23 : 16], w3[15 : 08], w0[07 : 00]};
ws2 = {w2[31 : 24], w3[23 : 16], w0[15 : 08], w1[07 : 00]};
ws3 = {w3[31 : 24], w0[23 : 16], w1[15 : 08], w2[07 : 00]};
shiftrows = {ws0, ws1, ws2, ws3};
end
endfunction // shiftrows
function [127 : 0] addroundkey(input [127 : 0] data, input [127 : 0] rkey);
begin
addroundkey = data ^ rkey;
end
endfunction // addroundkey
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [1 : 0] sword_ctr_reg;
reg [1 : 0] sword_ctr_new;
reg sword_ctr_we;
reg sword_ctr_inc;
reg sword_ctr_rst;
reg [3 : 0] round_ctr_reg;
reg [3 : 0] round_ctr_new;
reg round_ctr_we;
reg round_ctr_rst;
reg round_ctr_inc;
reg [127 : 0] block_new;
reg [31 : 0] block_w0_reg;
reg [31 : 0] block_w1_reg;
reg [31 : 0] block_w2_reg;
reg [31 : 0] block_w3_reg;
reg block_w0_we;
reg block_w1_we;
reg block_w2_we;
reg block_w3_we;
reg ready_reg;
reg ready_new;
reg ready_we;
reg [2 : 0] enc_ctrl_reg;
reg [2 : 0] enc_ctrl_new;
reg enc_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [2 : 0] update_type;
reg [31 : 0] muxed_sboxw;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign round = round_ctr_reg;
assign sboxw = muxed_sboxw;
assign new_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
assign ready = ready_reg;
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin: reg_update
if (!reset_n)
begin
block_w0_reg <= 32'h0;
block_w1_reg <= 32'h0;
block_w2_reg <= 32'h0;
block_w3_reg <= 32'h0;
sword_ctr_reg <= 2'h0;
round_ctr_reg <= 4'h0;
ready_reg <= 1'b1;
enc_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (block_w0_we)
block_w0_reg <= block_new[127 : 096];
if (block_w1_we)
block_w1_reg <= block_new[095 : 064];
if (block_w2_we)
block_w2_reg <= block_new[063 : 032];
if (block_w3_we)
block_w3_reg <= block_new[031 : 000];
if (sword_ctr_we)
sword_ctr_reg <= sword_ctr_new;
if (round_ctr_we)
round_ctr_reg <= round_ctr_new;
if (ready_we)
ready_reg <= ready_new;
if (enc_ctrl_we)
enc_ctrl_reg <= enc_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// round_logic
//
// The logic needed to implement init, main and final rounds.
//----------------------------------------------------------------
always @*
begin : round_logic
reg [127 : 0] old_block, shiftrows_block, mixcolumns_block;
reg [127 : 0] addkey_init_block, addkey_main_block, addkey_final_block;
block_new = 128'h0;
muxed_sboxw = 32'h0;
block_w0_we = 1'b0;
block_w1_we = 1'b0;
block_w2_we = 1'b0;
block_w3_we = 1'b0;
old_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
shiftrows_block = shiftrows(old_block);
mixcolumns_block = mixcolumns(shiftrows_block);
addkey_init_block = addroundkey(block, round_key);
addkey_main_block = addroundkey(mixcolumns_block, round_key);
addkey_final_block = addroundkey(shiftrows_block, round_key);
case (update_type)
INIT_UPDATE:
begin
block_new = addkey_init_block;
block_w0_we = 1'b1;
block_w1_we = 1'b1;
block_w2_we = 1'b1;
block_w3_we = 1'b1;
end
SBOX_UPDATE:
begin
block_new = {new_sboxw, new_sboxw, new_sboxw, new_sboxw};
case (sword_ctr_reg)
2'h0:
begin
muxed_sboxw = block_w0_reg;
block_w0_we = 1'b1;
end
2'h1:
begin
muxed_sboxw = block_w1_reg;
block_w1_we = 1'b1;
end
2'h2:
begin
muxed_sboxw = block_w2_reg;
block_w2_we = 1'b1;
end
2'h3:
begin
muxed_sboxw = block_w3_reg;
block_w3_we = 1'b1;
end
endcase // case (sbox_mux_ctrl_reg)
end
MAIN_UPDATE:
begin
block_new = addkey_main_block;
block_w0_we = 1'b1;
block_w1_we = 1'b1;
block_w2_we = 1'b1;
block_w3_we = 1'b1;
end
FINAL_UPDATE:
begin
block_new = addkey_final_block;
block_w0_we = 1'b1;
block_w1_we = 1'b1;
block_w2_we = 1'b1;
block_w3_we = 1'b1;
end
default:
begin
end
endcase // case (update_type)
end // round_logic
//----------------------------------------------------------------
// sword_ctr
//
// The subbytes word counter with reset and increase logic.
//----------------------------------------------------------------
always @*
begin : sword_ctr
sword_ctr_new = 2'h0;
sword_ctr_we = 1'b0;
if (sword_ctr_rst)
begin
sword_ctr_new = 2'h0;
sword_ctr_we = 1'b1;
end
else if (sword_ctr_inc)
begin
sword_ctr_new = sword_ctr_reg + 1'b1;
sword_ctr_we = 1'b1;
end
end // sword_ctr
//----------------------------------------------------------------
// round_ctr
//
// The round counter with reset and increase logic.
//----------------------------------------------------------------
always @*
begin : round_ctr
round_ctr_new = 4'h0;
round_ctr_we = 1'b0;
if (round_ctr_rst)
begin
round_ctr_new = 4'h0;
round_ctr_we = 1'b1;
end
else if (round_ctr_inc)
begin
round_ctr_new = round_ctr_reg + 1'b1;
round_ctr_we = 1'b1;
end
end // round_ctr
//----------------------------------------------------------------
// encipher_ctrl
//
// The FSM that controls the encipher operations.
//----------------------------------------------------------------
always @*
begin: encipher_ctrl
reg [3 : 0] num_rounds;
// Default assignments.
sword_ctr_inc = 1'b0;
sword_ctr_rst = 1'b0;
round_ctr_inc = 1'b0;
round_ctr_rst = 1'b0;
ready_new = 1'b0;
ready_we = 1'b0;
update_type = NO_UPDATE;
enc_ctrl_new = CTRL_IDLE;
enc_ctrl_we = 1'b0;
if (keylen == AES_256_BIT_KEY)
begin
num_rounds = AES256_ROUNDS;
end
else
begin
num_rounds = AES128_ROUNDS;
end
case(enc_ctrl_reg)
CTRL_IDLE:
begin
if (next)
begin
round_ctr_rst = 1'b1;
ready_new = 1'b0;
ready_we = 1'b1;
enc_ctrl_new = CTRL_INIT;
enc_ctrl_we = 1'b1;
end
end
CTRL_INIT:
begin
round_ctr_inc = 1'b1;
sword_ctr_rst = 1'b1;
update_type = INIT_UPDATE;
enc_ctrl_new = CTRL_SBOX;
enc_ctrl_we = 1'b1;
end
CTRL_SBOX:
begin
sword_ctr_inc = 1'b1;
update_type = SBOX_UPDATE;
if (sword_ctr_reg == 2'h3)
begin
enc_ctrl_new = CTRL_MAIN;
enc_ctrl_we = 1'b1;
end
end
CTRL_MAIN:
begin
sword_ctr_rst = 1'b1;
round_ctr_inc = 1'b1;
if (round_ctr_reg < num_rounds)
begin
update_type = MAIN_UPDATE;
enc_ctrl_new = CTRL_SBOX;
enc_ctrl_we = 1'b1;
end
else
begin
update_type = FINAL_UPDATE;
ready_new = 1'b1;
ready_we = 1'b1;
enc_ctrl_new = CTRL_IDLE;
enc_ctrl_we = 1'b1;
end
end
default:
begin
// Empty. Just here to make the synthesis tool happy.
end
endcase // case (enc_ctrl_reg)
end // encipher_ctrl
endmodule // aes_encipher_block
//======================================================================
// EOF aes_encipher_block.v
//======================================================================
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate case/endcase w/ label list - no default
module main ();
reg error;
reg [2:0] val1,val2;
reg [2:0] result ;
always @( val1 or val2)
case (val1 & val2 )
3'b000,3'b001: result = 0;
3'b101: result = 1 ;
3'b110,3'b111,3'b100: result = 2;
endcase
initial
begin
error = 0;
val1 = 3'b0;
val2 = 3'b0;
#1 if(result !==0)
begin
$display("FAILED case 3.8B - case (expr) lab1: ");
error = 1;
end
val1 = 3'b101;
val2 = 3'b111;
#1 if(result !==1)
begin
$display("FAILED case 3.8B - case (expr) lab2: ");
error = 1;
end
val1 = 3'b110;
#1 if(result !==2)
begin
$display("FAILED case 3.8B - case (expr) lab1: ");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
//======================================================================
//
// blockmem2r1w.v
// --------------
// Synchronous block memory with two read ports and one write port.
// The data size is the same for both read and write operations.
//
// The memory is used in the modexp core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blockmem2r1w(
input wire clk,
input wire [07 : 0] read_addr0,
output wire [31 : 0] read_data0,
input wire [07 : 0] read_addr1,
output wire [31 : 0] read_data1,
input wire wr,
input wire [07 : 0] write_addr,
input wire [31 : 0] write_data
);
reg [31 : 0] mem [0 : 255];
reg [31 : 0] tmp_read_data0;
reg [31 : 0] tmp_read_data1;
assign read_data0 = tmp_read_data0;
assign read_data1 = tmp_read_data1;
always @ (posedge clk)
begin : reg_mem
if (wr)
mem[write_addr] <= write_data;
tmp_read_data0 <= mem[read_addr0];
tmp_read_data1 <= mem[read_addr1];
end
endmodule // blockmem2r1w
//======================================================================
// EOF blockmem2r1w.v
//======================================================================
|
//altpll_avalon avalon_use_separate_sysclk="NO" CBX_SINGLE_OUTPUT_FILE="ON" CBX_SUBMODULE_USED_PORTS="altpll:areset,clk,locked,inclk" address areset c0 c1 clk locked phasedone read readdata reset write writedata bandwidth_type="AUTO" clk0_divide_by=22579 clk0_duty_cycle=50 clk0_multiply_by=116000 clk0_phase_shift="0" clk1_divide_by=22579 clk1_duty_cycle=50 clk1_multiply_by=232000 clk1_phase_shift="0" compensate_clock="CLK0" device_family="MAX10" inclk0_input_frequency=44288 intended_device_family="MAX 10" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5
//VERSION_BEGIN 15.0 cbx_altclkbuf 2015:04:22:18:04:07:SJ cbx_altiobuf_bidir 2015:04:22:18:04:07:SJ cbx_altiobuf_in 2015:04:22:18:04:07:SJ cbx_altiobuf_out 2015:04:22:18:04:07:SJ cbx_altpll 2015:04:22:18:04:07:SJ cbx_altpll_avalon 2015:04:22:18:04:07:SJ cbx_cycloneii 2015:04:22:18:04:07:SJ cbx_lpm_add_sub 2015:04:22:18:04:07:SJ cbx_lpm_compare 2015:04:22:18:04:07:SJ cbx_lpm_counter 2015:04:22:18:04:07:SJ cbx_lpm_decode 2015:04:22:18:04:08:SJ cbx_lpm_mux 2015:04:22:18:04:08:SJ cbx_lpm_shiftreg 2015:04:22:18:04:08:SJ cbx_mgl 2015:04:22:18:06:50:SJ cbx_stratix 2015:04:22:18:04:08:SJ cbx_stratixii 2015:04:22:18:04:08:SJ cbx_stratixiii 2015:04:22:18:04:08:SJ cbx_stratixv 2015:04:22:18:04:08:SJ cbx_util_mgl 2015:04:22:18:04:08:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus II License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//altera_std_synchronizer CBX_SINGLE_OUTPUT_FILE="ON" clk din dout reset_n
//VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_stratixii 2015:04:22:18:04:08:SJ cbx_util_mgl 2015:04:22:18:04:08:SJ VERSION_END
//dffpipe CBX_SINGLE_OUTPUT_FILE="ON" DELAY=3 WIDTH=1 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
//VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_stratixii 2015:04:22:18:04:08:SJ cbx_util_mgl 2015:04:22:18:04:08:SJ VERSION_END
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
module wasca_altpll_0_dffpipe_l2c
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dffe4a;
reg [0:0] dffe5a;
reg [0:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe4a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a <= {1{1'b1}};
else if (clrn == 1'b0) dffe4a <= 1'b0;
else if (ena == 1'b1) dffe4a <= (d & (~ sclr));
// synopsys translate_off
initial
dffe5a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe5a <= {1{1'b1}};
else if (clrn == 1'b0) dffe5a <= 1'b0;
else if (ena == 1'b1) dffe5a <= (dffe4a & (~ sclr));
// synopsys translate_off
initial
dffe6a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a <= {1{1'b1}};
else if (clrn == 1'b0) dffe6a <= 1'b0;
else if (ena == 1'b1) dffe6a <= (dffe5a & (~ sclr));
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule //wasca_altpll_0_dffpipe_l2c
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module wasca_altpll_0_stdsync_sv6
(
clk,
din,
dout,
reset_n) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
wasca_altpll_0_dffpipe_l2c dffpipe3
(
.clock(clk),
.clrn(reset_n),
.d(din),
.q(wire_dffpipe3_q));
assign
dout = wire_dffpipe3_q;
endmodule //wasca_altpll_0_stdsync_sv6
//altpll bandwidth_type="AUTO" CBX_SINGLE_OUTPUT_FILE="ON" clk0_divide_by=22579 clk0_duty_cycle=50 clk0_multiply_by=116000 clk0_phase_shift="0" clk1_divide_by=22579 clk1_duty_cycle=50 clk1_multiply_by=232000 clk1_phase_shift="0" compensate_clock="CLK0" device_family="MAX10" inclk0_input_frequency=44288 intended_device_family="MAX 10" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 areset clk inclk locked
//VERSION_BEGIN 15.0 cbx_altclkbuf 2015:04:22:18:04:07:SJ cbx_altiobuf_bidir 2015:04:22:18:04:07:SJ cbx_altiobuf_in 2015:04:22:18:04:07:SJ cbx_altiobuf_out 2015:04:22:18:04:07:SJ cbx_altpll 2015:04:22:18:04:07:SJ cbx_cycloneii 2015:04:22:18:04:07:SJ cbx_lpm_add_sub 2015:04:22:18:04:07:SJ cbx_lpm_compare 2015:04:22:18:04:07:SJ cbx_lpm_counter 2015:04:22:18:04:07:SJ cbx_lpm_decode 2015:04:22:18:04:08:SJ cbx_lpm_mux 2015:04:22:18:04:08:SJ cbx_mgl 2015:04:22:18:06:50:SJ cbx_stratix 2015:04:22:18:04:08:SJ cbx_stratixii 2015:04:22:18:04:08:SJ cbx_stratixiii 2015:04:22:18:04:08:SJ cbx_stratixv 2015:04:22:18:04:08:SJ cbx_util_mgl 2015:04:22:18:04:08:SJ VERSION_END
//synthesis_resources = fiftyfivenm_pll 1 reg 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *)
module wasca_altpll_0_altpll_pfa2
(
areset,
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg pll_lock_sync;
wire [4:0] wire_pll7_clk;
wire wire_pll7_fbout;
wire wire_pll7_locked;
// synopsys translate_off
initial
pll_lock_sync = 0;
// synopsys translate_on
always @ ( posedge wire_pll7_locked or posedge areset)
if (areset == 1'b1) pll_lock_sync <= 1'b0;
else pll_lock_sync <= 1'b1;
fiftyfivenm_pll pll7
(
.activeclock(),
.areset(areset),
.clk(wire_pll7_clk),
.clkbad(),
.fbin(wire_pll7_fbout),
.fbout(wire_pll7_fbout),
.inclk(inclk),
.locked(wire_pll7_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll7.bandwidth_type = "auto",
pll7.clk0_divide_by = 22579,
pll7.clk0_duty_cycle = 50,
pll7.clk0_multiply_by = 116000,
pll7.clk0_phase_shift = "0",
pll7.clk1_divide_by = 22579,
pll7.clk1_duty_cycle = 50,
pll7.clk1_multiply_by = 232000,
pll7.clk1_phase_shift = "0",
pll7.compensate_clock = "clk0",
pll7.inclk0_input_frequency = 44288,
pll7.operation_mode = "normal",
pll7.pll_type = "auto",
pll7.lpm_type = "fiftyfivenm_pll";
assign
clk = {wire_pll7_clk[4:0]},
locked = (wire_pll7_locked & pll_lock_sync);
endmodule //wasca_altpll_0_altpll_pfa2
//synthesis_resources = fiftyfivenm_pll 1 reg 6
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module wasca_altpll_0
(
address,
areset,
c0,
c1,
clk,
locked,
phasedone,
read,
readdata,
reset,
write,
writedata) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
output c1;
input clk;
output locked;
output phasedone;
input read;
output [31:0] readdata;
input reset;
input write;
input [31:0] writedata;
wire wire_stdsync2_dout;
wire [4:0] wire_sd1_clk;
wire wire_sd1_locked;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
reg pfdena_reg;
wire wire_pfdena_reg_ena;
reg prev_reset;
wire w_locked;
wire w_pfdena;
wire w_phasedone;
wire w_pll_areset_in;
wire w_reset;
wire w_select_control;
wire w_select_status;
wasca_altpll_0_stdsync_sv6 stdsync2
(
.clk(clk),
.din(wire_sd1_locked),
.dout(wire_stdsync2_dout),
.reset_n((~ reset)));
wasca_altpll_0_altpll_pfa2 sd1
(
.areset((w_pll_areset_in | areset)),
.clk(wire_sd1_clk),
.inclk({{1{1'b0}}, clk}),
.locked(wire_sd1_locked));
// synopsys translate_off
initial
pfdena_reg = {1{1'b1}};
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) pfdena_reg <= {1{1'b1}};
else if (wire_pfdena_reg_ena == 1'b1) pfdena_reg <= writedata[1];
assign
wire_pfdena_reg_ena = (write & w_select_control);
// synopsys translate_off
initial
prev_reset = 0;
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) prev_reset <= 1'b0;
else prev_reset <= w_reset;
assign
c0 = wire_sd1_clk[0],
locked = wire_sd1_locked,
phasedone = 1'b0,
readdata = {{30{1'b0}}, (read & ((w_select_control & w_pfdena) | (w_select_status & w_phasedone))), (read & ((w_select_control & w_pll_areset_in) | (w_select_status & w_locked)))},
w_locked = wire_stdsync2_dout,
w_pfdena = pfdena_reg,
w_phasedone = 1'b1,
w_pll_areset_in = prev_reset,
w_reset = ((write & w_select_control) & writedata[0]),
w_select_control = ((~ address[1]) & address[0]),
w_select_status = ((~ address[1]) & (~ address[0]));
endmodule //wasca_altpll_0
//VALID FILE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31O_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A31O_PP_BLACKBOX_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31O_PP_BLACKBOX_V
|
// Testbench for ltcminer_icarus.v
`timescale 1ns/1ps
`ifdef SIM // Avoids wrong top selected if included in ISE/PlanAhead sources
module test_ltcminer ();
reg clk = 1'b0;
reg [31:0] cycle = 32'd0;
initial begin
clk = 0;
while(1)
begin
#5 clk = 1; #5 clk = 0;
end
end
always @ (posedge clk)
begin
cycle <= cycle + 32'd1;
end
// Running with default zero's for the data1..3 regs.
// tx_hash=553a4b69b43913a61b42013ce210f713eaa7332e48cda1bdf3b93b10161d0876 at 187,990 nS and
// final_hash (if SIM is defined) at 188,000 nS with golden_nonce_match flag NOT set since it is
// not a diff=32 share. To test golden_nonce, just tweak the target eg 31'hffffffff will match everything
// With serial input(at comm_clk_frequency=1_000_000), we get rx_done at t=70,220nS, however there is already a
// PBKDF2_SHA256_80_128 loaded in Xbuf (for nonce=00000001). The first final_hash at 188,000 nS is corrupted as
// the input data has changed from all 0's. The Xbuf starts salsa rom at t=188,000 but the nonce is incorrectly
// taken from the newly loaded data so once salsa in complete it also generates a corrupt final_hash at ~362,000 nS.
// Nonce is incremented then the newly loaded data starts PBKDF2_SHA256_80_128, so we must supply a nonce 1 less
// than the expected golden_nonce. The correct PBKDF2_SHA256_80_128 is ready at ~ 197,000 nS. We get final_hash for
// the corrupted work at ~362,000 nS then our required golden_nonce is at 536,180 nS.
// This is only really a problem for simulation. With live hashing we just lose 2 nonces every time getwork is
// loaded, which isn't a big deal.
wire RxD;
wire TxD;
wire extminer_rxd = 0;
wire extminer_txd;
wire [3:0] dip = 0;
wire [3:0] led;
wire TMP_SCL=1, TMP_SDA=1, TMP_ALERT=1;
parameter comm_clk_frequency = 1_000_000; // Speeds up serial loading enormously rx_done is at t=70,220nS
parameter baud_rate = 115_200;
ltcminer_icarus #(.comm_clk_frequency(comm_clk_frequency)) uut
(clk, RxD, TxD, led, extminer_rxd, extminer_txd, dip, TMP_SCL, TMP_SDA, TMP_ALERT);
// Send serial data - 84 bytes, matches on nonce 318f (included in data)
// NB starting nonce is 381e NOT 381f (see note above)
// NORMAL...
// reg [671:0] data = 672'h000007ff0000318e7e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000;
// DYNPLL...
reg [671:0] data = 672'h55aa07ff0000318e7e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000;
reg serial_send = 0;
wire serial_busy;
reg [31:0] data_32 = 0;
reg [31:0] start_cycle = 0;
serial_transmit #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(baud_rate)) sertx (.clk(clk), .TxD(RxD), .send(serial_send), .busy(serial_busy), .word(data_32));
// TUNE this according to comm_clk_frequency so we send a single getwork (else it gets overwritten with 0's)
// parameter stop_cycle = 7020; // For comm_clk_frequency=1_000_000
parameter stop_cycle = 0; // Use this to DISABLE sending data
always @ (posedge clk)
begin
serial_send <= 0; // Default
// Send data every time tx goes idle (NB the !serial_send is to prevent serial_send
// going high for two cycles since serial_busy arrives one cycle after serial_send)
if (cycle > 5 && cycle < stop_cycle && !serial_busy && !serial_send)
begin
serial_send <= 1;
data_32 <= data[671:640];
data <= { data[639:0], 32'd0 };
start_cycle <= cycle; // Remember each start cycle (makes debugging easier)
end
end
endmodule
`endif |
// DeBounce_v.v
//////////////////////// Button Debounceer ///////////////////////////////////////
//***********************************************************************
// FileName: DeBounce_v.v
// FPGA: MachXO2 7000HE
// IDE: Diamond 2.0.1
//
// HDL IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
// WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
// PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
// BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
// DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
// PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
// BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
// ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
// DIGI-KEY ALSO DISCLAIMS ANY LIABILITY FOR PATENT OR COPYRIGHT
// INFRINGEMENT.
//
// Version History
// Version 1.0 04/11/2013 Tony Storey
// Initial Public Release
// Small Footprint Button Debouncer
`timescale 1 ns / 100 ps
module DeBounce
(
input clk, n_reset, button_in, // inputs
output reg DB_out // output
);
//// ---------------- internal constants --------------
parameter N = 11 ; // (2^ (21-1) )/ 38 MHz = 32 ms debounce time
////---------------- internal variables ---------------
reg [N-1 : 0] q_reg; // timing regs
reg [N-1 : 0] q_next;
reg DFF1, DFF2; // input flip-flops
wire q_add; // control flags
wire q_reset;
//// ------------------------------------------------------
////contenious assignment for counter control
assign q_reset = (DFF1 ^ DFF2); // xor input flip flops to look for level change to reset counter
assign q_add = ~(q_reg[N-1]); // add to counter when q_reg msb is equal to 0
//// combo counter to manage q_next
always @ ( q_reset, q_add, q_reg)
begin
case( {q_reset , q_add})
2'b00 : q_next <= q_reg;
2'b01 : q_next <= q_reg + ({{(N-1){1'b0}}, 1'b1});
default : q_next <= { N {1'b0} };
endcase
end
//// Flip flop inputs and q_reg update
always @ ( posedge clk )
begin
if(n_reset == 1'b0)
begin
DFF1 <= 1'b0;
DFF2 <= 1'b0;
q_reg <= { N {1'b0} };
end
else
begin
DFF1 <= button_in;
DFF2 <= DFF1;
q_reg <= q_next;
end
end
//// counter control
always @ ( posedge clk )
begin
if(q_reg[N-1] == 1'b1)
DB_out <= DFF2;
else
DB_out <= DB_out;
end
endmodule
|
`default_nettype none
`include "core.h"
`include "irq.h"
`include "common.h"
module execute(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Event CTRL
input wire iEVENT_HOLD,
input wire iEVENT_START,
input wire iEVENT_IRQ_FRONT2BACK,
input wire iEVENT_IRQ_BACK2FRONT,
input wire iEVENT_END,
//Lock
output wire oEXCEPTION_LOCK,
//System Register
input wire [31:0] iSYSREG_PFLAGR,
output wire [31:0] oSYSREG_FLAGR,
//Pipeline
input wire iPREVIOUS_VALID,
input wire iPREVIOUS_FAULT_PAGEFAULT,
input wire iPREVIOUS_FAULT_PRIVILEGE_ERROR,
input wire iPREVIOUS_FAULT_INVALID_INST,
input wire iPREVIOUS_PAGING_ENA,
input wire iPREVIOUS_KERNEL_ACCESS,
input wire iPREVIOUS_BRANCH_PREDICT,
input wire [31:0] iPREVIOUS_BRANCH_PREDICT_ADDR,
input wire [31:0] iPREVIOUS_SYSREG_PSR,
input wire [63:0] iPREVIOUS_SYSREG_FRCR,
input wire [31:0] iPREVIOUS_SYSREG_TIDR,
input wire [31:0] iPREVIOUS_SYSREG_PDTR,
input wire [31:0] iPREVIOUS_SYSREG_KPDTR,
input wire iPREVIOUS_DESTINATION_SYSREG,
input wire [4:0] iPREVIOUS_DESTINATION,
input wire iPREVIOUS_WRITEBACK,
input wire iPREVIOUS_FLAGS_WRITEBACK,
input wire [4:0] iPREVIOUS_CMD,
input wire [3:0] iPREVIOUS_CC_AFE,
input wire [31:0] iPREVIOUS_SPR,
input wire [31:0] iPREVIOUS_SOURCE0,
input wire [31:0] iPREVIOUS_SOURCE1,
input wire [5:0] iPREVIOUS_ADV_DATA,
input wire [4:0] iPREVIOUS_SOURCE0_POINTER,
input wire [4:0] iPREVIOUS_SOURCE1_POINTER,
input wire iPREVIOUS_SOURCE0_SYSREG,
input wire iPREVIOUS_SOURCE1_SYSREG,
input wire iPREVIOUS_SOURCE1_IMM,
input wire iPREVIOUS_SOURCE0_FLAGS,
input wire iPREVIOUS_ADV_ACTIVE,
input wire iPREVIOUS_EX_SYS_REG,
input wire iPREVIOUS_EX_SYS_LDST,
input wire iPREVIOUS_EX_LOGIC,
input wire iPREVIOUS_EX_SHIFT,
input wire iPREVIOUS_EX_ADDER,
input wire iPREVIOUS_EX_MUL,
input wire iPREVIOUS_EX_SDIV,
input wire iPREVIOUS_EX_UDIV,
input wire iPREVIOUS_EX_LDST,
input wire iPREVIOUS_EX_BRANCH,
input wire [31:0] iPREVIOUS_PC,
output wire oPREVIOUS_LOCK,
//Load Store Pipe
output wire oDATAIO_REQ,
input wire iDATAIO_BUSY,
output wire [1:0] oDATAIO_ORDER, //00=Byte Order 01=2Byte Order 10= Word Order 11= None
output wire [3:0] oDATAIO_MASK, //[0]=Byte0, [1]=Byte1...
output wire oDATAIO_RW, //0=Read 1=Write
output wire [13:0] oDATAIO_ASID,
output wire [1:0] oDATAIO_MMUMOD,
output wire [2:0] oDATAIO_MMUPS,
output wire [31:0] oDATAIO_PDT,
output wire [31:0] oDATAIO_ADDR,
output wire [31:0] oDATAIO_DATA,
input wire iDATAIO_REQ,
input wire [11:0] iDATAIO_MMU_FLAGS,
input wire [31:0] iDATAIO_DATA,
//Writeback
output wire oNEXT_VALID,
output wire [31:0] oNEXT_DATA,
output wire [4:0] oNEXT_DESTINATION,
output wire oNEXT_DESTINATION_SYSREG,
output wire oNEXT_WRITEBACK,
output wire oNEXT_SPR_WRITEBACK,
output wire [31:0] oNEXT_SPR,
output wire [63:0] oNEXT_FRCR,
output wire [31:0] oNEXT_PC,
//System Register Write
output wire oPDTR_WRITEBACK,
//Branch
output wire [31:0] oBRANCH_ADDR,
output wire oJUMP_VALID,
output wire oINTR_VALID,
output wire oIDTSET_VALID,
output wire oPDTSET_VALID,
output wire oPSRSET_VALID,
output wire oFAULT_VALID,
output wire [6:0] oFAULT_NUM,
output wire [31:0] oFAULT_FI0R,
output wire [31:0] oFAULT_FI1R,
//Branch Predictor
output wire oBPREDICT_JUMP_INST,
output wire oBPREDICT_PREDICT, //Branch Guess
output wire oBPREDICT_HIT, //Guess Hit!
output wire oBPREDICT_JUMP, //Branch Active
output wire [31:0] oBPREDICT_JUMP_ADDR, //Branch Address
output wire [31:0] oBPREDICT_INST_ADDR, //Branch Instruction Memory Address
//Debug
input wire iDEBUG_CTRL_REQ,
input wire iDEBUG_CTRL_STOP,
input wire iDEBUG_CTRL_START,
output wire oDEBUG_CTRL_ACK,
output wire [31:0] oDEBUG_REG_OUT_FLAGR
);
/*********************************************************************************************************
Wire
*********************************************************************************************************/
localparam L_PARAM_STT_NORMAL = 3'h0;
localparam L_PARAM_STT_DIV_WAIT = 3'h1;
localparam L_PARAM_STT_LOAD = 3'h2;
localparam L_PARAM_STT_STORE = 3'h3;
localparam L_PARAM_STT_BRANCH = 3'h4;
localparam L_PARAM_STT_RELOAD = 3'h5;
localparam L_PARAM_STT_EXCEPTION = 3'h6;
localparam L_PARAM_STT_HALT = 3'h7;
reg b_valid;
reg [31:0] b_sysreg_psr;
reg [31:0] b_sysreg_tidr;
reg [31:0] b_sysreg_pdt;
reg [2:0] b_state;
reg b_load_store;
reg b_writeback;
reg b_destination_sysreg;
reg [4:0] b_destination;
reg [3:0] b_afe;
reg [31:0] b_r_data;
reg b_spr_writeback;
reg [31:0] b_r_spr;
reg [31:0] b_pc;
reg [63:0] b_frcr;
wire div_wait;
wire debugger_pipeline_stop;
wire lock_condition = (b_state != L_PARAM_STT_NORMAL) || div_wait || debugger_pipeline_stop;// || iDATAIO_BUSY;
wire io_lock_condition = iDATAIO_BUSY;
assign oPREVIOUS_LOCK = lock_condition || iEVENT_HOLD || iEVENT_HOLD;
wire [31:0] ex_module_source0;
wire [31:0] ex_module_source1;
wire forwarding_reg_gr_valid;
wire [31:0] forwarding_reg_gr_data;
wire [4:0] forwarding_reg_gr_dest;
wire forwarding_reg_gr_dest_sysreg;
wire forwarding_reg_spr_valid;
wire [31:0] forwarding_reg_spr_data;
wire forwarding_reg_frcr_valid;
wire [63:0] forwarding_reg_frcr_data;
wire [31:0] ex_module_spr;// = forwarding_reg_spr_data;
wire [31:0] ex_module_pdtr;
wire [31:0] ex_module_kpdtr;
wire [31:0] ex_module_tidr;
wire [31:0] ex_module_psr;
//System Register
wire sys_reg_sf = 1'b0;
wire sys_reg_of = 1'b0;
wire sys_reg_cf = 1'b0;
wire sys_reg_pf = 1'b0;
wire sys_reg_zf = 1'b0;
wire [4:0] sys_reg_flags = {sys_reg_sf, sys_reg_of, sys_reg_cf, sys_reg_pf, sys_reg_zf};
wire [31:0] sys_reg_data;
//Logic
wire logic_sf;
wire logic_of;
wire logic_cf;
wire logic_pf;
wire logic_zf;
wire [31:0] logic_data;
wire [4:0] logic_flags = {logic_sf, logic_of, logic_cf, logic_pf, logic_zf};
//Shift
wire shift_sf, shift_of, shift_cf, shift_pf, shift_zf;
wire [31:0] shift_data;
wire [4:0] shift_flags = {shift_sf, shift_of, shift_cf, shift_pf, shift_zf};
//Adder
wire [31:0] adder_data;
wire adder_sf, adder_of, adder_cf, adder_pf, adder_zf;
wire [4:0] adder_flags = {adder_sf, adder_of, adder_cf, adder_pf, adder_zf};
//Mul
wire [4:0] mul_flags;
wire [31:0] mul_data;
//Div
wire [31:0] div_out_data;
wire div_out_valid;
/*
//Load Store
wire ldst_spr_valid;
wire [31:0] ldst_spr;
wire ldst_pipe_rw;
wire [31:0] ldst_pipe_addr;
wire [31:0] ldst_pipe_pdt;
wire [31:0] ldst_pipe_data;
wire [1:0] ldst_pipe_order;
wire [1:0] load_pipe_shift;
wire [3:0] ldst_pipe_mask;
*/
//Branch
wire [31:0] branch_branch_addr;
wire branch_jump_valid;
wire branch_not_jump_valid;
wire branch_ib_valid;
wire branch_halt_valid;
//AFE
wire [31:0] result_data_with_afe;
//Flag
wire [4:0] sysreg_flags_register;
/*********************************************************************************************************
Debug Module
*********************************************************************************************************/
execute_debugger DEBUGGER(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//Debugger Port
.iDEBUG_CTRL_REQ(iDEBUG_CTRL_REQ),
.iDEBUG_CTRL_STOP(iDEBUG_CTRL_STOP),
.iDEBUG_CTRL_START(iDEBUG_CTRL_START),
.oDEBUG_CTRL_ACK(oDEBUG_CTRL_ACK),
.oDEBUG_REG_OUT_FLAGR(oDEBUG_REG_OUT_FLAGR),
//Pipeline
.oPIPELINE_STOP(debugger_pipeline_stop),
//Registers
.iREGISTER_FLAGR(sysreg_flags_register),
//Busy
.iBUSY(lock_condition)
);
/*********************************************************************************************************
Forwarding
*********************************************************************************************************/
execute_forwarding_register FORWARDING_REGISTER(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iEVENT_HOLD || iEVENT_START || iRESET_SYNC),
//Writeback - General Register
.iWB_GR_VALID(b_valid && b_writeback),
.iWB_GR_DATA(result_data_with_afe),
.iWB_GR_DEST(b_destination),
.iWB_GR_DEST_SYSREG(b_destination_sysreg),
//Writeback - Stack Point Register
.iWB_SPR_VALID(b_valid && b_spr_writeback),
.iWB_SPR_DATA(b_r_spr),
//Writeback Auto - Stack Point Register
.iWB_AUTO_SPR_VALID(b_valid && b_destination_sysreg && b_writeback && b_destination == `SYSREG_SPR),
.iWB_AUTO_SPR_DATA(result_data_with_afe),
//Current -Stak Point Register
.iCUUR_SPR_DATA(iPREVIOUS_SPR),
//Writeback - FRCR
.iWB_FRCR_VALID(b_valid),
.iWB_FRCR_DATA(b_frcr),
//Current - FRCR
.iCUUR_FRCR_DATA(iPREVIOUS_SYSREG_FRCR),
//Fowerding Register Output
.oFDR_GR_VALID(forwarding_reg_gr_valid),
.oFDR_GR_DATA(forwarding_reg_gr_data),
.oFDR_GR_DEST(forwarding_reg_gr_dest),
.oFDR_GR_DEST_SYSREG(forwarding_reg_gr_dest_sysreg),
//Fowerding Register Output
.oFDR_SPR_VALID(forwarding_reg_spr_valid),
.oFDR_SPR_DATA(forwarding_reg_spr_data),
//Forwerding Register Output
.oFDR_FRCR_VALID(forwarding_reg_frcr_valid),
.oFDR_FRCR_DATA(forwarding_reg_frcr_data)
);
execute_forwarding FORWARDING_RS0(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iEVENT_HOLD || iEVENT_START || iRESET_SYNC),
//Writeback - General Register
.iWB_GR_VALID(b_valid && b_writeback),
.iWB_GR_DATA(result_data_with_afe),
.iWB_GR_DEST(b_destination),
.iWB_GR_DEST_SYSREG(b_destination_sysreg),
//Writeback - Stack Point Register
.iWB_SPR_VALID(b_valid && b_spr_writeback),
.iWB_SPR_DATA(b_r_spr),
//Writeback - FRCR
.iWR_FRCR_VALID(b_valid),
.iWR_FRCR_DATA(b_frcr),
//Previous Writeback - General Register
.iPREV_WB_GR_VALID(forwarding_reg_gr_valid),
.iPREV_WB_GR_DATA(forwarding_reg_gr_data),
.iPREV_WB_GR_DEST(forwarding_reg_gr_dest),
.iPREV_WB_GR_DEST_SYSREG(forwarding_reg_gr_dest_sysreg),
//Previous Writeback - Stack Point Register
.iPREV_WB_SPR_VALID(forwarding_reg_spr_valid),
.iPREV_WB_SPR_DATA(forwarding_reg_spr_data),
//Previous Writeback - FRCR
.iPREV_WB_FRCR_VALID(forwarding_reg_frcr_valid),
.iPREV_WB_FRCR_DATA(forwarding_reg_frcr_data),
//Source
.iPREVIOUS_SOURCE_SYSREG(iPREVIOUS_SOURCE0_SYSREG),
.iPREVIOUS_SOURCE_POINTER(iPREVIOUS_SOURCE0_POINTER),
.iPREVIOUS_SOURCE_IMM(1'b0/*iPREVIOUS_SOURCE0_IMM*/),
.iPREVIOUS_SOURCE_DATA(iPREVIOUS_SOURCE0),
.iPREVIOUS_SOURCE_PDTR(iPREVIOUS_SYSREG_PDTR),
.iPREVIOUS_SOURCE_KPDTR(iPREVIOUS_SYSREG_KPDTR),
.iPREVIOUS_SOURCE_TIDR(iPREVIOUS_SYSREG_TIDR),
.iPREVIOUS_SOURCE_PSR(iPREVIOUS_SYSREG_PSR),
//Output
.oNEXT_SOURCE_DATA(ex_module_source0),
.oNEXT_SOURCE_SPR(ex_module_spr),
.oNEXT_SOURCE_PDTR(ex_module_pdtr),
.oNEXT_SOURCE_KPDTR(ex_module_kpdtr),
.oNEXT_SOURCE_TIDR(ex_module_tidr),
.oNEXT_SOURCE_PSR(ex_module_psr)
);
/*
assign ex_module_pdtr = iPREVIOUS_SYSREG_PDTR;
assign ex_module_tidr = iPREVIOUS_SYSREG_TIDR;
assign ex_module_psr = iPREVIOUS_SYSREG_PSR;
*/
execute_forwarding FORWARDING_RS1(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iEVENT_HOLD || iEVENT_START || iRESET_SYNC),
//Writeback - General Register
.iWB_GR_VALID(b_valid && b_writeback),
.iWB_GR_DATA(result_data_with_afe),
.iWB_GR_DEST(b_destination),
.iWB_GR_DEST_SYSREG(b_destination_sysreg),
//Writeback - Stack Point Register
.iWB_SPR_VALID(b_valid && b_spr_writeback),
.iWB_SPR_DATA(b_r_spr),
//Writeback - FRCR
.iWR_FRCR_VALID(b_valid),
.iWR_FRCR_DATA(b_frcr),
//Previous Writeback - General Register
.iPREV_WB_GR_VALID(forwarding_reg_gr_valid),
.iPREV_WB_GR_DATA(forwarding_reg_gr_data),
.iPREV_WB_GR_DEST(forwarding_reg_gr_dest),
.iPREV_WB_GR_DEST_SYSREG(forwarding_reg_gr_dest_sysreg),
//Previous Writeback - Stack Point Register
.iPREV_WB_SPR_VALID(forwarding_reg_spr_valid),
.iPREV_WB_SPR_DATA(forwarding_reg_spr_data),
//Previous Writeback - FRCR
.iPREV_WB_FRCR_VALID(forwarding_reg_frcr_valid),
.iPREV_WB_FRCR_DATA(forwarding_reg_frcr_data),
//Source
.iPREVIOUS_SOURCE_SYSREG(iPREVIOUS_SOURCE1_SYSREG),
.iPREVIOUS_SOURCE_POINTER(iPREVIOUS_SOURCE1_POINTER),
.iPREVIOUS_SOURCE_IMM(iPREVIOUS_SOURCE1_IMM),
.iPREVIOUS_SOURCE_DATA(iPREVIOUS_SOURCE1),
.iPREVIOUS_SOURCE_PDTR(iPREVIOUS_SYSREG_PDTR),
.iPREVIOUS_SOURCE_KPDTR(iPREVIOUS_SYSREG_KPDTR),
.iPREVIOUS_SOURCE_TIDR(iPREVIOUS_SYSREG_TIDR),
.iPREVIOUS_SOURCE_PSR(iPREVIOUS_SYSREG_PSR),
//Output
.oNEXT_SOURCE_DATA(ex_module_source1),
.oNEXT_SOURCE_SPR(),
.oNEXT_SOURCE_PDTR(),
.oNEXT_SOURCE_KPDTR(),
.oNEXT_SOURCE_TIDR(),
.oNEXT_SOURCE_PSR()
);
/****************************************
Flag Register
****************************************/
execute_flag_register REG_FLAG(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//Control
.iCTRL_HOLD(iEVENT_HOLD || iEVENT_HOLD || iEVENT_START),
//PFLAGR
.iPFLAGR_VALID(iEVENT_IRQ_BACK2FRONT),
.iPFLAGR(iSYSREG_PFLAGR[4:0]),
//Prev
.iPREV_INST_VALID(iPREVIOUS_VALID),
.iPREV_BUSY(lock_condition),
.iPREV_FLAG_WRITE(iPREVIOUS_FLAGS_WRITEBACK),
//Shift
.iSHIFT_VALID(iPREVIOUS_EX_SHIFT),
.iSHIFT_FLAG(shift_flags),
//Adder
.iADDER_VALID(iPREVIOUS_EX_ADDER),
.iADDER_FLAG(adder_flags),
//Mul
.iMUL_VALID(iPREVIOUS_EX_MUL),
.iMUL_FLAG(mul_flags),
//Logic
.iLOGIC_VALID(iPREVIOUS_EX_LOGIC),
.iLOGIC_FLAG(logic_flags),
//oUTPUT
.oFLAG(sysreg_flags_register)
);
/*********************************************************************************************************
Execute
*********************************************************************************************************/
/****************************************
Logic
****************************************/
wire [4:0] logic_cmd;
execute_logic_decode EXE_LOGIC_DECODER(
.iPREV_INST(iPREVIOUS_CMD),
.oNEXT_INST(logic_cmd)
);
execute_logic #(32) EXE_LOGIC(
.iCONTROL_CMD(logic_cmd),
.iDATA_0(ex_module_source0),
.iDATA_1(ex_module_source1),
.oDATA(logic_data),
.oSF(logic_sf),
.oOF(logic_of),
.oCF(logic_cf),
.oPF(logic_pf),
.oZF(logic_zf)
);
/****************************************
Shift
****************************************/
wire [2:0] shift_cmd;
execute_shift_decode EXE_SHIFT_DECODER(
.iPREV_INST(iPREVIOUS_CMD),
.oNEXT_INST(shift_cmd)
);
execute_shift #(32) EXE_SHIFT(
.iCONTROL_MODE(shift_cmd),
.iDATA_0(ex_module_source0),
.iDATA_1(ex_module_source1),
.oDATA(shift_data),
.oSF(shift_sf),
.oOF(shift_of),
.oCF(shift_cf),
.oPF(shift_pf),
.oZF(shift_zf)
);
/****************************************
Adder
****************************************/
execute_adder #(32) EXE_ADDER(
.iDATA_0(ex_module_source0),
.iDATA_1(ex_module_source1),
.iADDER_CMD(iPREVIOUS_CMD),
.oDATA(adder_data),
.oSF(adder_sf),
.oOF(adder_of),
.oCF(adder_cf),
.oPF(adder_pf),
.oZF(adder_zf)
);
/****************************************
Mul
****************************************/
execute_mul EXE_MUL(
.iCMD(iPREVIOUS_CMD),
.iDATA_0(ex_module_source0),
.iDATA_1(ex_module_source1),
.oDATA(mul_data),
.oFLAGS(mul_flags)
);
/*
wire [4:0] mul_flags = (iPREVIOUS_CMD == `EXE_MUL_MULH)? {mul_sf_h, mul_of_h, mul_cf_h, mul_pf_h, mul_zf_h} : {mul_sf_l, mul_of_l, mul_cf_l, mul_pf_l, mul_zf_l};
wire [31:0] mul_data = (iPREVIOUS_CMD == `EXE_MUL_MULH)? mul_tmp[63:32] : mul_tmp[31:0];
execute_mul_booth32 EXE_MUL_BOOTH(
//iDATA
.iDATA_0(ex_module_source0),
.iDATA_1(ex_module_source1),
//oDATA
.oDATA(mul_tmp),
.oHSF(mul_sf_h),
.oHCF(mul_cf_h),
.oHOF(mul_of_h),
.oHPF(mul_pf_h),
.oHZF(mul_zf_h),
.oLSF(mul_sf_l),
.oLCF(mul_cf_l),
.oLOF(mul_of_l),
.oLPF(mul_pf_l),
.oLZF(mul_zf_l)
);
*/
/****************************************
Div
****************************************/
execute_div EXE_DIV(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iEVENT_HOLD || iEVENT_START || iRESET_SYNC),
//FLAG
.oFLAG_WAITING_DIV(div_wait),
//Prev
.iPREV_VALID(iPREVIOUS_VALID),
.iPREV_UDIV(iPREVIOUS_EX_UDIV),
.iPREV_SDIV(iPREVIOUS_EX_SDIV),
.iCMD(iPREVIOUS_CMD),
//iDATA
.iDATA_0(ex_module_source0),
.iDATA_1(ex_module_source1),
//oDATA
.iBUSY(lock_condition),
.oDATA_VALID(div_out_valid),
.oDATA(div_out_data)
);
/****************************************
Address calculate(Load Store)
****************************************/
//Load Store
wire ldst_spr_valid;
wire [31:0] ldst_spr;
wire ldst_pipe_rw;
wire [31:0] ldst_pipe_pdt;
wire [31:0] ldst_pipe_addr;
wire [31:0] ldst_pipe_data;
wire [1:0] ldst_pipe_order;
wire [1:0] load_pipe_shift;
wire [3:0] ldst_pipe_mask;
execute_adder_calc LDST_CALC_ADDR(
//Prev
.iCMD(iPREVIOUS_CMD),
.iLOADSTORE_MODE(iPREVIOUS_EX_LDST),
.iSOURCE0(ex_module_source0),
.iSOURCE1(ex_module_source1),
.iADV_ACTIVE(iPREVIOUS_ADV_ACTIVE),
//.iADV_DATA({26'h0, iPREVIOUS_ADV_DATA}),
.iADV_DATA({{26{iPREVIOUS_ADV_DATA[5]}}, iPREVIOUS_ADV_DATA}),
.iSPR(ex_module_spr),
.iPSR(ex_module_psr),
.iPDTR(ex_module_pdtr),
.iKPDTR(ex_module_kpdtr),
.iPC(iPREVIOUS_PC - 32'h4),
//Output - Writeback
.oOUT_SPR_VALID(ldst_spr_valid),
.oOUT_SPR(ldst_spr),
.oOUT_DATA(),
//Output - LDST Pipe
.oLDST_RW(ldst_pipe_rw),
.oLDST_PDT(ldst_pipe_pdt),
.oLDST_ADDR(ldst_pipe_addr),
.oLDST_DATA(ldst_pipe_data),
.oLDST_ORDER(ldst_pipe_order),
.oLDST_MASK(ldst_pipe_mask),
.oLOAD_SHIFT(load_pipe_shift)
);
//Load Store
wire [1:0] load_shift;
wire [3:0] load_mask;
execute_load_store STAGE_LDST(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//Event CTRL
.iEVENT_HOLD(iEVENT_HOLD),
.iEVENT_START(iEVENT_START),
.iEVENT_IRQ_FRONT2BACK(iEVENT_IRQ_FRONT2BACK),
.iEVENT_IRQ_BACK2FRONT(iEVENT_IRQ_BACK2FRONT),
.iEVENT_END(iEVENT_END),
//State
.iSTATE_NORMAL(b_state == L_PARAM_STT_NORMAL),
.iSTATE_LOAD(b_state == L_PARAM_STT_LOAD),
.iSTATE_STORE(b_state == L_PARAM_STT_STORE),
/*************************************
Previous
*************************************/
//Previous - PREDICT
.iPREV_VALID(iPREVIOUS_VALID),
.iPREV_EX_LDST(iPREVIOUS_EX_LDST),
//System Register
.iPREV_PSR(ex_module_psr),
.iPREV_TIDR(ex_module_tidr),
//Writeback
.iPREV_SPR_VALID(ldst_spr_valid),
.iPREV_SPR(ldst_spr),
//Output - LDST Pipe
.iPREV_LDST_RW(ldst_pipe_rw),
.iPREV_LDST_PDT(ldst_pipe_pdt),
.iPREV_LDST_ADDR(ldst_pipe_addr),
.iPREV_LDST_DATA(ldst_pipe_data),
.iPREV_LDST_ORDER(ldst_pipe_order),
.iPREV_LDST_MASK(ldst_pipe_mask),
.iPREV_LOAD_SHIFT(load_pipe_shift),
/*************************************
MA
*************************************/
//Output - LDST Pipe
.oLDST_REQ(oDATAIO_REQ),
.iLDST_BUSY(iEVENT_HOLD || io_lock_condition),
.oLDST_RW(oDATAIO_RW),
.oLDST_PDT(oDATAIO_PDT),
.oLDST_ADDR(oDATAIO_ADDR),
.oLDST_DATA(oDATAIO_DATA),
.oLDST_ORDER(oDATAIO_ORDER),
.oLDST_MASK(oDATAIO_MASK),
.oLDST_ASID(oDATAIO_ASID),
.oLDST_MMUMOD(oDATAIO_MMUMOD),
.oLDST_MMUPS(oDATAIO_MMUPS),
.iLDST_VALID(iDATAIO_REQ),
/*************************************
Next
*************************************/
//Next
.iNEXT_BUSY(lock_condition),
.oNEXT_VALID(),
.oNEXT_SPR_VALID(),
.oNEXT_SPR(),
.oNEXT_SHIFT(load_shift), //It's for after load data sigals
.oNEXT_MASK(load_mask) //It's for after load data sigals
);
//Load Data Mask and Shft
wire [31:0] load_data;
execute_load_data LOAD_MASK(
.iMASK(load_mask),
.iSHIFT(load_shift),
.iDATA(iDATAIO_DATA),
.oDATA(load_data)
);
/****************************************
System Register
****************************************/
wire sysreg_ctrl_idt_valid;
wire sysreg_ctrl_pdt_valid;
wire sysreg_ctrl_psr_valid;
wire [31:0] sysreg_reload_addr;
execute_sys_reg EXE_SYS_REG(
.iCMD(iPREVIOUS_CMD),
.iPC(iPREVIOUS_PC),
.iSOURCE0(ex_module_source0),
.iSOURCE1(ex_module_source1),
.oOUT(sys_reg_data),
.oCTRL_IDT_VALID(sysreg_ctrl_idt_valid),
.oCTRL_PDT_VALID(sysreg_ctrl_pdt_valid),
.oCTRL_PSR_VALID(sysreg_ctrl_psr_valid),
.oCTRL_RELOAD_ADDR(sysreg_reload_addr)
);
/****************************************
Jump
****************************************/
//Branch
execute_branch EXE_BRANCH(
.iDATA_0(ex_module_source0),
.iDATA_1(ex_module_source1),
.iPC(iPREVIOUS_PC - 32'h4),
.iFLAG(sysreg_flags_register),
.iCC(iPREVIOUS_CC_AFE),
.iCMD(iPREVIOUS_CMD),
.oBRANCH_ADDR(branch_branch_addr),
.oJUMP_VALID(branch_jump_valid),
.oNOT_JUMP_VALID(branch_not_jump_valid),
.oIB_VALID(branch_ib_valid),
.oHALT_VALID(branch_halt_valid)
);
//Branch Predict
wire branch_with_predict_predict_ena;
wire branch_with_predict_predict_hit;
wire branch_with_predict_branch_valid;
wire branch_with_predict_ib_valid;
wire [31:0] branch_with_predict_jump_addr;
//Branch Predicter
execute_branch_predict EXE_BRANCH_PREDICT(
//State
.iSTATE_NORMAL(b_state == L_PARAM_STT_NORMAL),
//Previous - PREDICT
.iPREV_VALID(iPREVIOUS_VALID),
.iPREV_EX_BRANCH(iPREVIOUS_EX_BRANCH),
.iPREV_BRANCH_PREDICT_ENA(iPREVIOUS_BRANCH_PREDICT),
.iPREV_BRANCH_PREDICT_ADDR(iPREVIOUS_BRANCH_PREDICT_ADDR),
//BRANCH
.iPREV_BRANCH_VALID(branch_jump_valid),
.iPREV_BRANCH_IB_VALID(branch_ib_valid),
.iPREV_JUMP_ADDR(branch_branch_addr),
//Next
.iNEXT_BUSY(lock_condition),
.oNEXT_PREDICT_HIT(branch_with_predict_predict_hit)
);
wire branch_valid_with_predict_miss = branch_not_jump_valid && iPREVIOUS_BRANCH_PREDICT; //not need jump, but predict jump
wire branch_valid_with_predict_addr_miss = branch_jump_valid && !(iPREVIOUS_BRANCH_PREDICT && branch_with_predict_predict_hit); //need jump, but predict addr is diffelent (predict address diffelent)
wire branch_valid_with_predict = branch_valid_with_predict_miss || branch_valid_with_predict_addr_miss;
//Jump
wire jump_stage_predict_ena;
wire jump_stage_predict_hit;
wire jump_stage_jump_valid;
wire [31:0] jump_stage_jump_addr;
wire jump_normal_jump_inst;
wire jump_stage_branch_valid;
wire jump_stage_branch_ib_valid;
wire jump_stage_sysreg_idt_valid;
wire jump_stage_sysreg_pdt_valid;
wire jump_stage_sysreg_psr_valid;
execute_jump STAGE_JUMP(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//Event CTRL
.iEVENT_HOLD(iEVENT_HOLD),
.iEVENT_START(iEVENT_START),
.iEVENT_IRQ_FRONT2BACK(iEVENT_IRQ_FRONT2BACK),
.iEVENT_IRQ_BACK2FRONT(iEVENT_IRQ_BACK2FRONT),
.iEVENT_END(iEVENT_END),
//State
.iSTATE_NORMAL(b_state == L_PARAM_STT_NORMAL),
//Previous - PREDICT
.iPREV_VALID(iPREVIOUS_VALID),
.iPREV_EX_BRANCH(iPREVIOUS_EX_BRANCH),
.iPREV_EX_SYS_REG(iPREVIOUS_EX_SYS_REG),
.iPREV_PC(iPREVIOUS_PC),
.iPREV_BRANCH_PREDICT_ENA(iPREVIOUS_BRANCH_PREDICT),
.iPREV_BRANCH_PREDICT_HIT(branch_with_predict_predict_hit),
.iPREV_BRANCH_NORMAL_JUMP_INST(branch_jump_valid || branch_not_jump_valid), //ignore branch predict result
//BRANCH
.iPREV_BRANCH_PREDICT_MISS_VALID(branch_valid_with_predict_miss),
.iPREV_BRANCH_PREDICT_ADDR_MISS_VALID(branch_valid_with_predict_addr_miss),
.iPREV_BRANCH_IB_VALID(branch_ib_valid),
.iPREV_BRANCH_ADDR(branch_branch_addr),
//SYSREG JUMP
.iPREV_SYSREG_IDT_VALID(sysreg_ctrl_idt_valid),
.iPREV_SYSREG_PDT_VALID(sysreg_ctrl_pdt_valid),
.iPREV_SYSREG_PSR_VALID(sysreg_ctrl_psr_valid),
.iPREV_SYSREG_ADDR(sysreg_reload_addr),
/*************************************
Next
*************************************/
//Next
.iNEXT_BUSY(lock_condition),
.oNEXT_PREDICT_ENA(jump_stage_predict_ena),
.oNEXT_PREDICT_HIT(jump_stage_predict_hit),
.oNEXT_JUMP_VALID(jump_stage_jump_valid),
.oNEXT_JUMP_ADDR(jump_stage_jump_addr),
//for Branch Predictor
.oNEXT_NORMAL_JUMP_INST(jump_normal_jump_inst), //ignore branch predict result
//Kaind of Jump
.oNEXT_TYPE_BRANCH_VALID(jump_stage_branch_valid),
.oNEXT_TYPE_BRANCH_IB_VALID(jump_stage_branch_ib_valid),
.oNEXT_TYPE_SYSREG_IDT_VALID(jump_stage_sysreg_idt_valid),
.oNEXT_TYPE_SYSREG_PDT_VALID(jump_stage_sysreg_pdt_valid),
.oNEXT_TYPE_SYSREG_PSR_VALID(jump_stage_sysreg_psr_valid)
);
/*********************************************************************************************************
Exception
*********************************************************************************************************/
wire except_inst_valid;
wire [6:0] except_inst_num;
wire except_ldst_valid;
wire [6:0] except_ldst_num;
execute_exception_check_inst EXE_EXCEPTION_INST(
//Execute Module State
.iPREV_STATE_NORMAL(b_state == L_PARAM_STT_NORMAL),
//Previous Instruxtion
.iPREV_FAULT_PAGEFAULT(iPREVIOUS_FAULT_PAGEFAULT),
.iPREV_FAULT_PRIVILEGE_ERROR(iPREVIOUS_FAULT_PRIVILEGE_ERROR),
.iPREV_FAULT_INVALID_INST(iPREVIOUS_FAULT_INVALID_INST),
.iPREV_FAULT_DIVIDE_ZERO((iPREVIOUS_EX_SDIV || iPREVIOUS_EX_UDIV) && (ex_module_source1 == 32'h0)),
//Output Exception
.oEXCEPT_VALID(except_inst_valid),
.oEXCEPT_NUM(except_inst_num)
);
execute_exception_check_ldst EXE_EXCEPTION_LDST(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//Event CTRL
.iEVENT_HOLD(iEVENT_HOLD),
.iEVENT_START(iEVENT_START),
.iEVENT_IRQ_FRONT2BACK(iEVENT_IRQ_FRONT2BACK),
.iEVENT_IRQ_BACK2FRONT(iEVENT_IRQ_BACK2FRONT),
.iEVENT_END(iEVENT_END),
//Execute Module State
.iPREV_STATE_NORMAL(b_state == L_PARAM_STT_NORMAL),
.iPREV_STATE_LDST(b_state == L_PARAM_STT_LOAD),
//Previous Instruxtion
.iPREV_VALID(b_state == L_PARAM_STT_NORMAL && iPREVIOUS_VALID && !lock_condition),
.iPREV_KERNEL_ACCESS(iPREVIOUS_KERNEL_ACCESS),
.iPREV_PAGING_ENA(iPREVIOUS_PAGING_ENA),
.iPREV_LDST_RW(ldst_pipe_rw),
//Load Store
.iLDST_VALID(iDATAIO_REQ),
.iLDST_MMU_FLAG(iDATAIO_MMU_FLAGS),
//Output Exception
.oEXCEPT_VALID(except_ldst_valid),
.oEXCEPT_NUM(except_ldst_num)
);
wire exception_valid;
wire [6:0] exception_num;
wire [31:0] exception_fi0r;
wire [31:0] exception_fi1r;
execute_exception STAGE_EXCEPTION(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//Event CTRL
.iEVENT_HOLD(iEVENT_HOLD),
.iEVENT_START(iEVENT_START),
.iEVENT_IRQ_FRONT2BACK(iEVENT_IRQ_FRONT2BACK),
.iEVENT_IRQ_BACK2FRONT(iEVENT_IRQ_BACK2FRONT),
.iEVENT_END(iEVENT_END),
//Execute Module State
.iPREV_STATE_NORMAL(b_state == L_PARAM_STT_NORMAL),
.iPREV_STATE_LDST(b_state == L_PARAM_STT_LOAD),
//Previous Instruxtion
.iPREV_VALID(b_state == L_PARAM_STT_NORMAL && iPREVIOUS_VALID && !lock_condition),
.iPREV_KERNEL_ACCESS(iPREVIOUS_KERNEL_ACCESS),
.iPREV_PC(iPREVIOUS_PC),
//Instruction Exception
.iEXCEPT_INST_VALID(except_inst_valid),
.iEXCEPT_INST_NUM(except_inst_num),
//Load Store Exception
.iEXCEPT_LDST_VALID(except_ldst_valid),
.iEXCEPT_LDST_NUM(except_ldst_num),
//Output Exception
.oEXCEPT_VALID(exception_valid),
.oEXCEPT_NUM(exception_num),
.oEXCEPT_FI0R(exception_fi0r),
.oEXCEPT_FI1R(exception_fi1r)
);
/*********************************************************************************************************
Pipelined Register
*********************************************************************************************************/
/****************************************
State
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_state <= L_PARAM_STT_NORMAL;
end
else if(iEVENT_HOLD || iEVENT_START || iRESET_SYNC)begin
b_state <= L_PARAM_STT_NORMAL;
end
else begin
case(b_state)
L_PARAM_STT_NORMAL:
begin
if(iPREVIOUS_VALID && !lock_condition)begin
//Fault Check
if(except_inst_valid)begin
b_state <= L_PARAM_STT_EXCEPTION;
end
//Execute
else begin
//Div instruction
if(iPREVIOUS_EX_SDIV || iPREVIOUS_EX_UDIV)begin
b_state <= L_PARAM_STT_DIV_WAIT;
end
//Load Store
else if(iPREVIOUS_EX_LDST)begin
if(!ldst_pipe_rw)begin
b_state <= L_PARAM_STT_LOAD;
end
else begin
b_state <= L_PARAM_STT_STORE;
end
end
//Branch
else if(iPREVIOUS_EX_BRANCH)begin
//Halt
if(branch_halt_valid)begin
b_state <= L_PARAM_STT_HALT;
end
//Interrupt Return Branch
else if(branch_ib_valid)begin
b_state <= L_PARAM_STT_BRANCH;
end
//Branch(with Branch predict)
else if(branch_valid_with_predict)begin
b_state <= L_PARAM_STT_BRANCH;
end
end
//System Register(for need re-load instructions)
if(iPREVIOUS_EX_SYS_REG)begin
if(sysreg_ctrl_idt_valid || sysreg_ctrl_pdt_valid || sysreg_ctrl_psr_valid)begin
b_state <= L_PARAM_STT_RELOAD;
end
end
end
end
end
L_PARAM_STT_DIV_WAIT:
begin
if(div_out_valid)begin
b_state <= L_PARAM_STT_NORMAL;
end
end
L_PARAM_STT_LOAD:
begin
if(iDATAIO_REQ)begin
//Pagefault || Exception Check(Load)
if(except_ldst_valid)begin
b_state <= L_PARAM_STT_EXCEPTION;
end
//Non Error
else begin
b_state <= L_PARAM_STT_NORMAL;
end
end
end
L_PARAM_STT_STORE:
begin
if(iDATAIO_REQ)begin
//Pagefault
//Exception Check(Load)
if(except_ldst_valid)begin
b_state <= L_PARAM_STT_EXCEPTION;
end
//Non Error
else begin
b_state <= L_PARAM_STT_NORMAL;
end
end
end
L_PARAM_STT_BRANCH:
begin
//Branch Wait
b_state <= L_PARAM_STT_BRANCH;
end
L_PARAM_STT_RELOAD:
begin
//Branch Wait
b_state <= L_PARAM_STT_RELOAD;
end
L_PARAM_STT_EXCEPTION:
begin
b_state <= L_PARAM_STT_EXCEPTION;
end
L_PARAM_STT_HALT:
begin
b_state <= L_PARAM_STT_HALT;
end
endcase
end
end //state always
/****************************************
For PC
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_pc <= 32'h0;
end
else if(iEVENT_HOLD || iEVENT_START || iRESET_SYNC)begin
b_pc <= 32'h0;
end
else begin
case(b_state)
L_PARAM_STT_NORMAL:
begin
if(iPREVIOUS_VALID && !lock_condition)begin
b_pc <= iPREVIOUS_PC;
end
end
default:
begin
b_pc <= b_pc;
end
endcase
end
end
/****************************************
For FRCR
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_frcr <= 64'h0;
end
else if(iEVENT_HOLD || iEVENT_START || iRESET_SYNC)begin
b_frcr <= 64'h0;
end
else begin
case(b_state)
L_PARAM_STT_NORMAL:
begin
if(iPREVIOUS_VALID && !lock_condition)begin
b_frcr <= iPREVIOUS_SYSREG_FRCR;
end
end
default:
begin
b_frcr <= b_frcr;
end
endcase
end
end
/****************************************
Result Data
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_r_data <= 32'h0;
end
else if(iEVENT_HOLD || iEVENT_START || iRESET_SYNC)begin
b_r_data <= 32'h0;
end
else begin
case(b_state)
L_PARAM_STT_NORMAL:
begin
if(iPREVIOUS_VALID && !lock_condition)begin
//SPR Read Store
if(iPREVIOUS_EX_SYS_LDST)begin
b_r_data <= ldst_spr;
end
//System Register
else if(iPREVIOUS_EX_SYS_REG)begin
b_r_data <= sys_reg_data;
end
//Logic
else if(iPREVIOUS_EX_LOGIC)begin
b_r_data <= logic_data;
end
//SHIFT
else if(iPREVIOUS_EX_SHIFT)begin
b_r_data <= shift_data;
end
//ADDER
else if(iPREVIOUS_EX_ADDER)begin
b_r_data <= adder_data;
end
//MUL
else if(iPREVIOUS_EX_MUL)begin
b_r_data <= mul_data;
end
//Error
else begin
b_r_data <= 32'h0;
end
end
end
L_PARAM_STT_DIV_WAIT:
begin
if(div_out_valid)begin
b_r_data <= div_out_data;
end
else begin
b_r_data <= 32'h0;
end
end
L_PARAM_STT_LOAD:
begin
if(iDATAIO_REQ)begin
b_r_data <= load_data;
end
end
default:
begin
b_r_data <= 32'h0;
end
endcase
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_r_spr <= 32'h0;
end
else if(iEVENT_HOLD || iEVENT_START || iRESET_SYNC)begin
b_r_spr <= 32'h0;
end
else begin
case(b_state)
L_PARAM_STT_NORMAL:
begin
if(iPREVIOUS_EX_LDST || iPREVIOUS_EX_SYS_LDST)begin
b_r_spr <= ldst_spr;
end
end
default:
begin
b_r_spr <= b_r_spr;
end
endcase
end
end
/****************************************
Execute Category
****************************************/
reg b_ex_category_ldst;
reg b_ex_category_branch;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_ex_category_ldst <= 1'b0;
end
else if(iEVENT_HOLD || iEVENT_START || iRESET_SYNC)begin
b_ex_category_ldst <= 1'b0;
end
else begin
if(b_state == L_PARAM_STT_NORMAL && iPREVIOUS_VALID && !lock_condition)begin
b_ex_category_ldst <= iPREVIOUS_EX_LDST;
b_ex_category_branch <= iPREVIOUS_EX_BRANCH;
end
end
end
/****************************************
Pass Line
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_writeback <= 1'b0;
b_destination_sysreg <= 1'b0;
b_destination <= 5'h0;
b_afe <= 4'h0;
b_spr_writeback <= 1'b0;
end
else if(iEVENT_HOLD || iRESET_SYNC || iEVENT_START)begin
b_writeback <= 1'b0;
b_destination_sysreg <= 1'b0;
b_destination <= 5'h0;
b_afe <= 4'h0;
b_spr_writeback <= 1'b0;
end
else if(b_state == L_PARAM_STT_NORMAL)begin
if(iPREVIOUS_VALID && !lock_condition)begin
if(iPREVIOUS_EX_SDIV || iPREVIOUS_EX_UDIV || iPREVIOUS_EX_LDST || iPREVIOUS_EX_SYS_LDST || iPREVIOUS_EX_SYS_REG || iPREVIOUS_EX_LOGIC || iPREVIOUS_EX_SHIFT || iPREVIOUS_EX_ADDER || iPREVIOUS_EX_MUL)begin
b_writeback <= iPREVIOUS_WRITEBACK && (!except_inst_valid);
b_destination_sysreg <= iPREVIOUS_DESTINATION_SYSREG;
b_destination <= iPREVIOUS_DESTINATION;
b_afe <= iPREVIOUS_CC_AFE;
b_spr_writeback <= (iPREVIOUS_EX_LDST || iPREVIOUS_EX_SYS_LDST) && ldst_spr_valid;
end
else if(iPREVIOUS_EX_BRANCH)begin
b_writeback <= 1'b0;
b_destination_sysreg <= iPREVIOUS_DESTINATION_SYSREG;
b_destination <= iPREVIOUS_DESTINATION;
b_afe <= iPREVIOUS_CC_AFE;
b_spr_writeback <= 1'b0;
end
end
end
end
/****************************************
Valid
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_valid <= 1'b0;
end
else if(iEVENT_HOLD || iEVENT_START || iRESET_SYNC)begin
b_valid <= 1'b0;
end
else begin
case(b_state)
L_PARAM_STT_NORMAL:
begin
//Fault Check
if(iPREVIOUS_VALID && !lock_condition && except_inst_valid)begin
b_valid <= 1'b1;
end
else if(iPREVIOUS_VALID && !lock_condition && (iPREVIOUS_EX_SDIV || iPREVIOUS_EX_UDIV || (iPREVIOUS_EX_LDST && !ldst_pipe_rw)))begin
b_valid <= 1'b0;
end
else if(iPREVIOUS_VALID && !lock_condition && iPREVIOUS_EX_BRANCH)begin
//Halt
if(branch_halt_valid)begin
b_valid <= 1'b1;
end
//Interrupt Return Branch
else if(branch_ib_valid)begin
b_valid <= 1'b1;
end
//Branch(with Branch predict) - True
else if(branch_valid_with_predict)begin
b_valid <= 1'b1;
end
else if(branch_with_predict_predict_hit)begin
b_valid <= 1'b1;
end
else begin
//b_valid <= 1'b0;
b_valid <= 1'b1;
end
end
else begin
b_valid <= iPREVIOUS_VALID && !lock_condition;
end
end
L_PARAM_STT_DIV_WAIT:
begin
if(div_out_valid)begin
b_valid <= 1'b1;
end
end
L_PARAM_STT_LOAD:
begin
if(iDATAIO_REQ)begin
//not error
if(!except_ldst_valid)begin
b_valid <= 1'b1;
end
end
end
L_PARAM_STT_STORE:
begin
if(iDATAIO_REQ)begin
//not error
if(!except_ldst_valid)begin
b_valid <= 1'b1;
end
end
end
default:
begin
b_valid <= 1'b0;
end
endcase
end
end
/*********************************************************************************************************
AFE
*********************************************************************************************************/
/****************************************
AFE - for Load Store
****************************************/
wire [31:0] afe_ldst_data_result;
execute_afe_load_store AFE_LDST(
//AFE-Conrtol
.iAFE_CODE(b_afe),
//Data-In/Out
.iDATA(b_r_data),
.oDATA(afe_ldst_data_result)
);
/****************************************
AFE - Select
****************************************/
execute_afe AFE_SELECT(
.iAFE_LDST(b_ex_category_ldst),
.iAFE_LDST_DATA(afe_ldst_data_result),
.iRAW_DATA(b_r_data),
.oDATA(result_data_with_afe)
);
/*********************************************************************************************************
Assign
*********************************************************************************************************/
//Fault
assign oFAULT_VALID = exception_valid;
assign oFAULT_NUM = exception_num;
assign oFAULT_FI0R = exception_fi0r;
assign oFAULT_FI1R = exception_fi1r;
//Branch Predict
assign oBPREDICT_JUMP_INST = jump_normal_jump_inst; //Is normal jump Instruction?
assign oBPREDICT_PREDICT = jump_stage_predict_ena;
assign oBPREDICT_HIT = b_ex_category_branch && (jump_stage_predict_hit);
assign oBPREDICT_JUMP = jump_stage_jump_valid; //it same of Unhit
assign oBPREDICT_JUMP_ADDR = jump_stage_jump_addr;
assign oBPREDICT_INST_ADDR = b_pc - 32'h00000004;
//Branch - Controller
assign oBRANCH_ADDR = jump_stage_jump_addr;
assign oJUMP_VALID = jump_stage_jump_valid;
assign oINTR_VALID = jump_stage_branch_ib_valid;
assign oIDTSET_VALID = jump_stage_sysreg_idt_valid;
assign oPDTSET_VALID = jump_stage_sysreg_pdt_valid;
assign oPSRSET_VALID = jump_stage_sysreg_psr_valid;
//Writeback
assign oNEXT_VALID = b_valid && !iEVENT_HOLD;
assign oNEXT_DATA = result_data_with_afe;
assign oNEXT_DESTINATION = b_destination;
assign oNEXT_DESTINATION_SYSREG = b_destination_sysreg;
assign oNEXT_WRITEBACK = b_writeback && !except_ldst_valid && (b_state != L_PARAM_STT_BRANCH);
assign oNEXT_SPR_WRITEBACK = b_spr_writeback && !except_ldst_valid && (b_state != L_PARAM_STT_BRANCH);
assign oNEXT_SPR = b_r_spr;
assign oNEXT_FRCR = b_frcr;
assign oNEXT_PC = b_pc;
//System Register Writeback
assign oPDTR_WRITEBACK = b_destination_sysreg && b_writeback && (b_destination == `SYSREG_PDTR);
assign oEXCEPTION_LOCK = (b_state == L_PARAM_STT_DIV_WAIT) || (b_state == L_PARAM_STT_LOAD) || (b_state == L_PARAM_STT_STORE) || (b_state == L_PARAM_STT_RELOAD);
assign oSYSREG_FLAGR = {27'h0, sysreg_flags_register};
/*********************************************************************************************************
Assertion
*********************************************************************************************************/
/*************************************************
Assertion - SVA
*************************************************/
//synthesis translate_off
`ifdef MIST1032ISA_SVA_ASSERTION
property PRO_DATAPIPE_REQ_ACK;
@(posedge iCLOCK) disable iff (!inRESET || iEVENT_START || iRESET_SYNC) (oDATAIO_REQ |-> ##[1:50] iDATAIO_REQ);
endproperty
assert property(PRO_DATAPIPE_REQ_ACK);
`endif
//synthesis translate_on
/*************************************************
Verilog Assertion
*************************************************/
//synthesis translate_off
function [31:0] func_assert_write_data;
input [4:0] func_mask;
input [31:0] func_data;
begin
if(func_mask == 4'hf)begin
func_assert_write_data = func_data;
end
else if(func_mask == 4'b0011)begin
func_assert_write_data = {16'h0, func_data[15:0]};
end
else if(func_mask == 4'b1100)begin
func_assert_write_data = {16'h0, func_data[31:16]};
end
else if(func_mask == 4'b1000)begin
func_assert_write_data = {24'h0, func_data[31:24]};
end
else if(func_mask == 4'b0100)begin
func_assert_write_data = {24'h0, func_data[23:16]};
end
else if(func_mask == 4'b0010)begin
func_assert_write_data = {24'h0, func_data[15:8]};
end
else if(func_mask == 4'b0001)begin
func_assert_write_data = {24'h0, func_data[7:0]};
end
else begin
func_assert_write_data = 32'h0;
end
end
endfunction
//`ifdef MIST1032ISA_VLG_ASSERTION
localparam time_ena = 0;
/*
integer F_HANDLE;
initial F_HANDLE = $fopen("ldst_time_dump.log");
*/
wire [31:0] for_assertion_store_real_data = func_assert_write_data(oDATAIO_MASK, oDATAIO_DATA);
//synthesis translate_on
/*
--------------------------------
[S], "PC", "spr", "addr", "data"
[L], "PC", "spr", "addr", "data"
--------------------------------
*/
endmodule
`default_nettype wire |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_axi_basic_top.v
// Version : 1.10
// //
// Description: //
// TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_core_axi_basic_top #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
pcie_core_axi_basic_rx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
pcie_core_axi_basic_tx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) tx_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tbuf_av( trn_tbuf_av ),
.trn_tecrc_gen( trn_tecrc_gen ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Series/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
module flag_generator(
opcode,
fu,
wf_halt,
wf_barrier,
wf_branch,
wf_waitcnt,
scc_write,
scc_read,
vcc_write,
vcc_read,
exec_write,
exec_read,
M0_write,
M0_read,
s1_width,
s2_width,
s3_width,
s4_width,
dest1_width,
dest2_width,
fp_instr,
copy_d1_to_s4,
copy_d1_to_s1,
d1_vdst_to_sdst
);
input [31:0] opcode;
input [1:0] fu;
output wf_halt;
output wf_barrier;
output wf_branch;
output wf_waitcnt;
output scc_write;
output scc_read;
output vcc_write;
output vcc_read;
output exec_write;
output exec_read;
output M0_write;
output M0_read;
output [2:0] s1_width;
output [2:0] s2_width;
output [2:0] s3_width;
output [2:0] s4_width;
output [2:0] dest1_width;
output [2:0] dest2_width;
output fp_instr;
output copy_d1_to_s4;
output copy_d1_to_s1;
output d1_vdst_to_sdst;
reg wf_halt;
reg wf_barrier;
reg wf_branch;
reg wf_waitcnt;
reg scc_write;
reg scc_read;
reg vcc_write;
reg vcc_read;
reg exec_write;
reg exec_read;
reg M0_write;
reg M0_read;
reg [2:0] s1_width;
reg [2:0] s2_width;
reg [2:0] s3_width;
reg [2:0] s4_width;
reg [2:0] dest1_width;
reg [2:0] dest2_width;
reg fp_instr;
reg copy_d1_to_s4;
reg copy_d1_to_s1;
reg d1_vdst_to_sdst;
wire [33:0] instruction_id;
//Opcode
//Bits 31:24 should be retained
//Out od 23:0, atleast 13 higher bits should be masked
// (MTBUF with 13 flag bits)
//Out of 23:0, atleast 9 bits should be retained
// (longest operand is 9 bits)
//Current choice: Retain only 9 bits!!
assign instruction_id = {fu,opcode} & {2'b11,8'hff,15'b0,{9{1'b1}}};
always @(instruction_id)
begin
casex(instruction_id)
//SOPP --------------------------------------------
//SOPP: S_NOP
{2'b10,8'd1,24'h0}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT0;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPP: S_ENDPGM
{2'b10,8'd1,24'h1}:
begin
wf_halt <= 1'b1;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT0;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPP: S_BRANCH
{2'b10,8'd1,24'h2}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b1;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT0;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPP: S_BRANCH_SCC0
{2'b10,8'd1,24'h4}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b1;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b1;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT0;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPP: S_BRANCH_SCC1
{2'b10,8'd1,24'h5}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b1;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b1;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT0;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPP: S_BRANCH_VCCZ
{2'b10,8'd1,24'h6}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b1;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b1;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT0;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPP: S_BRANCH_VCCNZ
{2'b10,8'd1,24'h7}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b1;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b1;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT0;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPP: S_BRANCH_EXECZ
{2'b10,8'd1,24'h8}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b1;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT0;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPP: S_BRANCH_EXECNZ
{2'b10,8'd1,24'h9}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b1;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT0;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPP: S_BARRIER
{2'b10,8'd1,24'ha}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b1;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT0;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPP: S_WAITCNT
{2'b10,8'd1,24'hc}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b1;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT0;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP1 --------------------------------------------
//SOP1: S_MOV_B32
{2'b10,8'd2,24'h3}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP1: S_MOV_B64
{2'b10,8'd2,24'h4}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP1: S_NOT_B32
{2'b10,8'd2,24'h7}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP1: S_NOT_B64
{2'b10,8'd2,24'h8}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP1: S_AND_SAVEEXEC_B64
{2'b10,8'd2,24'h24}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b1;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP1: S_OR_SAVEEXEC_B64
{2'b10,8'd2,24'h25}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b1;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP1: S_XOR_SAVEEXEC_B64
{2'b10,8'd2,24'h26}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b1;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP1: S_ANDN2_SAVEEXEC_B64
{2'b10,8'd2,24'h27}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b1;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP1: S_ORN2_SAVEEXEC_B64
{2'b10,8'd2,24'h28}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b1;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP1: S_NAND_SAVEEXEC_B64
{2'b10,8'd2,24'h29}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b1;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP1: S_NOR_SAVEEXEC_B64
{2'b10,8'd2,24'h2a}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b1;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP1: S_XNOR_SAVEEXEC_B64
{2'b10,8'd2,24'h2b}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b1;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPC --------------------------------------------
//SOPC: S_CMP_EQ_I32
{2'b10,8'd4,24'h0}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPC: S_CMP_LG_I32
{2'b10,8'd4,24'h1}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPC: S_CMP_GT_I32
{2'b10,8'd4,24'h2}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPC: S_CMP_GE_I32
{2'b10,8'd4,24'h3}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPC: S_CMP_LT_I32
{2'b10,8'd4,24'h4}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPC: S_CMP_LE_I32
{2'b10,8'd4,24'h5}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPC: S_CMP_EQ_U32
{2'b10,8'd4,24'h6}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPC: S_CMP_LG_U32
{2'b10,8'd4,24'h7}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPC: S_CMP_GT_U32
{2'b10,8'd4,24'h8}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPC: S_CMP_GE_U32
{2'b10,8'd4,24'h9}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPC: S_CMP_LT_U32
{2'b10,8'd4,24'ha}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPC: S_CMP_LE_U32
{2'b10,8'd4,24'hb}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2 --------------------------------------------
//SOP2: S_ADD_U32
{2'b10,8'd8,24'h0}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_SUB_U32
{2'b10,8'd8,24'h1}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_ADD_I32
{2'b10,8'd8,24'h2}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_SUB_I32
{2'b10,8'd8,24'h3}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_ADDC_U32
{2'b10,8'd8,24'h4}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b1;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_SUBB_U32
{2'b10,8'd8,24'h5}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b1;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_MIN_I32
{2'b10,8'd8,24'h6}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_MIN_U32
{2'b10,8'd8,24'h7}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_MAX_I32
{2'b10,8'd8,24'h8}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_MAX_U32
{2'b10,8'd8,24'h9}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_AND_B32
{2'b10,8'd8,24'he}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_AND_B64
{2'b10,8'd8,24'hf}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT64;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_OR_B32
{2'b10,8'd8,24'h10}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_OR_B64
{2'b10,8'd8,24'h11}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT64;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_XOR_B32
{2'b10,8'd8,24'h12}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_XOR_B64
{2'b10,8'd8,24'h13}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT64;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_ANDN2_B32
{2'b10,8'd8,24'h14}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_ANDN2_B64
{2'b10,8'd8,24'h15}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT64;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_ORN2_B32
{2'b10,8'd8,24'h16}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_ORN2_B64
{2'b10,8'd8,24'h17}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT64;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_NAND_B32
{2'b10,8'd8,24'h18}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_NAND_B64
{2'b10,8'd8,24'h19}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT64;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_NOR_B32
{2'b10,8'd8,24'h1a}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_NOR_B64
{2'b10,8'd8,24'h1b}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT64;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_XNOR_B32
{2'b10,8'd8,24'h1c}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_XNOR_B64
{2'b10,8'd8,24'h1d}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT64;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_LSHL_B32
{2'b10,8'd8,24'h1e}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_LSHL_B64
{2'b10,8'd8,24'h1f}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT64;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_LSHR_B32
{2'b10,8'd8,24'h20}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_LSHR_B64
{2'b10,8'd8,24'h21}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT64;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_ASHR_I32
{2'b10,8'd8,24'h22}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_ASHR_I64
{2'b10,8'd8,24'h23}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT64;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOP2: S_MUL_I32
{2'b10,8'd8,24'h26}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPK --------------------------------------------
//SOPK: S_MOVK_I32
{2'b10,8'd16,24'h0}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT0;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SOPK: S_ADDK_I32
{2'b10,8'd16,24'hf}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b1;
d1_vdst_to_sdst <= 1'b0;
end
//SOPK: S_MULK_I32
{2'b10,8'd16,24'h10}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b1;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b1;
d1_vdst_to_sdst <= 1'b0;
end
//VOPC --------------------------------------------
//VOPC: V_CMP/CMPX/CMPS/CMPSX_{OP16}_F32/64 (128 instructions)
//OP16: F,LT,EQ,LE,GT,LG,GE,O,U,NGE,NLG,NGT,NLE,NEQ,NLT,TRU
{2'b01,8'd1,16'h0,8'b0???_????}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b1;
vcc_read <= 1'b0;
exec_write <= opcode[4] ? 1'b1 : 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= opcode[5] ? `DECODE_BIT64 : `DECODE_BIT32;
s2_width <= opcode[5] ? `DECODE_BIT64 : `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOPC: V_CMP/CMPX_{OP8}_I/U32/64 (64 instructions)
//OP8: F,LT,EQ,LE,GT,LG,GE,TRU
{2'b01,8'd1,16'h0,8'b1???_0???}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b1;
vcc_read <= 1'b0;
exec_write <= opcode[4] ? 1'b1 : 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= opcode[5] ? `DECODE_BIT64 : `DECODE_BIT32;
s2_width <= opcode[5] ? `DECODE_BIT64 : `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1 --------------------------------------------
//VOP1: V_NOP
{2'b01,8'd2,24'h0}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT0;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_MOV_B32
{2'b01,8'd2,24'h1}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_CVT_I32_F64
{2'b01,8'd2,24'h3}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_CVT_F64_I32
{2'b01,8'd2,24'h4}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_CVT_F32_I32
{2'b01,8'd2,24'h5}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_CVT_F32_U32
{2'b01,8'd2,24'h6}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_CVT_U32_F32
{2'b01,8'd2,24'h7}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_CVT_I32_F32
{2'b01,8'd2,24'h8}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_CVT_F16_F32
{2'b01,8'd2,24'ha}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_CVT_F32_F16
{2'b01,8'd2,24'hb}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_CVT_F32_F64
{2'b01,8'd2,24'hf}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_CVT_F64_F32
{2'b01,8'd2,24'h10}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_CVT_U32_F64
{2'b01,8'd2,24'h15}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_CVT_F64_U32
{2'b01,8'd2,24'h16}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_FRAC_F32
{2'b01,8'd2,24'h20}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_TRUNC_F32
{2'b01,8'd2,24'h21}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_CEIL_F32
{2'b01,8'd2,24'h22}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_RNDNE_F32
{2'b01,8'd2,24'h23}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_FLOOR_F32
{2'b01,8'd2,24'h24}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_EXP_F32
{2'b01,8'd2,24'h25}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_LOG_CLAMP_F32
{2'b01,8'd2,24'h26}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_LOG_F32
{2'b01,8'd2,24'h27}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_RCP_CLAMP_F32
{2'b01,8'd2,24'h28}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_RCP_F32
{2'b01,8'd2,24'h2a}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_RSQ_CLAMP_F32
{2'b01,8'd2,24'h2c}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_RSQ_F32
{2'b01,8'd2,24'h2e}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_RCP_F64
{2'b01,8'd2,24'h2f}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <= 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_RCP_CLAMP_F64
{2'b01,8'd2,24'h30}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_RSQ_F64
{2'b01,8'd2,24'h31}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_RSQ_CLAMP_F64
{2'b01,8'd2,24'h32}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_SQRT_F32
{2'b01,8'd2,24'h33}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_SQRT_F64
{2'b01,8'd2,24'h34}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_SIN_F32
{2'b01,8'd2,24'h35}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_COS_F32
{2'b01,8'd2,24'h36}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_NOT_B32
{2'b01,8'd2,24'h37}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_BFREV_B32
{2'b01,8'd2,24'h38}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_FFBH_U32
{2'b01,8'd2,24'h39}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_FFBL_B32
{2'b01,8'd2,24'h3a}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_FFBH_I32
{2'b01,8'd2,24'h3b}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP1: V_FRACT_F64
{2'b01,8'd2,24'h3e}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2 --------------------------------------------
//VOP2: V_CNDMASK_B32
{2'b01,8'd4,24'h0}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b1;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_READLINE_B32
{2'b01,8'd4,24'h1}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_WRITELINE_B32
{2'b01,8'd4,24'h2}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_ADD_F32
{2'b01,8'd4,24'h3}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_SUB_F32
{2'b01,8'd4,24'h4}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_SUBREV_F32
{2'b01,8'd4,24'h5}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_MUL_F32
{2'b01,8'd4,24'h8}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_MUL_I32_I24
{2'b01,8'd4,24'h9}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_MUL_HI_I32_I24
{2'b01,8'd4,24'ha}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_MUL_U32_U24
{2'b01,8'd4,24'hb}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_MUL_HI_U32_U24
{2'b01,8'd4,24'hc}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_MIN_F32
{2'b01,8'd4,24'hf}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_MAX_F32
{2'b01,8'd4,24'h10}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_MIN_I32
{2'b01,8'd4,24'h11}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_MAX_I32
{2'b01,8'd4,24'h12}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_MIN_U32
{2'b01,8'd4,24'h13}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_MAX_U32
{2'b01,8'd4,24'h14}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_LSHR_B32
{2'b01,8'd4,24'h15}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_LSHRREV_B32
{2'b01,8'd4,24'h16}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_ASHR_I32
{2'b01,8'd4,24'h17}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_ASHRREV_I32
{2'b01,8'd4,24'h18}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_LSHL_B32
{2'b01,8'd4,24'h19}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_LSHLREV_B32
{2'b01,8'd4,24'h1a}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_AND_B32
{2'b01,8'd4,24'h1b}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_OR_B32
{2'b01,8'd4,24'h1c}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_XOR_B32
{2'b01,8'd4,24'h1d}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_BFM_B32
{2'b01,8'd4,24'h1e}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_MAC_F32
{2'b01,8'd4,24'h1f}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT32;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b1;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_ADD_I32
{2'b01,8'd4,24'h25}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b1;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_SUB_I32
{2'b01,8'd4,24'h26}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b1;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_SUBREV_I32
{2'b01,8'd4,24'h27}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b1;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_ADDC_U32
{2'b01,8'd4,24'h28}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b1;
vcc_read <= 1'b1;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_SUBB_U32
{2'b01,8'd4,24'h29}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b1;
vcc_read <= 1'b1;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP2: V_SUBBREV_U32
{2'b01,8'd4,24'h2a}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b1;
vcc_read <= 1'b1;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3b --------------------------------------------
//VOP3b (from VOP2): V_ADD_I32
{2'b01,8'd8,24'h125}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT32;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3b (from VOP2): V_SUB_I32
{2'b01,8'd8,24'h126}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT32;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3b (from VOP2): V_SUBREV_I32
{2'b01,8'd8,24'h127}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT32;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3b (from VOP2): V_ADDC_U32
{2'b01,8'd8,24'h128}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT32;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3b (from VOP2): V_SUBB_U32
{2'b01,8'd8,24'h129}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT32;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3b (from VOP2): V_SUBBREV_U32
{2'b01,8'd8,24'h12a}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT32;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a --------------------------------------------
//VOP3a (from VOPC): V_CMP/CMPX/CMPS/CMPSX_{OP16}_F32/64 (128 instructions)
//OP16: F,LT,EQ,LE,GT,LG,GE,O,U,NGE,NLG,NGT,NLE,NEQ,NLT,TRU
{2'b01,8'd16,16'h0,8'b0???_????}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=opcode[4] ? 1'b1 : 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= opcode[5] ? `DECODE_BIT64 : `DECODE_BIT32;
s2_width <= opcode[5] ? `DECODE_BIT64 : `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b1;
end
//VOP3a (from VOPC): V_CMP/CMPX_{OP8}_I/U32/64 (64 instructions)
//OP8: F,LT,EQ,LE,GT,LG,GE,TRU
{2'b01,8'd16,16'h0,8'b1???_0???}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=opcode[4] ? 1'b1 : 1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= opcode[5] ? `DECODE_BIT64 : `DECODE_BIT32;
s2_width <= opcode[5] ? `DECODE_BIT64 : `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b1;
end
//VOP3a (from VOP2): V_CNDMASK_B32
{2'b01,8'd16,24'h100}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT64;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_READLINE_B32
{2'b01,8'd16,24'h101}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_WRITELINE_B32
{2'b01,8'd16,24'h102}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_ADD_F32
{2'b01,8'd16,24'h103}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_SUB_F32
{2'b01,8'd16,24'h104}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_SUBREV_F32
{2'b01,8'd16,24'h105}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_MUL_F32
{2'b01,8'd16,24'h108}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_MUL_I32_I24
{2'b01,8'd16,24'h109}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_MUL_HI_I32_I24
{2'b01,8'd16,24'h10a}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_MUL_U32_U24
{2'b01,8'd16,24'h10b}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_MUL_HI_U32_U24
{2'b01,8'd16,24'h10c}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_MIN_F32
{2'b01,8'd16,24'h10f}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_MAX_F32
{2'b01,8'd16,24'h110}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_MIN_I32
{2'b01,8'd16,24'h111}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_MAX_I32
{2'b01,8'd16,24'h112}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_MIN_U32
{2'b01,8'd16,24'h113}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_MAX_U32
{2'b01,8'd16,24'h114}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_LSHR_B32
{2'b01,8'd16,24'h115}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_LSHRREV_B32
{2'b01,8'd16,24'h116}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_ASHR_I32
{2'b01,8'd16,24'h117}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_ASHRREV_I32
{2'b01,8'd16,24'h118}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_LSHL_B32
{2'b01,8'd16,24'h119}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_LSHLREV_B32
{2'b01,8'd16,24'h11a}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_AND_B32
{2'b01,8'd16,24'h11b}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_OR_B32
{2'b01,8'd16,24'h11c}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_XOR_B32
{2'b01,8'd16,24'h11d}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_BFM_B32
{2'b01,8'd16,24'h11e}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP2): V_MAC_F32
{2'b01,8'd16,24'h11f}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT32;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b1;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_MAD_F32
{2'b01,8'd16,24'h141}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_MAD_I32_I24
{2'b01,8'd16,24'h142}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_MAD_U32_U24
{2'b01,8'd16,24'h143}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_BFE_U32
{2'b01,8'd16,24'h148}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_BFE_I32
{2'b01,8'd16,24'h149}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_BFI_B32
{2'b01,8'd16,24'h14a}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_FMA_F32
{2'b01,8'd16,24'h14b}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_FMA_F64
{2'b01,8'd16,24'h14c}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT64;
s3_width <= `DECODE_BIT64;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_MIN3_F32
{2'b01,8'd16,24'h151}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_MIN3_I32
{2'b01,8'd16,24'h152}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_MIN3_U32
{2'b01,8'd16,24'h153}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_MAX3_F32
{2'b01,8'd16,24'h154}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_MAX3_I32
{2'b01,8'd16,24'h155}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_MAX3_U32
{2'b01,8'd16,24'h156}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_MED3_F32
{2'b01,8'd16,24'h157}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_MED3_I32
{2'b01,8'd16,24'h158}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_MED3_U32
{2'b01,8'd16,24'h159}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_LSHL_B64
{2'b01,8'd16,24'h161}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT64;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_LSHR_B64
{2'b01,8'd16,24'h162}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT64;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_ASHR_I64
{2'b01,8'd16,24'h163}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT64;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_NOP
{2'b01,8'd16,24'h180}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT0;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_MOV_B32
{2'b01,8'd16,24'h181}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_CVT_I32_F64
{2'b01,8'd16,24'h183}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_CVT_F64_I32
{2'b01,8'd16,24'h184}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_CVT_F32_I32
{2'b01,8'd16,24'h185}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_CVT_F32_U32
{2'b01,8'd16,24'h186}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_CVT_U32_F32
{2'b01,8'd16,24'h187}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_CVT_I32_F32
{2'b01,8'd16,24'h188}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_CVT_F16_F32
{2'b01,8'd16,24'h18a}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_CVT_F32_F16
{2'b01,8'd16,24'h18b}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_CVT_F32_F64
{2'b01,8'd16,24'h18f}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_CVT_F64_F32
{2'b01,8'd16,24'h190}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_CVT_U32_F64
{2'b01,8'd16,24'h195}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_CVT_F64_U32
{2'b01,8'd16,24'h196}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_FRAC_F32
{2'b01,8'd16,24'h1a0}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_TRUNC_F32
{2'b01,8'd16,24'h1a1}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_CEIL_F32
{2'b01,8'd16,24'h1a2}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_RNDNE_F32
{2'b01,8'd16,24'h1a3}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_FLOOR_F32
{2'b01,8'd16,24'h1a4}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_EXP_F32
{2'b01,8'd16,24'h1a5}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_LOG_CLAMP_F32
{2'b01,8'd16,24'h1a6}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_LOG_F32
{2'b01,8'd16,24'h1a7}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_RCP_CLAMP_F32
{2'b01,8'd16,24'h1a8}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_RCP_F32
{2'b01,8'd16,24'h1aa}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_RSQ_CLAMP_F32
{2'b01,8'd16,24'h1ac}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_RSQ_F32
{2'b01,8'd16,24'h1ae}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_RCP_F64
{2'b01,8'd16,24'h1af}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_RCP_CLAMP_F64
{2'b01,8'd16,24'h1b0}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_RSQ_F64
{2'b01,8'd16,24'h1b1}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_RSQ_CLAMP_F64
{2'b01,8'd16,24'h1b2}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_SQRT_F32
{2'b01,8'd16,24'h1b3}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_SQRT_F64
{2'b01,8'd16,24'h1b4}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_SIN_F32
{2'b01,8'd16,24'h1b5}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_COS_F32
{2'b01,8'd16,24'h1b6}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_NOT_B32
{2'b01,8'd16,24'h1b7}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_BFREV_B32
{2'b01,8'd16,24'h1b8}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_FFBH_U32
{2'b01,8'd16,24'h1b9}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_FFBL_B32
{2'b01,8'd16,24'h1ba}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_FFBH_I32
{2'b01,8'd16,24'h1bb}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a (from VOP1): V_FRACT_F64
{2'b01,8'd16,24'h1be}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_ADD_F64
{2'b01,8'd16,24'h164}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT64;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_MUL_F64
{2'b01,8'd16,24'h165}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT64;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_MIN_F64
{2'b01,8'd16,24'h166}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT64;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_MAX_F64
{2'b01,8'd16,24'h167}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT64;
s2_width <= `DECODE_BIT64;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b1;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_MUL_LO_U32
{2'b01,8'd16,24'h169}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_MUL_HI_U32
{2'b01,8'd16,24'h16a}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_MUL_LO_I32
{2'b01,8'd16,24'h16b}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//VOP3a: V_MUL_HI_I32
{2'b01,8'd16,24'h16c}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SMRD --------------------------------------------
//SMRD: S_LOAD_DWORD
{2'b11,8'd1,24'h0}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SMRD: S_LOAD_DWORDX2
{2'b11,8'd1,24'h1}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SMRD: S_LOAD_DWORDX4
{2'b11,8'd1,24'h2}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT128;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SMRD: S_LOAD_DWORDX8
{2'b11,8'd1,24'h3}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT256;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SMRD: S_LOAD_DWORDX16
{2'b11,8'd1,24'h4}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT512;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SMRD: S_BUFFER_LOAD_DWORD
{2'b11,8'd1,24'h8}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT128;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SMRD: S_BUFFER_LOAD_DWORDX2
{2'b11,8'd1,24'h9}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT128;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SMRD: S_BUFFER_LOAD_DWORDX4
{2'b11,8'd1,24'ha}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT128;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT128;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SMRD: S_BUFFER_LOAD_DWORDX8
{2'b11,8'd1,24'hb}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT128;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT256;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//SMRD: S_BUFFER_LOAD_DWORDX16
{2'b11,8'd1,24'hc}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b0;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT128;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT512;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//LDS/GDS --------------------------------------------
//LDS/GDS: DS_WRITE_32
{2'b11,8'd2,24'hd}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//LDS/GDS: DS_READ_32
{2'b11,8'd2,24'h36}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//MTBUF --------------------------------------------
//MTBUF: TBUFFER_LOAD_FORMAT_X
{2'b11,8'd4,24'h0}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT128;
dest1_width <= `DECODE_BIT32;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//MTBUF: TBUFFER_LOAD_FORMAT_XY
{2'b11,8'd4,24'h1}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT128;
dest1_width <= `DECODE_BIT64;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//MTBUF: TBUFFER_LOAD_FORMAT_XYZ
{2'b11,8'd4,24'h2}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT128;
dest1_width <= `DECODE_BIT96;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//MTBUF: TBUFFER_LOAD_FORMAT_XYZW
{2'b11,8'd4,24'h3}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT128;
dest1_width <= `DECODE_BIT128;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//MTBUF: TBUFFER_STORE_FORMAT_X
{2'b11,8'd4,24'h4}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT32;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT128;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//MTBUF: TBUFFER_STORE_FORMAT_XY
{2'b11,8'd4,24'h5}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT64;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT128;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//MTBUF: TBUFFER_STORE_FORMAT_XYZ
{2'b11,8'd4,24'h6}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT96;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT128;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//MTBUF: TBUFFER_STORE_FORMAT_XYZW
{2'b11,8'd4,24'h7}:
begin
wf_halt <= 1'b0;
wf_barrier <= 1'b0;
wf_branch <= 1'b0;
wf_waitcnt <= 1'b0;
scc_write <= 1'b0;
scc_read <= 1'b0;
vcc_write <= 1'b0;
vcc_read <= 1'b0;
exec_write <=1'b0;
exec_read <= 1'b1;
M0_write <= 1'b0;
M0_read <= 1'b0;
s1_width <= `DECODE_BIT32;
s2_width <= `DECODE_BIT128;
s3_width <= `DECODE_BIT32;
s4_width <= `DECODE_BIT128;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'b0;
copy_d1_to_s4 <= 1'b0;
copy_d1_to_s1 <= 1'b0;
d1_vdst_to_sdst <= 1'b0;
end
//Default error case
default:
begin
wf_halt <= 1'bx;
wf_barrier <= 1'bx;
wf_branch <= 1'bx;
wf_waitcnt <= 1'b0;
scc_write <= 1'bx;
scc_read <= 1'bx;
vcc_write <= 1'bx;
vcc_read <= 1'bx;
exec_write <=1'bx;
exec_read <= 1'bx;
M0_write <= 1'bx;
M0_read <= 1'bx;
s1_width <= `DECODE_BIT0;
s2_width <= `DECODE_BIT0;
s3_width <= `DECODE_BIT0;
s4_width <= `DECODE_BIT0;
dest1_width <= `DECODE_BIT0;
dest2_width <= `DECODE_BIT0;
fp_instr <= 1'bx;
copy_d1_to_s4 <= 1'bx;
copy_d1_to_s1 <= 1'bx;
d1_vdst_to_sdst <= 1'bx;
end
endcase
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module cf_spi (
spi_cs0n,
spi_cs1n,
spi_clk,
spi_sd_en,
spi_sd_o,
spi_sd_i,
up_rstn,
up_clk,
up_spi_start,
up_spi_devsel,
up_spi_wdata,
up_spi_rdata,
up_spi_status,
debug_data,
debug_trigger);
output spi_cs0n;
output spi_cs1n;
output spi_clk;
output spi_sd_en;
output spi_sd_o;
input spi_sd_i;
input up_rstn;
input up_clk;
input up_spi_start;
input up_spi_devsel;
input [23:0] up_spi_wdata;
output [ 7:0] up_spi_rdata;
output up_spi_status;
output [63:0] debug_data;
output [ 7:0] debug_trigger;
reg spi_cs0n;
reg spi_cs1n;
reg spi_clk;
reg spi_sd_en;
reg spi_sd_o;
reg spi_count_5_d;
reg [ 2:0] spi_clk_count;
reg [ 5:0] spi_count;
reg spi_rwn;
reg [23:0] spi_data_out;
reg [ 7:0] spi_data_in;
reg up_spi_start_d;
reg up_spi_status;
reg [ 7:0] up_spi_rdata;
wire spi_cs_en_s;
assign debug_trigger[7] = spi_cs0n;
assign debug_trigger[6] = spi_cs1n;
assign debug_trigger[5] = spi_sd_en;
assign debug_trigger[4] = spi_count[5];
assign debug_trigger[3] = up_spi_devsel;
assign debug_trigger[2] = up_spi_start;
assign debug_trigger[1] = up_spi_start_d;
assign debug_trigger[0] = up_spi_status;
assign debug_data[63:62] = 'd0;
assign debug_data[61:61] = spi_cs_en_s;
assign debug_data[60:60] = up_spi_start_d;
assign debug_data[59:52] = up_spi_rdata;
assign debug_data[51:44] = spi_data_in;
assign debug_data[43:20] = spi_data_out;
assign debug_data[19:19] = spi_rwn;
assign debug_data[18:18] = spi_count_5_d;
assign debug_data[17:12] = spi_count;
assign debug_data[11: 9] = spi_clk_count;
assign debug_data[ 8: 8] = up_spi_status;
assign debug_data[ 7: 7] = up_spi_devsel;
assign debug_data[ 6: 6] = up_spi_start;
assign debug_data[ 5: 5] = spi_sd_i;
assign debug_data[ 4: 4] = spi_sd_o;
assign debug_data[ 3: 3] = spi_sd_en;
assign debug_data[ 2: 2] = spi_clk;
assign debug_data[ 1: 1] = spi_cs1n;
assign debug_data[ 0: 0] = spi_cs0n;
assign spi_cs_en_s = spi_count_5_d | spi_count[5];
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
spi_cs0n <= 'd1;
spi_cs1n <= 'd1;
spi_clk <= 'd0;
spi_sd_en <= 'd0;
spi_sd_o <= 'd0;
spi_count_5_d <= 'd0;
spi_clk_count <= 'd0;
spi_count <= 'd0;
spi_rwn <= 'd0;
spi_data_out <= 'd0;
spi_data_in <= 'd0;
up_spi_start_d <= 'd0;
up_spi_status <= 'd0;
up_spi_rdata <= 'd0;
end else begin
spi_cs0n <= up_spi_devsel | (~spi_cs_en_s);
spi_cs1n <= (~up_spi_devsel) | (~spi_cs_en_s);
spi_clk <= spi_clk_count[2] & spi_count[5];
spi_sd_en <= (spi_count[5:3] == 3'b111) ? spi_rwn : 1'b0;
spi_sd_o <= spi_data_out[23];
if (spi_clk_count == 3'b100) begin
spi_count_5_d <= spi_count[5];
end
spi_clk_count <= spi_clk_count + 1'b1;
if (spi_count[5] == 1'b1) begin
if (spi_clk_count == 3'b111) begin
spi_count <= spi_count + 1'b1;
end
spi_rwn <= spi_rwn;
if (spi_clk_count == 3'b111) begin
spi_data_out <= {spi_data_out[22:0], 1'b0};
end
if ((spi_clk_count == 3'b100) && (spi_rwn == 1'b1) && (spi_count[5:3] == 3'b111)) begin
spi_data_in <= {spi_data_in[6:0], spi_sd_i};
end
end else if ((spi_clk_count == 3'b111) && (up_spi_start == 1'b1) &&
(up_spi_start_d == 1'b0)) begin
spi_count <= 6'h28;
spi_rwn <= up_spi_wdata[23];
spi_data_out <= up_spi_wdata;
spi_data_in <= 8'd0;
end
if (spi_clk_count == 3'b111) begin
up_spi_start_d <= up_spi_start;
end
up_spi_status <= ~(spi_count[5] | (up_spi_start & ~up_spi_start_d));
up_spi_rdata <= spi_data_in;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_mc_aw_channel.v
//
// Description:
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_0_axi_mc_aw_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of cmd_byte_addr
// Range: 30
parameter integer C_MC_ADDR_WIDTH = 30,
// Width of AXI xDATA and MC xx_data
// Range: 32, 64, 128.
parameter integer C_DATA_WIDTH = 32,
// MC burst length. = 1 for BL4 or BC4, = 2 for BL8
parameter integer C_MC_BURST_LEN = 1,
// DRAM clock to AXI clock ratio
// supported values 2, 4
parameter integer C_MC_nCK_PER_CLK = 2,
// Static value of axsize
// Range: 2-4
parameter integer C_AXSIZE = 2,
parameter C_ECC = "OFF"
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Write Address Ports
input wire [C_ID_WIDTH-1:0] awid ,
input wire [C_AXI_ADDR_WIDTH-1:0] awaddr ,
input wire [7:0] awlen ,
input wire [2:0] awsize ,
input wire [1:0] awburst ,
input wire [1:0] awlock ,
input wire [3:0] awcache ,
input wire [2:0] awprot ,
input wire [3:0] awqos ,
input wire awvalid ,
output wire awready ,
// MC Master Interface
//CMD PORT
output wire cmd_en ,
output wire cmd_en_last ,
output wire [2:0] cmd_instr ,
output wire [C_MC_ADDR_WIDTH-1:0] cmd_byte_addr ,
input wire cmd_full ,
// Connections to/from axi_mc_w_channel module
input wire w_data_rdy ,
input wire cmd_wr_bytes ,
output wire w_cmd_rdy ,
output wire w_ignore_begin ,
output wire w_ignore_end ,
output wire awvalid_int ,
output wire [3:0] awqos_int ,
// Connections to/from axi_mc_b_channel module
output wire b_push ,
output wire [C_ID_WIDTH-1:0] b_awid ,
input wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_CMD_WRITE = 3'b000;
localparam P_CMD_READ = 3'b001;
localparam P_CMD_WRITE_BYTES = 3'b011;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire next ;
wire next_pending ;
reg [C_ID_WIDTH-1:0] axid ;
reg [C_AXI_ADDR_WIDTH-1:0] axaddr ;
reg [7:0] axlen ;
reg [3:0] axqos ;
reg [1:0] axburst ;
reg axvalid ;
wire [C_ID_WIDTH-1:0] axid_int ;
wire [C_AXI_ADDR_WIDTH-1:0] axaddr_int ;
wire [7:0] axlen_int ;
wire [3:0] axqos_int ;
wire [1:0] axburst_int ;
wire axvalid_int ;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign awvalid_int = axvalid_int;
assign awqos_int = axqos_int;
assign axid_int = awready ? awid : axid;
assign axlen_int = awready ? awlen : axlen;
assign axqos_int = awready ? awqos : axqos;
assign axaddr_int = awready ? awaddr : axaddr;
assign axburst_int = awready ? awburst : axburst;
assign axvalid_int = awready ? awvalid : axvalid;
always @(posedge clk) begin
if(reset)
axvalid <= 1'b0;
else
axvalid <= axvalid_int;
end
always @(posedge clk) begin
axid <= axid_int;
axlen <= axlen_int;
axqos <= axqos_int;
axaddr <= axaddr_int;
axburst <= axburst_int;
end
// Translate the AXI transaction to the MC transaction(s)
mig_7series_v4_0_axi_mc_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_MC_ADDR_WIDTH ( C_MC_ADDR_WIDTH ) ,
.C_DATA_WIDTH ( C_DATA_WIDTH ) ,
.C_MC_BURST_LEN ( C_MC_BURST_LEN ) ,
.C_MC_nCK_PER_CLK ( C_MC_nCK_PER_CLK ) ,
.C_AXSIZE ( C_AXSIZE ) ,
.C_MC_RD_INST ( 0 )
)
axi_mc_cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( axaddr_int ) ,
.axlen ( axlen_int ) ,
.axsize ( awsize ) , // This is a constant, need not be sampled. Fed the direct input to aviod timing violations.
.axburst ( axburst_int ) ,
.axvalid ( axvalid_int ) ,
.axready ( awready ) ,
.cmd_byte_addr ( cmd_byte_addr ) ,
.ignore_begin ( w_ignore_begin ) ,
.ignore_end ( w_ignore_end ) ,
.next ( next ) ,
.next_pending ( next_pending )
);
mig_7series_v4_0_axi_mc_wr_cmd_fsm #
(
.C_MC_BURST_LEN (C_MC_BURST_LEN ),
.C_MC_RD_INST (0 )
)
aw_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axready ( awready ) ,
.axvalid ( axvalid_int ) ,
.cmd_en ( cmd_en ) ,
.cmd_full ( cmd_full ) ,
.next ( next ) ,
.next_pending ( next_pending ) ,
.data_rdy ( w_data_rdy ) ,
.b_push ( b_push ) ,
.b_full ( b_full ) ,
.cmd_en_last ( cmd_en_last )
);
// assign cmd_instr = (C_ECC == "ON") ? P_CMD_WRITE_BYTES : P_CMD_WRITE;
assign cmd_instr = ((C_ECC == "ON") & cmd_wr_bytes) ? P_CMD_WRITE_BYTES : P_CMD_WRITE;
assign b_awid = axid_int;
assign w_cmd_rdy = next;
endmodule
`default_nettype wire
|
// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module mig_7series_v4_0_ddr_comparator_sel #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = V;
end
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
mig_7series_v4_0_ddr_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// A simple circuit that can be used to detect brownouts and other hardware issues
module top (
input clk,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5
);
reg [7:0] reset_counter = 0;
reg resetn = 0;
always @(posedge clk) begin
reset_counter <= reset_counter + 1;
resetn <= resetn | &reset_counter;
end
reg error, rdmode, rdfin;
reg [31:0] scratchpad [0:1023];
reg [31:0] xorshift32_state;
reg [9:0] index;
reg [31:0] next_xorshift32_state;
always @* begin
next_xorshift32_state = xorshift32_state ^ ( xorshift32_state << 13);
next_xorshift32_state = next_xorshift32_state ^ (next_xorshift32_state >> 17);
next_xorshift32_state = next_xorshift32_state ^ (next_xorshift32_state << 5);
end
always @(posedge clk) begin
xorshift32_state <= &index ? 123456789 : next_xorshift32_state;
index <= index + 1;
if (!resetn) begin
xorshift32_state <= 123456789;
index <= 0;
error <= 0;
rdmode <= 0;
rdfin <= 0;
end else
if (!rdmode) begin
scratchpad[index] <= xorshift32_state;
rdmode <= &index;
end else begin
if (scratchpad[index] != xorshift32_state) error <= 1;
rdfin <= rdfin || &index;
end
end
wire ok = resetn && rdfin && !error;
assign LED1 = 0, LED2 = error, LED3 = 0, LED4 = error, LED5 = ok;
endmodule
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the users design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// 503-286-8001 (other locations)
//
// web: http://www.latticesemi.com/
// email: [email protected]
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm_mc_arithmetic.v
// Title : Multi-cycle arithmetic unit.
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
`define LM32_MC_STATE_RNG 2:0
`define LM32_MC_STATE_IDLE 3'b000
`define LM32_MC_STATE_MULTIPLY 3'b001
`define LM32_MC_STATE_MODULUS 3'b010
`define LM32_MC_STATE_DIVIDE 3'b011
`define LM32_MC_STATE_SHIFT_LEFT 3'b100
`define LM32_MC_STATE_SHIFT_RIGHT 3'b101
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_mc_arithmetic (
// ----- Inputs -----
clk_i,
rst_i,
stall_d,
kill_x,
`ifdef CFG_MC_DIVIDE_ENABLED
divide_d,
modulus_d,
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
multiply_d,
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
shift_left_d,
shift_right_d,
sign_extend_d,
`endif
operand_0_d,
operand_1_d,
// ----- Ouputs -----
result_x,
`ifdef CFG_MC_DIVIDE_ENABLED
divide_by_zero_x,
`endif
stall_request_x
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input stall_d; // Stall instruction in D stage
input kill_x; // Kill instruction in X stage
`ifdef CFG_MC_DIVIDE_ENABLED
input divide_d; // Perform divide
input modulus_d; // Perform modulus
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
input multiply_d; // Perform multiply
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
input shift_left_d; // Perform left shift
input shift_right_d; // Perform right shift
input sign_extend_d; // Whether to sign-extend (arithmetic) or zero-extend (logical)
`endif
input [`LM32_WORD_RNG] operand_0_d;
input [`LM32_WORD_RNG] operand_1_d;
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [`LM32_WORD_RNG] result_x; // Result of operation
reg [`LM32_WORD_RNG] result_x;
`ifdef CFG_MC_DIVIDE_ENABLED
output divide_by_zero_x; // A divide by zero was attempted
reg divide_by_zero_x;
`endif
output stall_request_x; // Request to stall pipeline from X stage back
wire stall_request_x;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
reg [`LM32_WORD_RNG] p; // Temporary registers
reg [`LM32_WORD_RNG] a;
reg [`LM32_WORD_RNG] b;
`ifdef CFG_MC_DIVIDE_ENABLED
wire [32:0] t;
`endif
reg [`LM32_MC_STATE_RNG] state; // Current state of FSM
reg [5:0] cycles; // Number of cycles remaining in the operation
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
reg sign_extend_x; // Whether to sign extend of zero extend right shifts
wire fill_value; // Value to fill with for right barrel-shifts
`endif
/////////////////////////////////////////////////////
// Combinational logic
/////////////////////////////////////////////////////
// Stall pipeline while any operation is being performed
assign stall_request_x = state != `LM32_MC_STATE_IDLE;
`ifdef CFG_MC_DIVIDE_ENABLED
// Subtraction
assign t = {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]} - b;
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
// Determine fill value for right shift - Sign bit for arithmetic shift, or zero for logical shift
assign fill_value = (sign_extend_x == `TRUE) & b[`LM32_WORD_WIDTH-1];
`endif
/////////////////////////////////////////////////////
// Sequential logic
/////////////////////////////////////////////////////
// Perform right shift
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
cycles <= #1 {6{1'b0}};
p <= #1 {`LM32_WORD_WIDTH{1'b0}};
a <= #1 {`LM32_WORD_WIDTH{1'b0}};
b <= #1 {`LM32_WORD_WIDTH{1'b0}};
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
sign_extend_x <= #1 1'b0;
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
divide_by_zero_x <= #1 `FALSE;
`endif
result_x <= #1 {`LM32_WORD_WIDTH{1'b0}};
state <= #1 `LM32_MC_STATE_IDLE;
end
else
begin
`ifdef CFG_MC_DIVIDE_ENABLED
divide_by_zero_x <= #1 `FALSE;
`endif
case (state)
`LM32_MC_STATE_IDLE:
begin
if (stall_d == `FALSE)
begin
cycles <= #1 `LM32_WORD_WIDTH;
p <= #1 32'b0;
a <= #1 operand_0_d;
b <= #1 operand_1_d;
`ifdef CFG_MC_DIVIDE_ENABLED
if (divide_d == `TRUE)
state <= #1 `LM32_MC_STATE_DIVIDE;
if (modulus_d == `TRUE)
state <= #1 `LM32_MC_STATE_MODULUS;
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
if (multiply_d == `TRUE)
state <= #1 `LM32_MC_STATE_MULTIPLY;
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
if (shift_left_d == `TRUE)
begin
state <= #1 `LM32_MC_STATE_SHIFT_LEFT;
sign_extend_x <= #1 sign_extend_d;
cycles <= #1 operand_1_d[4:0];
a <= #1 operand_0_d;
b <= #1 operand_0_d;
end
if (shift_right_d == `TRUE)
begin
state <= #1 `LM32_MC_STATE_SHIFT_RIGHT;
sign_extend_x <= #1 sign_extend_d;
cycles <= #1 operand_1_d[4:0];
a <= #1 operand_0_d;
b <= #1 operand_0_d;
end
`endif
end
end
`ifdef CFG_MC_DIVIDE_ENABLED
`LM32_MC_STATE_DIVIDE:
begin
if (t[32] == 1'b0)
begin
p <= #1 t[31:0];
a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b1};
end
else
begin
p <= #1 {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]};
a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b0};
end
result_x <= #1 a;
if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
begin
// Check for divide by zero
divide_by_zero_x <= #1 b == {`LM32_WORD_WIDTH{1'b0}};
state <= #1 `LM32_MC_STATE_IDLE;
end
cycles <= #1 cycles - 1'b1;
end
`LM32_MC_STATE_MODULUS:
begin
if (t[32] == 1'b0)
begin
p <= #1 t[31:0];
a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b1};
end
else
begin
p <= #1 {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]};
a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b0};
end
result_x <= #1 p;
if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
begin
// Check for divide by zero
divide_by_zero_x <= #1 b == {`LM32_WORD_WIDTH{1'b0}};
state <= #1 `LM32_MC_STATE_IDLE;
end
cycles <= #1 cycles - 1'b1;
end
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
`LM32_MC_STATE_MULTIPLY:
begin
if (b[0] == 1'b1)
p <= #1 p + a;
b <= #1 {1'b0, b[`LM32_WORD_WIDTH-1:1]};
a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b0};
result_x <= #1 p;
if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
state <= #1 `LM32_MC_STATE_IDLE;
cycles <= #1 cycles - 1'b1;
end
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
`LM32_MC_STATE_SHIFT_LEFT:
begin
a <= #1 {a[`LM32_WORD_WIDTH-2:0], 1'b0};
result_x <= #1 a;
if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
state <= #1 `LM32_MC_STATE_IDLE;
cycles <= #1 cycles - 1'b1;
end
`LM32_MC_STATE_SHIFT_RIGHT:
begin
b <= #1 {fill_value, b[`LM32_WORD_WIDTH-1:1]};
result_x <= #1 b;
if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
state <= #1 `LM32_MC_STATE_IDLE;
cycles <= #1 cycles - 1'b1;
end
`endif
endcase
end
end
endmodule
|
/*******************************************************************************
* Module: dly01_16
* Date:2014-05-30
* Author: Andrey Filippov
* Description: Synchronous delay by 1-16 clock cycles with reset (will map to primitive)
*
* Copyright (c) 2014 Elphel, Inc.
* dly01_16.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dly01_16.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
module dly01_16(
input clk,
input rst,
input [3:0] dly,
input din,
output dout
);
reg [15:0] sr=0;
`ifdef SHREG_SEQUENTIAL_RESET
always @ (posedge clk) begin
sr <= {sr[14:0], din & ~rst};
end
`else
// always @ (posedge rst or posedge clk) begin
always @ (posedge clk) begin
if (rst) sr <=0;
else sr <= {sr[14:0],din};
end
`endif
`ifdef SIMULATION
assign dout = (|sr) ? ((&sr) ? 1'b1 : sr[dly]) : 1'b0 ;
`else
assign dout =sr[dly];
`endif
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2010 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
typedef enum { EN_ZERO,
EN_ONE
} En_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Insure that we can declare a type with a function declaration
function enum integer {
EF_TRUE = 1,
EF_FALSE = 0 }
f_enum_inv ( input a);
f_enum_inv = a ? EF_FALSE : EF_TRUE;
endfunction
initial begin
if (f_enum_inv(1) != 0) $stop;
if (f_enum_inv(0) != 1) $stop;
end
En_t a, z;
sub sub (/*AUTOINST*/
// Outputs
.z (z),
// Inputs
.a (a));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= EN_ZERO;
end
if (cyc==2) begin
a <= EN_ONE;
if (z != EN_ONE) $stop;
end
if (cyc==3) begin
if (z != EN_ZERO) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module sub (input En_t a, output En_t z);
always @* z = (a==EN_ONE) ? EN_ZERO : EN_ONE;
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_dac(
clk,
// control ports
control,
status,
// FIFO interface
src_dac_en,
src_dac_ddata,
src_dac_dunf,
src_dac_dvalid,
dst_dac_en,
dst_dac_ddata,
dst_dac_dunf,
dst_dac_dvalid
);
localparam RP_ID = 8'hA0;
parameter CHANNEL_ID = 0;
input clk;
input [31:0] control;
output [31:0] status;
output src_dac_en;
input [31:0] src_dac_ddata;
input src_dac_dunf;
input src_dac_dvalid;
input dst_dac_en;
output [31:0] dst_dac_ddata;
output dst_dac_dunf;
output dst_dac_dvalid;
reg src_dac_en;
reg [31:0] dst_dac_ddata;
reg dst_dac_dunf;
reg dst_dac_dvalid;
assign status = {24'h0, RP_ID};
always @(posedge clk) begin
src_dac_en <= dst_dac_en;
dst_dac_ddata <= src_dac_ddata;
dst_dac_dunf <= src_dac_dunf;
dst_dac_dvalid <= src_dac_dvalid;
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Generates global and local ids for given set of group ids.
// Need one of these for each kernel instance.
module acl_id_iterator
#(
parameter WIDTH = 32 // width of all the counters
)
(
input clock,
input resetn,
input start,
// handshaking with work group dispatcher
input valid_in,
output stall_out,
// handshaking with kernel instance
input stall_in,
output valid_out,
// comes from group dispatcher
input [WIDTH-1:0] group_id_in[2:0],
input [WIDTH-1:0] global_id_base_in[2:0],
// kernel parameters from the higher level
input [WIDTH-1:0] local_size[2:0],
input [WIDTH-1:0] global_size[2:0],
// actual outputs
output [WIDTH-1:0] local_id[2:0],
output [WIDTH-1:0] global_id[2:0],
output [WIDTH-1:0] group_id[2:0]
);
// Storing group id vector and global id offsets vector.
// Global id offsets help work item iterators calculate global
// ids without using multipliers.
localparam FIFO_WIDTH = 2 * 3 * WIDTH;
localparam FIFO_DEPTH = 4;
wire last_in_group;
wire issue = valid_out & !stall_in;
reg just_seen_last_in_group;
wire [WIDTH-1:0] global_id_from_iter[2:0];
reg [WIDTH-1:0] global_id_base[2:0];
// takes one cycle for the work iterm iterator to register
// global_id_base. During that cycle, just use global_id_base
// directly.
wire use_base = just_seen_last_in_group;
assign global_id[0] = use_base ? global_id_base[0] : global_id_from_iter[0];
assign global_id[1] = use_base ? global_id_base[1] : global_id_from_iter[1];
assign global_id[2] = use_base ? global_id_base[2] : global_id_from_iter[2];
// Group ids (and global id offsets) are stored in a fifo.
acl_fifo #(
.DATA_WIDTH(FIFO_WIDTH),
.DEPTH(FIFO_DEPTH)
) group_id_fifo (
.clock(clock),
.resetn(resetn),
.data_in ( {group_id_in[2], group_id_in[1], group_id_in[0],
global_id_base_in[2], global_id_base_in[1], global_id_base_in[0]} ),
.data_out( {group_id[2], group_id[1], group_id[0],
global_id_base[2], global_id_base[1], global_id_base[0]} ),
.valid_in(valid_in),
.stall_out(stall_out),
.valid_out(valid_out),
.stall_in(!last_in_group | !issue)
);
acl_work_item_iterator #(
.WIDTH(WIDTH)
) work_item_iterator (
.clock(clock),
.resetn(resetn),
.start(start),
.issue(issue),
.local_size(local_size),
.global_size(global_size),
.global_id_base(global_id_base),
.local_id(local_id),
.global_id(global_id_from_iter),
.last_in_group(last_in_group)
);
// goes high one cycle after last_in_group. stays high until
// next cycle where 'issue' is high.
always @(posedge clock or negedge resetn) begin
if ( ~resetn )
just_seen_last_in_group <= 1'b1;
else if ( start )
just_seen_last_in_group <= 1'b1;
else if (last_in_group & issue)
just_seen_last_in_group <= 1'b1;
else if (issue)
just_seen_last_in_group <= 1'b0;
else
just_seen_last_in_group <= just_seen_last_in_group;
end
endmodule
|
/* pbkdfengine.v
*
* Copyright (c) 2013 kramble
* Parts copyright (c) 2011 [email protected]
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`define ICARUS // Comment this out when using the altera virtual_wire interface in ltcminer.v
`timescale 1ns/1ps
module pbkdfengine
(hash_clk, pbkdf_clk, data1, data2, data3, target, nonce_msb, nonce_out, golden_nonce_out, golden_nonce_match, loadnonce,
salsa_din, salsa_dout, salsa_busy, salsa_result, salsa_reset, salsa_start, salsa_shift, hash_out);
input hash_clk; // Just drives shift register
input pbkdf_clk;
input [255:0] data1;
input [255:0] data2;
input [127:0] data3;
input [31:0] target;
input [3:0] nonce_msb;
output reg [31:0] nonce_out;
output reg [31:0] hash_out; // Hash value for nonce_out (ztex port)
output [31:0] golden_nonce_out;
output golden_nonce_match; // Strobe valid one cycle on a match (needed for serial comms)
input loadnonce; // Strobe loads nonce (used for serial interface)
parameter SBITS = 8; // Shift data path width
input [SBITS-1:0] salsa_dout;
output [SBITS-1:0] salsa_din;
input salsa_busy, salsa_result; // NB hash_clk domain
output salsa_reset;
output salsa_start;
output reg salsa_shift = 1'b0; // NB hash_clk domain
reg [4:0]resetcycles = 4'd0;
reg reset = 1'b0;
assign salsa_reset = reset; // Propagate reset to salsaengine
`ifdef WANTCYCLICRESET
reg [23:0]cycresetcount = 24'd0;
`endif
always @ (posedge pbkdf_clk)
begin
// Hard code a 31 cycle reset (NB assumes THREADS=16 in salsaengine, else we need more)
// NB hash_clk is faster than pbkdf_clk so the salsaengine will actually be initialised well before
// this period ends, but keep to 15 for now as simulation uses equal pbkdf and salsa clock speeds.
resetcycles <= resetcycles + 1'd1;
if (resetcycles == 0)
reset <= 1'b1;
if (resetcycles == 31)
begin
reset <= 1'b0;
resetcycles <= 31;
end
`ifdef WANTCYCLICRESET
// Cyclical reset every 2_500_000 clocks to ensure salsa pipeline does not drift out of sync
// This may be unneccessary if we reset every loadnonce
// Actually it seems to do more harm than good, so disabled
cycresetcount <= cycresetcount + 1'd1;
if (cycresetcount == 2_500_000) // 10 per second at 25MHz (adjust as neccessary)
begin
cycresetcount <= 24'd0;
resetcycles <= 5'd0;
end
`endif
// Reset on loadnonce (the hash results will be junk anyway since data changes, so no loss of shares)
if (loadnonce)
resetcycles <= 5'd0;
end
`ifndef ICARUS
reg [31:0] nonce_previous_load = 32'hffffffff; // See note in salsa mix FSM
`endif
`ifndef NOMULTICORE
`ifdef SIM
reg [27:0] nonce_cnt = 28'h318f; // Start point for simulation (NB also define SIM in serial.v)
`else
reg [27:0] nonce_cnt = 28'd0; // Multiple cores use different prefix
`endif
wire [31:0] nonce;
assign nonce = { nonce_msb, nonce_cnt };
`else
reg [31:0] nonce = 32'd0; // NB Initially loaded from data3[127:96], see salsa mix FSM
`endif
reg [31:0] nonce_sr = 32'd0; // Nonce is shifted to salsaengine for storage/retrieval (hash_clk domain)
reg [31:0] golden_nonce = 32'd0;
assign golden_nonce_out = golden_nonce;
reg golden_nonce_match = 1'b0;
reg [2:0] nonce_wait = 3'd0;
reg [255:0] rx_state;
reg [511:0] rx_input;
wire [255:0] tx_hash;
reg [255:0] khash = 256'd0; // Key hash (NB scrypt.c calls this ihash)
reg [255:0] ihash = 256'd0; // IPAD hash
reg [255:0] ohash = 256'd0; // OPAD hash
`ifdef SIM
reg [255:0] final_hash = 256'd0; // Just for DEBUG, only need top 32 bits in live code.
`endif
reg [2:0] blockcnt = 3'd0; // Takes values 1..5 for block iteration
reg [1023:0] Xbuf = 1024'd0; // Shared input/output buffer and shift register (hash_clk domain)
reg [5:0] cnt = 6'd0;
wire feedback;
assign feedback = (cnt != 6'b0);
assign salsa_din = Xbuf[1023:1024-SBITS];
wire [1023:0] MixOutRewire; // Need to do endian conversion (see the generate below)
// MixOut is little-endian word format to match scrypt.c so convert back to big-endian
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : Xrewire
wire [31:0] mix;
assign mix = Xbuf[`IDX(i)]; // NB MixOut now shares Xbuf since shifted in/out
assign MixOutRewire[`IDX(i)] = { mix[7:0], mix[15:8], mix[23:16], mix[31:24] };
end
endgenerate
// Interface control. This should be OK provided the threads remain evenly spaced (hence we reset on loadnonce)
reg SMixInRdy_state = 1'b0; // SMix input ready flag (set in SHA256, reset in SMIX)
reg SMixOutRdy_state = 1'b0; // SMix output ready flag (set in SMIX, reset in SHA256)
wire SMixInRdy;
wire SMixOutRdy;
reg Set_SMixInRdy = 1'b0;
reg Clr_SMixOutRdy = 1'b0;
wire Clr_SMixInRdy;
wire Set_SMixOutRdy;
reg [4:0]salsa_busy_d = 0; // Sync to pbkdf_clk domain
reg [4:0]salsa_result_d = 0;
always @ (posedge hash_clk)
begin
// Sync to pbkdf_clk domain
salsa_busy_d[0] <= salsa_busy;
if (salsa_busy & ~ salsa_busy_d[0])
salsa_busy_d[1] <= ~ salsa_busy_d[1]; // Toggle on busy going high
salsa_result_d[0] <= salsa_result;
if (salsa_result & ~ salsa_result_d[0])
salsa_result_d[1] <= ~ salsa_result_d[1]; // Toggle on result going high
end
always @ (posedge pbkdf_clk)
begin
salsa_busy_d[4:2] <= salsa_busy_d[3:1];
salsa_result_d[4:2] <= salsa_result_d[3:1];
if (Set_SMixInRdy)
SMixInRdy_state <= 1'b1;
if (Clr_SMixInRdy)
SMixInRdy_state <= 1'b0; // Clr overrides set
if (Set_SMixOutRdy)
SMixOutRdy_state <= 1'b1;
if (Clr_SMixOutRdy)
SMixOutRdy_state <= 1'b0; // Clr overrides set
// CARE there is a race with Set_SMixInRdy, Clr_SMixOutRdy which are set in the FSM
// Need to assert reset for several cycles to ensure consistency (acutally use 15 since salsaengine needs more)
if (reset)
begin // Reset takes priority
SMixInRdy_state <= 1'b0;
SMixOutRdy_state <= 1'b0;
end
end
assign Clr_SMixInRdy = SMixInRdy_state & (salsa_busy_d[3] ^ salsa_busy_d[4]); // Clear on transition to busy
assign Set_SMixOutRdy = ~SMixOutRdy_state & (salsa_result_d[3] ^ salsa_result_d[4]); // Set on transition to result
// Achieves identical timing to original version, but probably overkill
assign SMixInRdy = Clr_SMixInRdy ? 1'b0 : Set_SMixInRdy ? 1'b1 : SMixInRdy_state;
assign SMixOutRdy = Clr_SMixOutRdy ? 1'b0 : Set_SMixOutRdy ? 1'b1 : SMixOutRdy_state;
assign salsa_start = SMixInRdy;
// Clock crossing flags for shift register control (span pbkdf_clk, hash_clk domains)
reg [3:0]Xbuf_load_request = 1'b0;
reg [3:0]shift_request = 1'b0;
reg [3:0]shift_acknowledge = 1'b0;
// Controller FSM for PBKDF2_SHA256_80_128 (multiple hashes using the sha256_transform)
// Based on scrypt.c from cgminer (Colin Percival, ArtForz)
parameter S_IDLE=0,
S_H1= 1, S_H2= 2, S_H3= 3, S_H4= 4, S_H5= 5, S_H6= 6, // Initial hash of block header (khash)
S_I1= 7, S_I2= 8, S_I3= 9, S_I4=10, S_I5=11, S_I6=12, // IPAD hash (ihash)
S_O1=13, S_O2=14, S_O3=15, // OPAD hash (ohash)
S_B1=16, S_B2=17, S_B3=18, S_B4=19, S_B5=20, S_B6=21, // Iterate blocks
S_NONCE=22, S_SHIFT_IN=41, S_SHIFT_OUT=42, // Direction relative to salsa unit
// Final PBKDF2_SHA256_80_128_32 (reuses S_H1 to S_H6 for khash, alternatively could piplenine value)
S_R1=23, S_R2=24, S_R3=25, S_R4=26, S_R5=27, S_R6=28, // Final PBKDF2_SHA256_80_128_32
S_R7=29, S_R8=30, S_R9=31, S_R10=32, S_R11=33, S_R12=34,
S_R13=35, S_R14=36, S_R15=37, S_R16=38, S_R17=39, S_R18=40;
reg [5:0] state = S_IDLE;
reg mode = 0; // 0=PBKDF2_SHA256_80_128, 1=PBKDF2_SHA256_80_128_32
reg start_output = 0;
always @ (posedge pbkdf_clk)
begin
Set_SMixInRdy <= 1'b0; // Ugly hack, these are overriden below
Clr_SMixOutRdy <= 1'b0;
golden_nonce_match <= 1'b0; // Default to reset
shift_acknowledge[3:1] <= shift_acknowledge[2:0]; // Clock crossing
`ifdef ICARUS
if (loadnonce) // Separate clock domains means comparison is unsafe
`else
if (loadnonce || (nonce_previous_load != data3[127:96]))
`endif
begin
`ifdef NOMULTICORE
nonce <= data3[127:96]; // Supports loading of initial nonce for test purposes (potentially
// overriden by the increment below, but this occurs very rarely)
// This also gives a consistent start point when we send the first work
// packet (but ONLY the first one since its always zero) when using live data
// as we initialise nonce_previous_load to ffffffff
`else
nonce_cnt <= data3[123:96]; // The 4 msb of nonce are hardwired in MULTICORE mode, so test nonce
// needs to be <= 0fffffff and will only match in the 0 core
`endif
`ifndef ICARUS
nonce_previous_load <= data3[127:96];
`endif
end
if (reset == 1'b1)
begin
state <= S_IDLE;
start_output <= 1'b0;
end
else
begin
case (state)
S_IDLE: begin
if (SMixOutRdy & ~start_output)
begin
shift_request[0] <= ~shift_request[0]; // Request shifter to start
state <= S_SHIFT_OUT;
end
else
begin
if (start_output || // Process output
!SMixInRdy) // Process input unless already done
begin
start_output <= 1'b0;
mode <= 1'b0;
// Both cases use same initial calculaton of khash (its not worth trying to reuse previous khash
// for the second case as we're not constrained by SHA256 timing)
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { data2, data1 }; // Block header is passwd (used as key)
blockcnt <= 3'd1;
cnt <= 6'd0;
if (SMixOutRdy) // Give preference to output
mode <= 1'b1;
state <= S_H1;
end
end
end
// Hash the block header (result is khash)
S_H1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H2;
end
end
S_H2: begin // Sync hash
state <= S_H3;
end
S_H3: begin // Sync hash
rx_state <= tx_hash;
// Hash last 16 bytes of header including nonce and padded to 64 bytes with 1, zeros and length
// NB this sequence is used for both input and final PBKDF2_SHA256, hence switch nonce on mode
rx_input <= { 384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000,
mode ? nonce_sr : nonce, data3[95:0] };
state <= S_H4;
end
S_H4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H5;
end
end
S_H5: begin // Sync hash
state <= S_H6;
end
S_H6: begin // Sync hash
khash <= tx_hash; // Save for OPAD hash
// Setup for IPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h3636363636363636363636363636363636363636363636363636363636363636 ,
tx_hash ^ 256'h3636363636363636363636363636363636363636363636363636363636363636 };
cnt <= 6'd0;
if (mode)
state <= S_R1;
else
state <= S_I1;
end
// IPAD hash
S_I1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I2;
end
end
S_I2: begin // Sync hash
state <= S_I3;
end
S_I3: begin // Sync hash
rx_state <= tx_hash;
rx_input <= { data2, data1 }; // Passwd (used as message)
state <= S_I4;
end
S_I4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I5;
end
end
S_I5: begin // Sync hash
state <= S_I6;
end
S_I6: begin // Sync hash
ihash <= tx_hash; // Save result
// Setup for OPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_O1;
end
// OPAD hash
S_O1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_O2;
end
end
S_O2: begin // Sync hash
state <= S_O3;
end
S_O3: begin // Sync hash
ohash <= tx_hash; // Save result
// Setup for block iteration
rx_state <= ihash;
// TODO hardwire top 29 bits of blockcnt as zero
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
29'd0, blockcnt, nonce, data3[95:0] }; // blockcnt is 3 bits, top 29 are hardcoded 0
blockcnt <= blockcnt + 1'd1; // Increment for next time
cnt <= 6'd0;
state <= S_B1;
end
// Block iteration (4 cycles)
S_B1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B2;
end
end
S_B2: begin // Sync hash
state <= S_B3;
end
S_B3: begin // Sync hash
rx_state <= ohash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, tx_hash };
state <= S_B4;
end
S_B4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B5;
end
end
S_B5: begin // Sync hash
state <= S_B6;
end
S_B6: begin
khash <= tx_hash; // Save temporarily (for Xbuf)
Xbuf_load_request[0] <= ~Xbuf_load_request[0]; // NB also loads nonce_sr
if (blockcnt == 3'd5)
begin
nonce_wait <= 3'd7;
state <= S_NONCE;
end
else begin
// Setup for next block
rx_state <= ihash;
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
29'd0, blockcnt, nonce, data3[95:0] }; // blockcnt is 3 bits, top 29 are hardcoded 0
blockcnt <= blockcnt + 1'd1; // Increment for next time
cnt <= 6'd0;
state <= S_B1;
end
end
S_NONCE: begin
// Need to delay a few clocks for Xbuf_load_request to complete
nonce_wait <= nonce_wait - 1'd1;
if (nonce_wait == 0)
begin
`ifndef NOMULTICORE
nonce_cnt <= nonce_cnt + 1'd1;
`else
nonce <= nonce + 1'd1;
`endif
shift_request[0] <= ~shift_request[0];
state <= S_SHIFT_IN;
end
end
S_SHIFT_IN: begin // Shifting from PBKDF2_SHA256 to salsa
if (shift_acknowledge[3] != shift_acknowledge[2])
begin
Set_SMixInRdy <= 1'd1; // Flag salsa to start
state <= S_IDLE;
end
end
S_SHIFT_OUT: begin // Shifting from salsa to PBKDF2_SHA256
if (shift_acknowledge[3] != shift_acknowledge[2])
begin
start_output <= 1'd1; // Flag self to start
state <= S_IDLE;
end
end
// Final PBKDF2_SHA256_80_128_32 NB Entered from S_H6 via mode flag
// Similar to S_I0 but using MixOut as salt and finalblk padding
S_R1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R2;
end
end
S_R2: begin // Sync hash
state <= S_R3;
end
S_R3: begin // Sync hash
rx_state <= tx_hash;
rx_input <= MixOutRewire[511:0]; // Salt (first block)
state <= S_R4;
end
S_R4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R5;
end
end
S_R5: begin // Sync hash
state <= S_R6;
end
S_R6: begin // Sync hash
rx_state <= tx_hash;
rx_input <= MixOutRewire[1023:512]; // Salt (second block)
state <= S_R7;
end
S_R7: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R8;
end
end
S_R8: begin // Sync hash
state <= S_R9;
end
S_R9: begin // Sync hash
rx_state <= tx_hash;
// Final padding
rx_input <= 512'h00000620000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000001;
state <= S_R10;
end
S_R10: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R11;
end
end
S_R11: begin // Sync hash
state <= S_R12;
end
S_R12: begin // Sync hash
ihash <= tx_hash; // Save (reuse ihash)
// Setup for OPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_R13;
end
S_R13: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R14;
end
end
S_R14: begin // Sync hash
state <= S_R15;
end
S_R15: begin // Sync hash
rx_state <= tx_hash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, ihash };
state <= S_R16;
end
S_R16: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R17;
end
end
S_R17: begin // Sync hash
state <= S_R18;
end
S_R18: begin // Sync hash
// Check for golden nonce in tx_hash
`ifdef SIM
final_hash <= tx_hash; // For debug
`endif
nonce_out <= nonce_sr; // Ztex port
hash_out <= tx_hash[255:224];
// Could optimise target calc ...
if ( { tx_hash[231:224], tx_hash[239:232], tx_hash[247:240], tx_hash[255:248] } < target)
begin
golden_nonce <= nonce_sr;
golden_nonce_match <= 1'b1; // Set flag (for one cycle only, see default at top)
end
state <= S_IDLE;
mode <= 1'b0;
// SMixOutRdy <= 1'b0; // Original version
Clr_SMixOutRdy <= 1'b1; // Ugly hack
end
endcase
end
end
// Shift register control - NB hash_clk domain
reg [10:0]shift_count = 11'd0; // hash_clk domain
always @ (posedge hash_clk)
begin
if (reset)
begin
salsa_shift <= 1'b0;
shift_count <= 11'd0;
end
// Clock crossing logic
Xbuf_load_request[3:1] <= Xbuf_load_request[2:0];
if (Xbuf_load_request[3] != Xbuf_load_request[2])
begin
// Shift output into X buffer from MSB->LSB
Xbuf[255:0] <= Xbuf[511:256];
Xbuf[511:256] <= Xbuf[767:512];
Xbuf[767:512] <= Xbuf[1023:768];
Xbuf[1023:768] <= khash;
nonce_sr <= nonce; // Loaded several times, but of no consequence
end
shift_request[3:1] <= shift_request[2:0];
if (shift_request[3] != shift_request[2])
begin
salsa_shift <= 1'b1;
end
if (salsa_shift)
begin
shift_count <= shift_count + 1'b1;
Xbuf <= { Xbuf[1023-SBITS:0], nonce_sr[31:32-SBITS] };
nonce_sr <= { nonce_sr[31-SBITS:0], salsa_dout };
end
if (shift_count == (1024+32)/SBITS-1)
begin
shift_acknowledge[0] = ~shift_acknowledge[0];
shift_count <= 0;
salsa_shift <= 0;
end
end
// Using LOOP=64 to simplify timing (needs slightly modified version of original sha256_transform.v)
// since pipelining is inappropriate for ltc (we need to rehash same data several times in succession)
sha256_transform # (.LOOP(64)) sha256_blk (
.clk(pbkdf_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(rx_state),
.rx_input(rx_input),
.tx_hash(tx_hash)
);
endmodule |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//===----------------------------------------------------------------------===//
//
// C backend 'pop' primitive
//
//===----------------------------------------------------------------------===//
module acl_pop (
clock,
resetn,
// input stream from kernel pipeline
dir,
valid_in,
data_in,
stall_out,
predicate,
// downstream, to kernel pipeline
valid_out,
stall_in,
data_out,
// feedback downstream, from feedback acl_push
feedback_in,
feedback_valid_in,
feedback_stall_out
);
parameter DATA_WIDTH = 32;
parameter string STYLE = "REGULAR"; // REGULAR vs COALESCE
// this will pop garbage off of the feedback
localparam POP_GARBAGE = STYLE == "COALESCE" ? 1 : 0;
input clock, resetn, stall_in, valid_in, feedback_valid_in;
output stall_out, valid_out, feedback_stall_out;
input [DATA_WIDTH-1:0] data_in;
input dir;
input predicate;
output [DATA_WIDTH-1:0] data_out;
input [DATA_WIDTH-1:0] feedback_in;
wire feedback_downstream, data_downstream;
reg pop_garbage;
reg last_dir;
always @(posedge clock or negedge resetn)
begin
if ( !resetn ) begin
pop_garbage = 0;
end
else if ( valid_in && ~dir && last_dir ) begin
pop_garbage = POP_GARBAGE;
end
end
always @(posedge clock or negedge resetn)
begin
if ( !resetn ) begin
last_dir = 0;
end
else if ( valid_in ) begin
last_dir = dir;
end
end
assign feedback_downstream = valid_in & ~dir & feedback_valid_in;
assign data_downstream = valid_in & dir;
assign valid_out = feedback_downstream | ( data_downstream & (~pop_garbage | feedback_valid_in ) ) ;
assign data_out = ~dir ? feedback_in : data_in;
//assign stall_out = stall_in;
//assign stall_out = valid_in & ~((feedback_downstream | data_downstream) & ~stall_in);
// assign stall_out = ~((feedback_downstream | data_downstream) & ~stall_in);
// stall upstream if
// downstream is stalling (stall_in)
// I'm waiting for data from feedback (valid_in&~dir&~feedback_valiid_in)
assign stall_out = ( valid_in & ( ( ~dir & ~feedback_valid_in ) | ( dir & ~feedback_valid_in & pop_garbage ) ) ) | stall_in;
// don't accept data if:
// downstream cannot accept data (stall_in)
// data from upstream is selected (data_downstream)
// no thread exists to read data (~valid_in)
// predicate is high
assign feedback_stall_out = stall_in | (data_downstream & ~pop_garbage) | ~valid_in | predicate;
endmodule
|
/*
* This module sends commands to the PS2 interface
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse_cmdout (
input clk,
input reset,
input [7:0] the_command,
input send_command,
input ps2_clk_posedge,
input ps2_clk_negedge,
input inhibit,
inout ps2_clk,
inout ps2_dat,
output reg command_was_sent,
output reg error_communication_timed_out
);
// --------------------------------------------------------------------
// Parameter Declarations , 1/12.5mhz => 0.08us
// --------------------------------------------------------------------
parameter CLOCK_CYCLES_FOR_101US = 1262; // Timing info for initiating
parameter NUMBER_OF_BITS_FOR_101US = 13; // Host-to-Device communication
parameter COUNTER_INCREMENT_FOR_101US = 13'h0001; // when using a 12.5MHz system clock
parameter CLOCK_CYCLES_FOR_15MS = 187500; // Timing info for start of
parameter NUMBER_OF_BITS_FOR_15MS = 20; // transmission error when
parameter COUNTER_INCREMENT_FOR_15MS = 20'h00001; // using a 12.5MHz system clock
parameter CLOCK_CYCLES_FOR_2MS = 25000; // Timing info for sending
parameter NUMBER_OF_BITS_FOR_2MS = 17; // data error when
parameter COUNTER_INCREMENT_FOR_2MS = 17'h00001; // using a 12.5MHz system clock
// --------------------------------------------------------------------
// Constant Declarations
// --------------------------------------------------------------------
parameter PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_INITIATE_COMMUNICATION = 3'h1,
PS2_STATE_2_WAIT_FOR_CLOCK = 3'h2,
PS2_STATE_3_TRANSMIT_DATA = 3'h3,
PS2_STATE_4_TRANSMIT_STOP_BIT = 3'h4,
PS2_STATE_5_RECEIVE_ACK_BIT = 3'h5,
PS2_STATE_6_COMMAND_WAS_SENT = 3'h6,
PS2_STATE_7_TRANSMISSION_ERROR = 3'h7;
// --------------------------------------------------------------------
// Internal wires and registers Declarations
// --------------------------------------------------------------------
reg [3:0] cur_bit; // Internal Registers
reg [8:0] ps2_command;
reg [NUMBER_OF_BITS_FOR_101US:1] command_initiate_counter;
reg [NUMBER_OF_BITS_FOR_15MS:1] waiting_counter;
reg [NUMBER_OF_BITS_FOR_2MS:1] transfer_counter;
reg [2:0] ns_ps2_transmitter; // State Machine Registers
reg [2:0] s_ps2_transmitter;
// --------------------------------------------------------------------
// Finite State Machine(s)
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) s_ps2_transmitter <= PS2_STATE_0_IDLE;
else s_ps2_transmitter <= ns_ps2_transmitter;
end
always @(*) begin // Defaults
ns_ps2_transmitter = PS2_STATE_0_IDLE;
case (s_ps2_transmitter)
PS2_STATE_0_IDLE:
begin
if (send_command == 1'b1) ns_ps2_transmitter = PS2_STATE_1_INITIATE_COMMUNICATION;
else ns_ps2_transmitter = PS2_STATE_0_IDLE;
end
PS2_STATE_1_INITIATE_COMMUNICATION:
begin
if (command_initiate_counter == CLOCK_CYCLES_FOR_101US)
ns_ps2_transmitter = PS2_STATE_2_WAIT_FOR_CLOCK;
else
ns_ps2_transmitter = PS2_STATE_1_INITIATE_COMMUNICATION;
end
PS2_STATE_2_WAIT_FOR_CLOCK:
begin
if (ps2_clk_negedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_3_TRANSMIT_DATA;
else if (waiting_counter == CLOCK_CYCLES_FOR_15MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_2_WAIT_FOR_CLOCK;
end
PS2_STATE_3_TRANSMIT_DATA:
begin
if ((cur_bit == 4'd8) && (ps2_clk_negedge == 1'b1))
ns_ps2_transmitter = PS2_STATE_4_TRANSMIT_STOP_BIT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_3_TRANSMIT_DATA;
end
PS2_STATE_4_TRANSMIT_STOP_BIT:
begin
if (ps2_clk_negedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_5_RECEIVE_ACK_BIT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_4_TRANSMIT_STOP_BIT;
end
PS2_STATE_5_RECEIVE_ACK_BIT:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_6_COMMAND_WAS_SENT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_5_RECEIVE_ACK_BIT;
end
PS2_STATE_6_COMMAND_WAS_SENT:
begin
if (send_command == 1'b0)
ns_ps2_transmitter = PS2_STATE_0_IDLE;
else
ns_ps2_transmitter = PS2_STATE_6_COMMAND_WAS_SENT;
end
PS2_STATE_7_TRANSMISSION_ERROR:
begin
if (send_command == 1'b0)
ns_ps2_transmitter = PS2_STATE_0_IDLE;
else
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
end
default:
begin
ns_ps2_transmitter = PS2_STATE_0_IDLE;
end
endcase
end
// --------------------------------------------------------------------
// Sequential logic
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) ps2_command <= 9'h000;
else if(s_ps2_transmitter == PS2_STATE_0_IDLE)
ps2_command <= {(^the_command) ^ 1'b1, the_command};
end
always @(posedge clk) begin
if(reset == 1'b1) command_initiate_counter <= {NUMBER_OF_BITS_FOR_101US{1'b0}};
else if((s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) &&
(command_initiate_counter != CLOCK_CYCLES_FOR_101US))
command_initiate_counter <=
command_initiate_counter + COUNTER_INCREMENT_FOR_101US;
else if(s_ps2_transmitter != PS2_STATE_1_INITIATE_COMMUNICATION)
command_initiate_counter <= {NUMBER_OF_BITS_FOR_101US{1'b0}};
end
always @(posedge clk) begin
if(reset == 1'b1) waiting_counter <= {NUMBER_OF_BITS_FOR_15MS{1'b0}};
else if((s_ps2_transmitter == PS2_STATE_2_WAIT_FOR_CLOCK) &&
(waiting_counter != CLOCK_CYCLES_FOR_15MS))
waiting_counter <= waiting_counter + COUNTER_INCREMENT_FOR_15MS;
else if(s_ps2_transmitter != PS2_STATE_2_WAIT_FOR_CLOCK)
waiting_counter <= {NUMBER_OF_BITS_FOR_15MS{1'b0}};
end
always @(posedge clk) begin
if(reset == 1'b1) transfer_counter <= {NUMBER_OF_BITS_FOR_2MS{1'b0}};
else begin
if((s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) ||
(s_ps2_transmitter == PS2_STATE_4_TRANSMIT_STOP_BIT) ||
(s_ps2_transmitter == PS2_STATE_5_RECEIVE_ACK_BIT))
begin
if(transfer_counter != CLOCK_CYCLES_FOR_2MS)
transfer_counter <= transfer_counter + COUNTER_INCREMENT_FOR_2MS;
end
else transfer_counter <= {NUMBER_OF_BITS_FOR_2MS{1'b0}};
end
end
always @(posedge clk) begin
if(reset == 1'b1) cur_bit <= 4'h0;
else if((s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) &&
(ps2_clk_negedge == 1'b1))
cur_bit <= cur_bit + 4'h1;
else if(s_ps2_transmitter != PS2_STATE_3_TRANSMIT_DATA)
cur_bit <= 4'h0;
end
always @(posedge clk) begin
if(reset == 1'b1) command_was_sent <= 1'b0;
else if(s_ps2_transmitter == PS2_STATE_6_COMMAND_WAS_SENT)
command_was_sent <= 1'b1;
else if(send_command == 1'b0) command_was_sent <= 1'b0;
end
always @(posedge clk) begin
if(reset == 1'b1) error_communication_timed_out <= 1'b0;
else if(s_ps2_transmitter == PS2_STATE_7_TRANSMISSION_ERROR)
error_communication_timed_out <= 1'b1;
else if(send_command == 1'b0)
error_communication_timed_out <= 1'b0;
end
// --------------------------------------------------------------------
// Combinational logic
// --------------------------------------------------------------------
assign ps2_clk = (s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION || inhibit) ? 1'b0 : 1'bz;
assign ps2_dat = (s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) ? ps2_command[cur_bit] :
(s_ps2_transmitter == PS2_STATE_2_WAIT_FOR_CLOCK) ? 1'b0 :
((s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) &&
(command_initiate_counter[NUMBER_OF_BITS_FOR_101US] == 1'b1)) ? 1'b0 : 1'bz;
endmodule
|
// megafunction wizard: %ALTFP_COMPARE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altfp_compare
// ============================================================
// File Name: acl_fp_cmp.v
// Megafunction Name(s):
// altfp_compare
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altfp_compare CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=3 WIDTH_EXP=8 WIDTH_MAN=23 aeb agb ageb alb aleb aneb clk_en clock dataa datab unordered
//VERSION_BEGIN 10.0SP1 cbx_altfp_compare 2010:08:18:21:07:09:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = lpm_compare 4 reg 25
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_cmp_altfp_compare_6me
(
aeb,
agb,
ageb,
alb,
aleb,
aneb,
clk_en,
clock,
dataa,
datab,
unordered) ;
output aeb;
output agb;
output ageb;
output alb;
output aleb;
output aneb;
input clk_en;
input clock;
input [31:0] dataa;
input [31:0] datab;
output unordered;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg aligned_dataa_sign_adjusted_w_dffe2;
reg aligned_dataa_sign_dffe1;
reg aligned_datab_sign_adjusted_w_dffe2;
reg aligned_datab_sign_dffe1;
reg both_inputs_zero_dffe2;
reg exp_a_all_one_w_dffe1;
reg exp_a_not_zero_w_dffe1;
reg exp_aeb_w_dffe2;
reg exp_agb_w_dffe2;
reg exp_b_all_one_w_dffe1;
reg exp_b_not_zero_w_dffe1;
reg flip_outputs_dffe2;
reg input_dataa_nan_dffe2;
reg input_datab_nan_dffe2;
reg [1:0] man_a_not_zero_w_dffe1;
reg [1:0] man_b_not_zero_w_dffe1;
reg out_aeb_w_dffe3;
reg out_agb_w_dffe3;
reg out_ageb_w_dffe3;
reg out_alb_w_dffe3;
reg out_aleb_w_dffe3;
reg out_aneb_w_dffe3;
reg out_unordered_w_dffe3;
wire wire_cmpr1_aeb;
wire wire_cmpr1_agb;
wire wire_cmpr2_aeb;
wire wire_cmpr2_agb;
wire wire_cmpr3_aeb;
wire wire_cmpr3_agb;
wire wire_cmpr4_aeb;
wire wire_cmpr4_agb;
wire aclr;
wire aligned_dataa_sign_adjusted_dffe2_wi;
wire aligned_dataa_sign_adjusted_dffe2_wo;
wire aligned_dataa_sign_adjusted_w;
wire aligned_dataa_sign_dffe1_wi;
wire aligned_dataa_sign_dffe1_wo;
wire aligned_dataa_sign_w;
wire [30:0] aligned_dataa_w;
wire aligned_datab_sign_adjusted_dffe2_wi;
wire aligned_datab_sign_adjusted_dffe2_wo;
wire aligned_datab_sign_adjusted_w;
wire aligned_datab_sign_dffe1_wi;
wire aligned_datab_sign_dffe1_wo;
wire aligned_datab_sign_w;
wire [30:0] aligned_datab_w;
wire both_inputs_zero;
wire both_inputs_zero_dffe2_wi;
wire both_inputs_zero_dffe2_wo;
wire exp_a_all_one_dffe1_wi;
wire exp_a_all_one_dffe1_wo;
wire [7:0] exp_a_all_one_w;
wire exp_a_not_zero_dffe1_wi;
wire exp_a_not_zero_dffe1_wo;
wire [7:0] exp_a_not_zero_w;
wire [3:0] exp_aeb;
wire [3:0] exp_aeb_tmp_w;
wire exp_aeb_w;
wire exp_aeb_w_dffe2_wi;
wire exp_aeb_w_dffe2_wo;
wire [3:0] exp_agb;
wire [3:0] exp_agb_tmp_w;
wire exp_agb_w;
wire exp_agb_w_dffe2_wi;
wire exp_agb_w_dffe2_wo;
wire exp_b_all_one_dffe1_wi;
wire exp_b_all_one_dffe1_wo;
wire [7:0] exp_b_all_one_w;
wire exp_b_not_zero_dffe1_wi;
wire exp_b_not_zero_dffe1_wo;
wire [7:0] exp_b_not_zero_w;
wire [2:0] exp_eq_grp;
wire [3:0] exp_eq_gt_grp;
wire flip_outputs_dffe2_wi;
wire flip_outputs_dffe2_wo;
wire flip_outputs_w;
wire input_dataa_nan_dffe2_wi;
wire input_dataa_nan_dffe2_wo;
wire input_dataa_nan_w;
wire input_dataa_zero_w;
wire input_datab_nan_dffe2_wi;
wire input_datab_nan_dffe2_wo;
wire input_datab_nan_w;
wire input_datab_zero_w;
wire [1:0] man_a_not_zero_dffe1_wi;
wire [1:0] man_a_not_zero_dffe1_wo;
wire [1:0] man_a_not_zero_merge_w;
wire [22:0] man_a_not_zero_w;
wire [1:0] man_b_not_zero_dffe1_wi;
wire [1:0] man_b_not_zero_dffe1_wo;
wire [1:0] man_b_not_zero_merge_w;
wire [22:0] man_b_not_zero_w;
wire out_aeb_dffe3_wi;
wire out_aeb_dffe3_wo;
wire out_aeb_w;
wire out_agb_dffe3_wi;
wire out_agb_dffe3_wo;
wire out_agb_w;
wire out_ageb_dffe3_wi;
wire out_ageb_dffe3_wo;
wire out_ageb_w;
wire out_alb_dffe3_wi;
wire out_alb_dffe3_wo;
wire out_alb_w;
wire out_aleb_dffe3_wi;
wire out_aleb_dffe3_wo;
wire out_aleb_w;
wire out_aneb_dffe3_wi;
wire out_aneb_dffe3_wo;
wire out_aneb_w;
wire out_unordered_dffe3_wi;
wire out_unordered_dffe3_wo;
wire out_unordered_w;
// synopsys translate_off
initial
aligned_dataa_sign_adjusted_w_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_dataa_sign_adjusted_w_dffe2 <= 1'b0;
else if (clk_en == 1'b1) aligned_dataa_sign_adjusted_w_dffe2 <= aligned_dataa_sign_adjusted_dffe2_wi;
// synopsys translate_off
initial
aligned_dataa_sign_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_dataa_sign_dffe1 <= 1'b0;
else if (clk_en == 1'b1) aligned_dataa_sign_dffe1 <= aligned_dataa_sign_dffe1_wi;
// synopsys translate_off
initial
aligned_datab_sign_adjusted_w_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_datab_sign_adjusted_w_dffe2 <= 1'b0;
else if (clk_en == 1'b1) aligned_datab_sign_adjusted_w_dffe2 <= aligned_datab_sign_adjusted_dffe2_wi;
// synopsys translate_off
initial
aligned_datab_sign_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_datab_sign_dffe1 <= 1'b0;
else if (clk_en == 1'b1) aligned_datab_sign_dffe1 <= aligned_datab_sign_dffe1_wi;
// synopsys translate_off
initial
both_inputs_zero_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) both_inputs_zero_dffe2 <= 1'b0;
else if (clk_en == 1'b1) both_inputs_zero_dffe2 <= both_inputs_zero_dffe2_wi;
// synopsys translate_off
initial
exp_a_all_one_w_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_a_all_one_w_dffe1 <= 1'b0;
else if (clk_en == 1'b1) exp_a_all_one_w_dffe1 <= exp_a_all_one_dffe1_wi;
// synopsys translate_off
initial
exp_a_not_zero_w_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_a_not_zero_w_dffe1 <= 1'b0;
else if (clk_en == 1'b1) exp_a_not_zero_w_dffe1 <= exp_a_not_zero_dffe1_wi;
// synopsys translate_off
initial
exp_aeb_w_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_aeb_w_dffe2 <= 1'b0;
else if (clk_en == 1'b1) exp_aeb_w_dffe2 <= exp_aeb_w_dffe2_wi;
// synopsys translate_off
initial
exp_agb_w_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_agb_w_dffe2 <= 1'b0;
else if (clk_en == 1'b1) exp_agb_w_dffe2 <= exp_agb_w_dffe2_wi;
// synopsys translate_off
initial
exp_b_all_one_w_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_b_all_one_w_dffe1 <= 1'b0;
else if (clk_en == 1'b1) exp_b_all_one_w_dffe1 <= exp_b_all_one_dffe1_wi;
// synopsys translate_off
initial
exp_b_not_zero_w_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_b_not_zero_w_dffe1 <= 1'b0;
else if (clk_en == 1'b1) exp_b_not_zero_w_dffe1 <= exp_b_not_zero_dffe1_wi;
// synopsys translate_off
initial
flip_outputs_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) flip_outputs_dffe2 <= 1'b0;
else if (clk_en == 1'b1) flip_outputs_dffe2 <= flip_outputs_dffe2_wi;
// synopsys translate_off
initial
input_dataa_nan_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_dataa_nan_dffe2 <= 1'b0;
else if (clk_en == 1'b1) input_dataa_nan_dffe2 <= input_dataa_nan_dffe2_wi;
// synopsys translate_off
initial
input_datab_nan_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_datab_nan_dffe2 <= 1'b0;
else if (clk_en == 1'b1) input_datab_nan_dffe2 <= input_datab_nan_dffe2_wi;
// synopsys translate_off
initial
man_a_not_zero_w_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_a_not_zero_w_dffe1 <= 2'b0;
else if (clk_en == 1'b1) man_a_not_zero_w_dffe1 <= man_a_not_zero_dffe1_wi;
// synopsys translate_off
initial
man_b_not_zero_w_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_b_not_zero_w_dffe1 <= 2'b0;
else if (clk_en == 1'b1) man_b_not_zero_w_dffe1 <= man_b_not_zero_dffe1_wi;
// synopsys translate_off
initial
out_aeb_w_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) out_aeb_w_dffe3 <= 1'b0;
else if (clk_en == 1'b1) out_aeb_w_dffe3 <= out_aeb_dffe3_wi;
// synopsys translate_off
initial
out_agb_w_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) out_agb_w_dffe3 <= 1'b0;
else if (clk_en == 1'b1) out_agb_w_dffe3 <= out_agb_dffe3_wi;
// synopsys translate_off
initial
out_ageb_w_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) out_ageb_w_dffe3 <= 1'b0;
else if (clk_en == 1'b1) out_ageb_w_dffe3 <= out_ageb_dffe3_wi;
// synopsys translate_off
initial
out_alb_w_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) out_alb_w_dffe3 <= 1'b0;
else if (clk_en == 1'b1) out_alb_w_dffe3 <= out_alb_dffe3_wi;
// synopsys translate_off
initial
out_aleb_w_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) out_aleb_w_dffe3 <= 1'b0;
else if (clk_en == 1'b1) out_aleb_w_dffe3 <= out_aleb_dffe3_wi;
// synopsys translate_off
initial
out_aneb_w_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) out_aneb_w_dffe3 <= 1'b0;
else if (clk_en == 1'b1) out_aneb_w_dffe3 <= out_aneb_dffe3_wi;
// synopsys translate_off
initial
out_unordered_w_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) out_unordered_w_dffe3 <= 1'b0;
else if (clk_en == 1'b1) out_unordered_w_dffe3 <= out_unordered_dffe3_wi;
lpm_compare cmpr1
(
.aclr(aclr),
.aeb(wire_cmpr1_aeb),
.agb(wire_cmpr1_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.clken(clk_en),
.clock(clock),
.dataa(aligned_dataa_w[30:23]),
.datab(aligned_datab_w[30:23]));
defparam
cmpr1.lpm_pipeline = 1,
cmpr1.lpm_representation = "UNSIGNED",
cmpr1.lpm_width = 8,
cmpr1.lpm_type = "lpm_compare";
lpm_compare cmpr2
(
.aclr(aclr),
.aeb(wire_cmpr2_aeb),
.agb(wire_cmpr2_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.clken(clk_en),
.clock(clock),
.dataa(aligned_dataa_w[22:15]),
.datab(aligned_datab_w[22:15]));
defparam
cmpr2.lpm_pipeline = 1,
cmpr2.lpm_representation = "UNSIGNED",
cmpr2.lpm_width = 8,
cmpr2.lpm_type = "lpm_compare";
lpm_compare cmpr3
(
.aclr(aclr),
.aeb(wire_cmpr3_aeb),
.agb(wire_cmpr3_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.clken(clk_en),
.clock(clock),
.dataa(aligned_dataa_w[14:7]),
.datab(aligned_datab_w[14:7]));
defparam
cmpr3.lpm_pipeline = 1,
cmpr3.lpm_representation = "UNSIGNED",
cmpr3.lpm_width = 8,
cmpr3.lpm_type = "lpm_compare";
lpm_compare cmpr4
(
.aclr(aclr),
.aeb(wire_cmpr4_aeb),
.agb(wire_cmpr4_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.clken(clk_en),
.clock(clock),
.dataa(aligned_dataa_w[6:0]),
.datab(aligned_datab_w[6:0]));
defparam
cmpr4.lpm_pipeline = 1,
cmpr4.lpm_representation = "UNSIGNED",
cmpr4.lpm_width = 7,
cmpr4.lpm_type = "lpm_compare";
assign
aclr = 1'b0,
aeb = out_aeb_dffe3_wo,
agb = out_agb_dffe3_wo,
ageb = out_ageb_dffe3_wo,
alb = out_alb_dffe3_wo,
aleb = out_aleb_dffe3_wo,
aligned_dataa_sign_adjusted_dffe2_wi = aligned_dataa_sign_adjusted_w,
aligned_dataa_sign_adjusted_dffe2_wo = aligned_dataa_sign_adjusted_w_dffe2,
aligned_dataa_sign_adjusted_w = (aligned_dataa_sign_dffe1_wo & (~ input_dataa_zero_w)),
aligned_dataa_sign_dffe1_wi = aligned_dataa_sign_w,
aligned_dataa_sign_dffe1_wo = aligned_dataa_sign_dffe1,
aligned_dataa_sign_w = dataa[31],
aligned_dataa_w = {dataa[30:0]},
aligned_datab_sign_adjusted_dffe2_wi = aligned_datab_sign_adjusted_w,
aligned_datab_sign_adjusted_dffe2_wo = aligned_datab_sign_adjusted_w_dffe2,
aligned_datab_sign_adjusted_w = (aligned_datab_sign_dffe1_wo & (~ input_datab_zero_w)),
aligned_datab_sign_dffe1_wi = aligned_datab_sign_w,
aligned_datab_sign_dffe1_wo = aligned_datab_sign_dffe1,
aligned_datab_sign_w = datab[31],
aligned_datab_w = {datab[30:0]},
aneb = out_aneb_dffe3_wo,
both_inputs_zero = (input_dataa_zero_w & input_datab_zero_w),
both_inputs_zero_dffe2_wi = both_inputs_zero,
both_inputs_zero_dffe2_wo = both_inputs_zero_dffe2,
exp_a_all_one_dffe1_wi = exp_a_all_one_w[7],
exp_a_all_one_dffe1_wo = exp_a_all_one_w_dffe1,
exp_a_all_one_w = {(dataa[30] & exp_a_all_one_w[6]), (dataa[29] & exp_a_all_one_w[5]), (dataa[28] & exp_a_all_one_w[4]), (dataa[27] & exp_a_all_one_w[3]), (dataa[26] & exp_a_all_one_w[2]), (dataa[25] & exp_a_all_one_w[1]), (dataa[24] & exp_a_all_one_w[0]), dataa[23]},
exp_a_not_zero_dffe1_wi = exp_a_not_zero_w[7],
exp_a_not_zero_dffe1_wo = exp_a_not_zero_w_dffe1,
exp_a_not_zero_w = {(dataa[30] | exp_a_not_zero_w[6]), (dataa[29] | exp_a_not_zero_w[5]), (dataa[28] | exp_a_not_zero_w[4]), (dataa[27] | exp_a_not_zero_w[3]), (dataa[26] | exp_a_not_zero_w[2]), (dataa[25] | exp_a_not_zero_w[1]), (dataa[24] | exp_a_not_zero_w[0]), dataa[23]},
exp_aeb = {wire_cmpr4_aeb, wire_cmpr3_aeb, wire_cmpr2_aeb, wire_cmpr1_aeb},
exp_aeb_tmp_w = {(exp_aeb[3] & exp_aeb_tmp_w[2]), (exp_aeb[2] & exp_aeb_tmp_w[1]), (exp_aeb[1] & exp_aeb_tmp_w[0]), exp_aeb[0]},
exp_aeb_w = exp_aeb_tmp_w[3],
exp_aeb_w_dffe2_wi = exp_aeb_w,
exp_aeb_w_dffe2_wo = exp_aeb_w_dffe2,
exp_agb = {wire_cmpr4_agb, wire_cmpr3_agb, wire_cmpr2_agb, wire_cmpr1_agb},
exp_agb_tmp_w = {(exp_agb_tmp_w[2] | exp_eq_gt_grp[3]), (exp_agb_tmp_w[1] | exp_eq_gt_grp[2]), (exp_agb_tmp_w[0] | exp_eq_gt_grp[1]), exp_eq_gt_grp[0]},
exp_agb_w = exp_agb_tmp_w[3],
exp_agb_w_dffe2_wi = exp_agb_w,
exp_agb_w_dffe2_wo = exp_agb_w_dffe2,
exp_b_all_one_dffe1_wi = exp_b_all_one_w[7],
exp_b_all_one_dffe1_wo = exp_b_all_one_w_dffe1,
exp_b_all_one_w = {(datab[30] & exp_b_all_one_w[6]), (datab[29] & exp_b_all_one_w[5]), (datab[28] & exp_b_all_one_w[4]), (datab[27] & exp_b_all_one_w[3]), (datab[26] & exp_b_all_one_w[2]), (datab[25] & exp_b_all_one_w[1]), (datab[24] & exp_b_all_one_w[0]), datab[23]},
exp_b_not_zero_dffe1_wi = exp_b_not_zero_w[7],
exp_b_not_zero_dffe1_wo = exp_b_not_zero_w_dffe1,
exp_b_not_zero_w = {(datab[30] | exp_b_not_zero_w[6]), (datab[29] | exp_b_not_zero_w[5]), (datab[28] | exp_b_not_zero_w[4]), (datab[27] | exp_b_not_zero_w[3]), (datab[26] | exp_b_not_zero_w[2]), (datab[25] | exp_b_not_zero_w[1]), (datab[24] | exp_b_not_zero_w[0]), datab[23]},
exp_eq_grp = {(exp_eq_grp[1] & exp_aeb[2]), (exp_eq_grp[0] & exp_aeb[1]), exp_aeb[0]},
exp_eq_gt_grp = {(exp_eq_grp[2] & exp_agb[3]), (exp_eq_grp[1] & exp_agb[2]), (exp_eq_grp[0] & exp_agb[1]), exp_agb[0]},
flip_outputs_dffe2_wi = flip_outputs_w,
flip_outputs_dffe2_wo = flip_outputs_dffe2,
flip_outputs_w = (aligned_dataa_sign_adjusted_w & aligned_datab_sign_adjusted_w),
input_dataa_nan_dffe2_wi = input_dataa_nan_w,
input_dataa_nan_dffe2_wo = input_dataa_nan_dffe2,
input_dataa_nan_w = (exp_a_all_one_dffe1_wo & man_a_not_zero_merge_w[1]),
input_dataa_zero_w = (~ exp_a_not_zero_dffe1_wo),
input_datab_nan_dffe2_wi = input_datab_nan_w,
input_datab_nan_dffe2_wo = input_datab_nan_dffe2,
input_datab_nan_w = (exp_b_all_one_dffe1_wo & man_b_not_zero_merge_w[1]),
input_datab_zero_w = (~ exp_b_not_zero_dffe1_wo),
man_a_not_zero_dffe1_wi = {man_a_not_zero_w[22], man_a_not_zero_w[11]},
man_a_not_zero_dffe1_wo = man_a_not_zero_w_dffe1,
man_a_not_zero_merge_w = {(man_a_not_zero_dffe1_wo[1] | man_a_not_zero_merge_w[0]), man_a_not_zero_dffe1_wo[0]},
man_a_not_zero_w = {(dataa[22] | man_a_not_zero_w[21]), (dataa[21] | man_a_not_zero_w[20]), (dataa[20] | man_a_not_zero_w[19]), (dataa[19] | man_a_not_zero_w[18]), (dataa[18] | man_a_not_zero_w[17]), (dataa[17] | man_a_not_zero_w[16]), (dataa[16] | man_a_not_zero_w[15]), (dataa[15] | man_a_not_zero_w[14]), (dataa[14] | man_a_not_zero_w[13]), (dataa[13] | man_a_not_zero_w[12]), dataa[12], (dataa[11] | man_a_not_zero_w[10]), (dataa[10] | man_a_not_zero_w[9]), (dataa[9] | man_a_not_zero_w[8]), (dataa[8] | man_a_not_zero_w[7]), (dataa[7] | man_a_not_zero_w[6]), (dataa[6] | man_a_not_zero_w[5]), (dataa[5] | man_a_not_zero_w[4]), (dataa[4] | man_a_not_zero_w[3]), (dataa[3] | man_a_not_zero_w[2]), (dataa[2] | man_a_not_zero_w[1]), (dataa[1] | man_a_not_zero_w[0]), dataa[0]},
man_b_not_zero_dffe1_wi = {man_b_not_zero_w[22], man_b_not_zero_w[11]},
man_b_not_zero_dffe1_wo = man_b_not_zero_w_dffe1,
man_b_not_zero_merge_w = {(man_b_not_zero_dffe1_wo[1] | man_b_not_zero_merge_w[0]), man_b_not_zero_dffe1_wo[0]},
man_b_not_zero_w = {(datab[22] | man_b_not_zero_w[21]), (datab[21] | man_b_not_zero_w[20]), (datab[20] | man_b_not_zero_w[19]), (datab[19] | man_b_not_zero_w[18]), (datab[18] | man_b_not_zero_w[17]), (datab[17] | man_b_not_zero_w[16]), (datab[16] | man_b_not_zero_w[15]), (datab[15] | man_b_not_zero_w[14]), (datab[14] | man_b_not_zero_w[13]), (datab[13] | man_b_not_zero_w[12]), datab[12], (datab[11] | man_b_not_zero_w[10]), (datab[10] | man_b_not_zero_w[9]), (datab[9] | man_b_not_zero_w[8]), (datab[8] | man_b_not_zero_w[7]), (datab[7] | man_b_not_zero_w[6]), (datab[6] | man_b_not_zero_w[5]), (datab[5] | man_b_not_zero_w[4]), (datab[4] | man_b_not_zero_w[3]), (datab[3] | man_b_not_zero_w[2]), (datab[2] | man_b_not_zero_w[1]), (datab[1] | man_b_not_zero_w[0]), datab[0]},
out_aeb_dffe3_wi = out_aeb_w,
out_aeb_dffe3_wo = out_aeb_w_dffe3,
out_aeb_w = ((((~ (aligned_dataa_sign_adjusted_dffe2_wo ^ aligned_datab_sign_adjusted_dffe2_wo)) & exp_aeb_w_dffe2_wo) | both_inputs_zero_dffe2_wo) & (~ out_unordered_w)),
out_agb_dffe3_wi = out_agb_w,
out_agb_dffe3_wo = out_agb_w_dffe3,
out_agb_w = (((((~ aligned_dataa_sign_adjusted_dffe2_wo) & aligned_datab_sign_adjusted_dffe2_wo) | ((exp_agb_w_dffe2_wo & (~ aligned_dataa_sign_adjusted_dffe2_wo)) & (~ both_inputs_zero_dffe2_wo))) | ((flip_outputs_dffe2_wo & (~ exp_agb_w_dffe2_wo)) & (~ out_aeb_w))) & (~ out_unordered_w)),
out_ageb_dffe3_wi = out_ageb_w,
out_ageb_dffe3_wo = out_ageb_w_dffe3,
out_ageb_w = ((out_agb_w | out_aeb_w) & (~ out_unordered_w)),
out_alb_dffe3_wi = out_alb_w,
out_alb_dffe3_wo = out_alb_w_dffe3,
out_alb_w = (((~ out_agb_w) & (~ out_aeb_w)) & (~ out_unordered_w)),
out_aleb_dffe3_wi = out_aleb_w,
out_aleb_dffe3_wo = out_aleb_w_dffe3,
out_aleb_w = ((out_alb_w | out_aeb_w) & (~ out_unordered_w)),
out_aneb_dffe3_wi = out_aneb_w,
out_aneb_dffe3_wo = out_aneb_w_dffe3,
out_aneb_w = ((~ out_aeb_w) & (~ out_unordered_w)),
out_unordered_dffe3_wi = out_unordered_w,
out_unordered_dffe3_wo = out_unordered_w_dffe3,
out_unordered_w = (input_dataa_nan_dffe2_wo | input_datab_nan_dffe2_wo),
unordered = out_unordered_dffe3_wo;
endmodule //acl_fp_cmp_altfp_compare_6me
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_cmp (
enable,
clock,
dataa,
datab,
result);
parameter COMPARISON_MODE = 0;
parameter UNORDERED_MODE = 0;
// The meaning of mode is:
// 0 -> ==
// 1 -> !=
// 2 -> >=
// 3 -> >
// 4 -> <=
// 5 -> <
input enable;
input clock;
input [31:0] dataa;
input [31:0] datab;
output reg result;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire sub_wire3;
wire sub_wire4;
wire sub_wire5;
wire sub_wire6;
wire aeb = sub_wire0;
wire aleb = sub_wire1;
wire unordered = sub_wire2;
wire ageb = sub_wire3;
wire alb = sub_wire4;
wire agb = sub_wire5;
wire aneb = sub_wire6;
acl_fp_cmp_altfp_compare_6me acl_fp_cmp_altfp_compare_6me_component (
.clk_en (enable),
.clock (clock),
.datab (datab),
.dataa (dataa),
.aeb (sub_wire0),
.aleb (sub_wire1),
.unordered (sub_wire2),
.ageb (sub_wire3),
.alb (sub_wire4),
.agb (sub_wire5),
.aneb (sub_wire6));
always@(*)
begin
case(COMPARISON_MODE)
1: result = (UNORDERED_MODE == 0) ? (aneb & ~unordered) : (aneb | unordered);
2: result = (UNORDERED_MODE == 0) ? (ageb & ~unordered) : (ageb | unordered);
3: result = (UNORDERED_MODE == 0) ? (agb & ~unordered) : (agb | unordered);
4: result = (UNORDERED_MODE == 0) ? (aleb & ~unordered) : (aleb | unordered);
5: result = (UNORDERED_MODE == 0) ? (alb & ~unordered) : (alb | unordered);
6: result = (UNORDERED_MODE == 0) ? (~unordered) : unordered;
default:
// default is the same as COMPARISON_MODE=0 and performs equality checking.
begin
result = (UNORDERED_MODE == 0) ? (aeb & ~unordered) : (aeb | unordered);
end
endcase
end
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "3"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
// Retrieval info: USED_PORT: aeb 0 0 0 0 OUTPUT NODEFVAL "aeb"
// Retrieval info: USED_PORT: agb 0 0 0 0 OUTPUT NODEFVAL "agb"
// Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
// Retrieval info: USED_PORT: alb 0 0 0 0 OUTPUT NODEFVAL "alb"
// Retrieval info: USED_PORT: aleb 0 0 0 0 OUTPUT NODEFVAL "aleb"
// Retrieval info: USED_PORT: aneb 0 0 0 0 OUTPUT NODEFVAL "aneb"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
// Retrieval info: USED_PORT: unordered 0 0 0 0 OUTPUT NODEFVAL "unordered"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
// Retrieval info: CONNECT: aeb 0 0 0 0 @aeb 0 0 0 0
// Retrieval info: CONNECT: agb 0 0 0 0 @agb 0 0 0 0
// Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
// Retrieval info: CONNECT: alb 0 0 0 0 @alb 0 0 0 0
// Retrieval info: CONNECT: aleb 0 0 0 0 @aleb 0 0 0 0
// Retrieval info: CONNECT: aneb 0 0 0 0 @aneb 0 0 0 0
// Retrieval info: CONNECT: unordered 0 0 0 0 @unordered 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_cmp.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_cmp.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_cmp.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_cmp.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_cmp_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_cmp_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32O_BEHAVIORAL_V
`define SKY130_FD_SC_HS__A32O_BEHAVIORAL_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a32o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
// Local signals
wire B1 and0_out ;
wire B1 and1_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
and and1 (and1_out , B1, B2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32O_BEHAVIORAL_V |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.1
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_start_indices_ram (addr0, ce0, d0, we0, q0, clk);
parameter DWIDTH = 32;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_start_indices(
reset,
clk,
address0,
ce0,
we0,
d0,
q0);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
nfa_accept_samples_generic_hw_start_indices_ram nfa_accept_samples_generic_hw_start_indices_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O311AI_FUNCTIONAL_V
`define SKY130_FD_SC_MS__O311AI_FUNCTIONAL_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o311ai (
Y ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y, C1, or0_out, B1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O311AI_FUNCTIONAL_V |
(** * Hoare: Hoare Logic, Part I *)
Require Export Imp.
(** In the past couple of chapters, we've begun applying the
mathematical tools developed in the first part of the course to
studying the theory of a small programming language, Imp.
- We defined a type of _abstract syntax trees_ for Imp, together
with an _evaluation relation_ (a partial function on states)
that specifies the _operational semantics_ of programs.
The language we defined, though small, captures some of the key
features of full-blown languages like C, C++, and Java,
including the fundamental notion of mutable state and some
common control structures.
- We proved a number of _metatheoretic properties_ -- "meta" in
the sense that they are properties of the language as a whole,
rather than properties of particular programs in the language.
These included:
- determinism of evaluation
- equivalence of some different ways of writing down the
definitions (e.g. functional and relational definitions of
arithmetic expression evaluation)
- guaranteed termination of certain classes of programs
- correctness (in the sense of preserving meaning) of a number
of useful program transformations
- behavioral equivalence of programs (in the [Equiv] chapter).
If we stopped here, we would already have something useful: a set
of tools for defining and discussing programming languages and
language features that are mathematically precise, flexible, and
easy to work with, applied to a set of key properties. All of
these properties are things that language designers, compiler
writers, and users might care about knowing. Indeed, many of them
are so fundamental to our understanding of the programming
languages we deal with that we might not consciously recognize
them as "theorems." But properties that seem intuitively obvious
can sometimes be quite subtle (in some cases, even subtly wrong!).
We'll return to the theme of metatheoretic properties of whole
languages later in the course when we discuss _types_ and _type
soundness_. In this chapter, though, we'll turn to a different
set of issues.
Our goal is to see how to carry out some simple examples of
_program verification_ -- i.e., using the precise definition of
Imp to prove formally that particular programs satisfy particular
specifications of their behavior. We'll develop a reasoning system
called _Floyd-Hoare Logic_ -- often shortened to just _Hoare
Logic_ -- in which each of the syntactic constructs of Imp is
equipped with a single, generic "proof rule" that can be used to
reason compositionally about the correctness of programs involving
this construct.
Hoare Logic originates in the 1960s, and it continues to be the
subject of intensive research right up to the present day. It
lies at the core of a multitude of tools that are being used in
academia and industry to specify and verify real software
systems. *)
(* ####################################################### *)
(** * Hoare Logic *)
(** Hoare Logic combines two beautiful ideas: a natural way of
writing down _specifications_ of programs, and a _compositional
proof technique_ for proving that programs are correct with
respect to such specifications -- where by "compositional" we mean
that the structure of proofs directly mirrors the structure of the
programs that they are about. *)
(* ####################################################### *)
(** ** Assertions *)
(** To talk about specifications of programs, the first thing we
need is a way of making _assertions_ about properties that hold at
particular points during a program's execution -- i.e., claims
about the current state of the memory when program execution
reaches that point. Formally, an assertion is just a family of
propositions indexed by a [state]. *)
Definition Assertion := state -> Prop.
(** **** Exercise: 1 star, optional (assertions) *)
Module ExAssertions.
(** Paraphrase the following assertions in English. *)
Definition as1 : Assertion := fun st => st X = 3.
Definition as2 : Assertion := fun st => st X <= st Y.
Definition as3 : Assertion :=
fun st => st X = 3 \/ st X <= st Y.
Definition as4 : Assertion :=
fun st => st Z * st Z <= st X /\
~ (((S (st Z)) * (S (st Z))) <= st X).
Definition as5 : Assertion := fun st => True.
Definition as6 : Assertion := fun st => False.
(* FILL IN HERE *)
End ExAssertions.
(** [] *)
(* ####################################################### *)
(** ** Notation for Assertions *)
(** This way of writing assertions can be a little bit heavy,
for two reasons: (1) every single assertion that we ever write is
going to begin with [fun st => ]; and (2) this state [st] is the
only one that we ever use to look up variables (we will never need
to talk about two different memory states at the same time). For
discussing examples informally, we'll adopt some simplifying
conventions: we'll drop the initial [fun st =>], and we'll write
just [X] to mean [st X]. Thus, instead of writing *)
(**
fun st => (st Z) * (st Z) <= m /\
~ ((S (st Z)) * (S (st Z)) <= m)
we'll write just
Z * Z <= m /\ ~((S Z) * (S Z) <= m).
*)
(** Given two assertions [P] and [Q], we say that [P] _implies_ [Q],
written [P ->> Q] (in ASCII, [P -][>][> Q]), if, whenever [P]
holds in some state [st], [Q] also holds. *)
Definition assert_implies (P Q : Assertion) : Prop :=
forall st, P st -> Q st.
Notation "P ->> Q" :=
(assert_implies P Q) (at level 80) : hoare_spec_scope.
Open Scope hoare_spec_scope.
(** We'll also have occasion to use the "iff" variant of implication
between assertions: *)
Notation "P <<->> Q" :=
(P ->> Q /\ Q ->> P) (at level 80) : hoare_spec_scope.
(* ####################################################### *)
(** ** Hoare Triples *)
(** Next, we need a way of making formal claims about the
behavior of commands. *)
(** Since the behavior of a command is to transform one state to
another, it is natural to express claims about commands in terms
of assertions that are true before and after the command executes:
- "If command [c] is started in a state satisfying assertion
[P], and if [c] eventually terminates in some final state,
then this final state will satisfy the assertion [Q]."
Such a claim is called a _Hoare Triple_. The property [P] is
called the _precondition_ of [c], while [Q] is the
_postcondition_. Formally: *)
Definition hoare_triple
(P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
(** Since we'll be working a lot with Hoare triples, it's useful to
have a compact notation:
{{P}} c {{Q}}.
*)
(** (The traditional notation is [{P} c {Q}], but single braces
are already used for other things in Coq.) *)
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level)
: hoare_spec_scope.
(** (The [hoare_spec_scope] annotation here tells Coq that this
notation is not global but is intended to be used in particular
contexts. The [Open Scope] tells Coq that this file is one such
context.) *)
(** **** Exercise: 1 star, optional (triples) *)
(** Paraphrase the following Hoare triples in English.
1) {{True}} c {{X = 5}}
2) {{X = m}} c {{X = m + 5)}}
3) {{X <= Y}} c {{Y <= X}}
4) {{True}} c {{False}}
5) {{X = m}}
c
{{Y = real_fact m}}.
6) {{True}}
c
{{(Z * Z) <= m /\ ~ (((S Z) * (S Z)) <= m)}}
*)
(** [] *)
(** **** Exercise: 1 star, optional (valid_triples) *)
(** Which of the following Hoare triples are _valid_ -- i.e., the
claimed relation between [P], [c], and [Q] is true?
1) {{True}} X ::= 5 {{X = 5}}
2) {{X = 2}} X ::= X + 1 {{X = 3}}
3) {{True}} X ::= 5; Y ::= 0 {{X = 5}}
4) {{X = 2 /\ X = 3}} X ::= 5 {{X = 0}}
5) {{True}} SKIP {{False}}
6) {{False}} SKIP {{True}}
7) {{True}} WHILE True DO SKIP END {{False}}
8) {{X = 0}}
WHILE X == 0 DO X ::= X + 1 END
{{X = 1}}
9) {{X = 1}}
WHILE X <> 0 DO X ::= X + 1 END
{{X = 100}}
*)
(* FILL IN HERE *)
(** [] *)
(** (Note that we're using informal mathematical notations for
expressions inside of commands, for readability, rather than their
formal [aexp] and [bexp] encodings. We'll continue doing so
throughout the chapter.) *)
(** To get us warmed up for what's coming, here are two simple
facts about Hoare triples. *)
Theorem hoare_post_true : forall (P Q : Assertion) c,
(forall st, Q st) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
apply H. Qed.
Theorem hoare_pre_false : forall (P Q : Assertion) c,
(forall st, ~(P st)) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
unfold not in H. apply H in HP.
inversion HP. Qed.
(* ####################################################### *)
(** ** Proof Rules *)
(** The goal of Hoare logic is to provide a _compositional_
method for proving the validity of Hoare triples. That is, the
structure of a program's correctness proof should mirror the
structure of the program itself. To this end, in the sections
below, we'll introduce one rule for reasoning about each of the
different syntactic forms of commands in Imp -- one for
assignment, one for sequencing, one for conditionals, etc. -- plus
a couple of "structural" rules that are useful for gluing things
together. We will prove programs correct using these proof rules,
without ever unfolding the definition of [hoare_triple]. *)
(* ####################################################### *)
(** *** Assignment *)
(** The rule for assignment is the most fundamental of the Hoare logic
proof rules. Here's how it works.
Consider this (valid) Hoare triple:
{{ Y = 1 }} X ::= Y {{ X = 1 }}
In English: if we start out in a state where the value of [Y]
is [1] and we assign [Y] to [X], then we'll finish in a
state where [X] is [1]. That is, the property of being equal
to [1] gets transferred from [Y] to [X].
Similarly, in
{{ Y + Z = 1 }} X ::= Y + Z {{ X = 1 }}
the same property (being equal to one) gets transferred to
[X] from the expression [Y + Z] on the right-hand side of
the assignment.
More generally, if [a] is _any_ arithmetic expression, then
{{ a = 1 }} X ::= a {{ X = 1 }}
is a valid Hoare triple.
This can be made even more general. To conclude that an
_arbitrary_ property [Q] holds after [X ::= a], we need to assume
that [Q] holds before [X ::= a], but _with all occurrences of_ [X]
replaced by [a] in [Q]. This leads to the Hoare rule for
assignment
{{ Q [X |-> a] }} X ::= a {{ Q }}
where "[Q [X |-> a]]" is pronounced "[Q] where [a] is substituted
for [X]".
For example, these are valid applications of the assignment
rule:
{{ (X <= 5) [X |-> X + 1]
i.e., X + 1 <= 5 }}
X ::= X + 1
{{ X <= 5 }}
{{ (X = 3) [X |-> 3]
i.e., 3 = 3}}
X ::= 3
{{ X = 3 }}
{{ (0 <= X /\ X <= 5) [X |-> 3]
i.e., (0 <= 3 /\ 3 <= 5)}}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
*)
(** To formalize the rule, we must first formalize the idea of
"substituting an expression for an Imp variable in an assertion."
That is, given a proposition [P], a variable [X], and an
arithmetic expression [a], we want to derive another proposition
[P'] that is just the same as [P] except that, wherever [P]
mentions [X], [P'] should instead mention [a].
Since [P] is an arbitrary Coq proposition, we can't directly
"edit" its text. Instead, we can achieve the effect we want by
evaluating [P] in an updated state: *)
Definition assn_sub X a P : Assertion :=
fun (st : state) =>
P (update st X (aeval st a)).
Notation "P [ X |-> a ]" := (assn_sub X a P) (at level 10).
(** That is, [P [X |-> a]] is an assertion [P'] that is just like [P]
except that, wherever [P] looks up the variable [X] in the current
state, [P'] instead uses the value of the expression [a].
To see how this works, let's calculate what happens with a couple
of examples. First, suppose [P'] is [(X <= 5) [X |-> 3]] -- that
is, more formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(update st X (aeval st (ANum 3))),
which simplifies to
fun st =>
(fun st' => st' X <= 5)
(update st X 3)
and further simplifies to
fun st =>
((update st X 3) X) <= 5)
and by further simplification to
fun st =>
(3 <= 5).
That is, [P'] is the assertion that [3] is less than or equal to
[5] (as expected).
For a more interesting example, suppose [P'] is [(X <= 5) [X |->
X+1]]. Formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(update st X (aeval st (APlus (AId X) (ANum 1)))),
which simplifies to
fun st =>
(((update st X (aeval st (APlus (AId X) (ANum 1))))) X) <= 5
and further simplifies to
fun st =>
(aeval st (APlus (AId X) (ANum 1))) <= 5.
That is, [P'] is the assertion that [X+1] is at most [5].
*)
(** Now we can give the precise proof rule for assignment:
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X ::= a {{Q}}
*)
(** We can prove formally that this rule is indeed valid. *)
Theorem hoare_asgn : forall Q X a,
{{Q [X |-> a]}} (X ::= a) {{Q}}.
Proof.
unfold hoare_triple.
intros Q X a st st' HE HQ.
inversion HE. subst.
unfold assn_sub in HQ. assumption. Qed.
(** Here's a first formal proof using this rule. *)
Example assn_sub_example :
{{(fun st => st X = 3) [X |-> ANum 3]}}
(X ::= (ANum 3))
{{fun st => st X = 3}}.
Proof.
apply hoare_asgn. Qed.
(** **** Exercise: 2 stars (hoare_asgn_examples) *)
(** Translate these informal Hoare triples...
1) {{ (X <= 5) [X |-> X + 1] }}
X ::= X + 1
{{ X <= 5 }}
2) {{ (0 <= X /\ X <= 5) [X |-> 3] }}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
...into formal statements [assn_sub_ex1, assn_sub_ex2]
and use [hoare_asgn] to prove them. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars (hoare_asgn_wrong) *)
(** The assignment rule looks backward to almost everyone the first
time they see it. If it still seems backward to you, it may help
to think a little about alternative "forward" rules. Here is a
seemingly natural one:
------------------------------ (hoare_asgn_wrong)
{{ True }} X ::= a {{ X = a }}
Give a counterexample showing that this rule is incorrect
(informally). Hint: The rule universally quantifies over the
arithmetic expression [a], and your counterexample needs to
exhibit an [a] for which the rule doesn't work. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, advanced (hoare_asgn_fwd) *)
(** However, using an auxiliary variable [m] to remember the original
value of [X] we can define a Hoare rule for assignment that does,
intuitively, "work forwards" rather than backwards.
------------------------------------------ (hoare_asgn_fwd)
{{fun st => P st /\ st X = m}}
X ::= a
{{fun st => P st' /\ st X = aeval st' a }}
(where st' = update st X m)
Note that we use the original value of [X] to reconstruct the
state [st'] before the assignment took place. Prove that this rule
is correct (the first hypothesis is the functional extensionality
axiom, which you will need at some point). Also note that this
rule is more complicated than [hoare_asgn].
*)
Theorem hoare_asgn_fwd :
(forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g) ->
forall m a P,
{{fun st => P st /\ st X = m}}
X ::= a
{{fun st => P (update st X m) /\ st X = aeval (update st X m) a }}.
Proof.
intros functional_extensionality m a P.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced (hoare_asgn_fwd_exists) *)
(** Another way to define a forward rule for assignment is to
existentially quantify over the previous value of the assigned
variable.
------------------------------------------ (hoare_asgn_fwd_exists)
{{fun st => P st}}
X ::= a
{{fun st => exists m, P (update st X m) /\
st X = aeval (update st X m) a }}
*)
(* This rule was proposed by Nick Giannarakis and Zoe Paraskevopoulou. *)
Theorem hoare_asgn_fwd_exists :
(forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g) ->
forall a P,
{{fun st => P st}}
X ::= a
{{fun st => exists m, P (update st X m) /\
st X = aeval (update st X m) a }}.
Proof.
intros functional_extensionality a P.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** *** Consequence *)
(** Sometimes the preconditions and postconditions we get from the
Hoare rules won't quite be the ones we want in the particular
situation at hand -- they may be logically equivalent but have a
different syntactic form that fails to unify with the goal we are
trying to prove, or they actually may be logically weaker (for
preconditions) or stronger (for postconditions) than what we need.
For instance, while
{{(X = 3) [X |-> 3]}} X ::= 3 {{X = 3}},
follows directly from the assignment rule,
{{True}} X ::= 3 {{X = 3}}.
does not. This triple is valid, but it is not an instance of
[hoare_asgn] because [True] and [(X = 3) [X |-> 3]] are not
syntactically equal assertions. However, they are logically
equivalent, so if one triple is valid, then the other must
certainly be as well. We might capture this observation with the
following rule:
{{P'}} c {{Q}}
P <<->> P'
----------------------------- (hoare_consequence_pre_equiv)
{{P}} c {{Q}}
Taking this line of thought a bit further, we can see that
strengthening the precondition or weakening the postcondition of a
valid triple always produces another valid triple. This
observation is captured by two _Rules of Consequence_.
{{P'}} c {{Q}}
P ->> P'
----------------------------- (hoare_consequence_pre)
{{P}} c {{Q}}
{{P}} c {{Q'}}
Q' ->> Q
----------------------------- (hoare_consequence_post)
{{P}} c {{Q}}
*)
(** Here are the formal versions: *)
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Proof.
intros P P' Q c Hhoare Himp.
intros st st' Hc HP. apply (Hhoare st st').
assumption. apply Himp. assumption. Qed.
Theorem hoare_consequence_post : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P Q Q' c Hhoare Himp.
intros st st' Hc HP.
apply Himp.
apply (Hhoare st st').
assumption. assumption. Qed.
(** For example, we might use the first consequence rule like this:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1
{{ X = 1 }}
Or, formally...
*)
Example hoare_asgn_example1 :
{{fun st => True}} (X ::= (ANum 1)) {{fun st => st X = 1}}.
Proof.
apply hoare_consequence_pre
with (P' := (fun st => st X = 1) [X |-> ANum 1]).
apply hoare_asgn.
intros st H. unfold assn_sub, update. simpl. reflexivity.
Qed.
(** Finally, for convenience in some proofs, we can state a "combined"
rule of consequence that allows us to vary both the precondition
and the postcondition.
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
*)
Theorem hoare_consequence : forall (P P' Q Q' : Assertion) c,
{{P'}} c {{Q'}} ->
P ->> P' ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P P' Q Q' c Hht HPP' HQ'Q.
apply hoare_consequence_pre with (P' := P').
apply hoare_consequence_post with (Q' := Q').
assumption. assumption. assumption. Qed.
(* ####################################################### *)
(** *** Digression: The [eapply] Tactic *)
(** This is a good moment to introduce another convenient feature of
Coq. We had to write "[with (P' := ...)]" explicitly in the proof
of [hoare_asgn_example1] and [hoare_consequence] above, to make
sure that all of the metavariables in the premises to the
[hoare_consequence_pre] rule would be set to specific
values. (Since [P'] doesn't appear in the conclusion of
[hoare_consequence_pre], the process of unifying the conclusion
with the current goal doesn't constrain [P'] to a specific
assertion.)
This is a little annoying, both because the assertion is a bit
long and also because for [hoare_asgn_example1] the very next
thing we are going to do -- applying the [hoare_asgn] rule -- will
tell us exactly what it should be! We can use [eapply] instead of
[apply] to tell Coq, essentially, "Be patient: The missing part is
going to be filled in soon." *)
Example hoare_asgn_example1' :
{{fun st => True}}
(X ::= (ANum 1))
{{fun st => st X = 1}}.
Proof.
eapply hoare_consequence_pre.
apply hoare_asgn.
intros st H. reflexivity. Qed.
(** In general, [eapply H] tactic works just like [apply H] except
that, instead of failing if unifying the goal with the conclusion
of [H] does not determine how to instantiate all of the variables
appearing in the premises of [H], [eapply H] will replace these
variables with so-called _existential variables_ (written [?nnn])
as placeholders for expressions that will be determined (by
further unification) later in the proof. *)
(** In order for [Qed] to succeed, all existential variables need to
be determined by the end of the proof. Otherwise Coq
will (rightly) refuse to accept the proof. Remember that the Coq
tactics build proof objects, and proof objects containing
existential variables are not complete. *)
Lemma silly1 : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(forall x y : nat, P x y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. apply HP.
(** Coq gives a warning after [apply HP]:
No more subgoals but non-instantiated existential variables:
Existential 1 =
?171 : [P : nat -> nat -> Prop
Q : nat -> Prop
HP : forall x y : nat, P x y
HQ : forall x y : nat, P x y -> Q x |- nat]
(dependent evars: ?171 open,)
You can use Grab Existential Variables.
Trying to finish the proof with [Qed] gives an error:
<<
Error: Attempt to save a proof with existential variables still
non-instantiated
>> *)
Abort.
(** An additional constraint is that existential variables cannot be
instantiated with terms containing (ordinary) variables that did
not exist at the time the existential variable was created. *)
Lemma silly2 :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. destruct HP as [y HP'].
(** Doing [apply HP'] above fails with the following error:
Error: Impossible to unify "?175" with "y".
In this case there is an easy fix:
doing [destruct HP] _before_ doing [eapply HQ].
*)
Abort.
Lemma silly2_fixed :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP'].
eapply HQ. apply HP'.
Qed.
(** In the last step we did [apply HP'] which unifies the existential
variable in the goal with the variable [y]. The [assumption]
tactic doesn't work in this case, since it cannot handle
existential variables. However, Coq also provides an [eassumption]
tactic that solves the goal if one of the premises matches the
goal up to instantiations of existential variables. We can use
it instead of [apply HP']. *)
Lemma silly2_eassumption : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP']. eapply HQ. eassumption.
Qed.
(** **** Exercise: 2 stars (hoare_asgn_examples_2) *)
(** Translate these informal Hoare triples...
{{ X + 1 <= 5 }} X ::= X + 1 {{ X <= 5 }}
{{ 0 <= 3 /\ 3 <= 5 }} X ::= 3 {{ 0 <= X /\ X <= 5 }}
...into formal statements [assn_sub_ex1', assn_sub_ex2'] and
use [hoare_asgn] and [hoare_consequence_pre] to prove them. *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** *** Skip *)
(** Since [SKIP] doesn't change the state, it preserves any
property P:
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
*)
Theorem hoare_skip : forall P,
{{P}} SKIP {{P}}.
Proof.
intros P st st' H HP. inversion H. subst.
assumption. Qed.
(* ####################################################### *)
(** *** Sequencing *)
(** More interestingly, if the command [c1] takes any state where
[P] holds to a state where [Q] holds, and if [c2] takes any
state where [Q] holds to one where [R] holds, then doing [c1]
followed by [c2] will take any state where [P] holds to one
where [R] holds:
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
*)
Theorem hoare_seq : forall P Q R c1 c2,
{{Q}} c2 {{R}} ->
{{P}} c1 {{Q}} ->
{{P}} c1;;c2 {{R}}.
Proof.
intros P Q R c1 c2 H1 H2 st st' H12 Pre.
inversion H12; subst.
apply (H1 st'0 st'); try assumption.
apply (H2 st st'0); assumption. Qed.
(** Note that, in the formal rule [hoare_seq], the premises are
given in "backwards" order ([c2] before [c1]). This matches the
natural flow of information in many of the situations where we'll
use the rule: the natural way to construct a Hoare-logic proof is
to begin at the end of the program (with the final postcondition)
and push postconditions backwards through commands until we reach
the beginning. *)
(** Informally, a nice way of recording a proof using the sequencing
rule is as a "decorated program" where the intermediate assertion
[Q] is written between [c1] and [c2]:
{{ a = n }}
X ::= a;;
{{ X = n }} <---- decoration for Q
SKIP
{{ X = n }}
*)
Example hoare_asgn_example3 : forall a n,
{{fun st => aeval st a = n}}
(X ::= a;; SKIP)
{{fun st => st X = n}}.
Proof.
intros a n. eapply hoare_seq.
Case "right part of seq".
apply hoare_skip.
Case "left part of seq".
eapply hoare_consequence_pre. apply hoare_asgn.
intros st H. subst. reflexivity. Qed.
(** You will most often use [hoare_seq] and
[hoare_consequence_pre] in conjunction with the [eapply] tactic,
as done above. *)
(** **** Exercise: 2 stars (hoare_asgn_example4) *)
(** Translate this "decorated program" into a formal proof:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1;;
{{ X = 1 }} ->>
{{ X = 1 /\ 2 = 2 }}
Y ::= 2
{{ X = 1 /\ Y = 2 }}
*)
Example hoare_asgn_example4 :
{{fun st => True}} (X ::= (ANum 1);; Y ::= (ANum 2))
{{fun st => st X = 1 /\ st Y = 2}}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (swap_exercise) *)
(** Write an Imp program [c] that swaps the values of [X] and [Y]
and show (in Coq) that it satisfies the following
specification:
{{X <= Y}} c {{Y <= X}}
*)
Definition swap_program : com :=
(* FILL IN HERE *) admit.
Theorem swap_exercise :
{{fun st => st X <= st Y}}
swap_program
{{fun st => st Y <= st X}}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (hoarestate1) *)
(** Explain why the following proposition can't be proven:
forall (a : aexp) (n : nat),
{{fun st => aeval st a = n}}
(X ::= (ANum 3);; Y ::= a)
{{fun st => st Y = n}}.
*)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** *** Conditionals *)
(** What sort of rule do we want for reasoning about conditional
commands? Certainly, if the same assertion [Q] holds after
executing either branch, then it holds after the whole
conditional. So we might be tempted to write:
{{P}} c1 {{Q}}
{{P}} c2 {{Q}}
--------------------------------
{{P}} IFB b THEN c1 ELSE c2 {{Q}}
However, this is rather weak. For example, using this rule,
we cannot show that:
{{ True }}
IFB X == 0
THEN Y ::= 2
ELSE Y ::= X + 1
FI
{{ X <= Y }}
since the rule tells us nothing about the state in which the
assignments take place in the "then" and "else" branches. *)
(** But we can actually say something more precise. In the
"then" branch, we know that the boolean expression [b] evaluates to
[true], and in the "else" branch, we know it evaluates to [false].
Making this information available in the premises of the rule gives
us more information to work with when reasoning about the behavior
of [c1] and [c2] (i.e., the reasons why they establish the
postcondition [Q]). *)
(**
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
*)
(** To interpret this rule formally, we need to do a little work.
Strictly speaking, the assertion we've written, [P /\ b], is the
conjunction of an assertion and a boolean expression -- i.e., it
doesn't typecheck. To fix this, we need a way of formally
"lifting" any bexp [b] to an assertion. We'll write [bassn b] for
the assertion "the boolean expression [b] evaluates to [true] (in
the given state)." *)
Definition bassn b : Assertion :=
fun st => (beval st b = true).
(** A couple of useful facts about [bassn]: *)
Lemma bexp_eval_true : forall b st,
beval st b = true -> (bassn b) st.
Proof.
intros b st Hbe.
unfold bassn. assumption. Qed.
Lemma bexp_eval_false : forall b st,
beval st b = false -> ~ ((bassn b) st).
Proof.
intros b st Hbe contra.
unfold bassn in contra.
rewrite -> contra in Hbe. inversion Hbe. Qed.
(** Now we can formalize the Hoare proof rule for conditionals
and prove it correct. *)
Theorem hoare_if : forall P Q b c1 c2,
{{fun st => P st /\ bassn b st}} c1 {{Q}} ->
{{fun st => P st /\ ~(bassn b st)}} c2 {{Q}} ->
{{P}} (IFB b THEN c1 ELSE c2 FI) {{Q}}.
Proof.
intros P Q b c1 c2 HTrue HFalse st st' HE HP.
inversion HE; subst.
Case "b is true".
apply (HTrue st st').
assumption.
split. assumption.
apply bexp_eval_true. assumption.
Case "b is false".
apply (HFalse st st').
assumption.
split. assumption.
apply bexp_eval_false. assumption. Qed.
(* ####################################################### *)
(** * Hoare Logic: So Far *)
(**
Idea: create a _domain specific logic_ for reasoning about properties of Imp programs.
- This hides the low-level details of the semantics of the program
- Leads to a compositional reasoning process
The basic structure is given by _Hoare triples_ of the form:
{{P}} c {{Q}}
]]
- [P] and [Q] are predicates about the state of the Imp program
- "If command [c] is started in a state satisfying assertion
[P], and if [c] eventually terminates in some final state,
then this final state will satisfy the assertion [Q]."
*)
(** ** Hoare Logic Rules (so far) *)
(**
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X::=a {{Q}}
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
*)
(** *** Example *)
(** Here is a formal proof that the program we used to motivate the
rule satisfies the specification we gave. *)
Example if_example :
{{fun st => True}}
IFB (BEq (AId X) (ANum 0))
THEN (Y ::= (ANum 2))
ELSE (Y ::= APlus (AId X) (ANum 1))
FI
{{fun st => st X <= st Y}}.
Proof.
(* WORKED IN CLASS *)
apply hoare_if.
Case "Then".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub, update, assert_implies.
simpl. intros st [_ H].
apply beq_nat_true in H.
rewrite H. omega.
Case "Else".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold assn_sub, update, assert_implies.
simpl; intros st _. omega.
Qed.
(** **** Exercise: 2 stars (if_minus_plus) *)
(** Prove the following hoare triple using [hoare_if]: *)
Theorem if_minus_plus :
{{fun st => True}}
IFB (BLe (AId X) (AId Y))
THEN (Z ::= AMinus (AId Y) (AId X))
ELSE (Y ::= APlus (AId X) (AId Z))
FI
{{fun st => st Y = st X + st Z}}.
Proof.
(* FILL IN HERE *) Admitted.
(* ####################################################### *)
(** *** Exercise: One-sided conditionals *)
(** **** Exercise: 4 stars (if1_hoare) *)
(** In this exercise we consider extending Imp with "one-sided
conditionals" of the form [IF1 b THEN c FI]. Here [b] is a
boolean expression, and [c] is a command. If [b] evaluates to
[true], then command [c] is evaluated. If [b] evaluates to
[false], then [IF1 b THEN c FI] does nothing.
We recommend that you do this exercise before the ones that
follow, as it should help solidify your understanding of the
material. *)
(** The first step is to extend the syntax of commands and introduce
the usual notations. (We've done this for you. We use a separate
module to prevent polluting the global name space.) *)
Module If1.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CIf1 : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "CIF1" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'IF1' b 'THEN' c 'FI'" :=
(CIf1 b c) (at level 80, right associativity).
(** Next we need to extend the evaluation relation to accommodate
[IF1] branches. This is for you to do... What rule(s) need to be
added to [ceval] to evaluate one-sided conditionals? *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
(* FILL IN HERE *)
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
(* FILL IN HERE *)
].
(** Now we repeat (verbatim) the definition and notation of Hoare triples. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Finally, we (i.e., you) need to state and prove a theorem,
[hoare_if1], that expresses an appropriate Hoare logic proof rule
for one-sided conditionals. Try to come up with a rule that is
both sound and as precise as possible. *)
(* FILL IN HERE *)
(** For full credit, prove formally [hoare_if1_good] that your rule is
precise enough to show the following valid Hoare triple:
{{ X + Y = Z }}
IF1 Y <> 0 THEN
X ::= X + Y
FI
{{ X = Z }}
*)
(** Hint: Your proof of this triple may need to use the other proof
rules also. Because we're working in a separate module, you'll
need to copy here the rules you find necessary. *)
Lemma hoare_if1_good :
{{ fun st => st X + st Y = st Z }}
IF1 BNot (BEq (AId Y) (ANum 0)) THEN
X ::= APlus (AId X) (AId Y)
FI
{{ fun st => st X = st Z }}.
Proof. (* FILL IN HERE *) Admitted.
End If1.
(** [] *)
(* ####################################################### *)
(** *** Loops *)
(** Finally, we need a rule for reasoning about while loops. *)
(** Suppose we have a loop
WHILE b DO c END
and we want to find a pre-condition [P] and a post-condition
[Q] such that
{{P}} WHILE b DO c END {{Q}}
is a valid triple. *)
(** *** *)
(** First of all, let's think about the case where [b] is false at the
beginning -- i.e., let's assume that the loop body never executes
at all. In this case, the loop behaves like [SKIP], so we might
be tempted to write: *)
(**
{{P}} WHILE b DO c END {{P}}.
*)
(**
But, as we remarked above for the conditional, we know a
little more at the end -- not just [P], but also the fact
that [b] is false in the current state. So we can enrich the
postcondition a little:
*)
(**
{{P}} WHILE b DO c END {{P /\ ~b}}
*)
(**
What about the case where the loop body _does_ get executed?
In order to ensure that [P] holds when the loop finally
exits, we certainly need to make sure that the command [c]
guarantees that [P] holds whenever [c] is finished.
Moreover, since [P] holds at the beginning of the first
execution of [c], and since each execution of [c]
re-establishes [P] when it finishes, we can always assume
that [P] holds at the beginning of [c]. This leads us to the
following rule:
*)
(**
{{P}} c {{P}}
-----------------------------------
{{P}} WHILE b DO c END {{P /\ ~b}}
*)
(**
This is almost the rule we want, but again it can be improved a
little: at the beginning of the loop body, we know not only that
[P] holds, but also that the guard [b] is true in the current
state. This gives us a little more information to use in
reasoning about [c] (showing that it establishes the invariant by
the time it finishes). This gives us the final version of the rule:
*)
(**
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
The proposition [P] is called an _invariant_ of the loop.
*)
Lemma hoare_while : forall P b c,
{{fun st => P st /\ bassn b st}} c {{P}} ->
{{P}} WHILE b DO c END {{fun st => P st /\ ~ (bassn b st)}}.
Proof.
intros P b c. intros Hhoare. intros st st' He HP.
(* Like we've seen before, we need to reason by induction
on [He], because, in the "keep looping" case, its hypotheses
talk about the whole loop instead of just [c]. *)
remember (WHILE b DO c END) as wcom eqn:Heqwcom.
ceval_cases (induction He) Case;
try (inversion Heqwcom); subst; clear Heqwcom.
Case "E_WhileEnd".
split. assumption. apply bexp_eval_false. assumption.
Case "E_WhileLoop".
apply IHHe2. reflexivity.
apply (Hhoare st st'). assumption.
split. assumption. apply bexp_eval_true. assumption.
Qed.
(**
One subtlety in the terminology is that calling some assertion [P]
a "loop invariant" doesn't just mean that it is preserved by the
body of the loop in question (i.e., [{{P}} c {{P}}], where [c] is
the loop body), but rather that [P] _together with the fact that
the loop's guard is true_ is a sufficient precondition for [c] to
ensure [P] as a postcondition.
This is a slightly (but significantly) weaker requirement. For
example, if [P] is the assertion [X = 0], then [P] _is_ an
invariant of the loop
WHILE X = 2 DO X := 1 END
although it is clearly _not_ preserved by the body of the
loop.
*)
Example while_example :
{{fun st => st X <= 3}}
WHILE (BLe (AId X) (ANum 2))
DO X ::= APlus (AId X) (ANum 1) END
{{fun st => st X = 3}}.
Proof.
eapply hoare_consequence_post.
apply hoare_while.
eapply hoare_consequence_pre.
apply hoare_asgn.
unfold bassn, assn_sub, assert_implies, update. simpl.
intros st [H1 H2]. apply ble_nat_true in H2. omega.
unfold bassn, assert_implies. intros st [Hle Hb].
simpl in Hb. destruct (ble_nat (st X) 2) eqn : Heqle.
apply ex_falso_quodlibet. apply Hb; reflexivity.
apply ble_nat_false in Heqle. omega.
Qed.
(** *** *)
(** We can use the while rule to prove the following Hoare triple,
which may seem surprising at first... *)
Theorem always_loop_hoare : forall P Q,
{{P}} WHILE BTrue DO SKIP END {{Q}}.
Proof.
(* WORKED IN CLASS *)
intros P Q.
apply hoare_consequence_pre with (P' := fun st : state => True).
eapply hoare_consequence_post.
apply hoare_while.
Case "Loop body preserves invariant".
apply hoare_post_true. intros st. apply I.
Case "Loop invariant and negated guard imply postcondition".
simpl. intros st [Hinv Hguard].
apply ex_falso_quodlibet. apply Hguard. reflexivity.
Case "Precondition implies invariant".
intros st H. constructor. Qed.
(** Of course, this result is not surprising if we remember that
the definition of [hoare_triple] asserts that the postcondition
must hold _only_ when the command terminates. If the command
doesn't terminate, we can prove anything we like about the
post-condition. *)
(** Hoare rules that only talk about terminating commands are
often said to describe a logic of "partial" correctness. It is
also possible to give Hoare rules for "total" correctness, which
build in the fact that the commands terminate. However, in this
course we will only talk about partial correctness. *)
(* ####################################################### *)
(** *** Exercise: [REPEAT] *)
Module RepeatExercise.
(** **** Exercise: 4 stars, advanced (hoare_repeat) *)
(** In this exercise, we'll add a new command to our language of
commands: [REPEAT] c [UNTIL] a [END]. You will write the
evaluation rule for [repeat] and add a new Hoare rule to
the language for programs involving it. *)
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CRepeat : com -> bexp -> com.
(** [REPEAT] behaves like [WHILE], except that the loop guard is
checked _after_ each execution of the body, with the loop
repeating as long as the guard stays _false_. Because of this,
the body will always execute at least once. *)
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE"
| Case_aux c "CRepeat" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'REPEAT' e1 'UNTIL' b2 'END'" :=
(CRepeat e1 b2) (at level 80, right associativity).
(** Add new rules for [REPEAT] to [ceval] below. You can use the rules
for [WHILE] as a guide, but remember that the body of a [REPEAT]
should always execute at least once, and that the loop ends when
the guard becomes true. Then update the [ceval_cases] tactic to
handle these added cases. *)
Inductive ceval : state -> com -> state -> Prop :=
| E_Skip : forall st,
ceval st SKIP st
| E_Ass : forall st a1 n X,
aeval st a1 = n ->
ceval st (X ::= a1) (update st X n)
| E_Seq : forall c1 c2 st st' st'',
ceval st c1 st' ->
ceval st' c2 st'' ->
ceval st (c1 ;; c2) st''
| E_IfTrue : forall st st' b1 c1 c2,
beval st b1 = true ->
ceval st c1 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_IfFalse : forall st st' b1 c1 c2,
beval st b1 = false ->
ceval st c2 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_WhileEnd : forall b1 st c1,
beval st b1 = false ->
ceval st (WHILE b1 DO c1 END) st
| E_WhileLoop : forall st st' st'' b1 c1,
beval st b1 = true ->
ceval st c1 st' ->
ceval st' (WHILE b1 DO c1 END) st'' ->
ceval st (WHILE b1 DO c1 END) st''
(* FILL IN HERE *)
.
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass"
| Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
(* FILL IN HERE *)
].
(** A couple of definitions from above, copied here so they use the
new [ceval]. *)
Notation "c1 '/' st '||' st'" := (ceval st c1 st')
(at level 40, st at level 39).
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion)
: Prop :=
forall st st', (c / st || st') -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level).
(** To make sure you've got the evaluation rules for [REPEAT] right,
prove that [ex1_repeat evaluates correctly. *)
Definition ex1_repeat :=
REPEAT
X ::= ANum 1;;
Y ::= APlus (AId Y) (ANum 1)
UNTIL (BEq (AId X) (ANum 1)) END.
Theorem ex1_repeat_works :
ex1_repeat / empty_state ||
update (update empty_state X 1) Y 1.
Proof.
(* FILL IN HERE *) Admitted.
(** Now state and prove a theorem, [hoare_repeat], that expresses an
appropriate proof rule for [repeat] commands. Use [hoare_while]
as a model, and try to make your rule as precise as possible. *)
(* FILL IN HERE *)
(** For full credit, make sure (informally) that your rule can be used
to prove the following valid Hoare triple:
{{ X > 0 }}
REPEAT
Y ::= X;;
X ::= X - 1
UNTIL X = 0 END
{{ X = 0 /\ Y > 0 }}
*)
End RepeatExercise.
(** [] *)
(* ####################################################### *)
(** ** Exercise: [HAVOC] *)
(** **** Exercise: 3 stars (himp_hoare) *)
(** In this exercise, we will derive proof rules for the [HAVOC] command
which we studied in the last chapter. First, we enclose this work
in a separate module, and recall the syntax and big-step semantics
of Himp commands. *)
Module Himp.
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CHavoc : id -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "HAVOC" ].
Notation "'SKIP'" :=
CSkip.
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'HAVOC' X" := (CHavoc X) (at level 60).
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
| E_Havoc : forall (st : state) (X : id) (n : nat),
(HAVOC X) / st || update st X n
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_Havoc" ].
(** The definition of Hoare triples is exactly as before. Unlike our
notion of program equivalence, which had subtle consequences with
occassionally nonterminating commands (exercise [havoc_diverge]),
this definition is still fully satisfactory. Convince yourself of
this before proceeding. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st', c / st || st' -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Complete the Hoare rule for [HAVOC] commands below by defining
[havoc_pre] and prove that the resulting rule is correct. *)
Definition havoc_pre (X : id) (Q : Assertion) : Assertion :=
(* FILL IN HERE *) admit.
Theorem hoare_havoc : forall (Q : Assertion) (X : id),
{{ havoc_pre X Q }} HAVOC X {{ Q }}.
Proof.
(* FILL IN HERE *) Admitted.
End Himp.
(** [] *)
(* ####################################################### *)
(** ** Complete List of Hoare Logic Rules *)
(** Above, we've introduced Hoare Logic as a tool to reasoning
about Imp programs. In the reminder of this chapter we will
explore a systematic way to use Hoare Logic to prove properties
about programs. The rules of Hoare Logic are the following: *)
(**
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X::=a {{Q}}
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
In the next chapter, we'll see how these rules are used to prove
that programs satisfy specifications of their behavior.
*)
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
reg a, b;
wire res;
has_ports test(res, a, b);
initial begin
a = 0;
b = 0;
#1 $display("has_ports (%b, %b, %b)", res, a, b);
if (res !== (a & b)) begin
$display("FAILED");
$finish;
end
a = 1;
#1 $display("has_ports (%b, %b, %b)", res, a, b);
if (res !== (a & b)) begin
$display("FAILED");
$finish;
end
b = 1;
#1 $display("has_ports (%b, %b, %b)", res, a, b);
if (res !== (a & b)) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
module has_ports (output reg o, input wire a, input wire b);
always @* o <= a & b;
endmodule // has_ports
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_64x22.v,v $
// Revision 1.9 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:41 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.7 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.6 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_spram_64x22(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 6;
parameter dw = 22;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire [9:0] unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire [9:0] unconnected;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_64x22 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_64x22_bist artisan_ssp(
`else
art_hssp_64x22 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_64x22 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_64x22_bist vs_ssp(
`else
vs_hdsp_64x22 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.ADDR({2'b00, addr}),
.DI(di[15:0]),
.EN(ce),
.WE(we),
.DO(doq[15:0])
);
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(rst),
.ADDR({2'b00, addr}),
.DI({10'b0000000000, di[21:16]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[21:16]})
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(rst),
.ADDR({3'b000, addr}),
.DI({10'b0000000000,di}),
.DIP(4'h0),
.EN(ce),
.WE(we),
.DO({unconnected, doq}),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
`timescale 1ns/10ps
module system_acl_iface_pll(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(1),
.output_clock_frequency0("100.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
//****************************************************************************************************
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : bus_addr_dec.v
//Project Name : azpr_soc
//Description : the bus arbiter.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl/bus_addr_dec.v
//License : CPL
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 01-07-2016 17:00(1th Fri,July,2016)
//First Author : lichangbeiju
//Modify Date : 02-09-2016 14:20(1th Sun,July,2016)
//Last Author : lichangbeiju
//Version Number : 002
//Last Commit : 03-09-2016 14:30(1th Sun,July,2016)
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.08 - lichangbeiju - Change the include.
//2016.11.21 - lichangbeiju - Add io port.
//****************************************************************************************************
`include "../sys_include.h"
`include "bus.h"
module bus_addr_dec(
input wire [`WordAddrBus] s_addr ,//30 address
output reg s0_cs_n ,//01 slave 0 chip select rom
output reg s1_cs_n ,//01 slave 1 chip select spm
output reg s2_cs_n ,//01 slave 2 chip select timer
output reg s3_cs_n ,//01 slave 3 chip select uart
output reg s4_cs_n ,//01 slave 4 chip select gpio
output reg s5_cs_n ,//01 slave 5 chip select nc
output reg s6_cs_n ,//01 slave 6 chip select nc
output reg s7_cs_n //01 slave 7 chip select nc
);
//************************************************************************************************
// 1.Parameter and constant define
//************************************************************************************************
// `define UDP
// `define CLK_TEST_EN
//************************************************************************************************
// 2.Register and wire declaration
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 2.1 the output reg
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 2.x the test logic
//------------------------------------------------------------------------------------------------
wire [02:00] s_index ;//the bus slave index
//************************************************************************************************
// 3.Main code
//************************************************************************************************
assign s_index = s_addr[`BusSlaveIndexLoc];
//------------------------------------------------------------------------------------------------
// 3.1 the master grant logic
//------------------------------------------------------------------------------------------------
always @(*) begin : BUS_SLAVE_INDEX
s0_cs_n = `DISABLE_N;
s1_cs_n = `DISABLE_N;
s2_cs_n = `DISABLE_N;
s3_cs_n = `DISABLE_N;
s4_cs_n = `DISABLE_N;
s5_cs_n = `DISABLE_N;
s6_cs_n = `DISABLE_N;
s7_cs_n = `DISABLE_N;
case(s_index)
`BUS_SLAVE_0 : begin
s0_cs_n = `ENABLE_N;
end
`BUS_SLAVE_1 : begin
s1_cs_n = `ENABLE_N;
end
`BUS_SLAVE_2 : begin
s2_cs_n = `ENABLE_N;
end
`BUS_SLAVE_3 : begin
s3_cs_n = `ENABLE_N;
end
`BUS_SLAVE_4 : begin
s4_cs_n = `ENABLE_N;
end
`BUS_SLAVE_5 : begin
s5_cs_n = `ENABLE_N;
end
`BUS_SLAVE_6 : begin
s6_cs_n = `ENABLE_N;
end
`BUS_SLAVE_7 : begin
s7_cs_n = `ENABLE_N;
end
endcase
end
//------------------------------------------------------------------------------------------------
// 3.2 the master owner control logic
//------------------------------------------------------------------------------------------------
//************************************************************************************************
// 4.Sub module instantiation
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 4.1 the clk generate module
//------------------------------------------------------------------------------------------------
endmodule
//****************************************************************************************************
//End of Module
//****************************************************************************************************
|
/*
*******************************************************************************
*
* FIFO Generator - Verilog Behavioral Model
*
*******************************************************************************
*
* (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information
* of Xilinx, Inc. and is protected under U.S. and
* international copyright and other intellectual property
* laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any
* rights to the materials distributed herewith. Except as
* otherwise provided in a valid license issued to you by
* Xilinx, and to the maximum extent permitted by applicable
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
* (2) Xilinx shall not be liable (whether in contract or tort,
* including negligence, or under any other theory of
* liability) for any loss or damage of any kind or nature
* related to, arising under or in connection with these
* materials, including for any direct, or any indirect,
* special, incidental, or consequential loss or damage
* (including loss of data, profits, goodwill, or any type of
* loss or damage suffered as a result of any action brought
* by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the
* possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-
* safe, or for use in any application requiring fail-safe
* performance, such as life-support or safety devices or
* systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any
* other applications that could lead to death, personal
* injury, or severe property or environmental damage
* (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and
* liability of any use of Xilinx products in Critical
* Applications, subject only to applicable laws and
* regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
* PART OF THIS FILE AT ALL TIMES.
*
*******************************************************************************
*******************************************************************************
*
* Filename: fifo_generator_vlog_beh.v
*
* Author : Xilinx
*
*******************************************************************************
* Structure:
*
* fifo_generator_vlog_beh.v
* |
* +-fifo_generator_v13_1_3_bhv_ver_as
* |
* +-fifo_generator_v13_1_3_bhv_ver_ss
* |
* +-fifo_generator_v13_1_3_bhv_ver_preload0
*
*******************************************************************************
* Description:
*
* The Verilog behavioral model for the FIFO Generator.
*
* The behavioral model has three parts:
* - The behavioral model for independent clocks FIFOs (_as)
* - The behavioral model for common clock FIFOs (_ss)
* - The "preload logic" block which implements First-word Fall-through
*
*******************************************************************************
* Description:
* The verilog behavioral model for the FIFO generator core.
*
*******************************************************************************
*/
`timescale 1ps/1ps
`ifndef TCQ
`define TCQ 100
`endif
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "",
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 1,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "4kx4",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_PIPELINE_REG = 0,
parameter C_POWER_SAVING_MODE = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3
parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3
parameter C_HAS_AXI_WR_CHANNEL = 0,
parameter C_HAS_AXI_RD_CHANNEL = 0,
parameter C_HAS_SLAVE_CE = 0,
parameter C_HAS_MASTER_CE = 0,
parameter C_ADD_NGC_CONSTRAINT = 0,
parameter C_USE_COMMON_UNDERFLOW = 0,
parameter C_USE_COMMON_OVERFLOW = 0,
parameter C_USE_DEFAULT_SETTINGS = 0,
// AXI Full/Lite
parameter C_AXI_ID_WIDTH = 0,
parameter C_AXI_ADDR_WIDTH = 0,
parameter C_AXI_DATA_WIDTH = 0,
parameter C_AXI_LEN_WIDTH = 8,
parameter C_AXI_LOCK_WIDTH = 2,
parameter C_HAS_AXI_ID = 0,
parameter C_HAS_AXI_AWUSER = 0,
parameter C_HAS_AXI_WUSER = 0,
parameter C_HAS_AXI_BUSER = 0,
parameter C_HAS_AXI_ARUSER = 0,
parameter C_HAS_AXI_RUSER = 0,
parameter C_AXI_ARUSER_WIDTH = 0,
parameter C_AXI_AWUSER_WIDTH = 0,
parameter C_AXI_WUSER_WIDTH = 0,
parameter C_AXI_BUSER_WIDTH = 0,
parameter C_AXI_RUSER_WIDTH = 0,
// AXI Streaming
parameter C_HAS_AXIS_TDATA = 0,
parameter C_HAS_AXIS_TID = 0,
parameter C_HAS_AXIS_TDEST = 0,
parameter C_HAS_AXIS_TUSER = 0,
parameter C_HAS_AXIS_TREADY = 0,
parameter C_HAS_AXIS_TLAST = 0,
parameter C_HAS_AXIS_TSTRB = 0,
parameter C_HAS_AXIS_TKEEP = 0,
parameter C_AXIS_TDATA_WIDTH = 1,
parameter C_AXIS_TID_WIDTH = 1,
parameter C_AXIS_TDEST_WIDTH = 1,
parameter C_AXIS_TUSER_WIDTH = 1,
parameter C_AXIS_TSTRB_WIDTH = 1,
parameter C_AXIS_TKEEP_WIDTH = 1,
// AXI Channel Type
// WACH --> Write Address Channel
// WDCH --> Write Data Channel
// WRCH --> Write Response Channel
// RACH --> Read Address Channel
// RDCH --> Read Data Channel
// AXIS --> AXI Streaming
parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic
parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
// AXI Implementation Type
// 1 = Common Clock Block RAM FIFO
// 2 = Common Clock Distributed RAM FIFO
// 11 = Independent Clock Block RAM FIFO
// 12 = Independent Clock Distributed RAM FIFO
parameter C_IMPLEMENTATION_TYPE_WACH = 0,
parameter C_IMPLEMENTATION_TYPE_WDCH = 0,
parameter C_IMPLEMENTATION_TYPE_WRCH = 0,
parameter C_IMPLEMENTATION_TYPE_RACH = 0,
parameter C_IMPLEMENTATION_TYPE_RDCH = 0,
parameter C_IMPLEMENTATION_TYPE_AXIS = 0,
// AXI FIFO Type
// 0 = Data FIFO
// 1 = Packet FIFO
// 2 = Low Latency Sync FIFO
// 3 = Low Latency Async FIFO
parameter C_APPLICATION_TYPE_WACH = 0,
parameter C_APPLICATION_TYPE_WDCH = 0,
parameter C_APPLICATION_TYPE_WRCH = 0,
parameter C_APPLICATION_TYPE_RACH = 0,
parameter C_APPLICATION_TYPE_RDCH = 0,
parameter C_APPLICATION_TYPE_AXIS = 0,
// AXI Built-in FIFO Primitive Type
// 512x36, 1kx18, 2kx9, 4kx4, etc
parameter C_PRIM_FIFO_TYPE_WACH = "512x36",
parameter C_PRIM_FIFO_TYPE_WDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_WRCH = "512x36",
parameter C_PRIM_FIFO_TYPE_RACH = "512x36",
parameter C_PRIM_FIFO_TYPE_RDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_AXIS = "512x36",
// Enable ECC
// 0 = ECC disabled
// 1 = ECC enabled
parameter C_USE_ECC_WACH = 0,
parameter C_USE_ECC_WDCH = 0,
parameter C_USE_ECC_WRCH = 0,
parameter C_USE_ECC_RACH = 0,
parameter C_USE_ECC_RDCH = 0,
parameter C_USE_ECC_AXIS = 0,
// ECC Error Injection Type
// 0 = No Error Injection
// 1 = Single Bit Error Injection
// 2 = Double Bit Error Injection
// 3 = Single Bit and Double Bit Error Injection
parameter C_ERROR_INJECTION_TYPE_WACH = 0,
parameter C_ERROR_INJECTION_TYPE_WDCH = 0,
parameter C_ERROR_INJECTION_TYPE_WRCH = 0,
parameter C_ERROR_INJECTION_TYPE_RACH = 0,
parameter C_ERROR_INJECTION_TYPE_RDCH = 0,
parameter C_ERROR_INJECTION_TYPE_AXIS = 0,
// Input Data Width
// Accumulation of all AXI input signal's width
parameter C_DIN_WIDTH_WACH = 1,
parameter C_DIN_WIDTH_WDCH = 1,
parameter C_DIN_WIDTH_WRCH = 1,
parameter C_DIN_WIDTH_RACH = 1,
parameter C_DIN_WIDTH_RDCH = 1,
parameter C_DIN_WIDTH_AXIS = 1,
parameter C_WR_DEPTH_WACH = 16,
parameter C_WR_DEPTH_WDCH = 16,
parameter C_WR_DEPTH_WRCH = 16,
parameter C_WR_DEPTH_RACH = 16,
parameter C_WR_DEPTH_RDCH = 16,
parameter C_WR_DEPTH_AXIS = 16,
parameter C_WR_PNTR_WIDTH_WACH = 4,
parameter C_WR_PNTR_WIDTH_WDCH = 4,
parameter C_WR_PNTR_WIDTH_WRCH = 4,
parameter C_WR_PNTR_WIDTH_RACH = 4,
parameter C_WR_PNTR_WIDTH_RDCH = 4,
parameter C_WR_PNTR_WIDTH_AXIS = 4,
parameter C_HAS_DATA_COUNTS_WACH = 0,
parameter C_HAS_DATA_COUNTS_WDCH = 0,
parameter C_HAS_DATA_COUNTS_WRCH = 0,
parameter C_HAS_DATA_COUNTS_RACH = 0,
parameter C_HAS_DATA_COUNTS_RDCH = 0,
parameter C_HAS_DATA_COUNTS_AXIS = 0,
parameter C_HAS_PROG_FLAGS_WACH = 0,
parameter C_HAS_PROG_FLAGS_WDCH = 0,
parameter C_HAS_PROG_FLAGS_WRCH = 0,
parameter C_HAS_PROG_FLAGS_RACH = 0,
parameter C_HAS_PROG_FLAGS_RDCH = 0,
parameter C_HAS_PROG_FLAGS_AXIS = 0,
parameter C_PROG_FULL_TYPE_WACH = 0,
parameter C_PROG_FULL_TYPE_WDCH = 0,
parameter C_PROG_FULL_TYPE_WRCH = 0,
parameter C_PROG_FULL_TYPE_RACH = 0,
parameter C_PROG_FULL_TYPE_RDCH = 0,
parameter C_PROG_FULL_TYPE_AXIS = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_PROG_EMPTY_TYPE_WACH = 0,
parameter C_PROG_EMPTY_TYPE_WDCH = 0,
parameter C_PROG_EMPTY_TYPE_WRCH = 0,
parameter C_PROG_EMPTY_TYPE_RACH = 0,
parameter C_PROG_EMPTY_TYPE_RDCH = 0,
parameter C_PROG_EMPTY_TYPE_AXIS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_REG_SLICE_MODE_WACH = 0,
parameter C_REG_SLICE_MODE_WDCH = 0,
parameter C_REG_SLICE_MODE_WRCH = 0,
parameter C_REG_SLICE_MODE_RACH = 0,
parameter C_REG_SLICE_MODE_RDCH = 0,
parameter C_REG_SLICE_MODE_AXIS = 0
)
(
//------------------------------------------------------------------------------
// Input and Output Declarations
//------------------------------------------------------------------------------
// Conventional FIFO Interface Signals
input backup,
input backup_marker,
input clk,
input rst,
input srst,
input wr_clk,
input wr_rst,
input rd_clk,
input rd_rst,
input [C_DIN_WIDTH-1:0] din,
input wr_en,
input rd_en,
// Optional inputs
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate,
input int_clk,
input injectdbiterr,
input injectsbiterr,
input sleep,
output [C_DOUT_WIDTH-1:0] dout,
output full,
output almost_full,
output wr_ack,
output overflow,
output empty,
output almost_empty,
output valid,
output underflow,
output [C_DATA_COUNT_WIDTH-1:0] data_count,
output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count,
output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count,
output prog_full,
output prog_empty,
output sbiterr,
output dbiterr,
output wr_rst_busy,
output rd_rst_busy,
// AXI Global Signal
input m_aclk,
input s_aclk,
input s_aresetn,
input s_aclk_en,
input m_aclk_en,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen,
input [3-1:0] s_axi_awsize,
input [2-1:0] s_axi_awburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock,
input [4-1:0] s_axi_awcache,
input [3-1:0] s_axi_awprot,
input [4-1:0] s_axi_awqos,
input [4-1:0] s_axi_awregion,
input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input s_axi_awvalid,
output s_axi_awready,
input [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input s_axi_wlast,
input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [2-1:0] s_axi_bresp,
output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output s_axi_bvalid,
input s_axi_bready,
// AXI Full/Lite Master Write Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen,
output [3-1:0] m_axi_awsize,
output [2-1:0] m_axi_awburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock,
output [4-1:0] m_axi_awcache,
output [3-1:0] m_axi_awprot,
output [4-1:0] m_axi_awqos,
output [4-1:0] m_axi_awregion,
output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output m_axi_awvalid,
input m_axi_awready,
output [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output m_axi_wlast,
output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output m_axi_wvalid,
input m_axi_wready,
input [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input [2-1:0] m_axi_bresp,
input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input m_axi_bvalid,
output m_axi_bready,
// AXI Full/Lite Slave Read Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen,
input [3-1:0] s_axi_arsize,
input [2-1:0] s_axi_arburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock,
input [4-1:0] s_axi_arcache,
input [3-1:0] s_axi_arprot,
input [4-1:0] s_axi_arqos,
input [4-1:0] s_axi_arregion,
input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [2-1:0] s_axi_rresp,
output s_axi_rlast,
output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output s_axi_rvalid,
input s_axi_rready,
// AXI Full/Lite Master Read Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen,
output [3-1:0] m_axi_arsize,
output [2-1:0] m_axi_arburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock,
output [4-1:0] m_axi_arcache,
output [3-1:0] m_axi_arprot,
output [4-1:0] m_axi_arqos,
output [4-1:0] m_axi_arregion,
output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
input [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [2-1:0] m_axi_rresp,
input m_axi_rlast,
input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
// AXI Streaming Slave Signals (Write side)
input s_axis_tvalid,
output s_axis_tready,
input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb,
input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep,
input s_axis_tlast,
input [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
// AXI Streaming Master Signals (Read side)
output m_axis_tvalid,
input m_axis_tready,
output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb,
output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep,
output m_axis_tlast,
output [C_AXIS_TID_WIDTH-1:0] m_axis_tid,
output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,
output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
// AXI Full/Lite Write Address Channel signals
input axi_aw_injectsbiterr,
input axi_aw_injectdbiterr,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count,
output axi_aw_sbiterr,
output axi_aw_dbiterr,
output axi_aw_overflow,
output axi_aw_underflow,
output axi_aw_prog_full,
output axi_aw_prog_empty,
// AXI Full/Lite Write Data Channel signals
input axi_w_injectsbiterr,
input axi_w_injectdbiterr,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count,
output axi_w_sbiterr,
output axi_w_dbiterr,
output axi_w_overflow,
output axi_w_underflow,
output axi_w_prog_full,
output axi_w_prog_empty,
// AXI Full/Lite Write Response Channel signals
input axi_b_injectsbiterr,
input axi_b_injectdbiterr,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count,
output axi_b_sbiterr,
output axi_b_dbiterr,
output axi_b_overflow,
output axi_b_underflow,
output axi_b_prog_full,
output axi_b_prog_empty,
// AXI Full/Lite Read Address Channel signals
input axi_ar_injectsbiterr,
input axi_ar_injectdbiterr,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count,
output axi_ar_sbiterr,
output axi_ar_dbiterr,
output axi_ar_overflow,
output axi_ar_underflow,
output axi_ar_prog_full,
output axi_ar_prog_empty,
// AXI Full/Lite Read Data Channel Signals
input axi_r_injectsbiterr,
input axi_r_injectdbiterr,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count,
output axi_r_sbiterr,
output axi_r_dbiterr,
output axi_r_overflow,
output axi_r_underflow,
output axi_r_prog_full,
output axi_r_prog_empty,
// AXI Streaming FIFO Related Signals
input axis_injectsbiterr,
input axis_injectdbiterr,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count,
output axis_sbiterr,
output axis_dbiterr,
output axis_overflow,
output axis_underflow,
output axis_prog_full,
output axis_prog_empty
);
wire BACKUP;
wire BACKUP_MARKER;
wire CLK;
wire RST;
wire SRST;
wire WR_CLK;
wire WR_RST;
wire RD_CLK;
wire RD_RST;
wire [C_DIN_WIDTH-1:0] DIN;
wire WR_EN;
wire RD_EN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire INT_CLK;
wire INJECTDBITERR;
wire INJECTSBITERR;
wire SLEEP;
wire [C_DOUT_WIDTH-1:0] DOUT;
wire FULL;
wire ALMOST_FULL;
wire WR_ACK;
wire OVERFLOW;
wire EMPTY;
wire ALMOST_EMPTY;
wire VALID;
wire UNDERFLOW;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
wire PROG_FULL;
wire PROG_EMPTY;
wire SBITERR;
wire DBITERR;
wire WR_RST_BUSY;
wire RD_RST_BUSY;
wire M_ACLK;
wire S_ACLK;
wire S_ARESETN;
wire S_ACLK_EN;
wire M_ACLK_EN;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN;
wire [3-1:0] S_AXI_AWSIZE;
wire [2-1:0] S_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK;
wire [4-1:0] S_AXI_AWCACHE;
wire [3-1:0] S_AXI_AWPROT;
wire [4-1:0] S_AXI_AWQOS;
wire [4-1:0] S_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER;
wire S_AXI_AWVALID;
wire S_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB;
wire S_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER;
wire S_AXI_WVALID;
wire S_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [2-1:0] S_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER;
wire S_AXI_BVALID;
wire S_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN;
wire [3-1:0] M_AXI_AWSIZE;
wire [2-1:0] M_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK;
wire [4-1:0] M_AXI_AWCACHE;
wire [3-1:0] M_AXI_AWPROT;
wire [4-1:0] M_AXI_AWQOS;
wire [4-1:0] M_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER;
wire M_AXI_AWVALID;
wire M_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB;
wire M_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER;
wire M_AXI_WVALID;
wire M_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID;
wire [2-1:0] M_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER;
wire M_AXI_BVALID;
wire M_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN;
wire [3-1:0] S_AXI_ARSIZE;
wire [2-1:0] S_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK;
wire [4-1:0] S_AXI_ARCACHE;
wire [3-1:0] S_AXI_ARPROT;
wire [4-1:0] S_AXI_ARQOS;
wire [4-1:0] S_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER;
wire S_AXI_ARVALID;
wire S_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA;
wire [2-1:0] S_AXI_RRESP;
wire S_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER;
wire S_AXI_RVALID;
wire S_AXI_RREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN;
wire [3-1:0] M_AXI_ARSIZE;
wire [2-1:0] M_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK;
wire [4-1:0] M_AXI_ARCACHE;
wire [3-1:0] M_AXI_ARPROT;
wire [4-1:0] M_AXI_ARQOS;
wire [4-1:0] M_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER;
wire M_AXI_ARVALID;
wire M_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA;
wire [2-1:0] M_AXI_RRESP;
wire M_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER;
wire M_AXI_RVALID;
wire M_AXI_RREADY;
wire S_AXIS_TVALID;
wire S_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP;
wire S_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER;
wire M_AXIS_TVALID;
wire M_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP;
wire M_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER;
wire AXI_AW_INJECTSBITERR;
wire AXI_AW_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT;
wire AXI_AW_SBITERR;
wire AXI_AW_DBITERR;
wire AXI_AW_OVERFLOW;
wire AXI_AW_UNDERFLOW;
wire AXI_AW_PROG_FULL;
wire AXI_AW_PROG_EMPTY;
wire AXI_W_INJECTSBITERR;
wire AXI_W_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT;
wire AXI_W_SBITERR;
wire AXI_W_DBITERR;
wire AXI_W_OVERFLOW;
wire AXI_W_UNDERFLOW;
wire AXI_W_PROG_FULL;
wire AXI_W_PROG_EMPTY;
wire AXI_B_INJECTSBITERR;
wire AXI_B_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT;
wire AXI_B_SBITERR;
wire AXI_B_DBITERR;
wire AXI_B_OVERFLOW;
wire AXI_B_UNDERFLOW;
wire AXI_B_PROG_FULL;
wire AXI_B_PROG_EMPTY;
wire AXI_AR_INJECTSBITERR;
wire AXI_AR_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT;
wire AXI_AR_SBITERR;
wire AXI_AR_DBITERR;
wire AXI_AR_OVERFLOW;
wire AXI_AR_UNDERFLOW;
wire AXI_AR_PROG_FULL;
wire AXI_AR_PROG_EMPTY;
wire AXI_R_INJECTSBITERR;
wire AXI_R_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT;
wire AXI_R_SBITERR;
wire AXI_R_DBITERR;
wire AXI_R_OVERFLOW;
wire AXI_R_UNDERFLOW;
wire AXI_R_PROG_FULL;
wire AXI_R_PROG_EMPTY;
wire AXIS_INJECTSBITERR;
wire AXIS_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT;
wire AXIS_SBITERR;
wire AXIS_DBITERR;
wire AXIS_OVERFLOW;
wire AXIS_UNDERFLOW;
wire AXIS_PROG_FULL;
wire AXIS_PROG_EMPTY;
wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in;
wire wr_rst_int;
wire rd_rst_int;
wire wr_rst_busy_o;
wire wr_rst_busy_ntve;
wire wr_rst_busy_axis;
wire wr_rst_busy_wach;
wire wr_rst_busy_wdch;
wire wr_rst_busy_wrch;
wire wr_rst_busy_rach;
wire wr_rst_busy_rdch;
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// Conventional FIFO Interface Signals
assign BACKUP = backup;
assign BACKUP_MARKER = backup_marker;
assign CLK = clk;
assign RST = rst;
assign SRST = srst;
assign WR_CLK = wr_clk;
assign WR_RST = wr_rst;
assign RD_CLK = rd_clk;
assign RD_RST = rd_rst;
assign WR_EN = wr_en;
assign RD_EN = rd_en;
assign INT_CLK = int_clk;
assign INJECTDBITERR = injectdbiterr;
assign INJECTSBITERR = injectsbiterr;
assign SLEEP = sleep;
assign full = FULL;
assign almost_full = ALMOST_FULL;
assign wr_ack = WR_ACK;
assign overflow = OVERFLOW;
assign empty = EMPTY;
assign almost_empty = ALMOST_EMPTY;
assign valid = VALID;
assign underflow = UNDERFLOW;
assign prog_full = PROG_FULL;
assign prog_empty = PROG_EMPTY;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
// assign wr_rst_busy = WR_RST_BUSY | wr_rst_busy_o;
assign wr_rst_busy = wr_rst_busy_o;
assign rd_rst_busy = RD_RST_BUSY;
assign M_ACLK = m_aclk;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_ACLK_EN = s_aclk_en;
assign M_ACLK_EN = m_aclk_en;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign m_axi_awvalid = M_AXI_AWVALID;
assign M_AXI_AWREADY = m_axi_awready;
assign m_axi_wlast = M_AXI_WLAST;
assign m_axi_wvalid = M_AXI_WVALID;
assign M_AXI_WREADY = m_axi_wready;
assign M_AXI_BVALID = m_axi_bvalid;
assign m_axi_bready = M_AXI_BREADY;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign m_axi_arvalid = M_AXI_ARVALID;
assign M_AXI_ARREADY = m_axi_arready;
assign M_AXI_RLAST = m_axi_rlast;
assign M_AXI_RVALID = m_axi_rvalid;
assign m_axi_rready = M_AXI_RREADY;
assign S_AXIS_TVALID = s_axis_tvalid;
assign s_axis_tready = S_AXIS_TREADY;
assign S_AXIS_TLAST = s_axis_tlast;
assign m_axis_tvalid = M_AXIS_TVALID;
assign M_AXIS_TREADY = m_axis_tready;
assign m_axis_tlast = M_AXIS_TLAST;
assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr;
assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr;
assign axi_aw_sbiterr = AXI_AW_SBITERR;
assign axi_aw_dbiterr = AXI_AW_DBITERR;
assign axi_aw_overflow = AXI_AW_OVERFLOW;
assign axi_aw_underflow = AXI_AW_UNDERFLOW;
assign axi_aw_prog_full = AXI_AW_PROG_FULL;
assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY;
assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr;
assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr;
assign axi_w_sbiterr = AXI_W_SBITERR;
assign axi_w_dbiterr = AXI_W_DBITERR;
assign axi_w_overflow = AXI_W_OVERFLOW;
assign axi_w_underflow = AXI_W_UNDERFLOW;
assign axi_w_prog_full = AXI_W_PROG_FULL;
assign axi_w_prog_empty = AXI_W_PROG_EMPTY;
assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr;
assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr;
assign axi_b_sbiterr = AXI_B_SBITERR;
assign axi_b_dbiterr = AXI_B_DBITERR;
assign axi_b_overflow = AXI_B_OVERFLOW;
assign axi_b_underflow = AXI_B_UNDERFLOW;
assign axi_b_prog_full = AXI_B_PROG_FULL;
assign axi_b_prog_empty = AXI_B_PROG_EMPTY;
assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr;
assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr;
assign axi_ar_sbiterr = AXI_AR_SBITERR;
assign axi_ar_dbiterr = AXI_AR_DBITERR;
assign axi_ar_overflow = AXI_AR_OVERFLOW;
assign axi_ar_underflow = AXI_AR_UNDERFLOW;
assign axi_ar_prog_full = AXI_AR_PROG_FULL;
assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY;
assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr;
assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr;
assign axi_r_sbiterr = AXI_R_SBITERR;
assign axi_r_dbiterr = AXI_R_DBITERR;
assign axi_r_overflow = AXI_R_OVERFLOW;
assign axi_r_underflow = AXI_R_UNDERFLOW;
assign axi_r_prog_full = AXI_R_PROG_FULL;
assign axi_r_prog_empty = AXI_R_PROG_EMPTY;
assign AXIS_INJECTSBITERR = axis_injectsbiterr;
assign AXIS_INJECTDBITERR = axis_injectdbiterr;
assign axis_sbiterr = AXIS_SBITERR;
assign axis_dbiterr = AXIS_DBITERR;
assign axis_overflow = AXIS_OVERFLOW;
assign axis_underflow = AXIS_UNDERFLOW;
assign axis_prog_full = AXIS_PROG_FULL;
assign axis_prog_empty = AXIS_PROG_EMPTY;
assign DIN = din;
assign PROG_EMPTY_THRESH = prog_empty_thresh;
assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert;
assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate;
assign PROG_FULL_THRESH = prog_full_thresh;
assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert;
assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate;
assign dout = DOUT;
assign data_count = DATA_COUNT;
assign rd_data_count = RD_DATA_COUNT;
assign wr_data_count = WR_DATA_COUNT;
assign S_AXI_AWID = s_axi_awid;
assign S_AXI_AWADDR = s_axi_awaddr;
assign S_AXI_AWLEN = s_axi_awlen;
assign S_AXI_AWSIZE = s_axi_awsize;
assign S_AXI_AWBURST = s_axi_awburst;
assign S_AXI_AWLOCK = s_axi_awlock;
assign S_AXI_AWCACHE = s_axi_awcache;
assign S_AXI_AWPROT = s_axi_awprot;
assign S_AXI_AWQOS = s_axi_awqos;
assign S_AXI_AWREGION = s_axi_awregion;
assign S_AXI_AWUSER = s_axi_awuser;
assign S_AXI_WID = s_axi_wid;
assign S_AXI_WDATA = s_axi_wdata;
assign S_AXI_WSTRB = s_axi_wstrb;
assign S_AXI_WUSER = s_axi_wuser;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_buser = S_AXI_BUSER;
assign m_axi_awid = M_AXI_AWID;
assign m_axi_awaddr = M_AXI_AWADDR;
assign m_axi_awlen = M_AXI_AWLEN;
assign m_axi_awsize = M_AXI_AWSIZE;
assign m_axi_awburst = M_AXI_AWBURST;
assign m_axi_awlock = M_AXI_AWLOCK;
assign m_axi_awcache = M_AXI_AWCACHE;
assign m_axi_awprot = M_AXI_AWPROT;
assign m_axi_awqos = M_AXI_AWQOS;
assign m_axi_awregion = M_AXI_AWREGION;
assign m_axi_awuser = M_AXI_AWUSER;
assign m_axi_wid = M_AXI_WID;
assign m_axi_wdata = M_AXI_WDATA;
assign m_axi_wstrb = M_AXI_WSTRB;
assign m_axi_wuser = M_AXI_WUSER;
assign M_AXI_BID = m_axi_bid;
assign M_AXI_BRESP = m_axi_bresp;
assign M_AXI_BUSER = m_axi_buser;
assign S_AXI_ARID = s_axi_arid;
assign S_AXI_ARADDR = s_axi_araddr;
assign S_AXI_ARLEN = s_axi_arlen;
assign S_AXI_ARSIZE = s_axi_arsize;
assign S_AXI_ARBURST = s_axi_arburst;
assign S_AXI_ARLOCK = s_axi_arlock;
assign S_AXI_ARCACHE = s_axi_arcache;
assign S_AXI_ARPROT = s_axi_arprot;
assign S_AXI_ARQOS = s_axi_arqos;
assign S_AXI_ARREGION = s_axi_arregion;
assign S_AXI_ARUSER = s_axi_aruser;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_ruser = S_AXI_RUSER;
assign m_axi_arid = M_AXI_ARID;
assign m_axi_araddr = M_AXI_ARADDR;
assign m_axi_arlen = M_AXI_ARLEN;
assign m_axi_arsize = M_AXI_ARSIZE;
assign m_axi_arburst = M_AXI_ARBURST;
assign m_axi_arlock = M_AXI_ARLOCK;
assign m_axi_arcache = M_AXI_ARCACHE;
assign m_axi_arprot = M_AXI_ARPROT;
assign m_axi_arqos = M_AXI_ARQOS;
assign m_axi_arregion = M_AXI_ARREGION;
assign m_axi_aruser = M_AXI_ARUSER;
assign M_AXI_RID = m_axi_rid;
assign M_AXI_RDATA = m_axi_rdata;
assign M_AXI_RRESP = m_axi_rresp;
assign M_AXI_RUSER = m_axi_ruser;
assign S_AXIS_TDATA = s_axis_tdata;
assign S_AXIS_TSTRB = s_axis_tstrb;
assign S_AXIS_TKEEP = s_axis_tkeep;
assign S_AXIS_TID = s_axis_tid;
assign S_AXIS_TDEST = s_axis_tdest;
assign S_AXIS_TUSER = s_axis_tuser;
assign m_axis_tdata = M_AXIS_TDATA;
assign m_axis_tstrb = M_AXIS_TSTRB;
assign m_axis_tkeep = M_AXIS_TKEEP;
assign m_axis_tid = M_AXIS_TID;
assign m_axis_tdest = M_AXIS_TDEST;
assign m_axis_tuser = M_AXIS_TUSER;
assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh;
assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh;
assign axi_aw_data_count = AXI_AW_DATA_COUNT;
assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT;
assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT;
assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh;
assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh;
assign axi_w_data_count = AXI_W_DATA_COUNT;
assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT;
assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT;
assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh;
assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh;
assign axi_b_data_count = AXI_B_DATA_COUNT;
assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT;
assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT;
assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh;
assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh;
assign axi_ar_data_count = AXI_AR_DATA_COUNT;
assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT;
assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT;
assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh;
assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh;
assign axi_r_data_count = AXI_R_DATA_COUNT;
assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT;
assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT;
assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh;
assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh;
assign axis_data_count = AXIS_DATA_COUNT;
assign axis_wr_data_count = AXIS_WR_DATA_COUNT;
assign axis_rd_data_count = AXIS_RD_DATA_COUNT;
generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo
fifo_generator_v13_1_3_CONV_VER
#(
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_FAMILY (C_FAMILY),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RD_RST (C_HAS_RD_RST),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_HAS_WR_RST (C_HAS_WR_RST),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_FREQ (C_RD_FREQ),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
)
fifo_generator_v13_1_3_conv_dut
(
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.CLK (CLK),
.RST (RST),
.SRST (SRST),
.WR_CLK (WR_CLK),
.WR_RST (WR_RST),
.RD_CLK (RD_CLK),
.RD_RST (RD_RST),
.DIN (DIN),
.WR_EN (WR_EN),
.RD_EN (RD_EN),
.PROG_EMPTY_THRESH (PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
.PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
.PROG_FULL_THRESH (PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT),
.PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE),
.INT_CLK (INT_CLK),
.INJECTDBITERR (INJECTDBITERR),
.INJECTSBITERR (INJECTSBITERR),
.DOUT (DOUT),
.FULL (FULL),
.ALMOST_FULL (ALMOST_FULL),
.WR_ACK (WR_ACK),
.OVERFLOW (OVERFLOW),
.EMPTY (EMPTY),
.ALMOST_EMPTY (ALMOST_EMPTY),
.VALID (VALID),
.UNDERFLOW (UNDERFLOW),
.DATA_COUNT (DATA_COUNT),
.RD_DATA_COUNT (RD_DATA_COUNT),
.WR_DATA_COUNT (wr_data_count_in),
.PROG_FULL (PROG_FULL),
.PROG_EMPTY (PROG_EMPTY),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.wr_rst_busy_o (wr_rst_busy_o),
.wr_rst_busy (wr_rst_busy_i),
.rd_rst_busy (rd_rst_busy),
.wr_rst_i_out (wr_rst_int),
.rd_rst_i_out (rd_rst_int)
);
end endgenerate
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_AXI_SIZE_WIDTH = 3;
localparam C_AXI_BURST_WIDTH = 2;
localparam C_AXI_CACHE_WIDTH = 4;
localparam C_AXI_PROT_WIDTH = 3;
localparam C_AXI_QOS_WIDTH = 4;
localparam C_AXI_REGION_WIDTH = 4;
localparam C_AXI_BRESP_WIDTH = 2;
localparam C_AXI_RRESP_WIDTH = 2;
localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0;
localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;
localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;
localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;
localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;
localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;
localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;
localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS);
localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH);
function [LOG_DEPTH_AXIS-1:0] bin2gray;
input [LOG_DEPTH_AXIS-1:0] x;
begin
bin2gray = x ^ (x>>1);
end
endfunction
function [LOG_DEPTH_AXIS-1:0] gray2bin;
input [LOG_DEPTH_AXIS-1:0] x;
integer i;
begin
gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];
for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin
gray2bin[i] = gray2bin[i+1] ^ x[i];
end
end
endfunction
wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;
wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ;
wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;
reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;
wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;
wire [LOG_WR_DEPTH : 0] r_inv_pad;
wire [LOG_WR_DEPTH-1 : 0] d_cnt;
reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;
reg adj_w_cnt_rd_pad_0 = 0;
reg r_inv_pad_0 = 0;
genvar l;
generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_WR_DEPTH)
)
rd_stg_inst
(
.RST (rd_rst_int),
.CLK (RD_CLK),
.DIN (w_q[l-1]),
.DOUT (w_q[l])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter
assign wr_eop_ad = WR_EN & !(FULL);
assign rd_eop_ad = RD_EN & !(EMPTY);
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt <= 1'b0;
else if (wr_eop_ad)
w_cnt <= w_cnt + 1;
end
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt_gc <= 1'b0;
else
w_cnt_gc <= bin2gray(w_cnt);
end
assign w_q[0] = w_cnt_gc;
assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE];
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
w_cnt_rd <= 1'b0;
else
w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last);
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
r_cnt <= 1'b0;
else if (rd_eop_ad)
r_cnt <= r_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;
assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt;
assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0;
assign r_inv_pad[0] = r_inv_pad_0;
always @ ( rd_eop_ad )
begin
if (!rd_eop_ad) begin
adj_w_cnt_rd_pad_0 <= 1'b1;
r_inv_pad_0 <= 1'b1;
end else begin
adj_w_cnt_rd_pad_0 <= 1'b0;
r_inv_pad_0 <= 1'b0;
end
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
d_cnt_pad <= 1'b0;
else
d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ;
end
assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;
assign WR_DATA_COUNT = d_cnt;
end endgenerate // fifo_ic_adapter
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter
assign WR_DATA_COUNT = wr_data_count_in;
end endgenerate // fifo_icn_adapter
wire inverted_reset = ~S_ARESETN;
wire axi_rs_rst;
wire [C_DIN_WIDTH_AXIS-1:0] axis_din ;
wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ;
wire axis_full ;
wire axis_almost_full ;
wire axis_empty ;
wire axis_s_axis_tready;
wire axis_m_axis_tvalid;
wire axis_wr_en ;
wire axis_rd_en ;
wire axis_we ;
wire axis_re ;
wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;
reg axis_pkt_read = 1'b0;
wire axis_rd_rst;
wire axis_wr_rst;
generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||
C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst
reg rst_d1 = 0 ;
reg rst_d2 = 0 ;
reg [3:0] axi_rst = 4'h0 ;
always @ (posedge inverted_reset or posedge S_ACLK) begin
if (inverted_reset) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
axi_rst <= 4'hf;
end else begin
rst_d1 <= #`TCQ 1'b0;
rst_d2 <= #`TCQ rst_d1;
axi_rst <= #`TCQ {axi_rst[2:0],1'b0};
end
end
assign axi_rs_rst = axi_rst[3];//rst_d2;
end endgenerate // gaxi_rs_rst
generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming
// Write protection when almost full or prog_full is high
assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;
// Read protection when almost empty or prog_empty is high
assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_AXIS),
.C_WR_DEPTH (C_WR_DEPTH_AXIS),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_DOUT_WIDTH (C_DIN_WIDTH_AXIS),
.C_RD_DEPTH (C_WR_DEPTH_AXIS),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),
.C_USE_ECC (C_USE_ECC_AXIS),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_axis_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (axis_wr_en),
.RD_EN (axis_rd_en),
.PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.INJECTDBITERR (AXIS_INJECTDBITERR),
.INJECTSBITERR (AXIS_INJECTSBITERR),
.DIN (axis_din),
.DOUT (axis_dout),
.FULL (axis_full),
.EMPTY (axis_empty),
.ALMOST_FULL (axis_almost_full),
.PROG_FULL (AXIS_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXIS_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (AXIS_OVERFLOW),
.VALID (),
.UNDERFLOW (AXIS_UNDERFLOW),
.DATA_COUNT (axis_dc),
.RD_DATA_COUNT (AXIS_RD_DATA_COUNT),
.WR_DATA_COUNT (AXIS_WR_DATA_COUNT),
.SBITERR (AXIS_SBITERR),
.DBITERR (AXIS_DBITERR),
.wr_rst_busy (wr_rst_busy_axis),
.rd_rst_busy (rd_rst_busy_axis),
.wr_rst_i_out (axis_wr_rst),
.rd_rst_i_out (axis_rd_rst),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;
assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;
assign S_AXIS_TREADY = axis_s_axis_tready;
assign M_AXIS_TVALID = axis_m_axis_tvalid;
end endgenerate // axi_streaming
wire axis_wr_eop;
reg axis_wr_eop_d1 = 1'b0;
wire axis_rd_eop;
integer axis_pkt_cnt;
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)
axis_pkt_read <= 1'b0;
else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_wr_eop_d1 <= 1'b0;
else
axis_wr_eop_d1 <= axis_wr_eop;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_cnt <= 0;
else if (axis_wr_eop_d1 && ~axis_rd_eop)
axis_pkt_cnt <= axis_pkt_cnt + 1;
else if (axis_rd_eop && ~axis_wr_eop_d1)
axis_pkt_cnt <= axis_pkt_cnt - 1;
end
end endgenerate // gaxis_pkt_fifo_cc
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;
wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;
wire axis_rd_has_rst;
wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ;
wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;
wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;
wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;
wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;
reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;
reg adj_axis_wpkt_cnt_rd_pad_0 = 0;
reg rpkt_inv_pad_0 = 0;
wire axis_af_rd ;
generate if (C_HAS_RST == 1) begin : rst_blk_has
assign axis_rd_has_rst = axis_rd_rst;
end endgenerate //rst_blk_has
generate if (C_HAS_RST == 0) begin :rst_blk_no
assign axis_rd_has_rst = 1'b0;
end endgenerate //rst_blk_no
genvar i;
generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_DEPTH_AXIS)
)
rd_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (wpkt_q[i-1]),
.DOUT (wpkt_q[i])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (1)
)
wr_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (axis_af_q[i-1]),
.DOUT (axis_af_q[i])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (diff_pkt_cnt == 1))
axis_pkt_read <= 1'b0;
else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt <= 1'b0;
else if (axis_wr_eop)
axis_wpkt_cnt <= axis_wpkt_cnt + 1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt_gc <= 1'b0;
else
axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt);
end
assign wpkt_q[0] = axis_wpkt_cnt_gc;
assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE];
assign axis_af_q[0] = axis_almost_full;
//assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];
assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_wpkt_cnt_rd <= 1'b0;
else
axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last);
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_rpkt_cnt <= 1'b0;
else if (axis_rd_eop)
axis_rpkt_cnt <= axis_rpkt_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;
assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt;
assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0;
assign rpkt_inv_pad[0] = rpkt_inv_pad_0;
always @ ( axis_rd_eop )
begin
if (!axis_rd_eop) begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1;
rpkt_inv_pad_0 <= 1'b1;
end else begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0;
rpkt_inv_pad_0 <= 1'b0;
end
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
diff_pkt_cnt_pad <= 1'b0;
else
diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;
end
assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;
end endgenerate // gaxis_pkt_fifo_ic
// Generate the accurate data count for axi stream packet fifo configuration
reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_dc_pkt_fifo <= 0;
else if (axis_wr_en && (~axis_rd_en))
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;
else if (~axis_wr_en && axis_rd_en)
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;
end
assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;
end endgenerate // gdc_pkt
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt
assign AXIS_DATA_COUNT = 0;
end endgenerate // gndc_pkt
generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc
assign AXIS_DATA_COUNT = axis_dc;
end endgenerate // gdc
// Register Slice for Write Address Channel
generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_AXIS),
.C_REG_CONFIG (C_REG_SLICE_MODE_AXIS)
)
axis_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (axis_din),
.S_VALID (axis_wr_en),
.S_READY (S_AXIS_TREADY),
// Master side
.M_PAYLOAD_DATA (axis_dout),
.M_VALID (M_AXIS_TVALID),
.M_READY (axis_rd_en)
);
end endgenerate // gaxis_reg_slice
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata
assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;
assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb
assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;
assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep
assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;
assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid
assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;
assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest
assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;
assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser
assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;
assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast
assign axis_din[0] = S_AXIS_TLAST;
assign M_AXIS_TLAST = axis_dout[0];
end endgenerate
//###########################################################################
// AXI FULL Write Channel (axi_write_channel)
//###########################################################################
localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;
localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;
localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;
localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;
localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;
localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;
localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;
localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;
localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH;
localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;
localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;
localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;
localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;
localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;
localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;
localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;
localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;
localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH;
localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;
localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;
localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH;
localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;
wire [C_DIN_WIDTH_WACH-1:0] wach_din ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ;
wire wach_full ;
wire wach_almost_full ;
wire wach_prog_full ;
wire wach_empty ;
wire wach_almost_empty ;
wire wach_prog_empty ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ;
wire wdch_full ;
wire wdch_almost_full ;
wire wdch_prog_full ;
wire wdch_empty ;
wire wdch_almost_empty ;
wire wdch_prog_empty ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ;
wire wrch_full ;
wire wrch_almost_full ;
wire wrch_prog_full ;
wire wrch_empty ;
wire wrch_almost_empty ;
wire wrch_prog_empty ;
wire axi_aw_underflow_i;
wire axi_w_underflow_i ;
wire axi_b_underflow_i ;
wire axi_aw_overflow_i ;
wire axi_w_overflow_i ;
wire axi_b_overflow_i ;
wire axi_wr_underflow_i;
wire axi_wr_overflow_i ;
wire wach_s_axi_awready;
wire wach_m_axi_awvalid;
wire wach_wr_en ;
wire wach_rd_en ;
wire wdch_s_axi_wready ;
wire wdch_m_axi_wvalid ;
wire wdch_wr_en ;
wire wdch_rd_en ;
wire wrch_s_axi_bvalid ;
wire wrch_m_axi_bready ;
wire wrch_wr_en ;
wire wrch_rd_en ;
wire txn_count_up ;
wire txn_count_down ;
wire awvalid_en ;
wire awvalid_pkt ;
wire awready_pkt ;
integer wr_pkt_count ;
wire wach_we ;
wire wach_re ;
wire wdch_we ;
wire wdch_re ;
wire wrch_we ;
wire wrch_re ;
generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel
// Write protection when almost full or prog_full is high
assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;
// Read protection when almost empty or prog_empty is high
assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ?
wach_m_axi_awvalid & awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY && wach_m_axi_awvalid :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ?
awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY : 1'b0;
assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we;
assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_DEPTH (C_WR_DEPTH_WACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WACH),
.C_RD_DEPTH (C_WR_DEPTH_WACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),
.C_USE_ECC (C_USE_ECC_WACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wach_wr_en),
.RD_EN (wach_rd_en),
.PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.INJECTDBITERR (AXI_AW_INJECTDBITERR),
.INJECTSBITERR (AXI_AW_INJECTSBITERR),
.DIN (wach_din),
.DOUT (wach_dout_pkt),
.FULL (wach_full),
.EMPTY (wach_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_AW_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_AW_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_aw_overflow_i),
.VALID (),
.UNDERFLOW (axi_aw_underflow_i),
.DATA_COUNT (AXI_AW_DATA_COUNT),
.RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT),
.SBITERR (AXI_AW_SBITERR),
.DBITERR (AXI_AW_DBITERR),
.wr_rst_busy (wr_rst_busy_wach),
.rd_rst_busy (rd_rst_busy_wach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;
assign wach_m_axi_awvalid = ~wach_empty;
assign S_AXI_AWREADY = wach_s_axi_awready;
assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;
assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0;
end endgenerate // axi_write_address_channel
// Register Slice for Write Address Channel
generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WACH)
)
wach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wach_din),
.S_VALID (S_AXI_AWVALID),
.S_READY (S_AXI_AWREADY),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
end endgenerate // gwach_reg_slice
generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (1)
)
wach_pkt_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (wach_dout_pkt),
.S_VALID (awvalid_pkt),
.S_READY (awready_pkt),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;
assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0];
assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset == 1) begin
wr_pkt_count <= 0;
end else begin
if(txn_count_up == 1 && txn_count_down == 0) begin
wr_pkt_count <= wr_pkt_count + 1;
end else if(txn_count_up == 0 && txn_count_down == 1) begin
wr_pkt_count <= wr_pkt_count - 1;
end
end
end //Always end
assign awvalid_en = (wr_pkt_count > 0)?1:0;
end endgenerate
generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr
assign awvalid_en = 1;
assign wach_dout = wach_dout_pkt;
assign M_AXI_AWVALID = wach_m_axi_awvalid;
end
endgenerate
generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel
// Write protection when almost full or prog_full is high
assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;
// Read protection when almost empty or prog_empty is high
assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;
assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we;
assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WDCH),
.C_WR_DEPTH (C_WR_DEPTH_WDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WDCH),
.C_RD_DEPTH (C_WR_DEPTH_WDCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),
.C_USE_ECC (C_USE_ECC_WDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wdch_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wdch_wr_en),
.RD_EN (wdch_rd_en),
.PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.INJECTDBITERR (AXI_W_INJECTDBITERR),
.INJECTSBITERR (AXI_W_INJECTSBITERR),
.DIN (wdch_din),
.DOUT (wdch_dout),
.FULL (wdch_full),
.EMPTY (wdch_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_W_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_W_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_w_overflow_i),
.VALID (),
.UNDERFLOW (axi_w_underflow_i),
.DATA_COUNT (AXI_W_DATA_COUNT),
.RD_DATA_COUNT (AXI_W_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_W_WR_DATA_COUNT),
.SBITERR (AXI_W_SBITERR),
.DBITERR (AXI_W_DBITERR),
.wr_rst_busy (wr_rst_busy_wdch),
.rd_rst_busy (rd_rst_busy_wdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;
assign wdch_m_axi_wvalid = ~wdch_empty;
assign S_AXI_WREADY = wdch_s_axi_wready;
assign M_AXI_WVALID = wdch_m_axi_wvalid;
assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0;
assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0;
end endgenerate // axi_write_data_channel
// Register Slice for Write Data Channel
generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WDCH)
)
wdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wdch_din),
.S_VALID (S_AXI_WVALID),
.S_READY (S_AXI_WREADY),
// Master side
.M_PAYLOAD_DATA (wdch_dout),
.M_VALID (M_AXI_WVALID),
.M_READY (M_AXI_WREADY)
);
end endgenerate // gwdch_reg_slice
generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel
// Write protection when almost full or prog_full is high
assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;
// Read protection when almost empty or prog_empty is high
assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;
assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we;
assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WRCH),
.C_WR_DEPTH (C_WR_DEPTH_WRCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WRCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_DEPTH (C_WR_DEPTH_WRCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),
.C_USE_ECC (C_USE_ECC_WRCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wrch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wrch_wr_en),
.RD_EN (wrch_rd_en),
.PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.INJECTDBITERR (AXI_B_INJECTDBITERR),
.INJECTSBITERR (AXI_B_INJECTSBITERR),
.DIN (wrch_din),
.DOUT (wrch_dout),
.FULL (wrch_full),
.EMPTY (wrch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_B_PROG_FULL),
.PROG_EMPTY (AXI_B_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_b_overflow_i),
.VALID (),
.UNDERFLOW (axi_b_underflow_i),
.DATA_COUNT (AXI_B_DATA_COUNT),
.RD_DATA_COUNT (AXI_B_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_B_WR_DATA_COUNT),
.SBITERR (AXI_B_SBITERR),
.DBITERR (AXI_B_DBITERR),
.wr_rst_busy (wr_rst_busy_wrch),
.rd_rst_busy (rd_rst_busy_wrch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wrch_s_axi_bvalid = ~wrch_empty;
assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;
assign S_AXI_BVALID = wrch_s_axi_bvalid;
assign M_AXI_BREADY = wrch_m_axi_bready;
assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0;
assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0;
end endgenerate // axi_write_resp_channel
// Register Slice for Write Response Channel
generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WRCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WRCH)
)
wrch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wrch_din),
.S_VALID (M_AXI_BVALID),
.S_READY (M_AXI_BREADY),
// Master side
.M_PAYLOAD_DATA (wrch_dout),
.M_VALID (S_AXI_BVALID),
.M_READY (S_AXI_BREADY)
);
end endgenerate // gwrch_reg_slice
assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;
assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0;
generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output
assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];
assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];
assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];
assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];
assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];
assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];
assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];
assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR;
assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN;
assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE;
assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;
assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;
assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;
assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;
assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS;
end endgenerate // axi_wach_output
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion
assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];
end endgenerate // axi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion
assign M_AXI_AWREGION = 0;
end endgenerate // naxi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser
assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];
end endgenerate // axi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser
assign M_AXI_AWUSER = 0;
end endgenerate // naxi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid
assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];
end endgenerate //axi_awid
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid
assign M_AXI_AWID = 0;
end endgenerate //naxi_awid
generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output
assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
assign M_AXI_WLAST = wdch_dout[0];
assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA;
assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;
assign wdch_din[0] = S_AXI_WLAST;
end endgenerate // axi_wdch_output
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin
assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin
assign M_AXI_WID = 0;
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin
assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];
end endgenerate
generate if (C_HAS_AXI_WUSER == 0) begin
assign M_AXI_WUSER = 0;
end endgenerate
generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output
assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET];
assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP;
end endgenerate // axi_wrch_output
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser
assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];
end endgenerate // axi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser
assign S_AXI_BUSER = 0;
end endgenerate // naxi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid
assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];
end endgenerate // axi_bid
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid
assign S_AXI_BID = 0 ;
end endgenerate // naxi_bid
generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1
assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT};
assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];
end endgenerate // axi_wach_output1
generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1
assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB};
assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
end endgenerate // axi_wdch_output1
generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1
assign wrch_din = M_AXI_BRESP;
assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET];
end endgenerate // axi_wrch_output1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1
assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER;
end endgenerate // gwach_din1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2
assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID;
end endgenerate // gwach_din2
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3
assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION;
end endgenerate // gwach_din3
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1
assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;
end endgenerate // gwdch_din1
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2
assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;
end endgenerate // gwdch_din2
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1
assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER;
end endgenerate // gwrch_din1
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2
assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID;
end endgenerate // gwrch_din2
//end of axi_write_channel
//###########################################################################
// AXI FULL Read Channel (axi_read_channel)
//###########################################################################
wire [C_DIN_WIDTH_RACH-1:0] rach_din ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ;
wire rach_full ;
wire rach_almost_full ;
wire rach_prog_full ;
wire rach_empty ;
wire rach_almost_empty ;
wire rach_prog_empty ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ;
wire rdch_full ;
wire rdch_almost_full ;
wire rdch_prog_full ;
wire rdch_empty ;
wire rdch_almost_empty ;
wire rdch_prog_empty ;
wire axi_ar_underflow_i ;
wire axi_r_underflow_i ;
wire axi_ar_overflow_i ;
wire axi_r_overflow_i ;
wire axi_rd_underflow_i ;
wire axi_rd_overflow_i ;
wire rach_s_axi_arready ;
wire rach_m_axi_arvalid ;
wire rach_wr_en ;
wire rach_rd_en ;
wire rdch_m_axi_rready ;
wire rdch_s_axi_rvalid ;
wire rdch_wr_en ;
wire rdch_rd_en ;
wire arvalid_pkt ;
wire arready_pkt ;
wire arvalid_en ;
wire rdch_rd_ok ;
wire accept_next_pkt ;
integer rdch_free_space ;
integer rdch_commited_space ;
wire rach_we ;
wire rach_re ;
wire rdch_we ;
wire rdch_re ;
localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;
localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH;
localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;
localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;
localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;
localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;
localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;
localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;
localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;
localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;
localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH;
localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH;
localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;
generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel
// Write protection when almost full or prog_full is high
assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;
// Read protection when almost empty or prog_empty is high
// assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;
assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ?
rach_m_axi_arvalid & arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY && rach_m_axi_arvalid :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ?
arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY : 1'b0;
assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we;
assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RACH),
.C_WR_DEPTH (C_WR_DEPTH_RACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_DOUT_WIDTH (C_DIN_WIDTH_RACH),
.C_RD_DEPTH (C_WR_DEPTH_RACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),
.C_USE_ECC (C_USE_ECC_RACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rach_wr_en),
.RD_EN (rach_rd_en),
.PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.INJECTDBITERR (AXI_AR_INJECTDBITERR),
.INJECTSBITERR (AXI_AR_INJECTSBITERR),
.DIN (rach_din),
.DOUT (rach_dout_pkt),
.FULL (rach_full),
.EMPTY (rach_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_AR_PROG_FULL),
.PROG_EMPTY (AXI_AR_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_ar_overflow_i),
.VALID (),
.UNDERFLOW (axi_ar_underflow_i),
.DATA_COUNT (AXI_AR_DATA_COUNT),
.RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT),
.SBITERR (AXI_AR_SBITERR),
.DBITERR (AXI_AR_DBITERR),
.wr_rst_busy (wr_rst_busy_rach),
.rd_rst_busy (rd_rst_busy_rach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;
assign rach_m_axi_arvalid = ~rach_empty;
assign S_AXI_ARREADY = rach_s_axi_arready;
assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;
assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0;
end endgenerate // axi_read_addr_channel
// Register Slice for Read Address Channel
generate if (C_RACH_TYPE == 1) begin : grach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RACH)
)
rach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rach_din),
.S_VALID (S_AXI_ARVALID),
.S_READY (S_AXI_ARREADY),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice
// Register Slice for Read Address Channel for MM Packet FIFO
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (1)
)
reg_slice_mm_pkt_fifo_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (rach_dout_pkt),
.S_VALID (arvalid_pkt),
.S_READY (arready_pkt),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice_mm_pkt_fifo
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid
assign M_AXI_ARVALID = rach_m_axi_arvalid;
assign rach_dout = rach_dout_pkt;
end endgenerate // grach_m_axi_arvalid
generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd
assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;
assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;
assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset) begin
rdch_commited_space <= 0;
end else begin
if(rdch_rd_ok && !accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space-1;
end else if(!rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);
end else if(rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);
end
end
end //Always end
always@(*) begin
rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));
end
assign arvalid_en = (rdch_free_space >= 0)?1:0;
end
endgenerate
generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd
assign arvalid_en = 1;
end
endgenerate
generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel
// Write protection when almost full or prog_full is high
assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID;
// Read protection when almost empty or prog_empty is high
assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY;
assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we;
assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RDCH),
.C_WR_DEPTH (C_WR_DEPTH_RDCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_RDCH),
.C_RD_DEPTH (C_WR_DEPTH_RDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),
.C_USE_ECC (C_USE_ECC_RDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rdch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rdch_wr_en),
.RD_EN (rdch_rd_en),
.PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.INJECTDBITERR (AXI_R_INJECTDBITERR),
.INJECTSBITERR (AXI_R_INJECTSBITERR),
.DIN (rdch_din),
.DOUT (rdch_dout),
.FULL (rdch_full),
.EMPTY (rdch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_R_PROG_FULL),
.PROG_EMPTY (AXI_R_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_r_overflow_i),
.VALID (),
.UNDERFLOW (axi_r_underflow_i),
.DATA_COUNT (AXI_R_DATA_COUNT),
.RD_DATA_COUNT (AXI_R_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_R_WR_DATA_COUNT),
.SBITERR (AXI_R_SBITERR),
.DBITERR (AXI_R_DBITERR),
.wr_rst_busy (wr_rst_busy_rdch),
.rd_rst_busy (rd_rst_busy_rdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rdch_s_axi_rvalid = ~rdch_empty;
assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;
assign S_AXI_RVALID = rdch_s_axi_rvalid;
assign M_AXI_RREADY = rdch_m_axi_rready;
assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0;
assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0;
end endgenerate //axi_read_data_channel
// Register Slice for read Data Channel
generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RDCH)
)
rdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rdch_din),
.S_VALID (M_AXI_RVALID),
.S_READY (M_AXI_RREADY),
// Master side
.M_PAYLOAD_DATA (rdch_dout),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY)
);
end endgenerate // grdch_reg_slice
assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;
assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0;
generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output
assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];
assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];
assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];
assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];
assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];
assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];
assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];
assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR;
assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN;
assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE;
assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;
assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;
assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;
assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;
assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS;
end endgenerate // axi_full_rach_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion
assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];
end endgenerate // axi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion
assign M_AXI_ARREGION = 0;
end endgenerate // naxi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser
assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];
end endgenerate // axi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser
assign M_AXI_ARUSER = 0;
end endgenerate // naxi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid
assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];
end endgenerate // axi_arid
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid
assign M_AXI_ARID = 0;
end endgenerate // naxi_arid
generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output
assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
assign S_AXI_RLAST = rdch_dout[0];
assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA;
assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;
assign rdch_din[0] = M_AXI_RLAST;
end endgenerate // axi_full_rdch_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output
assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];
end endgenerate // axi_full_ruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output
assign S_AXI_RUSER = 0;
end endgenerate // axi_full_nruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid
assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];
end endgenerate // axi_rid
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid
assign S_AXI_RID = 0;
end endgenerate // naxi_rid
generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1
assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT};
assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];
end endgenerate // axi_lite_rach_output
generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1
assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP};
assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
end endgenerate // axi_lite_rdch_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1
assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER;
end endgenerate // grach_din1
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2
assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID;
end endgenerate // grach_din2
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin
assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;
end endgenerate
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1
assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER;
end endgenerate // grdch_din1
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2
assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;
end endgenerate // grdch_din2
//end of axi_read_channel
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf
assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;
end endgenerate // gaxi_comm_uf
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of
assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;
end endgenerate // gaxi_comm_of
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic or Wiring Logic
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Write Address Channel
generate if (C_WACH_TYPE == 2) begin : gwach_pass_through
assign M_AXI_AWID = S_AXI_AWID;
assign M_AXI_AWADDR = S_AXI_AWADDR;
assign M_AXI_AWLEN = S_AXI_AWLEN;
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
assign M_AXI_AWBURST = S_AXI_AWBURST;
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_AWQOS = S_AXI_AWQOS;
assign M_AXI_AWREGION = S_AXI_AWREGION;
assign M_AXI_AWUSER = S_AXI_AWUSER;
assign S_AXI_AWREADY = M_AXI_AWREADY;
assign M_AXI_AWVALID = S_AXI_AWVALID;
end endgenerate // gwach_pass_through;
// Wiring logic for Write Data Channel
generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
assign S_AXI_WREADY = M_AXI_WREADY;
assign M_AXI_WVALID = S_AXI_WVALID;
end endgenerate // gwdch_pass_through;
// Wiring logic for Write Response Channel
generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through
assign S_AXI_BID = M_AXI_BID;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_BUSER = M_AXI_BUSER;
assign M_AXI_BREADY = S_AXI_BREADY;
assign S_AXI_BVALID = M_AXI_BVALID;
end endgenerate // gwrch_pass_through;
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Read Address Channel
generate if (C_RACH_TYPE == 2) begin : grach_pass_through
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARQOS = S_AXI_ARQOS;
assign M_AXI_ARREGION = S_AXI_ARREGION;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign S_AXI_ARREADY = M_AXI_ARREADY;
assign M_AXI_ARVALID = S_AXI_ARVALID;
end endgenerate // grach_pass_through;
// Wiring logic for Read Data Channel
generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
end endgenerate // grdch_pass_through;
// Wiring logic for AXI Streaming
generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through
assign M_AXIS_TDATA = S_AXIS_TDATA;
assign M_AXIS_TSTRB = S_AXIS_TSTRB;
assign M_AXIS_TKEEP = S_AXIS_TKEEP;
assign M_AXIS_TID = S_AXIS_TID;
assign M_AXIS_TDEST = S_AXIS_TDEST;
assign M_AXIS_TUSER = S_AXIS_TUSER;
assign M_AXIS_TLAST = S_AXIS_TLAST;
assign S_AXIS_TREADY = M_AXIS_TREADY;
assign M_AXIS_TVALID = S_AXIS_TVALID;
end endgenerate // gaxis_pass_through;
endmodule //fifo_generator_v13_1_3
/*******************************************************************************
* Declaration of top-level module for Conventional FIFO
******************************************************************************/
module fifo_generator_v13_1_3_CONV_VER
#(
parameter C_COMMON_CLOCK = 0,
parameter C_INTERFACE_TYPE = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "virtex7", //Not allowed in Verilog model
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
parameter C_AXI_TYPE = 0
)
(
input BACKUP,
input BACKUP_MARKER,
input CLK,
input RST,
input SRST,
input WR_CLK,
input WR_RST,
input RD_CLK,
input RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input WR_EN,
input RD_EN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input INT_CLK,
input INJECTDBITERR,
input INJECTSBITERR,
output [C_DOUT_WIDTH-1:0] DOUT,
output FULL,
output ALMOST_FULL,
output WR_ACK,
output OVERFLOW,
output EMPTY,
output ALMOST_EMPTY,
output VALID,
output UNDERFLOW,
output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_FULL,
output PROG_EMPTY,
output SBITERR,
output DBITERR,
output wr_rst_busy_o,
output wr_rst_busy,
output rd_rst_busy,
output wr_rst_i_out,
output rd_rst_i_out
);
/*
******************************************************************************
* Definition of Parameters
******************************************************************************
* C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
* C_COUNT_TYPE : *not used
* C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
* C_DEFAULT_VALUE : *not used
* C_DIN_WIDTH : Width of DIN bus
* C_DOUT_RST_VAL : Reset value of DOUT
* C_DOUT_WIDTH : Width of DOUT bus
* C_ENABLE_RLOCS : *not used
* C_FAMILY : not used in bhv model
* C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
* C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
* C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
* C_HAS_BACKUP : *not used
* C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
* C_HAS_INT_CLK : not used in bhv model
* C_HAS_MEMINIT_FILE : *not used
* C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
* C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
* C_HAS_RD_RST : *not used
* C_HAS_RST : 1=Core has Async Rst
* C_HAS_SRST : 1=Core has Sync Rst
* C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
* C_HAS_VALID : 1=Core has VALID flag
* C_HAS_WR_ACK : 1=Core has WR_ACK flag
* C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
* C_HAS_WR_RST : *not used
* C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
* 1=Common-Clock ShiftRam
* 2=Indep. Clocks Bram/Dram
* 3=Virtex-4 Built-in
* 4=Virtex-5 Built-in
* C_INIT_WR_PNTR_VAL : *not used
* C_MEMORY_TYPE : 1=Block RAM
* 2=Distributed RAM
* 3=Shift RAM
* 4=Built-in FIFO
* C_MIF_FILE_NAME : *not used
* C_OPTIMIZATION_MODE : *not used
* C_OVERFLOW_LOW : 1=OVERFLOW active low
* C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
* C_PRELOAD_REGS : 1=Use output registers
* C_PRIM_FIFO_TYPE : not used in bhv model
* C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
* C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
* C_PROG_EMPTY_TYPE : 0=No programmable empty
* 1=Single prog empty thresh constant
* 2=Multiple prog empty thresh constants
* 3=Single prog empty thresh input
* 4=Multiple prog empty thresh inputs
* C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
* C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
* C_PROG_FULL_TYPE : 0=No prog full
* 1=Single prog full thresh constant
* 2=Multiple prog full thresh constants
* 3=Single prog full thresh input
* 4=Multiple prog full thresh inputs
* C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
* C_RD_DEPTH : Depth of read interface (2^N)
* C_RD_FREQ : not used in bhv model
* C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
* C_UNDERFLOW_LOW : 1=UNDERFLOW active low
* C_USE_DOUT_RST : 1=Resets DOUT on RST
* C_USE_ECC : Used for error injection purpose
* C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
* C_USE_FIFO16_FLAGS : not used in bhv model
* C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
* C_VALID_LOW : 1=VALID active low
* C_WR_ACK_LOW : 1=WR_ACK active low
* C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
* C_WR_DEPTH : Depth of write interface (2^N)
* C_WR_FREQ : not used in bhv model
* C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
* C_WR_RESPONSE_LATENCY : *not used
* C_MSGON_VAL : *not used by bhv model
* C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST
* 1 = Use RST
* C_ERROR_INJECTION_TYPE : 0 = No error injection
* 1 = Single bit error injection only
* 2 = Double bit error injection only
* 3 = Single and double bit error injection
******************************************************************************
* Definition of Ports
******************************************************************************
* BACKUP : Not used
* BACKUP_MARKER: Not used
* CLK : Clock
* DIN : Input data bus
* PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
* PROG_FULL_THRESH : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
* RD_CLK : Read Domain Clock
* RD_EN : Read enable
* RD_RST : Read Reset
* RST : Asynchronous Reset
* SRST : Synchronous Reset
* WR_CLK : Write Domain Clock
* WR_EN : Write enable
* WR_RST : Write Reset
* INT_CLK : Internal Clock
* INJECTSBITERR: Inject Signle bit error
* INJECTDBITERR: Inject Double bit error
* ALMOST_EMPTY : One word remaining in FIFO
* ALMOST_FULL : One empty space remaining in FIFO
* DATA_COUNT : Number of data words in fifo( synchronous to CLK)
* DOUT : Output data bus
* EMPTY : Empty flag
* FULL : Full flag
* OVERFLOW : Last write rejected
* PROG_EMPTY : Programmable Empty Flag
* PROG_FULL : Programmable Full Flag
* RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
* UNDERFLOW : Last read rejected
* VALID : Last read acknowledged, DOUT bus VALID
* WR_ACK : Last write acknowledged
* WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
* SBITERR : Single Bit ECC Error Detected
* DBITERR : Double Bit ECC Error Detected
******************************************************************************
*/
//----------------------------------------------------------------------------
//- Internal Signals for delayed input signals
//- All the input signals except Clock are delayed by 100 ps and then given to
//- the models.
//----------------------------------------------------------------------------
reg rst_delayed ;
reg empty_fb ;
reg srst_delayed ;
reg wr_rst_delayed ;
reg rd_rst_delayed ;
reg wr_en_delayed ;
reg rd_en_delayed ;
reg [C_DIN_WIDTH-1:0] din_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ;
reg injectdbiterr_delayed ;
reg injectsbiterr_delayed ;
wire empty_p0_out;
always @* rst_delayed <= #`TCQ RST ;
always @* empty_fb <= #`TCQ empty_p0_out ;
always @* srst_delayed <= #`TCQ SRST ;
always @* wr_rst_delayed <= #`TCQ WR_RST ;
always @* rd_rst_delayed <= #`TCQ RD_RST ;
always @* din_delayed <= #`TCQ DIN ;
always @* wr_en_delayed <= #`TCQ WR_EN ;
always @* rd_en_delayed <= #`TCQ RD_EN ;
always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ;
always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ;
always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ;
always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ;
always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ;
always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ;
always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ;
always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ;
/*****************************************************************************
* Derived parameters
****************************************************************************/
//There are 2 Verilog behavioral models
// 0 = Common-Clock FIFO/ShiftRam FIFO
// 1 = Independent Clocks FIFO
// 2 = Low Latency Synchronous FIFO
// 3 = Low Latency Asynchronous FIFO
localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :
(C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//Internal reset signals
reg rd_rst_asreg = 0;
wire rd_rst_asreg_d1;
wire rd_rst_asreg_d2;
reg rd_rst_asreg_d3 = 0;
reg rd_rst_reg = 0;
wire rd_rst_comb;
reg wr_rst_d0 = 0;
reg wr_rst_d1 = 0;
reg wr_rst_d2 = 0;
reg rd_rst_d0 = 0;
reg rd_rst_d1 = 0;
reg rd_rst_d2 = 0;
reg rd_rst_d3 = 0;
reg wrrst_done = 0;
reg rdrst_done = 0;
reg wr_rst_asreg = 0;
wire wr_rst_asreg_d1;
wire wr_rst_asreg_d2;
reg wr_rst_asreg_d3 = 0;
reg rd_rst_wr_d0 = 0;
reg rd_rst_wr_d1 = 0;
reg rd_rst_wr_d2 = 0;
reg wr_rst_reg = 0;
reg rst_active_i = 1'b1;
reg rst_delayed_d1 = 1'b1;
reg rst_delayed_d2 = 1'b1;
wire wr_rst_comb;
wire wr_rst_i;
wire rd_rst_i;
wire rst_i;
//Internal reset signals
reg rst_asreg = 0;
reg srst_asreg = 0;
wire rst_asreg_d1;
wire rst_asreg_d2;
reg srst_asreg_d1 = 0;
reg srst_asreg_d2 = 0;
reg rst_reg = 0;
reg srst_reg = 0;
wire rst_comb;
wire srst_comb;
reg rst_full_gen_i = 0;
reg rst_full_ff_i = 0;
reg [2:0] sckt_ff0_bsy_o_i = {3{1'b0}};
wire RD_CLK_P0_IN;
wire RST_P0_IN;
wire RD_EN_FIFO_IN;
wire RD_EN_P0_IN;
wire ALMOST_EMPTY_FIFO_OUT;
wire ALMOST_FULL_FIFO_OUT;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT;
wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT;
wire EMPTY_FIFO_OUT;
wire fifo_empty_fb;
wire FULL_FIFO_OUT;
wire OVERFLOW_FIFO_OUT;
wire PROG_EMPTY_FIFO_OUT;
wire PROG_FULL_FIFO_OUT;
wire VALID_FIFO_OUT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT;
wire UNDERFLOW_FIFO_OUT;
wire WR_ACK_FIFO_OUT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT;
//***************************************************************************
// Internal Signals
// The core uses either the internal_ wires or the preload0_ wires depending
// on whether the core uses Preload0 or not.
// When using preload0, the internal signals connect the internal core to
// the preload logic, and the external core's interfaces are tied to the
// preload0 signals from the preload logic.
//***************************************************************************
wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT;
wire VALID_P0_OUT;
wire EMPTY_P0_OUT;
wire ALMOSTEMPTY_P0_OUT;
reg EMPTY_P0_OUT_Q;
reg ALMOSTEMPTY_P0_OUT_Q;
wire UNDERFLOW_P0_OUT;
wire RDEN_P0_OUT;
wire [C_DOUT_WIDTH-1:0] DATA_P0_IN;
wire EMPTY_P0_IN;
reg [31:0] DATA_COUNT_FWFT;
reg SS_FWFT_WR ;
reg SS_FWFT_RD ;
wire sbiterr_fifo_out;
wire dbiterr_fifo_out;
wire inject_sbit_err;
wire inject_dbit_err;
wire safety_ckt_wr_rst;
wire safety_ckt_rd_rst;
reg sckt_wr_rst_i_q = 1'b0;
wire w_fab_read_data_valid_i;
wire w_read_data_valid_i;
wire w_ram_valid_i;
// Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.
assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectsbiterr_delayed : 0;
assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectdbiterr_delayed : 0;
assign wr_rst_i_out = wr_rst_i;
assign rd_rst_i_out = rd_rst_i;
assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];
generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o
wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;
always @ (posedge clk_i)
sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy};
end endgenerate
// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL
// parameter (1=Independent Clocks, 0=Common Clock)
localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;
generate
case (C_VERILOG_IMPL)
0 : begin : block1
//Common Clock Behavioral Model
fifo_generator_v13_1_3_bhv_ver_ss
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ss
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.CLK (CLK),
.RST (rst_i),
.SRST (srst_delayed),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.USER_EMPTY_FB (empty_fb),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.DATA_COUNT (DATA_COUNT_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
1 : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.fab_read_data_valid_i (w_fab_read_data_valid_i),
.read_data_valid_i (w_read_data_valid_i),
.ram_valid_i (w_ram_valid_i),
.DBITERR (dbiterr_fifo_out)
);
end
2 : begin : ll_afifo_inst
fifo_generator_v13_1_3_beh_ver_ll_afifo
#(
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ll_afifo
(
.DIN (din_delayed),
.RD_CLK (RD_CLK),
.RD_EN (rd_en_delayed),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.WR_CLK (WR_CLK),
.WR_EN (wr_en_delayed),
.DOUT (DOUT),
.EMPTY (EMPTY),
.FULL (FULL)
);
end
default : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
endcase
endgenerate
//**************************************************************************
// Connect Internal Signals
// (Signals labeled internal_*)
// In the normal case, these signals tie directly to the FIFO's inputs and
// outputs.
// In the case of Preload Latency 0 or 1, there are intermediate
// signals between the internal FIFO and the preload logic.
//**************************************************************************
//***********************************************
// If First-Word Fall-Through, instantiate
// the preload0 (FWFT) module
//***********************************************
wire rd_en_to_fwft_fifo;
wire sbiterr_fwft;
wire dbiterr_fwft;
wire [C_DOUT_WIDTH-1:0] dout_fwft;
wire empty_fwft;
wire rd_en_fifo_in;
wire stage2_reg_en_i;
wire [1:0] valid_stages_i;
wire rst_fwft;
//wire empty_p0_out;
reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0;
localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;
assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
fgpl0
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (RST_P0_IN),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (RD_EN_P0_IN),
.FIFOEMPTY (EMPTY_P0_IN),
.FIFODATA (DATA_P0_IN),
.FIFOSBITERR (sbiterr_fifo_out),
.FIFODBITERR (dbiterr_fifo_out),
// Output
.USERDATA (dout_fwft),
.USERVALID (VALID_P0_OUT),
.USEREMPTY (empty_fwft),
.USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT),
.USERUNDERFLOW (UNDERFLOW_P0_OUT),
.RAMVALID (),
.FIFORDEN (rd_en_fifo_in),
.USERSBITERR (sbiterr_fwft),
.USERDBITERR (dbiterr_fwft),
.STAGE2_REG_EN (stage2_reg_en_i),
.fab_read_data_valid_i_o (w_fab_read_data_valid_i),
.read_data_valid_i_o (w_read_data_valid_i),
.ram_valid_i_o (w_ram_valid_i),
.VALID_STAGES (valid_stages_i)
);
//***********************************************
// Connect inputs to preload (FWFT) module
//***********************************************
//Connect the RD_CLK of the Preload (FWFT) module to CLK if we
// have a common-clock FIFO, or RD_CLK if we have an
// independent clock FIFO
assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);
assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
assign EMPTY_P0_IN = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;
assign DATA_P0_IN = DOUT_FIFO_OUT;
//***********************************************
// Connect outputs from preload (FWFT) module
//***********************************************
assign VALID = VALID_P0_OUT ;
assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT;
assign UNDERFLOW = UNDERFLOW_P0_OUT ;
assign RD_EN_FIFO_IN = rd_en_fifo_in;
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:
(C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] :
DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
EMPTY_P0_OUT_Q <= 1;
ALMOSTEMPTY_P0_OUT_Q <= 1;
end else begin
EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out;
// EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT;
ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;
end
end //always
//***********************************************
// logic for common-clock data count when FWFT is selected
//***********************************************
initial begin
SS_FWFT_RD = 1'b0;
DATA_COUNT_FWFT = 0 ;
SS_FWFT_WR = 1'b0 ;
end //initial
//***********************************************
// common-clock data count is implemented as an
// up-down counter. SS_FWFT_WR and SS_FWFT_RD
// are the up/down enables for the counter.
//***********************************************
always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin
if (C_VALID_LOW == 1) begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;
end else begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;
end
SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ;
end
//***********************************************
// common-clock data count is implemented as an
// up-down counter for FWFT. This always block
// calculates the counter.
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
DATA_COUNT_FWFT <= 0;
end else begin
//if (srst_delayed && (C_HAS_SRST == 1) ) begin
if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin
DATA_COUNT_FWFT <= #`TCQ 0;
end else begin
case ( {SS_FWFT_WR, SS_FWFT_RD})
2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;
2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;
2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
endcase
end //if SRST
end //IF RST
end //always
end endgenerate // : block2
// AXI Streaming Packet FIFO
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0;
reg partial_packet = 0;
reg stage1_eop_d1 = 0;
reg rd_en_fifo_in_d1 = 0;
reg eop_at_stage2 = 0;
reg ram_pkt_empty = 0;
reg ram_pkt_empty_d1 = 0;
wire [C_DOUT_WIDTH-1:0] dout_p0_out;
wire packet_empty_wr;
wire wr_rst_fwft_pkt_fifo;
wire dummy_wr_eop;
wire ram_wr_en_pkt_fifo;
wire wr_eop;
wire ram_rd_en_compare;
wire stage1_eop;
wire pkt_ready_to_read;
wire rd_en_2_stage2;
// Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
// When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
// When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
// write packet count
generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
partial_packet <= 1'b0;
else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy)
partial_packet <= #`TCQ 1'b0;
else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))
partial_packet <= #`TCQ 1'b1;
else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)
partial_packet <= #`TCQ 1'b0;
end
end
end endgenerate // gdummy_wr_eop
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin // gpkt_fifo_fwft
assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;
assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);
assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
stage1_eop_d1 <= 1'b0;
rd_en_fifo_in_d1 <= 1'b0;
end else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
stage1_eop_d1 <= #`TCQ 1'b0;
rd_en_fifo_in_d1 <= #`TCQ 1'b0;
end else begin
stage1_eop_d1 <= #`TCQ stage1_eop;
rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;
end
end
end
assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;
assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);
assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);
assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (2) // Enable low latency fwft logic
)
pkt_fifo_fwft
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (rst_fwft),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (rd_en_delayed),
.FIFOEMPTY (pkt_ready_to_read),
.FIFODATA (dout_fwft),
.FIFOSBITERR (sbiterr_fwft),
.FIFODBITERR (dbiterr_fwft),
// Output
.USERDATA (dout_p0_out),
.USERVALID (),
.USEREMPTY (empty_p0_out),
.USERALMOSTEMPTY (),
.USERUNDERFLOW (),
.RAMVALID (),
.FIFORDEN (rd_en_2_stage2),
.USERSBITERR (SBITERR),
.USERDBITERR (DBITERR),
.STAGE2_REG_EN (),
.VALID_STAGES ()
);
assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));
assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
eop_at_stage2 <= 1'b0;
else if (stage2_reg_en_i)
eop_at_stage2 <= #`TCQ stage1_eop;
end
//---------------------------------------------------------------------------
// Write and Read Packet Count
//---------------------------------------------------------------------------
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count <= 0;
else if (srst_delayed | wr_rst_busy | rd_rst_busy)
wr_pkt_count <= #`TCQ 0;
else if (wr_eop)
wr_pkt_count <= #`TCQ wr_pkt_count + 1;
end
end endgenerate // gpkt_fifo_fwft
assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;
assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
rd_pkt_count <= 0;
rd_pkt_count_plus1 <= 1;
end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
rd_pkt_count <= #`TCQ 0;
rd_pkt_count_plus1 <= #`TCQ 1;
end else if (stage2_reg_en_i && stage1_eop) begin
rd_pkt_count <= #`TCQ rd_pkt_count + 1;
rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;
end
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (SRST | wr_rst_busy | rd_rst_busy) begin
ram_pkt_empty <= #`TCQ 1'b1;
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
end endgenerate //grss_pkt_cnt
localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;
reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0;
wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt
// Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count_b2g <= 0;
else
wr_pkt_count_b2g <= #`TCQ wr_pkt_count;
end
// Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
wr_pkt_count_q <= 0;
else
wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};
end
always @* begin
if (stage1_eop)
rd_pkt_count <= rd_pkt_count_reg + 1;
else
rd_pkt_count <= rd_pkt_count_reg;
end
assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
rd_pkt_count_reg <= 0;
else if (rd_en_fifo_in)
rd_pkt_count_reg <= #`TCQ rd_pkt_count;
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (rd_pkt_count != wr_pkt_count_rd) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
// Synchronize the empty in write domain
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
pkt_empty_sync <= 'b1;
else
pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};
end
end endgenerate //gras_pkt_cnt
generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO
//***********************************************
// If NOT First-Word Fall-Through, wire the outputs
// of the internal _ss or _as FIFO directly to the
// output, and do not instantiate the preload0
// module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VALID = VALID_FIFO_OUT;
assign EMPTY = EMPTY_FIFO_OUT;
assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT;
assign EMPTY_P0_IN = 0;
assign UNDERFLOW = UNDERFLOW_FIFO_OUT;
assign DATA_COUNT = DATA_COUNT_FIFO_OUT;
assign SBITERR = sbiterr_fifo_out;
assign DBITERR = dbiterr_fifo_out;
end endgenerate // STD_FIFO
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO
assign empty_p0_out = empty_fwft;
assign SBITERR = sbiterr_fwft;
assign DBITERR = dbiterr_fwft;
assign DOUT = dout_fwft;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
end endgenerate // NO_PKT_FIFO
//***********************************************
// Connect user flags to internal signals
//***********************************************
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);
end //block_ic
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30_both
endgenerate
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));
end //block_ic_both
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3_both
endgenerate
//If we are not using extra logic for the FWFT data count,
//then connect RD_DATA_COUNT to the RD_DATA_COUNT from the
//internal FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal
//FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==1) begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
else begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Connect other flags to the internal FIFO instance
assign FULL = FULL_FIFO_OUT;
assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT;
assign WR_ACK = WR_ACK_FIFO_OUT;
assign OVERFLOW = OVERFLOW_FIFO_OUT;
assign PROG_FULL = PROG_FULL_FIFO_OUT;
assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT;
/**************************************************************************
* find_log2
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// if an asynchronous FIFO has been selected, display a message that the FIFO
// will not be cycle-accurate in simulation
initial begin
if (C_IMPLEMENTATION_TYPE == 2) begin
$display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.");
end else if (C_MEMORY_TYPE == 4) begin
$display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.");
$finish;
end
if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin
$display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.");
$finish;
end
if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin
$display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.");
$finish;
end
if (C_USE_ECC == 1) begin
if (C_DIN_WIDTH != C_DOUT_WIDTH) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.");
$finish;
end
if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.");
$finish;
end
end
end //initial
/**************************************************************************
* Internal reset logic
**************************************************************************/
assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0;
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0;
assign rst_i = C_HAS_RST ? rst_reg : 0;
wire rst_2_sync;
wire rst_2_sync_safety = (C_ENABLE_RST_SYNC == 1) ? rst_delayed : RD_RST;
wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;
wire clk_2_sync_safety = (C_COMMON_CLOCK == 1) ? CLK : RD_CLK;
localparam RST_SYNC_STAGES = (C_EN_SAFETY_CKT == 0) ? C_SYNCHRONIZER_STAGE :
(C_COMMON_CLOCK == 1) ? 3 : C_SYNCHRONIZER_STAGE+2;
reg [RST_SYNC_STAGES-1:0] wrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] arst_sync_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_wr = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_ext = {RST_SYNC_STAGES{1'b0}};
reg [1:0] wrst_cc = {2{1'b0}};
reg [1:0] rrst_cc = {2{1'b0}};
generate
if (C_EN_SAFETY_CKT == 1 && C_INTERFACE_TYPE == 0) begin : grst_safety_ckt
reg[1:0] rst_d1_safety =1;
reg[1:0] rst_d2_safety =1;
reg[1:0] rst_d3_safety =1;
reg[1:0] rst_d4_safety =1;
reg[1:0] rst_d5_safety =1;
reg[1:0] rst_d6_safety =1;
reg[1:0] rst_d7_safety =1;
always@(posedge rst_2_sync_safety or posedge clk_2_sync_safety) begin : prst
if (rst_2_sync_safety == 1'b1) begin
rst_d1_safety <= 1'b1;
rst_d2_safety <= 1'b1;
rst_d3_safety <= 1'b1;
rst_d4_safety <= 1'b1;
rst_d5_safety <= 1'b1;
rst_d6_safety <= 1'b1;
rst_d7_safety <= 1'b1;
end
else begin
rst_d1_safety <= #`TCQ 1'b0;
rst_d2_safety <= #`TCQ rst_d1_safety;
rst_d3_safety <= #`TCQ rst_d2_safety;
rst_d4_safety <= #`TCQ rst_d3_safety;
rst_d5_safety <= #`TCQ rst_d4_safety;
rst_d6_safety <= #`TCQ rst_d5_safety;
rst_d7_safety <= #`TCQ rst_d6_safety;
end //if
end //prst
always@(posedge rst_d7_safety or posedge WR_EN) begin : assert_safety
if(rst_d7_safety == 1 && WR_EN == 1) begin
$display("WARNING:A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled.");
end //if
end //always
end // grst_safety_ckt
endgenerate
// if (C_EN_SAFET_CKT == 1)
// assertion:the reset shud be atleast 3 cycles wide.
generate
reg safety_ckt_wr_rst_i = 1'b0;
if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync
always @* begin
wr_rst_reg <= wr_rst_delayed;
rd_rst_reg <= rd_rst_delayed;
rst_reg <= 1'b0;
srst_reg <= 1'b0;
end
assign rst_2_sync = wr_rst_delayed;
assign wr_rst_busy = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
// end : gnrst_sync
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : g7s_ic_rst
reg fifo_wrst_done = 1'b0;
reg fifo_rrst_done = 1'b0;
reg sckt_wrst_i = 1'b0;
reg sckt_wrst_i_q = 1'b0;
reg rd_rst_active = 1'b0;
reg rd_rst_middle = 1'b0;
reg sckt_rd_rst_d1 = 1'b0;
reg [1:0] rst_delayed_ic_w = 2'h0;
wire rst_delayed_ic_w_i;
reg [1:0] rst_delayed_ic_r = 2'h0;
wire rst_delayed_ic_r_i;
wire arst_sync_rst;
wire fifo_rst_done;
wire fifo_rst_active;
assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg;
assign rd_rst_comb = C_EN_SAFETY_CKT ? (!rd_rst_asreg_d2 && rd_rst_asreg) || rd_rst_active : !rd_rst_asreg_d2 && rd_rst_asreg;
assign rst_2_sync = rst_delayed_ic_w_i;
assign arst_sync_rst = arst_sync_q[RST_SYNC_STAGES-1];
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | fifo_rst_active : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? safety_ckt_rd_rst : 1'b0;
assign fifo_rst_done = fifo_wrst_done & fifo_rrst_done;
assign fifo_rst_active = sckt_wrst_i | wrst_ext[RST_SYNC_STAGES-1] | rrst_wr[RST_SYNC_STAGES-1];
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_w <= 2'b11;
else
rst_delayed_ic_w <= #`TCQ {rst_delayed_ic_w[0],1'b0};
end
assign rst_delayed_ic_w_i = rst_delayed_ic_w[1];
always @(posedge RD_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_r <= 2'b11;
else
rst_delayed_ic_r <= #`TCQ {rst_delayed_ic_r[0],1'b0};
end
assign rst_delayed_ic_r_i = rst_delayed_ic_r[1];
always @(posedge WR_CLK) begin
sckt_wrst_i_q <= #`TCQ sckt_wrst_i;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ sckt_wrst_i | wr_rst_busy | sckt_wr_rst_i_q;
if (arst_sync_rst && ~fifo_rst_active)
sckt_wrst_i <= #`TCQ 1'b1;
else if (sckt_wrst_i && fifo_rst_done)
sckt_wrst_i <= #`TCQ 1'b0;
else
sckt_wrst_i <= #`TCQ sckt_wrst_i;
if (rrst_wr[RST_SYNC_STAGES-2] & ~rrst_wr[RST_SYNC_STAGES-1])
fifo_rrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_rrst_done <= #`TCQ 1'b0;
else
fifo_rrst_done <= #`TCQ fifo_rrst_done;
if (wrst_ext[RST_SYNC_STAGES-2] & ~wrst_ext[RST_SYNC_STAGES-1])
fifo_wrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_wrst_done <= #`TCQ 1'b0;
else
fifo_wrst_done <= #`TCQ fifo_wrst_done;
end
always @(posedge WR_CLK or posedge rst_delayed_ic_w_i) begin
if (rst_delayed_ic_w_i == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],wr_rst_asreg};
wrst_ext <= #`TCQ {wrst_ext[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_wr <= #`TCQ {rrst_wr[RST_SYNC_STAGES-2:0],safety_ckt_rd_rst};
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_ic_w_i};
end
assign wr_rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign wr_rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge WR_CLK or posedge wr_rst_comb) begin
if (wr_rst_comb == 1'b1) begin
wr_rst_reg <= 1'b1;
end else begin
wr_rst_reg <= #`TCQ 1'b0;
end
end
always @(posedge RD_CLK or posedge rst_delayed_ic_r_i) begin
if (rst_delayed_ic_r_i == 1'b1) begin
rd_rst_asreg <= 1'b1;
end else begin
if (rd_rst_asreg_d1 == 1'b1) begin
rd_rst_asreg <= #`TCQ 1'b0;
end else begin
rd_rst_asreg <= #`TCQ rd_rst_asreg;
end
end
end
always @(posedge RD_CLK) begin
rrst_reg <= #`TCQ {rrst_reg[RST_SYNC_STAGES-2:0],rd_rst_asreg};
rrst_q <= #`TCQ {rrst_q[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_cc <= #`TCQ {rrst_cc[0],rd_rst_asreg_d2};
sckt_rd_rst_d1 <= #`TCQ safety_ckt_rd_rst;
if (!rd_rst_middle && rrst_reg[1] && !rrst_reg[2]) begin
rd_rst_active <= #`TCQ 1'b1;
rd_rst_middle <= #`TCQ 1'b1;
end else if (safety_ckt_rd_rst)
rd_rst_active <= #`TCQ 1'b0;
else if (sckt_rd_rst_d1 && !safety_ckt_rd_rst)
rd_rst_middle <= #`TCQ 1'b0;
end
assign rd_rst_asreg_d1 = rrst_reg[RST_SYNC_STAGES-2];
assign rd_rst_asreg_d2 = C_EN_SAFETY_CKT ? rrst_reg[RST_SYNC_STAGES-1] : rrst_reg[1];
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rrst_q[2] : 1'b0;
always @(posedge RD_CLK or posedge rd_rst_comb) begin
if (rd_rst_comb == 1'b1) begin
rd_rst_reg <= 1'b1;
end else begin
rd_rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_ic_rst
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_rst
reg [1:0] rst_delayed_cc = 2'h0;
wire rst_delayed_cc_i;
assign rst_comb = !rst_asreg_d2 && rst_asreg;
assign rst_2_sync = rst_delayed_cc_i;
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | wrst_cc[1] : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? arst_sync_q[1] | arst_sync_q[RST_SYNC_STAGES-1] | wrst_cc[1] : 1'b0;
always @(posedge CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1)
rst_delayed_cc <= 2'b11;
else
rst_delayed_cc <= #`TCQ {rst_delayed_cc,1'b0};
end
assign rst_delayed_cc_i = rst_delayed_cc[1];
always @(posedge CLK or posedge rst_delayed_cc_i) begin
if (rst_delayed_cc_i == 1'b1) begin
rst_asreg <= 1'b1;
end else begin
if (rst_asreg_d1 == 1'b1) begin
rst_asreg <= #`TCQ 1'b0;
end else begin
rst_asreg <= #`TCQ rst_asreg;
end
end
end
always @(posedge CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],rst_asreg};
wrst_cc <= #`TCQ {wrst_cc[0],arst_sync_q[RST_SYNC_STAGES-1]};
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ wrst_cc[1] | wr_rst_busy | sckt_wr_rst_i_q;
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_cc_i};
end
assign rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge CLK or posedge rst_comb) begin
if (rst_comb == 1'b1) begin
rst_reg <= 1'b1;
end else begin
rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_cc_rst
end else if (IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst
assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;
assign rd_rst_busy = rst_reg;
assign rst_2_sync = srst_delayed;
always @* rst_full_ff_i <= rst_reg;
always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
always @(posedge CLK) begin
rst_delayed_d1 <= #`TCQ srst_delayed;
rst_delayed_d2 <= #`TCQ rst_delayed_d1;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
if (rst_reg || rst_delayed_d2) begin
rst_active_i <= #`TCQ 1'b1;
end else begin
rst_active_i <= #`TCQ rst_reg;
end
end
always @(posedge CLK) begin
if (~rst_reg && srst_delayed) begin
rst_reg <= #`TCQ 1'b1;
end else if (rst_reg) begin
rst_reg <= #`TCQ 1'b0;
end else begin
rst_reg <= #`TCQ rst_reg;
end
end
// end : g8s_cc_rst
end else begin
assign wr_rst_busy = 1'b0;
assign rd_rst_busy = 1'b0;
assign safety_ckt_wr_rst = 1'b0;
assign safety_ckt_rd_rst = 1'b0;
end
endgenerate
generate
if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1
// RST_FULL_GEN replaces the reset falling edge detection used to de-assert
// FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
// RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
// PROG_FULL
reg rst_d1 = 1'b0;
reg rst_d2 = 1'b0;
reg rst_d3 = 1'b0;
reg rst_d4 = 1'b0;
reg rst_d5 = 1'b0;
always @ (posedge rst_2_sync or posedge clk_2_sync) begin
if (rst_2_sync) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
rst_d3 <= 1'b1;
rst_d4 <= 1'b1;
end else begin
if (srst_delayed) begin
rst_d1 <= #`TCQ 1'b1;
rst_d2 <= #`TCQ 1'b1;
rst_d3 <= #`TCQ 1'b1;
rst_d4 <= #`TCQ 1'b1;
end else begin
rst_d1 <= #`TCQ wr_rst_busy;
rst_d2 <= #`TCQ rst_d1;
rst_d3 <= #`TCQ rst_d2 | safety_ckt_wr_rst;
rst_d4 <= #`TCQ rst_d3;
end
end
end
always @* rst_full_ff_i <= (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ;
always @* rst_full_gen_i <= rst_d3;
end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full
always @* rst_full_ff_i <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
end
endgenerate // grstd1
endmodule //fifo_generator_v13_1_3_conv_ver
module fifo_generator_v13_1_3_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0;
else
DOUT <= #`TCQ DIN;
end
endmodule // fifo_generator_v13_1_3_sync_stage
/*******************************************************************************
* Declaration of Independent-Clocks FIFO Module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_as
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input SAFETY_CKT_WR_RST,
input SAFETY_CKT_RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_CLK,
input RD_EN,
input RD_EN_USER,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input USER_EMPTY_FB,
input fab_read_data_valid_i,
input read_data_valid_i,
input ram_valid_i,
output reg ALMOST_EMPTY = 1'b1,
output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL,
output [C_DOUT_WIDTH-1:0] DOUT,
output reg EMPTY = 1'b1,
output reg EMPTY_FB = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL,
output OVERFLOW,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output UNDERFLOW,
output WR_ACK,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;
// Array that holds the error injection type (single/double bit error) on
// a specific write operation, which is returned on read to corrupt the
// output data.
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
//The amount of data stored in the FIFO at any time is given
// by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK
// domain.
//num_wr_bits is calculated by considering the total words in the FIFO,
// and the state of the read pointer (which may not have yet crossed clock
// domains.)
//num_rd_bits is calculated by considering the total words in the FIFO,
// and the state of the write pointer (which may not have yet crossed clock
// domains.)
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
wire wr_rst_i = WR_RST;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire rd_rst_i = RD_RST;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
// Delayed ram_rd_en is needed only for STD Embedded register option
generate
if (C_PRELOAD_LATENCY == 2) begin : grd_d
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
end
endgenerate
generate
if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
endgenerate
// Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;
end else begin : rdl // Read depth lesser than or equal to write depth
assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
endgenerate
// Generate Empty and Almost Empty
// ram_rd_en used to determine EMPTY should depend on the EMPTY.
assign ram_rd_en = RD_EN & !EMPTY;
assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));
assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));
// Register Empty and Almost Empty
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin
EMPTY <= 1'b1;
ALMOST_EMPTY <= 1'b1;
rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};
end else begin
rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};
if (empty_int)
EMPTY <= #`TCQ 1'b1;
else
EMPTY <= #`TCQ 1'b0;
if (!EMPTY) begin
if (almost_empty_int)
ALMOST_EMPTY <= #`TCQ 1'b1;
else
ALMOST_EMPTY <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)
EMPTY_FB <= #`TCQ 1'b1;
else if (empty_int)
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ 1'b0;
end // rd_rst_i
end // always
// Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;
end else begin : wdl // Write depth lesser than or equal to read depth
assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end
endgenerate
// Generate FULL and ALMOST_FULL
// ram_wr_en used to determine FULL should depend on the FULL.
assign ram_wr_en = WR_EN & !FULL;
assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));
assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));
// Register FULL and ALMOST_FULL Empty
always @ (posedge WR_CLK or posedge RST_FULL_FF)
begin
if (RST_FULL_FF) begin
FULL <= C_FULL_FLAGS_RST_VAL;
ALMOST_FULL <= C_FULL_FLAGS_RST_VAL;
end else begin
if (full_int) begin
FULL <= #`TCQ 1'b1;
end else begin
FULL <= #`TCQ 1'b0;
end
if (RST_FULL_GEN) begin
ALMOST_FULL <= #`TCQ 1'b0;
end else if (!FULL) begin
if (almost_full_int)
ALMOST_FULL <= #`TCQ 1'b1;
else
ALMOST_FULL <= #`TCQ 1'b0;
end
end // wr_rst_i
end // always
always @ (posedge WR_CLK or posedge wr_rst_i)
begin
if (wr_rst_i) begin
wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};
end else begin
wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};
end // wr_rst_i
end // always
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
stage1_valid <= 0;
stage2_valid <= 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//Pointers passed into opposite clock domain
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_EMPTY.
wire [31:0] num_read_words_pe =
num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_FULL.
wire [31:0] num_write_words_pf =
num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/***************************************************************************
* Internal registers and wires
**************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire valid_i;
wire valid_out1;
wire valid_out2;
wire valid_out;
wire underflow_i;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
reg valid_d1 = 0;
reg valid_d2 = 0;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/****************************************************************************
* Function Declarations
***************************************************************************/
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
/***********************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_d2 = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_CLK;
wire RD_EN;
wire RST;
wire WR_CLK;
wire WR_EN;
*/
//***************************************************************************
// Dout may change behavior based on latency
//***************************************************************************
assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?
ideal_dout_d1: ideal_dout;
assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out;
//***************************************************************************
// Assign SBITERR and DBITERR based on latency
//***************************************************************************
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY == 2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
//***************************************************************************
// Safety-ckt logic with embedded reg/fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
// if (C_HAS_VALID == 1) begin
// assign valid_out = valid_d1;
// end
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)
begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else begin
if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end
end
endgenerate
//***************************************************************************
// Safety-ckt logic with embedded reg + fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else begin
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end
endgenerate
//***************************************************************************
// Overflow may be active-low
//***************************************************************************
generate
if (C_HAS_OVERFLOW==1) begin : blockOF1
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end
endgenerate
assign PROG_EMPTY = ideal_prog_empty;
assign PROG_FULL = ideal_prog_full;
//***************************************************************************
// Valid may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_VALID==1) begin : blockVL1
assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out1 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?
valid_d1: valid_i;
assign valid_out2 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?
valid_d2: valid_i;
assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end
endgenerate
//***************************************************************************
// Underflow may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_UNDERFLOW==1) begin : blockUF1
assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end
endgenerate
//***************************************************************************
// Write acknowledge may be active low
//***************************************************************************
generate
if (C_HAS_WR_ACK==1) begin : blockWK1
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext
reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0;
reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0;
wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp;
wire [C_PNTR_WIDTH:0] diff_wr_rd;
reg [C_PNTR_WIDTH:0] wr_data_count_i = 0;
always @* begin
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = 0;
adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin
adjusted_rd_pntr = rd_pntr_wr;
adjusted_wr_pntr = 0;
adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
end else begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = rd_pntr_wr;
end
end // always @*
assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;
assign diff_wr_rd = {1'b0,diff_wr_rd_tmp};
always @ (posedge wr_rst_i or posedge WR_CLK)
begin
if (wr_rst_i)
wr_data_count_i <= 0;
else
wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;
end // always @ (posedge WR_CLK or posedge WR_CLK)
always @* begin
if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];
else
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end // always @*
end // wdc_fwft_ext
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0;
generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= 0;
end else begin
if (!stage2_valid)
rdc_fwft_ext_as <= #`TCQ 0;
else if (!stage1_valid && stage2_valid)
rdc_fwft_ext_as <= #`TCQ 1;
else
rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;
end
end // always @ (posedge WR_CLK or posedge WR_CLK)
end // rdc_fwft_ext
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3) begin
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1;
// assign diff_rd_wr_1 = diff_rd_wr +2'h2;
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= #`TCQ 0;
end else begin
//if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b0;
//else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b1;
//else
rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;
end
end
end
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?
rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :
rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?
wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :
wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate
if (C_HAS_VALID==1) begin : blockVL2
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_d2 <= 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
valid_d2 <= #`TCQ valid_d1;
end
// if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin
// valid_d2 <= #`TCQ valid_d1;
// end
end
end
endgenerate
//Capture delayed version of dout
/**************************************************************************
*embedded/fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG < 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
endgenerate
/**************************************************************************
*embedded + fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG == 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate
if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge WR_CLK) begin
ideal_overflow <= #`TCQ WR_EN & FULL;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge WR_CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i);
ideal_overflow <= #`TCQ WR_EN & (FULL );
end
end
endgenerate
generate
if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ EMPTY & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ (EMPTY) & RD_EN;
//ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;
end
end
endgenerate
/**************************************************************************
* Write/Read Pointer Synchronization
**************************************************************************/
localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;
wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
genvar gss;
generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_WR_PNTR_WIDTH)
)
rd_stg_inst
(
.RST (rd_rst_i),
.CLK (RD_CLK),
.DIN (wr_pntr_sync_stgs[gss-1]),
.DOUT (wr_pntr_sync_stgs[gss])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_RD_PNTR_WIDTH)
)
wr_stg_inst
(
.RST (wr_rst_i),
.CLK (WR_CLK),
.DIN (rd_pntr_sync_stgs[gss-1]),
.DOUT (rd_pntr_sync_stgs[gss])
);
end endgenerate // Sync_stage_inst
assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;
assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;
always@* begin
wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
end
/**************************************************************************
* Write Domain Logic
**************************************************************************/
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp
if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)
wr_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)
wr_pntr <= #`TCQ 0;
end
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (wr_rst_i == 1'b1) begin
num_wr_bits <= 0;
next_num_wr_bits = 0;
wr_ptr <= C_WR_DEPTH - 1;
rd_ptr_wrclk <= C_RD_DEPTH - 1;
ideal_wr_ack <= 0;
ideal_wr_count <= 0;
tmp_wr_listsize = 0;
rd_ptr_wrclk_next <= 0;
wr_pntr_rd1 <= 0;
end else begin //wr_rst_i==0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
//If this is a write, handle the write by adding the value
// to the linked list, and updating all outputs appropriately
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD
>= C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full, but reporting full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//With DEPTH-1 words in the FIFO, it is almost_full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is completely empty, but it is
// reporting FULL for some reason (like reset)
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=
C_FIFO_WR_DEPTH-2) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//FIFO is really not close to full, so change flag status.
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end //(tmp_wr_listsize == 0)
end else begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=
C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//This write is CAUSING the FIFO to go full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is 2 from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Still 2 from full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is not close to being full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //wr_rst_i==0
end // gen_fifo_w
/***************************************************************************
* Programmable FULL flags
***************************************************************************/
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;
generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;
end else begin // STD
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;
end endgenerate
always @(posedge WR_CLK or posedge wr_rst_i) begin
if (wr_rst_i == 1'b1) begin
diff_pntr <= 0;
end else begin
if (ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);
else if (!ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);
end
end
always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf
if (RST_FULL_FF == 1'b1) begin
ideal_prog_full <= C_FULL_FLAGS_RST_VAL;
end else begin
if (RST_FULL_GEN)
ideal_prog_full <= #`TCQ 0;
//Single Programmable Full Constant Threshold
else if (C_PROG_FULL_TYPE == 1) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Constant Thresholds
end else if (C_PROG_FULL_TYPE == 2) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < pf_thr_negate_val)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Single Programmable Full Threshold Input
end else if (C_PROG_FULL_TYPE == 3) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Threshold Inputs
end else if (C_PROG_FULL_TYPE == 4) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH_ASSERT)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < PROG_FULL_THRESH_NEGATE)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
end // C_PROG_FULL_TYPE
end //wr_rst_i==0
end //
/**************************************************************************
* Read Domain Logic
**************************************************************************/
/*********************************************************
* Programmable EMPTY flags
*********************************************************/
//Determine the Assert and Negate thresholds for Programmable Empty
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0;
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe
if (rd_rst_i) begin
diff_pntr_rd <= 0;
ideal_prog_empty <= 1'b1;
end else begin
if (ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;
else if (!ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr);
else
diff_pntr_rd <= #`TCQ diff_pntr_rd;
if (C_PROG_EMPTY_TYPE == 1) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 2) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 3) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 4) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end //C_PROG_EMPTY_TYPE
end
end // gen_pe
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;
end endgenerate // single_pe_thr_input
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;
end endgenerate // multiple_pe_thr_input
generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;
end endgenerate // single_multiple_pe_thr_const
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
rd_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)
rd_pntr <= #`TCQ 0;
end
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as
/****** Reset fifo (case 1)***************************************/
if (rd_rst_i) begin
num_rd_bits <= 0;
next_num_rd_bits = 0;
rd_ptr <= C_RD_DEPTH -1;
rd_pntr_wr1 <= 0;
wr_ptr_rdclk <= C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)
ideal_dout <= dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= 1'b0;
ideal_rd_count <= 0;
end else begin //rd_rst_i==0
rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
/*****************************************************************/
// Read Operation - Read Latency 1
/*****************************************************************/
if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
//If the FIFO is one from empty, but it is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is two from empty, and is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end // else: if(ideal_empty == 1'b1)
else //if (ideal_empty == 1'b0)
begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)
//If the FIFO is not close to being empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
//If the FIFO is two from empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is one from empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is completely empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end //(RD_EN == 1'b1)
else //if (RD_EN == 1'b0)
begin
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
/*****************************************************************/
// Read Operation - Read Latency 0
/*****************************************************************/
end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty, but it is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty, and is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end else begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to being empty
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is completely empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end else begin//(RD_EN == 1'b0)
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //rd_rst_i==0
end //always gen_fifo_r_as
endmodule // fifo_generator_v13_1_3_bhv_ver_as
/*******************************************************************************
* Declaration of Low Latency Asynchronous FIFO
******************************************************************************/
module fifo_generator_v13_1_3_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_USE_DOUT_RST = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_FIFO_TYPE = 0
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input [C_DIN_WIDTH-1:0] DIN,
input RD_CLK,
input RD_EN,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
output reg [C_DOUT_WIDTH-1:0] DOUT = 0,
output reg EMPTY = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL
);
//-----------------------------------------------------------------------------
// Low Latency Asynchronous FIFO
//-----------------------------------------------------------------------------
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
integer i;
initial begin
for (i = 0; i < C_WR_DEPTH; i = i + 1)
memory[i] = 0;
end
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;
reg ll_afifo_full = 1'b0;
reg ll_afifo_empty = 1'b1;
wire write_allow;
wire read_allow;
assign write_allow = WR_EN & ~ll_afifo_full;
assign read_allow = RD_EN & ~ll_afifo_empty;
//-----------------------------------------------------------------------------
// Write Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
wr_pntr_ll_afifo <= 0;
else if (write_allow)
wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;
end
//-----------------------------------------------------------------------------
// Read Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
rd_pntr_ll_afifo_q <= 0;
else
rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;
end
assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;
//-----------------------------------------------------------------------------
// Fill the Memory
//-----------------------------------------------------------------------------
always @(posedge WR_CLK) begin
if (write_allow)
memory[wr_pntr_ll_afifo] <= #`TCQ DIN;
end
//-----------------------------------------------------------------------------
// Generate DOUT
//-----------------------------------------------------------------------------
always @(posedge RD_CLK) begin
DOUT <= #`TCQ memory[rd_pntr_ll_afifo];
end
//-----------------------------------------------------------------------------
// Generate EMPTY
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
ll_afifo_empty <= 1'b1;
else
ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) |
(read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));
end
//-----------------------------------------------------------------------------
// Generate FULL
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
ll_afifo_full <= 1'b1;
else
ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) |
(write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));
end
always @* begin
FULL <= ll_afifo_full;
EMPTY <= ll_afifo_empty;
end
endmodule // fifo_generator_v13_1_3_beh_ver_ll_afifo
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* Declare user parameters and their defaults
*************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
/**************************************************************************
* Declare Input and Output Ports
*************************************************************************/
(
//Inputs
input SAFETY_CKT_WR_RST,
input CLK,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_EN,
input RD_EN_USER,
input USER_EMPTY_FB,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input SRST,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input WR_RST_BUSY,
input RD_RST_BUSY,
//Outputs
output ALMOST_EMPTY,
output ALMOST_FULL,
output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,
output [C_DOUT_WIDTH-1:0] DOUT,
output EMPTY,
output reg EMPTY_FB = 1'b1,
output FULL,
output OVERFLOW,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output UNDERFLOW,
output WR_ACK,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;
wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
//localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
//localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
//The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not
//changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.
// Therefore, during SRST, all the FULL flags reset to 0.
localparam C_HAS_FAST_FIFO = 0;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH;
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;
localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;
localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;
localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}};
localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}};
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
/**************************************************************************
* Internal Registers and wires
*************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire underflow_i;
wire valid_i;
wire valid_out;
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_reg = 1'b0;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
wire srst_rrst_busy;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire fwft_enabled;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg full_i = C_FULL_FLAGS_RST_VAL;
reg full_i_temp = 0;
reg empty_i = 1;
reg almost_full_i = 0;
reg almost_empty_i = 1;
reg prog_full_i = 0;
reg prog_empty_i = 1;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0;
reg write_allow_q = 0;
reg read_allow_q = 0;
reg valid_d1 = 0;
reg valid_both = 0;
reg valid_d2 = 0;
wire rst_i;
wire srst_i;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
/****************************************************************************
* Function Declarations
***************************************************************************/
/****************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***************************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin
case (def_data[7:0])
8'b00000000 : begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default : begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1) begin
if ((index*4)+j < C_DOUT_WIDTH) begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
//reg valid_d1 = 0;
//user specified value for reseting the size of the fifo
//reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_dout_both = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_both = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_EN;
wire RST;
wire WR_EN;
*/
// Assign ALMOST_EPMTY
generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae
assign ALMOST_EMPTY = almost_empty_i;
end else begin : gnae
assign ALMOST_EMPTY = 0;
end endgenerate // gae
// Assign ALMOST_FULL
generate if (C_HAS_ALMOST_FULL==1) begin : gaf
assign ALMOST_FULL = almost_full_i;
end else begin : gnaf
assign ALMOST_FULL = 0;
end endgenerate // gaf
// Dout may change behavior based on latency
localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
ideal_dout_d1: ideal_dout;
assign DOUT = ideal_dout_out;
// Assign SBITERR and DBITERR based on latency
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
assign EMPTY = empty_i;
assign FULL = full_i;
//saftey_ckt with one register
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK)
begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)
begin
if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end
else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
valid_d1 <= #`TCQ valid_i;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end //if
endgenerate
//safety ckt with both registers
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK) begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end //if
endgenerate
//Overflow may be active-low
generate if (C_HAS_OVERFLOW==1) begin : gof
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end else begin : gnof
assign OVERFLOW = 0;
end endgenerate // gof
assign PROG_EMPTY = prog_empty_i;
assign PROG_FULL = prog_full_i;
//Valid may change behavior based on latency or active-low
generate if (C_HAS_VALID==1) begin : gvalid
assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?
valid_d1 : valid_i;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end else begin : gnvalid
assign VALID = 0;
end endgenerate // gvalid
//Trim data count differently depending on set widths
generate if (C_HAS_DATA_COUNT == 1) begin : gdc
always @* begin
diff_count <= wr_pntr - rd_pntr;
if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin
DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count;
DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ;
end else begin
DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
end
end
// end else begin : gndc
// always @* DATA_COUNT <= 0;
end endgenerate // gdc
//Underflow may change behavior based on latency or active-low
generate if (C_HAS_UNDERFLOW==1) begin : guf
assign underflow_i = ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end else begin : gnuf
assign UNDERFLOW = 0;
end endgenerate // guf
//Write acknowledge may be active low
generate if (C_HAS_WR_ACK==1) begin : gwr_ack
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end else begin : gnwr_ack
assign WR_ACK = 0;
end endgenerate // gwr_ack
/*****************************************************************************
* Internal reset logic
****************************************************************************/
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;
assign rst_i = C_HAS_RST ? RST : 0;
assign srst_wrst_busy = srst_i;
assign srst_rrst_busy = srst_i;
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_both <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
valid_both <= #`TCQ 1'b0;
end else begin
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge CLK or posedge rst_i) begin
if (rst_i) begin
stage1_valid <= #`TCQ 0;
stage2_valid <= #`TCQ 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//reg ram_rd_en_d1 = 1'b0;
//Capture delayed version of dout
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
ram_rd_en_d1 <= #`TCQ 1'b0;
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
end // always
end
endgenerate
//no safety ckt with both registers
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);
if (ram_rd_en_d1 ) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end // always
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge CLK) begin
ideal_overflow <= #`TCQ WR_EN & full_i;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i);
ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);
end
end endgenerate // blockOF20
generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge CLK) begin
ideal_underflow <= #`TCQ empty_i & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge CLK) begin
//ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN;
ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;
end
end endgenerate // blockUF20
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/*************************************************************************
* Write and Read Logic
************************************************************************/
wire write_allow;
wire read_allow;
wire read_allow_dc;
wire write_only;
wire read_only;
//wire write_only_q;
reg write_only_q;
//wire read_only_q;
reg read_only_q;
reg full_reg;
reg rst_full_ff_reg1;
reg rst_full_ff_reg2;
wire ram_full_comb;
wire carry;
assign write_allow = WR_EN & ~full_i;
assign read_allow = RD_EN & ~empty_i;
assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;
//assign write_only = write_allow & ~read_allow;
//assign write_only_q = write_allow_q;
//assign read_only = read_allow & ~write_allow;
//assign read_only_q = read_allow_q ;
wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;
reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;
wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;
wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;
assign diff_pntr_pe_max = DIFF_MAX_RD;
assign diff_pntr_max = DIFF_MAX_WR;
generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym
assign write_only = write_allow & ~read_allow;
assign read_only = read_allow & ~write_allow;
end endgenerate
generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd
assign read_only = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;
assign write_only = write_allow & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr
assign read_only = read_allow & ~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
assign write_only = write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;
end endgenerate
//-----------------------------------------------------------------------------
// Write and Read pointer generation
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
wr_pntr <= 0;
rd_pntr <= 0;
end else begin
if (srst_i) begin
wr_pntr <= #`TCQ 0;
rd_pntr <= #`TCQ 0;
end else begin
if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;
if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1;
end
end
end
generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout
always @(posedge CLK) begin
if (write_allow) begin
if (ENABLE_ERR_INJECTION == 1)
memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};
else
memory[wr_pntr] <= #`TCQ DIN;
end
end
reg [C_DATA_WIDTH-1:0] dout_tmp_q;
reg [C_DATA_WIDTH-1:0] dout_tmp = 0;
reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0;
always @(posedge CLK) begin
dout_tmp_q <= #`TCQ ideal_dout;
end
always @* begin
if (read_allow)
ideal_dout <= memory[rd_pntr];
else
ideal_dout <= dout_tmp_q;
end
end endgenerate // gll_dm_dout
/**************************************************************************
* Write Domain Logic
**************************************************************************/
assign ram_rd_en = RD_EN & !EMPTY;
//reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
generate if (C_FIFO_TYPE != 2) begin : gnll_din
always @(posedge CLK or posedge rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (rst_i == 1'b1) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin //rst_i==0
if (srst_wrst_busy) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin//srst_i=0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end else begin
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
//end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //srst_i==0
end //wr_rst_i==0
end // gen_fifo_w
end endgenerate
generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout
always @(posedge CLK) begin
if (rst_i || srst_rrst_busy) begin
if (C_USE_DOUT_RST == 1) begin
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end
end
end endgenerate
generate if (C_FIFO_TYPE != 2) begin : gnll_dout
always @(posedge CLK or posedge rst_i) begin : gen_fifo_r
/****** Reset fifo (case 1)***************************************/
if (rst_i) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end else begin //rd_rst_i==0
if (srst_rrst_busy) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets synchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end //srst_i
else begin
//rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
if (RD_EN == 1'b1) begin
if (EMPTY == 1'b1) begin
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end
else
begin
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
end
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //s_rst_i==0
end //rd_rst_i==0
end //always
end endgenerate
//-----------------------------------------------------------------------------
// Generate diff_pntr for PROG_FULL generation
// Generate diff_pntr_pe for PROG_EMPTY generation
//-----------------------------------------------------------------------------
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow
always @(posedge CLK ) begin
if (rst_i) begin
write_only_q <= 1'b0;
read_only_q <= 1'b0;
diff_pntr_reg1 <= 0;
diff_pntr_pe_reg1 <= 0;
diff_pntr_reg2 <= 0;
diff_pntr_pe_reg2 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_rrst_busy) begin
read_only_q <= #`TCQ 1'b0;
diff_pntr_pe_reg1 <= #`TCQ 0;
diff_pntr_pe_reg2 <= #`TCQ 0;
end
if (srst_wrst_busy) begin
write_only_q <= #`TCQ 1'b0;
diff_pntr_reg1 <= #`TCQ 0;
diff_pntr_reg2 <= #`TCQ 0;
end
end else begin
write_only_q <= #`TCQ write_only;
read_only_q <= #`TCQ read_only;
diff_pntr_reg2 <= #`TCQ diff_pntr_reg1;
diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1;
// Add 1 to the difference pointer value when only write happens.
if (write_only)
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;
else
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
// Add 1 to the difference pointer value when write or both write & read or no write & read happen.
if (read_only)
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;
else
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;
end
end
end
assign diff_pntr_pe = diff_pntr_pe_reg1;
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym
assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};
assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};
always @(posedge CLK ) begin
if (rst_i) begin
diff_pntr_pe_asym <= 0;
diff_pntr_reg1 <= 0;
full_reg <= 0;
rst_full_ff_reg1 <= 1;
rst_full_ff_reg2 <= 1;
diff_pntr_pe_reg1 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_wrst_busy)
diff_pntr_reg1 <= #`TCQ 0;
if (srst_rrst_busy)
full_reg <= #`TCQ 0;
rst_full_ff_reg1 <= #`TCQ 1;
rst_full_ff_reg2 <= #`TCQ 1;
diff_pntr_pe_asym <= #`TCQ 0;
diff_pntr_pe_reg1 <= #`TCQ 0;
end else begin
diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;
full_reg <= #`TCQ full_i;
rst_full_ff_reg1 <= #`TCQ RST_FULL_FF;
rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1;
if (~full_i) begin
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
end
end
end
end
assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));
assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow_asym
//-----------------------------------------------------------------------------
// Generate FULL flag
//-----------------------------------------------------------------------------
wire comp0;
wire comp1;
wire going_full;
wire leaving_full;
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad
assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim
assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1));
assign comp0 = (adj_rd_pntr_wr == wr_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym
assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_full_comb = going_full | (~leaving_full & full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
full_i <= #`TCQ ram_full_comb;
end
//-----------------------------------------------------------------------------
// Generate EMPTY flag
//-----------------------------------------------------------------------------
wire ecomp0;
wire ecomp1;
wire going_empty;
wire leaving_empty;
wire ram_empty_comb;
generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad
assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim
assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1));
assign ecomp0 = (adj_wr_pntr_rd == rd_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty = (ecomp0 & write_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp
assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty =(ecomp0 & write_allow);
end endgenerate
assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
empty_i <= 1'b1;
else if (srst_rrst_busy)
empty_i <= #`TCQ 1'b1;
else
empty_i <= #`TCQ ram_empty_comb;
end
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ ram_empty_comb;
end
end // always
//-----------------------------------------------------------------------------
// Generate Read and write data counts for asymmetic common clock
//-----------------------------------------------------------------------------
reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0;
wire [C_GRTR_PNTR_WIDTH :0] ratio;
wire decr_by_one;
wire incr_by_ratio;
wire incr_by_one;
wire decr_by_ratio;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr
assign ratio = C_DEPTH_RATIO_RD;
assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow;
assign incr_by_ratio = write_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (decr_by_one) begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc - 1;
else
count_dc <= #`TCQ count_dc - 1 + ratio ;
end
else begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc + ratio ;
end
end
end
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd
assign ratio = C_DEPTH_RATIO_WR;
assign incr_by_one = write_allow;
assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (incr_by_one) begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc + 1;
else
count_dc <= #`TCQ count_dc + 1 - ratio ;
end
else begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc - ratio ;
end
end
end
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
//-----------------------------------------------------------------------------
// Generate WR_ACK flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_wr_ack <= 1'b0;
else if (srst_wrst_busy)
ideal_wr_ack <= #`TCQ 1'b0;
else if (WR_EN & ~full_i)
ideal_wr_ack <= #`TCQ 1'b1;
else
ideal_wr_ack <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate VALID flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_valid <= 1'b0;
else if (srst_rrst_busy)
ideal_valid <= #`TCQ 1'b0;
else if (RD_EN & ~empty_i)
ideal_valid <= #`TCQ 1'b1;
else
ideal_valid <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate ALMOST_FULL flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss
wire fcomp2;
wire going_afull;
wire leaving_afull;
wire ram_afull_comb;
assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym
assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
almost_full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
almost_full_i <= #`TCQ ram_afull_comb;
end
// end endgenerate // gaf_ss
//-----------------------------------------------------------------------------
// Generate ALMOST_EMPTY flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss
wire ecomp2;
wire going_aempty;
wire leaving_aempty;
wire ram_aempty_comb;
assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty = (ecomp1 & write_allow & ~read_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp
assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);
end endgenerate
assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
almost_empty_i <= 1'b1;
else if (srst_rrst_busy)
almost_empty_i <= #`TCQ 1'b1;
else
almost_empty_i <= #`TCQ ram_aempty_comb;
end
// end endgenerate // gae_ss
//-----------------------------------------------------------------------------
// Generate PROG_FULL
//-----------------------------------------------------------------------------
localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT
C_PROG_FULL_THRESH_ASSERT_VAL; // STD
localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT
C_PROG_FULL_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold constant
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;
generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr>= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr) < C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b0;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate // single_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr >= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < C_PF_NEGATE_VAL)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ?
PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT
PROG_FULL_THRESH; // STD
generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input
always @(posedge CLK or posedge RST_FULL_FF) begin//0
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin //1
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin//2
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin//3
if (diff_pntr > pf3_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == pf3_assert_val) begin//4
if (read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b1;
end else//4
prog_full_i <= #`TCQ 1'b0;
end else//3
prog_full_i <= #`TCQ prog_full_i;
end //2
else begin//5
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin//6
if (diff_pntr >= pf3_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf3_assert_val) begin//7
prog_full_i <= #`TCQ 1'b0;
end//7
end//6
else
prog_full_i <= #`TCQ prog_full_i;
end//5
end//1
end//0
end endgenerate //single_pf_input
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_ASSERT; // STD
wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_NEGATE; // STD
generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin
if (diff_pntr >= pf_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr == pf_negate_val && read_only_q) ||
diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin
if (diff_pntr >= pf_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_inputs
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY
//-----------------------------------------------------------------------------
localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD
localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold constant
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b0;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_NEGATE_VAL)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate //multiple_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH -2) : // FWFT
PROG_EMPTY_THRESH; // STD
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe < pe3_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == pe3_assert_val) begin
if (write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ 1'b1;
end else
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe3_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe3_assert_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_input
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT
PROG_EMPTY_THRESH_ASSERT; // STD
wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT
PROG_EMPTY_THRESH_NEGATE; // STD
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe <= pe4_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) ||
(diff_pntr_pe > pe4_negate_val)) begin
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe4_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe4_negate_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // multiple_pe_inputs
endmodule // fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* First-Word Fall-Through module (preload 0)
**************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USERVALID_LOW = 0,
parameter C_USERUNDERFLOW_LOW = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
(
//Inputs
input SAFETY_CKT_RD_RST,
input RD_CLK,
input RD_RST,
input SRST,
input WR_RST_BUSY,
input RD_RST_BUSY,
input RD_EN,
input FIFOEMPTY,
input [C_DOUT_WIDTH-1:0] FIFODATA,
input FIFOSBITERR,
input FIFODBITERR,
//Outputs
output reg [C_DOUT_WIDTH-1:0] USERDATA,
output USERVALID,
output USERUNDERFLOW,
output USEREMPTY,
output USERALMOSTEMPTY,
output RAMVALID,
output FIFORDEN,
output reg USERSBITERR,
output reg USERDBITERR,
output reg STAGE2_REG_EN,
output fab_read_data_valid_i_o,
output read_data_valid_i_o,
output ram_valid_i_o,
output [1:0] VALID_STAGES
);
//Internal signals
wire preloadstage1;
wire preloadstage2;
reg ram_valid_i;
reg fab_valid;
reg read_data_valid_i;
reg fab_read_data_valid_i;
reg fab_read_data_valid_i_1;
reg ram_valid_i_d;
reg read_data_valid_i_d;
reg fab_read_data_valid_i_d;
wire ram_regout_en;
reg ram_regout_en_d1;
reg ram_regout_en_d2;
wire fab_regout_en;
wire ram_rd_en;
reg empty_i = 1'b1;
reg empty_sckt = 1'b1;
reg sckt_rrst_q = 1'b0;
reg sckt_rrst_done = 1'b0;
reg empty_q = 1'b1;
reg rd_en_q = 1'b0;
reg almost_empty_i = 1'b1;
reg almost_empty_q = 1'b1;
wire rd_rst_i;
wire srst_i;
reg [C_DOUT_WIDTH-1:0] userdata_both;
wire uservalid_both;
wire uservalid_one;
reg user_sbiterr_both = 1'b0;
reg user_dbiterr_both = 1'b0;
assign ram_valid_i_o = ram_valid_i;
assign read_data_valid_i_o = read_data_valid_i;
assign fab_read_data_valid_i_o = fab_read_data_valid_i;
/*************************************************************************
* FUNCTIONS
*************************************************************************/
/*************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
//*************************************************************************
// Set power-on states for regs
//*************************************************************************
initial begin
ram_valid_i = 1'b0;
fab_valid = 1'b0;
read_data_valid_i = 1'b0;
fab_read_data_valid_i = 1'b0;
fab_read_data_valid_i_1 = 1'b0;
USERDATA = hexstr_conv(C_DOUT_RST_VAL);
userdata_both = hexstr_conv(C_DOUT_RST_VAL);
USERSBITERR = 1'b0;
USERDBITERR = 1'b0;
user_sbiterr_both = 1'b0;
user_dbiterr_both = 1'b0;
end //initial
//***************************************************************************
// connect up optional reset
//***************************************************************************
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;
reg sckt_rd_rst_fwft = 1'b0;
reg fwft_rst_done_i = 1'b0;
wire fwft_rst_done;
assign fwft_rst_done = C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;
always @ (posedge RD_CLK) begin
sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i)
fwft_rst_done_i <= 1'b0;
else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)
fwft_rst_done_i <= #`TCQ 1'b1;
end
localparam INVALID = 0;
localparam STAGE1_VALID = 2;
localparam STAGE2_VALID = 1;
localparam BOTH_STAGES_VALID = 3;
reg [1:0] curr_fwft_state = INVALID;
reg [1:0] next_fwft_state = INVALID;
generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = preloadstage2;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
reg curr_state = 0;
reg next_state = 0;
reg leaving_empty_fwft = 0;
reg going_empty_fwft = 0;
reg empty_i_q = 0;
reg ram_rd_en_fwft = 0;
generate if (C_FIFO_TYPE == 2) begin : gll_fifo
always @* begin // FSM fo FWFT
case (curr_state)
1'b0: begin
if (~FIFOEMPTY)
next_state <= 1'b1;
else
next_state <= 1'b0;
end
1'b1: begin
if (FIFOEMPTY && RD_EN)
next_state <= 1'b0;
else
next_state <= 1'b1;
end
default: next_state <= 1'b0;
endcase
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_i <= 1'b1;
empty_i_q <= 1'b1;
ram_valid_i <= 1'b0;
end else if (srst_i) begin
empty_i <= #`TCQ 1'b1;
empty_i_q <= #`TCQ 1'b1;
ram_valid_i <= #`TCQ 1'b0;
end else begin
empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);
empty_i_q <= #`TCQ FIFOEMPTY;
ram_valid_i <= #`TCQ next_state;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
curr_state <= 1'b0;
end else if (srst_i) begin
curr_state <= #`TCQ 1'b0;
end else begin
curr_state <= #`TCQ next_state;
end
end //always
wire fe_of_empty;
assign fe_of_empty = empty_i_q & ~FIFOEMPTY;
always @* begin // Finding leaving empty
case (curr_state)
1'b0: leaving_empty_fwft <= fe_of_empty;
1'b1: leaving_empty_fwft <= 1'b1;
default: leaving_empty_fwft <= 1'b0;
endcase
end
always @* begin // Finding going empty
case (curr_state)
1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN;
default: going_empty_fwft <= 1'b0;
endcase
end
always @* begin // Generating FWFT rd_en
case (curr_state)
1'b0: ram_rd_en_fwft <= ~FIFOEMPTY;
1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;
default: ram_rd_en_fwft <= 1'b0;
endcase
end
assign ram_regout_en = ram_rd_en_fwft;
//assign ram_regout_en_d1 = ram_rd_en_fwft;
//assign ram_regout_en_d2 = ram_rd_en_fwft;
assign ram_rd_en = ram_rd_en_fwft;
end endgenerate // gll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false.
// Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (ram_rd_en == 1'b1) begin
ram_valid_i <= #`TCQ 1'b1;
end else begin
if (ram_regout_en == 1'b1)
ram_valid_i <= #`TCQ 1'b0;
else
ram_valid_i <= #`TCQ ram_valid_i;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_ram_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
generate if ( C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ FIFOEMPTY;
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
// BRAM resets synchronously
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin
always @ ( posedge rd_rst_i)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
//safety ckt with one register
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
//@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay
if (rd_rst_i == 1) begin
ram_regout_en_d1 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d1 <= #`TCQ 1'b0;
else
ram_regout_en_d1 <= #`TCQ ram_regout_en;
end
end //always
// assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));
assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1
if (rd_rst_i == 1) begin
ram_regout_en_d2 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d2 <= #`TCQ 1'b0;
else
ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;
end
end //always
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
always @ (posedge RD_CLK) begin
ram_valid_i_d <= #`TCQ ram_valid_i;
read_data_valid_i_d <= #`TCQ read_data_valid_i;
fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (ram_regout_en == 1'b1) begin
fab_valid <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
fab_valid <= #`TCQ 1'b0;
else
fab_valid <= #`TCQ fab_valid;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_fab_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG == 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else begin
if (ram_regout_en == 1'b1) begin
read_data_valid_i <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ read_data_valid_i;
end
end
end //always
end
endgenerate
//generate if(C_USE_EMBEDDED_REG == 3) begin
// always @ (posedge RD_CLK or posedge rd_rst_i) begin
// if (rd_rst_i)
// read_data_valid_i <= #`TCQ 1'b0;
// else if (srst_i)
// read_data_valid_i <= #`TCQ 1'b0;
//
// if (ram_regout_en == 1'b1) begin
// fab_read_data_valid_i <= #`TCQ 1'b0;
// end else begin
// if (fab_regout_en == 1'b1)
// fab_read_data_valid_i <= #`TCQ 1'b1;
// else
// fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;
// end
// end //always
//end
//endgenerate
generate if(C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid
if (rd_rst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else
fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
always @ (posedge RD_CLK ) begin : proc_del1
begin
fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;
end
end //always
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty_both
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
reg FIFOEMPTY_1;
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @(posedge RD_CLK) begin
FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;
end
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ (~ram_valid_i);
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_sckt <= #`TCQ 1'b1;
sckt_rrst_q <= #`TCQ 1'b0;
sckt_rrst_done <= #`TCQ 1'b0;
end else begin
sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;
if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin
sckt_rrst_done <= #`TCQ 1'b1;
end else if (sckt_rrst_done) begin
// rising clock edge
empty_sckt <= #`TCQ 1'b0;
end
end
end //always
// assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;
assign USEREMPTY = empty_i;
assign USERALMOSTEMPTY = almost_empty_i;
assign FIFORDEN = ram_rd_en;
assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;
assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);
assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);
assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;
assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;
//no safety ckt with both reg
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin
if (fwft_rst_done) begin
if (ram_regout_en) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end
end //always
end //if
endgenerate
//safety_ckt with both registers
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK) begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end //always
end //if
endgenerate
endmodule //fifo_generator_v13_1_3_bhv_ver_preload0
//-----------------------------------------------------------------------------
//
// Register Slice
// Register one AXI channel on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// reg_slice
//
//--------------------------------------------------------------------------
module fifo_generator_v13_1_3_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
generate
////////////////////////////////////////////////////////////////////
//
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000)
begin
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg [C_DATA_WIDTH-1:0] storage_data2 = 0;
reg load_s1;
wire load_s2;
wire load_s1_from_s2;
reg s_ready_i; //local signal of output
wire m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with slave side data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data1;
// Always load s2 on a valid transaction even if it's unnecessary
assign load_s2 = S_VALID & s_ready_i;
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
state <= ZERO;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else begin
case (state)
// No transaction stored locally
ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
s_ready_i <= 1'b0;
end
end
// TWO transaction stored locally
TWO: if (M_READY) begin
state <= ONE; // Read out one so move to ONE
s_ready_i <= 1'b1;
end
endcase // case (state)
end
end // always @ (posedge ACLK)
assign m_valid_i = state[0];
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000001)
begin
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with slave side data
always @(posedge ACLK)
begin
if (ARESET) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (m_valid_i & M_READY) begin
s_ready_i <= 1'b1;
m_valid_i <= 1'b0;
end else if (S_VALID & s_ready_i) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b1;
end
if (~m_valid_i) begin
storage_data1 <= S_PAYLOAD_DATA;
end
end
assign M_PAYLOAD_DATA = storage_data1;
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule // reg_slice
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_dbg_uart.v
//
// *Module Description:
// Debug UART communication interface (8N1, Half-duplex)
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_dbg_uart (
// OUTPUTs
dbg_addr, // Debug register address
dbg_din, // Debug register data input
dbg_rd, // Debug register data read
dbg_uart_txd, // Debug interface: UART TXD
dbg_wr, // Debug register data write
// INPUTs
dbg_clk, // Debug unit clock
dbg_dout, // Debug register data output
dbg_rd_rdy, // Debug register data is ready for read
dbg_rst, // Debug unit reset
dbg_uart_rxd, // Debug interface: UART RXD
mem_burst, // Burst on going
mem_burst_end, // End TX/RX burst
mem_burst_rd, // Start TX burst
mem_burst_wr, // Start RX burst
mem_bw // Burst byte width
);
// OUTPUTs
//=========
output [5:0] dbg_addr; // Debug register address
output [15:0] dbg_din; // Debug register data input
output dbg_rd; // Debug register data read
output dbg_uart_txd; // Debug interface: UART TXD
output dbg_wr; // Debug register data write
// INPUTs
//=========
input dbg_clk; // Debug unit clock
input [15:0] dbg_dout; // Debug register data output
input dbg_rd_rdy; // Debug register data is ready for read
input dbg_rst; // Debug unit reset
input dbg_uart_rxd; // Debug interface: UART RXD
input mem_burst; // Burst on going
input mem_burst_end; // End TX/RX burst
input mem_burst_rd; // Start TX burst
input mem_burst_wr; // Start RX burst
input mem_bw; // Burst byte width
//=============================================================================
// 1) UART RECEIVE LINE SYNCHRONIZTION & FILTERING
//=============================================================================
// Synchronize RXD input
//--------------------------------
`ifdef SYNC_DBG_UART_RXD
wire uart_rxd_n;
omsp_sync_cell sync_cell_uart_rxd (
.data_out (uart_rxd_n),
.data_in (~dbg_uart_rxd),
.clk (dbg_clk),
.rst (dbg_rst)
);
wire uart_rxd = ~uart_rxd_n;
`else
wire uart_rxd = dbg_uart_rxd;
`endif
// RXD input buffer
//--------------------------------
reg [1:0] rxd_buf;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) rxd_buf <= 2'h3;
else rxd_buf <= {rxd_buf[0], uart_rxd};
// Majority decision
//------------------------
reg rxd_maj;
wire rxd_maj_nxt = (uart_rxd & rxd_buf[0]) |
(uart_rxd & rxd_buf[1]) |
(rxd_buf[0] & rxd_buf[1]);
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) rxd_maj <= 1'b1;
else rxd_maj <= rxd_maj_nxt;
wire rxd_s = rxd_maj;
wire rxd_fe = rxd_maj & ~rxd_maj_nxt;
wire rxd_re = ~rxd_maj & rxd_maj_nxt;
wire rxd_edge = rxd_maj ^ rxd_maj_nxt;
//=============================================================================
// 2) UART STATE MACHINE
//=============================================================================
// Receive state
//------------------------
reg [2:0] uart_state;
reg [2:0] uart_state_nxt;
wire sync_done;
wire xfer_done;
reg [19:0] xfer_buf;
wire [19:0] xfer_buf_nxt;
// State machine definition
parameter RX_SYNC = 3'h0;
parameter RX_CMD = 3'h1;
parameter RX_DATA1 = 3'h2;
parameter RX_DATA2 = 3'h3;
parameter TX_DATA1 = 3'h4;
parameter TX_DATA2 = 3'h5;
// State transition
always @(uart_state or xfer_buf_nxt or mem_burst or mem_burst_wr or mem_burst_rd or mem_burst_end or mem_bw)
case (uart_state)
RX_SYNC : uart_state_nxt = RX_CMD;
RX_CMD : uart_state_nxt = mem_burst_wr ?
(mem_bw ? RX_DATA2 : RX_DATA1) :
mem_burst_rd ?
(mem_bw ? TX_DATA2 : TX_DATA1) :
(xfer_buf_nxt[`DBG_UART_WR] ?
(xfer_buf_nxt[`DBG_UART_BW] ? RX_DATA2 : RX_DATA1) :
(xfer_buf_nxt[`DBG_UART_BW] ? TX_DATA2 : TX_DATA1));
RX_DATA1 : uart_state_nxt = RX_DATA2;
RX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
(mem_bw ? RX_DATA2 : RX_DATA1) :
RX_CMD;
TX_DATA1 : uart_state_nxt = TX_DATA2;
TX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
(mem_bw ? TX_DATA2 : TX_DATA1) :
RX_CMD;
// pragma coverage off
default : uart_state_nxt = RX_CMD;
// pragma coverage on
endcase
// State machine
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) uart_state <= RX_SYNC;
else if (xfer_done | sync_done |
mem_burst_wr | mem_burst_rd) uart_state <= uart_state_nxt;
// Utility signals
wire cmd_valid = (uart_state==RX_CMD) & xfer_done;
wire rx_active = (uart_state==RX_DATA1) | (uart_state==RX_DATA2) | (uart_state==RX_CMD);
wire tx_active = (uart_state==TX_DATA1) | (uart_state==TX_DATA2);
//=============================================================================
// 3) UART SYNCHRONIZATION
//=============================================================================
// After DBG_RST, the host needs to fist send a synchronization character (0x80)
// If this feature doesn't work properly, it is possible to disable it by
// commenting the DBG_UART_AUTO_SYNC define in the openMSP430.inc file.
reg sync_busy;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) sync_busy <= 1'b0;
else if ((uart_state==RX_SYNC) & rxd_fe) sync_busy <= 1'b1;
else if ((uart_state==RX_SYNC) & rxd_re) sync_busy <= 1'b0;
assign sync_done = (uart_state==RX_SYNC) & rxd_re & sync_busy;
`ifdef DBG_UART_AUTO_SYNC
reg [`DBG_UART_XFER_CNT_W+2:0] sync_cnt;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) sync_cnt <= {{`DBG_UART_XFER_CNT_W{1'b1}}, 3'b000};
else if (sync_busy | (~sync_busy & sync_cnt[2])) sync_cnt <= sync_cnt+{{`DBG_UART_XFER_CNT_W+2{1'b0}}, 1'b1};
wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = sync_cnt[`DBG_UART_XFER_CNT_W+2:3];
`else
wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = `DBG_UART_CNT;
`endif
//=============================================================================
// 4) UART RECEIVE / TRANSMIT
//=============================================================================
// Transfer counter
//------------------------
reg [3:0] xfer_bit;
reg [`DBG_UART_XFER_CNT_W-1:0] xfer_cnt;
wire txd_start = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1));
wire rxd_start = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC));
wire xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt=={`DBG_UART_XFER_CNT_W{1'b0}});
assign xfer_done = rx_active ? (xfer_bit==4'ha) : (xfer_bit==4'hb);
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) xfer_bit <= 4'h0;
else if (txd_start | rxd_start) xfer_bit <= 4'h1;
else if (xfer_done) xfer_bit <= 4'h0;
else if (xfer_bit_inc) xfer_bit <= xfer_bit+4'h1;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) xfer_cnt <= {`DBG_UART_XFER_CNT_W{1'b0}};
else if (rx_active & rxd_edge) xfer_cnt <= {1'b0, bit_cnt_max[`DBG_UART_XFER_CNT_W-1:1]};
else if (txd_start | xfer_bit_inc) xfer_cnt <= bit_cnt_max;
else if (|xfer_cnt) xfer_cnt <= xfer_cnt+{`DBG_UART_XFER_CNT_W{1'b1}};
// Receive/Transmit buffer
//-------------------------
assign xfer_buf_nxt = {rxd_s, xfer_buf[19:1]};
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) xfer_buf <= 20'h00000;
else if (dbg_rd_rdy) xfer_buf <= {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0};
else if (xfer_bit_inc) xfer_buf <= xfer_buf_nxt;
// Generate TXD output
//------------------------
reg dbg_uart_txd;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_uart_txd <= 1'b1;
else if (xfer_bit_inc & tx_active) dbg_uart_txd <= xfer_buf[0];
//=============================================================================
// 5) INTERFACE TO DEBUG REGISTERS
//=============================================================================
reg [5:0] dbg_addr;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_addr <= 6'h00;
else if (cmd_valid) dbg_addr <= xfer_buf_nxt[`DBG_UART_ADDR];
reg dbg_bw;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_bw <= 1'b0;
else if (cmd_valid) dbg_bw <= xfer_buf_nxt[`DBG_UART_BW];
wire dbg_din_bw = mem_burst ? mem_bw : dbg_bw;
wire [15:0] dbg_din = dbg_din_bw ? {8'h00, xfer_buf_nxt[18:11]} :
{xfer_buf_nxt[18:11], xfer_buf_nxt[9:2]};
wire dbg_wr = (xfer_done & (uart_state==RX_DATA2));
wire dbg_rd = mem_burst ? (xfer_done & (uart_state==TX_DATA2)) :
(cmd_valid & ~xfer_buf_nxt[`DBG_UART_WR]) | mem_burst_rd;
endmodule // omsp_dbg_uart
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
// ============================================================================
// Copyright (c) 2013 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
//
//
// web: http://www.terasic.com/
// email: [email protected]
//
// ============================================================================
//Date: Mon Jun 17 20:35:29 2013
// ============================================================================
`define ENABLE_HPS
module HPS_LED_HEX(
///////// ADC /////////
inout ADC_CS_N,
output ADC_DIN,
input ADC_DOUT,
output ADC_SCLK,
///////// AUD /////////
input AUD_ADCDAT,
inout AUD_ADCLRCK,
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK,
///////// CLOCK2 /////////
input CLOCK2_50,
///////// CLOCK3 /////////
input CLOCK3_50,
///////// CLOCK4 /////////
input CLOCK4_50,
///////// CLOCK /////////
input CLOCK_50,
///////// DRAM /////////
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
///////// FAN /////////
output FAN_CTRL,
///////// FPGA /////////
output FPGA_I2C_SCLK,
inout FPGA_I2C_SDAT,
///////// GPIO /////////
inout [35:0] GPIO_0,
inout [35:0] GPIO_1,
///////// HEX0 /////////
output [6:0] HEX0,
///////// HEX1 /////////
output [6:0] HEX1,
///////// HEX2 /////////
output [6:0] HEX2,
///////// HEX3 /////////
output [6:0] HEX3,
///////// HEX4 /////////
output [6:0] HEX4,
///////// HEX5 /////////
output [6:0] HEX5,
`ifdef ENABLE_HPS
///////// HPS /////////
inout HPS_CONV_USB_N,
output [14:0] HPS_DDR3_ADDR,
output [2:0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CKE,
output HPS_DDR3_CK_N,
output HPS_DDR3_CK_P,
output HPS_DDR3_CS_N,
output [3:0] HPS_DDR3_DM,
inout [31:0] HPS_DDR3_DQ,
inout [3:0] HPS_DDR3_DQS_N,
inout [3:0] HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
output HPS_ENET_GTX_CLK,
inout HPS_ENET_INT_N,
output HPS_ENET_MDC,
inout HPS_ENET_MDIO,
input HPS_ENET_RX_CLK,
input [3:0] HPS_ENET_RX_DATA,
input HPS_ENET_RX_DV,
output [3:0] HPS_ENET_TX_DATA,
output HPS_ENET_TX_EN,
inout [3:0] HPS_FLASH_DATA,
output HPS_FLASH_DCLK,
output HPS_FLASH_NCSO,
inout HPS_GSENSOR_INT,
inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,
inout HPS_I2C2_SCLK,
inout HPS_I2C2_SDAT,
inout HPS_I2C_CONTROL,
inout HPS_KEY,
inout HPS_LED,
inout HPS_LTC_GPIO,
output HPS_SD_CLK,
inout HPS_SD_CMD,
inout [3:0] HPS_SD_DATA,
output HPS_SPIM_CLK,
input HPS_SPIM_MISO,
output HPS_SPIM_MOSI,
inout HPS_SPIM_SS,
input HPS_UART_RX,
output HPS_UART_TX,
input HPS_USB_CLKOUT,
inout [7:0] HPS_USB_DATA,
input HPS_USB_DIR,
input HPS_USB_NXT,
output HPS_USB_STP,
`endif /*ENABLE_HPS*/
///////// IRDA /////////
input IRDA_RXD,
output IRDA_TXD,
///////// KEY /////////
input [3:0] KEY,
///////// LEDR /////////
output [9:0] LEDR,
///////// PS2 /////////
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
///////// SW /////////
input [9:0] SW,
///////// TD /////////
input TD_CLK27,
input [7:0] TD_DATA,
input TD_HS,
output TD_RESET_N,
input TD_VS,
///////// VGA /////////
output [7:0] VGA_B,
output VGA_BLANK_N,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N,
output VGA_VS
);
//=======================================================
// REG/WIRE declarations
//=======================================================
wire clk_143;
wire HEX0P;
wire HEX1P;
wire HEX2P;
wire HEX3P;
wire HEX4P;
wire HEX5P;
wire [24:0] sdram_mm_slave_address; // sdram_mm_slave.address
wire [1:0] sdram_mm_slave_byteenable_n; // .byteenable_n
wire sdram_mm_slave_chipselect; // .chipselect
wire [15:0] sdram_mm_slave_writedata; // .writedata
wire sdram_mm_slave_read_n; // .read_n
wire sdram_mm_slave_write_n; // .write_n
wire [15:0] sdram_mm_slave_readdata; // .readdata
wire sdram_mm_slave_readdatavalid; // .readdatavalid
wire sdram_mm_slave_waitrequest; // .waitrequest
wire sdram_ref_clk_clk;
assign sdram_mm_slave_byteenable_n = 2'b11;
assign sdram_mm_slave_chipselect = 1'b1;
//=======================================================
// Structural coding
//=======================================================
soc_system u0 (
.clk_clk ( CLOCK_50), // clk.clk
.reset_reset_n ( KEY[0]), // reset.reset_n
.memory_mem_a ( HPS_DDR3_ADDR), // memory.mem_a
.memory_mem_ba ( HPS_DDR3_BA), // .mem_ba
.memory_mem_ck ( HPS_DDR3_CK_P), // .mem_ck
.memory_mem_ck_n ( HPS_DDR3_CK_N), // .mem_ck_n
.memory_mem_cke ( HPS_DDR3_CKE), // .mem_cke
.memory_mem_cs_n ( HPS_DDR3_CS_N), // .mem_cs_n
.memory_mem_ras_n ( HPS_DDR3_RAS_N), // .mem_ras_n
.memory_mem_cas_n ( HPS_DDR3_CAS_N), // .mem_cas_n
.memory_mem_we_n ( HPS_DDR3_WE_N), // .mem_we_n
.memory_mem_reset_n ( HPS_DDR3_RESET_N), // .mem_reset_n
.memory_mem_dq ( HPS_DDR3_DQ), // .mem_dq
.memory_mem_dqs ( HPS_DDR3_DQS_P), // .mem_dqs
.memory_mem_dqs_n ( HPS_DDR3_DQS_N), // .mem_dqs_n
.memory_mem_odt ( HPS_DDR3_ODT), // .mem_odt
.memory_mem_dm ( HPS_DDR3_DM), // .mem_dm
.memory_oct_rzqin ( HPS_DDR3_RZQ), // .oct_rzqin
.hps_0_hps_io_hps_io_emac1_inst_TX_CLK ( HPS_ENET_GTX_CLK), // hps_0_hps_io.hps_io_emac1_inst_TX_CLK
.hps_0_hps_io_hps_io_emac1_inst_TXD0 ( HPS_ENET_TX_DATA[0] ), // .hps_io_emac1_inst_TXD0
.hps_0_hps_io_hps_io_emac1_inst_TXD1 ( HPS_ENET_TX_DATA[1] ), // .hps_io_emac1_inst_TXD1
.hps_0_hps_io_hps_io_emac1_inst_TXD2 ( HPS_ENET_TX_DATA[2] ), // .hps_io_emac1_inst_TXD2
.hps_0_hps_io_hps_io_emac1_inst_TXD3 ( HPS_ENET_TX_DATA[3] ), // .hps_io_emac1_inst_TXD3
.hps_0_hps_io_hps_io_emac1_inst_RXD0 ( HPS_ENET_RX_DATA[0] ), // .hps_io_emac1_inst_RXD0
.hps_0_hps_io_hps_io_emac1_inst_MDIO ( HPS_ENET_MDIO ), // .hps_io_emac1_inst_MDIO
.hps_0_hps_io_hps_io_emac1_inst_MDC ( HPS_ENET_MDC ), // .hps_io_emac1_inst_MDC
.hps_0_hps_io_hps_io_emac1_inst_RX_CTL ( HPS_ENET_RX_DV), // .hps_io_emac1_inst_RX_CTL
.hps_0_hps_io_hps_io_emac1_inst_TX_CTL ( HPS_ENET_TX_EN), // .hps_io_emac1_inst_TX_CTL
.hps_0_hps_io_hps_io_emac1_inst_RX_CLK ( HPS_ENET_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_0_hps_io_hps_io_emac1_inst_RXD1 ( HPS_ENET_RX_DATA[1] ), // .hps_io_emac1_inst_RXD1
.hps_0_hps_io_hps_io_emac1_inst_RXD2 ( HPS_ENET_RX_DATA[2] ), // .hps_io_emac1_inst_RXD2
.hps_0_hps_io_hps_io_emac1_inst_RXD3 ( HPS_ENET_RX_DATA[3] ), // .hps_io_emac1_inst_RXD3
.hps_0_hps_io_hps_io_qspi_inst_IO0 ( HPS_FLASH_DATA[0] ), // .hps_io_qspi_inst_IO0
.hps_0_hps_io_hps_io_qspi_inst_IO1 ( HPS_FLASH_DATA[1] ), // .hps_io_qspi_inst_IO1
.hps_0_hps_io_hps_io_qspi_inst_IO2 ( HPS_FLASH_DATA[2] ), // .hps_io_qspi_inst_IO2
.hps_0_hps_io_hps_io_qspi_inst_IO3 ( HPS_FLASH_DATA[3] ), // .hps_io_qspi_inst_IO3
.hps_0_hps_io_hps_io_qspi_inst_SS0 ( HPS_FLASH_NCSO ), // .hps_io_qspi_inst_SS0
.hps_0_hps_io_hps_io_qspi_inst_CLK ( HPS_FLASH_DCLK ), // .hps_io_qspi_inst_CLK
.hps_0_hps_io_hps_io_sdio_inst_CMD ( HPS_SD_CMD ), // .hps_io_sdio_inst_CMD
.hps_0_hps_io_hps_io_sdio_inst_D0 ( HPS_SD_DATA[0] ), // .hps_io_sdio_inst_D0
.hps_0_hps_io_hps_io_sdio_inst_D1 ( HPS_SD_DATA[1] ), // .hps_io_sdio_inst_D1
.hps_0_hps_io_hps_io_sdio_inst_CLK ( HPS_SD_CLK ), // .hps_io_sdio_inst_CLK
.hps_0_hps_io_hps_io_sdio_inst_D2 ( HPS_SD_DATA[2] ), // .hps_io_sdio_inst_D2
.hps_0_hps_io_hps_io_sdio_inst_D3 ( HPS_SD_DATA[3] ), // .hps_io_sdio_inst_D3
.hps_0_hps_io_hps_io_usb1_inst_D0 ( HPS_USB_DATA[0] ), // .hps_io_usb1_inst_D0
.hps_0_hps_io_hps_io_usb1_inst_D1 ( HPS_USB_DATA[1] ), // .hps_io_usb1_inst_D1
.hps_0_hps_io_hps_io_usb1_inst_D2 ( HPS_USB_DATA[2] ), // .hps_io_usb1_inst_D2
.hps_0_hps_io_hps_io_usb1_inst_D3 ( HPS_USB_DATA[3] ), // .hps_io_usb1_inst_D3
.hps_0_hps_io_hps_io_usb1_inst_D4 ( HPS_USB_DATA[4] ), // .hps_io_usb1_inst_D4
.hps_0_hps_io_hps_io_usb1_inst_D5 ( HPS_USB_DATA[5] ), // .hps_io_usb1_inst_D5
.hps_0_hps_io_hps_io_usb1_inst_D6 ( HPS_USB_DATA[6] ), // .hps_io_usb1_inst_D6
.hps_0_hps_io_hps_io_usb1_inst_D7 ( HPS_USB_DATA[7] ), // .hps_io_usb1_inst_D7
.hps_0_hps_io_hps_io_usb1_inst_CLK ( HPS_USB_CLKOUT ), // .hps_io_usb1_inst_CLK
.hps_0_hps_io_hps_io_usb1_inst_STP ( HPS_USB_STP ), // .hps_io_usb1_inst_STP
.hps_0_hps_io_hps_io_usb1_inst_DIR ( HPS_USB_DIR ), // .hps_io_usb1_inst_DIR
.hps_0_hps_io_hps_io_usb1_inst_NXT ( HPS_USB_NXT ), // .hps_io_usb1_inst_NXT
.hps_0_hps_io_hps_io_spim1_inst_CLK ( HPS_SPIM_CLK ), // .hps_io_spim1_inst_CLK
.hps_0_hps_io_hps_io_spim1_inst_MOSI ( HPS_SPIM_MOSI ), // .hps_io_spim1_inst_MOSI
.hps_0_hps_io_hps_io_spim1_inst_MISO ( HPS_SPIM_MISO ), // .hps_io_spim1_inst_MISO
.hps_0_hps_io_hps_io_spim1_inst_SS0 ( HPS_SPIM_SS ), // .hps_io_spim1_inst_SS0
.hps_0_hps_io_hps_io_uart0_inst_RX ( HPS_UART_RX ), // .hps_io_uart0_inst_RX
.hps_0_hps_io_hps_io_uart0_inst_TX ( HPS_UART_TX ), // .hps_io_uart0_inst_TX
.hps_0_hps_io_hps_io_i2c0_inst_SDA ( HPS_I2C1_SDAT ), // .hps_io_i2c0_inst_SDA
.hps_0_hps_io_hps_io_i2c0_inst_SCL ( HPS_I2C1_SCLK ), // .hps_io_i2c0_inst_SCL
.hps_0_hps_io_hps_io_i2c1_inst_SDA ( HPS_I2C2_SDAT ), // .hps_io_i2c1_inst_SDA
.hps_0_hps_io_hps_io_i2c1_inst_SCL ( HPS_I2C2_SCLK ), // .hps_io_i2c1_inst_SCL
.hps_0_hps_io_hps_io_gpio_inst_GPIO09 ( HPS_CONV_USB_N), // .hps_io_gpio_inst_GPIO09
.hps_0_hps_io_hps_io_gpio_inst_GPIO35 ( HPS_ENET_INT_N), // .hps_io_gpio_inst_GPIO35
.hps_0_hps_io_hps_io_gpio_inst_GPIO40 ( HPS_LTC_GPIO), // .hps_io_gpio_inst_GPIO40
//.hps_0_hps_io_hps_io_gpio_inst_GPIO41 ( HPS_GPIO[1]), // .hps_io_gpio_inst_GPIO41
.hps_0_hps_io_hps_io_gpio_inst_GPIO48 ( HPS_I2C_CONTROL), // .hps_io_gpio_inst_GPIO48
.hps_0_hps_io_hps_io_gpio_inst_GPIO53 ( HPS_LED), // .hps_io_gpio_inst_GPIO53
.hps_0_hps_io_hps_io_gpio_inst_GPIO54 ( HPS_KEY), // .hps_io_gpio_inst_GPIO54
.hps_0_hps_io_hps_io_gpio_inst_GPIO61 ( HPS_GSENSOR_INT), // .hps_io_gpio_inst_GPIO61
// .led_pio_external_connection_export (LEDR), // led_pio_external_connection.export
.hps_0_h2f_reset_reset_n (1'b1), // hps_0_h2f_reset.reset_n
// .seg7_if_conduit_end_export ({HEX5P, HEX5, HEX4P, HEX4,
// HEX3P, HEX3, HEX2P, HEX2,
// HEX1P, HEX1, HEX0P, HEX0}), // seg7_if_conduit_end.export
.new_sdram_controller_0_wire_addr(DRAM_ADDR), // new_sdram_controller_0_wire.addr
.new_sdram_controller_0_wire_ba(DRAM_BA), // .ba
.new_sdram_controller_0_wire_cas_n(DRAM_CAS_N), // .cas_n
.new_sdram_controller_0_wire_cke(DRAM_CKE), // .cke
.new_sdram_controller_0_wire_cs_n(DRAM_CS_N), // .cs_n
.new_sdram_controller_0_wire_dq(DRAM_DQ), // .dq
.new_sdram_controller_0_wire_dqm({DRAM_LDQM, DRAM_UDQM}), // .dqm
.new_sdram_controller_0_wire_ras_n(DRAM_RAS_N), // .ras_n
.new_sdram_controller_0_wire_we_n(DRAM_WE_N), // .we_n
.sdram_clk_out_clk(DRAM_CLK),
.periph_subsystem_lcd_r(R), // periph_subsystem.lcd_r
.periph_subsystem_lcd_g(G), // .lcd_g
.periph_subsystem_lcd_b(B), // .lcd_b
.periph_subsystem_lcd_hsync(HSYNC), // .lcd_hsync
.periph_subsystem_lcd_vsync(VSYNC), // .lcd_vsync
.periph_subsystem_lcd_clk(LCD_CLK), // .lcd_clk
.periph_subsystem_lcd_de(DE),
.periph_subsystem_0_cam_conduit_camera_ref_clk(camera_xclk), // periph_subsystem_0_cam_conduit.camera_ref_clk
.periph_subsystem_0_cam_conduit_camera_vsync(camera_vsync), // .camera_vsync
.periph_subsystem_0_cam_conduit_camera_hsync(camera_href), // .camera_hsync
.periph_subsystem_0_cam_conduit_camera_pclk(camera_pclk), // .camera_pclk
.periph_subsystem_0_cam_conduit_camera_data(camera_data),
);
wire [7:0] R;
wire [7:0] G;
wire [7:0] B;
wire HSYNC;
wire VSYNC;
wire LCD_CLK;
reg DE = 0;
wire reset;
assign reset = KEY[0];
assign GPIO_1[7:0] = R[7:0];
assign GPIO_1[15:8] = G[7:0];
assign GPIO_1[23:16] = B[7:0];
assign GPIO_1[24] = HSYNC;
assign GPIO_1[25] = VSYNC;
assign GPIO_1[26] = LCD_CLK;
assign GPIO_1[27] = DE;
wire camera_vsync;
wire camera_href;
wire camera_xclk;
wire camera_pclk;
wire [7:0] camera_data;
wire camera_reset;
reg cam_clk_en = 1'b0;
assign camera_vsync = GPIO_0[23];
assign camera_href = GPIO_0[22];
assign camera_pclk = GPIO_0[21];
assign GPIO_0[20] = cam_clk_en == 1'b1 ? camera_xclk : 1'bz;
assign camera_data = GPIO_0[19:12];
assign GPIO_0[11] = 1'b0;
reg init_state;
wire init_ready;
wire init_ready_ex;
wire sda_oe;
wire sda;
wire sda_in;
wire scl;
camera_init u5
(
.clk(CLOCK_50),
.reset_n(KEY[0]),
.ready(init_ready),
.sda_oe(sda_oe),
.sda(sda),
.sda_in(sda_in),
.scl(scl)
);
assign GPIO_0[24] = sda_oe == 1'b1 ? sda : 1'bz;
assign sda_in = GPIO_0[24];
assign GPIO_0[25] = scl;
assign init_ready_ex = GPIO_0[8];
always@(posedge CLOCK_50)
begin
if(KEY[0] == 1'b0)
begin
init_state <= 0;
end
else
begin
case(init_state)
1'b0:
begin
cam_clk_en <= 1'b0;
if(init_ready == 1'b1 || init_ready_ex == 1'b1)
init_state <= 1'b1;
end
1'b1:
begin
init_state <= 1'b1;
cam_clk_en <= 1'b1;
end
default:
cam_clk_en <= 1'b0;
endcase
end
end
reg [19:0] frames_counter = 0;
always@(posedge camera_vsync or negedge KEY[0])
begin
if(KEY[0] == 1'b0)
frames_counter <= 0;
else
begin
if(frames_counter == 999999)
frames_counter <= 0;
else
frames_counter <= frames_counter + 1;
end
end
assign LEDR = frames_counter[9:0];
wire [3:0] seg1;
wire [3:0] seg2;
wire [3:0] seg3;
wire [3:0] seg4;
wire [3:0] seg5;
wire [3:0] seg6;
assign seg1 = frames_counter % 10;
assign seg2 = (frames_counter / 10) % 10;
assign seg3 = (frames_counter / 100) % 10;
assign seg4 = (frames_counter / 1000) % 10;
assign seg5 = (frames_counter / 10000) % 10;
assign seg6 = (frames_counter / 100000) % 10;
sev_seg_decoder hex0
(
.number(seg1),
.digit(HEX0)
);
sev_seg_decoder hex1
(
.number(seg2),
.digit(HEX1)
);
sev_seg_decoder hex2
(
.number(seg3),
.digit(HEX2)
);
sev_seg_decoder hex3
(
.number(seg4),
.digit(HEX3)
);
sev_seg_decoder hex4
(
.number(seg5),
.digit(HEX4)
);
sev_seg_decoder hex5
(
.number(seg6),
.digit(HEX5)
);
endmodule
|
/****************************************************************************
Register File
- Has two read ports (a and b) and one write port (c)
- sel chooses the register to be read/written
****************************************************************************/
module reg_file_spree(clk,resetn,
a_reg, a_readdataout, a_en,
b_reg, b_readdataout, b_en,
c_reg, c_writedatain, c_we);
parameter WIDTH=32;
parameter NUMREGS=32;
parameter LOG2NUMREGS=5;
input clk;
input resetn;
input a_en;
input b_en;
input [LOG2NUMREGS-1:0] a_reg,b_reg,c_reg;
output [WIDTH-1:0] a_readdataout, b_readdataout;
input [WIDTH-1:0] c_writedatain;
input c_we;
reg [WIDTH-1:0] a_readdataout, b_readdataout;
reg [31:0] rf [31:0];
always @(posedge clk) begin
if(a_en) begin
a_readdataout <= rf[a_reg];
end
if(b_en) begin
b_readdataout <= rf[b_reg];
end
if(c_we&(|c_reg)) begin
rf[c_reg] <= c_writedatain;
end
end
/*
altsyncram reg_file1(
.wren_a (c_we&(|c_reg)),
.clock0 (clk),
.clock1 (clk),
.clocken1 (a_en),
.address_a (c_reg[LOG2NUMREGS-1:0]),
.address_b (a_reg[LOG2NUMREGS-1:0]),
.data_a (c_writedatain),
.q_b (a_readdataout)
// synopsys translate_off
,
.aclr0 (1'b0),
.aclr1 (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.data_b (32'b11111111),
.wren_b (1'b0),
.rden_b(1'b1),
.q_a (),
.clocken0 (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0)
// synopsys translate_on
);
defparam
reg_file1.operation_mode = "DUAL_PORT",
reg_file1.width_a = WIDTH,
reg_file1.widthad_a = LOG2NUMREGS,
reg_file1.numwords_a = NUMREGS,
reg_file1.width_b = WIDTH,
reg_file1.widthad_b = LOG2NUMREGS,
reg_file1.numwords_b = NUMREGS,
reg_file1.lpm_type = "altsyncram",
reg_file1.width_byteena_a = 1,
reg_file1.outdata_reg_b = "UNREGISTERED",
reg_file1.indata_aclr_a = "NONE",
reg_file1.wrcontrol_aclr_a = "NONE",
reg_file1.address_aclr_a = "NONE",
reg_file1.rdcontrol_reg_b = "CLOCK1",
reg_file1.address_reg_b = "CLOCK1",
reg_file1.address_aclr_b = "NONE",
reg_file1.outdata_aclr_b = "NONE",
reg_file1.read_during_write_mode_mixed_ports = "OLD_DATA",
reg_file1.ram_block_type = "AUTO",
reg_file1.intended_device_family = "Stratix";
//Reg file duplicated to avoid contention between 2 read
//and 1 write
altsyncram reg_file2(
.wren_a (c_we&(|c_reg)),
.clock0 (clk),
.clock1 (clk),
.clocken1 (b_en),
.address_a (c_reg[LOG2NUMREGS-1:0]),
.address_b (b_reg[LOG2NUMREGS-1:0]),
.data_a (c_writedatain),
.q_b (b_readdataout)
// synopsys translate_off
,
.aclr0 (1'b0),
.aclr1 (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.data_b (32'b11111111),
.rden_b(1'b1),
.wren_b (1'b0),
.q_a (),
.clocken0 (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0)
// synopsys translate_on
);
defparam
reg_file2.operation_mode = "DUAL_PORT",
reg_file2.width_a = WIDTH,
reg_file2.widthad_a = LOG2NUMREGS,
reg_file2.numwords_a = NUMREGS,
reg_file2.width_b = WIDTH,
reg_file2.widthad_b = LOG2NUMREGS,
reg_file2.numwords_b = NUMREGS,
reg_file2.lpm_type = "altsyncram",
reg_file2.width_byteena_a = 1,
reg_file2.outdata_reg_b = "UNREGISTERED",
reg_file2.indata_aclr_a = "NONE",
reg_file2.wrcontrol_aclr_a = "NONE",
reg_file2.address_aclr_a = "NONE",
reg_file2.rdcontrol_reg_b = "CLOCK1",
reg_file2.address_reg_b = "CLOCK1",
reg_file2.address_aclr_b = "NONE",
reg_file2.outdata_aclr_b = "NONE",
reg_file2.read_during_write_mode_mixed_ports = "OLD_DATA",
reg_file2.ram_block_type = "AUTO",
reg_file2.intended_device_family = "Stratix";
*/
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2_BEHAVIORAL_V
`define SKY130_FD_SC_HD__MUX2_BEHAVIORAL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hd__mux2 (
X ,
A0,
A1,
S
);
// Module ports
output X ;
input A0;
input A1;
input S ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire mux_2to10_out_X;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S );
buf buf0 (X , mux_2to10_out_X);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2_BEHAVIORAL_V |
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.3
// \ \ Application : MIG
// / / Filename : dram_mig.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Tue Sept 21 2010
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR3 SDRAM
// Purpose :
// Top-level module. This module can be instantiated in the
// system and interconnect as shown in user design wrapper file (user top module).
// In addition to the memory controller, the module instantiates:
// 1. Clock generation/distribution, reset logic
// 2. IDELAY control block
// 3. Debug logic
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module dram_mig #
(
//***************************************************************************
// The following parameters refer to width of various ports
//***************************************************************************
parameter BANK_WIDTH = 3,
// # of memory Bank Address bits.
parameter CK_WIDTH = 1,
// # of CK/CK# outputs to memory.
parameter COL_WIDTH = 10,
// # of memory Column Address bits.
parameter CS_WIDTH = 1,
// # of unique CS outputs to memory.
parameter nCS_PER_RANK = 1,
// # of unique CS outputs per rank for phy
parameter CKE_WIDTH = 1,
// # of CKE outputs to memory.
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter DQ_CNT_WIDTH = 6,
// = ceil(log2(DQ_WIDTH))
parameter DQ_PER_DM = 8,
parameter DM_WIDTH = 8,
// # of DM (data mask)
parameter DQ_WIDTH = 64,
// # of DQ (data)
parameter DQS_WIDTH = 8,
parameter DQS_CNT_WIDTH = 3,
// = ceil(log2(DQS_WIDTH))
parameter DRAM_WIDTH = 8,
// # of DQ per DQS
parameter ECC = "OFF",
parameter DATA_WIDTH = 64,
parameter ECC_TEST = "OFF",
parameter PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
//Possible Parameters
//1.BANK_ROW_COLUMN : Address mapping is
// in form of Bank Row Column.
//2.ROW_BANK_COLUMN : Address mapping is
// in the form of Row Bank Column.
//3.TG_TEST : Scrambles Address bits
// for distributed Addressing.
parameter nBANK_MACHS = 4,
parameter RANKS = 1,
// # of Ranks.
parameter ODT_WIDTH = 1,
// # of ODT outputs to memory.
parameter ROW_WIDTH = 16,
// # of memory Row Address bits.
parameter ADDR_WIDTH = 30,
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
// Chip Select is always tied to low for
// single rank devices
parameter USE_CS_PORT = 1,
// # = 1, When Chip Select (CS#) output is enabled
// = 0, When Chip Select (CS#) output is disabled
// If CS_N disabled, user must connect
// DRAM CS_N input(s) to ground
parameter USE_DM_PORT = 1,
// # = 1, When Data Mask option is enabled
// = 0, When Data Mask option is disbaled
// When Data Mask option is disabled in
// MIG Controller Options page, the logic
// related to Data Mask should not get
// synthesized
parameter USE_ODT_PORT = 1,
// # = 1, When ODT output is enabled
// = 0, When ODT output is disabled
// Parameter configuration for Dynamic ODT support:
// USE_ODT_PORT = 0, RTT_NOM = "DISABLED", RTT_WR = "60/120".
// This configuration allows to save ODT pin mapping from FPGA.
// The user can tie the ODT input of DRAM to HIGH.
parameter IS_CLK_SHARED = "FALSE",
// # = "true" when clock is shared
// = "false" when clock is not shared
parameter PHY_CONTROL_MASTER_BANK = 1,
// The bank index where master PHY_CONTROL resides,
// equal to the PLL residing bank
parameter MEM_DENSITY = "4Gb",
// Indicates the density of the Memory part
// Added for the sake of Vivado simulations
parameter MEM_SPEEDGRADE = "125",
// Indicates the Speed grade of Memory Part
// Added for the sake of Vivado simulations
parameter MEM_DEVICE_WIDTH = 8,
// Indicates the device width of the Memory Part
// Added for the sake of Vivado simulations
//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
parameter AL = "0",
// DDR3 SDRAM:
// Additive Latency (Mode Register 1).
// # = "0", "CL-1", "CL-2".
// DDR2 SDRAM:
// Additive Latency (Extended Mode Register).
parameter nAL = 0,
// # Additive Latency in number of clock
// cycles.
parameter BURST_MODE = "8",
// DDR3 SDRAM:
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
// DDR2 SDRAM:
// Burst Length (Mode Register).
// # = "8", "4".
parameter BURST_TYPE = "SEQ",
// DDR3 SDRAM: Burst Type (Mode Register 0).
// DDR2 SDRAM: Burst Type (Mode Register).
// # = "SEQ" - (Sequential),
// = "INT" - (Interleaved).
parameter CL = 11,
// in number of clock cycles
// DDR3 SDRAM: CAS Latency (Mode Register 0).
// DDR2 SDRAM: CAS Latency (Mode Register).
parameter CWL = 8,
// in number of clock cycles
// DDR3 SDRAM: CAS Write Latency (Mode Register 2).
// DDR2 SDRAM: Can be ignored
parameter OUTPUT_DRV = "HIGH",
// Output Driver Impedance Control (Mode Register 1).
// # = "HIGH" - RZQ/7,
// = "LOW" - RZQ/6.
parameter RTT_NOM = "40",
// RTT_NOM (ODT) (Mode Register 1).
// = "120" - RZQ/2,
// = "60" - RZQ/4,
// = "40" - RZQ/6.
parameter RTT_WR = "OFF",
// RTT_WR (ODT) (Mode Register 2).
// # = "OFF" - Dynamic ODT off,
// = "120" - RZQ/2,
// = "60" - RZQ/4,
parameter ADDR_CMD_MODE = "1T" ,
// # = "1T", "2T".
parameter REG_CTRL = "OFF",
// # = "ON" - RDIMMs,
// = "OFF" - Components, SODIMMs, UDIMMs.
parameter CA_MIRROR = "OFF",
// C/A mirror opt for DDR3 dual rank
parameter VDD_OP_VOLT = "150",
// # = "150" - 1.5V Vdd Memory part
// = "135" - 1.35V Vdd Memory part
//***************************************************************************
// The following parameters are multiplier and divisor factors for PLLE2.
// Based on the selected design frequency these parameters vary.
//***************************************************************************
parameter CLKIN_PERIOD = 5000,
// Input Clock Period
parameter CLKFBOUT_MULT = 8,
// write PLL VCO multiplier
parameter DIVCLK_DIVIDE = 1,
// write PLL VCO divisor
parameter CLKOUT0_PHASE = 337.5,
// Phase for PLL output clock (CLKOUT0)
parameter CLKOUT0_DIVIDE = 2,
// VCO output divisor for PLL output clock (CLKOUT0)
parameter CLKOUT1_DIVIDE = 2,
// VCO output divisor for PLL output clock (CLKOUT1)
parameter CLKOUT2_DIVIDE = 32,
// VCO output divisor for PLL output clock (CLKOUT2)
parameter CLKOUT3_DIVIDE = 8,
// VCO output divisor for PLL output clock (CLKOUT3)
parameter MMCM_VCO = 800,
// Max Freq (MHz) of MMCM VCO
parameter MMCM_MULT_F = 4,
// write MMCM VCO multiplier
parameter MMCM_DIVCLK_DIVIDE = 1,
// write MMCM VCO divisor
//***************************************************************************
// Memory Timing Parameters. These parameters varies based on the selected
// memory part.
//***************************************************************************
parameter tCKE = 5000,
// memory tCKE paramter in pS
parameter tFAW = 32000,
// memory tRAW paramter in pS.
parameter tPRDI = 1_000_000,
// memory tPRDI paramter in pS.
parameter tRAS = 35000,
// memory tRAS paramter in pS.
parameter tRCD = 13750,
// memory tRCD paramter in pS.
parameter tREFI = 7800000,
// memory tREFI paramter in pS.
parameter tRFC = 260000,
// memory tRFC paramter in pS.
parameter tRP = 13750,
// memory tRP paramter in pS.
parameter tRRD = 6000,
// memory tRRD paramter in pS.
parameter tRTP = 7500,
// memory tRTP paramter in pS.
parameter tWTR = 7500,
// memory tWTR paramter in pS.
parameter tZQI = 128_000_000,
// memory tZQI paramter in nS.
parameter tZQCS = 64,
// memory tZQCS paramter in clock cycles.
//***************************************************************************
// Simulation parameters
//***************************************************************************
parameter SIM_BYPASS_INIT_CAL = "OFF",
// # = "OFF" - Complete memory init &
// calibration sequence
// # = "SKIP" - Not supported
// # = "FAST" - Complete memory init & use
// abbreviated calib sequence
parameter SIMULATION = "FALSE",
// Should be TRUE during design simulations and
// FALSE during implementations
//***************************************************************************
// The following parameters varies based on the pin out entered in MIG GUI.
// Do not change any of these parameters directly by editing the RTL.
// Any changes required should be done through GUI and the design regenerated.
//***************************************************************************
parameter BYTE_LANES_B0 = 4'b1111,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B1 = 4'b1110,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B2 = 4'b1111,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B3 = 4'b0000,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B4 = 4'b0000,
// Byte lanes used in an IO column.
parameter DATA_CTL_B0 = 4'b1111,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B1 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B2 = 4'b1111,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B3 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B4 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter PHY_0_BITLANES = 48'h3FE_1FF_1FF_2FF,
parameter PHY_1_BITLANES = 48'hFFE_FF0_CB4_000,
parameter PHY_2_BITLANES = 48'h3FE_3FE_3BF_2FF,
// control/address/data pin mapping parameters
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_11,
parameter ADDR_MAP
= 192'h126_127_132_136_135_133_139_124_131_129_137_134_13A_128_138_13B,
parameter BANK_MAP = 36'h125_12A_12B,
parameter CAS_MAP = 12'h115,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_117,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_112,
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_114,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h11A,
parameter WE_MAP = 12'h11B,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_20_21_22_23_03_02_01_00,
parameter DATA0_MAP = 96'h009_000_003_001_007_006_005_002,
parameter DATA1_MAP = 96'h014_018_010_011_017_016_012_013,
parameter DATA2_MAP = 96'h021_022_025_020_027_023_026_028,
parameter DATA3_MAP = 96'h033_039_031_035_032_038_034_037,
parameter DATA4_MAP = 96'h231_238_237_236_233_232_234_239,
parameter DATA5_MAP = 96'h226_227_225_229_221_222_224_228,
parameter DATA6_MAP = 96'h214_215_210_218_217_213_219_212,
parameter DATA7_MAP = 96'h207_203_204_206_202_201_205_209,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter MASK0_MAP = 108'h000_200_211_223_235_036_024_015_004,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter SLOT_0_CONFIG = 8'b0000_0001,
// Mapping of Ranks.
parameter SLOT_1_CONFIG = 8'b0000_0000,
// Mapping of Ranks.
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter IBUF_LPWR_MODE = "OFF",
// to phy_top
parameter DATA_IO_IDLE_PWRDWN = "ON",
// # = "ON", "OFF"
parameter BANK_TYPE = "HP_IO",
// # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "HP_LP",
// # = "HP_LP", "HR_LP", "DEFAULT"
parameter CKE_ODT_AUX = "FALSE",
parameter USER_REFRESH = "OFF",
parameter WRLVL = "ON",
// # = "ON" - DDR3 SDRAM
// = "OFF" - DDR2 SDRAM.
parameter ORDERING = "NORM",
// # = "NORM", "STRICT", "RELAXED".
parameter CALIB_ROW_ADD = 16'h0000,
// Calibration row address will be used for
// calibration read and write operations
parameter CALIB_COL_ADD = 12'h000,
// Calibration column address will be used for
// calibration read and write operations
parameter CALIB_BA_ADD = 3'h0,
// Calibration bank address will be used for
// calibration read and write operations
parameter TCQ = 100,
parameter IDELAY_ADJ = "ON",
parameter FINE_PER_BIT = "ON",
parameter CENTER_COMP_MODE = "ON",
parameter PI_VAL_ADJ = "ON",
parameter IODELAY_GRP0 = "DRAM_IODELAY_MIG0",
// It is associated to a set of IODELAYs with
// an IDELAYCTRL that have same IODELAY CONTROLLER
// clock frequency (200MHz).
parameter IODELAY_GRP1 = "DRAM_IODELAY_MIG1",
// It is associated to a set of IODELAYs with
// an IDELAYCTRL that have same IODELAY CONTROLLER
// clock frequency (300MHz/400MHz).
parameter SYSCLK_TYPE = "DIFFERENTIAL",
// System clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER
parameter REFCLK_TYPE = "USE_SYSTEM_CLOCK",
// Reference clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER, USE_SYSTEM_CLOCK
// parameter SYS_RST_PORT = "TRUE",
parameter SYS_RST_PORT = "FALSE",
// "TRUE" - if pin is selected for sys_rst
// and IBUF will be instantiated.
// "FALSE" - if pin is not selected for sys_rst
parameter FPGA_SPEED_GRADE = 2,
// FPGA speed grade
parameter CMD_PIPE_PLUS1 = "ON",
// add pipeline stage between MC and PHY
parameter DRAM_TYPE = "DDR3",
parameter CAL_WIDTH = "HALF",
parameter STARVE_LIMIT = 2,
// # = 2,3,4.
parameter REF_CLK_MMCM_IODELAY_CTRL = "TRUE",
//***************************************************************************
// Referece clock frequency parameters
//***************************************************************************
parameter REFCLK_FREQ = 200.0,
// IODELAYCTRL reference clock frequency
parameter DIFF_TERM_REFCLK = "TRUE",
// Differential Termination for idelay
// reference clock input pins
//***************************************************************************
// System clock frequency parameters
//***************************************************************************
parameter tCK = 1250,
// memory tCK paramter.
// # = Clock Period in pS.
parameter nCK_PER_CLK = 4,
// # of memory CKs per fabric CLK
parameter DIFF_TERM_SYSCLK = "FALSE",
// Differential Termination for System
// clock input pins
//***************************************************************************
// Debug parameters
//***************************************************************************
parameter DEBUG_PORT = "OFF",
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
//***************************************************************************
// Temparature monitor parameter
//***************************************************************************
parameter TEMP_MON_CONTROL = "INTERNAL",
// # = "INTERNAL", "EXTERNAL"
parameter RST_ACT_LOW = 0
// =1 for active low reset,
// =0 for active high.
)
(
// Inouts
inout [DQ_WIDTH-1:0] ddr3_dq,
inout [DQS_WIDTH-1:0] ddr3_dqs_n,
inout [DQS_WIDTH-1:0] ddr3_dqs_p,
// Outputs
output [ROW_WIDTH-1:0] ddr3_addr,
output [BANK_WIDTH-1:0] ddr3_ba,
output ddr3_ras_n,
output ddr3_cas_n,
output ddr3_we_n,
output ddr3_reset_n,
output [CK_WIDTH-1:0] ddr3_ck_p,
output [CK_WIDTH-1:0] ddr3_ck_n,
output [CKE_WIDTH-1:0] ddr3_cke,
output [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n,
output [DM_WIDTH-1:0] ddr3_dm,
output [ODT_WIDTH-1:0] ddr3_odt,
// Inputs
// Differential system clocks
input sys_clk_p,
input sys_clk_n,
// user interface signals
input [ADDR_WIDTH-1:0] app_addr,
input [2:0] app_cmd,
input app_en,
input [(nCK_PER_CLK*2*PAYLOAD_WIDTH)-1:0] app_wdf_data,
input app_wdf_end,
input [((nCK_PER_CLK*2*PAYLOAD_WIDTH)/8)-1:0] app_wdf_mask,
input app_wdf_wren,
output [(nCK_PER_CLK*2*PAYLOAD_WIDTH)-1:0] app_rd_data,
output app_rd_data_end,
output app_rd_data_valid,
output app_rdy,
output app_wdf_rdy,
input app_sr_req,
input app_ref_req,
input app_zq_req,
output app_sr_active,
output app_ref_ack,
output app_zq_ack,
output ui_clk,
output ui_clk_sync_rst,
output init_calib_complete,
// System reset - Default polarity of sys_rst pin is Active Low.
// System reset polarity will change based on the option
// selected in GUI.
input sys_rst
);
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam BM_CNT_WIDTH = clogb2(nBANK_MACHS);
localparam RANK_WIDTH = clogb2(RANKS);
localparam ECC_WIDTH = (ECC == "OFF")?
0 : (DATA_WIDTH <= 4)?
4 : (DATA_WIDTH <= 10)?
5 : (DATA_WIDTH <= 26)?
6 : (DATA_WIDTH <= 57)?
7 : (DATA_WIDTH <= 120)?
8 : (DATA_WIDTH <= 247)?
9 : 10;
localparam DATA_BUF_OFFSET_WIDTH = 1;
localparam MC_ERR_ADDR_WIDTH = ((CS_WIDTH == 1) ? 0 : RANK_WIDTH)
+ BANK_WIDTH + ROW_WIDTH + COL_WIDTH
+ DATA_BUF_OFFSET_WIDTH;
localparam APP_DATA_WIDTH = 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
localparam TEMP_MON_EN = (SIMULATION == "FALSE") ? "ON" : "OFF";
// Enable or disable the temp monitor module
localparam tTEMPSAMPLE = 10000000; // sample every 10 us
localparam XADC_CLK_PERIOD = 5000; // Use 200 MHz IODELAYCTRL clock
localparam TAPSPERKCLK = (56*MMCM_MULT_F)/nCK_PER_CLK;
// Wire declarations
wire [BM_CNT_WIDTH-1:0] bank_mach_next;
wire clk;
wire [1:0] clk_ref;
wire [1:0] iodelay_ctrl_rdy;
wire clk_ref_in;
wire sys_rst_o;
wire freq_refclk ;
wire mem_refclk ;
wire pll_lock ;
wire sync_pulse;
wire mmcm_ps_clk;
wire poc_sample_pd;
wire psen;
wire psincdec;
wire psdone;
wire iddr_rst;
wire ref_dll_lock;
wire rst_phaser_ref;
wire pll_locked;
wire rst;
wire [(2*nCK_PER_CLK)-1:0] app_ecc_multiple_err;
wire ddr3_parity;
wire sys_clk_i;
wire mmcm_clk;
wire clk_ref_p;
wire clk_ref_n;
wire clk_ref_i;
wire [11:0] device_temp;
wire [11:0] device_temp_i;
// Debug port signals
wire dbg_idel_down_all;
wire dbg_idel_down_cpt;
wire dbg_idel_up_all;
wire dbg_idel_up_cpt;
wire dbg_sel_all_idel_cpt;
wire [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt;
wire dbg_sel_pi_incdec;
wire [DQS_CNT_WIDTH:0] dbg_byte_sel;
wire dbg_pi_f_inc;
wire dbg_pi_f_dec;
wire [5:0] dbg_pi_counter_read_val;
wire [8:0] dbg_po_counter_read_val;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_tap_cnt;
wire [(5*DQS_WIDTH*RANKS)-1:0] dbg_dq_idelay_tap_cnt;
wire [255:0] dbg_calib_top;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_first_edge_cnt;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_second_edge_cnt;
wire [(6*RANKS)-1:0] dbg_rd_data_offset;
wire [255:0] dbg_phy_rdlvl;
wire [99:0] dbg_phy_wrcal;
wire [(6*DQS_WIDTH)-1:0] dbg_final_po_fine_tap_cnt;
wire [(3*DQS_WIDTH)-1:0] dbg_final_po_coarse_tap_cnt;
wire [255:0] dbg_phy_wrlvl;
wire [255:0] dbg_phy_init;
wire [255:0] dbg_prbs_rdlvl;
wire [255:0] dbg_dqs_found_cal;
wire dbg_pi_phaselock_start;
wire dbg_pi_phaselocked_done;
wire dbg_pi_phaselock_err;
wire dbg_pi_dqsfound_start;
wire dbg_pi_dqsfound_done;
wire dbg_pi_dqsfound_err;
wire dbg_wrcal_start;
wire dbg_wrcal_done;
wire dbg_wrcal_err;
wire [11:0] dbg_pi_dqs_found_lanes_phy4lanes;
wire [11:0] dbg_pi_phase_locked_phy4lanes;
wire dbg_oclkdelay_calib_start;
wire dbg_oclkdelay_calib_done;
wire [255:0] dbg_phy_oclkdelay_cal;
wire [(DRAM_WIDTH*16)-1:0] dbg_oclkdelay_rd_data;
wire [DQS_WIDTH-1:0] dbg_rd_data_edge_detect;
wire [(2*nCK_PER_CLK*DQ_WIDTH)-1:0] dbg_rddata;
wire dbg_rddata_valid;
wire [1:0] dbg_rdlvl_done;
wire [1:0] dbg_rdlvl_err;
wire [1:0] dbg_rdlvl_start;
wire [(6*DQS_WIDTH)-1:0] dbg_wrlvl_fine_tap_cnt;
wire [(3*DQS_WIDTH)-1:0] dbg_wrlvl_coarse_tap_cnt;
wire [5:0] dbg_tap_cnt_during_wrlvl;
wire dbg_wl_edge_detect_valid;
wire dbg_wrlvl_done;
wire dbg_wrlvl_err;
wire dbg_wrlvl_start;
reg [63:0] dbg_rddata_r;
reg dbg_rddata_valid_r;
wire [53:0] ocal_tap_cnt;
wire [4:0] dbg_dqs;
wire [8:0] dbg_bit;
wire [8:0] rd_data_edge_detect_r;
wire [53:0] wl_po_fine_cnt;
wire [26:0] wl_po_coarse_cnt;
wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_1;
wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_2;
wire [5:0] dbg_data_offset;
wire [5:0] dbg_data_offset_1;
wire [5:0] dbg_data_offset_2;
wire [390:0] ddr3_ila_wrpath_int;
wire [1023:0] ddr3_ila_rdpath_int;
wire [119:0] ddr3_ila_basic_int;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_final_dqs_tap_cnt_r_int;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_first_edge_taps_int;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_second_edge_taps_int;
//***************************************************************************
assign ui_clk = clk;
assign ui_clk_sync_rst = rst;
assign sys_clk_i = 1'b0;
assign clk_ref_i = 1'b0;
generate
if (REFCLK_TYPE == "USE_SYSTEM_CLOCK")
assign clk_ref_in = mmcm_clk;
else
assign clk_ref_in = clk_ref_i;
endgenerate
mig_7series_v2_3_iodelay_ctrl #
(
.TCQ (TCQ),
.IODELAY_GRP0 (IODELAY_GRP0),
.IODELAY_GRP1 (IODELAY_GRP1),
.REFCLK_TYPE (REFCLK_TYPE),
.SYSCLK_TYPE (SYSCLK_TYPE),
.SYS_RST_PORT (SYS_RST_PORT),
.RST_ACT_LOW (RST_ACT_LOW),
.DIFF_TERM_REFCLK (DIFF_TERM_REFCLK),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.REF_CLK_MMCM_IODELAY_CTRL (REF_CLK_MMCM_IODELAY_CTRL)
)
u_iodelay_ctrl
(
// Outputs
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
.sys_rst_o (sys_rst_o),
.clk_ref (clk_ref),
// Inputs
.clk_ref_p (clk_ref_p),
.clk_ref_n (clk_ref_n),
.clk_ref_i (clk_ref_in),
.sys_rst (sys_rst)
);
mig_7series_v2_3_clk_ibuf #
(
.SYSCLK_TYPE (SYSCLK_TYPE),
.DIFF_TERM_SYSCLK (DIFF_TERM_SYSCLK)
)
u_ddr3_clk_ibuf
(
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.sys_clk_i (sys_clk_i),
.mmcm_clk (mmcm_clk)
);
// Temperature monitoring logic
generate
if (TEMP_MON_EN == "ON") begin: temp_mon_enabled
mig_7series_v2_3_tempmon #
(
.TCQ (TCQ),
.TEMP_MON_CONTROL (TEMP_MON_CONTROL),
.XADC_CLK_PERIOD (XADC_CLK_PERIOD),
.tTEMPSAMPLE (tTEMPSAMPLE)
)
u_tempmon
(
.clk (clk),
.xadc_clk (clk_ref[0]),
.rst (rst),
.device_temp_i (device_temp_i),
.device_temp (device_temp)
);
end else begin: temp_mon_disabled
assign device_temp = 'b0;
end
endgenerate
mig_7series_v2_3_infrastructure #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLKIN_PERIOD (CLKIN_PERIOD),
.SYSCLK_TYPE (SYSCLK_TYPE),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKOUT0_PHASE (CLKOUT0_PHASE),
.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.MMCM_VCO (MMCM_VCO),
.MMCM_MULT_F (MMCM_MULT_F),
.MMCM_DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE),
.RST_ACT_LOW (RST_ACT_LOW),
.tCK (tCK),
.MEM_TYPE (DRAM_TYPE)
)
u_ddr3_infrastructure
(
// Outputs
.rstdiv0 (rst),
.clk (clk),
.mem_refclk (mem_refclk),
.freq_refclk (freq_refclk),
.sync_pulse (sync_pulse),
.mmcm_ps_clk (mmcm_ps_clk),
.poc_sample_pd (poc_sample_pd),
.psdone (psdone),
.iddr_rst (iddr_rst),
.auxout_clk (),
.ui_addn_clk_0 (),
.ui_addn_clk_1 (),
.ui_addn_clk_2 (),
.ui_addn_clk_3 (),
.ui_addn_clk_4 (),
.pll_locked (pll_locked),
.mmcm_locked (),
.rst_phaser_ref (rst_phaser_ref),
// Inputs
.psen (psen),
.psincdec (psincdec),
.mmcm_clk (mmcm_clk),
.sys_rst (sys_rst_o),
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
.ref_dll_lock (ref_dll_lock)
);
mig_7series_v2_3_memc_ui_top_std #
(
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.AL (AL),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CA_MIRROR (CA_MIRROR),
.DDR3_VDD_OP_VOLT (VDD_OP_VOLT),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DM_WIDTH (DM_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.ECC_TEST (ECC_TEST),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.nAL (nAL),
.nBANK_MACHS (nBANK_MACHS),
.CKE_ODT_AUX (CKE_ODT_AUX),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.IODELAY_GRP0 (IODELAY_GRP0),
.IODELAY_GRP1 (IODELAY_GRP1),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.CL (CL),
.CWL (CWL),
.tCK (tCK),
.tCKE (tCKE),
.tFAW (tFAW),
.tPRDI (tPRDI),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.USER_REFRESH (USER_REFRESH),
.TEMP_MON_EN (TEMP_MON_EN),
.WRLVL (WRLVL),
.DEBUG_PORT (DEBUG_PORT),
.CAL_WIDTH (CAL_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.IDELAY_ADJ (IDELAY_ADJ),
.FINE_PER_BIT (FINE_PER_BIT),
.CENTER_COMP_MODE (CENTER_COMP_MODE),
.PI_VAL_ADJ (PI_VAL_ADJ),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER),
.STARVE_LIMIT (STARVE_LIMIT),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.MASTER_PHY_CTL (PHY_CONTROL_MASTER_BANK),
.TAPSPERKCLK (TAPSPERKCLK)
)
u_memc_ui_top_std
(
.clk (clk),
.clk_ref (clk_ref),
.mem_refclk (mem_refclk), //memory clock
.freq_refclk (freq_refclk),
.pll_lock (pll_locked),
.sync_pulse (sync_pulse),
.mmcm_ps_clk (mmcm_ps_clk),
.poc_sample_pd (poc_sample_pd),
.psdone (psdone),
.iddr_rst (iddr_rst),
.psen (psen),
.psincdec (psincdec),
.rst (rst),
.rst_phaser_ref (rst_phaser_ref),
.ref_dll_lock (ref_dll_lock),
// Memory interface ports
.ddr_dq (ddr3_dq),
.ddr_dqs_n (ddr3_dqs_n),
.ddr_dqs (ddr3_dqs_p),
.ddr_addr (ddr3_addr),
.ddr_ba (ddr3_ba),
.ddr_cas_n (ddr3_cas_n),
.ddr_ck_n (ddr3_ck_n),
.ddr_ck (ddr3_ck_p),
.ddr_cke (ddr3_cke),
.ddr_cs_n (ddr3_cs_n),
.ddr_dm (ddr3_dm),
.ddr_odt (ddr3_odt),
.ddr_ras_n (ddr3_ras_n),
.ddr_reset_n (ddr3_reset_n),
.ddr_parity (ddr3_parity),
.ddr_we_n (ddr3_we_n),
.bank_mach_next (bank_mach_next),
// Application interface ports
.app_addr (app_addr),
.app_cmd (app_cmd),
.app_en (app_en),
.app_hi_pri (1'b0),
.app_wdf_data (app_wdf_data),
.app_wdf_end (app_wdf_end),
.app_wdf_mask (app_wdf_mask),
.app_wdf_wren (app_wdf_wren),
.app_ecc_multiple_err (app_ecc_multiple_err),
.app_rd_data (app_rd_data),
.app_rd_data_end (app_rd_data_end),
.app_rd_data_valid (app_rd_data_valid),
.app_rdy (app_rdy),
.app_wdf_rdy (app_wdf_rdy),
.app_sr_req (app_sr_req),
.app_sr_active (app_sr_active),
.app_ref_req (app_ref_req),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.app_zq_ack (app_zq_ack),
.app_raw_not_ecc ({2*nCK_PER_CLK{1'b0}}),
.app_correct_en_i (1'b1),
.device_temp (device_temp),
// Debug logic ports
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_sel_pi_incdec (dbg_sel_pi_incdec),
.dbg_sel_po_incdec (dbg_sel_po_incdec),
.dbg_byte_sel (dbg_byte_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_rd_data_offset (dbg_rd_data_offset),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rddata_valid (dbg_rddata_valid),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_phy_wrlvl (dbg_phy_wrlvl),
.dbg_phy_init (dbg_phy_init),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.dbg_pi_counter_read_val (dbg_pi_counter_read_val),
.dbg_po_counter_read_val (dbg_po_counter_read_val),
.dbg_prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r_int),
.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps_int),
.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps_int),
.dbg_pi_phaselock_start (dbg_pi_phaselock_start),
.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done),
.dbg_pi_phaselock_err (dbg_pi_phaselock_err),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1),
.dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2),
.dbg_data_offset (dbg_data_offset),
.dbg_data_offset_1 (dbg_data_offset_1),
.dbg_data_offset_2 (dbg_data_offset_2),
.dbg_wrcal_start (dbg_wrcal_start),
.dbg_wrcal_done (dbg_wrcal_done),
.dbg_wrcal_err (dbg_wrcal_err),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done),
.dbg_dqs_found_cal (dbg_dqs_found_cal),
.init_calib_complete (init_calib_complete)
);
//*********************************************************************
// Resetting all RTL debug inputs as the debug ports are not enabled
//*********************************************************************
assign dbg_idel_down_all = 1'b0;
assign dbg_idel_down_cpt = 1'b0;
assign dbg_idel_up_all = 1'b0;
assign dbg_idel_up_cpt = 1'b0;
assign dbg_sel_all_idel_cpt = 1'b0;
assign dbg_sel_idel_cpt = 'b0;
assign dbg_byte_sel = 'd0;
assign dbg_sel_pi_incdec = 1'b0;
assign dbg_pi_f_inc = 1'b0;
assign dbg_pi_f_dec = 1'b0;
assign dbg_po_f_inc = 'b0;
assign dbg_po_f_dec = 'b0;
assign dbg_po_f_stg23_sel = 'b0;
assign dbg_sel_po_incdec = 'b0;
endmodule
|
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_reset O 1 const
// av_read O 32
// RDY_av_read O 1
// RDY_write O 1
// master_awvalid O 1 reg
// master_awid O 16 reg
// master_awaddr O 64 reg
// master_awlen O 8 reg
// master_awsize O 3 reg
// master_awburst O 2 reg
// master_awlock O 1 reg
// master_awcache O 4 reg
// master_awprot O 3 reg
// master_awqos O 4 reg
// master_awregion O 4 reg
// master_wvalid O 1 reg
// master_wdata O 64 reg
// master_wstrb O 8 reg
// master_wlast O 1 reg
// master_bready O 1 reg
// master_arvalid O 1 reg
// master_arid O 16 reg
// master_araddr O 64 reg
// master_arlen O 8 reg
// master_arsize O 3 reg
// master_arburst O 2 reg
// master_arlock O 1 reg
// master_arcache O 4 reg
// master_arprot O 3 reg
// master_arqos O 4 reg
// master_arregion O 4 reg
// master_rready O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// av_read_dm_addr I 7
// write_dm_addr I 7
// write_dm_word I 32
// master_awready I 1
// master_wready I 1
// master_bvalid I 1
// master_bid I 16 reg
// master_bresp I 2 reg
// master_arready I 1
// master_rvalid I 1
// master_rid I 16 reg
// master_rdata I 64 reg
// master_rresp I 2 reg
// master_rlast I 1 reg
// EN_reset I 1
// EN_write I 1
// EN_av_read I 1
//
// Combinational paths from inputs to outputs:
// av_read_dm_addr -> av_read
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkDM_System_Bus(CLK,
RST_N,
EN_reset,
RDY_reset,
av_read_dm_addr,
EN_av_read,
av_read,
RDY_av_read,
write_dm_addr,
write_dm_word,
EN_write,
RDY_write,
master_awvalid,
master_awid,
master_awaddr,
master_awlen,
master_awsize,
master_awburst,
master_awlock,
master_awcache,
master_awprot,
master_awqos,
master_awregion,
master_awready,
master_wvalid,
master_wdata,
master_wstrb,
master_wlast,
master_wready,
master_bvalid,
master_bid,
master_bresp,
master_bready,
master_arvalid,
master_arid,
master_araddr,
master_arlen,
master_arsize,
master_arburst,
master_arlock,
master_arcache,
master_arprot,
master_arqos,
master_arregion,
master_arready,
master_rvalid,
master_rid,
master_rdata,
master_rresp,
master_rlast,
master_rready);
input CLK;
input RST_N;
// action method reset
input EN_reset;
output RDY_reset;
// actionvalue method av_read
input [6 : 0] av_read_dm_addr;
input EN_av_read;
output [31 : 0] av_read;
output RDY_av_read;
// action method write
input [6 : 0] write_dm_addr;
input [31 : 0] write_dm_word;
input EN_write;
output RDY_write;
// value method master_m_awvalid
output master_awvalid;
// value method master_m_awid
output [15 : 0] master_awid;
// value method master_m_awaddr
output [63 : 0] master_awaddr;
// value method master_m_awlen
output [7 : 0] master_awlen;
// value method master_m_awsize
output [2 : 0] master_awsize;
// value method master_m_awburst
output [1 : 0] master_awburst;
// value method master_m_awlock
output master_awlock;
// value method master_m_awcache
output [3 : 0] master_awcache;
// value method master_m_awprot
output [2 : 0] master_awprot;
// value method master_m_awqos
output [3 : 0] master_awqos;
// value method master_m_awregion
output [3 : 0] master_awregion;
// value method master_m_awuser
// action method master_m_awready
input master_awready;
// value method master_m_wvalid
output master_wvalid;
// value method master_m_wdata
output [63 : 0] master_wdata;
// value method master_m_wstrb
output [7 : 0] master_wstrb;
// value method master_m_wlast
output master_wlast;
// value method master_m_wuser
// action method master_m_wready
input master_wready;
// action method master_m_bvalid
input master_bvalid;
input [15 : 0] master_bid;
input [1 : 0] master_bresp;
// value method master_m_bready
output master_bready;
// value method master_m_arvalid
output master_arvalid;
// value method master_m_arid
output [15 : 0] master_arid;
// value method master_m_araddr
output [63 : 0] master_araddr;
// value method master_m_arlen
output [7 : 0] master_arlen;
// value method master_m_arsize
output [2 : 0] master_arsize;
// value method master_m_arburst
output [1 : 0] master_arburst;
// value method master_m_arlock
output master_arlock;
// value method master_m_arcache
output [3 : 0] master_arcache;
// value method master_m_arprot
output [2 : 0] master_arprot;
// value method master_m_arqos
output [3 : 0] master_arqos;
// value method master_m_arregion
output [3 : 0] master_arregion;
// value method master_m_aruser
// action method master_m_arready
input master_arready;
// action method master_m_rvalid
input master_rvalid;
input [15 : 0] master_rid;
input [63 : 0] master_rdata;
input [1 : 0] master_rresp;
input master_rlast;
// value method master_m_rready
output master_rready;
// signals for module outputs
reg [31 : 0] av_read;
wire [63 : 0] master_araddr, master_awaddr, master_wdata;
wire [15 : 0] master_arid, master_awid;
wire [7 : 0] master_arlen, master_awlen, master_wstrb;
wire [3 : 0] master_arcache,
master_arqos,
master_arregion,
master_awcache,
master_awqos,
master_awregion;
wire [2 : 0] master_arprot, master_arsize, master_awprot, master_awsize;
wire [1 : 0] master_arburst, master_awburst;
wire RDY_av_read,
RDY_reset,
RDY_write,
master_arlock,
master_arvalid,
master_awlock,
master_awvalid,
master_bready,
master_rready,
master_wlast,
master_wvalid;
// register rg_sb_state
reg [1 : 0] rg_sb_state;
wire [1 : 0] rg_sb_state$D_IN;
wire rg_sb_state$EN;
// register rg_sbaddress0
reg [31 : 0] rg_sbaddress0;
reg [31 : 0] rg_sbaddress0$D_IN;
wire rg_sbaddress0$EN;
// register rg_sbaddress1
reg [31 : 0] rg_sbaddress1;
reg [31 : 0] rg_sbaddress1$D_IN;
wire rg_sbaddress1$EN;
// register rg_sbaddress_reading
reg [63 : 0] rg_sbaddress_reading;
wire [63 : 0] rg_sbaddress_reading$D_IN;
wire rg_sbaddress_reading$EN;
// register rg_sbcs_sbaccess
reg [2 : 0] rg_sbcs_sbaccess;
wire [2 : 0] rg_sbcs_sbaccess$D_IN;
wire rg_sbcs_sbaccess$EN;
// register rg_sbcs_sbautoincrement
reg rg_sbcs_sbautoincrement;
wire rg_sbcs_sbautoincrement$D_IN, rg_sbcs_sbautoincrement$EN;
// register rg_sbcs_sbbusyerror
reg rg_sbcs_sbbusyerror;
reg rg_sbcs_sbbusyerror$D_IN;
wire rg_sbcs_sbbusyerror$EN;
// register rg_sbcs_sberror
reg [2 : 0] rg_sbcs_sberror;
reg [2 : 0] rg_sbcs_sberror$D_IN;
wire rg_sbcs_sberror$EN;
// register rg_sbcs_sbreadonaddr
reg rg_sbcs_sbreadonaddr;
wire rg_sbcs_sbreadonaddr$D_IN, rg_sbcs_sbreadonaddr$EN;
// register rg_sbcs_sbreadondata
reg rg_sbcs_sbreadondata;
wire rg_sbcs_sbreadondata$D_IN, rg_sbcs_sbreadondata$EN;
// register rg_sbdata0
reg [31 : 0] rg_sbdata0;
reg [31 : 0] rg_sbdata0$D_IN;
wire rg_sbdata0$EN;
// ports of submodule master_xactor_f_rd_addr
wire [108 : 0] master_xactor_f_rd_addr$D_IN, master_xactor_f_rd_addr$D_OUT;
wire master_xactor_f_rd_addr$CLR,
master_xactor_f_rd_addr$DEQ,
master_xactor_f_rd_addr$EMPTY_N,
master_xactor_f_rd_addr$ENQ,
master_xactor_f_rd_addr$FULL_N;
// ports of submodule master_xactor_f_rd_data
wire [82 : 0] master_xactor_f_rd_data$D_IN, master_xactor_f_rd_data$D_OUT;
wire master_xactor_f_rd_data$CLR,
master_xactor_f_rd_data$DEQ,
master_xactor_f_rd_data$EMPTY_N,
master_xactor_f_rd_data$ENQ,
master_xactor_f_rd_data$FULL_N;
// ports of submodule master_xactor_f_wr_addr
wire [108 : 0] master_xactor_f_wr_addr$D_IN, master_xactor_f_wr_addr$D_OUT;
wire master_xactor_f_wr_addr$CLR,
master_xactor_f_wr_addr$DEQ,
master_xactor_f_wr_addr$EMPTY_N,
master_xactor_f_wr_addr$ENQ,
master_xactor_f_wr_addr$FULL_N;
// ports of submodule master_xactor_f_wr_data
wire [72 : 0] master_xactor_f_wr_data$D_IN, master_xactor_f_wr_data$D_OUT;
wire master_xactor_f_wr_data$CLR,
master_xactor_f_wr_data$DEQ,
master_xactor_f_wr_data$EMPTY_N,
master_xactor_f_wr_data$ENQ,
master_xactor_f_wr_data$FULL_N;
// ports of submodule master_xactor_f_wr_resp
wire [17 : 0] master_xactor_f_wr_resp$D_IN, master_xactor_f_wr_resp$D_OUT;
wire master_xactor_f_wr_resp$CLR,
master_xactor_f_wr_resp$DEQ,
master_xactor_f_wr_resp$EMPTY_N,
master_xactor_f_wr_resp$ENQ,
master_xactor_f_wr_resp$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_rl_sb_read_finish,
CAN_FIRE_RL_rl_sb_write_response,
CAN_FIRE_av_read,
CAN_FIRE_master_m_arready,
CAN_FIRE_master_m_awready,
CAN_FIRE_master_m_bvalid,
CAN_FIRE_master_m_rvalid,
CAN_FIRE_master_m_wready,
CAN_FIRE_reset,
CAN_FIRE_write,
WILL_FIRE_RL_rl_sb_read_finish,
WILL_FIRE_RL_rl_sb_write_response,
WILL_FIRE_av_read,
WILL_FIRE_master_m_arready,
WILL_FIRE_master_m_awready,
WILL_FIRE_master_m_bvalid,
WILL_FIRE_master_m_rvalid,
WILL_FIRE_master_m_wready,
WILL_FIRE_reset,
WILL_FIRE_write;
// inputs to muxes for submodule ports
reg [31 : 0] MUX_rg_sbaddress0$write_1__VAL_2,
MUX_rg_sbaddress1$write_1__VAL_2;
reg [2 : 0] MUX_rg_sbcs_sberror$write_1__VAL_4;
wire [108 : 0] MUX_master_xactor_f_rd_addr$enq_1__VAL_1,
MUX_master_xactor_f_rd_addr$enq_1__VAL_2;
wire MUX_master_xactor_f_rd_addr$enq_1__SEL_1,
MUX_rg_sbaddress0$write_1__SEL_2,
MUX_rg_sbaddress0$write_1__SEL_3,
MUX_rg_sbaddress1$write_1__SEL_2,
MUX_rg_sbcs_sbbusyerror$write_1__SEL_2,
MUX_rg_sbcs_sbbusyerror$write_1__SEL_3,
MUX_rg_sbcs_sberror$write_1__SEL_1,
MUX_rg_sbcs_sberror$write_1__SEL_3,
MUX_rg_sbcs_sberror$write_1__SEL_4,
MUX_rg_sbdata0$write_1__SEL_3;
// remaining internal signals
reg [63 : 0] CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1,
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53,
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66,
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103,
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79,
wrd_wdata__h4397;
reg [7 : 0] wrd_wstrb__h4398;
reg [2 : 0] x__h2654, x__h4302;
wire [63 : 0] _theResult___fst__h4340,
addr64__h3701,
result__h1250,
result__h1280,
result__h1307,
result__h1334,
result__h1361,
result__h1388,
result__h1415,
result__h1442,
result__h1487,
result__h1514,
result__h1541,
result__h1568,
result__h1609,
result__h1636,
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104,
rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299,
sbaddress__h638,
word64__h4284;
wire [31 : 0] IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310,
IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301,
v__h2132,
v__h2266;
wire [7 : 0] strobe64__h4339, strobe64__h4342, strobe64__h4345;
wire [5 : 0] shift_bits__h4287;
wire rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110,
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316,
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95,
rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291,
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256,
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265,
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271,
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273,
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278,
write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326;
// action method reset
assign RDY_reset = 1'd1 ;
assign CAN_FIRE_reset = 1'd1 ;
assign WILL_FIRE_reset = EN_reset ;
// actionvalue method av_read
always@(av_read_dm_addr or
v__h2132 or rg_sbaddress0 or rg_sbaddress1 or v__h2266)
begin
case (av_read_dm_addr)
7'h38: av_read = v__h2132;
7'h39: av_read = rg_sbaddress0;
7'h3A: av_read = rg_sbaddress1;
7'h3C: av_read = v__h2266;
default: av_read = 32'd0;
endcase
end
assign RDY_av_read =
rg_sb_state == 2'd0 &&
(rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0 ||
!rg_sbcs_sbreadondata ||
master_xactor_f_rd_addr$FULL_N) ;
assign CAN_FIRE_av_read = RDY_av_read ;
assign WILL_FIRE_av_read = EN_av_read ;
// action method write
assign RDY_write = CAN_FIRE_write && !WILL_FIRE_RL_rl_sb_read_finish ;
assign CAN_FIRE_write =
(rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror ||
rg_sbcs_sberror != 3'd0 ||
!rg_sbcs_sbreadonaddr ||
master_xactor_f_rd_addr$FULL_N) &&
(rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror ||
rg_sbcs_sberror != 3'd0 ||
master_xactor_f_wr_addr$FULL_N &&
master_xactor_f_wr_data$FULL_N) ;
assign WILL_FIRE_write = EN_write ;
// value method master_m_awvalid
assign master_awvalid = master_xactor_f_wr_addr$EMPTY_N ;
// value method master_m_awid
assign master_awid = master_xactor_f_wr_addr$D_OUT[108:93] ;
// value method master_m_awaddr
assign master_awaddr = master_xactor_f_wr_addr$D_OUT[92:29] ;
// value method master_m_awlen
assign master_awlen = master_xactor_f_wr_addr$D_OUT[28:21] ;
// value method master_m_awsize
assign master_awsize = master_xactor_f_wr_addr$D_OUT[20:18] ;
// value method master_m_awburst
assign master_awburst = master_xactor_f_wr_addr$D_OUT[17:16] ;
// value method master_m_awlock
assign master_awlock = master_xactor_f_wr_addr$D_OUT[15] ;
// value method master_m_awcache
assign master_awcache = master_xactor_f_wr_addr$D_OUT[14:11] ;
// value method master_m_awprot
assign master_awprot = master_xactor_f_wr_addr$D_OUT[10:8] ;
// value method master_m_awqos
assign master_awqos = master_xactor_f_wr_addr$D_OUT[7:4] ;
// value method master_m_awregion
assign master_awregion = master_xactor_f_wr_addr$D_OUT[3:0] ;
// action method master_m_awready
assign CAN_FIRE_master_m_awready = 1'd1 ;
assign WILL_FIRE_master_m_awready = 1'd1 ;
// value method master_m_wvalid
assign master_wvalid = master_xactor_f_wr_data$EMPTY_N ;
// value method master_m_wdata
assign master_wdata = master_xactor_f_wr_data$D_OUT[72:9] ;
// value method master_m_wstrb
assign master_wstrb = master_xactor_f_wr_data$D_OUT[8:1] ;
// value method master_m_wlast
assign master_wlast = master_xactor_f_wr_data$D_OUT[0] ;
// action method master_m_wready
assign CAN_FIRE_master_m_wready = 1'd1 ;
assign WILL_FIRE_master_m_wready = 1'd1 ;
// action method master_m_bvalid
assign CAN_FIRE_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_master_m_bvalid = 1'd1 ;
// value method master_m_bready
assign master_bready = master_xactor_f_wr_resp$FULL_N ;
// value method master_m_arvalid
assign master_arvalid = master_xactor_f_rd_addr$EMPTY_N ;
// value method master_m_arid
assign master_arid = master_xactor_f_rd_addr$D_OUT[108:93] ;
// value method master_m_araddr
assign master_araddr = master_xactor_f_rd_addr$D_OUT[92:29] ;
// value method master_m_arlen
assign master_arlen = master_xactor_f_rd_addr$D_OUT[28:21] ;
// value method master_m_arsize
assign master_arsize = master_xactor_f_rd_addr$D_OUT[20:18] ;
// value method master_m_arburst
assign master_arburst = master_xactor_f_rd_addr$D_OUT[17:16] ;
// value method master_m_arlock
assign master_arlock = master_xactor_f_rd_addr$D_OUT[15] ;
// value method master_m_arcache
assign master_arcache = master_xactor_f_rd_addr$D_OUT[14:11] ;
// value method master_m_arprot
assign master_arprot = master_xactor_f_rd_addr$D_OUT[10:8] ;
// value method master_m_arqos
assign master_arqos = master_xactor_f_rd_addr$D_OUT[7:4] ;
// value method master_m_arregion
assign master_arregion = master_xactor_f_rd_addr$D_OUT[3:0] ;
// action method master_m_arready
assign CAN_FIRE_master_m_arready = 1'd1 ;
assign WILL_FIRE_master_m_arready = 1'd1 ;
// action method master_m_rvalid
assign CAN_FIRE_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_master_m_rvalid = 1'd1 ;
// value method master_m_rready
assign master_rready = master_xactor_f_rd_data$FULL_N ;
// submodule master_xactor_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(32'd1)) master_xactor_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_rd_addr$D_IN),
.ENQ(master_xactor_f_rd_addr$ENQ),
.DEQ(master_xactor_f_rd_addr$DEQ),
.CLR(master_xactor_f_rd_addr$CLR),
.D_OUT(master_xactor_f_rd_addr$D_OUT),
.FULL_N(master_xactor_f_rd_addr$FULL_N),
.EMPTY_N(master_xactor_f_rd_addr$EMPTY_N));
// submodule master_xactor_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(32'd1)) master_xactor_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_rd_data$D_IN),
.ENQ(master_xactor_f_rd_data$ENQ),
.DEQ(master_xactor_f_rd_data$DEQ),
.CLR(master_xactor_f_rd_data$CLR),
.D_OUT(master_xactor_f_rd_data$D_OUT),
.FULL_N(master_xactor_f_rd_data$FULL_N),
.EMPTY_N(master_xactor_f_rd_data$EMPTY_N));
// submodule master_xactor_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(32'd1)) master_xactor_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_addr$D_IN),
.ENQ(master_xactor_f_wr_addr$ENQ),
.DEQ(master_xactor_f_wr_addr$DEQ),
.CLR(master_xactor_f_wr_addr$CLR),
.D_OUT(master_xactor_f_wr_addr$D_OUT),
.FULL_N(master_xactor_f_wr_addr$FULL_N),
.EMPTY_N(master_xactor_f_wr_addr$EMPTY_N));
// submodule master_xactor_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) master_xactor_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_data$D_IN),
.ENQ(master_xactor_f_wr_data$ENQ),
.DEQ(master_xactor_f_wr_data$DEQ),
.CLR(master_xactor_f_wr_data$CLR),
.D_OUT(master_xactor_f_wr_data$D_OUT),
.FULL_N(master_xactor_f_wr_data$FULL_N),
.EMPTY_N(master_xactor_f_wr_data$EMPTY_N));
// submodule master_xactor_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(32'd1)) master_xactor_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_resp$D_IN),
.ENQ(master_xactor_f_wr_resp$ENQ),
.DEQ(master_xactor_f_wr_resp$DEQ),
.CLR(master_xactor_f_wr_resp$CLR),
.D_OUT(master_xactor_f_wr_resp$D_OUT),
.FULL_N(master_xactor_f_wr_resp$FULL_N),
.EMPTY_N(master_xactor_f_wr_resp$EMPTY_N));
// rule RL_rl_sb_read_finish
assign CAN_FIRE_RL_rl_sb_read_finish =
master_xactor_f_rd_data$EMPTY_N && rg_sb_state == 2'd1 &&
rg_sbcs_sberror == 3'd0 ;
assign WILL_FIRE_RL_rl_sb_read_finish = CAN_FIRE_RL_rl_sb_read_finish ;
// rule RL_rl_sb_write_response
assign CAN_FIRE_RL_rl_sb_write_response = master_xactor_f_wr_resp$EMPTY_N ;
assign WILL_FIRE_RL_rl_sb_write_response = master_xactor_f_wr_resp$EMPTY_N ;
// inputs to muxes for submodule ports
assign MUX_master_xactor_f_rd_addr$enq_1__SEL_1 =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 ;
assign MUX_rg_sbaddress0$write_1__SEL_2 =
EN_write && write_dm_addr != 7'h38 &&
(rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror &&
rg_sbcs_sberror == 3'd0 &&
write_dm_addr == 7'h39 ||
write_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95) ;
assign MUX_rg_sbaddress0$write_1__SEL_3 =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 ;
assign MUX_rg_sbaddress1$write_1__SEL_2 =
EN_write && write_dm_addr != 7'h38 &&
((write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) &&
rg_sb_state == 2'd0 &&
!rg_sbcs_sbbusyerror &&
rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291 ||
write_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95) ;
assign MUX_rg_sbcs_sbbusyerror$write_1__SEL_2 =
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 ;
assign MUX_rg_sbcs_sbbusyerror$write_1__SEL_3 =
EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0 ;
assign MUX_rg_sbcs_sberror$write_1__SEL_1 =
master_xactor_f_wr_resp$EMPTY_N &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 ;
assign MUX_rg_sbcs_sberror$write_1__SEL_3 =
WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
assign MUX_rg_sbcs_sberror$write_1__SEL_4 =
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 ;
assign MUX_rg_sbdata0$write_1__SEL_3 =
EN_write &&
write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 ;
assign MUX_master_xactor_f_rd_addr$enq_1__VAL_1 =
{ 16'd0, sbaddress__h638, 8'd0, x__h2654, 18'd65536 } ;
assign MUX_master_xactor_f_rd_addr$enq_1__VAL_2 =
{ 16'd0, addr64__h3701, 8'd0, x__h2654, 18'd65536 } ;
always@(write_dm_addr or
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104 or
IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310)
begin
case (write_dm_addr)
7'h39, 7'h3A:
MUX_rg_sbaddress0$write_1__VAL_2 =
IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310;
default: MUX_rg_sbaddress0$write_1__VAL_2 =
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104[31:0];
endcase
end
always@(write_dm_addr or
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104 or
IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301)
begin
case (write_dm_addr)
7'h39, 7'h3A:
MUX_rg_sbaddress1$write_1__VAL_2 =
IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301;
default: MUX_rg_sbaddress1$write_1__VAL_2 =
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104[63:32];
endcase
end
always@(write_dm_word)
begin
case (write_dm_word[19:17])
3'd3, 3'd4: MUX_rg_sbcs_sberror$write_1__VAL_4 = 3'd3;
default: MUX_rg_sbcs_sberror$write_1__VAL_4 = 3'd0;
endcase
end
// register rg_sb_state
assign rg_sb_state$D_IN =
(EN_reset || WILL_FIRE_RL_rl_sb_read_finish) ? 2'd0 : 2'd1 ;
assign rg_sb_state$EN =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 ||
EN_write && write_dm_addr == 7'h39 &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 ||
WILL_FIRE_RL_rl_sb_read_finish ||
EN_reset ;
// register rg_sbaddress0
always@(EN_reset or
MUX_rg_sbaddress0$write_1__SEL_2 or
MUX_rg_sbaddress0$write_1__VAL_2 or
MUX_rg_sbaddress0$write_1__SEL_3 or
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104)
case (1'b1)
EN_reset: rg_sbaddress0$D_IN = 32'd0;
MUX_rg_sbaddress0$write_1__SEL_2:
rg_sbaddress0$D_IN = MUX_rg_sbaddress0$write_1__VAL_2;
MUX_rg_sbaddress0$write_1__SEL_3:
rg_sbaddress0$D_IN =
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104[31:0];
default: rg_sbaddress0$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
assign rg_sbaddress0$EN =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 ||
MUX_rg_sbaddress0$write_1__SEL_2 ||
EN_reset ;
// register rg_sbaddress1
always@(EN_reset or
MUX_rg_sbaddress1$write_1__SEL_2 or
MUX_rg_sbaddress1$write_1__VAL_2 or
MUX_rg_sbaddress0$write_1__SEL_3 or
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104)
case (1'b1)
EN_reset: rg_sbaddress1$D_IN = 32'd0;
MUX_rg_sbaddress1$write_1__SEL_2:
rg_sbaddress1$D_IN = MUX_rg_sbaddress1$write_1__VAL_2;
MUX_rg_sbaddress0$write_1__SEL_3:
rg_sbaddress1$D_IN =
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104[63:32];
default: rg_sbaddress1$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
assign rg_sbaddress1$EN =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 ||
MUX_rg_sbaddress1$write_1__SEL_2 ||
EN_reset ;
// register rg_sbaddress_reading
assign rg_sbaddress_reading$D_IN =
MUX_master_xactor_f_rd_addr$enq_1__SEL_1 ?
sbaddress__h638 :
addr64__h3701 ;
assign rg_sbaddress_reading$EN =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 ||
EN_write && write_dm_addr == 7'h39 &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 ;
// register rg_sbcs_sbaccess
assign rg_sbcs_sbaccess$D_IN = EN_reset ? 3'd2 : write_dm_word[19:17] ;
assign rg_sbcs_sbaccess$EN =
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 ||
EN_reset ;
// register rg_sbcs_sbautoincrement
assign rg_sbcs_sbautoincrement$D_IN = !EN_reset && write_dm_word[16] ;
assign rg_sbcs_sbautoincrement$EN =
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 ||
EN_reset ;
// register rg_sbcs_sbbusyerror
always@(EN_reset or
MUX_rg_sbcs_sbbusyerror$write_1__SEL_2 or
write_dm_addr or MUX_rg_sbcs_sbbusyerror$write_1__SEL_3)
case (1'b1)
EN_reset: rg_sbcs_sbbusyerror$D_IN = 1'd0;
MUX_rg_sbcs_sbbusyerror$write_1__SEL_2:
rg_sbcs_sbbusyerror$D_IN = write_dm_addr != 7'h38;
MUX_rg_sbcs_sbbusyerror$write_1__SEL_3: rg_sbcs_sbbusyerror$D_IN = 1'd1;
default: rg_sbcs_sbbusyerror$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign rg_sbcs_sbbusyerror$EN =
EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0 ||
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 ||
EN_reset ;
// register rg_sbcs_sberror
always@(MUX_rg_sbcs_sberror$write_1__SEL_1 or
EN_reset or
MUX_rg_sbcs_sberror$write_1__SEL_3 or
MUX_rg_sbcs_sberror$write_1__SEL_4 or
MUX_rg_sbcs_sberror$write_1__VAL_4)
case (1'b1)
MUX_rg_sbcs_sberror$write_1__SEL_1: rg_sbcs_sberror$D_IN = 3'd3;
EN_reset: rg_sbcs_sberror$D_IN = 3'd0;
MUX_rg_sbcs_sberror$write_1__SEL_3: rg_sbcs_sberror$D_IN = 3'd3;
MUX_rg_sbcs_sberror$write_1__SEL_4:
rg_sbcs_sberror$D_IN = MUX_rg_sbcs_sberror$write_1__VAL_4;
default: rg_sbcs_sberror$D_IN = 3'b010 /* unspecified value */ ;
endcase
assign rg_sbcs_sberror$EN =
WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
master_xactor_f_wr_resp$EMPTY_N &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 ||
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 ||
EN_reset ;
// register rg_sbcs_sbreadonaddr
assign rg_sbcs_sbreadonaddr$D_IN = !EN_reset && write_dm_word[20] ;
assign rg_sbcs_sbreadonaddr$EN =
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 ||
EN_reset ;
// register rg_sbcs_sbreadondata
assign rg_sbcs_sbreadondata$D_IN = !EN_reset && write_dm_word[15] ;
assign rg_sbcs_sbreadondata$EN =
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 ||
EN_reset ;
// register rg_sbdata0
always@(EN_reset or
WILL_FIRE_RL_rl_sb_read_finish or
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 or
MUX_rg_sbdata0$write_1__SEL_3 or write_dm_word)
case (1'b1)
EN_reset: rg_sbdata0$D_IN = 32'd0;
WILL_FIRE_RL_rl_sb_read_finish:
rg_sbdata0$D_IN =
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79[31:0];
MUX_rg_sbdata0$write_1__SEL_3: rg_sbdata0$D_IN = write_dm_word;
default: rg_sbdata0$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
assign rg_sbdata0$EN =
EN_write &&
write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 ||
WILL_FIRE_RL_rl_sb_read_finish ||
EN_reset ;
// submodule master_xactor_f_rd_addr
assign master_xactor_f_rd_addr$D_IN =
MUX_master_xactor_f_rd_addr$enq_1__SEL_1 ?
MUX_master_xactor_f_rd_addr$enq_1__VAL_1 :
MUX_master_xactor_f_rd_addr$enq_1__VAL_2 ;
assign master_xactor_f_rd_addr$ENQ =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 ||
EN_write && write_dm_addr == 7'h39 &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 ;
assign master_xactor_f_rd_addr$DEQ =
master_xactor_f_rd_addr$EMPTY_N && master_arready ;
assign master_xactor_f_rd_addr$CLR = 1'b0 ;
// submodule master_xactor_f_rd_data
assign master_xactor_f_rd_data$D_IN =
{ master_rid, master_rdata, master_rresp, master_rlast } ;
assign master_xactor_f_rd_data$ENQ =
master_rvalid && master_xactor_f_rd_data$FULL_N ;
assign master_xactor_f_rd_data$DEQ =
master_xactor_f_rd_data$EMPTY_N && rg_sb_state == 2'd1 &&
rg_sbcs_sberror == 3'd0 ;
assign master_xactor_f_rd_data$CLR = 1'b0 ;
// submodule master_xactor_f_wr_addr
assign master_xactor_f_wr_addr$D_IN =
{ 16'd0, sbaddress__h638, 8'd0, x__h4302, 18'd65536 } ;
assign master_xactor_f_wr_addr$ENQ =
EN_write &&
write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 ;
assign master_xactor_f_wr_addr$DEQ =
master_xactor_f_wr_addr$EMPTY_N && master_awready ;
assign master_xactor_f_wr_addr$CLR = 1'b0 ;
// submodule master_xactor_f_wr_data
assign master_xactor_f_wr_data$D_IN =
{ wrd_wdata__h4397, wrd_wstrb__h4398, 1'd1 } ;
assign master_xactor_f_wr_data$ENQ =
EN_write &&
write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 ;
assign master_xactor_f_wr_data$DEQ =
master_xactor_f_wr_data$EMPTY_N && master_wready ;
assign master_xactor_f_wr_data$CLR = 1'b0 ;
// submodule master_xactor_f_wr_resp
assign master_xactor_f_wr_resp$D_IN = { master_bid, master_bresp } ;
assign master_xactor_f_wr_resp$ENQ =
master_bvalid && master_xactor_f_wr_resp$FULL_N ;
assign master_xactor_f_wr_resp$DEQ = master_xactor_f_wr_resp$EMPTY_N ;
assign master_xactor_f_wr_resp$CLR = 1'b0 ;
// remaining internal signals
assign IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310 =
rg_sbcs_sbreadonaddr ?
(rg_sbcs_sbautoincrement ?
rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299[31:0] :
write_dm_word) :
write_dm_word ;
assign IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301 =
(write_dm_addr == 7'h39) ?
rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299[63:32] :
write_dm_word ;
assign _theResult___fst__h4340 = word64__h4284 << shift_bits__h4287 ;
assign addr64__h3701 = { rg_sbaddress1, write_dm_word } ;
assign result__h1250 = { 56'd0, master_xactor_f_rd_data$D_OUT[10:3] } ;
assign result__h1280 = { 56'd0, master_xactor_f_rd_data$D_OUT[18:11] } ;
assign result__h1307 = { 56'd0, master_xactor_f_rd_data$D_OUT[26:19] } ;
assign result__h1334 = { 56'd0, master_xactor_f_rd_data$D_OUT[34:27] } ;
assign result__h1361 = { 56'd0, master_xactor_f_rd_data$D_OUT[42:35] } ;
assign result__h1388 = { 56'd0, master_xactor_f_rd_data$D_OUT[50:43] } ;
assign result__h1415 = { 56'd0, master_xactor_f_rd_data$D_OUT[58:51] } ;
assign result__h1442 = { 56'd0, master_xactor_f_rd_data$D_OUT[66:59] } ;
assign result__h1487 = { 48'd0, master_xactor_f_rd_data$D_OUT[18:3] } ;
assign result__h1514 = { 48'd0, master_xactor_f_rd_data$D_OUT[34:19] } ;
assign result__h1541 = { 48'd0, master_xactor_f_rd_data$D_OUT[50:35] } ;
assign result__h1568 = { 48'd0, master_xactor_f_rd_data$D_OUT[66:51] } ;
assign result__h1609 = { 32'd0, master_xactor_f_rd_data$D_OUT[34:3] } ;
assign result__h1636 = { 32'd0, master_xactor_f_rd_data$D_OUT[66:35] } ;
assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 =
rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror &&
rg_sbcs_sberror == 3'd0 &&
rg_sbcs_sbreadondata ;
assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 =
rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror &&
rg_sbcs_sberror == 3'd0 &&
rg_sbcs_sbreadonaddr ;
assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 =
rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror &&
rg_sbcs_sberror == 3'd0 &&
rg_sbcs_sbautoincrement ;
assign rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104 =
sbaddress__h638 +
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 ;
assign rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299 =
addr64__h3701 +
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 ;
assign rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291 =
rg_sbcs_sberror == 3'd0 &&
(rg_sbcs_sbreadonaddr && rg_sbcs_sbautoincrement ||
write_dm_addr != 7'h39) ;
assign sbaddress__h638 = { rg_sbaddress1, rg_sbaddress0 } ;
assign shift_bits__h4287 = { rg_sbaddress0[2:0], 3'b0 } ;
assign strobe64__h4339 = 8'b00000001 << rg_sbaddress0[2:0] ;
assign strobe64__h4342 = 8'b00000011 << rg_sbaddress0[2:0] ;
assign strobe64__h4345 = 8'b00001111 << rg_sbaddress0[2:0] ;
assign v__h2132 =
{ 9'd64,
rg_sbcs_sbbusyerror,
rg_sb_state != 2'd0,
rg_sbcs_sbreadonaddr,
rg_sbcs_sbaccess,
rg_sbcs_sbautoincrement,
rg_sbcs_sbreadondata,
rg_sbcs_sberror,
12'd2055 } ;
assign v__h2266 =
(rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror ||
rg_sbcs_sberror != 3'd0) ?
32'd0 :
rg_sbdata0 ;
assign word64__h4284 = { 32'd0, write_dm_word } ;
assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 =
write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
(!rg_sbcs_sbbusyerror || write_dm_word[22]) &&
write_dm_word[19:17] != 3'd4 &&
write_dm_word[19:17] != 3'd3 ;
assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 =
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 ||
(write_dm_addr == 7'h39 || write_dm_addr == 7'h3A ||
write_dm_addr == 7'h3C) &&
rg_sb_state != 2'd0 ;
assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271 =
write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
rg_sbcs_sbbusyerror &&
!write_dm_word[22] ;
assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 =
write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
(!rg_sbcs_sbbusyerror || write_dm_word[22]) ;
assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278 =
write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
(!rg_sbcs_sbbusyerror || write_dm_word[22]) &&
(write_dm_word[19:17] == 3'd4 || write_dm_word[19:17] == 3'd3) ;
assign write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 =
write_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
!rg_sbcs_sbbusyerror &&
rg_sbcs_sberror == 3'd0 ;
always@(rg_sbcs_sbaccess)
begin
case (rg_sbcs_sbaccess)
3'd0, 3'd1, 3'd2: x__h2654 = rg_sbcs_sbaccess;
default: x__h2654 = 3'b011;
endcase
end
always@(rg_sbcs_sbaccess)
begin
case (rg_sbcs_sbaccess)
3'd0, 3'd1, 3'd2, 3'd3: x__h4302 = rg_sbcs_sbaccess;
default: x__h4302 = 3'b111;
endcase
end
always@(rg_sbcs_sbaccess or
strobe64__h4339 or strobe64__h4342 or strobe64__h4345)
begin
case (rg_sbcs_sbaccess)
3'd0: wrd_wstrb__h4398 = strobe64__h4339;
3'd1: wrd_wstrb__h4398 = strobe64__h4342;
3'd2: wrd_wstrb__h4398 = strobe64__h4345;
3'd3: wrd_wstrb__h4398 = 8'b11111111;
default: wrd_wstrb__h4398 = 8'd0;
endcase
end
always@(rg_sbcs_sbaccess or word64__h4284 or _theResult___fst__h4340)
begin
case (rg_sbcs_sbaccess)
3'd0, 3'd1, 3'd2: wrd_wdata__h4397 = _theResult___fst__h4340;
default: wrd_wdata__h4397 = word64__h4284;
endcase
end
always@(rg_sbcs_sbaccess)
begin
case (rg_sbcs_sbaccess)
3'd0: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd1;
3'd1: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd2;
3'd2: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd4;
3'd3: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd8;
default: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 =
64'd16;
endcase
end
always@(rg_sbaddress_reading or
result__h1250 or
result__h1280 or
result__h1307 or
result__h1334 or
result__h1361 or result__h1388 or result__h1415 or result__h1442)
begin
case (rg_sbaddress_reading[2:0])
3'h0:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1250;
3'h1:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1280;
3'h2:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1307;
3'h3:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1334;
3'h4:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1361;
3'h5:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1388;
3'h6:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1415;
3'h7:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1442;
endcase
end
always@(rg_sbaddress_reading or
result__h1487 or result__h1514 or result__h1541 or result__h1568)
begin
case (rg_sbaddress_reading[2:0])
3'h0:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 =
result__h1487;
3'h2:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 =
result__h1514;
3'h4:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 =
result__h1541;
3'h6:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 =
result__h1568;
default: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 =
64'd0;
endcase
end
always@(rg_sbaddress_reading or result__h1609 or result__h1636)
begin
case (rg_sbaddress_reading[2:0])
3'h0:
CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 =
result__h1609;
3'h4:
CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 =
result__h1636;
default: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 = 64'd0;
endcase
end
always@(rg_sbcs_sbaccess or
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 or
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 or
CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 or
rg_sbaddress_reading or master_xactor_f_rd_data$D_OUT)
begin
case (rg_sbcs_sbaccess)
3'd0:
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 =
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53;
3'd1:
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 =
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66;
3'd2:
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 =
CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1;
3'd3:
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 =
(rg_sbaddress_reading[2:0] == 3'h0) ?
master_xactor_f_rd_data$D_OUT[66:3] :
64'd0;
default: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 =
64'd0;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY 32'd0;
rg_sbaddress1 <= `BSV_ASSIGNMENT_DELAY 32'd0;
end
else
begin
if (rg_sbaddress0$EN)
rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY rg_sbaddress0$D_IN;
if (rg_sbaddress1$EN)
rg_sbaddress1 <= `BSV_ASSIGNMENT_DELAY rg_sbaddress1$D_IN;
end
if (rg_sb_state$EN) rg_sb_state <= `BSV_ASSIGNMENT_DELAY rg_sb_state$D_IN;
if (rg_sbaddress_reading$EN)
rg_sbaddress_reading <= `BSV_ASSIGNMENT_DELAY rg_sbaddress_reading$D_IN;
if (rg_sbcs_sbaccess$EN)
rg_sbcs_sbaccess <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sbaccess$D_IN;
if (rg_sbcs_sbautoincrement$EN)
rg_sbcs_sbautoincrement <= `BSV_ASSIGNMENT_DELAY
rg_sbcs_sbautoincrement$D_IN;
if (rg_sbcs_sbbusyerror$EN)
rg_sbcs_sbbusyerror <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sbbusyerror$D_IN;
if (rg_sbcs_sberror$EN)
rg_sbcs_sberror <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sberror$D_IN;
if (rg_sbcs_sbreadonaddr$EN)
rg_sbcs_sbreadonaddr <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sbreadonaddr$D_IN;
if (rg_sbcs_sbreadondata$EN)
rg_sbcs_sbreadondata <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sbreadondata$D_IN;
if (rg_sbdata0$EN) rg_sbdata0 <= `BSV_ASSIGNMENT_DELAY rg_sbdata0$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_sb_state = 2'h2;
rg_sbaddress0 = 32'hAAAAAAAA;
rg_sbaddress1 = 32'hAAAAAAAA;
rg_sbaddress_reading = 64'hAAAAAAAAAAAAAAAA;
rg_sbcs_sbaccess = 3'h2;
rg_sbcs_sbautoincrement = 1'h0;
rg_sbcs_sbbusyerror = 1'h0;
rg_sbcs_sberror = 3'h2;
rg_sbcs_sbreadonaddr = 1'h0;
rg_sbcs_sbreadondata = 1'h0;
rg_sbdata0 = 32'hAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
rg_sbcs_sbbusyerror)
$display("DM_System_Bus.sbdata.read: ignoring due to sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
!rg_sbcs_sbbusyerror &&
rg_sbcs_sberror != 3'd0)
$display("DM_System_Bus.sbdata.read: ignoring due to sberror = 0x%0h",
rg_sbcs_sberror);
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0)
$display("DM_System_Bus.sbdata.read: busy, setting sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr != 7'h38 &&
av_read_dm_addr != 7'h39 &&
av_read_dm_addr != 7'h3A &&
av_read_dm_addr != 7'h3C)
$write("DM_System_Bus.read: [");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h10) $write("dm_addr_dmcontrol");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h11) $write("dm_addr_dmstatus");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h12) $write("dm_addr_hartinfo");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h13) $write("dm_addr_haltsum");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h14)
$write("dm_addr_hawindowsel");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h15) $write("dm_addr_hawindow");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h19)
$write("dm_addr_devtreeaddr0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h30) $write("dm_addr_authdata");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h40)
$write("dm_addr_haltregion0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h5F)
$write("dm_addr_haltregion31");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h60) $write("dm_addr_verbosity");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h16)
$write("dm_addr_abstractcs");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h17) $write("dm_addr_command");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h04) $write("dm_addr_data0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h05) $write("dm_addr_data1");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h06) $write("dm_addr_data2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h07) $write("dm_addr_data3");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h08) $write("dm_addr_data4");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h09) $write("dm_addr_data5");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h0A) $write("dm_addr_data6");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h0B) $write("dm_addr_data7");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h0C) $write("dm_addr_data8");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h0D) $write("dm_addr_data9");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h0F) $write("dm_addr_data11");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h18)
$write("dm_addr_abstractauto");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h20) $write("dm_addr_progbuf0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3B)
$write("dm_addr_sbaddress2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3D) $write("dm_addr_sbdata1");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3E) $write("dm_addr_sbdata2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3F) $write("dm_addr_sbdata3");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr != 7'h38 &&
av_read_dm_addr != 7'h39 &&
av_read_dm_addr != 7'h3A &&
av_read_dm_addr != 7'h3C &&
av_read_dm_addr != 7'h10 &&
av_read_dm_addr != 7'h11 &&
av_read_dm_addr != 7'h12 &&
av_read_dm_addr != 7'h13 &&
av_read_dm_addr != 7'h14 &&
av_read_dm_addr != 7'h15 &&
av_read_dm_addr != 7'h19 &&
av_read_dm_addr != 7'h30 &&
av_read_dm_addr != 7'h40 &&
av_read_dm_addr != 7'h5F &&
av_read_dm_addr != 7'h60 &&
av_read_dm_addr != 7'h16 &&
av_read_dm_addr != 7'h17 &&
av_read_dm_addr != 7'h04 &&
av_read_dm_addr != 7'h05 &&
av_read_dm_addr != 7'h06 &&
av_read_dm_addr != 7'h07 &&
av_read_dm_addr != 7'h08 &&
av_read_dm_addr != 7'h09 &&
av_read_dm_addr != 7'h0A &&
av_read_dm_addr != 7'h0B &&
av_read_dm_addr != 7'h0C &&
av_read_dm_addr != 7'h0D &&
av_read_dm_addr != 7'h0F &&
av_read_dm_addr != 7'h18 &&
av_read_dm_addr != 7'h20 &&
av_read_dm_addr != 7'h3B &&
av_read_dm_addr != 7'h3D &&
av_read_dm_addr != 7'h3E &&
av_read_dm_addr != 7'h3F)
$write("<Unknown dm_abstract_command dm_addr 0x%0h>",
av_read_dm_addr);
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr != 7'h38 &&
av_read_dm_addr != 7'h39 &&
av_read_dm_addr != 7'h3A &&
av_read_dm_addr != 7'h3C)
$write("] not supported", "\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h38 && rg_sbcs_sberror != 3'd0 &&
write_dm_word[14:12] == 3'd0)
$display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h38 && rg_sbcs_sberror != 3'd0 &&
write_dm_word[14:12] == 3'd0)
$display(" ERROR: existing sberror (0x%0h) is not being cleared.",
rg_sbcs_sberror);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h38 && rg_sbcs_sberror != 3'd0 &&
write_dm_word[14:12] == 3'd0)
$display(" Must be cleared to re-enable system bus access.");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271)
$display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271)
$display(" ERROR: existing sbbusyerror (%0d) is not being cleared.",
rg_sbcs_sbbusyerror);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271)
$display(" Must be cleared to re-enable system bus access.");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278)
$display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278)
$write(" ERROR: sbaccess ");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
(!rg_sbcs_sbbusyerror || write_dm_word[22]) &&
write_dm_word[19:17] == 3'd3)
$write("DM_SBACCESS_64_BIT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
(!rg_sbcs_sbbusyerror || write_dm_word[22]) &&
write_dm_word[19:17] == 3'd4)
$write("DM_SBACCESS_128_BIT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278)
$write(" not supported", "\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 &&
(write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) &&
rg_sb_state == 2'd0 &&
rg_sbcs_sbbusyerror)
$display("DM_System_Bus.sbaddress.write: ignoring due to sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 &&
(write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) &&
rg_sb_state == 2'd0 &&
!rg_sbcs_sbbusyerror &&
rg_sbcs_sberror != 3'd0)
$display("DM_System_Bus.sbaddress.write: ignoring due to sberror = 0x%0h",
rg_sbcs_sberror);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 &&
(write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) &&
rg_sb_state != 2'd0)
$display("DM_System_Bus.sbaddress.write: busy, setting sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
rg_sbcs_sbbusyerror)
$display("DM_System_Bus.sbdata.write: ignoring due to sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
!rg_sbcs_sbbusyerror &&
rg_sbcs_sberror != 3'd0)
$display("DM_System_Bus.sbdata.write: ignoring due to sberror = 0x%0h",
rg_sbcs_sberror);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3C && rg_sb_state != 2'd0)
$display("DM_System_Bus.sbdata.write: busy, setting sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 && write_dm_addr != 7'h39 &&
write_dm_addr != 7'h3A &&
write_dm_addr != 7'h3C)
$write("DM_System_Bus.write: [");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h10) $write("dm_addr_dmcontrol");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h11) $write("dm_addr_dmstatus");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h12) $write("dm_addr_hartinfo");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h13) $write("dm_addr_haltsum");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h14) $write("dm_addr_hawindowsel");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h15) $write("dm_addr_hawindow");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h19) $write("dm_addr_devtreeaddr0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h30) $write("dm_addr_authdata");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h40) $write("dm_addr_haltregion0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h5F) $write("dm_addr_haltregion31");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h60) $write("dm_addr_verbosity");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h16) $write("dm_addr_abstractcs");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h17) $write("dm_addr_command");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h04) $write("dm_addr_data0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h05) $write("dm_addr_data1");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h06) $write("dm_addr_data2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h07) $write("dm_addr_data3");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h08) $write("dm_addr_data4");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h09) $write("dm_addr_data5");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h0A) $write("dm_addr_data6");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h0B) $write("dm_addr_data7");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h0C) $write("dm_addr_data8");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h0D) $write("dm_addr_data9");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h0F) $write("dm_addr_data11");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h18) $write("dm_addr_abstractauto");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h20) $write("dm_addr_progbuf0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3B) $write("dm_addr_sbaddress2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3D) $write("dm_addr_sbdata1");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3E) $write("dm_addr_sbdata2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3F) $write("dm_addr_sbdata3");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 && write_dm_addr != 7'h39 &&
write_dm_addr != 7'h3A &&
write_dm_addr != 7'h3C &&
write_dm_addr != 7'h10 &&
write_dm_addr != 7'h11 &&
write_dm_addr != 7'h12 &&
write_dm_addr != 7'h13 &&
write_dm_addr != 7'h14 &&
write_dm_addr != 7'h15 &&
write_dm_addr != 7'h19 &&
write_dm_addr != 7'h30 &&
write_dm_addr != 7'h40 &&
write_dm_addr != 7'h5F &&
write_dm_addr != 7'h60 &&
write_dm_addr != 7'h16 &&
write_dm_addr != 7'h17 &&
write_dm_addr != 7'h04 &&
write_dm_addr != 7'h05 &&
write_dm_addr != 7'h06 &&
write_dm_addr != 7'h07 &&
write_dm_addr != 7'h08 &&
write_dm_addr != 7'h09 &&
write_dm_addr != 7'h0A &&
write_dm_addr != 7'h0B &&
write_dm_addr != 7'h0C &&
write_dm_addr != 7'h0D &&
write_dm_addr != 7'h0F &&
write_dm_addr != 7'h18 &&
write_dm_addr != 7'h20 &&
write_dm_addr != 7'h3B &&
write_dm_addr != 7'h3D &&
write_dm_addr != 7'h3E &&
write_dm_addr != 7'h3F)
$write("<Unknown dm_abstract_command dm_addr 0x%0h>", write_dm_addr);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 && write_dm_addr != 7'h39 &&
write_dm_addr != 7'h3A &&
write_dm_addr != 7'h3C)
$write("] <= 0x%08h; addr not supported", write_dm_word, "\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$display("DM_System_Bus.rule_sb_read_finish: setting rg_sbcs_sberror to DM_SBERROR_OTHER\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write(" rdr = ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write("'h%h", master_xactor_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
master_xactor_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
!master_xactor_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write("\n");
end
// synopsys translate_on
endmodule // mkDM_System_Bus
|
`timescale 1ps / 1ps
module main;
reg clk = 0;
always #300 clk = !clk;
reg [4:0] in = "11111";
reg [1:0] out;
reg [1:0] out_golden;
integer seed = 1234;
integer rvec_file;
integer ret;
integer soe0 = 0;
integer soe1 = 0;
initial begin
$sdf_annotate("mydesign.sdf",DUT,,,"MAXIMUM");
$dumpfile("test.vcd");
$dumpvars(0,main);
assert($urandom(seed));
`ifdef GENTEST
rvec_file = $fopen("../c17.rvec", "w");
`else
rvec_file = $fopen("../c17.rvec", "r");
`endif
if (rvec_file == 0) begin
$display("data_file handle was NULL");
$finish;
end
end
integer num_cycles = 0;
integer max_cycles = 100000;
always @ (posedge clk) begin
std::randomize(in);
if (num_cycles == max_cycles) begin
$display("SoE: %d,%d\n",soe0,soe1);
$fclose(rvec_file);
$finish;
end
num_cycles = num_cycles + 1;
end
c17 DUT (clk,in[0],in[1],in[2],in[3],in[4],out[0],out[1]);
always @ (posedge clk) begin
`ifdef GENTEST
// write output to generate golden result
$fwrite(rvec_file, "%b,%b\n", out[0],out[1]);
`else
$fscanf(rvec_file, "%b,%b\n", out_golden[0],out_golden[1]);
if (out[0] != out_golden[0]) begin
//$display("ERROR At time %t: out[0]=%b",$time,out[0]);
soe0 = soe0 + 1;
end
if (out[1] != out_golden[1]) begin
soe1 = soe1 + 1;
end
`endif
end // always @ (posedge clk)
always @(posedge clk) begin
//$display("At time %t: out[0]=%b,%b - out[1]=%b,%b",$time,out[0],out_golden[0],out[1],out_golden[1]);
end
endmodule
|
`include "define.h"
module uart_read( sync_reset, clk, rxd,buffer_reg, int_req);
input sync_reset;
input clk, rxd;
output [7:0] buffer_reg;
output int_req;
//________|-|______int_req (This module,, posedge interrupt)
//
//Spec. Upper module must service within 115.2Kbpsx8bit time. Maybe enough time...
//
//No error handling (overrun ) is supported.
reg rxq1;
reg [8:0] clk_ctr;
reg [2:0] bit_ctr;
reg [2:0] ua_state;
reg [7:0] rx_sr; //.,tx_sr;
reg int_req;
reg [7:0] buffer_reg;
wire clk_ctr_equ15, clk_ctr_equ31, bit_ctr_equ7,
clk_ctr_enable_state, bit_ctr_enable_state ;
wire clk_ctr_equ0;
//sync_reset
//synchronization
always @(posedge clk ) begin
rxq1 <=rxd ;
end
// 7bit counter
always @(posedge clk ) begin
if (sync_reset)
clk_ctr <= 0;
else if (clk_ctr_enable_state && clk_ctr_equ31) clk_ctr<=0;
else if (clk_ctr_enable_state) clk_ctr <= clk_ctr + 1;
else clk_ctr <= 0;
end
assign clk_ctr_equ15 = (clk_ctr==`COUNTER_VALUE1) ;//
assign clk_ctr_equ31 = (clk_ctr==`COUNTER_VALUE2) ;//
assign clk_ctr_equ0= (clk_ctr==`COUNTER_VALUE3); //
// 3bit counter
always @(posedge clk) begin
if (sync_reset)
bit_ctr <= 0;
else if (bit_ctr_enable_state) begin
if (clk_ctr_equ15)
bit_ctr <= bit_ctr + 1;
end
else
bit_ctr <= 0;
end
assign bit_ctr_equ7 = (bit_ctr==7);
assign clk_ctr_enable_state = ua_state !=3'b000 && ua_state<=3'b011;
assign bit_ctr_enable_state = ua_state==3'h2;
//
always @(posedge clk ) begin
if (sync_reset) ua_state <= 3'h0;
else begin
case (ua_state)
3'h0: if (rxq1==0) ua_state <= 3'h1; // if rxd==0 then goto next state and enable clock // start bit search
3'h1: if (clk_ctr_equ15) ua_state <= 3'h2; // start bit receive
3'h2: if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'h3;
3'h3: if (clk_ctr_equ15) ua_state <=3'h4; // stop bit receive
3'h4: ua_state <= 3'b000;
default: ua_state <= 3'b000;
endcase
end
end
//reg_we
always @(posedge clk ) begin
if (sync_reset) buffer_reg<=8'h00;
else if (ua_state==3'h3 && clk_ctr_equ0) buffer_reg<=rx_sr;
end
//int_req
always @(posedge clk ) begin
if (sync_reset) int_req<=1'b0;
else if (ua_state==3'h4 ) int_req<=1'b1; //
else int_req<=1'b0;
end
// rx shift reg.
always @(posedge clk ) begin
if (sync_reset) rx_sr <= 0;
else if (clk_ctr_equ15) rx_sr <= {rxq1, rx_sr[7:1]};
end
endmodule |
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SystemID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1500364641 : 255;
endmodule
|
/* pbkdfengine.v
*
* Copyright (c) 2013 kramble
* Parts copyright (c) 2011 [email protected]
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`define ICARUS // Comment this out when using the altera virtual_wire interface in ltcminer.v
`timescale 1ns/1ps
module pbkdfengine
(hash_clk, pbkdf_clk, data1, data2, data3, target, nonce_msb, nonce_out, golden_nonce_out, golden_nonce_match, loadnonce,
salsa_din, salsa_dout, salsa_busy, salsa_result, salsa_reset, salsa_start, salsa_shift);
input hash_clk; // Just drives shift register
input pbkdf_clk;
input [255:0] data1;
input [255:0] data2;
input [127:0] data3;
input [31:0] target;
input [3:0] nonce_msb;
output [31:0] nonce_out;
output [31:0] golden_nonce_out;
output golden_nonce_match; // Strobe valid one cycle on a match (needed for serial comms)
input loadnonce; // Strobe loads nonce (used for serial interface)
parameter SBITS = 8; // Shift data path width
input [SBITS-1:0] salsa_dout;
output [SBITS-1:0] salsa_din;
input salsa_busy, salsa_result; // NB hash_clk domain
output salsa_reset;
output salsa_start;
output reg salsa_shift = 1'b0; // NB hash_clk domain
reg [4:0]resetcycles = 4'd0;
reg reset = 1'b0;
assign salsa_reset = reset; // Propagate reset to salsaengine
`ifdef WANTCYCLICRESET
reg [23:0]cycresetcount = 24'd0;
`endif
always @ (posedge pbkdf_clk)
begin
// Hard code a 31 cycle reset (NB assumes THREADS=16 in salsaengine, else we need more)
// NB hash_clk is faster than pbkdf_clk so the salsaengine will actually be initialised well before
// this period ends, but keep to 15 for now as simulation uses equal pbkdf and salsa clock speeds.
resetcycles <= resetcycles + 1'd1;
if (resetcycles == 0)
reset <= 1'b1;
if (resetcycles == 31)
begin
reset <= 1'b0;
resetcycles <= 31;
end
`ifdef WANTCYCLICRESET
// Cyclical reset every 2_500_000 clocks to ensure salsa pipeline does not drift out of sync
// This may be unneccessary if we reset every loadnonce
// Actually it seems to do more harm than good, so disabled
cycresetcount <= cycresetcount + 1'd1;
if (cycresetcount == 2_500_000) // 10 per second at 25MHz (adjust as neccessary)
begin
cycresetcount <= 24'd0;
resetcycles <= 5'd0;
end
`endif
// Reset on loadnonce (the hash results will be junk anyway since data changes, so no loss of shares)
if (loadnonce)
resetcycles <= 5'd0;
end
`ifndef ICARUS
reg [31:0] nonce_previous_load = 32'hffffffff; // See note in salsa mix FSM
`endif
`ifndef NOMULTICORE
`ifdef SIM
reg [27:0] nonce_cnt = 28'h318f; // Start point for simulation (NB also define SIM in serial.v)
`else
reg [27:0] nonce_cnt = 28'd0; // Multiple cores use different prefix
`endif
wire [31:0] nonce;
assign nonce = { nonce_msb, nonce_cnt };
`else
reg [31:0] nonce = 32'd0; // NB Initially loaded from data3[127:96], see salsa mix FSM
`endif
assign nonce_out = nonce;
reg [31:0] nonce_sr = 32'd0; // Nonce is shifted to salsaengine for storage/retrieval (hash_clk domain)
reg [31:0] golden_nonce = 32'd0;
assign golden_nonce_out = golden_nonce;
reg golden_nonce_match = 1'b0;
reg [2:0] nonce_wait = 3'd0;
reg [255:0] rx_state;
reg [511:0] rx_input;
wire [255:0] tx_hash;
reg [255:0] khash = 256'd0; // Key hash (NB scrypt.c calls this ihash)
reg [255:0] ihash = 256'd0; // IPAD hash
reg [255:0] ohash = 256'd0; // OPAD hash
`ifdef SIM
reg [255:0] final_hash = 256'd0; // Just for DEBUG, only need top 32 bits in live code.
`endif
reg [2:0] blockcnt = 3'd0; // Takes values 1..5 for block iteration
reg [1023:0] Xbuf = 1024'd0; // Shared input/output buffer and shift register (hash_clk domain)
reg [5:0] cnt = 6'd0;
wire feedback;
assign feedback = (cnt != 6'b0);
assign salsa_din = Xbuf[1023:1024-SBITS];
wire [1023:0] MixOutRewire; // Need to do endian conversion (see the generate below)
// MixOut is little-endian word format to match scrypt.c so convert back to big-endian
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : Xrewire
wire [31:0] mix;
assign mix = Xbuf[`IDX(i)]; // NB MixOut now shares Xbuf since shifted in/out
assign MixOutRewire[`IDX(i)] = { mix[7:0], mix[15:8], mix[23:16], mix[31:24] };
end
endgenerate
// Interface control. This should be OK provided the threads remain evenly spaced (hence we reset on loadnonce)
reg SMixInRdy_state = 1'b0; // SMix input ready flag (set in SHA256, reset in SMIX)
reg SMixOutRdy_state = 1'b0; // SMix output ready flag (set in SMIX, reset in SHA256)
wire SMixInRdy;
wire SMixOutRdy;
reg Set_SMixInRdy = 1'b0;
reg Clr_SMixOutRdy = 1'b0;
wire Clr_SMixInRdy;
wire Set_SMixOutRdy;
reg [4:0]salsa_busy_d = 0; // Sync to pbkdf_clk domain
reg [4:0]salsa_result_d = 0;
always @ (posedge hash_clk)
begin
// Sync to pbkdf_clk domain
salsa_busy_d[0] <= salsa_busy;
if (salsa_busy & ~ salsa_busy_d[0])
salsa_busy_d[1] <= ~ salsa_busy_d[1]; // Toggle on busy going high
salsa_result_d[0] <= salsa_result;
if (salsa_result & ~ salsa_result_d[0])
salsa_result_d[1] <= ~ salsa_result_d[1]; // Toggle on result going high
end
always @ (posedge pbkdf_clk)
begin
salsa_busy_d[4:2] <= salsa_busy_d[3:1];
salsa_result_d[4:2] <= salsa_result_d[3:1];
if (Set_SMixInRdy)
SMixInRdy_state <= 1'b1;
if (Clr_SMixInRdy)
SMixInRdy_state <= 1'b0; // Clr overrides set
if (Set_SMixOutRdy)
SMixOutRdy_state <= 1'b1;
if (Clr_SMixOutRdy)
SMixOutRdy_state <= 1'b0; // Clr overrides set
// CARE there is a race with Set_SMixInRdy, Clr_SMixOutRdy which are set in the FSM
// Need to assert reset for several cycles to ensure consistency (acutally use 15 since salsaengine needs more)
if (reset)
begin // Reset takes priority
SMixInRdy_state <= 1'b0;
SMixOutRdy_state <= 1'b0;
end
end
assign Clr_SMixInRdy = SMixInRdy_state & (salsa_busy_d[3] ^ salsa_busy_d[4]); // Clear on transition to busy
assign Set_SMixOutRdy = ~SMixOutRdy_state & (salsa_result_d[3] ^ salsa_result_d[4]); // Set on transition to result
// Achieves identical timing to original version, but probably overkill
assign SMixInRdy = Clr_SMixInRdy ? 1'b0 : Set_SMixInRdy ? 1'b1 : SMixInRdy_state;
assign SMixOutRdy = Clr_SMixOutRdy ? 1'b0 : Set_SMixOutRdy ? 1'b1 : SMixOutRdy_state;
assign salsa_start = SMixInRdy;
// Clock crossing flags for shift register control (span pbkdf_clk, hash_clk domains)
reg [3:0]Xbuf_load_request = 1'b0;
reg [3:0]shift_request = 1'b0;
reg [3:0]shift_acknowledge = 1'b0;
// Controller FSM for PBKDF2_SHA256_80_128 (multiple hashes using the sha256_transform)
// Based on scrypt.c from cgminer (Colin Percival, ArtForz)
parameter S_IDLE=0,
S_H1= 1, S_H2= 2, S_H3= 3, S_H4= 4, S_H5= 5, S_H6= 6, // Initial hash of block header (khash)
S_I1= 7, S_I2= 8, S_I3= 9, S_I4=10, S_I5=11, S_I6=12, // IPAD hash (ihash)
S_O1=13, S_O2=14, S_O3=15, // OPAD hash (ohash)
S_B1=16, S_B2=17, S_B3=18, S_B4=19, S_B5=20, S_B6=21, // Iterate blocks
S_NONCE=22, S_SHIFT_IN=41, S_SHIFT_OUT=42, // Direction relative to salsa unit
// Final PBKDF2_SHA256_80_128_32 (reuses S_H1 to S_H6 for khash, alternatively could piplenine value)
S_R1=23, S_R2=24, S_R3=25, S_R4=26, S_R5=27, S_R6=28, // Final PBKDF2_SHA256_80_128_32
S_R7=29, S_R8=30, S_R9=31, S_R10=32, S_R11=33, S_R12=34,
S_R13=35, S_R14=36, S_R15=37, S_R16=38, S_R17=39, S_R18=40;
reg [5:0] state = S_IDLE;
reg mode = 0; // 0=PBKDF2_SHA256_80_128, 1=PBKDF2_SHA256_80_128_32
reg start_output = 0;
always @ (posedge pbkdf_clk)
begin
Set_SMixInRdy <= 1'b0; // Ugly hack, these are overriden below
Clr_SMixOutRdy <= 1'b0;
golden_nonce_match <= 1'b0; // Default to reset
shift_acknowledge[3:1] <= shift_acknowledge[2:0]; // Clock crossing
`ifdef ICARUS
if (loadnonce) // Separate clock domains means comparison is unsafe
`else
if (loadnonce || (nonce_previous_load != data3[127:96]))
`endif
begin
`ifdef NOMULTICORE
nonce <= data3[127:96]; // Supports loading of initial nonce for test purposes (potentially
// overriden by the increment below, but this occurs very rarely)
// This also gives a consistent start point when we send the first work
// packet (but ONLY the first one since its always zero) when using live data
// as we initialise nonce_previous_load to ffffffff
`else
nonce_cnt <= data3[123:96]; // The 4 msb of nonce are hardwired in MULTICORE mode, so test nonce
// needs to be <= 0fffffff and will only match in the 0 core
`endif
`ifndef ICARUS
nonce_previous_load <= data3[127:96];
`endif
end
if (reset == 1'b1)
begin
state <= S_IDLE;
start_output <= 1'b0;
end
else
begin
case (state)
S_IDLE: begin
if (SMixOutRdy & ~start_output)
begin
shift_request[0] <= ~shift_request[0]; // Request shifter to start
state <= S_SHIFT_OUT;
end
else
begin
if (start_output || // Process output
!SMixInRdy) // Process input unless already done
begin
start_output <= 1'b0;
mode <= 1'b0;
// Both cases use same initial calculaton of khash (its not worth trying to reuse previous khash
// for the second case as we're not constrained by SHA256 timing)
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { data2, data1 }; // Block header is passwd (used as key)
blockcnt <= 3'd1;
cnt <= 6'd0;
if (SMixOutRdy) // Give preference to output
mode <= 1'b1;
state <= S_H1;
end
end
end
// Hash the block header (result is khash)
S_H1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H2;
end
end
S_H2: begin // Sync hash
state <= S_H3;
end
S_H3: begin // Sync hash
rx_state <= tx_hash;
// Hash last 16 bytes of header including nonce and padded to 64 bytes with 1, zeros and length
// NB this sequence is used for both input and final PBKDF2_SHA256, hence switch nonce on mode
rx_input <= { 384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000,
mode ? nonce_sr : nonce, data3[95:0] };
state <= S_H4;
end
S_H4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H5;
end
end
S_H5: begin // Sync hash
state <= S_H6;
end
S_H6: begin // Sync hash
khash <= tx_hash; // Save for OPAD hash
// Setup for IPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h3636363636363636363636363636363636363636363636363636363636363636 ,
tx_hash ^ 256'h3636363636363636363636363636363636363636363636363636363636363636 };
cnt <= 6'd0;
if (mode)
state <= S_R1;
else
state <= S_I1;
end
// IPAD hash
S_I1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I2;
end
end
S_I2: begin // Sync hash
state <= S_I3;
end
S_I3: begin // Sync hash
rx_state <= tx_hash;
rx_input <= { data2, data1 }; // Passwd (used as message)
state <= S_I4;
end
S_I4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I5;
end
end
S_I5: begin // Sync hash
state <= S_I6;
end
S_I6: begin // Sync hash
ihash <= tx_hash; // Save result
// Setup for OPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_O1;
end
// OPAD hash
S_O1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_O2;
end
end
S_O2: begin // Sync hash
state <= S_O3;
end
S_O3: begin // Sync hash
ohash <= tx_hash; // Save result
// Setup for block iteration
rx_state <= ihash;
// TODO hardwire top 29 bits of blockcnt as zero
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
29'd0, blockcnt, nonce, data3[95:0] }; // blockcnt is 3 bits, top 29 are hardcoded 0
blockcnt <= blockcnt + 1'd1; // Increment for next time
cnt <= 6'd0;
state <= S_B1;
end
// Block iteration (4 cycles)
S_B1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B2;
end
end
S_B2: begin // Sync hash
state <= S_B3;
end
S_B3: begin // Sync hash
rx_state <= ohash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, tx_hash };
state <= S_B4;
end
S_B4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B5;
end
end
S_B5: begin // Sync hash
state <= S_B6;
end
S_B6: begin
khash <= tx_hash; // Save temporarily (for Xbuf)
Xbuf_load_request[0] <= ~Xbuf_load_request[0]; // NB also loads nonce_sr
if (blockcnt == 3'd5)
begin
nonce_wait <= 3'd7;
state <= S_NONCE;
end
else begin
// Setup for next block
rx_state <= ihash;
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
29'd0, blockcnt, nonce, data3[95:0] }; // blockcnt is 3 bits, top 29 are hardcoded 0
blockcnt <= blockcnt + 1'd1; // Increment for next time
cnt <= 6'd0;
state <= S_B1;
end
end
S_NONCE: begin
// Need to delay a few clocks for Xbuf_load_request to complete
nonce_wait <= nonce_wait - 1'd1;
if (nonce_wait == 0)
begin
`ifndef NOMULTICORE
nonce_cnt <= nonce_cnt + 1'd1;
`else
nonce <= nonce + 1'd1;
`endif
shift_request[0] <= ~shift_request[0];
state <= S_SHIFT_IN;
end
end
S_SHIFT_IN: begin // Shifting from PBKDF2_SHA256 to salsa
if (shift_acknowledge[3] != shift_acknowledge[2])
begin
Set_SMixInRdy <= 1'd1; // Flag salsa to start
state <= S_IDLE;
end
end
S_SHIFT_OUT: begin // Shifting from salsa to PBKDF2_SHA256
if (shift_acknowledge[3] != shift_acknowledge[2])
begin
start_output <= 1'd1; // Flag self to start
state <= S_IDLE;
end
end
// Final PBKDF2_SHA256_80_128_32 NB Entered from S_H6 via mode flag
// Similar to S_I0 but using MixOut as salt and finalblk padding
S_R1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R2;
end
end
S_R2: begin // Sync hash
state <= S_R3;
end
S_R3: begin // Sync hash
rx_state <= tx_hash;
rx_input <= MixOutRewire[511:0]; // Salt (first block)
state <= S_R4;
end
S_R4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R5;
end
end
S_R5: begin // Sync hash
state <= S_R6;
end
S_R6: begin // Sync hash
rx_state <= tx_hash;
rx_input <= MixOutRewire[1023:512]; // Salt (second block)
state <= S_R7;
end
S_R7: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R8;
end
end
S_R8: begin // Sync hash
state <= S_R9;
end
S_R9: begin // Sync hash
rx_state <= tx_hash;
// Final padding
rx_input <= 512'h00000620000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000001;
state <= S_R10;
end
S_R10: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R11;
end
end
S_R11: begin // Sync hash
state <= S_R12;
end
S_R12: begin // Sync hash
ihash <= tx_hash; // Save (reuse ihash)
// Setup for OPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_R13;
end
S_R13: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R14;
end
end
S_R14: begin // Sync hash
state <= S_R15;
end
S_R15: begin // Sync hash
rx_state <= tx_hash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, ihash };
state <= S_R16;
end
S_R16: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R17;
end
end
S_R17: begin // Sync hash
state <= S_R18;
end
S_R18: begin // Sync hash
// Check for golden nonce in tx_hash
`ifdef SIM
final_hash <= tx_hash; // For debug
`endif
// Could optimise target calc ...
if ( { tx_hash[231:224], tx_hash[239:232], tx_hash[247:240], tx_hash[255:248] } < target)
begin
golden_nonce <= nonce_sr;
golden_nonce_match <= 1'b1; // Set flag (for one cycle only, see default at top)
end
state <= S_IDLE;
mode <= 1'b0;
// SMixOutRdy <= 1'b0; // Original version
Clr_SMixOutRdy <= 1'b1; // Ugly hack
end
endcase
end
end
// Shift register control - NB hash_clk domain
reg [10:0]shift_count = 11'd0; // hash_clk domain
always @ (posedge hash_clk)
begin
if (reset)
begin
salsa_shift <= 1'b0;
shift_count <= 11'd0;
end
// Clock crossing logic
Xbuf_load_request[3:1] <= Xbuf_load_request[2:0];
if (Xbuf_load_request[3] != Xbuf_load_request[2])
begin
// Shift output into X buffer from MSB->LSB
Xbuf[255:0] <= Xbuf[511:256];
Xbuf[511:256] <= Xbuf[767:512];
Xbuf[767:512] <= Xbuf[1023:768];
Xbuf[1023:768] <= khash;
nonce_sr <= nonce; // Loaded several times, but of no consequence
end
shift_request[3:1] <= shift_request[2:0];
if (shift_request[3] != shift_request[2])
begin
salsa_shift <= 1'b1;
end
if (salsa_shift)
begin
shift_count <= shift_count + 1'b1;
Xbuf <= { Xbuf[1023-SBITS:0], nonce_sr[31:32-SBITS] };
nonce_sr <= { nonce_sr[31-SBITS:0], salsa_dout };
end
if (shift_count == (1024+32)/SBITS-1)
begin
shift_acknowledge[0] = ~shift_acknowledge[0];
shift_count <= 0;
salsa_shift <= 0;
end
end
// Using LOOP=64 to simplify timing (needs slightly modified version of original sha256_transform.v)
// since pipelining is inappropriate for ltc (we need to rehash same data several times in succession)
sha256_transform # (.LOOP(64)) sha256_blk (
.clk(pbkdf_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(rx_state),
.rx_input(rx_input),
.tx_hash(tx_hash)
);
endmodule |
/*
:Project
FPGA-Imaging-Library
:Design
FrameController2
:Function
Controlling a frame(block ram etc.), writing or reading with counts.
For controlling a BlockRAM from xilinx.
Give the first output after mul_delay + 2 + ram_read_latency cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-25
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
[email protected]
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module FrameController2(
clk,
rst_n,
in_count_x,
in_count_y,
in_enable,
in_data,
out_ready,
out_data,
ram_addr);
/*
::description
This module's working mode.
::range
0 for Pipline, 1 for Req-ack
*/
parameter work_mode = 0;
/*
::description
This module's WR mode.
::range
0 for Write, 1 for Read
*/
parameter wr_mode = 0;
/*
::description
Data bit width.
*/
parameter data_width = 8;
/*
::description
Width of image.
::range
1 - 4096
*/
parameter im_width = 320;
/*
::description
Height of image.
::range
1 - 4096
*/
parameter im_height = 240;
/*
::description
The bits of width of image.
::range
Depend on width of image
*/
parameter im_width_bits = 9;
/*
::description
Address bit width of a ram for storing this image.
::range
Depend on im_width and im_height.
*/
parameter addr_width = 17;
/*
::description
RL of RAM, in xilinx 7-series device, it is 2.
::range
0 - 15, Depend on your using ram.
*/
parameter ram_read_latency = 2;
/*
::description
Delay for multiplier.
::range
Depend on your multilpliers' configurations
*/
parameter mul_delay = 3;
/*
::description
Clock.
*/
input clk;
/*
::description
Reset, active low.
*/
input rst_n;
/*
::description
Input pixel count for width.
*/
input[im_width_bits - 1 : 0] in_count_x;
/*
::description
Input pixel count for height.
*/
input[im_width_bits - 1 : 0] in_count_y;
/*
::description
Input data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
*/
input in_enable;
/*
::description
Input data, it must be synchronous with in_enable.
*/
input [data_width - 1 : 0] in_data;
/*
::description
Output data ready, in both two mode, it will be high while the out_data can be read.
*/
output out_ready;
/*
::description
Output data, it will be synchronous with out_ready.
*/
output[data_width - 1 : 0] out_data;
/*
::description
Address for ram.
*/
output[addr_width - 1 : 0] ram_addr;
reg[3 : 0] con_enable;
reg[im_width_bits - 1 : 0] reg_in_count_x;
reg[im_width_bits - 1 : 0] reg_in_count_y;
reg[addr_width - 1 : 0] reg_addr;
wire[11 : 0] mul_a, mul_b;
wire[23 : 0] mul_p;
assign mul_a = {{(12 - im_width_bits){1'b0}}, in_count_y};
assign mul_b = im_width;
genvar i;
generate
/*
::description
Multiplier for Unsigned 12bits x Unsigned 12bits, used for creating address for frame.
You can configure the multiplier by yourself, then change the "mul_delay".
You can not change the ports' configurations!
*/
Multiplier12x12FR2 Mul(.CLK(clk), .A(mul_a), .B(mul_b), .SCLR(~rst_n), .P(mul_p));
for (i = 0; i < mul_delay; i = i + 1) begin : conut_buffer
reg[im_width_bits - 1 : 0] b;
if(i == 0) begin
always @(posedge clk)
b <= in_count_x;
end else begin
always @(posedge clk)
b <= conut_buffer[i - 1].b;
end
end
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable) begin
reg_addr <= 0;
end else begin
reg_addr <= mul_p + conut_buffer[mul_delay - 1].b;
end
end
assign ram_addr = reg_addr;
if(wr_mode == 0) begin
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
con_enable <= 0;
else if(con_enable == mul_delay + 1)
con_enable <= con_enable;
else
con_enable <= con_enable + 1;
end
assign out_ready = con_enable == mul_delay + 1 ? 1 : 0;
if(work_mode == 0) begin
for (i = 0; i < mul_delay + 1; i = i + 1) begin : buffer
reg[data_width - 1 : 0] b;
if(i == 0) begin
always @(posedge clk)
b <= in_data;
end else begin
always @(posedge clk)
b <= buffer[i - 1].b;
end
end
assign out_data = out_ready ? buffer[mul_delay].b : 0;
end else begin
reg[data_width - 1 : 0] reg_out_data;
always @(posedge in_enable)
reg_out_data = in_data;
assign out_data = out_ready ? reg_out_data : 0;
end
end else begin
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
con_enable <= 0;
else if (con_enable == mul_delay + 1 + ram_read_latency)
con_enable <= con_enable;
else
con_enable <= con_enable + 1;
end
assign out_data = out_ready ? in_data : 0;
assign out_ready = con_enable == mul_delay + 1 + ram_read_latency ? 1 : 0;
end
endgenerate
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND2_TB_V
`define SKY130_FD_SC_HD__TAPVGND2_TB_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__tapvgnd2.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hd__tapvgnd2 dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND2_TB_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
input clk;
m3 m3_inst (.clk(clk));
defparam m3_inst.FROMDEFP = 19;
defparam m3_inst.P2 = 2;
//defparam m3_inst.P3 = PAR;
defparam m3_inst.P3 = 3;
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module m3
(/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam LOC = 13;
parameter UNCH = 99;
parameter P1 = 10;
parameter P2 = 20;
parameter P3 = 30;
parameter FROMDEFP = 11;
initial begin
$display("%x %x %x",P1,P2,P3);
end
always @ (posedge clk) begin
if (UNCH !== 99) $stop;
if (P1 !== 10) $stop;
if (P2 !== 2) $stop;
if (P3 !== 3) $stop;
if (FROMDEFP !== 19) $stop;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : round_robin_arb.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// A simple round robin arbiter implemented in a not so simple
// way. Two things make this special. First, it takes width as
// a parameter and secondly it's constructed in a way to work with
// restrictions synthesis programs.
//
// Consider each req/grant pair to be a
// "channel". The arbiter computes a grant response to a request
// on a channel by channel basis.
//
// The arbiter implementes a "round robin" algorithm. Ie, the granting
// process is totally fair and symmetric. Each requester is given
// equal priority. If all requests are asserted, the arbiter will
// work sequentially around the list of requesters, giving each a grant.
//
// Grant priority is based on the "last_master". The last_master
// vector stores the channel receiving the most recent grant. The
// next higher numbered channel (wrapping around to zero) has highest
// priority in subsequent cycles. Relative priority wraps around
// the request vector with the last_master channel having lowest priority.
//
// At the highest implementation level, a per channel inhibit signal is computed.
// This inhibit is bit-wise AND'ed with the incoming requests to
// generate the grant.
//
// There will be at most a single grant per state. The logic
// of the arbiter depends on this.
//
// Once a grant is given, it is stored as the last_master. The
// last_master vector is initialized at reset to the zero'th channel.
// Although the particular channel doesn't matter, it does matter
// that the last_master contains a valid grant pattern.
//
// The heavy lifting is in computing the per channel inhibit signals.
// This is accomplished in the generate statement.
//
// The first "for" loop in the generate statement steps through the channels.
//
// The second "for" loop steps through the last mast_master vector
// for each channel. For each last_master bit, an inh_group is generated.
// Following the end of the second "for" loop, the inh_group signals are OR'ed
// together to generate the overall inhibit bit for the channel.
//
// For a four bit wide arbiter, this is what's generated for channel zero:
//
// inh_group[1] = last_master[0] && |req[3:1]; // any other req inhibits
// inh_group[2] = last_master[1] && |req[3:2]; // req[3], or req[2] inhibit
// inh_group[3] = last_master[2] && |req[3:3]; // only req[3] inhibits
//
// For req[0], last_master[3] is ignored because channel zero is highest priority
// if last_master[3] is true.
//
`timescale 1ps/1ps
module mig_7series_v4_0_round_robin_arb
#(
parameter TCQ = 100,
parameter WIDTH = 3
)
(
/*AUTOARG*/
// Outputs
grant_ns, grant_r,
// Inputs
clk, rst, req, disable_grant, current_master, upd_last_master
);
input clk;
input rst;
input [WIDTH-1:0] req;
wire [WIDTH-1:0] last_master_ns;
reg [WIDTH*2-1:0] dbl_last_master_ns;
always @(/*AS*/last_master_ns)
dbl_last_master_ns = {last_master_ns, last_master_ns};
reg [WIDTH*2-1:0] dbl_req;
always @(/*AS*/req) dbl_req = {req, req};
reg [WIDTH-1:0] inhibit = {WIDTH{1'b0}};
genvar i;
genvar j;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : channel
wire [WIDTH-1:1] inh_group;
for (j = 0; j < (WIDTH-1); j = j + 1) begin : last_master
assign inh_group[j+1] =
dbl_last_master_ns[i+j] && |dbl_req[i+WIDTH-1:i+j+1];
end
always @(/*AS*/inh_group) inhibit[i] = |inh_group;
end
endgenerate
input disable_grant;
output wire [WIDTH-1:0] grant_ns;
assign grant_ns = req & ~inhibit & {WIDTH{~disable_grant}};
output reg [WIDTH-1:0] grant_r;
always @(posedge clk) grant_r <= #TCQ grant_ns;
input [WIDTH-1:0] current_master;
input upd_last_master;
reg [WIDTH-1:0] last_master_r;
localparam ONE = 1 << (WIDTH - 1); //Changed form '1' to fix the CR #544024
//A '1' in the LSB of the last_master_r
//signal gives a low priority to req[0]
//after reset. To avoid this made MSB as
//'1' at reset.
assign last_master_ns = rst
? ONE[0+:WIDTH]
: upd_last_master
? current_master
: last_master_r;
always @(posedge clk) last_master_r <= #TCQ last_master_ns;
`ifdef MC_SVA
grant_is_one_hot_zero:
assert property (@(posedge clk) (rst || $onehot0(grant_ns)));
last_master_r_is_one_hot:
assert property (@(posedge clk) (rst || $onehot(last_master_r)));
`endif
endmodule
|
// megafunction wizard: %ALTFP_CONVERT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTFP_CONVERT
// ============================================================
// File Name: acl_fp_uitofp.v
// Megafunction Name(s):
// ALTFP_CONVERT
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altfp_convert CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" OPERATION="INT2FLOAT" ROUNDING="TO_NEAREST" WIDTH_DATA=33 WIDTH_EXP_INPUT=8 WIDTH_EXP_OUTPUT=8 WIDTH_INT=33 WIDTH_MAN_INPUT=23 WIDTH_MAN_OUTPUT=23 WIDTH_RESULT=32 clk_en clock dataa result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_convert 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsyncram 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_abs 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_decode 2010:08:18:21:07:12:SJ cbx_lpm_divide 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_stratixiii 2010:08:18:21:07:13:SJ cbx_stratixv 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=2 SHIFTDIR="LEFT" SHIFTTYPE="LOGICAL" WIDTH=33 WIDTHDIST=6 aclr clk_en clock data distance result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources = reg 71
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altbarrel_shift_ssf
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [32:0] data;
input [5:0] distance;
output [32:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [1:0] dir_pipe;
reg [32:0] sbit_piper1d;
reg [32:0] sbit_piper2d;
reg sel_pipec3r1d;
reg sel_pipec4r1d;
reg sel_pipec5r1d;
wire [6:0] dir_w;
wire direction_w;
wire [31:0] pad_w;
wire [230:0] sbit_w;
wire [5:0] sel_w;
wire [197:0] smux_w;
// synopsys translate_off
initial
dir_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 2'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[5], dir_w[2]};
// synopsys translate_off
initial
sbit_piper1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 33'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[98:66];
// synopsys translate_off
initial
sbit_piper2d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper2d <= 33'b0;
else if (clk_en == 1'b1) sbit_piper2d <= smux_w[197:165];
// synopsys translate_off
initial
sel_pipec3r1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec3r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec3r1d <= distance[3];
// synopsys translate_off
initial
sel_pipec4r1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec4r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec4r1d <= distance[4];
// synopsys translate_off
initial
sel_pipec5r1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec5r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec5r1d <= distance[5];
assign
dir_w = {dir_pipe[1], dir_w[4:3], dir_pipe[0], dir_w[1:0], direction_w},
direction_w = 1'b0,
pad_w = {32{1'b0}},
result = sbit_w[230:198],
sbit_w = {sbit_piper2d, smux_w[164:99], sbit_piper1d, smux_w[65:0], data},
sel_w = {sel_pipec5r1d, sel_pipec4r1d, sel_pipec3r1d, distance[2:0]},
smux_w = {((({33{(sel_w[5] & (~ dir_w[5]))}} & {sbit_w[165], pad_w[31:0]}) | ({33{(sel_w[5] & dir_w[5])}} & {pad_w[31:0], sbit_w[197]})) | ({33{(~ sel_w[5])}} & sbit_w[197:165])), ((({33{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[148:132], pad_w[15:0]}) | ({33{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[164:148]})) | ({33{(~ sel_w[4])}} & sbit_w[164:132])), ((({33{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[123:99], pad_w[7:0]}) | ({33{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[131:107]})) | ({33{(~ sel_w[3])}} & sbit_w[131:99])), ((({33{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[94:66], pad_w[3:0]}) | ({33{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[98:70]})) | ({33{(~ sel_w[2])}} & sbit_w[98:66])), ((({33{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[63:33], pad_w[1:0]}) | ({33{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[65:35]})) | ({33{(~ sel_w[1])}} & sbit_w[65:33])), ((({33{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[31:0], pad_w[0]}) | ({33{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[32:1]})) | ({33{(~ sel_w[0])}} & sbit_w[32:0]))};
endmodule //acl_fp_uitofp_altbarrel_shift_ssf
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" WIDTH=64 WIDTHAD=6 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=32 WIDTHAD=5 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altpriority_encoder_3e8
(
data,
q,
zero) ;
input [1:0] data;
output [0:0] q;
output zero;
assign
q = {data[1]},
zero = (~ (data[0] | data[1]));
endmodule //acl_fp_uitofp_altpriority_encoder_3e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altpriority_encoder_6e8
(
data,
q,
zero) ;
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder17_q;
wire wire_altpriority_encoder17_zero;
wire [0:0] wire_altpriority_encoder18_q;
wire wire_altpriority_encoder18_zero;
acl_fp_uitofp_altpriority_encoder_3e8 altpriority_encoder17
(
.data(data[1:0]),
.q(wire_altpriority_encoder17_q),
.zero(wire_altpriority_encoder17_zero));
acl_fp_uitofp_altpriority_encoder_3e8 altpriority_encoder18
(
.data(data[3:2]),
.q(wire_altpriority_encoder18_q),
.zero(wire_altpriority_encoder18_zero));
assign
q = {(~ wire_altpriority_encoder18_zero), ((wire_altpriority_encoder18_zero & wire_altpriority_encoder17_q) | ((~ wire_altpriority_encoder18_zero) & wire_altpriority_encoder18_q))},
zero = (wire_altpriority_encoder17_zero & wire_altpriority_encoder18_zero);
endmodule //acl_fp_uitofp_altpriority_encoder_6e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altpriority_encoder_be8
(
data,
q,
zero) ;
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder15_q;
wire wire_altpriority_encoder15_zero;
wire [1:0] wire_altpriority_encoder16_q;
wire wire_altpriority_encoder16_zero;
acl_fp_uitofp_altpriority_encoder_6e8 altpriority_encoder15
(
.data(data[3:0]),
.q(wire_altpriority_encoder15_q),
.zero(wire_altpriority_encoder15_zero));
acl_fp_uitofp_altpriority_encoder_6e8 altpriority_encoder16
(
.data(data[7:4]),
.q(wire_altpriority_encoder16_q),
.zero(wire_altpriority_encoder16_zero));
assign
q = {(~ wire_altpriority_encoder16_zero), (({2{wire_altpriority_encoder16_zero}} & wire_altpriority_encoder15_q) | ({2{(~ wire_altpriority_encoder16_zero)}} & wire_altpriority_encoder16_q))},
zero = (wire_altpriority_encoder15_zero & wire_altpriority_encoder16_zero);
endmodule //acl_fp_uitofp_altpriority_encoder_be8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altpriority_encoder_rf8
(
data,
q,
zero) ;
input [15:0] data;
output [3:0] q;
output zero;
wire [2:0] wire_altpriority_encoder13_q;
wire wire_altpriority_encoder13_zero;
wire [2:0] wire_altpriority_encoder14_q;
wire wire_altpriority_encoder14_zero;
acl_fp_uitofp_altpriority_encoder_be8 altpriority_encoder13
(
.data(data[7:0]),
.q(wire_altpriority_encoder13_q),
.zero(wire_altpriority_encoder13_zero));
acl_fp_uitofp_altpriority_encoder_be8 altpriority_encoder14
(
.data(data[15:8]),
.q(wire_altpriority_encoder14_q),
.zero(wire_altpriority_encoder14_zero));
assign
q = {(~ wire_altpriority_encoder14_zero), (({3{wire_altpriority_encoder14_zero}} & wire_altpriority_encoder13_q) | ({3{(~ wire_altpriority_encoder14_zero)}} & wire_altpriority_encoder14_q))},
zero = (wire_altpriority_encoder13_zero & wire_altpriority_encoder14_zero);
endmodule //acl_fp_uitofp_altpriority_encoder_rf8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altpriority_encoder_qf8
(
data,
q,
zero) ;
input [31:0] data;
output [4:0] q;
output zero;
wire [3:0] wire_altpriority_encoder11_q;
wire wire_altpriority_encoder11_zero;
wire [3:0] wire_altpriority_encoder12_q;
wire wire_altpriority_encoder12_zero;
acl_fp_uitofp_altpriority_encoder_rf8 altpriority_encoder11
(
.data(data[15:0]),
.q(wire_altpriority_encoder11_q),
.zero(wire_altpriority_encoder11_zero));
acl_fp_uitofp_altpriority_encoder_rf8 altpriority_encoder12
(
.data(data[31:16]),
.q(wire_altpriority_encoder12_q),
.zero(wire_altpriority_encoder12_zero));
assign
q = {(~ wire_altpriority_encoder12_zero), (({4{wire_altpriority_encoder12_zero}} & wire_altpriority_encoder11_q) | ({4{(~ wire_altpriority_encoder12_zero)}} & wire_altpriority_encoder12_q))},
zero = (wire_altpriority_encoder11_zero & wire_altpriority_encoder12_zero);
endmodule //acl_fp_uitofp_altpriority_encoder_qf8
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=32 WIDTHAD=5 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altpriority_encoder_3v7
(
data,
q) ;
input [1:0] data;
output [0:0] q;
assign
q = {data[1]};
endmodule //acl_fp_uitofp_altpriority_encoder_3v7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altpriority_encoder_6v7
(
data,
q) ;
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder25_q;
wire [0:0] wire_altpriority_encoder26_q;
wire wire_altpriority_encoder26_zero;
acl_fp_uitofp_altpriority_encoder_3v7 altpriority_encoder25
(
.data(data[1:0]),
.q(wire_altpriority_encoder25_q));
acl_fp_uitofp_altpriority_encoder_3e8 altpriority_encoder26
(
.data(data[3:2]),
.q(wire_altpriority_encoder26_q),
.zero(wire_altpriority_encoder26_zero));
assign
q = {(~ wire_altpriority_encoder26_zero), ((wire_altpriority_encoder26_zero & wire_altpriority_encoder25_q) | ((~ wire_altpriority_encoder26_zero) & wire_altpriority_encoder26_q))};
endmodule //acl_fp_uitofp_altpriority_encoder_6v7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altpriority_encoder_bv7
(
data,
q) ;
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder23_q;
wire [1:0] wire_altpriority_encoder24_q;
wire wire_altpriority_encoder24_zero;
acl_fp_uitofp_altpriority_encoder_6v7 altpriority_encoder23
(
.data(data[3:0]),
.q(wire_altpriority_encoder23_q));
acl_fp_uitofp_altpriority_encoder_6e8 altpriority_encoder24
(
.data(data[7:4]),
.q(wire_altpriority_encoder24_q),
.zero(wire_altpriority_encoder24_zero));
assign
q = {(~ wire_altpriority_encoder24_zero), (({2{wire_altpriority_encoder24_zero}} & wire_altpriority_encoder23_q) | ({2{(~ wire_altpriority_encoder24_zero)}} & wire_altpriority_encoder24_q))};
endmodule //acl_fp_uitofp_altpriority_encoder_bv7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altpriority_encoder_r08
(
data,
q) ;
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder21_q;
wire [2:0] wire_altpriority_encoder22_q;
wire wire_altpriority_encoder22_zero;
acl_fp_uitofp_altpriority_encoder_bv7 altpriority_encoder21
(
.data(data[7:0]),
.q(wire_altpriority_encoder21_q));
acl_fp_uitofp_altpriority_encoder_be8 altpriority_encoder22
(
.data(data[15:8]),
.q(wire_altpriority_encoder22_q),
.zero(wire_altpriority_encoder22_zero));
assign
q = {(~ wire_altpriority_encoder22_zero), (({3{wire_altpriority_encoder22_zero}} & wire_altpriority_encoder21_q) | ({3{(~ wire_altpriority_encoder22_zero)}} & wire_altpriority_encoder22_q))};
endmodule //acl_fp_uitofp_altpriority_encoder_r08
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altpriority_encoder_q08
(
data,
q) ;
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder19_q;
wire [3:0] wire_altpriority_encoder20_q;
wire wire_altpriority_encoder20_zero;
acl_fp_uitofp_altpriority_encoder_r08 altpriority_encoder19
(
.data(data[15:0]),
.q(wire_altpriority_encoder19_q));
acl_fp_uitofp_altpriority_encoder_rf8 altpriority_encoder20
(
.data(data[31:16]),
.q(wire_altpriority_encoder20_q),
.zero(wire_altpriority_encoder20_zero));
assign
q = {(~ wire_altpriority_encoder20_zero), (({4{wire_altpriority_encoder20_zero}} & wire_altpriority_encoder19_q) | ({4{(~ wire_altpriority_encoder20_zero)}} & wire_altpriority_encoder20_q))};
endmodule //acl_fp_uitofp_altpriority_encoder_q08
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altpriority_encoder_0c6
(
data,
q) ;
input [63:0] data;
output [5:0] q;
wire [4:0] wire_altpriority_encoder10_q;
wire wire_altpriority_encoder10_zero;
wire [4:0] wire_altpriority_encoder9_q;
acl_fp_uitofp_altpriority_encoder_qf8 altpriority_encoder10
(
.data(data[63:32]),
.q(wire_altpriority_encoder10_q),
.zero(wire_altpriority_encoder10_zero));
acl_fp_uitofp_altpriority_encoder_q08 altpriority_encoder9
(
.data(data[31:0]),
.q(wire_altpriority_encoder9_q));
assign
q = {(~ wire_altpriority_encoder10_zero), (({5{wire_altpriority_encoder10_zero}} & wire_altpriority_encoder9_q) | ({5{(~ wire_altpriority_encoder10_zero)}} & wire_altpriority_encoder10_q))};
endmodule //acl_fp_uitofp_altpriority_encoder_0c6
//synthesis_resources = lpm_add_sub 5 lpm_compare 1 reg 253
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altfp_convert_0jn
(
clk_en,
clock,
dataa,
result) ;
input clk_en;
input clock;
input [32:0] dataa;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [32:0] wire_altbarrel_shift5_result;
wire [5:0] wire_altpriority_encoder2_q;
reg add_1_adder1_cout_reg;
reg [11:0] add_1_adder1_reg;
reg add_1_adder2_cout_reg;
reg [11:0] add_1_adder2_reg;
reg add_1_reg;
reg [7:0] exponent_bus_pre_reg;
reg [7:0] exponent_bus_pre_reg2;
reg [7:0] exponent_bus_pre_reg3;
reg [31:0] mag_int_a_reg;
reg [31:0] mag_int_a_reg2;
reg [23:0] mantissa_pre_round_reg;
reg [5:0] priority_encoder_reg;
reg [31:0] result_reg;
reg sign_int_a_reg1;
reg sign_int_a_reg2;
reg sign_int_a_reg3;
reg sign_int_a_reg4;
reg sign_int_a_reg5;
wire [31:0] wire_add_sub1_result;
wire [7:0] wire_add_sub3_result;
wire wire_add_sub6_cout;
wire [11:0] wire_add_sub6_result;
wire wire_add_sub7_cout;
wire [11:0] wire_add_sub7_result;
wire [7:0] wire_add_sub8_result;
wire wire_cmpr4_alb;
wire aclr;
wire [11:0] add_1_adder1_w;
wire [11:0] add_1_adder2_w;
wire [23:0] add_1_adder_w;
wire add_1_w;
wire [7:0] bias_value_w;
wire [7:0] const_bias_value_add_width_int_w;
wire [7:0] exceptions_value;
wire [7:0] exponent_bus;
wire [7:0] exponent_bus_pre;
wire [7:0] exponent_output_w;
wire [7:0] exponent_rounded;
wire [7:0] exponent_zero_w;
wire guard_bit_w;
wire [31:0] int_a;
wire [31:0] int_a_2s;
wire [31:0] invert_int_a;
wire [5:0] leading_zeroes;
wire [31:0] mag_int_a;
wire [22:0] mantissa_bus;
wire mantissa_overflow;
wire [23:0] mantissa_post_round;
wire [23:0] mantissa_pre_round;
wire [23:0] mantissa_rounded;
wire max_neg_value_selector;
wire [7:0] max_neg_value_w;
wire [7:0] minus_leading_zero;
wire [32:0] prio_mag_int_a;
wire [30:0] priority_pad_one_w;
wire [31:0] result_w;
wire round_bit_w;
wire [31:0] shifted_mag_int_a;
wire sign_bus;
wire sign_int_a;
wire [6:0] sticky_bit_bus;
wire [6:0] sticky_bit_or_w;
wire sticky_bit_w;
wire [1:0] zero_padding_w;
acl_fp_uitofp_altbarrel_shift_ssf altbarrel_shift5
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({1'b0, mag_int_a_reg2}),
.distance(leading_zeroes),
.result(wire_altbarrel_shift5_result));
acl_fp_uitofp_altpriority_encoder_0c6 altpriority_encoder2
(
.data({prio_mag_int_a, priority_pad_one_w}),
.q(wire_altpriority_encoder2_q));
// synopsys translate_off
initial
add_1_adder1_cout_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) add_1_adder1_cout_reg <= 1'b0;
else if (clk_en == 1'b1) add_1_adder1_cout_reg <= wire_add_sub6_cout;
// synopsys translate_off
initial
add_1_adder1_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) add_1_adder1_reg <= 12'b0;
else if (clk_en == 1'b1) add_1_adder1_reg <= wire_add_sub6_result;
// synopsys translate_off
initial
add_1_adder2_cout_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) add_1_adder2_cout_reg <= 1'b0;
else if (clk_en == 1'b1) add_1_adder2_cout_reg <= wire_add_sub7_cout;
// synopsys translate_off
initial
add_1_adder2_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) add_1_adder2_reg <= 12'b0;
else if (clk_en == 1'b1) add_1_adder2_reg <= wire_add_sub7_result;
// synopsys translate_off
initial
add_1_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) add_1_reg <= 1'b0;
else if (clk_en == 1'b1) add_1_reg <= add_1_w;
// synopsys translate_off
initial
exponent_bus_pre_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg <= 8'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg <= exponent_bus_pre_reg2;
// synopsys translate_off
initial
exponent_bus_pre_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg2 <= 8'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg2 <= exponent_bus_pre_reg3;
// synopsys translate_off
initial
exponent_bus_pre_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg3 <= 8'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg3 <= exponent_bus_pre;
// synopsys translate_off
initial
mag_int_a_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mag_int_a_reg <= 32'b0;
else if (clk_en == 1'b1) mag_int_a_reg <= mag_int_a;
// synopsys translate_off
initial
mag_int_a_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mag_int_a_reg2 <= 32'b0;
else if (clk_en == 1'b1) mag_int_a_reg2 <= mag_int_a_reg;
// synopsys translate_off
initial
mantissa_pre_round_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mantissa_pre_round_reg <= 24'b0;
else if (clk_en == 1'b1) mantissa_pre_round_reg <= mantissa_pre_round;
// synopsys translate_off
initial
priority_encoder_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) priority_encoder_reg <= 6'b0;
else if (clk_en == 1'b1) priority_encoder_reg <= wire_altpriority_encoder2_q;
// synopsys translate_off
initial
result_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) result_reg <= 32'b0;
else if (clk_en == 1'b1) result_reg <= result_w;
// synopsys translate_off
initial
sign_int_a_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg1 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg1 <= sign_int_a;
// synopsys translate_off
initial
sign_int_a_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg2 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg2 <= sign_int_a_reg1;
// synopsys translate_off
initial
sign_int_a_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg3 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg3 <= sign_int_a_reg2;
// synopsys translate_off
initial
sign_int_a_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg4 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg4 <= sign_int_a_reg3;
// synopsys translate_off
initial
sign_int_a_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg5 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg5 <= sign_int_a_reg4;
lpm_add_sub add_sub1
(
.cout(),
.dataa(invert_int_a),
.datab(32'b00000000000000000000000000000001),
.overflow(),
.result(wire_add_sub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub1.lpm_direction = "ADD",
add_sub1.lpm_width = 32,
add_sub1.lpm_type = "lpm_add_sub",
add_sub1.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_add_sub add_sub3
(
.cout(),
.dataa(const_bias_value_add_width_int_w),
.datab(minus_leading_zero),
.overflow(),
.result(wire_add_sub3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub3.lpm_direction = "SUB",
add_sub3.lpm_width = 8,
add_sub3.lpm_type = "lpm_add_sub",
add_sub3.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_add_sub add_sub6
(
.cout(wire_add_sub6_cout),
.dataa(mantissa_pre_round[11:0]),
.datab(12'b000000000001),
.overflow(),
.result(wire_add_sub6_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub6.lpm_direction = "ADD",
add_sub6.lpm_width = 12,
add_sub6.lpm_type = "lpm_add_sub",
add_sub6.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_add_sub add_sub7
(
.cout(wire_add_sub7_cout),
.dataa(mantissa_pre_round[23:12]),
.datab(12'b000000000001),
.overflow(),
.result(wire_add_sub7_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub7.lpm_direction = "ADD",
add_sub7.lpm_width = 12,
add_sub7.lpm_type = "lpm_add_sub",
add_sub7.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_add_sub add_sub8
(
.cout(),
.dataa(exponent_bus_pre_reg),
.datab(8'b00000001),
.overflow(),
.result(wire_add_sub8_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub8.lpm_direction = "ADD",
add_sub8.lpm_width = 8,
add_sub8.lpm_type = "lpm_add_sub",
add_sub8.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_compare cmpr4
(
.aeb(),
.agb(),
.ageb(),
.alb(wire_cmpr4_alb),
.aleb(),
.aneb(),
.dataa(exponent_output_w),
.datab(bias_value_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr4.lpm_representation = "UNSIGNED",
cmpr4.lpm_width = 8,
cmpr4.lpm_type = "lpm_compare";
assign
aclr = 1'b0,
add_1_adder1_w = add_1_adder1_reg,
add_1_adder2_w = (({12{(~ add_1_adder1_cout_reg)}} & mantissa_pre_round_reg[23:12]) | ({12{add_1_adder1_cout_reg}} & add_1_adder2_reg)),
add_1_adder_w = {add_1_adder2_w, add_1_adder1_w},
add_1_w = ((((~ guard_bit_w) & round_bit_w) & sticky_bit_w) | (guard_bit_w & round_bit_w)),
bias_value_w = 8'b01111111,
const_bias_value_add_width_int_w = 8'b10011110,
exceptions_value = (({8{(~ max_neg_value_selector)}} & exponent_zero_w) | ({8{max_neg_value_selector}} & max_neg_value_w)),
exponent_bus = exponent_rounded,
exponent_bus_pre = (({8{(~ wire_cmpr4_alb)}} & exponent_output_w) | ({8{wire_cmpr4_alb}} & exceptions_value)),
exponent_output_w = wire_add_sub3_result,
exponent_rounded = (({8{(~ mantissa_overflow)}} & exponent_bus_pre_reg) | ({8{mantissa_overflow}} & wire_add_sub8_result)),
exponent_zero_w = {8{1'b0}},
guard_bit_w = shifted_mag_int_a[8],
int_a = dataa[31:0],
int_a_2s = wire_add_sub1_result,
invert_int_a = (~ int_a),
leading_zeroes = (~ priority_encoder_reg),
mag_int_a = (({32{(~ sign_int_a)}} & int_a) | ({32{sign_int_a}} & int_a_2s)),
mantissa_bus = mantissa_rounded[22:0],
mantissa_overflow = ((add_1_reg & add_1_adder1_cout_reg) & add_1_adder2_cout_reg),
mantissa_post_round = add_1_adder_w,
mantissa_pre_round = shifted_mag_int_a[31:8],
mantissa_rounded = (({24{(~ add_1_reg)}} & mantissa_pre_round_reg) | ({24{add_1_reg}} & mantissa_post_round)),
max_neg_value_selector = (wire_cmpr4_alb & sign_int_a_reg2),
max_neg_value_w = 8'b10011111,
minus_leading_zero = {zero_padding_w, leading_zeroes},
prio_mag_int_a = {mag_int_a_reg, 1'b1},
priority_pad_one_w = {31{1'b1}},
result = result_reg,
result_w = {sign_bus, exponent_bus, mantissa_bus},
round_bit_w = shifted_mag_int_a[7],
shifted_mag_int_a = wire_altbarrel_shift5_result[31:0],
sign_bus = sign_int_a_reg5,
sign_int_a = dataa[32],
sticky_bit_bus = shifted_mag_int_a[6:0],
sticky_bit_or_w = {(sticky_bit_or_w[5] | sticky_bit_bus[6]), (sticky_bit_or_w[4] | sticky_bit_bus[5]), (sticky_bit_or_w[3] | sticky_bit_bus[4]), (sticky_bit_or_w[2] | sticky_bit_bus[3]), (sticky_bit_or_w[1] | sticky_bit_bus[2]), (sticky_bit_or_w[0] | sticky_bit_bus[1]), sticky_bit_bus[0]},
sticky_bit_w = sticky_bit_or_w[6],
zero_padding_w = {2{1'b0}};
endmodule //acl_fp_uitofp_altfp_convert_0jn
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_uitofp (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
acl_fp_uitofp_altfp_convert_0jn acl_fp_uitofp_altfp_convert_0jn_component (
.clk_en (enable),
.clock (clock),
.dataa ({1'b0,dataa}),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_convert"
// Retrieval info: CONSTANT: OPERATION STRING "INT2FLOAT"
// Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
// Retrieval info: CONSTANT: WIDTH_DATA NUMERIC "33"
// Retrieval info: CONSTANT: WIDTH_EXP_INPUT NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_EXP_OUTPUT NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_INT NUMERIC "33"
// Retrieval info: CONSTANT: WIDTH_MAN_INPUT NUMERIC "23"
// Retrieval info: CONSTANT: WIDTH_MAN_OUTPUT NUMERIC "23"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "32"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: dataa 0 0 33 0 INPUT NODEFVAL "dataa[32..0]"
// Retrieval info: CONNECT: @dataa 0 0 33 0 dataa 0 0 33 0
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_uitofp.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_uitofp.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_uitofp.bsf TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_uitofp_inst.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_uitofp_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_uitofp.inc TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_uitofp.cmp TRUE TRUE
// Retrieval info: LIB_FILE: lpm
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer _mode;
reg _guard1;
reg [127:0] r_wide0;
reg _guard2;
wire [63:0] r_wide1;
reg _guard3;
reg _guard4;
reg _guard5;
reg _guard6;
assign r_wide1 = r_wide0[127:64];
// surefire lint_off STMINI
initial _mode = 0;
always @ (posedge clk) begin
if (_mode==0) begin
$write("[%0t] t_equal: Running\n", $time);
_guard1 <= 0;
_guard2 <= 0;
_guard3 <= 0;
_guard4 <= 0;
_guard5 <= 0;
_guard6 <= 0;
_mode<=1;
r_wide0 <= {32'h aa111111,32'hbb222222,32'hcc333333,32'hdd444444};
end
else if (_mode==1) begin
_mode<=2;
//
if (5'd10 != 5'b1010) $stop;
if (5'd10 != 5'd10) $stop;
if (5'd10 != 5'ha) $stop;
if (5'd10 != 5'o12) $stop;
if (5'd10 != 5'B 1010) $stop;
if (5'd10 != 5'D10) $stop;
if (5'd10 != 5'H a) $stop;
if (5'd10 != 5 'O 12) $stop;
//
if (r_wide0 !== {32'haa111111,32'hbb222222,32'hcc333333,32'hdd444444}) $stop;
if (r_wide1 !== {32'haa111111,32'hbb222222}) $stop;
if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin
$write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_qpll_reset.v
// Version : 3.0
//----------------------------------------------------------------------------//
// Filename : pcie3_7x_0_qpll_reset.v
// Description : QPLL Reset Module for 7 Series Transceiver
// Version : 11.4
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- QPLL Reset Module --------------------------------------------------
module pcie3_7x_0_qpll_reset #
(
//---------- Global ------------------------------------
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
parameter PCIE_LANE = 1, // PCIe number of lanes
parameter BYPASS_COARSE_OVRD = 1 // Bypass coarse frequency override
)
(
//---------- Input -------------------------------------
input QRST_CLK,
input QRST_RST_N,
input QRST_MMCM_LOCK,
input [PCIE_LANE-1:0] QRST_CPLLLOCK,
input [(PCIE_LANE-1)>>2:0]QRST_DRP_DONE,
input [(PCIE_LANE-1)>>2:0]QRST_QPLLLOCK,
input [ 1:0] QRST_RATE,
input [PCIE_LANE-1:0] QRST_QPLLRESET_IN,
input [PCIE_LANE-1:0] QRST_QPLLPD_IN,
//---------- Output ------------------------------------
output QRST_OVRD,
output QRST_DRP_START,
output QRST_QPLLRESET_OUT,
output QRST_QPLLPD_OUT,
output QRST_IDLE,
output [11:0] QRST_FSM
);
//---------- Input Register ----------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]drp_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]qplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllreset_in_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllpd_in_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]drp_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]qplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllreset_in_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllpd_in_reg2;
//---------- Output Register --------------------------
reg ovrd = 1'd0;
reg qpllreset = 1'd1;
reg qpllpd = 1'd0;
reg [11:0] fsm = 12'd2;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 12'b000000000001;
localparam FSM_WAIT_LOCK = 12'b000000000010;
localparam FSM_MMCM_LOCK = 12'b000000000100;
localparam FSM_DRP_START_NOM = 12'b000000001000;
localparam FSM_DRP_DONE_NOM = 12'b000000010000;
localparam FSM_QPLLLOCK = 12'b000000100000;
localparam FSM_DRP_START_OPT = 12'b000001000000;
localparam FSM_DRP_DONE_OPT = 12'b000010000000;
localparam FSM_QPLL_RESET = 12'b000100000000;
localparam FSM_QPLLLOCK2 = 12'b001000000000;
localparam FSM_QPLL_PDRESET = 12'b010000000000;
localparam FSM_QPLL_PD = 12'b100000000000;
//---------- Input FF ----------------------------------------------------------
always @ (posedge QRST_CLK)
begin
if (!QRST_RST_N)
begin
//---------- 1st Stage FF --------------------------
mmcm_lock_reg1 <= 1'd0;
cplllock_reg1 <= {PCIE_LANE{1'd1}};
drp_done_reg1 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
qplllock_reg1 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
rate_reg1 <= 2'd0;
qpllreset_in_reg1 <= {PCIE_LANE{1'd1}};
qpllpd_in_reg1 <= {PCIE_LANE{1'd0}};
//---------- 2nd Stage FF --------------------------
mmcm_lock_reg2 <= 1'd0;
cplllock_reg2 <= {PCIE_LANE{1'd1}};
drp_done_reg2 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
qplllock_reg2 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
rate_reg2 <= 2'd0;
qpllreset_in_reg2 <= {PCIE_LANE{1'd1}};
qpllpd_in_reg2 <= {PCIE_LANE{1'd0}};
end
else
begin
//---------- 1st Stage FF --------------------------
mmcm_lock_reg1 <= QRST_MMCM_LOCK;
cplllock_reg1 <= QRST_CPLLLOCK;
drp_done_reg1 <= QRST_DRP_DONE;
qplllock_reg1 <= QRST_QPLLLOCK;
rate_reg1 <= QRST_RATE;
qpllreset_in_reg1 <= QRST_QPLLRESET_IN;
qpllpd_in_reg1 <= QRST_QPLLPD_IN;
//---------- 2nd Stage FF --------------------------
mmcm_lock_reg2 <= mmcm_lock_reg1;
cplllock_reg2 <= cplllock_reg1;
drp_done_reg2 <= drp_done_reg1;
qplllock_reg2 <= qplllock_reg1;
rate_reg2 <= rate_reg1;
qpllreset_in_reg2 <= qpllreset_in_reg1;
qpllpd_in_reg2 <= qpllpd_in_reg1;
end
end
//---------- QPLL Reset FSM ----------------------------------------------------
always @ (posedge QRST_CLK)
begin
if (!QRST_RST_N)
begin
fsm <= FSM_WAIT_LOCK;
ovrd <= 1'd0;
qpllreset <= 1'd1;
qpllpd <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
if (!QRST_RST_N)
begin
fsm <= FSM_WAIT_LOCK;
ovrd <= 1'd0;
qpllreset <= 1'd1;
qpllpd <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
ovrd <= ovrd;
qpllreset <= &qpllreset_in_reg2;
qpllpd <= &qpllpd_in_reg2;
end
end
//---------- Wait for CPLL and QPLL to Lose Lock ---
FSM_WAIT_LOCK :
begin
fsm <= ((&(~cplllock_reg2)) && (&(~qplllock_reg2)) ? FSM_MMCM_LOCK : FSM_WAIT_LOCK);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for MMCM and CPLL Lock -----------
FSM_MMCM_LOCK :
begin
fsm <= ((mmcm_lock_reg2 && (&cplllock_reg2)) ? FSM_DRP_START_NOM : FSM_MMCM_LOCK);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Start QPLL DRP for Normal QPLL Lock Mode
FSM_DRP_START_NOM:
begin
fsm <= (&(~drp_done_reg2) ? FSM_DRP_DONE_NOM : FSM_DRP_START_NOM);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for QPLL DRP Done ----------------
FSM_DRP_DONE_NOM :
begin
fsm <= (&drp_done_reg2 ? FSM_QPLLLOCK : FSM_DRP_DONE_NOM);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for QPLL Lock --------------------
FSM_QPLLLOCK :
begin
fsm <= (&qplllock_reg2 ? ((BYPASS_COARSE_OVRD == 1) ? FSM_QPLL_PDRESET : FSM_DRP_START_OPT) : FSM_QPLLLOCK);
ovrd <= ovrd;
qpllreset <= 1'd0;
qpllpd <= qpllpd;
end
//---------- Start QPLL DRP for Optimized QPLL Lock Mode
FSM_DRP_START_OPT:
begin
fsm <= (&(~drp_done_reg2) ? FSM_DRP_DONE_OPT : FSM_DRP_START_OPT);
ovrd <= 1'd1;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for QPLL DRP Done ----------------
FSM_DRP_DONE_OPT :
begin
if (&drp_done_reg2)
begin
fsm <= ((PCIE_PLL_SEL == "QPLL") ? FSM_QPLL_RESET : FSM_QPLL_PDRESET);
ovrd <= ovrd;
qpllreset <= (PCIE_PLL_SEL == "QPLL");
qpllpd <= qpllpd;
end
else
begin
fsm <= FSM_DRP_DONE_OPT;
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
end
//---------- Reset QPLL ----------------------------
FSM_QPLL_RESET :
begin
fsm <= (&(~qplllock_reg2) ? FSM_QPLLLOCK2 : FSM_QPLL_RESET);
ovrd <= ovrd;
qpllreset <= 1'd1;
qpllpd <= 1'd0;
end
//---------- Wait for QPLL Lock --------------------
FSM_QPLLLOCK2 :
begin
fsm <= (&qplllock_reg2 ? FSM_IDLE : FSM_QPLLLOCK2);
ovrd <= ovrd;
qpllreset <= 1'd0;
qpllpd <= 1'd0;
end
//---------- Hold QPLL in Reset --------------------
FSM_QPLL_PDRESET :
begin
fsm <= FSM_QPLL_PD;
ovrd <= ovrd;
qpllreset <= (PCIE_PLL_SEL == "CPLL") ? (rate_reg2 != 2'd2) : 1'd0;
qpllpd <= qpllpd;
end
//---------- Power-down QPLL -----------------------
FSM_QPLL_PD :
begin
fsm <= FSM_IDLE;
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= (PCIE_PLL_SEL == "CPLL") ? (rate_reg2 != 2'd2) : 1'd0;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_WAIT_LOCK;
ovrd <= 1'd0;
qpllreset <= 1'd0;
qpllpd <= 1'd0;
end
endcase
end
end
//---------- QPLL Lock Output --------------------------------------------------
assign QRST_OVRD = ovrd;
assign QRST_DRP_START = (fsm == FSM_DRP_START_NOM) || (fsm == FSM_DRP_START_OPT);
assign QRST_QPLLRESET_OUT = qpllreset;
assign QRST_QPLLPD_OUT = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllpd);
assign QRST_IDLE = (fsm == FSM_IDLE);
assign QRST_FSM = fsm;
endmodule
|
`timescale 1ns / 1ps
`include "../src/include/axis_shifter_v2.v"
`include "../src/axis_window.v"
module testwindow(
);
localparam RANDOMOUTPUT = 1;
localparam RANDOMINPUT = 1;
wire[7:0] mdata;
wire mlast;
reg mready;
wire muser;
wire mvalid;
wire[7:0] sdata;
wire slast;
wire sready;
wire suser;
reg svalid;
reg[11:0] ori_height = 16;
reg[11:0] ori_width = 16;
reg[11:0] w_left = 3;
reg[11:0] w_top = 3;
reg[11:0] w_width = 5;
reg[11:0] w_height = 6;
reg resetn;
reg clk;
axis_window #(
.C_PIXEL_WIDTH(8),
.C_IMG_WBITS(12),
.C_IMG_HBITS(12)
)uut(
.m_axis_tdata(mdata),
.m_axis_tlast(mlast),
.m_axis_tready(mready),
.m_axis_tuser(muser),
.m_axis_tvalid(mvalid),
.s_axis_tdata(sdata),
.s_axis_tlast(slast),
.s_axis_tready(sready),
.s_axis_tuser(suser),
.s_axis_tvalid(svalid),
.win_height(w_height),
.win_left(w_left),
.win_top(w_top),
.win_width(w_width),
.clk(clk),
.resetn(resetn));
initial begin
clk <= 1'b1;
forever #1 clk <= ~clk;
end
initial begin
resetn <= 1'b0;
repeat (5) #2 resetn <= 1'b0;
forever #2 resetn <= 1'b1;
end
reg[11:0] in_row;
reg[11:0] in_col;
assign sdata = (in_row * 16 + in_col);
reg[11:0] out_row;
reg[11:0] out_col;
assign suser = (in_row == 0 && in_col == 0);
assign slast = (in_col == ori_height - 1);
reg randominput;
reg randomoutput;
reg input_done;
reg output_done;
always @(posedge clk) begin
if (resetn == 1'b0)
randominput <= 1'b0;
else
randominput <= (RANDOMINPUT ? {$random}%2 : 1);
if (resetn == 1'b0)
randomoutput <= 1'b0;
else
randomoutput <= (RANDOMOUTPUT ? {$random}%2 : 1);
if (resetn == 1'b0) begin
in_row <= 0;
in_col <= 0;
end
else if (svalid && sready) begin
if (in_col != ori_width - 1) begin
in_col <= in_col + 1;
in_row <= in_row;
end
else if (in_row != ori_height - 1) begin
in_col <= 0;
in_row <= in_row + 1;
end
else begin
in_row <= 0;
in_col <= 0;
end
end
if (resetn == 1'b0)
input_done <= 0;
else if (svalid && sready && in_col == ori_width-1 && in_row == ori_height-1)
input_done <= 1;
else if (input_done && output_done)
input_done <= 0;
if (resetn == 1'b0)
svalid <= 1'b0;
else if (~svalid) begin
if (randominput) begin
svalid <= 1'b1;
end
end
else if (svalid && sready) begin
if (randominput) begin
svalid <= 1'b1;
end
else begin
svalid <= 1'b0;
end
end
if (resetn == 1'b0)
mready <= 1'b0;
else if (randomoutput)
mready <= 1'b1;
else
mready <= 1'b0;
if (resetn == 1'b0) begin
out_col = 0;
out_row = 0;
end
else if (mready && mvalid) begin
if (muser) begin
out_col <= 0;
out_row <= 0;
end
else if (mlast) begin
out_col <= 0;
out_row <= out_row + 1;
end
else begin
out_col <= out_col + 1;
out_row <= out_row;
end
if (muser)
$write("start new frame: \n");
$write("%h ", mdata);
if (mlast)
$write("\n");
end
if (resetn == 1'b0)
output_done <= 0;
else if (output_done && input_done)
output_done <= 0;
else if (~output_done
&& (mready && mvalid
&& out_col == w_width-1
&& out_row == w_height-1) || (w_width == 0 || w_height == 0))
output_done <= 1;
/*
if (resetn == 1'b0) begin
end
else if (out_row == w_height) begin
w_left <= 0;
w_top <= 0;
w_height <= 0;
w_width <= 0;
end
*/
if (input_done && output_done) begin
if (w_left != 0) begin
w_left <= 0;
w_top <= 0;
w_height <= 0;
w_width <= 0;
end
else begin
w_left <= 3;
w_top <= 3;
w_width <= 5;
w_height <= 6;
end
end
end
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
// generate training pattern
// pattern is f4c2, it occupies two clock cycles
`timescale 1ns / 1ps
module RCB_FRL_TrainingPattern(
input clk,
input rst,
output reg [7:0] trainingpattern
);
always @ (posedge clk) begin
if(rst) begin
trainingpattern <= 8'h00;
end else begin
if(trainingpattern == 8'hf4)
trainingpattern <= 8'hc2;
else
trainingpattern <= 8'hf4;
end
end
endmodule
|
//***********************************************************************
// Top Module - ECG Feature extraction
// Author: Dwaipayan Biswas
// Email: [email protected]
// University of Southampton
// DWT with haar wavelet
//***********************************************************************
`timescale 1ns / 100ps
`include "parameter.v"
module ecg_top (q_peak_ref,q_peak_pos_ref,r_peak_ref,r_peak_pos_ref,
s_peak_ref,s_peak_pos_ref,start_qrs_fin_2,end_qrs_fin_2,p_begin,p_end,p_peak,p_peak_pos,t_begin,t_end,t_peak,
t_peak_pos,data_in,clk,nReset);
output signed [15:0] q_peak_ref,q_peak_pos_ref,r_peak_ref,r_peak_pos_ref,
s_peak_ref,s_peak_pos_ref,start_qrs_fin_2,end_qrs_fin_2,
p_begin,p_end,p_peak,p_peak_pos,t_begin,t_end,t_peak,t_peak_pos;
input signed [15:0] data_in;
input clk, nReset;
wire clk, nReset;
wire signed [15:0]
ecg0,ecg1,ecg2,ecg3,ecg4,ecg5,ecg6,ecg7,ecg8,ecg9,ecg10,ecg11,ecg12,ecg13,ecg14,ecg15,ecg16,ecg17,ecg18,ecg19,ecg20,ecg21,ecg22,ecg23,ecg24,ecg25,ecg26,ecg27,ecg28,ecg29,ecg30,ecg31,ecg32,ecg33,ecg34,ecg35,ecg36,ecg37,ecg38,ecg39,ecg40,ecg41,ecg42,ecg43,ecg44,ecg45,ecg46,ecg47,ecg48,ecg49,ecg50,ecg51,ecg52,ecg53,ecg54,ecg55,ecg56,ecg57,ecg58,ecg59,ecg60,ecg61,ecg62,ecg63,ecg64,ecg65,ecg66,ecg67,ecg68,ecg69,ecg70,ecg71,ecg72,ecg73,ecg74,ecg75,ecg76,ecg77,ecg78,ecg79,ecg80,ecg81,ecg82,ecg83,ecg84,ecg85,ecg86,ecg87,ecg88,ecg89,ecg90,ecg91,ecg92,ecg93,ecg94,ecg95,ecg96,ecg97,ecg98,ecg99,ecg100,ecg101,ecg102,ecg103,ecg104,ecg105,ecg106,ecg107,ecg108,ecg109,ecg110,ecg111,ecg112,ecg113,ecg114,ecg115,ecg116,ecg117,ecg118,ecg119,ecg120,ecg121,ecg122,ecg123,ecg124,ecg125,ecg126,ecg127,ecg128,ecg129,ecg130,ecg131,ecg132,ecg133,ecg134,ecg135,ecg136,ecg137,ecg138,ecg139,ecg140,ecg141,ecg142,ecg143,ecg144,ecg145,ecg146,ecg147,ecg148,ecg149,ecg150,ecg151,ecg152,ecg153,ecg154,ecg155,ecg156,ecg157,ecg158,ecg159,ecg160,ecg161,ecg162,ecg163,ecg164,ecg165,ecg166,ecg167,ecg168,ecg169,ecg170,ecg171,ecg172,ecg173,ecg174,ecg175,ecg176,ecg177,ecg178,ecg179,ecg180,ecg181,ecg182,ecg183,ecg184,ecg185,ecg186,ecg187,ecg188,ecg189,ecg190,ecg191,ecg192,ecg193,ecg194,ecg195,ecg196,ecg197,ecg198,ecg199,ecg200,ecg201,ecg202,ecg203,ecg204,ecg205,ecg206,ecg207,ecg208,ecg209,ecg210,ecg211,ecg212,ecg213,ecg214,ecg215,ecg216,ecg217,ecg218,ecg219,ecg220,ecg221,ecg222,ecg223,ecg224,ecg225,ecg226,ecg227,ecg228,ecg229,ecg230,ecg231,ecg232,ecg233,ecg234,ecg235,ecg236,ecg237,ecg238,ecg239,ecg240,ecg241,ecg242,ecg243,ecg244,ecg245,ecg246,ecg247,ecg248,ecg249,ecg250,ecg251,ecg252,ecg253,ecg254,ecg255,ecg256,ecg257,ecg258,ecg259,ecg260,ecg261,ecg262,ecg263,ecg264,ecg265,ecg266,ecg267,ecg268,ecg269,ecg270,ecg271,ecg272,ecg273,ecg274,ecg275,ecg276,ecg277,ecg278,ecg279,ecg280,ecg281,ecg282,ecg283,ecg284,ecg285,ecg286,ecg287,ecg288,ecg289,ecg290,ecg291,ecg292,ecg293,ecg294,ecg295,ecg296,ecg297,ecg298,ecg299,ecg300,ecg301,ecg302,ecg303,ecg304,ecg305,ecg306,ecg307,ecg308,ecg309,ecg310,ecg311,ecg312,ecg313,ecg314,ecg315,ecg316,ecg317,ecg318,ecg319,ecg320,ecg321,ecg322,ecg323,ecg324,ecg325,ecg326,ecg327,ecg328,ecg329,ecg330,ecg331,ecg332,ecg333,ecg334,ecg335,ecg336,ecg337,ecg338,ecg339,ecg340,ecg341,ecg342,ecg343,ecg344,ecg345,ecg346,ecg347,ecg348,ecg349,ecg350,ecg351,ecg352,ecg353,ecg354,ecg355,ecg356,ecg357,ecg358,ecg359,ecg360,ecg361,ecg362,ecg363,ecg364,ecg365,ecg366,ecg367,ecg368,ecg369,ecg370,ecg371,ecg372,ecg373,ecg374,ecg375,ecg376,ecg377,ecg378,ecg379,ecg380,ecg381,ecg382,ecg383,ecg384,ecg385,ecg386,ecg387,ecg388,ecg389,ecg390,ecg391,ecg392,ecg393,ecg394,ecg395,ecg396,ecg397,ecg398,ecg399,ecg400,ecg401,ecg402,ecg403,ecg404,ecg405,ecg406,ecg407,ecg408,ecg409,ecg410,ecg411,ecg412,ecg413,ecg414,ecg415,ecg416,ecg417,ecg418,ecg419,ecg420,ecg421,ecg422,ecg423,ecg424,ecg425,ecg426,ecg427,ecg428,ecg429,ecg430,ecg431,ecg432,ecg433,ecg434,ecg435,ecg436,ecg437,ecg438,ecg439,ecg440,ecg441,ecg442,ecg443,ecg444,ecg445,ecg446,ecg447,ecg448,ecg449,ecg450,ecg451,ecg452,ecg453,ecg454,ecg455,ecg456,ecg457,ecg458,ecg459,ecg460,ecg461,ecg462,ecg463,ecg464,ecg465,ecg466,ecg467,ecg468,ecg469,ecg470,ecg471,ecg472,ecg473,ecg474,ecg475,ecg476,ecg477,ecg478,ecg479,ecg480,ecg481,ecg482,ecg483,ecg484,ecg485,ecg486,ecg487,ecg488,ecg489,ecg490,ecg491,ecg492,ecg493,ecg494,ecg495,ecg496,ecg497,ecg498,ecg499,ecg500,ecg501,ecg502,ecg503,ecg504,ecg505,ecg506,ecg507,ecg508,ecg509,ecg510,ecg511,ecg512,ecg513,ecg514,ecg515,ecg516,ecg517,ecg518,ecg519,ecg520,ecg521,ecg522,ecg523,ecg524,ecg525,ecg526,ecg527,ecg528,ecg529,ecg530,ecg531,ecg532,ecg533,ecg534,ecg535,ecg536,ecg537,ecg538,ecg539,ecg540,ecg541,ecg542,ecg543,ecg544,ecg545,ecg546,ecg547,ecg548,ecg549,ecg550,ecg551,ecg552,ecg553,ecg554,ecg555,ecg556,ecg557,ecg558,ecg559,ecg560,ecg561,ecg562,ecg563,ecg564,ecg565,ecg566,ecg567,ecg568,ecg569,ecg570,ecg571,ecg572,ecg573,ecg574,ecg575,ecg576,ecg577,ecg578,ecg579,ecg580,ecg581,ecg582,ecg583,ecg584,ecg585,ecg586,ecg587,ecg588,ecg589,ecg590,ecg591,ecg592,ecg593,ecg594,ecg595,ecg596,ecg597,ecg598,ecg599,
ecg600,ecg601,ecg602,ecg603,ecg604,ecg605,ecg606,ecg607,ecg608,ecg609,ecg610,ecg611,ecg612,ecg613,ecg614,ecg615,ecg616,ecg617,ecg618,ecg619,ecg620,ecg621,ecg622,ecg623,ecg624,ecg625,ecg626,ecg627,ecg628,ecg629,ecg630,ecg631,ecg632,ecg633,ecg634,ecg635,ecg636,ecg637,ecg638,ecg639,ecg640,ecg641,ecg642,ecg643,ecg644,ecg645,ecg646,ecg647,ecg648,ecg649,ecg650,ecg651,ecg652,ecg653,ecg654,ecg655,ecg656,ecg657,ecg658,ecg659,ecg660,ecg661,ecg662,ecg663,ecg664,ecg665,ecg666,ecg667,ecg668,ecg669,ecg670,ecg671,ecg672,ecg673,ecg674,ecg675,ecg676,ecg677,ecg678,ecg679,ecg680,ecg681,ecg682,ecg683,ecg684,ecg685,ecg686,ecg687,ecg688,ecg689,ecg690,ecg691,ecg692,ecg693,ecg694,ecg695,ecg696,ecg697,ecg698,ecg699,ecg700,ecg701,ecg702,ecg703,ecg704,ecg705,ecg706,ecg707,ecg708,ecg709,ecg710,ecg711,ecg712,ecg713,ecg714,ecg715,ecg716,ecg717,ecg718,ecg719,ecg720,ecg721,ecg722,ecg723,ecg724,ecg725,ecg726,ecg727,ecg728,ecg729,ecg730,ecg731,ecg732,ecg733,ecg734,ecg735,ecg736,ecg737,ecg738,ecg739,ecg740,ecg741,ecg742,ecg743,ecg744,ecg745,ecg746,ecg747,ecg748,ecg749,ecg750,ecg751,ecg752,ecg753,ecg754,ecg755,ecg756,ecg757,ecg758,ecg759,ecg760,ecg761,ecg762,ecg763,ecg764,ecg765,ecg766,ecg767,ecg768,ecg769,ecg770,ecg771,ecg772,ecg773,ecg774,ecg775,ecg776,ecg777,ecg778,ecg779,ecg780,ecg781,ecg782,ecg783,ecg784,ecg785,ecg786,ecg787,ecg788,ecg789,ecg790,ecg791,ecg792,ecg793,ecg794,ecg795,ecg796,ecg797,ecg798,ecg799;
// Wavelet Level 2 architecture
level2arch l2_arch(data_in,clk,nReset);
// Wavelet Level 3 architecture
waveletl3 wv_l3(r_peak_ref,r_peak_pos_ref,start_qrs_fin_2,
end_qrs_fin_2,
ecg0,ecg1,ecg2,ecg3,ecg4,ecg5,ecg6,ecg7,ecg8,ecg9,ecg10,ecg11,ecg12,ecg13,ecg14,ecg15,ecg16,ecg17,ecg18,ecg19,ecg20,ecg21,ecg22,ecg23,ecg24,ecg25,ecg26,ecg27,ecg28,ecg29,ecg30,ecg31,ecg32,ecg33,ecg34,ecg35,ecg36,ecg37,ecg38,ecg39,ecg40,ecg41,ecg42,ecg43,ecg44,ecg45,ecg46,ecg47,ecg48,ecg49,ecg50,ecg51,ecg52,ecg53,ecg54,ecg55,ecg56,ecg57,ecg58,ecg59,ecg60,ecg61,ecg62,ecg63,ecg64,ecg65,ecg66,ecg67,ecg68,ecg69,ecg70,ecg71,ecg72,ecg73,ecg74,ecg75,ecg76,ecg77,ecg78,ecg79,ecg80,ecg81,ecg82,ecg83,ecg84,ecg85,ecg86,ecg87,ecg88,ecg89,ecg90,ecg91,ecg92,ecg93,ecg94,ecg95,ecg96,ecg97,ecg98,ecg99,ecg100,ecg101,ecg102,ecg103,ecg104,ecg105,ecg106,ecg107,ecg108,ecg109,ecg110,ecg111,ecg112,ecg113,ecg114,ecg115,ecg116,ecg117,ecg118,ecg119,ecg120,ecg121,ecg122,ecg123,ecg124,ecg125,ecg126,ecg127,ecg128,ecg129,ecg130,ecg131,ecg132,ecg133,ecg134,ecg135,ecg136,ecg137,ecg138,ecg139,ecg140,ecg141,ecg142,ecg143,ecg144,ecg145,ecg146,ecg147,ecg148,ecg149,ecg150,ecg151,ecg152,ecg153,ecg154,ecg155,ecg156,ecg157,ecg158,ecg159,ecg160,ecg161,ecg162,ecg163,ecg164,ecg165,ecg166,ecg167,ecg168,ecg169,ecg170,ecg171,ecg172,ecg173,ecg174,ecg175,ecg176,ecg177,ecg178,ecg179,ecg180,ecg181,ecg182,ecg183,ecg184,ecg185,ecg186,ecg187,ecg188,ecg189,ecg190,ecg191,ecg192,ecg193,ecg194,ecg195,ecg196,ecg197,ecg198,ecg199,ecg200,ecg201,ecg202,ecg203,ecg204,ecg205,ecg206,ecg207,ecg208,ecg209,ecg210,ecg211,ecg212,ecg213,ecg214,ecg215,ecg216,ecg217,ecg218,ecg219,ecg220,ecg221,ecg222,ecg223,ecg224,ecg225,ecg226,ecg227,ecg228,ecg229,ecg230,ecg231,ecg232,ecg233,ecg234,ecg235,ecg236,ecg237,ecg238,ecg239,ecg240,ecg241,ecg242,ecg243,ecg244,ecg245,ecg246,ecg247,ecg248,ecg249,ecg250,ecg251,ecg252,ecg253,ecg254,ecg255,ecg256,ecg257,ecg258,ecg259,ecg260,ecg261,ecg262,ecg263,ecg264,ecg265,ecg266,ecg267,ecg268,ecg269,ecg270,ecg271,ecg272,ecg273,ecg274,ecg275,ecg276,ecg277,ecg278,ecg279,ecg280,ecg281,ecg282,ecg283,ecg284,ecg285,ecg286,ecg287,ecg288,ecg289,ecg290,ecg291,ecg292,ecg293,ecg294,ecg295,ecg296,ecg297,ecg298,ecg299,ecg300,ecg301,ecg302,ecg303,ecg304,ecg305,ecg306,ecg307,ecg308,ecg309,ecg310,ecg311,ecg312,ecg313,ecg314,ecg315,ecg316,ecg317,ecg318,ecg319,ecg320,ecg321,ecg322,ecg323,ecg324,ecg325,ecg326,ecg327,ecg328,ecg329,ecg330,ecg331,ecg332,ecg333,ecg334,ecg335,ecg336,ecg337,ecg338,ecg339,ecg340,ecg341,ecg342,ecg343,ecg344,ecg345,ecg346,ecg347,ecg348,ecg349,ecg350,ecg351,ecg352,ecg353,ecg354,ecg355,ecg356,ecg357,ecg358,ecg359,ecg360,ecg361,ecg362,ecg363,ecg364,ecg365,ecg366,ecg367,ecg368,ecg369,ecg370,ecg371,ecg372,ecg373,ecg374,ecg375,ecg376,ecg377,ecg378,ecg379,ecg380,ecg381,ecg382,ecg383,ecg384,ecg385,ecg386,ecg387,ecg388,ecg389,ecg390,ecg391,ecg392,ecg393,ecg394,ecg395,ecg396,ecg397,ecg398,ecg399,ecg400,ecg401,ecg402,ecg403,ecg404,ecg405,ecg406,ecg407,ecg408,ecg409,ecg410,ecg411,ecg412,ecg413,ecg414,ecg415,ecg416,ecg417,ecg418,ecg419,ecg420,ecg421,ecg422,ecg423,ecg424,ecg425,ecg426,ecg427,ecg428,ecg429,ecg430,ecg431,ecg432,ecg433,ecg434,ecg435,ecg436,ecg437,ecg438,ecg439,ecg440,ecg441,ecg442,ecg443,ecg444,ecg445,ecg446,ecg447,ecg448,ecg449,ecg450,ecg451,ecg452,ecg453,ecg454,ecg455,ecg456,ecg457,ecg458,ecg459,ecg460,ecg461,ecg462,ecg463,ecg464,ecg465,ecg466,ecg467,ecg468,ecg469,ecg470,ecg471,ecg472,ecg473,ecg474,ecg475,ecg476,ecg477,ecg478,ecg479,ecg480,ecg481,ecg482,ecg483,ecg484,ecg485,ecg486,ecg487,ecg488,ecg489,ecg490,ecg491,ecg492,ecg493,ecg494,ecg495,ecg496,ecg497,ecg498,ecg499,ecg500,ecg501,ecg502,ecg503,ecg504,ecg505,ecg506,ecg507,ecg508,ecg509,ecg510,ecg511,ecg512,ecg513,ecg514,ecg515,ecg516,ecg517,ecg518,ecg519,ecg520,ecg521,ecg522,ecg523,ecg524,ecg525,ecg526,ecg527,ecg528,ecg529,ecg530,ecg531,ecg532,ecg533,ecg534,ecg535,ecg536,ecg537,ecg538,ecg539,ecg540,ecg541,ecg542,ecg543,ecg544,ecg545,ecg546,ecg547,ecg548,ecg549,ecg550,ecg551,ecg552,ecg553,ecg554,ecg555,ecg556,ecg557,ecg558,ecg559,ecg560,ecg561,ecg562,ecg563,ecg564,ecg565,ecg566,ecg567,ecg568,ecg569,ecg570,ecg571,ecg572,ecg573,ecg574,ecg575,ecg576,ecg577,ecg578,ecg579,ecg580,ecg581,ecg582,ecg583,ecg584,ecg585,ecg586,ecg587,ecg588,ecg589,ecg590,ecg591,ecg592,ecg593,ecg594,ecg595,ecg596,ecg597,ecg598,ecg599,
ecg600,ecg601,ecg602,ecg603,ecg604,ecg605,ecg606,ecg607,ecg608,ecg609,ecg610,ecg611,ecg612,ecg613,ecg614,ecg615,ecg616,ecg617,ecg618,ecg619,ecg620,ecg621,ecg622,ecg623,ecg624,ecg625,ecg626,ecg627,ecg628,ecg629,ecg630,ecg631,ecg632,ecg633,ecg634,ecg635,ecg636,ecg637,ecg638,ecg639,ecg640,ecg641,ecg642,ecg643,ecg644,ecg645,ecg646,ecg647,ecg648,ecg649,ecg650,ecg651,ecg652,ecg653,ecg654,ecg655,ecg656,ecg657,ecg658,ecg659,ecg660,ecg661,ecg662,ecg663,ecg664,ecg665,ecg666,ecg667,ecg668,ecg669,ecg670,ecg671,ecg672,ecg673,ecg674,ecg675,ecg676,ecg677,ecg678,ecg679,ecg680,ecg681,ecg682,ecg683,ecg684,ecg685,ecg686,ecg687,ecg688,ecg689,ecg690,ecg691,ecg692,ecg693,ecg694,ecg695,ecg696,ecg697,ecg698,ecg699,ecg700,ecg701,ecg702,ecg703,ecg704,ecg705,ecg706,ecg707,ecg708,ecg709,ecg710,ecg711,ecg712,ecg713,ecg714,ecg715,ecg716,ecg717,ecg718,ecg719,ecg720,ecg721,ecg722,ecg723,ecg724,ecg725,ecg726,ecg727,ecg728,ecg729,ecg730,ecg731,ecg732,ecg733,ecg734,ecg735,ecg736,ecg737,ecg738,ecg739,ecg740,ecg741,ecg742,ecg743,ecg744,ecg745,ecg746,ecg747,ecg748,ecg749,ecg750,ecg751,ecg752,ecg753,ecg754,ecg755,ecg756,ecg757,ecg758,ecg759,ecg760,ecg761,ecg762,ecg763,ecg764,ecg765,ecg766,ecg767,ecg768,ecg769,ecg770,ecg771,ecg772,ecg773,ecg774,ecg775,ecg776,ecg777,ecg778,ecg779,ecg780,ecg781,ecg782,ecg783,ecg784,ecg785,ecg786,ecg787,ecg788,ecg789,ecg790,ecg791,ecg792,ecg793,ecg794,ecg795,ecg796,ecg797,ecg798,ecg799,data_in,clk,nReset);
waveletl5 wv_l5(q_peak_ref,q_peak_pos_ref,s_peak_ref,s_peak_pos_ref,p_begin,p_end,p_peak,p_peak_pos,t_begin,t_end,t_peak,t_peak_pos,
start_qrs_fin_2,end_qrs_fin_2,r_peak_pos_ref,
ecg0,ecg1,ecg2,ecg3,ecg4,ecg5,ecg6,ecg7,ecg8,ecg9,ecg10,ecg11,ecg12,ecg13,ecg14,ecg15,ecg16,ecg17,ecg18,ecg19,ecg20,ecg21,ecg22,ecg23,ecg24,ecg25,ecg26,ecg27,ecg28,ecg29,ecg30,ecg31,ecg32,ecg33,ecg34,ecg35,ecg36,ecg37,ecg38,ecg39,ecg40,ecg41,ecg42,ecg43,ecg44,ecg45,ecg46,ecg47,ecg48,ecg49,ecg50,ecg51,ecg52,ecg53,ecg54,ecg55,ecg56,ecg57,ecg58,ecg59,ecg60,ecg61,ecg62,ecg63,ecg64,ecg65,ecg66,ecg67,ecg68,ecg69,ecg70,ecg71,ecg72,ecg73,ecg74,ecg75,ecg76,ecg77,ecg78,ecg79,ecg80,ecg81,ecg82,ecg83,ecg84,ecg85,ecg86,ecg87,ecg88,ecg89,ecg90,ecg91,ecg92,ecg93,ecg94,ecg95,ecg96,ecg97,ecg98,ecg99,ecg100,ecg101,ecg102,ecg103,ecg104,ecg105,ecg106,ecg107,ecg108,ecg109,ecg110,ecg111,ecg112,ecg113,ecg114,ecg115,ecg116,ecg117,ecg118,ecg119,ecg120,ecg121,ecg122,ecg123,ecg124,ecg125,ecg126,ecg127,ecg128,ecg129,ecg130,ecg131,ecg132,ecg133,ecg134,ecg135,ecg136,ecg137,ecg138,ecg139,ecg140,ecg141,ecg142,ecg143,ecg144,ecg145,ecg146,ecg147,ecg148,ecg149,ecg150,ecg151,ecg152,ecg153,ecg154,ecg155,ecg156,ecg157,ecg158,ecg159,ecg160,ecg161,ecg162,ecg163,ecg164,ecg165,ecg166,ecg167,ecg168,ecg169,ecg170,ecg171,ecg172,ecg173,ecg174,ecg175,ecg176,ecg177,ecg178,ecg179,ecg180,ecg181,ecg182,ecg183,ecg184,ecg185,ecg186,ecg187,ecg188,ecg189,ecg190,ecg191,ecg192,ecg193,ecg194,ecg195,ecg196,ecg197,ecg198,ecg199,ecg200,ecg201,ecg202,ecg203,ecg204,ecg205,ecg206,ecg207,ecg208,ecg209,ecg210,ecg211,ecg212,ecg213,ecg214,ecg215,ecg216,ecg217,ecg218,ecg219,ecg220,ecg221,ecg222,ecg223,ecg224,ecg225,ecg226,ecg227,ecg228,ecg229,ecg230,ecg231,ecg232,ecg233,ecg234,ecg235,ecg236,ecg237,ecg238,ecg239,ecg240,ecg241,ecg242,ecg243,ecg244,ecg245,ecg246,ecg247,ecg248,ecg249,ecg250,ecg251,ecg252,ecg253,ecg254,ecg255,ecg256,ecg257,ecg258,ecg259,ecg260,ecg261,ecg262,ecg263,ecg264,ecg265,ecg266,ecg267,ecg268,ecg269,ecg270,ecg271,ecg272,ecg273,ecg274,ecg275,ecg276,ecg277,ecg278,ecg279,ecg280,ecg281,ecg282,ecg283,ecg284,ecg285,ecg286,ecg287,ecg288,ecg289,ecg290,ecg291,ecg292,ecg293,ecg294,ecg295,ecg296,ecg297,ecg298,ecg299,ecg300,ecg301,ecg302,ecg303,ecg304,ecg305,ecg306,ecg307,ecg308,ecg309,ecg310,ecg311,ecg312,ecg313,ecg314,ecg315,ecg316,ecg317,ecg318,ecg319,ecg320,ecg321,ecg322,ecg323,ecg324,ecg325,ecg326,ecg327,ecg328,ecg329,ecg330,ecg331,ecg332,ecg333,ecg334,ecg335,ecg336,ecg337,ecg338,ecg339,ecg340,ecg341,ecg342,ecg343,ecg344,ecg345,ecg346,ecg347,ecg348,ecg349,ecg350,ecg351,ecg352,ecg353,ecg354,ecg355,ecg356,ecg357,ecg358,ecg359,ecg360,ecg361,ecg362,ecg363,ecg364,ecg365,ecg366,ecg367,ecg368,ecg369,ecg370,ecg371,ecg372,ecg373,ecg374,ecg375,ecg376,ecg377,ecg378,ecg379,ecg380,ecg381,ecg382,ecg383,ecg384,ecg385,ecg386,ecg387,ecg388,ecg389,ecg390,ecg391,ecg392,ecg393,ecg394,ecg395,ecg396,ecg397,ecg398,ecg399,ecg400,ecg401,ecg402,ecg403,ecg404,ecg405,ecg406,ecg407,ecg408,ecg409,ecg410,ecg411,ecg412,ecg413,ecg414,ecg415,ecg416,ecg417,ecg418,ecg419,ecg420,ecg421,ecg422,ecg423,ecg424,ecg425,ecg426,ecg427,ecg428,ecg429,ecg430,ecg431,ecg432,ecg433,ecg434,ecg435,ecg436,ecg437,ecg438,ecg439,ecg440,ecg441,ecg442,ecg443,ecg444,ecg445,ecg446,ecg447,ecg448,ecg449,ecg450,ecg451,ecg452,ecg453,ecg454,ecg455,ecg456,ecg457,ecg458,ecg459,ecg460,ecg461,ecg462,ecg463,ecg464,ecg465,ecg466,ecg467,ecg468,ecg469,ecg470,ecg471,ecg472,ecg473,ecg474,ecg475,ecg476,ecg477,ecg478,ecg479,ecg480,ecg481,ecg482,ecg483,ecg484,ecg485,ecg486,ecg487,ecg488,ecg489,ecg490,ecg491,ecg492,ecg493,ecg494,ecg495,ecg496,ecg497,ecg498,ecg499,ecg500,ecg501,ecg502,ecg503,ecg504,ecg505,ecg506,ecg507,ecg508,ecg509,ecg510,ecg511,ecg512,ecg513,ecg514,ecg515,ecg516,ecg517,ecg518,ecg519,ecg520,ecg521,ecg522,ecg523,ecg524,ecg525,ecg526,ecg527,ecg528,ecg529,ecg530,ecg531,ecg532,ecg533,ecg534,ecg535,ecg536,ecg537,ecg538,ecg539,ecg540,ecg541,ecg542,ecg543,ecg544,ecg545,ecg546,ecg547,ecg548,ecg549,ecg550,ecg551,ecg552,ecg553,ecg554,ecg555,ecg556,ecg557,ecg558,ecg559,ecg560,ecg561,ecg562,ecg563,ecg564,ecg565,ecg566,ecg567,ecg568,ecg569,ecg570,ecg571,ecg572,ecg573,ecg574,ecg575,ecg576,ecg577,ecg578,ecg579,ecg580,ecg581,ecg582,ecg583,ecg584,ecg585,ecg586,ecg587,ecg588,ecg589,ecg590,ecg591,ecg592,ecg593,ecg594,ecg595,ecg596,ecg597,ecg598,ecg599,
ecg600,ecg601,ecg602,ecg603,ecg604,ecg605,ecg606,ecg607,ecg608,ecg609,ecg610,ecg611,ecg612,ecg613,ecg614,ecg615,ecg616,ecg617,ecg618,ecg619,ecg620,ecg621,ecg622,ecg623,ecg624,ecg625,ecg626,ecg627,ecg628,ecg629,ecg630,ecg631,ecg632,ecg633,ecg634,ecg635,ecg636,ecg637,ecg638,ecg639,ecg640,ecg641,ecg642,ecg643,ecg644,ecg645,ecg646,ecg647,ecg648,ecg649,ecg650,ecg651,ecg652,ecg653,ecg654,ecg655,ecg656,ecg657,ecg658,ecg659,ecg660,ecg661,ecg662,ecg663,ecg664,ecg665,ecg666,ecg667,ecg668,ecg669,ecg670,ecg671,ecg672,ecg673,ecg674,ecg675,ecg676,ecg677,ecg678,ecg679,ecg680,ecg681,ecg682,ecg683,ecg684,ecg685,ecg686,ecg687,ecg688,ecg689,ecg690,ecg691,ecg692,ecg693,ecg694,ecg695,ecg696,ecg697,ecg698,ecg699,ecg700,ecg701,ecg702,ecg703,ecg704,ecg705,ecg706,ecg707,ecg708,ecg709,ecg710,ecg711,ecg712,ecg713,ecg714,ecg715,ecg716,ecg717,ecg718,ecg719,ecg720,ecg721,ecg722,ecg723,ecg724,ecg725,ecg726,ecg727,ecg728,ecg729,ecg730,ecg731,ecg732,ecg733,ecg734,ecg735,ecg736,ecg737,ecg738,ecg739,ecg740,ecg741,ecg742,ecg743,ecg744,ecg745,ecg746,ecg747,ecg748,ecg749,ecg750,ecg751,ecg752,ecg753,ecg754,ecg755,ecg756,ecg757,ecg758,ecg759,ecg760,ecg761,ecg762,ecg763,ecg764,ecg765,ecg766,ecg767,ecg768,ecg769,ecg770,ecg771,ecg772,ecg773,ecg774,ecg775,ecg776,ecg777,ecg778,ecg779,ecg780,ecg781,ecg782,ecg783,ecg784,ecg785,ecg786,ecg787,ecg788,ecg789,ecg790,ecg791,ecg792,ecg793,ecg794,ecg795,ecg796,ecg797,ecg798,ecg799,data_in,clk,nReset);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_p_src_rows_V_2_loc_channel_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_p_src_rows_V_2_loc_channel (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_p_src_rows_V_2_loc_channel_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_p_src_rows_V_2_loc_channel_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:12:22 08/30/2014
// Design Name: lab4dpath
// Module Name: C:/ece4743/projects/lab4_part1_solution/tb_lab4dpath.v
// Project Name: lab4_part1_solution
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: lab4dpath
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lab4dpath;
// Inputs
reg [9:0] x1;
reg [9:0] x2;
reg [9:0] x3;
// Outputs
wire [9:0] y;
reg clock;
reg[8*100:1] aline;
`define FSIZE 1024
`define LATENCY 2
integer infifo[(`FSIZE-1):0];
integer head,tail;
integer fd;
integer count,status;
integer i_a, i_b, i_c, i_result;
integer o_a, o_b, o_c, o_result;
integer errors;
integer clock_count;
// Instantiate the Unit Under Test (UUT)
lab4dpath uut (
.x1(x1),
.x2(x2),
.x3(x3),
.clk(clock),
.y(y)
);
initial begin
clock = 0;
#100 //reset delay
forever #25 clock = ~clock;
end
initial begin
// Initialize Inputs
x1 = 0;
x2 = 0;
x3 = 0;
head = 0;
tail = 0;
clock_count = 0;
fd = $fopen("multadd_vectors.txt","r");
count = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Add stimulus here
errors = 0;
while ($fgets(aline,fd)) begin
status = $sscanf(aline,"%x %x %x %x",i_a, i_b, i_c, i_result);
@(negedge clock);
x1 = i_a;
x2 = i_b;
x3 = i_c;
infifo[head]=i_a;inc_head;
infifo[head]=i_b;inc_head;
infifo[head]=i_c;inc_head;
infifo[head]=i_result;inc_head;
end //end while
end
task inc_head;
begin
head = head + 1;
if (head == `FSIZE) head = 0;
end
endtask
task inc_tail;
begin
tail = tail + 1;
if (tail == `FSIZE) tail = 0;
end
endtask
always @(negedge clock) begin
clock_count = clock_count + 1;
if (clock_count > `LATENCY+1) begin
o_a = infifo[tail];inc_tail;
o_b = infifo[tail];inc_tail;
o_c = infifo[tail];inc_tail;
o_result = infifo[tail];inc_tail;
if (o_result == y) begin
$display("%d PASS, x1: %x, x2: %x, x3: %x, y: %x\n",count,o_a,o_b,o_c,y);
end else begin
$display("%d FAIL, x1: %x, x2: %x, x3: %x, y (actual): %x, y (expected): %x\n",count,o_a,o_b,o_c,y,o_result);
errors = errors + 1;
end
end //end if
end
endmodule
|
/*
Framebuffer Format
scrIs320=0 //640x240, 4x4x1 in 32 bits
scrIs320=1 //320x240, 4x4x2 in 64 bits
32-bit blocks:
00pp-pppp pppp-pppp pppp-pppp pppp-pppp
4x4x2, prior colors, UL pixel is ColorA
01pp-pppp pppp-pppp pppp-pppp pppp-pppp
4x4x2, prior colors, UL pixel is ColorB
10yy-yzzz uuvv-wwxx pppp-pppp pppp-pppp
4x4x1, YUV pair, ColorA=yuv, ColorB=zwx
11yy-yydd dduu-uvvv pppp-pppp pppp-pppp
4x4x1, YUVD centroid
64-bit blocks:
00pp-pppp pppp-pppp pppp-pppp pppp-pppp
Reserved
01pp-pppp pppp-pppp pppp-pppp pppp-pppp
Reserved
10yy-yyyy yzzz-zzzz uuuu-vvvv wwww-xxxx
4x4x2, YUV pair, ColorA=yuv, ColorB=zwx
11uu-uuuu uvvv-vvvv yyyy-yyyy dddd-dddd
4x4x2, YUVD centroid
A0_A000_XXXX: VRAM/Ctrl
0000..7FFF: First 32kB
8000..9FFF: Last 8kB
FF00..FFFF: Registers
*/
module ModFbCc(clock, reset,
pixPosX, pixPosY, pixCy, pixCu, pixCv,
pixCellIx, cellData1, cellData2);
// busAddr, busData, busOE, busWR, busHold);
/* verilator lint_off UNUSED */
input clock;
input reset;
input[9:0] pixPosX;
input[9:0] pixPosY;
output[7:0] pixCy;
output[7:0] pixCu;
output[7:0] pixCv;
output[13:0] pixCellIx;
input[31:0] cellData1;
input[31:0] cellData2;
reg[9:0] tPixPosX;
reg[9:0] tPixPosY;
reg[7:0] tPixCy;
reg[7:0] tPixCu;
reg[7:0] tPixCv;
reg[7:0] tPixNextCy;
reg[7:0] tPixNextCu;
reg[7:0] tPixNextCv;
reg[13:0] tPixCellX; //base cell X
reg[13:0] tPixCellY; //base cell Y
reg[13:0] tPixCellIx; //base cell index
reg[3:0] tPixCellFx; //base cell index
reg[13:0] tPixCellNextIx; //base cell index
reg[3:0] tPixCellNextFx; //base cell index
reg scrIs320; //use 320x240 (vs 640x240)
reg scrIsCell64; //cells are 64-bit
reg scrCellNoRead;
reg[31:0] tCell;
reg[31:0] tCell1;
reg[31:0] tCell2;
reg[31:0] tNextCell1;
reg[31:0] tNextCell2;
reg[9:0] tCellCy;
reg[9:0] tCellDy;
reg[9:0] tCellCu;
reg[9:0] tCellCv;
reg[9:0] tCellMCy;
reg[9:0] tCellNCy;
reg[9:0] tCellMCu;
reg[9:0] tCellNCu;
reg[9:0] tCellMCv;
reg[9:0] tCellNCv;
reg[9:0] tCellNextMCy;
reg[9:0] tCellNextNCy;
reg[9:0] tCellNextMCu;
reg[9:0] tCellNextNCu;
reg[9:0] tCellNextMCv;
reg[9:0] tCellNextNCv;
reg[7:0] tCellCy0;
reg[7:0] tCellCu0;
reg[7:0] tCellCv0;
reg[7:0] tCellCy1;
reg[7:0] tCellCu1;
reg[7:0] tCellCv1;
reg[7:0] tCellCy2;
reg[7:0] tCellCu2;
reg[7:0] tCellCv2;
reg[7:0] tCellCy3;
reg[7:0] tCellCu3;
reg[7:0] tCellCv3;
reg[1:0] tCellBit;
reg[1:0] tCellNextBit;
reg[31:0] tCellBits;
reg[31:0] tCellNextBits;
reg tCellUse32;
reg tCellNextUse32;
assign pixCellIx = tPixCellIx;
assign pixCy = tPixCy;
assign pixCu = tPixCu;
assign pixCv = tPixCv;
always @ (clock)
begin
scrIs320 = 1;
scrIsCell64 = 0;
// scrIs320 = scrCell2[2047][0];
// scrIs320 = scrCell2[11'h7C0][0];
tCellCy=0;
tCellDy=0;
tCellCu=0;
tCellCv=0;
tCellNextMCy=tCellMCy;
tCellNextNCy=tCellNCy;
tCellNextMCu=tCellMCu;
tCellNextNCu=tCellNCy;
tCellNextMCv=tCellMCv;
tCellNextNCv=tCellNCv;
tCellNextBits=0;
tCellNextBit=0;
tCellNextUse32=0;
tPixCellX=0;
tPixCellY=0;
if(scrIs320)
begin
tPixCellX[6:0] = tPixPosX[9:3];
tPixCellY[6:0] = tPixPosY[8:2];
tPixCellNextFx[1:0] = tPixPosX[2:1];
tPixCellNextFx[3:2] = tPixPosY[1:0];
if(scrIsCell64)
tPixCellNextIx = tPixCellY*160 + tPixCellX*2;
else
tPixCellNextIx = tPixCellY*80 + tPixCellX;
end
else
begin
tPixCellX[7:0] = tPixPosX[9:2];
tPixCellY[6:0] = tPixPosY[8:2];
tPixCellNextFx[1:0] = tPixPosX[1:0];
tPixCellNextFx[3:2] = tPixPosY[1:0];
tPixCellNextIx = tPixCellY*160 + tPixCellX;
end
// if(scrIs320)
if(scrIsCell64)
begin
case(tCell1[31:30])
2: begin
tCellNextMCy[7:1]=tCell1[29:23];
tCellNextNCy[7:1]=tCell1[22:16];
tCellNextMCy[0]=tCell1[29];
tCellNextNCy[0]=tCell1[22];
tCellNextMCu[7:4]=tCell1[15:12];
tCellNextMCv[7:4]=tCell1[11: 8];
tCellNextNCu[7:4]=tCell1[ 7: 4];
tCellNextNCv[7:4]=tCell1[ 3: 0];
tCellNextMCu[3:0]=0;
tCellNextMCv[3:0]=0;
tCellNextNCu[3:0]=0;
tCellNextNCv[3:0]=0;
tCellNextBits = tCell2;
tCellNextUse32 = 1;
end
3: begin
tCellCy[7:0]=tCell1[15: 8];
tCellDy[7:0]=tCell1[ 7: 0];
tCellCu[7:1]=tCell1[29:23];
tCellCv[7:1]=tCell1[22:16];
tCellCu[0]=0;
tCellCv[0]=0;
tCellNextMCy=tCellCy-(tCellDy>>1);
tCellNextNCy=tCellMCy+tCellDy;
tCellNextMCu=tCellCu;
tCellNextNCu=tCellCu;
tCellNextMCv=tCellCv;
tCellNextNCv=tCellCv;
tCellNextBits = tCell2;
tCellNextUse32 = 1;
end
endcase
end
else
begin
tCell = tPixCellIx[0] ? tCell2 : tCell1;
case(tCell[31:30])
0: begin
tCellNextBits[31:0] = tCell[31:0];
tCellNextUse32=1;
end
1: begin
tCellNextBits[31:0] = tCell[31:0];
tCellNextUse32=1;
end
2: begin
tCellNextMCy[7:5]=tCell[29:27];
tCellNextNCy[7:5]=tCell[26:24];
tCellNextMCy[4:2]=tCell[29:27];
tCellNextNCy[4:2]=tCell[26:24];
tCellNextMCy[1:0]=tCell[29:28];
tCellNextNCy[1:0]=tCell[26:25];
tCellNextMCu[7:6]=tCell[23:22];
tCellNextMCv[7:6]=tCell[21:20];
tCellNextNCu[7:6]=tCell[19:18];
tCellNextNCv[7:6]=tCell[17:16];
tCellNextMCu[5:0]=0;
tCellNextMCv[5:0]=0;
tCellNextNCu[5:0]=0;
tCellNextNCv[5:0]=0;
tCellNextBits[15:0] = tCell[15:0];
end
3: begin
tCellCy[7:4]=tCell[29:26];
tCellCy[3:0]=tCell[29:26];
tCellDy[7:4]=tCell[25:22];
tCellDy[3:0]=tCell[25:22];
tCellCu[7:5]=tCell[21:19];
tCellCv[7:5]=tCell[18:16];
tCellCu[4:0]=0;
tCellCv[4:0]=0;
tCellNextMCy=tCellCy-(tCellDy>>1);
tCellNextNCy=tCellMCy+tCellDy;
tCellNextMCu=tCellCu;
tCellNextNCu=tCellCu;
tCellNextMCv=tCellCv;
tCellNextNCv=tCellCv;
tCellNextBits[15:0] = tCell[15:0];
end
endcase
end
// tCellNextMCy=128;
// tCellNextNCy=128;
// tCellNextMCu=0;
// tCellNextNCu=255;
// tCellNextMCv=0;
// tCellNextNCv=255;
if(tCellUse32)
begin
case(tPixCellFx)
0: tCellNextBit=tCellBits[31:30];
1: tCellNextBit=tCellBits[29:28];
2: tCellNextBit=tCellBits[27:26];
3: tCellNextBit=tCellBits[25:24];
4: tCellNextBit=tCellBits[23:22];
5: tCellNextBit=tCellBits[21:20];
6: tCellNextBit=tCellBits[19:18];
7: tCellNextBit=tCellBits[17:16];
8: tCellNextBit=tCellBits[15:14];
9: tCellNextBit=tCellBits[13:12];
10: tCellNextBit=tCellBits[11:10];
11: tCellNextBit=tCellBits[ 9: 8];
12: tCellNextBit=tCellBits[ 7: 6];
13: tCellNextBit=tCellBits[ 5: 4];
14: tCellNextBit=tCellBits[ 3: 2];
15: tCellNextBit=tCellBits[ 1: 0];
endcase
end
else
begin
tCellNextBit[1]=0;
case(tPixCellFx)
0: tCellNextBit[0]=tCellBits[15];
1: tCellNextBit[0]=tCellBits[14];
2: tCellNextBit[0]=tCellBits[13];
3: tCellNextBit[0]=tCellBits[12];
4: tCellNextBit[0]=tCellBits[11];
5: tCellNextBit[0]=tCellBits[10];
6: tCellNextBit[0]=tCellBits[ 9];
7: tCellNextBit[0]=tCellBits[ 8];
8: tCellNextBit[0]=tCellBits[ 7];
9: tCellNextBit[0]=tCellBits[ 6];
10: tCellNextBit[0]=tCellBits[ 5];
11: tCellNextBit[0]=tCellBits[ 5];
12: tCellNextBit[0]=tCellBits[ 3];
13: tCellNextBit[0]=tCellBits[ 2];
14: tCellNextBit[0]=tCellBits[ 1];
15: tCellNextBit[0]=tCellBits[ 0];
endcase
end
tPixNextCy = 0;
tPixNextCu = 0;
tPixNextCv = 0;
// tCellCy0 = tCellLastNCy[7:0];
// tCellCu0 = tCellLastNCu[7:0];
// tCellCv0 = tCellLastNCv[7:0];
// tCellCy1 = tCellLastMCy[7:0];
// tCellCu1 = tCellLastMCu[7:0];
// tCellCv1 = tCellLastMCv[7:0];
if(tCellNCy[9])
tCellCy0 = 0;
else if(tCellNCy[8])
tCellCy0 = 255;
else
tCellCy0 = tCellNCy[7:0];
if(tCellNCu[9])
tCellCu0 = 0;
else if(tCellNCu[8])
tCellCu0 = 255;
else
tCellCu0 = tCellNCu[7:0];
if(tCellNCv[9])
tCellCv0 = 0;
else if(tCellNCv[8])
tCellCv0 = 255;
else
tCellCv0 = tCellNCv[7:0];
if(tCellMCy[9])
tCellCy1 = 0;
else if(tCellMCy[8])
tCellCy1 = 255;
else
tCellCy1 = tCellMCy[7:0];
if(tCellMCu[9])
tCellCu1 = 0;
else if(tCellMCu[8])
tCellCu1 = 255;
else
tCellCu1 = tCellMCu[7:0];
if(tCellMCv[9])
tCellCv1 = 0;
else if(tCellMCv[8])
tCellCv1 = 255;
else
tCellCv1 = tCellMCv[7:0];
tCellCy2=(tCellCy0>>1)+(tCellCy0>>2)+(tCellCy1>>2);
tCellCu2=(tCellCu0>>1)+(tCellCu0>>2)+(tCellCu1>>2);
tCellCv2=(tCellCv0>>1)+(tCellCv0>>2)+(tCellCv1>>2);
tCellCy3=(tCellCy1>>1)+(tCellCy1>>2)+(tCellCy0>>2);
tCellCu3=(tCellCu1>>1)+(tCellCu1>>2)+(tCellCu0>>2);
tCellCv3=(tCellCv1>>1)+(tCellCv1>>2)+(tCellCv0>>2);
if(tCellBit[1])
begin
if(tCellBit[0])
begin
tPixNextCy = tCellCy2;
tPixNextCu = tCellCu2;
tPixNextCv = tCellCv2;
end
else
begin
tPixNextCy = tCellCy3;
tPixNextCu = tCellCu3;
tPixNextCv = tCellCv3;
end
end
else
begin
if(tCellBit[0])
begin
tPixNextCy = tCellCy0;
tPixNextCu = tCellCu0;
tPixNextCv = tCellCv0;
end
else
begin
tPixNextCy = tCellCy1;
tPixNextCu = tCellCu1;
tPixNextCv = tCellCv1;
end
end
// tPixNextCy = 128;
// tPixNextCu = 0;
// tPixNextCv = 0;
end
always @ (posedge clock)
begin
tPixPosX <= pixPosX;
tPixPosY <= pixPosY;
tPixCellIx <= tPixCellNextIx;
tPixCellFx <= tPixCellNextFx;
tCell1 <= cellData1;
tCell2 <= cellData2;
tCellMCy <= tCellNextMCy;
tCellNCy <= tCellNextNCy;
tCellMCu <= tCellNextMCu;
tCellNCu <= tCellNextNCu;
tCellMCv <= tCellNextMCv;
tCellNCv <= tCellNextNCv;
tCellBits <= tCellNextBits;
tCellBit <= tCellNextBit;
tCellUse32 <= tCellNextUse32;
tPixCy <= tPixNextCy;
tPixCu <= tPixNextCu;
tPixCv <= tPixNextCv;
end
endmodule
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module VCC (output V);
assign V = 1'b1;
endmodule // VCC
module GND (output G);
assign G = 1'b0;
endmodule // GND
/* Altera Cyclone V devices Input Buffer Primitive */
module cyclonev_io_ibuf
(output o,
(* iopad_external_pin *) input i,
(* iopad_external_pin *) input ibar,
input dynamicterminationcontrol);
parameter differential_mode = "false";
parameter bus_hold = "false";
parameter simulate_z_as = "Z";
parameter lpm_type = "cyclonev_io_ibuf";
assign o = i;
endmodule // cyclonev_io_ibuf
/* Altera Cyclone V devices Output Buffer Primitive */
module cyclonev_io_obuf
((* iopad_external_pin *) output o,
input i, oe, dynamicterminationcontrol,
input [15:0] seriesterminationcontrol, parallelterminationcontrol,
input devoe,
(* iopad_external_pin *) output obar);
parameter open_drain_output = "false";
parameter bus_hold = "false";
parameter shift_series_termination_control = "false";
parameter sim_dynamic_termination_control_is_connected = "false";
parameter lpm_type = "cyclonev_io_obuf";
assign o = oe ? i : 1'bz;
endmodule // cyclonev_io_obuf
/* Altera Cyclone V LUT Primitive */
module cyclonev_lcell_comb
(output combout, cout, sumout, shareout,
input dataa, datab, datac, datad,
input datae, dataf, datag, cin,
input sharein);
parameter lut_mask = 64'hFFFFFFFFFFFFFFFF;
parameter dont_touch = "off";
parameter lpm_type = "cyclonev_lcell_comb";
parameter shared_arith = "off";
parameter extended_lut = "off";
// Internal variables
// Sub mask for fragmented LUTs
wire [15:0] mask_a, mask_b, mask_c, mask_d;
// Independent output for fragmented LUTs
wire output_0, output_1, output_2, output_3;
// Extended mode uses mux to define the output
wire mux_0, mux_1;
// Input for hold the shared LUT mode value
wire shared_lut_alm;
// Simulation model of 4-input LUT
function lut4;
input [15:0] mask;
input dataa, datab, datac, datad;
reg [7:0] s3;
reg [3:0] s2;
reg [1:0] s1;
begin
s3 = datad ? mask[15:8] : mask[7:0];
s2 = datac ? s3[7:4] : s3[3:0];
s1 = datab ? s2[3:2] : s2[1:0];
lut4 = dataa ? s1[1] : s1[0];
end
endfunction // lut4
// Simulation model of 5-input LUT
function lut5;
input [31:0] mask; // wp-01003.pdf, page 3: "a 5-LUT can be built with two 4-LUTs and a multiplexer.
input dataa, datab, datac, datad, datae;
reg upper_lut_value;
reg lower_lut_value;
begin
upper_lut_value = lut4(mask[31:16], dataa, datab, datac, datad);
lower_lut_value = lut4(mask[15:0], dataa, datab, datac, datad);
lut5 = (datae) ? upper_lut_value : lower_lut_value;
end
endfunction // lut5
// Simulation model of 6-input LUT
function lut6;
input [63:0] mask;
input dataa, datab, datac, datad, datae, dataf;
reg upper_lut_value;
reg lower_lut_value;
reg out_0, out_1, out_2, out_3;
begin
upper_lut_value = lut5(mask[63:32], dataa, datab, datac, datad, datae);
lower_lut_value = lut5(mask[31:0], dataa, datab, datac, datad, datae);
lut6 = (dataf) ? upper_lut_value : lower_lut_value;
end
endfunction // lut6
assign {mask_a, mask_b, mask_c, mask_d} = {lut_mask[15:0], lut_mask[31:16], lut_mask[47:32], lut_mask[63:48]};
`ifdef ADVANCED_ALM
always @(*) begin
if(extended_lut == "on")
shared_lut_alm = datag;
else
shared_lut_alm = datac;
// Build the ALM behaviour
out_0 = lut4(mask_a, dataa, datab, datac, datad);
out_1 = lut4(mask_b, dataa, datab, shared_lut_alm, datad);
out_2 = lut4(mask_c, dataa, datab, datac, datad);
out_3 = lut4(mask_d, dataa, datab, shared_lut_alm, datad);
end
`else
`ifdef DEBUG
initial $display("Advanced ALM lut combine is not implemented yet");
`endif
`endif
endmodule // cyclonev_lcell_comb
/* Altera D Flip-Flop Primitive */
module dffeas
(output q,
input d, clk, clrn, prn, ena,
input asdata, aload, sclr, sload);
// Timing simulation is not covered
parameter power_up="dontcare";
parameter is_wysiwyg="false";
reg q_tmp;
wire reset;
reg [7:0] debug_net;
assign reset = (prn && sclr && ~clrn && ena);
assign q = q_tmp & 1'b1;
always @(posedge clk, posedge aload) begin
if(reset) q_tmp <= 0;
else q_tmp <= d;
end
assign q = q_tmp;
endmodule // dffeas
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:47:43 03/06/2017
// Design Name: MUX32
// Module Name: D:/Projects/XilinxISE/HW1/Homework1/testMUX32.v
// Project Name: Homework1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: MUX32
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testMUX32;
// Inputs
reg [31:0] in;
reg [4:0] sel;
// Outputs
wire out;
// Instantiate the DESIGN Under Test (DUT)
MUX32 dut (
.in(in),
.sel(sel),
.out(out)
);
/*
//integer i;
initial begin
// Initialize Inputs
in = 0;
sel = 0;
for(sel=0;sel<=4'b1111 ;sel=sel+1) begin
// Wait 100 ns for global reset to finish
for(in=0;in<=32'hEEEEEEEE ;in=in+1) begin
#30;
end
end
// Add stimulus here
end
*/
initial begin
// Initialize Inputs
in = 0;
sel = 0;
#30;
in=32'hEEEEEEEE ;
sel=4'b1111 ;
#30;
in=32'hEE0E5EA0 ;
sel=4'b0010 ;
#30;
in=32'hEEEE5EEE ;
sel=4'b1011 ;
#30;
in=32'h000050A0 ;
sel=4'b1000 ;
#30;
in=32'hEE3EEEEE ;
sel=4'b1011 ;
#30;
in=32'h0AB000A0 ;
sel=4'b1011 ;
#30;
in=32'hEE0E5EEE ;
sel=4'b1001 ;
#30;
in=32'h0AB000B0 ;
sel=4'b0011 ;
#30;
in=32'hEE0E5EAE ;
sel=4'b0011 ;
#30;
in=32'hEA003070 ;
sel=4'b1111 ;
#30;
in=32'h100200E5 ;
sel=4'b0110 ;
#30;
in=32'hD0D020E0 ;
sel=4'b1001 ;
#30;
in=32'h0607A061 ;
sel=4'b0001 ;
#30;
in=32'h09005E00 ;
sel=4'b1000 ;
end
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define SD #1
`timescale 1ns/1ps
`include "include/mbus_def.v"
module tb_layer_ctrl();
`include "include/mbus_func.v"
parameter LC_INT_DEPTH=13;
parameter LC_MEM_DEPTH=65536;
parameter LC_RF_DEPTH=256;
localparam BULK_MEM_CTRL_REG_IDX = 242;
localparam STREAM_CH0_REG0_IDX = 236;
localparam STREAM_CH0_REG1_IDX = 237;
localparam STREAM_CH0_REG2_IDX = 238;
localparam STREAM_CH1_REG0_IDX = 232;
localparam STREAM_CH1_REG1_IDX = 233;
localparam STREAM_CH1_REG2_IDX = 234;
reg clk, resetn;
wire SCLK;
// n0 connections
reg [LC_INT_DEPTH-1:0] n0_int_vector;
wire [LC_INT_DEPTH-1:0] n0_clr_int;
// end of n0 connections
// n1 connections
reg [LC_INT_DEPTH-1:0] n1_int_vector;
wire [LC_INT_DEPTH-1:0] n1_clr_int;
// end of n1 connections
// n2 connections
reg [LC_INT_DEPTH-1:0] n2_int_vector;
wire [LC_INT_DEPTH-1:0] n2_clr_int;
// end of n2 connections
// n3 connections
reg [LC_INT_DEPTH-1:0] n3_int_vector;
wire [LC_INT_DEPTH-1:0] n3_clr_int;
// end of n3 connections
// c0 connections
reg [`ADDR_WIDTH-1:0] c0_tx_addr;
reg [`DATA_WIDTH-1:0] c0_tx_data;
reg c0_tx_req, c0_priority, c0_tx_pend, c0_tx_resp_ack, c0_req_int;
wire c0_tx_ack, c0_tx_succ, c0_tx_fail;
wire [`ADDR_WIDTH-1:0] c0_rx_addr;
wire [`DATA_WIDTH-1:0] c0_rx_data;
wire c0_rx_req, c0_rx_fail, c0_rx_pend, c0_rx_broadcast;
reg c0_rx_ack;
wire c0_lc_pwr_on, c0_lc_release_clk, c0_lc_release_rst, c0_lc_release_iso;
// end of c0 connections
// connection between nodes
wire w_n0n1, w_n1n2, w_n2n3, w_n3c0, w_c0n0;
wire w_n0_clk_out, w_n1_clk_out, w_n2_clk_out, w_n3_clk_out;
// testbench variables
reg [31:0] rand_dat, rand_dat2;
reg [4:0] state;
reg [5:0] word_counter;
reg [7:0] rf_read_length;
reg [7:0] rf_addr;
reg [29:0] mem_addr;
reg mem_ptr_set;
reg [1:0] mem_access_state;
reg [7:0] relay_addr;
reg [29:0] mem_relay_loc;
reg [7:0] rf_relay_loc;
reg [3:0] dest_short_addr;
reg [23:0] rf_data;
reg [31:0] mem_data;
reg [19:0] mem_read_length;
reg [3:0] enum_short_addr;
reg [19:0] long_addr;
reg [1:0] layer_number;
reg [LC_INT_DEPTH-1:0] int_vec;
reg [31:0] mem_w_data;
reg [3:0] functional_id;
reg [23:0] rf_w_data;
reg [1:0] stream_channel;
integer handle;
integer task_counter;
localparam TB_PROC_UP = 0;
localparam TB_QUERY = 1;
localparam TB_ENUM = 2;
localparam TB_ALL_WAKEUP = 3;
localparam TB_RF_WRITE = 4;
localparam TB_RF_READ = 5;
localparam TB_MEM_WRITE = 6;
localparam TB_MEM_READ = 7;
localparam TB_SEL_SLEEP_FULL_PREFIX = 8;
localparam TB_ALL_SLEEP = 9;
localparam TB_ALL_SHORT_ADDR_INVALID = 10;
localparam TB_SINGLE_INTERRUPT = 11;
localparam TB_MULTIPLE_INTERRUPT = 12;
localparam TB_SINGLE_MEM_WRITE = 13;
localparam TB_ARBITRARY_CMD = 14;
localparam TB_SINGLE_RF_WRITE = 15;
localparam TB_SHORT_MEM_READ = 16;
localparam TB_STREAMING = 17;
localparam TX_WAIT = 31;
reg c0_auto_rx_ack;
layer_wrapper #(.ADDRESS(20'hbbbb0), .LC_INT_DEPTH(LC_INT_DEPTH)) layer0(
.CLK(clk), .RESETn(resetn),
.INT_VECTOR(n0_int_vector),
.CLR_INT_EXTERNAL(n0_clr_int),
// mbus
.CLKIN(SCLK), .CLKOUT(w_n0_clk_out), .DIN(w_c0n0), .DOUT(w_n0n1));
layer_wrapper #(.ADDRESS(20'hbbbb1), .LC_INT_DEPTH(LC_INT_DEPTH)) layer1(
.CLK(clk), .RESETn(resetn),
.INT_VECTOR(n1_int_vector),
.CLR_INT_EXTERNAL(n1_clr_int),
// mbus
.CLKIN(w_n0_clk_out), .CLKOUT(w_n1_clk_out), .DIN(w_n0n1), .DOUT(w_n1n2));
layer_wrapper #(.ADDRESS(20'hbbbb2), .LC_INT_DEPTH(LC_INT_DEPTH)) layer2(
.CLK(clk), .RESETn(resetn),
.INT_VECTOR(n2_int_vector),
.CLR_INT_EXTERNAL(n2_clr_int),
// mbus
.CLKIN(w_n1_clk_out), .CLKOUT(w_n2_clk_out), .DIN(w_n1n2), .DOUT(w_n2n3));
layer_wrapper #(.ADDRESS(20'hbbbb2), .LC_INT_DEPTH(LC_INT_DEPTH)) layer3(
.CLK(clk), .RESETn(resetn),
.INT_VECTOR(n3_int_vector),
.CLR_INT_EXTERNAL(n3_clr_int),
// mbus
.CLKIN(w_n2_clk_out), .CLKOUT(w_n3_clk_out), .DIN(w_n2n3), .DOUT(w_n3c0));
mbus_ctrl_layer_wrapper #(.ADDRESS(20'haaaa0)) c0
(.CLK_EXT(clk), .CLKIN(w_n3_clk_out), .CLKOUT(SCLK), .RESETn(resetn), .DIN(w_n3c0), .DOUT(w_c0n0),
.TX_ADDR(c0_tx_addr), .TX_DATA(c0_tx_data), .TX_REQ(c0_tx_req), .TX_ACK(c0_tx_ack), .TX_PEND(c0_tx_pend), .TX_PRIORITY(c0_priority),
.RX_ADDR(c0_rx_addr), .RX_DATA(c0_rx_data), .RX_REQ(c0_rx_req), .RX_ACK(c0_rx_ack), .RX_FAIL(c0_rx_fail), .RX_PEND(c0_rx_pend),
.TX_SUCC(c0_tx_succ), .TX_FAIL(c0_tx_fail), .TX_RESP_ACK(c0_tx_resp_ack), .RX_BROADCAST(c0_rx_broadcast),
.LC_POWER_ON(c0_lc_pwr_on), .LC_RELEASE_CLK(c0_lc_release_clk), .LC_RELEASE_RST(c0_lc_release_rst), .LC_RELEASE_ISO(c0_lc_release_iso),
.REQ_INT(c0_req_int));
`include "tasks.v"
initial
begin
task_counter = 0;
clk = 0;
resetn = 1;
mem_addr = 0;
mem_ptr_set = 0;
mem_access_state = 0;
mem_data = 0;
mem_relay_loc = 0;
mem_read_length = 0;
rf_addr = 0;
rf_data = 0;
rf_read_length = 0;
rf_relay_loc = 0;
relay_addr = 0;
enum_short_addr = 4'h2;
long_addr = 20'haaaa0;
layer_number = 0;
int_vec = 0;
mem_w_data = 0;
functional_id = 0;
stream_channel = 0;
@ (posedge clk);
@ (posedge clk);
@ (posedge clk);
`SD resetn = 0;
@ (posedge clk);
@ (posedge clk);
`SD resetn = 1;
@ (posedge clk);
@ (posedge clk);
//VCD DUMP SECTION
//`ifdef APR
/*
`ifdef TASK4
$dumpfile("task4.vcd");
`elsif TASK5
$dumpfile("task5.vcd");
`endif
$dumpvars(0, tb_ulpb_node32);
*/
//`endif
//SDF ANNOTATION
`ifdef SYN
$sdf_annotate("../syn/layer_ctrl_v2.dc.sdf", layer0.lc0);
$sdf_annotate("../syn/layer_ctrl_v2.dc.sdf", layer1.lc0);
$sdf_annotate("../syn/layer_ctrl_v2.dc.sdf", layer2.lc0);
$sdf_annotate("../syn/layer_ctrl_v2.dc.sdf", layer3.lc0);
`endif
/*
`elsif APR
$sdf_annotate("../apr/ulpb_ctrl_wrapper/ulpb_ctrl_wrapper.apr.sdf", c0);
$sdf_annotate("../apr/ulpb_node32_ab/ulpb_node32_ab.apr.sdf", n0);
$sdf_annotate("../apr/ulpb_node32_cd/ulpb_node32_cd.apr.sdf", n1);
$sdf_annotate("../apr/ulpb_node32_ef/ulpb_node32_ef.apr.sdf", n2);
`endif
*/
//************************
//TESTBENCH BEGINS
//Calls Tasks from tasks.v
//***********************
task0();
end // initial begin
//Changed to 400K for primetime calculations
always #1250 clk = ~clk;
`include "task_list.v"
always @ (posedge layer0.lc_pwr_on)
$fdisplay(handle, "N0 LC Sleep");
always @ (posedge layer1.lc_pwr_on)
$fdisplay(handle, "N1 LC Sleep");
always @ (posedge layer2.lc_pwr_on)
$fdisplay(handle, "N2 LC Sleep");
always @ (posedge layer3.lc_pwr_on)
$fdisplay(handle, "N3 LC Sleep");
always @ (posedge c0_lc_pwr_on)
$fdisplay(handle, "Processor Sleep");
always @ (negedge layer0.lc_pwr_on)
$fdisplay(handle, "N0 LC Wakeup");
always @ (negedge layer1.lc_pwr_on)
$fdisplay(handle, "N1 LC Wakeup");
always @ (negedge layer2.lc_pwr_on)
$fdisplay(handle, "N2 LC Wakeup");
always @ (negedge layer3.lc_pwr_on)
$fdisplay(handle, "N3 LC Wakeup");
always @ (negedge c0_lc_pwr_on)
$fdisplay(handle, "Processor Wakeup");
always @ (posedge clk or negedge resetn)
begin
if (~resetn)
begin
n0_int_vector <= 0;
n1_int_vector <= 0;
n2_int_vector <= 0;
n3_int_vector <= 0;
c0_tx_addr <= 0;
c0_tx_data <= 0;
c0_tx_pend <= 0;
c0_tx_req <= 0;
c0_priority <= 0;
c0_req_int <= 0;
c0_auto_rx_ack <= 1;
word_counter <= 0;
end
else
begin
if (c0_tx_ack) c0_tx_req <= 0;
if (c0_tx_fail & c0_tx_req) c0_tx_req <= 0;
end
end
// n0 interrupt control
wire [LC_INT_DEPTH-1:0] n0_int_clr_mask = (n0_clr_int & n0_int_vector);
always @ (posedge clk)
begin
if (n0_int_clr_mask)
n0_int_vector <= `SD (n0_int_vector & (~n0_int_clr_mask));
end
always @ (posedge layer0.rx_fail)
$fdisplay(handle, "N0 RX Fail");
always @ (posedge layer0.rx_req)
begin
$fdisplay(handle, "N0 RX Success");
//$fdisplay(handle, "N0 Data out =\t32'h%h", layer0.rx_data);
end
always @ (posedge layer0.tx_succ)
$fdisplay(handle, "N0 TX Success\n");
always @ (posedge layer0.tx_fail)
$fdisplay(handle, "N0 TX Fail\n");
// end of n0 interrupt control
// n1 interrupt control
wire [LC_INT_DEPTH-1:0] n1_int_clr_mask = (n1_clr_int & n1_int_vector);
always @ (posedge clk)
begin
if (n1_int_clr_mask)
n1_int_vector <= `SD (n1_int_vector & (~n1_int_clr_mask));
end
always @ (posedge layer1.rx_fail)
$fdisplay(handle, "N1 RX Fail");
always @ (posedge layer1.rx_req)
begin
$fdisplay(handle, "N1 RX Success");
//$fdisplay(handle, "N1 Data out =\t32'h%h", layer1.rx_data);
end
always @ (posedge layer1.tx_succ)
$fdisplay(handle, "N1 TX Success\n");
always @ (posedge layer1.tx_fail)
$fdisplay(handle, "N1 TX Fail\n");
// end of n1 interrupt control
// n2 interrupt control
wire [LC_INT_DEPTH-1:0] n2_int_clr_mask = (n2_clr_int & n2_int_vector);
always @ (posedge clk)
begin
if (n2_int_clr_mask)
n2_int_vector <= `SD (n2_int_vector & (~n2_int_clr_mask));
end
always @ (posedge layer2.rx_fail)
$fdisplay(handle, "N2 RX Fail");
always @ (posedge layer2.rx_req)
begin
$fdisplay(handle, "N2 RX Success");
//$fdisplay(handle, "N2 Data out =\t32'h%h", layer2.rx_data);
end
always @ (posedge layer2.tx_succ)
$fdisplay(handle, "N2 TX Success\n");
always @ (posedge layer2.tx_fail)
$fdisplay(handle, "N2 TX Fail\n");
// end of n2 interrupt control
// n3 interrupt control
wire [LC_INT_DEPTH-1:0] n3_int_clr_mask = (n3_clr_int & n3_int_vector);
always @ (posedge clk)
begin
if (n3_int_clr_mask)
n3_int_vector <= `SD (n3_int_vector & (~n3_int_clr_mask));
end
always @ (posedge layer3.rx_fail)
$fdisplay(handle, "N3 RX Fail");
always @ (posedge layer3.rx_req)
begin
$fdisplay(handle, "N3 RX Success");
//$fdisplay(handle, "N3 Data out =\t32'h%h", layer3.rx_data);
end
always @ (posedge layer3.tx_succ)
$fdisplay(handle, "N3 TX Success\n");
always @ (posedge layer3.tx_fail)
$fdisplay(handle, "N3 TX Fail\n");
// end of n3 interrupt control
// c0 rx tx ack control
always @ (negedge resetn)
begin
c0_rx_ack <= 0;
c0_tx_resp_ack <= 0;
end
always @ (posedge c0_rx_fail)
$fdisplay(handle, "C0 RX Fail");
always @ (posedge c0_rx_req)
begin
$fdisplay(handle, "C0 RX Success");
$fdisplay(handle, "C0 Data out =\t32'h%h", c0_rx_data);
end
always @ (posedge clk)
begin
if ((c0_rx_req | c0_rx_fail) & c0_auto_rx_ack)
`SD c0_rx_ack <= 1;
if (c0_rx_ack & (~c0_rx_req))
`SD c0_rx_ack <= 0;
if (c0_rx_ack & (~c0_rx_fail))
`SD c0_rx_ack <= 0;
end
always @ (posedge c0_tx_succ)
$fdisplay(handle, "C0 TX Success");
always @ (posedge c0_tx_fail)
$fdisplay(handle, "C0 TX Fail");
always @ (posedge clk)
begin
if (c0_tx_succ | c0_tx_fail)
`SD c0_tx_resp_ack <= 1;
if (c0_tx_resp_ack & (~c0_tx_succ))
`SD c0_tx_resp_ack <= 0;
if (c0_tx_resp_ack & (~c0_tx_fail))
`SD c0_tx_resp_ack <= 0;
end
// end of c0 rx, tx ack control
always @ (posedge clk or negedge resetn) begin
if (~resetn) begin
rand_dat <= 0;
rand_dat2 <= 0;
end
else begin
rand_dat <= $random;
rand_dat2 <= $random;
end
end
// RF Write output
wire [31:0] layer0_rf0_addr = log2long(layer0.rf0.LOAD) - 1;
wire [31:0] layer1_rf0_addr = log2long(layer1.rf0.LOAD) - 1;
wire [31:0] layer2_rf0_addr = log2long(layer2.rf0.LOAD) - 1;
wire [31:0] layer3_rf0_addr = log2long(layer3.rf0.LOAD) - 1;
genvar idx;
generate
for (idx=0; idx<LC_RF_DEPTH; idx = idx+1)
begin: rf_write
always @ (posedge layer0.rf0.LOAD[idx])
$fdisplay(handle, "Layer 0, RF Write, Addr: 8'h%h,\tData: 24'h%h", layer0_rf0_addr[7:0], layer0.rf0.DIN);
always @ (posedge layer1.rf0.LOAD[idx])
$fdisplay(handle, "Layer 1, RF Write, Addr: 8'h%h,\tData: 24'h%h", layer1_rf0_addr[7:0], layer1.rf0.DIN);
always @ (posedge layer2.rf0.LOAD[idx])
$fdisplay(handle, "Layer 2, RF Write, Addr: 8'h%h,\tData: 24'h%h", layer2_rf0_addr[7:0], layer2.rf0.DIN);
always @ (posedge layer3.rf0.LOAD[idx])
$fdisplay(handle, "Layer 3, RF Write, Addr: 8'h%h,\tData: 24'h%h", layer3_rf0_addr[7:0], layer3.rf0.DIN);
end
endgenerate
// End of RF Write output
// MEM Write output
always @ (posedge layer0.mem0.MEM_ACK_OUT)
if (layer0.mem0.MEM_WRITE)
$fdisplay(handle, "Layer 0, MEM Write, Addr: 30'h%h,\tData: 32'h%h", layer0.mem0.ADDR, layer0.mem0.DATA_IN);
else
$fdisplay(handle, "Layer 0, MEM Read, Addr: 30'h%h,\tData: 32'h%h", layer0.mem0.ADDR, layer0.mem0.DATA_OUT);
always @ (posedge layer1.mem0.MEM_ACK_OUT)
if (layer1.mem0.MEM_WRITE)
$fdisplay(handle, "Layer 1, MEM Write, Addr: 30'h%h,\tData: 32'h%h", layer1.mem0.ADDR, layer1.mem0.DATA_IN);
else
$fdisplay(handle, "Layer 1, MEM Read, Addr: 30'h%h,\tData: 32'h%h", layer1.mem0.ADDR, layer1.mem0.DATA_OUT);
always @ (posedge layer2.mem0.MEM_ACK_OUT)
if (layer2.mem0.MEM_WRITE)
$fdisplay(handle, "Layer 2, MEM Write, Addr: 30'h%h,\tData: 32'h%h", layer2.mem0.ADDR, layer2.mem0.DATA_IN);
else
$fdisplay(handle, "Layer 2, MEM Read, Addr: 30'h%h,\tData: 32'h%h", layer2.mem0.ADDR, layer2.mem0.DATA_OUT);
always @ (posedge layer3.mem0.MEM_ACK_OUT)
if (layer3.mem0.MEM_WRITE)
$fdisplay(handle, "Layer 3, MEM Write, Addr: 30'h%h,\tData: 32'h%h", layer3.mem0.ADDR, layer3.mem0.DATA_IN);
else
$fdisplay(handle, "Layer 3, MEM Read, Addr: 30'h%h,\tData: 32'h%h", layer3.mem0.ADDR, layer3.mem0.DATA_OUT);
// End of MEM Write output
endmodule // tb_layer_ctrl
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_nios2_gen2_0_cpu_mult_cell (
// inputs:
E_src1,
E_src2,
M_en,
clk,
reset_n,
// outputs:
M_mul_cell_p1,
M_mul_cell_p2,
M_mul_cell_p3
)
;
output [ 31: 0] M_mul_cell_p1;
output [ 31: 0] M_mul_cell_p2;
output [ 31: 0] M_mul_cell_p3;
input [ 31: 0] E_src1;
input [ 31: 0] E_src2;
input M_en;
input clk;
input reset_n;
wire [ 31: 0] M_mul_cell_p1;
wire [ 31: 0] M_mul_cell_p2;
wire [ 31: 0] M_mul_cell_p3;
wire mul_clr;
wire [ 31: 0] mul_src1;
wire [ 31: 0] mul_src2;
assign mul_clr = ~reset_n;
assign mul_src1 = E_src1;
assign mul_src2 = E_src2;
altera_mult_add the_altmult_add_p1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[15 : 0]),
.datab (mul_src2[15 : 0]),
.ena0 (M_en),
.result (M_mul_cell_p1)
);
defparam the_altmult_add_p1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p1.input_register_a0 = "UNREGISTERED",
the_altmult_add_p1.input_register_b0 = "UNREGISTERED",
the_altmult_add_p1.input_source_a0 = "DATAA",
the_altmult_add_p1.input_source_b0 = "DATAB",
the_altmult_add_p1.lpm_type = "altera_mult_add",
the_altmult_add_p1.multiplier1_direction = "ADD",
the_altmult_add_p1.multiplier_aclr0 = "ACLR0",
the_altmult_add_p1.multiplier_register0 = "CLOCK0",
the_altmult_add_p1.number_of_multipliers = 1,
the_altmult_add_p1.output_register = "UNREGISTERED",
the_altmult_add_p1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p1.representation_a = "UNSIGNED",
the_altmult_add_p1.representation_b = "UNSIGNED",
the_altmult_add_p1.selected_device_family = "CYCLONEIVE",
the_altmult_add_p1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p1.signed_register_a = "UNREGISTERED",
the_altmult_add_p1.signed_register_b = "UNREGISTERED",
the_altmult_add_p1.width_a = 16,
the_altmult_add_p1.width_b = 16,
the_altmult_add_p1.width_result = 32;
altera_mult_add the_altmult_add_p2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[15 : 0]),
.datab (mul_src2[31 : 16]),
.ena0 (M_en),
.result (M_mul_cell_p2)
);
defparam the_altmult_add_p2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p2.input_register_a0 = "UNREGISTERED",
the_altmult_add_p2.input_register_b0 = "UNREGISTERED",
the_altmult_add_p2.input_source_a0 = "DATAA",
the_altmult_add_p2.input_source_b0 = "DATAB",
the_altmult_add_p2.lpm_type = "altera_mult_add",
the_altmult_add_p2.multiplier1_direction = "ADD",
the_altmult_add_p2.multiplier_aclr0 = "ACLR0",
the_altmult_add_p2.multiplier_register0 = "CLOCK0",
the_altmult_add_p2.number_of_multipliers = 1,
the_altmult_add_p2.output_register = "UNREGISTERED",
the_altmult_add_p2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p2.representation_a = "UNSIGNED",
the_altmult_add_p2.representation_b = "UNSIGNED",
the_altmult_add_p2.selected_device_family = "CYCLONEIVE",
the_altmult_add_p2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p2.signed_register_a = "UNREGISTERED",
the_altmult_add_p2.signed_register_b = "UNREGISTERED",
the_altmult_add_p2.width_a = 16,
the_altmult_add_p2.width_b = 16,
the_altmult_add_p2.width_result = 32;
altera_mult_add the_altmult_add_p3
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[31 : 16]),
.datab (mul_src2[15 : 0]),
.ena0 (M_en),
.result (M_mul_cell_p3)
);
defparam the_altmult_add_p3.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p3.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p3.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p3.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p3.input_register_a0 = "UNREGISTERED",
the_altmult_add_p3.input_register_b0 = "UNREGISTERED",
the_altmult_add_p3.input_source_a0 = "DATAA",
the_altmult_add_p3.input_source_b0 = "DATAB",
the_altmult_add_p3.lpm_type = "altera_mult_add",
the_altmult_add_p3.multiplier1_direction = "ADD",
the_altmult_add_p3.multiplier_aclr0 = "ACLR0",
the_altmult_add_p3.multiplier_register0 = "CLOCK0",
the_altmult_add_p3.number_of_multipliers = 1,
the_altmult_add_p3.output_register = "UNREGISTERED",
the_altmult_add_p3.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p3.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p3.representation_a = "UNSIGNED",
the_altmult_add_p3.representation_b = "UNSIGNED",
the_altmult_add_p3.selected_device_family = "CYCLONEIVE",
the_altmult_add_p3.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p3.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p3.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p3.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p3.signed_register_a = "UNREGISTERED",
the_altmult_add_p3.signed_register_b = "UNREGISTERED",
the_altmult_add_p3.width_a = 16,
the_altmult_add_p3.width_b = 16,
the_altmult_add_p3.width_result = 32;
endmodule
|
`timescale 1ns / 1ps
`include "io.v"
`include "Defintions.v"
module tb_simple_io;
// Inputs
reg Clock;
reg Reset;
// Outputs
wire [5:0] oP;
wire oIE;
reg [5:0] rBotcode;
// Instantiate the Unit Under Test (UUT)
io ionew (
.Clock(Clock),
.Reset(Reset),
.iP(rBotcode),
.oP(oP),
.oIE(oIE)
);
always
begin
#5 Clock = ! Clock;
end
initial begin
$display("Starting GameBoy IO Test\n");
$dumpfile("tb_simple_io.vcd");
$dumpvars(0,tb_simple_io);
// Initialize Inputs
Clock = 0;
Reset = 0;
rBotcode = `NOBOT;
// Wait 100 ns for global reset to finish
#10;
Reset = 1;
#10
Reset = 0;
$display("Reset ready at time %dns", $time);
#10
rBotcode = `NOBOT;
$display("No button pressed at time %dns", $time);
#10
rBotcode = `A;
#10
rBotcode = `NOBOT;
#10
rBotcode = `B;
#10
rBotcode = `START;
#10
rBotcode = `SELECT;
#10
rBotcode = `UP;
#10
rBotcode = `DOWN;
#10
rBotcode = `LEFT;
#10
rBotcode = `RIGHT;
// #10
// rBotcode = `A;
// #10
// rBotcode = `NOBOT;
// #10
// rBotcode = `B;
// #10
// rBotcode = `B & `DOWN;
#100
rBotcode = `NOBOT;
$display("No button pressed at time %dns", $time);
// All done
#100
$finish();
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_b2s_wr_cmd_fsm.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_wr_cmd_fsm (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
output wire s_awready ,
input wire s_awvalid ,
output wire m_awvalid ,
input wire m_awready ,
// signal to increment to the next mc transaction
output wire next ,
// signal to the fsm there is another transaction required
input wire next_pending ,
// Write Data portion has completed or Read FIFO has a slot available (not
// full)
output wire b_push ,
input wire b_full ,
output wire a_push
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// States
localparam SM_IDLE = 2'b00;
localparam SM_CMD_EN = 2'b01;
localparam SM_CMD_ACCEPTED = 2'b10;
localparam SM_DONE_WAIT = 2'b11;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [1:0] state;
// synthesis attribute MAX_FANOUT of state is 20;
reg [1:0] next_state;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
if (reset) begin
state <= SM_IDLE;
end else begin
state <= next_state;
end
end
// Next state transitions.
always @( * )
begin
next_state = state;
case (state)
SM_IDLE:
if (s_awvalid) begin
next_state = SM_CMD_EN;
end else
next_state = state;
SM_CMD_EN:
if (m_awready & next_pending)
next_state = SM_CMD_ACCEPTED;
else if (m_awready & ~next_pending & b_full)
next_state = SM_DONE_WAIT;
else if (m_awready & ~next_pending & ~b_full)
next_state = SM_IDLE;
else
next_state = state;
SM_CMD_ACCEPTED:
next_state = SM_CMD_EN;
SM_DONE_WAIT:
if (!b_full)
next_state = SM_IDLE;
else
next_state = state;
default:
next_state = SM_IDLE;
endcase
end
// Assign outputs based on current state.
assign m_awvalid = (state == SM_CMD_EN);
assign next = ((state == SM_CMD_ACCEPTED)
| (((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE))) ;
assign a_push = (state == SM_IDLE);
assign s_awready = ((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE);
assign b_push = ((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE);
endmodule
`default_nettype wire
|
`include "elink_regmap.vh"
module dut(/*AUTOARG*/
// Outputs
dut_active, clkout, wait_out, access_out, packet_out,
// Inputs
clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
);
//##########################################################################
//# INTERFACE
//##########################################################################
parameter AW = 32;
parameter ID = 12'h810;
parameter S_IDW = 12;
parameter M_IDW = 6;
parameter PW = 2*AW + 40;
parameter N = 1;
parameter RETURN_ADDR = {ID,
`EGROUP_RR,
16'b0}; // axi return addr
//clock,reset
input clk1;
input clk2;
input nreset;
input [N*N-1:0] vdd;
input vss;
output dut_active;
output clkout;
//Stimulus Driven Transaction
input [N-1:0] access_in;
input [N*PW-1:0] packet_in;
output [N-1:0] wait_out;
//DUT driven transaction
output [N-1:0] access_out;
output [N*PW-1:0] packet_out;
input [N-1:0] wait_in;
//##########################################################################
//#BODY
//##########################################################################
wire mem_rd_wait;
wire mem_wr_wait;
wire mem_access;
wire [PW-1:0] mem_packet;
/*AUTOINPUT*/
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire cclk_n; // From elink0 of axi_elink.v
wire cclk_p; // From elink0 of axi_elink.v
wire chip_nreset; // From elink0 of axi_elink.v
wire [11:0] chipid; // From elink0 of axi_elink.v
wire [31:0] m_axi_araddr; // From emaxi of emaxi.v
wire [1:0] m_axi_arburst; // From emaxi of emaxi.v
wire [3:0] m_axi_arcache; // From emaxi of emaxi.v
wire [M_IDW-1:0] m_axi_arid; // From emaxi of emaxi.v
wire [7:0] m_axi_arlen; // From emaxi of emaxi.v
wire m_axi_arlock; // From emaxi of emaxi.v
wire [2:0] m_axi_arprot; // From emaxi of emaxi.v
wire [3:0] m_axi_arqos; // From emaxi of emaxi.v
wire m_axi_arready; // From elink0 of axi_elink.v
wire [2:0] m_axi_arsize; // From emaxi of emaxi.v
wire m_axi_arvalid; // From emaxi of emaxi.v
wire [31:0] m_axi_awaddr; // From emaxi of emaxi.v
wire [1:0] m_axi_awburst; // From emaxi of emaxi.v
wire [3:0] m_axi_awcache; // From emaxi of emaxi.v
wire [M_IDW-1:0] m_axi_awid; // From emaxi of emaxi.v
wire [7:0] m_axi_awlen; // From emaxi of emaxi.v
wire m_axi_awlock; // From emaxi of emaxi.v
wire [2:0] m_axi_awprot; // From emaxi of emaxi.v
wire [3:0] m_axi_awqos; // From emaxi of emaxi.v
wire m_axi_awready; // From elink0 of axi_elink.v
wire [2:0] m_axi_awsize; // From emaxi of emaxi.v
wire m_axi_awvalid; // From emaxi of emaxi.v
wire [S_IDW-1:0] m_axi_bid; // From elink0 of axi_elink.v
wire m_axi_bready; // From emaxi of emaxi.v
wire [1:0] m_axi_bresp; // From elink0 of axi_elink.v
wire m_axi_bvalid; // From elink0 of axi_elink.v
wire [31:0] m_axi_rdata; // From elink0 of axi_elink.v
wire [S_IDW-1:0] m_axi_rid; // From elink0 of axi_elink.v
wire m_axi_rlast; // From elink0 of axi_elink.v
wire m_axi_rready; // From emaxi of emaxi.v
wire [1:0] m_axi_rresp; // From elink0 of axi_elink.v
wire m_axi_rvalid; // From elink0 of axi_elink.v
wire [63:0] m_axi_wdata; // From emaxi of emaxi.v
wire [M_IDW-1:0] m_axi_wid; // From emaxi of emaxi.v
wire m_axi_wlast; // From emaxi of emaxi.v
wire m_axi_wready; // From elink0 of axi_elink.v
wire [7:0] m_axi_wstrb; // From emaxi of emaxi.v
wire m_axi_wvalid; // From emaxi of emaxi.v
wire mailbox_irq; // From elink0 of axi_elink.v
wire [31:0] mem_m_axi_araddr; // From elink0 of axi_elink.v
wire [1:0] mem_m_axi_arburst; // From elink0 of axi_elink.v
wire [3:0] mem_m_axi_arcache; // From elink0 of axi_elink.v
wire [M_IDW-1:0] mem_m_axi_arid; // From elink0 of axi_elink.v
wire [7:0] mem_m_axi_arlen; // From elink0 of axi_elink.v
wire mem_m_axi_arlock; // From elink0 of axi_elink.v
wire [2:0] mem_m_axi_arprot; // From elink0 of axi_elink.v
wire [3:0] mem_m_axi_arqos; // From elink0 of axi_elink.v
wire mem_m_axi_arready; // From esaxi of esaxi.v
wire [2:0] mem_m_axi_arsize; // From elink0 of axi_elink.v
wire mem_m_axi_arvalid; // From elink0 of axi_elink.v
wire [31:0] mem_m_axi_awaddr; // From elink0 of axi_elink.v
wire [1:0] mem_m_axi_awburst; // From elink0 of axi_elink.v
wire [3:0] mem_m_axi_awcache; // From elink0 of axi_elink.v
wire [M_IDW-1:0] mem_m_axi_awid; // From elink0 of axi_elink.v
wire [7:0] mem_m_axi_awlen; // From elink0 of axi_elink.v
wire mem_m_axi_awlock; // From elink0 of axi_elink.v
wire [2:0] mem_m_axi_awprot; // From elink0 of axi_elink.v
wire [3:0] mem_m_axi_awqos; // From elink0 of axi_elink.v
wire mem_m_axi_awready; // From esaxi of esaxi.v
wire [2:0] mem_m_axi_awsize; // From elink0 of axi_elink.v
wire mem_m_axi_awvalid; // From elink0 of axi_elink.v
wire [S_IDW-1:0] mem_m_axi_bid; // From esaxi of esaxi.v
wire mem_m_axi_bready; // From elink0 of axi_elink.v
wire [1:0] mem_m_axi_bresp; // From esaxi of esaxi.v
wire mem_m_axi_bvalid; // From esaxi of esaxi.v
wire [31:0] mem_m_axi_rdata; // From esaxi of esaxi.v
wire [S_IDW-1:0] mem_m_axi_rid; // From esaxi of esaxi.v
wire mem_m_axi_rlast; // From esaxi of esaxi.v
wire mem_m_axi_rready; // From elink0 of axi_elink.v
wire [1:0] mem_m_axi_rresp; // From esaxi of esaxi.v
wire mem_m_axi_rvalid; // From esaxi of esaxi.v
wire [63:0] mem_m_axi_wdata; // From elink0 of axi_elink.v
wire [M_IDW-1:0] mem_m_axi_wid; // From elink0 of axi_elink.v
wire mem_m_axi_wlast; // From elink0 of axi_elink.v
wire mem_m_axi_wready; // From esaxi of esaxi.v
wire [7:0] mem_m_axi_wstrb; // From elink0 of axi_elink.v
wire mem_m_axi_wvalid; // From elink0 of axi_elink.v
wire mem_rd_access; // From esaxi of esaxi.v
wire [PW-1:0] mem_rd_packet; // From esaxi of esaxi.v
wire mem_rr_access; // From ememory of ememory.v
wire [PW-1:0] mem_rr_packet; // From ememory of ememory.v
wire mem_rr_wait; // From esaxi of esaxi.v
wire mem_wr_access; // From esaxi of esaxi.v
wire [PW-1:0] mem_wr_packet; // From esaxi of esaxi.v
wire rxo_rd_wait_n; // From elink0 of axi_elink.v
wire rxo_rd_wait_p; // From elink0 of axi_elink.v
wire rxo_wr_wait_n; // From elink0 of axi_elink.v
wire rxo_wr_wait_p; // From elink0 of axi_elink.v
wire [7:0] txo_data_n; // From elink0 of axi_elink.v
wire [7:0] txo_data_p; // From elink0 of axi_elink.v
wire txo_frame_n; // From elink0 of axi_elink.v
wire txo_frame_p; // From elink0 of axi_elink.v
wire txo_lclk_n; // From elink0 of axi_elink.v
wire txo_lclk_p; // From elink0 of axi_elink.v
// End of automatics
//######################################################################
// GLUE
//######################################################################
assign clkout = clk1;
//######################################################################
//AXI MASTER
//######################################################################
//Split stimulus to read/write
assign wait_out = wr_wait | rd_wait;
assign write_in = access_in & packet_in[0];
assign read_in = access_in & ~packet_in[0];
emaxi #(.M_IDW(M_IDW))
emaxi (.m_axi_aclk (clk1),
.m_axi_aresetn (nreset),
.m_axi_rdata ({m_axi_rdata[31:0],m_axi_rdata[31:0]}),
.rr_wait (wait_in),
.rr_access (access_out),
.rr_packet (packet_out[PW-1:0]),
.wr_wait (wr_wait),
.wr_access (write_in),
.wr_packet (packet_in[PW-1:0]),
.rd_wait (rd_wait),
.rd_access (read_in),
.rd_packet (packet_in[PW-1:0]),
/*AUTOINST*/
// Outputs
.m_axi_awid (m_axi_awid[M_IDW-1:0]),
.m_axi_awaddr (m_axi_awaddr[31:0]),
.m_axi_awlen (m_axi_awlen[7:0]),
.m_axi_awsize (m_axi_awsize[2:0]),
.m_axi_awburst (m_axi_awburst[1:0]),
.m_axi_awlock (m_axi_awlock),
.m_axi_awcache (m_axi_awcache[3:0]),
.m_axi_awprot (m_axi_awprot[2:0]),
.m_axi_awqos (m_axi_awqos[3:0]),
.m_axi_awvalid (m_axi_awvalid),
.m_axi_wid (m_axi_wid[M_IDW-1:0]),
.m_axi_wdata (m_axi_wdata[63:0]),
.m_axi_wstrb (m_axi_wstrb[7:0]),
.m_axi_wlast (m_axi_wlast),
.m_axi_wvalid (m_axi_wvalid),
.m_axi_bready (m_axi_bready),
.m_axi_arid (m_axi_arid[M_IDW-1:0]),
.m_axi_araddr (m_axi_araddr[31:0]),
.m_axi_arlen (m_axi_arlen[7:0]),
.m_axi_arsize (m_axi_arsize[2:0]),
.m_axi_arburst (m_axi_arburst[1:0]),
.m_axi_arlock (m_axi_arlock),
.m_axi_arcache (m_axi_arcache[3:0]),
.m_axi_arprot (m_axi_arprot[2:0]),
.m_axi_arqos (m_axi_arqos[3:0]),
.m_axi_arvalid (m_axi_arvalid),
.m_axi_rready (m_axi_rready),
// Inputs
.m_axi_awready (m_axi_awready),
.m_axi_wready (m_axi_wready),
.m_axi_bid (m_axi_bid[M_IDW-1:0]),
.m_axi_bresp (m_axi_bresp[1:0]),
.m_axi_bvalid (m_axi_bvalid),
.m_axi_arready (m_axi_arready),
.m_axi_rid (m_axi_rid[M_IDW-1:0]),
.m_axi_rresp (m_axi_rresp[1:0]),
.m_axi_rlast (m_axi_rlast),
.m_axi_rvalid (m_axi_rvalid));
//######################################################################
//ELINK
//######################################################################
/*axi_elink AUTO_TEMPLATE (.m_axi_aresetn (nreset),
.s_axi_aresetn (nreset),
.sys_nreset (nreset),
.m_\(.*\) (mem_m_\1[]),
.s_\(.*\) (m_\1[]),
.sys_clk (clk1),
.rxi_\(.*\) (txo_\1[]),
.txi_\(.*\) (rxo_\1[]),
);
*/
axi_elink #(.ID(12'h810),
.ETYPE(0))
elink0 (.elink_active (dut_active),
.s_axi_wstrb ((m_axi_wstrb[3:0] | m_axi_wstrb[7:4])),//NOTE:HACK!!
.m_axi_rdata ({mem_m_axi_rdata[31:0],mem_m_axi_rdata[31:0]}),
/*AUTOINST*/
// Outputs
.rxo_wr_wait_p (rxo_wr_wait_p),
.rxo_wr_wait_n (rxo_wr_wait_n),
.rxo_rd_wait_p (rxo_rd_wait_p),
.rxo_rd_wait_n (rxo_rd_wait_n),
.txo_lclk_p (txo_lclk_p),
.txo_lclk_n (txo_lclk_n),
.txo_frame_p (txo_frame_p),
.txo_frame_n (txo_frame_n),
.txo_data_p (txo_data_p[7:0]),
.txo_data_n (txo_data_n[7:0]),
.chipid (chipid[11:0]),
.chip_nreset (chip_nreset),
.cclk_p (cclk_p),
.cclk_n (cclk_n),
.mailbox_irq (mailbox_irq),
.m_axi_awid (mem_m_axi_awid[M_IDW-1:0]), // Templated
.m_axi_awaddr (mem_m_axi_awaddr[31:0]), // Templated
.m_axi_awlen (mem_m_axi_awlen[7:0]), // Templated
.m_axi_awsize (mem_m_axi_awsize[2:0]), // Templated
.m_axi_awburst (mem_m_axi_awburst[1:0]), // Templated
.m_axi_awlock (mem_m_axi_awlock), // Templated
.m_axi_awcache (mem_m_axi_awcache[3:0]), // Templated
.m_axi_awprot (mem_m_axi_awprot[2:0]), // Templated
.m_axi_awqos (mem_m_axi_awqos[3:0]), // Templated
.m_axi_awvalid (mem_m_axi_awvalid), // Templated
.m_axi_wid (mem_m_axi_wid[M_IDW-1:0]), // Templated
.m_axi_wdata (mem_m_axi_wdata[63:0]), // Templated
.m_axi_wstrb (mem_m_axi_wstrb[7:0]), // Templated
.m_axi_wlast (mem_m_axi_wlast), // Templated
.m_axi_wvalid (mem_m_axi_wvalid), // Templated
.m_axi_bready (mem_m_axi_bready), // Templated
.m_axi_arid (mem_m_axi_arid[M_IDW-1:0]), // Templated
.m_axi_araddr (mem_m_axi_araddr[31:0]), // Templated
.m_axi_arlen (mem_m_axi_arlen[7:0]), // Templated
.m_axi_arsize (mem_m_axi_arsize[2:0]), // Templated
.m_axi_arburst (mem_m_axi_arburst[1:0]), // Templated
.m_axi_arlock (mem_m_axi_arlock), // Templated
.m_axi_arcache (mem_m_axi_arcache[3:0]), // Templated
.m_axi_arprot (mem_m_axi_arprot[2:0]), // Templated
.m_axi_arqos (mem_m_axi_arqos[3:0]), // Templated
.m_axi_arvalid (mem_m_axi_arvalid), // Templated
.m_axi_rready (mem_m_axi_rready), // Templated
.s_axi_arready (m_axi_arready), // Templated
.s_axi_awready (m_axi_awready), // Templated
.s_axi_bid (m_axi_bid[S_IDW-1:0]), // Templated
.s_axi_bresp (m_axi_bresp[1:0]), // Templated
.s_axi_bvalid (m_axi_bvalid), // Templated
.s_axi_rid (m_axi_rid[S_IDW-1:0]), // Templated
.s_axi_rdata (m_axi_rdata[31:0]), // Templated
.s_axi_rlast (m_axi_rlast), // Templated
.s_axi_rresp (m_axi_rresp[1:0]), // Templated
.s_axi_rvalid (m_axi_rvalid), // Templated
.s_axi_wready (m_axi_wready), // Templated
// Inputs
.sys_nreset (nreset), // Templated
.sys_clk (clk1), // Templated
.rxi_lclk_p (txo_lclk_p), // Templated
.rxi_lclk_n (txo_lclk_n), // Templated
.rxi_frame_p (txo_frame_p), // Templated
.rxi_frame_n (txo_frame_n), // Templated
.rxi_data_p (txo_data_p[7:0]), // Templated
.rxi_data_n (txo_data_n[7:0]), // Templated
.txi_wr_wait_p (rxo_wr_wait_p), // Templated
.txi_wr_wait_n (rxo_wr_wait_n), // Templated
.txi_rd_wait_p (rxo_rd_wait_p), // Templated
.txi_rd_wait_n (rxo_rd_wait_n), // Templated
.m_axi_aresetn (nreset), // Templated
.m_axi_awready (mem_m_axi_awready), // Templated
.m_axi_wready (mem_m_axi_wready), // Templated
.m_axi_bid (mem_m_axi_bid[M_IDW-1:0]), // Templated
.m_axi_bresp (mem_m_axi_bresp[1:0]), // Templated
.m_axi_bvalid (mem_m_axi_bvalid), // Templated
.m_axi_arready (mem_m_axi_arready), // Templated
.m_axi_rid (mem_m_axi_rid[M_IDW-1:0]), // Templated
.m_axi_rresp (mem_m_axi_rresp[1:0]), // Templated
.m_axi_rlast (mem_m_axi_rlast), // Templated
.m_axi_rvalid (mem_m_axi_rvalid), // Templated
.s_axi_aresetn (nreset), // Templated
.s_axi_arid (m_axi_arid[S_IDW-1:0]), // Templated
.s_axi_araddr (m_axi_araddr[31:0]), // Templated
.s_axi_arburst (m_axi_arburst[1:0]), // Templated
.s_axi_arcache (m_axi_arcache[3:0]), // Templated
.s_axi_arlock (m_axi_arlock), // Templated
.s_axi_arlen (m_axi_arlen[7:0]), // Templated
.s_axi_arprot (m_axi_arprot[2:0]), // Templated
.s_axi_arqos (m_axi_arqos[3:0]), // Templated
.s_axi_arsize (m_axi_arsize[2:0]), // Templated
.s_axi_arvalid (m_axi_arvalid), // Templated
.s_axi_awid (m_axi_awid[S_IDW-1:0]), // Templated
.s_axi_awaddr (m_axi_awaddr[31:0]), // Templated
.s_axi_awburst (m_axi_awburst[1:0]), // Templated
.s_axi_awcache (m_axi_awcache[3:0]), // Templated
.s_axi_awlock (m_axi_awlock), // Templated
.s_axi_awlen (m_axi_awlen[7:0]), // Templated
.s_axi_awprot (m_axi_awprot[2:0]), // Templated
.s_axi_awqos (m_axi_awqos[3:0]), // Templated
.s_axi_awsize (m_axi_awsize[2:0]), // Templated
.s_axi_awvalid (m_axi_awvalid), // Templated
.s_axi_bready (m_axi_bready), // Templated
.s_axi_rready (m_axi_rready), // Templated
.s_axi_wid (m_axi_wid[S_IDW-1:0]), // Templated
.s_axi_wdata (m_axi_wdata[31:0]), // Templated
.s_axi_wlast (m_axi_wlast), // Templated
.s_axi_wvalid (m_axi_wvalid)); // Templated
//######################################################################
//AXI SLAVE
//######################################################################
/*esaxi AUTO_TEMPLATE (//Stimulus
.s_\(.*\) (mem_m_\1[]),
.\(.*\) (mem_\1[]),
);
*/
esaxi #(.S_IDW(S_IDW), .RETURN_ADDR(RETURN_ADDR))
esaxi (.s_axi_aclk (clk),
.s_axi_aresetn (nreset),
.s_axi_wstrb (mem_m_axi_wstrb[7:4] | mem_m_axi_wstrb[3:0]),
/*AUTOINST*/
// Outputs
.wr_access (mem_wr_access), // Templated
.wr_packet (mem_wr_packet[PW-1:0]), // Templated
.rd_access (mem_rd_access), // Templated
.rd_packet (mem_rd_packet[PW-1:0]), // Templated
.rr_wait (mem_rr_wait), // Templated
.s_axi_arready (mem_m_axi_arready), // Templated
.s_axi_awready (mem_m_axi_awready), // Templated
.s_axi_bid (mem_m_axi_bid[S_IDW-1:0]), // Templated
.s_axi_bresp (mem_m_axi_bresp[1:0]), // Templated
.s_axi_bvalid (mem_m_axi_bvalid), // Templated
.s_axi_rid (mem_m_axi_rid[S_IDW-1:0]), // Templated
.s_axi_rdata (mem_m_axi_rdata[31:0]), // Templated
.s_axi_rlast (mem_m_axi_rlast), // Templated
.s_axi_rresp (mem_m_axi_rresp[1:0]), // Templated
.s_axi_rvalid (mem_m_axi_rvalid), // Templated
.s_axi_wready (mem_m_axi_wready), // Templated
// Inputs
.wr_wait (mem_wr_wait), // Templated
.rd_wait (mem_rd_wait), // Templated
.rr_access (mem_rr_access), // Templated
.rr_packet (mem_rr_packet[PW-1:0]), // Templated
.s_axi_arid (mem_m_axi_arid[S_IDW-1:0]), // Templated
.s_axi_araddr (mem_m_axi_araddr[31:0]), // Templated
.s_axi_arburst (mem_m_axi_arburst[1:0]), // Templated
.s_axi_arcache (mem_m_axi_arcache[3:0]), // Templated
.s_axi_arlock (mem_m_axi_arlock), // Templated
.s_axi_arlen (mem_m_axi_arlen[7:0]), // Templated
.s_axi_arprot (mem_m_axi_arprot[2:0]), // Templated
.s_axi_arqos (mem_m_axi_arqos[3:0]), // Templated
.s_axi_arsize (mem_m_axi_arsize[2:0]), // Templated
.s_axi_arvalid (mem_m_axi_arvalid), // Templated
.s_axi_awid (mem_m_axi_awid[S_IDW-1:0]), // Templated
.s_axi_awaddr (mem_m_axi_awaddr[31:0]), // Templated
.s_axi_awburst (mem_m_axi_awburst[1:0]), // Templated
.s_axi_awcache (mem_m_axi_awcache[3:0]), // Templated
.s_axi_awlock (mem_m_axi_awlock), // Templated
.s_axi_awlen (mem_m_axi_awlen[7:0]), // Templated
.s_axi_awprot (mem_m_axi_awprot[2:0]), // Templated
.s_axi_awqos (mem_m_axi_awqos[3:0]), // Templated
.s_axi_awsize (mem_m_axi_awsize[2:0]), // Templated
.s_axi_awvalid (mem_m_axi_awvalid), // Templated
.s_axi_bready (mem_m_axi_bready), // Templated
.s_axi_rready (mem_m_axi_rready), // Templated
.s_axi_wid (mem_m_axi_wid[S_IDW-1:0]), // Templated
.s_axi_wdata (mem_m_axi_wdata[31:0]), // Templated
.s_axi_wlast (mem_m_axi_wlast), // Templated
.s_axi_wvalid (mem_m_axi_wvalid)); // Templated
//######################################################################
// MEMORY PORT
//######################################################################
//"Arbitration" between read/write transaction
assign mem_access = mem_wr_access | mem_rd_access;
assign mem_packet[PW-1:0] = mem_wr_access ? mem_wr_packet[PW-1:0]:
mem_rd_packet[PW-1:0];
assign mem_rd_wait = (emem_wait & mem_rd_access) |
mem_wr_access;
assign mem_wr_wait = (emem_wait & mem_wr_access);
/*ememory AUTO_TEMPLATE (
// Outputsd
.\(.*\)_out (mem_rr_\1[]),
.\(.*\)_in (mem_\1[]),
.wait_out (mem_wait),
);
*/
ememory #(.WAIT(0),
.MON(1))
ememory (.wait_in (mem_rr_wait),//pushback on reads
.clk (clk1),
.wait_out (emem_wait),
.coreid (12'h0),
/*AUTOINST*/
// Outputs
.access_out (mem_rr_access), // Templated
.packet_out (mem_rr_packet[PW-1:0]), // Templated
// Inputs
.nreset (nreset),
.access_in (mem_access), // Templated
.packet_in (mem_packet[PW-1:0])); // Templated
endmodule // dv_elink
// Local Variables:
// verilog-library-directories:("." "../hdl" "../../emesh/dv" "../../axi/dv" "../../emesh/hdl" "../../memory/hdl" "../../axi/hdl")
// End:
|
/**
# XorShift128Plus #
Implements the xorshift128+ algorithm. Requires a 128-bit seed value, after
which it runs normally.
This algorithm requires 7 cycles to complete. If read is left asserted
constantly, and data is clocked out when randomReady is high, the maximum data
rate of this module is Clock Frequency / 7.
Note: This module is *NOT* cryptographically secure. It merely acts as a very
fast source of pseudo-random numbers.
## Algorithm ##
```
uint64_t state0 = 1;
uint64_t state1 = 2;
uint64_t xorshift128plus() {
uint64_t s1 = state0;
uint64_t s0 = state1;
state0 = s0;
s1 ^= s1 << 23;
s1 ^= s1 >> 17;
s1 ^= s0;
s1 ^= s0 >> 26;
state1 = s1;
return s1 + s0;
}
```
*/
module XorShift128Plus (
input clk,
input rst,
input [127:0] seed,
input seedStrobe,
input read,
output reg randomReady,
output reg [63:0] randomValue
);
localparam ST_IDLE = 0;
localparam ST_SEED = 1;
localparam ST_SWAP = 2;
localparam ST_XOR_SHIFT_23 = 3;
localparam ST_XOR_S0 = 4;
localparam ST_XOR_SHIFT_17 = 5;
localparam ST_XOR_S0_SHIFT_26 = 6;
reg [2:0] state;
reg [63:0] s0;
reg [63:0] s1;
reg [63:0] xorWord;
initial begin
randomReady = 1'b0;
randomValue = 64'd0;
state = ST_IDLE;
s0 = 64'd1;
s1 = 64'd2;
xorWord = 64'd0;
end
always @(posedge clk) begin
if (rst) begin
randomReady <= 1'b0;
randomValue <= 64'd0;
state <= ST_IDLE;
s0 <= 64'd1;
s1 <= 64'd2;
xorWord <= 64'd0;
end
else begin
// State machine (3 bit state, 3 inputs, so 6-LUT)
case (state)
ST_IDLE : begin
if (seedStrobe && randomReady) begin
state <= ST_SEED;
end
else if (read && randomReady) begin
state <= ST_SWAP;
end
else begin
state <= ST_IDLE;
end
end
ST_SEED : state <= ST_SWAP;
ST_SWAP : state <= ST_XOR_SHIFT_23;
ST_XOR_SHIFT_23 : state <= ST_XOR_S0;
ST_XOR_S0 : state <= ST_XOR_SHIFT_17;
ST_XOR_SHIFT_17 : state <= ST_XOR_S0_SHIFT_26;
ST_XOR_S0_SHIFT_26 : state <= ST_IDLE;
default : state <= ST_IDLE;
endcase
// Output is calculated on IDLE, when randomReady goes high
if (state == ST_IDLE) begin
randomValue <= s0 + s1;
randomReady <= ~randomReady | (~read & ~seedStrobe); // Ready until strobe occurs; make sure it asserts at least once
end
else begin
randomValue <= randomValue;
randomReady <= 1'b0;
end
// s0 only updates when seeded or during the swap operation
if (state == ST_SEED || state == ST_SWAP) begin
s0 <= (state == ST_SWAP) ? s1 : seed[63:0];
end
// s1 is either swapped, XOR'd, or seeded
case (state)
ST_IDLE : s1 <= s1;
ST_SEED : s1 <= seed[127:64];
ST_SWAP : s1 <= s0;
default : s1 <= s1 ^ xorWord;
endcase
// Get Word to use in the NEXT state
case (state)
ST_IDLE : xorWord <= s0;
ST_SEED : xorWord <= s0;
ST_SWAP : xorWord <= s0 << 23; // s0 because the swap hasn't occured when this is calculated
ST_XOR_SHIFT_23 : xorWord <= s0;
ST_XOR_S0 : xorWord <= s1 >> 17;
ST_XOR_SHIFT_17 : xorWord <= s0 >> 26;
ST_XOR_S0_SHIFT_26 : xorWord <= s0;
default : xorWord <= s0;
endcase
end
end
endmodule
|
/********************************************/
/* soc_tb.v */
/* DE1 skeleton testbench */
/* */
/* */
/* 2012, [email protected] */
/********************************************/
//`default_nettype none
`timescale 1ns/1ps
module soc_tb();
////////////////////////////////////////
// defines //
////////////////////////////////////////
`define SOC_SIM
`define HP_24 20.833
`define HP_27 18.519
`define HP_50 10.000
`define HP_EXT 5.000
`define VGA_MON_CLK CLOCK_50
`define VGA_MON_OA 1'b0
`define VGA_MON_F_CNT 'd0
`define VGA_MON_F_STA 1'b0
////////////////////////////////////////
// internal signals //
////////////////////////////////////////
//// system ////
reg RST;
reg ERR;
reg [ 32-1:0] datr;
//// soc ////
// clock inputs
reg [ 2-1:0] CLOCK_24; // 24 MHz
reg [ 2-1:0] CLOCK_27; // 27 MHz
reg CLOCK_50; // 50 MHz
reg CLOCK_EXT; // External Clock
// USB JTAG Link
reg TDI; // CPLD -> FPGA (data in)
reg TCK; // CPLD -> FPGA (clk)
reg TCS; // CPLD -> FPGA (CS)
wire TDO; // FPGA -> CPLD (data out)
// GPIO
tri [36-1:0] GPIO_0; // GPIO Connection 0
tri [36-1:0] GPIO_1; // GPIO Connection 1
// push button inputs
wire [ 4-1:0] BTN; // Pushbutton[3:0]
// switch inputs
wire [10-1:0] SW; // Toggle Switch[9:0]
// 7-seg display outputs
wire [ 7-1:0] HEX_0; // Seven Segment Digit 0
wire [ 7-1:0] HEX_1; // Seven Segment Digit 1
wire [ 7-1:0] HEX_2; // Seven Segment Digit 2
wire [ 7-1:0] HEX_3; // Seven Segment Digit 3
// LED outputs
wire [ 8-1:0] LED_G; // LED Green[7:0]
wire [10-1:0] LED_R; // LED Red[9:0]
// UART
wire UART_TXD; // UART Transmitter
reg UART_RXD; // UART Receiver
// I2C
tri I2C_SDAT; // I2C Data
wire I2C_SCLK; // I2C Clock
// PS2
tri PS2_DAT; // PS2 Data
tri PS2_CLK; // PS2 Clock
// VGA
wire VGA_HS; // VGA H_SYNC
wire VGA_VS; // VGA V_SYNC
wire [ 4-1:0] VGA_R; // VGA Red[3:0]
wire [ 4-1:0] VGA_G; // VGA Green[3:0]
wire [ 4-1:0] VGA_B; // VGA Blue[3:0]
// Audio CODEC
tri AUD_ADCLRCK; // Audio CODEC ADC LR Clock
reg AUD_ADCDAT; // Audio CODEC ADC Data
tri AUD_DACLRCK; // Audio CODEC DAC LR Clock
wire AUD_DACDAT; // Audio CODEC DAC Data
tri AUD_BCLK; // Audio CODEC Bit-Stream Clock
wire AUD_XCK; // Audio CODEC Chip Clock
// SD Card
wire SD_DAT; // SD Card Data
wire SD_DAT3; // SD Card Data 3
wire SD_CMD; // SD Card Command Signal
wire SD_CLK; // SD Card Clock
// SRAM
tri [16-1:0] SRAM_DQ; // SRAM Data bus 16 Bits
wire [18-1:0] SRAM_ADDR; // SRAM Address bus 18 Bits
wire SRAM_UB_N; // SRAM High-byte Data Mask
wire SRAM_LB_N; // SRAM Low-byte Data Mask
wire SRAM_WE_N; // SRAM Write Enable
wire SRAM_CE_N; // SRAM Chip Enable
wire SRAM_OE_N; // SRAM Output Enable
// SDRAM
tri [16-1:0] DRAM_DQ; // SDRAM Data bus 16 Bits
wire [12-1:0] DRAM_ADDR; // SDRAM Address bus 12 Bits
wire DRAM_LDQM; // SDRAM Low-byte Data Mask
wire DRAM_UDQM; // SDRAM High-byte Data Mask
wire DRAM_WE_N; // SDRAM Write Enable
wire DRAM_CAS_N; // SDRAM Column Address Strobe
wire DRAM_RAS_N; // SDRAM Row Address Strobe
wire DRAM_CS_N; // SDRAM Chip Select
wire DRAM_BA_0; // SDRAM Bank Address 0
wire DRAM_BA_1; // SDRAM Bank Address 1
wire DRAM_CLK; // SDRAM Clock
wire DRAM_CKE; // SDRAM Clock Enable
// FLASH
tri [ 8-1:0] FL_DQ; // FLASH Data bus 8 Bits
wire [22-1:0] FL_ADDR; // FLASH Address bus 22 Bits
wire FL_WE_N; // FLASH Write Enable
wire FL_RST_N; // FLASH Reset
wire FL_OE_N; // FLASH Output Enable
wire FL_CE_N; // FLASH Chip Enable
////////////////////////////////////////
// bench //
////////////////////////////////////////
//// clocks & async reset ////
initial begin
CLOCK_24 = 1'b1;
#2;
forever #`HP_24 CLOCK_24 = ~CLOCK_24;
end
initial begin
CLOCK_27 = 1'b1;
#3;
forever #`HP_27 CLOCK_27 = ~CLOCK_27;
end
initial begin
CLOCK_50 = 1'b1;
#5;
forever #`HP_50 CLOCK_50 = ~CLOCK_50;
end
initial begin
CLOCK_EXT = 1'b1;
#7;
forever #`HP_EXT CLOCK_EXT = ~CLOCK_EXT;
end
initial begin
RST = 1'b1;
#101;
RST = 1'b0;
end
initial begin
ERR = 1'b0;
end
//// set all inputs at initial time ////
initial begin
TDI = 0;
TCK = 0;
TCS = 0;
UART_RXD = 0;
AUD_ADCDAT = 0;
// SD_DAT = 0;
end
//// bench ////
initial begin
$display("BENCH : %t : soc test starting ...", $time);
// wait for reset
#5;
wait(!RST);
repeat (10) @ (posedge CLOCK_50);
#1;
// disable ctrl CPU
force soc_top.ctrl_top.ctrl_cpu.dcpu_cs = 1'b0;
force soc_top.ctrl_top.ctrl_cpu.icpu_cs = 1'b0;
force soc_top.ctrl_top.ctrl_cpu.dcpu_ack = 1'b0;
force soc_top.ctrl_top.ctrl_cpu.icpu_ack = 1'b0;
// force reset TG68
force soc_top.tg68_rst = 1'b0;
// wait for reset
//while (!soc_top.ctrl_top.rst) @ (posedge soc_top.ctrl_top.clk); #1;
wait (!soc_top.ctrl_top.ctrl_regs.rst);
// force unreset minimig
force soc_top.minimig.reset = 1'b0;
force soc_top.tg68_rst = 1'b1;
repeat(10) @ (posedge soc_top.clk_7);
force soc_top.tg68_rst = 1'b0;
repeat(10) @ (posedge soc_top.clk_7);
// try qmem bridge
ctrl_bridge_cycle(32'h00180000, 1'b1, 4'hf, 32'h01234567);
ctrl_bridge_cycle(32'h00180000, 1'b1, 4'hf, 32'hdeadbeef);
repeat(10) @ (posedge soc_top.ctrl_top.clk);
// write to OSD SPI slave
// enable OSD (SPI chip select)
ctrl_regs_cycle(32'h00800020, 1'b1, 4'hf, 32'h00000044);
// send write command
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h0000001c);
// send address
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h00000000);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h00000000);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h00000000);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h00000000);
// send data
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h000000aa);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h000000bb);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h000000cc);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h000000dd);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h000000ee);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h000000ff);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h00000001);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h00000023);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h00000045);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h00000067);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h00000089);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h000000ab);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h000000cd);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h000000ef);
repeat (10) @ (posedge soc_top.ctrl_top.clk);
// disable OSD (SPI chip select)
ctrl_regs_cycle(32'h00800020, 1'b1, 4'hf, 32'h00000040);
repeat (10) @ (posedge soc_top.ctrl_top.clk);
// write to OSD SPI slave
// enable OSD (SPI chip select)
ctrl_regs_cycle(32'h00800020, 1'b1, 4'hf, 32'h00000044);
// send write command
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h0000001c);
// send address
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h00000080);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h000000f0);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h000000df);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h00000000);
// send data
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h000000aa);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h000000bb);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h000000cc);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h000000dd);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h000000ee);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h000000ff);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h00000001);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h00000023);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h00000045);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h00000067);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h00000089);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h000000ab);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h000000cd);
ctrl_regs_cycle(32'h00800024, 1'b1, 4'hf, 32'h000000ef);
repeat (10) @ (posedge soc_top.ctrl_top.clk);
// readback
ctrl_bridge_cycle(32'h00180000, 1'b0, 4'hf, 32'h00000000, datr);
repeat (100) @ (posedge soc_top.clk_7);
/*
// try a TG68 cycle
force soc_top.tg68_adr = 24'h123456;
force soc_top.tg68_dat_out = 16'hbeef;
force soc_top.tg68_as = 1'b0;
force soc_top.tg68_uds = 1'b0;
force soc_top.tg68_lds = 1'b0;
force soc_top.tg68_rw = 1'b0;
@ (posedge soc_top.clk_7);
while (soc_top.tg68_dtack) @ (posedge soc_top.clk_7); #1;
@ (posedge soc_top.clk_7);
force soc_top.tg68_as = 1'b1;
@ (posedge soc_top.clk_7);
@ (posedge soc_top.clk_7);
force soc_top.tg68_adr = 24'h123456;
force soc_top.tg68_dat_out = 16'hdead;
force soc_top.tg68_as = 1'b0;
force soc_top.tg68_uds = 1'b1;
force soc_top.tg68_lds = 1'b1;
force soc_top.tg68_rw = 1'b1;
@ (posedge soc_top.clk_7);
while (soc_top.tg68_dtack) @ (posedge soc_top.clk_7); #1;
@ (posedge soc_top.clk_7);
force soc_top.tg68_as = 1'b1;
@ (posedge soc_top.clk_7);
@ (posedge soc_top.clk_7);
release soc_top.tg68_adr;
release soc_top.tg68_dat_out;
release soc_top.tg68_as;
release soc_top.tg68_uds;
release soc_top.tg68_lds;
release soc_top.tg68_rw;
repeat (10) @ (posedge soc_top.clk_7);
*/
// start monitor
$display("BENCH : %t : starting vga monitor ...", $time);
//vga_monitor.start;
// set pattern mode 2
// SW9 SW8 SW7 SW6-2 SW1 SW0
//switches.toggle({1'b0, 1'b0, 1'b0, 5'b00000, 1'b1, 1'b0});
// set dither
// SW9 SW8 SW7 SW6-2 SW1 SW0
//switches.toggle({1'b1, 1'b1, 1'b1, 5'b00000, 1'b0, 1'b0});
// wait for three frames
//$display("BENCH : %t : waiting for frames ...", $time);
//wait (`VGA_MON_F_CNT == 7'd3);
#100;
// display result
if (ERR) $display("BENCH : %t : vga_dma test FAILED - there were errors!", $time);
else $display("BENCH : %t : vga_dma test PASSED - no errors!", $time);
$display("BENCH : done.");
$finish;
end
////////////////////////////////////////
// tasks //
////////////////////////////////////////
// force ctrl regs bus
task ctrl_regs_cycle;
input [32-1:0] adr;
input we;
input [ 4-1:0] sel;
input [32-1:0] dat_w;
output [32-1:0] dat_r;
begin
@ (posedge soc_top.ctrl_top.clk); #1;
force soc_top.ctrl_top.ctrl_regs.adr = adr;
force soc_top.ctrl_top.ctrl_regs.cs = 1'b1;
force soc_top.ctrl_top.ctrl_regs.we = we;
force soc_top.ctrl_top.ctrl_regs.sel = sel;
force soc_top.ctrl_top.ctrl_regs.dat_w = dat_w;
@ (posedge soc_top.ctrl_top.clk); #1;
while (!soc_top.ctrl_top.ctrl_regs.ack) @ (posedge soc_top.ctrl_top.clk); #1;
release soc_top.ctrl_top.ctrl_regs.adr;
release soc_top.ctrl_top.ctrl_regs.cs;
release soc_top.ctrl_top.ctrl_regs.we;
release soc_top.ctrl_top.ctrl_regs.sel;
release soc_top.ctrl_top.ctrl_regs.dat_w;
@ (posedge soc_top.ctrl_top.clk); #1;
dat_r = soc_top.ctrl_top.ctrl_regs.dat_r;
end
endtask
// force ctrl bridge cycle
task ctrl_bridge_cycle;
input [32-1:0] adr;
input we;
input [ 4-1:0] sel;
input [32-1:0] dat_w;
output [32-1:0] dat_r;
begin
@ (posedge soc_top.ctrl_top.clk); #1;
force soc_top.ctrl_top.dram_adr = adr;
force soc_top.ctrl_top.dram_cs = 1'b1;
force soc_top.ctrl_top.dram_we = we;
force soc_top.ctrl_top.dram_sel = sel;
force soc_top.ctrl_top.dram_dat_w = dat_w;
@ (posedge soc_top.ctrl_top.clk); #1;
while (!soc_top.ctrl_top.dram_ack) @ (posedge soc_top.ctrl_top.clk); #1;
release soc_top.ctrl_top.dram_adr;
release soc_top.ctrl_top.dram_cs;
release soc_top.ctrl_top.dram_we;
release soc_top.ctrl_top.dram_sel;
release soc_top.ctrl_top.dram_dat_w;
@ (posedge soc_top.ctrl_top.clk); #1;
dat_r = soc_top.ctrl_top.dram_dat_r;
end
endtask
////////////////////////////////////////
// soc top module //
////////////////////////////////////////
minimig_de1_top soc_top (
.CLOCK_24 (CLOCK_24 ), // 24 MHz
.CLOCK_27 (CLOCK_27 ), // 27 MHz
.CLOCK_50 (CLOCK_50 ), // 50 MHz
.EXT_CLOCK (CLOCK_EXT ), // External Clock
.TDI (TDI ), // CPLD -> FPGA (data in)
.TCK (TCK ), // CPLD -> FPGA (clk)
.TCS (TCS ), // CPLD -> FPGA (CS)
.TDO (TDO ), // FPGA -> CPLD (data out)
//.GPIO_0 (GPIO_0 ), // GPIO Connection 0
//.GPIO_1 (GPIO_1 ), // GPIO Connection 1
.KEY (BTN ), // Pushbutton[3:0]
.SW (SW ), // Toggle Switch[9:0]
.HEX0 (HEX_0 ), // Seven Segment Digit 0
.HEX1 (HEX_1 ), // Seven Segment Digit 1
.HEX2 (HEX_2 ), // Seven Segment Digit 2
.HEX3 (HEX_3 ), // Seven Segment Digit 3
.LEDG (LED_G ), // LED Green[7:0]
.LEDR (LED_R ), // LED Red[9:0]
.UART_TXD (UART_TXD ), // UART Transmitter
.UART_RXD (UART_RXD ), // UART Receiver
.I2C_SDAT (I2C_SDAT ), // I2C Data
.I2C_SCLK (I2C_SCLK ), // I2C Clock
.PS2_DAT (PS2_DAT ), // PS2 Data
.PS2_CLK (PS2_CLK ), // PS2 Clock
.VGA_HS (VGA_HS ), // VGA H_SYNC
.VGA_VS (VGA_VS ), // VGA V_SYNC
.VGA_R (VGA_R ), // VGA Red[3:0]
.VGA_G (VGA_G ), // VGA Green[3:0]
.VGA_B (VGA_B ), // VGA Blue[3:0]
.AUD_ADCLRCK (AUD_ADCLRCK), // Audio CODEC ADC LR Clock
.AUD_ADCDAT (AUD_ADCDAT ), // Audio CODEC ADC Data
.AUD_DACLRCK (AUD_DACLRCK), // Audio CODEC DAC LR Clock
.AUD_DACDAT (AUD_DACDAT ), // Audio CODEC DAC Data
.AUD_BCLK (AUD_BCLK ), // Audio CODEC Bit-Stream Clock
.AUD_XCK (AUD_XCK ), // Audio CODEC Chip Clock
.SD_DAT (SD_DAT ), // SD Card Data - spi MISO
.SD_DAT3 (SD_DAT3 ), // SD Card Data 3 - spi CS
.SD_CMD (SD_CMD ), // SD Card Command Signal - spi MOSI
.SD_CLK (SD_CLK ), // SD Card Clock - spi CLK
.SRAM_DQ (SRAM_DQ ), // SRAM Data bus 16 Bits
.SRAM_ADDR (SRAM_ADDR ), // SRAM Address bus 18 Bits
.SRAM_UB_N (SRAM_UB_N ), // SRAM High-byte Data Mask
.SRAM_LB_N (SRAM_LB_N ), // SRAM Low-byte Data Mask
.SRAM_WE_N (SRAM_WE_N ), // SRAM Write Enable
.SRAM_CE_N (SRAM_CE_N ), // SRAM Chip Enable
.SRAM_OE_N (SRAM_OE_N ), // SRAM Output Enable
.DRAM_DQ (DRAM_DQ ), // SDRAM Data bus 16 Bits
.DRAM_ADDR (DRAM_ADDR ), // SDRAM Address bus 12 Bits
.DRAM_LDQM (DRAM_LDQM ), // SDRAM Low-byte Data Mask
.DRAM_UDQM (DRAM_UDQM ), // SDRAM High-byte Data Mask
.DRAM_WE_N (DRAM_WE_N ), // SDRAM Write Enable
.DRAM_CAS_N (DRAM_CAS_N ), // SDRAM Column Address Strobe
.DRAM_RAS_N (DRAM_RAS_N ), // SDRAM Row Address Strobe
.DRAM_CS_N (DRAM_CS_N ), // SDRAM Chip Select
.DRAM_BA_0 (DRAM_BA_0 ), // SDRAM Bank Address 0
.DRAM_BA_1 (DRAM_BA_1 ), // SDRAM Bank Address 1
.DRAM_CLK (DRAM_CLK ), // SDRAM Clock
.DRAM_CKE (DRAM_CKE ), // SDRAM Clock Enable
.FL_DQ (FL_DQ ), // FLASH Data bus 8 Bits
.FL_ADDR (FL_ADDR ), // FLASH Address bus 22 Bits
.FL_WE_N (FL_WE_N ), // FLASH Write Enable
.FL_RST_N (FL_RST_N ), // FLASH Reset
.FL_OE_N (FL_OE_N ), // FLASH Output Enable
.FL_CE_N (FL_CE_N ) // FLASH Chip Enable
);
////////////////////////////////////////
// input / output models //
////////////////////////////////////////
//// buttons ////
generic_input #(
.IW (4), // input width
.PD (10), // push delay
.DS (1'b1), // default state
.DBG (1) // debug output
) buttons (
.o (BTN)
);
//// switches ////
generic_input #(
.IW (10), // input width
.PD (10), // push delay
.DS (1'b1), // default state
.DBG (1) // debug output
) switches (
.o (SW)
);
//// LEDs ////
//// GPIOs ////
/*
//// vga_monitor ////
vga_monitor #(
.VGA (1), // SVGA or VGA mode
.IRW (4), // input red width
.IGW (4), // input green width
.IBW (4), // input blue width
.ODW (8), // output width
.DLY (2), // output delay
.COR ("RGB"), // color order (RGB or BGR)
.FNW (32), // filename string width
.FEX ("hex"), // filename extension
.FILE ("../out/hex/frame") // filename (without extension!)
) vga_monitor (
// system
.clk (`VGA_MON_CLK), // clock
// status
.oa (`VGA_MON_OA), // vga output active
.f_cnt (`VGA_MON_F_CNT), // frame counter (resets for every second)
.f_start (`VGA_MON_F_STA), // frame start
// vga data
.r_in (VGA_R), // red data
.g_in (VGA_G), // green data
.b_in (VGA_B) // blue data
);
*/
//// SRAM model ////
IS61LV6416L #(
.memdepth (262144),
.addbits (18)
) sram (
.A (SRAM_ADDR),
.IO (SRAM_DQ),
.CE_ (SRAM_CE_N),
.OE_ (SRAM_OE_N),
.WE_ (SRAM_WE_N),
.LB_ (SRAM_LB_N),
.UB_ (SRAM_UB_N)
);
//// SDRAM model ////
mt48lc16m16a2 #(
.tAC (5.4),
.tHZ (5.4),
.tOH (2.5),
.tMRD (2.0), // 2 Clk Cycles
.tRAS (40.0),
.tRC (58.0),
.tRCD (18.0),
.tRFC (60.0),
.tRP (18.0),
.tRRD (12.0),
.tWRa (7.0), // A2 Version - Auto precharge mode (1 Clk + 7 ns)
.tWRm (14.0) // A2 Version - Manual precharge mode (14 ns)
) sdram (
.Dq (DRAM_DQ),
.Addr (DRAM_ADDR),
.Ba ({DRAM_BA_1, DRAM_BA_0}),
.Clk (DRAM_CLK),
.Cke (DRAM_CKE),
.Cs_n (DRAM_CS_N),
.Ras_n (DRAM_RAS_N),
.Cas_n (DRAM_CAS_N),
.We_n (DRAM_WE_N),
.Dqm ({DRAM_UDQM, DRAM_LDQM})
);
//// SDCARD model ////
sd_card #(
.FNAME ("../../../../sd32MBNP.img")
) sdcard (
.sck (SD_CLK ),
.ss (SD_DAT3 ),
.mosi (SD_CMD ),
.miso (SD_DAT )
);
/* flash model */
endmodule
|
//altdq_dqs CBX_SINGLE_OUTPUT_FILE="ON" DELAY_BUFFER_MODE="HIGH" DELAY_DQS_ENABLE_BY_HALF_CYCLE="TRUE" device_family="arriaii" DQ_HALF_RATE_USE_DATAOUTBYPASS="FALSE" DQ_INPUT_REG_ASYNC_MODE="NONE" DQ_INPUT_REG_CLK_SOURCE="INVERTED_DQS_BUS" DQ_INPUT_REG_MODE="DDIO" DQ_INPUT_REG_POWER_UP="HIGH" DQ_INPUT_REG_SYNC_MODE="NONE" DQ_INPUT_REG_USE_CLKN="FALSE" DQ_IPA_ADD_INPUT_CYCLE_DELAY="FALSE" DQ_IPA_ADD_PHASE_TRANSFER_REG="FALSE" DQ_IPA_BYPASS_OUTPUT_REGISTER="FALSE" DQ_IPA_INVERT_PHASE="FALSE" DQ_IPA_PHASE_SETTING=0 DQ_OE_REG_ASYNC_MODE="NONE" DQ_OE_REG_MODE="FF" DQ_OE_REG_POWER_UP="LOW" DQ_OE_REG_SYNC_MODE="NONE" DQ_OUTPUT_REG_ASYNC_MODE="CLEAR" DQ_OUTPUT_REG_MODE="DDIO" DQ_OUTPUT_REG_POWER_UP="LOW" DQ_OUTPUT_REG_SYNC_MODE="NONE" DQS_CTRL_LATCHES_ENABLE="FALSE" DQS_DELAY_CHAIN_DELAYCTRLIN_SOURCE="DLL" DQS_DELAY_CHAIN_PHASE_SETTING=2 DQS_DQSN_MODE="DIFFERENTIAL" DQS_ENABLE_CTRL_ADD_PHASE_TRANSFER_REG="FALSE" DQS_ENABLE_CTRL_INVERT_PHASE="FALSE" DQS_ENABLE_CTRL_PHASE_SETTING=0 DQS_INPUT_FREQUENCY="300.0 MHz" DQS_OE_REG_ASYNC_MODE="NONE" DQS_OE_REG_MODE="FF" DQS_OE_REG_POWER_UP="LOW" DQS_OE_REG_SYNC_MODE="NONE" DQS_OFFSETCTRL_ENABLE="FALSE" DQS_OUTPUT_REG_ASYNC_MODE="NONE" DQS_OUTPUT_REG_MODE="DDIO" DQS_OUTPUT_REG_POWER_UP="LOW" DQS_OUTPUT_REG_SYNC_MODE="NONE" DQS_PHASE_SHIFT=7200 IO_CLOCK_DIVIDER_CLK_SOURCE="CORE" IO_CLOCK_DIVIDER_INVERT_PHASE="FALSE" IO_CLOCK_DIVIDER_PHASE_SETTING=0 LEVEL_DQS_ENABLE="FALSE" NUMBER_OF_BIDIR_DQ=8 NUMBER_OF_CLK_DIVIDER=0 NUMBER_OF_INPUT_DQ=0 NUMBER_OF_OUTPUT_DQ=1 OCT_REG_MODE="NONE" USE_DQ_INPUT_DELAY_CHAIN="FALSE" USE_DQ_IPA="FALSE" USE_DQ_IPA_PHASECTRLIN="FALSE" USE_DQ_OE_DELAY_CHAIN1="FALSE" USE_DQ_OE_DELAY_CHAIN2="FALSE" USE_DQ_OE_PATH="TRUE" USE_DQ_OUTPUT_DELAY_CHAIN1="FALSE" USE_DQ_OUTPUT_DELAY_CHAIN2="FALSE" USE_DQS="TRUE" USE_DQS_DELAY_CHAIN="TRUE" USE_DQS_DELAY_CHAIN_PHASECTRLIN="FALSE" USE_DQS_ENABLE="TRUE" USE_DQS_ENABLE_CTRL="TRUE" USE_DQS_ENABLE_CTRL_PHASECTRLIN="FALSE" USE_DQS_INPUT_DELAY_CHAIN="FALSE" USE_DQS_INPUT_PATH="TRUE" USE_DQS_OE_DELAY_CHAIN1="FALSE" USE_DQS_OE_DELAY_CHAIN2="FALSE" USE_DQS_OE_PATH="TRUE" USE_DQS_OUTPUT_DELAY_CHAIN1="FALSE" USE_DQS_OUTPUT_DELAY_CHAIN2="FALSE" USE_DQS_OUTPUT_PATH="TRUE" USE_DQSBUSOUT_DELAY_CHAIN="FALSE" USE_DQSENABLE_DELAY_CHAIN="FALSE" USE_DYNAMIC_OCT="FALSE" USE_HALF_RATE="FALSE" USE_IO_CLOCK_DIVIDER_MASTERIN="FALSE" USE_IO_CLOCK_DIVIDER_PHASECTRLIN="FALSE" USE_OCT_DELAY_CHAIN1="FALSE" USE_OCT_DELAY_CHAIN2="FALSE" bidir_dq_areset bidir_dq_input_data_in bidir_dq_input_data_out_high bidir_dq_input_data_out_low bidir_dq_oe_in bidir_dq_oe_out bidir_dq_output_data_in_high bidir_dq_output_data_in_low bidir_dq_output_data_out dll_delayctrlin dq_input_reg_clk dq_output_reg_clk dqs_enable_ctrl_clk dqs_enable_ctrl_in dqs_input_data_in dqs_oe_in dqs_oe_out dqs_output_data_in_high dqs_output_data_in_low dqs_output_data_out dqs_output_reg_clk dqsn_oe_in dqsn_oe_out output_dq_oe_in output_dq_oe_out output_dq_output_data_in_high output_dq_output_data_in_low output_dq_output_data_out
//VERSION_BEGIN 10.0SP1 cbx_altdq_dqs 2010:08:18:21:16:35:SJ cbx_mgl 2010:08:18:21:20:44:SJ cbx_stratixiii 2010:08:18:21:16:35:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2010 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = arriaii_ddio_in 8 arriaii_ddio_out 10 arriaii_dqs_delay_chain 1 arriaii_dqs_enable 1 arriaii_dqs_enable_ctrl 1 reg 11
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"-name DQ_GROUP 9 -from dqs_0_delay_chain_inst -to bidir_dq_0_output_ddio_out_inst;-name DQ_GROUP 9 -from dqs_0_delay_chain_inst -to bidir_dq_1_output_ddio_out_inst;-name DQ_GROUP 9 -from dqs_0_delay_chain_inst -to bidir_dq_2_output_ddio_out_inst;-name DQ_GROUP 9 -from dqs_0_delay_chain_inst -to bidir_dq_3_output_ddio_out_inst;-name DQ_GROUP 9 -from dqs_0_delay_chain_inst -to bidir_dq_4_output_ddio_out_inst;-name DQ_GROUP 9 -from dqs_0_delay_chain_inst -to bidir_dq_5_output_ddio_out_inst;-name DQ_GROUP 9 -from dqs_0_delay_chain_inst -to bidir_dq_6_output_ddio_out_inst;-name DQ_GROUP 9 -from dqs_0_delay_chain_inst -to bidir_dq_7_output_ddio_out_inst;-name DQ_GROUP 9 -from dqs_0_delay_chain_inst -to output_dq_0_output_ddio_out_inst"} *)
module ddr3_int_phy_alt_mem_phy_dq_dqs
(
bidir_dq_areset,
bidir_dq_input_data_in,
bidir_dq_input_data_out_high,
bidir_dq_input_data_out_low,
bidir_dq_oe_in,
bidir_dq_oe_out,
bidir_dq_output_data_in_high,
bidir_dq_output_data_in_low,
bidir_dq_output_data_out,
dll_delayctrlin,
dq_input_reg_clk,
dq_output_reg_clk,
dqs_enable_ctrl_clk,
dqs_enable_ctrl_in,
dqs_input_data_in,
dqs_oe_in,
dqs_oe_out,
dqs_output_data_in_high,
dqs_output_data_in_low,
dqs_output_data_out,
dqs_output_reg_clk,
dqsn_oe_in,
dqsn_oe_out,
output_dq_oe_in,
output_dq_oe_out,
output_dq_output_data_in_high,
output_dq_output_data_in_low,
output_dq_output_data_out) /* synthesis synthesis_clearbox=1 */;
input [7:0] bidir_dq_areset;
input [7:0] bidir_dq_input_data_in;
output [7:0] bidir_dq_input_data_out_high;
output [7:0] bidir_dq_input_data_out_low;
input [7:0] bidir_dq_oe_in;
output [7:0] bidir_dq_oe_out;
input [7:0] bidir_dq_output_data_in_high;
input [7:0] bidir_dq_output_data_in_low;
output [7:0] bidir_dq_output_data_out;
input [5:0] dll_delayctrlin;
input dq_input_reg_clk;
input dq_output_reg_clk;
input dqs_enable_ctrl_clk;
input dqs_enable_ctrl_in;
input [0:0] dqs_input_data_in;
input [0:0] dqs_oe_in;
output [0:0] dqs_oe_out;
input [0:0] dqs_output_data_in_high;
input [0:0] dqs_output_data_in_low;
output [0:0] dqs_output_data_out;
input dqs_output_reg_clk;
input [0:0] dqsn_oe_in;
output [0:0] dqsn_oe_out;
input [0:0] output_dq_oe_in;
output [0:0] output_dq_oe_out;
input [0:0] output_dq_output_data_in_high;
input [0:0] output_dq_output_data_in_low;
output [0:0] output_dq_output_data_out;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [7:0] bidir_dq_areset;
tri0 [7:0] bidir_dq_input_data_in;
tri0 [7:0] bidir_dq_oe_in;
tri0 [7:0] bidir_dq_output_data_in_high;
tri0 [7:0] bidir_dq_output_data_in_low;
tri0 [5:0] dll_delayctrlin;
tri0 dq_input_reg_clk;
tri0 dq_output_reg_clk;
tri1 dqs_enable_ctrl_clk;
tri1 dqs_enable_ctrl_in;
tri0 [0:0] dqs_input_data_in;
tri0 [0:0] dqs_oe_in;
tri0 [0:0] dqs_output_data_in_high;
tri0 [0:0] dqs_output_data_in_low;
tri0 dqs_output_reg_clk;
tri0 [0:0] dqsn_oe_in;
tri0 [0:0] output_dq_oe_in;
tri0 [0:0] output_dq_output_data_in_high;
tri0 [0:0] output_dq_output_data_in_low;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
(* ALTERA_ATTRIBUTE = {"FAST_OUTPUT_ENABLE_REGISTER=ON"} *)
reg bidir_dq_0_oe_ff_inst;
(* ALTERA_ATTRIBUTE = {"FAST_OUTPUT_ENABLE_REGISTER=ON"} *)
reg bidir_dq_1_oe_ff_inst;
(* ALTERA_ATTRIBUTE = {"FAST_OUTPUT_ENABLE_REGISTER=ON"} *)
reg bidir_dq_2_oe_ff_inst;
(* ALTERA_ATTRIBUTE = {"FAST_OUTPUT_ENABLE_REGISTER=ON"} *)
reg bidir_dq_3_oe_ff_inst;
(* ALTERA_ATTRIBUTE = {"FAST_OUTPUT_ENABLE_REGISTER=ON"} *)
reg bidir_dq_4_oe_ff_inst;
(* ALTERA_ATTRIBUTE = {"FAST_OUTPUT_ENABLE_REGISTER=ON"} *)
reg bidir_dq_5_oe_ff_inst;
(* ALTERA_ATTRIBUTE = {"FAST_OUTPUT_ENABLE_REGISTER=ON"} *)
reg bidir_dq_6_oe_ff_inst;
(* ALTERA_ATTRIBUTE = {"FAST_OUTPUT_ENABLE_REGISTER=ON"} *)
reg bidir_dq_7_oe_ff_inst;
(* ALTERA_ATTRIBUTE = {"FAST_OUTPUT_ENABLE_REGISTER=ON"} *)
reg dqs_0_oe_ff_inst;
(* ALTERA_ATTRIBUTE = {"FAST_OUTPUT_ENABLE_REGISTER=ON"} *)
reg dqsn_0_oe_ff_inst;
(* ALTERA_ATTRIBUTE = {"FAST_OUTPUT_ENABLE_REGISTER=ON"} *)
reg output_dq_0_oe_ff_inst;
wire wire_bidir_dq_0_ddio_in_inst_regouthi;
wire wire_bidir_dq_0_ddio_in_inst_regoutlo;
wire wire_bidir_dq_1_ddio_in_inst_regouthi;
wire wire_bidir_dq_1_ddio_in_inst_regoutlo;
wire wire_bidir_dq_2_ddio_in_inst_regouthi;
wire wire_bidir_dq_2_ddio_in_inst_regoutlo;
wire wire_bidir_dq_3_ddio_in_inst_regouthi;
wire wire_bidir_dq_3_ddio_in_inst_regoutlo;
wire wire_bidir_dq_4_ddio_in_inst_regouthi;
wire wire_bidir_dq_4_ddio_in_inst_regoutlo;
wire wire_bidir_dq_5_ddio_in_inst_regouthi;
wire wire_bidir_dq_5_ddio_in_inst_regoutlo;
wire wire_bidir_dq_6_ddio_in_inst_regouthi;
wire wire_bidir_dq_6_ddio_in_inst_regoutlo;
wire wire_bidir_dq_7_ddio_in_inst_regouthi;
wire wire_bidir_dq_7_ddio_in_inst_regoutlo;
wire wire_bidir_dq_0_output_ddio_out_inst_dataout;
wire wire_bidir_dq_1_output_ddio_out_inst_dataout;
wire wire_bidir_dq_2_output_ddio_out_inst_dataout;
wire wire_bidir_dq_3_output_ddio_out_inst_dataout;
wire wire_bidir_dq_4_output_ddio_out_inst_dataout;
wire wire_bidir_dq_5_output_ddio_out_inst_dataout;
wire wire_bidir_dq_6_output_ddio_out_inst_dataout;
wire wire_bidir_dq_7_output_ddio_out_inst_dataout;
wire wire_dqs_0_output_ddio_out_inst_dataout;
wire wire_output_dq_0_output_ddio_out_inst_dataout;
wire wire_dqs_0_delay_chain_inst_dqsbusout;
wire wire_dqs_0_enable_inst_dqsbusout;
wire wire_dqs_0_enable_ctrl_inst_dqsenableout;
wire [0:0] dqs_bus_wire;
// synopsys translate_off
initial
bidir_dq_0_oe_ff_inst = 0;
// synopsys translate_on
always @ ( posedge dq_output_reg_clk)
bidir_dq_0_oe_ff_inst <= (~ bidir_dq_oe_in[0]);
// synopsys translate_off
initial
bidir_dq_1_oe_ff_inst = 0;
// synopsys translate_on
always @ ( posedge dq_output_reg_clk)
bidir_dq_1_oe_ff_inst <= (~ bidir_dq_oe_in[1]);
// synopsys translate_off
initial
bidir_dq_2_oe_ff_inst = 0;
// synopsys translate_on
always @ ( posedge dq_output_reg_clk)
bidir_dq_2_oe_ff_inst <= (~ bidir_dq_oe_in[2]);
// synopsys translate_off
initial
bidir_dq_3_oe_ff_inst = 0;
// synopsys translate_on
always @ ( posedge dq_output_reg_clk)
bidir_dq_3_oe_ff_inst <= (~ bidir_dq_oe_in[3]);
// synopsys translate_off
initial
bidir_dq_4_oe_ff_inst = 0;
// synopsys translate_on
always @ ( posedge dq_output_reg_clk)
bidir_dq_4_oe_ff_inst <= (~ bidir_dq_oe_in[4]);
// synopsys translate_off
initial
bidir_dq_5_oe_ff_inst = 0;
// synopsys translate_on
always @ ( posedge dq_output_reg_clk)
bidir_dq_5_oe_ff_inst <= (~ bidir_dq_oe_in[5]);
// synopsys translate_off
initial
bidir_dq_6_oe_ff_inst = 0;
// synopsys translate_on
always @ ( posedge dq_output_reg_clk)
bidir_dq_6_oe_ff_inst <= (~ bidir_dq_oe_in[6]);
// synopsys translate_off
initial
bidir_dq_7_oe_ff_inst = 0;
// synopsys translate_on
always @ ( posedge dq_output_reg_clk)
bidir_dq_7_oe_ff_inst <= (~ bidir_dq_oe_in[7]);
// synopsys translate_off
initial
dqs_0_oe_ff_inst = 0;
// synopsys translate_on
always @ ( posedge dqs_output_reg_clk)
dqs_0_oe_ff_inst <= (~ dqs_oe_in[0]);
// synopsys translate_off
initial
dqsn_0_oe_ff_inst = 0;
// synopsys translate_on
always @ ( posedge dqs_output_reg_clk)
dqsn_0_oe_ff_inst <= (~ dqsn_oe_in[0]);
// synopsys translate_off
initial
output_dq_0_oe_ff_inst = 0;
// synopsys translate_on
always @ ( posedge dq_output_reg_clk)
output_dq_0_oe_ff_inst <= (~ output_dq_oe_in[0]);
arriaii_ddio_in bidir_dq_0_ddio_in_inst
(
.clk((~ dqs_bus_wire[0])),
.datain(bidir_dq_input_data_in[0]),
.regouthi(wire_bidir_dq_0_ddio_in_inst_regouthi),
.regoutlo(wire_bidir_dq_0_ddio_in_inst_regoutlo)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkn(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_0_ddio_in_inst.async_mode = "none",
bidir_dq_0_ddio_in_inst.sync_mode = "none",
bidir_dq_0_ddio_in_inst.use_clkn = "false",
bidir_dq_0_ddio_in_inst.lpm_type = "arriaii_ddio_in";
arriaii_ddio_in bidir_dq_1_ddio_in_inst
(
.clk((~ dqs_bus_wire[0])),
.datain(bidir_dq_input_data_in[1]),
.regouthi(wire_bidir_dq_1_ddio_in_inst_regouthi),
.regoutlo(wire_bidir_dq_1_ddio_in_inst_regoutlo)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkn(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_1_ddio_in_inst.async_mode = "none",
bidir_dq_1_ddio_in_inst.sync_mode = "none",
bidir_dq_1_ddio_in_inst.use_clkn = "false",
bidir_dq_1_ddio_in_inst.lpm_type = "arriaii_ddio_in";
arriaii_ddio_in bidir_dq_2_ddio_in_inst
(
.clk((~ dqs_bus_wire[0])),
.datain(bidir_dq_input_data_in[2]),
.regouthi(wire_bidir_dq_2_ddio_in_inst_regouthi),
.regoutlo(wire_bidir_dq_2_ddio_in_inst_regoutlo)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkn(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_2_ddio_in_inst.async_mode = "none",
bidir_dq_2_ddio_in_inst.sync_mode = "none",
bidir_dq_2_ddio_in_inst.use_clkn = "false",
bidir_dq_2_ddio_in_inst.lpm_type = "arriaii_ddio_in";
arriaii_ddio_in bidir_dq_3_ddio_in_inst
(
.clk((~ dqs_bus_wire[0])),
.datain(bidir_dq_input_data_in[3]),
.regouthi(wire_bidir_dq_3_ddio_in_inst_regouthi),
.regoutlo(wire_bidir_dq_3_ddio_in_inst_regoutlo)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkn(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_3_ddio_in_inst.async_mode = "none",
bidir_dq_3_ddio_in_inst.sync_mode = "none",
bidir_dq_3_ddio_in_inst.use_clkn = "false",
bidir_dq_3_ddio_in_inst.lpm_type = "arriaii_ddio_in";
arriaii_ddio_in bidir_dq_4_ddio_in_inst
(
.clk((~ dqs_bus_wire[0])),
.datain(bidir_dq_input_data_in[4]),
.regouthi(wire_bidir_dq_4_ddio_in_inst_regouthi),
.regoutlo(wire_bidir_dq_4_ddio_in_inst_regoutlo)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkn(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_4_ddio_in_inst.async_mode = "none",
bidir_dq_4_ddio_in_inst.sync_mode = "none",
bidir_dq_4_ddio_in_inst.use_clkn = "false",
bidir_dq_4_ddio_in_inst.lpm_type = "arriaii_ddio_in";
arriaii_ddio_in bidir_dq_5_ddio_in_inst
(
.clk((~ dqs_bus_wire[0])),
.datain(bidir_dq_input_data_in[5]),
.regouthi(wire_bidir_dq_5_ddio_in_inst_regouthi),
.regoutlo(wire_bidir_dq_5_ddio_in_inst_regoutlo)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkn(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_5_ddio_in_inst.async_mode = "none",
bidir_dq_5_ddio_in_inst.sync_mode = "none",
bidir_dq_5_ddio_in_inst.use_clkn = "false",
bidir_dq_5_ddio_in_inst.lpm_type = "arriaii_ddio_in";
arriaii_ddio_in bidir_dq_6_ddio_in_inst
(
.clk((~ dqs_bus_wire[0])),
.datain(bidir_dq_input_data_in[6]),
.regouthi(wire_bidir_dq_6_ddio_in_inst_regouthi),
.regoutlo(wire_bidir_dq_6_ddio_in_inst_regoutlo)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkn(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_6_ddio_in_inst.async_mode = "none",
bidir_dq_6_ddio_in_inst.sync_mode = "none",
bidir_dq_6_ddio_in_inst.use_clkn = "false",
bidir_dq_6_ddio_in_inst.lpm_type = "arriaii_ddio_in";
arriaii_ddio_in bidir_dq_7_ddio_in_inst
(
.clk((~ dqs_bus_wire[0])),
.datain(bidir_dq_input_data_in[7]),
.regouthi(wire_bidir_dq_7_ddio_in_inst_regouthi),
.regoutlo(wire_bidir_dq_7_ddio_in_inst_regoutlo)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkn(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_7_ddio_in_inst.async_mode = "none",
bidir_dq_7_ddio_in_inst.sync_mode = "none",
bidir_dq_7_ddio_in_inst.use_clkn = "false",
bidir_dq_7_ddio_in_inst.lpm_type = "arriaii_ddio_in";
arriaii_ddio_out bidir_dq_0_output_ddio_out_inst
(
.areset(bidir_dq_areset[0]),
.clkhi(dq_output_reg_clk),
.clklo(dq_output_reg_clk),
.datainhi(bidir_dq_output_data_in_high[0]),
.datainlo(bidir_dq_output_data_in_low[0]),
.dataout(wire_bidir_dq_0_output_ddio_out_inst_dataout),
.muxsel(dq_output_reg_clk)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dffhi(),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_0_output_ddio_out_inst.async_mode = "clear",
bidir_dq_0_output_ddio_out_inst.half_rate_mode = "false",
bidir_dq_0_output_ddio_out_inst.power_up = "low",
bidir_dq_0_output_ddio_out_inst.sync_mode = "none",
bidir_dq_0_output_ddio_out_inst.use_new_clocking_model = "true",
bidir_dq_0_output_ddio_out_inst.lpm_type = "arriaii_ddio_out";
arriaii_ddio_out bidir_dq_1_output_ddio_out_inst
(
.areset(bidir_dq_areset[1]),
.clkhi(dq_output_reg_clk),
.clklo(dq_output_reg_clk),
.datainhi(bidir_dq_output_data_in_high[1]),
.datainlo(bidir_dq_output_data_in_low[1]),
.dataout(wire_bidir_dq_1_output_ddio_out_inst_dataout),
.muxsel(dq_output_reg_clk)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dffhi(),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_1_output_ddio_out_inst.async_mode = "clear",
bidir_dq_1_output_ddio_out_inst.half_rate_mode = "false",
bidir_dq_1_output_ddio_out_inst.power_up = "low",
bidir_dq_1_output_ddio_out_inst.sync_mode = "none",
bidir_dq_1_output_ddio_out_inst.use_new_clocking_model = "true",
bidir_dq_1_output_ddio_out_inst.lpm_type = "arriaii_ddio_out";
arriaii_ddio_out bidir_dq_2_output_ddio_out_inst
(
.areset(bidir_dq_areset[2]),
.clkhi(dq_output_reg_clk),
.clklo(dq_output_reg_clk),
.datainhi(bidir_dq_output_data_in_high[2]),
.datainlo(bidir_dq_output_data_in_low[2]),
.dataout(wire_bidir_dq_2_output_ddio_out_inst_dataout),
.muxsel(dq_output_reg_clk)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dffhi(),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_2_output_ddio_out_inst.async_mode = "clear",
bidir_dq_2_output_ddio_out_inst.half_rate_mode = "false",
bidir_dq_2_output_ddio_out_inst.power_up = "low",
bidir_dq_2_output_ddio_out_inst.sync_mode = "none",
bidir_dq_2_output_ddio_out_inst.use_new_clocking_model = "true",
bidir_dq_2_output_ddio_out_inst.lpm_type = "arriaii_ddio_out";
arriaii_ddio_out bidir_dq_3_output_ddio_out_inst
(
.areset(bidir_dq_areset[3]),
.clkhi(dq_output_reg_clk),
.clklo(dq_output_reg_clk),
.datainhi(bidir_dq_output_data_in_high[3]),
.datainlo(bidir_dq_output_data_in_low[3]),
.dataout(wire_bidir_dq_3_output_ddio_out_inst_dataout),
.muxsel(dq_output_reg_clk)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dffhi(),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_3_output_ddio_out_inst.async_mode = "clear",
bidir_dq_3_output_ddio_out_inst.half_rate_mode = "false",
bidir_dq_3_output_ddio_out_inst.power_up = "low",
bidir_dq_3_output_ddio_out_inst.sync_mode = "none",
bidir_dq_3_output_ddio_out_inst.use_new_clocking_model = "true",
bidir_dq_3_output_ddio_out_inst.lpm_type = "arriaii_ddio_out";
arriaii_ddio_out bidir_dq_4_output_ddio_out_inst
(
.areset(bidir_dq_areset[4]),
.clkhi(dq_output_reg_clk),
.clklo(dq_output_reg_clk),
.datainhi(bidir_dq_output_data_in_high[4]),
.datainlo(bidir_dq_output_data_in_low[4]),
.dataout(wire_bidir_dq_4_output_ddio_out_inst_dataout),
.muxsel(dq_output_reg_clk)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dffhi(),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_4_output_ddio_out_inst.async_mode = "clear",
bidir_dq_4_output_ddio_out_inst.half_rate_mode = "false",
bidir_dq_4_output_ddio_out_inst.power_up = "low",
bidir_dq_4_output_ddio_out_inst.sync_mode = "none",
bidir_dq_4_output_ddio_out_inst.use_new_clocking_model = "true",
bidir_dq_4_output_ddio_out_inst.lpm_type = "arriaii_ddio_out";
arriaii_ddio_out bidir_dq_5_output_ddio_out_inst
(
.areset(bidir_dq_areset[5]),
.clkhi(dq_output_reg_clk),
.clklo(dq_output_reg_clk),
.datainhi(bidir_dq_output_data_in_high[5]),
.datainlo(bidir_dq_output_data_in_low[5]),
.dataout(wire_bidir_dq_5_output_ddio_out_inst_dataout),
.muxsel(dq_output_reg_clk)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dffhi(),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_5_output_ddio_out_inst.async_mode = "clear",
bidir_dq_5_output_ddio_out_inst.half_rate_mode = "false",
bidir_dq_5_output_ddio_out_inst.power_up = "low",
bidir_dq_5_output_ddio_out_inst.sync_mode = "none",
bidir_dq_5_output_ddio_out_inst.use_new_clocking_model = "true",
bidir_dq_5_output_ddio_out_inst.lpm_type = "arriaii_ddio_out";
arriaii_ddio_out bidir_dq_6_output_ddio_out_inst
(
.areset(bidir_dq_areset[6]),
.clkhi(dq_output_reg_clk),
.clklo(dq_output_reg_clk),
.datainhi(bidir_dq_output_data_in_high[6]),
.datainlo(bidir_dq_output_data_in_low[6]),
.dataout(wire_bidir_dq_6_output_ddio_out_inst_dataout),
.muxsel(dq_output_reg_clk)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dffhi(),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_6_output_ddio_out_inst.async_mode = "clear",
bidir_dq_6_output_ddio_out_inst.half_rate_mode = "false",
bidir_dq_6_output_ddio_out_inst.power_up = "low",
bidir_dq_6_output_ddio_out_inst.sync_mode = "none",
bidir_dq_6_output_ddio_out_inst.use_new_clocking_model = "true",
bidir_dq_6_output_ddio_out_inst.lpm_type = "arriaii_ddio_out";
arriaii_ddio_out bidir_dq_7_output_ddio_out_inst
(
.areset(bidir_dq_areset[7]),
.clkhi(dq_output_reg_clk),
.clklo(dq_output_reg_clk),
.datainhi(bidir_dq_output_data_in_high[7]),
.datainlo(bidir_dq_output_data_in_low[7]),
.dataout(wire_bidir_dq_7_output_ddio_out_inst_dataout),
.muxsel(dq_output_reg_clk)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dffhi(),
.dfflo()
// synopsys translate_on
);
defparam
bidir_dq_7_output_ddio_out_inst.async_mode = "clear",
bidir_dq_7_output_ddio_out_inst.half_rate_mode = "false",
bidir_dq_7_output_ddio_out_inst.power_up = "low",
bidir_dq_7_output_ddio_out_inst.sync_mode = "none",
bidir_dq_7_output_ddio_out_inst.use_new_clocking_model = "true",
bidir_dq_7_output_ddio_out_inst.lpm_type = "arriaii_ddio_out";
arriaii_ddio_out dqs_0_output_ddio_out_inst
(
.clkhi(dqs_output_reg_clk),
.clklo(dqs_output_reg_clk),
.datainhi(dqs_output_data_in_high[0]),
.datainlo(dqs_output_data_in_low[0]),
.dataout(wire_dqs_0_output_ddio_out_inst_dataout),
.muxsel(dqs_output_reg_clk)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clk(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dffhi(),
.dfflo()
// synopsys translate_on
);
defparam
dqs_0_output_ddio_out_inst.async_mode = "none",
dqs_0_output_ddio_out_inst.half_rate_mode = "false",
dqs_0_output_ddio_out_inst.sync_mode = "none",
dqs_0_output_ddio_out_inst.use_new_clocking_model = "true",
dqs_0_output_ddio_out_inst.lpm_type = "arriaii_ddio_out";
arriaii_ddio_out output_dq_0_output_ddio_out_inst
(
.clkhi(dq_output_reg_clk),
.clklo(dq_output_reg_clk),
.datainhi(output_dq_output_data_in_high[0]),
.datainlo(output_dq_output_data_in_low[0]),
.dataout(wire_output_dq_0_output_ddio_out_inst_dataout),
.muxsel(dq_output_reg_clk)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clk(1'b0),
.ena(1'b1),
.sreset(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1),
.dffhi(),
.dfflo()
// synopsys translate_on
);
defparam
output_dq_0_output_ddio_out_inst.async_mode = "clear",
output_dq_0_output_ddio_out_inst.half_rate_mode = "false",
output_dq_0_output_ddio_out_inst.sync_mode = "none",
output_dq_0_output_ddio_out_inst.use_new_clocking_model = "true",
output_dq_0_output_ddio_out_inst.lpm_type = "arriaii_ddio_out";
arriaii_dqs_delay_chain dqs_0_delay_chain_inst
(
.delayctrlin(dll_delayctrlin),
.dqsbusout(wire_dqs_0_delay_chain_inst_dqsbusout),
.dqsin(dqs_input_data_in[0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dqsupdateen(1'b0),
.offsetctrlin({6{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
dqs_0_delay_chain_inst.delay_buffer_mode = "high",
dqs_0_delay_chain_inst.dqs_ctrl_latches_enable = "false",
dqs_0_delay_chain_inst.dqs_input_frequency = "300.0 MHz",
dqs_0_delay_chain_inst.dqs_offsetctrl_enable = "false",
dqs_0_delay_chain_inst.dqs_phase_shift = 7200,
dqs_0_delay_chain_inst.phase_setting = 2,
dqs_0_delay_chain_inst.lpm_type = "arriaii_dqs_delay_chain";
arriaii_dqs_enable dqs_0_enable_inst
(
.dqsbusout(wire_dqs_0_enable_inst_dqsbusout),
.dqsenable(wire_dqs_0_enable_ctrl_inst_dqsenableout),
.dqsin(wire_dqs_0_delay_chain_inst_dqsbusout)
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
arriaii_dqs_enable_ctrl dqs_0_enable_ctrl_inst
(
.clk(dqs_enable_ctrl_clk),
.dqsenablein(dqs_enable_ctrl_in),
.dqsenableout(wire_dqs_0_enable_ctrl_inst_dqsenableout)
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
dqs_0_enable_ctrl_inst.delay_dqs_enable_by_half_cycle = "true",
dqs_0_enable_ctrl_inst.lpm_type = "arriaii_dqs_enable_ctrl";
assign
bidir_dq_input_data_out_high = {wire_bidir_dq_7_ddio_in_inst_regouthi, wire_bidir_dq_6_ddio_in_inst_regouthi, wire_bidir_dq_5_ddio_in_inst_regouthi, wire_bidir_dq_4_ddio_in_inst_regouthi, wire_bidir_dq_3_ddio_in_inst_regouthi, wire_bidir_dq_2_ddio_in_inst_regouthi, wire_bidir_dq_1_ddio_in_inst_regouthi, wire_bidir_dq_0_ddio_in_inst_regouthi},
bidir_dq_input_data_out_low = {wire_bidir_dq_7_ddio_in_inst_regoutlo, wire_bidir_dq_6_ddio_in_inst_regoutlo, wire_bidir_dq_5_ddio_in_inst_regoutlo, wire_bidir_dq_4_ddio_in_inst_regoutlo, wire_bidir_dq_3_ddio_in_inst_regoutlo, wire_bidir_dq_2_ddio_in_inst_regoutlo, wire_bidir_dq_1_ddio_in_inst_regoutlo, wire_bidir_dq_0_ddio_in_inst_regoutlo},
bidir_dq_oe_out = {(~ bidir_dq_7_oe_ff_inst), (~ bidir_dq_6_oe_ff_inst), (~ bidir_dq_5_oe_ff_inst), (~ bidir_dq_4_oe_ff_inst), (~ bidir_dq_3_oe_ff_inst), (~ bidir_dq_2_oe_ff_inst), (~ bidir_dq_1_oe_ff_inst), (~ bidir_dq_0_oe_ff_inst)},
bidir_dq_output_data_out = {wire_bidir_dq_7_output_ddio_out_inst_dataout, wire_bidir_dq_6_output_ddio_out_inst_dataout, wire_bidir_dq_5_output_ddio_out_inst_dataout, wire_bidir_dq_4_output_ddio_out_inst_dataout, wire_bidir_dq_3_output_ddio_out_inst_dataout, wire_bidir_dq_2_output_ddio_out_inst_dataout, wire_bidir_dq_1_output_ddio_out_inst_dataout, wire_bidir_dq_0_output_ddio_out_inst_dataout},
dqs_bus_wire = {wire_dqs_0_enable_inst_dqsbusout},
dqs_oe_out = {(~ dqs_0_oe_ff_inst)},
dqs_output_data_out = {wire_dqs_0_output_ddio_out_inst_dataout},
dqsn_oe_out = {(~ dqsn_0_oe_ff_inst)},
output_dq_oe_out = {(~ output_dq_0_oe_ff_inst)},
output_dq_output_data_out = {wire_output_dq_0_output_ddio_out_inst_dataout};
endmodule //ddr3_int_phy_alt_mem_phy_dq_dqs
//VALID FILE
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module converts resamples the chroma components of a video in *
* stream, whos colour space is YCrCb. *
* *
******************************************************************************/
module Computer_System_Video_In_Subsystem_Edge_Detection_Subsystem_Chroma_Filter (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IDW = 23; // Incoming frame's data width
parameter ODW = 7; // Outcoming frame's data width
parameter IEW = 1; // Incoming frame's empty width
parameter OEW = 0; // Outcoming frame's empty width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IDW:0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [IEW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [ODW:0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [OEW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire transfer_data;
wire [ODW:0] converted_data;
wire converted_startofpacket;
wire converted_endofpacket;
wire [OEW:0] converted_empty;
wire converted_valid;
// Internal Registers
reg [IDW:0] data;
reg startofpacket;
reg endofpacket;
reg [IEW:0] empty;
reg valid;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'h0;
stream_out_valid <= 1'b0;
end
else if (transfer_data)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= converted_startofpacket;
stream_out_endofpacket <= converted_endofpacket;
stream_out_empty <= converted_empty;
stream_out_valid <= converted_valid;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
else if (stream_in_ready)
begin
data <= stream_in_data;
startofpacket <= stream_in_startofpacket;
endofpacket <= stream_in_endofpacket;
empty <= stream_in_empty;
valid <= stream_in_valid;
end
else if (transfer_data)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_in_valid & (~valid | transfer_data);
// Internal Assignments
assign transfer_data =
~stream_out_valid | (stream_out_ready & stream_out_valid);
assign converted_data[ 7: 0] = data[ 7: 0];
assign converted_startofpacket = startofpacket;
assign converted_endofpacket = endofpacket;
assign converted_empty = empty;
assign converted_valid = valid;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
logic in1 = 1;
logic [1:0] in2 = 2'b11;
logic [31:0] out;
logic [7:0] ones = 8'b11111111;
logic [9:0] ones10 = 10'b1111111111;
typedef logic [7:0] data_t;
typedef logic [9:0] ten_t;
ten_t out10;
// verilator lint_off WIDTH
initial begin
in1 = 1;
in2 = 0;
out = data_t'(in1 << in2);
if (out != 8'b1) $stop;
in2 = 1;
out = data_t'(in1 << in2);
if (out != 8'b10) $stop;
in2 = 2;
out = data_t'(in1 << in2);
if (out != 8'b100) $stop;
in2 = 3;
out = data_t'(in1 << in2);
if (out != 8'b1000) $stop;
// Check upper bits get cleared when cast
in2 = 3;
out = data_t'(ones << in2);
if (out != 8'b11111000) $stop;
in2 = 3;
out = data_t'(ones10 << in2);
if (out != 8'b11111000) $stop;
// bug2597
out = data_t'(10'h208 >> 2);
if (out != 8'h82) $stop;
out = data_t'(10'h208 >> 2);
if (out != 8'h82) $stop;
out = data_t'('h208 >> 2);
if (out != 8'h82) $stop;
out10 = ten_t'('h404 >> 2);
if (out10 != 10'h101) $stop;
$write("*-* All Finished *-*\n");
$finish();
end
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*
*
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the Viterbi decoder
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
//`include "bmu.v"
module bmutb;
// Modify the number of bits in the ouput bus to be 2
wire [1:0] bm0, bm1, bm2, bm3, bm4, bm5, bm6, bm7;
reg cx0, cx1;
bmu bmu1 (cx0, cx1, bm0, bm1, bm2, bm3, bm4, bm5, bm6, bm7);
initial
begin
cx0=0; cx1=0;
#10;
cx0=0; cx1=1;
#10;
cx0=1; cx1=0;
#10;
cx0=1; cx1=1;
#10;
cx0=0; cx1=0;
#10;
end
initial
begin
$shm_open("bmu.shm");
$shm_probe("AC");
end
endmodule
|
module IDELAYE2 (/*AUTOARG*/
// Outputs
CNTVALUEOUT, DATAOUT,
// Inputs
C, CE, CINVCTRL, CNTVALUEIN, DATAIN, IDATAIN, INC, LD, LDPIPEEN,
REGRST
);
parameter CINVCTRL_SEL = "FALSE"; // Enable dynamic clock inversion
parameter DELAY_SRC = "IDATAIN"; // Delay input
parameter HIGH_PERFORMANCE_MODE = "FALSE"; // Reduced jitter
parameter IDELAY_TYPE = "FIXED"; // Type of delay line
parameter integer IDELAY_VALUE = 0; // Input delay tap setting
parameter [0:0] IS_C_INVERTED = 1'b0; //
parameter [0:0] IS_DATAIN_INVERTED = 1'b0; //
parameter [0:0] IS_IDATAIN_INVERTED = 1'b0; //
parameter PIPE_SEL = "FALSE"; // Select pipelined mode
parameter real REFCLK_FREQUENCY = 200.0; // Ref clock frequency
parameter SIGNAL_PATTERN = "DATA"; // Input signal type
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
parameter integer SIM_DELAY_D = 0;
localparam DELAY_D = (IDELAY_TYPE == "VARIABLE") ? SIM_DELAY_D : 0;
`endif // ifdef XIL_TIMING
`ifndef XIL_TIMING
integer DELAY_D=0;
`endif // ifndef XIL_TIMING
output [4:0] CNTVALUEOUT; // count value for monitoring tap value
output DATAOUT; // delayed data
input C; // clock input for variable mode
input CE; // enable increment/decrement function
input CINVCTRL; // dynamically inverts clock polarity
input [4:0] CNTVALUEIN; // counter value for tap delay
input DATAIN; // data input from FGPA logic
input IDATAIN; // data input from IBUF
input INC; // increment tap delay
input LD; // loads the delay primitive
input LDPIPEEN; // enables the pipeline register delay
input REGRST; // reset for pipeline register
assign DATAOUT = IDATAIN;
initial
begin
//$display("Delay %d %m",IDELAY_VALUE);
end
reg [4:0] idelay_reg=5'b0;
always @ (posedge C)
if(LD)
begin
idelay_reg[4:0] <= CNTVALUEIN[4:0];
$display("Delay %d",idelay_reg[4:0]);
end
endmodule // IDELAYE2
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (
input wire CLK,
output reg RESET
);
neg neg (.clk(CLK));
little little (.clk(CLK));
glbl glbl ();
// A vector
logic [2:1] vec [4:3];
integer val = 0;
always @ (posedge CLK) begin
if (RESET) val <= 0;
else val <= val + 1;
vec[3] <= val[1:0];
vec[4] <= val[3:2];
end
initial RESET = 1'b1;
always @ (posedge CLK)
RESET <= glbl.GSR;
endmodule
module glbl();
`ifdef PUB_FUNC
reg GSR;
task setGSR;
`ifdef ATTRIBUTES
/* verilator public */
`endif
input value;
GSR = value;
endtask
`else
`ifdef ATTRIBUTES
reg GSR /*verilator public*/;
`else
reg GSR;
`endif
`endif
endmodule
module neg (
input clk
);
reg [0:-7] i8; initial i8 = '0;
reg [-1:-48] i48; initial i48 = '0;
reg [63:-64] i128; initial i128 = '0;
always @ (posedge clk) begin
i8 <= ~i8;
i48 <= ~i48;
i128 <= ~i128;
end
endmodule
module little (
input clk
);
// verilator lint_off LITENDIAN
reg [0:7] i8; initial i8 = '0;
reg [1:49] i48; initial i48 = '0;
reg [63:190] i128; initial i128 = '0;
// verilator lint_on LITENDIAN
always @ (posedge clk) begin
i8 <= ~i8;
i48 <= ~i48;
i128 <= ~i128;
end
endmodule
|
`timescale 1ns/10ps
`include "pipeconnect.h"
/*
Notation:
_ low, 0
~ high, 1
/ posedge
\ negedge
. unknown,undetermined,unimportant
# valid data (held stable)
< changing
> --
*/
/*
Fasttarget presents the request address as the result data after one
cycle. Wait is never asserted.
WISHBONE - no wait states
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ####><#### A2 ####>.........................
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_________________________
wait _____________________________________________________________
readdata _____________<#### D1 ####><#### D2 ####>____________________
PIPECONNECT - no wait states
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ####><#### A2 ####>.........................
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_________________________
wait _____________________________________________________________
readdata ___________________________<#### D1 ####><#### D2 ####>______
PIPECONNECT - some wait states
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ##################><#### A2 ####>.........................
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_______________________________________
wait _____________/~~~~~~~~~~~~\________________________________________________
readdata _________________________________________<#### D1 ####><#### D2 ####>______
*/
module fasttarget // PIPECONNECT, no wait
(input wire clk,
input wire rst,
input wire `REQ req,
output reg `RES res);
always @(posedge clk) begin
res`WAIT <= 0;
res`RD <= ~rst && req`R ? req`A : 0;
end
endmodule
/*
PIPECONNECT - 1 wait state
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ##################><#### A2 ##################>...........
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\/~~~~~~~~~~~~~~~~~~~~~~~~~~\___________
wait _____________/~~~~~~~~~~~~\______________/~~~~~~~~~~~~\____________________
readdata _________________________________________<#### D1 ####>______________<#### D2 ####>______
_~_~_~_~_~_
.AAAABBBB..
_~~~~~~~~__
_~~__~~____
_____aa__bb
*/
module slowtarget // PIPECONNECT, 1 wait
(input wire clk,
input wire rst,
input wire `REQ req,
output wire `RES res);
reg [31:0] readData;
reg ready;
assign res`RD = readData;
assign res`WAIT = req`R & ~ready;
always @(posedge clk)
if (rst) begin
readData <= 0;
ready <= 0;
//$display("target in reset");
end else begin
readData <= ready ? req`A : 0;
ready <= req`R & ~ready;
//$display("target %d %d", ready, res`WAIT);
end
endmodule
/*
Simple master waits for a result before issuing new request
PIPECONNECT - no wait states
Request noticed by target
| Response captured by initiator
v v
clock /~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ...<#####req 1###>...........................<#####req 2
read ___/~~~~~~~~~~~~~\___________________________/~~~~~~~~~~
wait ________________________________________________________
readdata ______________________<#############>___________________
*/
/*
Streaming master keeps one outstanding command
PIPECONNECT - no wait states
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#####req 1###>.............<#####req 2
read ________/~~~~~~~~~~~~~\___________________________/~~~~~~~~~~
wait _____________________________________________________________
readdata ___________________________<#############>___________________
*/
module initiator
(input wire clk,
input wire rst,
output reg `REQ req,
input wire `RES res);
reg [31:0] counter;
reg [31:0] dataExpect;
reg dataValid;
parameter name = 1;
always @(posedge clk)
if (rst) begin
counter <= 0;
req <= 0;
dataValid <= 0;
dataExpect <= 0;
end else begin
dataValid <= req`R & ~res`WAIT;
if (dataValid) begin
if (dataExpect != res`RD)
$display("%6d init%d got %x !!! BAD!", $time, name, res`RD);
else
$display("%6d init%d got %x as expected", $time, name, res`RD);
end
if (~res`WAIT) begin
req`R <= 1;
req`A <= counter;
dataExpect <= req`A;
counter <= counter + 1;
$display("%6d init%d requests %x", $time, name, counter);
end
end
endmodule
module main();
reg rst, clk;
wire `REQ req;
wire `RES res;
wire [31:0] addr = req`A;
wire read = req`R;
wire wai = res`WAIT;
wire [31:0] data = res`RD;
initiator initiator1(clk, rst, req1, res1);
initiator initiator2(clk, rst, req2, res2);
mux2 mux_init(clk, req1, res1, req2, res2, req, res);
slowtarget target(clk, rst, req, res);
always # 5 clk = ~clk;
initial begin
$monitor("%d%d %4d %x %d %d %x", rst, clk, $time, addr, read, wai, data);
clk = 1;
rst = 1;
#15 rst = 0;
#200 $finish;
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
`include "def_nvme.vh"
module pcie_cntl_reg # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
output rx_np_ok,
output rx_np_req,
output mreq_fifo_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] mreq_fifo_rd_data,
input mreq_fifo_empty_n,
output tx_cpld_req,
output [7:0] tx_cpld_tag,
output [15:0] tx_cpld_req_id,
output [11:2] tx_cpld_len,
output [11:0] tx_cpld_bc,
output [6:0] tx_cpld_laddr,
output [63:0] tx_cpld_data,
input tx_cpld_req_ack,
output nvme_cc_en,
output [1:0] nvme_cc_shn,
input [1:0] nvme_csts_shst,
input nvme_csts_rdy,
output nvme_intms_ivms,
output nvme_intmc_ivmc,
input cq_irq_status,
input [8:0] sq_rst_n,
input [8:0] cq_rst_n,
output [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] admin_cq_bs_addr,
output [7:0] admin_sq_size,
output [7:0] admin_cq_size,
output [7:0] admin_sq_tail_ptr,
output [7:0] io_sq1_tail_ptr,
output [7:0] io_sq2_tail_ptr,
output [7:0] io_sq3_tail_ptr,
output [7:0] io_sq4_tail_ptr,
output [7:0] io_sq5_tail_ptr,
output [7:0] io_sq6_tail_ptr,
output [7:0] io_sq7_tail_ptr,
output [7:0] io_sq8_tail_ptr,
output [7:0] admin_cq_head_ptr,
output [7:0] io_cq1_head_ptr,
output [7:0] io_cq2_head_ptr,
output [7:0] io_cq3_head_ptr,
output [7:0] io_cq4_head_ptr,
output [7:0] io_cq5_head_ptr,
output [7:0] io_cq6_head_ptr,
output [7:0] io_cq7_head_ptr,
output [7:0] io_cq8_head_ptr,
output [8:0] cq_head_update
);
localparam S_IDLE = 9'b000000001;
localparam S_PCIE_RD_HEAD = 9'b000000010;
localparam S_PCIE_ADDR = 9'b000000100;
localparam S_PCIE_WAIT_WR_DATA = 9'b000001000;
localparam S_PCIE_WR_DATA = 9'b000010000;
localparam S_PCIE_MWR = 9'b000100000;
localparam S_PCIE_MRD = 9'b001000000;
localparam S_PCIE_CPLD_REQ = 9'b010000000;
localparam S_PCIE_CPLD_ACK = 9'b100000000;
reg [8:0] cur_state;
reg [8:0] next_state;
reg r_intms_ivms;
reg r_intmc_ivmc;
reg r_cq_irq_status;
reg [23:20] r_cc_iocqes;
reg [19:16] r_cc_iosqes;
reg [15:14] r_cc_shn;
reg [13:11] r_cc_asm;
reg [10:7] r_cc_mps;
reg [6:4] r_cc_ccs;
reg [0:0] r_cc_en;
reg [23:16] r_aqa_acqs;
reg [7:0] r_aqa_asqs;
reg [C_PCIE_ADDR_WIDTH-1:2] r_asq_asqb;
reg [C_PCIE_ADDR_WIDTH-1:2] r_acq_acqb;
reg [7:0] r_reg_sq0tdbl;
reg [7:0] r_reg_sq1tdbl;
reg [7:0] r_reg_sq2tdbl;
reg [7:0] r_reg_sq3tdbl;
reg [7:0] r_reg_sq4tdbl;
reg [7:0] r_reg_sq5tdbl;
reg [7:0] r_reg_sq6tdbl;
reg [7:0] r_reg_sq7tdbl;
reg [7:0] r_reg_sq8tdbl;
reg [7:0] r_reg_cq0hdbl;
reg [7:0] r_reg_cq1hdbl;
reg [7:0] r_reg_cq2hdbl;
reg [7:0] r_reg_cq3hdbl;
reg [7:0] r_reg_cq4hdbl;
reg [7:0] r_reg_cq5hdbl;
reg [7:0] r_reg_cq6hdbl;
reg [7:0] r_reg_cq7hdbl;
reg [7:0] r_reg_cq8hdbl;
reg [8:0] r_cq_head_update;
wire [31:0] w_pcie_head0;
wire [31:0] w_pcie_head1;
wire [31:0] w_pcie_head2;
wire [31:0] w_pcie_head3;
reg [31:0] r_pcie_head2;
reg [31:0] r_pcie_head3;
wire [2:0] w_mreq_head_fmt;
//wire [4:0] w_mreq_head_type;
//wire [2:0] w_mreq_head_tc;
//wire w_mreq_head_attr1;
//wire w_mreq_head_th;
//wire w_mreq_head_td;
//wire w_mreq_head_ep;
//wire [1:0] w_mreq_head_attr0;
//wire [1:0] w_mreq_head_at;
wire [9:0] w_mreq_head_len;
wire [7:0] w_mreq_head_req_bus_num;
wire [4:0] w_mreq_head_req_dev_num;
wire [2:0] w_mreq_head_req_func_num;
wire [15:0] w_mreq_head_req_id;
wire [7:0] w_mreq_head_tag;
wire [3:0] w_mreq_head_last_be;
wire [3:0] w_mreq_head_1st_be;
//reg [4:0] r_rx_np_req_cnt;
//reg r_rx_np_req;
wire w_mwr;
wire w_4dw;
reg [2:0] r_mreq_head_fmt;
reg [9:0] r_mreq_head_len;
reg [15:0] r_mreq_head_req_id;
reg [7:0] r_mreq_head_tag;
reg [3:0] r_mreq_head_last_be;
reg [3:0] r_mreq_head_1st_be;
reg [12:0] r_mreq_addr;
reg [63:0] r_mreq_data;
reg [3:0] r_cpld_bc;
reg r_lbytes_en;
reg r_hbytes_en;
reg r_wr_reg;
reg r_wr_doorbell;
reg r_tx_cpld_req;
reg [63:0] r_rd_data;
reg [63:0] r_rd_reg;
reg [63:0] r_rd_doorbell;
reg r_mreq_fifo_rd_en;
wire [8:0] w_sq_rst_n;
wire [8:0] w_cq_rst_n;
//pcie mrd or mwr, memory rd/wr request
assign w_pcie_head0 = mreq_fifo_rd_data[31:0];
assign w_pcie_head1 = mreq_fifo_rd_data[63:32];
assign w_pcie_head2 = mreq_fifo_rd_data[95:64];
assign w_pcie_head3 = mreq_fifo_rd_data[127:96];
assign w_mreq_head_fmt = w_pcie_head0[31:29];
//assign w_mreq_head_type = w_pcie_head0[28:24];
//assign w_mreq_head_tc = w_pcie_head0[22:20];
//assign w_mreq_head_attr1 = w_pcie_head0[18];
//assign w_mreq_head_th = w_pcie_head0[16];
//assign w_mreq_head_td = w_pcie_head0[15];
//assign w_mreq_head_ep = w_pcie_head0[14];
//assign w_mreq_head_attr0 = w_pcie_head0[13:12];
//assign w_mreq_head_at = w_pcie_head0[11:10];
assign w_mreq_head_len = w_pcie_head0[9:0];
assign w_mreq_head_req_bus_num = w_pcie_head1[31:24];
assign w_mreq_head_req_dev_num = w_pcie_head1[23:19];
assign w_mreq_head_req_func_num = w_pcie_head1[18:16];
assign w_mreq_head_req_id = {w_mreq_head_req_bus_num, w_mreq_head_req_dev_num, w_mreq_head_req_func_num};
assign w_mreq_head_tag = w_pcie_head1[15:8];
assign w_mreq_head_last_be = w_pcie_head1[7:4];
assign w_mreq_head_1st_be = w_pcie_head1[3:0];
assign w_mwr = r_mreq_head_fmt[1];
assign w_4dw = r_mreq_head_fmt[0];
assign tx_cpld_req = r_tx_cpld_req;
assign tx_cpld_tag = r_mreq_head_tag;
assign tx_cpld_req_id = r_mreq_head_req_id;
assign tx_cpld_len = {8'b0, r_mreq_head_len[1:0]};
assign tx_cpld_bc = {8'b0, r_cpld_bc};
assign tx_cpld_laddr = r_mreq_addr[6:0];
assign tx_cpld_data = (r_mreq_addr[2] == 1) ? {32'b0, r_rd_data[63:32]} : r_rd_data;
assign rx_np_ok = 1'b1;
assign rx_np_req = 1'b1;
assign mreq_fifo_rd_en = r_mreq_fifo_rd_en;
assign admin_sq_bs_addr = r_asq_asqb;
assign admin_cq_bs_addr = r_acq_acqb;
assign nvme_cc_en = r_cc_en;
assign nvme_cc_shn = r_cc_shn;
assign nvme_intms_ivms = r_intms_ivms;
assign nvme_intmc_ivmc = r_intmc_ivmc;
assign admin_sq_size = r_aqa_asqs;
assign admin_cq_size = r_aqa_acqs;
assign admin_sq_tail_ptr = r_reg_sq0tdbl;
assign io_sq1_tail_ptr = r_reg_sq1tdbl;
assign io_sq2_tail_ptr = r_reg_sq2tdbl;
assign io_sq3_tail_ptr = r_reg_sq3tdbl;
assign io_sq4_tail_ptr = r_reg_sq4tdbl;
assign io_sq5_tail_ptr = r_reg_sq5tdbl;
assign io_sq6_tail_ptr = r_reg_sq6tdbl;
assign io_sq7_tail_ptr = r_reg_sq7tdbl;
assign io_sq8_tail_ptr = r_reg_sq8tdbl;
assign admin_cq_head_ptr = r_reg_cq0hdbl;
assign io_cq1_head_ptr = r_reg_cq1hdbl;
assign io_cq2_head_ptr = r_reg_cq2hdbl;
assign io_cq3_head_ptr = r_reg_cq3hdbl;
assign io_cq4_head_ptr = r_reg_cq4hdbl;
assign io_cq5_head_ptr = r_reg_cq5hdbl;
assign io_cq6_head_ptr = r_reg_cq6hdbl;
assign io_cq7_head_ptr = r_reg_cq7hdbl;
assign io_cq8_head_ptr = r_reg_cq8hdbl;
assign cq_head_update = r_cq_head_update;
always @ (posedge pcie_user_clk)
begin
r_cq_irq_status <= cq_irq_status;
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(mreq_fifo_empty_n == 1)
next_state <= S_PCIE_RD_HEAD;
else
next_state <= S_IDLE;
end
S_PCIE_RD_HEAD: begin
next_state <= S_PCIE_ADDR;
end
S_PCIE_ADDR: begin
if(w_mwr == 1) begin
if(w_4dw == 1 || r_mreq_head_len[1] == 1) begin
if(mreq_fifo_empty_n == 1)
next_state <= S_PCIE_WR_DATA;
else
next_state <= S_PCIE_WAIT_WR_DATA;
end
else
next_state <= S_PCIE_MWR;
end
else begin
next_state <= S_PCIE_MRD;
end
end
S_PCIE_WAIT_WR_DATA: begin
if(mreq_fifo_empty_n == 1)
next_state <= S_PCIE_WR_DATA;
else
next_state <= S_PCIE_WAIT_WR_DATA;
end
S_PCIE_WR_DATA: begin
next_state <= S_PCIE_MWR;
end
S_PCIE_MWR: begin
next_state <= S_IDLE;
end
S_PCIE_MRD: begin
next_state <= S_PCIE_CPLD_REQ;
end
S_PCIE_CPLD_REQ: begin
next_state <= S_PCIE_CPLD_ACK;
end
S_PCIE_CPLD_ACK: begin
if(tx_cpld_req_ack == 1)
next_state <= S_IDLE;
else
next_state <= S_PCIE_CPLD_ACK;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_PCIE_RD_HEAD: begin
r_mreq_head_fmt <= w_mreq_head_fmt;
r_mreq_head_len <= w_mreq_head_len;
r_mreq_head_req_id <= w_mreq_head_req_id;
r_mreq_head_tag <= w_mreq_head_tag;
r_mreq_head_last_be <= w_mreq_head_last_be;
r_mreq_head_1st_be <= w_mreq_head_1st_be;
r_pcie_head2 <= w_pcie_head2;
r_pcie_head3 <= w_pcie_head3;
end
S_PCIE_ADDR: begin
if(w_4dw == 1) begin
r_mreq_addr[12:2] <= r_pcie_head3[12:2];
r_lbytes_en <= ~r_pcie_head3[2] & (r_pcie_head3[11:7] == 0);
r_hbytes_en <= (r_pcie_head3[2] | r_mreq_head_len[1]) & (r_pcie_head3[11:7] == 0);
end
else begin
r_mreq_addr[12:2] <= r_pcie_head2[12:2];
r_lbytes_en <= ~r_pcie_head2[2] & (r_pcie_head2[11:7] == 0);;
r_hbytes_en <= (r_pcie_head2[2] | r_mreq_head_len[1]) & (r_pcie_head2[11:7] == 0);
if(r_pcie_head2[2] == 1)
r_mreq_data[63:32] <= {r_pcie_head3[7:0], r_pcie_head3[15:8], r_pcie_head3[23:16], r_pcie_head3[31:24]};
else
r_mreq_data[31:0] <= {r_pcie_head3[7:0], r_pcie_head3[15:8], r_pcie_head3[23:16], r_pcie_head3[31:24]};
end
end
S_PCIE_WAIT_WR_DATA: begin
end
S_PCIE_WR_DATA: begin
if(w_4dw == 1) begin
if(r_mreq_addr[2] == 1)
r_mreq_data[63:32] <= {mreq_fifo_rd_data[7:0], mreq_fifo_rd_data[15:8], mreq_fifo_rd_data[23:16], mreq_fifo_rd_data[31:24]};
else begin
r_mreq_data[31:0] <= {mreq_fifo_rd_data[7:0], mreq_fifo_rd_data[15:8], mreq_fifo_rd_data[23:16], mreq_fifo_rd_data[31:24]};
r_mreq_data[63:32] <= {mreq_fifo_rd_data[39:32], mreq_fifo_rd_data[47:40], mreq_fifo_rd_data[55:48], mreq_fifo_rd_data[63:56]};
end
end
else
r_mreq_data[63:32] <= {mreq_fifo_rd_data[7:0], mreq_fifo_rd_data[15:8], mreq_fifo_rd_data[23:16], mreq_fifo_rd_data[31:24]};
end
S_PCIE_MWR: begin
end
S_PCIE_MRD: begin
if(r_lbytes_en | r_hbytes_en) begin
if(r_mreq_addr[12] == 1) begin
r_rd_data[31:0] <= {r_rd_doorbell[7:0], r_rd_doorbell[15:8], r_rd_doorbell[23:16], r_rd_doorbell[31:24]};
r_rd_data[63:32] <= {r_rd_doorbell[39:32], r_rd_doorbell[47:40], r_rd_doorbell[55:48], r_rd_doorbell[63:56]};
end
else begin
r_rd_data[31:0] <= {r_rd_reg[7:0], r_rd_reg[15:8], r_rd_reg[23:16], r_rd_reg[31:24]};
r_rd_data[63:32] <= {r_rd_reg[39:32], r_rd_reg[47:40], r_rd_reg[55:48], r_rd_reg[63:56]};
end
end
else
r_rd_data <= 64'b0;
if(r_mreq_head_1st_be[0] == 1)
r_mreq_addr[1:0] <= 2'b00;
else if(r_mreq_head_1st_be[1] == 1)
r_mreq_addr[1:0] <= 2'b01;
else if(r_mreq_head_1st_be[2] == 1)
r_mreq_addr[1:0] <= 2'b10;
else
r_mreq_addr[1:0] <= 2'b11;
r_cpld_bc <= ((r_mreq_head_1st_be[0] + r_mreq_head_1st_be[1])
+ (r_mreq_head_1st_be[2] + r_mreq_head_1st_be[3]))
+ ((r_mreq_head_last_be[0] + r_mreq_head_last_be[1])
+ (r_mreq_head_last_be[2] + r_mreq_head_last_be[3]));
end
S_PCIE_CPLD_REQ: begin
end
S_PCIE_CPLD_ACK: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_RD_HEAD: begin
r_mreq_fifo_rd_en <= 1;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_ADDR: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_WAIT_WR_DATA: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_WR_DATA: begin
r_mreq_fifo_rd_en <= 1;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_MWR: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= ~r_mreq_addr[12];
r_wr_doorbell <= r_mreq_addr[12];
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_MRD: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_CPLD_REQ: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 1;
//r_rx_np_req <= 1;
end
S_PCIE_CPLD_ACK: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
default: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_intms_ivms <= 0;
r_intmc_ivmc <= 0;
{r_cc_iocqes, r_cc_iosqes, r_cc_shn, r_cc_asm, r_cc_mps, r_cc_ccs, r_cc_en} <= 0;
{r_aqa_acqs, r_aqa_asqs} <= 0;
r_asq_asqb <= 0;
r_acq_acqb <= 0;
end
else begin
if(r_wr_reg == 1) begin
if(r_lbytes_en == 1) begin
case(r_mreq_addr[6:3]) // synthesis parallel_case
4'h5: r_asq_asqb[31:2] <= r_mreq_data[31:2];
4'h6: r_acq_acqb[31:2] <= r_mreq_data[31:2];
endcase
if(r_mreq_addr[6:3] == 4'h1)
r_intmc_ivmc <= r_mreq_data[0];
else
r_intmc_ivmc <= 0;
end
if(r_hbytes_en == 1) begin
case(r_mreq_addr[6:3]) // synthesis parallel_case
4'h2: {r_cc_iocqes, r_cc_iosqes, r_cc_shn, r_cc_asm, r_cc_mps, r_cc_ccs, r_cc_en}
<= {r_mreq_data[55:52], r_mreq_data[51:48], r_mreq_data[47:46], r_mreq_data[45:43], r_mreq_data[42:39], r_mreq_data[38:36], r_mreq_data[32]};
4'h4: {r_aqa_acqs, r_aqa_asqs} <= {r_mreq_data[55:48], r_mreq_data[39:32]};
4'h5: r_asq_asqb[C_PCIE_ADDR_WIDTH-1:32] <= r_mreq_data[C_PCIE_ADDR_WIDTH-1:32];
4'h6: r_acq_acqb[C_PCIE_ADDR_WIDTH-1:32] <= r_mreq_data[C_PCIE_ADDR_WIDTH-1:32];
endcase
if(r_mreq_addr[6:3] == 4'h1)
r_intms_ivms <= r_mreq_data[32];
else
r_intms_ivms <= 0;
end
end
else begin
r_intms_ivms <= 0;
r_intmc_ivmc <= 0;
end
end
end
assign w_sq_rst_n[0] = pcie_user_rst_n & sq_rst_n[0];
assign w_sq_rst_n[1] = pcie_user_rst_n & sq_rst_n[1];
assign w_sq_rst_n[2] = pcie_user_rst_n & sq_rst_n[2];
assign w_sq_rst_n[3] = pcie_user_rst_n & sq_rst_n[3];
assign w_sq_rst_n[4] = pcie_user_rst_n & sq_rst_n[4];
assign w_sq_rst_n[5] = pcie_user_rst_n & sq_rst_n[5];
assign w_sq_rst_n[6] = pcie_user_rst_n & sq_rst_n[6];
assign w_sq_rst_n[7] = pcie_user_rst_n & sq_rst_n[7];
assign w_sq_rst_n[8] = pcie_user_rst_n & sq_rst_n[8];
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[0])
begin
if(w_sq_rst_n[0] == 0) begin
r_reg_sq0tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h0)) == 1)
r_reg_sq0tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[1])
begin
if(w_sq_rst_n[1] == 0) begin
r_reg_sq1tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h1)) == 1)
r_reg_sq1tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[2])
begin
if(w_sq_rst_n[2] == 0) begin
r_reg_sq2tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h2)) == 1)
r_reg_sq2tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[3])
begin
if(w_sq_rst_n[3] == 0) begin
r_reg_sq3tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h3)) == 1)
r_reg_sq3tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[4])
begin
if(w_sq_rst_n[4] == 0) begin
r_reg_sq4tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h4)) == 1)
r_reg_sq4tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[5])
begin
if(w_sq_rst_n[5] == 0) begin
r_reg_sq5tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h5)) == 1)
r_reg_sq5tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[6])
begin
if(w_sq_rst_n[6] == 0) begin
r_reg_sq6tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h6)) == 1)
r_reg_sq6tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[7])
begin
if(w_sq_rst_n[7] == 0) begin
r_reg_sq7tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h7)) == 1)
r_reg_sq7tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[8])
begin
if(w_sq_rst_n[8] == 0) begin
r_reg_sq8tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h8)) == 1)
r_reg_sq8tdbl <= r_mreq_data[7:0];
end
end
assign w_cq_rst_n[0] = pcie_user_rst_n & cq_rst_n[0];
assign w_cq_rst_n[1] = pcie_user_rst_n & cq_rst_n[1];
assign w_cq_rst_n[2] = pcie_user_rst_n & cq_rst_n[2];
assign w_cq_rst_n[3] = pcie_user_rst_n & cq_rst_n[3];
assign w_cq_rst_n[4] = pcie_user_rst_n & cq_rst_n[4];
assign w_cq_rst_n[5] = pcie_user_rst_n & cq_rst_n[5];
assign w_cq_rst_n[6] = pcie_user_rst_n & cq_rst_n[6];
assign w_cq_rst_n[7] = pcie_user_rst_n & cq_rst_n[7];
assign w_cq_rst_n[8] = pcie_user_rst_n & cq_rst_n[8];
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[0])
begin
if(w_cq_rst_n[0] == 0) begin
r_reg_cq0hdbl <= 0;
r_cq_head_update[0] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h0)) == 1) begin
r_reg_cq0hdbl <= r_mreq_data[39:32];
r_cq_head_update[0] <= 1;
end
else
r_cq_head_update[0] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[1])
begin
if(w_cq_rst_n[1] == 0) begin
r_reg_cq1hdbl <= 0;
r_cq_head_update[1] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h1)) == 1) begin
r_reg_cq1hdbl <= r_mreq_data[39:32];
r_cq_head_update[1] <= 1;
end
else
r_cq_head_update[1] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[2])
begin
if(w_cq_rst_n[2] == 0) begin
r_reg_cq2hdbl <= 0;
r_cq_head_update[2] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h2)) == 1) begin
r_reg_cq2hdbl <= r_mreq_data[39:32];
r_cq_head_update[2] <= 1;
end
else
r_cq_head_update[2] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[3])
begin
if(w_cq_rst_n[3] == 0) begin
r_reg_cq3hdbl <= 0;
r_cq_head_update[3] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h3)) == 1) begin
r_reg_cq3hdbl <= r_mreq_data[39:32];
r_cq_head_update[3] <= 1;
end
else
r_cq_head_update[3] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[4])
begin
if(w_cq_rst_n[4] == 0) begin
r_reg_cq4hdbl <= 0;
r_cq_head_update[4] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h4)) == 1) begin
r_reg_cq4hdbl <= r_mreq_data[39:32];
r_cq_head_update[4] <= 1;
end
else
r_cq_head_update[4] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[5])
begin
if(w_cq_rst_n[5] == 0) begin
r_reg_cq5hdbl <= 0;
r_cq_head_update[5] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h5)) == 1) begin
r_reg_cq5hdbl <= r_mreq_data[39:32];
r_cq_head_update[5] <= 1;
end
else
r_cq_head_update[5] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[6])
begin
if(w_cq_rst_n[6] == 0) begin
r_reg_cq6hdbl <= 0;
r_cq_head_update[6] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h6)) == 1) begin
r_reg_cq6hdbl <= r_mreq_data[39:32];
r_cq_head_update[6] <= 1;
end
else
r_cq_head_update[6] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[7])
begin
if(w_cq_rst_n[7] == 0) begin
r_reg_cq7hdbl <= 0;
r_cq_head_update[7] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h7)) == 1) begin
r_reg_cq7hdbl <= r_mreq_data[39:32];
r_cq_head_update[7] <= 1;
end
else
r_cq_head_update[7] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[8])
begin
if(w_cq_rst_n[8] == 0) begin
r_reg_cq8hdbl <= 0;
r_cq_head_update[8] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h8)) == 1) begin
r_reg_cq8hdbl <= r_mreq_data[39:32];
r_cq_head_update[8] <= 1;
end
else
r_cq_head_update[8] <= 0;
end
end
always @ (*)
begin
case(r_mreq_addr[6:3]) // synthesis parallel_case
4'h0: r_rd_reg <= {8'h0, `D_CAP_MPSMAX, `D_CAP_MPSMIN, 3'h0, `D_CAP_CSS, `D_CAP_NSSRS, `D_CAP_DSTRD, `D_CAP_TO, 5'h0, `D_CAP_AMS, `D_CAP_CQR, `D_CAP_MQES};
4'h1: r_rd_reg <= {31'b0, r_cq_irq_status, `D_VS_MJR, `D_VS_MNR, 8'b0};
4'h2: r_rd_reg <= {8'b0, r_cc_iocqes, r_cc_iosqes, r_cc_shn, r_cc_asm, r_cc_mps, r_cc_ccs, 3'b0, r_cc_en, 31'b0, r_cq_irq_status};
4'h3: r_rd_reg <= {28'b0, nvme_csts_shst, 1'b0, nvme_csts_rdy, 32'b0};
4'h4: r_rd_reg <= {8'b0, r_aqa_acqs, 8'b0, r_aqa_asqs, 32'b0};
4'h5: r_rd_reg <= {26'b0, r_asq_asqb, 2'b0};
4'h6: r_rd_reg <= {26'b0, r_acq_acqb, 2'b0};
default: r_rd_reg <= 64'b0;
endcase
end
always @ (*)
begin
case(r_mreq_addr[6:3]) // synthesis parallel_case
4'h0: r_rd_doorbell <= {24'b0, r_reg_cq0hdbl, 24'b0, r_reg_sq0tdbl};
4'h1: r_rd_doorbell <= {24'b0, r_reg_cq1hdbl, 24'b0, r_reg_sq1tdbl};
4'h2: r_rd_doorbell <= {24'b0, r_reg_cq2hdbl, 24'b0, r_reg_sq2tdbl};
4'h3: r_rd_doorbell <= {24'b0, r_reg_cq3hdbl, 24'b0, r_reg_sq3tdbl};
4'h4: r_rd_doorbell <= {24'b0, r_reg_cq4hdbl, 24'b0, r_reg_sq4tdbl};
4'h5: r_rd_doorbell <= {24'b0, r_reg_cq5hdbl, 24'b0, r_reg_sq5tdbl};
4'h6: r_rd_doorbell <= {24'b0, r_reg_cq6hdbl, 24'b0, r_reg_sq6tdbl};
4'h7: r_rd_doorbell <= {24'b0, r_reg_cq7hdbl, 24'b0, r_reg_sq7tdbl};
4'h8: r_rd_doorbell <= {24'b0, r_reg_cq8hdbl, 24'b0, r_reg_sq8tdbl};
default: r_rd_doorbell <= 64'b0;
endcase
end
endmodule |
// /**
// * This Verilog HDL file is used for simulation and synthesis in
// * the chaining DMA design example. It manages DMA read data transfer from
// * the Root Complex memory to the End Point memory.
// */
// synthesis translate_off
`include "altpcierd_dma_dt_cst_sim.v"
`timescale 1ns / 1ps
// synthesis translate_on
// synthesis verilog_input_version verilog_2001
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//-----------------------------------------------------------------------------
// Title : DMA Read requestor module (altpcierd_read_dma_requester)
// Project : PCI Express MegaCore function
//-----------------------------------------------------------------------------
// File : altpcierd_read_dma_requester.v
// Author : Altera Corporation
//-----------------------------------------------------------------------------
//
// - Retrieve descriptor info from the dt_fifo (module read descriptor)
// states : cstate_tx = DT_FIFO_RD_QW0, DT_FIFO_RD_QW1
// cdt_length_dw_tx : number of DWORDs to transfer
// - For each descriptor:
// - Send multiple Mrd request for a max payload
// tx_length=< cdt_length_dw_tx
// - Each Tx MRd has TAG starting from 2--> MAX_NUMTAG.
// A counter issue the TAG up to MAX_NUMTAG; When MAX_NUMTAG
// the TAG are pop-ed from the TAG FIFO.
// when Rx received packet (CPLD), the TAG is recycled (pushed)
// into the TAG_FIFO if the completion of tx_length in TAG RAM
//
// - RAM : tag_dpram :
// hash table which tracks TAG information
// Port A : is used by the TX code section
// data_a = {tx_length_dw[9:1], tx_tag_addr_offset_qw[AVALON_WADDR-1:0]};
// Port B : is used by the RX code section
// data_b = {rx_length_dw[9:1], tx_tag_addr_offset_qw[AVALON_WADDR-1:0]};
// q =
// - FIFO : tag_scfifo :
// contains the list of TAG which can be re-used by the TX code section
// The RX code section updates this FIFO by writting recycled TAG upon
// completion
//
// - FIFO : rx_data_fifo :
// is used by the RX code section to eliminates RX_WS and increase
// DMA read throughput.
//
//-----------------------------------------------------------------------------
// Copyright (c) 2009 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
module altpcierd_read_dma_requester # (
parameter MAX_NUMTAG = 32,
parameter RC_SLAVE_USETAG = 0,
parameter FIFO_WIDTH = 64,
parameter TXCRED_WIDTH = 22,
parameter AVALON_WADDR = 12,
parameter AVALON_WDATA = 64,
parameter BOARD_DEMO = 0,
parameter USE_MSI = 1,
parameter USE_CREDIT_CTRL = 1,
parameter INTENDED_DEVICE_FAMILY = "Cyclone IV GX",
parameter RC_64BITS_ADDR = 0,
parameter AVALON_BYTE_WIDTH = AVALON_WDATA/8,
parameter DT_EP_ADDR_SPEC = 2, // Descriptor Table's EP Address is specified as: 3=QW Address, 2=DW Address, 1= W Address, 0= Byte Addr.
parameter CDMA_AST_RXWS_LATENCY = 2 // response time of rx_data to rx_ws
)
(
// Descriptor control signals
output dt_fifo_rdreq,
input dt_fifo_empty,
input [FIFO_WIDTH-1:0] dt_fifo_q ,
input [15:0] cfg_maxrdreq_dw,
input [2:0] cfg_maxrdreq ,
input [4:0] cfg_link_negociated ,
input [63:0] dt_base_rc ,
input dt_3dw_rcadd ,
input dt_eplast_ena,
input dt_msi ,
input [15:0] dt_size ,
//PCIe transmit
output tx_ready,
output tx_busy ,
input tx_sel ,
input [TXCRED_WIDTH-1:0] tx_cred,
input tx_have_creds,
input tx_ack ,
input tx_ws ,
output reg tx_req ,
output reg tx_dv ,
output tx_dfr ,
output [127:0] tx_desc ,
output [63:0] tx_data ,
input [15:0] rx_buffer_cpl_max_dw, // specifify the maximum amount of data available in RX Buffer for a given MRd
//PCIe receive
input rx_req ,
output rx_ack ,
input [135:0] rx_desc ,
input [63:0] rx_data ,
input [15:0] rx_be,
input rx_dv ,
input rx_dfr ,
output rx_ws ,
// MSI
input app_msi_ack,
output app_msi_req,
input msi_sel ,
output msi_ready ,
output msi_busy ,
//avalon slave port
output reg [AVALON_WDATA-1:0] writedata ,
output reg [AVALON_WADDR-1:0] address ,
output reg write ,
output waitrequest,
output reg [AVALON_BYTE_WIDTH-1:0] write_byteena,
// RC Slave control signals
input descriptor_mrd_cycle,
output reg requester_mrdmwr_cycle,
output [3:0] dma_sm_tx,
output [2:0] dma_sm_rx,
output [2:0] dma_sm_rx_data,
output [63:0] dma_status,
output reg cpl_pending,
input init ,
input clk_in ,
input rstn
);
// VHDL translation_on
// function integer ceil_log2;
// input integer numwords;
// begin
// ceil_log2=0;
// numwords = numwords-1;
// while (numwords>0)
// begin
// ceil_log2=ceil_log2+1;
// numwords = numwords >> 1;
// end
// end
// endfunction
//
// function integer get_numwords;
// input integer width;
// begin
// get_numwords = (1<<width);
// end
// endfunction
// VHDL translation_off
// Parameter for TX State machine
localparam DT_FIFO =0 , // Ready for next Descriptor FIFO (DT)
DT_FIFO_RD_QW0 =1 , // read First QWORD
DT_FIFO_RD_QW1 =2 , // read second QWORD
MAX_RREQ_UPD =3 , // Update lenght counters
TX_LENGTH =4 , // Update lenght counters
START_TX =5 , // Wait for top level arbitration tx_sel
MRD_REQ =6 , // Set tx_req, MRD
MRD_ACK =7 , // Get tx_ack
GET_TAG =8 , // Optional Tag FIFO Retrieve
CPLD =9 , // Wait for CPLD state machine (rx)
DONE =10, // Completed MRD-CPLD
START_TX_UPD_DT =11, // Wait for top level arbitration tx_sel
MWR_REQ_UPD_DT =12, // Set tx_req, MWR
MWR_ACK_UPD_DT =13; // Get tx_ack
// Parameter for RX State machine
localparam CPLD_IDLE = 0,
CPLD_REQ = 1,
CPLD_ACK = 2,
CPLD_DV = 3,
CPLD_LAST = 4;
// Parameter for RX DATA FIFO State machine
localparam SM_RX_DATA_FIFO_IDLE = 0,
SM_RX_DATA_FIFO_READ_TAGRAM_1 = 1,
SM_RX_DATA_FIFO_READ_TAGRAM_2 = 2,
SM_RX_DATA_FIFO_RREQ = 3,
SM_RX_DATA_FIFO_SINGLE_QWORD = 4,
SM_RX_DATA_FIFO_TAGRAM_UPD = 5;
// MSI State
localparam IDLE_MSI = 0,// MSI Stand by
START_MSI = 1,// Wait for msi_sel
MWR_REQ_MSI = 2;// Set app_msi_req, wait for app_msi_ack
localparam ZERO_INTEGER = 0;
localparam MAX_NUMTAG_VAL = MAX_NUMTAG-1;
localparam FIRST_DMARD_TAG = 2+RC_SLAVE_USETAG;
localparam FIRST_DMARD_TAG_SEC_DESCRIPTOR = (MAX_NUMTAG-FIRST_DMARD_TAG)/2+FIRST_DMARD_TAG;
localparam MAX_NUMTAG_VAL_FIRST_DESCRIPTOR = FIRST_DMARD_TAG_SEC_DESCRIPTOR-1;
localparam TAG_TRACK_WIDTH = MAX_NUMTAG-2-RC_SLAVE_USETAG;
localparam TAG_TRACK_HALF_WIDTH = TAG_TRACK_WIDTH/2;
localparam TAG_FIFO_DEPTH = MAX_NUMTAG-2;
// localparam MAX_TAG_WIDTH = ceil_log2(MAX_NUMTAG);
localparam MAX_TAG_WIDTH = (MAX_NUMTAG<3 )?1:
(MAX_NUMTAG<5 )?2:
(MAX_NUMTAG<9 )?3:
(MAX_NUMTAG<17 )?4:
(MAX_NUMTAG<33 )?5:
(MAX_NUMTAG<65 )?6:
(MAX_NUMTAG<129)?7:8;
// localparam MAX_TAG_WIDTHU = ceil_log2(TAG_FIFO_DEPTH);
localparam MAX_TAG_WIDTHU = (TAG_FIFO_DEPTH<3 )?1:
(TAG_FIFO_DEPTH<5 )?2:
(TAG_FIFO_DEPTH<9 )?3:
(TAG_FIFO_DEPTH<17 )?4:
(TAG_FIFO_DEPTH<33 )?5:
(TAG_FIFO_DEPTH<65 )?6:
(TAG_FIFO_DEPTH<129)?7:8;
localparam LENGTH_DW_WIDTH = 10;
localparam LENGTH_QW_WIDTH = 9;
localparam TAG_EP_ADDR_WIDTH = (AVALON_WADDR+3); // AVALON_WADDR is a QW Address, Tag Ram stores Byte Address
localparam TAG_RAM_WIDTH = LENGTH_DW_WIDTH+ TAG_EP_ADDR_WIDTH;
localparam TAG_RAM_WIDTHAD = MAX_TAG_WIDTH;
localparam TAG_RAM_NUMWORDS = (1<<TAG_RAM_WIDTHAD);
// localparam TAG_RAM_NUMWORDS = get_numwords(TAG_RAM_WIDTHAD);
localparam RX_DATA_FIFO_NUMWORDS = 16;
localparam RX_DATA_FIFO_WIDTHU = 4;
localparam RX_DATA_FIFO_ALMST_FULL_LIM= RX_DATA_FIFO_NUMWORDS-6;
localparam RX_DATA_FIFO_WIDTH = 74+MAX_TAG_WIDTH;
integer i;
assign waitrequest = 0;
// State machine registers for transmit MRd MWr (tx)
reg [3:0] cstate_tx;
reg [3:0] nstate_tx;
reg tx_mrd_cycle;
// State machine registers for Receive CPLD (rx)
reg [2:0] cstate_rx;
reg [2:0] nstate_rx;
//
reg [2:0] cstate_rx_data_fifo;
reg [2:0] nstate_rx_data_fifo;
// MSI State machine registers
// MSI could be send in parallel to EPLast
reg [2:0] cstate_msi;
reg [2:0] nstate_msi;
// control bits : set when ep_lastup transmit
reg ep_lastupd_cycle;
reg [2:0] rx_ws_ast; //rx_ws from Avalon ST
reg rx_ast_data_valid; //rx_ws from Avalon ST
// Control counter for payload and dma length
reg [15:0] cdt_length_dw_tx; // cdt : length of the transfer (in DWORD)
// for the current descriptor. This counter
// is used for tx (Mrd)
wire [12:0] cfg_maxrdreq_byte; // Max read request in bytes
reg [12:0] calc_4kbnd_mrd_ack_byte;
reg [12:0] calc_4kbnd_dt_fifo_byte;
wire [15:0] calc_4kbnd_mrd_ack_dw;
wire [15:0] calc_4kbnd_dt_fifo_dw;
reg [12:0] tx_desc_addr_4k;
wire [12:0] dt_fifo_q_addr_4k;
reg [15:0] maxrdreq_dw;
reg [9:0] tx_length_dw ; // length of tx_PCIE transfer in DWORD
// tx_desc[105:96] = tx_length_dw when tx_req
wire [11:0] tx_length_byte ; // length of tx_PCIE transfer in BYTE
// tx_desc[105:96] = tx_length_dw when tx_req
wire [31:0] tx_length_byte_32ext ;
wire [63:0] tx_length_byte_64ext ;
// control bits : check 32 bit vs 64 bit address
reg txadd_3dw;
// control bits : generate tx_dfr & tx_dv
reg tx_req_reg;
reg tx_req_delay;
// DMA registers
reg cdt_msi ;// When set, send MSI to RC host
reg cdt_eplast_ena;// When set, update RC Host memory with dt_ep_last
reg [15:0] dt_ep_last ;// Number of descriptors completed
// PCIe Signals RC address
wire [MAX_TAG_WIDTH-1:0] tx_tag_wire_mux_first_descriptor;
wire [MAX_TAG_WIDTH-1:0] tx_tag_wire_mux_second_descriptor;
wire tx_get_tag_from_fifo;
reg [7:0] tx_tag_tx_desc;
reg [63:0] tx_desc_addr ;
wire addrval_32b;
wire [63:0] tx_desc_addr_pipe ;
reg [31:0] tx_desc_addr_3dw_pipe;
reg [63:0] tx_addr_eplast;
wire [63:0] tx_addr_eplast_pipe;
reg tx_32addr_eplast;
reg [63:0] tx_data_eplast;
wire [3:0] tx_lbe_d ;
wire [3:0] tx_fbe_d ;
// tx_credit controls
wire tx_cred_non_posted_header_valid;
reg tx_cred_non_posted_header_valid_x8;
reg tx_cred_posted_data_valid_8x;
wire tx_cred_posted_data_valid_4x;
wire tx_cred_posted_data_valid ;
reg rx_buffer_cpl_ready;
reg rx_tag_is_sec_desc;
reg dt_ep_last_eq_dt_size;
//
// TAG management overview:
//
// TAG 8'h00 : Descriptor read
// TAG 8'h01 : Descriptor write
// TAG 8'h02 -> MAX TAG : Requester read
//
// TX issues MRd, with TAG "xyz" and length "tx_length" dword data
// RX ack CPLD with TAG "xyz", and length "rx_length" dword daata
//
// The TX state machine write a new TAG for every MRd on port A of
// tag_dpram
// The RX state machine uses the port B of tag_dpram
// When cstate_rx==CPLD_REQ --> Read tag_dpram word with "tx_length"
// info.
// When (cstate_rx==CPLD_DV)||(cstate_rx==CPLD_LAST) write tag_dpram
// to reflect the number of dword read for a given TAG
// If "tx_length" == "rx_length" the TAG is recycled in the tag_scfifo
reg [MAX_TAG_WIDTH-1:0] tx_tag_cnt_first_descriptor ;
reg [MAX_TAG_WIDTH-1:0] tx_tag_cnt_second_descriptor;
reg [MAX_TAG_WIDTH-1:0] rx_tag ;
reg tx_tag_mux_first_descriptor ;
reg tx_tag_mux_second_descriptor ;
// tag_scfifo:
// The tx_state machine read data
// The rx_statemachine pushes data
wire tag_fifo_sclr ;
wire rx_second_descriptor_tag;
wire rx_fifo_wrreq_first_descriptor ;
wire rx_fifo_wrreq_second_descriptor ;
reg tagram_wren_b_mrd_ack ;
wire tx_fifo_rdreq_first_descriptor ;
wire tx_fifo_rdreq_second_descriptor ;
wire [MAX_TAG_WIDTH-1:0] tx_tag_fifo_first_descriptor ;
wire [MAX_TAG_WIDTH-1:0] tx_tag_fifo_second_descriptor ;
wire tag_fifo_empty_first_descriptor ;
wire tag_fifo_empty_second_descriptor ;
wire tag_fifo_full_first_descriptor ;
wire tag_fifo_full_second_descriptor ;
wire rx_dmard_tag ; //set when rx_desc tag >FIRST_DMARD_TAG
reg rx_dmard_cpld;
reg valid_rx_dmard_cpld_next;
reg valid_rx_dv_for_dmard;
reg valid_rx_dmard_cpld_p0_reg;
wire valid_rx_dmard_cpld; //set when
// -- the second phase of rx_req,
// + Valid tag
// + Valid first phase of rx_req (CPLD and rx_dfr)
// Constant used for VHDL translation
wire cst_one;
wire cst_zero;
wire [63:0] cst_std_logic_vector_type_one;
wire [511:0] cst_std_logic_vector_type_zero;
wire [MAX_TAG_WIDTH-1:0] FIRST_DMARD_TAG_cst_width_eq_MAX_TAG_WIDTH;
wire [MAX_TAG_WIDTH-1:0] FIRST_DMARD_TAG_SEC_DESCRIPTOR_cst_width_eq_MAX_TAG_WIDTH;
// tag_dpram:
// data : tx_length_dw[9:1] :QWORD LENGTH to know when recycle TAG
// tx_tag_addr_offset_qw[AVALON_WADDR-1:0]:EP Address offset (where PCIE write to)
// {tx_length_dw[9:1], tx_tag_addr_offset_qw[AVALON_WADDR-1:0]}
// Address : TAG
wire tagram_wren_a ;
wire [TAG_RAM_WIDTH-1:0] tagram_data_a ;
wire [MAX_TAG_WIDTH-1:0] tagram_address_a;
reg tagram_wren_b ;
reg tagram_wren_b_reg_init;
reg [TAG_RAM_WIDTH-1:0] tagram_data_b ;
wire [MAX_TAG_WIDTH-1:0] tagram_address_b;
reg [MAX_TAG_WIDTH-1:0] tagram_address_b_mrd_ack;
wire [TAG_RAM_WIDTH-1:0] tagram_q_b ;
reg [9:0] rx_tag_length_dw ;
reg rx_tag_length_dw_equal_zero;
reg [9:0] last_rx_tag_length_dw ;
reg [TAG_EP_ADDR_WIDTH-1:0] rx_tag_addr_offset;
wire [9:0] rx_tag_length_dw_next ;
wire [TAG_EP_ADDR_WIDTH-1:0] rx_tag_addr_offset_next;
reg tx_first_descriptor_cycle;
reg eplast_upd_first_descriptor;
reg next_is_second;
reg eplast_upd_second_descriptor;
wire tx_cpld_first_descriptor;
wire tx_cpld_second_descriptor;
reg [TAG_TRACK_WIDTH-1:0] tag_track_one_hot;
reg [TAG_TRACK_WIDTH-1:0] tag_track_one_hot_rx;
// Avalon address
reg [TAG_EP_ADDR_WIDTH-1:0] tx_tag_addr_offset;
// If multiple are needed, this track the
// EP adress offset for each tag in the TAGRAM
// Receive signals section
wire [1:0] rx_fmt ;
wire [4:0] rx_type;
// RX Data fifo signals
wire [RX_DATA_FIFO_WIDTH + 10:0] rx_data_fifo_data;
wire [RX_DATA_FIFO_WIDTH + 10:0] rx_data_fifo_q;
wire rx_data_fifo_sclr;
wire rx_data_fifo_wrreq;
wire rx_data_fifo_rdreq;
wire rx_data_fifo_full;
wire [RX_DATA_FIFO_WIDTHU-1:0] rx_data_fifo_usedw;
reg rx_data_fifo_almost_full;
wire rx_data_fifo_empty;
reg rx_dv_pulse_reg;
wire rx_dv_start_pulse;
wire rx_dv_end_pulse;
reg rx_dv_end_pulse_reg;
reg [MAX_TAG_WIDTH-1:0] rx_data_fifo_rx_tag;
reg tagram_data_rd_cycle;
reg [23:0] performance_counter;
reg[127:0] tx_desc_reg;
reg rx_req_reg;
reg rx_req_p1 ;
wire rx_req_p0;
wire [63:0] dt_fifo_ep_addr_byte;
wire debug;
reg cdt_msi_first_descriptor;
reg cdt_msi_second_descriptor;
reg cdt_eplast_first_descriptor;
reg cdt_eplast_second_descriptor;
reg [9:0] rx_length_hold;
reg [9:0] rx_data_fifo_length_hold;
wire got_all_cpl_for_tag;
wire rcving_last_cpl_for_tag_n;
reg rcving_last_cpl_for_tag;
reg transferring_data, transferring_data_n;
reg [9:0] tag_remaining_length;
reg [MAX_TAG_WIDTH-1:0] tagram_address_b_reg;
reg rx_fifo_wrreq_first_descriptor_reg;
reg rx_fifo_wrreq_second_descriptor_reg;
assign dma_status = tx_data_eplast;
always @ (negedge rstn or posedge clk_in) begin
if (rstn==1'b0) begin
rx_req_reg <= 1'b1;
rx_req_p1 <= 1'b0;
end
else begin
rx_req_reg <= rx_req;
rx_req_p1 <= rx_req_p0;
end
end
assign rx_req_p0 = rx_req & ~rx_req_reg;
always @ (posedge clk_in) begin
if (init==1'b1)
rx_dv_pulse_reg <= 1'b0;
else if (CDMA_AST_RXWS_LATENCY==4) begin
if (rx_ast_data_valid==1'b1)
rx_dv_pulse_reg <= rx_dv;
end
else
rx_dv_pulse_reg <= rx_dv;
end
assign rx_dv_start_pulse = ((rx_dv==1'b1) && (rx_dv_pulse_reg==1'b0))?1'b1:1'b0;
assign rx_dv_end_pulse = ((rx_dfr==1'b0)&&(rx_dv==1'b1) &&(CDMA_AST_RXWS_LATENCY==4))?1'b1:
((rx_dfr==1'b0)&&(rx_dv==1'b1)&&(rx_ast_data_valid==1'b1)&&(CDMA_AST_RXWS_LATENCY==2))?1'b1:
1'b0;
assign dma_sm_tx = cstate_tx;
assign dma_sm_rx = cstate_rx;
assign dma_sm_rx_data = cstate_rx_data_fifo;
// Constant carrying width type for VHDL translation
assign cst_one = 1'b1;
assign cst_zero = 1'b0;
assign cst_std_logic_vector_type_one = 64'hFFFF_FFFF_FFFF_FFFF;
assign cst_std_logic_vector_type_zero = 512'h0;
assign FIRST_DMARD_TAG_cst_width_eq_MAX_TAG_WIDTH=
FIRST_DMARD_TAG;
assign FIRST_DMARD_TAG_SEC_DESCRIPTOR_cst_width_eq_MAX_TAG_WIDTH=
FIRST_DMARD_TAG_SEC_DESCRIPTOR;
assign dt_fifo_ep_addr_byte = (DT_EP_ADDR_SPEC==0) ? {cst_std_logic_vector_type_zero[31:0], dt_fifo_q[63:32]} : {dt_fifo_q[63-DT_EP_ADDR_SPEC:32], {DT_EP_ADDR_SPEC{1'b0}}}; // Convert the EP Address (from the Descriptor Table) to a Byte address
always @ (posedge clk_in) begin
if (cstate_tx==DT_FIFO_RD_QW0) begin
tx_tag_addr_offset <= dt_fifo_ep_addr_byte;
// Store the Targeted EP Byte Address for the completion of a given Tag
end
else if (cstate_tx==MRD_ACK)
tx_tag_addr_offset <= tx_tag_addr_offset + {tx_length_dw[9:0], 2'b00};
end
// PCIe 4K byte boundary off-set
assign cfg_maxrdreq_byte[1:0] = 2'b00;
assign cfg_maxrdreq_byte[12:2] = cfg_maxrdreq_dw[10:0];
// calc maxrdreq_dw after DT_FIFO_RD_QW1
assign dt_fifo_q_addr_4k[12] = 1'b0;
assign dt_fifo_q_addr_4k[11:0] = dt_fifo_q[43:32];
always @ (posedge clk_in) begin
if (init==1'b1)
calc_4kbnd_dt_fifo_byte <= cfg_maxrdreq_byte;
else if (cstate_tx==DT_FIFO_RD_QW1)
calc_4kbnd_dt_fifo_byte <= 13'h1000-dt_fifo_q_addr_4k;
end
assign calc_4kbnd_dt_fifo_dw[15:11] = 0;
assign calc_4kbnd_dt_fifo_dw[10:0] = calc_4kbnd_dt_fifo_byte[12:2];
// calc maxrdreq_dw after MRD_REQ
always @ (posedge clk_in) begin
if (init==1'b1)
calc_4kbnd_mrd_ack_byte <= cfg_maxrdreq_byte;
else if ((cstate_tx==MRD_REQ) && (tx_ack==1'b1))
calc_4kbnd_mrd_ack_byte <= 13'h1000-tx_desc_addr_4k;
end
assign calc_4kbnd_mrd_ack_dw[15:11] = 0;
assign calc_4kbnd_mrd_ack_dw[10:0] = calc_4kbnd_mrd_ack_byte[12:2];
always @ (posedge clk_in) begin
if (init==1'b1)
tx_desc_addr_4k <= 0;
else if ((cstate_tx==MRD_REQ) && (tx_ack==1'b0)) begin
if ((txadd_3dw==1'b1)||(RC_64BITS_ADDR==0))
tx_desc_addr_4k[11:0] <= tx_desc_addr[43:32]+tx_length_byte;
else
tx_desc_addr_4k[11:0] <= tx_desc_addr[11:0]+tx_length_byte;
end
end
always @ (posedge clk_in) begin
if (init==1'b1)
maxrdreq_dw <= cfg_maxrdreq_dw;
else if (cstate_tx==MRD_ACK) begin
if (cfg_maxrdreq_byte > calc_4kbnd_mrd_ack_byte)
maxrdreq_dw <= calc_4kbnd_mrd_ack_dw;
else
maxrdreq_dw <= cfg_maxrdreq_dw;
end
else if (cstate_tx==MAX_RREQ_UPD) begin
if (cfg_maxrdreq_byte > calc_4kbnd_dt_fifo_byte)
maxrdreq_dw <= calc_4kbnd_dt_fifo_dw;
else
maxrdreq_dw <= cfg_maxrdreq_dw;
end
end
always @ (posedge clk_in) begin
// DWORD handling
if (init==1'b1)
cdt_length_dw_tx <= 0;
else begin
if (cstate_tx==DT_FIFO_RD_QW0)
cdt_length_dw_tx <= dt_fifo_q[15:0];
else if (cstate_tx==TX_LENGTH) begin
if (cdt_length_dw_tx<maxrdreq_dw)
cdt_length_dw_tx <= 0;
else
cdt_length_dw_tx <= cdt_length_dw_tx-maxrdreq_dw;
end
end
end
// DWORD count management
always @ (posedge clk_in) begin
if ((cstate_tx==DT_FIFO)||(cstate_tx==MRD_ACK))
tx_length_dw <= 0;
else begin
if (cstate_tx==TX_LENGTH) begin
if (cdt_length_dw_tx<maxrdreq_dw)
tx_length_dw <= cdt_length_dw_tx;
else
tx_length_dw <= maxrdreq_dw;
end
end
end
always @ * begin
if (cdt_length_dw_tx<maxrdreq_dw) begin
if (rx_buffer_cpl_max_dw<cdt_length_dw_tx)
rx_buffer_cpl_ready<=1'b0;
else
rx_buffer_cpl_ready<=1'b1;
end
else begin
if (rx_buffer_cpl_max_dw<maxrdreq_dw)
rx_buffer_cpl_ready<=1'b0;
else
rx_buffer_cpl_ready<=1'b1;
end
end
assign tx_length_byte[11:2] = tx_length_dw[9:0];
assign tx_length_byte[1:0] = 2'b00;
assign tx_length_byte_32ext[11:0] = tx_length_byte[11:0];
assign tx_length_byte_32ext[31:12] = 0;
assign tx_length_byte_64ext[11:0] = tx_length_byte[11:0];
assign tx_length_byte_64ext[63:12] = 0;
// Credit and flow control signaling
generate
begin
if (TXCRED_WIDTH>36)
begin
always @ (posedge clk_in) begin
if (init==1'b1)
tx_cred_non_posted_header_valid_x8<=1'b0;
else begin
if ((tx_cred[27:20]>0)||(tx_cred[62]==1))
tx_cred_non_posted_header_valid_x8 <= 1'b1;
else
tx_cred_non_posted_header_valid_x8 <= 1'b0;
end
end
end
end
endgenerate
assign tx_cred_non_posted_header_valid = (USE_CREDIT_CTRL==0)?1'b1:
(TXCRED_WIDTH==66)?
tx_cred_non_posted_header_valid_x8:tx_have_creds;
always @ (posedge clk_in) begin
if (init==1'b1)
tx_cred_posted_data_valid_8x<=1'b0;
else begin
if (((tx_cred[7:0]>0)||(tx_cred[TXCRED_WIDTH-6]==1'b1))&&
((tx_cred[19:8]>0)||(tx_cred[TXCRED_WIDTH-5]==1'b1)))
tx_cred_posted_data_valid_8x <= 1'b1;
else
tx_cred_posted_data_valid_8x <= 1'b0;
end
end
assign tx_cred_posted_data_valid_4x = ((tx_cred[0]==1'b1)&&(tx_cred[9:1]>0))?
1'b1:1'b0;
assign tx_cred_posted_data_valid = (USE_CREDIT_CTRL==0)?1'b1:
(TXCRED_WIDTH==66)?
tx_cred_posted_data_valid_8x:
tx_cred_posted_data_valid_4x;
//
// Transmit sinal section tx_desc, tx_dv, tx_req...
//
assign tx_ready = (((cstate_tx==START_TX) &&
(tx_cred_non_posted_header_valid==1'b1)&&
(rx_buffer_cpl_ready==1'b1)) ||
((cstate_tx==START_TX_UPD_DT)&&
(tx_cred_posted_data_valid==1'b1) ))?1'b1:1'b0;
assign tx_busy = ((cstate_tx==MRD_REQ)||(tx_dv==1'b1)||
(tx_dfr==1'b1)||(cstate_tx==MWR_REQ_UPD_DT)) ?1'b1:1'b0;
always @ (posedge clk_in or negedge rstn) begin
if (rstn==1'b0) begin
tx_req <= 1'b0;
end
else begin
if (((cstate_tx==MRD_REQ)|| (cstate_tx==MWR_REQ_UPD_DT))& ((tx_ack==1'b1) || (init==1'b1))) // deassert on tx_ack or init
tx_req <= 1'b0;
else if (((nstate_tx==MRD_REQ) & tx_cred_non_posted_header_valid) ||(nstate_tx==MWR_REQ_UPD_DT)) // assert
tx_req <= 1'b1;
end
end
assign tx_lbe_d = (tx_length_dw[9:0]==10'h1) ? 4'h0 : 4'hf;
assign tx_fbe_d = 4'hF;
assign tx_desc[127] = `RESERVED_1BIT;
wire [1:0] tx_desc_fmt_32;
wire [1:0] tx_desc_fmt_64;
assign tx_desc_fmt_32 = (ep_lastupd_cycle==1'b1)?`TLP_FMT_3DW_W:
`TLP_FMT_3DW_R;
assign tx_desc_fmt_64 = ((ep_lastupd_cycle==1'b1)&&(tx_32addr_eplast==1'b1))?`TLP_FMT_3DW_W :
((ep_lastupd_cycle==1'b1)&&(tx_32addr_eplast==1'b0))?`TLP_FMT_4DW_W:
((ep_lastupd_cycle==1'b0)&&(addrval_32b==1'b1)) ?`TLP_FMT_3DW_R:
`TLP_FMT_4DW_R;
assign tx_desc[126:0] = tx_desc_reg[126:0];
assign addrval_32b = (tx_desc_addr[63:32]==32'h0)?1'b1:1'b0;
always @ (posedge clk_in) begin
tx_desc_reg[126:125] <= (RC_64BITS_ADDR==0)?tx_desc_fmt_32:tx_desc_fmt_64;
tx_desc_reg[124:120] <= (ep_lastupd_cycle==1'b1)?`TLP_TYPE_WRITE:`TLP_TYPE_READ;
tx_desc_reg[119] <= `RESERVED_1BIT ;
tx_desc_reg[118:116] <= `TLP_TC_DEFAULT ;
tx_desc_reg[115:112] <= `RESERVED_4BIT ;
tx_desc_reg[111] <= `TLP_TD_DEFAULT ;
tx_desc_reg[110] <= `TLP_EP_DEFAULT ;
tx_desc_reg[109:108] <= `TLP_ATTR_DEFAULT ;
tx_desc_reg[107:106] <= `RESERVED_2BIT ;
tx_desc_reg[105:96] <= (ep_lastupd_cycle==1'b1)?2:tx_length_dw[9:0];
tx_desc_reg[95:80] <= `ZERO_WORD ;
tx_desc_reg[79:72] <= (ep_lastupd_cycle==1'b1)?0:tx_tag_tx_desc ;
tx_desc_reg[71:64] <= {tx_lbe_d,tx_fbe_d};
tx_desc_reg[63:0] <= (ep_lastupd_cycle==1'b1)?tx_addr_eplast:
((ep_lastupd_cycle==1'b0)&&(addrval_32b==1'b1))?{tx_desc_addr[31:0] ,32'h0}:
tx_desc_addr;
end
// Hardware performance counter
always @ (posedge clk_in) begin
if (init==1'b1)
performance_counter <= 0;
// else if ((dt_ep_last==dt_size) && (cstate_tx==MWR_ACK_UPD_DT))
else if ((dt_ep_last_eq_dt_size==1'b1) && (cstate_tx==MWR_ACK_UPD_DT))
performance_counter <= 0;
else begin
if ((requester_mrdmwr_cycle==1'b1) || (descriptor_mrd_cycle==1'b1))
performance_counter <= performance_counter+1;
else if (tx_ws==0)
performance_counter <= 0;
end
end
always @ (posedge clk_in) begin
if (init==1'b1)
requester_mrdmwr_cycle<=1'b0;
else if ((dt_fifo_empty==1'b0) && (cstate_tx==DT_FIFO))
requester_mrdmwr_cycle<=1'b1;
else if ((dt_fifo_empty==1'b1)&&(cstate_tx==DT_FIFO) &&
(tx_ws==1'b0) &&
(eplast_upd_first_descriptor==1'b0)&&
(eplast_upd_second_descriptor==1'b0))
requester_mrdmwr_cycle<=1'b0;
end
// 63:57 Indicates which board is being used
// 0 - Altera Stratix II GX x1
// 1 - Altera Stratix II GX x4
// 2 - Altera Stratix II GX x8
// 3 - Cyclone II x1
// 4 - Arria GX x1
// 5 - Arria GX x4
// 6 - Custom PHY x1
// 7 - Custom PHY x4
// When bit 56 set, indicates x8 configuration 256 Mhz back-end
// 55:53 maxpayload for MWr
// 52:48 number of lanes negocatied
// 47:32 indicates the number of the last processed descriptor
// 31:24 Number of tags
// When 52:48 number of lanes negocatied
always @ (posedge clk_in) begin
tx_data_eplast[63:57] <= BOARD_DEMO;
if (TXCRED_WIDTH>36)
tx_data_eplast[56] <= 1'b1;
else
tx_data_eplast[56] <= 1'b0;
tx_data_eplast[55:53] <= cfg_maxrdreq;
tx_data_eplast[52:49] <= cfg_link_negociated[3:0];
tx_data_eplast[48] <= dt_fifo_empty;
tx_data_eplast[47:32] <= dt_ep_last;
tx_data_eplast[31:24] <= MAX_NUMTAG;
tx_data_eplast[23:0] <= performance_counter;
end
assign tx_data = tx_data_eplast;
// Generation of tx_dfr signal
always @ (posedge clk_in) begin
if ((cstate_tx==START_TX_UPD_DT)||(cstate_tx==DT_FIFO))
tx_req_reg <= 1'b0;
else if (cstate_tx==MWR_REQ_UPD_DT)
tx_req_reg <= 1'b1;
end
always @ (posedge clk_in) begin
if (init==1'b1)
tx_req_delay<=1'b0;
else
tx_req_delay<=tx_req;
end
assign tx_dfr = tx_req & ~tx_req_reg & ep_lastupd_cycle;
// Generation of tx_dv signal
always @ (posedge clk_in) begin
if (cstate_tx==DT_FIFO)
tx_dv <= 1'b0;
else if (ep_lastupd_cycle==1'b1)
tx_dv <= (tx_dfr==1'b1) ? 1'b1 : (tx_ws==1'b0) ? 1'b0 : tx_dv; // Hold tx_dv until accepted
end
// DT_FIFO signaling
assign dt_fifo_rdreq = ((dt_fifo_empty==1'b0)&&
(cstate_tx==DT_FIFO)) ||
(cstate_tx==DT_FIFO_RD_QW0)? 1'b1:1'b0;
// DMA Write control signal msi, ep_lastena
always @ (posedge clk_in) begin
if (cstate_tx==DT_FIFO_RD_QW0) begin
cdt_msi <= dt_msi |dt_fifo_q[16];
cdt_eplast_ena <= dt_eplast_ena|dt_fifo_q[17];
if (tx_first_descriptor_cycle==1'b1) begin
cdt_msi_first_descriptor <= (dt_msi |dt_fifo_q[16]) ? 1'b1 : 1'b0;
cdt_eplast_first_descriptor <= (dt_eplast_ena |dt_fifo_q[17])? 1'b1 : 1'b0;
cdt_msi_second_descriptor <= cdt_msi_second_descriptor;
cdt_eplast_second_descriptor <= cdt_eplast_second_descriptor;
end
else begin
cdt_msi_first_descriptor <= cdt_msi_first_descriptor;
cdt_eplast_first_descriptor <= cdt_eplast_first_descriptor;
cdt_msi_second_descriptor <= (dt_msi |dt_fifo_q[16]) ? 1'b1 : 1'b0;
cdt_eplast_second_descriptor <= (dt_eplast_ena |dt_fifo_q[17])? 1'b1 : 1'b0;
end
end
end
//Section related to EPLAST rewrite
// Upadting RC memory register dt_ep_last
always @ (posedge clk_in) begin
if ((nstate_tx == START_TX_UPD_DT)||(cstate_tx == START_TX_UPD_DT)||(cstate_tx == MWR_REQ_UPD_DT))
ep_lastupd_cycle <=1'b1;
else
ep_lastupd_cycle <=1'b0;
end
//
// EP Last counter dt_ep_last : track the number of descriptor processed
//
always @ (posedge clk_in) begin
if (init==1'b1) begin
dt_ep_last <=0;
dt_ep_last_eq_dt_size <= 1'b0;
end
else begin
dt_ep_last_eq_dt_size <= (dt_ep_last==dt_size) ? 1'b1 : 1'b0;
if (cstate_tx == MWR_ACK_UPD_DT) begin
// if (dt_ep_last==dt_size)
if (dt_ep_last_eq_dt_size==1'b1)
dt_ep_last <=0;
else
dt_ep_last <=dt_ep_last+1;
end
end
end
// TX_Address Generation section : tx_desc_addr, tx_addr_eplast
// check static parameter for 64 bit vs 32 bits RC : RC_64BITS_ADDR
always @ (posedge clk_in) begin
tx_desc_addr_3dw_pipe[31:0] <= tx_desc_addr[63:32]+tx_length_byte_32ext;
end
always @ (posedge clk_in) begin
if (cstate_tx==DT_FIFO) begin
tx_desc_addr <= 0;
txadd_3dw <= 1'b1;
end
else if (RC_64BITS_ADDR==0) begin
txadd_3dw <= 1'b1;
tx_desc_addr[31:0] <= `ZERO_DWORD;
// generate tx_desc_addr
if (cstate_tx==DT_FIFO_RD_QW1)
tx_desc_addr[63:32] <= dt_fifo_q[63:32];
else if (cstate_tx==MRD_ACK)
//
tx_desc_addr[63:32]<=tx_desc_addr_3dw_pipe[31:0];
end
else begin
if (cstate_tx==DT_FIFO_RD_QW1)
// RC ADDR MSB if qword aligned
if (dt_fifo_q[31:0]==`ZERO_DWORD) begin
txadd_3dw <= 1'b1;
tx_desc_addr[63:32] <= dt_fifo_q[63:32];
tx_desc_addr[31:0] <= `ZERO_DWORD;
end
else begin
txadd_3dw <= 1'b0;
tx_desc_addr[31:0] <= dt_fifo_q[63:32];
tx_desc_addr[63:32] <= dt_fifo_q[31:0];
end
else if (cstate_tx==MRD_ACK) begin
//
if (txadd_3dw==1'b1)
tx_desc_addr[63:32] <= tx_desc_addr[63:32]+tx_length_byte_32ext;
else
tx_desc_addr <= tx_desc_addr_pipe;
end
end
end
lpm_add_sub # (
.lpm_direction ("ADD"),
.lpm_hint ( "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
.lpm_pipeline ( 2),
.lpm_type ( "LPM_ADD_SUB"),
.lpm_width ( 64))
addr64_add (
.dataa (tx_desc_addr),
.datab (tx_length_byte_64ext),
.clock (clk_in),
.result (tx_desc_addr_pipe)
// synopsys translate_off
,
.aclr (),
.add_sub (),
.cin (),
.clken (),
.cout (),
.overflow ()
// synopsys translate_on
);
// Generation of address of tx_addr_eplast and
// tx_32addr_eplast bit which indicates that this is a 32 bit address
always @ (posedge clk_in) begin
if (RC_64BITS_ADDR==0) begin
tx_32addr_eplast <=1'b1;
tx_addr_eplast[31:0] <= `ZERO_DWORD;
// generate tx_addr_eplast
if (init==1'b1)
tx_addr_eplast[63:32]<=`ZERO_DWORD;
else if (cstate_tx == DT_FIFO_RD_QW0)
tx_addr_eplast[63:32]<=dt_base_rc[31:0]+32'h0000_0008;
end
else begin
if (init==1'b1) begin
tx_32addr_eplast <=1'b1;
tx_addr_eplast<=0;
end
else if (cstate_tx == DT_FIFO_RD_QW0) begin
if (dt_3dw_rcadd==1'b1) begin
tx_32addr_eplast <=1'b1;
tx_addr_eplast[63:32] <= dt_base_rc[31:0]+
32'h0000_0008;
tx_addr_eplast[31:0] <= `ZERO_DWORD;
end
else begin
tx_32addr_eplast <=1'b0;
tx_addr_eplast <= tx_addr_eplast_pipe;
end
end
end
end
lpm_add_sub # (
.lpm_direction ("ADD"),
.lpm_hint ( "ONE_INPUT_IS_CONSTANT=YES,CIN_USED=NO"),
.lpm_pipeline ( 2),
.lpm_type ( "LPM_ADD_SUB"),
.lpm_width ( 64))
addr64_add_eplast (
.dataa (dt_base_rc),
.datab (64'h8),
.clock (clk_in),
.result (tx_addr_eplast_pipe)
// synopsys translate_off
,
.aclr (),
.add_sub (),
.cin (),
.clken (),
.cout (),
.overflow ()
// synopsys translate_on
);
always @ (posedge clk_in) begin
if (init==1'b1)
tx_mrd_cycle<=1'b0;
else begin
if (cstate_tx==DT_FIFO_RD_QW0)
tx_mrd_cycle<=1'b1;
else if (cstate_tx==CPLD)
tx_mrd_cycle<=1'b0;
end
end
assign tx_get_tag_from_fifo = (((tx_tag_mux_first_descriptor==1'b1) &&
(tx_first_descriptor_cycle==1'b1))||
((tx_tag_mux_second_descriptor==1'b1) &&
(tx_first_descriptor_cycle==1'b0)))?
1'b1:1'b0;
assign debug = (cstate_tx==DT_FIFO_RD_QW0);
// Requester Read state machine (Transmit)
// Combinatorial state transition (case state)
always @*
case (cstate_tx)
DT_FIFO:
// Descriptor FIFO - ready to read the next descriptor 4 DWORDS
begin
if (init==1'b1)
nstate_tx = DT_FIFO;
else if (dt_fifo_empty==1'b0)
nstate_tx = DT_FIFO_RD_QW0;
else if ((eplast_upd_first_descriptor==1'b1) &&
(tx_cpld_first_descriptor==1'b1) )
nstate_tx = DONE;
else if ((eplast_upd_second_descriptor==1'b1) &&
(tx_cpld_second_descriptor==1'b1) )
nstate_tx = DONE;
else
nstate_tx = DT_FIFO;
end
DT_FIFO_RD_QW0:
// set dt_fifo_rd_req for DW0
nstate_tx = DT_FIFO_RD_QW1;
DT_FIFO_RD_QW1:
// Wait for any pending MSI to issue before transmitting
if (cstate_msi==IDLE_MSI)
// set dt_fifo_rd_req for DW1
nstate_tx = MAX_RREQ_UPD;
else
nstate_tx = cstate_tx;
MAX_RREQ_UPD:
begin
if (tx_get_tag_from_fifo==1'b1)
nstate_tx = GET_TAG;
else
nstate_tx = TX_LENGTH;
end
TX_LENGTH:
nstate_tx = START_TX;
START_TX:
// Waiting for Top level arbitration (tx_sel) prior to tx MEM64_WR
begin
if ((init==1'b1)||(tx_length_dw==0))
nstate_tx = DT_FIFO;
else begin
if ((tx_sel==1'b1)&&(rx_buffer_cpl_ready==1'b1))
nstate_tx = MRD_REQ;
else
nstate_tx = START_TX;
end
end
MRD_REQ: // Read Request Assert tx_req
// Set tx_req, Waiting for tx_ack
begin
if (init==1'b1)
nstate_tx = DT_FIFO;
else if (tx_ack==1'b1)
nstate_tx = MRD_ACK;
else
nstate_tx = MRD_REQ;
end
MRD_ACK: // Read Request Ack. tx_ack
// Received tx_ack, clear tx_req, MRd next data chunk
begin
if (cdt_length_dw_tx==0)
nstate_tx = CPLD;
else if (tx_get_tag_from_fifo==1'b1)
nstate_tx = GET_TAG;
else
nstate_tx = TX_LENGTH;
end
GET_TAG:
// Retrieve a TAG from the TAG FIFO
begin
if (init==1'b1)
nstate_tx = DT_FIFO;
else if ((tag_fifo_empty_first_descriptor==1'b0) &&
(tx_first_descriptor_cycle==1'b1))
nstate_tx = TX_LENGTH;
else if ((tag_fifo_empty_second_descriptor==1'b0) &&
(tx_first_descriptor_cycle==1'b0))
nstate_tx = TX_LENGTH;
else
nstate_tx = GET_TAG;// Waiting for a new TAG from the TAG FIFO
end
CPLD:
// Waiting for completion for RX state machine (CPLD)
begin
if (init == 1'b1)
nstate_tx = DT_FIFO;
else begin
if (tx_cpld_first_descriptor==1'b0) begin
if (tx_cpld_second_descriptor==1'b1) begin
if (eplast_upd_second_descriptor==1'b1)
nstate_tx = DONE;
else
nstate_tx = DT_FIFO;
end
else
// 2 descriptor are being processed, waiting
// for the completion of at least one descriptor
nstate_tx = CPLD;
end
else begin
if (eplast_upd_first_descriptor==1'b1)
nstate_tx = DONE;
else
nstate_tx = DT_FIFO;
end
end
end
DONE:
begin
if (((msi_ready==1'b0) & (msi_busy==1'b0)) | (cdt_msi==1'b0)) begin // if MSI is enabled, wait in DONE state until msi_req can be issued by MSI sm
if ( ((cdt_eplast_first_descriptor == 1'b1) & (eplast_upd_first_descriptor==1'b1) & (tx_cpld_first_descriptor==1'b1)) |
((cdt_eplast_second_descriptor == 1'b1) & (eplast_upd_second_descriptor==1'b1) & (tx_cpld_second_descriptor==1'b1)) )
nstate_tx = START_TX_UPD_DT;
else
nstate_tx = MWR_ACK_UPD_DT;
end
else begin
nstate_tx = DONE;
end
end
// Update RC Memory for polling info with the last
// processed/completed descriptor
START_TX_UPD_DT:
// Waiting for Top level arbitration (tx_sel) prior to tx MEM64_WR
begin
if (init==1'b1)
nstate_tx = DT_FIFO;
else begin
if ((tx_sel==1'b1)&&(rx_buffer_cpl_ready==1'b1))
nstate_tx = MWR_REQ_UPD_DT;
else
nstate_tx = START_TX_UPD_DT;
end
end
MWR_REQ_UPD_DT:
// Set tx_req, Waiting for tx_ack
begin
if (init==1'b1)
nstate_tx = DT_FIFO;
else if (tx_ack==1'b1)
nstate_tx = MWR_ACK_UPD_DT;
else
nstate_tx = MWR_REQ_UPD_DT;
end
MWR_ACK_UPD_DT:
// Received tx_ack, clear tx_req
nstate_tx = DT_FIFO;
default:
nstate_tx = DT_FIFO;
endcase
// Requester Read TX machine
// Registered state state transition
always @ (negedge rstn or posedge clk_in) begin
if (rstn==1'b0)
cstate_tx <= DT_FIFO;
else
cstate_tx <= nstate_tx;
end
////////////////////////////////////////////////////////////////
//
// RX TLP Receive section
//
assign rx_fmt = rx_desc[126:125];
assign rx_type = rx_desc[124:120];
assign rx_dmard_tag = (rx_desc[47:40]>=FIRST_DMARD_TAG) ?1'b1:1'b0;
always @ (posedge clk_in) begin
if (rx_req_p0==1'b0)
rx_dmard_cpld<=1'b0;
else if ((rx_dfr==1'b1)&&(rx_fmt ==`TLP_FMT_CPLD)&&
(rx_type ==`TLP_TYPE_CPLD))
rx_dmard_cpld <=1'b1;
end
// Set/Clear rx_ack
assign rx_ack = (nstate_rx==CPLD_ACK)?1'b1:1'b0;
// Avalon streaming back pressure control
// 4 cycles response : 1 cc registered rx_ws +
// 3 cc tx_stream_ready -> tx_stream_valid
// note: for simplicity, only data phase is throttled. all
// packets received are completions with dataphases.
// the rx_data_fifo needs to have enough overhead space to absorb
// a descriptor phase (plus rx_ws latency) beyond it's almost_full
// threshold.
assign rx_ws = (CDMA_AST_RXWS_LATENCY==4)?
rx_data_fifo_almost_full & ((cstate_rx==CPLD_IDLE)|(cstate_rx==CPLD_DV)|(cstate_rx==CPLD_LAST)):
((rx_data_fifo_almost_full==1'b1) && (rx_dv==1'b1))?1'b1:1'b0;
always @ (posedge clk_in or negedge rstn ) begin
if (rstn==1'b0) begin
rx_ast_data_valid <= 1'b0;
rx_ws_ast <= 3'h0;
end
else begin
rx_ws_ast[0] <= rx_ws;
rx_ws_ast[1] <= rx_ws_ast[0];
rx_ws_ast[2] <= rx_ws_ast[1];
if (CDMA_AST_RXWS_LATENCY==2)
rx_ast_data_valid <= ~rx_ws_ast[0]; // HIPCAB streaming IF
else if (CDMA_AST_RXWS_LATENCY==4)
rx_ast_data_valid <= ~rx_ws_ast[2]; // ICM streaming IF
else
rx_ast_data_valid <= ~rx_ws_ast[0]; // illegal selection
end
end
always @ (posedge clk_in) begin
if (init==1'b1)
rx_tag[MAX_TAG_WIDTH-1:0] <=
cst_std_logic_vector_type_zero[MAX_TAG_WIDTH-1:0];
else if (valid_rx_dmard_cpld==1'b1)
rx_tag <= rx_desc[MAX_TAG_WIDTH+39:40];
end
always @ (posedge clk_in) begin
if (init==1'b1)
rx_tag_is_sec_desc<= 0;
else if (valid_rx_dmard_cpld==1'b1)
rx_tag_is_sec_desc <= rx_desc[MAX_TAG_WIDTH+39:40] > MAX_NUMTAG_VAL_FIRST_DESCRIPTOR;
end
always @ (posedge clk_in) begin
if (rx_dv_start_pulse==1'b1)
rx_length_hold <= rx_desc[105:96];
else
rx_length_hold <= rx_length_hold;
end
//////////////////////////////////////////////////////////
//
// DATA FIFO RX_DATA side management (DATA_FIFO Write)
//
assign rx_data_fifo_data[63:0] = rx_data;
assign rx_data_fifo_data[71:64] = rx_be;
assign rx_data_fifo_data[RX_DATA_FIFO_WIDTH-3:72]=
(rx_dv_start_pulse==1'b0)?rx_tag:
rx_desc[MAX_TAG_WIDTH+39:40];
assign rx_data_fifo_data[RX_DATA_FIFO_WIDTH-2] = rx_dv_start_pulse;
assign rx_data_fifo_data[RX_DATA_FIFO_WIDTH-1] = rx_dv_end_pulse;
assign rx_data_fifo_data[RX_DATA_FIFO_WIDTH]= (rx_dv_start_pulse==1'b0)? rx_tag_is_sec_desc: rx_desc[MAX_TAG_WIDTH+39:40] > MAX_NUMTAG_VAL_FIRST_DESCRIPTOR;
assign rx_data_fifo_data[RX_DATA_FIFO_WIDTH + 10 : RX_DATA_FIFO_WIDTH + 1] = (rx_dv_start_pulse==1'b0)? rx_length_hold: rx_desc[105:96];
always @ (posedge clk_in) begin
if ((rx_dfr==1'b0) || (init==1'b1))
valid_rx_dmard_cpld_next <=1'b0;
else begin
if ((rx_req_p1==1'b1) &&
(rx_dmard_tag==1'b1) &&
(rx_dmard_cpld==1'b1))
valid_rx_dmard_cpld_next <=1'b1;
else if (rx_req==1'b0)
valid_rx_dmard_cpld_next <=1'b0;
end
end
assign valid_rx_dmard_cpld =((rx_req==1'b1) &&
(((rx_req_p1==1'b1)&&(rx_dmard_tag==1'b1)&&(rx_dmard_cpld==1'b1)) ||
(valid_rx_dmard_cpld_next==1'b1)))?1'b1:1'b0;
always @ (posedge clk_in) begin
rx_dv_end_pulse_reg <= rx_dv_end_pulse;
end
always @ (posedge clk_in) begin
if (rx_dv_end_pulse_reg==1'b1)
valid_rx_dv_for_dmard <=1'b0;
else if (valid_rx_dmard_cpld_next==1'b1)
valid_rx_dv_for_dmard <=1'b1;
end
assign rx_data_fifo_sclr = (init==1'b1)?1'b1:1'b0;
generate begin
if (CDMA_AST_RXWS_LATENCY==2) begin
assign rx_data_fifo_wrreq = (((valid_rx_dmard_cpld==1'b1)||
(valid_rx_dmard_cpld_next==1'b1) ||
(valid_rx_dv_for_dmard==1'b1) )&&
(rx_ast_data_valid==1'b1)&& (rx_dv==1'b1))?1'b1:1'b0;
end
if (CDMA_AST_RXWS_LATENCY==4) begin
assign rx_data_fifo_wrreq = (((valid_rx_dmard_cpld==1'b1 )||
(valid_rx_dmard_cpld_next==1'b1)||
(valid_rx_dv_for_dmard==1'b1 ) )&&
(((rx_ast_data_valid==1'b1)&& (rx_dv==1'b1) && (rx_dfr==1'b1)) ||
((rx_dv==1'b1) && (rx_dfr==1'b0)) ))?1'b1:1'b0;
end
end
endgenerate
//////////////////////////////////////////////////////////
//
// DATA FIFO Avalon side management (DATA_FIFO Read)
//
always @ (posedge clk_in) begin
if (cstate_rx_data_fifo==SM_RX_DATA_FIFO_READ_TAGRAM_2)
tagram_data_rd_cycle <=1'b1;
else
tagram_data_rd_cycle <=1'b0;
end
always @ (posedge clk_in) begin
if ((rx_data_fifo_empty==1'b1)||(init==1'b1))
rx_data_fifo_almost_full<=1'b0;
else begin
if (rx_data_fifo_usedw>RX_DATA_FIFO_ALMST_FULL_LIM)
rx_data_fifo_almost_full<=1'b1;
else
rx_data_fifo_almost_full<=1'b0;
end
end
always @ (posedge clk_in) begin
if (init==1'b1)
rx_data_fifo_rx_tag[MAX_TAG_WIDTH-1:0] <=
cst_std_logic_vector_type_zero[MAX_TAG_WIDTH-1:0];
else if (cstate_rx_data_fifo==SM_RX_DATA_FIFO_READ_TAGRAM_1)
rx_data_fifo_rx_tag <= rx_data_fifo_q[RX_DATA_FIFO_WIDTH-3:72];
end
//////////////////////////////////////////////////////////
//
// TAGRAM Update (port b) from the CPLD section
//
assign tagram_address_b =(cstate_rx_data_fifo==SM_RX_DATA_FIFO_READ_TAGRAM_1)?
rx_data_fifo_q[RX_DATA_FIFO_WIDTH-3:72]:
rx_data_fifo_rx_tag;
always @ (posedge clk_in) begin
if (init==1'b1)
tagram_wren_b <= 1'b0;
else
tagram_wren_b <= tagram_data_rd_cycle; // Update tag info as early as possible
end
always @ (posedge clk_in) begin
if (((cstate_rx_data_fifo==SM_RX_DATA_FIFO_RREQ) &&
(rx_data_fifo_q[RX_DATA_FIFO_WIDTH-1]==1'b1))||
(cstate_rx_data_fifo==SM_RX_DATA_FIFO_SINGLE_QWORD) )
tagram_wren_b_reg_init<=1'b1;
else
tagram_wren_b_reg_init<=1'b0;
end
// base the new tagram entries on descriptor info
always @ (posedge clk_in) begin
if (rx_data_fifo_q[RX_DATA_FIFO_WIDTH-2]==1'b1)
rx_data_fifo_length_hold <= rx_data_fifo_q[RX_DATA_FIFO_WIDTH + 10 : RX_DATA_FIFO_WIDTH + 1];
end
assign rx_tag_length_dw_next = (tagram_q_b[TAG_EP_ADDR_WIDTH+9:TAG_EP_ADDR_WIDTH] < 3) ? 0 : tagram_q_b[TAG_EP_ADDR_WIDTH+9:TAG_EP_ADDR_WIDTH] - rx_data_fifo_length_hold;
assign rx_tag_addr_offset_next = tagram_q_b[TAG_EP_ADDR_WIDTH-1:0] + {rx_data_fifo_length_hold, 2'h0}; // length is in DWords, tagram address uses byte addressing
always @ (posedge clk_in) begin
rcving_last_cpl_for_tag <= rcving_last_cpl_for_tag_n;
if (tagram_data_rd_cycle==1'b1) begin
rx_tag_length_dw[9:0]<= tagram_q_b[TAG_RAM_WIDTH-1:TAG_RAM_WIDTH-10];
rx_tag_addr_offset <= tagram_q_b[TAG_EP_ADDR_WIDTH-1:0];
tagram_data_b <= {rx_tag_length_dw_next[9:0], rx_tag_addr_offset_next[TAG_EP_ADDR_WIDTH-1:0]};
tag_remaining_length <= tagram_q_b[TAG_EP_ADDR_WIDTH+9:TAG_EP_ADDR_WIDTH];
end
else begin
tag_remaining_length <= tag_remaining_length;
rx_tag_addr_offset <= rx_tag_addr_offset+8; // rx_tag_addr_offset is in bytes, but mem access is in QW so increment every access by 8 bytes.
if (rx_tag_length_dw>0) begin
if (rx_tag_length_dw==1)
rx_tag_length_dw <= 0;
else
rx_tag_length_dw <= rx_tag_length_dw-2;
end
end
end
//////////////////////////////////////////////////////////
//
// Avalon memory write
//
assign rx_data_fifo_rdreq= (cstate_rx_data_fifo==SM_RX_DATA_FIFO_IDLE)||
((rx_data_fifo_empty==1'b0) &&
(cstate_rx_data_fifo==SM_RX_DATA_FIFO_RREQ) || (cstate_rx_data_fifo==SM_RX_DATA_FIFO_SINGLE_QWORD))?
1'b1:1'b0;
always @ (posedge clk_in) begin
writedata <= rx_data_fifo_q[63:0];
write_byteena <= rx_data_fifo_q[71:64];
end
always @ (posedge clk_in) begin
if ((cstate_rx_data_fifo==SM_RX_DATA_FIFO_RREQ) ||
(cstate_rx_data_fifo==SM_RX_DATA_FIFO_SINGLE_QWORD))
write <= 1'b1;
else
write <= 1'b0;
end
always @ (posedge clk_in) begin
if (init==1'b1)
address <=0;
else begin
if (tagram_data_rd_cycle==1'b1)
address <= tagram_q_b[TAG_EP_ADDR_WIDTH-1:3]; // tagram stores byte address. Convert to QW address.
else if (write==1'b1)
address <= address+1;
end
end
// Requester Read state machine (Receive)
// Combinatorial state transition (case state)
always @*
case (cstate_rx)
CPLD_IDLE :
// Reflects the beginning of a new descriptor
begin
if (init == 1'b0)
nstate_rx = CPLD_REQ;
else
nstate_rx = CPLD_IDLE;
end
CPLD_REQ : // rx_ack upon rx_req and CPLD, and DMA Read tag
begin
if (init==1'b1)
nstate_rx = CPLD_IDLE;
else if ((rx_req_p1==1'b1) && (valid_rx_dmard_cpld_p0_reg==1'b1))
nstate_rx = CPLD_ACK;
else
nstate_rx = CPLD_REQ;
end
CPLD_ACK: // set rx_ack
nstate_rx = CPLD_DV;
CPLD_DV: // collect data for a given tag
begin
if (rx_dfr==1'b0)
nstate_rx = CPLD_LAST;
else
nstate_rx = CPLD_DV;
end
CPLD_LAST:
// Last data (rx_dfr ==0) :
begin
if (rx_dv==1'b0)
nstate_rx = CPLD_REQ;
else
nstate_rx = CPLD_LAST;
end
default:
nstate_rx = CPLD_IDLE;
endcase
// Requester Read RX machine
// Registered state state transition
always @ (negedge rstn or posedge clk_in) begin
if (rstn==1'b0) begin
cstate_rx <= DT_FIFO;
valid_rx_dmard_cpld_p0_reg <= 1'b0;
end
else begin
cstate_rx <= nstate_rx;
valid_rx_dmard_cpld_p0_reg <= (rx_req_p0==1'b1) ? (((rx_dmard_tag==1'b1)&&(rx_fmt ==`TLP_FMT_CPLD)&& (rx_type ==`TLP_TYPE_CPLD)) ? 1'b1 : 1'b0)
: valid_rx_dmard_cpld_p0_reg;
end
end
always @* begin
transferring_data_n = transferring_data;
case (cstate_rx_data_fifo)
SM_RX_DATA_FIFO_IDLE:
begin
if (rx_data_fifo_empty==1'b0)
nstate_rx_data_fifo = SM_RX_DATA_FIFO_READ_TAGRAM_1;
else
nstate_rx_data_fifo = SM_RX_DATA_FIFO_IDLE;
end
SM_RX_DATA_FIFO_READ_TAGRAM_1:
begin
if (rx_data_fifo_q[RX_DATA_FIFO_WIDTH-2]==1'b0)
nstate_rx_data_fifo = SM_RX_DATA_FIFO_IDLE;
else
nstate_rx_data_fifo = SM_RX_DATA_FIFO_READ_TAGRAM_2;
end
SM_RX_DATA_FIFO_READ_TAGRAM_2:
begin
transferring_data_n = 1'b1;
if (rx_data_fifo_q[RX_DATA_FIFO_WIDTH-1]==1'b0)
nstate_rx_data_fifo = SM_RX_DATA_FIFO_RREQ;
else
nstate_rx_data_fifo = SM_RX_DATA_FIFO_SINGLE_QWORD;
end
SM_RX_DATA_FIFO_RREQ:
begin
if (rx_data_fifo_q[RX_DATA_FIFO_WIDTH-1]==1'b1) begin
nstate_rx_data_fifo = (rx_data_fifo_empty==1'b0) ? SM_RX_DATA_FIFO_READ_TAGRAM_1 : SM_RX_DATA_FIFO_IDLE;
transferring_data_n = 1'b0;
end
else
nstate_rx_data_fifo = SM_RX_DATA_FIFO_RREQ;
end
SM_RX_DATA_FIFO_SINGLE_QWORD:
begin
nstate_rx_data_fifo = (rx_data_fifo_empty==1'b0) ? SM_RX_DATA_FIFO_READ_TAGRAM_1 : SM_RX_DATA_FIFO_IDLE;
transferring_data_n = 1'b0;
end
SM_RX_DATA_FIFO_TAGRAM_UPD:
nstate_rx_data_fifo = SM_RX_DATA_FIFO_IDLE;
default:
nstate_rx_data_fifo = SM_RX_DATA_FIFO_IDLE;
endcase
end
// RX data fifo state machine
// Registered state state transition
always @ (negedge rstn or posedge clk_in)
begin
if (rstn==1'b0) begin
cstate_rx_data_fifo <= SM_RX_DATA_FIFO_IDLE;
transferring_data <= 1'b0;
end
else begin
cstate_rx_data_fifo <= nstate_rx_data_fifo;
transferring_data <= transferring_data_n;
end
end
///////////////////////////////////////////////////////////////////////////
//
// MSI section : if (USE_MSI>0)
//
assign app_msi_req = (USE_MSI==0)?1'b0:(cstate_msi==MWR_REQ_MSI)?1'b1:1'b0;
assign msi_ready = (USE_MSI==0)?1'b0:(cstate_msi==START_MSI)?1'b1:1'b0;
assign msi_busy = (USE_MSI==0)?1'b0:(cstate_msi==MWR_REQ_MSI)?1'b1:1'b0;
always @*
case (cstate_msi)
IDLE_MSI:
begin
if ((cstate_tx==DONE)&& //(cdt_msi==1'b1))
(((cdt_msi_first_descriptor == 1'b1) & (tx_cpld_first_descriptor==1'b1)) ||
((cdt_msi_second_descriptor == 1'b1) & (tx_cpld_second_descriptor==1'b1)) ) )
nstate_msi = START_MSI;
else
nstate_msi = IDLE_MSI;
end
START_MSI:
// Waiting for Top level arbitration (tx_sel) prior to tx MEM64_WR
begin
if ((msi_sel==1'b1)&&(tx_ws==1'b0))
nstate_msi = MWR_REQ_MSI;
else
nstate_msi = START_MSI;
end
MWR_REQ_MSI:
// Set tx_req, Waiting for tx_ack
begin
if (app_msi_ack==1'b1)
nstate_msi = IDLE_MSI;
else
nstate_msi = MWR_REQ_MSI;
end
default:
nstate_msi = IDLE_MSI;
endcase
// MSI state machine
// Registered state state transition
always @ (negedge rstn or posedge clk_in)
begin
if (rstn==1'b0)
cstate_msi <= IDLE_MSI;
else
cstate_msi <= nstate_msi;
end
/////////////////////////////////////////////////////////////////////
//
// TAG Section
// Write in TAG RAM the offset of EP memory
// The TAG RAM content {tx_length_dw[9:1], tx_tag_addr_offset[AVALON_WADDR-1:0]}
// tx_length_dw[9:1] : QWORD LENGTH to know when recycle TAG
// tx_tag_addr_offset[AVALON_WADDR-1:0] : EP Address offset (where PCIE write to)
assign tagram_wren_a = ((cstate_tx==MRD_REQ)&&(tx_req==1'b1)&&
(tx_req_delay==1'b0))? 1'b1:1'b0;
assign tagram_data_a = {tx_length_dw[9:0],tx_tag_addr_offset[TAG_EP_ADDR_WIDTH-1:0]}; // tx_tag_addr_offset is in Bytes
assign tagram_address_a[MAX_TAG_WIDTH-1:0] = tx_tag_tx_desc[MAX_TAG_WIDTH-1:0];
// TX TAG Signaling FIFO TAG
// There are 2 FIFO TAGs :
// tag_scfifo_first_descriptor
// tag_scfifo_second_descriptor
// The FIFO TAG are used to recycle TAGS
// The read requester module issues MRD for
// two consecutive descriptors (first_descriptor, second descriptor)
// The TAG assignment is such
// MAX_NUMTAG : Maximum number of TAG available from the core
// TAG_TRACK_WIDTH : Number of tag for both descritpor
// TAG_TRACK_HALF_WIDTH : Number of tag for each descriptor
// The one hot register tag_track_one_hot tracks the TAG which has been
// recycled accross both descriptors
assign tag_fifo_sclr = init;
assign rcving_last_cpl_for_tag_n = (tagram_data_rd_cycle==1'b1) ? ~(tagram_q_b[TAG_EP_ADDR_WIDTH+9:TAG_EP_ADDR_WIDTH] > rx_data_fifo_length_hold) : rcving_last_cpl_for_tag;
assign got_all_cpl_for_tag = (transferring_data == 1'b1 ) &
(rcving_last_cpl_for_tag_n == 1'b1) && (rx_data_fifo_q[RX_DATA_FIFO_WIDTH-1]==1'b1); // release tag when dv_end is received, and this is the end of the last cpl expected for the tag
always @ (posedge clk_in) begin
if (init==1'b1)
tag_track_one_hot[TAG_TRACK_WIDTH-1:0]
<= cst_std_logic_vector_type_zero[TAG_TRACK_WIDTH-1:0];
else if (cstate_tx==MRD_ACK) begin
for(i=2+RC_SLAVE_USETAG;i <MAX_NUMTAG;i=i+1)
if (tx_tag_tx_desc == i)
tag_track_one_hot[i-2] <= 1'b1;
end
else if (got_all_cpl_for_tag == 1'b1) begin
for(i=2+RC_SLAVE_USETAG;i <MAX_NUMTAG;i=i+1)
if (tagram_address_b == i)
tag_track_one_hot[i-2] <= 1'b0;
end
else if (tagram_wren_b_mrd_ack==1'b1) begin
for(i=2+RC_SLAVE_USETAG;i <MAX_NUMTAG;i=i+1)
if (tagram_address_b_mrd_ack == i)
tag_track_one_hot[i-2] <= 1'b0;
end
end
//cpl_pending logic
always @ (posedge clk_in) begin
if (init==1'b1)
cpl_pending<=1'b0;
else begin
if (tag_track_one_hot[TAG_TRACK_WIDTH-1:0]>cst_std_logic_vector_type_zero[TAG_TRACK_WIDTH-1:0])
cpl_pending<=1'b1;
else
cpl_pending<=1'b0;
end
end
always @ (posedge clk_in) begin
if ((cstate_tx==MRD_ACK)&& (got_all_cpl_for_tag == 1'b1))
tagram_wren_b_mrd_ack <= 1'b1;
else
tagram_wren_b_mrd_ack <= 1'b0;
end
always @ (posedge clk_in) begin
// Hold tagram address in case conflict between setting tag and releasing tag
if ((cstate_tx==MRD_ACK)&&(got_all_cpl_for_tag == 1'b1))
tagram_address_b_mrd_ack <= tagram_address_b;
else
tagram_address_b_mrd_ack[MAX_TAG_WIDTH-1:0] <=
cst_std_logic_vector_type_zero[MAX_TAG_WIDTH-1:0];
end
assign tx_cpld_first_descriptor = (MAX_NUMTAG==4)?~tag_track_one_hot[0]:
(tag_track_one_hot[TAG_TRACK_HALF_WIDTH-1:0]==0)?1'b1:1'b0;
assign tx_cpld_second_descriptor = (MAX_NUMTAG==4)?~tag_track_one_hot[1]:
(tag_track_one_hot[TAG_TRACK_WIDTH-1:TAG_TRACK_HALF_WIDTH]==0)?1'b1:1'b0;
assign tx_fifo_rdreq_first_descriptor = ((tx_first_descriptor_cycle==1'b1) &&
(cstate_tx==GET_TAG))?1'b1:1'b0;
assign tx_fifo_rdreq_second_descriptor = ((tx_first_descriptor_cycle==1'b0)&&
(cstate_tx==GET_TAG))?1'b1:1'b0;
// TX TAG counter first descriptor
always @ (posedge clk_in) begin
if (init==1'b1)
tx_tag_cnt_first_descriptor <=
FIRST_DMARD_TAG_cst_width_eq_MAX_TAG_WIDTH;
else if ((cstate_tx==MRD_REQ)&&(tx_ack==1'b1)&&
(tx_first_descriptor_cycle==1'b1) ) begin
if (tx_tag_cnt_first_descriptor!=MAX_NUMTAG_VAL_FIRST_DESCRIPTOR)
tx_tag_cnt_first_descriptor <= tx_tag_cnt_first_descriptor+1;
end
end
always @ (posedge clk_in) begin
if (init==1'b1)
tx_tag_mux_first_descriptor <= 1'b0;
else if ((tx_tag_cnt_first_descriptor==MAX_NUMTAG_VAL_FIRST_DESCRIPTOR)&&
(cstate_tx==MRD_REQ) && (tx_ack==1'b1))
tx_tag_mux_first_descriptor <= 1'b1;
end
assign tx_tag_wire_mux_first_descriptor[MAX_TAG_WIDTH-1:0] =
(tx_tag_mux_first_descriptor == 1'b0)?
tx_tag_cnt_first_descriptor[MAX_TAG_WIDTH-1:0]:
tx_tag_fifo_first_descriptor[MAX_TAG_WIDTH-1:0];
// TX TAG counter second descriptor
always @ (posedge clk_in) begin
if (init==1'b1)
tx_tag_cnt_second_descriptor <=
FIRST_DMARD_TAG_SEC_DESCRIPTOR_cst_width_eq_MAX_TAG_WIDTH ;
else if ((tx_ack==1'b1) && (cstate_tx==MRD_REQ) &&
(tx_first_descriptor_cycle==1'b0)) begin
if (tx_tag_cnt_second_descriptor!=MAX_NUMTAG_VAL)
tx_tag_cnt_second_descriptor <= tx_tag_cnt_second_descriptor+1;
end
end
always @ (posedge clk_in) begin
if (init==1'b1)
tx_tag_mux_second_descriptor <= 1'b0;
else if ((tx_tag_cnt_second_descriptor==MAX_NUMTAG_VAL) &&
(tx_ack==1'b1) && (cstate_tx==MRD_REQ) &&
(tx_first_descriptor_cycle==1'b0) )
tx_tag_mux_second_descriptor <= 1'b1;
end
assign tx_tag_wire_mux_second_descriptor[MAX_TAG_WIDTH-1:0] =
(tx_tag_mux_second_descriptor == 1'b0)?
tx_tag_cnt_second_descriptor[MAX_TAG_WIDTH-1:0]:
tx_tag_fifo_second_descriptor[MAX_TAG_WIDTH-1:0];
always @ (posedge clk_in) begin
if (init==1'b1)
tx_tag_tx_desc <=0;
else if ((cstate_tx==TX_LENGTH) && (tx_first_descriptor_cycle==1'b1))
tx_tag_tx_desc[MAX_TAG_WIDTH-1:0] <=
tx_tag_wire_mux_first_descriptor[MAX_TAG_WIDTH-1:0];
else if ((cstate_tx==TX_LENGTH) && (tx_first_descriptor_cycle==1'b0))
tx_tag_tx_desc[MAX_TAG_WIDTH-1:0] <=
tx_tag_wire_mux_second_descriptor[MAX_TAG_WIDTH-1:0];
end
assign rx_second_descriptor_tag = rx_data_fifo_q[RX_DATA_FIFO_WIDTH];
assign rx_fifo_wrreq_first_descriptor =
( (got_all_cpl_for_tag == 1'b1) &&
(rx_second_descriptor_tag==1'b0))?1'b1:1'b0;
assign rx_fifo_wrreq_second_descriptor =
( (got_all_cpl_for_tag == 1'b1) &&
(rx_second_descriptor_tag==1'b1))?1'b1:1'b0;
always @ (posedge clk_in) begin
if (init==1'b1)
tx_first_descriptor_cycle <=1'b1;
else if ((cstate_tx==MRD_ACK) && (cdt_length_dw_tx==0))
tx_first_descriptor_cycle <= ~tx_first_descriptor_cycle;
end
always @ (posedge clk_in) begin
if (init==1'b1)
next_is_second <=1'b0;
else if (cstate_tx==MWR_ACK_UPD_DT) begin
if ((eplast_upd_first_descriptor==1'b1) &&
(eplast_upd_second_descriptor==1'b1) &&
(next_is_second==1'b0))
next_is_second <=1'b1;
else
next_is_second <=1'b0;
end
end
always @ (posedge clk_in) begin
if (init==1'b1)
eplast_upd_first_descriptor <=1'b0;
else if ((cstate_tx==MRD_ACK) && (cdt_length_dw_tx==0)
&& (tx_first_descriptor_cycle==1'b1))
eplast_upd_first_descriptor <= 1'b1;
else if ((cstate_tx==MWR_ACK_UPD_DT) &&
(tx_cpld_first_descriptor==1'b1)) begin
if (eplast_upd_second_descriptor==1'b0)
eplast_upd_first_descriptor <= 1'b0;
else if (next_is_second==1'b0)
eplast_upd_first_descriptor <= 1'b0;
end
end
always @ (posedge clk_in) begin
if (init==1'b1)
eplast_upd_second_descriptor <=1'b0;
else if ((cstate_tx==MRD_ACK)&&(cdt_length_dw_tx==0)
&& (tx_first_descriptor_cycle==1'b0))
eplast_upd_second_descriptor <= 1'b1;
else if ((cstate_tx==MWR_ACK_UPD_DT) &&
(tx_cpld_second_descriptor==1'b1)) begin
if (eplast_upd_first_descriptor==1'b0)
eplast_upd_second_descriptor <= 1'b0;
else if (next_is_second==1'b1)
eplast_upd_second_descriptor <= 1'b0;
end
end
// Pipe the TAG Fifo Write inputs for performance
always @ (posedge clk_in) begin
tagram_address_b_reg <= tagram_address_b;
if (tag_fifo_sclr==1'b1) begin
rx_fifo_wrreq_first_descriptor_reg <= 1'b0;
rx_fifo_wrreq_second_descriptor_reg <= 1'b0;
end
else begin
rx_fifo_wrreq_first_descriptor_reg <= rx_fifo_wrreq_first_descriptor;
rx_fifo_wrreq_second_descriptor_reg <= rx_fifo_wrreq_second_descriptor;
end
end
// TAG FIFO
//
scfifo # (
.add_ram_output_register ("ON") ,
.intended_device_family (INTENDED_DEVICE_FAMILY),
.lpm_numwords (TAG_FIFO_DEPTH) ,
.lpm_showahead ("OFF") ,
.lpm_type ("scfifo") ,
.lpm_width (MAX_TAG_WIDTH) ,
.lpm_widthu (MAX_TAG_WIDTHU),
.overflow_checking ("ON") ,
.underflow_checking ("ON") ,
.use_eab ("ON")
)
tag_scfifo_first_descriptor (
.clock (clk_in),
.sclr (tag_fifo_sclr ),
// RX push TAGs into TAG_FIFO
.data (tagram_address_b_reg),
.wrreq (rx_fifo_wrreq_first_descriptor_reg),
// TX pop TAGs from TAG_FIFO
.rdreq (tx_fifo_rdreq_first_descriptor),
.q (tx_tag_fifo_first_descriptor ),
.empty (tag_fifo_empty_first_descriptor),
.full (tag_fifo_full_first_descriptor )
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full (),
.usedw ()
// synopsys translate_on
);
scfifo # (
.add_ram_output_register ("ON") ,
.intended_device_family (INTENDED_DEVICE_FAMILY),
.lpm_numwords (TAG_FIFO_DEPTH),
.lpm_showahead ("OFF") ,
.lpm_type ("scfifo") ,
.lpm_width (MAX_TAG_WIDTH) ,
.lpm_widthu (MAX_TAG_WIDTHU),
.overflow_checking ("ON") ,
.underflow_checking ("ON") ,
.use_eab ("ON"),
.lpm_hint ("RAM_BLOCK_TYPE=M4K")
)
tag_scfifo_second_descriptor (
.clock (clk_in),
.sclr (tag_fifo_sclr ),
// RX push TAGs into TAG_FIFO
.data (tagram_address_b_reg),
.wrreq (rx_fifo_wrreq_second_descriptor_reg),
// TX pop TAGs from TAG_FIFO
.rdreq (tx_fifo_rdreq_second_descriptor),
.q (tx_tag_fifo_second_descriptor),
.empty (tag_fifo_empty_second_descriptor),
.full (tag_fifo_full_second_descriptor )
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full (),
.usedw ()
// synopsys translate_on
);
altsyncram # (
.address_reg_b ("CLOCK0" ),
.indata_reg_b ("CLOCK0" ),
.wrcontrol_wraddress_reg_b ("CLOCK0" ),
.intended_device_family (INTENDED_DEVICE_FAMILY),
.lpm_type ("altsyncram" ),
.numwords_a (TAG_RAM_NUMWORDS ),
.numwords_b (TAG_RAM_NUMWORDS ),
.operation_mode ("BIDIR_DUAL_PORT" ),
.outdata_aclr_a ("NONE" ),
.outdata_aclr_b ("NONE" ),
.outdata_reg_a ("CLOCK0" ),
.outdata_reg_b ("CLOCK0" ),
.power_up_uninitialized ("FALSE" ),
.read_during_write_mode_mixed_ports ("DONT_CARE" ),
.widthad_a (TAG_RAM_WIDTHAD ),
.widthad_b (TAG_RAM_WIDTHAD ),
.width_a (TAG_RAM_WIDTH ),
.width_b (TAG_RAM_WIDTH ),
.width_byteena_a (1 ),
.width_byteena_b (1 )
) tag_dpram (
.clock0 (clk_in),
// Port B is used by TX module to update the TAG
.data_a (tagram_data_a),
.wren_a (tagram_wren_a),
.address_a (tagram_address_a),
// Port B is used by RX module to update the TAG
.data_b (tagram_data_b),
.wren_b (tagram_wren_b),
.address_b (tagram_address_b),
.q_b (tagram_q_b),
.rden_b (cst_one),
.aclr0 (cst_zero),
.aclr1 (cst_zero),
.addressstall_a (cst_zero),
.addressstall_b (cst_zero),
.byteena_a (cst_std_logic_vector_type_one[0]),
.byteena_b (cst_std_logic_vector_type_one[0]),
.clock1 (cst_one),
.clocken0 (cst_one),
.clocken1 (cst_one),
.q_a ()
);
scfifo # (
.add_ram_output_register ("ON") ,
.intended_device_family (INTENDED_DEVICE_FAMILY),
.lpm_numwords (RX_DATA_FIFO_NUMWORDS),
.lpm_showahead ("OFF") ,
.lpm_type ("scfifo") ,
.lpm_width (RX_DATA_FIFO_WIDTH+11) ,
.lpm_widthu (RX_DATA_FIFO_WIDTHU),
.overflow_checking ("ON") ,
.underflow_checking ("ON") ,
.use_eab ("ON")
// .lpm_hint ("RAM_BLOCK_TYPE=M4K")
)
rx_data_fifo (
.clock (clk_in),
.sclr (rx_data_fifo_sclr ),
// RX push TAGs into TAG_FIFO
.data (rx_data_fifo_data),
.wrreq (rx_data_fifo_wrreq),
// TX pop TAGs from TAG_FIFO
.rdreq (rx_data_fifo_rdreq),
.q (rx_data_fifo_q ),
.empty (rx_data_fifo_empty),
.full (rx_data_fifo_full ),
.usedw (rx_data_fifo_usedw)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full ()
// synopsys translate_on
);
endmodule
|
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This problem shows the case of a function with no input ports,
* and also a function with a parameter (not a port).
*
* A function without an argument is an error, so this should fail.
*/
module main;
function [3:0] test;
parameter a = 3;
reg [a:0] out;
begin
out = a;
test[3:0] = out[3:0];
end
endfunction
reg [3:0] tmp;
initial begin
tmp = test();
if (tmp !== 4'b0011) begin
$display("FAILED -- tmp == %b", tmp);
$finish;
end
$display("PASSED");
end
endmodule // main
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2017 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk, d0, d1
);
input clk;
input [7:0] d0, d1;
logic [7:0] inia [1:0][3:0] = '{ '{ '0, '1, 8'hfe, 8'hed },
'{ '1, '1, 8'h11, 8'h22 }};
logic [7:0] inil [0:1][0:3] = '{ '{ '0, '1, 8'hfe, 8'hed },
'{ '1, '1, 8'h11, 8'h22 }};
logic [7:0] data [1:0][3:0];
logic [7:0] datl [0:1][0:3];
initial begin
data = '{ '{ d0, d1, 8'hfe, 8'hed },
'{ d1, d1, 8'h11, 8'h22 }};
data[0] = '{ d0, d1, 8'h19, 8'h39 };
datl = '{ '{ d0, d1, 8'hfe, 8'hed },
'{ d1, d1, 8'h11, 8'h22 }};
datl[0] = '{ d0, d1, 8'h19, 8'h39 };
`ifdef TEST_VERBOSE
$display("D=%x %x %x %x -> 39 19 x x", data[0][0], data[0][1], data[0][2], data[0][3]);
$display("D=%x %x %x %x -> ed fe x x", data[1][0], data[1][1], data[1][2], data[1][3]);
$display("L=%x %x %x %x -> x x 19 39", datl[0][0], datl[0][1], datl[0][2], datl[0][3]);
$display("L=%x %x %x %x -> x x 11 12", datl[1][0], datl[1][1], datl[1][2], datl[1][3]);
`endif
if (inia[0][0] !== 8'h22) $stop;
if (inia[0][1] !== 8'h11) $stop;
if (inia[1][0] !== 8'hed) $stop;
if (inia[1][1] !== 8'hfe) $stop;
if (inil[0][2] !== 8'hfe) $stop;
if (inil[0][3] !== 8'hed) $stop;
if (inil[1][2] !== 8'h11) $stop;
if (inil[1][3] !== 8'h22) $stop;
if (data[0][0] !== 8'h39) $stop;
if (data[0][1] !== 8'h19) $stop;
if (data[1][0] !== 8'hed) $stop;
if (data[1][1] !== 8'hfe) $stop;
if (datl[0][2] !== 8'h19) $stop;
if (datl[0][3] !== 8'h39) $stop;
if (datl[1][2] !== 8'h11) $stop;
if (datl[1][3] !== 8'h22) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// -- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Description: N-deep SRL pipeline element with generic single-channel AXI interfaces.
// Interface outputs are synchronized using ordinary flops for improved timing.
//--------------------------------------------------------------------------
// Structure:
// axic_reg_srl_fifo
// ndeep_srl
// nto1_mux
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_8_axic_reg_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg m_valid_i;
reg s_ready_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
reg [C_FIFO_WIDTH-1:0] storage_data1;
wire [C_FIFO_WIDTH-1:0] storage_data2; // Intermediate SRL data
reg load_s1;
wire load_s1_from_s2;
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
assign M_VALID = m_valid_i;
assign S_READY = C_USE_FULL ? s_ready_i : 1'b1;
assign push = (S_VALID & (C_USE_FULL ? s_ready_i : 1'b1) & (state == TWO)) | (~M_READY & S_VALID & (state == ONE));
assign pop = M_READY & (state == TWO);
assign M_MESG = storage_data1;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_MESG;
end
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (areset_d1) begin
state <= ZERO;
m_valid_i <= 1'b0;
end else begin
case (state)
// No transaction stored locally
ZERO: begin
if (S_VALID) begin
state <= ONE; // Got one so move to ONE
m_valid_i <= 1'b1;
end
end
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) begin
state <= ZERO; // Read out one so move to ZERO
m_valid_i <= 1'b0;
end else if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
m_valid_i <= 1'b1;
end
end
// TWO transaction stored locally
TWO: begin
if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
state <= ONE; // Read out one so move to ONE
m_valid_i <= 1'b1;
end
end
endcase // case (state)
end
end // always @ (posedge ACLK)
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
s_ready_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
s_ready_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_8_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (storage_data2[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_pcie_bram_7x.v
// Version : 1.11
// Description : single bram wrapper for the mb pcie block
// The bram A port is the write port
// the B port is the read port
//
//
//-----------------------------------------------------------------------------//
`timescale 1ps/1ps
module PCIEBus_pcie_bram_7x
#(
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8
parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT
parameter DOB_REG = 0, // 1 - use the output register;
// 0 - don't use the output register
parameter WIDTH = 0 // supported WIDTH's : 4, 9, 18, 36 - uses RAMB36
// 72 - uses RAMB36SDP
)
(
input user_clk_i,// user clock
input reset_i, // bram reset
input wen_i, // write enable
input [12:0] waddr_i, // write address
input [WIDTH - 1:0] wdata_i, // write data
input ren_i, // read enable
input rce_i, // output register clock enable
input [12:0] raddr_i, // read address
output [WIDTH - 1:0] rdata_o // read data
);
// map the address bits
localparam ADDR_MSB = ((WIDTH == 4) ? 12 :
(WIDTH == 9) ? 11 :
(WIDTH == 18) ? 10 :
(WIDTH == 36) ? 9 :
8
);
// set the width of the tied off low address bits
localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 :
(WIDTH == 9) ? 3 :
(WIDTH == 18) ? 4 :
(WIDTH == 36) ? 5 :
0 // for WIDTH 72 use RAMB36SDP
);
// map the data bits
localparam D_MSB = ((WIDTH == 4) ? 3 :
(WIDTH == 9) ? 7 :
(WIDTH == 18) ? 15 :
(WIDTH == 36) ? 31 :
63
);
// map the data parity bits
localparam DP_LSB = D_MSB + 1;
localparam DP_MSB = ((WIDTH == 4) ? 4 :
(WIDTH == 9) ? 8 :
(WIDTH == 18) ? 17 :
(WIDTH == 36) ? 35 :
71
);
localparam DPW = DP_MSB - DP_LSB + 1;
localparam WRITE_MODE = ((WIDTH == 72) && (!((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)))) ? "WRITE_FIRST" :
((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)) ? "WRITE_FIRST" : "NO_CHANGE";
localparam DEVICE = (IMPL_TARGET == "HARD") ? "7SERIES" : "VIRTEX6";
localparam BRAM_SIZE = "36Kb";
localparam WE_WIDTH =(DEVICE == "VIRTEX5" || DEVICE == "VIRTEX6" || DEVICE == "7SERIES") ?
((WIDTH <= 9) ? 1 :
(WIDTH > 9 && WIDTH <= 18) ? 2 :
(WIDTH > 18 && WIDTH <= 36) ? 4 :
(WIDTH > 36 && WIDTH <= 72) ? 8 :
(BRAM_SIZE == "18Kb") ? 4 : 8 ) : 8;
//synthesis translate_off
initial begin
//$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d",
// $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB);
case (WIDTH)
4,9,18,36,72:;
default:
begin
$display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH);
$finish;
end
endcase // case (WIDTH)
end
//synthesis translate_on
generate
if ((LINK_CAP_MAX_LINK_WIDTH == 6'h08 && LINK_CAP_MAX_LINK_SPEED == 4'h2) || (WIDTH == 72)) begin : use_sdp
BRAM_SDP_MACRO #(
.DEVICE (DEVICE),
.BRAM_SIZE (BRAM_SIZE),
.DO_REG (DOB_REG),
.READ_WIDTH (WIDTH),
.WRITE_WIDTH (WIDTH),
.WRITE_MODE (WRITE_MODE)
)
ramb36sdp(
.DO (rdata_o[WIDTH-1:0]),
.DI (wdata_i[WIDTH-1:0]),
.RDADDR (raddr_i[ADDR_MSB:0]),
.RDCLK (user_clk_i),
.RDEN (ren_i),
.REGCE (rce_i),
.RST (reset_i),
.WE ({WE_WIDTH{1'b1}}),
.WRADDR (waddr_i[ADDR_MSB:0]),
.WRCLK (user_clk_i),
.WREN (wen_i)
);
end // block: use_sdp
else if (WIDTH <= 36) begin : use_tdp
// use RAMB36's if the width is 4, 9, 18, or 36
BRAM_TDP_MACRO #(
.DEVICE (DEVICE),
.BRAM_SIZE (BRAM_SIZE),
.DOA_REG (0),
.DOB_REG (DOB_REG),
.READ_WIDTH_A (WIDTH),
.READ_WIDTH_B (WIDTH),
.WRITE_WIDTH_A (WIDTH),
.WRITE_WIDTH_B (WIDTH),
.WRITE_MODE_A (WRITE_MODE)
)
ramb36(
.DOA (),
.DOB (rdata_o[WIDTH-1:0]),
.ADDRA (waddr_i[ADDR_MSB:0]),
.ADDRB (raddr_i[ADDR_MSB:0]),
.CLKA (user_clk_i),
.CLKB (user_clk_i),
.DIA (wdata_i[WIDTH-1:0]),
.DIB ({WIDTH{1'b0}}),
.ENA (wen_i),
.ENB (ren_i),
.REGCEA (1'b0),
.REGCEB (rce_i),
.RSTA (reset_i),
.RSTB (reset_i),
.WEA ({WE_WIDTH{1'b1}}),
.WEB ({WE_WIDTH{1'b0}})
);
end // block: use_tdp
endgenerate
endmodule // pcie_bram_7x
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:15:25 09/05/2012
// Design Name:
// Module Name: posted_pkt_scheduler_4radios
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module posted_pkt_scheduler_4radios(
input clk,
input rst,
//interface to PCIe Endpoint Block Plus
input [2:0] max_pay_size,
//interface from/to RX data fifo
input [63:0] RX_FIFO_data,
output RX_FIFO_RDEN,
input RX_FIFO_pempty,
input [31:0] RX_TS_FIFO_data,
output RX_TS_FIFO_RDEN,
input RX_TS_FIFO_empty,
//interface from/to the 2nd RX data fifo
input [63:0] RX_FIFO_2nd_data,
output RX_FIFO_2nd_RDEN,
input RX_FIFO_2nd_pempty,
input [31:0] RX_TS_FIFO_2nd_data,
output RX_TS_FIFO_2nd_RDEN,
input RX_TS_FIFO_2nd_empty,
//interface from/to the 3rd RX data fifo
input [63:0] RX_FIFO_3rd_data,
output RX_FIFO_3rd_RDEN,
input RX_FIFO_3rd_pempty,
input [31:0] RX_TS_FIFO_3rd_data,
output RX_TS_FIFO_3rd_RDEN,
input RX_TS_FIFO_3rd_empty,
//interface from/to the 4th RX data fifo
input [63:0] RX_FIFO_4th_data,
output RX_FIFO_4th_RDEN,
input RX_FIFO_4th_pempty,
input [31:0] RX_TS_FIFO_4th_data,
output RX_TS_FIFO_4th_RDEN,
input RX_TS_FIFO_4th_empty,
//interface from/to dma ctrl wrapper
/// TX descriptor write back
input TX_desc_write_back_req,
output reg TX_desc_write_back_ack,
input [63:0] SourceAddr,
input [31:0] DestAddr,
input [23:0] FrameSize,
input [7:0] FrameControl,
input [63:0] DescAddr,
/// RX control signals
input RXEnable,
input [63:0] RXBuf_1stAddr,
input [31:0] RXBuf_1stSize,
/// RX control signals for the 2nd RX buffer
input RXEnable_2nd,
input [63:0] RXBuf_2ndAddr,
input [31:0] RXBuf_2ndSize,
/// RX control signals for the 3rd RX buffer
input RXEnable_3rd,
input [63:0] RXBuf_3rdAddr,
input [31:0] RXBuf_3rdSize,
/// RX control signals for the 4th RX buffer
input RXEnable_4th,
input [63:0] RXBuf_4thAddr,
input [31:0] RXBuf_4thSize,
//interface from/to dma write data fifo in TX engine
output reg [63:0] dma_write_data_fifo_data,
output reg dma_write_data_fifo_wren,
input dma_write_data_fifo_full,
//interface to posted pkt builder
output reg go,
input ack,
output reg [63:0] dmawad,
output [9:0] length,
//interface from a64_128_distram_p(posted header fifo)
input posted_fifo_full
// debug interface
// output reg [31:0] Debug20RX1,
//// output reg [4:0] Debug22RX3,
// output reg [31:0] Debug24RX5,
// output reg [31:0] Debug26RX7,
// output reg [31:0] Debug27RX8,
// output reg [31:0] Debug28RX9,
// output reg [31:0] Debug29RX10
);
//state machine state definitions for state
localparam IDLE = 5'b00000;
localparam TX_DESC_WRITE_BACK = 5'b00001;
localparam TX_DESC_WRITE_BACK2 = 5'b00010;
localparam TX_DESC_WRITE_BACK3 = 5'b00011;
localparam TX_DESC_WRITE_BACK4 = 5'b00100;
localparam WAIT_FOR_ACK = 5'b00101;
localparam RX_PACKET = 5'b00110;
localparam RX_PACKET2 = 5'b00111;
localparam RX_PACKET3 = 5'b01000;
localparam RX_PACKET4 = 5'b01001;
localparam RX_PACKET5 = 5'b01010;
localparam RX_PACKET6 = 5'b01011;
localparam RX_PACKET_WAIT_FOR_ACK = 5'b01100;
localparam RX_DESC_WAIT = 5'b10011;
localparam RX_DESC = 5'b01101;
localparam RX_DESC2 = 5'b01110;
localparam RX_CLEAR = 5'b10000;
localparam RX_CLEAR2 = 5'b11111;
localparam RX_CLEAR_WAIT_FOR_ACK = 5'b10101;
localparam RX_CLEAR_WAIT = 5'b11100;
reg [4:0] state;
localparam RX_FRAME_SIZE_BYTES = 13'h0070; // data frame size is 112 bytes
localparam TX_DESC_SIZE_BYTES = 13'h0020; // TX descriptor size is 32 bytes
localparam RX_DESC_SIZE_BYTES = 13'h0010; // RX descriptor size is 16 bytes
// Signals for RoundRobin scheduling, two RX paths, pending
// reg Current_Path; // 0: Current path is RX FIFO 1; 1: Current path is RX FIFO 2
// Signals for RoundRobin scheduling, four RX paths
reg [1:0] pathindex_inturn; // 00: path 1; 01: path 2; 10: path 3; 11: path 4
reg RX_FIFO_RDEN_cntl; // read RX FIFO signal, we use one state machine for all the FIFOs, pathindex_inturn
// is used to select one of the RX FIFOs
reg RX_TS_FIFO_RDEN_cntl; // read RX TS FIFO signal, we use one state machine for all the FIFOs, pathindex_inturn
// is used to select one of the RX FIFOs
wire [31:0] RX_TS_FIFO_data_cntl;
reg [13:0] cnt; // counter for RX data
reg [63:0] fifo_data_pipe; // pipeline data register between RX fifo and
// dma write data fifo, also swap the upper and lower
// DW
reg [12:0] length_byte; // output posted packet length
////////////// RX Path 1 //////////////////////
reg buf_inuse; // whether this RX Buf is in use
reg [31:0] RoundNumber; // indicates how many rounds we have wroten in RX buffer
reg [31:0] RoundNumber_next;
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] dmawad_now1_1st, dmawad_now2_1st;
reg [63:0] dmawad_next_1st; // next RX data destination address
// reg [63:0] dmawad_desc; // current rx descriptor address
// Pipeline registers
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] RXBuf_1stAddr_r1, RXBuf_1stAddr_r2;
reg [31:0] RXBuf_1stSize_r;
////////////// RX Path 2 //////////////////////
reg buf_inuse_2nd; // whether this RX Buf is in use
reg [31:0] RoundNumber_2nd; // indicates how many rounds we have wroten in RX buffer
reg [31:0] RoundNumber_next_2nd;
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] dmawad_now1_2nd, dmawad_now2_2nd;
reg [63:0] dmawad_next_2nd; // next RX data destination address
// reg [63:0] dmawad_desc_2nd; // current rx descriptor address
// Pipeline registers
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] RXBuf_2ndAddr_r1, RXBuf_2ndAddr_r2;
reg [31:0] RXBuf_2ndSize_r;
////////////// RX Path 3 //////////////////////
reg buf_inuse_3rd; // whether this RX Buf is in use
reg [31:0] RoundNumber_3rd; // indicates how many rounds we have wroten in RX buffer
reg [31:0] RoundNumber_next_3rd;
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] dmawad_now1_3rd, dmawad_now2_3rd;
reg [63:0] dmawad_next_3rd; // next RX data destination address
// reg [63:0] dmawad_desc_3rd; // current rx descriptor address
// Pipeline registers
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] RXBuf_3rdAddr_r1, RXBuf_3rdAddr_r2;
reg [31:0] RXBuf_3rdSize_r;
////////////// RX Path 4 //////////////////////
reg buf_inuse_4th; // whether this RX Buf is in use
reg [31:0] RoundNumber_4th; // indicates how many rounds we have wroten in RX buffer
reg [31:0] RoundNumber_next_4th;
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] dmawad_now1_4th, dmawad_now2_4th;
reg [63:0] dmawad_next_4th; // next RX data destination address
// reg [63:0] dmawad_desc_4th; // current rx descriptor address
// Pipeline registers
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] RXBuf_4thAddr_r1, RXBuf_4thAddr_r2;
reg [31:0] RXBuf_4thSize_r;
reg rst_reg;
always@(posedge clk) rst_reg <= rst;
// // Debug register
// always@(posedge clk)begin
// Debug20RX1[3:0] <= state[3:0];
// Debug20RX1[7:4] <= {3'b000,buf_inuse};
// Debug20RX1[23:8] <= {3'b000,length_byte[12:0]};
// Debug20RX1[27:24] <= {1'b0,max_pay_size};
// Debug20RX1[31:28] <= {3'b000,posted_fifo_full};
// end
//
//// always@(posedge clk)begin
//// Debug22RX3[3:0] <= {3'b000,dma_write_data_fifo_full};
//// Debug22RX3[4] <= RX_FIFO_pempty;
//// end
//
// always@(posedge clk)begin
// if (rst)
// Debug24RX5[31:0] <= 32'h0000_0000;
// else begin
// if (RX_FIFO_RDEN)
// Debug24RX5 <= Debug24RX5 + 8'h0000_0001;
// else
// Debug24RX5 <= Debug24RX5;
// end
// end
//
// always@(posedge clk)begin
// if(rst)
// Debug26RX7 <= 32'h0000_0000;
// else if (dma_write_data_fifo_wren)
// Debug26RX7 <= Debug26RX7 + 32'h0000_0001;
// else
// Debug26RX7 <= Debug26RX7;
// end
//
// always@(posedge clk)begin
// if (rst)
// Debug27RX8 <= 32'h0000_0000;
// else if (state == RX_PACKET)
// Debug27RX8 <= Debug27RX8 + 32'h0000_0001;
// else
// Debug27RX8 <= Debug27RX8;
// end
//
// always@(posedge clk)begin
// Debug28RX9 <= dmawad[31:0];
// Debug29RX10 <= dmawad[63:32];
// end
// pipeline registers for RX path 1
always@(posedge clk)begin
RXBuf_1stAddr_r1 <= RXBuf_1stAddr;
RXBuf_1stAddr_r2 <= RXBuf_1stAddr;
RXBuf_1stSize_r <= RXBuf_1stSize;
end
// pipeline registers for RX path 2
always@(posedge clk)begin
RXBuf_2ndAddr_r1 <= RXBuf_2ndAddr;
RXBuf_2ndAddr_r2 <= RXBuf_2ndAddr;
RXBuf_2ndSize_r <= RXBuf_2ndSize;
end
// pipeline registers for RX path 3
always@(posedge clk)begin
RXBuf_3rdAddr_r1 <= RXBuf_3rdAddr;
RXBuf_3rdAddr_r2 <= RXBuf_3rdAddr;
RXBuf_3rdSize_r <= RXBuf_3rdSize;
end
// pipeline registers for RX path 4
always@(posedge clk)begin
RXBuf_4thAddr_r1 <= RXBuf_4thAddr;
RXBuf_4thAddr_r2 <= RXBuf_4thAddr;
RXBuf_4thSize_r <= RXBuf_4thSize;
end
wire [12:0] frame_size_bytes; // RX data frame size, min(RX_FRAME_SIZE_BYTES, max_pay_size_bytes)
wire [12:0] max_pay_size_bytes; // max payload size from pcie core
//calculate the max payload size in bytes for ease of calculations
//instead of the encoding as specified
//in the PCI Express Base Specification
assign max_pay_size_bytes =13'h0001<<(max_pay_size+7);
assign frame_size_bytes = (RX_FRAME_SIZE_BYTES <= max_pay_size_bytes) ? RX_FRAME_SIZE_BYTES :
max_pay_size_bytes;
//generate TX_desc_write_back_ack signal
always@(posedge clk) begin
if (rst_reg)
TX_desc_write_back_ack <= 1'b0;
else if (state == TX_DESC_WRITE_BACK)
TX_desc_write_back_ack <= 1'b1;
else
TX_desc_write_back_ack <= 1'b0;
end
/// Jiansong: pipeline data register between RX fifo and
/// dma write data fifo, also swap the upper and lower DW
//always@(posedge clk) fifo_data_pipe[63:0] <= {RX_FIFO_data[31:0],RX_FIFO_data[63:32]};
// always@(posedge clk) fifo_data_pipe[63:0] <= (~Current_Path) ?
// {RX_FIFO_data[15:0],RX_FIFO_data[31:16],
// RX_FIFO_data[47:32],RX_FIFO_data[63:48]} :
// {RX_FIFO_2nd_data[15:0],RX_FIFO_2nd_data[31:16],
// RX_FIFO_2nd_data[47:32],RX_FIFO_2nd_data[63:48]};
always@(posedge clk) fifo_data_pipe[63:0] <= (pathindex_inturn[1] == 1'b0) ?
( (pathindex_inturn[0] == 1'b0) ?
{RX_FIFO_data[15:0],RX_FIFO_data[31:16],
RX_FIFO_data[47:32],RX_FIFO_data[63:48]} :
{RX_FIFO_2nd_data[15:0],RX_FIFO_2nd_data[31:16],
RX_FIFO_2nd_data[47:32],RX_FIFO_2nd_data[63:48]}
)
: ( (pathindex_inturn[0] == 1'b0) ?
{RX_FIFO_3rd_data[15:0],RX_FIFO_3rd_data[31:16],
RX_FIFO_3rd_data[47:32],RX_FIFO_3rd_data[63:48]} :
{RX_FIFO_4th_data[15:0],RX_FIFO_4th_data[31:16],
RX_FIFO_4th_data[47:32],RX_FIFO_4th_data[63:48]}
);
// assign RX_FIFO_RDEN = Current_Path & RX_FIFO_RDEN_cntl;
// assign RX_FIFO_2nd_RDEN = (~Current_Path) & RX_FIFO_RDEN_cntl;
assign RX_FIFO_RDEN = (pathindex_inturn == 2'b00) & RX_FIFO_RDEN_cntl;
assign RX_FIFO_2nd_RDEN = (pathindex_inturn == 2'b01) & RX_FIFO_RDEN_cntl;
assign RX_FIFO_3rd_RDEN = (pathindex_inturn == 2'b10) & RX_FIFO_RDEN_cntl;
assign RX_FIFO_4th_RDEN = (pathindex_inturn == 2'b11) & RX_FIFO_RDEN_cntl;
assign RX_TS_FIFO_RDEN = (pathindex_inturn == 2'b00) & RX_TS_FIFO_RDEN_cntl;
assign RX_TS_FIFO_2nd_RDEN = (pathindex_inturn == 2'b01) & RX_TS_FIFO_RDEN_cntl;
assign RX_TS_FIFO_3rd_RDEN = (pathindex_inturn == 2'b10) & RX_TS_FIFO_RDEN_cntl;
assign RX_TS_FIFO_4th_RDEN = (pathindex_inturn == 2'b11) & RX_TS_FIFO_RDEN_cntl;
assign RX_TS_FIFO_data_cntl[31:0] = (pathindex_inturn[1] == 1'b0) ?
( (pathindex_inturn[0] == 1'b0) ? RX_TS_FIFO_data[31:0] : RX_TS_FIFO_2nd_data[31:0] )
: ( (pathindex_inturn[0] == 1'b0) ? RX_TS_FIFO_3rd_data[31:0] : RX_TS_FIFO_4th_data[31:0] );
//main state machine
always@ (posedge clk) begin
if (rst_reg) begin
state <= IDLE;
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b0;
dma_write_data_fifo_data <= 64'h0000_0000_0000_0000;
go <= 1'b0;
buf_inuse <= 1'b0;
buf_inuse_2nd <= 1'b0;
buf_inuse_3rd <= 1'b0;
buf_inuse_4th <= 1'b0;
pathindex_inturn <= 2'b00;
cnt <= 13'h0000;
end else begin
case (state)
IDLE : begin
cnt <= 13'h0000;
go <= 1'b0;
RX_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b0;
dma_write_data_fifo_data <= 64'h0000_0000_0000_0000;
// check if need to generate a posted packet
if(~posted_fifo_full & ~dma_write_data_fifo_full) begin
if(TX_desc_write_back_req)
state <= TX_DESC_WRITE_BACK;
else begin
casex({ pathindex_inturn[1:0],
((~RX_FIFO_pempty)&(~RX_TS_FIFO_empty)),
((~RX_FIFO_2nd_pempty)&(~RX_TS_FIFO_2nd_empty)),
((~RX_FIFO_3rd_pempty)&(~RX_TS_FIFO_3rd_empty)),
((~RX_FIFO_4th_pempty)&(~RX_TS_FIFO_4th_empty)) })
6'b00_1xxx, 6'b01_1000, 6'b10_1x00, 6'b11_1xx0: begin // path1's turn
pathindex_inturn <= 2'b00;
buf_inuse <= 1'b1;
cnt <= frame_size_bytes;
RX_TS_FIFO_RDEN_cntl <= 1'b1;
state <= RX_CLEAR;
end
6'b00_01xx, 6'b01_x1xx, 6'b10_0100, 6'b11_01x0: begin // path2's turn
pathindex_inturn <= 2'b01;
buf_inuse_2nd <= 1'b1;
cnt <= frame_size_bytes;
RX_TS_FIFO_RDEN_cntl <= 1'b1;
state <= RX_CLEAR;
end
6'b00_001x, 6'b01_x01x, 6'b10_xx1x, 6'b11_0010: begin // path3's turn
pathindex_inturn <= 2'b10;
buf_inuse_3rd <= 1'b1;
cnt <= frame_size_bytes;
RX_TS_FIFO_RDEN_cntl <= 1'b1;
state <= RX_CLEAR;
end
6'b00_0001, 6'b01_x001, 6'b10_xx01, 6'b11_xxx1: begin // path4's turn
pathindex_inturn <= 2'b11;
buf_inuse_4th <= 1'b1;
cnt <= frame_size_bytes;
RX_TS_FIFO_RDEN_cntl <= 1'b1;
state <= RX_CLEAR;
end
default: begin // IDLE state
RX_TS_FIFO_RDEN_cntl <= 1'b1;
state <= IDLE;
end
endcase
// case({Path_Priority, ~RX_FIFO_pempty, ~RX_FIFO_2nd_pempty})
// 3'b010, 3'b011, 3'b110: begin
// Current_Path <= 1'b0;
// buf_inuse <= 1'b0;
// cnt <= frame_size_bytes;
// state <= RX_CLEAR;
// end
// 3'b101, 3'b111, 3'b001: begin
// Current_Path <= 1'b1;
// buf_inuse_2nd <= 1'b0;
// cnt <= frame_size_bytes;
// state <= RX_CLEAR;
// end
// 3'b000, 3'b100: begin
// state <= IDLE;
// end
// endcase
end
end else
state <= IDLE;
end
// start TX desc write back flow
TX_DESC_WRITE_BACK : begin // write TX descriptor into dma write data fifo
go <= 1'b0;
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b1;
// TimeStamp(4B), TXStatus(2B), CRC(2B)
dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
state <= TX_DESC_WRITE_BACK2;
end
TX_DESC_WRITE_BACK2 : begin
go <= 1'b0;
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b1;
// SourceAddr(8B)
dma_write_data_fifo_data[63:0] <= SourceAddr;
state <= TX_DESC_WRITE_BACK3;
end
TX_DESC_WRITE_BACK3 : begin
go <= 1'b0;
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b1;
// NextDesc(4B), DestAddr(4B)
dma_write_data_fifo_data[63:0] <= {32'h0000_0000,DestAddr};
state <= TX_DESC_WRITE_BACK4;
end
TX_DESC_WRITE_BACK4 : begin
go <= 1'b1;
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b1;
// Reserved(4B), FrameControl, FrameSize(3B)
dma_write_data_fifo_data[63:0] <= {32'h0000_0000,FrameControl,FrameSize};
state <= WAIT_FOR_ACK;
end
WAIT_FOR_ACK : begin
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b0;
dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
if(ack) begin
go <= 1'b0;
state <= IDLE;
end else begin
go <= 1'b1;
state <= WAIT_FOR_ACK;
end
end
// start of a clear next desc -> generate RX packet -> write des flow,
// clear RX descriptor of next block
RX_CLEAR : begin
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
go <= 1'b0;
dma_write_data_fifo_wren <= 1'b1;
// clear RX desc
dma_write_data_fifo_data[63:0] <= {64'h0000_0000_0000_0000};
state <= RX_CLEAR2;
end
RX_CLEAR2 : begin
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
go <= 1'b1;
dma_write_data_fifo_wren <= 1'b1;
// write round number in RX desc. In case it's the head of RX buffer,
// RoundNumber could be old
// dma_write_data_fifo_data[63:0] <= {32'h0000_0000,RoundNumber};
dma_write_data_fifo_data[63:0] <= {RX_TS_FIFO_data_cntl[31:0]+32'h0000_001C,RoundNumber[31:0]};
state <= RX_CLEAR_WAIT_FOR_ACK;
end
RX_CLEAR_WAIT_FOR_ACK : begin
// RX_FIFO_RDEN <= 1'b0; // this is a modification here, previously (in SISO), we read out the first data in IDLE state
dma_write_data_fifo_wren <= 1'b0;
dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
if(ack) begin
go <= 1'b0;
if (~posted_fifo_full & ~dma_write_data_fifo_full) begin
RX_FIFO_RDEN_cntl <= 1'b1;
state <= RX_PACKET;
end else begin
RX_FIFO_RDEN_cntl <= 1'b0;
state <= RX_CLEAR_WAIT;
end
end else begin
go <= 1'b1;
RX_FIFO_RDEN_cntl <= 1'b0;
state <= RX_CLEAR_WAIT_FOR_ACK;
end
end
RX_CLEAR_WAIT : begin
RX_TS_FIFO_RDEN_cntl <= 1'b0;
if (~posted_fifo_full & ~dma_write_data_fifo_full) begin
RX_FIFO_RDEN_cntl <= 1'b1;
state <= RX_PACKET;
end else begin
RX_FIFO_RDEN_cntl <= 1'b0;
state <= RX_CLEAR_WAIT;
end
end
// start of RX packet generation flow
RX_PACKET : begin
go <= 1'b0;
cnt <= cnt - 13'h0008;
RX_FIFO_RDEN_cntl <= 1'b1;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b0;
dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
state <= RX_PACKET2;
end
RX_PACKET2 : begin
go <= 1'b0;
cnt <= cnt - 13'h0008;
RX_FIFO_RDEN_cntl <= 1'b1;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b0;
dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
//// fifo_data_pipe[63:0] <= {RX_FIFO_data[31:0],RX_FIFO_data[63:32]};
state <= RX_PACKET3;
end
RX_PACKET3 : begin
go <= 1'b0;
RX_FIFO_RDEN_cntl <= 1'b1;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b1;
//// fifo_data_pipe[63:0] <= {RX_FIFO_data[31:0],RX_FIFO_data[63:32]};
dma_write_data_fifo_data[63:0] <= fifo_data_pipe[63:0];
if (cnt == 13'h0010) begin
state <= RX_PACKET4;
end else begin
cnt <= cnt - 13'h0008;
state <= RX_PACKET3;
end
end
RX_PACKET4 : begin
go <= 1'b0;
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b1;
//// fifo_data_pipe[63:0] <= {RX_FIFO_data[31:0],RX_FIFO_data[63:32]};
dma_write_data_fifo_data[63:0] <= fifo_data_pipe[63:0];
state <= RX_PACKET5;
end
RX_PACKET5 : begin
go <= 1'b0;
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b1;
//// fifo_data_pipe[63:0] <= {RX_FIFO_data[31:0],RX_FIFO_data[63:32]};
dma_write_data_fifo_data[63:0] <= fifo_data_pipe[63:0];
state <= RX_PACKET6;
end
RX_PACKET6 : begin
go <= 1'b1;
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b1;
//// fifo_data_pipe[63:0] <= {RX_FIFO_data[31:0],RX_FIFO_data[63:32]};
dma_write_data_fifo_data[63:0] <= fifo_data_pipe[63:0];
state <= RX_PACKET_WAIT_FOR_ACK;
end
RX_PACKET_WAIT_FOR_ACK : begin
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b0;
dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
if(ack) begin
go <= 1'b0;
if (~posted_fifo_full & ~dma_write_data_fifo_full)
state <= RX_DESC;
else
state <= RX_DESC_WAIT;
end else begin
go <= 1'b1;
state <= RX_PACKET_WAIT_FOR_ACK;
end
end
RX_DESC_WAIT : begin
RX_TS_FIFO_RDEN_cntl <= 1'b0;
if (~posted_fifo_full & ~dma_write_data_fifo_full)
state <= RX_DESC;
else
state <= RX_DESC_WAIT;
end
// start of RX desc flow
RX_DESC : begin
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
go <= 1'b0;
dma_write_data_fifo_wren <= 1'b1;
// data will be swapped later
// dma_write_data_fifo_data[63:0] <= {56'h00_0000_0000_0000,8'h01};
dma_write_data_fifo_data[63:0] <= 64'hFFFF_FFFF_FFFF_FFFF;
state <= RX_DESC2;
end
RX_DESC2 : begin
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
go <= 1'b1;
dma_write_data_fifo_wren <= 1'b1;
// dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
// Write Round number in RX desc. It's used as debug info
// dma_write_data_fifo_data[63:0] <= {32'h0000_0000,RoundNumber};
dma_write_data_fifo_data[63:0] <= {RX_TS_FIFO_data_cntl[31:0],RoundNumber[31:0]};
state <= WAIT_FOR_ACK;
end
default: begin
go <= 1'b0;
RX_FIFO_RDEN_cntl <= 1'b0;
RX_TS_FIFO_RDEN_cntl <= 1'b0;
dma_write_data_fifo_wren <= 1'b0;
dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
state <= IDLE;
end
endcase
end
end
// update dmawad_next_1st and RoundNumber_next for RX path 1
always@(posedge clk) begin
if(~buf_inuse | rst_reg) begin
dmawad_next_1st <= RXBuf_1stAddr_r1;
RoundNumber_next <= 32'h0000_0000;
end else if ((state == RX_PACKET3) && (pathindex_inturn[1:0] == 2'b00)) begin
// if end of RX buf is arrived, dmawad_next_1st will return to start address at next cycle
// if((dmawad_now2_1st + 64'h0000_0000_0000_0080) == (RXBuf_1stAddr_r2+RXBuf_1stSize_r))
if((dmawad_now2_1st + 64'h0000_0000_0000_0080) >= (RXBuf_1stAddr_r2+RXBuf_1stSize_r)) begin
dmawad_next_1st <= RXBuf_1stAddr_r1;
RoundNumber_next <= RoundNumber + 32'h0000_0001;
end else begin
dmawad_next_1st <= dmawad_now1_1st + 64'h0000_0000_0000_0080;
RoundNumber_next <= RoundNumber_next;
end
end else begin
dmawad_next_1st <= dmawad_next_1st;
RoundNumber_next <= RoundNumber_next;
end
end
// update dmawad_next_2nd and RoundNumber_next_2nd for RX path 2
always@(posedge clk) begin
if(~buf_inuse_2nd | rst_reg) begin
dmawad_next_2nd <= RXBuf_2ndAddr_r1;
RoundNumber_next_2nd <= 32'h0000_0000;
end else if ((state == RX_PACKET3) && (pathindex_inturn[1:0] == 2'b01)) begin
// if end of RX buf is arrived, dmawad_next will return to start address at next cycle
// if((dmawad_now2_1st + 64'h0000_0000_0000_0080) == (RXBuf_1stAddr_r2+RXBuf_1stSize_r))
if((dmawad_now2_2nd + 64'h0000_0000_0000_0080) >= (RXBuf_2ndAddr_r2+RXBuf_2ndSize_r)) begin
dmawad_next_2nd <= RXBuf_2ndAddr_r1;
RoundNumber_next_2nd <= RoundNumber_2nd + 32'h0000_0001;
end else begin
dmawad_next_2nd <= dmawad_now1_2nd + 64'h0000_0000_0000_0080;
RoundNumber_next_2nd <= RoundNumber_next_2nd;
end
end else begin
dmawad_next_2nd <= dmawad_next_2nd;
RoundNumber_next_2nd <= RoundNumber_next_2nd;
end
end
// update dmawad_next_3rd and RoundNumber_next_3rd for RX path 3
always@(posedge clk) begin
if(~buf_inuse_3rd | rst_reg) begin
dmawad_next_3rd <= RXBuf_3rdAddr_r1;
RoundNumber_next_3rd <= 32'h0000_0000;
end else if ((state == RX_PACKET3) && (pathindex_inturn[1:0] == 2'b10)) begin
// if end of RX buf is arrived, dmawad_next will return to start address at next cycle
// if((dmawad_now2 + 64'h0000_0000_0000_0080) == (RXBufAddr_r2+RXBufSize_r))
if((dmawad_now2_3rd + 64'h0000_0000_0000_0080) >= (RXBuf_3rdAddr_r2+RXBuf_3rdSize_r)) begin
dmawad_next_3rd <= RXBuf_3rdAddr_r1;
RoundNumber_next_3rd <= RoundNumber_3rd + 32'h0000_0001;
end else begin
dmawad_next_3rd <= dmawad_now1_3rd + 64'h0000_0000_0000_0080;
RoundNumber_next_3rd <= RoundNumber_next_3rd;
end
end else begin
dmawad_next_3rd <= dmawad_next_3rd;
RoundNumber_next_3rd <= RoundNumber_next_3rd;
end
end
// update dmawad_next_2nd and RoundNumber_next_2nd for RX path 4
always@(posedge clk) begin
if(~buf_inuse_4th | rst_reg) begin
dmawad_next_4th <= RXBuf_4thAddr_r1;
RoundNumber_next_4th <= 32'h0000_0000;
end else if ((state == RX_PACKET3) && (pathindex_inturn[1:0] == 2'b11)) begin
// if end of RX buf is arrived, dmawad_next will return to start address at next cycle
// if((dmawad_now2 + 64'h0000_0000_0000_0080) == (RXBufAddr_r2+RXBufSize_r))
if((dmawad_now2_4th + 64'h0000_0000_0000_0080) >= (RXBuf_4thAddr_r2+RXBuf_4thSize_r)) begin
dmawad_next_4th <= RXBuf_4thAddr_r1;
RoundNumber_next_4th <= RoundNumber_4th + 32'h0000_0001;
end else begin
dmawad_next_4th <= dmawad_now1_4th + 64'h0000_0000_0000_0080;
RoundNumber_next_4th <= RoundNumber_next_4th;
end
end else begin
dmawad_next_4th <= dmawad_next_4th;
RoundNumber_next_4th <= RoundNumber_next_4th;
end
end
// update dmawad_now for RX path 1
always@(posedge clk)begin
if(state == IDLE)begin
dmawad_now1_1st <= dmawad_next_1st;
dmawad_now2_1st <= dmawad_next_1st;
RoundNumber <= RoundNumber_next;
end else begin
dmawad_now1_1st <= dmawad_now1_1st;
dmawad_now2_1st <= dmawad_now2_1st;
RoundNumber <= RoundNumber;
end
end
// update dmawad_now_2nd for RX path 2
always@(posedge clk)begin
if(state == IDLE)begin
dmawad_now1_2nd <= dmawad_next_2nd;
dmawad_now2_2nd <= dmawad_next_2nd;
RoundNumber_2nd <= RoundNumber_next_2nd;
end else begin
dmawad_now1_2nd <= dmawad_now1_2nd;
dmawad_now2_2nd <= dmawad_now2_2nd;
RoundNumber_2nd <= RoundNumber_2nd;
end
end
// update dmawad_now_3rd for RX path 3
always@(posedge clk)begin
if(state == IDLE)begin
dmawad_now1_3rd <= dmawad_next_3rd;
dmawad_now2_3rd <= dmawad_next_3rd;
RoundNumber_3rd <= RoundNumber_next_3rd;
end else begin
dmawad_now1_3rd <= dmawad_now1_3rd;
dmawad_now2_3rd <= dmawad_now2_3rd;
RoundNumber_3rd <= RoundNumber_3rd;
end
end
// update dmawad_now_4th for RX path 4
always@(posedge clk)begin
if(state == IDLE)begin
dmawad_now1_4th <= dmawad_next_4th;
dmawad_now2_4th <= dmawad_next_4th;
RoundNumber_4th <= RoundNumber_next_4th;
end else begin
dmawad_now1_4th <= dmawad_now1_4th;
dmawad_now2_4th <= dmawad_now2_4th;
RoundNumber_4th <= RoundNumber_4th;
end
end
// dmawad output
always@(posedge clk) begin
if(rst_reg) begin
dmawad <= 64'h0000_0000_0000_0000;
end else if (state == TX_DESC_WRITE_BACK) begin
dmawad <= DescAddr;
end else if (state == RX_CLEAR) begin
if (pathindex_inturn[1] == 1'b0) begin
if (pathindex_inturn[0] == 1'b0) begin // pathindex_inturn == 2'b00
if((dmawad_now2_1st + 64'h0000_0000_0000_0080) >= (RXBuf_1stAddr_r2+RXBuf_1stSize_r)) begin
dmawad <= RXBuf_1stAddr_r1;
end else begin
dmawad <= dmawad_now1_1st + 64'h0000_0000_0000_0080;
end
end else begin // pathindex_inturn == 2'b01
if((dmawad_now2_2nd + 64'h0000_0000_0000_0080) >= (RXBuf_2ndAddr_r2+RXBuf_2ndSize_r)) begin
dmawad <= RXBuf_2ndAddr_r1;
end else begin
dmawad <= dmawad_now1_2nd + 64'h0000_0000_0000_0080;
end
end
end else begin
if (pathindex_inturn[0] == 1'b0) begin // pathindex_inturn == 2'b10
if((dmawad_now2_3rd + 64'h0000_0000_0000_0080) >= (RXBuf_3rdAddr_r2+RXBuf_3rdSize_r)) begin
dmawad <= RXBuf_3rdAddr_r1;
end else begin
dmawad <= dmawad_now1_3rd + 64'h0000_0000_0000_0080;
end
end else begin // pathindex_inturn == 2'b11
if((dmawad_now2_4th + 64'h0000_0000_0000_0080) >= (RXBuf_4thAddr_r2+RXBuf_4thSize_r)) begin
dmawad <= RXBuf_4thAddr_r1;
end else begin
dmawad <= dmawad_now1_4th + 64'h0000_0000_0000_0080;
end
end
end
end else if (state == RX_PACKET) begin // calculation
dmawad <= (pathindex_inturn[1] == 1'b0) ?
( (pathindex_inturn[0] == 1'b0) ?
dmawad_now1_1st + 64'h0000_0000_0000_0010 : dmawad_now1_2nd + 64'h0000_0000_0000_0010
)
: ( (pathindex_inturn[0] == 1'b0) ?
dmawad_now1_3rd + 64'h0000_0000_0000_0010 : dmawad_now1_4th + 64'h0000_0000_0000_0010
);
end else if (state == RX_DESC) begin
dmawad <= (pathindex_inturn[1] == 1'b0) ?
( (pathindex_inturn[0] == 1'b0) ?
dmawad_now1_1st : dmawad_now1_2nd
)
: ( (pathindex_inturn[0] == 1'b0) ?
dmawad_now1_3rd : dmawad_now1_4th
);
end else begin
dmawad <= dmawad;
end
end
// length output value from state machine
always@(posedge clk) begin
if(rst_reg)
length_byte[12:0] <= 13'h0000;
else if (state == TX_DESC_WRITE_BACK)
length_byte[12:0] <= TX_DESC_SIZE_BYTES[12:0];
else if (state == RX_CLEAR)
length_byte[12:0] <= RX_DESC_SIZE_BYTES[12:0];
else if (state == RX_PACKET)
length_byte[12:0] <= frame_size_bytes[12:0];
else if (state == RX_DESC)
length_byte[12:0] <= RX_DESC_SIZE_BYTES[12:0];
else
length_byte <= length_byte;
end
assign length[9:0] = length_byte[11:2];
endmodule
|
// Copyright 2007, Martin Whitaker.
// This code may be freely copied for any purpose.
module unnamed_generate_block();
localparam up = 1;
wire [2:0] count1;
wire [2:0] count2;
wire [2:0] count3;
generate
if (up)
count_up counter(count1);
else
count_down counter(count1);
endgenerate
generate
if (up)
begin:genblk1
count_up counter(count2);
end
else
begin:genblk1
count_down counter(count2);
end
endgenerate
count_down genblk01(count3);
initial begin:genblk001
reg [2:0] count;
#1 count = 4;
#1 count = 5;
#1 count = 6;
#1 count = 7;
end
always @(genblk0001.counter.count) begin
$display(genblk0001.counter.count);
end
//initial begin
// $dumpfile("dump.vcd");
// $dumpvars;
//end
endmodule
module count_up(output reg [2:0] count);
initial begin
#1 count = 0;
#1 count = 1;
#1 count = 2;
#1 count = 3;
end
endmodule
module count_down(output reg [2:0] count);
initial begin
#1 count = 3;
#1 count = 2;
#1 count = 1;
#1 count = 0;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's register file inside CPU ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of register file memories ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_rf(
// Clock and reset
clk, rst,
// Write i/f
supv, wb_freeze, addrw, dataw, we, flushpipe,
// Read i/f
id_freeze, addra, addrb, dataa, datab, rda, rdb,
// Debug
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// Write i/f
//
input supv;
input wb_freeze;
input [aw-1:0] addrw;
input [dw-1:0] dataw;
input we;
input flushpipe;
//
// Read i/f
//
input id_freeze;
input [aw-1:0] addra;
input [aw-1:0] addrb;
output [dw-1:0] dataa;
output [dw-1:0] datab;
input rda;
input rdb;
//
// SPR access for debugging purposes
//
input spr_cs;
input spr_write;
input [31:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
//
// Internal wires and regs
//
wire [dw-1:0] from_rfa;
wire [dw-1:0] from_rfb;
reg [dw:0] dataa_saved;
reg [dw:0] datab_saved;
wire [aw-1:0] rf_addra;
wire [aw-1:0] rf_addrw;
wire [dw-1:0] rf_dataw;
wire rf_we;
wire spr_valid;
wire rf_ena;
wire rf_enb;
reg rf_we_allow;
//
// SPR access is valid when spr_cs is asserted and
// SPR address matches GPR addresses
//
assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF);
//
// SPR data output is always from RF A
//
assign spr_dat_o = from_rfa;
//
// Operand A comes from RF or from saved A register
//
assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa;
//
// Operand B comes from RF or from saved B register
//
assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb;
//
// RF A read address is either from SPRS or normal from CPU control
//
assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : addra;
//
// RF write address is either from SPRS or normal from CPU control
//
assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;
//
// RF write data is either from SPRS or normal from CPU datapath
//
assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;
//
// RF write enable is either from SPRS or normal from CPU control
//
always @(posedge rst or posedge clk)
if (rst)
rf_we_allow <= #1 1'b1;
else if (~wb_freeze)
rf_we_allow <= #1 ~flushpipe;
assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow & (supv | (|rf_addrw));
//
// CS RF A asserted when instruction reads operand A and ID stage
// is not stalled
//
assign rf_ena = rda & ~id_freeze | spr_valid; // probably works with fixed binutils
// assign rf_ena = 1'b1; // does not work with single-stepping
//assign rf_ena = ~id_freeze | spr_valid; // works with broken binutils
//
// CS RF B asserted when instruction reads operand B and ID stage
// is not stalled
//
assign rf_enb = rdb & ~id_freeze | spr_valid;
// assign rf_enb = 1'b1;
//assign rf_enb = ~id_freeze | spr_valid; // works with broken binutils
//
// Stores operand from RF_A into temp reg when pipeline is frozen
//
always @(posedge clk or posedge rst)
if (rst) begin
dataa_saved <= #1 33'b0;
end
else if (id_freeze & !dataa_saved[32]) begin
dataa_saved <= #1 {1'b1, from_rfa};
end
else if (!id_freeze)
dataa_saved <= #1 33'b0;
//
// Stores operand from RF_B into temp reg when pipeline is frozen
//
always @(posedge clk or posedge rst)
if (rst) begin
datab_saved <= #1 33'b0;
end
else if (id_freeze & !datab_saved[32]) begin
datab_saved <= #1 {1'b1, from_rfb};
end
else if (!id_freeze)
datab_saved <= #1 33'b0;
`ifdef OR1200_RFRAM_TWOPORT
//
// Instantiation of register file two-port RAM A
//
or1200_tpram_32x32 rf_a(
// Port A
.clk_a(clk),
.rst_a(rst),
.ce_a(rf_ena),
.we_a(1'b0),
.oe_a(1'b1),
.addr_a(rf_addra),
.di_a(32'h0000_0000),
.do_a(from_rfa),
// Port B
.clk_b(clk),
.rst_b(rst),
.ce_b(rf_we),
.we_b(rf_we),
.oe_b(1'b0),
.addr_b(rf_addrw),
.di_b(rf_dataw),
.do_b()
);
//
// Instantiation of register file two-port RAM B
//
or1200_tpram_32x32 rf_b(
// Port A
.clk_a(clk),
.rst_a(rst),
.ce_a(rf_enb),
.we_a(1'b0),
.oe_a(1'b1),
.addr_a(addrb),
.di_a(32'h0000_0000),
.do_a(from_rfb),
// Port B
.clk_b(clk),
.rst_b(rst),
.ce_b(rf_we),
.we_b(rf_we),
.oe_b(1'b0),
.addr_b(rf_addrw),
.di_b(rf_dataw),
.do_b()
);
`else
`ifdef OR1200_RFRAM_DUALPORT
//
// Instantiation of register file two-port RAM A
//
or1200_dpram_32x32 rf_a(
// Port A
.clk_a(clk),
.rst_a(rst),
.ce_a(rf_ena),
.oe_a(1'b1),
.addr_a(rf_addra),
.do_a(from_rfa),
// Port B
.clk_b(clk),
.rst_b(rst),
.ce_b(rf_we),
.we_b(rf_we),
.addr_b(rf_addrw),
.di_b(rf_dataw)
);
//
// Instantiation of register file two-port RAM B
//
or1200_dpram_32x32 rf_b(
// Port A
.clk_a(clk),
.rst_a(rst),
.ce_a(rf_enb),
.oe_a(1'b1),
.addr_a(addrb),
.do_a(from_rfb),
// Port B
.clk_b(clk),
.rst_b(rst),
.ce_b(rf_we),
.we_b(rf_we),
.addr_b(rf_addrw),
.di_b(rf_dataw)
);
`else
`ifdef OR1200_RFRAM_GENERIC
//
// Instantiation of generic (flip-flop based) register file
//
or1200_rfram_generic rf_a(
// Clock and reset
.clk(clk),
.rst(rst),
// Port A
.ce_a(rf_ena),
.addr_a(rf_addra),
.do_a(from_rfa),
// Port B
.ce_b(rf_enb),
.addr_b(addrb),
.do_b(from_rfb),
// Port W
.ce_w(rf_we),
.we_w(rf_we),
.addr_w(rf_addrw),
.di_w(rf_dataw)
);
`else
//
// RFRAM type not specified
//
initial begin
$display("Define RFRAM type.");
$finish;
end
`endif
`endif
`endif
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
`include "pcie_defines.v"
`include "nysa_pcie_defines.v"
module pcie_egress (
input clk,
input rst,
input i_enable,
output reg o_finished,
input [7:0] i_command,
input [13:0] i_flags,
input [31:0] i_address,
input [15:0] i_requester_id,
input [7:0] i_tag,
//PCIE Egress
input [9:0] i_req_dword_cnt,
//AXI Stream Device 2 Host
input i_axi_egress_ready,
//output reg [31:0] o_axi_egress_data,
output [31:0] o_axi_egress_data,
output [3:0] o_axi_egress_keep,
output reg o_axi_egress_last,
output reg o_axi_egress_valid,
//Outgoing FIFO Data
input i_fifo_rdy,
output reg o_fifo_act,
input [23:0] i_fifo_size,
input [31:0] i_fifo_data,
output reg o_fifo_stb,
output reg dbg_ready_drop
);
//Local Parameters
localparam IDLE = 4'h0;
localparam WAIT_FOR_FIFO = 4'h1;
localparam WAIT_FOR_PCIE_CORE = 4'h2;
localparam SEND_HDR = 4'h3;
localparam SEND_DATA = 4'h4;
localparam SEND_NON_DATA_PKT_START = 4'h5;
localparam SEND_NON_DATA_PKT = 4'h6;
localparam SEND_NON_DATA_PKT_FIN = 4'h7;
localparam FINISHED = 4'h8;
//Registers/Wires
reg [3:0] state;
reg [23:0] r_data_count;
wire [31:0] w_hdr[0:3];
wire [2:0] w_hdr_size;
reg [2:0] r_hdr_index;
wire [9:0] w_pkt_data_count;
wire [31:0] w_hdr0;
wire [31:0] w_hdr1;
wire [31:0] w_hdr2;
wire [31:0] w_hdr3;
wire w_non_data_packet;
//Submodules
//Asynchronous Logic
assign o_axi_egress_keep = 4'hF;
//1st Dword
assign w_non_data_packet = (i_command == `PCIE_MRD_32B);
assign w_pkt_data_count = (i_command == `PCIE_MRD_32B) ? i_req_dword_cnt : i_fifo_size;
assign w_hdr[0][`PCIE_TYPE_RANGE] = i_command;
assign w_hdr[0][`PCIE_FLAGS_RANGE] = i_flags;
assign w_hdr[0][`PCIE_DWORD_PKT_CNT_RANGE] = w_pkt_data_count;
//2nd Dword
assign w_hdr[1] = (i_command == `PCIE_MRD_32B) ? {i_requester_id, i_tag, 8'h00} :
(i_fifo_size == 1) ? 32'h0000000F : //== 1 DWORD
32'h000000FF; // > 1 DWORD
assign w_hdr[2] = i_address;
assign w_hdr_size = (w_hdr[0][29]) ? 3'h4 : 3'h3; //Index Size is dependent on 64-bit vs 32-bit address space
assign w_hdr0 = w_hdr[0];
assign w_hdr1 = w_hdr[1];
assign w_hdr2 = w_hdr[2];
assign o_axi_egress_data = ((state == WAIT_FOR_PCIE_CORE) || (state == SEND_HDR) || (state == SEND_NON_DATA_PKT) || (state == SEND_NON_DATA_PKT_FIN)) ? w_hdr[r_hdr_index]:
i_fifo_data;
//Synchronous Logic
always @ (posedge clk) begin
//Clear Strobes
o_fifo_stb <= 0;
dbg_ready_drop <= 0;
if (rst) begin
state <= IDLE;
o_finished <= 0;
r_hdr_index <= 0;
o_axi_egress_valid <= 0;
o_axi_egress_last <= 0;
//o_axi_egress_data <= 0;
o_fifo_act <= 0;
r_data_count <= 0;
end
else begin
case (state)
IDLE: begin
o_axi_egress_valid <= 0;
o_finished <= 0;
r_data_count <= 0;
r_hdr_index <= 0;
if (i_enable) begin
if (w_non_data_packet) begin
state <= SEND_NON_DATA_PKT_START;
end
else begin
state <= WAIT_FOR_FIFO;
end
end
end
WAIT_FOR_FIFO: begin
if (i_fifo_rdy && !o_fifo_act) begin
r_data_count <= 0;
o_fifo_act <= 1;
state <= WAIT_FOR_PCIE_CORE;
//o_axi_egress_data <= w_hdr[r_hdr_index];
//r_hdr_index <= r_hdr_index + 1;
end
end
WAIT_FOR_PCIE_CORE: begin
if (i_axi_egress_ready && o_axi_egress_valid) begin
r_hdr_index <= r_hdr_index + 1;
if (r_hdr_index + 1 >= w_hdr_size) begin
if (w_non_data_packet) begin
o_axi_egress_last <= 1;
state <= FINISHED;
end
else begin
state <= SEND_DATA;
o_fifo_stb <= 1;
r_data_count <= r_data_count + 1;
end
end
end
o_axi_egress_valid <= 1;
end
SEND_DATA: begin
//o_axi_egress_data <= i_fifo_data;
o_fifo_stb <= 1;
if (r_data_count + 1 >= i_fifo_size) begin
state <= FINISHED;
o_axi_egress_last <= 1;
end
r_data_count <= r_data_count + 1;
end
SEND_NON_DATA_PKT_START: begin
if (i_axi_egress_ready) begin
state <= SEND_NON_DATA_PKT;
end
end
SEND_NON_DATA_PKT: begin
//if (i_axi_egress_ready && o_axi_egress_valid) begin
if (o_axi_egress_valid) begin
if (!i_axi_egress_ready) begin
dbg_ready_drop <= 1;
end
r_hdr_index <= r_hdr_index + 1;
if (r_hdr_index + 2 >= w_hdr_size) begin
o_axi_egress_last <= 1;
state <= SEND_NON_DATA_PKT_FIN;
end
end
o_axi_egress_valid <= 1;
end
SEND_NON_DATA_PKT_FIN: begin
o_axi_egress_valid <= 0;
o_axi_egress_last <= 0;
o_fifo_act <= 0;
state <= FINISHED;
end
FINISHED: begin
o_axi_egress_valid <= 0;
o_axi_egress_last <= 0;
o_fifo_act <= 0;
o_finished <= 1;
if (!i_enable) begin
o_finished <= 0;
state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: altpcie_pll_125_250.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Internal Build 139 08/21/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcie_pll_125_250 (
areset,
inclk0,
c0);
input areset;
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire2 = 1'h0;
wire [0:0] sub_wire4 = 1'h1;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire [5:0] sub_wire3 = {sub_wire2, sub_wire2, sub_wire2, sub_wire2, sub_wire2, sub_wire4};
wire sub_wire5 = inclk0;
wire [1:0] sub_wire6 = {sub_wire2, sub_wire5};
wire [3:0] sub_wire7 = {sub_wire2, sub_wire2, sub_wire2, sub_wire2};
altpll altpll_component (
.clkena (sub_wire3),
.inclk (sub_wire6),
.extclkena (sub_wire7),
.areset (areset),
.clk (sub_wire0)
// synopsys translate_off
,
.scanclk (),
.pllena (),
.sclkout1 (),
.sclkout0 (),
.fbin (),
.scandone (),
.clkloss (),
.extclk (),
.clkswitch (),
.pfdena (),
.scanaclr (),
.clkbad (),
.scandata (),
.enable1 (),
.scandataout (),
.enable0 (),
.scanwrite (),
.locked (),
.activeclock (),
.scanread ()
// synopsys translate_on
);
defparam
altpll_component.bandwidth = 500000,
altpll_component.bandwidth_type = "CUSTOM",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 8000,
altpll_component.intended_device_family = "Stratix GX",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "ENHANCED",
altpll_component.spread_frequency = 0;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "2.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "10"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix GX"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "125.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "250.000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH NUMERIC "500000"
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "CUSTOM"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "ENHANCED"
// Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 2 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0
// Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250_bb.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250_waveforms.html FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250_wave*.jpg FALSE FALSE
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//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
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// All rights reserved.
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// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: ddr2_ctrl.v
// /___/ /\ Date Last Modified: $Date: 2009/11/03 04:43:17 $
// \ \ / \ Date Created: Wed Aug 30 2006
// \___\/\___\
//
//
//Device: Virtex-5
//Design Name: DDR/DDR2
//Purpose:
// This module is the main control logic of the memory interface. All
// commands are issued from here according to the burst, CAS Latency and the
// user commands.
//Reference:
//Revision History:
// Rev 1.2 - Fixed auto refresh to activate bug. KP 11-19-2007
// Rev 1.3 - For Dual Rank parts support CS logic modified. KP. 05/08/08
// Rev 1.4 - AUTO_REFRESH_WAIT state modified for Auto Refresh flag asserted
// immediately after calibration is completed. KP. 07/28/08
// Rev 1.5 - Assignment of bank_valid_r is modified to fix a bug in
// Bank Management logic. PK. 10/29/08
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_ctrl #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_v3_4 module. Please refer to
// the mig_v3_4 module for actual values.
parameter BANK_WIDTH = 2,
parameter COL_WIDTH = 10,
parameter CS_BITS = 0,
parameter CS_NUM = 1,
parameter ROW_WIDTH = 14,
parameter ADDITIVE_LAT = 0,
parameter BURST_LEN = 4,
parameter CAS_LAT = 5,
parameter ECC_ENABLE = 0,
parameter REG_ENABLE = 1,
parameter TREFI_NS = 7800,
parameter TRAS = 40000,
parameter TRCD = 15000,
parameter TRRD = 10000,
parameter TRFC = 105000,
parameter TRP = 15000,
parameter TRTP = 7500,
parameter TWR = 15000,
parameter TWTR = 10000,
parameter CLK_PERIOD = 3000,
parameter MULTI_BANK_EN = 1,
parameter TWO_T_TIME_EN = 0,
parameter DDR_TYPE = 1
)
(
input clk,
input rst,
input [2:0] af_cmd,
input [30:0] af_addr,
input af_empty,
input phy_init_done,
output ctrl_ref_flag,
output ctrl_af_rden,
output reg ctrl_wren,
output reg ctrl_rden,
output [ROW_WIDTH-1:0] ctrl_addr,
output [BANK_WIDTH-1:0] ctrl_ba,
output ctrl_ras_n,
output ctrl_cas_n,
output ctrl_we_n,
output [CS_NUM-1:0] ctrl_cs_n
);
// input address split into various ranges
localparam ROW_RANGE_START = COL_WIDTH;
localparam ROW_RANGE_END = ROW_WIDTH + ROW_RANGE_START - 1;
localparam BANK_RANGE_START = ROW_RANGE_END + 1;
localparam BANK_RANGE_END = BANK_WIDTH + BANK_RANGE_START - 1;
localparam CS_RANGE_START = BANK_RANGE_START + BANK_WIDTH;
localparam CS_RANGE_END = CS_BITS + CS_RANGE_START - 1;
// compare address (for determining bank/row hits) split into various ranges
// (compare address doesn't include column bits)
localparam CMP_WIDTH = CS_BITS + BANK_WIDTH + ROW_WIDTH;
localparam CMP_ROW_RANGE_START = 0;
localparam CMP_ROW_RANGE_END = ROW_WIDTH + CMP_ROW_RANGE_START - 1;
localparam CMP_BANK_RANGE_START = CMP_ROW_RANGE_END + 1;
localparam CMP_BANK_RANGE_END = BANK_WIDTH + CMP_BANK_RANGE_START - 1;
localparam CMP_CS_RANGE_START = CMP_BANK_RANGE_END + 1;
localparam CMP_CS_RANGE_END = CS_BITS + CMP_CS_RANGE_START-1;
localparam BURST_LEN_DIV2 = BURST_LEN / 2;
localparam OPEN_BANK_NUM = 4;
localparam CS_BITS_FIX = (CS_BITS == 0) ? 1 : CS_BITS;
// calculation counters based on clock cycle and memory parameters
// TRAS: ACTIVE->PRECHARGE interval - 2
localparam integer TRAS_CYC = (TRAS + CLK_PERIOD)/CLK_PERIOD;
// TRCD: ACTIVE->READ/WRITE interval - 3 (for DDR2 factor in ADD_LAT)
localparam integer TRRD_CYC = (TRRD + CLK_PERIOD)/CLK_PERIOD;
localparam integer TRCD_CYC = (((TRCD + CLK_PERIOD)/CLK_PERIOD) >
ADDITIVE_LAT )?
((TRCD+CLK_PERIOD)/ CLK_PERIOD) - ADDITIVE_LAT : 0;
// TRFC: REFRESH->REFRESH, REFRESH->ACTIVE interval - 2
localparam integer TRFC_CYC = (TRFC + CLK_PERIOD)/CLK_PERIOD;
// TRP: PRECHARGE->COMMAND interval - 2
// for precharge all add 1 extra clock cycle
localparam integer TRP_CYC = ((TRP + CLK_PERIOD)/CLK_PERIOD) +1;
// TRTP: READ->PRECHARGE interval - 2 (Al + BL/2 + (max (TRTP, 2tck))-2
localparam integer TRTP_TMP_MIN = (((TRTP + CLK_PERIOD)/CLK_PERIOD) >= 2)?
((TRTP + CLK_PERIOD)/CLK_PERIOD) : 2;
localparam integer TRTP_CYC = TRTP_TMP_MIN + ADDITIVE_LAT
+ BURST_LEN_DIV2 - 2;
// TWR: WRITE->PRECHARGE interval - 2
localparam integer WR_LAT = (DDR_TYPE > 0) ? CAS_LAT + ADDITIVE_LAT - 1 : 1;
localparam integer TWR_CYC = ((TWR + CLK_PERIOD)/CLK_PERIOD) +
WR_LAT + BURST_LEN_DIV2 ;
// TWTR: WRITE->READ interval - 3 (for DDR1, TWTR = 2 clks)
// DDR2 = CL-1 + BL/2 +TWTR
localparam integer TWTR_TMP_MIN = ((TWTR + CLK_PERIOD) % CLK_PERIOD)?((TWTR + CLK_PERIOD)/CLK_PERIOD) + 1:(TWTR + CLK_PERIOD)/CLK_PERIOD;
localparam integer TWTR_CYC = (DDR_TYPE > 0) ? (TWTR_TMP_MIN + (CAS_LAT -1)
+ BURST_LEN_DIV2 ): 2;
// TRTW: READ->WRITE interval - 3
// DDR1: CL + (BL/2)
// DDR2: (BL/2) + 2. Two more clocks are added to
// the DDR2 counter to account for the delay in
// arrival of the DQS during reads (pcb trace + buffer
// delays + memory parameters).
localparam TRTW_CYC = (DDR_TYPE > 0) ? BURST_LEN_DIV2 + 4 :
(CAS_LAT == 25) ? 2 + BURST_LEN_DIV2 : CAS_LAT + BURST_LEN_DIV2;
localparam integer CAS_LAT_RD = (CAS_LAT == 25) ? 2 : CAS_LAT;
// Make sure all values >= 0 (some may be = 0)
localparam TRAS_COUNT = (TRAS_CYC > 0) ? TRAS_CYC : 0;
localparam TRCD_COUNT = (TRCD_CYC > 0) ? TRCD_CYC : 0;
localparam TRRD_COUNT = (TRRD_CYC > 0) ? TRRD_CYC : 0;
localparam TRFC_COUNT = (TRFC_CYC > 0) ? TRFC_CYC : 0;
localparam TRP_COUNT = (TRP_CYC > 0) ? TRP_CYC : 0;
localparam TRTP_COUNT = (TRTP_CYC > 0) ? TRTP_CYC : 0;
localparam TWR_COUNT = (TWR_CYC > 0) ? TWR_CYC : 0;
localparam TWTR_COUNT = (TWTR_CYC > 0) ? TWTR_CYC : 0;
localparam TRTW_COUNT = (TRTW_CYC > 0) ? TRTW_CYC : 0;
// Auto refresh interval
localparam TREFI_COUNT = ((TREFI_NS * 1000)/CLK_PERIOD) - 1;
// memory controller states
localparam CTRL_IDLE = 5'h00;
localparam CTRL_PRECHARGE = 5'h01;
localparam CTRL_PRECHARGE_WAIT = 5'h02;
localparam CTRL_AUTO_REFRESH = 5'h03;
localparam CTRL_AUTO_REFRESH_WAIT = 5'h04;
localparam CTRL_ACTIVE = 5'h05;
localparam CTRL_ACTIVE_WAIT = 5'h06;
localparam CTRL_BURST_READ = 5'h07;
localparam CTRL_READ_WAIT = 5'h08;
localparam CTRL_BURST_WRITE = 5'h09;
localparam CTRL_WRITE_WAIT = 5'h0A;
localparam CTRL_PRECHARGE_WAIT1 = 5'h0B;
reg [CMP_WIDTH-1:0] act_addr_r;
wire [30:0] af_addr_r;
reg [30:0] af_addr_r1;
reg [30:0] af_addr_r2;
reg [30:0] af_addr_r3;
wire [2:0] af_cmd_r;
reg [2:0] af_cmd_r1;
reg [2:0] af_cmd_r2;
reg af_valid_r;
reg af_valid_r1;
reg af_valid_r2;
reg [CS_BITS_FIX :0] auto_cnt_r;
reg auto_ref_r;
reg [(OPEN_BANK_NUM*CMP_WIDTH)-1:0] bank_cmp_addr_r;
reg [OPEN_BANK_NUM-1:0] bank_hit;
reg [OPEN_BANK_NUM-1:0] bank_hit_r;
reg [OPEN_BANK_NUM-1:0] bank_hit_r1;
reg [OPEN_BANK_NUM-1:0] bank_valid_r;
reg bank_conflict_r;
reg conflict_resolved_r;
reg ctrl_af_rden_r;
reg conflict_detect_r;
wire conflict_detect;
reg cs_change_r;
reg cs_change_sticky_r;
reg [ROW_WIDTH-1:0] ddr_addr_r;
wire [ROW_WIDTH-1:0] ddr_addr_col;
wire [ROW_WIDTH-1:0] ddr_addr_row;
reg [BANK_WIDTH-1:0] ddr_ba_r;
reg ddr_cas_n_r;
reg [CS_NUM-1:0] ddr_cs_n_r;
reg ddr_ras_n_r;
reg ddr_we_n_r;
reg [4:0] next_state;
reg no_precharge_wait_r;
reg no_precharge_r;
reg no_precharge_r1;
reg phy_init_done_r;
reg [4:0] precharge_ok_cnt_r;
reg precharge_ok_r;
reg [4:0] ras_cnt_r;
reg [3:0] rcd_cnt_r;
reg rcd_cnt_ok_r;
reg [2:0] rdburst_cnt_r;
reg rdburst_ok_r;
reg rdburst_rden_ok_r;
reg rd_af_flag_r;
wire rd_flag;
reg rd_flag_r;
reg [4:0] rd_to_wr_cnt_r;
reg rd_to_wr_ok_r;
reg ref_flag_r;
reg [11:0] refi_cnt_r;
reg refi_cnt_ok_r;
reg rst_r
/* synthesis syn_preserve = 1 */;
reg rst_r1
/* synthesis syn_maxfan = 10 */;
reg [7:0] rfc_cnt_r;
reg rfc_ok_r;
reg [3:0] row_miss;
reg [3:0] row_conflict_r;
reg [3:0] rp_cnt_r;
reg rp_cnt_ok_r;
reg [CMP_WIDTH-1:0] sb_open_add_r;
reg [4:0] state_r;
reg [4:0] state_r1;
wire sm_rden;
reg sm_rden_r;
reg [2:0] trrd_cnt_r;
reg trrd_cnt_ok_r;
reg [2:0] two_t_enable_r;
reg [CS_NUM-1:0] two_t_enable_r1;
reg [2:0] wrburst_cnt_r;
reg wrburst_ok_r;
reg wrburst_wren_ok_r;
wire wr_flag;
reg wr_flag_r;
reg [4:0] wr_to_rd_cnt_r;
reg wr_to_rd_ok_r;
// XST attributes for local reset "tree"
// synthesis attribute shreg_extract of rst_r is "no";
// synthesis attribute shreg_extract of rst_r1 is "no";
// synthesis attribute equivalent_register_removal of rst_r is "no"
//***************************************************************************
// sm_rden is used to assert read enable to the address FIFO
assign sm_rden = ((state_r == CTRL_BURST_WRITE) ||
(state_r == CTRL_BURST_READ)) ;
// assert read flag to the adress FIFO
assign ctrl_af_rden = sm_rden || rd_af_flag_r;
// local reset "tree" for controller logic only. Create this to ease timing
// on reset path. Prohibit equivalent register removal on RST_R to prevent
// "sharing" with other local reset trees (caution: make sure global fanout
// limit is set to large enough value, otherwise SLICES may be used for
// fanout control on RST_R.
always @(posedge clk) begin
rst_r <= rst;
rst_r1 <= rst_r;
end
//*****************************************************************
// interpret commands from Command/Address FIFO
//*****************************************************************
assign wr_flag = (af_valid_r2) ? ((af_cmd_r2 == 3'b000) ? 1'b1 : 1'b0): 1'b0;
assign rd_flag = (af_valid_r2) ? ((af_cmd_r2 == 3'b001) ? 1'b1 : 1'b0): 1'b0;
always @(posedge clk) begin
rd_flag_r <= rd_flag;
wr_flag_r <= wr_flag;
end
//////////////////////////////////////////////////
// The data from the address FIFO is fetched and
// stored in two register stages. The data will be
// pulled out of the second register stage whenever
// the state machine can handle new data from the
// address FIFO.
// This flag is asserted when there is no
// cmd & address in the pipe. When there is
// valid cmd & addr from the address FIFO the
// af_valid signals will be asserted. This flag will
// be set the cycle af_valid_r is de-asserted.
always @(posedge clk) begin
// for simulation purposes - to force CTRL_AF_RDEN low during reset
if (rst_r1)
rd_af_flag_r <= 1'd0;
else if((ctrl_af_rden_r) ||
(rd_af_flag_r && (af_valid_r || af_valid_r1)))
rd_af_flag_r <= 1'd0;
else if (~af_valid_r1 || ~af_valid_r)
rd_af_flag_r <= 1'd1;
end
// First register stage for the cmd & add from the FIFO.
// The af_valid_r signal gives the status of the data
// in this stage. The af_valid_r will be asserted when there
// is valid data. This register stage will be updated
// 1. read to the FIFO and the FIFO not empty
// 2. After write and read states
// 3. The valid signal is not asserted in the last stage.
always @(posedge clk) begin
if (rst_r1)begin
af_valid_r <= 1'd0;
end else begin
if (ctrl_af_rden_r || sm_rden_r || ~af_valid_r1
|| ~af_valid_r2)begin
af_valid_r <= ctrl_af_rden_r;
end
end
end
// The output register in the FIFO is used. The addr
// and command are already registered in the FIFO.
assign af_addr_r = af_addr;
assign af_cmd_r = af_cmd;
// Second register stage for the cmd & add from the FIFO.
// The af_valid_r1 signal gives the status of the data
// in this stage. The af_valid_r will be asserted when there
// is valid data. This register stage will be updated
// 1. read to the FIFO and the FIFO not empty and there
// is no valid data on this stage
// 2. After write and read states
// 3. The valid signal is not asserted in the last stage.
always@(posedge clk) begin
if (rst_r1)begin
af_valid_r1 <= 1'd0;
af_addr_r1 <= {31{1'bx}};
af_cmd_r1 <= {3{1'bx}};
end else if (~af_valid_r1 || sm_rden_r ||
~af_valid_r2) begin
af_valid_r1 <= af_valid_r;
af_addr_r1 <= af_addr_r;
af_cmd_r1 <= af_cmd_r;
end
end
// The state machine uses the address and command in this
// register stage. The data is fetched from the second
// register stage whenever the state machine can accept new
// addr. The conflict flags are also generated based on the
// second register stage and updated when the new address
// is loaded for the state machine.
always@(posedge clk) begin
if (rst_r1)begin
af_valid_r2 <= 1'd0;
af_addr_r2 <= {31{1'bx}};
af_cmd_r2 <= {3{1'bx}};
bank_hit_r <= {OPEN_BANK_NUM{1'bx}};
bank_conflict_r <= 1'bx;
row_conflict_r <= 4'bx;
end else if(sm_rden || ~af_valid_r2)begin
af_valid_r2 <= af_valid_r1;
af_addr_r2 <= af_addr_r1;
af_cmd_r2 <= af_cmd_r1;
if(MULTI_BANK_EN)begin
bank_hit_r <= bank_hit;
row_conflict_r <= row_miss;
bank_conflict_r <= (~(|bank_hit));
end else begin
bank_hit_r <= {OPEN_BANK_NUM{1'b0}};
bank_conflict_r <= 1'd0;
row_conflict_r[0] <= (af_addr_r1[CS_RANGE_END:ROW_RANGE_START]
!= sb_open_add_r[CMP_WIDTH-1:0]);
end
end
end // always@ (posedge clk)
//detecting cs change for multi chip select case
generate
if(CS_NUM > 1) begin: gen_cs_change
always @(posedge clk) begin
if(sm_rden || ~af_valid_r2)begin
cs_change_r <= af_addr_r1[CS_RANGE_END:CS_RANGE_START] !=
af_addr_r2[CS_RANGE_END:CS_RANGE_START] ;
cs_change_sticky_r <=
af_addr_r1[CS_RANGE_END:CS_RANGE_START] !=
af_addr_r2[CS_RANGE_END:CS_RANGE_START] ;
end else
cs_change_r <= 1'd0;
end
end // block: gen_cs_change
else begin: gen_cs_0
always @(posedge clk) begin
cs_change_r <= 1'd0;
cs_change_sticky_r <= 1'd0;
end
end
endgenerate
assign conflict_detect = (MULTI_BANK_EN) ?
((|(row_conflict_r[3:0] & bank_hit_r[3:0]))
| bank_conflict_r) & af_valid_r2 :
row_conflict_r[0] & af_valid_r2;
always @(posedge clk) begin
conflict_detect_r <= conflict_detect;
sm_rden_r <= sm_rden;
af_addr_r3 <= af_addr_r2;
ctrl_af_rden_r <= ctrl_af_rden & ~af_empty;
end
// conflict resolved signal. When this signal is asserted
// the conflict is resolved. The address to be compared
// for the conflict_resolved_r will be stored in act_add_r
// when the bank is opened.
always @(posedge clk) begin
conflict_resolved_r <= (act_addr_r ==
af_addr_r2[CS_RANGE_END:ROW_RANGE_START]);
if((state_r == CTRL_ACTIVE))
act_addr_r <= af_addr_r2[CS_RANGE_END:ROW_RANGE_START];
end
//***************************************************************************
// Bank management logic
// Semi-hardcoded for now for 4 banks
// will keep multiple banks open if MULTI_BANK_EN is true.
//***************************************************************************
genvar bank_i;
generate // if multiple bank option chosen
if(MULTI_BANK_EN) begin: gen_multi_bank_open
for (bank_i = 0; bank_i < OPEN_BANK_NUM;
bank_i = bank_i + 1) begin: gen_bank_hit1
// asserted if bank address match + open bank entry is valid
always @(*) begin
bank_hit[bank_i]
= ((bank_cmp_addr_r[(CMP_WIDTH*(bank_i+1))-1:
(CMP_WIDTH*bank_i)+ROW_WIDTH] ==
af_addr_r1[CS_RANGE_END:BANK_RANGE_START]) &&
bank_valid_r[bank_i]);
// asserted if row address match (no check for bank entry valid, rely
// on this term to be used in conjunction with BANK_HIT[])
row_miss[bank_i]
= (bank_cmp_addr_r[(CMP_WIDTH*bank_i)+ROW_WIDTH-1:
(CMP_WIDTH*bank_i)] !=
af_addr_r1[ROW_RANGE_END:ROW_RANGE_START]);
end
end
always @(posedge clk) begin
no_precharge_wait_r <= bank_valid_r[3] & bank_conflict_r;
bank_hit_r1 <= bank_hit_r;
end
always@(*)
no_precharge_r = ~bank_valid_r[3] & bank_conflict_r;
always@(posedge clk)
no_precharge_r1 <= no_precharge_r;
always @(posedge clk) begin
// Clear all bank valid bits during AR (i.e. since all banks get
// precharged during auto-refresh)
if ((state_r1 == CTRL_AUTO_REFRESH)) begin
bank_valid_r <= {OPEN_BANK_NUM{1'b0}};
bank_cmp_addr_r <= {(OPEN_BANK_NUM*CMP_WIDTH-1){1'b0}};
end else begin
if (state_r1 == CTRL_ACTIVE) begin
// 00 is always going to have the latest bank and row.
bank_cmp_addr_r[CMP_WIDTH-1:0]
<= af_addr_r3[CS_RANGE_END:ROW_RANGE_START];
// This indicates the bank was activated
bank_valid_r[0] <= 1'b1;
case ({bank_hit_r1[2:0]})
3'b001: begin
bank_cmp_addr_r[CMP_WIDTH-1:0]
<= af_addr_r3[CS_RANGE_END:ROW_RANGE_START];
// This indicates the bank was activated
bank_valid_r[0] <= 1'b1;
end
3'b010: begin //(b0->b1)
bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH]
<= bank_cmp_addr_r[CMP_WIDTH-1:0];
bank_valid_r[1] <= bank_valid_r[0];
end
3'b100:begin //(b0->b1, b1->b2)
bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH]
<= bank_cmp_addr_r[CMP_WIDTH-1:0];
bank_cmp_addr_r[(3*CMP_WIDTH)-1:2*CMP_WIDTH]
<= bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH];
bank_valid_r[1] <= bank_valid_r[0];
bank_valid_r[2] <= bank_valid_r[1];
end
default: begin //(b0->b1, b1->b2, b2->b3)
bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH]
<= bank_cmp_addr_r[CMP_WIDTH-1:0];
bank_cmp_addr_r[(3*CMP_WIDTH)-1:2*CMP_WIDTH]
<= bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH];
bank_cmp_addr_r[(4*CMP_WIDTH)-1:3*CMP_WIDTH]
<= bank_cmp_addr_r[(3*CMP_WIDTH)-1:2*CMP_WIDTH];
bank_valid_r[1] <= bank_valid_r[0];
bank_valid_r[2] <= bank_valid_r[1];
bank_valid_r[3] <= bank_valid_r[2];
end
endcase
end
end
end
end else begin: gen_single_bank_open // single bank option
always @(posedge clk) begin
no_precharge_r <= 1'd0;
no_precharge_r1 <= 1'd0;
no_precharge_wait_r <= 1'd0;
if (rst_r1)
sb_open_add_r <= {CMP_WIDTH{1'b0}};
else if (state_r == CTRL_ACTIVE)
sb_open_add_r <= af_addr_r2[CS_RANGE_END:ROW_RANGE_START];
end
end
endgenerate
//***************************************************************************
// Timing counters
//***************************************************************************
//*****************************************************************
// Write and read enable generation for PHY
//*****************************************************************
// write burst count. Counts from (BL/2 to 1).
// Also logic for controller write enable.
always @(posedge clk) begin
if (state_r == CTRL_BURST_WRITE) begin
wrburst_cnt_r <= BURST_LEN_DIV2;
end else if (wrburst_cnt_r >= 3'd1)
wrburst_cnt_r <= wrburst_cnt_r - 1;
end // always @ (posedge clk)
always @(posedge clk) begin
if (rst_r1) begin
ctrl_wren <= 1'b0;
end else if (state_r == CTRL_BURST_WRITE) begin
ctrl_wren <= 1'b1;
end else if (wrburst_wren_ok_r)
ctrl_wren <= 1'b0;
end
always @(posedge clk) begin
if ((state_r == CTRL_BURST_WRITE)
&& (BURST_LEN_DIV2 > 2))
wrburst_ok_r <= 1'd0;
else if ((wrburst_cnt_r <= 3'd3) ||
(BURST_LEN_DIV2 <= 2))
wrburst_ok_r <= 1'b1;
end
// flag to check when wrburst count has reached
// a value of 1. This flag is used in the ctrl_wren
// logic
always @(posedge clk) begin
if(wrburst_cnt_r == 3'd2)
wrburst_wren_ok_r <=1'b1;
else
wrburst_wren_ok_r <= 1'b0;
end
// read burst count. Counts from (BL/2 to 1)
always @(posedge clk) begin
if (state_r == CTRL_BURST_READ) begin
rdburst_cnt_r <= BURST_LEN_DIV2;
end else if (rdburst_cnt_r >= 3'd1)
rdburst_cnt_r <= rdburst_cnt_r - 1;
end // always @ (posedge clk)
always @(posedge clk) begin
if (rst_r1) begin
ctrl_rden <= 1'b0;
end else if (state_r == CTRL_BURST_READ) begin
ctrl_rden <= 1'b1;
end else if (rdburst_rden_ok_r)
ctrl_rden <= 1'b0;
end
// the rd_burst_ok_r signal will be asserted one cycle later
// in multi chip select cases if the back to back read is to
// different chip selects. The cs_changed_sticky_r signal will
// be asserted only for multi chip select cases.
always @(posedge clk) begin
if ((state_r == CTRL_BURST_READ)
&& (BURST_LEN_DIV2 > 2))
rdburst_ok_r <= 1'd0;
else if ((rdburst_cnt_r <=( 3'd3 - cs_change_sticky_r)) ||
(BURST_LEN_DIV2 <= 2))
rdburst_ok_r <= 1'b1;
end
// flag to check when rdburst count has reached
// a value of 1. This flag is used in the ctrl_rden
// logic
always @(posedge clk) begin
if (rdburst_cnt_r == 3'd2)
rdburst_rden_ok_r <= 1'b1;
else
rdburst_rden_ok_r <= 1'b0;
end
//*****************************************************************
// Various delay counters
// The counters are checked for value of <= 3 to determine the
// if the count values are reached during different commands.
// It is checked for 3 because
// 1. The counters are loaded during the state when the command
// state is reached (+1)
// 2. After the <= 3 condition is reached the sm takes two cycles
// to transition to the new command state (+2)
//*****************************************************************
// tRP count - precharge command period
always @(posedge clk) begin
if (state_r == CTRL_PRECHARGE)
rp_cnt_r <= TRP_COUNT;
else if (rp_cnt_r != 4'd0)
rp_cnt_r <= rp_cnt_r - 1;
end
always @(posedge clk) begin
if (state_r == CTRL_PRECHARGE)
rp_cnt_ok_r <= 1'd0;
else if (rp_cnt_r <= 4'd3)
rp_cnt_ok_r <= 1'd1;
end
// tRFC count - refresh-refresh, refresh-active
always @(posedge clk) begin
if (state_r == CTRL_AUTO_REFRESH)
rfc_cnt_r <= TRFC_COUNT;
else if (rfc_cnt_r != 8'd0)
rfc_cnt_r <= rfc_cnt_r - 1;
end
always @(posedge clk) begin
if (state_r == CTRL_AUTO_REFRESH)
rfc_ok_r <= 1'b0;
else if(rfc_cnt_r <= 8'd3)
rfc_ok_r <= 1'b1;
end
// tRCD count - active to read/write
always @(posedge clk) begin
if (state_r == CTRL_ACTIVE)
rcd_cnt_r <= TRCD_COUNT;
else if (rcd_cnt_r != 4'd0)
rcd_cnt_r <= rcd_cnt_r - 1;
end
always @(posedge clk) begin
if ((state_r == CTRL_ACTIVE)
&& (TRCD_COUNT > 2))
rcd_cnt_ok_r <= 1'd0;
else if (rcd_cnt_r <= 4'd3)
rcd_cnt_ok_r <= 1;
end
// tRRD count - active to active
always @(posedge clk) begin
if (state_r == CTRL_ACTIVE)
trrd_cnt_r <= TRRD_COUNT;
else if (trrd_cnt_r != 3'd0)
trrd_cnt_r <= trrd_cnt_r - 1;
end
always @(posedge clk) begin
if (state_r == CTRL_ACTIVE)
trrd_cnt_ok_r <= 1'd0;
else if (trrd_cnt_r <= 3'd3)
trrd_cnt_ok_r <= 1;
end
// tRAS count - active to precharge
always @(posedge clk) begin
if (state_r == CTRL_ACTIVE)
ras_cnt_r <= TRAS_COUNT;
else if (ras_cnt_r != 5'd0)
ras_cnt_r <= ras_cnt_r - 1;
end
// counter for write to prcharge
// read to precharge and
// activate to precharge
// precharge_ok_cnt_r is added with trtp count,
// there can be cases where the sm can go from
// activate to read and the act->pre count time
// would not have been satisfied. The rd->pre
// time is very less. wr->pre time is almost the
// same as act-> pre
always @(posedge clk) begin
if (state_r == CTRL_BURST_READ) begin
// assign only if the cnt is < TRTP_COUNT
if (precharge_ok_cnt_r < TRTP_COUNT)
precharge_ok_cnt_r <= TRTP_COUNT;
end else if (state_r == CTRL_BURST_WRITE)
precharge_ok_cnt_r <= TWR_COUNT;
else if (state_r == CTRL_ACTIVE)
if (precharge_ok_cnt_r <= TRAS_COUNT)
precharge_ok_cnt_r <= TRAS_COUNT;
else
precharge_ok_cnt_r <= precharge_ok_cnt_r - 1;
else if (precharge_ok_cnt_r != 5'd0)
precharge_ok_cnt_r <= precharge_ok_cnt_r - 1;
end
always @(posedge clk) begin
if ((state_r == CTRL_BURST_READ) ||
(state_r == CTRL_BURST_WRITE)||
(state_r == CTRL_ACTIVE))
precharge_ok_r <= 1'd0;
else if(precharge_ok_cnt_r <= 5'd3)
precharge_ok_r <=1'd1;
end
// write to read counter
// write to read includes : write latency + burst time + tWTR
always @(posedge clk) begin
if (rst_r1)
wr_to_rd_cnt_r <= 5'd0;
else if (state_r == CTRL_BURST_WRITE)
wr_to_rd_cnt_r <= (TWTR_COUNT);
else if (wr_to_rd_cnt_r != 5'd0)
wr_to_rd_cnt_r <= wr_to_rd_cnt_r - 1;
end
always @(posedge clk) begin
if (state_r == CTRL_BURST_WRITE)
wr_to_rd_ok_r <= 1'd0;
else if (wr_to_rd_cnt_r <= 5'd3)
wr_to_rd_ok_r <= 1'd1;
end
// read to write counter
always @(posedge clk) begin
if (rst_r1)
rd_to_wr_cnt_r <= 5'd0;
else if (state_r == CTRL_BURST_READ)
rd_to_wr_cnt_r <= (TRTW_COUNT);
else if (rd_to_wr_cnt_r != 5'd0)
rd_to_wr_cnt_r <= rd_to_wr_cnt_r - 1;
end
always @(posedge clk) begin
if (state_r == CTRL_BURST_READ)
rd_to_wr_ok_r <= 1'b0;
else if (rd_to_wr_cnt_r <= 5'd3)
rd_to_wr_ok_r <= 1'b1;
end
always @(posedge clk) begin
if(refi_cnt_r == (TREFI_COUNT -1))
refi_cnt_ok_r <= 1'b1;
else
refi_cnt_ok_r <= 1'b0;
end
// auto refresh interval counter in refresh_clk domain
always @(posedge clk) begin
if ((rst_r1) || (refi_cnt_ok_r)) begin
refi_cnt_r <= 12'd0;
end else begin
refi_cnt_r <= refi_cnt_r + 1;
end
end // always @ (posedge clk)
// auto refresh flag
always @(posedge clk) begin
if (refi_cnt_ok_r) begin
ref_flag_r <= 1'b1;
end else begin
ref_flag_r <= 1'b0;
end
end // always @ (posedge clk)
assign ctrl_ref_flag = ref_flag_r;
//refresh flag detect
//auto_ref high indicates auto_refresh requirement
//auto_ref is held high until auto refresh command is issued.
always @(posedge clk)begin
if (rst_r1)
auto_ref_r <= 1'b0;
else if (ref_flag_r)
auto_ref_r <= 1'b1;
else if (state_r == CTRL_AUTO_REFRESH)
auto_ref_r <= 1'b0;
end
// keep track of which chip selects got auto-refreshed (avoid auto-refreshing
// all CS's at once to avoid current spike)
always @(posedge clk)begin
if (rst_r1 || (state_r1 == CTRL_PRECHARGE))
auto_cnt_r <= 'd0;
else if (state_r1 == CTRL_AUTO_REFRESH)
auto_cnt_r <= auto_cnt_r + 1;
end
// register for timing purposes. Extra delay doesn't really matter
always @(posedge clk)
phy_init_done_r <= phy_init_done;
always @(posedge clk)begin
if (rst_r1) begin
state_r <= CTRL_IDLE;
state_r1 <= CTRL_IDLE;
end else begin
state_r <= next_state;
state_r1 <= state_r;
end
end
//***************************************************************************
// main control state machine
//***************************************************************************
always @(*) begin
next_state = state_r;
(* full_case, parallel_case *) case (state_r)
CTRL_IDLE: begin
// perform auto refresh as soon as we are done with calibration.
// The calibration logic does not do any refreshes.
if (phy_init_done_r)
next_state = CTRL_AUTO_REFRESH;
end
CTRL_PRECHARGE: begin
if (auto_ref_r)
next_state = CTRL_PRECHARGE_WAIT1;
// when precharging an LRU bank, do not have to go to wait state
// since we can't possibly be activating row in same bank next
// disabled for 2t timing. There needs to be a gap between cmds
// in 2t timing
else if (no_precharge_wait_r && !TWO_T_TIME_EN)
next_state = CTRL_ACTIVE;
else
next_state = CTRL_PRECHARGE_WAIT;
end
CTRL_PRECHARGE_WAIT:begin
if (rp_cnt_ok_r)begin
if (auto_ref_r)
// precharge again to make sure we close all the banks
next_state = CTRL_PRECHARGE;
else
next_state = CTRL_ACTIVE;
end
end
CTRL_PRECHARGE_WAIT1:
if (rp_cnt_ok_r)
next_state = CTRL_AUTO_REFRESH;
CTRL_AUTO_REFRESH:
next_state = CTRL_AUTO_REFRESH_WAIT;
CTRL_AUTO_REFRESH_WAIT:
//staggering Auto refresh for multi
// chip select designs. The SM waits
// for the rfc time before issuing the
// next auto refresh.
if (auto_cnt_r < (CS_NUM))begin
if (rfc_ok_r )
next_state = CTRL_AUTO_REFRESH;
end else if (rfc_ok_r)begin
if(auto_ref_r)
// MIG 2.3: For deep designs if Auto Refresh
// flag asserted immediately after calibration is completed
next_state = CTRL_PRECHARGE;
else if ( wr_flag || rd_flag)
next_state = CTRL_ACTIVE;
end
CTRL_ACTIVE:
next_state = CTRL_ACTIVE_WAIT;
CTRL_ACTIVE_WAIT: begin
if (rcd_cnt_ok_r) begin
if ((conflict_detect_r && ~conflict_resolved_r) ||
auto_ref_r) begin
if (no_precharge_r1 && ~auto_ref_r && trrd_cnt_ok_r)
next_state = CTRL_ACTIVE;
else if(precharge_ok_r)
next_state = CTRL_PRECHARGE;
end else if ((wr_flag_r) && (rd_to_wr_ok_r))
next_state = CTRL_BURST_WRITE;
else if ((rd_flag_r)&& (wr_to_rd_ok_r))
next_state = CTRL_BURST_READ;
end
end
// beginning of write burst
CTRL_BURST_WRITE: begin
if (BURST_LEN_DIV2 == 1) begin
// special case if BL = 2 (i.e. burst lasts only one clk cycle)
if (wr_flag)
// if we have another non-conflict write command right after the
// current write, then stay in this state
next_state = CTRL_BURST_WRITE;
else
// otherwise, if we're done with this burst, and have no write
// immediately scheduled after this one, wait until write-read
// delay has passed
next_state = CTRL_WRITE_WAIT;
end else
// otherwise BL > 2, and we have at least one more write cycle for
// current burst
next_state = CTRL_WRITE_WAIT;
// continuation of write burst (also covers waiting after write burst
// has completed for write-read delay to pass)
end
CTRL_WRITE_WAIT: begin
if ((conflict_detect) || auto_ref_r) begin
if (no_precharge_r && ~auto_ref_r && wrburst_ok_r)
next_state = CTRL_ACTIVE;
else if (precharge_ok_r)
next_state = CTRL_PRECHARGE;
end else if (wrburst_ok_r && wr_flag)
next_state = CTRL_BURST_WRITE;
else if ((rd_flag) && (wr_to_rd_ok_r))
next_state = CTRL_BURST_READ;
end
CTRL_BURST_READ: begin
if (BURST_LEN_DIV2 == 1) begin
// special case if BL = 2 (i.e. burst lasts only one clk cycle)
if (rd_flag)
next_state = CTRL_BURST_READ;
else
next_state = CTRL_READ_WAIT;
end else
next_state = CTRL_READ_WAIT;
end
CTRL_READ_WAIT: begin
if ((conflict_detect) || auto_ref_r)begin
if (no_precharge_r && ~auto_ref_r && rdburst_ok_r)
next_state = CTRL_ACTIVE;
else if (precharge_ok_r)
next_state = CTRL_PRECHARGE;
// for burst of 4 in multi chip select
// if there is a change in cs wait one cycle before the
// next read command. cs_change_r will be asserted.
end else if (rdburst_ok_r && rd_flag && ~cs_change_r)
next_state = CTRL_BURST_READ;
else if (wr_flag && (rd_to_wr_ok_r))
next_state = CTRL_BURST_WRITE;
end
endcase
end
//***************************************************************************
// control signals to memory
//***************************************************************************
always @(posedge clk) begin
if ((state_r == CTRL_AUTO_REFRESH) ||
(state_r == CTRL_ACTIVE) ||
(state_r == CTRL_PRECHARGE)) begin
ddr_ras_n_r <= 1'b0;
two_t_enable_r[0] <= 1'b0;
end else begin
if (TWO_T_TIME_EN)
ddr_ras_n_r <= two_t_enable_r[0] ;
else
ddr_ras_n_r <= 1'd1;
two_t_enable_r[0] <= 1'b1;
end
end
always @(posedge clk)begin
if ((state_r == CTRL_BURST_WRITE) ||
(state_r == CTRL_BURST_READ) ||
(state_r == CTRL_AUTO_REFRESH)) begin
ddr_cas_n_r <= 1'b0;
two_t_enable_r[1] <= 1'b0;
end else begin
if (TWO_T_TIME_EN)
ddr_cas_n_r <= two_t_enable_r[1];
else
ddr_cas_n_r <= 1'b1;
two_t_enable_r[1] <= 1'b1;
end
end
always @(posedge clk) begin
if ((state_r == CTRL_BURST_WRITE) ||
(state_r == CTRL_PRECHARGE)) begin
ddr_we_n_r <= 1'b0;
two_t_enable_r[2] <= 1'b0;
end else begin
if(TWO_T_TIME_EN)
ddr_we_n_r <= two_t_enable_r[2];
else
ddr_we_n_r <= 1'b1;
two_t_enable_r[2] <= 1'b1;
end
end
// turn off auto-precharge when issuing commands (A10 = 0)
// mapping the col add for linear addressing.
generate
if (TWO_T_TIME_EN) begin: gen_addr_col_two_t
if (COL_WIDTH == ROW_WIDTH-1) begin: gen_ddr_addr_col_0
assign ddr_addr_col = {af_addr_r3[COL_WIDTH-1:10], 1'b0,
af_addr_r3[9:0]};
end else begin
if (COL_WIDTH > 10) begin: gen_ddr_addr_col_1
assign ddr_addr_col = {{(ROW_WIDTH-COL_WIDTH-1){1'b0}},
af_addr_r3[COL_WIDTH-1:10], 1'b0,
af_addr_r3[9:0]};
end else begin: gen_ddr_addr_col_2
assign ddr_addr_col = {{(ROW_WIDTH-COL_WIDTH-1){1'b0}}, 1'b0,
af_addr_r3[COL_WIDTH-1:0]};
end
end
end else begin: gen_addr_col_one_t
if (COL_WIDTH == ROW_WIDTH-1) begin: gen_ddr_addr_col_0_1
assign ddr_addr_col = {af_addr_r2[COL_WIDTH-1:10], 1'b0,
af_addr_r2[9:0]};
end else begin
if (COL_WIDTH > 10) begin: gen_ddr_addr_col_1_1
assign ddr_addr_col = {{(ROW_WIDTH-COL_WIDTH-1){1'b0}},
af_addr_r2[COL_WIDTH-1:10], 1'b0,
af_addr_r2[9:0]};
end else begin: gen_ddr_addr_col_2_1
assign ddr_addr_col = {{(ROW_WIDTH-COL_WIDTH-1){1'b0}}, 1'b0,
af_addr_r2[COL_WIDTH-1:0]};
end
end
end
endgenerate
// Assign address during row activate
generate
if (TWO_T_TIME_EN)
assign ddr_addr_row = af_addr_r3[ROW_RANGE_END:ROW_RANGE_START];
else
assign ddr_addr_row = af_addr_r2[ROW_RANGE_END:ROW_RANGE_START];
endgenerate
always @(posedge clk)begin
if ((state_r == CTRL_ACTIVE) ||
((state_r1 == CTRL_ACTIVE) && TWO_T_TIME_EN))
ddr_addr_r <= ddr_addr_row;
else if ((state_r == CTRL_BURST_WRITE) ||
(state_r == CTRL_BURST_READ) ||
(((state_r1 == CTRL_BURST_WRITE) ||
(state_r1 == CTRL_BURST_READ)) &&
TWO_T_TIME_EN))
ddr_addr_r <= ddr_addr_col;
else if (((state_r == CTRL_PRECHARGE) ||
((state_r1 == CTRL_PRECHARGE) && TWO_T_TIME_EN))
&& auto_ref_r) begin
// if we're precharging as a result of AUTO-REFRESH, precharge all banks
ddr_addr_r <= {ROW_WIDTH{1'b0}};
ddr_addr_r[10] <= 1'b1;
end else if ((state_r == CTRL_PRECHARGE) ||
((state_r1 == CTRL_PRECHARGE) && TWO_T_TIME_EN))
// if we're precharging to close a specific bank/row, set A10=0
ddr_addr_r <= {ROW_WIDTH{1'b0}};
else
ddr_addr_r <= {ROW_WIDTH{1'bx}};
end
always @(posedge clk)begin
// whenever we're precharging, we're either: (1) precharging all banks (in
// which case banks bits are don't care, (2) precharging the LRU bank,
// b/c we've exceeded the limit of # of banks open (need to close the LRU
// bank to make room for a new one), (3) we haven't exceed the maximum #
// of banks open, but we trying to open a different row in a bank that's
// already open
if (((state_r == CTRL_PRECHARGE) ||
((state_r1 == CTRL_PRECHARGE) && TWO_T_TIME_EN)) &&
bank_conflict_r && MULTI_BANK_EN)
// When LRU bank needs to be closed
ddr_ba_r <= bank_cmp_addr_r[(3*CMP_WIDTH)+CMP_BANK_RANGE_END:
(3*CMP_WIDTH)+CMP_BANK_RANGE_START];
else begin
// Either precharge due to refresh or bank hit case
if (TWO_T_TIME_EN)
ddr_ba_r <= af_addr_r3[BANK_RANGE_END:BANK_RANGE_START];
else
ddr_ba_r <= af_addr_r2[BANK_RANGE_END:BANK_RANGE_START];
end
end
// chip enable generation logic
generate
// if only one chip select, always assert it after reset
if (CS_BITS == 0) begin: gen_ddr_cs_0
always @(posedge clk)
if (rst_r1)
ddr_cs_n_r[0] <= 1'b1;
else
ddr_cs_n_r[0] <= 1'b0;
// otherwise if we have multiple chip selects
end else begin: gen_ddr_cs_1
if(TWO_T_TIME_EN) begin: gen_2t_cs
always @(posedge clk)
if (rst_r1)
ddr_cs_n_r <= {CS_NUM{1'b1}};
else if ((state_r1 == CTRL_AUTO_REFRESH)) begin
// if auto-refreshing, only auto-refresh one CS at any time (avoid
// beating on the ground plane by refreshing all CS's at same time)
ddr_cs_n_r <= {CS_NUM{1'b1}};
ddr_cs_n_r[auto_cnt_r] <= 1'b0;
end else if (auto_ref_r && (state_r1 == CTRL_PRECHARGE)) begin
ddr_cs_n_r <= {CS_NUM{1'b0}};
end else if ((state_r1 == CTRL_PRECHARGE) && ( bank_conflict_r
&& MULTI_BANK_EN))begin
// precharging the LRU bank
ddr_cs_n_r <= {CS_NUM{1'b1}};
ddr_cs_n_r[bank_cmp_addr_r[(3*CMP_WIDTH)+CMP_CS_RANGE_END:
(3*CMP_WIDTH)+CMP_CS_RANGE_START]] <= 1'b0;
end else begin
// otherwise, check the upper address bits to see which CS to assert
ddr_cs_n_r <= {CS_NUM{1'b1}};
ddr_cs_n_r[af_addr_r3[CS_RANGE_END:CS_RANGE_START]] <= 1'b0;
end // else: !if(((state_r == CTRL_PRECHARGE) ||...
end else begin: gen_1t_cs // block: gen_2t_cs
always @(posedge clk)
if (rst_r1)
ddr_cs_n_r <= {CS_NUM{1'b1}};
else if ((state_r == CTRL_AUTO_REFRESH) ) begin
// if auto-refreshing, only auto-refresh one CS at any time (avoid
// beating on the ground plane by refreshing all CS's at same time)
ddr_cs_n_r <= {CS_NUM{1'b1}};
ddr_cs_n_r[auto_cnt_r] <= 1'b0;
end else if (auto_ref_r && (state_r == CTRL_PRECHARGE) ) begin
ddr_cs_n_r <= {CS_NUM{1'b0}};
end else if ((state_r == CTRL_PRECHARGE) &&
(bank_conflict_r && MULTI_BANK_EN))begin
// precharging the LRU bank
ddr_cs_n_r <= {CS_NUM{1'b1}};
ddr_cs_n_r[bank_cmp_addr_r[(3*CMP_WIDTH)+CMP_CS_RANGE_END:
(3*CMP_WIDTH)+CMP_CS_RANGE_START]] <= 1'b0;
end else begin
// otherwise, check the upper address bits to see which CS to assert
ddr_cs_n_r <= {CS_NUM{1'b1}};
ddr_cs_n_r[af_addr_r2[CS_RANGE_END:CS_RANGE_START]] <= 1'b0;
end // else: !if(((state_r == CTRL_PRECHARGE) ||...
end // block: gen_1t_cs
end
endgenerate
// registring the two_t timing enable signal.
// This signal will be asserted (low) when the
// chip select has to be asserted.
always @(posedge clk)begin
if(&two_t_enable_r)
two_t_enable_r1 <= {CS_NUM{1'b1}};
else
two_t_enable_r1 <= {CS_NUM{1'b0}};
end
assign ctrl_addr = ddr_addr_r;
assign ctrl_ba = ddr_ba_r;
assign ctrl_ras_n = ddr_ras_n_r;
assign ctrl_cas_n = ddr_cas_n_r;
assign ctrl_we_n = ddr_we_n_r;
assign ctrl_cs_n = (TWO_T_TIME_EN) ?
(ddr_cs_n_r | two_t_enable_r1) :
ddr_cs_n_r;
endmodule
|
(** * Hoare: Hoare Logic, Part I *)
Set Warnings "-notation-overridden,-parsing".
Require Import Coq.Bool.Bool.
Require Import Coq.Arith.Arith.
Require Import Coq.Arith.EqNat.
Require Import Coq.omega.Omega.
Require Import Imp.
Require Import Maps.
(** In the final chaper of _Logical Foundations_ (_Software
Foundations_, volume 1), we began applying the mathematical tools
developed in the first part of the course to studying the theory
of a small programming language, Imp.
- We defined a type of _abstract syntax trees_ for Imp, together
with an _evaluation relation_ (a partial function on states)
that specifies the _operational semantics_ of programs.
The language we defined, though small, captures some of the key
features of full-blown languages like C, C++, and Java,
including the fundamental notion of mutable state and some
common control structures.
- We proved a number of _metatheoretic properties_ -- "meta" in
the sense that they are properties of the language as a whole,
rather than of particular programs in the language. These
included:
- determinism of evaluation
- equivalence of some different ways of writing down the
definitions (e.g., functional and relational definitions of
arithmetic expression evaluation)
- guaranteed termination of certain classes of programs
- correctness (in the sense of preserving meaning) of a number
of useful program transformations
- behavioral equivalence of programs (in the [Equiv]
chapter).
If we stopped here, we would already have something useful: a set
of tools for defining and discussing programming languages and
language features that are mathematically precise, flexible, and
easy to work with, applied to a set of key properties. All of
these properties are things that language designers, compiler
writers, and users might care about knowing. Indeed, many of them
are so fundamental to our understanding of the programming
languages we deal with that we might not consciously recognize
them as "theorems." But properties that seem intuitively obvious
can sometimes be quite subtle (sometimes also subtly wrong!).
We'll return to the theme of metatheoretic properties of whole
languages later in this volume when we discuss _types_ and _type
soundness_. In this chapter, though, we turn to a different set
of issues.
Our goal is to carry out some simple examples of _program
verification_ -- i.e., to use the precise definition of Imp to
prove formally that particular programs satisfy particular
specifications of their behavior. We'll develop a reasoning
system called _Floyd-Hoare Logic_ -- often shortened to just
_Hoare Logic_ -- in which each of the syntactic constructs of Imp
is equipped with a generic "proof rule" that can be used to reason
compositionally about the correctness of programs involving this
construct.
Hoare Logic originated in the 1960s, and it continues to be the
subject of intensive research right up to the present day. It
lies at the core of a multitude of tools that are being used in
academia and industry to specify and verify real software systems.
Hoare Logic combines two beautiful ideas: a natural way of writing
down _specifications_ of programs, and a _compositional proof
technique_ for proving that programs are correct with respect to
such specifications -- where by "compositional" we mean that the
structure of proofs directly mirrors the structure of the programs
that they are about. *)
(** This chapter:
- A systematic method for reasoning about the correctness of
particular programs in Imp
Goals:
- a natural notation for _program specifications_ and
- a _compositional_ proof technique for program correctness
Plan:
- assertions (Hoare Triples)
- proof rules
- decorated programs
- loop invariants
- examples *)
(* ################################################################# *)
(** * Assertions *)
(** To talk about specifications of programs, the first thing we
need is a way of making _assertions_ about properties that hold at
particular points during a program's execution -- i.e., claims
about the current state of the memory when execution reaches that
point. Formally, an assertion is just a family of propositions
indexed by a [state]. *)
Definition Assertion := state -> Prop.
(** **** Exercise: 1 star, optional (assertions) *)
(** Paraphrase the following assertions in English (or your favorite
natural language). *)
Module ExAssertions.
Definition as1 : Assertion := fun st => st X = 3.
Definition as2 : Assertion := fun st => st X <= st Y.
Definition as3 : Assertion :=
fun st => st X = 3 \/ st X <= st Y.
Definition as4 : Assertion :=
fun st => st Z * st Z <= st X /\
~ (((S (st Z)) * (S (st Z))) <= st X).
Definition as5 : Assertion := fun st => True.
Definition as6 : Assertion := fun st => False.
(* FILL IN HERE *)
End ExAssertions.
(** [] *)
(** This way of writing assertions can be a little bit heavy,
for two reasons: (1) every single assertion that we ever write is
going to begin with [fun st => ]; and (2) this state [st] is the
only one that we ever use to look up variables in assertions (we
will never need to talk about two different memory states at the
same time). For discussing examples informally, we'll adopt some
simplifying conventions: we'll drop the initial [fun st =>], and
we'll write just [X] to mean [st X]. Thus, instead of writing *)
(**
fun st => (st Z) * (st Z) <= m /\
~ ((S (st Z)) * (S (st Z)) <= m)
we'll write just
Z * Z <= m /\ ~((S Z) * (S Z) <= m).
*)
(** This example also illustrates a convention that we'll use
throughout the Hoare Logic chapters: in informal assertions,
capital letters like [X], [Y], and [Z] are Imp variables, while
lowercase letters like [x], [y], [m], and [n] are ordinary Coq
variables (of type [nat]). This is why, when translating from
informal to formal, we replace [X] with [st X] but leave [m]
alone. *)
(** Given two assertions [P] and [Q], we say that [P] _implies_ [Q],
written [P ->> Q] (in ASCII, [P -][>][> Q]), if, whenever [P]
holds in some state [st], [Q] also holds. *)
Definition assert_implies (P Q : Assertion) : Prop :=
forall st, P st -> Q st.
Notation "P ->> Q" := (assert_implies P Q)
(at level 80) : hoare_spec_scope.
Open Scope hoare_spec_scope.
(** (The [hoare_spec_scope] annotation here tells Coq that this
notation is not global but is intended to be used in particular
contexts. The [Open Scope] tells Coq that this file is one such
context.) *)
(** We'll also want the "iff" variant of implication between
assertions: *)
Notation "P <<->> Q" :=
(P ->> Q /\ Q ->> P) (at level 80) : hoare_spec_scope.
(* ################################################################# *)
(** * Hoare Triples *)
(** Next, we need a way of making formal claims about the
behavior of commands. *)
(** In general, the behavior of a command is to transform one state to
another, so it is natural to express claims about commands in
terms of assertions that are true before and after the command
executes:
- "If command [c] is started in a state satisfying assertion
[P], and if [c] eventually terminates in some final state,
then this final state will satisfy the assertion [Q]."
Such a claim is called a _Hoare Triple_. The property [P] is
called the _precondition_ of [c], while [Q] is the
_postcondition_. Formally: *)
Definition hoare_triple
(P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st \\ st' ->
P st ->
Q st'.
(** Since we'll be working a lot with Hoare triples, it's useful to
have a compact notation:
{{P}} c {{Q}}.
*)
(** (The traditional notation is [{P} c {Q}], but single braces
are already used for other things in Coq.) *)
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level)
: hoare_spec_scope.
(** **** Exercise: 1 star, optional (triples) *)
(** Paraphrase the following Hoare triples in English.
1) {{True}} c {{X = 5}}
2) {{X = m}} c {{X = m + 5)}}
3) {{X <= Y}} c {{Y <= X}}
4) {{True}} c {{False}}
5) {{X = m}}
c
{{Y = real_fact m}}
6) {{True}}
c
{{(Z * Z) <= m /\ ~ (((S Z) * (S Z)) <= m)}}
*)
(** [] *)
(** **** Exercise: 1 star, optional (valid_triples) *)
(** Which of the following Hoare triples are _valid_ -- i.e., the
claimed relation between [P], [c], and [Q] is true?
1) {{True}} X ::= 5 {{X = 5}}
2) {{X = 2}} X ::= X + 1 {{X = 3}}
3) {{True}} X ::= 5; Y ::= 0 {{X = 5}}
4) {{X = 2 /\ X = 3}} X ::= 5 {{X = 0}}
5) {{True}} SKIP {{False}}
6) {{False}} SKIP {{True}}
7) {{True}} WHILE True DO SKIP END {{False}}
8) {{X = 0}}
WHILE X == 0 DO X ::= X + 1 END
{{X = 1}}
9) {{X = 1}}
WHILE X <> 0 DO X ::= X + 1 END
{{X = 100}}
*)
(*
True: 1, 2, 3, 6
False: 4?, 5, 7?, 8, 9
*)
(** [] *)
(** (Note that we're using informal mathematical notations for
expressions inside of commands, for readability, rather than their
formal [aexp] and [bexp] encodings. We'll continue doing so
throughout the chapter.)
To get us warmed up for what's coming, here are two simple
facts about Hoare triples. *)
Theorem hoare_post_true : forall (P Q : Assertion) c,
(forall st, Q st) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
apply H. Qed.
Theorem hoare_pre_false : forall (P Q : Assertion) c,
(forall st, ~(P st)) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
unfold not in H. apply H in HP.
inversion HP. Qed.
(* ################################################################# *)
(** * Proof Rules *)
(** The goal of Hoare logic is to provide a _compositional_
method for proving the validity of specific Hoare triples. That
is, we want the structure of a program's correctness proof to
mirror the structure of the program itself. To this end, in the
sections below, we'll introduce a rule for reasoning about each of
the different syntactic forms of commands in Imp -- one for
assignment, one for sequencing, one for conditionals, etc. -- plus
a couple of "structural" rules for gluing things together. We
will then be able to prove programs correct using these proof
rules, without ever unfolding the definition of [hoare_triple]. *)
(* ================================================================= *)
(** ** Assignment *)
(** The rule for assignment is the most fundamental of the Hoare logic
proof rules. Here's how it works.
Consider this valid Hoare triple:
{{ Y = 1 }} X ::= Y {{ X = 1 }}
In English: if we start out in a state where the value of [Y]
is [1] and we assign [Y] to [X], then we'll finish in a
state where [X] is [1].
That is, the property of being equal to [1] gets transferred
from [Y] to [X].
Similarly, in
{{ Y + Z = 1 }} X ::= Y + Z {{ X = 1 }}
the same property (being equal to one) gets transferred to
[X] from the expression [Y + Z] on the right-hand side of
the assignment. *)
(** More generally, if [a] is _any_ arithmetic expression, then
{{ a = 1 }} X ::= a {{ X = 1 }}
is a valid Hoare triple. *)
(** This can be made even more general. To conclude that an
arbitrary property [Q] holds after [X ::= a], we need to assume
that [Q] holds before [X ::= a], but _with all occurrences of_ [X]
replaced by [a] in [Q]. This leads to the Hoare rule for
assignment
{{ Q [X |-> a] }} X ::= a {{ Q }}
where "[Q [X |-> a]]" is pronounced "[Q] where [a] is substituted
for [X]". *)
(** For example, these are valid applications of the assignment
rule:
{{ (X <= 5) [X |-> X + 1]
i.e., X + 1 <= 5 }}
X ::= X + 1
{{ X <= 5 }}
{{ (X = 3) [X |-> 3]
i.e., 3 = 3}}
X ::= 3
{{ X = 3 }}
{{ (0 <= X /\ X <= 5) [X |-> 3]
i.e., (0 <= 3 /\ 3 <= 5)}}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
*)
(** To formalize the rule, we must first formalize the idea of
"substituting an expression for an Imp variable in an assertion."
That is, given a proposition [P], a variable [X], and an
arithmetic expression [a], we want to derive another proposition
[P'] that is just the same as [P] except that, wherever [P]
mentions [X], [P'] should instead mention [a].
Since [P] is an arbitrary Coq proposition, we can't directly
"edit" its text. Instead, we can achieve the same effect by
evaluating [P] in an updated state: *)
Definition assn_sub X a P : Assertion :=
fun (st : state) =>
P (t_update st X (aeval st a)).
Notation "P [ X |-> a ]" := (assn_sub X a P) (at level 10).
(** That is, [P [X |-> a]] stands for an assertion -- let's call it [P'] --
that is just like [P] except that, wherever [P] looks up the
variable [X] in the current state, [P'] instead uses the value
of the expression [a]. *)
(** To see how this works, let's calculate what happens with a couple
of examples. First, suppose [P'] is [(X <= 5) [X |-> 3]] -- that
is, more formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(t_update st X (aeval st (ANum 3))),
which simplifies to
fun st =>
(fun st' => st' X <= 5)
(t_update st X 3)
and further simplifies to
fun st =>
((t_update st X 3) X) <= 5)
and finally to
fun st =>
(3 <= 5).
That is, [P'] is the assertion that [3] is less than or equal to
[5] (as expected). *)
(** For a more interesting example, suppose [P'] is [(X <= 5) [X |->
X+1]]. Formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(t_update st X (aeval st (APlus (AId X) (ANum 1)))),
which simplifies to
fun st =>
(((t_update st X (aeval st (APlus (AId X) (ANum 1))))) X) <= 5
and further simplifies to
fun st =>
(aeval st (APlus (AId X) (ANum 1))) <= 5.
That is, [P'] is the assertion that [X+1] is at most [5].
*)
(** Now, using the concept of substitution, we can give the precise
proof rule for assignment:
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X ::= a {{Q}}
*)
(** We can prove formally that this rule is indeed valid. *)
Theorem hoare_asgn : forall Q X a,
{{Q [X |-> a]}} (X ::= a) {{Q}}.
Proof.
unfold hoare_triple.
intros Q X a st st' HE HQ.
inversion HE. subst.
unfold assn_sub in HQ. assumption. Qed.
(** Here's a first formal proof using this rule. *)
Example assn_sub_example :
{{(fun st => st X = 3) [X |-> ANum 3]}}
(X ::= (ANum 3))
{{fun st => st X = 3}}.
Proof.
(* WORKED IN CLASS *)
apply hoare_asgn. Qed.
(** **** Exercise: 2 starsM (hoare_asgn_examples) *)
(** Translate these informal Hoare triples...
1) {{ (X <= 5) [X |-> X + 1] }}
X ::= X + 1
{{ X <= 5 }}
2) {{ (0 <= X /\ X <= 5) [X |-> 3] }}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
...into formal statements (use the names [assn_sub_ex1]
and [assn_sub_ex2]) and use [hoare_asgn] to prove them. *)
Example assn_sub_ex1 :
{{(fun st => st X <= 5) [X |-> APlus (AId X) (ANum 1)] }}
(X ::= APlus (AId X) (ANum 1))
{{fun st => st X <= 5 }}.
Proof.
apply hoare_asgn.
Qed.
Example assn_sub_ex2 :
{{(fun st => st X <= 0 /\ st X <= 5) [X |-> ANum 3] }}
(X ::= ANum 3)
{{fun st => st X <= 0 /\ st X <= 5 }}.
Proof.
apply hoare_asgn.
Qed.
(** [] *)
(** **** Exercise: 2 stars, recommendedM (hoare_asgn_wrong) *)
(** The assignment rule looks backward to almost everyone the first
time they see it. If it still seems puzzling, it may help
to think a little about alternative "forward" rules. Here is a
seemingly natural one:
------------------------------ (hoare_asgn_wrong)
{{ True }} X ::= a {{ X = a }}
Give a counterexample showing that this rule is incorrect and
argue informally that it is really a counterexample. (Hint:
The rule universally quantifies over the arithmetic expression
[a], and your counterexample needs to exhibit an [a] for which
the rule doesn't work.) *)
(* X + 1 would not work for a, because X is not defined in precondition *)
(** [] *)
(** **** Exercise: 3 stars, advanced (hoare_asgn_fwd) *)
(** However, by using a _parameter_ [m] (a Coq number) to remember the
original value of [X] we can define a Hoare rule for assignment
that does, intuitively, "work forwards" rather than backwards.
------------------------------------------ (hoare_asgn_fwd)
{{fun st => P st /\ st X = m}}
X ::= a
{{fun st => P st' /\ st X = aeval st' a }}
(where st' = t_update st X m)
Note that we use the original value of [X] to reconstruct the
state [st'] before the assignment took place. Prove that this rule
is correct. (Also note that this rule is more complicated than
[hoare_asgn].)
*)
Theorem hoare_asgn_fwd :
(forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g) ->
forall m a P,
{{fun st => P st /\ st X = m}}
X ::= a
{{fun st => P (t_update st X m)
/\ st X = aeval (t_update st X m) a }}.
Proof.
intros _ m a P.
unfold hoare_triple.
intros st st' Heval [HP HX].
inversion Heval; subst.
rewrite t_update_shadow.
rewrite t_update_same.
rewrite t_update_eq.
split; trivial.
Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced (hoare_asgn_fwd_exists) *)
(** Another way to define a forward rule for assignment is to
existentially quantify over the previous value of the assigned
variable.
------------------------------------ (hoare_asgn_fwd_exists)
{{fun st => P st}}
X ::= a
{{fun st => exists m, P (t_update st X m) /\
st X = aeval (t_update st X m) a }}
*)
Theorem hoare_asgn_fwd_exists :
(forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g) ->
forall a P,
{{fun st => P st}}
X ::= a
{{fun st => exists m, P (t_update st X m) /\
st X = aeval (t_update st X m) a }}.
Proof.
intros _ a P.
unfold hoare_triple.
intros st st' Heval He.
inversion Heval; subst.
eexists.
rewrite t_update_shadow.
rewrite t_update_same.
rewrite t_update_eq.
split; trivial.
Qed.
(** [] *)
(* ================================================================= *)
(** ** Consequence *)
(** Sometimes the preconditions and postconditions we get from the
Hoare rules won't quite be the ones we want in the particular
situation at hand -- they may be logically equivalent but have a
different syntactic form that fails to unify with the goal we are
trying to prove, or they actually may be logically weaker (for
preconditions) or stronger (for postconditions) than what we need.
For instance, while
{{(X = 3) [X |-> 3]}} X ::= 3 {{X = 3}},
follows directly from the assignment rule,
{{True}} X ::= 3 {{X = 3}}
does not. This triple is valid, but it is not an instance of
[hoare_asgn] because [True] and [(X = 3) [X |-> 3]] are not
syntactically equal assertions. However, they are logically
_equivalent_, so if one triple is valid, then the other must
certainly be as well. We can capture this observation with the
following rule:
{{P'}} c {{Q}}
P <<->> P'
----------------------------- (hoare_consequence_pre_equiv)
{{P}} c {{Q}}
*)
(** Taking this line of thought a bit further, we can see that
strengthening the precondition or weakening the postcondition of a
valid triple always produces another valid triple. This
observation is captured by two _Rules of Consequence_.
{{P'}} c {{Q}}
P ->> P'
----------------------------- (hoare_consequence_pre)
{{P}} c {{Q}}
{{P}} c {{Q'}}
Q' ->> Q
----------------------------- (hoare_consequence_post)
{{P}} c {{Q}}
*)
(** Here are the formal versions: *)
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Proof.
intros P P' Q c Hhoare Himp.
intros st st' Hc HP. apply (Hhoare st st').
assumption. apply Himp. assumption. Qed.
Theorem hoare_consequence_post : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P Q Q' c Hhoare Himp.
intros st st' Hc HP.
apply Himp.
apply (Hhoare st st').
assumption. assumption. Qed.
(** For example, we can use the first consequence rule like this:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1
{{ X = 1 }}
Or, formally... *)
Example hoare_asgn_example1 :
{{fun st => True}} (X ::= (ANum 1)) {{fun st => st X = 1}}.
Proof.
(* WORKED IN CLASS *)
apply hoare_consequence_pre
with (P' := (fun st => st X = 1) [X |-> ANum 1]).
apply hoare_asgn.
intros st H. unfold assn_sub, t_update. simpl. reflexivity.
Qed.
(** Finally, for convenience in proofs, we can state a combined
rule of consequence that allows us to vary both the precondition
and the postcondition at the same time.
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
*)
Theorem hoare_consequence : forall (P P' Q Q' : Assertion) c,
{{P'}} c {{Q'}} ->
P ->> P' ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P P' Q Q' c Hht HPP' HQ'Q.
apply hoare_consequence_pre with (P' := P').
apply hoare_consequence_post with (Q' := Q').
assumption. assumption. assumption. Qed.
(* ================================================================= *)
(** ** Digression: The [eapply] Tactic *)
(** This is a good moment to take another look at the [eapply] tactic,
which we introduced briefly in the \CHAPV1{Auto} chapter of
_Logical Foundations_.
We had to write "[with (P' := ...)]" explicitly in the proof of
[hoare_asgn_example1] and [hoare_consequence] above, to make sure
that all of the metavariables in the premises to the
[hoare_consequence_pre] rule would be set to specific
values. (Since [P'] doesn't appear in the conclusion of
[hoare_consequence_pre], the process of unifying the conclusion
with the current goal doesn't constrain [P'] to a specific
assertion.)
This is annoying, both because the assertion is a bit long and
also because, in [hoare_asgn_example1], the very next thing we are
going to do -- applying the [hoare_asgn] rule -- will tell us
exactly what it should be! We can use [eapply] instead of [apply]
to tell Coq, essentially, "Be patient: The missing part is going
to be filled in later in the proof." *)
Example hoare_asgn_example1' :
{{fun st => True}}
(X ::= (ANum 1))
{{fun st => st X = 1}}.
Proof.
eapply hoare_consequence_pre.
apply hoare_asgn.
intros st H. reflexivity. Qed.
(** In general, [eapply H] tactic works just like [apply H] except
that, instead of failing if unifying the goal with the conclusion
of [H] does not determine how to instantiate all of the variables
appearing in the premises of [H], [eapply H] will replace these
variables with _existential variables_ (written [?nnn]), which
function as placeholders for expressions that will be
determined (by further unification) later in the proof. *)
(** In order for [Qed] to succeed, all existential variables need to
be determined by the end of the proof. Otherwise Coq
will (rightly) refuse to accept the proof. Remember that the Coq
tactics build proof objects, and proof objects containing
existential variables are not complete. *)
Lemma silly1 : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(forall x y : nat, P x y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. apply HP.
(** Coq gives a warning after [apply HP]. ("All the remaining goals
are on the shelf," means that we've finished all our top-level
proof obligations but along the way we've put some aside to be
done later, and we have not finished those.) Trying to close the
proof with [Qed] gives an error. *)
Abort.
(** An additional constraint is that existential variables cannot be
instantiated with terms containing ordinary variables that did not
exist at the time the existential variable was created. (The
reason for this technical restriction is that allowing such
instantiation would lead to inconsistency of Coq's logic.) *)
Lemma silly2 :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. destruct HP as [y HP'].
(** Doing [apply HP'] above fails with the following error:
Error: Impossible to unify "?175" with "y".
In this case there is an easy fix: doing [destruct HP] _before_
doing [eapply HQ]. *)
Abort.
Lemma silly2_fixed :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP'].
eapply HQ. apply HP'.
Qed.
(** The [apply HP'] in the last step unifies the existential variable
in the goal with the variable [y].
Note that the [assumption] tactic doesn't work in this case, since
it cannot handle existential variables. However, Coq also
provides an [eassumption] tactic that solves the goal if one of
the premises matches the goal up to instantiations of existential
variables. We can use it instead of [apply HP'] if we like. *)
Lemma silly2_eassumption : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP']. eapply HQ. eassumption.
Qed.
(** **** Exercise: 2 starsM (hoare_asgn_examples_2) *)
(** Translate these informal Hoare triples...
{{ X + 1 <= 5 }} X ::= X + 1 {{ X <= 5 }}
{{ 0 <= 3 /\ 3 <= 5 }} X ::= 3 {{ 0 <= X /\ X <= 5 }}
...into formal statements (name them [assn_sub_ex1'] and
[assn_sub_ex2']) and use [hoare_asgn] and [hoare_consequence_pre]
to prove them. *)
Example assn_sub_ex1' :
{{fun st => st X + 1 <= 5 }}
X ::= APlus (AId X) (ANum 1)
{{fun st => st X <= 5 }}.
Proof.
eapply hoare_consequence_pre.
apply hoare_asgn.
unfold assert_implies, assn_sub.
intros. simpl. rewrite t_update_eq. assumption.
Qed.
Example assn_sub_ex2' :
{{fun st => 0 <= 3 /\ 3 <= 5 }}
X ::= ANum 3
{{fun st => 0 <= st X /\ st X <= 5 }}.
Proof.
eapply hoare_consequence_pre.
apply hoare_asgn.
unfold assert_implies, assn_sub. intros.
rewrite t_update_eq. simpl. trivial.
Qed.
(** [] *)
(* ================================================================= *)
(** ** Skip *)
(** Since [SKIP] doesn't change the state, it preserves any
property [P]:
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
*)
Theorem hoare_skip : forall P,
{{P}} SKIP {{P}}.
Proof.
intros P st st' H HP. inversion H. subst.
assumption. Qed.
(* ================================================================= *)
(** ** Sequencing *)
(** More interestingly, if the command [c1] takes any state where
[P] holds to a state where [Q] holds, and if [c2] takes any
state where [Q] holds to one where [R] holds, then doing [c1]
followed by [c2] will take any state where [P] holds to one
where [R] holds:
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
*)
Theorem hoare_seq : forall P Q R c1 c2,
{{Q}} c2 {{R}} ->
{{P}} c1 {{Q}} ->
{{P}} c1;;c2 {{R}}.
Proof.
intros P Q R c1 c2 H1 H2 st st' H12 Pre.
inversion H12; subst.
apply (H1 st'0 st'); try assumption.
apply (H2 st st'0); assumption. Qed.
(** Note that, in the formal rule [hoare_seq], the premises are
given in backwards order ([c2] before [c1]). This matches the
natural flow of information in many of the situations where we'll
use the rule, since the natural way to construct a Hoare-logic
proof is to begin at the end of the program (with the final
postcondition) and push postconditions backwards through commands
until we reach the beginning. *)
(** Informally, a nice way of displaying a proof using the sequencing
rule is as a "decorated program" where the intermediate assertion
[Q] is written between [c1] and [c2]:
{{ a = n }}
X ::= a;;
{{ X = n }} <---- decoration for Q
SKIP
{{ X = n }}
*)
(** Here's an example of a program involving both assignment and
sequencing. *)
Example hoare_asgn_example3 : forall a n,
{{fun st => aeval st a = n}}
(X ::= a;; SKIP)
{{fun st => st X = n}}.
Proof.
intros a n. eapply hoare_seq.
- (* right part of seq *)
apply hoare_skip.
- (* left part of seq *)
eapply hoare_consequence_pre. apply hoare_asgn.
intros st H. subst. reflexivity.
Qed.
(** We typically use [hoare_seq] in conjunction with
[hoare_consequence_pre] and the [eapply] tactic, as in this
example. *)
(** **** Exercise: 2 stars, recommended (hoare_asgn_example4) *)
(** Translate this "decorated program" into a formal proof:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1;;
{{ X = 1 }} ->>
{{ X = 1 /\ 2 = 2 }}
Y ::= 2
{{ X = 1 /\ Y = 2 }}
(Note the use of "[->>]" decorations, each marking a use of
[hoare_consequence_pre].) *)
Example hoare_asgn_example4 :
{{fun st => True}} (X ::= (ANum 1);; Y ::= (ANum 2))
{{fun st => st X = 1 /\ st Y = 2}}.
Proof.
apply hoare_seq with (fun st : state => st X = 1 /\ 2 = 2).
eapply hoare_consequence_pre. apply hoare_asgn.
intros st [Hx _]. cbv. auto.
apply hoare_consequence_post with (fun st : state => st X = 1).
eapply hoare_consequence_pre. apply hoare_asgn.
intros st _. reflexivity.
intros st H. auto.
Qed.
(** [] *)
(** **** Exercise: 3 stars (swap_exercise) *)
(** Write an Imp program [c] that swaps the values of [X] and [Y] and
show that it satisfies the following specification:
{{X <= Y}} c {{Y <= X}}
Your proof should not need to use [unfold hoare_triple]. *)
Definition swap_program : com :=
Z ::= AId X;;
X ::= AId Y;;
Y ::= AId X.
Theorem swap_exercise :
{{fun st => st X <= st Y}}
swap_program
{{fun st => st Y <= st X}}.
Proof.
(* Proof outline:
{{X <= Y}}
Z ::= AId X;;
{{X <= Y}} ->>
{{Y <= Y}}
X ::= AId Y;;
{{X <= Y}}
Y ::= AId X
{{Y <= X}}
*)
unfold swap_program.
eapply hoare_seq with (fun st : state => st Y <= st Y). eapply hoare_seq.
eapply hoare_consequence_pre with (fun st : state => st X <= st X).
eapply hoare_consequence_pre.
eapply hoare_asgn.
intros st _. cbv. reflexivity.
intros st _. reflexivity.
instantiate (1 := fun st : state => st X <= st Y).
eapply hoare_consequence_pre.
eapply hoare_asgn.
intro st. cbv. auto.
intros st st' _ _. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (hoarestate1) *)
(** Explain why the following proposition can't be proven:
forall (a : aexp) (n : nat),
{{fun st => aeval st a = n}}
(X ::= (ANum 3);; Y ::= a)
{{fun st => st Y = n}}.
*)
(* FILL IN HERE *)
(** [] *)
(* ================================================================= *)
(** ** Conditionals *)
(** What sort of rule do we want for reasoning about conditional
commands?
Certainly, if the same assertion [Q] holds after executing
either of the branches, then it holds after the whole conditional.
So we might be tempted to write:
{{P}} c1 {{Q}}
{{P}} c2 {{Q}}
--------------------------------
{{P}} IFB b THEN c1 ELSE c2 {{Q}}
*)
(** However, this is rather weak. For example, using this rule,
we cannot show
{{ True }}
IFB X == 0
THEN Y ::= 2
ELSE Y ::= X + 1
FI
{{ X <= Y }}
since the rule tells us nothing about the state in which the
assignments take place in the "then" and "else" branches. *)
(** Fortunately, we can say something more precise. In the
"then" branch, we know that the boolean expression [b] evaluates to
[true], and in the "else" branch, we know it evaluates to [false].
Making this information available in the premises of the rule gives
us more information to work with when reasoning about the behavior
of [c1] and [c2] (i.e., the reasons why they establish the
postcondition [Q]). *)
(**
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
*)
(** To interpret this rule formally, we need to do a little work.
Strictly speaking, the assertion we've written, [P /\ b], is the
conjunction of an assertion and a boolean expression -- i.e., it
doesn't typecheck. To fix this, we need a way of formally
"lifting" any bexp [b] to an assertion. We'll write [bassn b] for
the assertion "the boolean expression [b] evaluates to [true] (in
the given state)." *)
Definition bassn b : Assertion :=
fun st => (beval st b = true).
(** A couple of useful facts about [bassn]: *)
Lemma bexp_eval_true : forall b st,
beval st b = true -> (bassn b) st.
Proof.
intros b st Hbe.
unfold bassn. assumption. Qed.
Lemma bexp_eval_false : forall b st,
beval st b = false -> ~ ((bassn b) st).
Proof.
intros b st Hbe contra.
unfold bassn in contra.
rewrite -> contra in Hbe. inversion Hbe. Qed.
(** Now we can formalize the Hoare proof rule for conditionals
and prove it correct. *)
Theorem hoare_if : forall P Q b c1 c2,
{{fun st => P st /\ bassn b st}} c1 {{Q}} ->
{{fun st => P st /\ ~(bassn b st)}} c2 {{Q}} ->
{{P}} (IFB b THEN c1 ELSE c2 FI) {{Q}}.
Proof.
intros P Q b c1 c2 HTrue HFalse st st' HE HP.
inversion HE; subst.
- (* b is true *)
apply (HTrue st st').
assumption.
split. assumption.
apply bexp_eval_true. assumption.
- (* b is false *)
apply (HFalse st st').
assumption.
split. assumption.
apply bexp_eval_false. assumption. Qed.
(* ----------------------------------------------------------------- *)
(** *** Example *)
(** Here is a formal proof that the program we used to motivate the
rule satisfies the specification we gave. *)
Example if_example :
{{fun st => True}}
IFB (BEq (AId X) (ANum 0))
THEN (Y ::= (ANum 2))
ELSE (Y ::= APlus (AId X) (ANum 1))
FI
{{fun st => st X <= st Y}}.
Proof.
(* WORKED IN CLASS *)
apply hoare_if.
- (* Then *)
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub, t_update, assert_implies.
simpl. intros st [_ H].
apply beq_nat_true in H.
rewrite H. omega.
- (* Else *)
eapply hoare_consequence_pre. apply hoare_asgn.
unfold assn_sub, t_update, assert_implies.
simpl; intros st _. omega.
Qed.
(** **** Exercise: 2 stars (if_minus_plus) *)
(** Prove the following hoare triple using [hoare_if]. Do not
use [unfold hoare_triple]. *)
Theorem if_minus_plus :
{{fun st => True}}
IFB (BLe (AId X) (AId Y))
THEN (Z ::= AMinus (AId Y) (AId X))
ELSE (Y ::= APlus (AId X) (AId Z))
FI
{{fun st => st Y = st X + st Z}}.
Proof.
apply hoare_if.
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub, t_update, assert_implies.
simpl. intros st [_ H].
apply leb_complete in H. omega.
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub, t_update, assert_implies.
simpl. intros. omega.
Qed.
(** [] *)
(* ----------------------------------------------------------------- *)
(** *** Exercise: One-sided conditionals *)
(** **** Exercise: 4 starsM (if1_hoare) *)
(** In this exercise we consider extending Imp with "one-sided
conditionals" of the form [IF1 b THEN c FI]. Here [b] is a
boolean expression, and [c] is a command. If [b] evaluates to
[true], then command [c] is evaluated. If [b] evaluates to
[false], then [IF1 b THEN c FI] does nothing.
We recommend that you do this exercise before the ones that
follow, as it should help solidify your understanding of the
material. *)
(** The first step is to extend the syntax of commands and introduce
the usual notations. (We've done this for you. We use a separate
module to prevent polluting the global name space.) *)
Module If1.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CIf1 : bexp -> com -> com.
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'IF1' b 'THEN' c 'FI'" :=
(CIf1 b c) (at level 80, right associativity).
(** Next we need to extend the evaluation relation to accommodate
[IF1] branches. This is for you to do... What rule(s) need to be
added to [ceval] to evaluate one-sided conditionals? *)
Reserved Notation "c1 '/' st '\\' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st \\ st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st \\ t_update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st \\ st' -> c2 / st' \\ st'' -> (c1 ;; c2) / st \\ st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st \\ st' -> (IFB b1 THEN c1 ELSE c2 FI) / st \\ st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st \\ st' -> (IFB b1 THEN c1 ELSE c2 FI) / st \\ st'
| E_WhileFalse : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st \\ st
| E_WhileTrue : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st \\ st' ->
(WHILE b1 DO c1 END) / st' \\ st'' ->
(WHILE b1 DO c1 END) / st \\ st''
| E_If1True : forall (st st' : state) (b : bexp) (c : com),
beval st b = true ->
c / st \\ st' -> (IF1 b THEN c FI) / st \\ st'
| E_If1False : forall (st st' : state) (b : bexp) (c : com),
beval st b = false ->
(IF1 b THEN c FI) / st \\ st
where "c1 '/' st '\\' st'" := (ceval c1 st st').
(** Now we repeat (verbatim) the definition and notation of Hoare triples. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st \\ st' ->
P st ->
Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Finally, we (i.e., you) need to state and prove a theorem,
[hoare_if1], that expresses an appropriate Hoare logic proof rule
for one-sided conditionals. Try to come up with a rule that is
both sound and as precise as possible. *)
Theorem hoare_if1 : forall P Q b c,
{{fun st => P st /\ bassn b st}} c {{Q}} ->
{{fun st => P st /\ ~bassn b st}} SKIP {{Q}} ->
{{P}} (IF1 b THEN c FI) {{Q}}.
Proof.
intros P Q b c HTrue HFalse st st' HE HP.
inversion HE; subst.
apply (HTrue st st').
assumption. split. assumption. apply bexp_eval_true. assumption.
apply (HFalse st' st').
apply E_Skip.
apply bexp_eval_false in H3. split; assumption.
Qed.
(** For full credit, prove formally [hoare_if1_good] that your rule is
precise enough to show the following valid Hoare triple:
{{ X + Y = Z }}
IF1 Y <> 0 THEN
X ::= X + Y
FI
{{ X = Z }}
*)
(** Hint: Your proof of this triple may need to use the other proof
rules also. Because we're working in a separate module, you'll
need to copy here the rules you find necessary. *)
Lemma hoare_if1_good :
{{ fun st => st X + st Y = st Z }}
IF1 BNot (BEq (AId Y) (ANum 0)) THEN
X ::= APlus (AId X) (AId Y)
FI
{{ fun st => st X = st Z }}.
Proof.
apply hoare_if1.
intros st st' HAssn [H Hb].
inversion HAssn; subst. simpl. rewrite H.
destruct (beq_id X Z) eqn:Heq. rewrite beq_id_true_iff in Heq. rewrite Heq.
reflexivity.
rewrite beq_id_false_iff in Heq.
rewrite t_update_eq. rewrite t_update_neq. reflexivity. assumption.
intros st st' HAssn [H Hb].
inversion HAssn; subst.
unfold not, bassn in Hb. simpl in Hb.
destruct (st' Y =? 0) eqn:Heq. rewrite Nat.eqb_eq in Heq. rewrite Heq in H.
omega.
simpl in Hb. contradiction.
Qed.
End If1.
(** [] *)
(* ================================================================= *)
(** ** Loops *)
(** Finally, we need a rule for reasoning about while loops. *)
(** Suppose we have a loop
WHILE b DO c END
and we want to find a pre-condition [P] and a post-condition
[Q] such that
{{P}} WHILE b DO c END {{Q}}
is a valid triple. *)
(** First of all, let's think about the case where [b] is false at the
beginning -- i.e., let's assume that the loop body never executes
at all. In this case, the loop behaves like [SKIP], so we might
be tempted to write: *)
(**
{{P}} WHILE b DO c END {{P}}.
*)
(** But, as we remarked above for the conditional, we know a
little more at the end -- not just [P], but also the fact
that [b] is false in the current state. So we can enrich the
postcondition a little: *)
(**
{{P}} WHILE b DO c END {{P /\ ~b}}
*)
(** What about the case where the loop body _does_ get executed?
In order to ensure that [P] holds when the loop finally
exits, we certainly need to make sure that the command [c]
guarantees that [P] holds whenever [c] is finished.
Moreover, since [P] holds at the beginning of the first
execution of [c], and since each execution of [c]
re-establishes [P] when it finishes, we can always assume
that [P] holds at the beginning of [c]. This leads us to the
following rule: *)
(**
{{P}} c {{P}}
-----------------------------------
{{P}} WHILE b DO c END {{P /\ ~b}}
*)
(** This is almost the rule we want, but again it can be improved a
little: at the beginning of the loop body, we know not only that
[P] holds, but also that the guard [b] is true in the current
state. This gives us a little more information to use in
reasoning about [c] (showing that it establishes the invariant by
the time it finishes). This gives us the final version of the
rule:
*)
(**
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
The proposition [P] is called an _invariant_ of the loop.
*)
Lemma hoare_while : forall P b c,
{{fun st => P st /\ bassn b st}} c {{P}} ->
{{P}} WHILE b DO c END {{fun st => P st /\ ~ (bassn b st)}}.
Proof.
intros P b c Hhoare st st' He HP.
(* Like we've seen before, we need to reason by induction
on [He], because, in the "keep looping" case, its hypotheses
talk about the whole loop instead of just [c]. *)
remember (WHILE b DO c END) as wcom eqn:Heqwcom.
induction He;
try (inversion Heqwcom); subst; clear Heqwcom.
- (* E_WhileFalse *)
split. assumption. apply bexp_eval_false. assumption.
- (* E_WhileTrue *)
apply IHHe2. reflexivity.
apply (Hhoare st st'). assumption.
split. assumption. apply bexp_eval_true. assumption.
Qed.
(** One subtlety in the terminology is that calling some assertion [P]
a "loop invariant" doesn't just mean that it is preserved by the
body of the loop in question (i.e., [{{P}} c {{P}}], where [c] is
the loop body), but rather that [P] _together with the fact that
the loop's guard is true_ is a sufficient precondition for [c] to
ensure [P] as a postcondition.
This is a slightly (but significantly) weaker requirement. For
example, if [P] is the assertion [X = 0], then [P] _is_ an
invariant of the loop
WHILE X = 2 DO X := 1 END
although it is clearly _not_ preserved by the body of the
loop. *)
Example while_example :
{{fun st => st X <= 3}}
WHILE (BLe (AId X) (ANum 2))
DO X ::= APlus (AId X) (ANum 1) END
{{fun st => st X = 3}}.
Proof.
eapply hoare_consequence_post.
apply hoare_while.
eapply hoare_consequence_pre.
apply hoare_asgn.
unfold bassn, assn_sub, assert_implies, t_update. simpl.
intros st [H1 H2]. apply leb_complete in H2. omega.
unfold bassn, assert_implies. intros st [Hle Hb].
simpl in Hb. destruct (leb (st X) 2) eqn : Heqle.
exfalso. apply Hb; reflexivity.
apply leb_iff_conv in Heqle. omega.
Qed.
(** We can use the WHILE rule to prove the following Hoare triple... *)
Theorem always_loop_hoare : forall P Q,
{{P}} WHILE BTrue DO SKIP END {{Q}}.
Proof.
(* WORKED IN CLASS *)
intros P Q.
apply hoare_consequence_pre with (P' := fun st : state => True).
eapply hoare_consequence_post.
apply hoare_while.
- (* Loop body preserves invariant *)
apply hoare_post_true. intros st. apply I.
- (* Loop invariant and negated guard imply postcondition *)
simpl. intros st [Hinv Hguard].
exfalso. apply Hguard. reflexivity.
- (* Precondition implies invariant *)
intros st H. constructor. Qed.
(** Of course, this result is not surprising if we remember that
the definition of [hoare_triple] asserts that the postcondition
must hold _only_ when the command terminates. If the command
doesn't terminate, we can prove anything we like about the
post-condition. *)
(** Hoare rules that only talk about terminating commands are
often said to describe a logic of "partial" correctness. It is
also possible to give Hoare rules for "total" correctness, which
build in the fact that the commands terminate. However, in this
course we will only talk about partial correctness. *)
(* ----------------------------------------------------------------- *)
(** *** Exercise: [REPEAT] *)
(** **** Exercise: 4 stars, advancedM (hoare_repeat) *)
(** In this exercise, we'll add a new command to our language of
commands: [REPEAT] c [UNTIL] a [END]. You will write the
evaluation rule for [repeat] and add a new Hoare rule to the
language for programs involving it. (You may recall that the
evaluation rule is given in an example in the \CHAPV1{Auto} chapter.
Try to figure it out yourself here rather than peeking.) *)
Module RepeatExercise.
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CRepeat : com -> bexp -> com.
(** [REPEAT] behaves like [WHILE], except that the loop guard is
checked _after_ each execution of the body, with the loop
repeating as long as the guard stays _false_. Because of this,
the body will always execute at least once. *)
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'REPEAT' e1 'UNTIL' b2 'END'" :=
(CRepeat e1 b2) (at level 80, right associativity).
(** Add new rules for [REPEAT] to [ceval] below. You can use the rules
for [WHILE] as a guide, but remember that the body of a [REPEAT]
should always execute at least once, and that the loop ends when
the guard becomes true. Then update the [ceval_cases] tactic to
handle these added cases. *)
Inductive ceval : state -> com -> state -> Prop :=
| E_Skip : forall st,
ceval st SKIP st
| E_Ass : forall st a1 n X,
aeval st a1 = n ->
ceval st (X ::= a1) (t_update st X n)
| E_Seq : forall c1 c2 st st' st'',
ceval st c1 st' ->
ceval st' c2 st'' ->
ceval st (c1 ;; c2) st''
| E_IfTrue : forall st st' b1 c1 c2,
beval st b1 = true ->
ceval st c1 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_IfFalse : forall st st' b1 c1 c2,
beval st b1 = false ->
ceval st c2 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_WhileFalse : forall b1 st c1,
beval st b1 = false ->
ceval st (WHILE b1 DO c1 END) st
| E_WhileTrue : forall st st' st'' b1 c1,
beval st b1 = true ->
ceval st c1 st' ->
ceval st' (WHILE b1 DO c1 END) st'' ->
ceval st (WHILE b1 DO c1 END) st''
| E_RepeatFalse : forall b1 st st' st'' c1,
beval st b1 = false ->
ceval st c1 st' ->
ceval st' (REPEAT c1 UNTIL b1 END) st'' ->
ceval st (REPEAT c1 UNTIL b1 END) st''
| E_RepeatTrue : forall st st' b1 c1,
ceval st c1 st' ->
beval st' b1 = true ->
ceval st (REPEAT c1 UNTIL b1 END) st'.
Hint Constructors ceval.
(** A couple of definitions from above, copied here so they use the
new [ceval]. *)
Notation "c1 '/' st '\\' st'" := (ceval st c1 st')
(at level 40, st at level 39).
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion)
: Prop :=
forall st st', (c / st \\ st') -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level).
(** To make sure you've got the evaluation rules for [REPEAT] right,
prove that [ex1_repeat] evaluates correctly. *)
Definition ex1_repeat :=
REPEAT
X ::= ANum 1;;
Y ::= APlus (AId Y) (ANum 1)
UNTIL (BEq (AId X) (ANum 1)) END.
Theorem ex1_repeat_works :
ex1_repeat / empty_state \\
t_update (t_update empty_state X 1) Y 1.
Proof.
unfold ex1_repeat.
apply E_RepeatTrue.
eapply E_Seq. apply E_Ass. instantiate (1 := 1). trivial.
apply E_Ass. trivial. trivial.
Qed.
(** Now state and prove a theorem, [hoare_repeat], that expresses an
appropriate proof rule for [repeat] commands. Use [hoare_while]
as a model, and try to make your rule as precise as possible. *)
Lemma hoare_repeat : forall P Q b c,
{{fun st => Q st /\ ~ (bassn b st)}} c {{Q}} ->
{{P}} c {{Q}} ->
{{P}} REPEAT c UNTIL b END {{fun st => Q st /\ bassn b st}}.
Proof.
unfold hoare_triple.
intros P Q b c Hhoare Hhoare' st st' He HP.
generalize dependent P.
remember (REPEAT c UNTIL b END) as wcom eqn:Heqwcom.
induction He;
try (inversion Heqwcom); subst; intros P Hhoare' HP.
Focus 2.
split; inversion Heqwcom; subst.
eapply Hhoare'; eassumption.
apply bexp_eval_true. assumption.
inversion He2; subst.
(* FILL IN HERE *)
Admitted.
(** For full credit, make sure (informally) that your rule can be used
to prove the following valid Hoare triple:
{{ X > 0 }}
REPEAT
Y ::= X;;
X ::= X - 1
UNTIL X = 0 END
{{ X = 0 /\ Y > 0 }}
*)
(*
{{ X > 0 }} REPEAT Y ::= X;; X ::= X - 1 UNTIL X = 0 END {{ X = 0 /\ Y > 0 }}
We need to rewrite post-condition to match conclussion of hoare_repeat:
{{ X > 0 }} REPEAT Y ::= X;; X ::= X - 1 UNTIL X = 0 END {{ X = 0 /\ Y > 0 /\
X = 0 }}
Now apply hoare_repeat:
{{ X = 0 /\ Y > 0 /\ ~ (X = 0) }} Y ::= X;; X ::= X - 1 {{ X = 0 /\ Y > 0 }}
Pre-condition contains contradiction, so we use hoare_pre_false to finish the
proof.
*)
End RepeatExercise.
(** [] *)
(* ################################################################# *)
(** * Summary *)
(** So far, we've introduced Hoare Logic as a tool for reasoning about
Imp programs. In the reminder of this chapter we'll explore a
systematic way to use Hoare Logic to prove properties about
programs. The rules of Hoare Logic are:
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X::=a {{Q}}
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
In the next chapter, we'll see how these rules are used to prove
that programs satisfy specifications of their behavior. *)
(* ################################################################# *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (himp_hoare) *)
(** In this exercise, we will derive proof rules for the [HAVOC]
command, which we studied in the last chapter.
First, we enclose this work in a separate module, and recall the
syntax and big-step semantics of Himp commands. *)
Module Himp.
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CHavoc : id -> com.
Notation "'SKIP'" :=
CSkip.
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'HAVOC' X" := (CHavoc X) (at level 60).
Reserved Notation "c1 '/' st '\\' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st \\ st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st \\ t_update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st \\ st' -> c2 / st' \\ st'' -> (c1 ;; c2) / st \\ st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st \\ st' -> (IFB b1 THEN c1 ELSE c2 FI) / st \\ st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st \\ st' -> (IFB b1 THEN c1 ELSE c2 FI) / st \\ st'
| E_WhileFalse : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st \\ st
| E_WhileTrue : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st \\ st' ->
(WHILE b1 DO c1 END) / st' \\ st'' ->
(WHILE b1 DO c1 END) / st \\ st''
| E_Havoc : forall (st : state) (X : id) (n : nat),
(HAVOC X) / st \\ t_update st X n
where "c1 '/' st '\\' st'" := (ceval c1 st st').
(** The definition of Hoare triples is exactly as before. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st', c / st \\ st' -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Complete the Hoare rule for [HAVOC] commands below by defining
[havoc_pre] and prove that the resulting rule is correct. *)
Definition havoc_pre (X : id) (Q : Assertion) : Assertion
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Theorem hoare_havoc : forall (Q : Assertion) (X : id),
{{ havoc_pre X Q }} HAVOC X {{ Q }}.
Proof.
(* FILL IN HERE *) Admitted.
End Himp.
(** [] *)
(** $Date: 2017-05-24 10:56:51 -0400 (Wed, 24 May 2017) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22A_TB_V
`define SKY130_FD_SC_LS__O22A_TB_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o22a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_ls__o22a dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22A_TB_V
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate unary nand ~&(value)
//
module main;
reg [3:0] vect;
reg error;
wire result;
assign result = ~&(vect);
initial
begin
error = 0;
for(vect=4'b000;vect<4'b1111;vect = vect + 1)
begin
#1;
if(result !== 1'b1)
begin
$display("FAILED - Unary nand ~&(%b)=%b",vect,result);
error = 1'b1;
end
end
#1;
vect = 4'b1111;
#1;
if(result !== 1'b0)
begin
$display("FAILED - Unary nand ~&(%b)=%b",vect,result);
error = 1'b1;
end
if(error === 0 )
$display("PASSED");
end
endmodule // main
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
interface counter_if;
logic [3:0] value;
logic reset;
modport counter_mp (input reset, output value);
modport core_mp (output reset, input value);
endinterface
// Check can have inst module before top module
module counter_ansi
(
input clkm,
counter_if c_data,
input logic [3:0] i_value
);
always @ (posedge clkm) begin
c_data.value <= c_data.reset ? i_value : c_data.value + 1;
end
endmodule : counter_ansi
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=1;
counter_if c1_data();
counter_if c2_data();
counter_if c3_data();
counter_if c4_data();
counter_ansi c1 (.clkm(clk),
.c_data(c1_data.counter_mp),
.i_value(4'h1));
`ifdef VERILATOR counter_ansi `else counter_nansi `endif
/**/ c2 (.clkm(clk),
.c_data(c2_data.counter_mp),
.i_value(4'h2));
counter_ansi_m c3 (.clkm(clk),
.c_data(c3_data),
.i_value(4'h3));
`ifdef VERILATOR counter_ansi_m `else counter_nansi_m `endif
/**/ c4 (.clkm(clk),
.c_data(c4_data),
.i_value(4'h4));
initial begin
c1_data.value = 4'h4;
c2_data.value = 4'h5;
c3_data.value = 4'h6;
c4_data.value = 4'h7;
end
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc<2) begin
c1_data.reset <= 1;
c2_data.reset <= 1;
c3_data.reset <= 1;
c4_data.reset <= 1;
end
if (cyc==2) begin
c1_data.reset <= 0;
c2_data.reset <= 0;
c3_data.reset <= 0;
c4_data.reset <= 0;
end
if (cyc==20) begin
$write("[%0t] cyc%0d: c1 %0x %0x c2 %0x %0x c3 %0x %0x c4 %0x %0x\n", $time, cyc,
c1_data.value, c1_data.reset,
c2_data.value, c2_data.reset,
c3_data.value, c3_data.reset,
c4_data.value, c4_data.reset);
if (c1_data.value != 2) $stop;
if (c2_data.value != 3) $stop;
if (c3_data.value != 4) $stop;
if (c4_data.value != 5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
`ifndef VERILATOR
// non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too.
module counter_nansi
(clkm, c_data, i_value);
input clkm;
counter_if c_data;
input logic [3:0] i_value;
always @ (posedge clkm) begin
c_data.value <= c_data.reset ? i_value : c_data.value + 1;
end
endmodule : counter_nansi
`endif
module counter_ansi_m
(
input clkm,
counter_if.counter_mp c_data,
input logic [3:0] i_value
);
always @ (posedge clkm) begin
c_data.value <= c_data.reset ? i_value : c_data.value + 1;
end
endmodule : counter_ansi_m
`ifndef VERILATOR
// non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too.
module counter_nansi_m
(clkm, c_data, i_value);
input clkm;
counter_if.counter_mp c_data;
input logic [3:0] i_value;
always @ (posedge clkm) begin
c_data.value <= c_data.reset ? i_value : c_data.value + 1;
end
endmodule : counter_nansi_m
`endif
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_register(clock, resetn, i_counter_reset, i_settings, i_datain, i_datain_valid, o_datain_stall, o_dataout, o_dataout_valid, i_dataout_stall);
parameter DATA_WIDTH = 32;
input clock, resetn, i_counter_reset;
input [DATA_WIDTH-1:0] i_settings;
input [DATA_WIDTH-1:0] i_datain;
input i_datain_valid;
output o_datain_stall;
output [DATA_WIDTH-1:0] o_dataout;
output o_dataout_valid;
input i_dataout_stall;
vfabric_counter_fifo fifo0 (.clock(clock), .resetn(resetn), .i_counter_reset(i_counter_reset),
.i_datain_valid(i_datain_valid), .o_datain_stall(o_datain_stall),
.o_dataout_valid(o_dataout_valid), .i_dataout_stall(i_dataout_stall));
assign o_dataout = i_settings;
endmodule
|
// /**
// * This Verilog HDL file is used for simulation and synthesis in
// * the chaining DMA design example. It manage the interface between the
// * chaining DMA and the Avalon Streaming ports
// */
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// synthesis verilog_input_version verilog_2001
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//-----------------------------------------------------------------------------
// Title : PCI Express Reference Design Example Application
// Project : PCI Express MegaCore function
//-----------------------------------------------------------------------------
// File : altpcierd_example_app_chaining.v
// Author : Altera Corporation
//-----------------------------------------------------------------------------
// Copyright (c) 2008 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
// Parameters
//
// AVALON_WDATA : Width of the data port of the on chip Avalon memory
// AVALON_WADDR : Width of the address port of the on chip Avalon memory
// MAX_NUMTAG : Indicates the maximum number of PCIe tags
// BOARD_DEMO : Indicates to the software application which board is being
// used
// 0 - Altera Stratix II GX x1
// 1 - Altera Stratix II GX x4
// 2 - Altera Stratix II GX x8
// 3 - Cyclone II x1
// 4 - Arria GX x1
// 5 - Arria GX x4
// 6 - Custom PHY x1
// 7 - Custom PHY x4
// USE_RCSLAVE : When USE_RCSLAVE is set an additional module (~1000 LE)
// is added to the design to provide instrumentation to the
// PCI Express Chained DMA design such as Performance
// counter, debug register and EP memory Write a Read by
// bypassing the DMA engine.
// TXCRED_WIDTH : Width of the PCIe tx_cred back bus
// TL_SELECTION : Interface type
// 0 : Descriptor data interface (in use with ICM)
// 6 : Avalon-ST interface
// MAX_PAYLOAD_SIZE_BYTE : Indicates the Maxpayload parameter specified in the
// PCIe MegaWizzard
//
module altpcierd_example_app_chaining #(
parameter AVALON_WADDR = 12,
parameter AVALON_WDATA = 128,
parameter MAX_NUMTAG = 64,
parameter MAX_PAYLOAD_SIZE_BYTE = 512,
parameter BOARD_DEMO = 1,
parameter TL_SELECTION = 0,
parameter CLK_250_APP = 0,// When 1 indicate application clock rate is 250MHz instead of 125 MHz
parameter ECRC_FORWARD_CHECK = 0,
parameter ECRC_FORWARD_GENER = 0,
parameter CHECK_RX_BUFFER_CPL = 0,
parameter CHECK_BUS_MASTER_ENA = 0,
parameter AVALON_ST_128 = (TL_SELECTION == 7) ? 1 : 0 ,
parameter INTENDED_DEVICE_FAMILY = "Cyclone IV GX",
parameter RC_64BITS_ADDR = 0, // When 1 RC Capable of 64 bit address --> 4DW header rx_desc/tx_desc address instead of 3DW
parameter USE_CREDIT_CTRL = 0,
parameter USE_MSI = 1, // When 1, tx_arbitration uses tx_cred
parameter USE_DMAWRITE = 1,
parameter USE_DMAREAD = 1,
parameter USE_RCSLAVE = 0, // Deprecated
parameter TXCRED_WIDTH = 22
)(
// Avalon streaming interface Transmit Data
// Desc/Data Interface + Avalon ST Interface
input tx_stream_ready0, //reg
output[74:0] tx_stream_data0_0,
output[74:0] tx_stream_data0_1,
output tx_stream_valid0,
input tx_stream_fifo_empty0,
// Avalon streaming interface Receive Data
// Desc/Data Interface + Avalon ST Interface
input[81:0] rx_stream_data0_0, //reg
input[81:0] rx_stream_data0_1, //reg
input rx_stream_valid0, //reg
output rx_stream_ready0,
output rx_stream_mask0,
// MSI Interrupt
// Desc/Data Interface only
input msi_stream_ready0,
output[7:0] msi_stream_data0,
output msi_stream_valid0,
// MSI Interrupt
// Avalon ST Interface only
output[4:0] aer_msi_num,
output[4:0] pex_msi_num,
output app_msi_req,
input app_msi_ack, //reg
output[2:0] app_msi_tc,
output[4:0] app_msi_num,
// Legacy Interrupt
output app_int_sts,
input app_int_ack,
// Side band static signals
// Desc/Data Interface only
input tx_stream_mask0,
// Side band static signals
// Desc/Data Interface + Avalon ST Interface
input [TXCRED_WIDTH-1:0] tx_stream_cred0,
// Configuration info signals
// Desc/Data Interface + Avalon ST Interface
input[12:0] cfg_busdev, // Bus device number captured by the core
input[31:0] cfg_devcsr, // Configuration dev control status register of
// PCIe capability structure (address 0x88)
input[31:0] cfg_prmcsr, // Control and status of the PCI configuration space (address 0x4)
input[23:0] cfg_tcvcmap,
input[31:0] cfg_linkcsr,
input[15:0] cfg_msicsr,
output cpl_pending,
output[6:0] cpl_err,
output[127:0] err_desc,
input[19:0] ko_cpl_spc_vc0,
// Unused signals
output[9:0] pm_data,
input test_sim,
input clk_in ,
input rstn
);
// Receive section channel 0
wire open_rx_retry0;
wire open_rx_mask0 ;
wire[7:0] open_rx_be0 ;
wire rx_ack0 ;
wire rx_ws0 ;
wire rx_req0 ;
wire[135:0] rx_desc0 ;
wire[127:0] rx_data0 ;
wire[15:0] rx_be0 ;
wire rx_dv0 ;
wire rx_dfr0 ;
wire [15:0] rx_ecrc_bad_cnt;
//transmit section channel 0
wire tx_req0 ;
wire tx_mask0;
wire tx_ack0 ;
wire[127:0] tx_desc0;
wire tx_ws0 ;
wire tx_err0 ;
wire tx_dv0 ;
wire tx_dfr0 ;
wire[127:0] tx_data0;
wire app_msi_req_int;
wire[2:0] app_msi_tc_int ;
wire[4:0] app_msi_num_int;
wire app_msi_ack_int;
reg app_msi_ack_reg;
reg tx_stream_ready0_reg;
reg[81:0] rx_stream_data0_0_reg;
reg[81:0] rx_stream_data0_1_reg;
reg rx_stream_valid0_reg ;
reg[81:0] rx_stream_data0_0_reg2;
reg[81:0] rx_stream_data0_1_reg2;
reg rx_stream_valid0_reg2 ;
reg app_msi_req_synced;
reg[3:0] tx_fifo_empty_timer;
wire tx_local_fifo_empty;
reg app_msi_req_synced_n;
reg[3:0] tx_fifo_empty_timer_n;
reg[3:0] msi_req_state;
reg[3:0] msi_req_state_n;
always @(posedge clk_in) begin
tx_stream_ready0_reg <= tx_stream_ready0 ;
rx_stream_data0_0_reg2 <= rx_stream_data0_0;
rx_stream_data0_1_reg2 <= rx_stream_data0_1;
rx_stream_valid0_reg2 <= rx_stream_valid0 ;
end
always @(posedge clk_in) begin
rx_stream_data0_0_reg <= rx_stream_data0_0_reg2;
rx_stream_data0_1_reg <= rx_stream_data0_1_reg2;
rx_stream_valid0_reg <= rx_stream_valid0_reg2 ;
end
//------------------------------------------------------------
// MSI Streaming Interface
// - generates streaming interface signals
//------------------------------------------------------------
wire app_msi_ack_dd;
reg srst;
always @(posedge clk_in or negedge rstn) begin
if (rstn==0)
srst <= 1'b1;
else
srst <=1'b0;
end
//------------------------------------------------------------
// RX buffer cpld credit tracking
//------------------------------------------------------------
wire cpld_rx_buffer_ready;
wire [15:0] rx_buffer_cpl_max_dw;
altpcierd_cpld_rx_buffer #(
.CHECK_RX_BUFFER_CPL(CHECK_RX_BUFFER_CPL),
.MAX_NUMTAG(MAX_NUMTAG)
)
altpcierd_cpld_rx_buffer_i (
.clk_in (clk_in),
.srst (srst),
.rx_req0 (rx_req0),
.rx_ack0 (rx_ack0),
.rx_desc0 (rx_desc0),
.tx_req0 (tx_req0),
.tx_ack0 (tx_ack0),
.tx_desc0 (tx_desc0),
.ko_cpl_spc_vc0 (ko_cpl_spc_vc0),
.rx_buffer_cpl_max_dw(rx_buffer_cpl_max_dw),
.cpld_rx_buffer_ready(cpld_rx_buffer_ready)
);
altpcierd_cdma_ast_msi altpcierd_cdma_ast_msi_i (
.clk_in(clk_in),
.rstn(rstn), //TODO Use srst
.app_msi_req(app_msi_req_int),
.app_msi_ack(app_msi_ack_dd),
.app_msi_tc(app_msi_tc_int),
.app_msi_num(app_msi_num_int),
.stream_ready(msi_stream_ready0),
.stream_data(msi_stream_data0),
.stream_valid(msi_stream_valid0));
generate begin : HIPCAP_64
if ((AVALON_ST_128==0) & (TL_SELECTION == 6)) begin
//------------------------------------------------------------
// TX Streaming Interface
// - generates streaming interface signals
// - arbitrates between master and slave requests
//------------------------------------------------------------
wire [132:0] txdata;
assign tx_stream_data0_0[74] = txdata[132];//err
assign tx_stream_data0_0[73] = txdata[131];//sop
assign tx_stream_data0_0[72] = txdata[128];//eop
assign tx_stream_data0_0[71:64] = 0;
assign tx_stream_data0_1[74] = txdata[132];
assign tx_stream_data0_1[73] = txdata[131];
assign tx_stream_data0_1[72] = txdata[128];
assign tx_stream_data0_1[71:64] = 0;
assign tx_stream_data0_0[63:0] = {txdata[95:64], txdata[127:96]};
assign tx_stream_data0_1[63:0] = {txdata[95:64], txdata[127:96]};
wire otx_req0 ;
wire [127:0] otx_desc0;
wire otx_err0 ;
wire otx_dv0 ;
wire otx_dfr0 ;
wire [127:0] otx_data0;
altpcierd_tx_req_reg #(
.TX_PIPE_REQ(0)
) altpcierd_tx_req128_reg (
.clk_in (clk_in ),
.rstn (rstn ),
.itx_req0 (tx_req0 ),
.itx_desc0(tx_desc0 ),
.itx_err0 (tx_err0 ),
.itx_dv0 (tx_dv0 ),
.itx_dfr0 (tx_dfr0 ),
.itx_data0(tx_data0 ),
.otx_req0 (otx_req0 ),
.otx_desc0(otx_desc0),
.otx_err0 (otx_err0 ),
.otx_dv0 (otx_dv0 ),
.otx_dfr0 (otx_dfr0 ),
.otx_data0(otx_data0)
);
altpcierd_cdma_ast_tx_64
#( .TX_PIPE_REQ(0),
.INTENDED_DEVICE_FAMILY (INTENDED_DEVICE_FAMILY),
.ECRC_FORWARD_GENER(ECRC_FORWARD_GENER)
)
altpcierd_cdma_ast_tx_i_64 (
.clk_in(clk_in),
.srst(srst),
// Avalon-ST
.txdata(txdata),
.tx_stream_ready0(tx_stream_ready0_reg),
.tx_stream_valid0(tx_stream_valid0),
// Application iterface
.tx_req0 (otx_req0),
.tx_ack0 (tx_ack0),
.tx_desc0 (otx_desc0),
.tx_data0 (otx_data0),
.tx_dfr0 (otx_dfr0),
.tx_dv0 (otx_dv0),
.tx_err0 (otx_err0),
.tx_ws0 (tx_ws0),
.tx_fifo_empty (tx_local_fifo_empty));
//------------------------------------------------------------
// RX Streaming Interface
// - generates streaming interface signals
// - routes data to master/slave
//------------------------------------------------------------
wire [139:0] rxdata;
wire [15:0] rxdata_be; // rx byte enables
assign rxdata_be = {rx_stream_data0_0_reg[77:74], rx_stream_data0_0_reg[81:78],
rx_stream_data0_1_reg[77:74], rx_stream_data0_1_reg[81:78]};
assign rxdata = {
rx_stream_data0_0_reg[73], //rx_sop0 [139]
rx_stream_data0_0_reg[72], //rx_eop0 [138]
rx_stream_data0_1_reg[73], //rx_eop1 [137]
rx_stream_data0_1_reg[72], //rx_eop1 [136]
rx_stream_data0_0_reg[71:64], //bar [135:128] | Aligned | Un-aligned 3 DW | UN-aligned 4 DW
rx_stream_data0_0_reg[31:0], // rx_desc[127:96] aka H0 | D0 | - -> D1 | -> D3
rx_stream_data0_0_reg[63:32], // rx_desc[95:64 ] aka H1 | D1 | - -> D2 | D0 -> D4
rx_stream_data0_1_reg[31:0], // rx_desc[63:32 ] aka H2 | D2 | - -> D3 | D1 -> D5
rx_stream_data0_1_reg[63:32]}; // rx_desc[31:0 ] aka H4 | D3 | D0 -> D4 | D2 -> D6
altpcierd_cdma_ast_rx_64
#( .INTENDED_DEVICE_FAMILY (INTENDED_DEVICE_FAMILY),
.ECRC_FORWARD_CHECK(ECRC_FORWARD_CHECK))
altpcierd_cdma_ast_rx_i_64 (
.clk_in(clk_in),
.srst(srst),
.rx_stream_ready0(rx_stream_ready0),
.rx_stream_valid0(rx_stream_valid0_reg),
.rxdata (rxdata),
.rxdata_be (rxdata_be),
.rx_req0 (rx_req0),
.rx_ack0 (rx_ack0),
.rx_data0 (rx_data0),
.rx_be0 (rx_be0),
.rx_desc0 (rx_desc0),
.rx_dfr0 (rx_dfr0),
.rx_dv0 (rx_dv0),
.rx_ws0 (rx_ws0),
.ecrc_bad_cnt(rx_ecrc_bad_cnt));
end
end
endgenerate
generate begin : ICM
if (TL_SELECTION == 0) begin
//------------------------------------------------------------
// TX Streaming Interface
// - generates streaming interface signals
// - arbitrates between master and slave requests
//------------------------------------------------------------
// rx_req is generated one clk cycle ahead of
// other control signals.
// re-align here.
altpcierd_cdma_ast_tx #(.TL_SELECTION(TL_SELECTION))
altpcierd_cdma_ast_tx_i (
.clk_in(clk_in), //TODO Use srst
.rstn(rstn),
.tx_stream_data0(tx_stream_data0_0),
.tx_stream_ready0(tx_stream_ready0),
.tx_stream_valid0(tx_stream_valid0),
.tx_req0 (tx_req0),
.tx_ack0 (tx_ack0),
.tx_desc0 (tx_desc0),
.tx_data0 (tx_data0[63:0]),
.tx_dfr0 (tx_dfr0),
.tx_dv0 (tx_dv0),
.tx_err0 (tx_err0),
.tx_ws0 (tx_ws0));
//------------------------------------------------------------
// RX Streaming Interface
// - generates streaming interface signals
// - routes data to master/slave
//------------------------------------------------------------
altpcierd_cdma_ast_rx #(.TL_SELECTION(TL_SELECTION))
altpcierd_cdma_ast_rx_i (
.clk_in(clk_in),
.rstn(rstn), //TODO Use srst
.rx_stream_ready0(rx_stream_ready0),
.rx_stream_valid0(rx_stream_valid0),
.rx_stream_data0(rx_stream_data0_0),
.rx_req0 (rx_req0),
.rx_ack0 (rx_ack0),
.rx_data0 (rx_data0[63:0]),
.rx_desc0 (rx_desc0),
.rx_dfr0 (rx_dfr0),
.rx_dv0 (rx_dv0),
.rx_ws0 (rx_ws0),
.rx_be0 (rx_be0),
.ecrc_bad_cnt(rx_ecrc_bad_cnt));
assign rx_data0[127:64] = 0;
end
end
endgenerate
generate begin : HIPCAB_128
if (AVALON_ST_128==1) begin
//------------------------------------------------------------
// TX Streaming Interface
// - generates streaming interface signals
// - arbitrates between master and slave requests
//------------------------------------------------------------
// rx_req is generated one clk cycle ahead of
// other control signals.
// re-align here.
wire [132:0] txdata;
wire otx_req0 ;
wire [127:0] otx_desc0;
wire otx_err0 ;
wire otx_dv0 ;
wire otx_dfr0 ;
wire [127:0] otx_data0;
assign tx_stream_data0_0[74] = txdata[132];//err
assign tx_stream_data0_0[73] = txdata[131];//sop
assign tx_stream_data0_0[72] = txdata[130];//eop
assign tx_stream_data0_0[71:64] = 0;
assign tx_stream_data0_1[74] = txdata[132];//err
assign tx_stream_data0_1[73] = txdata[129];//sop
assign tx_stream_data0_1[72] = txdata[128];//eop
assign tx_stream_data0_1[71:64] = 0;
assign tx_stream_data0_0[63:0] = {txdata[95:64], txdata[127:96]};
assign tx_stream_data0_1[63:0] = {txdata[31:0] , txdata[63:32]};
altpcierd_tx_req_reg #(
.TX_PIPE_REQ(CLK_250_APP)
) altpcierd_tx_req128_reg (
.clk_in (clk_in ),
.rstn (rstn ),
.itx_req0 (tx_req0 ),
.itx_desc0(tx_desc0 ),
.itx_err0 (tx_err0 ),
.itx_dv0 (tx_dv0 ),
.itx_dfr0 (tx_dfr0 ),
.itx_data0(tx_data0 ),
.otx_req0 (otx_req0 ),
.otx_desc0(otx_desc0),
.otx_err0 (otx_err0 ),
.otx_dv0 (otx_dv0 ),
.otx_dfr0 (otx_dfr0 ),
.otx_data0(otx_data0)
);
altpcierd_cdma_ast_tx_128
#( .TX_PIPE_REQ(CLK_250_APP),
.ECRC_FORWARD_GENER(ECRC_FORWARD_GENER))
altpcierd_cdma_ast_tx_i_128 (
.clk_in(clk_in),
.rstn(rstn),
// Avalon-ST
.txdata(txdata),
.tx_stream_ready0(tx_stream_ready0_reg),
.tx_stream_valid0(tx_stream_valid0),
// Application iterface
.tx_req0 (otx_req0),
.tx_ack0 (tx_ack0),
.tx_desc0 (otx_desc0),
.tx_data0 (otx_data0),
.tx_dfr0 (otx_dfr0),
.tx_dv0 (otx_dv0),
.tx_err0 (otx_err0),
.tx_ws0 (tx_ws0),
.tx_fifo_empty (tx_local_fifo_empty));
//------------------------------------------------------------
// RX Streaming Interface
// - generates streaming interface signals
// - routes data to master/slave
//------------------------------------------------------------
wire [139:0] rxdata;
wire [15:0] rxdata_be; // rx byte enables
assign rxdata_be = {rx_stream_data0_0_reg[77:74], rx_stream_data0_0_reg[81:78],
rx_stream_data0_1_reg[77:74], rx_stream_data0_1_reg[81:78]}; // swapped to keep consistent with DW swapping on data field
assign rxdata = {
rx_stream_data0_0_reg[73], //rx_sop0 [139]
rx_stream_data0_0_reg[72], //rx_eop0 [138]
rx_stream_data0_1_reg[73], //rx_eop1 [137]
rx_stream_data0_1_reg[72], //rx_eop1 [136]
rx_stream_data0_0_reg[71:64], //bar [135:128] | Aligned | Un-aligned 3 DW | UN-aligned 4 DW
rx_stream_data0_0_reg[31:0], // rx_desc[127:96] aka H0 | D0 | - -> D1 | -> D3
rx_stream_data0_0_reg[63:32], // rx_desc[95:64 ] aka H1 | D1 | - -> D2 | D0 -> D4
rx_stream_data0_1_reg[31:0], // rx_desc[63:32 ] aka H2 | D2 | - -> D3 | D1 -> D5
rx_stream_data0_1_reg[63:32]}; // rx_desc[31:0 ] aka H4 | D3 | D0 -> D4 | D2 -> D6
altpcierd_cdma_ast_rx_128
#(.ECRC_FORWARD_CHECK(ECRC_FORWARD_CHECK))
altpcierd_cdma_ast_rx_i_128 (
.clk_in(clk_in),
.rstn(rstn),
.rx_stream_ready0(rx_stream_ready0),
.rx_stream_valid0(rx_stream_valid0_reg),
.rxdata(rxdata),
.rxdata_be(rxdata_be),
.rx_req0 (rx_req0),
.rx_ack0 (rx_ack0),
.rx_data0 (rx_data0),
.rx_be0 (rx_be0),
.rx_desc0 (rx_desc0),
.rx_dfr0 (rx_dfr0),
.rx_dv0 (rx_dv0),
.rx_ws0 (rx_ws0),
.ecrc_bad_cnt(rx_ecrc_bad_cnt));
end
end
endgenerate
//------------------------------------------------------------
// Chaining DMA application interface
//------------------------------------------------------------
// This parameter is specific to the implementation of the
// Avalon streaming interface in the Chaining DMA design example.
// It specifies the cdma_ast_rx's response time to an rx_ws assertion.
// i.e. rx_data responds "CDMA_AST_RXWS_LATENCY" clock cycles after rx_ws asserts.
localparam CDMA_AST_RXWS_LATENCY = (TL_SELECTION==0) ? 4 : 2;
assign aer_msi_num = 0;
assign pm_data = 0;
assign pex_msi_num = 0;
assign app_msi_ack_int = (USE_MSI==0)?0:(TL_SELECTION==0)?app_msi_ack_dd:app_msi_ack_reg;
assign app_msi_req = (USE_MSI==0)?0:(TL_SELECTION==0)?0:app_msi_req_synced;
assign app_msi_tc = (USE_MSI==0)?0:(TL_SELECTION==0)?0:app_msi_tc_int;
assign app_msi_num = (USE_MSI==0)?0:(TL_SELECTION==0)?0:app_msi_num_int;
assign tx_mask0 = (TL_SELECTION==0)?tx_stream_mask0:1'b0;
// states for msi_req_state
parameter MSI_MON_IDLE = 4'h0;
parameter MSI_WAIT_LOCAL_EMPTY = 4'h1;
parameter MSI_WAIT_LATENCY = 4'h2;
parameter MSI_WAIT_CORE_EMPTY = 4'h3;
parameter MSI_WAIT_CORE_ACK = 4'h4;
// this state machine synchronizes the app_msi_req
// generation to the tx streaming datapath so that
// it is issued only after the previously issued tx
// data has been transferred to the core
always @(posedge clk_in) begin
if (srst==1'b1) begin
app_msi_req_synced <= 1'b0;
tx_fifo_empty_timer <= 4'h0;
msi_req_state <= MSI_MON_IDLE;
app_msi_ack_reg <= 1'b0;
end
else begin
app_msi_req_synced <= app_msi_req_synced_n;
tx_fifo_empty_timer <= tx_fifo_empty_timer_n;
msi_req_state <= (USE_MSI==0)?MSI_MON_IDLE:msi_req_state_n;
app_msi_ack_reg <= app_msi_ack;
end
end
always @(*) begin
// defaults
app_msi_req_synced_n = app_msi_req_synced;
tx_fifo_empty_timer_n = tx_fifo_empty_timer;
msi_req_state_n = msi_req_state;
case (msi_req_state)
MSI_MON_IDLE: begin
app_msi_req_synced_n = 1'b0;
if (USE_MSI==0)
msi_req_state_n = MSI_MON_IDLE;
else if (app_msi_req_int==1'b1)
msi_req_state_n = MSI_WAIT_LOCAL_EMPTY;
else
msi_req_state_n = msi_req_state;
end
MSI_WAIT_LOCAL_EMPTY: begin
tx_fifo_empty_timer_n = 4'h0;
if (tx_local_fifo_empty==1'b1)
msi_req_state_n = MSI_WAIT_LATENCY;
else
msi_req_state_n = msi_req_state;
end
MSI_WAIT_LATENCY: begin
tx_fifo_empty_timer_n = tx_fifo_empty_timer + 1;
if (tx_fifo_empty_timer[3]==1'b1)
msi_req_state_n = MSI_WAIT_CORE_EMPTY;
else
msi_req_state_n = msi_req_state;
end
MSI_WAIT_CORE_EMPTY: begin
if (tx_stream_fifo_empty0==1'b1) begin
app_msi_req_synced_n = 1'b1;
msi_req_state_n = MSI_WAIT_CORE_ACK;
end
else begin
app_msi_req_synced_n = app_msi_req_synced;
msi_req_state_n = msi_req_state;
end
end
MSI_WAIT_CORE_ACK: begin
if (app_msi_ack_reg==1'b1) begin
msi_req_state_n = MSI_MON_IDLE;
app_msi_req_synced_n = 1'b0;
end
else begin
msi_req_state_n = msi_req_state;
app_msi_req_synced_n = app_msi_req_synced;
end
end
default: begin
app_msi_req_synced_n = app_msi_req_synced;
msi_req_state_n = msi_req_state;
tx_fifo_empty_timer_n = tx_fifo_empty_timer;
end
endcase
end
altpcierd_cdma_app_icm #(
.AVALON_WADDR (AVALON_WADDR),
.AVALON_WDATA (AVALON_WDATA),
.MAX_NUMTAG (MAX_NUMTAG),
.MAX_PAYLOAD_SIZE_BYTE (MAX_PAYLOAD_SIZE_BYTE),
.BOARD_DEMO (BOARD_DEMO),
.USE_CREDIT_CTRL (USE_CREDIT_CTRL),
.USE_DMAWRITE (USE_DMAWRITE),
.USE_DMAREAD (USE_DMAREAD ),
.USE_MSI (USE_MSI),
.CHECK_BUS_MASTER_ENA (CHECK_BUS_MASTER_ENA),
.RC_64BITS_ADDR (RC_64BITS_ADDR),
.CLK_250_APP (CLK_250_APP),
.TL_SELECTION (TL_SELECTION),
.INTENDED_DEVICE_FAMILY (INTENDED_DEVICE_FAMILY),
.AVALON_ST_128 (AVALON_ST_128),
.TXCRED_WIDTH (TXCRED_WIDTH),
.CDMA_AST_RXWS_LATENCY (CDMA_AST_RXWS_LATENCY)
) chaining_dma_arb (
.app_msi_ack (app_msi_ack_int),
.app_msi_req (app_msi_req_int),
.app_msi_num (app_msi_num_int),
.app_msi_tc (app_msi_tc_int),
.app_int_sts (app_int_sts),
.app_int_ack (app_int_ack),
.cfg_busdev (cfg_busdev),
.cfg_prmcsr (cfg_prmcsr),
.cfg_devcsr (cfg_devcsr),
.cfg_linkcsr (cfg_linkcsr),
.cfg_tcvcmap (cfg_tcvcmap),
.cfg_msicsr (cfg_msicsr),
.cpl_err (cpl_err),
.err_desc (err_desc),
.cpl_pending (cpl_pending),
.ko_cpl_spc_vc0 (ko_cpl_spc_vc0),
.tx_mask0 (tx_mask0),
.cpld_rx_buffer_ready (cpld_rx_buffer_ready),
.tx_cred0 (tx_stream_cred0),
.tx_stream_ready0 (tx_stream_ready0),
.clk_in (clk_in),
.rstn (rstn), //TODO Use srst
.rx_req0 (rx_req0),
.rx_ack0 (rx_ack0),
.rx_data0 (rx_data0),
.rx_be0 (rx_be0),
.rx_desc0 (rx_desc0),
.rx_dfr0 (rx_dfr0),
.rx_dv0 (rx_dv0),
.rx_ws0 (rx_ws0),
.rx_mask0 (rx_stream_mask0),
.rx_ecrc_bad_cnt(rx_ecrc_bad_cnt),
.rx_buffer_cpl_max_dw(rx_buffer_cpl_max_dw),
.tx_req0 (tx_req0),
.tx_ack0 (tx_ack0),
.tx_desc0 (tx_desc0),
.tx_data0 (tx_data0),
.tx_dfr0 (tx_dfr0),
.tx_dv0 (tx_dv0),
.tx_err0 (tx_err0),
.tx_ws0 (tx_ws0));
endmodule
module altpcierd_tx_req_reg #(
parameter TX_PIPE_REQ=0
)(
input clk_in,
input rstn,
//transmit section channel 0
input itx_req0 ,
input [127:0] itx_desc0,
input itx_err0 ,
input itx_dv0 ,
input itx_dfr0 ,
input[127:0] itx_data0,
output otx_req0 ,
output [127:0] otx_desc0,
output otx_err0 ,
output otx_dv0 ,
output otx_dfr0 ,
output [127:0] otx_data0
);
generate begin
if (TX_PIPE_REQ==0) begin : g_comb
assign otx_req0 = itx_req0 ;
assign otx_desc0 = itx_desc0;
assign otx_err0 = itx_err0 ;
assign otx_dv0 = itx_dv0 ;
assign otx_dfr0 = itx_dfr0 ;
assign otx_data0 = itx_data0;
end
end
endgenerate
generate begin
if (TX_PIPE_REQ>0) begin : g_pipe
reg rtx_req0 ;
reg [127:0] rtx_desc0;
reg rtx_err0 ;
reg rtx_dv0 ;
reg rtx_dfr0 ;
reg [127:0] rtx_data0;
assign otx_req0 = rtx_req0 ;
assign otx_desc0 = rtx_desc0;
assign otx_err0 = rtx_err0 ;
assign otx_dv0 = rtx_dv0 ;
assign otx_dfr0 = rtx_dfr0 ;
assign otx_data0 = rtx_data0;
always @ (negedge rstn or posedge clk_in) begin
if (rstn==1'b0) begin
rtx_req0 <= 0;
rtx_desc0 <= 0;
rtx_err0 <= 0;
rtx_dv0 <= 0;
rtx_dfr0 <= 0;
rtx_data0 <= 0;
end
else begin
rtx_req0 <= itx_req0 ;
rtx_desc0 <= itx_desc0;
rtx_err0 <= itx_err0 ;
rtx_dv0 <= itx_dv0 ;
rtx_dfr0 <= itx_dfr0 ;
rtx_data0 <= itx_data0;
end
end
end
end
endgenerate
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <[email protected]>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_dest_fifo_inf (
input clk,
input resetn,
input enable,
output enabled,
input sync_id,
output sync_id_ret,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
output [C_ID_WIDTH-1:0] data_id,
input data_eot,
input response_eot,
input en,
output [C_DATA_WIDTH-1:0] dout,
output valid,
output underflow,
output xfer_req,
output fifo_ready,
input fifo_valid,
input [C_DATA_WIDTH-1:0] fifo_data,
input req_valid,
output req_ready,
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
output response_valid,
input response_ready,
output response_resp_eot,
output [1:0] response_resp
);
parameter C_ID_WIDTH = 3;
parameter C_DATA_WIDTH = 64;
parameter C_BEATS_PER_BURST_WIDTH = 4;
assign sync_id_ret = sync_id;
wire data_enabled;
wire _fifo_ready;
assign fifo_ready = _fifo_ready | ~enabled;
reg en_d1;
wire data_ready;
wire data_valid;
always @(posedge clk)
begin
if (resetn == 1'b0) begin
en_d1 <= 1'b0;
end else begin
en_d1 <= en;
end
end
assign underflow = en_d1 & (~data_valid | ~enable);
assign data_ready = en_d1 & (data_valid | ~enable);
assign valid = en_d1 & data_valid & enable;
dmac_data_mover # (
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH),
.C_DISABLE_WAIT_FOR_ID(0)
) i_data_mover (
.clk(clk),
.resetn(resetn),
.enable(enable),
.enabled(data_enabled),
.sync_id(sync_id),
.xfer_req(xfer_req),
.request_id(request_id),
.response_id(data_id),
.eot(data_eot),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.s_axi_ready(_fifo_ready),
.s_axi_valid(fifo_valid),
.s_axi_data(fifo_data),
.m_axi_ready(data_ready),
.m_axi_valid(data_valid),
.m_axi_data(dout),
.m_axi_last()
);
dmac_response_generator # (
.C_ID_WIDTH(C_ID_WIDTH)
) i_response_generator (
.clk(clk),
.resetn(resetn),
.enable(data_enabled),
.enabled(enabled),
.sync_id(sync_id),
.request_id(data_id),
.response_id(response_id),
.eot(response_eot),
.resp_valid(response_valid),
.resp_ready(response_ready),
.resp_eot(response_resp_eot),
.resp_resp(response_resp)
);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : bram_common.v
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
module bram_common #
(
parameter NUM_BRAMS = 16,
parameter ADDR_WIDTH = 13,
parameter READ_LATENCY = 3,
parameter WRITE_LATENCY = 1,
parameter WRITE_PIPE = 0,
parameter READ_ADDR_PIPE = 0,
parameter READ_DATA_PIPE = 0,
parameter BRAM_OREG = 1 //parameter to enable use of output register on BRAM
)
(
input clka, // Port A Clk,
input ena, // Port A enable
input wena, // read/write enable
input [63:0] dina, // Port A Write data
output [63:0] douta,// Port A Write data
input [ADDR_WIDTH - 1:0] addra,// Write Address for TL RX Buffers,
input clkb, // Port B Clk,
input enb, // Port B enable
input wenb, // read/write enable
input [63:0] dinb, // Port B Write data
output [63:0] doutb,// Port B Write data
input [ADDR_WIDTH - 1:0] addrb // Write Address for TL RX Buffers,
);
// width of the BRAM: used bits
localparam BRAM_WIDTH = 64/NUM_BRAMS;
// unused bits of the databus
localparam UNUSED_DATA = 32 - BRAM_WIDTH;
parameter UNUSED_ADDR = (BRAM_WIDTH == 64) ? 6: (BRAM_WIDTH == 32)
? 5: (BRAM_WIDTH == 16)
? 4: (BRAM_WIDTH == 8)
? 3: (BRAM_WIDTH == 4)
? 2: (BRAM_WIDTH == 2)
? 1:0;
parameter BRAM_WIDTH_PARITY = (BRAM_WIDTH == 32) ? 36: (BRAM_WIDTH == 16)? 18: (BRAM_WIDTH == 8)? 9: BRAM_WIDTH;
//used address bits. This will be used to determine the slice of the
//address bits from the upper level
localparam USED_ADDR = 15 - UNUSED_ADDR;
wire [31:0]ex_dat_a = 32'b0;
wire [31:0]ex_dat_b = 32'b0;
generate
genvar i;
if (NUM_BRAMS == 1)
begin: generate_sdp
// single BRAM implies Simple Dual Port and width of 64
RAMB36SDP
#(
.DO_REG (BRAM_OREG)
)
ram_sdp_inst
(
.DI (dina),
.WRADDR (addra[8:0]),
.WE ({8{wena}}),
.WREN (ena),
.WRCLK (clka),
.DO (doutb),
.RDADDR (addrb[8:0]),
.RDEN (enb),
.REGCE (1'b1),
.SSR (1'b0),
.RDCLK (clkb),
.DIP (8'h00),
.DBITERR(),
.SBITERR(),
.DOP(),
.ECCPARITY()
);
end
else if (NUM_BRAMS ==2)
for (i=0; i < NUM_BRAMS; i = i+1)
begin:generate_tdp2
RAMB36
#(
.READ_WIDTH_A (BRAM_WIDTH_PARITY),
.WRITE_WIDTH_A (BRAM_WIDTH_PARITY),
.READ_WIDTH_B (BRAM_WIDTH_PARITY),
.WRITE_WIDTH_B (BRAM_WIDTH_PARITY),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.DOB_REG (BRAM_OREG)
)
ram_tdp2_inst
(
.DOA (douta[(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH]),
.DIA (dina[(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH]),
.ADDRA ({ 1'b0, addra[USED_ADDR - 1:0], {UNUSED_ADDR{1'b0}} }),
.WEA ({4{wena}}),
.ENA (ena),
.CLKA (clka),
.DOB (doutb[(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH]),
.DIB (dinb [(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH]),
.ADDRB ({ 1'b0, addrb[USED_ADDR - 1:0], {UNUSED_ADDR{1'b0}} }),
.WEB (4'b0),
.ENB (enb),
.REGCEB (1'b1),
.REGCEA (1'b1),
// .REGCLKB (clkb),
.SSRA (1'b0),
.SSRB (1'b0),
.CLKB (clkb)
);
end
else
for (i=0; i < NUM_BRAMS; i = i+1)
begin:generate_tdp
RAMB36
#(
.READ_WIDTH_A (BRAM_WIDTH_PARITY),
.WRITE_WIDTH_A (BRAM_WIDTH_PARITY),
.READ_WIDTH_B (BRAM_WIDTH_PARITY),
.WRITE_WIDTH_B (BRAM_WIDTH_PARITY),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.DOB_REG (BRAM_OREG)
)
ram_tdp_inst
(
.DOA ({ ex_dat_a[UNUSED_DATA-1:0], douta[(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH] }),
.DIA ({ {UNUSED_DATA{1'b0}} ,dina[(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH] }),
.ADDRA ({ 1'b0, addra[USED_ADDR - 1:0], {UNUSED_ADDR{1'b0}} }),
.WEA ({4{wena}}),
.ENA (ena),
.CLKA (clka),
.DOB ({ ex_dat_b[UNUSED_DATA-1:0], doutb[(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH] }),
.DIB ({ {UNUSED_DATA{1'b0}}, dinb [(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH] }),
.ADDRB ({ 1'b0, addrb[USED_ADDR - 1:0], {UNUSED_ADDR{1'b0}} }),
.WEB (4'b0),
.ENB (enb),
.REGCEB (1'b1),
.REGCEA (1'b1),
// .REGCLKB (clkb),
.SSRA (1'b0),
.SSRB (1'b0),
.CLKB (clkb)
);
end
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized OR with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_carry_latch_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN | I;
end else begin : USE_FPGA
OR2L or2l_inst1
(
.O(O),
.DI(CIN),
.SRI(I)
);
end
endgenerate
endmodule
|
//Copyright 2011 Andreas Lindh
//This file is part of genMem.
//genMem is free software: you can redistribute it and/or modify
//it under the terms of the GNU Lesser General Public License as published by
//the Free Software Foundation, either version 3 of the License, or
//(at your option) any later version.
//
//genMem is distributed in the hope that it will be useful,
//but WITHOUT ANY WARRANTY; without even the implied warranty of
//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//GNU Lesser General Public License for more details.
//
//You should have received a copy of the GNU Lesser General Public License
//along with genMem. If not, see <http://www.gnu.org/licenses/>.
`timescale 1 ns/1 ps
module twoPortMem (
writeAddress,
writeClk,
writeEnable,
writeData,
readAddress,
readClk,
readEnable,
readData);
//user defined
parameter addresses = 32;
parameter width = 8;
parameter muxFactor = 0;
parameter writeMask = 1;
//Auto-calculated, user dont touch
localparam addressWidth =$clog2(addresses);
input [addressWidth-1:0] writeAddress;
input writeClk;
input [writeMask-1:0] writeEnable;
input [width-1:0] writeData;
input [addressWidth-1:0] readAddress;
input readClk;
input readEnable;
output [width-1:0] readData;
generate
if((addresses==0)&&(width==0))
begin
initial
begin
$display("FAIL!! :%m:Parameters, addresses and width can not be set to 0");
$stop;
end
end
`include "scriptGeneratedListOfVendorTwoPortMems.vh"
else
begin
twoPortMemSim #(.addresses (addresses),
.width (width),
.muxFactor (muxFactor),
.writeMask (writeMask)
) mem (.writeAddress(writeAddress),
.writeClk(writeClk),
.writeEnable(writeEnable),
.writeData(writeData),
.readAddress(readAddress),
.readClk(readClk),
.readEnable(readEnable),
.readData(readData));
end
endgenerate
endmodule // twoPortMem
module twoPortMemSim (
writeAddress,
writeClk,
writeEnable,
writeData,
readAddress,
readClk,
readEnable,
readData);
//user defined
parameter addresses = 32;
parameter width = 8;
parameter muxFactor = 0;
parameter writeMask = 1;
//Auto-calculated, user dont touch
localparam addressWidth =$clog2(addresses);
input [addressWidth-1:0] writeAddress;
input writeClk;
input [writeMask-1:0] writeEnable;
input [width-1:0] writeData;
input [addressWidth-1:0] readAddress;
input readClk;
input readEnable;
output [width-1:0] readData;
reg [width-1:0] mem [addresses-1:0];
reg [width-1:0] readData;
integer i;
initial
begin
$display("%m : simulation model of memory");
end
always @(posedge writeClk)
begin
if (writeEnable!=0)
begin
if(writeMask==1)
begin
mem[writeAddress] <= writeData;
end
else
begin
for(i=0; i<writeMask; i=i+1)
if(writeEnable[i]==1)
mem[writeAddress][i] <= writeData[i];
end
end
end
always @(posedge writeClk)
begin
if(readEnable)
begin
readData <= mem[readAddress];
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2014/05/23 15:11:30
// Design Name:
// Module Name: ov7725_capture
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ov7670_capture(
input pclk,
input vsync,
input href,
input[7:0] d,
output[16:0] addr,
output reg[15:0] dout,
output reg we
);
reg [15:0] d_latch;
reg [16:0] address;
reg [16:0] address_next;
reg [1:0] wr_hold;
reg [1:0] cnt;
initial d_latch = 16'b0;
initial address = 19'b0;
initial address_next = 19'b0;
initial wr_hold = 2'b0;
initial cnt = 2'b0;
assign addr = address;
always@(posedge pclk)begin
if( vsync ==1) begin
address <=17'b0;
address_next <= 17'b0;
wr_hold <= 2'b0;
cnt <= 2'b0;
end
else begin
if(address<76800) // Check if at end of frame buffer
address <= address_next;
else
address <= 76800;
// Get 1 byte from camera each cycle. Have to get two bytes to form a pixel.
// wr_hold is used to generate the write enable every other cycle.
// No changes until href = 1 indicating valid data
we <= wr_hold[1]; // Set to 1 one cycle after dout is updated
wr_hold <= {wr_hold[0] , (href &&( ! wr_hold[0])) };
d_latch <= {d_latch[7:0] , d};
if (wr_hold[1] ==1 )begin // increment write address and output new pixel
address_next <=address_next+1;
dout[15:0] <= {d_latch[15:11] , d_latch[10:5] , d_latch[4:0] };
end
end;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rx_port_64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Receives data from the rx_engine and buffers the output
// for the RIFFA channel.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module rx_port_64 #(
parameter C_DATA_WIDTH = 9'd64,
parameter C_MAIN_FIFO_DEPTH = 1024,
parameter C_SG_FIFO_DEPTH = 512,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1),
parameter C_MAIN_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_MAIN_FIFO_DEPTH))+1),
parameter C_SG_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_SG_FIFO_DEPTH))+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input [31:0] SG_RX_BUF_DATA, // Scatter gather RX buffer data
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input [31:0] SG_TX_BUF_DATA, // Scatter gather TX buffer data
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
output [C_DATA_WIDTH-1:0] SG_DATA, // Scatter gather TX buffer data
output SG_DATA_EMPTY, // Scatter gather TX buffer data empty
input SG_DATA_REN, // Scatter gather TX buffer data read enable
input SG_RST, // Scatter gather TX buffer data reset
output SG_ERR, // Scatter gather TX encountered an error
input [31:0] TXN_DATA, // Read transaction data
input TXN_LEN_VALID, // Read transaction length valid
input TXN_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_DONE_LEN, // Read transaction actual transfer length
output TXN_DONE, // Read transaction done
input TXN_DONE_ACK, // Read transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
input [C_DATA_WIDTH-1:0] MAIN_DATA, // Main incoming data
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WIDTH-1:0] SG_RX_DATA, // Scatter gather for RX incoming data
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WIDTH-1:0] SG_TX_DATA, // Scatter gather for TX incoming data
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN // Channel read data has been recieved
);
`include "functions.vh"
wire [C_DATA_WIDTH-1:0] wPackedMainData;
wire wPackedMainWen;
wire wPackedMainDone;
wire wPackedMainErr;
wire wMainFlush;
wire wMainFlushed;
wire [C_DATA_WIDTH-1:0] wPackedSgRxData;
wire wPackedSgRxWen;
wire wPackedSgRxDone;
wire wPackedSgRxErr;
wire wSgRxFlush;
wire wSgRxFlushed;
wire [C_DATA_WIDTH-1:0] wPackedSgTxData;
wire wPackedSgTxWen;
wire wPackedSgTxDone;
wire wPackedSgTxErr;
wire wSgTxFlush;
wire wSgTxFlushed;
wire wMainDataRen;
wire wMainDataEmpty;
wire [C_DATA_WIDTH-1:0] wMainData;
wire wSgRxRst;
wire wSgRxDataRen;
wire wSgRxDataEmpty;
wire [C_DATA_WIDTH-1:0] wSgRxData;
wire [C_SG_FIFO_DEPTH_WIDTH-1:0] wSgRxFifoCount;
wire wSgTxRst;
wire [C_SG_FIFO_DEPTH_WIDTH-1:0] wSgTxFifoCount;
wire wSgRxReq;
wire [63:0] wSgRxReqAddr;
wire [9:0] wSgRxReqLen;
wire wSgTxReq;
wire [63:0] wSgTxReqAddr;
wire [9:0] wSgTxReqLen;
wire wSgRxReqProc;
wire wSgTxReqProc;
wire wMainReqProc;
wire wReqAck;
wire wSgElemRdy;
wire wSgElemRen;
wire [63:0] wSgElemAddr;
wire [31:0] wSgElemLen;
wire wSgRst;
wire wMainReq;
wire [63:0] wMainReqAddr;
wire [9:0] wMainReqLen;
wire wTxnErr;
wire wChnlRx;
wire wChnlRxRecvd;
wire wChnlRxAckRecvd;
wire wChnlRxLast;
wire [31:0] wChnlRxLen;
wire [30:0] wChnlRxOff;
wire [31:0] wChnlRxConsumed;
reg [4:0] rWideRst=0;
reg rRst=0;
assign SG_ERR = (wPackedSgTxDone & wPackedSgTxErr);
// Generate a wide reset from the input reset.
always @ (posedge CLK) begin
rRst <= #1 rWideRst[4];
if (RST)
rWideRst <= #1 5'b11111;
else
rWideRst <= (rWideRst<<1);
end
// Pack received data tightly into our FIFOs
fifo_packer_64 mainFifoPacker (
.CLK(CLK),
.RST(rRst),
.DATA_IN(MAIN_DATA),
.DATA_IN_EN(MAIN_DATA_EN),
.DATA_IN_DONE(MAIN_DONE),
.DATA_IN_ERR(MAIN_ERR),
.DATA_IN_FLUSH(wMainFlush),
.PACKED_DATA(wPackedMainData),
.PACKED_WEN(wPackedMainWen),
.PACKED_DATA_DONE(wPackedMainDone),
.PACKED_DATA_ERR(wPackedMainErr),
.PACKED_DATA_FLUSHED(wMainFlushed)
);
fifo_packer_64 sgRxFifoPacker (
.CLK(CLK),
.RST(rRst),
.DATA_IN(SG_RX_DATA),
.DATA_IN_EN(SG_RX_DATA_EN),
.DATA_IN_DONE(SG_RX_DONE),
.DATA_IN_ERR(SG_RX_ERR),
.DATA_IN_FLUSH(wSgRxFlush),
.PACKED_DATA(wPackedSgRxData),
.PACKED_WEN(wPackedSgRxWen),
.PACKED_DATA_DONE(wPackedSgRxDone),
.PACKED_DATA_ERR(wPackedSgRxErr),
.PACKED_DATA_FLUSHED(wSgRxFlushed)
);
fifo_packer_64 sgTxFifoPacker (
.CLK(CLK),
.RST(rRst),
.DATA_IN(SG_TX_DATA),
.DATA_IN_EN(SG_TX_DATA_EN),
.DATA_IN_DONE(SG_TX_DONE),
.DATA_IN_ERR(SG_TX_ERR),
.DATA_IN_FLUSH(wSgTxFlush),
.PACKED_DATA(wPackedSgTxData),
.PACKED_WEN(wPackedSgTxWen),
.PACKED_DATA_DONE(wPackedSgTxDone),
.PACKED_DATA_ERR(wPackedSgTxErr),
.PACKED_DATA_FLUSHED(wSgTxFlushed)
);
// FIFOs for storing received data for the channel.
(* RAM_STYLE="BLOCK" *)
async_fifo_fwft #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_MAIN_FIFO_DEPTH)) mainFifo (
.WR_CLK(CLK),
.WR_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),
.WR_EN(wPackedMainWen),
.WR_DATA(wPackedMainData),
.WR_FULL(),
.RD_CLK(CHNL_CLK),
.RD_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),
.RD_EN(wMainDataRen),
.RD_DATA(wMainData),
.RD_EMPTY(wMainDataEmpty)
);
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgRxFifo (
.RST(rRst | wSgRxRst),
.CLK(CLK),
.WR_EN(wPackedSgRxWen),
.WR_DATA(wPackedSgRxData),
.FULL(),
.RD_EN(wSgRxDataRen),
.RD_DATA(wSgRxData),
.EMPTY(wSgRxDataEmpty),
.COUNT(wSgRxFifoCount)
);
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgTxFifo (
.RST(rRst | wSgTxRst),
.CLK(CLK),
.WR_EN(wPackedSgTxWen),
.WR_DATA(wPackedSgTxData),
.FULL(),
.RD_EN(SG_DATA_REN),
.RD_DATA(SG_DATA),
.EMPTY(SG_DATA_EMPTY),
.COUNT(wSgTxFifoCount)
);
// Manage requesting and acknowledging scatter gather data. Note that
// these modules will share the main requestor's RX channel. They will
// take priority over the main logic's use of the RX channel.
sg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgRxReq (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.USER_RST(wSgRst),
.BUF_RECVD(SG_RX_BUF_RECVD),
.BUF_DATA(SG_RX_BUF_DATA),
.BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
.BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
.BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
.FIFO_COUNT(wSgRxFifoCount),
.FIFO_FLUSH(wSgRxFlush),
.FIFO_FLUSHED(wSgRxFlushed),
.FIFO_RST(wSgRxRst),
.RX_REQ(wSgRxReq),
.RX_ADDR(wSgRxReqAddr),
.RX_LEN(wSgRxReqLen),
.RX_REQ_ACK(wReqAck & wSgRxReqProc),
.RX_DONE(wPackedSgRxDone)
);
sg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgTxReq (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.USER_RST(SG_RST),
.BUF_RECVD(SG_TX_BUF_RECVD),
.BUF_DATA(SG_TX_BUF_DATA),
.BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
.BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
.BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
.FIFO_COUNT(wSgTxFifoCount),
.FIFO_FLUSH(wSgTxFlush),
.FIFO_FLUSHED(wSgTxFlushed),
.FIFO_RST(wSgTxRst),
.RX_REQ(wSgTxReq),
.RX_ADDR(wSgTxReqAddr),
.RX_LEN(wSgTxReqLen),
.RX_REQ_ACK(wReqAck & wSgTxReqProc),
.RX_DONE(wPackedSgTxDone)
);
// A read requester for the channel and scatter gather requesters.
rx_port_requester_mux requesterMux (
.RST(rRst),
.CLK(CLK),
.SG_RX_REQ(wSgRxReq),
.SG_RX_LEN(wSgRxReqLen),
.SG_RX_ADDR(wSgRxReqAddr),
.SG_RX_REQ_PROC(wSgRxReqProc),
.SG_TX_REQ(wSgTxReq),
.SG_TX_LEN(wSgTxReqLen),
.SG_TX_ADDR(wSgTxReqAddr),
.SG_TX_REQ_PROC(wSgTxReqProc),
.MAIN_REQ(wMainReq),
.MAIN_LEN(wMainReqLen),
.MAIN_ADDR(wMainReqAddr),
.MAIN_REQ_PROC(wMainReqProc),
.RX_REQ(RX_REQ),
.RX_REQ_ACK(RX_REQ_ACK),
.RX_REQ_TAG(RX_REQ_TAG),
.RX_REQ_ADDR(RX_REQ_ADDR),
.RX_REQ_LEN(RX_REQ_LEN),
.REQ_ACK(wReqAck)
);
// Read the scatter gather buffer address and length, continuously so that
// we have it ready whenever the next buffer is needed.
sg_list_reader_64 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
.CLK(CLK),
.RST(rRst | wSgRst),
.BUF_DATA(wSgRxData),
.BUF_DATA_EMPTY(wSgRxDataEmpty),
.BUF_DATA_REN(wSgRxDataRen),
.VALID(wSgElemRdy),
.EMPTY(),
.REN(wSgElemRen),
.ADDR(wSgElemAddr),
.LEN(wSgElemLen)
);
// Main port reader logic
rx_port_reader #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_MAIN_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) reader (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.TXN_DATA(TXN_DATA),
.TXN_LEN_VALID(TXN_LEN_VALID),
.TXN_OFF_LAST_VALID(TXN_OFF_LAST_VALID),
.TXN_DONE_LEN(TXN_DONE_LEN),
.TXN_DONE(TXN_DONE),
.TXN_ERR(wTxnErr),
.TXN_DONE_ACK(TXN_DONE_ACK),
.TXN_DATA_FLUSH(wMainFlush),
.TXN_DATA_FLUSHED(wMainFlushed),
.RX_REQ(wMainReq),
.RX_ADDR(wMainReqAddr),
.RX_LEN(wMainReqLen),
.RX_REQ_ACK(wReqAck & wMainReqProc),
.RX_DATA_EN(MAIN_DATA_EN),
.RX_DONE(wPackedMainDone),
.RX_ERR(wPackedMainErr),
.SG_DONE(wPackedSgRxDone),
.SG_ERR(wPackedSgRxErr),
.SG_ELEM_ADDR(wSgElemAddr),
.SG_ELEM_LEN(wSgElemLen),
.SG_ELEM_RDY(wSgElemRdy),
.SG_ELEM_REN(wSgElemRen),
.SG_RST(wSgRst),
.CHNL_RX(wChnlRx),
.CHNL_RX_LEN(wChnlRxLen),
.CHNL_RX_LAST(wChnlRxLast),
.CHNL_RX_OFF(wChnlRxOff),
.CHNL_RX_RECVD(wChnlRxRecvd),
.CHNL_RX_ACK_RECVD(wChnlRxAckRecvd),
.CHNL_RX_CONSUMED(wChnlRxConsumed)
);
// Manage the CHNL_RX* signals in the CHNL_CLK domain.
rx_port_channel_gate #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
.RST(rRst),
.CLK(CLK),
.RX(wChnlRx),
.RX_RECVD(wChnlRxRecvd),
.RX_ACK_RECVD(wChnlRxAckRecvd),
.RX_LAST(wChnlRxLast),
.RX_LEN(wChnlRxLen),
.RX_OFF(wChnlRxOff),
.RX_CONSUMED(wChnlRxConsumed),
.RD_DATA(wMainData),
.RD_EMPTY(wMainDataEmpty),
.RD_EN(wMainDataRen),
.CHNL_CLK(CHNL_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CLK),
.CONTROL(wControl0),
.TRIG0({SG_RX_DATA_EN != 0, wSgElemRen, wMainReq | wSgRxReq | wSgTxReq,
RX_REQ, SG_RX_BUF_ADDR_LO_VALID | SG_RX_BUF_ADDR_HI_VALID | SG_RX_BUF_LEN_VALID,
wSgRst, wTxnErr | wPackedSgRxDone | wSgRxFlush | wSgRxFlushed, TXN_OFF_LAST_VALID | TXN_LEN_VALID}),
.DATA({
wPackedSgRxErr, // 1
wPackedSgRxDone, // 1
wPackedSgRxWen, // 1
wPackedSgRxData, // 64
SG_RX_ERR, // 1
SG_RX_DONE, // 1
SG_RX_DATA_EN, // 2
SG_RX_DATA, // 64
wSgRxDataRen, // 1
wSgRxDataEmpty, // 1
wSgRxData, // 64
wSgRst, // 1
SG_RST, // 1
wPackedSgRxDone, // 1
wSgRxRst, // 1
wSgRxFlushed, // 1
wSgRxFlush, // 1
SG_RX_BUF_ADDR_LO_VALID, // 1
SG_RX_BUF_ADDR_HI_VALID, // 1
SG_RX_BUF_LEN_VALID, // 1
SG_RX_BUF_DATA, // 32
RX_REQ_ADDR, // 64
RX_REQ_TAG, // 2
RX_REQ_ACK, // 1
RX_REQ, // 1
wSgTxReqProc, // 1
wSgTxReqAddr, // 64
wSgTxReq, // 1
wSgRxReqProc, // 1
wSgRxReqAddr, // 64
wSgRxReq, // 1
wMainReqProc, // 1
wMainReqAddr, // 64
wMainReq, // 1
wReqAck, // 1
wTxnErr, // 1
TXN_OFF_LAST_VALID, // 1
TXN_LEN_VALID}) // 1
);
*/
endmodule
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
// altera message_off 10036
// altera message_off 10230
// altera message_off 10858
module vector_add_basic_block_0
(
input clock,
input resetn,
input [63:0] input_x,
input [31:0] input_global_size_0,
input [63:0] input_y,
input [63:0] input_z,
input valid_in,
output stall_out,
input [31:0] input_global_id_0,
output valid_out,
input stall_in,
input [31:0] workgroup_size,
input start,
output avm_local_bb0_ld__enable,
input [255:0] avm_local_bb0_ld__readdata,
input avm_local_bb0_ld__readdatavalid,
input avm_local_bb0_ld__waitrequest,
output [29:0] avm_local_bb0_ld__address,
output avm_local_bb0_ld__read,
output avm_local_bb0_ld__write,
input avm_local_bb0_ld__writeack,
output [255:0] avm_local_bb0_ld__writedata,
output [31:0] avm_local_bb0_ld__byteenable,
output [4:0] avm_local_bb0_ld__burstcount,
output profile_lsu_local_bb0_ld__profile_bw_cntl,
output [31:0] profile_lsu_local_bb0_ld__profile_bw_incr,
output profile_lsu_local_bb0_ld__profile_total_ivalid_cntl,
output profile_lsu_local_bb0_ld__profile_avm_readwrite_count_cntl,
output profile_lsu_local_bb0_ld__profile_avm_burstcount_total_cntl,
output [31:0] profile_lsu_local_bb0_ld__profile_avm_burstcount_total_incr,
output profile_lsu_local_bb0_ld__profile_avm_stall_cntl,
output local_bb0_ld__active,
input clock2x,
output avm_local_bb0_ld__u0_enable,
input [255:0] avm_local_bb0_ld__u0_readdata,
input avm_local_bb0_ld__u0_readdatavalid,
input avm_local_bb0_ld__u0_waitrequest,
output [29:0] avm_local_bb0_ld__u0_address,
output avm_local_bb0_ld__u0_read,
output avm_local_bb0_ld__u0_write,
input avm_local_bb0_ld__u0_writeack,
output [255:0] avm_local_bb0_ld__u0_writedata,
output [31:0] avm_local_bb0_ld__u0_byteenable,
output [4:0] avm_local_bb0_ld__u0_burstcount,
output profile_lsu_local_bb0_ld__u0_profile_bw_cntl,
output [31:0] profile_lsu_local_bb0_ld__u0_profile_bw_incr,
output profile_lsu_local_bb0_ld__u0_profile_total_ivalid_cntl,
output profile_lsu_local_bb0_ld__u0_profile_avm_readwrite_count_cntl,
output profile_lsu_local_bb0_ld__u0_profile_avm_burstcount_total_cntl,
output [31:0] profile_lsu_local_bb0_ld__u0_profile_avm_burstcount_total_incr,
output profile_lsu_local_bb0_ld__u0_profile_avm_stall_cntl,
output local_bb0_ld__u0_active,
output avm_local_bb0_st_add_enable,
input [255:0] avm_local_bb0_st_add_readdata,
input avm_local_bb0_st_add_readdatavalid,
input avm_local_bb0_st_add_waitrequest,
output [29:0] avm_local_bb0_st_add_address,
output avm_local_bb0_st_add_read,
output avm_local_bb0_st_add_write,
input avm_local_bb0_st_add_writeack,
output [255:0] avm_local_bb0_st_add_writedata,
output [31:0] avm_local_bb0_st_add_byteenable,
output [4:0] avm_local_bb0_st_add_burstcount,
output profile_lsu_local_bb0_st_add_profile_bw_cntl,
output [31:0] profile_lsu_local_bb0_st_add_profile_bw_incr,
output profile_lsu_local_bb0_st_add_profile_total_ivalid_cntl,
output profile_lsu_local_bb0_st_add_profile_avm_readwrite_count_cntl,
output profile_lsu_local_bb0_st_add_profile_avm_burstcount_total_cntl,
output [31:0] profile_lsu_local_bb0_st_add_profile_avm_burstcount_total_incr,
output profile_lsu_local_bb0_st_add_profile_avm_stall_cntl,
output local_bb0_st_add_active
);
// Values used for debugging. These are swept away by synthesis.
wire _entry;
wire _exit;
reg [31:0] _num_entry_NO_SHIFT_REG;
reg [31:0] _num_exit_NO_SHIFT_REG;
wire [31:0] _num_live;
assign _entry = ((&valid_in) & ~((|stall_out)));
assign _exit = ((&valid_out) & ~((|stall_in)));
assign _num_live = (_num_entry_NO_SHIFT_REG - _num_exit_NO_SHIFT_REG);
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
_num_entry_NO_SHIFT_REG <= 32'h0;
_num_exit_NO_SHIFT_REG <= 32'h0;
end
else
begin
if (_entry)
begin
_num_entry_NO_SHIFT_REG <= (_num_entry_NO_SHIFT_REG + 2'h1);
end
if (_exit)
begin
_num_exit_NO_SHIFT_REG <= (_num_exit_NO_SHIFT_REG + 2'h1);
end
end
end
// This section defines the behaviour of the MERGE node
wire merge_node_stall_in;
reg merge_node_valid_out_NO_SHIFT_REG;
wire merge_stalled_by_successors;
reg merge_block_selector_NO_SHIFT_REG;
reg merge_node_valid_in_staging_reg_NO_SHIFT_REG;
reg [31:0] input_global_id_0_staging_reg_NO_SHIFT_REG;
reg [31:0] local_lvm_input_global_id_0_NO_SHIFT_REG;
reg is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
reg invariant_valid_NO_SHIFT_REG;
assign merge_stalled_by_successors = (|(merge_node_stall_in & merge_node_valid_out_NO_SHIFT_REG));
assign stall_out = merge_node_valid_in_staging_reg_NO_SHIFT_REG;
always @(*)
begin
if ((merge_node_valid_in_staging_reg_NO_SHIFT_REG | valid_in))
begin
merge_block_selector_NO_SHIFT_REG = 1'b0;
is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b1;
end
else
begin
merge_block_selector_NO_SHIFT_REG = 1'b0;
is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b0;
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
input_global_id_0_staging_reg_NO_SHIFT_REG <= 'x;
merge_node_valid_in_staging_reg_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (((merge_block_selector_NO_SHIFT_REG != 1'b0) | merge_stalled_by_successors))
begin
if (~(merge_node_valid_in_staging_reg_NO_SHIFT_REG))
begin
input_global_id_0_staging_reg_NO_SHIFT_REG <= input_global_id_0;
merge_node_valid_in_staging_reg_NO_SHIFT_REG <= valid_in;
end
end
else
begin
merge_node_valid_in_staging_reg_NO_SHIFT_REG <= 1'b0;
end
end
end
always @(posedge clock)
begin
if (~(merge_stalled_by_successors))
begin
case (merge_block_selector_NO_SHIFT_REG)
1'b0:
begin
if (merge_node_valid_in_staging_reg_NO_SHIFT_REG)
begin
local_lvm_input_global_id_0_NO_SHIFT_REG <= input_global_id_0_staging_reg_NO_SHIFT_REG;
end
else
begin
local_lvm_input_global_id_0_NO_SHIFT_REG <= input_global_id_0;
end
end
default:
begin
end
endcase
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
merge_node_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (~(merge_stalled_by_successors))
begin
merge_node_valid_out_NO_SHIFT_REG <= is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
end
else
begin
if (~(merge_node_stall_in))
begin
merge_node_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
invariant_valid_NO_SHIFT_REG <= 1'b0;
end
else
begin
invariant_valid_NO_SHIFT_REG <= (~(start) & (invariant_valid_NO_SHIFT_REG | is_merge_data_to_local_regs_valid_NO_SHIFT_REG));
end
end
// This section implements an unregistered operation.
//
wire local_bb0_idxprom_stall_local;
wire [63:0] local_bb0_idxprom;
assign local_bb0_idxprom[32] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[33] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[34] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[35] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[36] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[37] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[38] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[39] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[40] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[41] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[42] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[43] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[44] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[45] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[46] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[47] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[48] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[49] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[50] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[51] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[52] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[53] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[54] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[55] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[56] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[57] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[58] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[59] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[60] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[61] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[62] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[63] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb0_idxprom[31:0] = local_lvm_input_global_id_0_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb0_arrayidx_stall_local;
wire [63:0] local_bb0_arrayidx;
assign local_bb0_arrayidx = ((input_x & 64'hFFFFFFFFFFFFFC00) + (local_bb0_idxprom << 6'h2));
// This section implements an unregistered operation.
//
wire local_bb0_arrayidx2_stall_local;
wire [63:0] local_bb0_arrayidx2;
assign local_bb0_arrayidx2 = ((input_y & 64'hFFFFFFFFFFFFFC00) + (local_bb0_idxprom << 6'h2));
// This section implements an unregistered operation.
//
wire local_bb0_arrayidx_valid_out;
wire local_bb0_arrayidx_stall_in;
wire local_bb0_arrayidx2_valid_out;
wire local_bb0_arrayidx2_stall_in;
wire local_bb0_arrayidx4_valid_out;
wire local_bb0_arrayidx4_stall_in;
wire local_bb0_arrayidx4_inputs_ready;
wire local_bb0_arrayidx4_stall_local;
wire [63:0] local_bb0_arrayidx4;
reg local_bb0_arrayidx_consumed_0_NO_SHIFT_REG;
reg local_bb0_arrayidx2_consumed_0_NO_SHIFT_REG;
reg local_bb0_arrayidx4_consumed_0_NO_SHIFT_REG;
assign local_bb0_arrayidx4_inputs_ready = merge_node_valid_out_NO_SHIFT_REG;
assign local_bb0_arrayidx4 = ((input_z & 64'hFFFFFFFFFFFFFC00) + (local_bb0_idxprom << 6'h2));
assign local_bb0_arrayidx4_stall_local = ((local_bb0_arrayidx_stall_in & ~(local_bb0_arrayidx_consumed_0_NO_SHIFT_REG)) | (local_bb0_arrayidx2_stall_in & ~(local_bb0_arrayidx2_consumed_0_NO_SHIFT_REG)) | (local_bb0_arrayidx4_stall_in & ~(local_bb0_arrayidx4_consumed_0_NO_SHIFT_REG)));
assign local_bb0_arrayidx_valid_out = (local_bb0_arrayidx4_inputs_ready & ~(local_bb0_arrayidx_consumed_0_NO_SHIFT_REG));
assign local_bb0_arrayidx2_valid_out = (local_bb0_arrayidx4_inputs_ready & ~(local_bb0_arrayidx2_consumed_0_NO_SHIFT_REG));
assign local_bb0_arrayidx4_valid_out = (local_bb0_arrayidx4_inputs_ready & ~(local_bb0_arrayidx4_consumed_0_NO_SHIFT_REG));
assign merge_node_stall_in = (|local_bb0_arrayidx4_stall_local);
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb0_arrayidx_consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb0_arrayidx2_consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb0_arrayidx4_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb0_arrayidx_consumed_0_NO_SHIFT_REG <= (local_bb0_arrayidx4_inputs_ready & (local_bb0_arrayidx_consumed_0_NO_SHIFT_REG | ~(local_bb0_arrayidx_stall_in)) & local_bb0_arrayidx4_stall_local);
local_bb0_arrayidx2_consumed_0_NO_SHIFT_REG <= (local_bb0_arrayidx4_inputs_ready & (local_bb0_arrayidx2_consumed_0_NO_SHIFT_REG | ~(local_bb0_arrayidx2_stall_in)) & local_bb0_arrayidx4_stall_local);
local_bb0_arrayidx4_consumed_0_NO_SHIFT_REG <= (local_bb0_arrayidx4_inputs_ready & (local_bb0_arrayidx4_consumed_0_NO_SHIFT_REG | ~(local_bb0_arrayidx4_stall_in)) & local_bb0_arrayidx4_stall_local);
end
end
// This section implements a staging register.
//
wire rstag_1to1_bb0_arrayidx_valid_out;
wire rstag_1to1_bb0_arrayidx_stall_in;
wire rstag_1to1_bb0_arrayidx_inputs_ready;
wire rstag_1to1_bb0_arrayidx_stall_local;
reg rstag_1to1_bb0_arrayidx_staging_valid_NO_SHIFT_REG;
wire rstag_1to1_bb0_arrayidx_combined_valid;
reg [63:0] rstag_1to1_bb0_arrayidx_staging_reg_NO_SHIFT_REG;
wire [63:0] rstag_1to1_bb0_arrayidx;
assign rstag_1to1_bb0_arrayidx_inputs_ready = local_bb0_arrayidx_valid_out;
assign rstag_1to1_bb0_arrayidx = (rstag_1to1_bb0_arrayidx_staging_valid_NO_SHIFT_REG ? rstag_1to1_bb0_arrayidx_staging_reg_NO_SHIFT_REG : (local_bb0_arrayidx & 64'hFFFFFFFFFFFFFFFC));
assign rstag_1to1_bb0_arrayidx_combined_valid = (rstag_1to1_bb0_arrayidx_staging_valid_NO_SHIFT_REG | rstag_1to1_bb0_arrayidx_inputs_ready);
assign rstag_1to1_bb0_arrayidx_valid_out = rstag_1to1_bb0_arrayidx_combined_valid;
assign rstag_1to1_bb0_arrayidx_stall_local = rstag_1to1_bb0_arrayidx_stall_in;
assign local_bb0_arrayidx_stall_in = (|rstag_1to1_bb0_arrayidx_staging_valid_NO_SHIFT_REG);
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
rstag_1to1_bb0_arrayidx_staging_valid_NO_SHIFT_REG <= 1'b0;
rstag_1to1_bb0_arrayidx_staging_reg_NO_SHIFT_REG <= 'x;
end
else
begin
if (rstag_1to1_bb0_arrayidx_stall_local)
begin
if (~(rstag_1to1_bb0_arrayidx_staging_valid_NO_SHIFT_REG))
begin
rstag_1to1_bb0_arrayidx_staging_valid_NO_SHIFT_REG <= rstag_1to1_bb0_arrayidx_inputs_ready;
end
end
else
begin
rstag_1to1_bb0_arrayidx_staging_valid_NO_SHIFT_REG <= 1'b0;
end
if (~(rstag_1to1_bb0_arrayidx_staging_valid_NO_SHIFT_REG))
begin
rstag_1to1_bb0_arrayidx_staging_reg_NO_SHIFT_REG <= (local_bb0_arrayidx & 64'hFFFFFFFFFFFFFFFC);
end
end
end
// This section implements a staging register.
//
wire rstag_1to1_bb0_arrayidx2_valid_out;
wire rstag_1to1_bb0_arrayidx2_stall_in;
wire rstag_1to1_bb0_arrayidx2_inputs_ready;
wire rstag_1to1_bb0_arrayidx2_stall_local;
reg rstag_1to1_bb0_arrayidx2_staging_valid_NO_SHIFT_REG;
wire rstag_1to1_bb0_arrayidx2_combined_valid;
reg [63:0] rstag_1to1_bb0_arrayidx2_staging_reg_NO_SHIFT_REG;
wire [63:0] rstag_1to1_bb0_arrayidx2;
assign rstag_1to1_bb0_arrayidx2_inputs_ready = local_bb0_arrayidx2_valid_out;
assign rstag_1to1_bb0_arrayidx2 = (rstag_1to1_bb0_arrayidx2_staging_valid_NO_SHIFT_REG ? rstag_1to1_bb0_arrayidx2_staging_reg_NO_SHIFT_REG : (local_bb0_arrayidx2 & 64'hFFFFFFFFFFFFFFFC));
assign rstag_1to1_bb0_arrayidx2_combined_valid = (rstag_1to1_bb0_arrayidx2_staging_valid_NO_SHIFT_REG | rstag_1to1_bb0_arrayidx2_inputs_ready);
assign rstag_1to1_bb0_arrayidx2_valid_out = rstag_1to1_bb0_arrayidx2_combined_valid;
assign rstag_1to1_bb0_arrayidx2_stall_local = rstag_1to1_bb0_arrayidx2_stall_in;
assign local_bb0_arrayidx2_stall_in = (|rstag_1to1_bb0_arrayidx2_staging_valid_NO_SHIFT_REG);
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
rstag_1to1_bb0_arrayidx2_staging_valid_NO_SHIFT_REG <= 1'b0;
rstag_1to1_bb0_arrayidx2_staging_reg_NO_SHIFT_REG <= 'x;
end
else
begin
if (rstag_1to1_bb0_arrayidx2_stall_local)
begin
if (~(rstag_1to1_bb0_arrayidx2_staging_valid_NO_SHIFT_REG))
begin
rstag_1to1_bb0_arrayidx2_staging_valid_NO_SHIFT_REG <= rstag_1to1_bb0_arrayidx2_inputs_ready;
end
end
else
begin
rstag_1to1_bb0_arrayidx2_staging_valid_NO_SHIFT_REG <= 1'b0;
end
if (~(rstag_1to1_bb0_arrayidx2_staging_valid_NO_SHIFT_REG))
begin
rstag_1to1_bb0_arrayidx2_staging_reg_NO_SHIFT_REG <= (local_bb0_arrayidx2 & 64'hFFFFFFFFFFFFFFFC);
end
end
end
// Register node:
// * latency = 2
// * capacity = 2
logic rnode_1to3_bb0_arrayidx4_0_valid_out_NO_SHIFT_REG;
logic rnode_1to3_bb0_arrayidx4_0_stall_in_NO_SHIFT_REG;
logic [63:0] rnode_1to3_bb0_arrayidx4_0_NO_SHIFT_REG;
logic rnode_1to3_bb0_arrayidx4_0_reg_3_inputs_ready_NO_SHIFT_REG;
logic [63:0] rnode_1to3_bb0_arrayidx4_0_reg_3_NO_SHIFT_REG;
logic rnode_1to3_bb0_arrayidx4_0_valid_out_reg_3_NO_SHIFT_REG;
logic rnode_1to3_bb0_arrayidx4_0_stall_in_reg_3_NO_SHIFT_REG;
logic rnode_1to3_bb0_arrayidx4_0_stall_out_reg_3_NO_SHIFT_REG;
acl_data_fifo rnode_1to3_bb0_arrayidx4_0_reg_3_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_1to3_bb0_arrayidx4_0_reg_3_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_1to3_bb0_arrayidx4_0_stall_in_reg_3_NO_SHIFT_REG),
.valid_out(rnode_1to3_bb0_arrayidx4_0_valid_out_reg_3_NO_SHIFT_REG),
.stall_out(rnode_1to3_bb0_arrayidx4_0_stall_out_reg_3_NO_SHIFT_REG),
.data_in((local_bb0_arrayidx4 & 64'hFFFFFFFFFFFFFFFC)),
.data_out(rnode_1to3_bb0_arrayidx4_0_reg_3_NO_SHIFT_REG)
);
defparam rnode_1to3_bb0_arrayidx4_0_reg_3_fifo.DEPTH = 3;
defparam rnode_1to3_bb0_arrayidx4_0_reg_3_fifo.DATA_WIDTH = 64;
defparam rnode_1to3_bb0_arrayidx4_0_reg_3_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_1to3_bb0_arrayidx4_0_reg_3_fifo.IMPL = "ll_reg";
assign rnode_1to3_bb0_arrayidx4_0_reg_3_inputs_ready_NO_SHIFT_REG = local_bb0_arrayidx4_valid_out;
assign local_bb0_arrayidx4_stall_in = rnode_1to3_bb0_arrayidx4_0_stall_out_reg_3_NO_SHIFT_REG;
assign rnode_1to3_bb0_arrayidx4_0_NO_SHIFT_REG = rnode_1to3_bb0_arrayidx4_0_reg_3_NO_SHIFT_REG;
assign rnode_1to3_bb0_arrayidx4_0_stall_in_reg_3_NO_SHIFT_REG = rnode_1to3_bb0_arrayidx4_0_stall_in_NO_SHIFT_REG;
assign rnode_1to3_bb0_arrayidx4_0_valid_out_NO_SHIFT_REG = rnode_1to3_bb0_arrayidx4_0_valid_out_reg_3_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb0_ld__inputs_ready;
reg local_bb0_ld__valid_out_NO_SHIFT_REG;
wire local_bb0_ld__stall_in;
wire local_bb0_ld__output_regs_ready;
wire local_bb0_ld__fu_stall_out;
wire local_bb0_ld__fu_valid_out;
wire [31:0] local_bb0_ld__lsu_dataout;
reg [31:0] local_bb0_ld__NO_SHIFT_REG;
wire local_bb0_ld__causedstall;
lsu_top lsu_local_bb0_ld_ (
.clock(clock),
.clock2x(clock2x),
.resetn(resetn),
.flush(start),
.stream_base_addr((rstag_1to1_bb0_arrayidx & 64'hFFFFFFFFFFFFFFFC)),
.stream_size(input_global_size_0),
.stream_reset(valid_in),
.o_stall(local_bb0_ld__fu_stall_out),
.i_valid(local_bb0_ld__inputs_ready),
.i_address((rstag_1to1_bb0_arrayidx & 64'hFFFFFFFFFFFFFFFC)),
.i_writedata(),
.i_cmpdata(),
.i_predicate(1'b0),
.i_bitwiseor(64'h0),
.i_byteenable(),
.i_stall(~(local_bb0_ld__output_regs_ready)),
.o_valid(local_bb0_ld__fu_valid_out),
.o_readdata(local_bb0_ld__lsu_dataout),
.o_input_fifo_depth(),
.o_writeack(),
.i_atomic_op(3'h0),
.o_active(local_bb0_ld__active),
.avm_address(avm_local_bb0_ld__address),
.avm_read(avm_local_bb0_ld__read),
.avm_enable(avm_local_bb0_ld__enable),
.avm_readdata(avm_local_bb0_ld__readdata),
.avm_write(avm_local_bb0_ld__write),
.avm_writeack(avm_local_bb0_ld__writeack),
.avm_burstcount(avm_local_bb0_ld__burstcount),
.avm_writedata(avm_local_bb0_ld__writedata),
.avm_byteenable(avm_local_bb0_ld__byteenable),
.avm_waitrequest(avm_local_bb0_ld__waitrequest),
.avm_readdatavalid(avm_local_bb0_ld__readdatavalid),
.profile_bw(profile_lsu_local_bb0_ld__profile_bw_cntl),
.profile_bw_incr(profile_lsu_local_bb0_ld__profile_bw_incr),
.profile_total_ivalid(profile_lsu_local_bb0_ld__profile_total_ivalid_cntl),
.profile_total_req(),
.profile_i_stall_count(),
.profile_o_stall_count(),
.profile_avm_readwrite_count(profile_lsu_local_bb0_ld__profile_avm_readwrite_count_cntl),
.profile_avm_burstcount_total(profile_lsu_local_bb0_ld__profile_avm_burstcount_total_cntl),
.profile_avm_burstcount_total_incr(profile_lsu_local_bb0_ld__profile_avm_burstcount_total_incr),
.profile_req_cache_hit_count(),
.profile_extra_unaligned_reqs(),
.profile_avm_stall(profile_lsu_local_bb0_ld__profile_avm_stall_cntl)
);
defparam lsu_local_bb0_ld_.AWIDTH = 30;
defparam lsu_local_bb0_ld_.WIDTH_BYTES = 4;
defparam lsu_local_bb0_ld_.MWIDTH_BYTES = 32;
defparam lsu_local_bb0_ld_.WRITEDATAWIDTH_BYTES = 32;
defparam lsu_local_bb0_ld_.ALIGNMENT_BYTES = 4;
defparam lsu_local_bb0_ld_.READ = 1;
defparam lsu_local_bb0_ld_.ATOMIC = 0;
defparam lsu_local_bb0_ld_.WIDTH = 32;
defparam lsu_local_bb0_ld_.MWIDTH = 256;
defparam lsu_local_bb0_ld_.ATOMIC_WIDTH = 3;
defparam lsu_local_bb0_ld_.BURSTCOUNT_WIDTH = 5;
defparam lsu_local_bb0_ld_.KERNEL_SIDE_MEM_LATENCY = 2;
defparam lsu_local_bb0_ld_.MEMORY_SIDE_MEM_LATENCY = 89;
defparam lsu_local_bb0_ld_.USE_WRITE_ACK = 0;
defparam lsu_local_bb0_ld_.ENABLE_BANKED_MEMORY = 0;
defparam lsu_local_bb0_ld_.ABITS_PER_LMEM_BANK = 0;
defparam lsu_local_bb0_ld_.NUMBER_BANKS = 1;
defparam lsu_local_bb0_ld_.LMEM_ADDR_PERMUTATION_STYLE = 0;
defparam lsu_local_bb0_ld_.INTENDED_DEVICE_FAMILY = "Cyclone V";
defparam lsu_local_bb0_ld_.USEINPUTFIFO = 0;
defparam lsu_local_bb0_ld_.USECACHING = 0;
defparam lsu_local_bb0_ld_.USEOUTPUTFIFO = 1;
defparam lsu_local_bb0_ld_.FORCE_NOP_SUPPORT = 0;
defparam lsu_local_bb0_ld_.ACL_PROFILE = 1;
defparam lsu_local_bb0_ld_.ACL_PROFILE_INCREMENT_WIDTH = 32;
defparam lsu_local_bb0_ld_.ADDRSPACE = 1;
defparam lsu_local_bb0_ld_.STYLE = "STREAMING";
assign local_bb0_ld__inputs_ready = rstag_1to1_bb0_arrayidx_valid_out;
assign local_bb0_ld__output_regs_ready = (&(~(local_bb0_ld__valid_out_NO_SHIFT_REG) | ~(local_bb0_ld__stall_in)));
assign rstag_1to1_bb0_arrayidx_stall_in = (local_bb0_ld__fu_stall_out | ~(local_bb0_ld__inputs_ready));
assign local_bb0_ld__causedstall = (local_bb0_ld__inputs_ready && (local_bb0_ld__fu_stall_out && !(~(local_bb0_ld__output_regs_ready))));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb0_ld__NO_SHIFT_REG <= 'x;
local_bb0_ld__valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb0_ld__output_regs_ready)
begin
local_bb0_ld__NO_SHIFT_REG <= local_bb0_ld__lsu_dataout;
local_bb0_ld__valid_out_NO_SHIFT_REG <= local_bb0_ld__fu_valid_out;
end
else
begin
if (~(local_bb0_ld__stall_in))
begin
local_bb0_ld__valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements a registered operation.
//
wire local_bb0_ld__u0_inputs_ready;
reg local_bb0_ld__u0_valid_out_NO_SHIFT_REG;
wire local_bb0_ld__u0_stall_in;
wire local_bb0_ld__u0_output_regs_ready;
wire local_bb0_ld__u0_fu_stall_out;
wire local_bb0_ld__u0_fu_valid_out;
wire [31:0] local_bb0_ld__u0_lsu_dataout;
reg [31:0] local_bb0_ld__u0_NO_SHIFT_REG;
wire local_bb0_ld__u0_causedstall;
lsu_top lsu_local_bb0_ld__u0 (
.clock(clock),
.clock2x(clock2x),
.resetn(resetn),
.flush(start),
.stream_base_addr((rstag_1to1_bb0_arrayidx2 & 64'hFFFFFFFFFFFFFFFC)),
.stream_size(input_global_size_0),
.stream_reset(valid_in),
.o_stall(local_bb0_ld__u0_fu_stall_out),
.i_valid(local_bb0_ld__u0_inputs_ready),
.i_address((rstag_1to1_bb0_arrayidx2 & 64'hFFFFFFFFFFFFFFFC)),
.i_writedata(),
.i_cmpdata(),
.i_predicate(1'b0),
.i_bitwiseor(64'h0),
.i_byteenable(),
.i_stall(~(local_bb0_ld__u0_output_regs_ready)),
.o_valid(local_bb0_ld__u0_fu_valid_out),
.o_readdata(local_bb0_ld__u0_lsu_dataout),
.o_input_fifo_depth(),
.o_writeack(),
.i_atomic_op(3'h0),
.o_active(local_bb0_ld__u0_active),
.avm_address(avm_local_bb0_ld__u0_address),
.avm_read(avm_local_bb0_ld__u0_read),
.avm_enable(avm_local_bb0_ld__u0_enable),
.avm_readdata(avm_local_bb0_ld__u0_readdata),
.avm_write(avm_local_bb0_ld__u0_write),
.avm_writeack(avm_local_bb0_ld__u0_writeack),
.avm_burstcount(avm_local_bb0_ld__u0_burstcount),
.avm_writedata(avm_local_bb0_ld__u0_writedata),
.avm_byteenable(avm_local_bb0_ld__u0_byteenable),
.avm_waitrequest(avm_local_bb0_ld__u0_waitrequest),
.avm_readdatavalid(avm_local_bb0_ld__u0_readdatavalid),
.profile_bw(profile_lsu_local_bb0_ld__u0_profile_bw_cntl),
.profile_bw_incr(profile_lsu_local_bb0_ld__u0_profile_bw_incr),
.profile_total_ivalid(profile_lsu_local_bb0_ld__u0_profile_total_ivalid_cntl),
.profile_total_req(),
.profile_i_stall_count(),
.profile_o_stall_count(),
.profile_avm_readwrite_count(profile_lsu_local_bb0_ld__u0_profile_avm_readwrite_count_cntl),
.profile_avm_burstcount_total(profile_lsu_local_bb0_ld__u0_profile_avm_burstcount_total_cntl),
.profile_avm_burstcount_total_incr(profile_lsu_local_bb0_ld__u0_profile_avm_burstcount_total_incr),
.profile_req_cache_hit_count(),
.profile_extra_unaligned_reqs(),
.profile_avm_stall(profile_lsu_local_bb0_ld__u0_profile_avm_stall_cntl)
);
defparam lsu_local_bb0_ld__u0.AWIDTH = 30;
defparam lsu_local_bb0_ld__u0.WIDTH_BYTES = 4;
defparam lsu_local_bb0_ld__u0.MWIDTH_BYTES = 32;
defparam lsu_local_bb0_ld__u0.WRITEDATAWIDTH_BYTES = 32;
defparam lsu_local_bb0_ld__u0.ALIGNMENT_BYTES = 4;
defparam lsu_local_bb0_ld__u0.READ = 1;
defparam lsu_local_bb0_ld__u0.ATOMIC = 0;
defparam lsu_local_bb0_ld__u0.WIDTH = 32;
defparam lsu_local_bb0_ld__u0.MWIDTH = 256;
defparam lsu_local_bb0_ld__u0.ATOMIC_WIDTH = 3;
defparam lsu_local_bb0_ld__u0.BURSTCOUNT_WIDTH = 5;
defparam lsu_local_bb0_ld__u0.KERNEL_SIDE_MEM_LATENCY = 2;
defparam lsu_local_bb0_ld__u0.MEMORY_SIDE_MEM_LATENCY = 89;
defparam lsu_local_bb0_ld__u0.USE_WRITE_ACK = 0;
defparam lsu_local_bb0_ld__u0.ENABLE_BANKED_MEMORY = 0;
defparam lsu_local_bb0_ld__u0.ABITS_PER_LMEM_BANK = 0;
defparam lsu_local_bb0_ld__u0.NUMBER_BANKS = 1;
defparam lsu_local_bb0_ld__u0.LMEM_ADDR_PERMUTATION_STYLE = 0;
defparam lsu_local_bb0_ld__u0.INTENDED_DEVICE_FAMILY = "Cyclone V";
defparam lsu_local_bb0_ld__u0.USEINPUTFIFO = 0;
defparam lsu_local_bb0_ld__u0.USECACHING = 0;
defparam lsu_local_bb0_ld__u0.USEOUTPUTFIFO = 1;
defparam lsu_local_bb0_ld__u0.FORCE_NOP_SUPPORT = 0;
defparam lsu_local_bb0_ld__u0.ACL_PROFILE = 1;
defparam lsu_local_bb0_ld__u0.ACL_PROFILE_INCREMENT_WIDTH = 32;
defparam lsu_local_bb0_ld__u0.ADDRSPACE = 1;
defparam lsu_local_bb0_ld__u0.STYLE = "STREAMING";
assign local_bb0_ld__u0_inputs_ready = rstag_1to1_bb0_arrayidx2_valid_out;
assign local_bb0_ld__u0_output_regs_ready = (&(~(local_bb0_ld__u0_valid_out_NO_SHIFT_REG) | ~(local_bb0_ld__u0_stall_in)));
assign rstag_1to1_bb0_arrayidx2_stall_in = (local_bb0_ld__u0_fu_stall_out | ~(local_bb0_ld__u0_inputs_ready));
assign local_bb0_ld__u0_causedstall = (local_bb0_ld__u0_inputs_ready && (local_bb0_ld__u0_fu_stall_out && !(~(local_bb0_ld__u0_output_regs_ready))));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb0_ld__u0_NO_SHIFT_REG <= 'x;
local_bb0_ld__u0_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb0_ld__u0_output_regs_ready)
begin
local_bb0_ld__u0_NO_SHIFT_REG <= local_bb0_ld__u0_lsu_dataout;
local_bb0_ld__u0_valid_out_NO_SHIFT_REG <= local_bb0_ld__u0_fu_valid_out;
end
else
begin
if (~(local_bb0_ld__u0_stall_in))
begin
local_bb0_ld__u0_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements a staging register.
//
wire rstag_3to3_bb0_ld__valid_out;
wire rstag_3to3_bb0_ld__stall_in;
wire rstag_3to3_bb0_ld__inputs_ready;
wire rstag_3to3_bb0_ld__stall_local;
reg rstag_3to3_bb0_ld__staging_valid_NO_SHIFT_REG;
wire rstag_3to3_bb0_ld__combined_valid;
reg [31:0] rstag_3to3_bb0_ld__staging_reg_NO_SHIFT_REG;
wire [31:0] rstag_3to3_bb0_ld_;
assign rstag_3to3_bb0_ld__inputs_ready = local_bb0_ld__valid_out_NO_SHIFT_REG;
assign rstag_3to3_bb0_ld_ = (rstag_3to3_bb0_ld__staging_valid_NO_SHIFT_REG ? rstag_3to3_bb0_ld__staging_reg_NO_SHIFT_REG : local_bb0_ld__NO_SHIFT_REG);
assign rstag_3to3_bb0_ld__combined_valid = (rstag_3to3_bb0_ld__staging_valid_NO_SHIFT_REG | rstag_3to3_bb0_ld__inputs_ready);
assign rstag_3to3_bb0_ld__valid_out = rstag_3to3_bb0_ld__combined_valid;
assign rstag_3to3_bb0_ld__stall_local = rstag_3to3_bb0_ld__stall_in;
assign local_bb0_ld__stall_in = (|rstag_3to3_bb0_ld__staging_valid_NO_SHIFT_REG);
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
rstag_3to3_bb0_ld__staging_valid_NO_SHIFT_REG <= 1'b0;
rstag_3to3_bb0_ld__staging_reg_NO_SHIFT_REG <= 'x;
end
else
begin
if (rstag_3to3_bb0_ld__stall_local)
begin
if (~(rstag_3to3_bb0_ld__staging_valid_NO_SHIFT_REG))
begin
rstag_3to3_bb0_ld__staging_valid_NO_SHIFT_REG <= rstag_3to3_bb0_ld__inputs_ready;
end
end
else
begin
rstag_3to3_bb0_ld__staging_valid_NO_SHIFT_REG <= 1'b0;
end
if (~(rstag_3to3_bb0_ld__staging_valid_NO_SHIFT_REG))
begin
rstag_3to3_bb0_ld__staging_reg_NO_SHIFT_REG <= local_bb0_ld__NO_SHIFT_REG;
end
end
end
// This section implements a staging register.
//
wire rstag_3to3_bb0_ld__u0_valid_out;
wire rstag_3to3_bb0_ld__u0_stall_in;
wire rstag_3to3_bb0_ld__u0_inputs_ready;
wire rstag_3to3_bb0_ld__u0_stall_local;
reg rstag_3to3_bb0_ld__u0_staging_valid_NO_SHIFT_REG;
wire rstag_3to3_bb0_ld__u0_combined_valid;
reg [31:0] rstag_3to3_bb0_ld__u0_staging_reg_NO_SHIFT_REG;
wire [31:0] rstag_3to3_bb0_ld__u0;
assign rstag_3to3_bb0_ld__u0_inputs_ready = local_bb0_ld__u0_valid_out_NO_SHIFT_REG;
assign rstag_3to3_bb0_ld__u0 = (rstag_3to3_bb0_ld__u0_staging_valid_NO_SHIFT_REG ? rstag_3to3_bb0_ld__u0_staging_reg_NO_SHIFT_REG : local_bb0_ld__u0_NO_SHIFT_REG);
assign rstag_3to3_bb0_ld__u0_combined_valid = (rstag_3to3_bb0_ld__u0_staging_valid_NO_SHIFT_REG | rstag_3to3_bb0_ld__u0_inputs_ready);
assign rstag_3to3_bb0_ld__u0_valid_out = rstag_3to3_bb0_ld__u0_combined_valid;
assign rstag_3to3_bb0_ld__u0_stall_local = rstag_3to3_bb0_ld__u0_stall_in;
assign local_bb0_ld__u0_stall_in = (|rstag_3to3_bb0_ld__u0_staging_valid_NO_SHIFT_REG);
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
rstag_3to3_bb0_ld__u0_staging_valid_NO_SHIFT_REG <= 1'b0;
rstag_3to3_bb0_ld__u0_staging_reg_NO_SHIFT_REG <= 'x;
end
else
begin
if (rstag_3to3_bb0_ld__u0_stall_local)
begin
if (~(rstag_3to3_bb0_ld__u0_staging_valid_NO_SHIFT_REG))
begin
rstag_3to3_bb0_ld__u0_staging_valid_NO_SHIFT_REG <= rstag_3to3_bb0_ld__u0_inputs_ready;
end
end
else
begin
rstag_3to3_bb0_ld__u0_staging_valid_NO_SHIFT_REG <= 1'b0;
end
if (~(rstag_3to3_bb0_ld__u0_staging_valid_NO_SHIFT_REG))
begin
rstag_3to3_bb0_ld__u0_staging_reg_NO_SHIFT_REG <= local_bb0_ld__u0_NO_SHIFT_REG;
end
end
end
// This section implements an unregistered operation.
//
wire local_bb0_add_valid_out;
wire local_bb0_add_stall_in;
wire local_bb0_add_inputs_ready;
wire local_bb0_add_stall_local;
wire [31:0] local_bb0_add;
assign local_bb0_add_inputs_ready = (rstag_3to3_bb0_ld__u0_valid_out & rstag_3to3_bb0_ld__valid_out);
assign local_bb0_add = (rstag_3to3_bb0_ld__u0 + rstag_3to3_bb0_ld_);
assign local_bb0_add_valid_out = local_bb0_add_inputs_ready;
assign local_bb0_add_stall_local = local_bb0_add_stall_in;
assign rstag_3to3_bb0_ld__u0_stall_in = (local_bb0_add_stall_local | ~(local_bb0_add_inputs_ready));
assign rstag_3to3_bb0_ld__stall_in = (local_bb0_add_stall_local | ~(local_bb0_add_inputs_ready));
// This section implements a staging register.
//
wire rstag_3to3_bb0_add_valid_out;
wire rstag_3to3_bb0_add_stall_in;
wire rstag_3to3_bb0_add_inputs_ready;
wire rstag_3to3_bb0_add_stall_local;
reg rstag_3to3_bb0_add_staging_valid_NO_SHIFT_REG;
wire rstag_3to3_bb0_add_combined_valid;
reg [31:0] rstag_3to3_bb0_add_staging_reg_NO_SHIFT_REG;
wire [31:0] rstag_3to3_bb0_add;
assign rstag_3to3_bb0_add_inputs_ready = local_bb0_add_valid_out;
assign rstag_3to3_bb0_add = (rstag_3to3_bb0_add_staging_valid_NO_SHIFT_REG ? rstag_3to3_bb0_add_staging_reg_NO_SHIFT_REG : local_bb0_add);
assign rstag_3to3_bb0_add_combined_valid = (rstag_3to3_bb0_add_staging_valid_NO_SHIFT_REG | rstag_3to3_bb0_add_inputs_ready);
assign rstag_3to3_bb0_add_valid_out = rstag_3to3_bb0_add_combined_valid;
assign rstag_3to3_bb0_add_stall_local = rstag_3to3_bb0_add_stall_in;
assign local_bb0_add_stall_in = (|rstag_3to3_bb0_add_staging_valid_NO_SHIFT_REG);
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
rstag_3to3_bb0_add_staging_valid_NO_SHIFT_REG <= 1'b0;
rstag_3to3_bb0_add_staging_reg_NO_SHIFT_REG <= 'x;
end
else
begin
if (rstag_3to3_bb0_add_stall_local)
begin
if (~(rstag_3to3_bb0_add_staging_valid_NO_SHIFT_REG))
begin
rstag_3to3_bb0_add_staging_valid_NO_SHIFT_REG <= rstag_3to3_bb0_add_inputs_ready;
end
end
else
begin
rstag_3to3_bb0_add_staging_valid_NO_SHIFT_REG <= 1'b0;
end
if (~(rstag_3to3_bb0_add_staging_valid_NO_SHIFT_REG))
begin
rstag_3to3_bb0_add_staging_reg_NO_SHIFT_REG <= local_bb0_add;
end
end
end
// This section implements a registered operation.
//
wire local_bb0_st_add_inputs_ready;
reg local_bb0_st_add_valid_out_NO_SHIFT_REG;
wire local_bb0_st_add_stall_in;
wire local_bb0_st_add_output_regs_ready;
wire local_bb0_st_add_fu_stall_out;
wire local_bb0_st_add_fu_valid_out;
wire local_bb0_st_add_causedstall;
lsu_top lsu_local_bb0_st_add (
.clock(clock),
.clock2x(clock2x),
.resetn(resetn),
.flush(start),
.stream_base_addr((rnode_1to3_bb0_arrayidx4_0_NO_SHIFT_REG & 64'hFFFFFFFFFFFFFFFC)),
.stream_size(input_global_size_0),
.stream_reset(valid_in),
.o_stall(local_bb0_st_add_fu_stall_out),
.i_valid(local_bb0_st_add_inputs_ready),
.i_address((rnode_1to3_bb0_arrayidx4_0_NO_SHIFT_REG & 64'hFFFFFFFFFFFFFFFC)),
.i_writedata(rstag_3to3_bb0_add),
.i_cmpdata(),
.i_predicate(1'b0),
.i_bitwiseor(64'h0),
.i_byteenable(),
.i_stall(~(local_bb0_st_add_output_regs_ready)),
.o_valid(local_bb0_st_add_fu_valid_out),
.o_readdata(),
.o_input_fifo_depth(),
.o_writeack(),
.i_atomic_op(3'h0),
.o_active(local_bb0_st_add_active),
.avm_address(avm_local_bb0_st_add_address),
.avm_read(avm_local_bb0_st_add_read),
.avm_enable(avm_local_bb0_st_add_enable),
.avm_readdata(avm_local_bb0_st_add_readdata),
.avm_write(avm_local_bb0_st_add_write),
.avm_writeack(avm_local_bb0_st_add_writeack),
.avm_burstcount(avm_local_bb0_st_add_burstcount),
.avm_writedata(avm_local_bb0_st_add_writedata),
.avm_byteenable(avm_local_bb0_st_add_byteenable),
.avm_waitrequest(avm_local_bb0_st_add_waitrequest),
.avm_readdatavalid(avm_local_bb0_st_add_readdatavalid),
.profile_bw(profile_lsu_local_bb0_st_add_profile_bw_cntl),
.profile_bw_incr(profile_lsu_local_bb0_st_add_profile_bw_incr),
.profile_total_ivalid(profile_lsu_local_bb0_st_add_profile_total_ivalid_cntl),
.profile_total_req(),
.profile_i_stall_count(),
.profile_o_stall_count(),
.profile_avm_readwrite_count(profile_lsu_local_bb0_st_add_profile_avm_readwrite_count_cntl),
.profile_avm_burstcount_total(profile_lsu_local_bb0_st_add_profile_avm_burstcount_total_cntl),
.profile_avm_burstcount_total_incr(profile_lsu_local_bb0_st_add_profile_avm_burstcount_total_incr),
.profile_req_cache_hit_count(),
.profile_extra_unaligned_reqs(),
.profile_avm_stall(profile_lsu_local_bb0_st_add_profile_avm_stall_cntl)
);
defparam lsu_local_bb0_st_add.AWIDTH = 30;
defparam lsu_local_bb0_st_add.WIDTH_BYTES = 4;
defparam lsu_local_bb0_st_add.MWIDTH_BYTES = 32;
defparam lsu_local_bb0_st_add.WRITEDATAWIDTH_BYTES = 32;
defparam lsu_local_bb0_st_add.ALIGNMENT_BYTES = 4;
defparam lsu_local_bb0_st_add.READ = 0;
defparam lsu_local_bb0_st_add.ATOMIC = 0;
defparam lsu_local_bb0_st_add.WIDTH = 32;
defparam lsu_local_bb0_st_add.MWIDTH = 256;
defparam lsu_local_bb0_st_add.ATOMIC_WIDTH = 3;
defparam lsu_local_bb0_st_add.BURSTCOUNT_WIDTH = 5;
defparam lsu_local_bb0_st_add.KERNEL_SIDE_MEM_LATENCY = 2;
defparam lsu_local_bb0_st_add.MEMORY_SIDE_MEM_LATENCY = 32;
defparam lsu_local_bb0_st_add.USE_WRITE_ACK = 0;
defparam lsu_local_bb0_st_add.ENABLE_BANKED_MEMORY = 0;
defparam lsu_local_bb0_st_add.ABITS_PER_LMEM_BANK = 0;
defparam lsu_local_bb0_st_add.NUMBER_BANKS = 1;
defparam lsu_local_bb0_st_add.LMEM_ADDR_PERMUTATION_STYLE = 0;
defparam lsu_local_bb0_st_add.INTENDED_DEVICE_FAMILY = "Cyclone V";
defparam lsu_local_bb0_st_add.USEINPUTFIFO = 0;
defparam lsu_local_bb0_st_add.USECACHING = 0;
defparam lsu_local_bb0_st_add.USEOUTPUTFIFO = 1;
defparam lsu_local_bb0_st_add.FORCE_NOP_SUPPORT = 0;
defparam lsu_local_bb0_st_add.ACL_PROFILE = 1;
defparam lsu_local_bb0_st_add.ACL_PROFILE_INCREMENT_WIDTH = 32;
defparam lsu_local_bb0_st_add.ADDRSPACE = 1;
defparam lsu_local_bb0_st_add.STYLE = "STREAMING";
defparam lsu_local_bb0_st_add.USE_BYTE_EN = 0;
assign local_bb0_st_add_inputs_ready = (rnode_1to3_bb0_arrayidx4_0_valid_out_NO_SHIFT_REG & rstag_3to3_bb0_add_valid_out);
assign local_bb0_st_add_output_regs_ready = (&(~(local_bb0_st_add_valid_out_NO_SHIFT_REG) | ~(local_bb0_st_add_stall_in)));
assign rnode_1to3_bb0_arrayidx4_0_stall_in_NO_SHIFT_REG = (local_bb0_st_add_fu_stall_out | ~(local_bb0_st_add_inputs_ready));
assign rstag_3to3_bb0_add_stall_in = (local_bb0_st_add_fu_stall_out | ~(local_bb0_st_add_inputs_ready));
assign local_bb0_st_add_causedstall = (local_bb0_st_add_inputs_ready && (local_bb0_st_add_fu_stall_out && !(~(local_bb0_st_add_output_regs_ready))));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb0_st_add_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb0_st_add_output_regs_ready)
begin
local_bb0_st_add_valid_out_NO_SHIFT_REG <= local_bb0_st_add_fu_valid_out;
end
else
begin
if (~(local_bb0_st_add_stall_in))
begin
local_bb0_st_add_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements a staging register.
//
wire rstag_5to5_bb0_st_add_valid_out;
wire rstag_5to5_bb0_st_add_stall_in;
wire rstag_5to5_bb0_st_add_inputs_ready;
wire rstag_5to5_bb0_st_add_stall_local;
reg rstag_5to5_bb0_st_add_staging_valid_NO_SHIFT_REG;
wire rstag_5to5_bb0_st_add_combined_valid;
assign rstag_5to5_bb0_st_add_inputs_ready = local_bb0_st_add_valid_out_NO_SHIFT_REG;
assign rstag_5to5_bb0_st_add_combined_valid = (rstag_5to5_bb0_st_add_staging_valid_NO_SHIFT_REG | rstag_5to5_bb0_st_add_inputs_ready);
assign rstag_5to5_bb0_st_add_valid_out = rstag_5to5_bb0_st_add_combined_valid;
assign rstag_5to5_bb0_st_add_stall_local = rstag_5to5_bb0_st_add_stall_in;
assign local_bb0_st_add_stall_in = (|rstag_5to5_bb0_st_add_staging_valid_NO_SHIFT_REG);
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
rstag_5to5_bb0_st_add_staging_valid_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (rstag_5to5_bb0_st_add_stall_local)
begin
if (~(rstag_5to5_bb0_st_add_staging_valid_NO_SHIFT_REG))
begin
rstag_5to5_bb0_st_add_staging_valid_NO_SHIFT_REG <= rstag_5to5_bb0_st_add_inputs_ready;
end
end
else
begin
rstag_5to5_bb0_st_add_staging_valid_NO_SHIFT_REG <= 1'b0;
end
end
end
// This section describes the behaviour of the BRANCH node.
wire branch_var__inputs_ready;
wire branch_var__output_regs_ready;
assign branch_var__inputs_ready = rstag_5to5_bb0_st_add_valid_out;
assign branch_var__output_regs_ready = ~(stall_in);
assign rstag_5to5_bb0_st_add_stall_in = (~(branch_var__output_regs_ready) | ~(branch_var__inputs_ready));
assign valid_out = branch_var__inputs_ready;
endmodule
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
// altera message_off 10036
// altera message_off 10230
// altera message_off 10858
module vector_add_function
(
input clock,
input resetn,
input [31:0] input_global_id_0,
output stall_out,
input valid_in,
output valid_out,
input stall_in,
input [31:0] workgroup_size,
output avm_local_bb0_ld__enable,
input [255:0] avm_local_bb0_ld__readdata,
input avm_local_bb0_ld__readdatavalid,
input avm_local_bb0_ld__waitrequest,
output [29:0] avm_local_bb0_ld__address,
output avm_local_bb0_ld__read,
output avm_local_bb0_ld__write,
input avm_local_bb0_ld__writeack,
output [255:0] avm_local_bb0_ld__writedata,
output [31:0] avm_local_bb0_ld__byteenable,
output [4:0] avm_local_bb0_ld__burstcount,
output profile_lsu_local_bb0_ld__profile_bw_cntl,
output [31:0] profile_lsu_local_bb0_ld__profile_bw_incr,
output profile_lsu_local_bb0_ld__profile_total_ivalid_cntl,
output profile_lsu_local_bb0_ld__profile_avm_readwrite_count_cntl,
output profile_lsu_local_bb0_ld__profile_avm_burstcount_total_cntl,
output [31:0] profile_lsu_local_bb0_ld__profile_avm_burstcount_total_incr,
output profile_lsu_local_bb0_ld__profile_avm_stall_cntl,
output avm_local_bb0_ld__u0_enable,
input [255:0] avm_local_bb0_ld__u0_readdata,
input avm_local_bb0_ld__u0_readdatavalid,
input avm_local_bb0_ld__u0_waitrequest,
output [29:0] avm_local_bb0_ld__u0_address,
output avm_local_bb0_ld__u0_read,
output avm_local_bb0_ld__u0_write,
input avm_local_bb0_ld__u0_writeack,
output [255:0] avm_local_bb0_ld__u0_writedata,
output [31:0] avm_local_bb0_ld__u0_byteenable,
output [4:0] avm_local_bb0_ld__u0_burstcount,
output profile_lsu_local_bb0_ld__u0_profile_bw_cntl,
output [31:0] profile_lsu_local_bb0_ld__u0_profile_bw_incr,
output profile_lsu_local_bb0_ld__u0_profile_total_ivalid_cntl,
output profile_lsu_local_bb0_ld__u0_profile_avm_readwrite_count_cntl,
output profile_lsu_local_bb0_ld__u0_profile_avm_burstcount_total_cntl,
output [31:0] profile_lsu_local_bb0_ld__u0_profile_avm_burstcount_total_incr,
output profile_lsu_local_bb0_ld__u0_profile_avm_stall_cntl,
output avm_local_bb0_st_add_enable,
input [255:0] avm_local_bb0_st_add_readdata,
input avm_local_bb0_st_add_readdatavalid,
input avm_local_bb0_st_add_waitrequest,
output [29:0] avm_local_bb0_st_add_address,
output avm_local_bb0_st_add_read,
output avm_local_bb0_st_add_write,
input avm_local_bb0_st_add_writeack,
output [255:0] avm_local_bb0_st_add_writedata,
output [31:0] avm_local_bb0_st_add_byteenable,
output [4:0] avm_local_bb0_st_add_burstcount,
output profile_lsu_local_bb0_st_add_profile_bw_cntl,
output [31:0] profile_lsu_local_bb0_st_add_profile_bw_incr,
output profile_lsu_local_bb0_st_add_profile_total_ivalid_cntl,
output profile_lsu_local_bb0_st_add_profile_avm_readwrite_count_cntl,
output profile_lsu_local_bb0_st_add_profile_avm_burstcount_total_cntl,
output [31:0] profile_lsu_local_bb0_st_add_profile_avm_burstcount_total_incr,
output profile_lsu_local_bb0_st_add_profile_avm_stall_cntl,
input clock2x,
input start,
input [63:0] input_x,
input [31:0] input_global_size_0,
input [63:0] input_y,
input [63:0] input_z,
output profile_clock,
output reg has_a_write_pending,
output reg has_a_lsu_active
);
wire [31:0] cur_cycle;
wire bb_0_stall_out;
wire bb_0_valid_out;
wire bb_0_local_bb0_ld__active;
wire bb_0_local_bb0_ld__u0_active;
wire bb_0_local_bb0_st_add_active;
wire writes_pending;
wire [2:0] lsus_active;
vector_add_sys_cycle_time system_cycle_time_module (
.clock(clock),
.resetn(resetn),
.cur_cycle(cur_cycle)
);
vector_add_basic_block_0 vector_add_basic_block_0 (
.clock(clock),
.resetn(resetn),
.input_x(input_x),
.input_global_size_0(input_global_size_0),
.input_y(input_y),
.input_z(input_z),
.valid_in(valid_in),
.stall_out(bb_0_stall_out),
.input_global_id_0(input_global_id_0),
.valid_out(bb_0_valid_out),
.stall_in(stall_in),
.workgroup_size(workgroup_size),
.start(start),
.avm_local_bb0_ld__enable(avm_local_bb0_ld__enable),
.avm_local_bb0_ld__readdata(avm_local_bb0_ld__readdata),
.avm_local_bb0_ld__readdatavalid(avm_local_bb0_ld__readdatavalid),
.avm_local_bb0_ld__waitrequest(avm_local_bb0_ld__waitrequest),
.avm_local_bb0_ld__address(avm_local_bb0_ld__address),
.avm_local_bb0_ld__read(avm_local_bb0_ld__read),
.avm_local_bb0_ld__write(avm_local_bb0_ld__write),
.avm_local_bb0_ld__writeack(avm_local_bb0_ld__writeack),
.avm_local_bb0_ld__writedata(avm_local_bb0_ld__writedata),
.avm_local_bb0_ld__byteenable(avm_local_bb0_ld__byteenable),
.avm_local_bb0_ld__burstcount(avm_local_bb0_ld__burstcount),
.profile_lsu_local_bb0_ld__profile_bw_cntl(profile_lsu_local_bb0_ld__profile_bw_cntl),
.profile_lsu_local_bb0_ld__profile_bw_incr(profile_lsu_local_bb0_ld__profile_bw_incr),
.profile_lsu_local_bb0_ld__profile_total_ivalid_cntl(profile_lsu_local_bb0_ld__profile_total_ivalid_cntl),
.profile_lsu_local_bb0_ld__profile_avm_readwrite_count_cntl(profile_lsu_local_bb0_ld__profile_avm_readwrite_count_cntl),
.profile_lsu_local_bb0_ld__profile_avm_burstcount_total_cntl(profile_lsu_local_bb0_ld__profile_avm_burstcount_total_cntl),
.profile_lsu_local_bb0_ld__profile_avm_burstcount_total_incr(profile_lsu_local_bb0_ld__profile_avm_burstcount_total_incr),
.profile_lsu_local_bb0_ld__profile_avm_stall_cntl(profile_lsu_local_bb0_ld__profile_avm_stall_cntl),
.local_bb0_ld__active(bb_0_local_bb0_ld__active),
.clock2x(clock2x),
.avm_local_bb0_ld__u0_enable(avm_local_bb0_ld__u0_enable),
.avm_local_bb0_ld__u0_readdata(avm_local_bb0_ld__u0_readdata),
.avm_local_bb0_ld__u0_readdatavalid(avm_local_bb0_ld__u0_readdatavalid),
.avm_local_bb0_ld__u0_waitrequest(avm_local_bb0_ld__u0_waitrequest),
.avm_local_bb0_ld__u0_address(avm_local_bb0_ld__u0_address),
.avm_local_bb0_ld__u0_read(avm_local_bb0_ld__u0_read),
.avm_local_bb0_ld__u0_write(avm_local_bb0_ld__u0_write),
.avm_local_bb0_ld__u0_writeack(avm_local_bb0_ld__u0_writeack),
.avm_local_bb0_ld__u0_writedata(avm_local_bb0_ld__u0_writedata),
.avm_local_bb0_ld__u0_byteenable(avm_local_bb0_ld__u0_byteenable),
.avm_local_bb0_ld__u0_burstcount(avm_local_bb0_ld__u0_burstcount),
.profile_lsu_local_bb0_ld__u0_profile_bw_cntl(profile_lsu_local_bb0_ld__u0_profile_bw_cntl),
.profile_lsu_local_bb0_ld__u0_profile_bw_incr(profile_lsu_local_bb0_ld__u0_profile_bw_incr),
.profile_lsu_local_bb0_ld__u0_profile_total_ivalid_cntl(profile_lsu_local_bb0_ld__u0_profile_total_ivalid_cntl),
.profile_lsu_local_bb0_ld__u0_profile_avm_readwrite_count_cntl(profile_lsu_local_bb0_ld__u0_profile_avm_readwrite_count_cntl),
.profile_lsu_local_bb0_ld__u0_profile_avm_burstcount_total_cntl(profile_lsu_local_bb0_ld__u0_profile_avm_burstcount_total_cntl),
.profile_lsu_local_bb0_ld__u0_profile_avm_burstcount_total_incr(profile_lsu_local_bb0_ld__u0_profile_avm_burstcount_total_incr),
.profile_lsu_local_bb0_ld__u0_profile_avm_stall_cntl(profile_lsu_local_bb0_ld__u0_profile_avm_stall_cntl),
.local_bb0_ld__u0_active(bb_0_local_bb0_ld__u0_active),
.avm_local_bb0_st_add_enable(avm_local_bb0_st_add_enable),
.avm_local_bb0_st_add_readdata(avm_local_bb0_st_add_readdata),
.avm_local_bb0_st_add_readdatavalid(avm_local_bb0_st_add_readdatavalid),
.avm_local_bb0_st_add_waitrequest(avm_local_bb0_st_add_waitrequest),
.avm_local_bb0_st_add_address(avm_local_bb0_st_add_address),
.avm_local_bb0_st_add_read(avm_local_bb0_st_add_read),
.avm_local_bb0_st_add_write(avm_local_bb0_st_add_write),
.avm_local_bb0_st_add_writeack(avm_local_bb0_st_add_writeack),
.avm_local_bb0_st_add_writedata(avm_local_bb0_st_add_writedata),
.avm_local_bb0_st_add_byteenable(avm_local_bb0_st_add_byteenable),
.avm_local_bb0_st_add_burstcount(avm_local_bb0_st_add_burstcount),
.profile_lsu_local_bb0_st_add_profile_bw_cntl(profile_lsu_local_bb0_st_add_profile_bw_cntl),
.profile_lsu_local_bb0_st_add_profile_bw_incr(profile_lsu_local_bb0_st_add_profile_bw_incr),
.profile_lsu_local_bb0_st_add_profile_total_ivalid_cntl(profile_lsu_local_bb0_st_add_profile_total_ivalid_cntl),
.profile_lsu_local_bb0_st_add_profile_avm_readwrite_count_cntl(profile_lsu_local_bb0_st_add_profile_avm_readwrite_count_cntl),
.profile_lsu_local_bb0_st_add_profile_avm_burstcount_total_cntl(profile_lsu_local_bb0_st_add_profile_avm_burstcount_total_cntl),
.profile_lsu_local_bb0_st_add_profile_avm_burstcount_total_incr(profile_lsu_local_bb0_st_add_profile_avm_burstcount_total_incr),
.profile_lsu_local_bb0_st_add_profile_avm_stall_cntl(profile_lsu_local_bb0_st_add_profile_avm_stall_cntl),
.local_bb0_st_add_active(bb_0_local_bb0_st_add_active)
);
assign valid_out = bb_0_valid_out;
assign stall_out = bb_0_stall_out;
assign profile_clock = 1'b1;
assign writes_pending = bb_0_local_bb0_st_add_active;
assign lsus_active[0] = bb_0_local_bb0_ld__active;
assign lsus_active[1] = bb_0_local_bb0_ld__u0_active;
assign lsus_active[2] = bb_0_local_bb0_st_add_active;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
has_a_write_pending <= 1'b0;
has_a_lsu_active <= 1'b0;
end
else
begin
has_a_write_pending <= (|writes_pending);
has_a_lsu_active <= (|lsus_active);
end
end
endmodule
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
// altera message_off 10036
// altera message_off 10230
// altera message_off 10858
module vector_add_function_wrapper
(
input clock,
input resetn,
input clock2x,
input local_router_hang,
input profile_extmem_vector_add_function_bank0_port0_read_data_inc_en,
input profile_extmem_vector_add_function_bank0_port0_read_burst_count_en,
input profile_extmem_vector_add_function_bank0_port0_write_data_inc_en,
input profile_extmem_vector_add_function_bank0_port0_write_burst_count_en,
input avs_cra_enable,
input avs_cra_read,
input avs_cra_write,
input [3:0] avs_cra_address,
input [63:0] avs_cra_writedata,
input [7:0] avs_cra_byteenable,
output reg [63:0] avs_cra_readdata,
output reg avs_cra_readdatavalid,
output cra_irq,
output avm_local_bb0_ld__inst0_enable,
input [255:0] avm_local_bb0_ld__inst0_readdata,
input avm_local_bb0_ld__inst0_readdatavalid,
input avm_local_bb0_ld__inst0_waitrequest,
output [29:0] avm_local_bb0_ld__inst0_address,
output avm_local_bb0_ld__inst0_read,
output avm_local_bb0_ld__inst0_write,
input avm_local_bb0_ld__inst0_writeack,
output [255:0] avm_local_bb0_ld__inst0_writedata,
output [31:0] avm_local_bb0_ld__inst0_byteenable,
output [4:0] avm_local_bb0_ld__inst0_burstcount,
output avm_local_bb0_ld__u0_inst0_enable,
input [255:0] avm_local_bb0_ld__u0_inst0_readdata,
input avm_local_bb0_ld__u0_inst0_readdatavalid,
input avm_local_bb0_ld__u0_inst0_waitrequest,
output [29:0] avm_local_bb0_ld__u0_inst0_address,
output avm_local_bb0_ld__u0_inst0_read,
output avm_local_bb0_ld__u0_inst0_write,
input avm_local_bb0_ld__u0_inst0_writeack,
output [255:0] avm_local_bb0_ld__u0_inst0_writedata,
output [31:0] avm_local_bb0_ld__u0_inst0_byteenable,
output [4:0] avm_local_bb0_ld__u0_inst0_burstcount,
output avm_local_bb0_st_add_inst0_enable,
input [255:0] avm_local_bb0_st_add_inst0_readdata,
input avm_local_bb0_st_add_inst0_readdatavalid,
input avm_local_bb0_st_add_inst0_waitrequest,
output [29:0] avm_local_bb0_st_add_inst0_address,
output avm_local_bb0_st_add_inst0_read,
output avm_local_bb0_st_add_inst0_write,
input avm_local_bb0_st_add_inst0_writeack,
output [255:0] avm_local_bb0_st_add_inst0_writedata,
output [31:0] avm_local_bb0_st_add_inst0_byteenable,
output [4:0] avm_local_bb0_st_add_inst0_burstcount
);
// Responsible for interfacing a kernel with the outside world. It comprises a
// slave interface to specify the kernel arguments and retain kernel status.
// This section of the wrapper implements the slave interface.
// twoXclock_consumer uses clock2x, even if nobody inside the kernel does. Keeps interface to acl_iface consistent for all kernels.
reg start_NO_SHIFT_REG;
reg started_NO_SHIFT_REG;
wire finish;
reg [31:0] status_NO_SHIFT_REG;
wire has_a_write_pending;
wire has_a_lsu_active;
reg [191:0] kernel_arguments_NO_SHIFT_REG;
reg twoXclock_consumer_NO_SHIFT_REG /* synthesis preserve noprune */;
reg [31:0] workgroup_size_NO_SHIFT_REG;
reg [31:0] global_size_NO_SHIFT_REG[2:0];
reg [31:0] num_groups_NO_SHIFT_REG[2:0];
reg [31:0] local_size_NO_SHIFT_REG[2:0];
reg [31:0] work_dim_NO_SHIFT_REG;
reg [31:0] global_offset_NO_SHIFT_REG[2:0];
reg [63:0] profile_data_NO_SHIFT_REG;
reg [31:0] profile_ctrl_NO_SHIFT_REG;
reg [63:0] profile_start_cycle_NO_SHIFT_REG;
reg [63:0] profile_stop_cycle_NO_SHIFT_REG;
wire dispatched_all_groups;
wire [31:0] group_id_tmp[2:0];
wire [31:0] global_id_base_out[2:0];
wire start_out;
wire [31:0] local_id[0:0][2:0];
wire [31:0] global_id[0:0][2:0];
wire [31:0] group_id[0:0][2:0];
wire iter_valid_in;
wire iter_stall_out;
wire stall_in;
wire stall_out;
wire valid_in;
wire valid_out;
always @(posedge clock2x or negedge resetn)
begin
if (~(resetn))
begin
twoXclock_consumer_NO_SHIFT_REG <= 1'b0;
end
else
begin
twoXclock_consumer_NO_SHIFT_REG <= 1'b1;
end
end
// Profiling IP for various signals.
reg profile_reset_reg_NO_SHIFT_REG;
reg [63:0] profile_cycle_counter_NO_SHIFT_REG;
reg profile_cycle_count_in_range_reg_NO_SHIFT_REG;
wire [63:0] profile_data_wire;
wire profile_shift_wire;
wire profile_reset_n_wire;
wire profile_enable_wire;
wire [19:0] profile_increment_cntl;
wire [639:0] profile_increment_val;
acl_profiler profiler_inst (
.clock(clock),
.profile_shift(profile_shift_wire),
.incr_cntl(profile_increment_cntl),
.incr_val(profile_increment_val),
.daisy_out(profile_data_wire),
.resetn(profile_reset_n_wire),
.enable(profile_enable_wire)
);
defparam profiler_inst.COUNTER_WIDTH = 64;
defparam profiler_inst.INCREMENT_WIDTH = 32;
defparam profiler_inst.NUM_COUNTERS = 20;
defparam profiler_inst.DAISY_WIDTH = 64;
// Work group dispatcher is responsible for issuing work-groups to id iterator(s)
acl_work_group_dispatcher group_dispatcher (
.clock(clock),
.resetn(resetn),
.start(start_NO_SHIFT_REG),
.num_groups(num_groups_NO_SHIFT_REG),
.local_size(local_size_NO_SHIFT_REG),
.stall_in(iter_stall_out),
.valid_out(iter_valid_in),
.group_id_out(group_id_tmp),
.global_id_base_out(global_id_base_out),
.start_out(start_out),
.dispatched_all_groups(dispatched_all_groups)
);
defparam group_dispatcher.NUM_COPIES = 1;
defparam group_dispatcher.RUN_FOREVER = 0;
// This section of the wrapper implements an Avalon Slave Interface used to configure a kernel invocation.
// The few words words contain the status and the workgroup size registers.
// The remaining addressable space is reserved for kernel arguments.
reg [63:0] cra_readdata_st1_NO_SHIFT_REG;
reg [3:0] cra_addr_st1_NO_SHIFT_REG;
reg cra_read_st1_NO_SHIFT_REG;
wire [63:0] bitenable;
assign bitenable[7:0] = (avs_cra_byteenable[0] ? 8'hFF : 8'h0);
assign bitenable[15:8] = (avs_cra_byteenable[1] ? 8'hFF : 8'h0);
assign bitenable[23:16] = (avs_cra_byteenable[2] ? 8'hFF : 8'h0);
assign bitenable[31:24] = (avs_cra_byteenable[3] ? 8'hFF : 8'h0);
assign bitenable[39:32] = (avs_cra_byteenable[4] ? 8'hFF : 8'h0);
assign bitenable[47:40] = (avs_cra_byteenable[5] ? 8'hFF : 8'h0);
assign bitenable[55:48] = (avs_cra_byteenable[6] ? 8'hFF : 8'h0);
assign bitenable[63:56] = (avs_cra_byteenable[7] ? 8'hFF : 8'h0);
assign cra_irq = (status_NO_SHIFT_REG[1] | status_NO_SHIFT_REG[3]);
assign profile_enable_wire = (profile_cycle_count_in_range_reg_NO_SHIFT_REG & (started_NO_SHIFT_REG & profile_ctrl_NO_SHIFT_REG[2]));
assign profile_reset_n_wire = (resetn & ~(profile_reset_reg_NO_SHIFT_REG));
assign profile_shift_wire = profile_ctrl_NO_SHIFT_REG[0];
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
start_NO_SHIFT_REG <= 1'b0;
started_NO_SHIFT_REG <= 1'b0;
kernel_arguments_NO_SHIFT_REG <= 192'h0;
status_NO_SHIFT_REG <= 32'h30000;
profile_ctrl_NO_SHIFT_REG <= 32'h4;
profile_start_cycle_NO_SHIFT_REG <= 64'h0;
profile_stop_cycle_NO_SHIFT_REG <= 64'hFFFFFFFFFFFFFFFF;
work_dim_NO_SHIFT_REG <= 32'h0;
workgroup_size_NO_SHIFT_REG <= 32'h0;
global_size_NO_SHIFT_REG[0] <= 32'h0;
global_size_NO_SHIFT_REG[1] <= 32'h0;
global_size_NO_SHIFT_REG[2] <= 32'h0;
num_groups_NO_SHIFT_REG[0] <= 32'h0;
num_groups_NO_SHIFT_REG[1] <= 32'h0;
num_groups_NO_SHIFT_REG[2] <= 32'h0;
local_size_NO_SHIFT_REG[0] <= 32'h0;
local_size_NO_SHIFT_REG[1] <= 32'h0;
local_size_NO_SHIFT_REG[2] <= 32'h0;
global_offset_NO_SHIFT_REG[0] <= 32'h0;
global_offset_NO_SHIFT_REG[1] <= 32'h0;
global_offset_NO_SHIFT_REG[2] <= 32'h0;
profile_reset_reg_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (avs_cra_write)
begin
case (avs_cra_address)
4'h0:
begin
status_NO_SHIFT_REG[31:16] <= 16'h3;
status_NO_SHIFT_REG[15:0] <= ((status_NO_SHIFT_REG[15:0] & ~(bitenable[15:0])) | (avs_cra_writedata[15:0] & bitenable[15:0]));
end
4'h1:
begin
profile_ctrl_NO_SHIFT_REG <= ((profile_ctrl_NO_SHIFT_REG & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'h3:
begin
profile_start_cycle_NO_SHIFT_REG[31:0] <= ((profile_start_cycle_NO_SHIFT_REG[31:0] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
profile_start_cycle_NO_SHIFT_REG[63:32] <= ((profile_start_cycle_NO_SHIFT_REG[63:32] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'h4:
begin
profile_stop_cycle_NO_SHIFT_REG[31:0] <= ((profile_stop_cycle_NO_SHIFT_REG[31:0] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
profile_stop_cycle_NO_SHIFT_REG[63:32] <= ((profile_stop_cycle_NO_SHIFT_REG[63:32] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'h5:
begin
work_dim_NO_SHIFT_REG <= ((work_dim_NO_SHIFT_REG & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
workgroup_size_NO_SHIFT_REG <= ((workgroup_size_NO_SHIFT_REG & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'h6:
begin
global_size_NO_SHIFT_REG[0] <= ((global_size_NO_SHIFT_REG[0] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
global_size_NO_SHIFT_REG[1] <= ((global_size_NO_SHIFT_REG[1] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'h7:
begin
global_size_NO_SHIFT_REG[2] <= ((global_size_NO_SHIFT_REG[2] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
num_groups_NO_SHIFT_REG[0] <= ((num_groups_NO_SHIFT_REG[0] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'h8:
begin
num_groups_NO_SHIFT_REG[1] <= ((num_groups_NO_SHIFT_REG[1] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
num_groups_NO_SHIFT_REG[2] <= ((num_groups_NO_SHIFT_REG[2] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'h9:
begin
local_size_NO_SHIFT_REG[0] <= ((local_size_NO_SHIFT_REG[0] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
local_size_NO_SHIFT_REG[1] <= ((local_size_NO_SHIFT_REG[1] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'hA:
begin
local_size_NO_SHIFT_REG[2] <= ((local_size_NO_SHIFT_REG[2] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
global_offset_NO_SHIFT_REG[0] <= ((global_offset_NO_SHIFT_REG[0] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'hB:
begin
global_offset_NO_SHIFT_REG[1] <= ((global_offset_NO_SHIFT_REG[1] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
global_offset_NO_SHIFT_REG[2] <= ((global_offset_NO_SHIFT_REG[2] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'hC:
begin
kernel_arguments_NO_SHIFT_REG[31:0] <= ((kernel_arguments_NO_SHIFT_REG[31:0] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
kernel_arguments_NO_SHIFT_REG[63:32] <= ((kernel_arguments_NO_SHIFT_REG[63:32] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'hD:
begin
kernel_arguments_NO_SHIFT_REG[95:64] <= ((kernel_arguments_NO_SHIFT_REG[95:64] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
kernel_arguments_NO_SHIFT_REG[127:96] <= ((kernel_arguments_NO_SHIFT_REG[127:96] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'hE:
begin
kernel_arguments_NO_SHIFT_REG[159:128] <= ((kernel_arguments_NO_SHIFT_REG[159:128] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
kernel_arguments_NO_SHIFT_REG[191:160] <= ((kernel_arguments_NO_SHIFT_REG[191:160] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
default:
begin
end
endcase
end
else
begin
if (profile_ctrl_NO_SHIFT_REG[1])
begin
if (profile_reset_reg_NO_SHIFT_REG)
begin
profile_ctrl_NO_SHIFT_REG[1] <= 1'b0;
end
else
begin
profile_reset_reg_NO_SHIFT_REG <= 1'b1;
end
end
else
begin
profile_reset_reg_NO_SHIFT_REG <= 1'b0;
end
profile_ctrl_NO_SHIFT_REG[0] <= 1'b0;
if (status_NO_SHIFT_REG[0])
begin
start_NO_SHIFT_REG <= 1'b1;
end
if (start_NO_SHIFT_REG)
begin
status_NO_SHIFT_REG[0] <= 1'b0;
started_NO_SHIFT_REG <= 1'b1;
end
if (started_NO_SHIFT_REG)
begin
start_NO_SHIFT_REG <= 1'b0;
end
if (finish)
begin
status_NO_SHIFT_REG[1] <= 1'b1;
started_NO_SHIFT_REG <= 1'b0;
end
end
status_NO_SHIFT_REG[11] <= 1'b0;
status_NO_SHIFT_REG[12] <= (|has_a_lsu_active);
status_NO_SHIFT_REG[13] <= (|has_a_write_pending);
status_NO_SHIFT_REG[14] <= (|valid_in);
status_NO_SHIFT_REG[15] <= started_NO_SHIFT_REG;
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
cra_read_st1_NO_SHIFT_REG <= 1'b0;
cra_addr_st1_NO_SHIFT_REG <= 4'h0;
cra_readdata_st1_NO_SHIFT_REG <= 64'h0;
end
else
begin
cra_read_st1_NO_SHIFT_REG <= avs_cra_read;
cra_addr_st1_NO_SHIFT_REG <= avs_cra_address;
case (avs_cra_address)
4'h0:
begin
cra_readdata_st1_NO_SHIFT_REG[31:0] <= status_NO_SHIFT_REG;
cra_readdata_st1_NO_SHIFT_REG[63:32] <= 32'h0;
end
4'h1:
begin
cra_readdata_st1_NO_SHIFT_REG[31:0] <= 'x;
cra_readdata_st1_NO_SHIFT_REG[63:32] <= profile_ctrl_NO_SHIFT_REG;
end
4'h2:
begin
cra_readdata_st1_NO_SHIFT_REG[63:0] <= profile_data_NO_SHIFT_REG;
end
4'h3:
begin
cra_readdata_st1_NO_SHIFT_REG[63:0] <= profile_start_cycle_NO_SHIFT_REG;
end
4'h4:
begin
cra_readdata_st1_NO_SHIFT_REG[63:0] <= profile_stop_cycle_NO_SHIFT_REG;
end
default:
begin
cra_readdata_st1_NO_SHIFT_REG <= status_NO_SHIFT_REG;
end
endcase
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
avs_cra_readdatavalid <= 1'b0;
avs_cra_readdata <= 64'h0;
end
else
begin
avs_cra_readdatavalid <= cra_read_st1_NO_SHIFT_REG;
case (cra_addr_st1_NO_SHIFT_REG)
4'h2:
begin
avs_cra_readdata[63:0] <= profile_data_NO_SHIFT_REG;
end
default:
begin
avs_cra_readdata <= cra_readdata_st1_NO_SHIFT_REG;
end
endcase
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
profile_data_NO_SHIFT_REG <= 64'h0;
end
else
begin
if (profile_shift_wire)
begin
profile_data_NO_SHIFT_REG <= profile_data_wire;
end
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
profile_cycle_counter_NO_SHIFT_REG <= 64'h0;
end
else
begin
if (started_NO_SHIFT_REG)
begin
profile_cycle_counter_NO_SHIFT_REG <= (profile_cycle_counter_NO_SHIFT_REG + 64'h1);
end
else
begin
profile_cycle_counter_NO_SHIFT_REG <= 64'h0;
end
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
profile_cycle_count_in_range_reg_NO_SHIFT_REG <= 1'b0;
end
else
begin
profile_cycle_count_in_range_reg_NO_SHIFT_REG <= ((profile_cycle_counter_NO_SHIFT_REG >= profile_start_cycle_NO_SHIFT_REG) & (profile_cycle_counter_NO_SHIFT_REG < profile_stop_cycle_NO_SHIFT_REG));
end
end
// Handshaking signals used to control data through the pipeline
// Determine when the kernel is finished.
acl_kernel_finish_detector kernel_finish_detector (
.clock(clock),
.resetn(resetn),
.start(start_NO_SHIFT_REG),
.wg_size(workgroup_size_NO_SHIFT_REG),
.wg_dispatch_valid_out(iter_valid_in),
.wg_dispatch_stall_in(iter_stall_out),
.dispatched_all_groups(dispatched_all_groups),
.kernel_copy_valid_out(valid_out),
.kernel_copy_stall_in(stall_in),
.pending_writes(has_a_write_pending),
.finish(finish)
);
defparam kernel_finish_detector.TESSELLATION_SIZE = 0;
defparam kernel_finish_detector.NUM_COPIES = 1;
defparam kernel_finish_detector.WG_SIZE_W = 32;
assign stall_in = 1'b0;
// Creating ID iterator and kernel instance for every requested kernel copy
// ID iterator is responsible for iterating over all local ids for given work-groups
acl_id_iterator id_iter_inst0 (
.clock(clock),
.resetn(resetn),
.start(start_out),
.valid_in(iter_valid_in),
.stall_out(iter_stall_out),
.stall_in(stall_out),
.valid_out(valid_in),
.group_id_in(group_id_tmp),
.global_id_base_in(global_id_base_out),
.local_size(local_size_NO_SHIFT_REG),
.global_size(global_size_NO_SHIFT_REG),
.local_id(local_id[0]),
.global_id(global_id[0]),
.group_id(group_id[0])
);
defparam id_iter_inst0.LOCAL_WIDTH_X = 32;
defparam id_iter_inst0.LOCAL_WIDTH_Y = 32;
defparam id_iter_inst0.LOCAL_WIDTH_Z = 32;
// This section instantiates a kernel function block
wire profile_lsu_local_bb0_ld__profile_bw_cntl_inst0_wire_0;
wire [31:0] profile_lsu_local_bb0_ld__profile_bw_incr_inst0_wire_0;
wire profile_lsu_local_bb0_ld__profile_total_ivalid_cntl_inst0_wire_0;
wire profile_lsu_local_bb0_ld__profile_avm_readwrite_count_cntl_inst0_wire_0;
wire profile_lsu_local_bb0_ld__profile_avm_burstcount_total_cntl_inst0_wire_0;
wire [31:0] profile_lsu_local_bb0_ld__profile_avm_burstcount_total_incr_inst0_wire_0;
wire profile_lsu_local_bb0_ld__profile_avm_stall_cntl_inst0_wire_0;
wire profile_lsu_local_bb0_ld__u0_profile_bw_cntl_inst0_wire_0;
wire [31:0] profile_lsu_local_bb0_ld__u0_profile_bw_incr_inst0_wire_0;
wire profile_lsu_local_bb0_ld__u0_profile_total_ivalid_cntl_inst0_wire_0;
wire profile_lsu_local_bb0_ld__u0_profile_avm_readwrite_count_cntl_inst0_wire_0;
wire profile_lsu_local_bb0_ld__u0_profile_avm_burstcount_total_cntl_inst0_wire_0;
wire [31:0] profile_lsu_local_bb0_ld__u0_profile_avm_burstcount_total_incr_inst0_wire_0;
wire profile_lsu_local_bb0_ld__u0_profile_avm_stall_cntl_inst0_wire_0;
wire profile_lsu_local_bb0_st_add_profile_bw_cntl_inst0_wire_0;
wire [31:0] profile_lsu_local_bb0_st_add_profile_bw_incr_inst0_wire_0;
wire profile_lsu_local_bb0_st_add_profile_total_ivalid_cntl_inst0_wire_0;
wire profile_lsu_local_bb0_st_add_profile_avm_readwrite_count_cntl_inst0_wire_0;
wire profile_lsu_local_bb0_st_add_profile_avm_burstcount_total_cntl_inst0_wire_0;
wire [31:0] profile_lsu_local_bb0_st_add_profile_avm_burstcount_total_incr_inst0_wire_0;
wire profile_lsu_local_bb0_st_add_profile_avm_stall_cntl_inst0_wire_0;
wire profile_clock_inst0_wire_0;
vector_add_function vector_add_function_inst0 (
.clock(clock),
.resetn(resetn),
.input_global_id_0(global_id[0][0]),
.stall_out(stall_out),
.valid_in(valid_in),
.valid_out(valid_out),
.stall_in(stall_in),
.workgroup_size(workgroup_size_NO_SHIFT_REG),
.avm_local_bb0_ld__enable(avm_local_bb0_ld__inst0_enable),
.avm_local_bb0_ld__readdata(avm_local_bb0_ld__inst0_readdata),
.avm_local_bb0_ld__readdatavalid(avm_local_bb0_ld__inst0_readdatavalid),
.avm_local_bb0_ld__waitrequest(avm_local_bb0_ld__inst0_waitrequest),
.avm_local_bb0_ld__address(avm_local_bb0_ld__inst0_address),
.avm_local_bb0_ld__read(avm_local_bb0_ld__inst0_read),
.avm_local_bb0_ld__write(avm_local_bb0_ld__inst0_write),
.avm_local_bb0_ld__writeack(avm_local_bb0_ld__inst0_writeack),
.avm_local_bb0_ld__writedata(avm_local_bb0_ld__inst0_writedata),
.avm_local_bb0_ld__byteenable(avm_local_bb0_ld__inst0_byteenable),
.avm_local_bb0_ld__burstcount(avm_local_bb0_ld__inst0_burstcount),
.profile_lsu_local_bb0_ld__profile_bw_cntl(profile_lsu_local_bb0_ld__profile_bw_cntl_inst0_wire_0),
.profile_lsu_local_bb0_ld__profile_bw_incr(profile_lsu_local_bb0_ld__profile_bw_incr_inst0_wire_0),
.profile_lsu_local_bb0_ld__profile_total_ivalid_cntl(profile_lsu_local_bb0_ld__profile_total_ivalid_cntl_inst0_wire_0),
.profile_lsu_local_bb0_ld__profile_avm_readwrite_count_cntl(profile_lsu_local_bb0_ld__profile_avm_readwrite_count_cntl_inst0_wire_0),
.profile_lsu_local_bb0_ld__profile_avm_burstcount_total_cntl(profile_lsu_local_bb0_ld__profile_avm_burstcount_total_cntl_inst0_wire_0),
.profile_lsu_local_bb0_ld__profile_avm_burstcount_total_incr(profile_lsu_local_bb0_ld__profile_avm_burstcount_total_incr_inst0_wire_0),
.profile_lsu_local_bb0_ld__profile_avm_stall_cntl(profile_lsu_local_bb0_ld__profile_avm_stall_cntl_inst0_wire_0),
.avm_local_bb0_ld__u0_enable(avm_local_bb0_ld__u0_inst0_enable),
.avm_local_bb0_ld__u0_readdata(avm_local_bb0_ld__u0_inst0_readdata),
.avm_local_bb0_ld__u0_readdatavalid(avm_local_bb0_ld__u0_inst0_readdatavalid),
.avm_local_bb0_ld__u0_waitrequest(avm_local_bb0_ld__u0_inst0_waitrequest),
.avm_local_bb0_ld__u0_address(avm_local_bb0_ld__u0_inst0_address),
.avm_local_bb0_ld__u0_read(avm_local_bb0_ld__u0_inst0_read),
.avm_local_bb0_ld__u0_write(avm_local_bb0_ld__u0_inst0_write),
.avm_local_bb0_ld__u0_writeack(avm_local_bb0_ld__u0_inst0_writeack),
.avm_local_bb0_ld__u0_writedata(avm_local_bb0_ld__u0_inst0_writedata),
.avm_local_bb0_ld__u0_byteenable(avm_local_bb0_ld__u0_inst0_byteenable),
.avm_local_bb0_ld__u0_burstcount(avm_local_bb0_ld__u0_inst0_burstcount),
.profile_lsu_local_bb0_ld__u0_profile_bw_cntl(profile_lsu_local_bb0_ld__u0_profile_bw_cntl_inst0_wire_0),
.profile_lsu_local_bb0_ld__u0_profile_bw_incr(profile_lsu_local_bb0_ld__u0_profile_bw_incr_inst0_wire_0),
.profile_lsu_local_bb0_ld__u0_profile_total_ivalid_cntl(profile_lsu_local_bb0_ld__u0_profile_total_ivalid_cntl_inst0_wire_0),
.profile_lsu_local_bb0_ld__u0_profile_avm_readwrite_count_cntl(profile_lsu_local_bb0_ld__u0_profile_avm_readwrite_count_cntl_inst0_wire_0),
.profile_lsu_local_bb0_ld__u0_profile_avm_burstcount_total_cntl(profile_lsu_local_bb0_ld__u0_profile_avm_burstcount_total_cntl_inst0_wire_0),
.profile_lsu_local_bb0_ld__u0_profile_avm_burstcount_total_incr(profile_lsu_local_bb0_ld__u0_profile_avm_burstcount_total_incr_inst0_wire_0),
.profile_lsu_local_bb0_ld__u0_profile_avm_stall_cntl(profile_lsu_local_bb0_ld__u0_profile_avm_stall_cntl_inst0_wire_0),
.avm_local_bb0_st_add_enable(avm_local_bb0_st_add_inst0_enable),
.avm_local_bb0_st_add_readdata(avm_local_bb0_st_add_inst0_readdata),
.avm_local_bb0_st_add_readdatavalid(avm_local_bb0_st_add_inst0_readdatavalid),
.avm_local_bb0_st_add_waitrequest(avm_local_bb0_st_add_inst0_waitrequest),
.avm_local_bb0_st_add_address(avm_local_bb0_st_add_inst0_address),
.avm_local_bb0_st_add_read(avm_local_bb0_st_add_inst0_read),
.avm_local_bb0_st_add_write(avm_local_bb0_st_add_inst0_write),
.avm_local_bb0_st_add_writeack(avm_local_bb0_st_add_inst0_writeack),
.avm_local_bb0_st_add_writedata(avm_local_bb0_st_add_inst0_writedata),
.avm_local_bb0_st_add_byteenable(avm_local_bb0_st_add_inst0_byteenable),
.avm_local_bb0_st_add_burstcount(avm_local_bb0_st_add_inst0_burstcount),
.profile_lsu_local_bb0_st_add_profile_bw_cntl(profile_lsu_local_bb0_st_add_profile_bw_cntl_inst0_wire_0),
.profile_lsu_local_bb0_st_add_profile_bw_incr(profile_lsu_local_bb0_st_add_profile_bw_incr_inst0_wire_0),
.profile_lsu_local_bb0_st_add_profile_total_ivalid_cntl(profile_lsu_local_bb0_st_add_profile_total_ivalid_cntl_inst0_wire_0),
.profile_lsu_local_bb0_st_add_profile_avm_readwrite_count_cntl(profile_lsu_local_bb0_st_add_profile_avm_readwrite_count_cntl_inst0_wire_0),
.profile_lsu_local_bb0_st_add_profile_avm_burstcount_total_cntl(profile_lsu_local_bb0_st_add_profile_avm_burstcount_total_cntl_inst0_wire_0),
.profile_lsu_local_bb0_st_add_profile_avm_burstcount_total_incr(profile_lsu_local_bb0_st_add_profile_avm_burstcount_total_incr_inst0_wire_0),
.profile_lsu_local_bb0_st_add_profile_avm_stall_cntl(profile_lsu_local_bb0_st_add_profile_avm_stall_cntl_inst0_wire_0),
.clock2x(clock2x),
.start(start_out),
.input_x(kernel_arguments_NO_SHIFT_REG[63:0]),
.input_global_size_0(global_size_NO_SHIFT_REG[0]),
.input_y(kernel_arguments_NO_SHIFT_REG[127:64]),
.input_z(kernel_arguments_NO_SHIFT_REG[191:128]),
.profile_clock(profile_clock_inst0_wire_0),
.has_a_write_pending(has_a_write_pending),
.has_a_lsu_active(has_a_lsu_active)
);
assign profile_increment_cntl[0] = profile_lsu_local_bb0_ld__profile_bw_cntl_inst0_wire_0;
assign profile_increment_val[31:0] = profile_lsu_local_bb0_ld__profile_bw_incr_inst0_wire_0;
assign profile_increment_cntl[1] = profile_lsu_local_bb0_ld__profile_total_ivalid_cntl_inst0_wire_0;
assign profile_increment_val[63:32] = 32'h1;
assign profile_increment_cntl[2] = profile_lsu_local_bb0_ld__profile_avm_readwrite_count_cntl_inst0_wire_0;
assign profile_increment_val[95:64] = 32'h1;
assign profile_increment_cntl[3] = profile_lsu_local_bb0_ld__profile_avm_burstcount_total_cntl_inst0_wire_0;
assign profile_increment_val[127:96] = profile_lsu_local_bb0_ld__profile_avm_burstcount_total_incr_inst0_wire_0;
assign profile_increment_cntl[4] = profile_lsu_local_bb0_ld__profile_avm_stall_cntl_inst0_wire_0;
assign profile_increment_val[159:128] = 32'h1;
assign profile_increment_cntl[5] = profile_lsu_local_bb0_ld__u0_profile_bw_cntl_inst0_wire_0;
assign profile_increment_val[191:160] = profile_lsu_local_bb0_ld__u0_profile_bw_incr_inst0_wire_0;
assign profile_increment_cntl[6] = profile_lsu_local_bb0_ld__u0_profile_total_ivalid_cntl_inst0_wire_0;
assign profile_increment_val[223:192] = 32'h1;
assign profile_increment_cntl[7] = profile_lsu_local_bb0_ld__u0_profile_avm_readwrite_count_cntl_inst0_wire_0;
assign profile_increment_val[255:224] = 32'h1;
assign profile_increment_cntl[8] = profile_lsu_local_bb0_ld__u0_profile_avm_burstcount_total_cntl_inst0_wire_0;
assign profile_increment_val[287:256] = profile_lsu_local_bb0_ld__u0_profile_avm_burstcount_total_incr_inst0_wire_0;
assign profile_increment_cntl[9] = profile_lsu_local_bb0_ld__u0_profile_avm_stall_cntl_inst0_wire_0;
assign profile_increment_val[319:288] = 32'h1;
assign profile_increment_cntl[10] = profile_lsu_local_bb0_st_add_profile_bw_cntl_inst0_wire_0;
assign profile_increment_val[351:320] = profile_lsu_local_bb0_st_add_profile_bw_incr_inst0_wire_0;
assign profile_increment_cntl[11] = profile_lsu_local_bb0_st_add_profile_total_ivalid_cntl_inst0_wire_0;
assign profile_increment_val[383:352] = 32'h1;
assign profile_increment_cntl[12] = profile_lsu_local_bb0_st_add_profile_avm_readwrite_count_cntl_inst0_wire_0;
assign profile_increment_val[415:384] = 32'h1;
assign profile_increment_cntl[13] = profile_lsu_local_bb0_st_add_profile_avm_burstcount_total_cntl_inst0_wire_0;
assign profile_increment_val[447:416] = profile_lsu_local_bb0_st_add_profile_avm_burstcount_total_incr_inst0_wire_0;
assign profile_increment_cntl[14] = profile_lsu_local_bb0_st_add_profile_avm_stall_cntl_inst0_wire_0;
assign profile_increment_val[479:448] = 32'h1;
assign profile_increment_cntl[15] = profile_clock_inst0_wire_0;
assign profile_increment_val[511:480] = 32'h1;
assign profile_increment_cntl[16] = profile_extmem_vector_add_function_bank0_port0_read_data_inc_en;
assign profile_increment_val[543:512] = 32'h1;
assign profile_increment_cntl[17] = profile_extmem_vector_add_function_bank0_port0_read_burst_count_en;
assign profile_increment_val[575:544] = 32'h1;
assign profile_increment_cntl[18] = profile_extmem_vector_add_function_bank0_port0_write_data_inc_en;
assign profile_increment_val[607:576] = 32'h1;
assign profile_increment_cntl[19] = profile_extmem_vector_add_function_bank0_port0_write_burst_count_en;
assign profile_increment_val[639:608] = 32'h1;
endmodule
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
// altera message_off 10036
// altera message_off 10230
// altera message_off 10858
module vector_add_sys_cycle_time
(
input clock,
input resetn,
output [31:0] cur_cycle
);
reg [31:0] cur_count_NO_SHIFT_REG;
assign cur_cycle = cur_count_NO_SHIFT_REG;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
cur_count_NO_SHIFT_REG <= 32'h0;
end
else
begin
cur_count_NO_SHIFT_REG <= (cur_count_NO_SHIFT_REG + 32'h1);
end
end
endmodule
|
`timescale 1ns/1ps
module SPIFSM #(
parameter SPPRWidth = 4,
parameter SPRWidth = 4,
parameter DataWidth = 8
) (
input Reset_n_i,
input Clk_i,
// FSM control
input Start_i,
output reg Done_o,
output reg [DataWidth-1:0] Byte0_o,
output reg [DataWidth-1:0] Byte1_o,
// to/from SPI_Master
input SPI_Transmission_i,
output reg SPI_Write_o,
output reg SPI_ReadNext_o,
output reg [DataWidth-1:0] SPI_Data_o,
input [DataWidth-1:0] SPI_Data_i,
input SPI_FIFOFull_i,
input SPI_FIFOEmpty_i,
// to ADT7310
output reg ADT7310CS_n_o,
// parameters
input [15:0] ParamCounterPreset_i
);
// SPI FSM
localparam stIdle = 4'b0000;
localparam stWriteValue = 4'b0001;
localparam stWaitSent = 4'b0010;
localparam stConsume1 = 4'b0011;
localparam stWait = 4'b0100;
localparam stWriteDummy1= 4'b0101;
localparam stWriteDummy2= 4'b0110;
localparam stRead1 = 4'b0111;
localparam stRead2 = 4'b1000;
localparam stRead3 = 4'b1001;
localparam stPause = 4'b1010;
reg [3:0] SPI_FSM_State;
reg [3:0] SPI_FSM_NextState;
wire SPI_FSM_TimerOvfl;
reg SPI_FSM_TimerPreset;
reg SPI_FSM_TimerEnable;
reg SPI_FSM_Wr1;
reg SPI_FSM_Wr0;
/////////////////////////////////////////////////////////////////////////////
// FSM //////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SPI_FSM_State <= stIdle;
end
else
begin
SPI_FSM_State <= SPI_FSM_NextState;
end
end
always @(SPI_FSM_State, Start_i, SPI_Transmission_i, SPI_FSM_TimerOvfl)
begin // process SPI_FSM_CombProc
SPI_FSM_NextState = SPI_FSM_State;
// control signal default values
ADT7310CS_n_o = 1'b1;
SPI_Data_o = 8'bxxxxxxxx; // most time we don't care which value is set
SPI_Write_o = 1'b0;
SPI_ReadNext_o = 1'b0;
SPI_FSM_TimerPreset = 1'b1;
SPI_FSM_TimerEnable = 1'b0;
SPI_FSM_Wr1 = 1'b0;
SPI_FSM_Wr0 = 1'b0;
Done_o = 1'b1;
// next state and output logic
case (SPI_FSM_State)
stIdle: begin
if (Start_i == 1'b1)
begin
// single-shot measurement mode: write to 8-bit configuration
// register (0x01): send 0x08 0x20 (one shot mode)
SPI_FSM_NextState = stWriteValue;
ADT7310CS_n_o = 1'b0;
SPI_Data_o = 8'h08;
SPI_Write_o = 1'b1;
Done_o = 1'b0;
end
end
stWriteValue: begin
SPI_FSM_NextState = stWaitSent;
ADT7310CS_n_o = 1'b0;
// send 0x20
SPI_Data_o = 8'h20;
SPI_Write_o = 1'b1;
Done_o = 1'b0;
end
stWaitSent: begin
// wait until SPI transmission has finished
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
if (SPI_Transmission_i == 1'b0)
begin
SPI_FSM_NextState = stConsume1;
SPI_ReadNext_o = 1'b1; // consume first received value
end
end
stConsume1: begin
SPI_FSM_NextState = stWait;
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
SPI_ReadNext_o = 1'b1; // consume second received value
SPI_FSM_TimerPreset = 1'b0;
SPI_FSM_TimerEnable = 1'b1; // start timer
end
stWait: begin
// wait for 240ms
ADT7310CS_n_o = 1'b1;
Done_o = 1'b0;
if (SPI_FSM_TimerOvfl == 1'b0)
begin
SPI_FSM_TimerPreset = 1'b0;
SPI_FSM_TimerEnable = 1'b1; // timer running
end
else
begin
// timer overflow -> continue: send read command and two dummy bytes
ADT7310CS_n_o = 1'b0;
SPI_FSM_NextState = stWriteDummy1;
SPI_Data_o = 8'h50;
SPI_Write_o = 1'b1;
end
end
stWriteDummy1: begin
SPI_FSM_NextState = stWriteDummy2;
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
SPI_Data_o = 8'hFF;
SPI_Write_o = 1'b1;
end
stWriteDummy2: begin
SPI_FSM_NextState = stRead1;
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
SPI_Data_o = 8'hFF;
SPI_Write_o = 1'b1;
end
stRead1: begin
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
// wait until SPI transmission has finished
if (SPI_Transmission_i == 1'b0) begin
SPI_FSM_NextState = stRead2;
// consume and ignore first byte
SPI_ReadNext_o = 1'b1;
end
end
stRead2: begin
Done_o = 1'b0;
// consume and store second byte
SPI_ReadNext_o = 1'b1;
SPI_FSM_Wr1 = 1'b1;
SPI_FSM_NextState = stRead3;
end
stRead3: begin
Done_o = 1'b0;
// consume and store third byte
SPI_ReadNext_o = 1'b1;
SPI_FSM_Wr0 = 1'b1;
SPI_FSM_NextState = stPause;
end
stPause: begin
SPI_FSM_NextState = stIdle;
end
default: begin
end
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Byte-wide Memory /////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Byte0_o <= 8'd0;
Byte1_o <= 8'd0;
end
else
begin
if (SPI_FSM_Wr0)
begin
Byte0_o <= SPI_Data_i;
end
if (SPI_FSM_Wr1)
begin
Byte1_o <= SPI_Data_i;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic //////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
reg [15:0] SPI_FSM_Timer;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SPI_FSM_Timer <= 16'd0;
end
else
begin
if (SPI_FSM_TimerPreset)
begin
SPI_FSM_Timer <= ParamCounterPreset_i;
end
else if (SPI_FSM_TimerEnable)
begin
SPI_FSM_Timer <= SPI_FSM_Timer - 1'b1;
end
end
end
assign SPI_FSM_TimerOvfl = (SPI_FSM_Timer == 0) ? 1'b1 : 1'b0;
endmodule // SPIFSM
|
//ÊýÂë¹Ü¼Æ·ÖÄ£¿é
module Seg_Display
(
input clk,
input rst,
input add_cube,
inout [1:0]game_status,
output reg[15:0]point,
output reg[7:0]seg_out,
output reg[3:0]sel
);
localparam RESTART = 2'b00;
reg[31:0]clk_cnt;
always@(posedge clk or posedge rst)
begin
if(!rst)
begin
seg_out <= 0;
clk_cnt <= 0;
sel <= 0;
end
else if (game_status == RESTART) begin
seg_out <= 0;
clk_cnt <= 0;
sel <= 0;
end
else
begin
if(clk_cnt <= 20_0000)
begin
clk_cnt <= clk_cnt+1;
if(clk_cnt == 5_0000)
begin
sel <= 4'b0111;
case(point[3:0])
4'b0000:seg_out <= 8'b1100_0000;
4'b0001:seg_out <= 8'b1111_1001;
4'b0010:seg_out <= 8'b1010_0100;
4'b0011:seg_out <= 8'b1011_0000;
4'b0100:seg_out <= 8'b1001_1001;
4'b0101:seg_out <= 8'b1001_0010;
4'b0110:seg_out <= 8'b1000_0010;
4'b0111:seg_out <= 8'b1111_1000;
4'b1000:seg_out <= 8'b1000_0000;
4'b1001:seg_out <= 8'b1001_0000;
default;
endcase
end
else if(clk_cnt == 10_0000)
begin
sel <= 4'b1011;
case(point[7:4])
4'b0000:seg_out <= 8'b1100_0000;
4'b0001:seg_out <= 8'b1111_1001;
4'b0010:seg_out <= 8'b1010_0100;
4'b0011:seg_out <= 8'b1011_0000;
4'b0100:seg_out <= 8'b1001_1001;
4'b0101:seg_out <= 8'b1001_0010;
4'b0110:seg_out <= 8'b1000_0010;
4'b0111:seg_out <= 8'b1111_1000;
4'b1000:seg_out <= 8'b1000_0000;
4'b1001:seg_out <= 8'b1001_0000;
default;
endcase
end
else if(clk_cnt == 15_0000)
begin
sel <= 4'b1101;
case(point[11:8])
4'b0000:seg_out <= 8'b1100_0000;
4'b0001:seg_out <= 8'b1111_1001;
4'b0010:seg_out <= 8'b1010_0100;
4'b0011:seg_out <= 8'b1011_0000;
4'b0100:seg_out <= 8'b1001_1001;
4'b0101:seg_out <= 8'b1001_0010;
4'b0110:seg_out <= 8'b1000_0010;
4'b0111:seg_out <= 8'b1111_1000;
4'b1000:seg_out <= 8'b1000_0000;
4'b1001:seg_out <= 8'b1001_0000;
default;
endcase
end
else if(clk_cnt == 20_0000)
begin
sel <= 4'b1110;
case(point[15:12])
4'b0000:seg_out <= 8'b1100_0000;
4'b0001:seg_out <= 8'b1111_1001;
4'b0010:seg_out <= 8'b1010_0100;
4'b0011:seg_out <= 8'b1011_0000;
4'b0100:seg_out <= 8'b1001_1001;
4'b0101:seg_out <= 8'b1001_0010;
4'b0110:seg_out <= 8'b1000_0010;
4'b0111:seg_out <= 8'b1111_1000;
4'b1000:seg_out <= 8'b1000_0000;
4'b1001:seg_out <= 8'b1001_0000;
default;
endcase
end
end
else
clk_cnt <= 0;
end
end
reg addcube_state;
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
point <= 0;
addcube_state <= 0;
end
else if (game_status == RESTART) begin
point <= 0;
addcube_state <= 0;
end
else begin
case(addcube_state)
0: begin
if(add_cube) begin
if(point[3:0] < 9)
point[3:0] <= point[3:0] + 1;
else begin
point[3:0] <= 0;
if(point[7:4] < 9)
point[7:4] <= point[7:4] + 1;
else begin
point[7:4] <= 0;
if(point[11:8] < 9)
point[11:8] <= point[11:8] + 1;
else begin
point[11:8] <= 0;
point[15:12] <= point[15:12] + 1;
end
end
end
addcube_state <= 1;
end
end
1: begin
if(!add_cube)
addcube_state <= 0;
end
endcase
end
end
endmodule |
module x;
always @(/*AUTOSENSE*/arb_select_f or octet_idx) begin
octet_flag[0] = |arb_select_f[ 7: 0];
octet_flag[1] = |arb_select_f[15: 8];
octet_flag[2] = |arb_select_f[23:16];
octet_flag[3] = |arb_select_f[31:24];
octet_flag[4] = |arb_select_f[39:32];
octet_flag[5] = |arb_select_f[47:40];
octet_flag[6] = |arb_select_f[55:48];
octet_flag[7] = |arb_select_f[63:56];
octet_available = |octet_flag;
shifted8_64 = barrel_shifter(octet_flag, octet_idx[5:3]);
end // always @ (arb_select_f)
endmodule
function [7:0] barrel_shifter;
input [7:0] source;
input [2:0] shift_amt;
begin
case (shift_amt) //synopsys parallel_case full_case
3'b0: barrel_shifter = source;
3'b1: barrel_shifter = {source[0], source[7:1]};
3'b2: barrel_shifter = {source[1:0], source[7:2]};
3'b3: barrel_shifter = {source[2:0], source[7:3]};
3'b4: barrel_shifter = {source[3:0], source[7:4]};
3'b5: barrel_shifter = {source[4:0], source[7:5]};
3'b6: barrel_shifter = {source[5:0], source[7:6]};
3'b7: barrel_shifter = {source[6:0], source[7]};
endcase // case(shift_amt)
end
endfunction // barrel_shifter
|
// A Data Channel
`include "globalVariable.v"
module dataChannel (clk, reset, inPort, counterGolden, injectGrant,winningFlitPortTag, winningFlitValid, inRouterFlitLocal,inner_wire_in1, inner_wire_in2,swap1, swap2, inner_wire_out1, inner_wire_out2,outPort);
input clk, reset;
input [`CHANNEL_SIZE-1:0] inPort;
input [`COORDINATE_SIZE+`PKTID_SIZE-1:0] counterGolden;
input [`PORT_TAG_SIZE-1:0] winningFlitPortTag;
input winningFlitValid, injectGrant, swap1, swap2;
input [`IN_ROUTER_SIZE-1:0] inRouterFlitLocal;
input [`IN_ROUTER_SIZE-1:0] inner_wire_in1, inner_wire_in2;
output [`IN_ROUTER_SIZE-1:0] inner_wire_out1, inner_wire_out2;
output reg [`CHANNEL_SIZE-1:0] outPort;
reg [`CHANNEL_SIZE-1:0] inputLatch;
always @ (posedge clk or negedge reset) begin
if (~reset) begin
inputLatch<= 0;
end
else begin
inputLatch <= inPort;
end
end
wire [`COORDINATE_SIZE-1:0] CURRENT_POSITION = {`CURRENT_POSITION_X,`CURRENT_POSITION_Y};
wire [`IN_ROUTER_SIZE-1:0] inRouterFlit;
routerComputation RC (
.flit (inputLatch),
.CURRENT_POSITION (CURRENT_POSITION),
.counterGolden (counterGolden),
.PORT_INDEX (3'd0), // use East port as an example
.inRouterFlit (inRouterFlit)
);
wire valid;
ejectKill ejectKill(
.portIndex (inRouterFlit[`PORT_TAG]),
.winnerPort (winningFlitPortTag),
.validIn (inRouterFlit[`VALID]),
.winnerValid (winningFlitValid),
.validOut (valid) // check if there is any racing
);
wire [`IN_ROUTER_SIZE-1:0] inj2PipelineLatch;
reg [`IN_ROUTER_SIZE-1:0] pipelineLatch;
mux2to1InRouter Inject (
.aIn ({valid,inRouterFlit[`IN_ROUTER_SIZE-2:0]}),
.bIn (inRouterFlitLocal),
.sel (injectGrant),
.dataOut (inj2PipelineLatch)
);
always @ (posedge clk or negedge reset) begin
if (~reset) begin
pipelineLatch <= 0;
end
else begin
pipelineLatch <= inj2PipelineLatch;
end
end
wire [`IN_ROUTER_SIZE-1:0] straightFlit [1:0];
wire [`IN_ROUTER_SIZE-1:0] interStageFlit;
wire [`IN_ROUTER_SIZE-1:0] w_outPort;
demux1to2InRouter demux0(
.dataIn (pipelineLatch),
.sel (swap1),
.aOut (straightFlit[0]),
.bOut (inner_wire_out1)
);
mux2to1InRouter mux0(
.aIn (straightFlit[0]),
.bIn (inner_wire_in1),
.sel (swap1),
.dataOut (interStageFlit)
);
demux1to2InRouter demux1(
.dataIn (interStageFlit),
.sel (swap2),
.aOut (straightFlit[1]),
.bOut (inner_wire_out2)
);
mux2to1InRouter mux1(
.aIn (straightFlit[1]),
.bIn (inner_wire_in2),
.sel (swap2),
.dataOut (w_outPort)
);
always @ (posedge clk or negedge reset) begin
if (~reset) begin
outPort <= 0;
end
else begin
outPort <= w_outPort[`CHANNEL_SIZE-1:0];
end
end
endmodule |