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// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Reduced Normalization module
//
// This module performs realignment of data such that the most significant
// bit is 1 for any number with exponent >= 1, and zero otherwise.
//
module acl_fp_custom_reduced_normalize(
clock, resetn,
mantissa, exponent, sign,
// Used in HIGH_CAPACITY = 1 mode
stall_in, valid_in, stall_out, valid_out,
// Used in HIGH_CAPACITY = 0 mode
enable,
mantissa_out, exponent_out, sign_out);
parameter HIGH_CAPACITY = 1;
parameter FLUSH_DENORMS = 0;
parameter HIGH_LATENCY = 1;
parameter REMOVE_STICKY = 1;
parameter FINITE_MATH_ONLY = 1;
input clock, resetn;
input stall_in, valid_in;
output stall_out, valid_out;
input enable;
// Data in
input [27:0] mantissa;
input [8:0] exponent; // Exponent with MSB set to 1 is an exception.
input sign;
// Data output
output [26:0] mantissa_out; // When mantissa_out[25] = 1 and exponent_out[8] == 1 then the number is NaN.
output [8:0] exponent_out; // Exponent with MSB set to 1 is an exception.
output sign_out;
// Stall/valid and enable signals on per-stage basis.
reg c1_valid;
reg c2_valid;
reg c3_valid;
reg c4_valid;
wire c1_stall;
wire c2_stall;
wire c3_stall;
wire c4_stall;
wire c1_enable;
wire c2_enable;
wire c3_enable;
wire c4_enable;
// Cycle 1 - We are just doing the shifting here.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [27:0] c1_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [8:0] c1_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [4:0] c1_max_shift;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_sign;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_exponent_is_max;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_exponent_is_nonzero;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [5:0] c1_mantissa_nonzero;
assign c1_enable = (HIGH_CAPACITY == 1) ? (~c1_valid | ~c1_stall) : enable;
assign stall_out = c1_valid & c1_stall;
generate
if (FINITE_MATH_ONLY == 1)
begin
always@(*)
begin
c1_valid <= valid_in;
c1_sign <= sign;
c1_exponent <= exponent;
c1_exponent_is_max <= (&exponent[7:1]) & ~exponent[0];
c1_exponent_is_nonzero <= |exponent[7:0];
c1_mantissa_nonzero <= {|mantissa[26:23], |mantissa[22:19], |mantissa[18:15], |mantissa[14:11], |mantissa[10:7], |mantissa[6:3]};
c1_mantissa <= mantissa;
c1_max_shift <= exponent[8] ? 5'd0 : ({5{|exponent[7:5]}} | {exponent[4:0] - 1'b1});
end
end
else
begin
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c1_mantissa <= 28'dx;
c1_exponent <= 9'dx;
c1_sign <= 1'bx;
c1_exponent_is_max <= 1'bx;
c1_exponent_is_nonzero <= 1'bx;
c1_mantissa_nonzero <= 6'dx;
c1_max_shift <= 5'dx;
c1_valid <= 1'b0;
end
else if (c1_enable)
begin
c1_valid <= valid_in;
c1_sign <= sign;
c1_exponent <= exponent;
c1_exponent_is_max <= (&exponent[7:1]) & ~exponent[0];
c1_exponent_is_nonzero <= |exponent[7:0];
c1_mantissa_nonzero <= {|mantissa[26:23], |mantissa[22:19], |mantissa[18:15], |mantissa[14:11], |mantissa[10:7], |mantissa[6:3]};
if ((FINITE_MATH_ONLY == 0) && ((exponent == 9'h0fe) && mantissa[27]))
c1_mantissa <= 28'h8000000;
else
c1_mantissa <= mantissa;
c1_max_shift <= exponent[8] ? 5'd0 : ({5{|exponent[7:5]}} | {exponent[4:0] - 1'b1});
end
end
end
endgenerate
// Cycle 2 - Shift by 16, 0 or -1.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [26:0] c2_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [8:0] c2_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c2_sign;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [3:0] c2_max_shift;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [2:0] c2_mantissa_nonzero;
assign c2_enable = (HIGH_CAPACITY == 1) ? (~c2_valid | ~c2_stall) : enable;
assign c1_stall = c2_valid & c2_stall;
reg [1:0] c2_select;
reg [8:0] c2_exponent_adjust;
always@(*)
begin
if (c1_mantissa[27])
begin
c2_select = 2'b11;
c2_exponent_adjust = {7'd0, ~c1_exponent_is_nonzero, c1_exponent_is_nonzero}; // +1/+2
end
else if (~(|c1_mantissa_nonzero[5:2]) && (c1_max_shift[4]) && c1_exponent_is_nonzero)
begin
c2_select = 2'b10;
c2_exponent_adjust = 9'b111110000; // -16
end
else
begin
c2_select = 2'b00;
c2_exponent_adjust = 9'd0; //0
end
end
generate
if (HIGH_LATENCY == 1)
begin
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c2_mantissa <= 27'dx;
c2_exponent <= 9'dx;
c2_sign <= 1'bx;
c2_mantissa_nonzero <= 3'dx;
c2_max_shift <= 4'dx;
c2_valid <= 1'b0;
end
else if (c2_enable)
begin
c2_valid <= c1_valid;
c2_sign <= c1_sign;
case (c2_select)
2'b11:
begin
// -1
c2_mantissa_nonzero <= 3'b111;
if (REMOVE_STICKY == 1)
c2_mantissa <= c1_mantissa[27:1];
else
c2_mantissa <= {c1_mantissa[27:2], |c1_mantissa[1:0]};
c2_max_shift <= 4'd0;
if ((c1_exponent_is_max) && (FINITE_MATH_ONLY == 0))
c2_exponent <= 9'h1ff;
else
c2_exponent <= c1_exponent + c2_exponent_adjust;
end
2'b10:
begin
// 16
c2_mantissa <= {c1_mantissa[10:0], 16'd0};
c2_exponent <= c1_exponent + c2_exponent_adjust;
c2_mantissa_nonzero <= {c1_mantissa_nonzero[1:0], |c1_mantissa[2:0]};
c2_max_shift <= (c1_max_shift[3:0]) & {4{c1_exponent_is_nonzero}};
end
default:
begin
// 0
c2_mantissa <= c1_mantissa[26:0];
c2_exponent <= c1_exponent + c2_exponent_adjust;
c2_mantissa_nonzero <= c1_mantissa_nonzero[5:3];
c2_max_shift <= ({4{c1_max_shift[4]}} | c1_max_shift[3:0]) & {4{c1_exponent_is_nonzero}};
end
endcase
end
end
end
else
begin
// in low latency mode, do not register this stage.
always@(*)
begin
c2_valid <= c1_valid;
c2_sign <= c1_sign;
case (c2_select)
2'b11:
begin
// -1
c2_mantissa_nonzero <= 3'b111;
if (REMOVE_STICKY == 1)
c2_mantissa <= c1_mantissa[27:1];
else
c2_mantissa <= {c1_mantissa[27:2], |c1_mantissa[1:0]};
c2_max_shift <= 4'd0;
if ((c1_exponent_is_max) && (FINITE_MATH_ONLY == 0))
c2_exponent <= 9'h1ff;
else
c2_exponent <= c1_exponent + c2_exponent_adjust;
end
2'b10:
begin
// 16
c2_mantissa <= {c1_mantissa[10:0], 16'd0};
c2_exponent <= c1_exponent + c2_exponent_adjust;
c2_mantissa_nonzero <= {c1_mantissa_nonzero[1:0], |c1_mantissa[2:0]};
c2_max_shift <= (c1_max_shift[3:0]) & {4{c1_exponent_is_nonzero}};
end
default:
begin
// 0
c2_mantissa <= c1_mantissa[26:0];
c2_exponent <= c1_exponent + c2_exponent_adjust;
c2_mantissa_nonzero <= c1_mantissa_nonzero[5:3];
c2_max_shift <= ({4{c1_max_shift[4]}} | c1_max_shift[3:0]) & {4{c1_exponent_is_nonzero}};
end
endcase
end
end
endgenerate
// Cycle 3 - Shift by 12, 8, 4 or 0 here.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [26:0] c3_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [8:0] c3_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [1:0] c3_max_shift;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c3_sign;
assign c3_enable = (HIGH_CAPACITY == 1) ? (~c3_valid | ~c3_stall) : enable;
assign c2_stall = c3_valid & c3_stall;
reg [1:0] c3_select;
always@(*)
begin
if (~(|c2_mantissa_nonzero) && (&c2_max_shift[3:2]))
c3_select = 2'b11;
else if (~(|c2_mantissa_nonzero[2:1]) && (c2_max_shift[3]))
c3_select = 2'b10;
else if (~c2_mantissa_nonzero[2] && (|c2_max_shift[3:2]))
c3_select = 2'b01;
else
c3_select = 2'b00;
end
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c3_mantissa <= 27'dx;
c3_exponent <= 9'dx;
c3_sign <= 1'bx;
c3_max_shift <= 2'dx;
c3_valid <= 1'b0;
end
else if (c3_enable)
begin
c3_valid <= c2_valid;
c3_sign <= c2_sign;
c3_exponent <= c2_exponent - {1'b0, c3_select, 2'b00};
case(c3_select)
2'b11:
begin
// 12
c3_mantissa <= {c2_mantissa[14:0], 12'd0};
c3_max_shift <= c2_max_shift[1:0];
end
2'b10:
begin
// 8
c3_mantissa <= {c2_mantissa[18:0], 8'd0};
c3_max_shift <= c2_max_shift[1:0] | {2{c2_max_shift[2]}};
end
2'b01:
begin
// 4
c3_mantissa <= {c2_mantissa[22:0], 4'd0};
c3_max_shift <= c2_max_shift[1:0] | {2{c2_max_shift[3]}};
end
2'b00:
begin
// 0
c3_mantissa <= c2_mantissa;
c3_max_shift <= c2_max_shift[1:0] | {2{|c2_max_shift[3:2]}};
end
endcase
end
end
// Cycle 4 - Shift by 2, 1, or 0 here.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [26:0] c4_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [8:0] c4_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c4_sign;
assign c4_enable = (HIGH_CAPACITY == 1) ? (~c4_valid | ~c4_stall) : enable;
assign c3_stall = c4_valid & c4_stall;
reg [1:0] shift_by;
always@(*)
begin
if (~(|c3_mantissa[26:24]) && ~c3_exponent[8])
shift_by <= c3_max_shift;
else if (~(|c3_mantissa[26:25]) && ~c3_exponent[8])
shift_by <= {c3_max_shift[1], ~c3_max_shift[1] & c3_max_shift[0]};
else if (~(c3_mantissa[26]) && ~c3_exponent[8])
shift_by <= {1'b0, |c3_max_shift};
else
shift_by <= 2'b00;
end
wire [26:0] resulting_mantissa = c3_mantissa << shift_by;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c4_mantissa <= 27'dx;
c4_exponent <= 9'dx;
c4_sign <= 1'bx;
c4_valid <= 1'b0;
end
else if (c4_enable)
begin
c4_valid <= c3_valid;
c4_sign <= c3_sign;
c4_mantissa <= resulting_mantissa;
if (~c3_exponent[8] && ~resulting_mantissa[26])
begin
// This number just became denormalized
c4_exponent <= 9'd0;
end
else
begin
c4_exponent <= c3_exponent - {1'b0, shift_by};
end
end
end
assign mantissa_out = c4_mantissa;
assign exponent_out = c4_exponent;
assign sign_out = c4_sign;
assign valid_out = c4_valid;
assign c4_stall = stall_in;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [7:0] crc;
reg [2:0] sum;
wire [2:0] in = crc[2:0];
wire [2:0] out;
MxN_pipeline pipe (in, out, clk);
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b sum=%x\n",$time, cyc, crc, sum);
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==0) begin
// Setup
crc <= 8'hed;
sum <= 3'h0;
end
else if (cyc>10 && cyc<90) begin
sum <= {sum[1:0],sum[2]} ^ out;
end
else if (cyc==99) begin
if (crc !== 8'b01110000) $stop;
if (sum !== 3'h3) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module dffn (q,d,clk);
parameter BITS = 1;
input [BITS-1:0] d;
output reg [BITS-1:0] q;
input clk;
always @ (posedge clk) begin
q <= d;
end
endmodule
module MxN_pipeline (in, out, clk);
parameter M=3, N=4;
input [M-1:0] in;
output [M-1:0] out;
input clk;
// Unsupported: Per-bit array instantiations with output connections to non-wires.
//wire [M*(N-1):1] t;
//dffn #(M) p[N:1] ({out,t},{t,in},clk);
wire [M*(N-1):1] w;
wire [M*N:1] q;
dffn #(M) p[N:1] (q,{w,in},clk);
assign {out,w} = q;
endmodule
|
// megafunction wizard: %ALTGX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt4gxb
// ============================================================
// File Name: altpcie_serdes_4sgx_x4d_gen2_08p.v
// Megafunction Name(s):
// alt4gxb
//
// Simulation Library Files(s):
// stratixiv_hssi
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Internal Build 118 02/15/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//alt4gxb CBX_AUTO_BLACKBOX="ALL" coreclkout_control_width=1 device_family="Stratix IV" effective_data_rate="5000 Mbps" elec_idle_infer_enable="false" enable_0ppm="false" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=1 gen_reconfig_pll="false" gx_channel_type="auto" gxb_analog_power="3.0v" gxb_powerdown_width=1 input_clock_frequency="100.0 MHz" intended_device_speed_grade="2" intended_device_variant="GX" loopback_mode="none" number_of_channels=4 number_of_quads=1 operation_mode="duplex" pll_control_width=1 pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 protocol="pcie2" rateswitch_control_width=1 receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=1 reconfig_fromgxb_port_width=17 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="x4" rx_channel_width=16 rx_common_mode="0.82v" rx_cru_bandwidth_type="auto" rx_cru_inclock0_period=10000 rx_cru_m_divider=25 rx_cru_n_divider=1 rx_cru_vco_post_scale_divider=1 rx_data_rate=5000 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=2 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=3 rx_signal_detect_threshold=4 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="true" rx_use_external_termination="false" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="auto" tx_channel_bonding="x4" tx_channel_width=16 tx_clkout_width=4 tx_common_mode="0.65v" tx_data_rate=5000 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=2 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=10000 tx_pll_m_divider=25 tx_pll_n_divider=1 tx_pll_type="CMU" tx_pll_vco_post_scale_divider=1 tx_slew_rate="off" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="true" tx_use_external_termination="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=3 cal_blk_clk coreclkout gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked powerdn rateswitch reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_freqlocked rx_patterndetect rx_pll_locked rx_syncstatus tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle tx_pipedeemph tx_pipemargin
//VERSION_BEGIN 11.0 cbx_alt4gxb 2011:02:15:21:24:41:SJ cbx_mgl 2011:02:15:21:26:30:SJ cbx_tgx 2011:02:15:21:24:41:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = reg 26 stratixiv_hssi_calibration_block 1 stratixiv_hssi_clock_divider 1 stratixiv_hssi_cmu 1 stratixiv_hssi_pll 5 stratixiv_hssi_rx_pcs 4 stratixiv_hssi_rx_pma 4 stratixiv_hssi_tx_pcs 4 stratixiv_hssi_tx_pma 4
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
module altpcie_serdes_4sgx_x4d_gen2_08p_alt4gxb_a0ea
(
cal_blk_clk,
coreclkout,
gxb_powerdown,
pipe8b10binvpolarity,
pipedatavalid,
pipeelecidle,
pipephydonestatus,
pipestatus,
pll_inclk,
pll_locked,
powerdn,
rateswitch,
reconfig_clk,
reconfig_fromgxb,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_ctrldetect,
rx_datain,
rx_dataout,
rx_digitalreset,
rx_freqlocked,
rx_patterndetect,
rx_pll_locked,
rx_syncstatus,
tx_ctrlenable,
tx_datain,
tx_dataout,
tx_detectrxloop,
tx_digitalreset,
tx_forcedispcompliance,
tx_forceelecidle,
tx_pipedeemph,
tx_pipemargin) /* synthesis synthesis_clearbox=2 */;
input cal_blk_clk;
output [0:0] coreclkout;
input [0:0] gxb_powerdown;
input [3:0] pipe8b10binvpolarity;
output [3:0] pipedatavalid;
output [3:0] pipeelecidle;
output [3:0] pipephydonestatus;
output [11:0] pipestatus;
input pll_inclk;
output [0:0] pll_locked;
input [7:0] powerdn;
input [0:0] rateswitch;
input reconfig_clk;
output [16:0] reconfig_fromgxb;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [3:0] rx_cruclk;
output [7:0] rx_ctrldetect;
input [3:0] rx_datain;
output [63:0] rx_dataout;
input [0:0] rx_digitalreset;
output [3:0] rx_freqlocked;
output [7:0] rx_patterndetect;
output [3:0] rx_pll_locked;
output [7:0] rx_syncstatus;
input [7:0] tx_ctrlenable;
input [63:0] tx_datain;
output [3:0] tx_dataout;
input [3:0] tx_detectrxloop;
input [0:0] tx_digitalreset;
input [3:0] tx_forcedispcompliance;
input [3:0] tx_forceelecidle;
input [3:0] tx_pipedeemph;
input [11:0] tx_pipemargin;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 cal_blk_clk;
tri0 [0:0] gxb_powerdown;
tri0 [3:0] pipe8b10binvpolarity;
tri0 pll_inclk;
tri0 [7:0] powerdn;
tri0 [0:0] rateswitch;
tri0 reconfig_clk;
tri0 [0:0] rx_analogreset;
tri0 [3:0] rx_cruclk;
tri0 [0:0] rx_digitalreset;
tri0 [7:0] tx_ctrlenable;
tri0 [63:0] tx_datain;
tri0 [3:0] tx_detectrxloop;
tri0 [0:0] tx_digitalreset;
tri0 [3:0] tx_forcedispcompliance;
tri0 [3:0] tx_forceelecidle;
tri0 [3:0] tx_pipedeemph;
tri0 [11:0] tx_pipemargin;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
wire [9:0] wire_pcie_sw_sel_delay_blk0c_d;
reg [9:0] pcie_sw_sel_delay_blk0c;
wire [9:0] wire_pcie_sw_sel_delay_blk0c_prn;
wire [9:0] wire_pllreset_delay_blk0c_d;
reg [9:0] pllreset_delay_blk0c;
wire [9:0] wire_pllreset_delay_blk0c_prn;
wire [2:0] wire_rx_digitalreset_reg0c_d;
reg [2:0] rx_digitalreset_reg0c;
wire [2:0] wire_rx_digitalreset_reg0c_clk;
wire [2:0] wire_tx_digitalreset_reg0c_d;
reg [2:0] tx_digitalreset_reg0c;
wire [2:0] wire_tx_digitalreset_reg0c_clk;
wire wire_cal_blk0_nonusertocmu;
wire [1:0] wire_central_clk_div0_analogfastrefclkout;
wire [1:0] wire_central_clk_div0_analogrefclkout;
wire wire_central_clk_div0_analogrefclkpulse;
wire wire_central_clk_div0_coreclkout;
wire [99:0] wire_central_clk_div0_dprioout;
wire wire_central_clk_div0_rateswitchdone;
wire wire_central_clk_div0_refclkout;
wire wire_cent_unit0_autospdx4configsel;
wire wire_cent_unit0_autospdx4rateswitchout;
wire wire_cent_unit0_autospdx4spdchg;
wire [1:0] wire_cent_unit0_clkdivpowerdn;
wire [599:0] wire_cent_unit0_cmudividerdprioout;
wire [1799:0] wire_cent_unit0_cmuplldprioout;
wire [9:0] wire_cent_unit0_digitaltestout;
wire wire_cent_unit0_dpriodisableout;
wire wire_cent_unit0_dprioout;
wire wire_cent_unit0_phfifiox4ptrsreset;
wire [1:0] wire_cent_unit0_pllpowerdn;
wire [1:0] wire_cent_unit0_pllresetout;
wire wire_cent_unit0_quadresetout;
wire [5:0] wire_cent_unit0_rxanalogresetout;
wire [5:0] wire_cent_unit0_rxcrupowerdown;
wire [5:0] wire_cent_unit0_rxcruresetout;
wire [3:0] wire_cent_unit0_rxdigitalresetout;
wire [5:0] wire_cent_unit0_rxibpowerdown;
wire [1599:0] wire_cent_unit0_rxpcsdprioout;
wire wire_cent_unit0_rxphfifox4byteselout;
wire wire_cent_unit0_rxphfifox4rdenableout;
wire wire_cent_unit0_rxphfifox4wrclkout;
wire wire_cent_unit0_rxphfifox4wrenableout;
wire [1799:0] wire_cent_unit0_rxpmadprioout;
wire [5:0] wire_cent_unit0_txanalogresetout;
wire [3:0] wire_cent_unit0_txctrlout;
wire [31:0] wire_cent_unit0_txdataout;
wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
wire [3:0] wire_cent_unit0_txdigitalresetout;
wire [5:0] wire_cent_unit0_txobpowerdown;
wire [599:0] wire_cent_unit0_txpcsdprioout;
wire wire_cent_unit0_txphfifox4byteselout;
wire wire_cent_unit0_txphfifox4rdclkout;
wire wire_cent_unit0_txphfifox4rdenableout;
wire wire_cent_unit0_txphfifox4wrenableout;
wire [1799:0] wire_cent_unit0_txpmadprioout;
wire [3:0] wire_rx_cdr_pll0_clk;
wire [1:0] wire_rx_cdr_pll0_dataout;
wire [299:0] wire_rx_cdr_pll0_dprioout;
wire wire_rx_cdr_pll0_freqlocked;
wire wire_rx_cdr_pll0_locked;
wire wire_rx_cdr_pll0_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll1_clk;
wire [1:0] wire_rx_cdr_pll1_dataout;
wire [299:0] wire_rx_cdr_pll1_dprioout;
wire wire_rx_cdr_pll1_freqlocked;
wire wire_rx_cdr_pll1_locked;
wire wire_rx_cdr_pll1_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll2_clk;
wire [1:0] wire_rx_cdr_pll2_dataout;
wire [299:0] wire_rx_cdr_pll2_dprioout;
wire wire_rx_cdr_pll2_freqlocked;
wire wire_rx_cdr_pll2_locked;
wire wire_rx_cdr_pll2_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll3_clk;
wire [1:0] wire_rx_cdr_pll3_dataout;
wire [299:0] wire_rx_cdr_pll3_dprioout;
wire wire_rx_cdr_pll3_freqlocked;
wire wire_rx_cdr_pll3_locked;
wire wire_rx_cdr_pll3_pfdrefclkout;
wire [3:0] wire_tx_pll0_clk;
wire [299:0] wire_tx_pll0_dprioout;
wire wire_tx_pll0_locked;
wire wire_receive_pcs0_autospdrateswitchout;
wire wire_receive_pcs0_cdrctrlearlyeios;
wire wire_receive_pcs0_cdrctrllocktorefclkout;
wire wire_receive_pcs0_coreclkout;
wire [3:0] wire_receive_pcs0_ctrldetect;
wire [39:0] wire_receive_pcs0_dataout;
wire [399:0] wire_receive_pcs0_dprioout;
wire [3:0] wire_receive_pcs0_patterndetect;
wire wire_receive_pcs0_phfifobyteserdisableout;
wire wire_receive_pcs0_phfifoptrsresetout;
wire wire_receive_pcs0_phfifordenableout;
wire wire_receive_pcs0_phfiforesetout;
wire wire_receive_pcs0_phfifowrdisableout;
wire wire_receive_pcs0_pipedatavalid;
wire wire_receive_pcs0_pipeelecidle;
wire wire_receive_pcs0_pipephydonestatus;
wire wire_receive_pcs0_pipestatetransdoneout;
wire [2:0] wire_receive_pcs0_pipestatus;
wire wire_receive_pcs0_rateswitchout;
wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
wire wire_receive_pcs0_signaldetect;
wire [3:0] wire_receive_pcs0_syncstatus;
wire wire_receive_pcs1_autospdrateswitchout;
wire wire_receive_pcs1_cdrctrlearlyeios;
wire wire_receive_pcs1_cdrctrllocktorefclkout;
wire wire_receive_pcs1_coreclkout;
wire [3:0] wire_receive_pcs1_ctrldetect;
wire [39:0] wire_receive_pcs1_dataout;
wire [399:0] wire_receive_pcs1_dprioout;
wire [3:0] wire_receive_pcs1_patterndetect;
wire wire_receive_pcs1_phfifobyteserdisableout;
wire wire_receive_pcs1_phfifoptrsresetout;
wire wire_receive_pcs1_phfifordenableout;
wire wire_receive_pcs1_phfiforesetout;
wire wire_receive_pcs1_phfifowrdisableout;
wire wire_receive_pcs1_pipedatavalid;
wire wire_receive_pcs1_pipeelecidle;
wire wire_receive_pcs1_pipephydonestatus;
wire wire_receive_pcs1_pipestatetransdoneout;
wire [2:0] wire_receive_pcs1_pipestatus;
wire wire_receive_pcs1_rateswitchout;
wire [19:0] wire_receive_pcs1_revparallelfdbkdata;
wire wire_receive_pcs1_signaldetect;
wire [3:0] wire_receive_pcs1_syncstatus;
wire wire_receive_pcs2_autospdrateswitchout;
wire wire_receive_pcs2_cdrctrlearlyeios;
wire wire_receive_pcs2_cdrctrllocktorefclkout;
wire wire_receive_pcs2_coreclkout;
wire [3:0] wire_receive_pcs2_ctrldetect;
wire [39:0] wire_receive_pcs2_dataout;
wire [399:0] wire_receive_pcs2_dprioout;
wire [3:0] wire_receive_pcs2_patterndetect;
wire wire_receive_pcs2_phfifobyteserdisableout;
wire wire_receive_pcs2_phfifoptrsresetout;
wire wire_receive_pcs2_phfifordenableout;
wire wire_receive_pcs2_phfiforesetout;
wire wire_receive_pcs2_phfifowrdisableout;
wire wire_receive_pcs2_pipedatavalid;
wire wire_receive_pcs2_pipeelecidle;
wire wire_receive_pcs2_pipephydonestatus;
wire wire_receive_pcs2_pipestatetransdoneout;
wire [2:0] wire_receive_pcs2_pipestatus;
wire wire_receive_pcs2_rateswitchout;
wire [19:0] wire_receive_pcs2_revparallelfdbkdata;
wire wire_receive_pcs2_signaldetect;
wire [3:0] wire_receive_pcs2_syncstatus;
wire wire_receive_pcs3_autospdrateswitchout;
wire wire_receive_pcs3_cdrctrlearlyeios;
wire wire_receive_pcs3_cdrctrllocktorefclkout;
wire wire_receive_pcs3_coreclkout;
wire [3:0] wire_receive_pcs3_ctrldetect;
wire [39:0] wire_receive_pcs3_dataout;
wire [399:0] wire_receive_pcs3_dprioout;
wire [3:0] wire_receive_pcs3_patterndetect;
wire wire_receive_pcs3_phfifobyteserdisableout;
wire wire_receive_pcs3_phfifoptrsresetout;
wire wire_receive_pcs3_phfifordenableout;
wire wire_receive_pcs3_phfiforesetout;
wire wire_receive_pcs3_phfifowrdisableout;
wire wire_receive_pcs3_pipedatavalid;
wire wire_receive_pcs3_pipeelecidle;
wire wire_receive_pcs3_pipephydonestatus;
wire wire_receive_pcs3_pipestatetransdoneout;
wire [2:0] wire_receive_pcs3_pipestatus;
wire wire_receive_pcs3_rateswitchout;
wire [19:0] wire_receive_pcs3_revparallelfdbkdata;
wire wire_receive_pcs3_signaldetect;
wire [3:0] wire_receive_pcs3_syncstatus;
wire [7:0] wire_receive_pma0_analogtestbus;
wire wire_receive_pma0_clockout;
wire wire_receive_pma0_dataout;
wire [299:0] wire_receive_pma0_dprioout;
wire wire_receive_pma0_locktorefout;
wire [63:0] wire_receive_pma0_recoverdataout;
wire wire_receive_pma0_signaldetect;
wire [7:0] wire_receive_pma1_analogtestbus;
wire wire_receive_pma1_clockout;
wire wire_receive_pma1_dataout;
wire [299:0] wire_receive_pma1_dprioout;
wire wire_receive_pma1_locktorefout;
wire [63:0] wire_receive_pma1_recoverdataout;
wire wire_receive_pma1_signaldetect;
wire [7:0] wire_receive_pma2_analogtestbus;
wire wire_receive_pma2_clockout;
wire wire_receive_pma2_dataout;
wire [299:0] wire_receive_pma2_dprioout;
wire wire_receive_pma2_locktorefout;
wire [63:0] wire_receive_pma2_recoverdataout;
wire wire_receive_pma2_signaldetect;
wire [7:0] wire_receive_pma3_analogtestbus;
wire wire_receive_pma3_clockout;
wire wire_receive_pma3_dataout;
wire [299:0] wire_receive_pma3_dprioout;
wire wire_receive_pma3_locktorefout;
wire [63:0] wire_receive_pma3_recoverdataout;
wire wire_receive_pma3_signaldetect;
wire wire_transmit_pcs0_coreclkout;
wire [19:0] wire_transmit_pcs0_dataout;
wire [149:0] wire_transmit_pcs0_dprioout;
wire wire_transmit_pcs0_forceelecidleout;
wire [2:0] wire_transmit_pcs0_grayelecidleinferselout;
wire wire_transmit_pcs0_phfiforddisableout;
wire wire_transmit_pcs0_phfiforesetout;
wire wire_transmit_pcs0_phfifowrenableout;
wire wire_transmit_pcs0_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs0_pipepowerdownout;
wire [3:0] wire_transmit_pcs0_pipepowerstateout;
wire wire_transmit_pcs0_txdetectrx;
wire wire_transmit_pcs1_coreclkout;
wire [19:0] wire_transmit_pcs1_dataout;
wire [149:0] wire_transmit_pcs1_dprioout;
wire wire_transmit_pcs1_forceelecidleout;
wire [2:0] wire_transmit_pcs1_grayelecidleinferselout;
wire wire_transmit_pcs1_phfiforddisableout;
wire wire_transmit_pcs1_phfiforesetout;
wire wire_transmit_pcs1_phfifowrenableout;
wire wire_transmit_pcs1_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs1_pipepowerdownout;
wire [3:0] wire_transmit_pcs1_pipepowerstateout;
wire wire_transmit_pcs1_txdetectrx;
wire wire_transmit_pcs2_coreclkout;
wire [19:0] wire_transmit_pcs2_dataout;
wire [149:0] wire_transmit_pcs2_dprioout;
wire wire_transmit_pcs2_forceelecidleout;
wire [2:0] wire_transmit_pcs2_grayelecidleinferselout;
wire wire_transmit_pcs2_phfiforddisableout;
wire wire_transmit_pcs2_phfiforesetout;
wire wire_transmit_pcs2_phfifowrenableout;
wire wire_transmit_pcs2_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs2_pipepowerdownout;
wire [3:0] wire_transmit_pcs2_pipepowerstateout;
wire wire_transmit_pcs2_txdetectrx;
wire wire_transmit_pcs3_coreclkout;
wire [19:0] wire_transmit_pcs3_dataout;
wire [149:0] wire_transmit_pcs3_dprioout;
wire wire_transmit_pcs3_forceelecidleout;
wire [2:0] wire_transmit_pcs3_grayelecidleinferselout;
wire wire_transmit_pcs3_phfiforddisableout;
wire wire_transmit_pcs3_phfiforesetout;
wire wire_transmit_pcs3_phfifowrenableout;
wire wire_transmit_pcs3_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs3_pipepowerdownout;
wire [3:0] wire_transmit_pcs3_pipepowerstateout;
wire wire_transmit_pcs3_txdetectrx;
wire wire_transmit_pma0_clockout;
wire wire_transmit_pma0_dataout;
wire [299:0] wire_transmit_pma0_dprioout;
wire wire_transmit_pma0_rxdetectvalidout;
wire wire_transmit_pma0_rxfoundout;
wire wire_transmit_pma1_clockout;
wire wire_transmit_pma1_dataout;
wire [299:0] wire_transmit_pma1_dprioout;
wire wire_transmit_pma1_rxdetectvalidout;
wire wire_transmit_pma1_rxfoundout;
wire wire_transmit_pma2_clockout;
wire wire_transmit_pma2_dataout;
wire [299:0] wire_transmit_pma2_dprioout;
wire wire_transmit_pma2_rxdetectvalidout;
wire wire_transmit_pma2_rxfoundout;
wire wire_transmit_pma3_clockout;
wire wire_transmit_pma3_dataout;
wire [299:0] wire_transmit_pma3_dprioout;
wire wire_transmit_pma3_rxdetectvalidout;
wire wire_transmit_pma3_rxfoundout;
wire cal_blk_powerdown;
wire [0:0] cent_unit_clkdivpowerdn;
wire [599:0] cent_unit_cmudividerdprioout;
wire [1799:0] cent_unit_cmuplldprioout;
wire [1:0] cent_unit_pllpowerdn;
wire [1:0] cent_unit_pllresetout;
wire [0:0] cent_unit_quadresetout;
wire [5:0] cent_unit_rxcrupowerdn;
wire [5:0] cent_unit_rxibpowerdn;
wire [1599:0] cent_unit_rxpcsdprioin;
wire [1599:0] cent_unit_rxpcsdprioout;
wire [1799:0] cent_unit_rxpmadprioin;
wire [1799:0] cent_unit_rxpmadprioout;
wire [1199:0] cent_unit_tx_dprioin;
wire [31:0] cent_unit_tx_xgmdataout;
wire [3:0] cent_unit_txctrlout;
wire [5:0] cent_unit_txdetectrxpowerdn;
wire [599:0] cent_unit_txdprioout;
wire [5:0] cent_unit_txobpowerdn;
wire [1799:0] cent_unit_txpmadprioin;
wire [1799:0] cent_unit_txpmadprioout;
wire [3:0] clk_div_clk0in;
wire [599:0] clk_div_cmudividerdprioin;
wire [1:0] cmu_analogfastrefclkout;
wire [1:0] cmu_analogrefclkout;
wire [0:0] cmu_analogrefclkpulse;
wire [0:0] coreclkout_wire;
wire fixedclk;
wire [5:0] fixedclk_to_cmu;
wire [11:0] grayelecidleinfersel_from_tx;
wire [0:0] int_autospdx4configsel;
wire [0:0] int_autospdx4spdchg;
wire [0:0] int_hiprateswtichdone;
wire [0:0] int_pcie_sw;
wire [0:0] int_pcie_sw_select;
wire [0:0] int_phfifiox4ptrsreset;
wire [3:0] int_pipeenrevparallellpbkfromtx;
wire [0:0] int_pll_reset_delayed;
wire [0:0] int_rateswitch;
wire [11:0] int_rx_autospdxnconfigsel;
wire [11:0] int_rx_autospdxnspdchg;
wire [3:0] int_rx_coreclkout;
wire [0:0] int_rx_digitalreset_reg;
wire [11:0] int_rx_phfifioxnptrsreset;
wire [3:0] int_rx_phfifobyteserdisable;
wire [3:0] int_rx_phfifoptrsresetout;
wire [3:0] int_rx_phfifordenableout;
wire [3:0] int_rx_phfiforesetout;
wire [3:0] int_rx_phfifowrdisableout;
wire [11:0] int_rx_phfifoxnbytesel;
wire [11:0] int_rx_phfifoxnrdenable;
wire [11:0] int_rx_phfifoxnwrclk;
wire [11:0] int_rx_phfifoxnwrenable;
wire [3:0] int_rx_rateswitchout;
wire [0:0] int_rxcoreclk;
wire [3:0] int_rxpcs_cdrctrlearlyeios;
wire [0:0] int_rxphfifordenable;
wire [0:0] int_rxphfiforeset;
wire [0:0] int_rxphfifox4byteselout;
wire [0:0] int_rxphfifox4rdenableout;
wire [0:0] int_rxphfifox4wrclkout;
wire [0:0] int_rxphfifox4wrenableout;
wire [3:0] int_tx_coreclkout;
wire [0:0] int_tx_digitalreset_reg;
wire [11:0] int_tx_phfifioxnptrsreset;
wire [3:0] int_tx_phfiforddisableout;
wire [3:0] int_tx_phfiforesetout;
wire [3:0] int_tx_phfifowrenableout;
wire [11:0] int_tx_phfifoxnbytesel;
wire [11:0] int_tx_phfifoxnrdclk;
wire [11:0] int_tx_phfifoxnrdenable;
wire [11:0] int_tx_phfifoxnwrenable;
wire [0:0] int_txcoreclk;
wire [0:0] int_txphfiforddisable;
wire [0:0] int_txphfiforeset;
wire [0:0] int_txphfifowrenable;
wire [0:0] int_txphfifox4byteselout;
wire [0:0] int_txphfifox4rdclkout;
wire [0:0] int_txphfifox4rdenableout;
wire [0:0] int_txphfifox4wrenableout;
wire [0:0] nonusertocmu_out;
wire [0:0] pcie_sw_wire;
wire [3:0] pipedatavalid_out;
wire [3:0] pipeelecidle_out;
wire [9:0] pll0_clkin;
wire [299:0] pll0_dprioin;
wire [299:0] pll0_dprioout;
wire [3:0] pll0_out;
wire [7:0] pll_ch_dataout_wire;
wire [1199:0] pll_ch_dprioout;
wire [1799:0] pll_cmuplldprioout;
wire [0:0] pll_inclk_wire;
wire [0:0] pll_locked_out;
wire [0:0] pll_powerdown;
wire [1:0] pllpowerdn_in;
wire [1:0] pllreset_in;
wire [0:0] reconfig_togxb_busy;
wire [0:0] reconfig_togxb_disable;
wire [0:0] reconfig_togxb_in;
wire [0:0] reconfig_togxb_load;
wire [0:0] refclk_pma;
wire [5:0] rx_analogreset_in;
wire [5:0] rx_analogreset_out;
wire [3:0] rx_coreclk_in;
wire [39:0] rx_cruclk_in;
wire [15:0] rx_deserclock_in;
wire [3:0] rx_digitalreset_in;
wire [3:0] rx_digitalreset_out;
wire [11:0] rx_elecidleinfersel;
wire [3:0] rx_enapatternalign;
wire [3:0] rx_freqlocked_wire;
wire [3:0] rx_locktodata;
wire [3:0] rx_locktodata_wire;
wire [3:0] rx_locktorefclk_wire;
wire [63:0] rx_out_wire;
wire [7:0] rx_pcs_rxfound_wire;
wire [1599:0] rx_pcsdprioin_wire;
wire [1599:0] rx_pcsdprioout;
wire [3:0] rx_phfifordenable;
wire [3:0] rx_phfiforeset;
wire [3:0] rx_phfifowrdisable;
wire [3:0] rx_pipestatetransdoneout;
wire [3:0] rx_pldcruclk_in;
wire [15:0] rx_pll_clkout;
wire [3:0] rx_pll_pfdrefclkout_wire;
wire [3:0] rx_plllocked_wire;
wire [67:0] rx_pma_analogtestbus;
wire [3:0] rx_pma_clockout;
wire [3:0] rx_pma_dataout;
wire [3:0] rx_pma_locktorefout;
wire [79:0] rx_pma_recoverdataout_wire;
wire [1799:0] rx_pmadprioin_wire;
wire [1799:0] rx_pmadprioout;
wire [3:0] rx_powerdown;
wire [5:0] rx_powerdown_in;
wire [3:0] rx_prbscidenable;
wire [79:0] rx_revparallelfdbkdata;
wire [3:0] rx_rmfiforeset;
wire [5:0] rx_rxcruresetout;
wire [3:0] rx_signaldetect_wire;
wire [0:0] rxphfifowrdisable;
wire [1799:0] rxpll_dprioin;
wire [5:0] tx_analogreset_out;
wire [3:0] tx_clkout_int_wire;
wire [3:0] tx_coreclk_in;
wire [63:0] tx_datain_wire;
wire [79:0] tx_dataout_pcs_to_pma;
wire [3:0] tx_digitalreset_in;
wire [3:0] tx_digitalreset_out;
wire [1199:0] tx_dprioin_wire;
wire [7:0] tx_forcedisp_wire;
wire [3:0] tx_invpolarity;
wire [3:0] tx_localrefclk;
wire [3:0] tx_pcs_forceelecidleout;
wire [3:0] tx_phfiforeset;
wire [7:0] tx_pipepowerdownout;
wire [15:0] tx_pipepowerstateout;
wire [3:0] tx_pipeswing;
wire [1799:0] tx_pmadprioin_wire;
wire [1799:0] tx_pmadprioout;
wire [3:0] tx_revparallellpbken;
wire [3:0] tx_rxdetectvalidout;
wire [3:0] tx_rxfoundout;
wire [599:0] tx_txdprioout;
wire [3:0] txdetectrxout;
wire [0:0] w_cent_unit_dpriodisableout1w;
// synopsys translate_off
initial
pcie_sw_sel_delay_blk0c[0:0] = 0;
// synopsys translate_on
always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[0:0])
if (wire_pcie_sw_sel_delay_blk0c_prn[0:0] == 1'b0) pcie_sw_sel_delay_blk0c[0:0] <= 1'b1;
else pcie_sw_sel_delay_blk0c[0:0] <= wire_pcie_sw_sel_delay_blk0c_d[0:0];
// synopsys translate_off
initial
pcie_sw_sel_delay_blk0c[1:1] = 0;
// synopsys translate_on
always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[1:1])
if (wire_pcie_sw_sel_delay_blk0c_prn[1:1] == 1'b0) pcie_sw_sel_delay_blk0c[1:1] <= 1'b1;
else pcie_sw_sel_delay_blk0c[1:1] <= wire_pcie_sw_sel_delay_blk0c_d[1:1];
// synopsys translate_off
initial
pcie_sw_sel_delay_blk0c[2:2] = 0;
// synopsys translate_on
always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[2:2])
if (wire_pcie_sw_sel_delay_blk0c_prn[2:2] == 1'b0) pcie_sw_sel_delay_blk0c[2:2] <= 1'b1;
else pcie_sw_sel_delay_blk0c[2:2] <= wire_pcie_sw_sel_delay_blk0c_d[2:2];
// synopsys translate_off
initial
pcie_sw_sel_delay_blk0c[3:3] = 0;
// synopsys translate_on
always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[3:3])
if (wire_pcie_sw_sel_delay_blk0c_prn[3:3] == 1'b0) pcie_sw_sel_delay_blk0c[3:3] <= 1'b1;
else pcie_sw_sel_delay_blk0c[3:3] <= wire_pcie_sw_sel_delay_blk0c_d[3:3];
// synopsys translate_off
initial
pcie_sw_sel_delay_blk0c[4:4] = 0;
// synopsys translate_on
always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[4:4])
if (wire_pcie_sw_sel_delay_blk0c_prn[4:4] == 1'b0) pcie_sw_sel_delay_blk0c[4:4] <= 1'b1;
else pcie_sw_sel_delay_blk0c[4:4] <= wire_pcie_sw_sel_delay_blk0c_d[4:4];
// synopsys translate_off
initial
pcie_sw_sel_delay_blk0c[5:5] = 0;
// synopsys translate_on
always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[5:5])
if (wire_pcie_sw_sel_delay_blk0c_prn[5:5] == 1'b0) pcie_sw_sel_delay_blk0c[5:5] <= 1'b1;
else pcie_sw_sel_delay_blk0c[5:5] <= wire_pcie_sw_sel_delay_blk0c_d[5:5];
// synopsys translate_off
initial
pcie_sw_sel_delay_blk0c[6:6] = 0;
// synopsys translate_on
always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[6:6])
if (wire_pcie_sw_sel_delay_blk0c_prn[6:6] == 1'b0) pcie_sw_sel_delay_blk0c[6:6] <= 1'b1;
else pcie_sw_sel_delay_blk0c[6:6] <= wire_pcie_sw_sel_delay_blk0c_d[6:6];
// synopsys translate_off
initial
pcie_sw_sel_delay_blk0c[7:7] = 0;
// synopsys translate_on
always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[7:7])
if (wire_pcie_sw_sel_delay_blk0c_prn[7:7] == 1'b0) pcie_sw_sel_delay_blk0c[7:7] <= 1'b1;
else pcie_sw_sel_delay_blk0c[7:7] <= wire_pcie_sw_sel_delay_blk0c_d[7:7];
// synopsys translate_off
initial
pcie_sw_sel_delay_blk0c[8:8] = 0;
// synopsys translate_on
always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[8:8])
if (wire_pcie_sw_sel_delay_blk0c_prn[8:8] == 1'b0) pcie_sw_sel_delay_blk0c[8:8] <= 1'b1;
else pcie_sw_sel_delay_blk0c[8:8] <= wire_pcie_sw_sel_delay_blk0c_d[8:8];
// synopsys translate_off
initial
pcie_sw_sel_delay_blk0c[9:9] = 0;
// synopsys translate_on
always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[9:9])
if (wire_pcie_sw_sel_delay_blk0c_prn[9:9] == 1'b0) pcie_sw_sel_delay_blk0c[9:9] <= 1'b1;
else pcie_sw_sel_delay_blk0c[9:9] <= wire_pcie_sw_sel_delay_blk0c_d[9:9];
assign
wire_pcie_sw_sel_delay_blk0c_d = {pcie_sw_sel_delay_blk0c[8:0], pllreset_delay_blk0c[9]};
assign
wire_pcie_sw_sel_delay_blk0c_prn = {10{(~ pll_powerdown[0])}};
// synopsys translate_off
initial
pllreset_delay_blk0c[0:0] = 0;
// synopsys translate_on
always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[0:0])
if (wire_pllreset_delay_blk0c_prn[0:0] == 1'b0) pllreset_delay_blk0c[0:0] <= 1'b1;
else pllreset_delay_blk0c[0:0] <= wire_pllreset_delay_blk0c_d[0:0];
// synopsys translate_off
initial
pllreset_delay_blk0c[1:1] = 0;
// synopsys translate_on
always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[1:1])
if (wire_pllreset_delay_blk0c_prn[1:1] == 1'b0) pllreset_delay_blk0c[1:1] <= 1'b1;
else pllreset_delay_blk0c[1:1] <= wire_pllreset_delay_blk0c_d[1:1];
// synopsys translate_off
initial
pllreset_delay_blk0c[2:2] = 0;
// synopsys translate_on
always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[2:2])
if (wire_pllreset_delay_blk0c_prn[2:2] == 1'b0) pllreset_delay_blk0c[2:2] <= 1'b1;
else pllreset_delay_blk0c[2:2] <= wire_pllreset_delay_blk0c_d[2:2];
// synopsys translate_off
initial
pllreset_delay_blk0c[3:3] = 0;
// synopsys translate_on
always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[3:3])
if (wire_pllreset_delay_blk0c_prn[3:3] == 1'b0) pllreset_delay_blk0c[3:3] <= 1'b1;
else pllreset_delay_blk0c[3:3] <= wire_pllreset_delay_blk0c_d[3:3];
// synopsys translate_off
initial
pllreset_delay_blk0c[4:4] = 0;
// synopsys translate_on
always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[4:4])
if (wire_pllreset_delay_blk0c_prn[4:4] == 1'b0) pllreset_delay_blk0c[4:4] <= 1'b1;
else pllreset_delay_blk0c[4:4] <= wire_pllreset_delay_blk0c_d[4:4];
// synopsys translate_off
initial
pllreset_delay_blk0c[5:5] = 0;
// synopsys translate_on
always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[5:5])
if (wire_pllreset_delay_blk0c_prn[5:5] == 1'b0) pllreset_delay_blk0c[5:5] <= 1'b1;
else pllreset_delay_blk0c[5:5] <= wire_pllreset_delay_blk0c_d[5:5];
// synopsys translate_off
initial
pllreset_delay_blk0c[6:6] = 0;
// synopsys translate_on
always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[6:6])
if (wire_pllreset_delay_blk0c_prn[6:6] == 1'b0) pllreset_delay_blk0c[6:6] <= 1'b1;
else pllreset_delay_blk0c[6:6] <= wire_pllreset_delay_blk0c_d[6:6];
// synopsys translate_off
initial
pllreset_delay_blk0c[7:7] = 0;
// synopsys translate_on
always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[7:7])
if (wire_pllreset_delay_blk0c_prn[7:7] == 1'b0) pllreset_delay_blk0c[7:7] <= 1'b1;
else pllreset_delay_blk0c[7:7] <= wire_pllreset_delay_blk0c_d[7:7];
// synopsys translate_off
initial
pllreset_delay_blk0c[8:8] = 0;
// synopsys translate_on
always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[8:8])
if (wire_pllreset_delay_blk0c_prn[8:8] == 1'b0) pllreset_delay_blk0c[8:8] <= 1'b1;
else pllreset_delay_blk0c[8:8] <= wire_pllreset_delay_blk0c_d[8:8];
// synopsys translate_off
initial
pllreset_delay_blk0c[9:9] = 0;
// synopsys translate_on
always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[9:9])
if (wire_pllreset_delay_blk0c_prn[9:9] == 1'b0) pllreset_delay_blk0c[9:9] <= 1'b1;
else pllreset_delay_blk0c[9:9] <= wire_pllreset_delay_blk0c_d[9:9];
assign
wire_pllreset_delay_blk0c_d = {pllreset_delay_blk0c[8:0], (pll_powerdown[0] | (~ pll_locked_out[0]))};
assign
wire_pllreset_delay_blk0c_prn = {10{(~ pll_powerdown[0])}};
// synopsys translate_off
initial
rx_digitalreset_reg0c[0:0] = 0;
// synopsys translate_on
always @ ( posedge wire_rx_digitalreset_reg0c_clk[0:0])
rx_digitalreset_reg0c[0:0] <= wire_rx_digitalreset_reg0c_d[0:0];
// synopsys translate_off
initial
rx_digitalreset_reg0c[1:1] = 0;
// synopsys translate_on
always @ ( posedge wire_rx_digitalreset_reg0c_clk[1:1])
rx_digitalreset_reg0c[1:1] <= wire_rx_digitalreset_reg0c_d[1:1];
// synopsys translate_off
initial
rx_digitalreset_reg0c[2:2] = 0;
// synopsys translate_on
always @ ( posedge wire_rx_digitalreset_reg0c_clk[2:2])
rx_digitalreset_reg0c[2:2] <= wire_rx_digitalreset_reg0c_d[2:2];
assign
wire_rx_digitalreset_reg0c_d = {rx_digitalreset_reg0c[1:0], rx_digitalreset[0]};
assign
wire_rx_digitalreset_reg0c_clk = {3{coreclkout_wire[0]}};
// synopsys translate_off
initial
tx_digitalreset_reg0c[0:0] = 0;
// synopsys translate_on
always @ ( posedge wire_tx_digitalreset_reg0c_clk[0:0])
tx_digitalreset_reg0c[0:0] <= wire_tx_digitalreset_reg0c_d[0:0];
// synopsys translate_off
initial
tx_digitalreset_reg0c[1:1] = 0;
// synopsys translate_on
always @ ( posedge wire_tx_digitalreset_reg0c_clk[1:1])
tx_digitalreset_reg0c[1:1] <= wire_tx_digitalreset_reg0c_d[1:1];
// synopsys translate_off
initial
tx_digitalreset_reg0c[2:2] = 0;
// synopsys translate_on
always @ ( posedge wire_tx_digitalreset_reg0c_clk[2:2])
tx_digitalreset_reg0c[2:2] <= wire_tx_digitalreset_reg0c_d[2:2];
assign
wire_tx_digitalreset_reg0c_d = {tx_digitalreset_reg0c[1:0], tx_digitalreset[0]};
assign
wire_tx_digitalreset_reg0c_clk = {3{coreclkout_wire[0]}};
stratixiv_hssi_calibration_block cal_blk0
(
.calibrationstatus(),
.clk(cal_blk_clk),
.enabletestbus(1'b1),
.nonusertocmu(wire_cal_blk0_nonusertocmu),
.powerdn(cal_blk_powerdown)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.testctrl(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
stratixiv_hssi_clock_divider central_clk_div0
(
.analogfastrefclkout(wire_central_clk_div0_analogfastrefclkout),
.analogfastrefclkoutshifted(),
.analogrefclkout(wire_central_clk_div0_analogrefclkout),
.analogrefclkoutshifted(),
.analogrefclkpulse(wire_central_clk_div0_analogrefclkpulse),
.analogrefclkpulseshifted(),
.clk0in(clk_div_clk0in[3:0]),
.coreclkout(wire_central_clk_div0_coreclkout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(cent_unit_cmudividerdprioout[499:400]),
.dprioout(wire_central_clk_div0_dprioout),
.powerdn(cent_unit_clkdivpowerdn[0]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitch(int_pcie_sw[0]),
.rateswitchbaseclock(),
.rateswitchdone(wire_central_clk_div0_rateswitchdone),
.rateswitchout(),
.refclkout(wire_central_clk_div0_refclkout)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1in({4{1'b0}}),
.rateswitchbaseclkin({2{1'b0}}),
.rateswitchdonein({2{1'b0}}),
.refclkdig(1'b0),
.refclkin({2{1'b0}}),
.vcobypassin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
central_clk_div0.divide_by = 5,
central_clk_div0.divider_type = "CENTRAL_ENHANCED",
central_clk_div0.effective_data_rate = "5000 Mbps",
central_clk_div0.enable_dynamic_divider = "true",
central_clk_div0.enable_refclk_out = "true",
central_clk_div0.inclk_select = 0,
central_clk_div0.logical_channel_address = 0,
central_clk_div0.pre_divide_by = 1,
central_clk_div0.refclkin_select = 0,
central_clk_div0.select_local_rate_switch_base_clock = "true",
central_clk_div0.select_local_rate_switch_done = "true",
central_clk_div0.select_local_refclk = "true",
central_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
central_clk_div0.sim_analogrefclkout_phase_shift = 0,
central_clk_div0.sim_coreclkout_phase_shift = 0,
central_clk_div0.sim_refclkout_phase_shift = 0,
central_clk_div0.use_coreclk_out_post_divider = "true",
central_clk_div0.use_refclk_post_divider = "false",
central_clk_div0.use_vco_bypass = "false",
central_clk_div0.lpm_type = "stratixiv_hssi_clock_divider";
stratixiv_hssi_cmu cent_unit0
(
.adet({4{1'b0}}),
.alignstatus(),
.autospdx4configsel(wire_cent_unit0_autospdx4configsel),
.autospdx4rateswitchout(wire_cent_unit0_autospdx4rateswitchout),
.autospdx4spdchg(wire_cent_unit0_autospdx4spdchg),
.clkdivpowerdn(wire_cent_unit0_clkdivpowerdn),
.cmudividerdprioin({clk_div_cmudividerdprioin[599:0]}),
.cmudividerdprioout(wire_cent_unit0_cmudividerdprioout),
.cmuplldprioin(pll_cmuplldprioout[1799:0]),
.cmuplldprioout(wire_cent_unit0_cmuplldprioout),
.digitaltestout(wire_cent_unit0_digitaltestout),
.dpclk(reconfig_clk),
.dpriodisable(reconfig_togxb_disable),
.dpriodisableout(wire_cent_unit0_dpriodisableout),
.dprioin(reconfig_togxb_in),
.dprioload(reconfig_togxb_load),
.dpriooe(),
.dprioout(wire_cent_unit0_dprioout),
.enabledeskew(),
.extra10gout(),
.fiforesetrd(),
.fixedclk({{2{1'b0}}, fixedclk_to_cmu[3:0]}),
.lccmutestbus(),
.nonuserfromcal(nonusertocmu_out[0]),
.phfifiox4ptrsreset(wire_cent_unit0_phfifiox4ptrsreset),
.pllpowerdn(wire_cent_unit0_pllpowerdn),
.pllresetout(wire_cent_unit0_pllresetout),
.quadreset(gxb_powerdown[0]),
.quadresetout(wire_cent_unit0_quadresetout),
.rateswitch(int_rateswitch[0]),
.rateswitchdonein(int_hiprateswtichdone[0]),
.rdalign({4{1'b0}}),
.rdenablesync(1'b0),
.recovclk(1'b0),
.refclkdividerdprioin({2{1'b0}}),
.refclkdividerdprioout(),
.rxadcepowerdown(),
.rxadceresetout(),
.rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
.rxanalogresetout(wire_cent_unit0_rxanalogresetout),
.rxclk(refclk_pma[0]),
.rxcoreclk(int_rxcoreclk[0]),
.rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
.rxcruresetout(wire_cent_unit0_rxcruresetout),
.rxctrl({4{1'b0}}),
.rxctrlout(),
.rxdatain({32{1'b0}}),
.rxdataout(),
.rxdatavalid({4{1'b0}}),
.rxdigitalreset({rx_digitalreset_in[3:0]}),
.rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
.rxibpowerdown(wire_cent_unit0_rxibpowerdown),
.rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),
.rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
.rxphfifordenable(int_rxphfifordenable[0]),
.rxphfiforeset(int_rxphfiforeset[0]),
.rxphfifowrdisable(rxphfifowrdisable[0]),
.rxphfifox4byteselout(wire_cent_unit0_rxphfifox4byteselout),
.rxphfifox4rdenableout(wire_cent_unit0_rxphfifox4rdenableout),
.rxphfifox4wrclkout(wire_cent_unit0_rxphfifox4wrclkout),
.rxphfifox4wrenableout(wire_cent_unit0_rxphfifox4wrenableout),
.rxpmadprioin({cent_unit_rxpmadprioin[1799:0]}),
.rxpmadprioout(wire_cent_unit0_rxpmadprioout),
.rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
.rxrunningdisp({4{1'b0}}),
.scanout(),
.syncstatus({4{1'b0}}),
.testout(),
.txanalogresetout(wire_cent_unit0_txanalogresetout),
.txclk(refclk_pma[0]),
.txcoreclk(int_txcoreclk[0]),
.txctrl({4{1'b0}}),
.txctrlout(wire_cent_unit0_txctrlout),
.txdatain({32{1'b0}}),
.txdataout(wire_cent_unit0_txdataout),
.txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
.txdigitalreset({tx_digitalreset_in[3:0]}),
.txdigitalresetout(wire_cent_unit0_txdigitalresetout),
.txdividerpowerdown(),
.txobpowerdown(wire_cent_unit0_txobpowerdown),
.txpcsdprioin({cent_unit_tx_dprioin[599:0]}),
.txpcsdprioout(wire_cent_unit0_txpcsdprioout),
.txphfiforddisable(int_txphfiforddisable[0]),
.txphfiforeset(int_txphfiforeset[0]),
.txphfifowrenable(int_txphfifowrenable[0]),
.txphfifox4byteselout(wire_cent_unit0_txphfifox4byteselout),
.txphfifox4rdclkout(wire_cent_unit0_txphfifox4rdclkout),
.txphfifox4rdenableout(wire_cent_unit0_txphfifox4rdenableout),
.txphfifox4wrenableout(wire_cent_unit0_txphfifox4wrenableout),
.txpllreset({{1{1'b0}}, pll_powerdown[0]}),
.txpmadprioin({cent_unit_txpmadprioin[1799:0]}),
.txpmadprioout(wire_cent_unit0_txpmadprioout)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({7{1'b0}}),
.lccmurtestbussel({3{1'b0}}),
.pmacramtest(1'b0),
.scanclk(1'b0),
.scanin({23{1'b0}}),
.scanmode(1'b0),
.scanshift(1'b0),
.testin({10000{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
cent_unit0.auto_spd_phystatus_notify_count = 14,
cent_unit0.bonded_quad_mode = "none",
cent_unit0.central_test_bus_select = 0,
cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
cent_unit0.in_xaui_mode = "false",
cent_unit0.offset_all_errors_align = "false",
cent_unit0.pipe_auto_speed_nego_enable = "true",
cent_unit0.pipe_freq_scale_mode = "Frequency",
cent_unit0.pma_done_count = 249950,
cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
cent_unit0.rx0_auto_spd_self_switch_enable = "false",
cent_unit0.rx0_channel_bonding = "x4",
cent_unit0.rx0_clk1_mux_select = "recovered clock",
cent_unit0.rx0_clk2_mux_select = "digital reference clock",
cent_unit0.rx0_ph_fifo_reg_mode = "false",
cent_unit0.rx0_rd_clk_mux_select = "core clock",
cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
cent_unit0.rx0_use_double_data_mode = "true",
cent_unit0.tx0_auto_spd_self_switch_enable = "false",
cent_unit0.tx0_channel_bonding = "x4",
cent_unit0.tx0_ph_fifo_reg_mode = "false",
cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
cent_unit0.tx0_use_double_data_mode = "true",
cent_unit0.tx0_wr_clk_mux_select = "core_clk",
cent_unit0.use_deskew_fifo = "false",
cent_unit0.vcceh_voltage = "3.0V",
cent_unit0.lpm_type = "stratixiv_hssi_cmu";
stratixiv_hssi_pll rx_cdr_pll0
(
.areset(rx_rxcruresetout[0]),
.clk(wire_rx_cdr_pll0_clk),
.datain(rx_pma_dataout[0]),
.dataout(wire_rx_cdr_pll0_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rxpll_dprioin[299:0]),
.dprioout(wire_rx_cdr_pll0_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[0]),
.freqlocked(wire_rx_cdr_pll0_freqlocked),
.inclk({rx_cruclk_in[9:0]}),
.locked(wire_rx_cdr_pll0_locked),
.locktorefclk(rx_pma_locktorefout[0]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[0]),
.rateswitch(int_pcie_sw[0]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll0.bandwidth_type = "Auto",
rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
rx_cdr_pll0.dprio_config_mode = 6'h00,
rx_cdr_pll0.effective_data_rate = "5000 Mbps",
rx_cdr_pll0.enable_dynamic_divider = "true",
rx_cdr_pll0.fast_lock_control = "false",
rx_cdr_pll0.inclk0_input_period = 10000,
rx_cdr_pll0.input_clock_frequency = "100.0 MHz",
rx_cdr_pll0.m = 25,
rx_cdr_pll0.n = 1,
rx_cdr_pll0.pfd_clk_select = 0,
rx_cdr_pll0.pll_type = "RX CDR",
rx_cdr_pll0.use_refclk_pin = "false",
rx_cdr_pll0.vco_post_scale = 1,
rx_cdr_pll0.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll1
(
.areset(rx_rxcruresetout[1]),
.clk(wire_rx_cdr_pll1_clk),
.datain(rx_pma_dataout[1]),
.dataout(wire_rx_cdr_pll1_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rxpll_dprioin[599:300]),
.dprioout(wire_rx_cdr_pll1_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[1]),
.freqlocked(wire_rx_cdr_pll1_freqlocked),
.inclk({rx_cruclk_in[19:10]}),
.locked(wire_rx_cdr_pll1_locked),
.locktorefclk(rx_pma_locktorefout[1]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll1_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[1]),
.rateswitch(int_pcie_sw[0]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll1.bandwidth_type = "Auto",
rx_cdr_pll1.channel_num = ((starting_channel_number + 1) % 4),
rx_cdr_pll1.dprio_config_mode = 6'h00,
rx_cdr_pll1.effective_data_rate = "5000 Mbps",
rx_cdr_pll1.enable_dynamic_divider = "true",
rx_cdr_pll1.fast_lock_control = "false",
rx_cdr_pll1.inclk0_input_period = 10000,
rx_cdr_pll1.input_clock_frequency = "100.0 MHz",
rx_cdr_pll1.m = 25,
rx_cdr_pll1.n = 1,
rx_cdr_pll1.pfd_clk_select = 0,
rx_cdr_pll1.pll_type = "RX CDR",
rx_cdr_pll1.use_refclk_pin = "false",
rx_cdr_pll1.vco_post_scale = 1,
rx_cdr_pll1.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll2
(
.areset(rx_rxcruresetout[2]),
.clk(wire_rx_cdr_pll2_clk),
.datain(rx_pma_dataout[2]),
.dataout(wire_rx_cdr_pll2_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rxpll_dprioin[899:600]),
.dprioout(wire_rx_cdr_pll2_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[2]),
.freqlocked(wire_rx_cdr_pll2_freqlocked),
.inclk({rx_cruclk_in[29:20]}),
.locked(wire_rx_cdr_pll2_locked),
.locktorefclk(rx_pma_locktorefout[2]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll2_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[2]),
.rateswitch(int_pcie_sw[0]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll2.bandwidth_type = "Auto",
rx_cdr_pll2.channel_num = ((starting_channel_number + 2) % 4),
rx_cdr_pll2.dprio_config_mode = 6'h00,
rx_cdr_pll2.effective_data_rate = "5000 Mbps",
rx_cdr_pll2.enable_dynamic_divider = "true",
rx_cdr_pll2.fast_lock_control = "false",
rx_cdr_pll2.inclk0_input_period = 10000,
rx_cdr_pll2.input_clock_frequency = "100.0 MHz",
rx_cdr_pll2.m = 25,
rx_cdr_pll2.n = 1,
rx_cdr_pll2.pfd_clk_select = 0,
rx_cdr_pll2.pll_type = "RX CDR",
rx_cdr_pll2.use_refclk_pin = "false",
rx_cdr_pll2.vco_post_scale = 1,
rx_cdr_pll2.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll3
(
.areset(rx_rxcruresetout[3]),
.clk(wire_rx_cdr_pll3_clk),
.datain(rx_pma_dataout[3]),
.dataout(wire_rx_cdr_pll3_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rxpll_dprioin[1199:900]),
.dprioout(wire_rx_cdr_pll3_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[3]),
.freqlocked(wire_rx_cdr_pll3_freqlocked),
.inclk({rx_cruclk_in[39:30]}),
.locked(wire_rx_cdr_pll3_locked),
.locktorefclk(rx_pma_locktorefout[3]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll3_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[3]),
.rateswitch(int_pcie_sw[0]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll3.bandwidth_type = "Auto",
rx_cdr_pll3.channel_num = ((starting_channel_number + 3) % 4),
rx_cdr_pll3.dprio_config_mode = 6'h00,
rx_cdr_pll3.effective_data_rate = "5000 Mbps",
rx_cdr_pll3.enable_dynamic_divider = "true",
rx_cdr_pll3.fast_lock_control = "false",
rx_cdr_pll3.inclk0_input_period = 10000,
rx_cdr_pll3.input_clock_frequency = "100.0 MHz",
rx_cdr_pll3.m = 25,
rx_cdr_pll3.n = 1,
rx_cdr_pll3.pfd_clk_select = 0,
rx_cdr_pll3.pll_type = "RX CDR",
rx_cdr_pll3.use_refclk_pin = "false",
rx_cdr_pll3.vco_post_scale = 1,
rx_cdr_pll3.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll tx_pll0
(
.areset(pllreset_in[0]),
.clk(wire_tx_pll0_clk),
.dataout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(pll0_dprioin[299:0]),
.dprioout(wire_tx_pll0_dprioout),
.freqlocked(),
.inclk({pll0_clkin[9:0]}),
.locked(wire_tx_pll0_locked),
.pfdfbclkout(),
.pfdrefclkout(),
.powerdown(pllpowerdn_in[0]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datain(1'b0),
.earlyeios(1'b0),
.extra10gin({6{1'b0}}),
.locktorefclk(1'b1),
.pfdfbclk(1'b0),
.rateswitch(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
tx_pll0.bandwidth_type = "High",
tx_pll0.channel_num = 4,
tx_pll0.dprio_config_mode = 6'h00,
tx_pll0.inclk0_input_period = 10000,
tx_pll0.input_clock_frequency = "100.0 MHz",
tx_pll0.logical_tx_pll_number = 0,
tx_pll0.m = 25,
tx_pll0.n = 1,
tx_pll0.pfd_clk_select = 0,
tx_pll0.pfd_fb_select = "internal",
tx_pll0.pll_type = "CMU",
tx_pll0.use_refclk_pin = "false",
tx_pll0.vco_post_scale = 1,
tx_pll0.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_rx_pcs receive_pcs0
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs0_autospdrateswitchout),
.autospdspdchgout(),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[2:0]),
.autospdxnspdchg(int_rx_autospdxnspdchg[2:0]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs0_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
.clkout(),
.coreclk(rx_coreclk_in[0]),
.coreclkout(wire_receive_pcs0_coreclkout),
.ctrldetect(wire_receive_pcs0_ctrldetect),
.datain(rx_pma_recoverdataout_wire[19:0]),
.dataout(wire_receive_pcs0_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[0]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[399:0]),
.dprioout(wire_receive_pcs0_dprioout),
.elecidleinfersel({3{1'b0}}),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[0]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[2:0]),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.iqpphfifobyteselout(),
.iqpphfifoptrsresetout(),
.iqpphfifordenableout(),
.iqpphfifowrclkout(),
.iqpphfifowrenableout(),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs0_patterndetect),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs0_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs0_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[0]),
.phfifordenableout(wire_receive_pcs0_phfifordenableout),
.phfiforeset(rx_phfiforeset[0]),
.phfiforesetout(wire_receive_pcs0_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[0]),
.phfifowrdisableout(wire_receive_pcs0_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[2:0]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[2:0]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[2:0]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[2:0]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[2:0]),
.pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
.pipebufferstat(),
.pipedatavalid(wire_receive_pcs0_pipedatavalid),
.pipeelecidle(wire_receive_pcs0_pipeelecidle),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[0]),
.pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
.pipepowerdown(tx_pipepowerdownout[1:0]),
.pipepowerstate(tx_pipepowerstateout[3:0]),
.pipestatetransdoneout(wire_receive_pcs0_pipestatetransdoneout),
.pipestatus(wire_receive_pcs0_pipestatus),
.powerdn(powerdn[1:0]),
.prbscidenable(rx_prbscidenable[0]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitch(rateswitch[0]),
.rateswitchout(wire_receive_pcs0_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[0]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[0]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[0]),
.rxfound(rx_pcs_rxfound_wire[1:0]),
.signaldetect(wire_receive_pcs0_signaldetect),
.signaldetected(rx_signaldetect_wire[0]),
.syncstatus(wire_receive_pcs0_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.hiprateswitch(1'b0),
.iqpautospdxnspgchg({2{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnptrsreset({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrclk({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pmatestbusin({8{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs0.align_pattern = "0101111100",
receive_pcs0.align_pattern_length = 10,
receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs0.allow_align_polarity_inversion = "false",
receive_pcs0.allow_pipe_polarity_inversion = "true",
receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs0.auto_spd_phystatus_notify_count = 14,
receive_pcs0.auto_spd_self_switch_enable = "false",
receive_pcs0.bit_slip_enable = "false",
receive_pcs0.byte_order_double_data_mode_mask_enable = "false",
receive_pcs0.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs0.byte_order_mode = "none",
receive_pcs0.byte_order_pad_pattern = "0",
receive_pcs0.byte_order_pattern = "0",
receive_pcs0.byte_order_pld_ctrl_enable = "false",
receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs0.cdrctrl_cid_mode_enable = "true",
receive_pcs0.cdrctrl_enable = "true",
receive_pcs0.cdrctrl_rxvalid_mask = "true",
receive_pcs0.channel_bonding = "x4",
receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
receive_pcs0.channel_width = 16,
receive_pcs0.clk1_mux_select = "recovered clock",
receive_pcs0.clk2_mux_select = "digital reference clock",
receive_pcs0.core_clock_0ppm = "false",
receive_pcs0.datapath_low_latency_mode = "false",
receive_pcs0.datapath_protocol = "pipe",
receive_pcs0.dec_8b_10b_compatibility_mode = "true",
receive_pcs0.dec_8b_10b_mode = "normal",
receive_pcs0.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs0.deskew_pattern = "0",
receive_pcs0.disable_auto_idle_insertion = "false",
receive_pcs0.disable_running_disp_in_word_align = "false",
receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs0.dprio_config_mode = 6'h01,
receive_pcs0.elec_idle_gen1_sigdet_enable = "true",
receive_pcs0.elec_idle_infer_enable = "false",
receive_pcs0.elec_idle_num_com_detect = 3,
receive_pcs0.enable_bit_reversal = "false",
receive_pcs0.enable_deep_align = "false",
receive_pcs0.enable_deep_align_byte_swap = "false",
receive_pcs0.enable_self_test_mode = "false",
receive_pcs0.enable_true_complement_match_in_word_align = "false",
receive_pcs0.force_signal_detect_dig = "true",
receive_pcs0.hip_enable = "false",
receive_pcs0.infiniband_invalid_code = 0,
receive_pcs0.insert_pad_on_underflow = "false",
receive_pcs0.logical_channel_address = (starting_channel_number + 0),
receive_pcs0.num_align_code_groups_in_ordered_set = 0,
receive_pcs0.num_align_cons_good_data = 16,
receive_pcs0.num_align_cons_pat = 4,
receive_pcs0.num_align_loss_sync_error = 17,
receive_pcs0.ph_fifo_low_latency_enable = "true",
receive_pcs0.ph_fifo_reg_mode = "false",
receive_pcs0.ph_fifo_xn_mapping0 = "none",
receive_pcs0.ph_fifo_xn_mapping1 = "none",
receive_pcs0.ph_fifo_xn_mapping2 = "central",
receive_pcs0.ph_fifo_xn_select = 2,
receive_pcs0.pipe_auto_speed_nego_enable = "true",
receive_pcs0.pipe_freq_scale_mode = "Frequency",
receive_pcs0.pma_done_count = 249950,
receive_pcs0.protocol_hint = "pcie2",
receive_pcs0.rate_match_almost_empty_threshold = 11,
receive_pcs0.rate_match_almost_full_threshold = 13,
receive_pcs0.rate_match_back_to_back = "false",
receive_pcs0.rate_match_delete_threshold = 13,
receive_pcs0.rate_match_empty_threshold = 5,
receive_pcs0.rate_match_fifo_mode = "true",
receive_pcs0.rate_match_full_threshold = 20,
receive_pcs0.rate_match_insert_threshold = 11,
receive_pcs0.rate_match_ordered_set_based = "false",
receive_pcs0.rate_match_pattern1 = "11010000111010000011",
receive_pcs0.rate_match_pattern2 = "00101111000101111100",
receive_pcs0.rate_match_pattern_size = 20,
receive_pcs0.rate_match_pipe_enable = "true",
receive_pcs0.rate_match_reset_enable = "false",
receive_pcs0.rate_match_skip_set_based = "true",
receive_pcs0.rate_match_start_threshold = 7,
receive_pcs0.rd_clk_mux_select = "core clock",
receive_pcs0.recovered_clk_mux_select = "recovered clock",
receive_pcs0.run_length = 40,
receive_pcs0.run_length_enable = "true",
receive_pcs0.rx_detect_bypass = "false",
receive_pcs0.rx_phfifo_wait_cnt = 32,
receive_pcs0.rxstatus_error_report_mode = 1,
receive_pcs0.self_test_mode = "incremental",
receive_pcs0.test_bus_sel = 10,
receive_pcs0.use_alignment_state_machine = "true",
receive_pcs0.use_deserializer_double_data_mode = "false",
receive_pcs0.use_deskew_fifo = "false",
receive_pcs0.use_double_data_mode = "true",
receive_pcs0.use_parallel_loopback = "false",
receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
receive_pcs0.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs1
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs1_autospdrateswitchout),
.autospdspdchgout(),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[5:3]),
.autospdxnspdchg(int_rx_autospdxnspdchg[5:3]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs1_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs1_cdrctrllocktorefclkout),
.clkout(),
.coreclk(rx_coreclk_in[1]),
.coreclkout(wire_receive_pcs1_coreclkout),
.ctrldetect(wire_receive_pcs1_ctrldetect),
.datain(rx_pma_recoverdataout_wire[39:20]),
.dataout(wire_receive_pcs1_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[1]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[799:400]),
.dprioout(wire_receive_pcs1_dprioout),
.elecidleinfersel({3{1'b0}}),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[1]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[5:3]),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.iqpphfifobyteselout(),
.iqpphfifoptrsresetout(),
.iqpphfifordenableout(),
.iqpphfifowrclkout(),
.iqpphfifowrenableout(),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs1_patterndetect),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs1_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs1_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[1]),
.phfifordenableout(wire_receive_pcs1_phfifordenableout),
.phfiforeset(rx_phfiforeset[1]),
.phfiforesetout(wire_receive_pcs1_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[1]),
.phfifowrdisableout(wire_receive_pcs1_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[5:3]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[5:3]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[5:3]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[5:3]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[5:3]),
.pipe8b10binvpolarity(pipe8b10binvpolarity[1]),
.pipebufferstat(),
.pipedatavalid(wire_receive_pcs1_pipedatavalid),
.pipeelecidle(wire_receive_pcs1_pipeelecidle),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[1]),
.pipephydonestatus(wire_receive_pcs1_pipephydonestatus),
.pipepowerdown(tx_pipepowerdownout[3:2]),
.pipepowerstate(tx_pipepowerstateout[7:4]),
.pipestatetransdoneout(wire_receive_pcs1_pipestatetransdoneout),
.pipestatus(wire_receive_pcs1_pipestatus),
.powerdn(powerdn[3:2]),
.prbscidenable(rx_prbscidenable[1]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitch(rateswitch[0]),
.rateswitchout(wire_receive_pcs1_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[1]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs1_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[1]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[1]),
.rxfound(rx_pcs_rxfound_wire[3:2]),
.signaldetect(wire_receive_pcs1_signaldetect),
.signaldetected(rx_signaldetect_wire[1]),
.syncstatus(wire_receive_pcs1_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.hiprateswitch(1'b0),
.iqpautospdxnspgchg({2{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnptrsreset({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrclk({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pmatestbusin({8{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs1.align_pattern = "0101111100",
receive_pcs1.align_pattern_length = 10,
receive_pcs1.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs1.allow_align_polarity_inversion = "false",
receive_pcs1.allow_pipe_polarity_inversion = "true",
receive_pcs1.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs1.auto_spd_phystatus_notify_count = 14,
receive_pcs1.auto_spd_self_switch_enable = "false",
receive_pcs1.bit_slip_enable = "false",
receive_pcs1.byte_order_double_data_mode_mask_enable = "false",
receive_pcs1.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs1.byte_order_mode = "none",
receive_pcs1.byte_order_pad_pattern = "0",
receive_pcs1.byte_order_pattern = "0",
receive_pcs1.byte_order_pld_ctrl_enable = "false",
receive_pcs1.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs1.cdrctrl_cid_mode_enable = "true",
receive_pcs1.cdrctrl_enable = "true",
receive_pcs1.cdrctrl_rxvalid_mask = "true",
receive_pcs1.channel_bonding = "x4",
receive_pcs1.channel_number = ((starting_channel_number + 1) % 4),
receive_pcs1.channel_width = 16,
receive_pcs1.clk1_mux_select = "recovered clock",
receive_pcs1.clk2_mux_select = "digital reference clock",
receive_pcs1.core_clock_0ppm = "false",
receive_pcs1.datapath_low_latency_mode = "false",
receive_pcs1.datapath_protocol = "pipe",
receive_pcs1.dec_8b_10b_compatibility_mode = "true",
receive_pcs1.dec_8b_10b_mode = "normal",
receive_pcs1.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs1.deskew_pattern = "0",
receive_pcs1.disable_auto_idle_insertion = "false",
receive_pcs1.disable_running_disp_in_word_align = "false",
receive_pcs1.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs1.dprio_config_mode = 6'h01,
receive_pcs1.elec_idle_gen1_sigdet_enable = "true",
receive_pcs1.elec_idle_infer_enable = "false",
receive_pcs1.elec_idle_num_com_detect = 3,
receive_pcs1.enable_bit_reversal = "false",
receive_pcs1.enable_deep_align = "false",
receive_pcs1.enable_deep_align_byte_swap = "false",
receive_pcs1.enable_self_test_mode = "false",
receive_pcs1.enable_true_complement_match_in_word_align = "false",
receive_pcs1.force_signal_detect_dig = "true",
receive_pcs1.hip_enable = "false",
receive_pcs1.infiniband_invalid_code = 0,
receive_pcs1.insert_pad_on_underflow = "false",
receive_pcs1.logical_channel_address = (starting_channel_number + 1),
receive_pcs1.num_align_code_groups_in_ordered_set = 0,
receive_pcs1.num_align_cons_good_data = 16,
receive_pcs1.num_align_cons_pat = 4,
receive_pcs1.num_align_loss_sync_error = 17,
receive_pcs1.ph_fifo_low_latency_enable = "true",
receive_pcs1.ph_fifo_reg_mode = "false",
receive_pcs1.ph_fifo_xn_mapping0 = "none",
receive_pcs1.ph_fifo_xn_mapping1 = "none",
receive_pcs1.ph_fifo_xn_mapping2 = "central",
receive_pcs1.ph_fifo_xn_select = 2,
receive_pcs1.pipe_auto_speed_nego_enable = "true",
receive_pcs1.pipe_freq_scale_mode = "Frequency",
receive_pcs1.pma_done_count = 249950,
receive_pcs1.protocol_hint = "pcie2",
receive_pcs1.rate_match_almost_empty_threshold = 11,
receive_pcs1.rate_match_almost_full_threshold = 13,
receive_pcs1.rate_match_back_to_back = "false",
receive_pcs1.rate_match_delete_threshold = 13,
receive_pcs1.rate_match_empty_threshold = 5,
receive_pcs1.rate_match_fifo_mode = "true",
receive_pcs1.rate_match_full_threshold = 20,
receive_pcs1.rate_match_insert_threshold = 11,
receive_pcs1.rate_match_ordered_set_based = "false",
receive_pcs1.rate_match_pattern1 = "11010000111010000011",
receive_pcs1.rate_match_pattern2 = "00101111000101111100",
receive_pcs1.rate_match_pattern_size = 20,
receive_pcs1.rate_match_pipe_enable = "true",
receive_pcs1.rate_match_reset_enable = "false",
receive_pcs1.rate_match_skip_set_based = "true",
receive_pcs1.rate_match_start_threshold = 7,
receive_pcs1.rd_clk_mux_select = "core clock",
receive_pcs1.recovered_clk_mux_select = "recovered clock",
receive_pcs1.run_length = 40,
receive_pcs1.run_length_enable = "true",
receive_pcs1.rx_detect_bypass = "false",
receive_pcs1.rx_phfifo_wait_cnt = 32,
receive_pcs1.rxstatus_error_report_mode = 1,
receive_pcs1.self_test_mode = "incremental",
receive_pcs1.test_bus_sel = 10,
receive_pcs1.use_alignment_state_machine = "true",
receive_pcs1.use_deserializer_double_data_mode = "false",
receive_pcs1.use_deskew_fifo = "false",
receive_pcs1.use_double_data_mode = "true",
receive_pcs1.use_parallel_loopback = "false",
receive_pcs1.use_rising_edge_triggered_pattern_align = "false",
receive_pcs1.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs2
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs2_autospdrateswitchout),
.autospdspdchgout(),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[8:6]),
.autospdxnspdchg(int_rx_autospdxnspdchg[8:6]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs2_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs2_cdrctrllocktorefclkout),
.clkout(),
.coreclk(rx_coreclk_in[2]),
.coreclkout(wire_receive_pcs2_coreclkout),
.ctrldetect(wire_receive_pcs2_ctrldetect),
.datain(rx_pma_recoverdataout_wire[59:40]),
.dataout(wire_receive_pcs2_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[2]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[1199:800]),
.dprioout(wire_receive_pcs2_dprioout),
.elecidleinfersel({3{1'b0}}),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[2]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[8:6]),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.iqpphfifobyteselout(),
.iqpphfifoptrsresetout(),
.iqpphfifordenableout(),
.iqpphfifowrclkout(),
.iqpphfifowrenableout(),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs2_patterndetect),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs2_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs2_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[2]),
.phfifordenableout(wire_receive_pcs2_phfifordenableout),
.phfiforeset(rx_phfiforeset[2]),
.phfiforesetout(wire_receive_pcs2_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[2]),
.phfifowrdisableout(wire_receive_pcs2_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[8:6]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[8:6]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[8:6]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[8:6]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[8:6]),
.pipe8b10binvpolarity(pipe8b10binvpolarity[2]),
.pipebufferstat(),
.pipedatavalid(wire_receive_pcs2_pipedatavalid),
.pipeelecidle(wire_receive_pcs2_pipeelecidle),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[2]),
.pipephydonestatus(wire_receive_pcs2_pipephydonestatus),
.pipepowerdown(tx_pipepowerdownout[5:4]),
.pipepowerstate(tx_pipepowerstateout[11:8]),
.pipestatetransdoneout(wire_receive_pcs2_pipestatetransdoneout),
.pipestatus(wire_receive_pcs2_pipestatus),
.powerdn(powerdn[5:4]),
.prbscidenable(rx_prbscidenable[2]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitch(rateswitch[0]),
.rateswitchout(wire_receive_pcs2_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[2]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs2_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[2]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[2]),
.rxfound(rx_pcs_rxfound_wire[5:4]),
.signaldetect(wire_receive_pcs2_signaldetect),
.signaldetected(rx_signaldetect_wire[2]),
.syncstatus(wire_receive_pcs2_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.hiprateswitch(1'b0),
.iqpautospdxnspgchg({2{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnptrsreset({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrclk({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pmatestbusin({8{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs2.align_pattern = "0101111100",
receive_pcs2.align_pattern_length = 10,
receive_pcs2.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs2.allow_align_polarity_inversion = "false",
receive_pcs2.allow_pipe_polarity_inversion = "true",
receive_pcs2.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs2.auto_spd_phystatus_notify_count = 14,
receive_pcs2.auto_spd_self_switch_enable = "false",
receive_pcs2.bit_slip_enable = "false",
receive_pcs2.byte_order_double_data_mode_mask_enable = "false",
receive_pcs2.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs2.byte_order_mode = "none",
receive_pcs2.byte_order_pad_pattern = "0",
receive_pcs2.byte_order_pattern = "0",
receive_pcs2.byte_order_pld_ctrl_enable = "false",
receive_pcs2.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs2.cdrctrl_cid_mode_enable = "true",
receive_pcs2.cdrctrl_enable = "true",
receive_pcs2.cdrctrl_rxvalid_mask = "true",
receive_pcs2.channel_bonding = "x4",
receive_pcs2.channel_number = ((starting_channel_number + 2) % 4),
receive_pcs2.channel_width = 16,
receive_pcs2.clk1_mux_select = "recovered clock",
receive_pcs2.clk2_mux_select = "digital reference clock",
receive_pcs2.core_clock_0ppm = "false",
receive_pcs2.datapath_low_latency_mode = "false",
receive_pcs2.datapath_protocol = "pipe",
receive_pcs2.dec_8b_10b_compatibility_mode = "true",
receive_pcs2.dec_8b_10b_mode = "normal",
receive_pcs2.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs2.deskew_pattern = "0",
receive_pcs2.disable_auto_idle_insertion = "false",
receive_pcs2.disable_running_disp_in_word_align = "false",
receive_pcs2.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs2.dprio_config_mode = 6'h01,
receive_pcs2.elec_idle_gen1_sigdet_enable = "true",
receive_pcs2.elec_idle_infer_enable = "false",
receive_pcs2.elec_idle_num_com_detect = 3,
receive_pcs2.enable_bit_reversal = "false",
receive_pcs2.enable_deep_align = "false",
receive_pcs2.enable_deep_align_byte_swap = "false",
receive_pcs2.enable_self_test_mode = "false",
receive_pcs2.enable_true_complement_match_in_word_align = "false",
receive_pcs2.force_signal_detect_dig = "true",
receive_pcs2.hip_enable = "false",
receive_pcs2.infiniband_invalid_code = 0,
receive_pcs2.insert_pad_on_underflow = "false",
receive_pcs2.logical_channel_address = (starting_channel_number + 2),
receive_pcs2.num_align_code_groups_in_ordered_set = 0,
receive_pcs2.num_align_cons_good_data = 16,
receive_pcs2.num_align_cons_pat = 4,
receive_pcs2.num_align_loss_sync_error = 17,
receive_pcs2.ph_fifo_low_latency_enable = "true",
receive_pcs2.ph_fifo_reg_mode = "false",
receive_pcs2.ph_fifo_xn_mapping0 = "none",
receive_pcs2.ph_fifo_xn_mapping1 = "none",
receive_pcs2.ph_fifo_xn_mapping2 = "central",
receive_pcs2.ph_fifo_xn_select = 2,
receive_pcs2.pipe_auto_speed_nego_enable = "true",
receive_pcs2.pipe_freq_scale_mode = "Frequency",
receive_pcs2.pma_done_count = 249950,
receive_pcs2.protocol_hint = "pcie2",
receive_pcs2.rate_match_almost_empty_threshold = 11,
receive_pcs2.rate_match_almost_full_threshold = 13,
receive_pcs2.rate_match_back_to_back = "false",
receive_pcs2.rate_match_delete_threshold = 13,
receive_pcs2.rate_match_empty_threshold = 5,
receive_pcs2.rate_match_fifo_mode = "true",
receive_pcs2.rate_match_full_threshold = 20,
receive_pcs2.rate_match_insert_threshold = 11,
receive_pcs2.rate_match_ordered_set_based = "false",
receive_pcs2.rate_match_pattern1 = "11010000111010000011",
receive_pcs2.rate_match_pattern2 = "00101111000101111100",
receive_pcs2.rate_match_pattern_size = 20,
receive_pcs2.rate_match_pipe_enable = "true",
receive_pcs2.rate_match_reset_enable = "false",
receive_pcs2.rate_match_skip_set_based = "true",
receive_pcs2.rate_match_start_threshold = 7,
receive_pcs2.rd_clk_mux_select = "core clock",
receive_pcs2.recovered_clk_mux_select = "recovered clock",
receive_pcs2.run_length = 40,
receive_pcs2.run_length_enable = "true",
receive_pcs2.rx_detect_bypass = "false",
receive_pcs2.rx_phfifo_wait_cnt = 32,
receive_pcs2.rxstatus_error_report_mode = 1,
receive_pcs2.self_test_mode = "incremental",
receive_pcs2.test_bus_sel = 10,
receive_pcs2.use_alignment_state_machine = "true",
receive_pcs2.use_deserializer_double_data_mode = "false",
receive_pcs2.use_deskew_fifo = "false",
receive_pcs2.use_double_data_mode = "true",
receive_pcs2.use_parallel_loopback = "false",
receive_pcs2.use_rising_edge_triggered_pattern_align = "false",
receive_pcs2.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs3
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs3_autospdrateswitchout),
.autospdspdchgout(),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[11:9]),
.autospdxnspdchg(int_rx_autospdxnspdchg[11:9]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs3_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs3_cdrctrllocktorefclkout),
.clkout(),
.coreclk(rx_coreclk_in[3]),
.coreclkout(wire_receive_pcs3_coreclkout),
.ctrldetect(wire_receive_pcs3_ctrldetect),
.datain(rx_pma_recoverdataout_wire[79:60]),
.dataout(wire_receive_pcs3_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[3]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[1599:1200]),
.dprioout(wire_receive_pcs3_dprioout),
.elecidleinfersel({3{1'b0}}),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[3]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[11:9]),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.iqpphfifobyteselout(),
.iqpphfifoptrsresetout(),
.iqpphfifordenableout(),
.iqpphfifowrclkout(),
.iqpphfifowrenableout(),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs3_patterndetect),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs3_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs3_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[3]),
.phfifordenableout(wire_receive_pcs3_phfifordenableout),
.phfiforeset(rx_phfiforeset[3]),
.phfiforesetout(wire_receive_pcs3_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[3]),
.phfifowrdisableout(wire_receive_pcs3_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[11:9]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[11:9]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[11:9]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[11:9]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[11:9]),
.pipe8b10binvpolarity(pipe8b10binvpolarity[3]),
.pipebufferstat(),
.pipedatavalid(wire_receive_pcs3_pipedatavalid),
.pipeelecidle(wire_receive_pcs3_pipeelecidle),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[3]),
.pipephydonestatus(wire_receive_pcs3_pipephydonestatus),
.pipepowerdown(tx_pipepowerdownout[7:6]),
.pipepowerstate(tx_pipepowerstateout[15:12]),
.pipestatetransdoneout(wire_receive_pcs3_pipestatetransdoneout),
.pipestatus(wire_receive_pcs3_pipestatus),
.powerdn(powerdn[7:6]),
.prbscidenable(rx_prbscidenable[3]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitch(rateswitch[0]),
.rateswitchout(wire_receive_pcs3_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[3]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs3_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[3]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[3]),
.rxfound(rx_pcs_rxfound_wire[7:6]),
.signaldetect(wire_receive_pcs3_signaldetect),
.signaldetected(rx_signaldetect_wire[3]),
.syncstatus(wire_receive_pcs3_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.hiprateswitch(1'b0),
.iqpautospdxnspgchg({2{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnptrsreset({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrclk({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pmatestbusin({8{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs3.align_pattern = "0101111100",
receive_pcs3.align_pattern_length = 10,
receive_pcs3.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs3.allow_align_polarity_inversion = "false",
receive_pcs3.allow_pipe_polarity_inversion = "true",
receive_pcs3.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs3.auto_spd_phystatus_notify_count = 14,
receive_pcs3.auto_spd_self_switch_enable = "false",
receive_pcs3.bit_slip_enable = "false",
receive_pcs3.byte_order_double_data_mode_mask_enable = "false",
receive_pcs3.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs3.byte_order_mode = "none",
receive_pcs3.byte_order_pad_pattern = "0",
receive_pcs3.byte_order_pattern = "0",
receive_pcs3.byte_order_pld_ctrl_enable = "false",
receive_pcs3.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs3.cdrctrl_cid_mode_enable = "true",
receive_pcs3.cdrctrl_enable = "true",
receive_pcs3.cdrctrl_rxvalid_mask = "true",
receive_pcs3.channel_bonding = "x4",
receive_pcs3.channel_number = ((starting_channel_number + 3) % 4),
receive_pcs3.channel_width = 16,
receive_pcs3.clk1_mux_select = "recovered clock",
receive_pcs3.clk2_mux_select = "digital reference clock",
receive_pcs3.core_clock_0ppm = "false",
receive_pcs3.datapath_low_latency_mode = "false",
receive_pcs3.datapath_protocol = "pipe",
receive_pcs3.dec_8b_10b_compatibility_mode = "true",
receive_pcs3.dec_8b_10b_mode = "normal",
receive_pcs3.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs3.deskew_pattern = "0",
receive_pcs3.disable_auto_idle_insertion = "false",
receive_pcs3.disable_running_disp_in_word_align = "false",
receive_pcs3.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs3.dprio_config_mode = 6'h01,
receive_pcs3.elec_idle_gen1_sigdet_enable = "true",
receive_pcs3.elec_idle_infer_enable = "false",
receive_pcs3.elec_idle_num_com_detect = 3,
receive_pcs3.enable_bit_reversal = "false",
receive_pcs3.enable_deep_align = "false",
receive_pcs3.enable_deep_align_byte_swap = "false",
receive_pcs3.enable_self_test_mode = "false",
receive_pcs3.enable_true_complement_match_in_word_align = "false",
receive_pcs3.force_signal_detect_dig = "true",
receive_pcs3.hip_enable = "false",
receive_pcs3.infiniband_invalid_code = 0,
receive_pcs3.insert_pad_on_underflow = "false",
receive_pcs3.logical_channel_address = (starting_channel_number + 3),
receive_pcs3.num_align_code_groups_in_ordered_set = 0,
receive_pcs3.num_align_cons_good_data = 16,
receive_pcs3.num_align_cons_pat = 4,
receive_pcs3.num_align_loss_sync_error = 17,
receive_pcs3.ph_fifo_low_latency_enable = "true",
receive_pcs3.ph_fifo_reg_mode = "false",
receive_pcs3.ph_fifo_xn_mapping0 = "none",
receive_pcs3.ph_fifo_xn_mapping1 = "none",
receive_pcs3.ph_fifo_xn_mapping2 = "central",
receive_pcs3.ph_fifo_xn_select = 2,
receive_pcs3.pipe_auto_speed_nego_enable = "true",
receive_pcs3.pipe_freq_scale_mode = "Frequency",
receive_pcs3.pma_done_count = 249950,
receive_pcs3.protocol_hint = "pcie2",
receive_pcs3.rate_match_almost_empty_threshold = 11,
receive_pcs3.rate_match_almost_full_threshold = 13,
receive_pcs3.rate_match_back_to_back = "false",
receive_pcs3.rate_match_delete_threshold = 13,
receive_pcs3.rate_match_empty_threshold = 5,
receive_pcs3.rate_match_fifo_mode = "true",
receive_pcs3.rate_match_full_threshold = 20,
receive_pcs3.rate_match_insert_threshold = 11,
receive_pcs3.rate_match_ordered_set_based = "false",
receive_pcs3.rate_match_pattern1 = "11010000111010000011",
receive_pcs3.rate_match_pattern2 = "00101111000101111100",
receive_pcs3.rate_match_pattern_size = 20,
receive_pcs3.rate_match_pipe_enable = "true",
receive_pcs3.rate_match_reset_enable = "false",
receive_pcs3.rate_match_skip_set_based = "true",
receive_pcs3.rate_match_start_threshold = 7,
receive_pcs3.rd_clk_mux_select = "core clock",
receive_pcs3.recovered_clk_mux_select = "recovered clock",
receive_pcs3.run_length = 40,
receive_pcs3.run_length_enable = "true",
receive_pcs3.rx_detect_bypass = "false",
receive_pcs3.rx_phfifo_wait_cnt = 32,
receive_pcs3.rxstatus_error_report_mode = 1,
receive_pcs3.self_test_mode = "incremental",
receive_pcs3.test_bus_sel = 10,
receive_pcs3.use_alignment_state_machine = "true",
receive_pcs3.use_deserializer_double_data_mode = "false",
receive_pcs3.use_deskew_fifo = "false",
receive_pcs3.use_double_data_mode = "true",
receive_pcs3.use_parallel_loopback = "false",
receive_pcs3.use_rising_edge_triggered_pattern_align = "false",
receive_pcs3.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pma receive_pma0
(
.adaptdone(),
.analogtestbus(wire_receive_pma0_analogtestbus),
.clockout(wire_receive_pma0_clockout),
.datain(rx_datain[0]),
.dataout(wire_receive_pma0_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[3:0]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[299:0]),
.dprioout(wire_receive_pma0_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[0]),
.locktoref(rx_locktorefclk_wire[0]),
.locktorefout(wire_receive_pma0_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[0]),
.powerdn(cent_unit_rxibpowerdn[0]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
.recoverdatain(pll_ch_dataout_wire[1:0]),
.recoverdataout(wire_receive_pma0_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[0]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma0_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma0.adaptive_equalization_mode = "none",
receive_pma0.allow_serial_loopback = "false",
receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
receive_pma0.channel_type = "auto",
receive_pma0.common_mode = "0.82V",
receive_pma0.deserialization_factor = 10,
receive_pma0.dprio_config_mode = 6'h01,
receive_pma0.enable_ltd = "false",
receive_pma0.enable_ltr = "true",
receive_pma0.eq_dc_gain = 3,
receive_pma0.eqa_ctrl = 0,
receive_pma0.eqb_ctrl = 0,
receive_pma0.eqc_ctrl = 0,
receive_pma0.eqd_ctrl = 0,
receive_pma0.eqv_ctrl = 0,
receive_pma0.eyemon_bandwidth = 0,
receive_pma0.force_signal_detect = "true",
receive_pma0.logical_channel_address = (starting_channel_number + 0),
receive_pma0.low_speed_test_select = 0,
receive_pma0.offset_cancellation = 1,
receive_pma0.ppmselect = 32,
receive_pma0.protocol_hint = "pcie2",
receive_pma0.send_direct_reverse_serial_loopback = "None",
receive_pma0.signal_detect_hysteresis = 4,
receive_pma0.signal_detect_hysteresis_valid_threshold = 14,
receive_pma0.signal_detect_loss_threshold = 3,
receive_pma0.termination = "OCT 100 Ohms",
receive_pma0.use_deser_double_data_width = "false",
receive_pma0.use_external_termination = "false",
receive_pma0.use_pma_direct = "false",
receive_pma0.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma1
(
.adaptdone(),
.analogtestbus(wire_receive_pma1_analogtestbus),
.clockout(wire_receive_pma1_clockout),
.datain(rx_datain[1]),
.dataout(wire_receive_pma1_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[7:4]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[599:300]),
.dprioout(wire_receive_pma1_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[1]),
.locktoref(rx_locktorefclk_wire[1]),
.locktorefout(wire_receive_pma1_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[1]),
.powerdn(cent_unit_rxibpowerdn[1]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[1]),
.recoverdatain(pll_ch_dataout_wire[3:2]),
.recoverdataout(wire_receive_pma1_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[1]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma1_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma1.adaptive_equalization_mode = "none",
receive_pma1.allow_serial_loopback = "false",
receive_pma1.channel_number = ((starting_channel_number + 1) % 4),
receive_pma1.channel_type = "auto",
receive_pma1.common_mode = "0.82V",
receive_pma1.deserialization_factor = 10,
receive_pma1.dprio_config_mode = 6'h01,
receive_pma1.enable_ltd = "false",
receive_pma1.enable_ltr = "true",
receive_pma1.eq_dc_gain = 3,
receive_pma1.eqa_ctrl = 0,
receive_pma1.eqb_ctrl = 0,
receive_pma1.eqc_ctrl = 0,
receive_pma1.eqd_ctrl = 0,
receive_pma1.eqv_ctrl = 0,
receive_pma1.eyemon_bandwidth = 0,
receive_pma1.force_signal_detect = "true",
receive_pma1.logical_channel_address = (starting_channel_number + 1),
receive_pma1.low_speed_test_select = 0,
receive_pma1.offset_cancellation = 1,
receive_pma1.ppmselect = 32,
receive_pma1.protocol_hint = "pcie2",
receive_pma1.send_direct_reverse_serial_loopback = "None",
receive_pma1.signal_detect_hysteresis = 4,
receive_pma1.signal_detect_hysteresis_valid_threshold = 14,
receive_pma1.signal_detect_loss_threshold = 3,
receive_pma1.termination = "OCT 100 Ohms",
receive_pma1.use_deser_double_data_width = "false",
receive_pma1.use_external_termination = "false",
receive_pma1.use_pma_direct = "false",
receive_pma1.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma2
(
.adaptdone(),
.analogtestbus(wire_receive_pma2_analogtestbus),
.clockout(wire_receive_pma2_clockout),
.datain(rx_datain[2]),
.dataout(wire_receive_pma2_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[11:8]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[899:600]),
.dprioout(wire_receive_pma2_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[2]),
.locktoref(rx_locktorefclk_wire[2]),
.locktorefout(wire_receive_pma2_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[2]),
.powerdn(cent_unit_rxibpowerdn[2]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[2]),
.recoverdatain(pll_ch_dataout_wire[5:4]),
.recoverdataout(wire_receive_pma2_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[2]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma2_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma2.adaptive_equalization_mode = "none",
receive_pma2.allow_serial_loopback = "false",
receive_pma2.channel_number = ((starting_channel_number + 2) % 4),
receive_pma2.channel_type = "auto",
receive_pma2.common_mode = "0.82V",
receive_pma2.deserialization_factor = 10,
receive_pma2.dprio_config_mode = 6'h01,
receive_pma2.enable_ltd = "false",
receive_pma2.enable_ltr = "true",
receive_pma2.eq_dc_gain = 3,
receive_pma2.eqa_ctrl = 0,
receive_pma2.eqb_ctrl = 0,
receive_pma2.eqc_ctrl = 0,
receive_pma2.eqd_ctrl = 0,
receive_pma2.eqv_ctrl = 0,
receive_pma2.eyemon_bandwidth = 0,
receive_pma2.force_signal_detect = "true",
receive_pma2.logical_channel_address = (starting_channel_number + 2),
receive_pma2.low_speed_test_select = 0,
receive_pma2.offset_cancellation = 1,
receive_pma2.ppmselect = 32,
receive_pma2.protocol_hint = "pcie2",
receive_pma2.send_direct_reverse_serial_loopback = "None",
receive_pma2.signal_detect_hysteresis = 4,
receive_pma2.signal_detect_hysteresis_valid_threshold = 14,
receive_pma2.signal_detect_loss_threshold = 3,
receive_pma2.termination = "OCT 100 Ohms",
receive_pma2.use_deser_double_data_width = "false",
receive_pma2.use_external_termination = "false",
receive_pma2.use_pma_direct = "false",
receive_pma2.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma3
(
.adaptdone(),
.analogtestbus(wire_receive_pma3_analogtestbus),
.clockout(wire_receive_pma3_clockout),
.datain(rx_datain[3]),
.dataout(wire_receive_pma3_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[15:12]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[1199:900]),
.dprioout(wire_receive_pma3_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[3]),
.locktoref(rx_locktorefclk_wire[3]),
.locktorefout(wire_receive_pma3_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[3]),
.powerdn(cent_unit_rxibpowerdn[3]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[3]),
.recoverdatain(pll_ch_dataout_wire[7:6]),
.recoverdataout(wire_receive_pma3_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[3]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma3_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma3.adaptive_equalization_mode = "none",
receive_pma3.allow_serial_loopback = "false",
receive_pma3.channel_number = ((starting_channel_number + 3) % 4),
receive_pma3.channel_type = "auto",
receive_pma3.common_mode = "0.82V",
receive_pma3.deserialization_factor = 10,
receive_pma3.dprio_config_mode = 6'h01,
receive_pma3.enable_ltd = "false",
receive_pma3.enable_ltr = "true",
receive_pma3.eq_dc_gain = 3,
receive_pma3.eqa_ctrl = 0,
receive_pma3.eqb_ctrl = 0,
receive_pma3.eqc_ctrl = 0,
receive_pma3.eqd_ctrl = 0,
receive_pma3.eqv_ctrl = 0,
receive_pma3.eyemon_bandwidth = 0,
receive_pma3.force_signal_detect = "true",
receive_pma3.logical_channel_address = (starting_channel_number + 3),
receive_pma3.low_speed_test_select = 0,
receive_pma3.offset_cancellation = 1,
receive_pma3.ppmselect = 32,
receive_pma3.protocol_hint = "pcie2",
receive_pma3.send_direct_reverse_serial_loopback = "None",
receive_pma3.signal_detect_hysteresis = 4,
receive_pma3.signal_detect_hysteresis_valid_threshold = 14,
receive_pma3.signal_detect_loss_threshold = 3,
receive_pma3.termination = "OCT 100 Ohms",
receive_pma3.use_deser_double_data_width = "false",
receive_pma3.use_external_termination = "false",
receive_pma3.use_pma_direct = "false",
receive_pma3.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_tx_pcs transmit_pcs0
(
.clkout(),
.coreclk(tx_coreclk_in[0]),
.coreclkout(wire_transmit_pcs0_coreclkout),
.ctrlenable({{2{1'b0}}, tx_ctrlenable[1:0]}),
.datain({{24{1'b0}}, tx_datain_wire[15:0]}),
.dataout(wire_transmit_pcs0_dataout),
.detectrxloop(tx_detectrxloop[0]),
.digitalreset(tx_digitalreset_out[0]),
.dispval({{2{1'b0}}, {2{tx_forceelecidle[0]}}}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[149:0]),
.dprioout(wire_transmit_pcs0_dprioout),
.elecidleinfersel(rx_elecidleinfersel[2:0]),
.enrevparallellpbk(tx_revparallellpbken[0]),
.forcedisp({{2{1'b0}}, tx_forcedisp_wire[1:0]}),
.forcedispcompliance(1'b0),
.forceelecidle(tx_forceelecidle[0]),
.forceelecidleout(wire_transmit_pcs0_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs0_grayelecidleinferselout),
.hiptxclkout(),
.invpol(tx_invpolarity[0]),
.iqpphfifobyteselout(),
.iqpphfifordclkout(),
.iqpphfifordenableout(),
.iqpphfifowrenableout(),
.localrefclk(tx_localrefclk[0]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[0]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[0]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs0_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[0]),
.phfiforesetout(wire_transmit_pcs0_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs0_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[2:0]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[2:0]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[2:0]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[2:0]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[2:0]),
.pipeenrevparallellpbkout(wire_transmit_pcs0_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[0]),
.pipetxdeemph(tx_pipedeemph[0]),
.pipetxmargin(tx_pipemargin[2:0]),
.pipetxswing(tx_pipeswing[0]),
.powerdn(powerdn[1:0]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[19:0]),
.txdetectrx(wire_transmit_pcs0_txdetectrx),
.xgmctrl(cent_unit_txctrlout[0]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[7:0]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.datainfull({44{1'b0}}),
.freezptr(1'b0),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.hiptxdeemph(1'b0),
.hiptxmargin({3{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnrdclk({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs0.allow_polarity_inversion = "false",
transmit_pcs0.auto_spd_self_switch_enable = "false",
transmit_pcs0.bitslip_enable = "false",
transmit_pcs0.channel_bonding = "x4",
transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pcs0.channel_width = 16,
transmit_pcs0.core_clock_0ppm = "false",
transmit_pcs0.datapath_low_latency_mode = "false",
transmit_pcs0.datapath_protocol = "pipe",
transmit_pcs0.disable_ph_low_latency_mode = "false",
transmit_pcs0.disparity_mode = "new",
transmit_pcs0.dprio_config_mode = 6'h01,
transmit_pcs0.elec_idle_delay = 6,
transmit_pcs0.enable_bit_reversal = "false",
transmit_pcs0.enable_idle_selection = "false",
transmit_pcs0.enable_reverse_parallel_loopback = "true",
transmit_pcs0.enable_self_test_mode = "false",
transmit_pcs0.enable_symbol_swap = "false",
transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
transmit_pcs0.enc_8b_10b_mode = "normal",
transmit_pcs0.force_echar = "false",
transmit_pcs0.force_kchar = "false",
transmit_pcs0.hip_enable = "false",
transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
transmit_pcs0.ph_fifo_reg_mode = "false",
transmit_pcs0.ph_fifo_xn_mapping0 = "none",
transmit_pcs0.ph_fifo_xn_mapping1 = "none",
transmit_pcs0.ph_fifo_xn_mapping2 = "central",
transmit_pcs0.ph_fifo_xn_select = 2,
transmit_pcs0.pipe_auto_speed_nego_enable = "true",
transmit_pcs0.pipe_freq_scale_mode = "Frequency",
transmit_pcs0.pipe_voltage_swing_control = "false",
transmit_pcs0.prbs_cid_pattern = "false",
transmit_pcs0.protocol_hint = "pcie2",
transmit_pcs0.refclk_select = "cmu_clock_divider",
transmit_pcs0.self_test_mode = "incremental",
transmit_pcs0.use_double_data_mode = "true",
transmit_pcs0.use_serializer_double_data_mode = "false",
transmit_pcs0.wr_clk_mux_select = "core_clk",
transmit_pcs0.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs1
(
.clkout(),
.coreclk(tx_coreclk_in[1]),
.coreclkout(wire_transmit_pcs1_coreclkout),
.ctrlenable({{2{1'b0}}, tx_ctrlenable[3:2]}),
.datain({{24{1'b0}}, tx_datain_wire[31:16]}),
.dataout(wire_transmit_pcs1_dataout),
.detectrxloop(tx_detectrxloop[1]),
.digitalreset(tx_digitalreset_out[1]),
.dispval({{2{1'b0}}, {2{tx_forceelecidle[1]}}}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[299:150]),
.dprioout(wire_transmit_pcs1_dprioout),
.elecidleinfersel(rx_elecidleinfersel[5:3]),
.enrevparallellpbk(tx_revparallellpbken[1]),
.forcedisp({{2{1'b0}}, tx_forcedisp_wire[3:2]}),
.forcedispcompliance(1'b0),
.forceelecidle(tx_forceelecidle[1]),
.forceelecidleout(wire_transmit_pcs1_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs1_grayelecidleinferselout),
.hiptxclkout(),
.invpol(tx_invpolarity[1]),
.iqpphfifobyteselout(),
.iqpphfifordclkout(),
.iqpphfifordenableout(),
.iqpphfifowrenableout(),
.localrefclk(tx_localrefclk[1]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[1]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[1]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs1_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[1]),
.phfiforesetout(wire_transmit_pcs1_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs1_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[5:3]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[5:3]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[5:3]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[5:3]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[5:3]),
.pipeenrevparallellpbkout(wire_transmit_pcs1_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs1_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs1_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[1]),
.pipetxdeemph(tx_pipedeemph[1]),
.pipetxmargin(tx_pipemargin[5:3]),
.pipetxswing(tx_pipeswing[1]),
.powerdn(powerdn[3:2]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[39:20]),
.txdetectrx(wire_transmit_pcs1_txdetectrx),
.xgmctrl(cent_unit_txctrlout[1]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[15:8]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.datainfull({44{1'b0}}),
.freezptr(1'b0),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.hiptxdeemph(1'b0),
.hiptxmargin({3{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnrdclk({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs1.allow_polarity_inversion = "false",
transmit_pcs1.auto_spd_self_switch_enable = "false",
transmit_pcs1.bitslip_enable = "false",
transmit_pcs1.channel_bonding = "x4",
transmit_pcs1.channel_number = ((starting_channel_number + 1) % 4),
transmit_pcs1.channel_width = 16,
transmit_pcs1.core_clock_0ppm = "false",
transmit_pcs1.datapath_low_latency_mode = "false",
transmit_pcs1.datapath_protocol = "pipe",
transmit_pcs1.disable_ph_low_latency_mode = "false",
transmit_pcs1.disparity_mode = "new",
transmit_pcs1.dprio_config_mode = 6'h01,
transmit_pcs1.elec_idle_delay = 6,
transmit_pcs1.enable_bit_reversal = "false",
transmit_pcs1.enable_idle_selection = "false",
transmit_pcs1.enable_reverse_parallel_loopback = "true",
transmit_pcs1.enable_self_test_mode = "false",
transmit_pcs1.enable_symbol_swap = "false",
transmit_pcs1.enc_8b_10b_compatibility_mode = "true",
transmit_pcs1.enc_8b_10b_mode = "normal",
transmit_pcs1.force_echar = "false",
transmit_pcs1.force_kchar = "false",
transmit_pcs1.hip_enable = "false",
transmit_pcs1.logical_channel_address = (starting_channel_number + 1),
transmit_pcs1.ph_fifo_reg_mode = "false",
transmit_pcs1.ph_fifo_xn_mapping0 = "none",
transmit_pcs1.ph_fifo_xn_mapping1 = "none",
transmit_pcs1.ph_fifo_xn_mapping2 = "central",
transmit_pcs1.ph_fifo_xn_select = 2,
transmit_pcs1.pipe_auto_speed_nego_enable = "true",
transmit_pcs1.pipe_freq_scale_mode = "Frequency",
transmit_pcs1.pipe_voltage_swing_control = "false",
transmit_pcs1.prbs_cid_pattern = "false",
transmit_pcs1.protocol_hint = "pcie2",
transmit_pcs1.refclk_select = "cmu_clock_divider",
transmit_pcs1.self_test_mode = "incremental",
transmit_pcs1.use_double_data_mode = "true",
transmit_pcs1.use_serializer_double_data_mode = "false",
transmit_pcs1.wr_clk_mux_select = "core_clk",
transmit_pcs1.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs2
(
.clkout(),
.coreclk(tx_coreclk_in[2]),
.coreclkout(wire_transmit_pcs2_coreclkout),
.ctrlenable({{2{1'b0}}, tx_ctrlenable[5:4]}),
.datain({{24{1'b0}}, tx_datain_wire[47:32]}),
.dataout(wire_transmit_pcs2_dataout),
.detectrxloop(tx_detectrxloop[2]),
.digitalreset(tx_digitalreset_out[2]),
.dispval({{2{1'b0}}, {2{tx_forceelecidle[2]}}}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[449:300]),
.dprioout(wire_transmit_pcs2_dprioout),
.elecidleinfersel(rx_elecidleinfersel[8:6]),
.enrevparallellpbk(tx_revparallellpbken[2]),
.forcedisp({{2{1'b0}}, tx_forcedisp_wire[5:4]}),
.forcedispcompliance(1'b0),
.forceelecidle(tx_forceelecidle[2]),
.forceelecidleout(wire_transmit_pcs2_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs2_grayelecidleinferselout),
.hiptxclkout(),
.invpol(tx_invpolarity[2]),
.iqpphfifobyteselout(),
.iqpphfifordclkout(),
.iqpphfifordenableout(),
.iqpphfifowrenableout(),
.localrefclk(tx_localrefclk[2]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[2]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[2]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs2_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[2]),
.phfiforesetout(wire_transmit_pcs2_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs2_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[8:6]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[8:6]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[8:6]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[8:6]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[8:6]),
.pipeenrevparallellpbkout(wire_transmit_pcs2_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs2_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs2_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[2]),
.pipetxdeemph(tx_pipedeemph[2]),
.pipetxmargin(tx_pipemargin[8:6]),
.pipetxswing(tx_pipeswing[2]),
.powerdn(powerdn[5:4]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[59:40]),
.txdetectrx(wire_transmit_pcs2_txdetectrx),
.xgmctrl(cent_unit_txctrlout[2]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[23:16]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.datainfull({44{1'b0}}),
.freezptr(1'b0),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.hiptxdeemph(1'b0),
.hiptxmargin({3{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnrdclk({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs2.allow_polarity_inversion = "false",
transmit_pcs2.auto_spd_self_switch_enable = "false",
transmit_pcs2.bitslip_enable = "false",
transmit_pcs2.channel_bonding = "x4",
transmit_pcs2.channel_number = ((starting_channel_number + 2) % 4),
transmit_pcs2.channel_width = 16,
transmit_pcs2.core_clock_0ppm = "false",
transmit_pcs2.datapath_low_latency_mode = "false",
transmit_pcs2.datapath_protocol = "pipe",
transmit_pcs2.disable_ph_low_latency_mode = "false",
transmit_pcs2.disparity_mode = "new",
transmit_pcs2.dprio_config_mode = 6'h01,
transmit_pcs2.elec_idle_delay = 6,
transmit_pcs2.enable_bit_reversal = "false",
transmit_pcs2.enable_idle_selection = "false",
transmit_pcs2.enable_reverse_parallel_loopback = "true",
transmit_pcs2.enable_self_test_mode = "false",
transmit_pcs2.enable_symbol_swap = "false",
transmit_pcs2.enc_8b_10b_compatibility_mode = "true",
transmit_pcs2.enc_8b_10b_mode = "normal",
transmit_pcs2.force_echar = "false",
transmit_pcs2.force_kchar = "false",
transmit_pcs2.hip_enable = "false",
transmit_pcs2.logical_channel_address = (starting_channel_number + 2),
transmit_pcs2.ph_fifo_reg_mode = "false",
transmit_pcs2.ph_fifo_xn_mapping0 = "none",
transmit_pcs2.ph_fifo_xn_mapping1 = "none",
transmit_pcs2.ph_fifo_xn_mapping2 = "central",
transmit_pcs2.ph_fifo_xn_select = 2,
transmit_pcs2.pipe_auto_speed_nego_enable = "true",
transmit_pcs2.pipe_freq_scale_mode = "Frequency",
transmit_pcs2.pipe_voltage_swing_control = "false",
transmit_pcs2.prbs_cid_pattern = "false",
transmit_pcs2.protocol_hint = "pcie2",
transmit_pcs2.refclk_select = "cmu_clock_divider",
transmit_pcs2.self_test_mode = "incremental",
transmit_pcs2.use_double_data_mode = "true",
transmit_pcs2.use_serializer_double_data_mode = "false",
transmit_pcs2.wr_clk_mux_select = "core_clk",
transmit_pcs2.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs3
(
.clkout(),
.coreclk(tx_coreclk_in[3]),
.coreclkout(wire_transmit_pcs3_coreclkout),
.ctrlenable({{2{1'b0}}, tx_ctrlenable[7:6]}),
.datain({{24{1'b0}}, tx_datain_wire[63:48]}),
.dataout(wire_transmit_pcs3_dataout),
.detectrxloop(tx_detectrxloop[3]),
.digitalreset(tx_digitalreset_out[3]),
.dispval({{2{1'b0}}, {2{tx_forceelecidle[3]}}}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[599:450]),
.dprioout(wire_transmit_pcs3_dprioout),
.elecidleinfersel(rx_elecidleinfersel[11:9]),
.enrevparallellpbk(tx_revparallellpbken[3]),
.forcedisp({{2{1'b0}}, tx_forcedisp_wire[7:6]}),
.forcedispcompliance(1'b0),
.forceelecidle(tx_forceelecidle[3]),
.forceelecidleout(wire_transmit_pcs3_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs3_grayelecidleinferselout),
.hiptxclkout(),
.invpol(tx_invpolarity[3]),
.iqpphfifobyteselout(),
.iqpphfifordclkout(),
.iqpphfifordenableout(),
.iqpphfifowrenableout(),
.localrefclk(tx_localrefclk[3]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[3]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[3]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs3_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[3]),
.phfiforesetout(wire_transmit_pcs3_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs3_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[11:9]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[11:9]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[11:9]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[11:9]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[11:9]),
.pipeenrevparallellpbkout(wire_transmit_pcs3_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs3_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs3_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[3]),
.pipetxdeemph(tx_pipedeemph[3]),
.pipetxmargin(tx_pipemargin[11:9]),
.pipetxswing(tx_pipeswing[3]),
.powerdn(powerdn[7:6]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[79:60]),
.txdetectrx(wire_transmit_pcs3_txdetectrx),
.xgmctrl(cent_unit_txctrlout[3]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[31:24]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.datainfull({44{1'b0}}),
.freezptr(1'b0),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.hiptxdeemph(1'b0),
.hiptxmargin({3{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnrdclk({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs3.allow_polarity_inversion = "false",
transmit_pcs3.auto_spd_self_switch_enable = "false",
transmit_pcs3.bitslip_enable = "false",
transmit_pcs3.channel_bonding = "x4",
transmit_pcs3.channel_number = ((starting_channel_number + 3) % 4),
transmit_pcs3.channel_width = 16,
transmit_pcs3.core_clock_0ppm = "false",
transmit_pcs3.datapath_low_latency_mode = "false",
transmit_pcs3.datapath_protocol = "pipe",
transmit_pcs3.disable_ph_low_latency_mode = "false",
transmit_pcs3.disparity_mode = "new",
transmit_pcs3.dprio_config_mode = 6'h01,
transmit_pcs3.elec_idle_delay = 6,
transmit_pcs3.enable_bit_reversal = "false",
transmit_pcs3.enable_idle_selection = "false",
transmit_pcs3.enable_reverse_parallel_loopback = "true",
transmit_pcs3.enable_self_test_mode = "false",
transmit_pcs3.enable_symbol_swap = "false",
transmit_pcs3.enc_8b_10b_compatibility_mode = "true",
transmit_pcs3.enc_8b_10b_mode = "normal",
transmit_pcs3.force_echar = "false",
transmit_pcs3.force_kchar = "false",
transmit_pcs3.hip_enable = "false",
transmit_pcs3.logical_channel_address = (starting_channel_number + 3),
transmit_pcs3.ph_fifo_reg_mode = "false",
transmit_pcs3.ph_fifo_xn_mapping0 = "none",
transmit_pcs3.ph_fifo_xn_mapping1 = "none",
transmit_pcs3.ph_fifo_xn_mapping2 = "central",
transmit_pcs3.ph_fifo_xn_select = 2,
transmit_pcs3.pipe_auto_speed_nego_enable = "true",
transmit_pcs3.pipe_freq_scale_mode = "Frequency",
transmit_pcs3.pipe_voltage_swing_control = "false",
transmit_pcs3.prbs_cid_pattern = "false",
transmit_pcs3.protocol_hint = "pcie2",
transmit_pcs3.refclk_select = "cmu_clock_divider",
transmit_pcs3.self_test_mode = "incremental",
transmit_pcs3.use_double_data_mode = "true",
transmit_pcs3.use_serializer_double_data_mode = "false",
transmit_pcs3.wr_clk_mux_select = "core_clk",
transmit_pcs3.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pma transmit_pma0
(
.clockout(wire_transmit_pma0_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[19:0]}),
.dataout(wire_transmit_pma0_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[299:0]),
.dprioout(wire_transmit_pma0_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
.fastrefclk2in({2{1'b0}}),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[0]),
.powerdn(cent_unit_txobpowerdn[0]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in(cmu_analogrefclkout[1:0]),
.refclk1inpulse(cmu_analogrefclkpulse[0]),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[0]),
.rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
.rxfoundout(wire_transmit_pma0_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma0.analog_power = "auto",
transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pma0.channel_type = "auto",
transmit_pma0.clkin_select = 1,
transmit_pma0.clkmux_delay = "false",
transmit_pma0.common_mode = "0.65V",
transmit_pma0.dprio_config_mode = 6'h01,
transmit_pma0.enable_reverse_serial_loopback = "false",
transmit_pma0.logical_channel_address = (starting_channel_number + 0),
transmit_pma0.logical_protocol_hint_0 = "pcie2",
transmit_pma0.low_speed_test_select = 0,
transmit_pma0.physical_clkin1_mapping = "x4",
transmit_pma0.preemp_pretap = 0,
transmit_pma0.preemp_pretap_inv = "false",
transmit_pma0.preemp_tap_1 = 0,
transmit_pma0.preemp_tap_1_a = 28,
transmit_pma0.preemp_tap_1_b = 22,
transmit_pma0.preemp_tap_1_c = 7,
transmit_pma0.preemp_tap_2 = 0,
transmit_pma0.preemp_tap_2_inv = "false",
transmit_pma0.protocol_hint = "pcie2",
transmit_pma0.rx_detect = 0,
transmit_pma0.serialization_factor = 10,
transmit_pma0.slew_rate = "off",
transmit_pma0.termination = "OCT 100 Ohms",
transmit_pma0.use_external_termination = "false",
transmit_pma0.use_pma_direct = "false",
transmit_pma0.use_ser_double_data_mode = "false",
transmit_pma0.vod_selection = 3,
transmit_pma0.vod_selection_a = 6,
transmit_pma0.vod_selection_c = 1,
transmit_pma0.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma1
(
.clockout(wire_transmit_pma1_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[39:20]}),
.dataout(wire_transmit_pma1_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[1]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[599:300]),
.dprioout(wire_transmit_pma1_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
.fastrefclk2in({2{1'b0}}),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[1]),
.powerdn(cent_unit_txobpowerdn[1]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in(cmu_analogrefclkout[1:0]),
.refclk1inpulse(cmu_analogrefclkpulse[0]),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[1]),
.rxdetectvalidout(wire_transmit_pma1_rxdetectvalidout),
.rxfoundout(wire_transmit_pma1_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[1])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma1.analog_power = "auto",
transmit_pma1.channel_number = ((starting_channel_number + 1) % 4),
transmit_pma1.channel_type = "auto",
transmit_pma1.clkin_select = 1,
transmit_pma1.clkmux_delay = "false",
transmit_pma1.common_mode = "0.65V",
transmit_pma1.dprio_config_mode = 6'h01,
transmit_pma1.enable_reverse_serial_loopback = "false",
transmit_pma1.logical_channel_address = (starting_channel_number + 1),
transmit_pma1.logical_protocol_hint_0 = "pcie2",
transmit_pma1.low_speed_test_select = 0,
transmit_pma1.physical_clkin1_mapping = "x4",
transmit_pma1.preemp_pretap = 0,
transmit_pma1.preemp_pretap_inv = "false",
transmit_pma1.preemp_tap_1 = 0,
transmit_pma1.preemp_tap_1_a = 28,
transmit_pma1.preemp_tap_1_b = 22,
transmit_pma1.preemp_tap_1_c = 7,
transmit_pma1.preemp_tap_2 = 0,
transmit_pma1.preemp_tap_2_inv = "false",
transmit_pma1.protocol_hint = "pcie2",
transmit_pma1.rx_detect = 0,
transmit_pma1.serialization_factor = 10,
transmit_pma1.slew_rate = "off",
transmit_pma1.termination = "OCT 100 Ohms",
transmit_pma1.use_external_termination = "false",
transmit_pma1.use_pma_direct = "false",
transmit_pma1.use_ser_double_data_mode = "false",
transmit_pma1.vod_selection = 3,
transmit_pma1.vod_selection_a = 6,
transmit_pma1.vod_selection_c = 1,
transmit_pma1.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma2
(
.clockout(wire_transmit_pma2_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[59:40]}),
.dataout(wire_transmit_pma2_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[2]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[899:600]),
.dprioout(wire_transmit_pma2_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
.fastrefclk2in({2{1'b0}}),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[2]),
.powerdn(cent_unit_txobpowerdn[2]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in(cmu_analogrefclkout[1:0]),
.refclk1inpulse(cmu_analogrefclkpulse[0]),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[2]),
.rxdetectvalidout(wire_transmit_pma2_rxdetectvalidout),
.rxfoundout(wire_transmit_pma2_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[2])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma2.analog_power = "auto",
transmit_pma2.channel_number = ((starting_channel_number + 2) % 4),
transmit_pma2.channel_type = "auto",
transmit_pma2.clkin_select = 1,
transmit_pma2.clkmux_delay = "false",
transmit_pma2.common_mode = "0.65V",
transmit_pma2.dprio_config_mode = 6'h01,
transmit_pma2.enable_reverse_serial_loopback = "false",
transmit_pma2.logical_channel_address = (starting_channel_number + 2),
transmit_pma2.logical_protocol_hint_0 = "pcie2",
transmit_pma2.low_speed_test_select = 0,
transmit_pma2.physical_clkin1_mapping = "x4",
transmit_pma2.preemp_pretap = 0,
transmit_pma2.preemp_pretap_inv = "false",
transmit_pma2.preemp_tap_1 = 0,
transmit_pma2.preemp_tap_1_a = 28,
transmit_pma2.preemp_tap_1_b = 22,
transmit_pma2.preemp_tap_1_c = 7,
transmit_pma2.preemp_tap_2 = 0,
transmit_pma2.preemp_tap_2_inv = "false",
transmit_pma2.protocol_hint = "pcie2",
transmit_pma2.rx_detect = 0,
transmit_pma2.serialization_factor = 10,
transmit_pma2.slew_rate = "off",
transmit_pma2.termination = "OCT 100 Ohms",
transmit_pma2.use_external_termination = "false",
transmit_pma2.use_pma_direct = "false",
transmit_pma2.use_ser_double_data_mode = "false",
transmit_pma2.vod_selection = 3,
transmit_pma2.vod_selection_a = 6,
transmit_pma2.vod_selection_c = 1,
transmit_pma2.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma3
(
.clockout(wire_transmit_pma3_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[79:60]}),
.dataout(wire_transmit_pma3_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[3]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[1199:900]),
.dprioout(wire_transmit_pma3_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
.fastrefclk2in({2{1'b0}}),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[3]),
.powerdn(cent_unit_txobpowerdn[3]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in(cmu_analogrefclkout[1:0]),
.refclk1inpulse(cmu_analogrefclkpulse[0]),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[3]),
.rxdetectvalidout(wire_transmit_pma3_rxdetectvalidout),
.rxfoundout(wire_transmit_pma3_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[3])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma3.analog_power = "auto",
transmit_pma3.channel_number = ((starting_channel_number + 3) % 4),
transmit_pma3.channel_type = "auto",
transmit_pma3.clkin_select = 1,
transmit_pma3.clkmux_delay = "false",
transmit_pma3.common_mode = "0.65V",
transmit_pma3.dprio_config_mode = 6'h01,
transmit_pma3.enable_reverse_serial_loopback = "false",
transmit_pma3.logical_channel_address = (starting_channel_number + 3),
transmit_pma3.logical_protocol_hint_0 = "pcie2",
transmit_pma3.low_speed_test_select = 0,
transmit_pma3.physical_clkin1_mapping = "x4",
transmit_pma3.preemp_pretap = 0,
transmit_pma3.preemp_pretap_inv = "false",
transmit_pma3.preemp_tap_1 = 0,
transmit_pma3.preemp_tap_1_a = 28,
transmit_pma3.preemp_tap_1_b = 22,
transmit_pma3.preemp_tap_1_c = 7,
transmit_pma3.preemp_tap_2 = 0,
transmit_pma3.preemp_tap_2_inv = "false",
transmit_pma3.protocol_hint = "pcie2",
transmit_pma3.rx_detect = 0,
transmit_pma3.serialization_factor = 10,
transmit_pma3.slew_rate = "off",
transmit_pma3.termination = "OCT 100 Ohms",
transmit_pma3.use_external_termination = "false",
transmit_pma3.use_pma_direct = "false",
transmit_pma3.use_ser_double_data_mode = "false",
transmit_pma3.vod_selection = 3,
transmit_pma3.vod_selection_a = 6,
transmit_pma3.vod_selection_c = 1,
transmit_pma3.lpm_type = "stratixiv_hssi_tx_pma";
assign
cal_blk_powerdown = 1'b0,
cent_unit_clkdivpowerdn = {wire_cent_unit0_clkdivpowerdn[0]},
cent_unit_cmudividerdprioout = {wire_cent_unit0_cmudividerdprioout},
cent_unit_cmuplldprioout = {wire_cent_unit0_cmuplldprioout},
cent_unit_pllpowerdn = {wire_cent_unit0_pllpowerdn[1:0]},
cent_unit_pllresetout = {wire_cent_unit0_pllresetout[1:0]},
cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[5:0]},
cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[5:0]},
cent_unit_rxpcsdprioin = {rx_pcsdprioout[1599:0]},
cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout[1599:0]},
cent_unit_rxpmadprioin = {{2{{300{1'b0}}}}, rx_pmadprioout[1199:0]},
cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout[1799:0]},
cent_unit_tx_dprioin = {{600{1'b0}}, tx_txdprioout[599:0]},
cent_unit_tx_xgmdataout = {wire_cent_unit0_txdataout[31:0]},
cent_unit_txctrlout = {wire_cent_unit0_txctrlout},
cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[5:0]},
cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout[599:0]},
cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[5:0]},
cent_unit_txpmadprioin = {{2{{300{1'b0}}}}, tx_pmadprioout[1199:0]},
cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout[1799:0]},
clk_div_clk0in = {pll0_out[3:0]},
clk_div_cmudividerdprioin = {{100{1'b0}}, wire_central_clk_div0_dprioout, {400{1'b0}}},
cmu_analogfastrefclkout = {wire_central_clk_div0_analogfastrefclkout},
cmu_analogrefclkout = {wire_central_clk_div0_analogrefclkout},
cmu_analogrefclkpulse = {wire_central_clk_div0_analogrefclkpulse},
coreclkout = {coreclkout_wire[0]},
coreclkout_wire = {wire_central_clk_div0_coreclkout},
fixedclk = 1'b0,
fixedclk_to_cmu = {6{reconfig_clk}},
grayelecidleinfersel_from_tx = {wire_transmit_pcs3_grayelecidleinferselout, wire_transmit_pcs2_grayelecidleinferselout, wire_transmit_pcs1_grayelecidleinferselout, wire_transmit_pcs0_grayelecidleinferselout},
int_autospdx4configsel = {wire_cent_unit0_autospdx4configsel},
int_autospdx4spdchg = {wire_cent_unit0_autospdx4spdchg},
int_hiprateswtichdone = {wire_central_clk_div0_rateswitchdone},
int_pcie_sw = {((int_pcie_sw_select[0] & int_pll_reset_delayed[0]) | ((~ int_pcie_sw_select[0]) & pcie_sw_wire[0]))},
int_pcie_sw_select = {pcie_sw_sel_delay_blk0c[9]},
int_phfifiox4ptrsreset = {wire_cent_unit0_phfifiox4ptrsreset},
int_pipeenrevparallellpbkfromtx = {wire_transmit_pcs3_pipeenrevparallellpbkout, wire_transmit_pcs2_pipeenrevparallellpbkout, wire_transmit_pcs1_pipeenrevparallellpbkout, wire_transmit_pcs0_pipeenrevparallellpbkout},
int_pll_reset_delayed = {pllreset_delay_blk0c[9]},
int_rateswitch = {int_rx_rateswitchout[0]},
int_rx_autospdxnconfigsel = {int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}},
int_rx_autospdxnspdchg = {int_autospdx4spdchg[0], {2{1'b0}}, int_autospdx4spdchg[0], {2{1'b0}}, int_autospdx4spdchg[0], {2{1'b0}}, int_autospdx4spdchg[0], {2{1'b0}}},
int_rx_coreclkout = {wire_receive_pcs3_coreclkout, wire_receive_pcs2_coreclkout, wire_receive_pcs1_coreclkout, wire_receive_pcs0_coreclkout},
int_rx_digitalreset_reg = {rx_digitalreset_reg0c[2]},
int_rx_phfifioxnptrsreset = {int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}},
int_rx_phfifobyteserdisable = {wire_receive_pcs3_phfifobyteserdisableout, wire_receive_pcs2_phfifobyteserdisableout, wire_receive_pcs1_phfifobyteserdisableout, wire_receive_pcs0_phfifobyteserdisableout},
int_rx_phfifoptrsresetout = {wire_receive_pcs3_phfifoptrsresetout, wire_receive_pcs2_phfifoptrsresetout, wire_receive_pcs1_phfifoptrsresetout, wire_receive_pcs0_phfifoptrsresetout},
int_rx_phfifordenableout = {wire_receive_pcs3_phfifordenableout, wire_receive_pcs2_phfifordenableout, wire_receive_pcs1_phfifordenableout, wire_receive_pcs0_phfifordenableout},
int_rx_phfiforesetout = {wire_receive_pcs3_phfiforesetout, wire_receive_pcs2_phfiforesetout, wire_receive_pcs1_phfiforesetout, wire_receive_pcs0_phfiforesetout},
int_rx_phfifowrdisableout = {wire_receive_pcs3_phfifowrdisableout, wire_receive_pcs2_phfifowrdisableout, wire_receive_pcs1_phfifowrdisableout, wire_receive_pcs0_phfifowrdisableout},
int_rx_phfifoxnbytesel = {int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}},
int_rx_phfifoxnrdenable = {int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}},
int_rx_phfifoxnwrclk = {int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}},
int_rx_phfifoxnwrenable = {int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}},
int_rx_rateswitchout = {wire_receive_pcs3_rateswitchout, wire_receive_pcs2_rateswitchout, wire_receive_pcs1_rateswitchout, wire_receive_pcs0_rateswitchout},
int_rxcoreclk = {int_rx_coreclkout[0]},
int_rxpcs_cdrctrlearlyeios = {wire_receive_pcs3_cdrctrlearlyeios, wire_receive_pcs2_cdrctrlearlyeios, wire_receive_pcs1_cdrctrlearlyeios, wire_receive_pcs0_cdrctrlearlyeios},
int_rxphfifordenable = {int_rx_phfifordenableout[0]},
int_rxphfiforeset = {int_rx_phfiforesetout[0]},
int_rxphfifox4byteselout = {wire_cent_unit0_rxphfifox4byteselout},
int_rxphfifox4rdenableout = {wire_cent_unit0_rxphfifox4rdenableout},
int_rxphfifox4wrclkout = {wire_cent_unit0_rxphfifox4wrclkout},
int_rxphfifox4wrenableout = {wire_cent_unit0_rxphfifox4wrenableout},
int_tx_coreclkout = {wire_transmit_pcs3_coreclkout, wire_transmit_pcs2_coreclkout, wire_transmit_pcs1_coreclkout, wire_transmit_pcs0_coreclkout},
int_tx_digitalreset_reg = {tx_digitalreset_reg0c[2]},
int_tx_phfifioxnptrsreset = {int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}},
int_tx_phfiforddisableout = {wire_transmit_pcs3_phfiforddisableout, wire_transmit_pcs2_phfiforddisableout, wire_transmit_pcs1_phfiforddisableout, wire_transmit_pcs0_phfiforddisableout},
int_tx_phfiforesetout = {wire_transmit_pcs3_phfiforesetout, wire_transmit_pcs2_phfiforesetout, wire_transmit_pcs1_phfiforesetout, wire_transmit_pcs0_phfiforesetout},
int_tx_phfifowrenableout = {wire_transmit_pcs3_phfifowrenableout, wire_transmit_pcs2_phfifowrenableout, wire_transmit_pcs1_phfifowrenableout, wire_transmit_pcs0_phfifowrenableout},
int_tx_phfifoxnbytesel = {int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}},
int_tx_phfifoxnrdclk = {int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}},
int_tx_phfifoxnrdenable = {int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}},
int_tx_phfifoxnwrenable = {int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}},
int_txcoreclk = {int_tx_coreclkout[0]},
int_txphfiforddisable = {int_tx_phfiforddisableout[0]},
int_txphfiforeset = {int_tx_phfiforesetout[0]},
int_txphfifowrenable = {int_tx_phfifowrenableout[0]},
int_txphfifox4byteselout = {wire_cent_unit0_txphfifox4byteselout},
int_txphfifox4rdclkout = {wire_cent_unit0_txphfifox4rdclkout},
int_txphfifox4rdenableout = {wire_cent_unit0_txphfifox4rdenableout},
int_txphfifox4wrenableout = {wire_cent_unit0_txphfifox4wrenableout},
nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
pcie_sw_wire = {wire_cent_unit0_digitaltestout[2]},
pipedatavalid = {pipedatavalid_out[3:0]},
pipedatavalid_out = {wire_receive_pcs3_pipedatavalid, wire_receive_pcs2_pipedatavalid, wire_receive_pcs1_pipedatavalid, wire_receive_pcs0_pipedatavalid},
pipeelecidle = {pipeelecidle_out[3:0]},
pipeelecidle_out = {wire_receive_pcs3_pipeelecidle, wire_receive_pcs2_pipeelecidle, wire_receive_pcs1_pipeelecidle, wire_receive_pcs0_pipeelecidle},
pipephydonestatus = {wire_receive_pcs3_pipephydonestatus, wire_receive_pcs2_pipephydonestatus, wire_receive_pcs1_pipephydonestatus, wire_receive_pcs0_pipephydonestatus},
pipestatus = {wire_receive_pcs3_pipestatus, wire_receive_pcs2_pipestatus, wire_receive_pcs1_pipestatus, wire_receive_pcs0_pipestatus},
pll0_clkin = {{9{1'b0}}, pll_inclk_wire[0]},
pll0_dprioin = {cent_unit_cmuplldprioout[1499:1200]},
pll0_dprioout = {wire_tx_pll0_dprioout},
pll0_out = {wire_tx_pll0_clk[3:0]},
pll_ch_dataout_wire = {wire_rx_cdr_pll3_dataout, wire_rx_cdr_pll2_dataout, wire_rx_cdr_pll1_dataout, wire_rx_cdr_pll0_dataout},
pll_ch_dprioout = {wire_rx_cdr_pll3_dprioout, wire_rx_cdr_pll2_dprioout, wire_rx_cdr_pll1_dprioout, wire_rx_cdr_pll0_dprioout},
pll_cmuplldprioout = {{300{1'b0}}, pll0_dprioout[299:0], pll_ch_dprioout[1199:0]},
pll_inclk_wire = {pll_inclk},
pll_locked = {pll_locked_out[0]},
pll_locked_out = {wire_tx_pll0_locked},
pll_powerdown = 1'b0,
pllpowerdn_in = {1'b0, cent_unit_pllpowerdn[0]},
pllreset_in = {1'b0, cent_unit_pllresetout[0]},
reconfig_fromgxb = {rx_pma_analogtestbus[16:1], wire_cent_unit0_dprioout},
reconfig_togxb_busy = reconfig_togxb[3],
reconfig_togxb_disable = reconfig_togxb[1],
reconfig_togxb_in = reconfig_togxb[0],
reconfig_togxb_load = reconfig_togxb[2],
refclk_pma = {wire_central_clk_div0_refclkout},
rx_analogreset_in = {{2{1'b0}}, {4{((~ reconfig_togxb_busy) & rx_analogreset[0])}}},
rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[5:0]},
rx_coreclk_in = {4{coreclkout_wire[0]}},
rx_cruclk_in = {{9{1'b0}}, rx_pldcruclk_in[3], {9{1'b0}}, rx_pldcruclk_in[2], {9{1'b0}}, rx_pldcruclk_in[1], {9{1'b0}}, rx_pldcruclk_in[0]},
rx_ctrldetect = {wire_receive_pcs3_ctrldetect[1:0], wire_receive_pcs2_ctrldetect[1:0], wire_receive_pcs1_ctrldetect[1:0], wire_receive_pcs0_ctrldetect[1:0]},
rx_dataout = {rx_out_wire[63:0]},
rx_deserclock_in = {rx_pll_clkout[15:0]},
rx_digitalreset_in = {4{int_rx_digitalreset_reg[0]}},
rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[3:0]},
rx_elecidleinfersel = {12{1'b0}},
rx_enapatternalign = {4{1'b0}},
rx_freqlocked = {(rx_freqlocked_wire[3] & (~ rx_analogreset[0])), (rx_freqlocked_wire[2] & (~ rx_analogreset[0])), (rx_freqlocked_wire[1] & (~ rx_analogreset[0])), (rx_freqlocked_wire[0] & (~ rx_analogreset[0]))},
rx_freqlocked_wire = {wire_rx_cdr_pll3_freqlocked, wire_rx_cdr_pll2_freqlocked, wire_rx_cdr_pll1_freqlocked, wire_rx_cdr_pll0_freqlocked},
rx_locktodata = {4{1'b0}},
rx_locktodata_wire = {((~ reconfig_togxb_busy) & rx_locktodata[3]), ((~ reconfig_togxb_busy) & rx_locktodata[2]), ((~ reconfig_togxb_busy) & rx_locktodata[1]), ((~ reconfig_togxb_busy) & rx_locktodata[0])},
rx_locktorefclk_wire = {wire_receive_pcs3_cdrctrllocktorefclkout, wire_receive_pcs2_cdrctrllocktorefclkout, wire_receive_pcs1_cdrctrllocktorefclkout, wire_receive_pcs0_cdrctrllocktorefclkout},
rx_out_wire = {wire_receive_pcs3_dataout[15:0], wire_receive_pcs2_dataout[15:0], wire_receive_pcs1_dataout[15:0], wire_receive_pcs0_dataout[15:0]},
rx_patterndetect = {wire_receive_pcs3_patterndetect[1:0], wire_receive_pcs2_patterndetect[1:0], wire_receive_pcs1_patterndetect[1:0], wire_receive_pcs0_patterndetect[1:0]},
rx_pcs_rxfound_wire = {txdetectrxout[3], tx_rxfoundout[3], txdetectrxout[2], tx_rxfoundout[2], txdetectrxout[1], tx_rxfoundout[1], txdetectrxout[0], tx_rxfoundout[0]},
rx_pcsdprioin_wire = {cent_unit_rxpcsdprioout[1599:0]},
rx_pcsdprioout = {wire_receive_pcs3_dprioout, wire_receive_pcs2_dprioout, wire_receive_pcs1_dprioout, wire_receive_pcs0_dprioout},
rx_phfifordenable = {4{1'b1}},
rx_phfiforeset = {4{1'b0}},
rx_phfifowrdisable = {4{1'b0}},
rx_pipestatetransdoneout = {wire_receive_pcs3_pipestatetransdoneout, wire_receive_pcs2_pipestatetransdoneout, wire_receive_pcs1_pipestatetransdoneout, wire_receive_pcs0_pipestatetransdoneout},
rx_pldcruclk_in = {rx_cruclk[3:0]},
rx_pll_clkout = {wire_rx_cdr_pll3_clk, wire_rx_cdr_pll2_clk, wire_rx_cdr_pll1_clk, wire_rx_cdr_pll0_clk},
rx_pll_locked = {(rx_plllocked_wire[3] & (~ rx_analogreset[0])), (rx_plllocked_wire[2] & (~ rx_analogreset[0])), (rx_plllocked_wire[1] & (~ rx_analogreset[0])), (rx_plllocked_wire[0] & (~ rx_analogreset[0]))},
rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll3_pfdrefclkout, wire_rx_cdr_pll2_pfdrefclkout, wire_rx_cdr_pll1_pfdrefclkout, wire_rx_cdr_pll0_pfdrefclkout},
rx_plllocked_wire = {wire_rx_cdr_pll3_locked, wire_rx_cdr_pll2_locked, wire_rx_cdr_pll1_locked, wire_rx_cdr_pll0_locked},
rx_pma_analogtestbus = {{51{1'b0}}, wire_receive_pma3_analogtestbus[5:2], wire_receive_pma2_analogtestbus[5:2], wire_receive_pma1_analogtestbus[5:2], wire_receive_pma0_analogtestbus[5:2], 1'b0},
rx_pma_clockout = {wire_receive_pma3_clockout, wire_receive_pma2_clockout, wire_receive_pma1_clockout, wire_receive_pma0_clockout},
rx_pma_dataout = {wire_receive_pma3_dataout, wire_receive_pma2_dataout, wire_receive_pma1_dataout, wire_receive_pma0_dataout},
rx_pma_locktorefout = {wire_receive_pma3_locktorefout, wire_receive_pma2_locktorefout, wire_receive_pma1_locktorefout, wire_receive_pma0_locktorefout},
rx_pma_recoverdataout_wire = {wire_receive_pma3_recoverdataout[19:0], wire_receive_pma2_recoverdataout[19:0], wire_receive_pma1_recoverdataout[19:0], wire_receive_pma0_recoverdataout[19:0]},
rx_pmadprioin_wire = {{2{{300{1'b0}}}}, cent_unit_rxpmadprioout[1199:0]},
rx_pmadprioout = {{2{{300{1'b0}}}}, wire_receive_pma3_dprioout, wire_receive_pma2_dprioout, wire_receive_pma1_dprioout, wire_receive_pma0_dprioout},
rx_powerdown = {4{1'b0}},
rx_powerdown_in = {{2{1'b0}}, rx_powerdown[3:0]},
rx_prbscidenable = {4{1'b0}},
rx_revparallelfdbkdata = {wire_receive_pcs3_revparallelfdbkdata, wire_receive_pcs2_revparallelfdbkdata, wire_receive_pcs1_revparallelfdbkdata, wire_receive_pcs0_revparallelfdbkdata},
rx_rmfiforeset = {4{1'b0}},
rx_rxcruresetout = {wire_cent_unit0_rxcruresetout[5:0]},
rx_signaldetect_wire = {wire_receive_pma3_signaldetect, wire_receive_pma2_signaldetect, wire_receive_pma1_signaldetect, wire_receive_pma0_signaldetect},
rx_syncstatus = {wire_receive_pcs3_syncstatus[1:0], wire_receive_pcs2_syncstatus[1:0], wire_receive_pcs1_syncstatus[1:0], wire_receive_pcs0_syncstatus[1:0]},
rxphfifowrdisable = {int_rx_phfifowrdisableout[0]},
rxpll_dprioin = {{2{{300{1'b0}}}}, cent_unit_cmuplldprioout[1199:0]},
tx_analogreset_out = {wire_cent_unit0_txanalogresetout[5:0]},
tx_coreclk_in = {4{coreclkout_wire[0]}},
tx_datain_wire = {tx_datain[63:0]},
tx_dataout = {wire_transmit_pma3_dataout, wire_transmit_pma2_dataout, wire_transmit_pma1_dataout, wire_transmit_pma0_dataout},
tx_dataout_pcs_to_pma = {wire_transmit_pcs3_dataout, wire_transmit_pcs2_dataout, wire_transmit_pcs1_dataout, wire_transmit_pcs0_dataout},
tx_digitalreset_in = {4{int_tx_digitalreset_reg[0]}},
tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[3:0]},
tx_dprioin_wire = {{600{1'b0}}, cent_unit_txdprioout[599:0]},
tx_forcedisp_wire = {1'b0, tx_forcedispcompliance[3], 1'b0, tx_forcedispcompliance[2], 1'b0, tx_forcedispcompliance[1], 1'b0, tx_forcedispcompliance[0]},
tx_invpolarity = {4{1'b0}},
tx_localrefclk = {wire_transmit_pma3_clockout, wire_transmit_pma2_clockout, wire_transmit_pma1_clockout, wire_transmit_pma0_clockout},
tx_pcs_forceelecidleout = {wire_transmit_pcs3_forceelecidleout, wire_transmit_pcs2_forceelecidleout, wire_transmit_pcs1_forceelecidleout, wire_transmit_pcs0_forceelecidleout},
tx_phfiforeset = {4{1'b0}},
tx_pipepowerdownout = {wire_transmit_pcs3_pipepowerdownout, wire_transmit_pcs2_pipepowerdownout, wire_transmit_pcs1_pipepowerdownout, wire_transmit_pcs0_pipepowerdownout},
tx_pipepowerstateout = {wire_transmit_pcs3_pipepowerstateout, wire_transmit_pcs2_pipepowerstateout, wire_transmit_pcs1_pipepowerstateout, wire_transmit_pcs0_pipepowerstateout},
tx_pipeswing = {4{1'b0}},
tx_pmadprioin_wire = {{2{{300{1'b0}}}}, cent_unit_txpmadprioout[1199:0]},
tx_pmadprioout = {{2{{300{1'b0}}}}, wire_transmit_pma3_dprioout, wire_transmit_pma2_dprioout, wire_transmit_pma1_dprioout, wire_transmit_pma0_dprioout},
tx_revparallellpbken = {4{1'b0}},
tx_rxdetectvalidout = {wire_transmit_pma3_rxdetectvalidout, wire_transmit_pma2_rxdetectvalidout, wire_transmit_pma1_rxdetectvalidout, wire_transmit_pma0_rxdetectvalidout},
tx_rxfoundout = {wire_transmit_pma3_rxfoundout, wire_transmit_pma2_rxfoundout, wire_transmit_pma1_rxfoundout, wire_transmit_pma0_rxfoundout},
tx_txdprioout = {wire_transmit_pcs3_dprioout, wire_transmit_pcs2_dprioout, wire_transmit_pcs1_dprioout, wire_transmit_pcs0_dprioout},
txdetectrxout = {wire_transmit_pcs3_txdetectrx, wire_transmit_pcs2_txdetectrx, wire_transmit_pcs1_txdetectrx, wire_transmit_pcs0_txdetectrx},
w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
endmodule //altpcie_serdes_4sgx_x4d_gen2_08p_alt4gxb_a0ea
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcie_serdes_4sgx_x4d_gen2_08p (
cal_blk_clk,
gxb_powerdown,
pipe8b10binvpolarity,
pll_inclk,
powerdn,
rateswitch,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_datain,
rx_digitalreset,
tx_ctrlenable,
tx_datain,
tx_detectrxloop,
tx_digitalreset,
tx_forcedispcompliance,
tx_forceelecidle,
tx_pipedeemph,
tx_pipemargin,
coreclkout,
pipedatavalid,
pipeelecidle,
pipephydonestatus,
pipestatus,
pll_locked,
reconfig_fromgxb,
rx_ctrldetect,
rx_dataout,
rx_freqlocked,
rx_patterndetect,
rx_pll_locked,
rx_syncstatus,
tx_dataout)/* synthesis synthesis_clearbox = 2 */;
input cal_blk_clk;
input [0:0] gxb_powerdown;
input [3:0] pipe8b10binvpolarity;
input pll_inclk;
input [7:0] powerdn;
input [0:0] rateswitch;
input reconfig_clk;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [3:0] rx_cruclk;
input [3:0] rx_datain;
input [0:0] rx_digitalreset;
input [7:0] tx_ctrlenable;
input [63:0] tx_datain;
input [3:0] tx_detectrxloop;
input [0:0] tx_digitalreset;
input [3:0] tx_forcedispcompliance;
input [3:0] tx_forceelecidle;
input [3:0] tx_pipedeemph;
input [11:0] tx_pipemargin;
output [0:0] coreclkout;
output [3:0] pipedatavalid;
output [3:0] pipeelecidle;
output [3:0] pipephydonestatus;
output [11:0] pipestatus;
output [0:0] pll_locked;
output [16:0] reconfig_fromgxb;
output [7:0] rx_ctrldetect;
output [63:0] rx_dataout;
output [3:0] rx_freqlocked;
output [7:0] rx_patterndetect;
output [3:0] rx_pll_locked;
output [7:0] rx_syncstatus;
output [3:0] tx_dataout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [3:0] rx_cruclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
wire [7:0] sub_wire0;
wire [3:0] sub_wire1;
wire [0:0] sub_wire2;
wire [16:0] sub_wire3;
wire [3:0] sub_wire4;
wire [11:0] sub_wire5;
wire [3:0] sub_wire6;
wire [7:0] sub_wire7;
wire [0:0] sub_wire8;
wire [63:0] sub_wire9;
wire [3:0] sub_wire10;
wire [3:0] sub_wire11;
wire [7:0] sub_wire12;
wire [3:0] sub_wire13;
wire [7:0] rx_patterndetect = sub_wire0[7:0];
wire [3:0] pipephydonestatus = sub_wire1[3:0];
wire [0:0] pll_locked = sub_wire2[0:0];
wire [16:0] reconfig_fromgxb = sub_wire3[16:0];
wire [3:0] rx_freqlocked = sub_wire4[3:0];
wire [11:0] pipestatus = sub_wire5[11:0];
wire [3:0] rx_pll_locked = sub_wire6[3:0];
wire [7:0] rx_syncstatus = sub_wire7[7:0];
wire [0:0] coreclkout = sub_wire8[0:0];
wire [63:0] rx_dataout = sub_wire9[63:0];
wire [3:0] pipeelecidle = sub_wire10[3:0];
wire [3:0] tx_dataout = sub_wire11[3:0];
wire [7:0] rx_ctrldetect = sub_wire12[7:0];
wire [3:0] pipedatavalid = sub_wire13[3:0];
altpcie_serdes_4sgx_x4d_gen2_08p_alt4gxb_a0ea altpcie_serdes_4sgx_x4d_gen2_08p_alt4gxb_a0ea_component (
.reconfig_togxb (reconfig_togxb),
.cal_blk_clk (cal_blk_clk),
.tx_forceelecidle (tx_forceelecidle),
.rx_datain (rx_datain),
.rx_digitalreset (rx_digitalreset),
.pipe8b10binvpolarity (pipe8b10binvpolarity),
.tx_datain (tx_datain),
.tx_digitalreset (tx_digitalreset),
.tx_pipedeemph (tx_pipedeemph),
.gxb_powerdown (gxb_powerdown),
.rx_cruclk (rx_cruclk),
.tx_forcedispcompliance (tx_forcedispcompliance),
.rateswitch (rateswitch),
.reconfig_clk (reconfig_clk),
.rx_analogreset (rx_analogreset),
.powerdn (powerdn),
.tx_ctrlenable (tx_ctrlenable),
.tx_pipemargin (tx_pipemargin),
.pll_inclk (pll_inclk),
.tx_detectrxloop (tx_detectrxloop),
.rx_patterndetect (sub_wire0),
.pipephydonestatus (sub_wire1),
.pll_locked (sub_wire2),
.reconfig_fromgxb (sub_wire3),
.rx_freqlocked (sub_wire4),
.pipestatus (sub_wire5),
.rx_pll_locked (sub_wire6),
.rx_syncstatus (sub_wire7),
.coreclkout (sub_wire8),
.rx_dataout (sub_wire9),
.pipeelecidle (sub_wire10),
.tx_dataout (sub_wire11),
.rx_ctrldetect (sub_wire12),
.pipedatavalid (sub_wire13))/* synthesis synthesis_clearbox=2
clearbox_macroname = alt4gxb
clearbox_defparam = "effective_data_rate=5000 Mbps;enable_lc_tx_pll=false;equalizer_ctrl_a_setting=0;equalizer_ctrl_b_setting=0;equalizer_ctrl_c_setting=0;equalizer_ctrl_d_setting=0;equalizer_ctrl_v_setting=0;equalizer_dcgain_setting=1;gen_reconfig_pll=false;gxb_analog_power=3.0v;gx_channel_type=AUTO;input_clock_frequency=100.0 MHz;intended_device_family=Stratix IV;intended_device_speed_grade=2;intended_device_variant=GX;loopback_mode=none;lpm_type=alt4gxb;number_of_channels=4;operation_mode=duplex;pll_control_width=1;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=0;protocol=pcie2;receiver_termination=oct_100_ohms;reconfig_dprio_mode=1;rx_8b_10b_mode=normal;rx_align_pattern=0101111100;rx_align_pattern_length=10;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=true;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_bonding=x4;rx_channel_width=16;rx_common_mode=0.82v;rx_cru_bandwidth_type=Auto;rx_cru_inclock0_period=10000;rx_datapath_protocol=pipe;rx_data_rate=5000;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=true;rx_ppmselect=32;rx_rate_match_fifo_mode=normal;rx_rate_match_pattern1=11010000111010000011;rx_rate_match_pattern2=00101111000101111100;rx_rate_match_pattern_size=20;rx_run_length=40;rx_run_length_enable=true;rx_signal_detect_threshold=4;rx_use_align_state_machine=true;
rx_use_clkout=false;rx_use_coreclk=false;rx_use_cruclk=true;rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=true;rx_use_pipe8b10binvpolarity=true;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_analog_power=AUTO;tx_channel_bonding=x4;tx_channel_width=16;tx_clkout_width=4;tx_common_mode=0.65v;tx_data_rate=5000;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=High;tx_pll_inclk0_period=10000;tx_pll_type=CMU;tx_slew_rate=off;tx_transmit_protocol=pipe;tx_use_coreclk=false;tx_use_double_data_mode=true;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=3;coreclkout_control_width=1;elec_idle_infer_enable=false;enable_0ppm=false;gxb_powerdown_width=1;number_of_quads=1;rateswitch_control_width=1;reconfig_calibration=true;reconfig_fromgxb_port_width=17;reconfig_togxb_port_width=4;rx_cdrctrl_enable=true;rx_cru_m_divider=25;rx_cru_n_divider=1;rx_cru_vco_post_scale_divider=1;rx_dwidth_factor=2;rx_signal_detect_loss_threshold=3;rx_signal_detect_valid_threshold=14;rx_use_external_termination=false;rx_word_aligner_num_byte=1;tx_dwidth_factor=2;tx_pll_clock_post_divider=1;tx_pll_m_divider=25;tx_pll_n_divider=1;tx_pll_vco_post_scale_divider=1;tx_use_external_termination=false;" */;
defparam
altpcie_serdes_4sgx_x4d_gen2_08p_alt4gxb_a0ea_component.starting_channel_number = starting_channel_number;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "5000.0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "5000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100.0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100.0"
// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "5000"
// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100.0"
// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 2-x4"
// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "5000 Mbps"
// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
// Retrieval info: CONSTANT: GXB_ANALOG_POWER STRING "3.0v"
// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "100.0 MHz"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "2"
// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "GX"
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "4"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PROTOCOL STRING "pcie2"
// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "x4"
// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Auto"
// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "5000"
// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "4"
// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "true"
// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "AUTO"
// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x4"
// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "4"
// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "5000"
// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "off"
// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "true"
// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "3"
// Retrieval info: CONSTANT: coreclkout_control_width NUMERIC "1"
// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
// Retrieval info: CONSTANT: enable_0ppm STRING "false"
// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
// Retrieval info: CONSTANT: rateswitch_control_width NUMERIC "1"
// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "17"
// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "25"
// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "1"
// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "1"
// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "2"
// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "3"
// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "14"
// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "2"
// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "25"
// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
// Retrieval info: USED_PORT: coreclkout 0 0 1 0 OUTPUT NODEFVAL "coreclkout[0..0]"
// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 4 0 INPUT NODEFVAL "pipe8b10binvpolarity[3..0]"
// Retrieval info: USED_PORT: pipedatavalid 0 0 4 0 OUTPUT NODEFVAL "pipedatavalid[3..0]"
// Retrieval info: USED_PORT: pipeelecidle 0 0 4 0 OUTPUT NODEFVAL "pipeelecidle[3..0]"
// Retrieval info: USED_PORT: pipephydonestatus 0 0 4 0 OUTPUT NODEFVAL "pipephydonestatus[3..0]"
// Retrieval info: USED_PORT: pipestatus 0 0 12 0 OUTPUT NODEFVAL "pipestatus[11..0]"
// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
// Retrieval info: USED_PORT: powerdn 0 0 8 0 INPUT NODEFVAL "powerdn[7..0]"
// Retrieval info: USED_PORT: rateswitch 0 0 1 0 INPUT NODEFVAL "rateswitch[0..0]"
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 17 0 OUTPUT NODEFVAL "reconfig_fromgxb[16..0]"
// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
// Retrieval info: USED_PORT: rx_cruclk 0 0 4 0 INPUT GND "rx_cruclk[3..0]"
// Retrieval info: USED_PORT: rx_ctrldetect 0 0 8 0 OUTPUT NODEFVAL "rx_ctrldetect[7..0]"
// Retrieval info: USED_PORT: rx_datain 0 0 4 0 INPUT NODEFVAL "rx_datain[3..0]"
// Retrieval info: USED_PORT: rx_dataout 0 0 64 0 OUTPUT NODEFVAL "rx_dataout[63..0]"
// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
// Retrieval info: USED_PORT: rx_freqlocked 0 0 4 0 OUTPUT NODEFVAL "rx_freqlocked[3..0]"
// Retrieval info: USED_PORT: rx_patterndetect 0 0 8 0 OUTPUT NODEFVAL "rx_patterndetect[7..0]"
// Retrieval info: USED_PORT: rx_pll_locked 0 0 4 0 OUTPUT NODEFVAL "rx_pll_locked[3..0]"
// Retrieval info: USED_PORT: rx_syncstatus 0 0 8 0 OUTPUT NODEFVAL "rx_syncstatus[7..0]"
// Retrieval info: USED_PORT: tx_ctrlenable 0 0 8 0 INPUT NODEFVAL "tx_ctrlenable[7..0]"
// Retrieval info: USED_PORT: tx_datain 0 0 64 0 INPUT NODEFVAL "tx_datain[63..0]"
// Retrieval info: USED_PORT: tx_dataout 0 0 4 0 OUTPUT NODEFVAL "tx_dataout[3..0]"
// Retrieval info: USED_PORT: tx_detectrxloop 0 0 4 0 INPUT NODEFVAL "tx_detectrxloop[3..0]"
// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 4 0 INPUT NODEFVAL "tx_forcedispcompliance[3..0]"
// Retrieval info: USED_PORT: tx_forceelecidle 0 0 4 0 INPUT NODEFVAL "tx_forceelecidle[3..0]"
// Retrieval info: USED_PORT: tx_pipedeemph 0 0 4 0 INPUT NODEFVAL "tx_pipedeemph[3..0]"
// Retrieval info: USED_PORT: tx_pipemargin 0 0 12 0 INPUT NODEFVAL "tx_pipemargin[11..0]"
// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 4 0 pipe8b10binvpolarity 0 0 4 0
// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
// Retrieval info: CONNECT: @powerdn 0 0 8 0 powerdn 0 0 8 0
// Retrieval info: CONNECT: @rateswitch 0 0 1 0 rateswitch 0 0 1 0
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
// Retrieval info: CONNECT: @rx_cruclk 0 0 4 0 rx_cruclk 0 0 4 0
// Retrieval info: CONNECT: @rx_datain 0 0 4 0 rx_datain 0 0 4 0
// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @tx_ctrlenable 0 0 8 0 tx_ctrlenable 0 0 8 0
// Retrieval info: CONNECT: @tx_datain 0 0 64 0 tx_datain 0 0 64 0
// Retrieval info: CONNECT: @tx_detectrxloop 0 0 4 0 tx_detectrxloop 0 0 4 0
// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 4 0 tx_forcedispcompliance 0 0 4 0
// Retrieval info: CONNECT: @tx_forceelecidle 0 0 4 0 tx_forceelecidle 0 0 4 0
// Retrieval info: CONNECT: @tx_pipedeemph 0 0 4 0 tx_pipedeemph 0 0 4 0
// Retrieval info: CONNECT: @tx_pipemargin 0 0 12 0 tx_pipemargin 0 0 12 0
// Retrieval info: CONNECT: coreclkout 0 0 1 0 @coreclkout 0 0 1 0
// Retrieval info: CONNECT: pipedatavalid 0 0 4 0 @pipedatavalid 0 0 4 0
// Retrieval info: CONNECT: pipeelecidle 0 0 4 0 @pipeelecidle 0 0 4 0
// Retrieval info: CONNECT: pipephydonestatus 0 0 4 0 @pipephydonestatus 0 0 4 0
// Retrieval info: CONNECT: pipestatus 0 0 12 0 @pipestatus 0 0 12 0
// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
// Retrieval info: CONNECT: reconfig_fromgxb 0 0 17 0 @reconfig_fromgxb 0 0 17 0
// Retrieval info: CONNECT: rx_ctrldetect 0 0 8 0 @rx_ctrldetect 0 0 8 0
// Retrieval info: CONNECT: rx_dataout 0 0 64 0 @rx_dataout 0 0 64 0
// Retrieval info: CONNECT: rx_freqlocked 0 0 4 0 @rx_freqlocked 0 0 4 0
// Retrieval info: CONNECT: rx_patterndetect 0 0 8 0 @rx_patterndetect 0 0 8 0
// Retrieval info: CONNECT: rx_pll_locked 0 0 4 0 @rx_pll_locked 0 0 4 0
// Retrieval info: CONNECT: rx_syncstatus 0 0 8 0 @rx_syncstatus 0 0 8 0
// Retrieval info: CONNECT: tx_dataout 0 0 4 0 @tx_dataout 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen2_08p.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen2_08p.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen2_08p.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen2_08p.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen2_08p.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen2_08p_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen2_08p_bb.v TRUE
// Retrieval info: LIB_FILE: stratixiv_hssi
|
`timescale 1 ns / 1 ps
module axi_cfg_register #
(
parameter integer CFG_DATA_WIDTH = 1024,
parameter integer AXI_DATA_WIDTH = 32,
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer CFG_DATA_DEFAULT = 0
)
(
// System signals
input wire aclk,
input wire aresetn,
// Configuration bits
output wire [CFG_DATA_WIDTH-1:0] cfg_data,
// Slave side
input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr, // AXI4-Lite slave: Write address
input wire s_axi_awvalid, // AXI4-Lite slave: Write address valid
output wire s_axi_awready, // AXI4-Lite slave: Write address ready
input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata, // AXI4-Lite slave: Write data
input wire [AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, // AXI4-Lite slave: Write strobe
input wire s_axi_wvalid, // AXI4-Lite slave: Write data valid
output wire s_axi_wready, // AXI4-Lite slave: Write data ready
output wire [1:0] s_axi_bresp, // AXI4-Lite slave: Write response
output wire s_axi_bvalid, // AXI4-Lite slave: Write response valid
input wire s_axi_bready, // AXI4-Lite slave: Write response ready
input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr, // AXI4-Lite slave: Read address
input wire s_axi_arvalid, // AXI4-Lite slave: Read address valid
output wire s_axi_arready, // AXI4-Lite slave: Read address ready
output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata, // AXI4-Lite slave: Read data
output wire [1:0] s_axi_rresp, // AXI4-Lite slave: Read data response
output wire s_axi_rvalid, // AXI4-Lite slave: Read data valid
input wire s_axi_rready // AXI4-Lite slave: Read data ready
);
function integer clogb2 (input integer value);
for(clogb2 = 0; value > 0; clogb2 = clogb2 + 1) value = value >> 1;
endfunction
localparam integer ADDR_LSB = clogb2(AXI_DATA_WIDTH/8 - 1);
localparam integer CFG_SIZE = CFG_DATA_WIDTH/AXI_DATA_WIDTH;
localparam integer CFG_WIDTH = CFG_SIZE > 1 ? clogb2(CFG_SIZE-1) : 1;
reg int_awready_reg, int_awready_next;
reg int_wready_reg, int_wready_next;
reg int_bvalid_reg, int_bvalid_next;
reg int_arready_reg, int_arready_next;
reg int_rvalid_reg, int_rvalid_next;
reg [AXI_DATA_WIDTH-1:0] int_rdata_reg, int_rdata_next;
wire [AXI_DATA_WIDTH-1:0] int_data_mux [CFG_SIZE-1:0];
wire [CFG_DATA_WIDTH-1:0] int_data_wire;
wire [CFG_SIZE-1:0] int_ce_wire;
wire int_wvalid_wire;
genvar j, k;
assign int_wvalid_wire = s_axi_awvalid & s_axi_wvalid;
generate
for(j = 0; j < CFG_SIZE; j = j + 1)
begin : WORDS
assign int_data_mux[j] = int_data_wire[j*AXI_DATA_WIDTH+AXI_DATA_WIDTH-1:j*AXI_DATA_WIDTH];
assign int_ce_wire[j] = int_wvalid_wire & (s_axi_awaddr[ADDR_LSB+CFG_WIDTH-1:ADDR_LSB] == j);
for(k = 0; k < AXI_DATA_WIDTH; k = k + 1)
begin : BITS
FDRE #(
.INIT(1'b0)
) FDRE_inst (
.CE(int_ce_wire[j] & s_axi_wstrb[k/8]),
.C(aclk),
.R(~aresetn),
.D(s_axi_wdata[k]),
.Q(int_data_wire[j*AXI_DATA_WIDTH + k])
);
end
end
endgenerate
always @(posedge aclk)
begin
if(~aresetn)
begin
int_awready_reg <= 1'b0;
int_wready_reg <= 1'b0;
int_bvalid_reg <= 1'b0;
int_arready_reg <= 1'b0;
int_rvalid_reg <= 1'b0;
int_rdata_reg <= {(AXI_DATA_WIDTH){CFG_DATA_DEFAULT}};
end
else
begin
int_awready_reg <= int_awready_next;
int_wready_reg <= int_wready_next;
int_bvalid_reg <= int_bvalid_next;
int_arready_reg <= int_arready_next;
int_rvalid_reg <= int_rvalid_next;
int_rdata_reg <= int_rdata_next;
end
end
always @*
begin
int_awready_next = int_awready_reg;
int_wready_next = int_wready_reg;
int_bvalid_next = int_bvalid_reg;
if(int_wvalid_wire & ~int_awready_reg)
begin
int_awready_next = 1'b1;
int_wready_next = 1'b1;
end
if(int_awready_reg)
begin
int_awready_next = 1'b0;
int_wready_next = 1'b0;
int_bvalid_next = 1'b1;
end
if(s_axi_bready & int_bvalid_reg)
begin
int_bvalid_next = 1'b0;
end
end
always @*
begin
int_arready_next = int_arready_reg;
int_rvalid_next = int_rvalid_reg;
int_rdata_next = int_rdata_reg;
if(s_axi_arvalid)
begin
int_arready_next = 1'b1;
int_rvalid_next = 1'b1;
int_rdata_next = int_data_mux[s_axi_araddr[ADDR_LSB+CFG_WIDTH-1:ADDR_LSB]];
end
if(int_arready_reg)
begin
int_arready_next = 1'b0;
end
if(s_axi_rready & int_rvalid_reg)
begin
int_rvalid_next = 1'b0;
end
end
assign cfg_data = int_data_wire;
assign s_axi_bresp = 2'd0;
assign s_axi_rresp = 2'd0;
assign s_axi_awready = int_awready_reg;
assign s_axi_wready = int_wready_reg;
assign s_axi_bvalid = int_bvalid_reg;
assign s_axi_arready = int_arready_reg;
assign s_axi_rdata = int_rdata_reg;
assign s_axi_rvalid = int_rvalid_reg;
endmodule
|
/*
* Copyright (c) 2001 Stephan Boettcher <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: deposit.v,v 1.4 2001/11/22 04:36:33 sib4 Exp $
// Test for vpi_put_value() to properly propagate in structural context.
module deposit_test;
reg ck;
reg start;
initial start = 0;
`ifdef RTL
reg [3:0] cnt;
wire cnt_tc = &cnt;
always @(posedge ck)
if (start | ~cnt_tc)
cnt <= cnt + 1;
`else // !ifdef RTL
wire [3:0] cnt;
wire [3:0] cnt_1;
wire [3:0] cnt_c;
wire cnt_tc;
wire ne, e;
and (cnt_tc, cnt[0], cnt[1], cnt[2], cnt[3]);
not (ne, cnt_tc);
or (e, ne, start);
had A0 (cnt[0], 1'b1, cnt_c[0], cnt_1[0]);
had A1 (cnt[1], cnt_c[0], cnt_c[1], cnt_1[1]);
had A2 (cnt[2], cnt_c[1], cnt_c[2], cnt_1[2]);
had A3 (cnt[3], cnt_c[2], cnt_c[3], cnt_1[3]);
dffe C0 (ck, e, cnt_1[0], cnt[0]);
dffe C1 (ck, e, cnt_1[1], cnt[1]);
dffe C2 (ck, e, cnt_1[2], cnt[2]);
dffe C3 (ck, e, cnt_1[3], cnt[3]);
`endif // !ifdef RTL
integer r0; initial r0 = 0;
integer r1; initial r1 = 0;
always
begin
#5 ck <= 0;
#4;
$display("%b %b %d %d", cnt, cnt_tc, r0, r1);
if (cnt_tc === 1'b0) r0 = r0 + 1;
if (cnt_tc === 1'b1) r1 = r1 + 1;
#1 ck <= 1;
end
initial
begin
// $dumpfile("deposit.vcd");
// $dumpvars(0, deposit_test);
#22;
`ifdef RTL
cnt <= 4'b 1010;
`else
$deposit(C0.Q, 1'b0);
$deposit(C1.Q, 1'b1);
$deposit(C2.Q, 1'b0);
$deposit(C3.Q, 1'b1);
`endif
#1 if (cnt !== 4'b1010)
$display("FAILED");
#99;
$display("%d/%d", r0, r1);
if (r0===5 && r1===5)
$display("PASSED");
else
$display("FAILED");
$finish;
end
endmodule
`ifdef RTL
`else
module dffe (CK, E, D, Q);
input CK, E, D;
output Q;
wire qq;
UDP_dffe ff (qq, CK, E, D);
buf #1 (Q, qq);
endmodule
primitive UDP_dffe (q, cp, e, d);
output q;
reg q;
input cp, e, d;
table
(01) 1 1 : ? : 1 ;
(01) 1 0 : ? : 0 ;
* 0 ? : ? : - ;
* ? 1 : 1 : - ;
* ? 0 : 0 : - ;
(1x) ? ? : ? : - ;
(?0) ? ? : ? : - ;
? ? * : ? : - ;
? * ? : ? : - ;
endtable
endprimitive
module had (A, B, C, S);
input A, B;
output C, S;
xor s (S, A, B);
and c (C, A, B);
endmodule
`endif // !ifdef RTL
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_gep(clock, resetn,
i_addressin, i_addressin_valid, o_addressin_stall,
i_indexin, i_indexin_valid, o_indexin_stall,
o_dataout, i_stall, o_dataout_valid,
i_settings, i_offset_settings);
parameter ADDRESS_WIDTH = 32;
parameter INDEX_WIDTH = 32;
parameter CONFIG_WIDTH = 5;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [ADDRESS_WIDTH-1:0] i_addressin;
input i_addressin_valid;
output o_addressin_stall;
input [INDEX_WIDTH-1:0] i_indexin;
input i_indexin_valid;
output o_indexin_stall;
output [ADDRESS_WIDTH-1:0] o_dataout;
input i_stall;
output o_dataout_valid;
input [CONFIG_WIDTH-1:0] i_settings;
input [ADDRESS_WIDTH-1:0] i_offset_settings;
wire [ADDRESS_WIDTH-1:0] addressin_from_fifo;
wire [ADDRESS_WIDTH-1:0] addressin;
wire [INDEX_WIDTH-1:0] indexin_from_fifo;
wire [INDEX_WIDTH-1:0] indexin;
wire is_fifo_a_valid;
wire is_fifo_b_valid;
wire is_stalled;
wire [CONFIG_WIDTH-2:0] index_shift_settings;
wire is_index_connected;
wire is_addressin_zero;
assign index_shift_settings = i_settings[CONFIG_WIDTH-1:2];
assign is_index_connected = i_settings[1];
assign is_addressin_zero = i_settings[0];
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(i_addressin), .data_out(addressin_from_fifo), .valid_in(i_addressin_valid),
.valid_out( is_fifo_a_valid ), .stall_in(is_stalled), .stall_out(o_addressin_stall) );
defparam fifo_a.DATA_WIDTH = ADDRESS_WIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_b ( .clock(clock), .resetn(resetn),
.data_in(i_indexin), .data_out(indexin_from_fifo), .valid_in(i_indexin_valid),
.valid_out( is_fifo_b_valid ), .stall_in(is_stalled), .stall_out(o_indexin_stall) );
defparam fifo_b.DATA_WIDTH = INDEX_WIDTH;
defparam fifo_b.DEPTH = FIFO_DEPTH;
assign is_stalled = ~((is_addressin_zero | is_fifo_a_valid) &
(is_fifo_b_valid | ~is_index_connected) & ~i_stall);
assign addressin = is_addressin_zero ? {ADDRESS_WIDTH{1'b0}} : addressin_from_fifo;
assign indexin = is_index_connected ? indexin_from_fifo : {INDEX_WIDTH{1'b0}};
assign o_dataout = addressin + (indexin << index_shift_settings) + i_offset_settings;
assign o_dataout_valid = (is_addressin_zero | is_fifo_a_valid) & (is_fifo_b_valid | ~is_index_connected);
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate repeat concatenation literal behavior.
//
module test ();
wire [7:0] result;
assign result = {2{4'b1011}};
initial
begin
#1;
if(result === 8'b10111011)
$display("PASSED");
else
$display("FAILED - {2{4'b1011}} s/b 8'b10111011 - is %b",result);
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized OR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_carry_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = CIN | S;
end else begin : USE_FPGA
wire S_n;
assign S_n = ~S;
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (1'b1),
.S (S_n)
);
end
endgenerate
endmodule
|
module ISP1362_IF( // avalon MM slave port, ISP1362, host control
// avalon MM slave, hc interface to nios
avs_hc_writedata_iDATA,
avs_hc_readdata_oDATA,
avs_hc_address_iADDR,
avs_hc_read_n_iRD_N,
avs_hc_write_n_iWR_N,
avs_hc_chipselect_n_iCS_N,
avs_hc_reset_n_iRST_N,
avs_hc_clk_iCLK,
avs_hc_irq_n_oINT0_N,
// avalon MM slave, dcc interface to nios
avs_dc_writedata_iDATA,
avs_dc_readdata_oDATA,
avs_dc_address_iADDR,
avs_dc_read_n_iRD_N,
avs_dc_write_n_iWR_N,
avs_dc_chipselect_n_iCS_N,
avs_dc_reset_n_iRST_N,
avs_dc_clk_iCLK,
avs_dc_irq_n_oINT0_N,
// ISP1362 Side
USB_DATA,
USB_ADDR,
USB_RD_N,
USB_WR_N,
USB_CS_N,
USB_RST_N,
USB_INT0,
USB_INT1
);
// to nios
// slave hc
input [15:0] avs_hc_writedata_iDATA;
input avs_hc_address_iADDR;
input avs_hc_read_n_iRD_N;
input avs_hc_write_n_iWR_N;
input avs_hc_chipselect_n_iCS_N;
input avs_hc_reset_n_iRST_N;
input avs_hc_clk_iCLK;
output [15:0] avs_hc_readdata_oDATA;
output avs_hc_irq_n_oINT0_N;
// slave dc
input [15:0] avs_dc_writedata_iDATA;
input avs_dc_address_iADDR;
input avs_dc_read_n_iRD_N;
input avs_dc_write_n_iWR_N;
input avs_dc_chipselect_n_iCS_N;
input avs_dc_reset_n_iRST_N;
input avs_dc_clk_iCLK;
output [15:0] avs_dc_readdata_oDATA;
output avs_dc_irq_n_oINT0_N;
// ISP1362 Side
inout [15:0] USB_DATA;
output [1:0] USB_ADDR;
output USB_RD_N;
output USB_WR_N;
output USB_CS_N;
output USB_RST_N;
input USB_INT0;
input USB_INT1;
assign USB_DATA = avs_dc_chipselect_n_iCS_N ? (avs_hc_write_n_iWR_N ? 16'hzzzz : avs_hc_writedata_iDATA) : (avs_dc_write_n_iWR_N ? 16'hzzzz : avs_dc_writedata_iDATA) ;
assign avs_hc_readdata_oDATA = avs_hc_read_n_iRD_N ? 16'hzzzz : USB_DATA;
assign avs_dc_readdata_oDATA = avs_dc_read_n_iRD_N ? 16'hzzzz : USB_DATA;
assign USB_ADDR = avs_dc_chipselect_n_iCS_N? {1'b0,avs_hc_address_iADDR} : {1'b1,avs_dc_address_iADDR};
assign USB_CS_N = avs_hc_chipselect_n_iCS_N & avs_dc_chipselect_n_iCS_N;
assign USB_WR_N = avs_dc_chipselect_n_iCS_N? avs_hc_write_n_iWR_N : avs_dc_write_n_iWR_N;
assign USB_RD_N = avs_dc_chipselect_n_iCS_N? avs_hc_read_n_iRD_N : avs_dc_read_n_iRD_N;
assign USB_RST_N = avs_dc_chipselect_n_iCS_N? avs_hc_reset_n_iRST_N: avs_dc_reset_n_iRST_N;
assign avs_hc_irq_n_oINT0_N = USB_INT0;
assign avs_dc_irq_n_oINT0_N = USB_INT1;
endmodule |
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_modf_s5 (
enable,
clock,
dataa,
datab,
result);
input enable;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_modf_s5 inst (
.en (enable),
.areset(1'b0),
.clk(clock),
.a(dataa),
.b(datab),
.q(sub_wire0));
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_fsub(clock, resetn,
i_dataa, i_dataa_valid, o_dataa_stall,
i_datab, i_datab_valid, o_datab_stall,
o_dataout, o_dataout_valid, i_stall);
parameter DATA_WIDTH = 32;
parameter LATENCY = 8;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [DATA_WIDTH-1:0] i_dataa;
input [DATA_WIDTH-1:0] i_datab;
input i_dataa_valid, i_datab_valid;
output o_dataa_stall, o_datab_stall;
output [DATA_WIDTH-1:0] o_dataout;
output o_dataout_valid;
input i_stall;
wire [DATA_WIDTH-1:0] dataa, datab, datab_neg;
wire is_fifo_a_valid, is_fifo_b_valid;
wire is_fifo_stalled, is_fsub_stalled;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(i_dataa), .data_out(dataa), .valid_in(i_dataa_valid),
.valid_out( is_fifo_a_valid ), .stall_in(is_fifo_stalled), .stall_out(o_dataa_stall) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_b ( .clock(clock), .resetn(resetn),
.data_in(i_datab), .data_out(datab), .valid_in(i_datab_valid),
.valid_out( is_fifo_b_valid ), .stall_in(is_fifo_stalled), .stall_out(o_datab_stall) );
defparam fifo_b.DATA_WIDTH = DATA_WIDTH;
defparam fifo_b.DEPTH = FIFO_DEPTH;
assign is_fifo_stalled = ~(is_fifo_a_valid & is_fifo_b_valid) | is_fsub_stalled;
assign datab_neg = {~datab[DATA_WIDTH-1],datab[DATA_WIDTH-2:0]};
acl_fp_custom_add_ll_hc fsub_unit(
.clock(clock), .resetn(resetn), .dataa(dataa), .datab(datab_neg),
.result(o_dataout), .valid_in(is_fifo_a_valid & is_fifo_b_valid),
.valid_out(o_dataout_valid),
.stall_in(i_stall), .stall_out(is_fsub_stalled));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SEDFXTP_1_V
`define SKY130_FD_SC_MS__SEDFXTP_1_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog wrapper for sedfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sedfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sedfxtp_1 (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sedfxtp_1 (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SEDFXTP_1_V
|
// CONFIG:
// NUM_COEFF = 38
// PIPLINED = 0
// WARNING: more than enough COEFFICIENTS in array (there are 26, and we only need 19)
module fir (
clk,
reset,
clk_ena,
i_valid,
i_in,
o_valid,
o_out
);
// Data Width
parameter dw = 18; //Data input/output bits
// Number of filter coefficients
parameter N = 38;
parameter N_UNIQ = 19; // ciel(N/2) assuming symmetric filter coefficients
//Number of extra valid cycles needed to align output (i.e. computation pipeline depth + input/output registers
localparam N_VALID_REGS = 39;
input clk;
input reset;
input clk_ena;
input i_valid;
input [dw-1:0] i_in; // signed
output o_valid;
output [dw-1:0] o_out; // signed
// Data Width dervied parameters
localparam dw_add_int = 18; //Internal adder precision bits
localparam dw_mult_int = 36; //Internal multiplier precision bits
localparam scale_factor = 17; //Multiplier normalization shift amount
// Number of extra registers in INPUT_PIPELINE_REG to prevent contention for CHAIN_END's chain adders
localparam N_INPUT_REGS = 38;
// Debug
// initial begin
// $display ("Data Width: %d", dw);
// $display ("Data Width Add Internal: %d", dw_add_int);
// $display ("Data Width Mult Internal: %d", dw_mult_int);
// $display ("Scale Factor: %d", scale_factor);
// end
reg [dw-1:0] COEFFICIENT_0;
reg [dw-1:0] COEFFICIENT_1;
reg [dw-1:0] COEFFICIENT_2;
reg [dw-1:0] COEFFICIENT_3;
reg [dw-1:0] COEFFICIENT_4;
reg [dw-1:0] COEFFICIENT_5;
reg [dw-1:0] COEFFICIENT_6;
reg [dw-1:0] COEFFICIENT_7;
reg [dw-1:0] COEFFICIENT_8;
reg [dw-1:0] COEFFICIENT_9;
reg [dw-1:0] COEFFICIENT_10;
reg [dw-1:0] COEFFICIENT_11;
reg [dw-1:0] COEFFICIENT_12;
reg [dw-1:0] COEFFICIENT_13;
reg [dw-1:0] COEFFICIENT_14;
reg [dw-1:0] COEFFICIENT_15;
reg [dw-1:0] COEFFICIENT_16;
reg [dw-1:0] COEFFICIENT_17;
reg [dw-1:0] COEFFICIENT_18;
always@(posedge clk) begin
COEFFICIENT_0 <= 18'd88;
COEFFICIENT_1 <= 18'd0;
COEFFICIENT_2 <= -18'd97;
COEFFICIENT_3 <= -18'd197;
COEFFICIENT_4 <= -18'd294;
COEFFICIENT_5 <= -18'd380;
COEFFICIENT_6 <= -18'd447;
COEFFICIENT_7 <= -18'd490;
COEFFICIENT_8 <= -18'd504;
COEFFICIENT_9 <= -18'd481;
COEFFICIENT_10 <= -18'd420;
COEFFICIENT_11 <= -18'd319;
COEFFICIENT_12 <= -18'd178;
COEFFICIENT_13 <= 18'd0;
COEFFICIENT_14 <= 18'd212;
COEFFICIENT_15 <= 18'd451;
COEFFICIENT_16 <= 18'd710;
COEFFICIENT_17 <= 18'd980;
COEFFICIENT_18 <= 18'd1252;
end
////******************************************************
// *
// * Valid Delay Pipeline
// *
// *****************************************************
//Input valid signal is pipelined to become output valid signal
//Valid registers
reg [N_VALID_REGS-1:0] VALID_PIPELINE_REGS;
always@(posedge clk or posedge reset) begin
if(reset) begin
VALID_PIPELINE_REGS <= 0;
end else begin
if(clk_ena) begin
VALID_PIPELINE_REGS <= {VALID_PIPELINE_REGS[N_VALID_REGS-2:0], i_valid};
end else begin
VALID_PIPELINE_REGS <= VALID_PIPELINE_REGS;
end
end
end
////******************************************************
// *
// * Input Register Pipeline
// *
// *****************************************************
//Pipelined input values
//Input value registers
wire [dw-1:0] INPUT_PIPELINE_REG_0;
wire [dw-1:0] INPUT_PIPELINE_REG_1;
wire [dw-1:0] INPUT_PIPELINE_REG_2;
wire [dw-1:0] INPUT_PIPELINE_REG_3;
wire [dw-1:0] INPUT_PIPELINE_REG_4;
wire [dw-1:0] INPUT_PIPELINE_REG_5;
wire [dw-1:0] INPUT_PIPELINE_REG_6;
wire [dw-1:0] INPUT_PIPELINE_REG_7;
wire [dw-1:0] INPUT_PIPELINE_REG_8;
wire [dw-1:0] INPUT_PIPELINE_REG_9;
wire [dw-1:0] INPUT_PIPELINE_REG_10;
wire [dw-1:0] INPUT_PIPELINE_REG_11;
wire [dw-1:0] INPUT_PIPELINE_REG_12;
wire [dw-1:0] INPUT_PIPELINE_REG_13;
wire [dw-1:0] INPUT_PIPELINE_REG_14;
wire [dw-1:0] INPUT_PIPELINE_REG_15;
wire [dw-1:0] INPUT_PIPELINE_REG_16;
wire [dw-1:0] INPUT_PIPELINE_REG_17;
wire [dw-1:0] INPUT_PIPELINE_REG_18;
wire [dw-1:0] INPUT_PIPELINE_REG_19;
wire [dw-1:0] INPUT_PIPELINE_REG_20;
wire [dw-1:0] INPUT_PIPELINE_REG_21;
wire [dw-1:0] INPUT_PIPELINE_REG_22;
wire [dw-1:0] INPUT_PIPELINE_REG_23;
wire [dw-1:0] INPUT_PIPELINE_REG_24;
wire [dw-1:0] INPUT_PIPELINE_REG_25;
wire [dw-1:0] INPUT_PIPELINE_REG_26;
wire [dw-1:0] INPUT_PIPELINE_REG_27;
wire [dw-1:0] INPUT_PIPELINE_REG_28;
wire [dw-1:0] INPUT_PIPELINE_REG_29;
wire [dw-1:0] INPUT_PIPELINE_REG_30;
wire [dw-1:0] INPUT_PIPELINE_REG_31;
wire [dw-1:0] INPUT_PIPELINE_REG_32;
wire [dw-1:0] INPUT_PIPELINE_REG_33;
wire [dw-1:0] INPUT_PIPELINE_REG_34;
wire [dw-1:0] INPUT_PIPELINE_REG_35;
wire [dw-1:0] INPUT_PIPELINE_REG_36;
wire [dw-1:0] INPUT_PIPELINE_REG_37;
input_pipeline in_pipe(
.clk(clk), .clk_ena(clk_ena),
.in_stream(i_in),
.pipeline_reg_0(INPUT_PIPELINE_REG_0),
.pipeline_reg_1(INPUT_PIPELINE_REG_1),
.pipeline_reg_2(INPUT_PIPELINE_REG_2),
.pipeline_reg_3(INPUT_PIPELINE_REG_3),
.pipeline_reg_4(INPUT_PIPELINE_REG_4),
.pipeline_reg_5(INPUT_PIPELINE_REG_5),
.pipeline_reg_6(INPUT_PIPELINE_REG_6),
.pipeline_reg_7(INPUT_PIPELINE_REG_7),
.pipeline_reg_8(INPUT_PIPELINE_REG_8),
.pipeline_reg_9(INPUT_PIPELINE_REG_9),
.pipeline_reg_10(INPUT_PIPELINE_REG_10),
.pipeline_reg_11(INPUT_PIPELINE_REG_11),
.pipeline_reg_12(INPUT_PIPELINE_REG_12),
.pipeline_reg_13(INPUT_PIPELINE_REG_13),
.pipeline_reg_14(INPUT_PIPELINE_REG_14),
.pipeline_reg_15(INPUT_PIPELINE_REG_15),
.pipeline_reg_16(INPUT_PIPELINE_REG_16),
.pipeline_reg_17(INPUT_PIPELINE_REG_17),
.pipeline_reg_18(INPUT_PIPELINE_REG_18),
.pipeline_reg_19(INPUT_PIPELINE_REG_19),
.pipeline_reg_20(INPUT_PIPELINE_REG_20),
.pipeline_reg_21(INPUT_PIPELINE_REG_21),
.pipeline_reg_22(INPUT_PIPELINE_REG_22),
.pipeline_reg_23(INPUT_PIPELINE_REG_23),
.pipeline_reg_24(INPUT_PIPELINE_REG_24),
.pipeline_reg_25(INPUT_PIPELINE_REG_25),
.pipeline_reg_26(INPUT_PIPELINE_REG_26),
.pipeline_reg_27(INPUT_PIPELINE_REG_27),
.pipeline_reg_28(INPUT_PIPELINE_REG_28),
.pipeline_reg_29(INPUT_PIPELINE_REG_29),
.pipeline_reg_30(INPUT_PIPELINE_REG_30),
.pipeline_reg_31(INPUT_PIPELINE_REG_31),
.pipeline_reg_32(INPUT_PIPELINE_REG_32),
.pipeline_reg_33(INPUT_PIPELINE_REG_33),
.pipeline_reg_34(INPUT_PIPELINE_REG_34),
.pipeline_reg_35(INPUT_PIPELINE_REG_35),
.pipeline_reg_36(INPUT_PIPELINE_REG_36),
.pipeline_reg_37(INPUT_PIPELINE_REG_37),
.reset(reset) );
defparam in_pipe.WIDTH = 18; // = dw
////******************************************************
// *
// * Computation Pipeline
// *
// *****************************************************
// ************************* LEVEL 0 ************************* \\
wire [dw-1:0] L0_output_wires_0;
wire [dw-1:0] L0_output_wires_1;
wire [dw-1:0] L0_output_wires_2;
wire [dw-1:0] L0_output_wires_3;
wire [dw-1:0] L0_output_wires_4;
wire [dw-1:0] L0_output_wires_5;
wire [dw-1:0] L0_output_wires_6;
wire [dw-1:0] L0_output_wires_7;
wire [dw-1:0] L0_output_wires_8;
wire [dw-1:0] L0_output_wires_9;
wire [dw-1:0] L0_output_wires_10;
wire [dw-1:0] L0_output_wires_11;
wire [dw-1:0] L0_output_wires_12;
wire [dw-1:0] L0_output_wires_13;
wire [dw-1:0] L0_output_wires_14;
wire [dw-1:0] L0_output_wires_15;
wire [dw-1:0] L0_output_wires_16;
wire [dw-1:0] L0_output_wires_17;
wire [dw-1:0] L0_output_wires_18;
adder_with_1_reg L0_adder_0and37(
.dataa (INPUT_PIPELINE_REG_0),
.datab (INPUT_PIPELINE_REG_37),
.result(L0_output_wires_0)
);
adder_with_1_reg L0_adder_1and36(
.dataa (INPUT_PIPELINE_REG_1),
.datab (INPUT_PIPELINE_REG_36),
.result(L0_output_wires_1)
);
adder_with_1_reg L0_adder_2and35(
.dataa (INPUT_PIPELINE_REG_2),
.datab (INPUT_PIPELINE_REG_35),
.result(L0_output_wires_2)
);
adder_with_1_reg L0_adder_3and34(
.dataa (INPUT_PIPELINE_REG_3),
.datab (INPUT_PIPELINE_REG_34),
.result(L0_output_wires_3)
);
adder_with_1_reg L0_adder_4and33(
.dataa (INPUT_PIPELINE_REG_4),
.datab (INPUT_PIPELINE_REG_33),
.result(L0_output_wires_4)
);
adder_with_1_reg L0_adder_5and32(
.dataa (INPUT_PIPELINE_REG_5),
.datab (INPUT_PIPELINE_REG_32),
.result(L0_output_wires_5)
);
adder_with_1_reg L0_adder_6and31(
.dataa (INPUT_PIPELINE_REG_6),
.datab (INPUT_PIPELINE_REG_31),
.result(L0_output_wires_6)
);
adder_with_1_reg L0_adder_7and30(
.dataa (INPUT_PIPELINE_REG_7),
.datab (INPUT_PIPELINE_REG_30),
.result(L0_output_wires_7)
);
adder_with_1_reg L0_adder_8and29(
.dataa (INPUT_PIPELINE_REG_8),
.datab (INPUT_PIPELINE_REG_29),
.result(L0_output_wires_8)
);
adder_with_1_reg L0_adder_9and28(
.dataa (INPUT_PIPELINE_REG_9),
.datab (INPUT_PIPELINE_REG_28),
.result(L0_output_wires_9)
);
adder_with_1_reg L0_adder_10and27(
.dataa (INPUT_PIPELINE_REG_10),
.datab (INPUT_PIPELINE_REG_27),
.result(L0_output_wires_10)
);
adder_with_1_reg L0_adder_11and26(
.dataa (INPUT_PIPELINE_REG_11),
.datab (INPUT_PIPELINE_REG_26),
.result(L0_output_wires_11)
);
adder_with_1_reg L0_adder_12and25(
.dataa (INPUT_PIPELINE_REG_12),
.datab (INPUT_PIPELINE_REG_25),
.result(L0_output_wires_12)
);
adder_with_1_reg L0_adder_13and24(
.dataa (INPUT_PIPELINE_REG_13),
.datab (INPUT_PIPELINE_REG_24),
.result(L0_output_wires_13)
);
adder_with_1_reg L0_adder_14and23(
.dataa (INPUT_PIPELINE_REG_14),
.datab (INPUT_PIPELINE_REG_23),
.result(L0_output_wires_14)
);
adder_with_1_reg L0_adder_15and22(
.dataa (INPUT_PIPELINE_REG_15),
.datab (INPUT_PIPELINE_REG_22),
.result(L0_output_wires_15)
);
adder_with_1_reg L0_adder_16and21(
.dataa (INPUT_PIPELINE_REG_16),
.datab (INPUT_PIPELINE_REG_21),
.result(L0_output_wires_16)
);
adder_with_1_reg L0_adder_17and20(
.dataa (INPUT_PIPELINE_REG_17),
.datab (INPUT_PIPELINE_REG_20),
.result(L0_output_wires_17)
);
adder_with_1_reg L0_adder_18and19(
.dataa (INPUT_PIPELINE_REG_18),
.datab (INPUT_PIPELINE_REG_19),
.result(L0_output_wires_18)
);
// (19 main tree Adders)
// ************************* LEVEL 1 ************************* \\
// **************** Multipliers **************** \\
wire [dw-1:0] L1_mult_wires_0;
wire [dw-1:0] L1_mult_wires_1;
wire [dw-1:0] L1_mult_wires_2;
wire [dw-1:0] L1_mult_wires_3;
wire [dw-1:0] L1_mult_wires_4;
wire [dw-1:0] L1_mult_wires_5;
wire [dw-1:0] L1_mult_wires_6;
wire [dw-1:0] L1_mult_wires_7;
wire [dw-1:0] L1_mult_wires_8;
wire [dw-1:0] L1_mult_wires_9;
wire [dw-1:0] L1_mult_wires_10;
wire [dw-1:0] L1_mult_wires_11;
wire [dw-1:0] L1_mult_wires_12;
wire [dw-1:0] L1_mult_wires_13;
wire [dw-1:0] L1_mult_wires_14;
wire [dw-1:0] L1_mult_wires_15;
wire [dw-1:0] L1_mult_wires_16;
wire [dw-1:0] L1_mult_wires_17;
wire [dw-1:0] L1_mult_wires_18;
multiplier_with_reg L1_mul_0(
.dataa (L0_output_wires_0),
.datab (COEFFICIENT_0),
.result(L1_mult_wires_0)
);
multiplier_with_reg L1_mul_1(
.dataa (L0_output_wires_1),
.datab (COEFFICIENT_1),
.result(L1_mult_wires_1)
);
multiplier_with_reg L1_mul_2(
.dataa (L0_output_wires_2),
.datab (COEFFICIENT_2),
.result(L1_mult_wires_2)
);
multiplier_with_reg L1_mul_3(
.dataa (L0_output_wires_3),
.datab (COEFFICIENT_3),
.result(L1_mult_wires_3)
);
multiplier_with_reg L1_mul_4(
.dataa (L0_output_wires_4),
.datab (COEFFICIENT_4),
.result(L1_mult_wires_4)
);
multiplier_with_reg L1_mul_5(
.dataa (L0_output_wires_5),
.datab (COEFFICIENT_5),
.result(L1_mult_wires_5)
);
multiplier_with_reg L1_mul_6(
.dataa (L0_output_wires_6),
.datab (COEFFICIENT_6),
.result(L1_mult_wires_6)
);
multiplier_with_reg L1_mul_7(
.dataa (L0_output_wires_7),
.datab (COEFFICIENT_7),
.result(L1_mult_wires_7)
);
multiplier_with_reg L1_mul_8(
.dataa (L0_output_wires_8),
.datab (COEFFICIENT_8),
.result(L1_mult_wires_8)
);
multiplier_with_reg L1_mul_9(
.dataa (L0_output_wires_9),
.datab (COEFFICIENT_9),
.result(L1_mult_wires_9)
);
multiplier_with_reg L1_mul_10(
.dataa (L0_output_wires_10),
.datab (COEFFICIENT_10),
.result(L1_mult_wires_10)
);
multiplier_with_reg L1_mul_11(
.dataa (L0_output_wires_11),
.datab (COEFFICIENT_11),
.result(L1_mult_wires_11)
);
multiplier_with_reg L1_mul_12(
.dataa (L0_output_wires_12),
.datab (COEFFICIENT_12),
.result(L1_mult_wires_12)
);
multiplier_with_reg L1_mul_13(
.dataa (L0_output_wires_13),
.datab (COEFFICIENT_13),
.result(L1_mult_wires_13)
);
multiplier_with_reg L1_mul_14(
.dataa (L0_output_wires_14),
.datab (COEFFICIENT_14),
.result(L1_mult_wires_14)
);
multiplier_with_reg L1_mul_15(
.dataa (L0_output_wires_15),
.datab (COEFFICIENT_15),
.result(L1_mult_wires_15)
);
multiplier_with_reg L1_mul_16(
.dataa (L0_output_wires_16),
.datab (COEFFICIENT_16),
.result(L1_mult_wires_16)
);
multiplier_with_reg L1_mul_17(
.dataa (L0_output_wires_17),
.datab (COEFFICIENT_17),
.result(L1_mult_wires_17)
);
multiplier_with_reg L1_mul_18(
.dataa (L0_output_wires_18),
.datab (COEFFICIENT_18),
.result(L1_mult_wires_18)
);
// (19 Multipliers)
// **************** Adders **************** \\
wire [dw-1:0] L1_output_wires_0;
wire [dw-1:0] L1_output_wires_1;
wire [dw-1:0] L1_output_wires_2;
wire [dw-1:0] L1_output_wires_3;
wire [dw-1:0] L1_output_wires_4;
wire [dw-1:0] L1_output_wires_5;
wire [dw-1:0] L1_output_wires_6;
wire [dw-1:0] L1_output_wires_7;
wire [dw-1:0] L1_output_wires_8;
wire [dw-1:0] L1_output_wires_9;
adder_with_1_reg L1_adder_0and1(
.dataa (L1_mult_wires_0),
.datab (L1_mult_wires_1),
.result(L1_output_wires_0)
);
adder_with_1_reg L1_adder_2and3(
.dataa (L1_mult_wires_2),
.datab (L1_mult_wires_3),
.result(L1_output_wires_1)
);
adder_with_1_reg L1_adder_4and5(
.dataa (L1_mult_wires_4),
.datab (L1_mult_wires_5),
.result(L1_output_wires_2)
);
adder_with_1_reg L1_adder_6and7(
.dataa (L1_mult_wires_6),
.datab (L1_mult_wires_7),
.result(L1_output_wires_3)
);
adder_with_1_reg L1_adder_8and9(
.dataa (L1_mult_wires_8),
.datab (L1_mult_wires_9),
.result(L1_output_wires_4)
);
adder_with_1_reg L1_adder_10and11(
.dataa (L1_mult_wires_10),
.datab (L1_mult_wires_11),
.result(L1_output_wires_5)
);
adder_with_1_reg L1_adder_12and13(
.dataa (L1_mult_wires_12),
.datab (L1_mult_wires_13),
.result(L1_output_wires_6)
);
adder_with_1_reg L1_adder_14and15(
.dataa (L1_mult_wires_14),
.datab (L1_mult_wires_15),
.result(L1_output_wires_7)
);
adder_with_1_reg L1_adder_16and17(
.dataa (L1_mult_wires_16),
.datab (L1_mult_wires_17),
.result(L1_output_wires_8)
);
// (9 main tree Adders)
// ********* Byes ******** \\
one_register L1_byereg_for_18(
.dataa (L1_mult_wires_18),
.result(L1_output_wires_9)
);
// (1 byes)
// ************************* LEVEL 2 ************************* \\
wire [dw-1:0] L2_output_wires_0;
wire [dw-1:0] L2_output_wires_1;
wire [dw-1:0] L2_output_wires_2;
wire [dw-1:0] L2_output_wires_3;
wire [dw-1:0] L2_output_wires_4;
adder_with_1_reg L2_adder_0and1(
.dataa (L1_output_wires_0),
.datab (L1_output_wires_1),
.result(L2_output_wires_0)
);
adder_with_1_reg L2_adder_2and3(
.dataa (L1_output_wires_2),
.datab (L1_output_wires_3),
.result(L2_output_wires_1)
);
adder_with_1_reg L2_adder_4and5(
.dataa (L1_output_wires_4),
.datab (L1_output_wires_5),
.result(L2_output_wires_2)
);
adder_with_1_reg L2_adder_6and7(
.dataa (L1_output_wires_6),
.datab (L1_output_wires_7),
.result(L2_output_wires_3)
);
adder_with_1_reg L2_adder_8and9(
.dataa (L1_output_wires_8),
.datab (L1_output_wires_9),
.result(L2_output_wires_4)
);
// (5 main tree Adders)
// ************************* LEVEL 3 ************************* \\
wire [dw-1:0] L3_output_wires_0;
wire [dw-1:0] L3_output_wires_1;
wire [dw-1:0] L3_output_wires_2;
adder_with_1_reg L3_adder_0and1(
.dataa (L2_output_wires_0),
.datab (L2_output_wires_1),
.result(L3_output_wires_0)
);
adder_with_1_reg L3_adder_2and3(
.dataa (L2_output_wires_2),
.datab (L2_output_wires_3),
.result(L3_output_wires_1)
);
// (2 main tree Adders)
// ********* Byes ******** \\
one_register L3_byereg_for_4(
.dataa (L2_output_wires_4),
.result(L3_output_wires_2)
);
// (1 byes)
// ************************* LEVEL 4 ************************* \\
wire [dw-1:0] L4_output_wires_0;
wire [dw-1:0] L4_output_wires_1;
adder_with_1_reg L4_adder_0and1(
.dataa (L3_output_wires_0),
.datab (L3_output_wires_1),
.result(L4_output_wires_0)
);
// (1 main tree Adders)
// ********* Byes ******** \\
one_register L4_byereg_for_2(
.dataa (L3_output_wires_2),
.result(L4_output_wires_1)
);
// (1 byes)
// ************************* LEVEL 5 ************************* \\
wire [dw-1:0] L5_output_wires_0;
adder_with_1_reg L5_adder_0and1(
.dataa (L4_output_wires_0),
.datab (L4_output_wires_1),
.result(L5_output_wires_0)
);
// (1 main tree Adders)
////******************************************************
// *
// * Output Logic
// *
// *****************************************************
//Actual outputs
reg [17:0] o_out;
always @(posedge clk) begin
if(clk_ena) begin
o_out <= L5_output_wires_0;
end
end
assign o_valid = VALID_PIPELINE_REGS[N_VALID_REGS-1];
endmodule
module input_pipeline (
clk,
clk_ena,
in_stream,
pipeline_reg_0,
pipeline_reg_1,
pipeline_reg_2,
pipeline_reg_3,
pipeline_reg_4,
pipeline_reg_5,
pipeline_reg_6,
pipeline_reg_7,
pipeline_reg_8,
pipeline_reg_9,
pipeline_reg_10,
pipeline_reg_11,
pipeline_reg_12,
pipeline_reg_13,
pipeline_reg_14,
pipeline_reg_15,
pipeline_reg_16,
pipeline_reg_17,
pipeline_reg_18,
pipeline_reg_19,
pipeline_reg_20,
pipeline_reg_21,
pipeline_reg_22,
pipeline_reg_23,
pipeline_reg_24,
pipeline_reg_25,
pipeline_reg_26,
pipeline_reg_27,
pipeline_reg_28,
pipeline_reg_29,
pipeline_reg_30,
pipeline_reg_31,
pipeline_reg_32,
pipeline_reg_33,
pipeline_reg_34,
pipeline_reg_35,
pipeline_reg_36,
pipeline_reg_37,
reset);
parameter WIDTH = 1;
//Input value registers
input clk;
input clk_ena;
input [WIDTH-1:0] in_stream;
output [WIDTH-1:0] pipeline_reg_0;
output [WIDTH-1:0] pipeline_reg_1;
output [WIDTH-1:0] pipeline_reg_2;
output [WIDTH-1:0] pipeline_reg_3;
output [WIDTH-1:0] pipeline_reg_4;
output [WIDTH-1:0] pipeline_reg_5;
output [WIDTH-1:0] pipeline_reg_6;
output [WIDTH-1:0] pipeline_reg_7;
output [WIDTH-1:0] pipeline_reg_8;
output [WIDTH-1:0] pipeline_reg_9;
output [WIDTH-1:0] pipeline_reg_10;
output [WIDTH-1:0] pipeline_reg_11;
output [WIDTH-1:0] pipeline_reg_12;
output [WIDTH-1:0] pipeline_reg_13;
output [WIDTH-1:0] pipeline_reg_14;
output [WIDTH-1:0] pipeline_reg_15;
output [WIDTH-1:0] pipeline_reg_16;
output [WIDTH-1:0] pipeline_reg_17;
output [WIDTH-1:0] pipeline_reg_18;
output [WIDTH-1:0] pipeline_reg_19;
output [WIDTH-1:0] pipeline_reg_20;
output [WIDTH-1:0] pipeline_reg_21;
output [WIDTH-1:0] pipeline_reg_22;
output [WIDTH-1:0] pipeline_reg_23;
output [WIDTH-1:0] pipeline_reg_24;
output [WIDTH-1:0] pipeline_reg_25;
output [WIDTH-1:0] pipeline_reg_26;
output [WIDTH-1:0] pipeline_reg_27;
output [WIDTH-1:0] pipeline_reg_28;
output [WIDTH-1:0] pipeline_reg_29;
output [WIDTH-1:0] pipeline_reg_30;
output [WIDTH-1:0] pipeline_reg_31;
output [WIDTH-1:0] pipeline_reg_32;
output [WIDTH-1:0] pipeline_reg_33;
output [WIDTH-1:0] pipeline_reg_34;
output [WIDTH-1:0] pipeline_reg_35;
output [WIDTH-1:0] pipeline_reg_36;
output [WIDTH-1:0] pipeline_reg_37;
reg [WIDTH-1:0] pipeline_reg_0;
reg [WIDTH-1:0] pipeline_reg_1;
reg [WIDTH-1:0] pipeline_reg_2;
reg [WIDTH-1:0] pipeline_reg_3;
reg [WIDTH-1:0] pipeline_reg_4;
reg [WIDTH-1:0] pipeline_reg_5;
reg [WIDTH-1:0] pipeline_reg_6;
reg [WIDTH-1:0] pipeline_reg_7;
reg [WIDTH-1:0] pipeline_reg_8;
reg [WIDTH-1:0] pipeline_reg_9;
reg [WIDTH-1:0] pipeline_reg_10;
reg [WIDTH-1:0] pipeline_reg_11;
reg [WIDTH-1:0] pipeline_reg_12;
reg [WIDTH-1:0] pipeline_reg_13;
reg [WIDTH-1:0] pipeline_reg_14;
reg [WIDTH-1:0] pipeline_reg_15;
reg [WIDTH-1:0] pipeline_reg_16;
reg [WIDTH-1:0] pipeline_reg_17;
reg [WIDTH-1:0] pipeline_reg_18;
reg [WIDTH-1:0] pipeline_reg_19;
reg [WIDTH-1:0] pipeline_reg_20;
reg [WIDTH-1:0] pipeline_reg_21;
reg [WIDTH-1:0] pipeline_reg_22;
reg [WIDTH-1:0] pipeline_reg_23;
reg [WIDTH-1:0] pipeline_reg_24;
reg [WIDTH-1:0] pipeline_reg_25;
reg [WIDTH-1:0] pipeline_reg_26;
reg [WIDTH-1:0] pipeline_reg_27;
reg [WIDTH-1:0] pipeline_reg_28;
reg [WIDTH-1:0] pipeline_reg_29;
reg [WIDTH-1:0] pipeline_reg_30;
reg [WIDTH-1:0] pipeline_reg_31;
reg [WIDTH-1:0] pipeline_reg_32;
reg [WIDTH-1:0] pipeline_reg_33;
reg [WIDTH-1:0] pipeline_reg_34;
reg [WIDTH-1:0] pipeline_reg_35;
reg [WIDTH-1:0] pipeline_reg_36;
reg [WIDTH-1:0] pipeline_reg_37;
input reset;
always@(posedge clk or posedge reset) begin
if(reset) begin
pipeline_reg_0 <= 0;
pipeline_reg_1 <= 0;
pipeline_reg_2 <= 0;
pipeline_reg_3 <= 0;
pipeline_reg_4 <= 0;
pipeline_reg_5 <= 0;
pipeline_reg_6 <= 0;
pipeline_reg_7 <= 0;
pipeline_reg_8 <= 0;
pipeline_reg_9 <= 0;
pipeline_reg_10 <= 0;
pipeline_reg_11 <= 0;
pipeline_reg_12 <= 0;
pipeline_reg_13 <= 0;
pipeline_reg_14 <= 0;
pipeline_reg_15 <= 0;
pipeline_reg_16 <= 0;
pipeline_reg_17 <= 0;
pipeline_reg_18 <= 0;
pipeline_reg_19 <= 0;
pipeline_reg_20 <= 0;
pipeline_reg_21 <= 0;
pipeline_reg_22 <= 0;
pipeline_reg_23 <= 0;
pipeline_reg_24 <= 0;
pipeline_reg_25 <= 0;
pipeline_reg_26 <= 0;
pipeline_reg_27 <= 0;
pipeline_reg_28 <= 0;
pipeline_reg_29 <= 0;
pipeline_reg_30 <= 0;
pipeline_reg_31 <= 0;
pipeline_reg_32 <= 0;
pipeline_reg_33 <= 0;
pipeline_reg_34 <= 0;
pipeline_reg_35 <= 0;
pipeline_reg_36 <= 0;
pipeline_reg_37 <= 0;
end else begin
if(clk_ena) begin
pipeline_reg_0 <= in_stream;
pipeline_reg_1 <= pipeline_reg_0;
pipeline_reg_2 <= pipeline_reg_1;
pipeline_reg_3 <= pipeline_reg_2;
pipeline_reg_4 <= pipeline_reg_3;
pipeline_reg_5 <= pipeline_reg_4;
pipeline_reg_6 <= pipeline_reg_5;
pipeline_reg_7 <= pipeline_reg_6;
pipeline_reg_8 <= pipeline_reg_7;
pipeline_reg_9 <= pipeline_reg_8;
pipeline_reg_10 <= pipeline_reg_9;
pipeline_reg_11 <= pipeline_reg_10;
pipeline_reg_12 <= pipeline_reg_11;
pipeline_reg_13 <= pipeline_reg_12;
pipeline_reg_14 <= pipeline_reg_13;
pipeline_reg_15 <= pipeline_reg_14;
pipeline_reg_16 <= pipeline_reg_15;
pipeline_reg_17 <= pipeline_reg_16;
pipeline_reg_18 <= pipeline_reg_17;
pipeline_reg_19 <= pipeline_reg_18;
pipeline_reg_20 <= pipeline_reg_19;
pipeline_reg_21 <= pipeline_reg_20;
pipeline_reg_22 <= pipeline_reg_21;
pipeline_reg_23 <= pipeline_reg_22;
pipeline_reg_24 <= pipeline_reg_23;
pipeline_reg_25 <= pipeline_reg_24;
pipeline_reg_26 <= pipeline_reg_25;
pipeline_reg_27 <= pipeline_reg_26;
pipeline_reg_28 <= pipeline_reg_27;
pipeline_reg_29 <= pipeline_reg_28;
pipeline_reg_30 <= pipeline_reg_29;
pipeline_reg_31 <= pipeline_reg_30;
pipeline_reg_32 <= pipeline_reg_31;
pipeline_reg_33 <= pipeline_reg_32;
pipeline_reg_34 <= pipeline_reg_33;
pipeline_reg_35 <= pipeline_reg_34;
pipeline_reg_36 <= pipeline_reg_35;
pipeline_reg_37 <= pipeline_reg_36;
end //else begin
//pipeline_reg_0 <= pipeline_reg_0;
//pipeline_reg_1 <= pipeline_reg_1;
//pipeline_reg_2 <= pipeline_reg_2;
//pipeline_reg_3 <= pipeline_reg_3;
//pipeline_reg_4 <= pipeline_reg_4;
//pipeline_reg_5 <= pipeline_reg_5;
//pipeline_reg_6 <= pipeline_reg_6;
//pipeline_reg_7 <= pipeline_reg_7;
//pipeline_reg_8 <= pipeline_reg_8;
//pipeline_reg_9 <= pipeline_reg_9;
//pipeline_reg_10 <= pipeline_reg_10;
//pipeline_reg_11 <= pipeline_reg_11;
//pipeline_reg_12 <= pipeline_reg_12;
//pipeline_reg_13 <= pipeline_reg_13;
//pipeline_reg_14 <= pipeline_reg_14;
//pipeline_reg_15 <= pipeline_reg_15;
//pipeline_reg_16 <= pipeline_reg_16;
//pipeline_reg_17 <= pipeline_reg_17;
//pipeline_reg_18 <= pipeline_reg_18;
//pipeline_reg_19 <= pipeline_reg_19;
//pipeline_reg_20 <= pipeline_reg_20;
//pipeline_reg_21 <= pipeline_reg_21;
//pipeline_reg_22 <= pipeline_reg_22;
//pipeline_reg_23 <= pipeline_reg_23;
//pipeline_reg_24 <= pipeline_reg_24;
//pipeline_reg_25 <= pipeline_reg_25;
//pipeline_reg_26 <= pipeline_reg_26;
//pipeline_reg_27 <= pipeline_reg_27;
//pipeline_reg_28 <= pipeline_reg_28;
//pipeline_reg_29 <= pipeline_reg_29;
//pipeline_reg_30 <= pipeline_reg_30;
//pipeline_reg_31 <= pipeline_reg_31;
//pipeline_reg_32 <= pipeline_reg_32;
//pipeline_reg_33 <= pipeline_reg_33;
//pipeline_reg_34 <= pipeline_reg_34;
//pipeline_reg_35 <= pipeline_reg_35;
//pipeline_reg_36 <= pipeline_reg_36;
//pipeline_reg_37 <= pipeline_reg_37;
//end
end
end
endmodule
module adder_with_1_reg (
dataa,
datab,
result);
input clk;
input clk_ena;
input [17:0] dataa;
input [17:0] datab;
output [17:0] result;
assign result = dataa + datab;
endmodule
module multiplier_with_reg (
dataa,
datab,
result);
input clk;
input clk_ena;
input [17:0] dataa;
input [17:0] datab;
output [17:0] result;
assign result = dataa * datab;
endmodule
module one_register (
dataa,
result);
input clk;
input clk_ena;
input [17:0] dataa;
output [17:0] result;
assign result = dataa;
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_gen_clock.v
*
* Date : 2012-11
*
* Description : Module that generates FCLK clocks and internal clock for Zynq BFM.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_gen_clock(
ps_clk,
sw_clk,
fclk_clk3,
fclk_clk2,
fclk_clk1,
fclk_clk0
);
input ps_clk;
output sw_clk;
output fclk_clk3;
output fclk_clk2;
output fclk_clk1;
output fclk_clk0;
parameter freq_clk3 = 50;
parameter freq_clk2 = 50;
parameter freq_clk1 = 50;
parameter freq_clk0 = 50;
reg clk0 = 1'b0;
reg clk1 = 1'b0;
reg clk2 = 1'b0;
reg clk3 = 1'b0;
reg sw_clk = 1'b0;
assign fclk_clk0 = clk0;
assign fclk_clk1 = clk1;
assign fclk_clk2 = clk2;
assign fclk_clk3 = clk3;
real clk3_p = (1000.00/freq_clk3)/2;
real clk2_p = (1000.00/freq_clk2)/2;
real clk1_p = (1000.00/freq_clk1)/2;
real clk0_p = (1000.00/freq_clk0)/2;
always #(clk3_p) clk3 = !clk3;
always #(clk2_p) clk2 = !clk2;
always #(clk1_p) clk1 = !clk1;
always #(clk0_p) clk0 = !clk0;
always #(0.5) sw_clk = !sw_clk;
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_4kx16_dc.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_4kx16_dc (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
wire sub_wire0;
wire [11:0] sub_wire1;
wire sub_wire2;
wire [15:0] sub_wire3;
wire [11:0] sub_wire4;
wire rdempty = sub_wire0;
wire [11:0] wrusedw = sub_wire1[11:0];
wire wrfull = sub_wire2;
wire [15:0] q = sub_wire3[15:0];
wire [11:0] rdusedw = sub_wire4[11:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.q (sub_wire3),
.rdusedw (sub_wire4)
// synopsys translate_off
,
.wrempty (),
.rdfull ()
// synopsys translate_on
);
defparam
dcfifo_component.add_ram_output_register = "OFF",
dcfifo_component.clocks_are_synchronized = "FALSE",
dcfifo_component.intended_device_family = "Cyclone",
dcfifo_component.lpm_numwords = 4096,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 16,
dcfifo_component.lpm_widthu = 12,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <[email protected]>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_response_generator (
input clk,
input resetn,
input enable,
output reg enabled,
input [C_ID_WIDTH-1:0] request_id,
output reg [C_ID_WIDTH-1:0] response_id,
input sync_id,
input eot,
output resp_valid,
input resp_ready,
output resp_eot,
output [1:0] resp_resp
);
parameter C_ID_WIDTH = 3;
`include "inc_id.v"
`include "resp.v"
assign resp_resp = RESP_OKAY;
assign resp_eot = eot;
assign resp_valid = request_id != response_id;
// We have to wait for all responses before we can disable the response handler
always @(posedge clk) begin
if (resetn == 1'b0) begin
enabled <= 1'b0;
end else begin
if (enable)
enabled <= 1'b1;
else if (request_id == response_id)
enabled <= 1'b0;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
response_id <= 'h0;
end else begin
if ((resp_valid && resp_ready) ||
(sync_id && response_id != request_id))
response_id <= inc_id(response_id);
end
end
endmodule
|
/*****************************************************************************
* *
* Module: Altera_UP_Avalon_RS232 *
* Description: *
* This module reads and writes data to the RS232 connector on Altera's *
* DE1 and DE2 Development and Education Boards. *
* *
*****************************************************************************/
/* Settings */
`define USE_DATA_WIDTH_8 1
/* End settings */
module Altera_UP_Avalon_RS232 (
// Inputs
clk,
reset,
address,
chipselect,
byteenable,
read,
write,
writedata,
UART_RXD,
// Bidirectionals
// Outputs
irq,
readdata,
UART_TXD
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter BAUD_COUNTER_WIDTH = 9;
parameter BAUD_TICK_INCREMENT = 9'd1;
parameter BAUD_TICK_COUNT = 9'd433;
parameter HALF_BAUD_TICK_COUNT = 9'd216;
parameter TOTAL_DATA_WIDTH = 10;
parameter DATA_WIDTH = 8;
parameter ODD_PARITY = 1'b0;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input address;
input chipselect;
input [3:0] byteenable;
input read;
input write;
input [31:0] writedata;
input UART_RXD;
// Bidirectionals
// Outputs
output reg irq;
output reg [31:0] readdata;
output UART_TXD;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_fifo_read_en;
wire [7:0] read_available;
`ifdef USE_PARITY
wire [DATA_WIDTH:0] read_data;
`else
wire [(DATA_WIDTH - 1):0] read_data;
`endif
wire parity_error;
wire write_data_parity;
wire [7:0] write_space;
// Internal Registers
reg read_interrupt_en;
reg write_interrupt_en;
reg read_interrupt;
reg write_interrupt;
reg write_fifo_write_en;
reg [(DATA_WIDTH - 1):0] data_to_uart;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
irq <= 1'b0;
else
irq <= write_interrupt | read_interrupt;
end
always @(posedge clk)
begin
if (reset == 1'b1)
readdata <= 32'h00000000;
else if (chipselect == 1'b1)
begin
if (address == 1'b0)
readdata <=
{8'h00,
read_available,
6'h00,
parity_error,
`ifdef USE_DATA_WIDTH_7
2'h0,
`endif
`ifdef USE_DATA_WIDTH_8
1'b0,
`endif
read_data[(DATA_WIDTH - 1):0]};
else
readdata <=
{8'h00,
write_space,
6'h00,
write_interrupt,
read_interrupt,
6'h00,
write_interrupt_en,
read_interrupt_en};
end
end
always @(posedge clk)
begin
if (reset == 1'b1)
read_interrupt_en <= 1'b0;
else if ((chipselect == 1'b1) && (write == 1'b1) && (address == 1'b1) && (byteenable[0] == 1'b1))
read_interrupt_en <= writedata[0];
end
always @(posedge clk)
begin
if (reset == 1'b1)
write_interrupt_en <= 1'b0;
else if ((chipselect == 1'b1) && (write == 1'b1) && (address == 1'b1) && (byteenable[0] == 1'b1))
write_interrupt_en <= writedata[1];
end
always @(posedge clk)
begin
if (reset == 1'b1)
read_interrupt <= 1'b0;
else if (read_interrupt_en == 1'b0)
read_interrupt <= 1'b0;
else
read_interrupt <= (|read_available);
end
always @(posedge clk)
begin
if (reset == 1'b1)
write_interrupt <= 1'b0;
else if (write_interrupt_en == 1'b0)
write_interrupt <= 1'b0;
else
write_interrupt <= (&(write_space[6:5]) | write_space[7]);
end
always @(posedge clk)
begin
if (reset == 1'b1)
write_fifo_write_en <= 1'b0;
else
write_fifo_write_en <=
chipselect & write & ~address & byteenable[0];
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_to_uart <= 1'b0;
else
data_to_uart <= writedata[(DATA_WIDTH - 1):0];
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
`ifdef USE_PARITY
assign parity_error = (read_available != 8'h00) ?
((^(read_data[DATA_WIDTH:0])) ^ ODD_PARITY) :
1'b0;
`else
assign parity_error = 1'b0;
`endif
assign read_fifo_read_en = chipselect & read & ~address & byteenable[0];
assign write_data_parity = (^(data_to_uart)) ^ ODD_PARITY;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Altera_UP_RS232_In_Deserializer RS232_In_Deserializer (
// Inputs
.clk (clk),
.reset (reset),
.serial_data_in (UART_RXD),
.receive_data_en (read_fifo_read_en),
// Bidirectionals
// Outputs
.fifo_read_available (read_available),
.received_data (read_data)
);
defparam
RS232_In_Deserializer.BAUD_COUNTER_WIDTH = BAUD_COUNTER_WIDTH,
RS232_In_Deserializer.BAUD_TICK_INCREMENT = BAUD_TICK_INCREMENT,
RS232_In_Deserializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_In_Deserializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_In_Deserializer.TOTAL_DATA_WIDTH = TOTAL_DATA_WIDTH,
`ifdef USE_PARITY
RS232_In_Deserializer.DATA_WIDTH = (DATA_WIDTH + 1);
`else
RS232_In_Deserializer.DATA_WIDTH = DATA_WIDTH;
`endif
Altera_UP_RS232_Out_Serializer RS232_Out_Serializer (
// Inputs
.clk (clk),
.reset (reset),
`ifdef USE_PARITY
.transmit_data ({write_data_parity, data_to_uart}),
`else
.transmit_data (data_to_uart),
`endif
.transmit_data_en (write_fifo_write_en),
// Bidirectionals
// Outputs
.fifo_write_space (write_space),
.serial_data_out (UART_TXD)
);
defparam
RS232_Out_Serializer.BAUD_COUNTER_WIDTH = BAUD_COUNTER_WIDTH,
RS232_Out_Serializer.BAUD_TICK_INCREMENT = BAUD_TICK_INCREMENT,
RS232_Out_Serializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_Out_Serializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_Out_Serializer.TOTAL_DATA_WIDTH = TOTAL_DATA_WIDTH,
`ifdef USE_PARITY
RS232_Out_Serializer.DATA_WIDTH = (DATA_WIDTH + 1);
`else
RS232_Out_Serializer.DATA_WIDTH = DATA_WIDTH;
`endif
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 13
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zqynq_lab_1_design_auto_pc_2 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_13_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(12'H000),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
//
module some_module (
input wrclk
);
logic [ 1 : 0 ] some_state;
logic [1:0] some_other_state;
always @(posedge wrclk) begin
case (some_state)
2'b11:
if (some_other_state == 0)
some_state <= 2'b00;
default:
$display ("This is a display statement");
endcase
if (wrclk)
some_other_state <= 0;
end
endmodule
`define BROKEN
module t1(
input [3:0] i_clks,
input i_clk0,
input i_clk1
);
generate
genvar i;
for (i = 0; i < 2; i = i + 1) begin: a_generate_block
some_module
some_module
(
`ifdef BROKEN
.wrclk (i_clks[3])
`else
.wrclk (i_clk1)
`endif
);
end
endgenerate
endmodule
module t2(
input [2:0] i_clks,
input i_clk0,
input i_clk1,
input i_clk2,
input i_data
);
logic [3:0] the_clks;
logic data_q;
assign the_clks[3] = i_clk1;
assign the_clks[2] = i_clk2;
assign the_clks[1] = i_clk1;
assign the_clks[0] = i_clk0;
always @(posedge i_clk0) begin
data_q <= i_data;
end
t1 t1
(
.i_clks (the_clks),
.i_clk0 (i_clk0),
.i_clk1 (i_clk1)
);
endmodule
module t(
input clk0 /*verilator clocker*/,
input clk1 /*verilator clocker*/,
input clk2 /*verilator clocker*/,
input data_in
);
logic [2:0] clks;
assign clks = {1'b0, clk1, clk0};
t2
t2
(
.i_clks (clks),
.i_clk0 (clk0),
.i_clk1 (clk1),
.i_clk2 (clk2),
.i_data (data_in)
);
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
module test();
reg a, b;
wire a1, a2, a3, a4, a5, a6, a7;
assign (supply1, supply0) a1 = a;
rtran t1(a1, a2);
rtran t2(a2, a3);
rtran t3(a3, a4);
rtran t4(a4, a5);
rtran t5(a5, a6);
rtran t6(a6, a7);
wire a11, a12, a13, a14, a15, b11, b12, b13, b14, b15;
wire a21, a22, a23, a24, a25, b21, b22, b23, b24, b25;
wire a31, a32, a33, a34, a35, b31, b32, b33, b34, b35;
wire a41, a42, a43, a44, a45, b41, b42, b43, b44, b45;
wire a51, a52, a53, a54, a55, b51, b52, b53, b54, b55;
assign (supply1, supply0) a11 = a, b11 = b;
assign (supply1, strong0) a12 = a, b12 = b;
assign (supply1, pull0) a13 = a, b13 = b;
assign (supply1, weak0) a14 = a, b14 = b;
assign (supply1, highz0) a15 = a, b15 = b;
assign (strong1, supply0) a21 = a, b21 = b;
assign (strong1, strong0) a22 = a, b22 = b;
assign (strong1, pull0) a23 = a, b23 = b;
assign (strong1, weak0) a24 = a, b24 = b;
assign (strong1, highz0) a25 = a, b25 = b;
assign ( pull1, supply0) a31 = a, b31 = b;
assign ( pull1, strong0) a32 = a, b32 = b;
assign ( pull1, pull0) a33 = a, b33 = b;
assign ( pull1, weak0) a34 = a, b34 = b;
assign ( pull1, highz0) a35 = a, b35 = b;
assign ( weak1, supply0) a41 = a, b41 = b;
assign ( weak1, strong0) a42 = a, b42 = b;
assign ( weak1, pull0) a43 = a, b43 = b;
assign ( weak1, weak0) a44 = a, b44 = b;
assign ( weak1, highz0) a45 = a, b45 = b;
assign ( highz1, supply0) a51 = a, b51 = b;
assign ( highz1, strong0) a52 = a, b52 = b;
assign ( highz1, pull0) a53 = a, b53 = b;
assign ( highz1, weak0) a54 = a, b54 = b;
rtran t11(a11, b11);
rtran t12(a12, b12);
rtran t13(a13, b13);
rtran t14(a14, b14);
rtran t15(a15, b15);
rtran t21(a21, b21);
rtran t22(a22, b22);
rtran t23(a23, b23);
rtran t24(a24, b24);
rtran t25(a25, b25);
rtran t31(a31, b31);
rtran t32(a32, b32);
rtran t33(a33, b33);
rtran t34(a34, b34);
rtran t35(a35, b35);
rtran t41(a41, b41);
rtran t42(a42, b42);
rtran t43(a43, b43);
rtran t44(a44, b44);
rtran t45(a45, b45);
rtran t51(a51, b51);
rtran t52(a52, b52);
rtran t53(a53, b53);
rtran t54(a54, b54);
rtran t55(a55, b55);
task display_strengths;
input ta, tb;
begin
a = ta;
b = tb;
#1;
$display("a = %b b = %b", a, b);
$display("a1(%v) a2(%v) a3(%v) a4(%v) a5(%v) a6(%v) a7(%v)", a1, a2, a3, a4, a5, a6, a7);
$display("t11(%v %v) t12(%v %v) t13(%v %v) t14(%v %v) t15(%v %v)", a11, b11, a12, b12, a13, b13, a14, b14, a15, b15);
$display("t21(%v %v) t22(%v %v) t23(%v %v) t24(%v %v) t25(%v %v)", a21, b21, a22, b22, a23, b23, a24, b24, a25, b25);
$display("t31(%v %v) t32(%v %v) t33(%v %v) t34(%v %v) t35(%v %v)", a31, b31, a32, b32, a33, b33, a34, b34, a35, b35);
$display("t41(%v %v) t42(%v %v) t43(%v %v) t44(%v %v) t45(%v %v)", a41, b41, a42, b42, a43, b43, a44, b44, a45, b45);
$display("t51(%v %v) t52(%v %v) t53(%v %v) t54(%v %v) t55(%v %v)", a51, b51, a52, b52, a53, b53, a54, b54, a55, b55);
end
endtask
initial begin
display_strengths(1'bz, 1'bz);
display_strengths(1'bx, 1'bz);
display_strengths(1'b0, 1'bz);
display_strengths(1'b1, 1'bz);
display_strengths(1'bz, 1'bx);
display_strengths(1'bx, 1'bx);
display_strengths(1'b0, 1'bx);
display_strengths(1'b1, 1'bx);
display_strengths(1'bz, 1'b0);
display_strengths(1'bx, 1'b0);
display_strengths(1'b0, 1'b0);
display_strengths(1'b1, 1'b0);
display_strengths(1'bz, 1'b1);
display_strengths(1'bx, 1'b1);
display_strengths(1'b0, 1'b1);
display_strengths(1'b1, 1'b1);
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Register Slice
// Generic single-channel AXI pipeline register on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axic_register_slice
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_register_slice_v2_1_11_srl_rtl #
(
parameter C_A_WIDTH = 2 // Address Width (>= 1)
)
(
input wire clk, // Clock
input wire [C_A_WIDTH-1:0] a, // Address
input wire ce, // Clock Enable
input wire d, // Input Data
output wire q // Output Data
);
localparam integer P_SRLDEPTH = 2**C_A_WIDTH;
reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};
always @(posedge clk)
if (ce)
shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};
assign q = shift_reg[a];
endmodule
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_register_slice_v2_1_11_axic_register_slice #
(
parameter C_FAMILY = "virtex6",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
// C_REG_CONFIG:
// 0 => BYPASS = The channel is just wired through the module.
// 1 => FWD_REV = Both FWD and REV (fully-registered)
// 2 => FWD = The master VALID and payload signals are registrated.
// 3 => REV = The slave ready signal is registrated
// 4 => RESERVED (all outputs driven to 0).
// 5 => RESERVED (all outputs driven to 0).
// 6 => INPUTS = Slave and Master side inputs are registrated.
// 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// 9 => SI/MI_REG = Source side completely registered (including S_VALID input)
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
(* use_clock_enable = "yes" *)
generate
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 0
// Bypass mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000) begin
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 9
// Source (SI) interface completely registered
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000009) begin
reg [C_DATA_WIDTH-1:0] s_payload_d;
wire [C_DATA_WIDTH-1:0] srl_out;
reg s_ready_i;
reg m_valid_i;
reg payld_sel;
reg push;
reg pop;
wire s_handshake_d;
(* max_fanout = 66 *) reg s_valid_d;
(* max_fanout = 66 *) reg s_ready_d = 1'b0;
(* max_fanout = 66 *) reg s_ready_reg = 1'b0;
(* max_fanout = 66 *) reg [2:0] fifoaddr = 3'b110;
reg areset_d = 1'b0;
always @(posedge ACLK) begin
areset_d <= ARESET;
end
assign s_handshake_d = s_valid_d & s_ready_d;
always @ * begin
case (fifoaddr)
3'b111: begin // EMPTY: No payload in SRL; pre-assert m_ready
s_ready_i = 1'b1;
payld_sel = 1'b0;
pop = 1'b0;
case ({s_handshake_d, M_READY})
2'b00, 2'b01: begin // Idle
m_valid_i = 1'b0;
push = 1'b0;
end
2'b10: begin // Payload received
m_valid_i = 1'b1;
push = 1'b1;
end
2'b11: begin // Payload received and read out combinatorially
m_valid_i = 1'b1;
push = 1'b0;
end
endcase
end
3'b000: begin // 1 payload item in SRL
m_valid_i = 1'b1;
payld_sel = 1'b1;
case ({s_handshake_d, M_READY})
2'b00: begin // Idle
s_ready_i = 1'b1;
push = 1'b0;
pop = 1'b0;
end
2'b01: begin // Pop
s_ready_i = 1'b1;
push = 1'b0;
pop = 1'b1;
end
2'b10: begin // Push
s_ready_i = 1'b0; // Doesn't de-assert on SI until next cycle
push = 1'b1;
pop = 1'b0;
end
2'b11: begin // Push and Pop
s_ready_i = 1'b1;
push = 1'b1;
pop = 1'b1;
end
endcase
end
3'b001: begin // 2 payload items in SRL
m_valid_i = 1'b1;
payld_sel = 1'b1;
case ({s_handshake_d, M_READY})
2'b00: begin // Idle
s_ready_i = 1'b0;
push = 1'b0;
pop = 1'b0;
end
2'b01: begin // Pop
s_ready_i = 1'b1;
push = 1'b0;
pop = 1'b1;
end
2'b10: begin // Push (Handshake completes on SI while pushing 2nd item into SRL)
s_ready_i = 1'b0;
push = 1'b1;
pop = 1'b0;
end
2'b11: begin // Push and Pop
s_ready_i = 1'b0;
push = 1'b1;
pop = 1'b1;
end
endcase
end
3'b010: begin // 3 payload items in SRL
m_valid_i = 1'b1;
s_ready_i = 1'b0;
payld_sel = 1'b1;
push = 1'b0;
if (M_READY) begin // Handshake cannot complete on SI
pop = 1'b1;
end else begin
pop = 1'b0;
end
end
default: begin // RESET state (fifoaddr = 3'b110)
m_valid_i = 1'b0;
s_ready_i = 1'b0;
payld_sel = 1'b0;
push = 1'b1; // Advance to Empty state
pop = 1'b0;
end // RESET
endcase
end
always @(posedge ACLK) begin
if (areset_d) begin
fifoaddr <= 3'b110;
s_ready_reg <= 1'b0;
s_ready_d <= 1'b0;
end else begin
s_ready_reg <= s_ready_i;
s_ready_d <= s_ready_reg;
if (push & ~pop) begin
fifoaddr <= fifoaddr + 1;
end else if (~push & pop) begin
fifoaddr <= fifoaddr - 1;
end
end
end
always @(posedge ACLK) begin
s_valid_d <= S_VALID;
s_payload_d <= S_PAYLOAD_DATA;
end
assign S_READY = s_ready_reg;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
genvar i;
for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls
axi_register_slice_v2_1_11_srl_rtl #
(
.C_A_WIDTH (2)
)
srl_nx1
(
.clk (ACLK),
.a (fifoaddr[1:0]),
.ce (push),
.d (s_payload_d[i]),
.q (srl_out[i])
);
end
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 1 (or 8)
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg [C_DATA_WIDTH-1:0] skid_buffer;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1'b0;
end else begin
s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);
end
if (~aresetn_d[1]) begin
m_valid_i <= 1'b0;
end else begin
m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);
end
if (M_READY | ~m_valid_i) begin
m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;
end
if (s_ready_i) begin
skid_buffer <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 2
// Only FWD mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000002)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
wire s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg aresetn_d = 1'b0; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 1'b0;
end else begin
aresetn_d <= ~ARESET;
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data;
// M_Valid set to high when we have a completed transfer on slave side
// Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK)
begin
if (~aresetn_d)
m_valid_i <= 1'b0;
else
if (S_VALID) // Always set m_valid_i when slave side is valid
m_valid_i <= 1'b1;
else
if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready
m_valid_i <= 1'b0;
end // always @ (posedge ACLK)
// Slave Ready is either when Master side drives M_Ready or we have space in our storage data
assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;
end // if (C_REG_CONFIG == 2)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 3
// Only REV mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000003)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
reg s_ready_i; //local signal of output
reg has_valid_storage_i;
reg has_valid_storage;
reg [1:0] aresetn_d = 2'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;
// Need to determine when we need to save a payload
// Need a combinatorial signals since it will also effect S_READY
always @ *
begin
// Set the value if we have a slave transaction but master side is not ready
if (S_VALID & s_ready_i & ~M_READY)
has_valid_storage_i = 1'b1;
// Clear the value if it's set and Master side completes the transaction but we don't have a new slave side
// transaction
else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))
has_valid_storage_i = 1'b0;
else
has_valid_storage_i = has_valid_storage;
end // always @ *
always @(posedge ACLK)
begin
if (~aresetn_d[0])
has_valid_storage <= 1'b0;
else
has_valid_storage <= has_valid_storage_i;
end
// S_READY is either clocked M_READY or that we have room in local storage
always @(posedge ACLK)
begin
if (~aresetn_d[0])
s_ready_i <= 1'b0;
else
s_ready_i <= M_READY | ~has_valid_storage_i;
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
// M_READY is either combinatorial S_READY or that we have valid data in local storage
assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];
end // if (C_REG_CONFIG == 3)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))
begin
// synthesis translate_off
initial begin
$display ("ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.");
end
// synthesis translate_on
assign M_PAYLOAD_DATA = 0;
assign M_VALID = 1'b0;
assign S_READY = 1'b0;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 6
// INPUTS mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000006)
begin
reg [1:0] state;
reg [1:0] next_state;
localparam [1:0]
ZERO = 2'b00,
ONE = 2'b01,
TWO = 2'b11;
reg [C_DATA_WIDTH-1:0] storage_data1;
reg [C_DATA_WIDTH-1:0] storage_data2;
reg s_valid_d;
reg s_ready_d;
reg m_ready_d;
reg m_valid_d;
reg load_s2;
reg sel_s2;
wire new_access;
wire access_done;
wire s_ready_i; //local signal of output
reg s_ready_ii;
reg m_valid_i; //local signal of output
reg [1:0] aresetn_d = 2'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign s_ready_i = s_ready_ii & aresetn_d[1];
// Registrate input control signals
always @(posedge ACLK)
begin
if (~aresetn_d[0]) begin
s_valid_d <= 1'b0;
s_ready_d <= 1'b0;
m_ready_d <= 1'b0;
end else begin
s_valid_d <= S_VALID;
s_ready_d <= s_ready_i;
m_ready_d <= M_READY;
end
end // always @ (posedge ACLK)
// Load storage1 with slave side payload data when slave side ready is high
always @(posedge ACLK)
begin
if (s_ready_i)
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with storage data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= storage_data1;
end
always @(posedge ACLK)
begin
if (~aresetn_d[0])
m_valid_d <= 1'b0;
else
m_valid_d <= m_valid_i;
end
// Local help signals
assign new_access = s_ready_d & s_valid_d;
assign access_done = m_ready_d & m_valid_d;
// State Machine for handling output signals
always @*
begin
next_state = state; // Stay in the same state unless we need to move to another state
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 0;
case (state)
// No transaction stored locally
ZERO: begin
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 1;
if (new_access) begin
next_state = ONE; // Got one so move to ONE
load_s2 = 1;
m_valid_i = 0;
end
else begin
next_state = next_state;
load_s2 = load_s2;
m_valid_i = m_valid_i;
end
end // case: ZERO
// One transaction stored locally
ONE: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 1;
if (~new_access & access_done) begin
next_state = ZERO; // Read out one so move to ZERO
m_valid_i = 0;
end
else if (new_access & ~access_done) begin
next_state = TWO; // Got another one so move to TWO
s_ready_ii = 0;
end
else if (new_access & access_done) begin
load_s2 = 1;
sel_s2 = 0;
end
else begin
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: ONE
// TWO transaction stored locally
TWO: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 0;
if (access_done) begin
next_state = ONE; // Read out one so move to ONE
s_ready_ii = 1;
load_s2 = 1;
sel_s2 = 0;
end
else begin
next_state = next_state;
s_ready_ii = s_ready_ii;
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: TWO
endcase // case (state)
end // always @ *
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (~aresetn_d[0])
state <= ZERO;
else
state <= next_state; // Stay in the same state unless we need to move to another state
end
// Master Payload mux
assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;
end // if (C_REG_CONFIG == 6)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 7
// Light-weight mode.
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000007) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1'b0;
end else if (~aresetn_d[1]) begin
s_ready_i <= 1'b1;
end else begin
s_ready_i <= m_valid_i ? M_READY : ~S_VALID;
end
if (~aresetn_d[1]) begin
m_valid_i <= 1'b0;
end else begin
m_valid_i <= s_ready_i ? S_VALID : ~M_READY;
end
if (~m_valid_i) begin
m_payload_i <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule // reg_slice
// (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// AXI Register Slice
// Register selected channels on the forward and/or reverse signal paths.
// 5-channel memory-mapped AXI4 interfaces.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axi_register_slice
// axic_register_slice
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_register_slice_v2_1_11_axi_register_slice #
(
parameter C_FAMILY = "virtex6",
parameter C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
// C_REG_CONFIG_*:
// 0 => BYPASS = The channel is just wired through the module.
// 1 => FWD_REV = Both FWD and REV (fully-registered)
// 2 => FWD = The master VALID and payload signals are registrated.
// 3 => REV = The slave ready signal is registrated
// 4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.
// 5 => SLAVE_RDY = All slave side signals and master READY are registrated.
// 6 => INPUTS = Slave and Master side inputs are registrated.
// 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// 9 => SI/MI_REG = Source side completely registered (including S_VALID input)
parameter integer C_REG_CONFIG_AW = 7,
parameter integer C_REG_CONFIG_W = 1,
parameter integer C_REG_CONFIG_B = 7,
parameter integer C_REG_CONFIG_AR = 7,
parameter integer C_REG_CONFIG_R = 1
)
(
// System Signals
input wire aclk,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire m_axi_rvalid,
output wire m_axi_rready
);
wire reset;
localparam C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;
`include "axi_infrastructure_v1_1_0.vh"
wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;
wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;
wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;
wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;
wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;
wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;
wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;
wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;
wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;
wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;
assign reset = ~aresetn;
axi_infrastructure_v1_1_0_axi2vector #(
.C_AXI_PROTOCOL ( C_AXI_PROTOCOL ) ,
.C_AXI_ID_WIDTH ( C_AXI_ID_WIDTH ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( C_AXI_SUPPORTS_USER_SIGNALS ) ,
.C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,
.C_AXI_AWUSER_WIDTH ( C_AXI_AWUSER_WIDTH ) ,
.C_AXI_ARUSER_WIDTH ( C_AXI_ARUSER_WIDTH ) ,
.C_AXI_WUSER_WIDTH ( C_AXI_WUSER_WIDTH ) ,
.C_AXI_RUSER_WIDTH ( C_AXI_RUSER_WIDTH ) ,
.C_AXI_BUSER_WIDTH ( C_AXI_BUSER_WIDTH ) ,
.C_AWPAYLOAD_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,
.C_WPAYLOAD_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,
.C_BPAYLOAD_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,
.C_ARPAYLOAD_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,
.C_RPAYLOAD_WIDTH ( G_AXI_RPAYLOAD_WIDTH )
)
axi_infrastructure_v1_1_0_axi2vector_0 (
.s_axi_awid ( s_axi_awid ) ,
.s_axi_awaddr ( s_axi_awaddr ) ,
.s_axi_awlen ( s_axi_awlen ) ,
.s_axi_awsize ( s_axi_awsize ) ,
.s_axi_awburst ( s_axi_awburst ) ,
.s_axi_awlock ( s_axi_awlock ) ,
.s_axi_awcache ( s_axi_awcache ) ,
.s_axi_awprot ( s_axi_awprot ) ,
.s_axi_awqos ( s_axi_awqos ) ,
.s_axi_awuser ( s_axi_awuser ) ,
.s_axi_awregion ( s_axi_awregion ) ,
.s_axi_wid ( s_axi_wid ) ,
.s_axi_wdata ( s_axi_wdata ) ,
.s_axi_wstrb ( s_axi_wstrb ) ,
.s_axi_wlast ( s_axi_wlast ) ,
.s_axi_wuser ( s_axi_wuser ) ,
.s_axi_bid ( s_axi_bid ) ,
.s_axi_bresp ( s_axi_bresp ) ,
.s_axi_buser ( s_axi_buser ) ,
.s_axi_arid ( s_axi_arid ) ,
.s_axi_araddr ( s_axi_araddr ) ,
.s_axi_arlen ( s_axi_arlen ) ,
.s_axi_arsize ( s_axi_arsize ) ,
.s_axi_arburst ( s_axi_arburst ) ,
.s_axi_arlock ( s_axi_arlock ) ,
.s_axi_arcache ( s_axi_arcache ) ,
.s_axi_arprot ( s_axi_arprot ) ,
.s_axi_arqos ( s_axi_arqos ) ,
.s_axi_aruser ( s_axi_aruser ) ,
.s_axi_arregion ( s_axi_arregion ) ,
.s_axi_rid ( s_axi_rid ) ,
.s_axi_rdata ( s_axi_rdata ) ,
.s_axi_rresp ( s_axi_rresp ) ,
.s_axi_rlast ( s_axi_rlast ) ,
.s_axi_ruser ( s_axi_ruser ) ,
.s_awpayload ( s_awpayload ) ,
.s_wpayload ( s_wpayload ) ,
.s_bpayload ( s_bpayload ) ,
.s_arpayload ( s_arpayload ) ,
.s_rpayload ( s_rpayload )
);
axi_register_slice_v2_1_11_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_AW )
)
aw_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(s_awpayload),
.S_VALID(s_axi_awvalid),
.S_READY(s_axi_awready),
// Master side
.M_PAYLOAD_DATA(m_awpayload),
.M_VALID(m_axi_awvalid),
.M_READY(m_axi_awready)
);
axi_register_slice_v2_1_11_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_W )
)
w_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(s_wpayload),
.S_VALID(s_axi_wvalid),
.S_READY(s_axi_wready),
// Master side
.M_PAYLOAD_DATA(m_wpayload),
.M_VALID(m_axi_wvalid),
.M_READY(m_axi_wready)
);
axi_register_slice_v2_1_11_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_B )
)
b_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(m_bpayload),
.S_VALID(m_axi_bvalid),
.S_READY(m_axi_bready),
// Master side
.M_PAYLOAD_DATA(s_bpayload),
.M_VALID(s_axi_bvalid),
.M_READY(s_axi_bready)
);
axi_register_slice_v2_1_11_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_AR )
)
ar_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(s_arpayload),
.S_VALID(s_axi_arvalid),
.S_READY(s_axi_arready),
// Master side
.M_PAYLOAD_DATA(m_arpayload),
.M_VALID(m_axi_arvalid),
.M_READY(m_axi_arready)
);
axi_register_slice_v2_1_11_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_R )
)
r_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(m_rpayload),
.S_VALID(m_axi_rvalid),
.S_READY(m_axi_rready),
// Master side
.M_PAYLOAD_DATA(s_rpayload),
.M_VALID(s_axi_rvalid),
.M_READY(s_axi_rready)
);
axi_infrastructure_v1_1_0_vector2axi #(
.C_AXI_PROTOCOL ( C_AXI_PROTOCOL ) ,
.C_AXI_ID_WIDTH ( C_AXI_ID_WIDTH ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( C_AXI_SUPPORTS_USER_SIGNALS ) ,
.C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,
.C_AXI_AWUSER_WIDTH ( C_AXI_AWUSER_WIDTH ) ,
.C_AXI_ARUSER_WIDTH ( C_AXI_ARUSER_WIDTH ) ,
.C_AXI_WUSER_WIDTH ( C_AXI_WUSER_WIDTH ) ,
.C_AXI_RUSER_WIDTH ( C_AXI_RUSER_WIDTH ) ,
.C_AXI_BUSER_WIDTH ( C_AXI_BUSER_WIDTH ) ,
.C_AWPAYLOAD_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,
.C_WPAYLOAD_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,
.C_BPAYLOAD_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,
.C_ARPAYLOAD_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,
.C_RPAYLOAD_WIDTH ( G_AXI_RPAYLOAD_WIDTH )
)
axi_infrastructure_v1_1_0_vector2axi_0 (
.m_awpayload ( m_awpayload ) ,
.m_wpayload ( m_wpayload ) ,
.m_bpayload ( m_bpayload ) ,
.m_arpayload ( m_arpayload ) ,
.m_rpayload ( m_rpayload ) ,
.m_axi_awid ( m_axi_awid ) ,
.m_axi_awaddr ( m_axi_awaddr ) ,
.m_axi_awlen ( m_axi_awlen ) ,
.m_axi_awsize ( m_axi_awsize ) ,
.m_axi_awburst ( m_axi_awburst ) ,
.m_axi_awlock ( m_axi_awlock ) ,
.m_axi_awcache ( m_axi_awcache ) ,
.m_axi_awprot ( m_axi_awprot ) ,
.m_axi_awqos ( m_axi_awqos ) ,
.m_axi_awuser ( m_axi_awuser ) ,
.m_axi_awregion ( m_axi_awregion ) ,
.m_axi_wid ( m_axi_wid ) ,
.m_axi_wdata ( m_axi_wdata ) ,
.m_axi_wstrb ( m_axi_wstrb ) ,
.m_axi_wlast ( m_axi_wlast ) ,
.m_axi_wuser ( m_axi_wuser ) ,
.m_axi_bid ( m_axi_bid ) ,
.m_axi_bresp ( m_axi_bresp ) ,
.m_axi_buser ( m_axi_buser ) ,
.m_axi_arid ( m_axi_arid ) ,
.m_axi_araddr ( m_axi_araddr ) ,
.m_axi_arlen ( m_axi_arlen ) ,
.m_axi_arsize ( m_axi_arsize ) ,
.m_axi_arburst ( m_axi_arburst ) ,
.m_axi_arlock ( m_axi_arlock ) ,
.m_axi_arcache ( m_axi_arcache ) ,
.m_axi_arprot ( m_axi_arprot ) ,
.m_axi_arqos ( m_axi_arqos ) ,
.m_axi_aruser ( m_axi_aruser ) ,
.m_axi_arregion ( m_axi_arregion ) ,
.m_axi_rid ( m_axi_rid ) ,
.m_axi_rdata ( m_axi_rdata ) ,
.m_axi_rresp ( m_axi_rresp ) ,
.m_axi_rlast ( m_axi_rlast ) ,
.m_axi_ruser ( m_axi_ruser )
);
endmodule // axi_register_slice
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_multiplier.v
//
// *Module Description:
// 16x16 Hardware multiplier.
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 23 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_multiplier (
// OUTPUTs
per_dout, // Peripheral data output
// INPUTs
mclk, // Main system clock
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write enable (high active)
puc_rst, // Main system reset
scan_enable // Scan enable (active during scan shifting)
);
// OUTPUTs
//=========
output [15:0] per_dout; // Peripheral data output
// INPUTs
//=========
input mclk; // Main system clock
input [13:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc_rst; // Main system reset
input scan_enable; // Scan enable (active during scan shifting)
//=============================================================================
// 1) PARAMETER/REGISTERS & WIRE DECLARATION
//=============================================================================
// Register base address (must be aligned to decoder bit width)
parameter [14:0] BASE_ADDR = 15'h0130;
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 4;
// Register addresses offset
parameter [DEC_WD-1:0] OP1_MPY = 'h0,
OP1_MPYS = 'h2,
OP1_MAC = 'h4,
OP1_MACS = 'h6,
OP2 = 'h8,
RESLO = 'hA,
RESHI = 'hC,
SUMEXT = 'hE;
// Register one-hot decoder utilities
parameter DEC_SZ = (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] OP1_MPY_D = (BASE_REG << OP1_MPY),
OP1_MPYS_D = (BASE_REG << OP1_MPYS),
OP1_MAC_D = (BASE_REG << OP1_MAC),
OP1_MACS_D = (BASE_REG << OP1_MACS),
OP2_D = (BASE_REG << OP2),
RESLO_D = (BASE_REG << RESLO),
RESHI_D = (BASE_REG << RESHI),
SUMEXT_D = (BASE_REG << SUMEXT);
// Wire pre-declarations
wire result_wr;
wire result_clr;
wire early_read;
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1'b0};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (OP1_MPY_D & {DEC_SZ{(reg_addr == OP1_MPY )}}) |
(OP1_MPYS_D & {DEC_SZ{(reg_addr == OP1_MPYS )}}) |
(OP1_MAC_D & {DEC_SZ{(reg_addr == OP1_MAC )}}) |
(OP1_MACS_D & {DEC_SZ{(reg_addr == OP1_MACS )}}) |
(OP2_D & {DEC_SZ{(reg_addr == OP2 )}}) |
(RESLO_D & {DEC_SZ{(reg_addr == RESLO )}}) |
(RESHI_D & {DEC_SZ{(reg_addr == RESHI )}}) |
(SUMEXT_D & {DEC_SZ{(reg_addr == SUMEXT )}});
// Read/Write probes
wire reg_write = |per_we & reg_sel;
wire reg_read = ~|per_we & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
// Masked input data for byte access
wire [15:0] per_din_msk = per_din & {{8{per_we[1]}}, 8'hff};
//============================================================================
// 3) REGISTERS
//============================================================================
// OP1 Register
//-----------------
reg [15:0] op1;
wire op1_wr = reg_wr[OP1_MPY] |
reg_wr[OP1_MPYS] |
reg_wr[OP1_MAC] |
reg_wr[OP1_MACS];
`ifdef CLOCK_GATING
wire mclk_op1;
omsp_clock_gate clock_gate_op1 (.gclk(mclk_op1),
.clk (mclk), .enable(op1_wr), .scan_enable(scan_enable));
`else
wire UNUSED_scan_enable = scan_enable;
wire mclk_op1 = mclk;
`endif
always @ (posedge mclk_op1 or posedge puc_rst)
if (puc_rst) op1 <= 16'h0000;
`ifdef CLOCK_GATING
else op1 <= per_din_msk;
`else
else if (op1_wr) op1 <= per_din_msk;
`endif
wire [15:0] op1_rd = op1;
// OP2 Register
//-----------------
reg [15:0] op2;
wire op2_wr = reg_wr[OP2];
`ifdef CLOCK_GATING
wire mclk_op2;
omsp_clock_gate clock_gate_op2 (.gclk(mclk_op2),
.clk (mclk), .enable(op2_wr), .scan_enable(scan_enable));
`else
wire mclk_op2 = mclk;
`endif
always @ (posedge mclk_op2 or posedge puc_rst)
if (puc_rst) op2 <= 16'h0000;
`ifdef CLOCK_GATING
else op2 <= per_din_msk;
`else
else if (op2_wr) op2 <= per_din_msk;
`endif
wire [15:0] op2_rd = op2;
// RESLO Register
//-----------------
reg [15:0] reslo;
wire [15:0] reslo_nxt;
wire reslo_wr = reg_wr[RESLO];
`ifdef CLOCK_GATING
wire reslo_en = reslo_wr | result_clr | result_wr;
wire mclk_reslo;
omsp_clock_gate clock_gate_reslo (.gclk(mclk_reslo),
.clk (mclk), .enable(reslo_en), .scan_enable(scan_enable));
`else
wire mclk_reslo = mclk;
`endif
always @ (posedge mclk_reslo or posedge puc_rst)
if (puc_rst) reslo <= 16'h0000;
else if (reslo_wr) reslo <= per_din_msk;
else if (result_clr) reslo <= 16'h0000;
`ifdef CLOCK_GATING
else reslo <= reslo_nxt;
`else
else if (result_wr) reslo <= reslo_nxt;
`endif
wire [15:0] reslo_rd = early_read ? reslo_nxt : reslo;
// RESHI Register
//-----------------
reg [15:0] reshi;
wire [15:0] reshi_nxt;
wire reshi_wr = reg_wr[RESHI];
`ifdef CLOCK_GATING
wire reshi_en = reshi_wr | result_clr | result_wr;
wire mclk_reshi;
omsp_clock_gate clock_gate_reshi (.gclk(mclk_reshi),
.clk (mclk), .enable(reshi_en), .scan_enable(scan_enable));
`else
wire mclk_reshi = mclk;
`endif
always @ (posedge mclk_reshi or posedge puc_rst)
if (puc_rst) reshi <= 16'h0000;
else if (reshi_wr) reshi <= per_din_msk;
else if (result_clr) reshi <= 16'h0000;
`ifdef CLOCK_GATING
else reshi <= reshi_nxt;
`else
else if (result_wr) reshi <= reshi_nxt;
`endif
wire [15:0] reshi_rd = early_read ? reshi_nxt : reshi;
// SUMEXT Register
//-----------------
reg [1:0] sumext_s;
wire [1:0] sumext_s_nxt;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) sumext_s <= 2'b00;
else if (op2_wr) sumext_s <= 2'b00;
else if (result_wr) sumext_s <= sumext_s_nxt;
wire [15:0] sumext_nxt = {{14{sumext_s_nxt[1]}}, sumext_s_nxt};
wire [15:0] sumext = {{14{sumext_s[1]}}, sumext_s};
wire [15:0] sumext_rd = early_read ? sumext_nxt : sumext;
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] op1_mux = op1_rd & {16{reg_rd[OP1_MPY] |
reg_rd[OP1_MPYS] |
reg_rd[OP1_MAC] |
reg_rd[OP1_MACS]}};
wire [15:0] op2_mux = op2_rd & {16{reg_rd[OP2]}};
wire [15:0] reslo_mux = reslo_rd & {16{reg_rd[RESLO]}};
wire [15:0] reshi_mux = reshi_rd & {16{reg_rd[RESHI]}};
wire [15:0] sumext_mux = sumext_rd & {16{reg_rd[SUMEXT]}};
wire [15:0] per_dout = op1_mux |
op2_mux |
reslo_mux |
reshi_mux |
sumext_mux;
//============================================================================
// 5) HARDWARE MULTIPLIER FUNCTIONAL LOGIC
//============================================================================
// Multiplier configuration
//--------------------------
// Detect signed mode
reg sign_sel;
always @ (posedge mclk_op1 or posedge puc_rst)
if (puc_rst) sign_sel <= 1'b0;
`ifdef CLOCK_GATING
else sign_sel <= reg_wr[OP1_MPYS] | reg_wr[OP1_MACS];
`else
else if (op1_wr) sign_sel <= reg_wr[OP1_MPYS] | reg_wr[OP1_MACS];
`endif
// Detect accumulate mode
reg acc_sel;
always @ (posedge mclk_op1 or posedge puc_rst)
if (puc_rst) acc_sel <= 1'b0;
`ifdef CLOCK_GATING
else acc_sel <= reg_wr[OP1_MAC] | reg_wr[OP1_MACS];
`else
else if (op1_wr) acc_sel <= reg_wr[OP1_MAC] | reg_wr[OP1_MACS];
`endif
// Detect whenever the RESHI and RESLO registers should be cleared
assign result_clr = op2_wr & ~acc_sel;
// Combine RESHI & RESLO
wire [31:0] result = {reshi, reslo};
// 16x16 Multiplier (result computed in 1 clock cycle)
//-----------------------------------------------------
`ifdef MPY_16x16
// Detect start of a multiplication
reg cycle;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cycle <= 1'b0;
else cycle <= op2_wr;
assign result_wr = cycle;
// Expand the operands to support signed & unsigned operations
wire signed [16:0] op1_xp = {sign_sel & op1[15], op1};
wire signed [16:0] op2_xp = {sign_sel & op2[15], op2};
// 17x17 signed multiplication
wire signed [33:0] product = op1_xp * op2_xp;
// Accumulate
wire [32:0] result_nxt = {1'b0, result} + {1'b0, product[31:0]};
// Next register values
assign reslo_nxt = result_nxt[15:0];
assign reshi_nxt = result_nxt[31:16];
assign sumext_s_nxt = sign_sel ? {2{result_nxt[31]}} :
{1'b0, result_nxt[32]};
// Since the MAC is completed within 1 clock cycle,
// an early read can't happen.
assign early_read = 1'b0;
// 16x8 Multiplier (result computed in 2 clock cycles)
//-----------------------------------------------------
`else
// Detect start of a multiplication
reg [1:0] cycle;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cycle <= 2'b00;
else cycle <= {cycle[0], op2_wr};
assign result_wr = |cycle;
// Expand the operands to support signed & unsigned operations
wire signed [16:0] op1_xp = {sign_sel & op1[15], op1};
wire signed [8:0] op2_hi_xp = {sign_sel & op2[15], op2[15:8]};
wire signed [8:0] op2_lo_xp = { 1'b0, op2[7:0]};
wire signed [8:0] op2_xp = cycle[0] ? op2_hi_xp : op2_lo_xp;
// 17x9 signed multiplication
wire signed [25:0] product = op1_xp * op2_xp;
wire [31:0] product_xp = cycle[0] ? {product[23:0], 8'h00} :
{{8{sign_sel & product[23]}}, product[23:0]};
// Accumulate
wire [32:0] result_nxt = {1'b0, result} + {1'b0, product_xp[31:0]};
// Next register values
assign reslo_nxt = result_nxt[15:0];
assign reshi_nxt = result_nxt[31:16];
assign sumext_s_nxt = sign_sel ? {2{result_nxt[31]}} :
{1'b0, result_nxt[32] | sumext_s[0]};
// Since the MAC is completed within 2 clock cycle,
// an early read can happen during the second cycle.
assign early_read = cycle[1];
`endif
endmodule // omsp_multiplier
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: [email protected]
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_cpu.v
// Title : Top-level of CPU.
// Dependencies : lm32_include.v
//
// Version 3.4
// 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were
// never serviced.
//
// Version 3.3
// 1. Feature: Support for memory that is tightly coupled to processor core, and
// has a single-cycle access latency (same as caches). Instruction port has
// access to a dedicated physically-mapped memory. Data port has access to
// a dedicated physically-mapped memory. In order to be able to manipulate
// values in both these memories via the debugger, these memories also
// interface with the data port of LM32.
// 2. Feature: Extended Configuration Register
// 3. Bug Fix: Removed port names that conflict with keywords reserved in System-
// Verilog.
//
// Version 3.2
// 1. Bug Fix: Single-stepping a load/store to invalid address causes debugger to
// hang. At the same time CPU fails to register data bus error exception. Bug
// is caused because (a) data bus error exception occurs after load/store has
// passed X stage and next sequential instruction (e.g., brk) is already in X
// stage, and (b) data bus error exception had lower priority than, say, brk
// exception.
// 2. Bug Fix: If a brk (or scall/eret/bret) sequentially follows a load/store to
// invalid location, CPU will fail to register data bus error exception. The
// solution is to stall scall/eret/bret/brk instructions in D pipeline stage
// until load/store has completed.
// 3. Feature: Enable precise identification of load/store that causes seg fault.
// 4. SYNC resets used for register file when implemented in EBRs.
//
// Version 3.1
// 1. Feature: LM32 Register File can now be mapped in to on-chip block RAM (EBR)
// instead of distributed memory by enabling the option in LM32 GUI.
// 2. Feature: LM32 also adds a static branch predictor to improve branch
// performance. All immediate-based forward-pointing branches are predicted
// not-taken. All immediate-based backward-pointing branches are predicted taken.
//
// Version 7.0SP2, 3.0
// No Change
//
// Version 6.1.17
// Initial Release
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_cpu (
// ----- Inputs -------
clk_i,
`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
clk_n_i,
`endif
rst_i,
// From external devices
`ifdef CFG_INTERRUPTS_ENABLED
interrupt,
`endif
// From user logic
`ifdef CFG_USER_ENABLED
user_result,
user_complete,
`endif
`ifdef CFG_JTAG_ENABLED
// From JTAG
jtag_clk,
jtag_update,
jtag_reg_q,
jtag_reg_addr_q,
`endif
`ifdef CFG_IWB_ENABLED
// Instruction Wishbone master
I_DAT_I,
I_ACK_I,
I_ERR_I,
I_RTY_I,
`endif
// Data Wishbone master
D_DAT_I,
D_ACK_I,
D_ERR_I,
D_RTY_I,
// ----- Outputs -------
`ifdef CFG_TRACE_ENABLED
trace_pc,
trace_pc_valid,
trace_exception,
trace_eid,
trace_eret,
`ifdef CFG_DEBUG_ENABLED
trace_bret,
`endif
`endif
`ifdef CFG_JTAG_ENABLED
jtag_reg_d,
jtag_reg_addr_d,
`endif
`ifdef CFG_USER_ENABLED
user_valid,
user_opcode,
user_operand_0,
user_operand_1,
`endif
`ifdef CFG_IWB_ENABLED
// Instruction Wishbone master
I_DAT_O,
I_ADR_O,
I_CYC_O,
I_SEL_O,
I_STB_O,
I_WE_O,
I_CTI_O,
I_LOCK_O,
I_BTE_O,
`endif
// Data Wishbone master
D_DAT_O,
D_ADR_O,
D_CYC_O,
D_SEL_O,
D_STB_O,
D_WE_O,
D_CTI_O,
D_LOCK_O,
D_BTE_O
);
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
parameter eba_reset = `CFG_EBA_RESET; // Reset value for EBA CSR
`ifdef CFG_DEBUG_ENABLED
parameter deba_reset = `CFG_DEBA_RESET; // Reset value for DEBA CSR
`endif
`ifdef CFG_ICACHE_ENABLED
parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways)
parameter icache_sets = `CFG_ICACHE_SETS; // Number of sets
parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE; // Number of bytes per cache line
parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS; // Base address of cachable memory
parameter icache_limit = `CFG_ICACHE_LIMIT; // Limit (highest address) of cachable memory
`else
parameter icache_associativity = 1;
parameter icache_sets = 512;
parameter icache_bytes_per_line = 16;
parameter icache_base_address = 0;
parameter icache_limit = 0;
`endif
`ifdef CFG_DCACHE_ENABLED
parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways)
parameter dcache_sets = `CFG_DCACHE_SETS; // Number of sets
parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE; // Number of bytes per cache line
parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS; // Base address of cachable memory
parameter dcache_limit = `CFG_DCACHE_LIMIT; // Limit (highest address) of cachable memory
`else
parameter dcache_associativity = 1;
parameter dcache_sets = 512;
parameter dcache_bytes_per_line = 16;
parameter dcache_base_address = 0;
parameter dcache_limit = 0;
`endif
`ifdef CFG_DEBUG_ENABLED
parameter watchpoints = `CFG_WATCHPOINTS; // Number of h/w watchpoint CSRs
`else
parameter watchpoints = 0;
`endif
`ifdef CFG_ROM_DEBUG_ENABLED
parameter breakpoints = `CFG_BREAKPOINTS; // Number of h/w breakpoint CSRs
`else
parameter breakpoints = 0;
`endif
`ifdef CFG_INTERRUPTS_ENABLED
parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts
`else
parameter interrupts = 0;
`endif
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
input clk_n_i; // Inverted clock
`endif
input rst_i; // Reset
`ifdef CFG_INTERRUPTS_ENABLED
input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins
`endif
`ifdef CFG_USER_ENABLED
input [`LM32_WORD_RNG] user_result; // User-defined instruction result
input user_complete; // User-defined instruction execution is complete
`endif
`ifdef CFG_JTAG_ENABLED
input jtag_clk; // JTAG clock
input jtag_update; // JTAG state machine is in data register update state
input [`LM32_BYTE_RNG] jtag_reg_q;
input [2:0] jtag_reg_addr_q;
`endif
`ifdef CFG_IWB_ENABLED
input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
input I_ACK_I; // Instruction Wishbone interface acknowledgement
input I_ERR_I; // Instruction Wishbone interface error
input I_RTY_I; // Instruction Wishbone interface retry
`endif
input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
input D_ACK_I; // Data Wishbone interface acknowledgement
input D_ERR_I; // Data Wishbone interface error
input D_RTY_I; // Data Wishbone interface retry
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
`ifdef CFG_TRACE_ENABLED
output [`LM32_PC_RNG] trace_pc; // PC to trace
reg [`LM32_PC_RNG] trace_pc;
output trace_pc_valid; // Indicates that a new trace PC is valid
reg trace_pc_valid;
output trace_exception; // Indicates an exception has occured
reg trace_exception;
output [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured
reg [`LM32_EID_RNG] trace_eid;
output trace_eret; // Indicates an eret instruction has been executed
reg trace_eret;
`ifdef CFG_DEBUG_ENABLED
output trace_bret; // Indicates a bret instruction has been executed
reg trace_bret;
`endif
`endif
`ifdef CFG_JTAG_ENABLED
output [`LM32_BYTE_RNG] jtag_reg_d;
wire [`LM32_BYTE_RNG] jtag_reg_d;
output [2:0] jtag_reg_addr_d;
wire [2:0] jtag_reg_addr_d;
`endif
`ifdef CFG_USER_ENABLED
output user_valid; // Indicates if user_opcode is valid
wire user_valid;
output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
reg [`LM32_USER_OPCODE_RNG] user_opcode;
output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
wire [`LM32_WORD_RNG] user_operand_0;
output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
wire [`LM32_WORD_RNG] user_operand_1;
`endif
`ifdef CFG_IWB_ENABLED
output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
wire [`LM32_WORD_RNG] I_DAT_O;
output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
wire [`LM32_WORD_RNG] I_ADR_O;
output I_CYC_O; // Instruction Wishbone interface cycle
wire I_CYC_O;
output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
output I_STB_O; // Instruction Wishbone interface strobe
wire I_STB_O;
output I_WE_O; // Instruction Wishbone interface write enable
wire I_WE_O;
output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
wire [`LM32_CTYPE_RNG] I_CTI_O;
output I_LOCK_O; // Instruction Wishbone interface lock bus
wire I_LOCK_O;
output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
wire [`LM32_BTYPE_RNG] I_BTE_O;
`endif
output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
wire [`LM32_WORD_RNG] D_DAT_O;
output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
wire [`LM32_WORD_RNG] D_ADR_O;
output D_CYC_O; // Data Wishbone interface cycle
wire D_CYC_O;
output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
output D_STB_O; // Data Wishbone interface strobe
wire D_STB_O;
output D_WE_O; // Data Wishbone interface write enable
wire D_WE_O;
output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
wire [`LM32_CTYPE_RNG] D_CTI_O;
output D_LOCK_O; // Date Wishbone interface lock bus
wire D_LOCK_O;
output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
wire [`LM32_BTYPE_RNG] D_BTE_O;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
// Pipeline registers
`ifdef LM32_CACHE_ENABLED
reg valid_a; // Instruction in A stage is valid
`endif
reg valid_f; // Instruction in F stage is valid
reg valid_d; // Instruction in D stage is valid
reg valid_x; // Instruction in X stage is valid
reg valid_m; // Instruction in M stage is valid
reg valid_w; // Instruction in W stage is valid
wire q_x;
wire [`LM32_WORD_RNG] immediate_d; // Immediate operand
wire load_d; // Indicates a load instruction
reg load_x;
reg load_m;
wire load_q_x;
wire store_q_x;
wire store_d; // Indicates a store instruction
reg store_x;
reg store_m;
wire [`LM32_SIZE_RNG] size_d; // Size of load/store (byte, hword, word)
reg [`LM32_SIZE_RNG] size_x;
wire branch_d; // Indicates a branch instruction
wire branch_predict_d; // Indicates a branch is predicted
wire branch_predict_taken_d; // Indicates a branch is predicted taken
wire [`LM32_PC_RNG] branch_predict_address_d; // Address to which predicted branch jumps
wire [`LM32_PC_RNG] branch_target_d;
wire bi_unconditional;
wire bi_conditional;
reg branch_x;
reg branch_predict_x;
reg branch_predict_taken_x;
reg branch_m;
reg branch_predict_m;
reg branch_predict_taken_m;
wire branch_mispredict_taken_m; // Indicates a branch was mispredicted as taken
wire branch_flushX_m; // Indicates that instruction in X stage must be squashed
wire branch_reg_d; // Branch to register or immediate
wire [`LM32_PC_RNG] branch_offset_d; // Branch offset for immediate branches
reg [`LM32_PC_RNG] branch_target_x; // Address to branch to
reg [`LM32_PC_RNG] branch_target_m;
wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0
wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1
wire x_result_sel_csr_d; // Select X stage result from CSRs
reg x_result_sel_csr_x;
`ifdef LM32_MC_ARITHMETIC_ENABLED
wire x_result_sel_mc_arith_d; // Select X stage result from multi-cycle arithmetic unit
reg x_result_sel_mc_arith_x;
`endif
`ifdef LM32_NO_BARREL_SHIFT
wire x_result_sel_shift_d; // Select X stage result from shifter
reg x_result_sel_shift_x;
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
wire x_result_sel_sext_d; // Select X stage result from sign-extend logic
reg x_result_sel_sext_x;
`endif
wire x_result_sel_logic_d; // Select X stage result from logic op unit
reg x_result_sel_logic_x;
`ifdef CFG_USER_ENABLED
wire x_result_sel_user_d; // Select X stage result from user-defined logic
reg x_result_sel_user_x;
`endif
wire x_result_sel_add_d; // Select X stage result from adder
reg x_result_sel_add_x;
wire m_result_sel_compare_d; // Select M stage result from comparison logic
reg m_result_sel_compare_x;
reg m_result_sel_compare_m;
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
wire m_result_sel_shift_d; // Select M stage result from shifter
reg m_result_sel_shift_x;
reg m_result_sel_shift_m;
`endif
wire w_result_sel_load_d; // Select W stage result from load/store unit
reg w_result_sel_load_x;
reg w_result_sel_load_m;
reg w_result_sel_load_w;
`ifdef CFG_PL_MULTIPLY_ENABLED
wire w_result_sel_mul_d; // Select W stage result from multiplier
reg w_result_sel_mul_x;
reg w_result_sel_mul_m;
reg w_result_sel_mul_w;
`endif
wire x_bypass_enable_d; // Whether result is bypassable in X stage
reg x_bypass_enable_x;
wire m_bypass_enable_d; // Whether result is bypassable in M stage
reg m_bypass_enable_x;
reg m_bypass_enable_m;
wire sign_extend_d; // Whether to sign-extend or zero-extend
reg sign_extend_x;
wire write_enable_d; // Register file write enable
reg write_enable_x;
wire write_enable_q_x;
reg write_enable_m;
wire write_enable_q_m;
reg write_enable_w;
wire write_enable_q_w;
wire read_enable_0_d; // Register file read enable 0
wire [`LM32_REG_IDX_RNG] read_idx_0_d; // Register file read index 0
wire read_enable_1_d; // Register file read enable 1
wire [`LM32_REG_IDX_RNG] read_idx_1_d; // Register file read index 1
wire [`LM32_REG_IDX_RNG] write_idx_d; // Register file write index
reg [`LM32_REG_IDX_RNG] write_idx_x;
reg [`LM32_REG_IDX_RNG] write_idx_m;
reg [`LM32_REG_IDX_RNG] write_idx_w;
wire [`LM32_CSR_RNG] csr_d; // CSR read/write index
reg [`LM32_CSR_RNG] csr_x;
wire [`LM32_CONDITION_RNG] condition_d; // Branch condition
reg [`LM32_CONDITION_RNG] condition_x;
`ifdef CFG_DEBUG_ENABLED
wire break_d; // Indicates a break instruction
reg break_x;
`endif
wire scall_d; // Indicates a scall instruction
reg scall_x;
wire eret_d; // Indicates an eret instruction
reg eret_x;
wire eret_q_x;
reg eret_m;
`ifdef CFG_TRACE_ENABLED
reg eret_w;
`endif
`ifdef CFG_DEBUG_ENABLED
wire bret_d; // Indicates a bret instruction
reg bret_x;
wire bret_q_x;
reg bret_m;
`ifdef CFG_TRACE_ENABLED
reg bret_w;
`endif
`endif
wire csr_write_enable_d; // CSR write enable
reg csr_write_enable_x;
wire csr_write_enable_q_x;
`ifdef CFG_USER_ENABLED
wire [`LM32_USER_OPCODE_RNG] user_opcode_d; // User-defined instruction opcode
`endif
`ifdef CFG_BUS_ERRORS_ENABLED
wire bus_error_d; // Indicates an bus error occured while fetching the instruction in this pipeline stage
reg bus_error_x;
reg data_bus_error_exception_m;
reg [`LM32_PC_RNG] memop_pc_w;
`endif
reg [`LM32_WORD_RNG] d_result_0; // Result of instruction in D stage (operand 0)
reg [`LM32_WORD_RNG] d_result_1; // Result of instruction in D stage (operand 1)
reg [`LM32_WORD_RNG] x_result; // Result of instruction in X stage
reg [`LM32_WORD_RNG] m_result; // Result of instruction in M stage
reg [`LM32_WORD_RNG] w_result; // Result of instruction in W stage
reg [`LM32_WORD_RNG] operand_0_x; // Operand 0 for X stage instruction
reg [`LM32_WORD_RNG] operand_1_x; // Operand 1 for X stage instruction
reg [`LM32_WORD_RNG] store_operand_x; // Data read from register to store
reg [`LM32_WORD_RNG] operand_m; // Operand for M stage instruction
reg [`LM32_WORD_RNG] operand_w; // Operand for W stage instruction
// To/from register file
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
reg [`LM32_WORD_RNG] reg_data_live_0;
reg [`LM32_WORD_RNG] reg_data_live_1;
reg use_buf; // Whether to use reg_data_live or reg_data_buf
reg [`LM32_WORD_RNG] reg_data_buf_0;
reg [`LM32_WORD_RNG] reg_data_buf_1;
`endif
`ifdef LM32_EBR_REGISTER_FILE
`else
reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1]; // Register file
`endif
wire [`LM32_WORD_RNG] reg_data_0; // Register file read port 0 data
wire [`LM32_WORD_RNG] reg_data_1; // Register file read port 1 data
reg [`LM32_WORD_RNG] bypass_data_0; // Register value 0 after bypassing
reg [`LM32_WORD_RNG] bypass_data_1; // Register value 1 after bypassing
wire reg_write_enable_q_w;
reg interlock; // Indicates pipeline should be stalled because of a read-after-write hazzard
wire stall_a; // Stall instruction in A pipeline stage
wire stall_f; // Stall instruction in F pipeline stage
wire stall_d; // Stall instruction in D pipeline stage
wire stall_x; // Stall instruction in X pipeline stage
wire stall_m; // Stall instruction in M pipeline stage
// To/from adder
wire adder_op_d; // Whether to add or subtract
reg adder_op_x;
reg adder_op_x_n; // Inverted version of adder_op_x
wire [`LM32_WORD_RNG] adder_result_x; // Result from adder
wire adder_overflow_x; // Whether a signed overflow occured
wire adder_carry_n_x; // Whether a carry was generated
// To/from logical operations unit
wire [`LM32_LOGIC_OP_RNG] logic_op_d; // Which operation to perform
reg [`LM32_LOGIC_OP_RNG] logic_op_x;
wire [`LM32_WORD_RNG] logic_result_x; // Result of logical operation
`ifdef CFG_SIGN_EXTEND_ENABLED
// From sign-extension unit
wire [`LM32_WORD_RNG] sextb_result_x; // Result of byte sign-extension
wire [`LM32_WORD_RNG] sexth_result_x; // Result of half-word sign-extenstion
wire [`LM32_WORD_RNG] sext_result_x; // Result of sign-extension specified by instruction
`endif
// To/from shifter
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
`ifdef CFG_ROTATE_ENABLED
wire rotate_d; // Whether we should rotate or shift
reg rotate_x;
`endif
wire direction_d; // Which direction to shift in
reg direction_x;
reg direction_m;
wire [`LM32_WORD_RNG] shifter_result_m; // Result of shifter
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
wire shift_left_d; // Indicates whether to perform a left shift or not
wire shift_left_q_d;
wire shift_right_d; // Indicates whether to perform a right shift or not
wire shift_right_q_d;
`endif
`ifdef LM32_NO_BARREL_SHIFT
wire [`LM32_WORD_RNG] shifter_result_x; // Result of single-bit right shifter
`endif
// To/from multiplier
`ifdef LM32_MULTIPLY_ENABLED
wire [`LM32_WORD_RNG] multiplier_result_w; // Result from multiplier
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
wire multiply_d; // Indicates whether to perform a multiply or not
wire multiply_q_d;
`endif
// To/from divider
`ifdef CFG_MC_DIVIDE_ENABLED
wire divide_d; // Indicates whether to perform a divider or not
wire divide_q_d;
wire modulus_d;
wire modulus_q_d;
wire divide_by_zero_x; // Indicates an attempt was made to divide by zero
`endif
// To from multi-cycle arithmetic unit
`ifdef LM32_MC_ARITHMETIC_ENABLED
wire mc_stall_request_x; // Multi-cycle arithmetic unit stall request
wire [`LM32_WORD_RNG] mc_result_x;
`endif
// From CSRs
`ifdef CFG_INTERRUPTS_ENABLED
wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs
`endif
wire [`LM32_WORD_RNG] cfg; // Configuration CSR
wire [`LM32_WORD_RNG] cfg2; // Extended Configuration CSR
`ifdef CFG_CYCLE_COUNTER_ENABLED
reg [`LM32_WORD_RNG] cc; // Cycle counter CSR
`endif
reg [`LM32_WORD_RNG] csr_read_data_x; // Data read from CSRs
// To/from instruction unit
wire [`LM32_PC_RNG] pc_f; // PC of instruction in F stage
wire [`LM32_PC_RNG] pc_d; // PC of instruction in D stage
wire [`LM32_PC_RNG] pc_x; // PC of instruction in X stage
wire [`LM32_PC_RNG] pc_m; // PC of instruction in M stage
wire [`LM32_PC_RNG] pc_w; // PC of instruction in W stage
`ifdef CFG_TRACE_ENABLED
reg [`LM32_PC_RNG] pc_c; // PC of last commited instruction
`endif
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
wire [`LM32_INSTRUCTION_RNG] instruction_f; // Instruction in F stage
`endif
//pragma attribute instruction_d preserve_signal true
//pragma attribute instruction_d preserve_driver true
wire [`LM32_INSTRUCTION_RNG] instruction_d; // Instruction in D stage
`ifdef CFG_ICACHE_ENABLED
wire iflush; // Flush instruction cache
wire icache_stall_request; // Stall pipeline because instruction cache is busy
wire icache_restart_request; // Restart instruction that caused an instruction cache miss
wire icache_refill_request; // Request to refill instruction cache
wire icache_refilling; // Indicates the instruction cache is being refilled
`endif
`ifdef CFG_IROM_ENABLED
wire [`LM32_WORD_RNG] irom_store_data_m; // Store data to instruction ROM
wire [`LM32_WORD_RNG] irom_address_xm; // Address to instruction ROM from load-store unit
wire [`LM32_WORD_RNG] irom_data_m; // Load data from instruction ROM
wire irom_we_xm; // Indicates data needs to be written to instruction ROM
wire irom_stall_request_x; // Indicates D stage needs to be stalled on a store to instruction ROM
`endif
// To/from load/store unit
`ifdef CFG_DCACHE_ENABLED
wire dflush_x; // Flush data cache
reg dflush_m;
wire dcache_stall_request; // Stall pipeline because data cache is busy
wire dcache_restart_request; // Restart instruction that caused a data cache miss
wire dcache_refill_request; // Request to refill data cache
wire dcache_refilling; // Indicates the data cache is being refilled
`endif
wire [`LM32_WORD_RNG] load_data_w; // Result of a load instruction
wire stall_wb_load; // Stall pipeline because of a load via the data Wishbone interface
// To/from JTAG interface
`ifdef CFG_JTAG_ENABLED
`ifdef CFG_JTAG_UART_ENABLED
wire [`LM32_WORD_RNG] jtx_csr_read_data; // Read data for JTX CSR
wire [`LM32_WORD_RNG] jrx_csr_read_data; // Read data for JRX CSR
`endif
`ifdef CFG_HW_DEBUG_ENABLED
wire jtag_csr_write_enable; // Debugger CSR write enable
wire [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR
wire [`LM32_CSR_RNG] jtag_csr; // Which CSR to write
wire jtag_read_enable;
wire [`LM32_BYTE_RNG] jtag_read_data;
wire jtag_write_enable;
wire [`LM32_BYTE_RNG] jtag_write_data;
wire [`LM32_WORD_RNG] jtag_address;
wire jtag_access_complete;
`endif
`ifdef CFG_DEBUG_ENABLED
wire jtag_break; // Request from debugger to raise a breakpoint
`endif
`endif
// Hazzard detection
wire raw_x_0; // RAW hazzard between instruction in X stage and read port 0
wire raw_x_1; // RAW hazzard between instruction in X stage and read port 1
wire raw_m_0; // RAW hazzard between instruction in M stage and read port 0
wire raw_m_1; // RAW hazzard between instruction in M stage and read port 1
wire raw_w_0; // RAW hazzard between instruction in W stage and read port 0
wire raw_w_1; // RAW hazzard between instruction in W stage and read port 1
// Control flow
wire cmp_zero; // Result of comparison is zero
wire cmp_negative; // Result of comparison is negative
wire cmp_overflow; // Comparison produced an overflow
wire cmp_carry_n; // Comparison produced a carry, inverted
reg condition_met_x; // Condition of branch instruction is met
reg condition_met_m;
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
wire branch_taken_x; // Branch is taken in X stage
`endif
wire branch_taken_m; // Branch is taken in M stage
wire kill_f; // Kill instruction in F stage
wire kill_d; // Kill instruction in D stage
wire kill_x; // Kill instruction in X stage
wire kill_m; // Kill instruction in M stage
wire kill_w; // Kill instruction in W stage
reg [`LM32_PC_WIDTH+2-1:8] eba; // Exception Base Address (EBA) CSR
`ifdef CFG_DEBUG_ENABLED
reg [`LM32_PC_WIDTH+2-1:8] deba; // Debug Exception Base Address (DEBA) CSR
`endif
reg [`LM32_EID_RNG] eid_x; // Exception ID in X stage
`ifdef CFG_TRACE_ENABLED
reg [`LM32_EID_RNG] eid_m; // Exception ID in M stage
reg [`LM32_EID_RNG] eid_w; // Exception ID in W stage
`endif
`ifdef CFG_DEBUG_ENABLED
`ifdef LM32_SINGLE_STEP_ENABLED
wire dc_ss; // Is single-step enabled
`endif
wire dc_re; // Remap all exceptions
wire exception_x; // An exception occured in the X stage
reg exception_m; // An instruction that caused an exception is in the M stage
wire debug_exception_x; // Indicates if a debug exception has occured
reg debug_exception_m;
reg debug_exception_w;
wire debug_exception_q_w;
wire non_debug_exception_x; // Indicates if a non debug exception has occured
reg non_debug_exception_m;
reg non_debug_exception_w;
wire non_debug_exception_q_w;
`else
wire exception_x; // Indicates if a debug exception has occured
reg exception_m;
reg exception_w;
wire exception_q_w;
`endif
`ifdef CFG_DEBUG_ENABLED
`ifdef CFG_JTAG_ENABLED
wire reset_exception; // Indicates if a reset exception has occured
`endif
`endif
`ifdef CFG_INTERRUPTS_ENABLED
wire interrupt_exception; // Indicates if an interrupt exception has occured
`endif
`ifdef CFG_DEBUG_ENABLED
wire breakpoint_exception; // Indicates if a breakpoint exception has occured
wire watchpoint_exception; // Indicates if a watchpoint exception has occured
`endif
`ifdef CFG_BUS_ERRORS_ENABLED
wire instruction_bus_error_exception; // Indicates if an instruction bus error exception has occured
wire data_bus_error_exception; // Indicates if a data bus error exception has occured
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
wire divide_by_zero_exception; // Indicates if a divide by zero exception has occured
`endif
wire system_call_exception; // Indicates if a system call exception has occured
`ifdef CFG_BUS_ERRORS_ENABLED
reg data_bus_error_seen; // Indicates if a data bus error was seen
`endif
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
`include "lm32_functions.v"
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
// Instruction unit
lm32_instruction_unit #(
.associativity (icache_associativity),
.sets (icache_sets),
.bytes_per_line (icache_bytes_per_line),
.base_address (icache_base_address),
.limit (icache_limit)
) instruction_unit (
// ----- Inputs -------
.clk_i (clk_i),
.rst_i (rst_i),
// From pipeline
.stall_a (stall_a),
.stall_f (stall_f),
.stall_d (stall_d),
.stall_x (stall_x),
.stall_m (stall_m),
.valid_f (valid_f),
.valid_d (valid_d),
.kill_f (kill_f),
.branch_predict_taken_d (branch_predict_taken_d),
.branch_predict_address_d (branch_predict_address_d),
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
.branch_taken_x (branch_taken_x),
.branch_target_x (branch_target_x),
`endif
.exception_m (exception_m),
.branch_taken_m (branch_taken_m),
.branch_mispredict_taken_m (branch_mispredict_taken_m),
.branch_target_m (branch_target_m),
`ifdef CFG_ICACHE_ENABLED
.iflush (iflush),
`endif
`ifdef CFG_IROM_ENABLED
.irom_store_data_m (irom_store_data_m),
.irom_address_xm (irom_address_xm),
.irom_we_xm (irom_we_xm),
`endif
`ifdef CFG_DCACHE_ENABLED
.dcache_restart_request (dcache_restart_request),
.dcache_refill_request (dcache_refill_request),
.dcache_refilling (dcache_refilling),
`endif
`ifdef CFG_IWB_ENABLED
// From Wishbone
.i_dat_i (I_DAT_I),
.i_ack_i (I_ACK_I),
.i_err_i (I_ERR_I),
.i_rty_i (I_RTY_I),
`endif
`ifdef CFG_HW_DEBUG_ENABLED
.jtag_read_enable (jtag_read_enable),
.jtag_write_enable (jtag_write_enable),
.jtag_write_data (jtag_write_data),
.jtag_address (jtag_address),
`endif
// ----- Outputs -------
// To pipeline
.pc_f (pc_f),
.pc_d (pc_d),
.pc_x (pc_x),
.pc_m (pc_m),
.pc_w (pc_w),
`ifdef CFG_ICACHE_ENABLED
.icache_stall_request (icache_stall_request),
.icache_restart_request (icache_restart_request),
.icache_refill_request (icache_refill_request),
.icache_refilling (icache_refilling),
`endif
`ifdef CFG_IROM_ENABLED
.irom_data_m (irom_data_m),
`endif
`ifdef CFG_IWB_ENABLED
// To Wishbone
.i_dat_o (I_DAT_O),
.i_adr_o (I_ADR_O),
.i_cyc_o (I_CYC_O),
.i_sel_o (I_SEL_O),
.i_stb_o (I_STB_O),
.i_we_o (I_WE_O),
.i_cti_o (I_CTI_O),
.i_lock_o (I_LOCK_O),
.i_bte_o (I_BTE_O),
`endif
`ifdef CFG_HW_DEBUG_ENABLED
.jtag_read_data (jtag_read_data),
.jtag_access_complete (jtag_access_complete),
`endif
`ifdef CFG_BUS_ERRORS_ENABLED
.bus_error_d (bus_error_d),
`endif
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
.instruction_f (instruction_f),
`endif
.instruction_d (instruction_d)
);
// Instruction decoder
lm32_decoder decoder (
// ----- Inputs -------
.instruction (instruction_d),
// ----- Outputs -------
.d_result_sel_0 (d_result_sel_0_d),
.d_result_sel_1 (d_result_sel_1_d),
.x_result_sel_csr (x_result_sel_csr_d),
`ifdef LM32_MC_ARITHMETIC_ENABLED
.x_result_sel_mc_arith (x_result_sel_mc_arith_d),
`endif
`ifdef LM32_NO_BARREL_SHIFT
.x_result_sel_shift (x_result_sel_shift_d),
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
.x_result_sel_sext (x_result_sel_sext_d),
`endif
.x_result_sel_logic (x_result_sel_logic_d),
`ifdef CFG_USER_ENABLED
.x_result_sel_user (x_result_sel_user_d),
`endif
.x_result_sel_add (x_result_sel_add_d),
.m_result_sel_compare (m_result_sel_compare_d),
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
.m_result_sel_shift (m_result_sel_shift_d),
`endif
.w_result_sel_load (w_result_sel_load_d),
`ifdef CFG_PL_MULTIPLY_ENABLED
.w_result_sel_mul (w_result_sel_mul_d),
`endif
.x_bypass_enable (x_bypass_enable_d),
.m_bypass_enable (m_bypass_enable_d),
.read_enable_0 (read_enable_0_d),
.read_idx_0 (read_idx_0_d),
.read_enable_1 (read_enable_1_d),
.read_idx_1 (read_idx_1_d),
.write_enable (write_enable_d),
.write_idx (write_idx_d),
.immediate (immediate_d),
.branch_offset (branch_offset_d),
.load (load_d),
.store (store_d),
.size (size_d),
.sign_extend (sign_extend_d),
.adder_op (adder_op_d),
.logic_op (logic_op_d),
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
.direction (direction_d),
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
.shift_left (shift_left_d),
.shift_right (shift_right_d),
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
.multiply (multiply_d),
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
.divide (divide_d),
.modulus (modulus_d),
`endif
.branch (branch_d),
.bi_unconditional (bi_unconditional),
.bi_conditional (bi_conditional),
.branch_reg (branch_reg_d),
.condition (condition_d),
`ifdef CFG_DEBUG_ENABLED
.break_opcode (break_d),
`endif
.scall (scall_d),
.eret (eret_d),
`ifdef CFG_DEBUG_ENABLED
.bret (bret_d),
`endif
`ifdef CFG_USER_ENABLED
.user_opcode (user_opcode_d),
`endif
.csr_write_enable (csr_write_enable_d)
);
// Load/store unit
lm32_load_store_unit #(
.associativity (dcache_associativity),
.sets (dcache_sets),
.bytes_per_line (dcache_bytes_per_line),
.base_address (dcache_base_address),
.limit (dcache_limit)
) load_store_unit (
// ----- Inputs -------
.clk_i (clk_i),
.rst_i (rst_i),
// From pipeline
.stall_a (stall_a),
.stall_x (stall_x),
.stall_m (stall_m),
.kill_x (kill_x),
.kill_m (kill_m),
.exception_m (exception_m),
.store_operand_x (store_operand_x),
.load_store_address_x (adder_result_x),
.load_store_address_m (operand_m),
.load_store_address_w (operand_w[1:0]),
.load_x (load_x),
.store_x (store_x),
.load_q_x (load_q_x),
.store_q_x (store_q_x),
.load_q_m (load_q_m),
.store_q_m (store_q_m),
.sign_extend_x (sign_extend_x),
.size_x (size_x),
`ifdef CFG_DCACHE_ENABLED
.dflush (dflush_m),
`endif
`ifdef CFG_IROM_ENABLED
.irom_data_m (irom_data_m),
`endif
// From Wishbone
.d_dat_i (D_DAT_I),
.d_ack_i (D_ACK_I),
.d_err_i (D_ERR_I),
.d_rty_i (D_RTY_I),
// ----- Outputs -------
// To pipeline
`ifdef CFG_DCACHE_ENABLED
.dcache_refill_request (dcache_refill_request),
.dcache_restart_request (dcache_restart_request),
.dcache_stall_request (dcache_stall_request),
.dcache_refilling (dcache_refilling),
`endif
`ifdef CFG_IROM_ENABLED
.irom_store_data_m (irom_store_data_m),
.irom_address_xm (irom_address_xm),
.irom_we_xm (irom_we_xm),
.irom_stall_request_x (irom_stall_request_x),
`endif
.load_data_w (load_data_w),
.stall_wb_load (stall_wb_load),
// To Wishbone
.d_dat_o (D_DAT_O),
.d_adr_o (D_ADR_O),
.d_cyc_o (D_CYC_O),
.d_sel_o (D_SEL_O),
.d_stb_o (D_STB_O),
.d_we_o (D_WE_O),
.d_cti_o (D_CTI_O),
.d_lock_o (D_LOCK_O),
.d_bte_o (D_BTE_O)
);
// Adder
lm32_adder adder (
// ----- Inputs -------
.adder_op_x (adder_op_x),
.adder_op_x_n (adder_op_x_n),
.operand_0_x (operand_0_x),
.operand_1_x (operand_1_x),
// ----- Outputs -------
.adder_result_x (adder_result_x),
.adder_carry_n_x (adder_carry_n_x),
.adder_overflow_x (adder_overflow_x)
);
// Logic operations
lm32_logic_op logic_op (
// ----- Inputs -------
.logic_op_x (logic_op_x),
.operand_0_x (operand_0_x),
.operand_1_x (operand_1_x),
// ----- Outputs -------
.logic_result_x (logic_result_x)
);
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
// Pipelined barrel-shifter
lm32_shifter shifter (
// ----- Inputs -------
.clk_i (clk_i),
.rst_i (rst_i),
.stall_x (stall_x),
.direction_x (direction_x),
.sign_extend_x (sign_extend_x),
.operand_0_x (operand_0_x),
.operand_1_x (operand_1_x),
// ----- Outputs -------
.shifter_result_m (shifter_result_m)
);
`endif
`ifdef CFG_PL_MULTIPLY_ENABLED
// Pipeline fixed-point multiplier
lm32_multiplier multiplier (
// ----- Inputs -------
.clk_i (clk_i),
.rst_i (rst_i),
.stall_x (stall_x),
.stall_m (stall_m),
.operand_0 (d_result_0),
.operand_1 (d_result_1),
// ----- Outputs -------
.result (multiplier_result_w)
);
`endif
`ifdef LM32_MC_ARITHMETIC_ENABLED
// Multi-cycle arithmetic
lm32_mc_arithmetic mc_arithmetic (
// ----- Inputs -------
.clk_i (clk_i),
.rst_i (rst_i),
.stall_d (stall_d),
.kill_x (kill_x),
`ifdef CFG_MC_DIVIDE_ENABLED
.divide_d (divide_q_d),
.modulus_d (modulus_q_d),
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
.multiply_d (multiply_q_d),
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
.shift_left_d (shift_left_q_d),
.shift_right_d (shift_right_q_d),
.sign_extend_d (sign_extend_d),
`endif
.operand_0_d (d_result_0),
.operand_1_d (d_result_1),
// ----- Outputs -------
.result_x (mc_result_x),
`ifdef CFG_MC_DIVIDE_ENABLED
.divide_by_zero_x (divide_by_zero_x),
`endif
.stall_request_x (mc_stall_request_x)
);
`endif
`ifdef CFG_INTERRUPTS_ENABLED
// Interrupt unit
lm32_interrupt interrupt_unit (
// ----- Inputs -------
.clk_i (clk_i),
.rst_i (rst_i),
// From external devices
.interrupt (interrupt),
// From pipeline
.stall_x (stall_x),
`ifdef CFG_DEBUG_ENABLED
.non_debug_exception (non_debug_exception_q_w),
.debug_exception (debug_exception_q_w),
`else
.exception (exception_q_w),
`endif
.eret_q_x (eret_q_x),
`ifdef CFG_DEBUG_ENABLED
.bret_q_x (bret_q_x),
`endif
.csr (csr_x),
.csr_write_data (operand_1_x),
.csr_write_enable (csr_write_enable_q_x),
// ----- Outputs -------
.interrupt_exception (interrupt_exception),
// To pipeline
.csr_read_data (interrupt_csr_read_data_x)
);
`endif
`ifdef CFG_JTAG_ENABLED
// JTAG interface
lm32_jtag jtag (
// ----- Inputs -------
.clk_i (clk_i),
.rst_i (rst_i),
// From JTAG
.jtag_clk (jtag_clk),
.jtag_update (jtag_update),
.jtag_reg_q (jtag_reg_q),
.jtag_reg_addr_q (jtag_reg_addr_q),
// From pipeline
`ifdef CFG_JTAG_UART_ENABLED
.csr (csr_x),
.csr_write_data (operand_1_x),
.csr_write_enable (csr_write_enable_q_x),
.stall_x (stall_x),
`endif
`ifdef CFG_HW_DEBUG_ENABLED
.jtag_read_data (jtag_read_data),
.jtag_access_complete (jtag_access_complete),
`endif
`ifdef CFG_DEBUG_ENABLED
.exception_q_w (debug_exception_q_w || non_debug_exception_q_w),
`endif
// ----- Outputs -------
// To pipeline
`ifdef CFG_JTAG_UART_ENABLED
.jtx_csr_read_data (jtx_csr_read_data),
.jrx_csr_read_data (jrx_csr_read_data),
`endif
`ifdef CFG_HW_DEBUG_ENABLED
.jtag_csr_write_enable (jtag_csr_write_enable),
.jtag_csr_write_data (jtag_csr_write_data),
.jtag_csr (jtag_csr),
.jtag_read_enable (jtag_read_enable),
.jtag_write_enable (jtag_write_enable),
.jtag_write_data (jtag_write_data),
.jtag_address (jtag_address),
`endif
`ifdef CFG_DEBUG_ENABLED
.jtag_break (jtag_break),
.jtag_reset (reset_exception),
`endif
// To JTAG
.jtag_reg_d (jtag_reg_d),
.jtag_reg_addr_d (jtag_reg_addr_d)
);
`endif
`ifdef CFG_DEBUG_ENABLED
// Debug unit
lm32_debug #(
.breakpoints (breakpoints),
.watchpoints (watchpoints)
) hw_debug (
// ----- Inputs -------
.clk_i (clk_i),
.rst_i (rst_i),
.pc_x (pc_x),
.load_x (load_x),
.store_x (store_x),
.load_store_address_x (adder_result_x),
.csr_write_enable_x (csr_write_enable_q_x),
.csr_write_data (operand_1_x),
.csr_x (csr_x),
`ifdef CFG_HW_DEBUG_ENABLED
.jtag_csr_write_enable (jtag_csr_write_enable),
.jtag_csr_write_data (jtag_csr_write_data),
.jtag_csr (jtag_csr),
`endif
`ifdef LM32_SINGLE_STEP_ENABLED
.eret_q_x (eret_q_x),
.bret_q_x (bret_q_x),
.stall_x (stall_x),
.exception_x (exception_x),
.q_x (q_x),
`ifdef CFG_DCACHE_ENABLED
.dcache_refill_request (dcache_refill_request),
`endif
`endif
// ----- Outputs -------
`ifdef LM32_SINGLE_STEP_ENABLED
.dc_ss (dc_ss),
`endif
.dc_re (dc_re),
.bp_match (bp_match),
.wp_match (wp_match)
);
`endif
// Register file
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
/*----------------------------------------------------------------------
Register File is implemented using EBRs. There can be three accesses to
the register file in each cycle: two reads and one write. On-chip block
RAM has two read/write ports. To accomodate three accesses, two on-chip
block RAMs are used (each register file "write" is made to both block
RAMs).
One limitation of the on-chip block RAMs is that one cannot perform a
read and write to same location in a cycle (if this is done, then the
data read out is indeterminate).
----------------------------------------------------------------------*/
wire [31:0] regfile_data_0, regfile_data_1;
reg [31:0] w_result_d;
reg regfile_raw_0, regfile_raw_0_nxt;
reg regfile_raw_1, regfile_raw_1_nxt;
/*----------------------------------------------------------------------
Check if read and write is being performed to same register in current
cycle? This is done by comparing the read and write IDXs.
----------------------------------------------------------------------*/
always @(reg_write_enable_q_w or write_idx_w or instruction_f)
begin
if (reg_write_enable_q_w
&& (write_idx_w == instruction_f[25:21]))
regfile_raw_0_nxt = 1'b1;
else
regfile_raw_0_nxt = 1'b0;
if (reg_write_enable_q_w
&& (write_idx_w == instruction_f[20:16]))
regfile_raw_1_nxt = 1'b1;
else
regfile_raw_1_nxt = 1'b0;
end
/*----------------------------------------------------------------------
Select latched (delayed) write value or data from register file. If
read in previous cycle was performed to register written to in same
cycle, then latched (delayed) write value is selected.
----------------------------------------------------------------------*/
always @(regfile_raw_0 or w_result_d or regfile_data_0)
if (regfile_raw_0)
reg_data_live_0 = w_result_d;
else
reg_data_live_0 = regfile_data_0;
/*----------------------------------------------------------------------
Select latched (delayed) write value or data from register file. If
read in previous cycle was performed to register written to in same
cycle, then latched (delayed) write value is selected.
----------------------------------------------------------------------*/
always @(regfile_raw_1 or w_result_d or regfile_data_1)
if (regfile_raw_1)
reg_data_live_1 = w_result_d;
else
reg_data_live_1 = regfile_data_1;
/*----------------------------------------------------------------------
Latch value written to register file
----------------------------------------------------------------------*/
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
if (rst_i == `TRUE)
begin
regfile_raw_0 <= 1'b0;
regfile_raw_1 <= 1'b0;
w_result_d <= 32'b0;
end
else
begin
regfile_raw_0 <= regfile_raw_0_nxt;
regfile_raw_1 <= regfile_raw_1_nxt;
w_result_d <= w_result;
end
/*----------------------------------------------------------------------
Register file instantiation as Pseudo-Dual Port EBRs.
----------------------------------------------------------------------*/
pmi_ram_dp
#(
// ----- Parameters -----
.pmi_wr_addr_depth(1<<5),
.pmi_wr_addr_width(5),
.pmi_wr_data_width(32),
.pmi_rd_addr_depth(1<<5),
.pmi_rd_addr_width(5),
.pmi_rd_data_width(32),
.pmi_regmode("noreg"),
.pmi_gsr("enable"),
.pmi_resetmode("sync"),
.pmi_init_file("none"),
.pmi_init_file_format("binary"),
.pmi_family(`LATTICE_FAMILY),
.module_type("pmi_ram_dp")
)
reg_0
(
// ----- Inputs -----
.Data(w_result),
.WrAddress(write_idx_w),
.RdAddress(instruction_f[25:21]),
.WrClock(clk_i),
.RdClock(clk_i),
.WrClockEn(`TRUE),
.RdClockEn(`TRUE),
.WE(reg_write_enable_q_w),
.Reset(rst_i),
// ----- Outputs -----
.Q(regfile_data_0)
);
pmi_ram_dp
#(
// ----- Parameters -----
.pmi_wr_addr_depth(1<<5),
.pmi_wr_addr_width(5),
.pmi_wr_data_width(32),
.pmi_rd_addr_depth(1<<5),
.pmi_rd_addr_width(5),
.pmi_rd_data_width(32),
.pmi_regmode("noreg"),
.pmi_gsr("enable"),
.pmi_resetmode("sync"),
.pmi_init_file("none"),
.pmi_init_file_format("binary"),
.pmi_family(`LATTICE_FAMILY),
.module_type("pmi_ram_dp")
)
reg_1
(
// ----- Inputs -----
.Data(w_result),
.WrAddress(write_idx_w),
.RdAddress(instruction_f[20:16]),
.WrClock(clk_i),
.RdClock(clk_i),
.WrClockEn(`TRUE),
.RdClockEn(`TRUE),
.WE(reg_write_enable_q_w),
.Reset(rst_i),
// ----- Outputs -----
.Q(regfile_data_1)
);
`endif
`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
pmi_ram_dp
#(
// ----- Parameters -----
.pmi_wr_addr_depth(1<<5),
.pmi_wr_addr_width(5),
.pmi_wr_data_width(32),
.pmi_rd_addr_depth(1<<5),
.pmi_rd_addr_width(5),
.pmi_rd_data_width(32),
.pmi_regmode("noreg"),
.pmi_gsr("enable"),
.pmi_resetmode("sync"),
.pmi_init_file("none"),
.pmi_init_file_format("binary"),
.pmi_family(`LATTICE_FAMILY),
.module_type("pmi_ram_dp")
)
reg_0
(
// ----- Inputs -----
.Data(w_result),
.WrAddress(write_idx_w),
.RdAddress(read_idx_0_d),
.WrClock(clk_i),
.RdClock(clk_n_i),
.WrClockEn(`TRUE),
.RdClockEn(stall_f == `FALSE),
.WE(reg_write_enable_q_w),
.Reset(rst_i),
// ----- Outputs -----
.Q(reg_data_0)
);
pmi_ram_dp
#(
// ----- Parameters -----
.pmi_wr_addr_depth(1<<5),
.pmi_wr_addr_width(5),
.pmi_wr_data_width(32),
.pmi_rd_addr_depth(1<<5),
.pmi_rd_addr_width(5),
.pmi_rd_data_width(32),
.pmi_regmode("noreg"),
.pmi_gsr("enable"),
.pmi_resetmode("sync"),
.pmi_init_file("none"),
.pmi_init_file_format("binary"),
.pmi_family(`LATTICE_FAMILY),
.module_type("pmi_ram_dp")
)
reg_1
(
// ----- Inputs -----
.Data(w_result),
.WrAddress(write_idx_w),
.RdAddress(read_idx_1_d),
.WrClock(clk_i),
.RdClock(clk_n_i),
.WrClockEn(`TRUE),
.RdClockEn(stall_f == `FALSE),
.WE(reg_write_enable_q_w),
.Reset(rst_i),
// ----- Outputs -----
.Q(reg_data_1)
);
`endif
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
// Select between buffered and live data from register file
assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
`endif
`ifdef LM32_EBR_REGISTER_FILE
`else
// Register file read ports
assign reg_data_0 = registers[read_idx_0_d];
assign reg_data_1 = registers[read_idx_1_d];
`endif
// Detect read-after-write hazzards
assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == `TRUE);
assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == `TRUE);
assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == `TRUE);
assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == `TRUE);
assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == `TRUE);
assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == `TRUE);
// Interlock detection - Raise an interlock for RAW hazzards
always @(*)
begin
if ( ( (x_bypass_enable_x == `FALSE)
&& ( ((read_enable_0_d == `TRUE) && (raw_x_0 == `TRUE))
|| ((read_enable_1_d == `TRUE) && (raw_x_1 == `TRUE))
)
)
|| ( (m_bypass_enable_m == `FALSE)
&& ( ((read_enable_0_d == `TRUE) && (raw_m_0 == `TRUE))
|| ((read_enable_1_d == `TRUE) && (raw_m_1 == `TRUE))
)
)
)
interlock = `TRUE;
else
interlock = `FALSE;
end
// Bypass for reg port 0
always @(*)
begin
if (raw_x_0 == `TRUE)
bypass_data_0 = x_result;
else if (raw_m_0 == `TRUE)
bypass_data_0 = m_result;
else if (raw_w_0 == `TRUE)
bypass_data_0 = w_result;
else
bypass_data_0 = reg_data_0;
end
// Bypass for reg port 1
always @(*)
begin
if (raw_x_1 == `TRUE)
bypass_data_1 = x_result;
else if (raw_m_1 == `TRUE)
bypass_data_1 = m_result;
else if (raw_w_1 == `TRUE)
bypass_data_1 = w_result;
else
bypass_data_1 = reg_data_1;
end
/*----------------------------------------------------------------------
Branch prediction is performed in D stage of pipeline. Only PC-relative
branches are predicted: forward-pointing conditional branches are not-
taken, while backward-pointing conditional branches are taken.
Unconditional branches are always predicted taken!
----------------------------------------------------------------------*/
assign branch_predict_d = bi_unconditional | bi_conditional;
assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
// Compute branch target address: Branch PC PLUS Offset
assign branch_target_d = pc_d + branch_offset_d;
// Compute fetch address. Address of instruction sequentially after the
// branch if branch is not taken. Target address of branch is branch is
// taken
assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
// D stage result selection
always @(*)
begin
d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0;
case (d_result_sel_1_d)
`LM32_D_RESULT_SEL_1_ZERO: d_result_1 = {`LM32_WORD_WIDTH{1'b0}};
`LM32_D_RESULT_SEL_1_REG_1: d_result_1 = bypass_data_1;
`LM32_D_RESULT_SEL_1_IMMEDIATE: d_result_1 = immediate_d;
default: d_result_1 = {`LM32_WORD_WIDTH{1'bx}};
endcase
end
`ifdef CFG_USER_ENABLED
// Operands for user-defined instructions
assign user_operand_0 = operand_0_x;
assign user_operand_1 = operand_1_x;
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
// Sign-extension
assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
assign sext_result_x = size_x == `LM32_SIZE_BYTE ? sextb_result_x : sexth_result_x;
`endif
`ifdef LM32_NO_BARREL_SHIFT
// Only single bit shift operations are supported when barrel-shifter isn't implemented
assign shifter_result_x = {operand_0_x[`LM32_WORD_WIDTH-1] & sign_extend_x, operand_0_x[`LM32_WORD_WIDTH-1:1]};
`endif
// Condition evaluation
assign cmp_zero = operand_0_x == operand_1_x;
assign cmp_negative = adder_result_x[`LM32_WORD_WIDTH-1];
assign cmp_overflow = adder_overflow_x;
assign cmp_carry_n = adder_carry_n_x;
always @(*)
begin
case (condition_x)
`LM32_CONDITION_U1: condition_met_x = `TRUE;
`LM32_CONDITION_U2: condition_met_x = `TRUE;
`LM32_CONDITION_E: condition_met_x = cmp_zero;
`LM32_CONDITION_NE: condition_met_x = !cmp_zero;
`LM32_CONDITION_G: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
`LM32_CONDITION_GU: condition_met_x = cmp_carry_n && !cmp_zero;
`LM32_CONDITION_GE: condition_met_x = cmp_negative == cmp_overflow;
`LM32_CONDITION_GEU: condition_met_x = cmp_carry_n;
default: condition_met_x = 1'bx;
endcase
end
// X stage result selection
always @(*)
begin
x_result = x_result_sel_add_x ? adder_result_x
: x_result_sel_csr_x ? csr_read_data_x
`ifdef CFG_SIGN_EXTEND_ENABLED
: x_result_sel_sext_x ? sext_result_x
`endif
`ifdef CFG_USER_ENABLED
: x_result_sel_user_x ? user_result
`endif
`ifdef LM32_NO_BARREL_SHIFT
: x_result_sel_shift_x ? shifter_result_x
`endif
`ifdef LM32_MC_ARITHMETIC_ENABLED
: x_result_sel_mc_arith_x ? mc_result_x
`endif
: logic_result_x;
end
// M stage result selection
always @(*)
begin
m_result = m_result_sel_compare_m ? {{`LM32_WORD_WIDTH-1{1'b0}}, condition_met_m}
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
: m_result_sel_shift_m ? shifter_result_m
`endif
: operand_m;
end
// W stage result selection
always @(*)
begin
w_result = w_result_sel_load_w ? load_data_w
`ifdef CFG_PL_MULTIPLY_ENABLED
: w_result_sel_mul_w ? multiplier_result_w
`endif
: operand_w;
end
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
// Indicate when a branch should be taken in X stage
assign branch_taken_x = (stall_x == `FALSE)
&& ( (branch_x == `TRUE)
&& ((condition_x == `LM32_CONDITION_U1) || (condition_x == `LM32_CONDITION_U2))
&& (valid_x == `TRUE)
&& (branch_predict_x == `FALSE)
);
`endif
// Indicate when a branch should be taken in M stage (exceptions are a type of branch)
assign branch_taken_m = (stall_m == `FALSE)
&& ( ( (branch_m == `TRUE)
&& (valid_m == `TRUE)
&& ( ( (condition_met_m == `TRUE)
&& (branch_predict_taken_m == `FALSE)
)
|| ( (condition_met_m == `FALSE)
&& (branch_predict_m == `TRUE)
&& (branch_predict_taken_m == `TRUE)
)
)
)
|| (exception_m == `TRUE)
);
// Indicate when a branch in M stage is mispredicted as being taken
assign branch_mispredict_taken_m = (condition_met_m == `FALSE)
&& (branch_predict_m == `TRUE)
&& (branch_predict_taken_m == `TRUE);
// Indicate when a branch in M stage will cause flush in X stage
assign branch_flushX_m = (stall_m == `FALSE)
&& ( ( (branch_m == `TRUE)
&& (valid_m == `TRUE)
&& ( (condition_met_m == `TRUE)
|| ( (condition_met_m == `FALSE)
&& (branch_predict_m == `TRUE)
&& (branch_predict_taken_m == `TRUE)
)
)
)
|| (exception_m == `TRUE)
);
// Generate signal that will kill instructions in each pipeline stage when necessary
assign kill_f = ( (valid_d == `TRUE)
&& (branch_predict_taken_d == `TRUE)
)
|| (branch_taken_m == `TRUE)
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
|| (branch_taken_x == `TRUE)
`endif
`ifdef CFG_ICACHE_ENABLED
|| (icache_refill_request == `TRUE)
`endif
`ifdef CFG_DCACHE_ENABLED
|| (dcache_refill_request == `TRUE)
`endif
;
assign kill_d = (branch_taken_m == `TRUE)
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
|| (branch_taken_x == `TRUE)
`endif
`ifdef CFG_ICACHE_ENABLED
|| (icache_refill_request == `TRUE)
`endif
`ifdef CFG_DCACHE_ENABLED
|| (dcache_refill_request == `TRUE)
`endif
;
assign kill_x = (branch_flushX_m == `TRUE)
`ifdef CFG_DCACHE_ENABLED
|| (dcache_refill_request == `TRUE)
`endif
;
assign kill_m = `FALSE
`ifdef CFG_DCACHE_ENABLED
|| (dcache_refill_request == `TRUE)
`endif
;
assign kill_w = `FALSE
`ifdef CFG_DCACHE_ENABLED
|| (dcache_refill_request == `TRUE)
`endif
;
// Exceptions
`ifdef CFG_DEBUG_ENABLED
assign breakpoint_exception = ( ( (break_x == `TRUE)
|| (bp_match == `TRUE)
)
&& (valid_x == `TRUE)
)
`ifdef CFG_JTAG_ENABLED
|| (jtag_break == `TRUE)
`endif
;
`endif
`ifdef CFG_DEBUG_ENABLED
assign watchpoint_exception = wp_match == `TRUE;
`endif
`ifdef CFG_BUS_ERRORS_ENABLED
assign instruction_bus_error_exception = ( (bus_error_x == `TRUE)
&& (valid_x == `TRUE)
);
assign data_bus_error_exception = data_bus_error_seen == `TRUE;
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
assign divide_by_zero_exception = divide_by_zero_x == `TRUE;
`endif
assign system_call_exception = ( (scall_x == `TRUE)
`ifdef CFG_BUS_ERRORS_ENABLED
&& (valid_x == `TRUE)
`endif
);
`ifdef CFG_DEBUG_ENABLED
assign debug_exception_x = (breakpoint_exception == `TRUE)
|| (watchpoint_exception == `TRUE)
;
assign non_debug_exception_x = (system_call_exception == `TRUE)
`ifdef CFG_JTAG_ENABLED
|| (reset_exception == `TRUE)
`endif
`ifdef CFG_BUS_ERRORS_ENABLED
|| (instruction_bus_error_exception == `TRUE)
|| (data_bus_error_exception == `TRUE)
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
|| (divide_by_zero_exception == `TRUE)
`endif
`ifdef CFG_INTERRUPTS_ENABLED
|| ( (interrupt_exception == `TRUE)
`ifdef LM32_SINGLE_STEP_ENABLED
&& (dc_ss == `FALSE)
`endif
`ifdef CFG_BUS_ERRORS_ENABLED
&& (store_q_m == `FALSE)
&& (D_CYC_O == `FALSE)
`endif
)
`endif
;
assign exception_x = (debug_exception_x == `TRUE) || (non_debug_exception_x == `TRUE);
`else
assign exception_x = (system_call_exception == `TRUE)
`ifdef CFG_BUS_ERRORS_ENABLED
|| (instruction_bus_error_exception == `TRUE)
|| (data_bus_error_exception == `TRUE)
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
|| (divide_by_zero_exception == `TRUE)
`endif
`ifdef CFG_INTERRUPTS_ENABLED
|| ( (interrupt_exception == `TRUE)
`ifdef LM32_SINGLE_STEP_ENABLED
&& (dc_ss == `FALSE)
`endif
`ifdef CFG_BUS_ERRORS_ENABLED
&& (store_q_m == `FALSE)
&& (D_CYC_O == `FALSE)
`endif
)
`endif
;
`endif
// Exception ID
always @(*)
begin
`ifdef CFG_DEBUG_ENABLED
`ifdef CFG_JTAG_ENABLED
if (reset_exception == `TRUE)
eid_x = `LM32_EID_RESET;
else
`endif
`ifdef CFG_BUS_ERRORS_ENABLED
if (data_bus_error_exception == `TRUE)
eid_x = `LM32_EID_DATA_BUS_ERROR;
else
`endif
if (breakpoint_exception == `TRUE)
eid_x = `LM32_EID_BREAKPOINT;
else
`endif
`ifdef CFG_BUS_ERRORS_ENABLED
if (data_bus_error_exception == `TRUE)
eid_x = `LM32_EID_DATA_BUS_ERROR;
else
if (instruction_bus_error_exception == `TRUE)
eid_x = `LM32_EID_INST_BUS_ERROR;
else
`endif
`ifdef CFG_DEBUG_ENABLED
if (watchpoint_exception == `TRUE)
eid_x = `LM32_EID_WATCHPOINT;
else
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
if (divide_by_zero_exception == `TRUE)
eid_x = `LM32_EID_DIVIDE_BY_ZERO;
else
`endif
`ifdef CFG_INTERRUPTS_ENABLED
if ( (interrupt_exception == `TRUE)
`ifdef LM32_SINGLE_STEP_ENABLED
&& (dc_ss == `FALSE)
`endif
)
eid_x = `LM32_EID_INTERRUPT;
else
`endif
eid_x = `LM32_EID_SCALL;
end
// Stall generation
assign stall_a = (stall_f == `TRUE);
assign stall_f = (stall_d == `TRUE);
assign stall_d = (stall_x == `TRUE)
|| ( (interlock == `TRUE)
&& (kill_d == `FALSE)
)
|| ( ( (eret_d == `TRUE)
|| (scall_d == `TRUE)
|| (bus_error_d == `TRUE)
)
&& ( (load_q_x == `TRUE)
|| (load_q_m == `TRUE)
|| (store_q_x == `TRUE)
|| (store_q_m == `TRUE)
|| (D_CYC_O == `TRUE)
)
&& (kill_d == `FALSE)
)
`ifdef CFG_DEBUG_ENABLED
|| ( ( (break_d == `TRUE)
|| (bret_d == `TRUE)
)
&& ( (load_q_x == `TRUE)
|| (store_q_x == `TRUE)
|| (load_q_m == `TRUE)
|| (store_q_m == `TRUE)
|| (D_CYC_O == `TRUE)
)
&& (kill_d == `FALSE)
)
`endif
|| ( (csr_write_enable_d == `TRUE)
&& (load_q_x == `TRUE)
)
;
assign stall_x = (stall_m == `TRUE)
`ifdef LM32_MC_ARITHMETIC_ENABLED
|| ( (mc_stall_request_x == `TRUE)
&& (kill_x == `FALSE)
)
`endif
`ifdef CFG_IROM_ENABLED
// Stall load/store instruction in D stage if there is an ongoing store
// operation to instruction ROM in M stage
|| ( (irom_stall_request_x == `TRUE)
&& ( (load_d == `TRUE)
|| (store_d == `TRUE)
)
)
`endif
;
assign stall_m = (stall_wb_load == `TRUE)
`ifdef CFG_SIZE_OVER_SPEED
|| (D_CYC_O == `TRUE)
`else
|| ( (D_CYC_O == `TRUE)
&& ( (store_m == `TRUE)
/*
Bug: Following loop does not allow interrupts to be services since
either D_CYC_O or store_m is always high during entire duration of
loop.
L1: addi r1, r1, 1
sw (r2,0), r1
bi L1
Introduce a single-cycle stall when a wishbone cycle is in progress
and a new store instruction is in Execute stage and a interrupt
exception has occured. This stall will ensure that D_CYC_O and
store_m will both be low for one cycle.
*/
|| ((store_x == `TRUE) && (interrupt_exception == `TRUE))
|| (load_m == `TRUE)
|| (load_x == `TRUE)
)
)
`endif
`ifdef CFG_DCACHE_ENABLED
|| (dcache_stall_request == `TRUE) // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted
`endif
`ifdef CFG_ICACHE_ENABLED
|| (icache_stall_request == `TRUE) // Pipeline needs to be stalled otherwise branches may be lost
|| ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) || (exception_m == `TRUE)))
`else
`ifdef CFG_IWB_ENABLED
|| (I_CYC_O == `TRUE)
`endif
`endif
`ifdef CFG_USER_ENABLED
|| ( (user_valid == `TRUE) // Stall whole pipeline, rather than just X stage, where the instruction is, so we don't have to worry about exceptions (maybe)
&& (user_complete == `FALSE)
)
`endif
;
// Qualify state changing control signals
`ifdef LM32_MC_ARITHMETIC_ENABLED
assign q_d = (valid_d == `TRUE) && (kill_d == `FALSE);
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
assign shift_left_q_d = (shift_left_d == `TRUE) && (q_d == `TRUE);
assign shift_right_q_d = (shift_right_d == `TRUE) && (q_d == `TRUE);
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
assign multiply_q_d = (multiply_d == `TRUE) && (q_d == `TRUE);
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
assign divide_q_d = (divide_d == `TRUE) && (q_d == `TRUE);
assign modulus_q_d = (modulus_d == `TRUE) && (q_d == `TRUE);
`endif
assign q_x = (valid_x == `TRUE) && (kill_x == `FALSE);
assign csr_write_enable_q_x = (csr_write_enable_x == `TRUE) && (q_x == `TRUE);
assign eret_q_x = (eret_x == `TRUE) && (q_x == `TRUE);
`ifdef CFG_DEBUG_ENABLED
assign bret_q_x = (bret_x == `TRUE) && (q_x == `TRUE);
`endif
assign load_q_x = (load_x == `TRUE)
&& (q_x == `TRUE)
`ifdef CFG_DEBUG_ENABLED
&& (bp_match == `FALSE)
`endif
;
assign store_q_x = (store_x == `TRUE)
&& (q_x == `TRUE)
`ifdef CFG_DEBUG_ENABLED
&& (bp_match == `FALSE)
`endif
;
`ifdef CFG_USER_ENABLED
assign user_valid = (x_result_sel_user_x == `TRUE) && (q_x == `TRUE);
`endif
assign q_m = (valid_m == `TRUE) && (kill_m == `FALSE) && (exception_m == `FALSE);
assign load_q_m = (load_m == `TRUE) && (q_m == `TRUE);
assign store_q_m = (store_m == `TRUE) && (q_m == `TRUE);
`ifdef CFG_DEBUG_ENABLED
assign debug_exception_q_w = ((debug_exception_w == `TRUE) && (valid_w == `TRUE));
assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE));
`else
assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE));
`endif
// Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately)
assign write_enable_q_x = (write_enable_x == `TRUE) && (valid_x == `TRUE) && (branch_flushX_m == `FALSE);
assign write_enable_q_m = (write_enable_m == `TRUE) && (valid_m == `TRUE);
assign write_enable_q_w = (write_enable_w == `TRUE) && (valid_w == `TRUE);
// The enable that actually does write the registers needs to be qualified with kill
assign reg_write_enable_q_w = (write_enable_w == `TRUE) && (kill_w == `FALSE) && (valid_w == `TRUE);
// Configuration (CFG) CSR
assign cfg = {
`LM32_REVISION,
watchpoints[3:0],
breakpoints[3:0],
interrupts[5:0],
`ifdef CFG_JTAG_UART_ENABLED
`TRUE,
`else
`FALSE,
`endif
`ifdef CFG_ROM_DEBUG_ENABLED
`TRUE,
`else
`FALSE,
`endif
`ifdef CFG_HW_DEBUG_ENABLED
`TRUE,
`else
`FALSE,
`endif
`ifdef CFG_DEBUG_ENABLED
`TRUE,
`else
`FALSE,
`endif
`ifdef CFG_ICACHE_ENABLED
`TRUE,
`else
`FALSE,
`endif
`ifdef CFG_DCACHE_ENABLED
`TRUE,
`else
`FALSE,
`endif
`ifdef CFG_CYCLE_COUNTER_ENABLED
`TRUE,
`else
`FALSE,
`endif
`ifdef CFG_USER_ENABLED
`TRUE,
`else
`FALSE,
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
`TRUE,
`else
`FALSE,
`endif
`ifdef LM32_BARREL_SHIFT_ENABLED
`TRUE,
`else
`FALSE,
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
`TRUE,
`else
`FALSE,
`endif
`ifdef LM32_MULTIPLY_ENABLED
`TRUE
`else
`FALSE
`endif
};
assign cfg2 = {
30'b0,
`ifdef CFG_IROM_ENABLED
`TRUE,
`else
`FALSE,
`endif
`ifdef CFG_DRAM_ENABLED
`TRUE
`else
`FALSE
`endif
};
// Cache flush
`ifdef CFG_ICACHE_ENABLED
assign iflush = (csr_write_enable_d == `TRUE)
&& (csr_d == `LM32_CSR_ICC)
&& (stall_d == `FALSE)
&& (kill_d == `FALSE)
&& (valid_d == `TRUE);
`endif
`ifdef CFG_DCACHE_ENABLED
assign dflush_x = (csr_write_enable_q_x == `TRUE)
&& (csr_x == `LM32_CSR_DCC);
`endif
// Extract CSR index
assign csr_d = read_idx_0_d[`LM32_CSR_RNG];
// CSR reads
always @(*)
begin
case (csr_x)
`ifdef CFG_INTERRUPTS_ENABLED
`LM32_CSR_IE,
`LM32_CSR_IM,
`LM32_CSR_IP: csr_read_data_x = interrupt_csr_read_data_x;
`endif
`ifdef CFG_CYCLE_COUNTER_ENABLED
`LM32_CSR_CC: csr_read_data_x = cc;
`endif
`LM32_CSR_CFG: csr_read_data_x = cfg;
`LM32_CSR_EBA: csr_read_data_x = {eba, 8'h00};
`ifdef CFG_DEBUG_ENABLED
`LM32_CSR_DEBA: csr_read_data_x = {deba, 8'h00};
`endif
`ifdef CFG_JTAG_UART_ENABLED
`LM32_CSR_JTX: csr_read_data_x = jtx_csr_read_data;
`LM32_CSR_JRX: csr_read_data_x = jrx_csr_read_data;
`endif
`LM32_CSR_CFG2: csr_read_data_x = cfg2;
default: csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
endcase
end
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
// Exception Base Address (EBA) CSR
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
eba <= eba_reset[`LM32_PC_WIDTH+2-1:8];
else
begin
if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE))
eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
`ifdef CFG_HW_DEBUG_ENABLED
if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA))
eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
`endif
end
end
`ifdef CFG_DEBUG_ENABLED
// Debug Exception Base Address (DEBA) CSR
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
deba <= deba_reset[`LM32_PC_WIDTH+2-1:8];
else
begin
if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE))
deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
`ifdef CFG_HW_DEBUG_ENABLED
if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA))
deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
`endif
end
end
`endif
// Cycle Counter (CC) CSR
`ifdef CFG_CYCLE_COUNTER_ENABLED
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
cc <= {`LM32_WORD_WIDTH{1'b0}};
else
cc <= cc + 1'b1;
end
`endif
`ifdef CFG_BUS_ERRORS_ENABLED
// Watch for data bus errors
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
data_bus_error_seen <= `FALSE;
else
begin
// Set flag when bus error is detected
if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE))
data_bus_error_seen <= `TRUE;
// Clear flag when exception is taken
if ((exception_m == `TRUE) && (kill_m == `FALSE))
data_bus_error_seen <= `FALSE;
end
end
`endif
// Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not
`ifdef CFG_ICACHE_ENABLED
`ifdef CFG_DCACHE_ENABLED
always @(*)
begin
if ( (icache_refill_request == `TRUE)
|| (dcache_refill_request == `TRUE)
)
valid_a = `FALSE;
else if ( (icache_restart_request == `TRUE)
|| (dcache_restart_request == `TRUE)
)
valid_a = `TRUE;
else
valid_a = !icache_refilling && !dcache_refilling;
end
`else
always @(*)
begin
if (icache_refill_request == `TRUE)
valid_a = `FALSE;
else if (icache_restart_request == `TRUE)
valid_a = `TRUE;
else
valid_a = !icache_refilling;
end
`endif
`else
`ifdef CFG_DCACHE_ENABLED
always @(*)
begin
if (dcache_refill_request == `TRUE)
valid_a = `FALSE;
else if (dcache_restart_request == `TRUE)
valid_a = `TRUE;
else
valid_a = !dcache_refilling;
end
`endif
`endif
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
valid_f <= `FALSE;
valid_d <= `FALSE;
valid_x <= `FALSE;
valid_m <= `FALSE;
valid_w <= `FALSE;
end
else
begin
if ((kill_f == `TRUE) || (stall_a == `FALSE))
`ifdef LM32_CACHE_ENABLED
valid_f <= valid_a;
`else
valid_f <= `TRUE;
`endif
else if (stall_f == `FALSE)
valid_f <= `FALSE;
if (kill_d == `TRUE)
valid_d <= `FALSE;
else if (stall_f == `FALSE)
valid_d <= valid_f & !kill_f;
else if (stall_d == `FALSE)
valid_d <= `FALSE;
if (stall_d == `FALSE)
valid_x <= valid_d & !kill_d;
else if (kill_x == `TRUE)
valid_x <= `FALSE;
else if (stall_x == `FALSE)
valid_x <= `FALSE;
if (kill_m == `TRUE)
valid_m <= `FALSE;
else if (stall_x == `FALSE)
valid_m <= valid_x & !kill_x;
else if (stall_m == `FALSE)
valid_m <= `FALSE;
if (stall_m == `FALSE)
valid_w <= valid_m & !kill_m;
else
valid_w <= `FALSE;
end
end
// Microcode pipeline registers
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
`ifdef CFG_USER_ENABLED
user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}};
`endif
operand_0_x <= {`LM32_WORD_WIDTH{1'b0}};
operand_1_x <= {`LM32_WORD_WIDTH{1'b0}};
store_operand_x <= {`LM32_WORD_WIDTH{1'b0}};
branch_target_x <= {`LM32_WORD_WIDTH{1'b0}};
x_result_sel_csr_x <= `FALSE;
`ifdef LM32_MC_ARITHMETIC_ENABLED
x_result_sel_mc_arith_x <= `FALSE;
`endif
`ifdef LM32_NO_BARREL_SHIFT
x_result_sel_shift_x <= `FALSE;
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
x_result_sel_sext_x <= `FALSE;
`endif
x_result_sel_logic_x <= `FALSE;
`ifdef CFG_USER_ENABLED
x_result_sel_user_x <= `FALSE;
`endif
x_result_sel_add_x <= `FALSE;
m_result_sel_compare_x <= `FALSE;
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
m_result_sel_shift_x <= `FALSE;
`endif
w_result_sel_load_x <= `FALSE;
`ifdef CFG_PL_MULTIPLY_ENABLED
w_result_sel_mul_x <= `FALSE;
`endif
x_bypass_enable_x <= `FALSE;
m_bypass_enable_x <= `FALSE;
write_enable_x <= `FALSE;
write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}};
csr_x <= {`LM32_CSR_WIDTH{1'b0}};
load_x <= `FALSE;
store_x <= `FALSE;
size_x <= {`LM32_SIZE_WIDTH{1'b0}};
sign_extend_x <= `FALSE;
adder_op_x <= `FALSE;
adder_op_x_n <= `FALSE;
logic_op_x <= 4'h0;
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
direction_x <= `FALSE;
`endif
`ifdef CFG_ROTATE_ENABLED
rotate_x <= `FALSE;
`endif
branch_x <= `FALSE;
branch_predict_x <= `FALSE;
branch_predict_taken_x <= `FALSE;
condition_x <= `LM32_CONDITION_U1;
`ifdef CFG_DEBUG_ENABLED
break_x <= `FALSE;
`endif
scall_x <= `FALSE;
eret_x <= `FALSE;
`ifdef CFG_DEBUG_ENABLED
bret_x <= `FALSE;
`endif
`ifdef CFG_BUS_ERRORS_ENABLED
bus_error_x <= `FALSE;
data_bus_error_exception_m <= `FALSE;
`endif
csr_write_enable_x <= `FALSE;
operand_m <= {`LM32_WORD_WIDTH{1'b0}};
branch_target_m <= {`LM32_WORD_WIDTH{1'b0}};
m_result_sel_compare_m <= `FALSE;
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
m_result_sel_shift_m <= `FALSE;
`endif
w_result_sel_load_m <= `FALSE;
`ifdef CFG_PL_MULTIPLY_ENABLED
w_result_sel_mul_m <= `FALSE;
`endif
m_bypass_enable_m <= `FALSE;
branch_m <= `FALSE;
branch_predict_m <= `FALSE;
branch_predict_taken_m <= `FALSE;
exception_m <= `FALSE;
load_m <= `FALSE;
store_m <= `FALSE;
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
direction_m <= `FALSE;
`endif
write_enable_m <= `FALSE;
write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}};
condition_met_m <= `FALSE;
`ifdef CFG_DCACHE_ENABLED
dflush_m <= `FALSE;
`endif
`ifdef CFG_DEBUG_ENABLED
debug_exception_m <= `FALSE;
non_debug_exception_m <= `FALSE;
`endif
operand_w <= {`LM32_WORD_WIDTH{1'b0}};
w_result_sel_load_w <= `FALSE;
`ifdef CFG_PL_MULTIPLY_ENABLED
w_result_sel_mul_w <= `FALSE;
`endif
write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}};
write_enable_w <= `FALSE;
`ifdef CFG_DEBUG_ENABLED
debug_exception_w <= `FALSE;
non_debug_exception_w <= `FALSE;
`else
exception_w <= `FALSE;
`endif
`ifdef CFG_BUS_ERRORS_ENABLED
memop_pc_w <= {`LM32_PC_WIDTH{1'b0}};
`endif
end
else
begin
// D/X stage registers
if (stall_x == `FALSE)
begin
`ifdef CFG_USER_ENABLED
user_opcode <= user_opcode_d;
`endif
operand_0_x <= d_result_0;
operand_1_x <= d_result_1;
store_operand_x <= bypass_data_1;
branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d;
x_result_sel_csr_x <= x_result_sel_csr_d;
`ifdef LM32_MC_ARITHMETIC_ENABLED
x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
`endif
`ifdef LM32_NO_BARREL_SHIFT
x_result_sel_shift_x <= x_result_sel_shift_d;
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
x_result_sel_sext_x <= x_result_sel_sext_d;
`endif
x_result_sel_logic_x <= x_result_sel_logic_d;
`ifdef CFG_USER_ENABLED
x_result_sel_user_x <= x_result_sel_user_d;
`endif
x_result_sel_add_x <= x_result_sel_add_d;
m_result_sel_compare_x <= m_result_sel_compare_d;
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
m_result_sel_shift_x <= m_result_sel_shift_d;
`endif
w_result_sel_load_x <= w_result_sel_load_d;
`ifdef CFG_PL_MULTIPLY_ENABLED
w_result_sel_mul_x <= w_result_sel_mul_d;
`endif
x_bypass_enable_x <= x_bypass_enable_d;
m_bypass_enable_x <= m_bypass_enable_d;
load_x <= load_d;
store_x <= store_d;
branch_x <= branch_d;
branch_predict_x <= branch_predict_d;
branch_predict_taken_x <= branch_predict_taken_d;
write_idx_x <= write_idx_d;
csr_x <= csr_d;
size_x <= size_d;
sign_extend_x <= sign_extend_d;
adder_op_x <= adder_op_d;
adder_op_x_n <= ~adder_op_d;
logic_op_x <= logic_op_d;
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
direction_x <= direction_d;
`endif
`ifdef CFG_ROTATE_ENABLED
rotate_x <= rotate_d;
`endif
condition_x <= condition_d;
csr_write_enable_x <= csr_write_enable_d;
`ifdef CFG_DEBUG_ENABLED
break_x <= break_d;
`endif
scall_x <= scall_d;
`ifdef CFG_BUS_ERRORS_ENABLED
bus_error_x <= bus_error_d;
`endif
eret_x <= eret_d;
`ifdef CFG_DEBUG_ENABLED
bret_x <= bret_d;
`endif
write_enable_x <= write_enable_d;
end
// X/M stage registers
if (stall_m == `FALSE)
begin
operand_m <= x_result;
m_result_sel_compare_m <= m_result_sel_compare_x;
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
m_result_sel_shift_m <= m_result_sel_shift_x;
`endif
if (exception_x == `TRUE)
begin
w_result_sel_load_m <= `FALSE;
`ifdef CFG_PL_MULTIPLY_ENABLED
w_result_sel_mul_m <= `FALSE;
`endif
end
else
begin
w_result_sel_load_m <= w_result_sel_load_x;
`ifdef CFG_PL_MULTIPLY_ENABLED
w_result_sel_mul_m <= w_result_sel_mul_x;
`endif
end
m_bypass_enable_m <= m_bypass_enable_x;
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
direction_m <= direction_x;
`endif
load_m <= load_x;
store_m <= store_x;
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
branch_m <= branch_x && !branch_taken_x;
`else
branch_m <= branch_x;
branch_predict_m <= branch_predict_x;
branch_predict_taken_m <= branch_predict_taken_x;
`endif
`ifdef CFG_DEBUG_ENABLED
// Data bus errors are generated by the wishbone and are
// made known to the processor only in next cycle (as a
// non-debug exception). A break instruction can be seen
// in same cycle (causing a debug exception). Handle non
// -debug exception first!
if (non_debug_exception_x == `TRUE)
write_idx_m <= `LM32_EA_REG;
else if (debug_exception_x == `TRUE)
write_idx_m <= `LM32_BA_REG;
else
write_idx_m <= write_idx_x;
`else
if (exception_x == `TRUE)
write_idx_m <= `LM32_EA_REG;
else
write_idx_m <= write_idx_x;
`endif
condition_met_m <= condition_met_x;
`ifdef CFG_DEBUG_ENABLED
if (exception_x == `TRUE)
if ((dc_re == `TRUE)
|| ((debug_exception_x == `TRUE)
&& (non_debug_exception_x == `FALSE)))
branch_target_m <= {deba, eid_x, {3{1'b0}}};
else
branch_target_m <= {eba, eid_x, {3{1'b0}}};
else
branch_target_m <= branch_target_x;
`else
branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
`endif
`ifdef CFG_TRACE_ENABLED
eid_m <= eid_x;
`endif
`ifdef CFG_DCACHE_ENABLED
dflush_m <= dflush_x;
`endif
eret_m <= eret_q_x;
`ifdef CFG_DEBUG_ENABLED
bret_m <= bret_q_x;
`endif
write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x;
`ifdef CFG_DEBUG_ENABLED
debug_exception_m <= debug_exception_x;
non_debug_exception_m <= non_debug_exception_x;
`endif
end
// State changing regs
if (stall_m == `FALSE)
begin
if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
exception_m <= `TRUE;
else
exception_m <= `FALSE;
`ifdef CFG_BUS_ERRORS_ENABLED
data_bus_error_exception_m <= (data_bus_error_exception == `TRUE)
`ifdef CFG_DEBUG_ENABLED
&& (reset_exception == `FALSE)
`endif
;
`endif
end
// M/W stage registers
`ifdef CFG_BUS_ERRORS_ENABLED
operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
`else
operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result;
`endif
w_result_sel_load_w <= w_result_sel_load_m;
`ifdef CFG_PL_MULTIPLY_ENABLED
w_result_sel_mul_w <= w_result_sel_mul_m;
`endif
write_idx_w <= write_idx_m;
`ifdef CFG_TRACE_ENABLED
eid_w <= eid_m;
eret_w <= eret_m;
`ifdef CFG_DEBUG_ENABLED
bret_w <= bret_m;
`endif
`endif
write_enable_w <= write_enable_m;
`ifdef CFG_DEBUG_ENABLED
debug_exception_w <= debug_exception_m;
non_debug_exception_w <= non_debug_exception_m;
`else
exception_w <= exception_m;
`endif
`ifdef CFG_BUS_ERRORS_ENABLED
if ( (stall_m == `FALSE)
&& ( (load_q_m == `TRUE)
|| (store_q_m == `TRUE)
)
)
memop_pc_w <= pc_m;
`endif
end
end
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
// Buffer data read from register file, in case a stall occurs, and watch for
// any writes to the modified registers
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
use_buf <= `FALSE;
reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}};
reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}};
end
else
begin
if (stall_d == `FALSE)
use_buf <= `FALSE;
else if (use_buf == `FALSE)
begin
reg_data_buf_0 <= reg_data_live_0;
reg_data_buf_1 <= reg_data_live_1;
use_buf <= `TRUE;
end
if (reg_write_enable_q_w == `TRUE)
begin
if (write_idx_w == read_idx_0_d)
reg_data_buf_0 <= w_result;
if (write_idx_w == read_idx_1_d)
reg_data_buf_1 <= w_result;
end
end
end
`endif
`ifdef LM32_EBR_REGISTER_FILE
`else
// Register file write port
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE) begin
registers[0] <= {`LM32_WORD_WIDTH{1'b0}};
registers[1] <= {`LM32_WORD_WIDTH{1'b0}};
registers[2] <= {`LM32_WORD_WIDTH{1'b0}};
registers[3] <= {`LM32_WORD_WIDTH{1'b0}};
registers[4] <= {`LM32_WORD_WIDTH{1'b0}};
registers[5] <= {`LM32_WORD_WIDTH{1'b0}};
registers[6] <= {`LM32_WORD_WIDTH{1'b0}};
registers[7] <= {`LM32_WORD_WIDTH{1'b0}};
registers[8] <= {`LM32_WORD_WIDTH{1'b0}};
registers[9] <= {`LM32_WORD_WIDTH{1'b0}};
registers[10] <= {`LM32_WORD_WIDTH{1'b0}};
registers[11] <= {`LM32_WORD_WIDTH{1'b0}};
registers[12] <= {`LM32_WORD_WIDTH{1'b0}};
registers[13] <= {`LM32_WORD_WIDTH{1'b0}};
registers[14] <= {`LM32_WORD_WIDTH{1'b0}};
registers[15] <= {`LM32_WORD_WIDTH{1'b0}};
registers[16] <= {`LM32_WORD_WIDTH{1'b0}};
registers[17] <= {`LM32_WORD_WIDTH{1'b0}};
registers[18] <= {`LM32_WORD_WIDTH{1'b0}};
registers[19] <= {`LM32_WORD_WIDTH{1'b0}};
registers[20] <= {`LM32_WORD_WIDTH{1'b0}};
registers[21] <= {`LM32_WORD_WIDTH{1'b0}};
registers[22] <= {`LM32_WORD_WIDTH{1'b0}};
registers[23] <= {`LM32_WORD_WIDTH{1'b0}};
registers[24] <= {`LM32_WORD_WIDTH{1'b0}};
registers[25] <= {`LM32_WORD_WIDTH{1'b0}};
registers[26] <= {`LM32_WORD_WIDTH{1'b0}};
registers[27] <= {`LM32_WORD_WIDTH{1'b0}};
registers[28] <= {`LM32_WORD_WIDTH{1'b0}};
registers[29] <= {`LM32_WORD_WIDTH{1'b0}};
registers[30] <= {`LM32_WORD_WIDTH{1'b0}};
registers[31] <= {`LM32_WORD_WIDTH{1'b0}};
end
else begin
if (reg_write_enable_q_w == `TRUE)
registers[write_idx_w] <= w_result;
end
end
`endif
`ifdef CFG_TRACE_ENABLED
// PC tracing logic
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
trace_pc_valid <= `FALSE;
trace_pc <= {`LM32_PC_WIDTH{1'b0}};
trace_exception <= `FALSE;
trace_eid <= `LM32_EID_RESET;
trace_eret <= `FALSE;
`ifdef CFG_DEBUG_ENABLED
trace_bret <= `FALSE;
`endif
pc_c <= `CFG_EBA_RESET/4;
end
else
begin
trace_pc_valid <= `FALSE;
// Has an exception occured
`ifdef CFG_DEBUG_ENABLED
if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE))
`else
if (exception_q_w == `TRUE)
`endif
begin
trace_exception <= `TRUE;
trace_pc_valid <= `TRUE;
trace_pc <= pc_w;
trace_eid <= eid_w;
end
else
trace_exception <= `FALSE;
if ((valid_w == `TRUE) && (!kill_w))
begin
// An instruction is commiting. Determine if it is non-sequential
if (pc_c + 1'b1 != pc_w)
begin
// Non-sequential instruction
trace_pc_valid <= `TRUE;
trace_pc <= pc_w;
end
// Record PC so we can determine if next instruction is sequential or not
pc_c <= pc_w;
// Indicate if it was an eret/bret instruction
trace_eret <= eret_w;
`ifdef CFG_DEBUG_ENABLED
trace_bret <= bret_w;
`endif
end
else
begin
trace_eret <= `FALSE;
`ifdef CFG_DEBUG_ENABLED
trace_bret <= `FALSE;
`endif
end
end
end
`endif
/////////////////////////////////////////////////////
// Behavioural Logic
/////////////////////////////////////////////////////
// synthesis translate_off
// Reset register 0. Only needed for simulation.
initial
begin
`ifdef LM32_EBR_REGISTER_FILE
reg_0.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
reg_1.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
`else
registers[0] = {`LM32_WORD_WIDTH{1'b0}};
`endif
end
// synthesis translate_on
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_arb_wr_4.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 4 write requests from 4 ports.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_arb_wr_4(
rstn,
sw_clk,
qos1,
qos2,
qos3,
qos4,
prt_dv1,
prt_dv2,
prt_dv3,
prt_dv4,
prt_data1,
prt_data2,
prt_data3,
prt_data4,
prt_addr1,
prt_addr2,
prt_addr3,
prt_addr4,
prt_bytes1,
prt_bytes2,
prt_bytes3,
prt_bytes4,
prt_ack1,
prt_ack2,
prt_ack3,
prt_ack4,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_ack
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
input [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
input prt_dv1, prt_dv2,prt_dv3, prt_dv4, prt_ack;
output reg prt_ack1,prt_ack2,prt_ack3,prt_ack4,prt_req;
output reg [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 4'b100,wait_ack_low = 3'b101;
reg [2:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
prt_req = 0;
if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
serv_req1:begin
state = serv_req1;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack1 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv2) begin
state = serv_req2;
prt_qos = qos2;
prt_req = 1;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
end
serv_req2:begin
state = serv_req2;
prt_ack1 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack2 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv3) begin
state = serv_req3;
prt_qos = qos3;
prt_req = 1;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
state = serv_req4;
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_dv1) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req3:begin
state = serv_req3;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack3 = 1'b1;
// state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv4) begin
state = serv_req4;
prt_qos = qos4;
prt_req = 1;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end
end
end
serv_req4:begin
state = serv_req4;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
if(prt_ack)begin
prt_ack4 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
state = serv_req3;
end
end
end
wait_ack_low:begin
state = wait_ack_low;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(!prt_ack)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_sync_flops.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver logic ////
//// ////
//// Known problems (limits): ////
//// None known ////
//// ////
//// To Do: ////
//// Thourough testing. ////
//// ////
//// Author(s): ////
//// - Andrej Erzen ([email protected]) ////
//// - Tadej Markovic ([email protected]) ////
//// ////
//// Created: 2004/05/20 ////
//// Last Updated: 2004/05/20 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_sync_flops.v.rca $
//
// Revision: 1.1.1.1 Tue Jun 7 09:39:01 2011 copew1
// first stab at merging s0903a branch.
//
// Revision: 1.1 Fri Jun 3 12:44:14 2011 tractp1
// UART in test bench to send/receive ASCII bytes with FPGA UART and
// command processing task in firmware
//
`include "timescale.v"
module uart_sync_flops
(
// internal signals
rst_i,
clk_i,
stage1_rst_i,
stage1_clk_en_i,
async_dat_i,
sync_dat_o
);
parameter Tp = 1;
parameter width = 1;
parameter init_value = 1'b0;
input rst_i; // reset input
input clk_i; // clock input
input stage1_rst_i; // synchronous reset for stage 1 FF
input stage1_clk_en_i; // synchronous clock enable for stage 1 FF
input [width-1:0] async_dat_i; // asynchronous data input
output [width-1:0] sync_dat_o; // synchronous data output
//
// Interal signal declarations
//
reg [width-1:0] sync_dat_o;
reg [width-1:0] flop_0;
// first stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
flop_0 <= #Tp {width{init_value}};
else
flop_0 <= #Tp async_dat_i;
end
// second stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
sync_dat_o <= #Tp {width{init_value}};
else if (stage1_rst_i)
sync_dat_o <= #Tp {width{init_value}};
else if (stage1_clk_en_i)
sync_dat_o <= #Tp flop_0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EINVP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__EINVP_PP_BLACKBOX_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__einvp (
A ,
TE ,
Z ,
VPWR,
VGND
);
input A ;
input TE ;
output Z ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EINVP_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
/*
-- Module Name: Control Path
-- Description: Modulo top level para el camino de control de un router.
Instancia a los modulos 'control de enlace' y
'planificador de salida'.
Ademas de los modulos mencionados, en este archivo se
encuentra el desglose necesario de señales y la
interconexion de los modulos.
-- Dependencies: -- system.vh
-- link_controller.v x 4
-- outport_scheduler.v x 4
-- Parameters: -- X_LOCAL: Direccion en dimension "x" del nodo
en la red.
-- Y_LOCAL: Direccion en dimension "y" del nodo
en la red.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas: ** Esta pendiente arreglar los indices de las señales
'input_channel_xxxx_din' y 'buffer_xxxx_din'
-- History:
-- 05 de Junio 2015: Creacion
-- 10 de Junio 2015: * actualizacion de instancia de link
controllers.
* se agregan puerto para recibir el campo
'destino' del flit de cabecera desde las
colas de almacenamiento temporal del
datapath
*/
`include "system.vh"
module control_path #(
parameter X_LOCAL = 2,
parameter Y_LOCAL = 2,
parameter X_WIDTH = 2,
parameter Y_WIDTH = 2
)
(
input wire clk,
input wire reset,
// -- segmentos de puertos de entrada ------------------------ >>>>>
output wire credit_out_xpos_dout,
input wire [31:24] input_channel_xpos_din,
input wire [29:24] buffer_xpos_din,
input wire done_buffer_xpos_din,
output wire credit_out_ypos_dout,
input wire [31:24] input_channel_ypos_din,
input wire [29:24] buffer_ypos_din,
input wire done_buffer_ypos_din,
output wire credit_out_xneg_dout,
input wire [31:24] input_channel_xneg_din,
input wire [29:24] buffer_xneg_din,
input wire done_buffer_xneg_din,
output wire credit_out_yneg_dout,
input wire [31:24] input_channel_yneg_din,
input wire [29:24] buffer_yneg_din,
input wire done_buffer_yneg_din,
output wire credit_out_pe_dout,
input wire [31:24] input_channel_pe_din,
input wire [29:24] buffer_pe_din,
input wire done_buffer_pe_din,
// -- puertos de recepcion de creditos ----------------------- >>>>>
input wire credit_in_xpos_din,
input wire credit_in_ypos_din,
input wire credit_in_xneg_din,
input wire credit_in_yneg_din,
input wire credit_in_pe_din,
// -- señales de salida a camino de datos -------------------- >>>>>
output wire [4:0] write_strobe_dout,
output wire [4:0] read_strobe_dout,
output wire [3:0] xbar_conf_vector_xpos_dout,
output wire [3:0] xbar_conf_vector_ypos_dout,
output wire [3:0] xbar_conf_vector_xneg_dout,
output wire [3:0] xbar_conf_vector_yneg_dout,
output wire [3:0] xbar_conf_vector_pe_dout
);
// -- Parametros locales ----------------------------------------- >>>>>
localparam X_ADDR = clog2(X_WIDTH);
localparam Y_ADDR = clog2(Y_WIDTH);
/*
-- Instancia :: Controladores de Enlace
-- Descripcion: Modulo para la administracion de paquetes entrando al
router. Se encarga de la recepcion de paquetes,
solicitud del uso de un puerto de salida y de la
transferencia de paquetes recibidos al puerto de salida
destino.
Cada instancia de este modulo esta ligada a un puerto
de entrada y a una cola de almacenamiento.
La negociacion de recursos se lleva a cabo con los
modulos "planificador de salida".
*/
// -- Link Controllers ------------------------------------------- >>>>>
/*
-- Las señales son agrupadas en vectores para poder hacer el enlace
entre puertos dentro de los ciclos Generate.
*/
// -- Desglose de Señales ------------------------------------ >>>>>
// -- Entrada :: Campo header de Flit de Cabecera -------- >>>>>
wire [4:0] header_field;
assign header_field[`X_POS] = input_channel_xpos_din[31];
assign header_field[`Y_POS] = input_channel_ypos_din[31];
assign header_field[`X_NEG] = input_channel_xneg_din[31];
assign header_field[`Y_NEG] = input_channel_yneg_din[31];
assign header_field[`PE] = input_channel_pe_din [31];
// -- Entrada :: Campo done de Flit de Cabecera ---------- >>>>>
wire [4:0] done_field;
assign done_field[`X_POS] = input_channel_xpos_din[30];
assign done_field[`Y_POS] = input_channel_ypos_din[30];
assign done_field[`X_NEG] = input_channel_xneg_din[30];
assign done_field[`Y_NEG] = input_channel_yneg_din[30];
assign done_field[`PE] = input_channel_pe_din [30];
// -- Entrada :: Campo done desde Buffer ----------------- >>>>>
wire [4:0] done_buffer;
assign done_buffer[`X_POS] = done_buffer_xpos_din;
assign done_buffer[`Y_POS] = done_buffer_ypos_din;
assign done_buffer[`X_NEG] = done_buffer_xneg_din;
assign done_buffer[`Y_NEG] = done_buffer_yneg_din;
assign done_buffer[`PE] = done_buffer_pe_din;
// -- Entrada :: Campo destino X de Flit de Cabecera ----- >>>>>
wire [`ADDR_FIELD-1:0] x_field [4:0];
assign x_field[`X_POS] = input_channel_xpos_din[29-:`ADDR_FIELD];
assign x_field[`Y_POS] = input_channel_ypos_din[29-:`ADDR_FIELD];
assign x_field[`X_NEG] = input_channel_xneg_din[29-:`ADDR_FIELD];
assign x_field[`Y_NEG] = input_channel_yneg_din[29-:`ADDR_FIELD];
assign x_field[`PE] = input_channel_pe_din [29-:`ADDR_FIELD];
// -- Entrada :: Campo destino Y de Flit de Cabecera ----- >>>>>
wire [`ADDR_FIELD-1:0] y_field [4:0];
assign y_field[`X_POS] = input_channel_xpos_din[(29-`ADDR_FIELD)-:`ADDR_FIELD];
assign y_field[`Y_POS] = input_channel_ypos_din[(29-`ADDR_FIELD)-:`ADDR_FIELD];
assign y_field[`X_NEG] = input_channel_xneg_din[(29-`ADDR_FIELD)-:`ADDR_FIELD];
assign y_field[`Y_NEG] = input_channel_yneg_din[(29-`ADDR_FIELD)-:`ADDR_FIELD];
assign y_field[`PE] = input_channel_pe_din [(29-`ADDR_FIELD)-:`ADDR_FIELD];
// -- Entrada :: Campo destino X desde Buffer ------------ >>>>>
wire [`ADDR_FIELD-1:0] x_buffer [4:0];
assign x_buffer[`X_POS] = buffer_xpos_din[29-:`ADDR_FIELD];
assign x_buffer[`Y_POS] = buffer_ypos_din[29-:`ADDR_FIELD];
assign x_buffer[`X_NEG] = buffer_xneg_din[29-:`ADDR_FIELD];
assign x_buffer[`Y_NEG] = buffer_yneg_din[29-:`ADDR_FIELD];
assign x_buffer[`PE] = buffer_pe_din [29-:`ADDR_FIELD];
// -- Entrada :: Campo destino Y desde Buffer ------------ >>>>>
wire [`ADDR_FIELD-1:0] y_buffer [4:0];
assign y_buffer[`X_POS] = buffer_xpos_din[(29-`ADDR_FIELD)-:`ADDR_FIELD];
assign y_buffer[`Y_POS] = buffer_ypos_din[(29-`ADDR_FIELD)-:`ADDR_FIELD];
assign y_buffer[`X_NEG] = buffer_xneg_din[(29-`ADDR_FIELD)-:`ADDR_FIELD];
assign y_buffer[`Y_NEG] = buffer_yneg_din[(29-`ADDR_FIELD)-:`ADDR_FIELD];
assign y_buffer[`PE] = buffer_pe_din [(29-`ADDR_FIELD)-:`ADDR_FIELD];
// -- Salida :: Señal transfer strobe -------------------- >>>>>
wire [4:0] transfer_strobe;
// -- Salida :: Señal credit add out --------------------- >>>>>
wire [4:0] credit_out; // +1
assign credit_out_xpos_dout = credit_out[`X_POS];
assign credit_out_ypos_dout = credit_out[`Y_POS];
assign credit_out_xneg_dout = credit_out[`X_NEG];
assign credit_out_yneg_dout = credit_out[`Y_NEG];
assign credit_out_pe_dout = credit_out[`PE]; // PE
// -- Salida :: Señal request vector --------------------- >>>>>
wire [3:0] request_vector [4:0]; // +1
// -- Intancias :: Link Controller --------------------------- >>>>>
genvar index;
generate
for (index = `X_POS; index < (`PE + 1); index=index + 1)
begin: link_controller
link_controller
#(
.PORT_DIR (index),
.X_LOCAL (X_LOCAL),
.Y_LOCAL (Y_LOCAL),
.X_WIDTH (X_WIDTH),
.Y_WIDTH (Y_WIDTH)
)
controlador_de_enlace
(
.clk (clk),
.reset (reset),
// -- input ------------------------------ >>>>>
.transfer_strobe_din(transfer_strobe[index]),
.header_field_din (header_field[index]),
.done_field_din (done_field[index]),
.done_buffer_din (done_buffer[index]),
.x_field_din (x_field[index]),
.y_field_din (y_field[index]),
.x_buffer_din (x_buffer[index]),
.y_buffer_din (y_buffer[index]),
// -- output ----------------------------- >>>>>
.write_strobe_dout (write_strobe_dout[index]),
.read_strobe_dout (read_strobe_dout[index]),
.credit_out_dout (credit_out[index]),
.request_vector_dout(request_vector[index])
);
end
endgenerate
/*
-- Instancia :: Selector
-- Descripcion: Modulo de filtrado de peticiones. El uso de algoritmos
adaptativos o parcialmente adaptativos ofrece varios
caminos para dar salida a un paquete, sin embargo la
ejecucion de multiples peticiones produce resultados
impredecibles: duplicacion de paquetes, paquetes
corruptos, etc.
Los modulos 'selector' solo permiten la salida de una
peticion por ciclo de reloj (por puerto de salida).
*/
// -- Selector de Peticiones ------------------------------------- >>>>>
// -- Desglose de Señales ------------------------------------ >>>>>
// -- Entrada :: Status Register ------------------------- >>>>>
// -- Nota :: PSR esta modelado como una memoria pero debe de
// -- inferir registros (memoria distribuida).
wire [3:0] port_status_register [4:0];
// -- Salida :: Vector de Solicitudes Acotado ------------ >>>>>
wire [3:0] masked_request_vector [4:0];
// -- Instancias :: Selector --------------------------------- >>>>>
generate
for (index = `X_POS; index < (`PE + 1); index=index + 1)
begin: selectores
selector
#(
.PORT_DIR (index)
)
selector
(
// -- inputs ------------------------- >>>>>
.request_vector_din (request_vector[index]),
.transfer_strobe_din (transfer_strobe[index]),
.status_register_din (port_status_register[index]),
// -- outputs ------------------------ >>>>>
.masked_request_vector_dout (masked_request_vector[index])
);
end
endgenerate
/*
-- Descripcion: Cada puerto de salida solo puede recibir peticiones de
puertos de entrada opuestos a el.
Ej: Puerto de salida 'x+' solo puede recibir peticiones
de los puertos {pe, y+, x-, y-}. Las lineas de codigo
a continuacion reparten peticiones a sus repestectivos
'planificadores de salida'.
*/
// -- Distribucion de Peticiones por Puerto ---------------------- >>>>>
wire [3:0] request_to_port [4:0];
assign request_to_port[`X_POS] = {
masked_request_vector[`Y_NEG][`YNEG_XPOS],
masked_request_vector[`X_NEG][`XNEG_XPOS],
masked_request_vector[`Y_POS][`YPOS_XPOS],
masked_request_vector[`PE][`PE_XPOS]
};
assign request_to_port[`Y_POS] = {
masked_request_vector[`Y_NEG][`YNEG_YPOS],
masked_request_vector[`X_NEG][`XNEG_YPOS],
masked_request_vector[`X_POS][`XPOS_YPOS],
masked_request_vector[`PE][`PE_YPOS]
};
assign request_to_port[`X_NEG] = {
masked_request_vector[`Y_NEG][`YNEG_XNEG],
masked_request_vector[`Y_POS][`YPOS_XNEG],
masked_request_vector[`X_POS][`XPOS_XNEG],
masked_request_vector[`PE][`PE_XNEG]
};
assign request_to_port[`Y_NEG] = {
masked_request_vector[`X_NEG][`XNEG_YNEG],
masked_request_vector[`Y_POS][`YPOS_YNEG],
masked_request_vector[`X_POS][`XPOS_YNEG],
masked_request_vector[`PE][`PE_YNEG]
};
assign request_to_port[`PE] = {
masked_request_vector[`Y_NEG][`YNEG_PE],
masked_request_vector[`X_NEG][`XNEG_PE],
masked_request_vector[`Y_POS][`YPOS_PE],
masked_request_vector[`X_POS][`XPOS_PE]
};
// -- Planificador de Salida ------------------------------------- >>>>>
// -- Desglose de Señales ------------------------------------ >>>>>
// -- Entrada :: credit add in ----------------------- >>>>>
wire [4:0] credit_in; // +1
assign credit_in[`X_POS] = credit_in_xpos_din;
assign credit_in[`Y_POS] = credit_in_ypos_din;
assign credit_in[`X_NEG] = credit_in_xneg_din;
assign credit_in[`Y_NEG] = credit_in_yneg_din;
assign credit_in[`PE] = credit_in_pe_din; // PE
// -- Salida :: vector de configuracion de crossbar ------ >>>>>
wire [3:0] xbar_conf_vector [4:0]; // +1
// -- Salida :: vector de pulso de transferencia --------- >>>>>
wire [3:0] transfer_strobe_vector [4:0]; // +1
// -- Salida :: bits del registro de estado de puertos --- >>>>>
wire [4:0] status_register;
// -- Instancias :: Planificador de Salida --------------------------- >>>>>
generate
for (index = `X_POS; index < (`PE + 1); index=index + 1)
begin: output_scheduler
outport_scheduler
#(
.PORT_DIR(index)
)
planificador_de_salida
(
.clk (clk),
.reset (reset),
// -- inputs ------------------------------------- >>>>>
.port_request_din (request_to_port[index]),
.credit_in_din (credit_in[index]),
// -- outputs ------------------------------------ >>>>>
.transfer_strobe_vector_dout (transfer_strobe_vector[index]),
.port_status_dout (status_register[index]),
.xbar_conf_vector_dout (xbar_conf_vector[index])
);
end
endgenerate
// -- Asignador de vectores de configuracion para crossbar ----------- >>>>>
assign xbar_conf_vector_xpos_dout = xbar_conf_vector[`X_POS];
assign xbar_conf_vector_ypos_dout = xbar_conf_vector[`Y_POS];
assign xbar_conf_vector_xneg_dout = xbar_conf_vector[`X_NEG];
assign xbar_conf_vector_yneg_dout = xbar_conf_vector[`Y_NEG];
assign xbar_conf_vector_pe_dout = xbar_conf_vector[`PE];
// -- Distribucion de Bits de estado de puerto ----------------------- >>>>>
assign port_status_register[`X_POS] = {
status_register[`Y_NEG],
status_register[`X_NEG],
status_register[`Y_POS],
status_register[`PE]
};
assign port_status_register[`Y_POS] = {
status_register[`Y_NEG],
status_register[`X_NEG],
status_register[`X_POS],
status_register[`PE]
};
assign port_status_register[`X_NEG] = {
status_register[`Y_NEG],
status_register[`Y_POS],
status_register[`X_POS],
status_register[`PE]
};
assign port_status_register[`Y_NEG] = {
status_register[`X_NEG],
status_register[`Y_POS],
status_register[`X_POS],
status_register[`PE]
};
assign port_status_register[`PE] = {
status_register[`Y_NEG],
status_register[`X_NEG],
status_register[`Y_POS],
status_register[`X_POS]
};
// -- Distribucion de Señales Transfer Strobe ---------------------- >>>>>
assign transfer_strobe[`X_POS] = transfer_strobe_vector[`Y_POS][`YPOS_XPOS] |
transfer_strobe_vector[`X_NEG][`XNEG_XPOS] |
transfer_strobe_vector[`Y_NEG][`YNEG_XPOS] |
transfer_strobe_vector[`PE][`PE_XPOS];
assign transfer_strobe[`Y_POS] = transfer_strobe_vector[`X_POS][`XPOS_YPOS] |
transfer_strobe_vector[`X_NEG][`XNEG_YPOS] |
transfer_strobe_vector[`Y_NEG][`YNEG_YPOS] |
transfer_strobe_vector[`PE][`PE_YPOS];
assign transfer_strobe[`X_NEG] = transfer_strobe_vector[`X_POS][`XPOS_XNEG] |
transfer_strobe_vector[`Y_POS][`YPOS_XNEG] |
transfer_strobe_vector[`Y_NEG][`YNEG_XNEG] |
transfer_strobe_vector[`PE][`PE_XNEG];
assign transfer_strobe[`Y_NEG] = transfer_strobe_vector[`X_POS][`XPOS_YNEG] |
transfer_strobe_vector[`Y_POS][`YPOS_YNEG] |
transfer_strobe_vector[`X_NEG][`XNEG_YNEG] |
transfer_strobe_vector[`PE][`PE_YNEG];
assign transfer_strobe[`PE] = transfer_strobe_vector[`X_POS][`XPOS_PE] |
transfer_strobe_vector[`Y_POS][`YPOS_PE] |
transfer_strobe_vector[`X_NEG][`XNEG_PE] |
transfer_strobe_vector[`Y_NEG][`YNEG_PE];
// -- Codigo no sintetizable ------------------------------------- >>>>>
// -- Funciones ---------------------------------------------- >>>>>
// Funcion de calculo: log2(x) ---------------------- >>>>>
function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction
endmodule
/* -- Plantilla de Instancia ------------------------------------- >>>>>
control_path
#(
.X_LOCAL (X_LOCAL),
.Y_LOCAL (Y_LOCAL)
)
camino_de_control
(
.clk (clk),
.reset (reset),
// -- segmentos de puertos de entrada ------------------------ >>>>>
.credit_out_xpos_dout (credit_out_xpos_dout),
.input_channel_xpos_din (input_channel_xpos_din),
.buffer_xpos_din (buffer_xpos_din),
.done_buffer_xpos_din (done_buffer_xpos_din),
.credit_out_ypos_dout (credit_out_ypos_dout),
.input_channel_ypos_din (input_channel_ypos_din),
.buffer_ypos_din (buffer_ypos_din),
.done_buffer_ypos_din (done_buffer_ypos_din),
.credit_out_xneg_dout (credit_out_xneg_dout),
.input_channel_xneg_din (input_channel_xneg_din),
.buffer_xneg_din (buffer_xneg_din),
.done_buffer_xneg_din (done_buffer_xneg_din),
.credit_out_yneg_dout (credit_out_yneg_dout),
.input_channel_yneg_din (input_channel_yneg_din),
.buffer_yneg_din (buffer_yneg_din),
.done_buffer_yneg_din (done_buffer_yneg_din),
.credit_out_pe_dout (credit_out_pe_dout),
.input_channel_pe_din (input_channel_pe_din),
.buffer_pe_din (buffer_pe_din),
.done_buffer_pe_din (done_buffer_pe_din),
// -- puertos de recepcion de creditos ----------------------- >>>>>
.credit_in_xpos_din (credit_in_xpos_din),
.credit_in_ypos_din (credit_in_ypos_din),
.credit_in_xneg_din (credit_in_xneg_din),
.credit_in_yneg_din (credit_in_yneg_din),
.credit_in_pe_din (credit_in_pe_din),
// -- señales de salida a camino de datos -------------------- >>>>>
.write_strobe_dout (write_strobe_dout),
.read_strobe_dout (read_strobe_dout),
.xbar_conf_vector_xpos_dout (xbar_conf_vector_xpos_dout),
.xbar_conf_vector_ypos_dout (xbar_conf_vector_ypos_dout),
.xbar_conf_vector_xneg_dout (xbar_conf_vector_xneg_dout),
.xbar_conf_vector_yneg_dout (xbar_conf_vector_yneg_dout),
.xbar_conf_vector_pe_dout (xbar_conf_vector_pe_dout)
);
*/ |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder
`define STRINGIFY(x) `"x`"
module t;
initial begin
`ifdef D1A
if (`STRINGIFY(`D4B) !== "") $stop;
`else
$write("%%Error: Missing define\n"); $stop;
`endif
`ifdef D2A
if (`STRINGIFY(`D2A) !== "VALA") $stop;
`else
$write("%%Error: Missing define\n"); $stop;
`endif
`ifdef D3A
if (`STRINGIFY(`D4B) !== "") $stop;
`else
$write("%%Error: Missing define\n"); $stop;
`endif
`ifdef D3B
if (`STRINGIFY(`D4B) !== "") $stop;
`else
$write("%%Error: Missing define\n"); $stop;
`endif
`ifdef D4A
if (`STRINGIFY(`D4A) !== "VALA") $stop;
`else
$write("%%Error: Missing define\n"); $stop;
`endif
`ifdef D4B
if (`STRINGIFY(`D4B) !== "") $stop;
`else
$write("%%Error: Missing define\n"); $stop;
`endif
`ifdef D5A
if (`STRINGIFY(`D5A) !== "VALA") $stop;
`else
$write("%%Error: Missing define\n"); $stop;
`endif
`ifdef D5A
if (`STRINGIFY(`D5B) !== "VALB") $stop;
`else
$write("%%Error: Missing define\n"); $stop;
`endif
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module image_filter_Block_proc (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
rows,
cols,
ap_return_0,
ap_return_1,
ap_return_2,
ap_return_3
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 1'b1;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv12_0 = 12'b000000000000;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [31:0] rows;
input [31:0] cols;
output [11:0] ap_return_0;
output [11:0] ap_return_1;
output [11:0] ap_return_2;
output [11:0] ap_return_3;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[11:0] ap_return_0;
reg[11:0] ap_return_1;
reg[11:0] ap_return_2;
reg[11:0] ap_return_3;
reg ap_done_reg = 1'b0;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm = 1'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_20;
reg ap_sig_bdd_38;
wire [11:0] img_0_rows_V_fu_31_p1;
wire [11:0] img_0_cols_V_fu_35_p1;
reg [11:0] ap_return_0_preg = 12'b000000000000;
reg [11:0] ap_return_1_preg = 12'b000000000000;
reg [11:0] ap_return_2_preg = 12'b000000000000;
reg [11:0] ap_return_3_preg = 12'b000000000000;
reg [0:0] ap_NS_fsm;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_done_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_done_reg
if (ap_rst == 1'b1) begin
ap_done_reg <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_continue)) begin
ap_done_reg <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_38)) begin
ap_done_reg <= ap_const_logic_1;
end
end
end
/// ap_return_0_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_0_preg
if (ap_rst == 1'b1) begin
ap_return_0_preg <= ap_const_lv12_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_38)) begin
ap_return_0_preg <= img_0_rows_V_fu_31_p1;
end
end
end
/// ap_return_1_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_1_preg
if (ap_rst == 1'b1) begin
ap_return_1_preg <= ap_const_lv12_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_38)) begin
ap_return_1_preg <= img_0_cols_V_fu_35_p1;
end
end
end
/// ap_return_2_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_2_preg
if (ap_rst == 1'b1) begin
ap_return_2_preg <= ap_const_lv12_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_38)) begin
ap_return_2_preg <= img_0_rows_V_fu_31_p1;
end
end
end
/// ap_return_3_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_3_preg
if (ap_rst == 1'b1) begin
ap_return_3_preg <= ap_const_lv12_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_38)) begin
ap_return_3_preg <= img_0_cols_V_fu_35_p1;
end
end
end
/// ap_done assign process. ///
always @ (ap_done_reg or ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_38)
begin
if (((ap_const_logic_1 == ap_done_reg) | ((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_38))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_38)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_38)) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_return_0 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_38 or img_0_rows_V_fu_31_p1 or ap_return_0_preg)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_38)) begin
ap_return_0 = img_0_rows_V_fu_31_p1;
end else begin
ap_return_0 = ap_return_0_preg;
end
end
/// ap_return_1 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_38 or img_0_cols_V_fu_35_p1 or ap_return_1_preg)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_38)) begin
ap_return_1 = img_0_cols_V_fu_35_p1;
end else begin
ap_return_1 = ap_return_1_preg;
end
end
/// ap_return_2 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_38 or img_0_rows_V_fu_31_p1 or ap_return_2_preg)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_38)) begin
ap_return_2 = img_0_rows_V_fu_31_p1;
end else begin
ap_return_2 = ap_return_2_preg;
end
end
/// ap_return_3 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_38 or img_0_cols_V_fu_35_p1 or ap_return_3_preg)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_38)) begin
ap_return_3 = img_0_cols_V_fu_35_p1;
end else begin
ap_return_3 = ap_return_3_preg;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_20)
begin
if (ap_sig_bdd_20) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_CS_fsm or ap_sig_bdd_38)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
/// ap_sig_bdd_20 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_20 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
/// ap_sig_bdd_38 assign process. ///
always @ (ap_start or ap_done_reg)
begin
ap_sig_bdd_38 = ((ap_start == ap_const_logic_0) | (ap_done_reg == ap_const_logic_1));
end
assign img_0_cols_V_fu_35_p1 = cols[11:0];
assign img_0_rows_V_fu_31_p1 = rows[11:0];
endmodule //image_filter_Block_proc
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:32:42 04/14/2015
// Design Name: memory
// Module Name: H:/Users/ll024/Desktop/PrimeFactorization/test_memory.v
// Project Name: PrimeFactorization
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: memory
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_memory;
// Inputs
reg clka;
reg [0:0] wea;
reg [12:0] addra;
reg [8:0] dina;
// Outputs
wire [8:0] douta;
// Instantiate the Unit Under Test (UUT)
memory uut (
.clka(clka),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta)
);
always #5 clka = ~clka;
initial begin
// Test writing data
clka = 1;
wea = 1;
addra = 13'b0010001000101;
dina = 23;
// Test reading data
#100;
clka = 1;
wea = 0;
addra = 13'b0010001000101;
dina = 78; // this won't overwrite data because wea is 0
end
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Reset_Delay.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Reset_Delay
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Electrical_Velocity_To_Position/Reset_Delay
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Reset_Delay
(
CLK_IN,
reset,
enb_1_2000_0,
Reset_1,
In,
Out
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reset_1;
input signed [31:0] In; // sfix32_En27
output signed [31:0] Out; // sfix32_En27
wire signed [31:0] Constant1_out1; // sfix32_En27
wire signed [31:0] Reset_Switch1_out1; // sfix32_En27
reg signed [31:0] In_Delay_out1; // sfix32_En27
wire signed [31:0] Constant_out1; // sfix32_En27
wire signed [31:0] Reset_Switch_out1; // sfix32_En27
// <S24>/Constant1
assign Constant1_out1 = 32'sb00000000000000000000000000000000;
// <S24>/Reset_Switch1
assign Reset_Switch1_out1 = (Reset_1 == 1'b0 ? In :
Constant1_out1);
// <S24>/In_Delay
always @(posedge CLK_IN)
begin : In_Delay_process
if (reset == 1'b1) begin
In_Delay_out1 <= 32'sb00000000000000000000000000000000;
end
else if (enb_1_2000_0) begin
In_Delay_out1 <= Reset_Switch1_out1;
end
end
// <S24>/Constant
assign Constant_out1 = 32'sb00000000000000000000000000000000;
// <S24>/Reset_Switch
assign Reset_Switch_out1 = (Reset_1 == 1'b0 ? In_Delay_out1 :
Constant_out1);
assign Out = Reset_Switch_out1;
endmodule // controllerHdl_Reset_Delay
|
//-----------------------------------------------------------------
//
// Filename : xlclockdriver.v
//
// Date : 6/29/2004
//
// Description : Verilog description of a clock enable generator block.
// This code is synthesizable.
//
// Assumptions : period >= 1
//
// Mod. History : Translated VHDL clockdriver to Verilog
// : Added pipeline registers
//
// Mod. Dates : 6/29/2004
// : 12/14/2004
//
//-------------------------------------------------------------------
`timescale 1 ns / 10 ps
module xlclockdriver (sysclk, sysclr, sysce, clk, clr, ce, ce_logic);
parameter signed [31:0] log_2_period = 1;
parameter signed [31:0] period = 2;
parameter signed [31:0] use_bufg = 1'b0;
parameter signed [31:0] pipeline_regs = 5;
input sysclk;
input sysclr;
input sysce;
output clk;
output clr;
output ce;
output ce_logic;
//A maximum value of 8 would allow register balancing to the tune of 10^8
//It is set to 8 since we do not have more than 10^8 nets in an FPGA
parameter signed [31:0] max_pipeline_regs = 8;
//Check if requested pipeline regs are greater than the max amount
parameter signed [31:0] num_pipeline_regs = (max_pipeline_regs > pipeline_regs)? pipeline_regs : max_pipeline_regs;
parameter signed [31:0] factor = num_pipeline_regs/period;
parameter signed [31:0] rem_pipeline_regs = num_pipeline_regs - (period * factor) + 1;
//Old constant values
parameter [log_2_period-1:0] trunc_period = ~period + 1;
parameter signed [31:0] period_floor = (period>2)? period : 2;
parameter signed [31:0] power_of_2_counter = (trunc_period == period) ? 1 : 0;
parameter signed [31:0] cnt_width = (power_of_2_counter & (log_2_period>1)) ? (log_2_period - 1) : log_2_period;
parameter [cnt_width-1:0] clk_for_ce_pulse_minus1 = period_floor-2;
parameter [cnt_width-1:0] clk_for_ce_pulse_minus2 = (period-3>0)? period-3 : 0;
parameter [cnt_width-1:0] clk_for_ce_pulse_minus_regs = ((period-rem_pipeline_regs)>0)? (period-rem_pipeline_regs) : 0;
reg [cnt_width-1:0] clk_num;
reg temp_ce_vec;
wire [num_pipeline_regs:0] ce_vec;
wire [num_pipeline_regs:0] ce_vec_logic;
wire internal_ce;
wire internal_ce_logic;
reg cnt_clr;
wire cnt_clr_dly;
genvar index;
initial
begin
clk_num = 'b0;
end
assign clk = sysclk ;
assign clr = sysclr ;
// Clock Number Counter
always @(posedge sysclk)
begin : cntr_gen
if (sysce == 1'b1)
begin:hc
if ((cnt_clr_dly == 1'b1) || (sysclr == 1'b1))
begin:u1
clk_num = {cnt_width{1'b0}};
end
else
begin:u2
clk_num = clk_num + 1 ;
end
end
end
// Clear logic for counter
generate
if (power_of_2_counter == 1)
begin:clr_gen_p2
always @(sysclr)
begin:u1
cnt_clr = sysclr;
end
end
endgenerate
generate
if (power_of_2_counter == 0)
begin:clr_gen
always @(clk_num or sysclr)
begin:u1
if ( (clk_num == clk_for_ce_pulse_minus1) | (sysclr == 1'b1) )
begin:u2
cnt_clr = 1'b1 ;
end
else
begin:u3
cnt_clr = 1'b0 ;
end
end
end // block: clr_gen
endgenerate
synth_reg_w_init #(1, 0, 'b0000, 1)
clr_reg(.i(cnt_clr),
.ce(sysce),
.clr(sysclr),
.clk(sysclk),
.o(cnt_clr_dly));
//Clock Enable Generation
generate
if (period > 1)
begin:pipelined_ce
always @(clk_num)
begin:np_ce_gen
if (clk_num == clk_for_ce_pulse_minus_regs)
begin
temp_ce_vec = 1'b1 ;
end
else
begin
temp_ce_vec = 1'b0 ;
end
end
for(index=0; index<num_pipeline_regs; index=index+1)
begin:ce_pipeline
synth_reg_w_init #(1, ((((index+1)%period)>0)?0:1), 1'b0, 1)
ce_reg(.i(ce_vec[index+1]),
.ce(sysce),
.clr(sysclr),
.clk(sysclk),
.o(ce_vec[index]));
end //block ce_pipeline
for(index=0; index<num_pipeline_regs; index=index+1)
begin:ce_pipeline_logic
synth_reg_w_init #(1, ((((index+1)%period)>0)?0:1), 1'b0, 1)
ce_reg_logic(.i(ce_vec_logic[index+1]),
.ce(sysce),
.clr(sysclr),
.clk(sysclk),
.o(ce_vec_logic[index]));
end //block ce_pipeline
assign ce_vec_logic[num_pipeline_regs] = temp_ce_vec;
assign ce_vec[num_pipeline_regs] = temp_ce_vec;
assign internal_ce = ce_vec[0];
assign internal_ce_logic = ce_vec_logic[0];
end // block: pipelined_ce
endgenerate
generate
if (period > 1)
begin:period_greater_than_1
if (use_bufg == 1'b1)
begin:use_bufg
BUFG ce_bufg_inst(.I(internal_ce), .O(ce));
BUFG ce_logic_bufg_inst(.I(internal_ce_logic), .O(ce_logic));
end
else
begin:no_bufg
assign ce = internal_ce & sysce;
assign ce_logic = internal_ce_logic & sysce;
end
end
endgenerate
generate
if (period == 1)
begin:period_1
assign ce = sysce;
assign ce_logic = sysce;
end
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.8
// \ \ Application: MIG
// / / Filename: phy_init.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:03 $
// \ \ / \ Date Created: Mon Jun 23 2008
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Memory initialization and overall master state control during
// initialization and calibration. Specifically, the following functions
// are performed:
// 1. Memory initialization (initial AR, mode register programming, etc.)
// 2. Initiating write leveling
// 3. Generate training pattern writes for read leveling. Generate
// memory readback for read leveling.
// This module has a DFI interface for providing control/address and write
// data to the rest of the PHY datapath during initialization/calibration.
// Once initialization is complete, control is passed to the MC.
// NOTES:
// 1. Multiple CS (multi-rank) not supported
// 2. DDR2 not supported
//Reference:
//Revision History:
// 9-16-2008 Adding DDR2 initialization sequence. Also adding the DDR_MODE
// parmater. KP
// 12-8-2008 Fixed the address[12] for OTF mode. KP
//*****************************************************************************
/******************************************************************************
**$Id: phy_init.v,v 1.1 2011/06/02 07:18:03 mishra Exp $
**$Date: 2011/06/02 07:18:03 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/phy_init.v,v $
******************************************************************************/
`timescale 1ps/1ps
module phy_init #
(
parameter TCQ = 100,
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter CLK_PERIOD = 3333, // Logic (internal) clk period (in ps)
parameter BANK_WIDTH = 2,
parameter COL_WIDTH = 10,
parameter nCS_PER_RANK = 1, // # of CS bits per rank e.g. for
// component I/F with CS_WIDTH=1,
// nCS_PER_RANK=# of components
parameter DQ_WIDTH = 64,
parameter ROW_WIDTH = 14,
parameter CS_WIDTH = 1,
parameter CKE_WIDTH = 1, // # of cke outputs
parameter DRAM_TYPE = "DDR3",
parameter REG_CTRL = "ON",
// calibration Address
parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
// DRAM mode settings
parameter AL = "0", // Additive Latency option
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter nAL = 0, // Additive latency (in clk cyc)
parameter nCL = 5, // Read CAS latency (in clk cyc)
parameter nCWL = 5, // Write CAS latency (in clk cyc)
parameter tRFC = 110000, // Refresh-to-command delay (in ps)
parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option
parameter RTT_NOM = "60", // Nominal ODT termination value
parameter RTT_WR = "60", // Write ODT termination value
parameter WRLVL = "ON", // Enable write leveling
parameter PHASE_DETECT = "ON", // Enable read phase detector
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter nSLOTS = 1, // Number of DIMM SLOTs in the system
parameter SIM_INIT_OPTION = "NONE", // "NONE", "SKIP_PU_DLY", "SKIP_INIT"
parameter SIM_CAL_OPTION = "NONE" // "NONE", "FAST_CAL", "SKIP_CAL"
)
(
input clk,
input rst,
// Read/write calibration interface
input [2:0] calib_width,
input rdpath_rdy,
input wrlvl_done,
input wrlvl_rank_done,
input [7:0] slot_0_present,
input [7:0] slot_1_present,
output reg wrlvl_active,
input [1:0] rdlvl_done,
output reg [1:0] rdlvl_start,
input rdlvl_clkdiv_done,
output reg rdlvl_clkdiv_start,
input rdlvl_prech_req,
input rdlvl_resume,
// To phy_write for write bitslip during read leveling
output [1:0] chip_cnt,
// Read phase detector calibration control
output reg pd_cal_start,
input pd_cal_done,
input pd_prech_req,
// Signals shared btw multiple calibration stages
output reg prech_done,
// Data select / status
output reg dfi_init_complete,
// PHY DFI address/control
output reg [ROW_WIDTH-1:0] phy_address0,
output reg [ROW_WIDTH-1:0] phy_address1,
output reg [BANK_WIDTH-1:0] phy_bank0,
output reg [BANK_WIDTH-1:0] phy_bank1,
output reg phy_cas_n0,
output reg phy_cas_n1,
output reg [CKE_WIDTH-1:0] phy_cke0,
output reg [CKE_WIDTH-1:0] phy_cke1,
output reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_cs_n0,
output reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_cs_n1,
output phy_init_data_sel,
output reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_odt0,
output reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_odt1,
output reg phy_ras_n0,
output reg phy_ras_n1,
output reg phy_reset_n,
output reg phy_we_n0,
output reg phy_we_n1,
// PHY DFI Write
output reg phy_wrdata_en,
output reg [4*DQ_WIDTH-1:0] phy_wrdata,
// PHY DFI Read
output reg phy_rddata_en,
// PHY sideband signals
output reg [0:0] phy_ioconfig,
output reg phy_ioconfig_en
);
// In a 2 slot dual rank per system RTT_NOM values
// for Rank2 and Rank3 default to 40 ohms
localparam RTT_NOM2 = "40";
localparam RTT_NOM3 = "40";
// Specifically for use with half-frequency controller (nCK_PER_CLK=2)
// = 1 if burst length = 4, = 0 if burst length = 8. Determines how
// often row command needs to be issued during read-leveling
// For DDR3 the burst length is fixed during calibration
localparam BURST4_FLAG = (DRAM_TYPE == "DDR3")? 1'b0 :
(BURST_MODE == "8") ? 1'b0 :
((BURST_MODE == "4") ? 1'b1 : 1'b0);
//***************************************************************************
// Counter values used to determine bus timing
// NOTE on all counter terminal counts - these can/should be one less than
// the actual delay to take into account extra clock cycle delay in
// generating the corresponding "done" signal
//***************************************************************************
localparam CLK_MEM_PERIOD = CLK_PERIOD / nCK_PER_CLK;
// Calculate initial delay required in number of CLK clock cycles
// to delay initially. The counter is clocked by [CLK/1024] - which
// is approximately division by 1000 - note that the formulas below will
// result in more than the minimum wait time because of this approximation.
// NOTE: For DDR3 JEDEC specifies to delay reset
// by 200us, and CKE by an additional 500us after power-up
// For DDR2 CKE is delayed by 200us after power up.
localparam DDR3_RESET_DELAY_NS = 200000;
localparam DDR3_CKE_DELAY_NS = 500000 + DDR3_RESET_DELAY_NS;
localparam DDR2_CKE_DELAY_NS = 200000;
localparam PWRON_RESET_DELAY_CNT =
((DDR3_RESET_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD);
localparam PWRON_CKE_DELAY_CNT = (DRAM_TYPE == "DDR3") ?
(((DDR3_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)) :
(((DDR2_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD));
// FOR DDR2 -1 taken out. With -1 not getting 200us. The equation
// needs to be reworked.
localparam DDR2_INIT_PRE_DELAY_PS = 400000;
localparam DDR2_INIT_PRE_CNT =
((DDR2_INIT_PRE_DELAY_PS+CLK_PERIOD-1)/CLK_PERIOD)-1;
// Calculate tXPR time: reset from CKE HIGH to valid command after power-up
// tXPR = (max(5nCK, tRFC(min)+10ns). Add a few (blah, messy) more clock
// cycles because this counter actually starts up before CKE is asserted
// to memory.
localparam TXPR_DELAY_CNT =
(5*CLK_MEM_PERIOD > tRFC+10000) ?
(((5+nCK_PER_CLK-1)/nCK_PER_CLK)-1)+5 :
(((tRFC+10000+CLK_PERIOD-1)/CLK_PERIOD)-1)+5;
// tDLLK/tZQINIT time = 512*tCK = 256*tCLKDIV
localparam TDLLK_TZQINIT_DELAY_CNT = 255;
// TWR values in ns. Both DDR2 and DDR3 have the same value.
// 15000ns/tCK
localparam TWR_CYC = ((15000) % CLK_MEM_PERIOD) ?
(15000/CLK_MEM_PERIOD) + 1 : 15000/CLK_MEM_PERIOD;
// time to wait between consecutive commands in PHY_INIT - this is a
// generic number, and must be large enough to account for worst case
// timing parameter (tRFC - refresh-to-active) across all memory speed
// grades and operating frequencies. Expressed in CLKDIV clock cycles.
localparam CNTNEXT_CMD = 7'b1111111;
// Counter values to keep track of which MR register to load during init
// Set value of INIT_CNT_MR_DONE to equal value of counter for last mode
// register configured during initialization.
// NOTE: Reserve more bits for DDR2 - more MR accesses for DDR2 init
localparam INIT_CNT_MR2 = 2'b00;
localparam INIT_CNT_MR3 = 2'b01;
localparam INIT_CNT_MR1 = 2'b10;
localparam INIT_CNT_MR0 = 2'b11;
localparam INIT_CNT_MR_DONE = 2'b11;
// Register chip programmable values for DDR3
// The register chip for the registered DIMM needs to be programmed
// before the initialization of the registered DIMM.
// Address for the control word is in : DBA2, DA2, DA1, DA0
// Data for the control word is in: DBA1 DBA0, DA4, DA3
// The values will be stored in the local param in the following format
// {DBA[2:0], DA[4:0]}
// RC0 is global features control word. Address == 000
localparam REG_RC0 = 8'b00000000;
// RC1 Clock driver enable control word. Enables or disables the four
// output clocks in the register chip. For single rank and dual rank
// two clocks will be enabled and for quad rank all the four clocks
// will be enabled. Address == 000. Data = 0110 for single and dual rank.
// = 0000 for quad rank
localparam REG_RC1 = (CS_WIDTH <= 2) ? 8'b00110001 : 8'b00000001;
// RC2 timing control word. Set in 1T timing mode
// Address = 010. Data = 0000
localparam REG_RC2 = 8'b00000010;
// RC3 timing control word. Setting the data to 0000
localparam REG_RC3 = 8'b00000011;
// RC4 timing control work. Setting the data to 0000
localparam REG_RC4 = 8'b00000100;
// RC5 timing control work. Setting the data to 0000
localparam REG_RC5 = 8'b00000101;
// Adding the register dimm latency to write latency
localparam CWL_M = (REG_CTRL == "ON") ? nCWL + 1 : nCWL;
// Master state machine encoding
localparam INIT_IDLE = 6'b000000; //0
localparam INIT_WAIT_CKE_EXIT = 6'b000001; //1
localparam INIT_LOAD_MR = 6'b000010; //2
localparam INIT_LOAD_MR_WAIT = 6'b000011; //3
localparam INIT_ZQCL = 6'b000100; //4
localparam INIT_WAIT_DLLK_ZQINIT = 6'b000101; //5
localparam INIT_WRLVL_START = 6'b000110; //6
localparam INIT_WRLVL_WAIT = 6'b000111; //7
localparam INIT_WRLVL_LOAD_MR = 6'b001000; //8
localparam INIT_WRLVL_LOAD_MR_WAIT = 6'b001001; //9
localparam INIT_WRLVL_LOAD_MR2 = 6'b001010; //A
localparam INIT_WRLVL_LOAD_MR2_WAIT = 6'b001011; //B
localparam INIT_RDLVL_ACT = 6'b001100; //C
localparam INIT_RDLVL_ACT_WAIT = 6'b001101; //D
localparam INIT_RDLVL_STG1_WRITE = 6'b001110; //E
localparam INIT_RDLVL_STG1_WRITE_READ = 6'b001111; //F
localparam INIT_RDLVL_STG1_READ = 6'b010000; //10
localparam INIT_RDLVL_STG2_WRITE = 6'b010001; //11
localparam INIT_RDLVL_STG2_WRITE_READ = 6'b010010; //12
localparam INIT_RDLVL_STG2_READ = 6'b010011; //13
localparam INIT_RDLVL_STG2_READ_WAIT = 6'b010100; //14
localparam INIT_PRECHARGE_PREWAIT = 6'b010101; //15
localparam INIT_PRECHARGE = 6'b010110; //16
localparam INIT_PRECHARGE_WAIT = 6'b010111; //17
localparam INIT_DONE = 6'b011000; //18
localparam INIT_IOCONFIG_WR = 6'b011001; //19
localparam INIT_IOCONFIG_RD = 6'b011010; //1A
localparam INIT_IOCONFIG_WR_WAIT = 6'b011011; //1B
localparam INIT_IOCONFIG_RD_WAIT = 6'b011100; //1C
localparam INIT_DDR2_PRECHARGE = 6'b011101; //1D
localparam INIT_DDR2_PRECHARGE_WAIT = 6'b011110; //1E
localparam INIT_REFRESH = 6'b011111; //1F
localparam INIT_REFRESH_WAIT = 6'b100000; //20
localparam INIT_PD_ACT = 6'b100001; //21
localparam INIT_PD_ACT_WAIT = 6'b100010; //22
localparam INIT_PD_READ = 6'b100011; //23
localparam INIT_REG_WRITE = 6'b100100; //24
localparam INIT_REG_WRITE_WAIT = 6'b100101; //25
localparam INIT_DDR2_MULTI_RANK = 6'b100110; //26
localparam INIT_DDR2_MULTI_RANK_WAIT = 6'b100111; //27
localparam INIT_RDLVL_CLKDIV_WRITE = 6'b101000; //28
localparam INIT_RDLVL_CLKDIV_WRITE_READ = 6'b101001; //29
localparam INIT_RDLVL_CLKDIV_READ = 6'b101010; //2A
reg [1:0] auto_cnt_r;
reg [1:0] burst_addr_r;
reg [1:0] chip_cnt_r;
reg [6:0] cnt_cmd_r;
reg cnt_cmd_done_r;
reg [7:0] cnt_dllk_zqinit_r;
reg cnt_dllk_zqinit_done_r;
reg cnt_init_af_done_r;
reg [1:0] cnt_init_af_r;
reg [3:0] cnt_init_data_r;
reg [1:0] cnt_init_mr_r;
reg cnt_init_mr_done_r;
reg cnt_init_pre_wait_done_r;
reg [7:0] cnt_init_pre_wait_r;
reg [9:0] cnt_pwron_ce_r;
reg cnt_pwron_cke_done_r;
reg [8:0] cnt_pwron_r;
reg cnt_pwron_reset_done_r;
reg cnt_txpr_done_r;
reg [7:0] cnt_txpr_r;
reg ddr2_pre_flag_r;
reg ddr2_refresh_flag_r;
reg ddr3_lm_done_r;
reg [4:0] enable_wrlvl_cnt;
reg init_complete_r;
reg init_complete_r1;
reg init_complete_r2;
reg [5:0] init_next_state;
reg [5:0] init_state_r;
reg [5:0] init_state_r1;
wire [15:0] load_mr0;
wire [15:0] load_mr1;
wire [15:0] load_mr2;
wire [15:0] load_mr3;
reg mem_init_done_r;
reg mem_init_done_r1;
reg [1:0] mr2_r [0:3];
reg [2:0] mr1_r [0:3];
reg new_burst_r;
reg [15:0] pd_cal_start_dly_r;
wire pd_cal_start_pre;
reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_tmp_odt0_r;
reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_tmp_odt1_r;
reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_tmp_odt0_r1;
reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_tmp_odt1_r1;
reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_tmp_cs1_r;
wire prech_done_pre;
reg [15:0] prech_done_dly_r;
reg prech_pending_r;
reg prech_req_posedge_r;
reg prech_req_r;
reg pwron_ce_r;
reg [ROW_WIDTH-1:0] address_w;
reg [BANK_WIDTH-1:0] bank_w;
reg [15:0] rdlvl_start_dly0_r;
reg [15:0] rdlvl_start_dly1_r;
reg [15:0] rdlvl_start_dly_clkdiv_r;
wire [1:0] rdlvl_start_pre;
wire rdlvl_start_pre_clkdiv;
wire rdlvl_rd;
wire rdlvl_wr;
reg rdlvl_wr_r;
wire rdlvl_wr_rd;
reg [2:0] reg_ctrl_cnt_r;
reg [1:0] tmp_mr2_r [0:3];
reg [2:0] tmp_mr1_r [0:3];
reg wrlvl_done_r;
reg wrlvl_done_r1;
reg wrlvl_rank_done_r1;
reg wrlvl_rank_done_r2;
reg wrlvl_rank_done_r3;
reg [2:0] wrlvl_rank_cntr;
reg wrlvl_odt;
reg wrlvl_odt_r1;
//***************************************************************************
// Debug
//***************************************************************************
//synthesis translate_off
always @(posedge mem_init_done_r1) begin
if (!rst)
$display ("PHY_INIT: Memory Initialization completed at %t", $time);
end
always @(posedge wrlvl_done) begin
if (!rst && (WRLVL == "ON"))
$display ("PHY_INIT: Write Leveling completed at %t", $time);
end
always @(posedge rdlvl_done[0]) begin
if (!rst)
$display ("PHY_INIT: Read Leveling Stage 1 completed at %t", $time);
end
always @(posedge rdlvl_done[1]) begin
if (!rst)
$display ("PHY_INIT: Read Leveling Stage 2 completed at %t", $time);
end
always @(posedge rdlvl_clkdiv_done) begin
if (!rst)
$display ("PHY_INIT: Read Leveling CLKDIV cal completed at %t", $time);
end
always @(posedge pd_cal_done) begin
if (!rst && (PHASE_DETECT == "ON"))
$display ("PHY_INIT: Phase Detector Initial Cal completed at %t", $time);
end
//synthesis translate_on
//***************************************************************************
// Signal PHY completion when calibration is finished
// Signal assertion is delayed by four clock cycles to account for the
// multi cycle path constraint to (phy_init_data_sel) signal.
//***************************************************************************
always @(posedge clk)
if (rst) begin
init_complete_r <= #TCQ 1'b0;
init_complete_r1 <= #TCQ 1'b0;
init_complete_r2 <= #TCQ 1'b0;
dfi_init_complete <= #TCQ 1'b0;
end else begin
if (init_state_r == INIT_DONE)
init_complete_r <= #TCQ 1'b1;
init_complete_r1 <= #TCQ init_complete_r;
init_complete_r2 <= #TCQ init_complete_r1;
dfi_init_complete <= #TCQ init_complete_r2;
end
//***************************************************************************
// Instantiate FF for the phy_init_data_sel signal. A multi cycle path
// constraint will be assigned to this signal. This signal will only be
// used within the PHY
//***************************************************************************
FDRSE u_ff_phy_init_data_sel
(
.Q (phy_init_data_sel),
.C (clk),
.CE (1'b1),
.D (init_complete_r),
.R (1'b0),
.S (1'b0)
) /* synthesis syn_preserve=1 */
/* synthesis syn_replicate = 0 */;
//***************************************************************************
// Mode register programming
//***************************************************************************
//*****************************************************************
// DDR3 Load mode reg0
// Mode Register (MR0):
// [15:13] - unused - 000
// [12] - Precharge Power-down DLL usage - 0 (DLL frozen, slow-exit),
// 1 (DLL maintained)
// [11:9] - write recovery for Auto Precharge (tWR/tCK = 6)
// [8] - DLL reset - 0 or 1
// [7] - Test Mode - 0 (normal)
// [6:4],[2] - CAS latency - CAS_LAT
// [3] - Burst Type - BURST_TYPE
// [1:0] - Burst Length - BURST_LEN
// DDR2 Load mode register
// Mode Register (MR):
// [15:14] - unused - 00
// [13] - reserved - 0
// [12] - Power-down mode - 0 (normal)
// [11:9] - write recovery - write recovery for Auto Precharge
// (tWR/tCK = 6)
// [8] - DLL reset - 0 or 1
// [7] - Test Mode - 0 (normal)
// [6:4] - CAS latency - CAS_LAT
// [3] - Burst Type - BURST_TYPE
// [2:0] - Burst Length - BURST_LEN
//*****************************************************************
generate
if(DRAM_TYPE == "DDR3") begin: gen_load_mr0_DDR3
assign load_mr0[1:0] = (BURST_MODE == "8") ? 2'b00 :
(BURST_MODE == "OTF") ? 2'b01 :
(BURST_MODE == "4") ? 2'b10 : 2'b11;
assign load_mr0[2] = 1'b0; // LSb of CAS latency
assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1;
assign load_mr0[6:4] = (nCL == 5) ? 3'b001 :
(nCL == 6) ? 3'b010 :
(nCL == 7) ? 3'b011 :
(nCL == 8) ? 3'b100 :
(nCL == 9) ? 3'b101 :
(nCL == 10) ? 3'b110 :
(nCL == 11) ? 3'b111 : 3'b111;
assign load_mr0[7] = 1'b0;
assign load_mr0[8] = 1'b1; // Reset DLL (init only)
assign load_mr0[11:9] = (TWR_CYC == 5) ? 3'b001 :
(TWR_CYC == 6) ? 3'b010 :
(TWR_CYC == 7) ? 3'b011 :
(TWR_CYC == 8) ? 3'b100 :
(TWR_CYC == 9) ? 3'b101 :
(TWR_CYC == 10) ? 3'b101 :
(TWR_CYC == 11) ? 3'b110 :
(TWR_CYC == 12) ? 3'b110 : 3'b010;
assign load_mr0[12] = 1'b0; // Precharge Power-Down DLL 'slow-exit'
assign load_mr0[15:13] = 3'b000;
end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr0_DDR2 // block: gen
assign load_mr0[2:0] = (BURST_MODE == "8") ? 3'b011 :
(BURST_MODE == "4") ? 3'b010 : 3'b111;
assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1;
assign load_mr0[6:4] = (nCL == 3) ? 3'b011 :
(nCL == 4) ? 3'b100 :
(nCL == 5) ? 3'b101 :
(nCL == 6) ? 3'b110 : 3'b111;
assign load_mr0[7] = 1'b0;
assign load_mr0[8] = 1'b1; // Reset DLL (init only)
assign load_mr0[11:9] = (TWR_CYC == 2) ? 3'b001 :
(TWR_CYC == 3) ? 3'b010 :
(TWR_CYC == 4) ? 3'b011 :
(TWR_CYC == 5) ? 3'b100 :
(TWR_CYC == 6) ? 3'b101 : 3'b010;
assign load_mr0[15:12]= 4'b0000; // Reserved
end
endgenerate
//*****************************************************************
// DDR3 Load mode reg1
// Mode Register (MR1):
// [15:13] - unused - 00
// [12] - output enable - 0 (enabled for DQ, DQS, DQS#)
// [11] - TDQS enable - 0 (TDQS disabled and DM enabled)
// [10] - reserved - 0 (must be '0')
// [9] - RTT[2] - 0
// [8] - reserved - 0 (must be '0')
// [7] - write leveling - 0 (disabled), 1 (enabled)
// [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50)
// [5] - Output driver impedance[1] - 0 (RZQ/6 and RZQ/7)
// [4:3] - Additive CAS - ADDITIVE_CAS
// [2] - RTT[0]
// [1] - Output driver impedance[0] - 0(RZQ/6), or 1 (RZQ/7)
// [0] - DLL enable - 0 (normal)
// DDR2 ext mode register
// Extended Mode Register (MR):
// [15:14] - unused - 00
// [13] - reserved - 0
// [12] - output enable - 0 (enabled)
// [11] - RDQS enable - 0 (disabled)
// [10] - DQS# enable - 0 (enabled)
// [9:7] - OCD Program - 111 or 000 (first 111, then 000 during init)
// [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50)
// [5:3] - Additive CAS - ADDITIVE_CAS
// [2] - RTT[0]
// [1] - Output drive - REDUCE_DRV (= 0(full), = 1 (reduced)
// [0] - DLL enable - 0 (normal)
//*****************************************************************
generate
if(DRAM_TYPE == "DDR3") begin: gen_load_mr1_DDR3
assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization
assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b0 : 1'b1;
assign load_mr1[2] = ((RTT_NOM == "30") || (RTT_NOM == "40") ||
(RTT_NOM == "60")) ? 1'b1 : 1'b0;
assign load_mr1[4:3] = (AL == "0") ? 2'b00 :
(AL == "CL-1") ? 2'b01 :
(AL == "CL-2") ? 2'b10 : 2'b11;
assign load_mr1[5] = 1'b0;
assign load_mr1[6] = ((RTT_NOM == "40") || (RTT_NOM == "120")) ?
1'b1 : 1'b0;
assign load_mr1[7] = 1'b0; // Enable write lvl after init sequence
assign load_mr1[8] = 1'b0;
assign load_mr1[9] = ((RTT_NOM == "20") || (RTT_NOM == "30")) ?
1'b1 : 1'b0;
assign load_mr1[10] = 1'b0;
assign load_mr1[15:11] = 5'b00000;
end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr1_DDR2
assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization
assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b1 : 1'b0;
assign load_mr1[2] = ((RTT_NOM == "75") || (RTT_NOM == "50")) ?
1'b1 : 1'b0;
assign load_mr1[5:3] = (AL == "0") ? 3'b000 :
(AL == "1") ? 3'b001 :
(AL == "2") ? 3'b010 :
(AL == "3") ? 3'b011 :
(AL == "4") ? 3'b100 : 3'b111;
assign load_mr1[6] = ((RTT_NOM == "50") ||
(RTT_NOM == "150")) ? 1'b1 : 1'b0;
assign load_mr1[9:7] = 3'b000;
assign load_mr1[10] = (DDR2_DQSN_ENABLE == "YES") ? 1'b0 : 1'b1;
assign load_mr1[15:11] = 5'b00000;
end
endgenerate
//*****************************************************************
// DDR3 Load mode reg2
// Mode Register (MR2):
// [15:11] - unused - 00
// [10:9] - RTT_WR - 00 (Dynamic ODT off)
// [8] - reserved - 0 (must be '0')
// [7] - self-refresh temperature range -
// 0 (normal), 1 (extended)
// [6] - Auto Self-Refresh - 0 (manual), 1(auto)
// [5:3] - CAS Write Latency (CWL) -
// 000 (5 for 400 MHz device),
// 001 (6 for 400 MHz to 533 MHz devices),
// 010 (7 for 533 MHz to 667 MHz devices),
// 011 (8 for 667 MHz to 800 MHz)
// [2:0] - Partial Array Self-Refresh (Optional) -
// 000 (full array)
// Not used for DDR2
//*****************************************************************
generate
if(DRAM_TYPE == "DDR3") begin: gen_load_mr2_DDR3
assign load_mr2[2:0] = 3'b000;
assign load_mr2[5:3] = (nCWL == 5) ? 3'b000 :
(nCWL == 6) ? 3'b001 :
(nCWL == 7) ? 3'b010 :
(nCWL == 8) ? 3'b011 : 3'b111;
assign load_mr2[6] = 1'b0;
assign load_mr2[7] = 1'b0;
assign load_mr2[8] = 1'b0;
// Dynamic ODT disabled
assign load_mr2[10:9] = 2'b00;
assign load_mr2[15:11] = 5'b00000;
end else begin: gen_load_mr2_DDR2
assign load_mr2[15:0] = 16'd0;
end
endgenerate
//*****************************************************************
// DDR3 Load mode reg3
// Mode Register (MR3):
// [15:3] - unused - All zeros
// [2] - MPR Operation - 0(normal operation), 1(data flow from MPR)
// [1:0] - MPR location - 00 (Predefined pattern)
//*****************************************************************
assign load_mr3[1:0] = 2'b00;
assign load_mr3[2] = 1'b0;
assign load_mr3[15:3] = 13'b0000000000000;
// For multi-rank systems the rank being accessed during writes in
// Read Leveling must be sent to phy_write for the bitslip logic
// Due to timing issues this signal is registered in phy_top.v
assign chip_cnt = chip_cnt_r;
//***************************************************************************
// Logic to begin initial calibration, and to handle precharge requests
// during read-leveling (to avoid tRAS violations if individual read
// levelling calibration stages take more than max{tRAS) to complete).
//***************************************************************************
// Assert when readback for each stage of read-leveling begins. However,
// note this indicates only when the read command is issued, it does not
// indicate when the read data is present on the bus (when this happens
// after the read command is issued depends on CAS LATENCY) - there will
// need to be some delay before valid data is present on the bus.
assign rdlvl_start_pre[0] = (init_state_r == INIT_RDLVL_STG1_READ);
assign rdlvl_start_pre[1] = (init_state_r == INIT_RDLVL_STG2_READ);
assign rdlvl_start_pre_clkdiv = (init_state_r == INIT_RDLVL_CLKDIV_READ);
// Similar comment applies to start of PHASE DETECTOR
assign pd_cal_start_pre = (init_state_r == INIT_PD_READ);
// Common precharge signal done signal - pulses only when there has been
// a precharge issued as a result of a PRECH_REQ pulse. Note also a common
// PRECH_DONE signal is used for all blocks
assign prech_done_pre = (((init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_RDLVL_CLKDIV_READ) ||
(init_state_r == INIT_PD_READ)) &&
prech_pending_r &&
!prech_req_posedge_r);
// Delay start of each calibration by 16 clock cycles to ensure that when
// calibration logic begins, read data is already appearing on the bus.
// Each circuit should synthesize using an SRL16. Assume that reset is
// long enough to clear contents of SRL16.
always @(posedge clk) begin
rdlvl_start_dly0_r <= #TCQ {rdlvl_start_dly0_r[14:0],
rdlvl_start_pre[0]};
rdlvl_start_dly1_r <= #TCQ {rdlvl_start_dly1_r[14:0],
rdlvl_start_pre[1]};
rdlvl_start_dly_clkdiv_r <= #TCQ {rdlvl_start_dly_clkdiv_r[14:0],
rdlvl_start_pre_clkdiv};
pd_cal_start_dly_r <= #TCQ {pd_cal_start_dly_r[14:0],
pd_cal_start_pre};
prech_done_dly_r <= #TCQ {prech_done_dly_r[14:0],
prech_done_pre};
end
always @(posedge clk)
prech_done <= #TCQ prech_done_dly_r[15];
// Generate latched signals for start of write and read leveling
always @(posedge clk)
if (rst) begin
rdlvl_start <= #TCQ 2'b00;
rdlvl_clkdiv_start <= #TCQ 1'b0;
pd_cal_start <= #TCQ 1'b0;
end else begin
if (rdlvl_start_dly0_r[15])
rdlvl_start[0] <= #TCQ 1'b1;
if (rdlvl_start_dly1_r[15])
rdlvl_start[1] <= #TCQ 1'b1;
if (rdlvl_start_dly_clkdiv_r[15])
rdlvl_clkdiv_start <= #TCQ 1'b1;
if (pd_cal_start_dly_r[15])
pd_cal_start <= #TCQ 1'b1;
end
// Constantly enable DQS while write leveling is enabled in the memory
// This is more to get rid of warnings in simulation, can later change
// this code to only enable WRLVL_ACTIVE when WRLVL_START is asserted
always @ (posedge clk)
if (rst)
enable_wrlvl_cnt <= #TCQ 5'd0;
else if (init_state_r == INIT_WRLVL_START)
enable_wrlvl_cnt <= #TCQ 5'd20;
else if (enable_wrlvl_cnt > 5'd0)
enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1;
always @(posedge clk)
if (rst || wrlvl_rank_done || wrlvl_done)
wrlvl_active <= #TCQ 1'b0;
else if ((enable_wrlvl_cnt == 5'd1) && !wrlvl_active)
wrlvl_active <= #TCQ 1'b1;
always @(posedge clk)
if (rst || wrlvl_rank_done || wrlvl_done)
wrlvl_odt <= #TCQ 1'b0;
else if (enable_wrlvl_cnt == 5'd14)
wrlvl_odt <= #TCQ 1'b1;
always @(posedge clk) begin
wrlvl_odt_r1 <= wrlvl_odt;
wrlvl_done_r <= #TCQ wrlvl_done;
wrlvl_done_r1 <= #TCQ wrlvl_done_r;
wrlvl_rank_done_r1 <= #TCQ wrlvl_rank_done;
wrlvl_rank_done_r2 <= #TCQ wrlvl_rank_done_r1;
wrlvl_rank_done_r3 <= #TCQ wrlvl_rank_done_r2;
end
always @ (posedge clk) begin
if (rst)
wrlvl_rank_cntr <= #TCQ 3'd0;
else if (wrlvl_rank_done)
wrlvl_rank_cntr <= #TCQ wrlvl_rank_cntr + 1'b1;
end
//*****************************************************************
// Precharge request logic - those calibration logic blocks
// that require greater than tRAS(max) to finish must break up
// their calibration into smaller units of time, with precharges
// issued in between. This is done using the XXX_PRECH_REQ and
// PRECH_DONE handshaking between PHY_INIT and those blocks
//*****************************************************************
// Shared request from multiple sources
assign prech_req = rdlvl_prech_req | pd_prech_req;
// Handshaking logic to force precharge during read leveling, and to
// notify read leveling logic when precharge has been initiated and
// it's okay to proceed with leveling again
always @(posedge clk)
if (rst) begin
prech_req_r <= #TCQ 1'b0;
prech_req_posedge_r <= #TCQ 1'b0;
prech_pending_r <= #TCQ 1'b0;
end else begin
prech_req_r <= #TCQ prech_req;
prech_req_posedge_r <= #TCQ prech_req & ~prech_req_r;
if (prech_req_posedge_r)
prech_pending_r <= #TCQ 1'b1;
// Clear after we've finished with the precharge and have
// returned to issuing read leveling calibration reads
else if (prech_done_pre)
prech_pending_r <= #TCQ 1'b0;
end
//***************************************************************************
// Various timing counters
//***************************************************************************
//*****************************************************************
// Generic delay for various states that require it (e.g. for turnaround
// between read and write). Make this a sufficiently large number of clock
// cycles to cover all possible frequencies and memory components)
// Requirements for this counter:
// 1. Greater than tMRD
// 2. tRFC (refresh-active) for DDR2
// 3. (list the other requirements, slacker...)
//*****************************************************************
always @(posedge clk) begin
case (init_state_r)
INIT_LOAD_MR_WAIT,
INIT_WRLVL_LOAD_MR_WAIT,
INIT_WRLVL_LOAD_MR2_WAIT,
INIT_RDLVL_ACT_WAIT,
INIT_RDLVL_STG1_WRITE_READ,
INIT_RDLVL_STG2_WRITE_READ,
INIT_RDLVL_CLKDIV_WRITE_READ,
INIT_RDLVL_STG2_READ_WAIT,
INIT_PD_ACT_WAIT,
INIT_PRECHARGE_PREWAIT,
INIT_PRECHARGE_WAIT,
INIT_DDR2_PRECHARGE_WAIT,
INIT_REG_WRITE_WAIT,
INIT_REFRESH_WAIT:
cnt_cmd_r <= #TCQ cnt_cmd_r + 1;
INIT_WRLVL_WAIT:
cnt_cmd_r <= #TCQ 'b0;
default:
cnt_cmd_r <= #TCQ 'b0;
endcase
end
// pulse when count reaches terminal count
always @(posedge clk)
cnt_cmd_done_r <= #TCQ (cnt_cmd_r == CNTNEXT_CMD);
//*****************************************************************
// Initial delay after power-on for RESET, CKE
// NOTE: Could reduce power consumption by turning off these counters
// after initial power-up (at expense of more logic)
// NOTE: Likely can combine multiple counters into single counter
//*****************************************************************
// Create divided by 1024 version of clock
always @(posedge clk)
if (rst) begin
cnt_pwron_ce_r <= #TCQ 10'h000;
pwron_ce_r <= #TCQ 1'b0;
end else begin
cnt_pwron_ce_r <= #TCQ cnt_pwron_ce_r + 1;
pwron_ce_r <= #TCQ (cnt_pwron_ce_r == 10'h3FF);
end
// "Main" power-on counter - ticks every CLKDIV/1024 cycles
always @(posedge clk)
if (rst)
cnt_pwron_r <= #TCQ 'b0;
else if (pwron_ce_r)
cnt_pwron_r <= #TCQ cnt_pwron_r + 1;
always @(posedge clk)
if (rst) begin
cnt_pwron_reset_done_r <= #TCQ 1'b0;
cnt_pwron_cke_done_r <= #TCQ 1'b0;
end else begin
// skip power-up count for simulation purposes only
if ((SIM_INIT_OPTION == "SKIP_PU_DLY") ||
(SIM_INIT_OPTION == "SKIP_INIT")) begin
cnt_pwron_reset_done_r <= #TCQ 1'b1;
cnt_pwron_cke_done_r <= #TCQ 1'b1;
end else begin
// otherwise, create latched version of done signal for RESET, CKE
if (DRAM_TYPE == "DDR3") begin
if (!cnt_pwron_reset_done_r)
cnt_pwron_reset_done_r
<= #TCQ (cnt_pwron_r == PWRON_RESET_DELAY_CNT);
if (!cnt_pwron_cke_done_r)
cnt_pwron_cke_done_r
<= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT);
end else begin // DDR2
cnt_pwron_reset_done_r <= #TCQ 1'b1; // not needed
if (!cnt_pwron_cke_done_r)
cnt_pwron_cke_done_r
<= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT);
end
end
end
// Keep RESET asserted and CKE deasserted until after power-on delay
always @(posedge clk) begin
phy_reset_n <= #TCQ cnt_pwron_reset_done_r;
phy_cke0 <= #TCQ {CKE_WIDTH{cnt_pwron_cke_done_r}};
phy_cke1 <= #TCQ {CKE_WIDTH{cnt_pwron_cke_done_r}};
end
//*****************************************************************
// Counter for tXPR (pronouned "Tax-Payer") - wait time after
// CKE deassertion before first MRS command can be asserted
//*****************************************************************
always @(posedge clk)
if (!cnt_pwron_cke_done_r) begin
cnt_txpr_r <= #TCQ 'b0;
cnt_txpr_done_r <= #TCQ 1'b0;
end else begin
cnt_txpr_r <= #TCQ cnt_txpr_r + 1;
if (!cnt_txpr_done_r)
cnt_txpr_done_r <= #TCQ (cnt_txpr_r == TXPR_DELAY_CNT);
end
//*****************************************************************
// Counter for the initial 400ns wait for issuing precharge all
// command after CKE assertion. Only for DDR2.
//*****************************************************************
always @(posedge clk)
if (!cnt_pwron_cke_done_r) begin
cnt_init_pre_wait_r <= #TCQ 'b0;
cnt_init_pre_wait_done_r <= #TCQ 1'b0;
end else begin
cnt_init_pre_wait_r <= #TCQ cnt_init_pre_wait_r + 1;
if (!cnt_init_pre_wait_done_r)
cnt_init_pre_wait_done_r
<= #TCQ (cnt_init_pre_wait_r >= DDR2_INIT_PRE_CNT);
end
//*****************************************************************
// Wait for both DLL to lock (tDLLK) and ZQ calibration to finish
// (tZQINIT). Both take the same amount of time (512*tCK)
//*****************************************************************
// Reset condition added to cnt_dll_zqinit_r, cnt_dll_zqinit_done_r
// and stopped cnt_dllk_zqinit_r from free running to avoid corner
// case where downstream signal mem_init_done_r can be asserted early in H/W (i.e.
// without a reset if cnt_dll_zqinit_r is free running mem_init_done_r could be high earlier)
always @(posedge clk)
if (rst) begin
cnt_dllk_zqinit_r <= 'b0;
end else if (init_state_r == INIT_ZQCL) begin
cnt_dllk_zqinit_r <= #TCQ 'b0;
end else if ((init_state_r == INIT_WAIT_DLLK_ZQINIT)
&& (cnt_dllk_zqinit_r != TDLLK_TZQINIT_DELAY_CNT)) begin
cnt_dllk_zqinit_r <= #TCQ cnt_dllk_zqinit_r + 1;
end
always @(posedge clk)
if (rst) begin
cnt_dllk_zqinit_done_r <= #TCQ 1'b0;
end else if (init_state_r == INIT_ZQCL) begin
cnt_dllk_zqinit_done_r <= #TCQ 1'b0;
end else begin
cnt_dllk_zqinit_done_r
<= #TCQ (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT);
end
//*****************************************************************
// Keep track of which MRS counter needs to be programmed during
// memory initialization
// The counter and the done signal are reset an additional time
// for DDR2. The same signals are used for the additional DDR2
// initialization sequence.
//*****************************************************************
always @(posedge clk)
if ((init_state_r == INIT_IDLE)||
((init_state_r == INIT_REFRESH)
&& (~mem_init_done_r1))) begin
cnt_init_mr_r <= #TCQ 'b0;
cnt_init_mr_done_r <= #TCQ 1'b0;
end else if (init_state_r == INIT_LOAD_MR) begin
cnt_init_mr_r <= #TCQ cnt_init_mr_r + 1;
cnt_init_mr_done_r <= #TCQ (cnt_init_mr_r == INIT_CNT_MR_DONE);
end
//*****************************************************************
// Flag to tell if the first precharge for DDR2 init sequence is
// done
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_IDLE)
ddr2_pre_flag_r<= #TCQ 'b0;
else if (init_state_r == INIT_LOAD_MR)
ddr2_pre_flag_r<= #TCQ 1'b1;
// reset the flag for multi rank case
else if ((ddr2_refresh_flag_r) &&
(init_state_r == INIT_LOAD_MR_WAIT)&&
(cnt_cmd_done_r) && (cnt_init_mr_done_r))
ddr2_pre_flag_r <= #TCQ 'b0;
//*****************************************************************
// Flag to tell if the refresh stat for DDR2 init sequence is
// reached
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_IDLE)
ddr2_refresh_flag_r<= #TCQ 'b0;
else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r1))
// reset the flag for multi rank case
ddr2_refresh_flag_r<= #TCQ 1'b1;
else if ((ddr2_refresh_flag_r) &&
(init_state_r == INIT_LOAD_MR_WAIT)&&
(cnt_cmd_done_r) && (cnt_init_mr_done_r))
ddr2_refresh_flag_r <= #TCQ 'b0;
//*****************************************************************
// Keep track of the number of auto refreshes for DDR2
// initialization. The spec asks for a minimum of two refreshes.
// Four refreshes are performed here. The two extra refreshes is to
// account for the 200 clock cycle wait between step h and l.
// Without the two extra refreshes we would have to have a
// wait state.
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_IDLE) begin
cnt_init_af_r <= #TCQ 'b0;
cnt_init_af_done_r <= #TCQ 1'b0;
end else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r1)) begin
cnt_init_af_r <= #TCQ cnt_init_af_r + 1;
cnt_init_af_done_r <= #TCQ (cnt_init_af_r == 2'b11);
end
//*****************************************************************
// Keep track of the register control word programming for
// DDR3 RDIMM
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_IDLE)
reg_ctrl_cnt_r <= #TCQ 'b0;
else if (init_state_r == INIT_REG_WRITE)
reg_ctrl_cnt_r <= #TCQ reg_ctrl_cnt_r + 1;
//***************************************************************************
// Initialization state machine
//***************************************************************************
//*****************************************************************
// Next-state logic
//*****************************************************************
always @(posedge clk)
if (rst)begin
init_state_r <= #TCQ INIT_IDLE;
init_state_r1 <= #TCQ INIT_IDLE;
end else begin
init_state_r <= #TCQ init_next_state;
init_state_r1 <= #TCQ init_state_r;
end
always @(burst_addr_r or chip_cnt_r or cnt_cmd_done_r
or cnt_dllk_zqinit_done_r or cnt_init_af_done_r
or cnt_init_mr_done_r
or cnt_init_pre_wait_done_r or cnt_pwron_cke_done_r
or cnt_txpr_done_r or ddr2_pre_flag_r
or ddr2_refresh_flag_r or ddr3_lm_done_r
or init_state_r or mem_init_done_r1
or pd_cal_done or prech_req_posedge_r
or rdlvl_done or rdlvl_clkdiv_done or rdlvl_resume
or rdlvl_start or rdlvl_clkdiv_start or rdpath_rdy
or reg_ctrl_cnt_r or wrlvl_done_r1 or wrlvl_rank_done_r3) begin
init_next_state = init_state_r;
(* full_case, parallel_case *) case (init_state_r)
//*******************************************************
// DRAM initialization
//*******************************************************
// Initial state - wait for:
// 1. Power-on delays to pass
// 2. Read path initialization to finish
INIT_IDLE:
if (cnt_pwron_cke_done_r && rdpath_rdy) begin
// If skipping memory initialization (simulation only)
if (SIM_INIT_OPTION == "SKIP_INIT")
if (WRLVL == "ON")
// Proceed to write leveling
init_next_state = INIT_WRLVL_START;
else if (SIM_CAL_OPTION != "SKIP_CAL")
// Proceed to read leveling
init_next_state = INIT_RDLVL_ACT;
else
// Skip read leveling
init_next_state = INIT_DONE;
else
init_next_state = INIT_WAIT_CKE_EXIT;
end
// Wait minimum of Reset CKE exit time (tXPR = max(tXS,
INIT_WAIT_CKE_EXIT:
if ((cnt_txpr_done_r) && (DRAM_TYPE == "DDR3")) begin
if((REG_CTRL == "ON") && ((nCS_PER_RANK > 1) ||
(CS_WIDTH > 1)))
//register write for reg dimm. Some register chips
// have the register chip in a pre-programmed state
// in that case the nCS_PER_RANK == 1 && CS_WIDTH == 1
init_next_state = INIT_REG_WRITE;
else
// Load mode register - this state is repeated multiple times
init_next_state = INIT_LOAD_MR;
end else if ((cnt_init_pre_wait_done_r) && (DRAM_TYPE == "DDR2"))
// DDR2 start with a precharge all command
init_next_state = INIT_DDR2_PRECHARGE;
INIT_REG_WRITE:
init_next_state = INIT_REG_WRITE_WAIT;
INIT_REG_WRITE_WAIT:
if (cnt_cmd_done_r) begin
if(reg_ctrl_cnt_r == 3'd5)
init_next_state = INIT_LOAD_MR;
else
init_next_state = INIT_REG_WRITE;
end
INIT_LOAD_MR:
init_next_state = INIT_LOAD_MR_WAIT;
// After loading MR, wait at least tMRD
INIT_LOAD_MR_WAIT:
if (cnt_cmd_done_r) begin
// If finished loading all mode registers, proceed to next step
if(&rdlvl_done)
// for ddr3 when the correct burst length is writtern at end
init_next_state = INIT_PRECHARGE;
else if (cnt_init_mr_done_r)begin
if(DRAM_TYPE == "DDR3")
init_next_state = INIT_ZQCL;
else begin //DDR2
if(ddr2_refresh_flag_r)begin
// memory initialization per rank for multi-rank case
if (!mem_init_done_r1 && (chip_cnt_r <= CS_WIDTH-1))
init_next_state = INIT_DDR2_MULTI_RANK;
else
init_next_state = INIT_RDLVL_ACT;
// ddr2 initialization done.load mode state after refresh
end else
init_next_state = INIT_DDR2_PRECHARGE;
end
end else
init_next_state = INIT_LOAD_MR;
end // if (cnt_cmd_done_r)
// DDR2 multi rank transition state
INIT_DDR2_MULTI_RANK:
init_next_state = INIT_DDR2_MULTI_RANK_WAIT;
INIT_DDR2_MULTI_RANK_WAIT:
init_next_state = INIT_DDR2_PRECHARGE;
// Initial ZQ calibration
INIT_ZQCL:
init_next_state = INIT_WAIT_DLLK_ZQINIT;
// Wait until both DLL have locked, and ZQ calibration done
INIT_WAIT_DLLK_ZQINIT:
if (cnt_dllk_zqinit_done_r)
// memory initialization per rank for multi-rank case
if (!mem_init_done_r && (chip_cnt_r <= CS_WIDTH-1))
init_next_state = INIT_LOAD_MR;
else if (WRLVL == "ON")
init_next_state = INIT_WRLVL_START;
else
// skip write-leveling (e.g. for component interface)
init_next_state = INIT_RDLVL_ACT;
// Initial precharge for DDR2
INIT_DDR2_PRECHARGE:
init_next_state = INIT_DDR2_PRECHARGE_WAIT;
INIT_DDR2_PRECHARGE_WAIT:
if (cnt_cmd_done_r) begin
if(ddr2_pre_flag_r)
init_next_state = INIT_REFRESH;
else// from precharge state initally go to load mode
init_next_state = INIT_LOAD_MR;
end
INIT_REFRESH:
init_next_state = INIT_REFRESH_WAIT;
INIT_REFRESH_WAIT:
if (cnt_cmd_done_r)begin
if(cnt_init_af_done_r && (~mem_init_done_r1))
// go to lm state as part of DDR2 init sequence
init_next_state = INIT_LOAD_MR;
else if (mem_init_done_r1)begin
if(auto_cnt_r < (CS_WIDTH))
init_next_state = INIT_REFRESH;
else if ((&rdlvl_done) && (PHASE_DETECT == "ON"))
init_next_state = INIT_PD_ACT;
else
init_next_state = INIT_RDLVL_ACT;
end else // to DDR2 init state as part of DDR2 init sequence
init_next_state = INIT_REFRESH;
end
//******************************************************
// Write Leveling
//*******************************************************
// Enable write leveling in MR1 and start write leveling
// for current rank
INIT_WRLVL_START:
init_next_state = INIT_WRLVL_WAIT;
// Wait for both MR load and write leveling to complete
// (write leveling should take much longer than MR load..)
INIT_WRLVL_WAIT:
if (wrlvl_rank_done_r3)
init_next_state = INIT_WRLVL_LOAD_MR;
// Disable write leveling in MR1 for current rank
INIT_WRLVL_LOAD_MR:
init_next_state = INIT_WRLVL_LOAD_MR_WAIT;
INIT_WRLVL_LOAD_MR_WAIT:
if (cnt_cmd_done_r)
init_next_state = INIT_WRLVL_LOAD_MR2;
// Load MR2 to set ODT: Dynamic ODT for single rank case
// And ODTs for multi-rank case as well
INIT_WRLVL_LOAD_MR2:
init_next_state = INIT_WRLVL_LOAD_MR2_WAIT;
// Wait tMRD before proceeding
INIT_WRLVL_LOAD_MR2_WAIT:
if (cnt_cmd_done_r) begin
if (~wrlvl_done_r1)
init_next_state = INIT_WRLVL_START;
else if (SIM_CAL_OPTION == "SKIP_CAL")
// If skip rdlvl, then we're done
init_next_state = INIT_DONE;
else
// Otherwise, proceed to read leveling
init_next_state = INIT_RDLVL_ACT;
end
//*******************************************************
// Read Leveling
//*******************************************************
// single row activate. All subsequent read leveling writes and
// read will take place in this row
INIT_RDLVL_ACT:
init_next_state = INIT_RDLVL_ACT_WAIT;
// hang out for awhile before issuing subsequent column commands
// it's also possible to reach this state at various points
// during read leveling - determine what the current stage is
INIT_RDLVL_ACT_WAIT:
if (cnt_cmd_done_r) begin
// Just finished an activate. Now either write, read, or precharge
// depending on where we are in the training sequence
if (!rdlvl_done[0] && !rdlvl_start[0])
// Case 1: If in stage 1, and entering for first time, then
// write training pattern to memory
init_next_state = INIT_IOCONFIG_WR;
else if (!rdlvl_done[0] && rdlvl_start[0])
// Case 2: If in stage 1, and just precharged after training
// previous byte, then continue reading
init_next_state = INIT_IOCONFIG_RD;
else if (!rdlvl_clkdiv_done && !rdlvl_clkdiv_start)
// Case 3: If in CLKDIV cal, and entering for first time, then
// write training pattern to memory
init_next_state = INIT_IOCONFIG_WR;
else if (!rdlvl_clkdiv_done && rdlvl_clkdiv_start)
// Case 4: If in CLKDIV cal, and just precharged after training
// previous byte, then continue reading
init_next_state = INIT_IOCONFIG_RD;
else if (!rdlvl_done[1] && !rdlvl_start[1])
// Case 5: If in stage 2, and entering for first time, then
// write training pattern to memory
init_next_state = INIT_IOCONFIG_WR;
else if (!rdlvl_done[1] && rdlvl_start[1])
// Case 6: If in stage 2, and just precharged after training
// previous byte, then continue reading
init_next_state = INIT_IOCONFIG_RD;
else
// Otherwise, if we're finished with calibration, then precharge
// the row - silly, because we just opened it - possible to take
// this out by adding logic to avoid the ACT in first place. Make
// sure that cnt_cmd_done will handle tRAS(min)
init_next_state = INIT_PRECHARGE_PREWAIT;
end
//*********************************************
// Stage 1 read-leveling (write and continuous read)
//*********************************************
// Write training pattern for stage 1
INIT_RDLVL_STG1_WRITE:
// Once we've issued enough commands for 16 words - proceed to reads
// Note that 16 words are written even though the training pattern
// is only 8 words (training pattern is written twice) because at
// this point in the calibration process we may be generating the
// DQS and DQ a few cycles early (that part of the write timing
// adjustment doesn't happen until stage 2)
if (burst_addr_r == 2'b11)
init_next_state = INIT_RDLVL_STG1_WRITE_READ;
// Write-read turnaround
INIT_RDLVL_STG1_WRITE_READ:
if (cnt_cmd_done_r)
init_next_state = INIT_IOCONFIG_RD;
// Continuous read, where interruptible by precharge request from
// calibration logic. Also precharges when stage 1 is complete
INIT_RDLVL_STG1_READ:
if (rdlvl_done[0] || prech_req_posedge_r)
init_next_state = INIT_PRECHARGE_PREWAIT;
//*********************************************
// CLKDIV calibration read-leveling (write and continuous read)
//*********************************************
// Write training pattern for stage 1
INIT_RDLVL_CLKDIV_WRITE:
// Once we've issued enough commands for 16 words - proceed to reads
// See comment for state RDLVL_STG1_WRITE
if (burst_addr_r == 2'b11)
init_next_state = INIT_RDLVL_CLKDIV_WRITE_READ;
// Write-read turnaround
INIT_RDLVL_CLKDIV_WRITE_READ:
if (cnt_cmd_done_r)
init_next_state = INIT_IOCONFIG_RD;
// Continuous read, where interruptible by precharge request from
// calibration logic. Also precharges when stage 1 is complete
INIT_RDLVL_CLKDIV_READ:
if (rdlvl_clkdiv_done || prech_req_posedge_r)
init_next_state = INIT_PRECHARGE_PREWAIT;
//*********************************************
// Stage 2 read-leveling (write and continuous read)
//*********************************************
// Write training pattern for stage 1
INIT_RDLVL_STG2_WRITE:
// Once we've issued enough commands for 16 words - proceed to reads
// Write 8 extra words in order to prevent any previous data in
// memory from skewing calibration results (write 8 words for
// training pattern followed by 8 zeros)
if (burst_addr_r == 2'b11)
init_next_state = INIT_RDLVL_STG2_WRITE_READ;
// Write-read turnaround
INIT_RDLVL_STG2_WRITE_READ:
if (cnt_cmd_done_r)
init_next_state = INIT_IOCONFIG_RD;
// Read of training data. Note that Stage 2 is not a constant read,
// instead there is a large gap between each read
INIT_RDLVL_STG2_READ:
// Keep reading for 8 words
if (burst_addr_r == 2'b01)
init_next_state = INIT_RDLVL_STG2_READ_WAIT;
// Wait before issuing the next read. If a precharge request comes in
// then handle it
INIT_RDLVL_STG2_READ_WAIT:
if (rdlvl_resume)
init_next_state = INIT_IOCONFIG_WR;
else if (rdlvl_done[1] || prech_req_posedge_r)
init_next_state = INIT_PRECHARGE_PREWAIT;
else if (cnt_cmd_done_r)
init_next_state = INIT_RDLVL_STG2_READ;
//*********************************************
// Phase detector initial calibration
//*********************************************
// single row activate. All subsequent PD calibration takes place
// using this row
INIT_PD_ACT:
init_next_state = INIT_PD_ACT_WAIT;
// hang out for awhile before issuing subsequent column command
INIT_PD_ACT_WAIT:
if (cnt_cmd_done_r)
init_next_state = INIT_IOCONFIG_RD;
// Read of training data - constant reads. Note that for PD
// calibration, data is not important - only DQS is used.
// PD calibration is interruptible by precharge request from
// calibration logic. Also precharges a final time when PD cal done
INIT_PD_READ:
if (pd_cal_done || prech_req_posedge_r)
init_next_state = INIT_PRECHARGE_PREWAIT;
//*********************************************
// Handling of precharge during and in between read-level stages
//*********************************************
// Make sure we aren't violating any timing specs by precharging
// immediately
INIT_PRECHARGE_PREWAIT:
if (cnt_cmd_done_r)
init_next_state = INIT_PRECHARGE;
// Initiate precharge
INIT_PRECHARGE:
init_next_state = INIT_PRECHARGE_WAIT;
INIT_PRECHARGE_WAIT:
if (cnt_cmd_done_r) begin
if ((pd_cal_done || (PHASE_DETECT != "ON")) && (&rdlvl_done)
&& ( (ddr3_lm_done_r)|| (DRAM_TYPE == "DDR2")))
// If read leveling and phase detection calibration complete,
// and programing the correct burst length then we're finished
init_next_state = INIT_DONE;
else if ((pd_cal_done || (PHASE_DETECT != "ON")) && (&rdlvl_done))
// after all calibration program the correct burst length
init_next_state = INIT_LOAD_MR;
else
// Otherwise, open row for read-leveling purposes
init_next_state = INIT_REFRESH;
end
//*******************************************************
// Wait a cycle before switching commands to pulse the IOCONFIG
// Time is needed to turn around the IODELAY. Wait state is
// added because IOCONFIG must be asserted 2 clock cycles before
// before corresponding command/address (probably a less logic-
// intensive way of doing this, that doesn't involve extra states)
//*******************************************************
INIT_IOCONFIG_WR:
init_next_state = INIT_IOCONFIG_WR_WAIT;
INIT_IOCONFIG_WR_WAIT:
if (!rdlvl_done[0])
// Write Stage 1 training pattern to memory
init_next_state = INIT_RDLVL_STG1_WRITE;
else if (!rdlvl_clkdiv_done)
// Write CLKDIV cal training pattern to memory
init_next_state = INIT_RDLVL_CLKDIV_WRITE;
else
// Write Stage 2 training pattern to memory
init_next_state = INIT_RDLVL_STG2_WRITE;
INIT_IOCONFIG_RD:
init_next_state = INIT_IOCONFIG_RD_WAIT;
INIT_IOCONFIG_RD_WAIT:
if (!rdlvl_done[0])
// Read Stage 1 training pattern from memory
init_next_state = INIT_RDLVL_STG1_READ;
else if (!rdlvl_clkdiv_done)
// Read CLKDIV cal training pattern from memory
init_next_state = INIT_RDLVL_CLKDIV_READ;
else if (!rdlvl_done[1])
// Read Stage 2 training pattern from memory
init_next_state = INIT_RDLVL_STG2_READ;
else
// Phase Detector read
init_next_state = INIT_PD_READ;
//*******************************************************
// Initialization/Calibration done. Take a long rest, relax
//*******************************************************
INIT_DONE:
init_next_state = INIT_DONE;
endcase
end
//*****************************************************************
// Initialization done signal - asserted before leveling starts
//*****************************************************************
always @(posedge clk)
if (rst)
mem_init_done_r <= #TCQ 1'b0;
else if ((!cnt_dllk_zqinit_done_r &&
(cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT) &&
(chip_cnt_r == CS_WIDTH-1) && (DRAM_TYPE == "DDR3"))
|| ( (init_state_r == INIT_LOAD_MR_WAIT) &&
(ddr2_refresh_flag_r) && (chip_cnt_r == CS_WIDTH-1)
&& (cnt_init_mr_done_r) && (DRAM_TYPE == "DDR2")))
mem_init_done_r <= #TCQ 1'b1;
// registered for timing. mem_init_done_r1 will be used in the
// design. The design can tolerate the extra cycle of latency.
always @(posedge clk)
mem_init_done_r1 <= #TCQ mem_init_done_r;
//*****************************************************************
// DDR3 final burst length programming done. For DDR3 during
// calibration the burst length is fixed to BL8. After calibration
// the correct burst length is programmed.
//*****************************************************************
always @(posedge clk)
if (rst)
ddr3_lm_done_r <= #TCQ 1'b0;
else if ((init_state_r == INIT_LOAD_MR_WAIT) &&
(chip_cnt_r == CS_WIDTH-1) && (&rdlvl_done))
ddr3_lm_done_r <= #TCQ 1'b1;
//***************************************************************************
// Logic for deep memory (multi-rank) configurations
//
//***************************************************************************
// For DDR3 asserted when
always @(posedge clk)
if (rst || (wrlvl_done_r &&
(init_state_r==INIT_WRLVL_LOAD_MR2_WAIT))
|| ((mem_init_done_r & (~mem_init_done_r1))
&& (DRAM_TYPE == "DDR2"))) begin
chip_cnt_r <= #TCQ 2'b00;
end else if (((init_state_r1 == INIT_REFRESH) &&
mem_init_done_r1) )begin
if (chip_cnt_r < CS_WIDTH-1)
chip_cnt_r <= #TCQ chip_cnt_r + 1;
else
chip_cnt_r <= #TCQ 2'b00;
end else if ((((init_state_r == INIT_WAIT_DLLK_ZQINIT) &&
(cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT) &&
(!cnt_dllk_zqinit_done_r)) ||
((init_state_r!=INIT_WRLVL_LOAD_MR2_WAIT) &&
(init_next_state==INIT_WRLVL_LOAD_MR2_WAIT)) &&
(DRAM_TYPE == "DDR3")) ||
((init_state_r == INIT_DDR2_MULTI_RANK)
&& (DRAM_TYPE == "DDR2")) ||
// condition to increment chip_cnt during
// final burst length programming for DDR3
((init_state_r == INIT_LOAD_MR_WAIT) &&
(cnt_cmd_done_r)&& (&rdlvl_done)))
begin
if (((~mem_init_done_r1 || (&rdlvl_done)) &&
(chip_cnt_r != CS_WIDTH-1)) ||
(mem_init_done_r1 && ~(&rdlvl_done) &&
(chip_cnt_r != calib_width -1)))
chip_cnt_r <= #TCQ chip_cnt_r + 1;
else
chip_cnt_r <= #TCQ 2'b00;
end
// keep track of which chip selects got auto-refreshed (avoid auto-refreshing
// all CS's at once to avoid current spike)
always @(posedge clk)begin
if (rst || init_state_r == INIT_PRECHARGE)
auto_cnt_r <= #TCQ 'd0;
else if (init_state_r == INIT_REFRESH && mem_init_done_r1) begin
if (auto_cnt_r < CS_WIDTH)
auto_cnt_r <= #TCQ auto_cnt_r + 1;
end
end
always @(posedge clk)
if (rst) begin
phy_cs_n0 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
phy_cs_n1 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
end else begin
phy_cs_n0 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
phy_cs_n1 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
if (init_state_r == INIT_REG_WRITE) begin
phy_cs_n0 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
phy_cs_n1 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
end else if (wrlvl_odt) begin
// Component interface without fly-by topology
// must have all CS# outputs asserted simultaneously
// since it is a wide not deep interface
if ((REG_CTRL == "OFF") && (nCS_PER_RANK > 1))
phy_cs_n0 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
// For single and dual rank RDIMMS and UDIMMs only
// CS# of the selected rank must be asserted
else begin
phy_cs_n0 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
phy_cs_n0[chip_cnt_r] <= #TCQ 1'd0;
end
phy_cs_n1 <= #TCQ phy_tmp_cs1_r;
end else if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_RDLVL_STG2_WRITE) ||
(init_state_r == INIT_RDLVL_CLKDIV_READ) ||
(init_state_r == INIT_RDLVL_CLKDIV_WRITE) ||
(init_state_r == INIT_PD_ACT) ||
(init_state_r == INIT_PD_READ) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH)) begin
phy_cs_n0 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
phy_cs_n1 <= #TCQ phy_tmp_cs1_r;
end
end
//***************************************************************************
// Write/read burst logic for calibration
//***************************************************************************
assign rdlvl_wr = (init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG2_WRITE) ||
(init_state_r == INIT_RDLVL_CLKDIV_WRITE);
assign rdlvl_rd = (init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_RDLVL_CLKDIV_READ) ||
(init_state_r == INIT_PD_READ);
assign rdlvl_wr_rd = rdlvl_wr | rdlvl_rd;
// Determine current DRAM address (lower bits of address) when writing or
// reading from memory during calibration (to access training patterns):
// (1) address must be initialized to 0 before entering all write/read
// states
// (2) for writes, the maximum address is = {2 * length of calibration
// training pattern}
// (3) for reads, the maximum address is = {length of calibration
// training pattern}, therefore it will need to be reinitialized
// while we remain in a read state since reads can occur continuously
// NOTE: For a training pattern length of 8, burst_addr is used to
// such that the lower order bits of the address are given by =
// {burst_addr, 2'b00}. This can be expanded for more bits if the training
// sequence is longer than 8 words
always @(posedge clk)
if (rdlvl_rd)
// Reads only access first 8 words of memory, and the access can
// occur continously (i.e. w/o leaving the read state)
burst_addr_r <= #TCQ {1'b0, ~burst_addr_r[0]};
else if (rdlvl_wr)
// Writes will access first 16 words fo memory, and the access is
// only one-time (before leaving the write state)
burst_addr_r <= #TCQ burst_addr_r + 1;
else
// Otherwise, during any other states, reset address to 0
burst_addr_r <= #TCQ 2'b00;
// determine how often to issue row command during read leveling writes
// and reads
always @(posedge clk)
if (rdlvl_wr_rd) begin
if (BURST4_FLAG)
new_burst_r <= #TCQ 1'b1;
else
new_burst_r <= #TCQ ~new_burst_r;
end else
new_burst_r <= #TCQ 1'b1;
// indicate when a write is occurring. PHY_WRDATA_EN must be asserted
// simultaneous with the corresponding command/address for CWL = 5,6
always @(posedge clk) begin
rdlvl_wr_r <= #TCQ rdlvl_wr;
end
// As per the tPHY_WRLAT spec phy_wrdata_en should be delayed
// for CWL >= 7
always @(posedge clk) begin
if (CWL_M <= 4) begin
phy_wrdata_en <= #TCQ rdlvl_wr;
end else if (CWL_M == 5) begin
phy_wrdata_en <= #TCQ rdlvl_wr;
end else if (CWL_M == 6) begin
phy_wrdata_en <= #TCQ rdlvl_wr;
end else if (CWL_M == 7) begin
phy_wrdata_en <= #TCQ rdlvl_wr_r;
end else if (CWL_M == 8) begin
phy_wrdata_en <= #TCQ rdlvl_wr_r;
end else if (CWL_M == 9) begin
phy_wrdata_en <= #TCQ rdlvl_wr_r;
end
end
// generate the sideband signal to indicate when the bus turns around
// from a write to a read, or vice versa. Used asserting signals related
// to the bus turnaround (e.g. IODELAY delay value)
always @(posedge clk) begin
if (init_state_r == INIT_IOCONFIG_WR) begin
// Transition for writes
phy_ioconfig_en <= #TCQ 1'b1;
phy_ioconfig[0] <= #TCQ 1'b1;
end else if (init_state_r == INIT_IOCONFIG_RD) begin
//Transition for reads
phy_ioconfig_en <= #TCQ 1'b1;
phy_ioconfig[0] <= #TCQ 1'b0;
end else
// Keep PHY_IOCONFIG at whatever value it currently is
// Only assert strobe when a new value appears
phy_ioconfig_en <= #TCQ 1'b0;
end
// indicate when a write is occurring. PHY_RDDATA_EN must be asserted
// simultaneous with the corresponding command/address. PHY_RDDATA_EN
// is used during read-leveling to determine read latency
always @(posedge clk)
phy_rddata_en <= #TCQ rdlvl_rd;
//***************************************************************************
// Generate training data written at start of each read-leveling stage
// For every stage of read leveling, 8 words are written into memory
// The format is as follows (shown as {rise,fall}):
// Stage 1: 0xF, 0x0, 0xF, 0x0, 0xF, 0x0, 0xF, 0x0
// CLKDIV cal: 0xF, 0xF, 0xF. 0xF, 0x0, 0x0, 0x0, 0x0
// Stage 2: 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6
//***************************************************************************
always @(posedge clk)
// NOTE: No need to initialize cnt_init_data_r except possibly for
// simulation purposes (to prevent excessive warnings) since first
// state encountered before its use is RDLVL_STG1_WRITE
if (phy_wrdata_en)
cnt_init_data_r <= #TCQ cnt_init_data_r + 1;
else if ((init_state_r == INIT_IDLE) ||
(init_state_r == INIT_RDLVL_STG1_WRITE))
cnt_init_data_r <= #TCQ 4'b0000;
else if (init_state_r == INIT_RDLVL_CLKDIV_WRITE)
cnt_init_data_r <= #TCQ 4'b0100;
else if (init_state_r == INIT_RDLVL_STG2_WRITE)
cnt_init_data_r <= #TCQ 4'b1000;
always @(posedge clk)
(* full_case, parallel_case *) case (cnt_init_data_r)
// Stage 1 calibration pattern (all 4 writes have same data)
4'b0000, 4'b0001, 4'b0010, 4'b0011:
phy_wrdata <= #TCQ {{DQ_WIDTH{1'b0}},{DQ_WIDTH{1'b1}},
{DQ_WIDTH{1'b0}},{DQ_WIDTH{1'b1}}};
// Stage 3 calibration pattern (repeat twice)
4'b0100, 4'b0110:
phy_wrdata <= #TCQ {{DQ_WIDTH{1'b1}},{DQ_WIDTH{1'b1}},
{DQ_WIDTH{1'b1}},{DQ_WIDTH{1'b1}}};
4'b0101, 4'b0111:
phy_wrdata <= #TCQ {{DQ_WIDTH{1'b0}},{DQ_WIDTH{1'b0}},
{DQ_WIDTH{1'b0}},{DQ_WIDTH{1'b0}}};
// Stage 2 calibration pattern (2 different sets of writes, each 8
// 2 different sets of writes, each 8words long
4'b1000:
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}},
{DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}};
4'b1001:
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}};
4'b1010, 4'b1011:
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'h0}},
{DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'h0}}};
endcase
//***************************************************************************
// Memory control/address
//***************************************************************************
// Assert RAS when: (1) Loading MRS, (2) Activating Row, (3) Precharging
// (4) auto refresh
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_PD_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH))begin
phy_ras_n1 <= #TCQ 1'b0;
phy_ras_n0 <= #TCQ 1'b0;
end else begin
phy_ras_n1 <= #TCQ 1'b1;
phy_ras_n0 <= #TCQ 1'b1;
end
end
// Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command
// (3) auto refresh
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_REFRESH) ||
(rdlvl_wr_rd && new_burst_r))begin
phy_cas_n1 <= #TCQ 1'b0;
phy_cas_n0 <= #TCQ 1'b0;
end else begin
phy_cas_n1 <= #TCQ 1'b1;
phy_cas_n0 <= #TCQ 1'b1;
end
end
// Assert WE when: (1) Loading MRS, (2) Issuing Write command (only
// occur during read leveling), (3) Issuing ZQ Long Calib command,
// (4) Precharge
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE)||
(rdlvl_wr && new_burst_r))begin
phy_we_n1 <= #TCQ 1'b0;
phy_we_n0 <= #TCQ 1'b0;
end else begin
phy_we_n1 <= #TCQ 1'b1;
phy_we_n0 <= #TCQ 1'b1;
end
end
generate
genvar rnk_i;
for (rnk_i = 0; rnk_i < 4; rnk_i = rnk_i + 1) begin: gen_rnk
always @(posedge clk) begin
if (rst) begin
mr2_r[rnk_i] <= #TCQ 2'b00;
mr1_r[rnk_i] <= #TCQ 3'b000;
end else begin
mr2_r[rnk_i] <= #TCQ tmp_mr2_r[rnk_i];
mr1_r[rnk_i] <= #TCQ tmp_mr1_r[rnk_i];
end
end
end
endgenerate
// ODT assignment based on slot config and slot present
// Assuming CS_WIDTH equals number of ranks configured
// For single slot systems slot_1_present input will be ignored
// Assuming component interfaces to be single slot systems
generate
if (nSLOTS == 1) begin: gen_single_slot_odt
always @(posedge clk) begin
tmp_mr2_r[1] <= #TCQ 2'b00;
tmp_mr2_r[2] <= #TCQ 2'b00;
tmp_mr2_r[3] <= #TCQ 2'b00;
tmp_mr1_r[1] <= #TCQ 3'b000;
tmp_mr1_r[2] <= #TCQ 3'b000;
tmp_mr1_r[3] <= #TCQ 3'b000;
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
phy_tmp_odt0_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
phy_tmp_odt1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
phy_tmp_odt0_r1 <= #TCQ phy_tmp_odt0_r;
phy_tmp_odt1_r1 <= #TCQ phy_tmp_odt1_r;
case ({slot_0_present[0],slot_0_present[1],
slot_0_present[2],slot_0_present[3]})
// Single slot configuration with quad rank
// Assuming same behavior as single slot dual rank for now
// DDR2 does not have quad rank parts
4'b1111: begin
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
phy_tmp_odt0_r[nCS_PER_RANK-1:0] <= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[nCS_PER_RANK-1:0] <= #TCQ {nCS_PER_RANK{1'b1}};
// Chip Select assignments
phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK)
) +: nCS_PER_RANK] <= #TCQ 'b0;
end
// Single slot configuration with single rank
4'b1000: begin
phy_tmp_odt0_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
if ((REG_CTRL == "ON") && (nCS_PER_RANK > 1)) begin
phy_tmp_cs1_r[chip_cnt_r] <= #TCQ 1'b0;
end else begin
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
end
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
// Single slot configuration with dual rank
4'b1100: begin
phy_tmp_odt0_r[nCS_PER_RANK-1:0] <= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[nCS_PER_RANK-1:0] <= #TCQ {nCS_PER_RANK{1'b1}};
// Chip Select assignments
phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK)
) +: nCS_PER_RANK] <= #TCQ 'b0;
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
default: begin
phy_tmp_odt0_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
endcase
end
end else if (nSLOTS == 2) begin: gen_dual_slot_odt
always @ (posedge clk) begin
tmp_mr2_r[1] <= #TCQ 2'b00;
tmp_mr2_r[2] <= #TCQ 2'b00;
tmp_mr2_r[3] <= #TCQ 2'b00;
tmp_mr1_r[1] <= #TCQ 3'b000;
tmp_mr1_r[2] <= #TCQ 3'b000;
tmp_mr1_r[3] <= #TCQ 3'b000;
phy_tmp_odt0_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
phy_tmp_odt1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
phy_tmp_odt0_r1 <= #TCQ phy_tmp_odt0_r;
phy_tmp_odt1_r1 <= #TCQ phy_tmp_odt1_r;
case ({slot_0_present[0],slot_0_present[1],
slot_1_present[0],slot_1_present[1]})
// Two slot configuration, one slot present, single rank
4'b10_00: begin
if (wrlvl_odt || (init_state_r == INIT_IOCONFIG_WR_WAIT) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG2_WRITE) ||
(init_state_r == INIT_RDLVL_CLKDIV_WRITE)) begin
// odt turned on only during write
phy_tmp_odt0_r <= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r <= #TCQ {nCS_PER_RANK{1'b1}};
end
phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
4'b00_10: begin
//Rank1 ODT enabled
if (wrlvl_odt || (init_state_r == INIT_IOCONFIG_WR_WAIT) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG2_WRITE) ||
(init_state_r == INIT_RDLVL_CLKDIV_WRITE)) begin
// odt turned on only during write
phy_tmp_odt0_r <= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r <= #TCQ {nCS_PER_RANK{1'b1}};
end
phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank1 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
// Two slot configuration, one slot present, dual rank
4'b00_11: begin
if (wrlvl_odt || (init_state_r == INIT_IOCONFIG_WR_WAIT) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG2_WRITE) ||
(init_state_r == INIT_RDLVL_CLKDIV_WRITE)) begin
// odt turned on only during write
phy_tmp_odt0_r[nCS_PER_RANK-1:0]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[nCS_PER_RANK-1:0]
<= #TCQ {nCS_PER_RANK{1'b1}};
end
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
4'b11_00: begin
if (wrlvl_odt || (init_state_r == INIT_IOCONFIG_WR_WAIT) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG2_WRITE) ||
(init_state_r == INIT_RDLVL_CLKDIV_WRITE)) begin
// odt turned on only during write
phy_tmp_odt0_r[nCS_PER_RANK-1] <= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[nCS_PER_RANK-1] <= #TCQ {nCS_PER_RANK{1'b1}};
end
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank1 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
// Two slot configuration, one rank per slot
4'b10_10: begin
if (DRAM_TYPE == "DDR2")begin
if (chip_cnt_r == 2'b00)begin
phy_tmp_odt0_r[(0*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
phy_tmp_odt0_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(0*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
phy_tmp_odt1_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
end else begin
phy_tmp_odt0_r[(0*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt0_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
phy_tmp_odt1_r[(0*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
end
end else begin
if (wrlvl_odt || (init_state_r == INIT_IOCONFIG_WR_WAIT) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG2_WRITE) ||
(init_state_r == INIT_RDLVL_CLKDIV_WRITE)) begin
phy_tmp_odt0_r[(0*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt0_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(0*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
end else if ((init_state_r == INIT_IOCONFIG_RD_WAIT) ||
(init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_RDLVL_CLKDIV_READ)) begin
if (chip_cnt_r == 2'b00) begin
phy_tmp_odt0_r[(0*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
phy_tmp_odt0_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(0*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
phy_tmp_odt1_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
end else if (chip_cnt_r == 2'b01) begin
phy_tmp_odt0_r[(0*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt0_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
phy_tmp_odt1_r[(0*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
end
end
end
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "60") ? 3'b001 :
(RTT_NOM == "120") ? 3'b010 :
(RTT_NOM == "20") ? 3'b100 :
(RTT_NOM == "30") ? 3'b101 :
3'b011;
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "60") ? 3'b001 :
(RTT_NOM == "120") ? 3'b010 :
(RTT_NOM == "20") ? 3'b100 :
(RTT_NOM == "30") ? 3'b101 :
3'b011;
end
end
// Two Slots - One slot with dual rank and the other with single rank
4'b10_11: begin
//Rank3 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[2] <= #TCQ (RTT_NOM3 == "60") ? 3'b001 :
(RTT_NOM3 == "120") ? 3'b010 :
(RTT_NOM3 == "20") ? 3'b100 :
(RTT_NOM3 == "30") ? 3'b101 :
3'b011;
tmp_mr2_r[2] <= #TCQ 2'b00;
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "60") ? 3'b001 :
(RTT_NOM == "120") ? 3'b010 :
(RTT_NOM == "20") ? 3'b100 :
(RTT_NOM == "30") ? 3'b101 :
3'b011;
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM
tmp_mr1_r[1] <= #TCQ 3'b000;
end
//Slot1 Rank1 or Rank3 is being written
if (DRAM_TYPE == "DDR2")begin
if (chip_cnt_r == 2'b00)begin
phy_tmp_odt0_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
end else begin
phy_tmp_odt0_r[(0*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(0*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
end
end else begin
if (wrlvl_odt || (init_state_r == INIT_IOCONFIG_WR_WAIT) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG2_WRITE) ||
(init_state_r == INIT_RDLVL_CLKDIV_WRITE)) begin
if (chip_cnt_r[0] == 1'b1) begin
phy_tmp_odt0_r[(0*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(0*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt0_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
//Slot0 Rank0 is being written
end else begin
phy_tmp_odt0_r[(0*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(0*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt0_r[(2*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(2*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
end
end else if ((init_state_r == INIT_IOCONFIG_RD_WAIT) ||
(init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_RDLVL_CLKDIV_READ)) begin
if (chip_cnt_r == 2'b00) begin
phy_tmp_odt0_r[(2*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(2*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
end else begin
phy_tmp_odt0_r[(0*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(0*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
end
end
end
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
end
// Two Slots - One slot with dual rank and the other with single rank
4'b11_10: begin
//Rank2 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 :
(RTT_NOM2 == "120") ? 3'b010 :
(RTT_NOM2 == "20") ? 3'b100 :
(RTT_NOM2 == "30") ? 3'b101 :
3'b011;
tmp_mr2_r[2] <= #TCQ 2'b00;
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "60") ? 3'b001 :
(RTT_NOM == "120") ? 3'b010 :
(RTT_NOM == "20") ? 3'b100 :
(RTT_NOM == "30") ? 3'b101 :
3'b011;
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
if (DRAM_TYPE == "DDR2")begin
if (chip_cnt_r[1] == 1'b1)begin
phy_tmp_odt0_r[nCS_PER_RANK-1:0]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[nCS_PER_RANK-1:0]
<= #TCQ {nCS_PER_RANK{1'b1}};
end else begin
phy_tmp_odt0_r[(2*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(2*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
end
end else begin
if (wrlvl_odt || (init_state_r == INIT_IOCONFIG_WR_WAIT) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG2_WRITE) ||
(init_state_r == INIT_RDLVL_CLKDIV_WRITE)) begin
if (chip_cnt_r[1] == 1'b1) begin
phy_tmp_odt0_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt0_r[(2*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(2*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
end else begin
phy_tmp_odt0_r[nCS_PER_RANK-1:0]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[nCS_PER_RANK-1:0]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt0_r[(2*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(2*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
end
end else if ((init_state_r == INIT_IOCONFIG_RD_WAIT) ||
(init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_RDLVL_CLKDIV_READ)) begin
if (chip_cnt_r[1] == 1'b1) begin
phy_tmp_odt0_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
end else begin
phy_tmp_odt0_r[(2*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(2*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
end
end
end
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
end
// Two Slots - two ranks per slot
4'b11_11: begin
//Rank2 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 :
(RTT_NOM2 == "120") ? 3'b010 :
(RTT_NOM2 == "20") ? 3'b100 :
(RTT_NOM2 == "30") ? 3'b101 :
3'b011;
//Rank3 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[3] <= #TCQ (RTT_NOM3 == "60") ? 3'b001 :
(RTT_NOM3 == "120") ? 3'b010 :
(RTT_NOM3 == "20") ? 3'b100 :
(RTT_NOM3 == "30") ? 3'b101 :
3'b011;
tmp_mr2_r[2] <= #TCQ 2'b00;
tmp_mr2_r[3] <= #TCQ 2'b00;
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM
tmp_mr1_r[1] <= #TCQ 3'b000;
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end // else: !if((RTT_WR == "OFF") ||...
if(DRAM_TYPE == "DDR2")begin
if(chip_cnt_r[1] == 1'b1)begin
phy_tmp_odt0_r[(0*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(0*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
end else begin
phy_tmp_odt0_r[(2*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(2*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
end
end else begin
if (wrlvl_odt || (init_state_r == INIT_IOCONFIG_WR_WAIT) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG2_WRITE) ||
(init_state_r == INIT_RDLVL_CLKDIV_WRITE)) begin
//Slot1 Rank1 or Rank3 is being written
if (chip_cnt_r[0] == 1'b1) begin
phy_tmp_odt0_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt0_r[(2*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(2*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
//Slot0 Rank0 or Rank2 is being written
end else begin
phy_tmp_odt0_r[(0*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(0*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt0_r[(3*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(3*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
end
end else if ((init_state_r == INIT_IOCONFIG_RD_WAIT) ||
(init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_RDLVL_CLKDIV_READ)) begin
//Slot1 Rank1 or Rank3 is being read
if (chip_cnt_r[0] == 1'b1) begin
phy_tmp_odt0_r[(2*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(2*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
//Slot0 Rank0 or Rank2 is being read
end else begin
phy_tmp_odt0_r[(3*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
phy_tmp_odt1_r[(3*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b1}};
end
end // if (init_state_r == INIT_IOCONFIG_RD)
end // else: !if(DRAM_TYPE == "DDR2")
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
end
default: begin
phy_tmp_odt0_r <= #TCQ {nCS_PER_RANK*CS_WIDTH{1'b1}};
phy_tmp_odt1_r <= #TCQ {nCS_PER_RANK*CS_WIDTH{1'b1}};
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "60") ? 3'b001 :
(RTT_NOM == "120") ? 3'b010 :
(RTT_NOM == "20") ? 3'b100 :
(RTT_NOM == "30") ? 3'b101 :
3'b011;
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "60") ? 3'b001 :
(RTT_NOM == "120") ? 3'b010 :
(RTT_NOM == "20") ? 3'b100 :
(RTT_NOM == "30") ? 3'b101 :
3'b011;
end
end
endcase
end
end
endgenerate
// Assert ODT when: (1) Write Leveling, (2) Issuing Write command
// Timing of ODT is not particularly precise (i.e. does not turn
// on right before write data, and turn off immediately after
// write is finished), but it doesn't have to be
generate
if (nSLOTS == 1) begin
always @(posedge clk)
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) ||
(wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3"))begin
phy_odt0 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
phy_odt1 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
end
else if (((DRAM_TYPE == "DDR3")
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
&& ((wrlvl_odt) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG1_WRITE_READ) ||
(init_state_r == INIT_RDLVL_STG2_WRITE) ||
(init_state_r == INIT_RDLVL_STG2_WRITE_READ) ||
(init_state_r == INIT_RDLVL_CLKDIV_WRITE) ||
(init_state_r == INIT_RDLVL_CLKDIV_WRITE_READ))) begin
phy_odt0 <= #TCQ phy_tmp_odt0_r;
phy_odt1 <= #TCQ phy_tmp_odt1_r;
end else begin
phy_odt0 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
phy_odt1 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
end
end else if (nSLOTS == 2) begin
always @(posedge clk)
if (((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) ||
wrlvl_rank_done || wrlvl_rank_done_r1 ||
(wrlvl_done && !wrlvl_done_r)) begin
phy_odt0 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
phy_odt1 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
end
else if (((DRAM_TYPE == "DDR3")
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
&& ((wrlvl_odt_r1) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG1_WRITE_READ) ||
(init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_RDLVL_CLKDIV_WRITE) ||
(init_state_r == INIT_RDLVL_CLKDIV_WRITE_READ) ||
(init_state_r == INIT_RDLVL_CLKDIV_READ) ||
(init_state_r == INIT_RDLVL_STG2_WRITE) ||
(init_state_r == INIT_RDLVL_STG2_WRITE_READ) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_RDLVL_STG2_READ_WAIT) ||
(init_state_r == INIT_PRECHARGE_PREWAIT))) begin
phy_odt0 <= #TCQ phy_tmp_odt0_r | phy_tmp_odt0_r1;
phy_odt1 <= #TCQ phy_tmp_odt1_r | phy_tmp_odt1_r1 ;
end else begin
phy_odt0 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
phy_odt1 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
end
end
endgenerate
//*****************************************************************
// memory address during init
//*****************************************************************
always @(burst_addr_r or cnt_init_mr_r or chip_cnt_r
or ddr2_refresh_flag_r or init_state_r or load_mr0
or load_mr1 or load_mr2 or load_mr3 or mr1_r[chip_cnt_r][0]
or mr1_r[chip_cnt_r][1] or mr1_r[chip_cnt_r][2] or mr2_r[chip_cnt_r]
or rdlvl_done or rdlvl_wr_rd or reg_ctrl_cnt_r)begin
// Bus 0 for address/bank never used
address_w = 'b0;
bank_w = 'b0;
if ((init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_DDR2_PRECHARGE)) begin
// Set A10=1 for ZQ long calibration or Precharge All
address_w = 'b0;
address_w[10] = 1'b1;
bank_w = 'b0;
end else if (init_state_r == INIT_WRLVL_START) begin
// Enable wrlvl in MR1
bank_w[1:0] = 2'b01;
address_w = load_mr1[ROW_WIDTH-1:0];
address_w[7] = 1'b1;
end else if (init_state_r == INIT_WRLVL_LOAD_MR) begin
// Finished with write leveling, disable wrlvl in MR1
// For single rank disable Rtt_Nom
bank_w[1:0] = 2'b01;
address_w = load_mr1[ROW_WIDTH-1:0];
address_w[2] = mr1_r[chip_cnt_r][0];
address_w[6] = mr1_r[chip_cnt_r][1];
address_w[9] = mr1_r[chip_cnt_r][2];
end else if (init_state_r == INIT_WRLVL_LOAD_MR2) begin
// Set RTT_WR in MR2 after write leveling disabled
bank_w[1:0] = 2'b10;
address_w = load_mr2[ROW_WIDTH-1:0];
address_w[10:9] = mr2_r[chip_cnt_r];
end else if ((init_state_r == INIT_REG_WRITE)&
(DRAM_TYPE == "DDR3"))begin
// bank_w is assigned a 3 bit value. In some
// DDR2 cases there will be only two bank bits.
//Qualifying the condition with DDR3
bank_w = 'b0;
address_w = 'b0;
case (reg_ctrl_cnt_r)
REG_RC0[2:0]: address_w[4:0] = REG_RC0[4:0];
REG_RC1[2:0]:begin
address_w[4:0] = REG_RC1[4:0];
bank_w = REG_RC1[7:5];
end
REG_RC2[2:0]: address_w[4:0] = REG_RC2[4:0];
REG_RC3[2:0]: address_w[4:0] = REG_RC3[4:0];
REG_RC4[2:0]: address_w[4:0] = REG_RC4[4:0];
REG_RC5[2:0]: address_w[4:0] = REG_RC5[4:0];
endcase
end else if (init_state_r == INIT_LOAD_MR) begin
// If loading mode register, look at cnt_init_mr to determine
// which MR is currently being programmed
address_w = 'b0;
bank_w = 'b0;
if(DRAM_TYPE == "DDR3")begin
if(&rdlvl_done)begin
// end of the calibration programming correct
// burst length
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
address_w[8]= 1'b0; //Don't reset DLL
end else begin
case (cnt_init_mr_r)
INIT_CNT_MR2: begin
bank_w[1:0] = 2'b10;
address_w = load_mr2[ROW_WIDTH-1:0];
address_w[10:9] = mr2_r[chip_cnt_r];
end
INIT_CNT_MR3: begin
bank_w[1:0] = 2'b11;
address_w = load_mr3[ROW_WIDTH-1:0];
end
INIT_CNT_MR1: begin
bank_w[1:0] = 2'b01;
address_w = load_mr1[ROW_WIDTH-1:0];
address_w[2] = mr1_r[chip_cnt_r][0];
address_w[6] = mr1_r[chip_cnt_r][1];
address_w[9] = mr1_r[chip_cnt_r][2];
end
INIT_CNT_MR0: begin
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
// fixing it to BL8 for calibration
address_w[1:0] = 2'b00;
end
default: begin
bank_w = {BANK_WIDTH{1'bx}};
address_w = {ROW_WIDTH{1'bx}};
end
endcase // case(cnt_init_mr_r)
end // else: !if(&rdlvl_done)
end else begin // DDR2
case (cnt_init_mr_r)
INIT_CNT_MR2: begin
if(~ddr2_refresh_flag_r)begin
bank_w[1:0] = 2'b10;
address_w = load_mr2[ROW_WIDTH-1:0];
end else begin // second set of lm commands
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
address_w[8]= 1'b0;
//MRS command without resetting DLL
end
end
INIT_CNT_MR3: begin
if(~ddr2_refresh_flag_r)begin
bank_w[1:0] = 2'b11;
address_w = load_mr3[ROW_WIDTH-1:0];
end else begin // second set of lm commands
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
address_w[8]= 1'b0;
//MRS command without resetting DLL. Repeted again
// because there is an extra state.
end
end
INIT_CNT_MR1: begin
bank_w[1:0] = 2'b01;
if(~ddr2_refresh_flag_r)begin
address_w = load_mr1[ROW_WIDTH-1:0];
end else begin // second set of lm commands
address_w = load_mr1[ROW_WIDTH-1:0];
address_w[9:7] = 3'b111;
//OCD default state
end
end
INIT_CNT_MR0: begin
if(~ddr2_refresh_flag_r)begin
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
end else begin // second set of lm commands
bank_w[1:0] = 2'b01;
address_w = load_mr1[ROW_WIDTH-1:0];
if((chip_cnt_r == 2'd1) || (chip_cnt_r == 2'd3))begin
// always disable odt for rank 1 and rank 3 as per SPEC
address_w[2] = 'b0;
address_w[6] = 'b0;
end
//OCD exit
end
end
default: begin
bank_w = {BANK_WIDTH{1'bx}};
address_w = {ROW_WIDTH{1'bx}};
end
endcase // case(cnt_init_mr_r)
end
end else if (rdlvl_wr_rd) begin
// when writing or reading back training pattern for read leveling
// need to support both burst length of 4 or 8. This may mean issuing
// multiple commands to cover the entire range of addresses accessed
// during read leveling.
// Hard coding A[12] to 1 so that it will always be burst length of 8
// for DDR3. Does not have any effect on DDR2.
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};
address_w[COL_WIDTH-1:0] =
{CALIB_COL_ADD[COL_WIDTH-1:4],burst_addr_r, 2'b00};
address_w[12] = 1'b1;
address_w[10] = 1'b0;
end else if ((init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_PD_ACT)) begin
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
address_w = CALIB_ROW_ADD[ROW_WIDTH-1:0];
end else begin
bank_w = {BANK_WIDTH{1'bx}};
address_w = {ROW_WIDTH{1'bx}};
end
end
// registring before sending out
always @(posedge clk) begin
phy_bank0 <= #TCQ bank_w;
phy_address0 <= #TCQ address_w;
phy_bank1 <= #TCQ bank_w;
phy_address1 <= #TCQ address_w;
end
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_always_assert
assert_always_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_always_assume
assert_always_assume (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_always.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_always_assert (clk, reset_n, test_expr, xzcheck_enable);
input clk, reset_n, test_expr, xzcheck_enable;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_always_assume (clk, reset_n, test_expr, xzcheck_enable);
input clk, reset_n, test_expr, xzcheck_enable;
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_nios2_gen2_0_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
niosii_nios2_gen2_0_cpu_debug_slave_tck the_niosii_nios2_gen2_0_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
niosii_nios2_gen2_0_cpu_debug_slave_sysclk the_niosii_nios2_gen2_0_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic niosii_nios2_gen2_0_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_instance_index = 0,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_ir_width = 2,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_mfg_id = 70,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_action = "",
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_total_length = 0,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_type_id = 34,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t;
reg signed [20:0] longp; initial longp = 21'shbbccc;
reg signed [20:0] longn; initial longn = 21'shbbccc; initial longn[20]=1'b1;
reg signed [40:0] quadp; initial quadp = 41'sh1_bbbb_cccc;
reg signed [40:0] quadn; initial quadn = 41'sh1_bbbb_cccc; initial quadn[40]=1'b1;
reg signed [80:0] widep; initial widep = 81'shbc_1234_5678_1234_5678;
reg signed [80:0] widen; initial widen = 81'shbc_1234_5678_1234_5678; initial widen[40]=1'b1;
initial begin
// Display formatting
$display("[%0t] lp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
longp, longp, longp, longp, longp, longp);
$display("[%0t] ln %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
longn, longn, longn, longn, longn, longn);
$display("[%0t] qp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
quadp, quadp, quadp, quadp, quadp, quadp);
$display("[%0t] qn %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
quadn, quadn, quadn, quadn, quadn, quadn);
$display("[%0t] wp %%x=%x %%x=%x %%o=%o %%b=%b", $time,
widep, widep, widep, widep);
$display("[%0t] wn %%x=%x %%x=%x %%o=%o %%b=%b", $time,
widen, widen, widen, widen);
$display;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Store Buffer FIFO ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Implementation of store buffer FIFO. ////
//// ////
//// To Do: ////
//// - N/A ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_sb_fifo.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// No update
//
// Revision 1.3 2002/11/06 13:53:41 simons
// SB mem width fixed.
//
// Revision 1.2 2002/08/22 02:18:55 lampret
// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
//
// Revision 1.1 2002/08/18 19:53:08 lampret
// Added store buffer.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_sb_fifo(
clk_i, rst_i, dat_i, wr_i, rd_i, dat_o, full_o, empty_o
);
parameter dw = 68;
parameter fw = `OR1200_SB_LOG;
parameter fl = `OR1200_SB_ENTRIES;
//
// FIFO signals
//
input clk_i; // Clock
input rst_i; // Reset
input [dw-1:0] dat_i; // Input data bus
input wr_i; // Write request
input rd_i; // Read request
output [dw-1:0] dat_o; // Output data bus
output full_o; // FIFO full
output empty_o;// FIFO empty
//
// Internal regs
//
reg [dw-1:0] mem [fl-1:0];
reg [dw-1:0] dat_o;
reg [fw+1:0] cntr;
reg [fw-1:0] wr_pntr;
reg [fw-1:0] rd_pntr;
reg empty_o;
reg full_o;
always @(posedge clk_i or `OR1200_RST_EVENT rst_i)
if (rst_i == `OR1200_RST_VALUE) begin
full_o <= 1'b0;
empty_o <= 1'b1;
wr_pntr <= {fw{1'b0}};
rd_pntr <= {fw{1'b0}};
cntr <= {fw+2{1'b0}};
dat_o <= {dw{1'b0}};
end
else if (wr_i && rd_i) begin // FIFO Read and Write
mem[wr_pntr] <= dat_i;
if (wr_pntr >= fl-1)
wr_pntr <= {fw{1'b0}};
else
wr_pntr <= wr_pntr + 1'b1;
if (empty_o) begin
dat_o <= dat_i;
end
else begin
dat_o <= mem[rd_pntr];
end
if (rd_pntr >= fl-1)
rd_pntr <= {fw{1'b0}};
else
rd_pntr <= rd_pntr + 1'b1;
end
else if (wr_i && !full_o) begin // FIFO Write
mem[wr_pntr] <= dat_i;
cntr <= cntr + 1'b1;
empty_o <= 1'b0;
if (cntr >= (fl-1)) begin
full_o <= 1'b1;
cntr <= fl;
end
if (wr_pntr >= fl-1)
wr_pntr <= {fw{1'b0}};
else
wr_pntr <= wr_pntr + 1'b1;
end
else if (rd_i && !empty_o) begin // FIFO Read
dat_o <= mem[rd_pntr];
cntr <= cntr - 1'b1;
full_o <= 1'b0;
if (cntr <= 1) begin
empty_o <= 1'b1;
cntr <= {fw+2{1'b0}};
end
if (rd_pntr >= fl-1)
rd_pntr <= {fw{1'b0}};
else
rd_pntr <= rd_pntr + 1'b1;
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 7
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_auto_us_df_0 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_dwidth_converter_v2_1_7_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_FIFO_MODE(1),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*
ORSoC GFX accelerator core
Copyright 2012, ORSoC, Per Lenander, Anton Fosselius.
WBM reader
Loosely based on the vga lcds wishbone reader (LGPL) in orpsocv2 by Julius Baxter, [email protected]
This file is part of orgfx.
orgfx is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
orgfx is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public License
along with orgfx. If not, see <http://www.gnu.org/licenses/>.
*/
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
module gfx_wbm_read (clk_i, rst_i,
cyc_o, stb_o, cti_o, bte_o, we_o, adr_o, sel_o, ack_i, err_i, dat_i, sint_o,
read_request_i,
texture_addr_i, texture_sel_i, texture_dat_o, texture_data_ack);
// inputs & outputs
// wishbone signals
input clk_i; // master clock input
input rst_i; // asynchronous active high reset
output reg cyc_o; // cycle output
output stb_o; // strobe ouput
output [ 2:0] cti_o; // cycle type id
output [ 1:0] bte_o; // burst type extension
output we_o; // write enable output
output [31:0] adr_o; // address output
output reg [ 3:0] sel_o; // byte select outputs (only 32bits accesses are supported)
input ack_i; // wishbone cycle acknowledge
input err_i; // wishbone cycle error
input [31:0] dat_i; // wishbone data in
output sint_o; // non recoverable error, interrupt host
// Request stuff
input read_request_i;
input [31:2] texture_addr_i;
input [3:0] texture_sel_i;
output [31:0] texture_dat_o;
output reg texture_data_ack;
//
// variable declarations
//
reg busy;
//
// module body
//
assign adr_o = {texture_addr_i, 2'b00};
assign texture_dat_o = dat_i;
// This interface is read only
assign we_o = 1'b0;
assign stb_o = 1'b1;
assign sint_o = err_i;
assign bte_o = 2'b00;
assign cti_o = 3'b000;
always @(posedge clk_i or posedge rst_i)
if (rst_i) // Reset
begin
texture_data_ack <= 1'b0;
cyc_o <= 1'b0;
sel_o <= 4'b1111;
busy <= 1'b0;
end
else
begin
sel_o <= texture_sel_i;
if(ack_i) // On ack, stop current read, send ack to arbiter
begin
cyc_o <= 1'b0;
texture_data_ack <= 1'b1;
busy <= 1'b0;
end
else if(read_request_i & !texture_data_ack) // Else, is there a pending request? Start a read
begin
cyc_o <= 1'b1;
texture_data_ack <= 1'b0;
busy <= 1'b1;
end
else if(!busy) // Else, are we done? Zero ack
texture_data_ack <= 1'b0;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SREGSBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__SREGSBP_BEHAVIORAL_PP_V
/**
* sregsbp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_lp__udp_dff_ps_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sregsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
ASYNC,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input ASYNC;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire set ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire ASYNC_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (set , ASYNC_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, set, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( ASYNC_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( ASYNC === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SREGSBP_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_PP_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__ebufn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_PP_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_gclk_inv_r90_256x.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// --------------------------------------------------
// File: bw_clk_gclk_inv_r90_256x.behV
// --------------------------------------------------
//
module bw_clk_gclk_inv_r90_256x (
clkout,
clkin );
output clkout;
input clkin;
assign clkout = ~( clkin );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BAI_1_V
`define SKY130_FD_SC_LP__O21BAI_1_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21bai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o21bai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21bai_1 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21bai_1 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BAI_1_V
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: crossbar_sasd.v
//
// Description:
// This module is a M-master to N-slave AXI axi_crossbar_v2_1_crossbar switch.
// Single transaction issuing, single arbiter (both W&R), single data pathways.
// The interface of this module consists of a vectored slave and master interface
// in which all slots are sized and synchronized to the native width and clock
// of the interconnect, and are all AXI4 protocol.
// All width, clock and protocol conversions are done outside this block, as are
// any pipeline registers or data FIFOs.
// This module contains all arbitration, decoders and channel multiplexing logic.
// It also contains the diagnostic registers and control interface.
//
//--------------------------------------------------------------------------
//
// Structure:
// crossbar_sasd
// addr_arbiter_sasd
// mux_enc
// addr_decoder
// comparator_static
// splitter
// mux_enc
// axic_register_slice
// decerr_slave
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_crossbar_sasd #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_SLAVE_SLOTS = 1,
parameter integer C_NUM_MASTER_SLOTS = 1,
parameter integer C_NUM_ADDR_RANGES = 1,
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_PROTOCOL = 0,
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b1}},
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}},
parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_BASE_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},
parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_HIGH_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_WRITE = {C_NUM_SLAVE_SLOTS{1'b1}},
parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_READ = {C_NUM_SLAVE_SLOTS{1'b1}},
parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_WRITE = {C_NUM_MASTER_SLOTS{1'b1}},
parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_READ = {C_NUM_MASTER_SLOTS{1'b1}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY = {C_NUM_SLAVE_SLOTS{32'h00000000}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE = {C_NUM_MASTER_SLOTS{32'h00000000}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}},
parameter integer C_R_REGISTER = 0,
parameter integer C_RANGE_CHECK = 0,
parameter integer C_ADDR_DECODE = 0,
parameter integer C_DEBUG = 1
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_AWLEN,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWSIZE,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWBURST,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWLOCK,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWCACHE,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWPROT,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWREGION,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWQOS,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WLAST,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_BRESP,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BVALID,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_ARLEN,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARSIZE,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARBURST,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARLOCK,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARCACHE,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARPROT,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARREGION,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARQOS,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_RRESP,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RLAST,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RVALID,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_AWLEN,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWSIZE,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWBURST,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWLOCK,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWCACHE,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWPROT,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWREGION,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWQOS,
output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWVALID,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WLAST,
output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WVALID,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_BID, // Unused
input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_BRESP,
input wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BVALID,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_ARLEN,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARSIZE,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARBURST,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARLOCK,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARCACHE,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARPROT,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARREGION,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARQOS,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARVALID,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_RID, // Unused
input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_RRESP,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RLAST,
input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RVALID,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RREADY
);
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
localparam integer P_NUM_MASTER_SLOTS_DE = C_RANGE_CHECK ? C_NUM_MASTER_SLOTS+1 : C_NUM_MASTER_SLOTS;
localparam integer P_NUM_MASTER_SLOTS_LOG = (C_NUM_MASTER_SLOTS>1) ? f_ceil_log2(C_NUM_MASTER_SLOTS) : 1;
localparam integer P_NUM_MASTER_SLOTS_DE_LOG = (P_NUM_MASTER_SLOTS_DE>1) ? f_ceil_log2(P_NUM_MASTER_SLOTS_DE) : 1;
localparam integer P_NUM_SLAVE_SLOTS_LOG = (C_NUM_SLAVE_SLOTS>1) ? f_ceil_log2(C_NUM_SLAVE_SLOTS) : 1;
localparam integer P_AXI_AUSER_WIDTH = (C_AXI_AWUSER_WIDTH > C_AXI_ARUSER_WIDTH) ? C_AXI_AWUSER_WIDTH : C_AXI_ARUSER_WIDTH;
localparam integer P_AXI_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 1;
localparam integer P_AMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+2+4+4 + P_AXI_AUSER_WIDTH + 4;
localparam integer P_BMESG_WIDTH = 2 + C_AXI_BUSER_WIDTH;
localparam integer P_RMESG_WIDTH = 1+2 + C_AXI_DATA_WIDTH + C_AXI_RUSER_WIDTH;
localparam integer P_WMESG_WIDTH = 1 + C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_WUSER_WIDTH + P_AXI_WID_WIDTH;
localparam [31:0] P_AXILITE_ERRMODE = 32'h00000001;
localparam integer P_NONSECURE_BIT = 1;
localparam [C_NUM_MASTER_SLOTS-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE); // Mask of secure MI-slots
localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXILITE_MASK = f_m_axilite(0); // Mask of axilite rule-check MI-slots
localparam [1:0] P_FIXED = 2'b00;
localparam integer P_BYPASS = 0;
localparam integer P_LIGHTWT = 7;
localparam integer P_FULLY_REG = 1;
localparam integer P_R_REG_CONFIG = C_R_REGISTER == 8 ? // "Automatic" reg-slice
(C_RANGE_CHECK ? ((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHTWT : P_FULLY_REG) : P_BYPASS) : // Bypass if no R-channel mux
C_R_REGISTER;
localparam P_DECERR = 2'b11;
//---------------------------------------------------------------------------
// Functions
//---------------------------------------------------------------------------
// Ceiling of log2(x)
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// Isolate thread bits of input S_ID and add to BASE_ID (RNG00) to form MI-side ID value
// only for end-point SI-slots
function [C_AXI_ID_WIDTH-1:0] f_extend_ID
(
input [C_AXI_ID_WIDTH-1:0] s_id,
input integer slot
);
begin
f_extend_ID = C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] | (s_id & (C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] ^ C_S_AXI_HIGH_ID[slot*64+:C_AXI_ID_WIDTH]));
end
endfunction
// Convert Bit32 vector of range [0,1] to Bit1 vector on MI
function [C_NUM_MASTER_SLOTS-1:0] f_bit32to1_mi
(input [C_NUM_MASTER_SLOTS*32-1:0] vec32);
integer mi;
begin
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
f_bit32to1_mi[mi] = vec32[mi*32];
end
end
endfunction
// AxiLite error-checking mask (on MI)
function [C_NUM_MASTER_SLOTS-1:0] f_m_axilite
(
input integer null_arg
);
integer mi;
begin
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
f_m_axilite[mi] = (C_M_AXI_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE);
end
end
endfunction
genvar gen_si_slot;
genvar gen_mi_slot;
wire [C_NUM_SLAVE_SLOTS*P_AMESG_WIDTH-1:0] si_awmesg ;
wire [C_NUM_SLAVE_SLOTS*P_AMESG_WIDTH-1:0] si_armesg ;
wire [P_AMESG_WIDTH-1:0] aa_amesg ;
wire [C_AXI_ID_WIDTH-1:0] mi_aid ;
wire [C_AXI_ADDR_WIDTH-1:0] mi_aaddr ;
wire [8-1:0] mi_alen ;
wire [3-1:0] mi_asize ;
wire [2-1:0] mi_alock ;
wire [3-1:0] mi_aprot ;
wire [2-1:0] mi_aburst ;
wire [4-1:0] mi_acache ;
wire [4-1:0] mi_aregion ;
wire [4-1:0] mi_aqos ;
wire [P_AXI_AUSER_WIDTH-1:0] mi_auser ;
wire [4-1:0] target_region ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] aa_grant_hot ;
wire [P_NUM_SLAVE_SLOTS_LOG-1:0] aa_grant_enc ;
wire aa_grant_rnw ;
wire aa_grant_any ;
wire [C_NUM_MASTER_SLOTS-1:0] target_mi_hot ;
wire [P_NUM_MASTER_SLOTS_LOG-1:0] target_mi_enc ;
reg [P_NUM_MASTER_SLOTS_DE-1:0] m_atarget_hot ;
reg [P_NUM_MASTER_SLOTS_DE_LOG-1:0] m_atarget_enc ;
wire [P_NUM_MASTER_SLOTS_DE_LOG-1:0] m_atarget_enc_comb ;
wire match;
wire any_error ;
wire [7:0] m_aerror_i ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_awvalid ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_awready ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_arvalid ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_arready ;
wire aa_awvalid ;
wire aa_awready ;
wire aa_arvalid ;
wire aa_arready ;
wire mi_awvalid_en;
wire mi_awready_mux;
wire mi_arvalid_en;
wire mi_arready_mux;
wire w_transfer_en;
wire w_complete_mux;
wire b_transfer_en;
wire b_complete_mux;
wire r_transfer_en;
wire r_complete_mux;
wire target_secure;
wire target_write;
wire target_read;
wire target_axilite;
wire [P_BMESG_WIDTH-1:0] si_bmesg ;
wire [P_NUM_MASTER_SLOTS_DE*P_BMESG_WIDTH-1:0] mi_bmesg ;
wire [P_NUM_MASTER_SLOTS_DE*2-1:0] mi_bresp ;
wire [P_NUM_MASTER_SLOTS_DE*C_AXI_BUSER_WIDTH-1:0] mi_buser ;
wire [2-1:0] si_bresp ;
wire [C_AXI_BUSER_WIDTH-1:0] si_buser ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_bvalid ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_bready ;
wire aa_bvalid ;
wire aa_bready ;
wire si_bready ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_bvalid;
wire [P_RMESG_WIDTH-1:0] aa_rmesg ;
wire [P_RMESG_WIDTH-1:0] sr_rmesg ;
wire [P_NUM_MASTER_SLOTS_DE*P_RMESG_WIDTH-1:0] mi_rmesg ;
wire [P_NUM_MASTER_SLOTS_DE*2-1:0] mi_rresp ;
wire [P_NUM_MASTER_SLOTS_DE*C_AXI_RUSER_WIDTH-1:0] mi_ruser ;
wire [P_NUM_MASTER_SLOTS_DE*C_AXI_DATA_WIDTH-1:0] mi_rdata ;
wire [P_NUM_MASTER_SLOTS_DE*1-1:0] mi_rlast ;
wire [2-1:0] si_rresp ;
wire [C_AXI_RUSER_WIDTH-1:0] si_ruser ;
wire [C_AXI_DATA_WIDTH-1:0] si_rdata ;
wire si_rlast ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_rvalid ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_rready ;
wire aa_rvalid ;
wire aa_rready ;
wire sr_rvalid ;
wire si_rready ;
wire sr_rready ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_rvalid;
wire [C_NUM_SLAVE_SLOTS*P_WMESG_WIDTH-1:0] si_wmesg ;
wire [P_WMESG_WIDTH-1:0] mi_wmesg ;
wire [C_AXI_ID_WIDTH-1:0] mi_wid ;
wire [C_AXI_DATA_WIDTH-1:0] mi_wdata ;
wire [C_AXI_DATA_WIDTH/8-1:0] mi_wstrb ;
wire [C_AXI_WUSER_WIDTH-1:0] mi_wuser ;
wire [1-1:0] mi_wlast ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_wvalid ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_wready ;
wire aa_wvalid ;
wire aa_wready ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_wready;
reg [7:0] debug_r_beat_cnt_i;
reg [7:0] debug_w_beat_cnt_i;
reg [7:0] debug_aw_trans_seq_i;
reg [7:0] debug_ar_trans_seq_i;
reg aresetn_d = 1'b0; // Reset delay register
always @(posedge ACLK) begin
if (~ARESETN) begin
aresetn_d <= 1'b0;
end else begin
aresetn_d <= ARESETN;
end
end
wire reset;
assign reset = ~aresetn_d;
generate
axi_crossbar_v2_1_addr_arbiter_sasd #
(
.C_FAMILY (C_FAMILY),
.C_NUM_S (C_NUM_SLAVE_SLOTS),
.C_NUM_S_LOG (P_NUM_SLAVE_SLOTS_LOG),
.C_AMESG_WIDTH (P_AMESG_WIDTH),
.C_GRANT_ENC (1),
.C_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY)
)
addr_arbiter_inst
(
.ACLK (ACLK),
.ARESET (reset),
// Vector of SI-side AW command request inputs
.S_AWMESG (si_awmesg),
.S_ARMESG (si_armesg),
.S_AWVALID (S_AXI_AWVALID),
.S_AWREADY (S_AXI_AWREADY),
.S_ARVALID (S_AXI_ARVALID),
.S_ARREADY (S_AXI_ARREADY),
.M_GRANT_ENC (aa_grant_enc),
.M_GRANT_HOT (aa_grant_hot), // SI-slot 1-hot mask of granted command
.M_GRANT_ANY (aa_grant_any),
.M_GRANT_RNW (aa_grant_rnw),
.M_AMESG (aa_amesg), // Either S_AWMESG or S_ARMESG, as indicated by M_AWVALID and M_ARVALID.
.M_AWVALID (aa_awvalid),
.M_AWREADY (aa_awready),
.M_ARVALID (aa_arvalid),
.M_ARREADY (aa_arready)
);
if (C_ADDR_DECODE) begin : gen_addr_decoder
axi_crossbar_v2_1_addr_decoder #
(
.C_FAMILY (C_FAMILY),
.C_NUM_TARGETS (C_NUM_MASTER_SLOTS),
.C_NUM_TARGETS_LOG (P_NUM_MASTER_SLOTS_LOG),
.C_NUM_RANGES (C_NUM_ADDR_RANGES),
.C_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_TARGET_ENC (1),
.C_TARGET_HOT (1),
.C_REGION_ENC (1),
.C_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_HIGH_ADDR (C_M_AXI_HIGH_ADDR),
.C_TARGET_QUAL ({C_NUM_MASTER_SLOTS{1'b1}}),
.C_RESOLUTION (2)
)
addr_decoder_inst
(
.ADDR (mi_aaddr),
.TARGET_HOT (target_mi_hot),
.TARGET_ENC (target_mi_enc),
.MATCH (match),
.REGION (target_region)
);
end else begin : gen_no_addr_decoder
assign target_mi_hot = 1;
assign match = 1'b1;
assign target_region = 4'b0000;
end // gen_addr_decoder
// AW-channel arbiter command transfer completes upon completion of both M-side AW-channel transfer and B channel completion.
axi_crossbar_v2_1_splitter #
(
.C_NUM_M (3)
)
splitter_aw
(
.ACLK (ACLK),
.ARESET (reset),
.S_VALID (aa_awvalid),
.S_READY (aa_awready),
.M_VALID ({mi_awvalid_en, w_transfer_en, b_transfer_en}),
.M_READY ({mi_awready_mux, w_complete_mux, b_complete_mux})
);
// AR-channel arbiter command transfer completes upon completion of both M-side AR-channel transfer and R channel completion.
axi_crossbar_v2_1_splitter #
(
.C_NUM_M (2)
)
splitter_ar
(
.ACLK (ACLK),
.ARESET (reset),
.S_VALID (aa_arvalid),
.S_READY (aa_arready),
.M_VALID ({mi_arvalid_en, r_transfer_en}),
.M_READY ({mi_arready_mux, r_complete_mux})
);
assign target_secure = |(target_mi_hot & P_M_SECURE_MASK);
assign target_write = |(target_mi_hot & C_M_AXI_SUPPORTS_WRITE);
assign target_read = |(target_mi_hot & C_M_AXI_SUPPORTS_READ);
assign target_axilite = |(target_mi_hot & P_M_AXILITE_MASK);
assign any_error = C_RANGE_CHECK && (m_aerror_i != 0); // DECERR if error-detection enabled and any error condition.
assign m_aerror_i[0] = ~match; // Invalid target address
assign m_aerror_i[1] = target_secure && mi_aprot[P_NONSECURE_BIT]; // TrustZone violation
assign m_aerror_i[2] = target_axilite && ((mi_alen != 0) ||
(mi_asize[1:0] == 2'b11) || (mi_asize[2] == 1'b1)); // AxiLite access violation
assign m_aerror_i[3] = (~aa_grant_rnw && ~target_write) ||
(aa_grant_rnw && ~target_read); // R/W direction unsupported by target
assign m_aerror_i[7:4] = 4'b0000; // Reserved
assign m_atarget_enc_comb = any_error ? (P_NUM_MASTER_SLOTS_DE-1) : target_mi_enc; // Select MI slot or decerr_slave
always @(posedge ACLK) begin
if (reset) begin
m_atarget_hot <= 0;
m_atarget_enc <= 0;
end else begin
m_atarget_hot <= {P_NUM_MASTER_SLOTS_DE{aa_grant_any}} & (any_error ? {1'b1, {C_NUM_MASTER_SLOTS{1'b0}}} : {1'b0, target_mi_hot}); // Select MI slot or decerr_slave
m_atarget_enc <= m_atarget_enc_comb;
end
end
// Receive AWREADY from targeted MI.
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (P_NUM_MASTER_SLOTS_DE),
.C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG),
.C_DATA_WIDTH (1)
) mi_awready_mux_inst
(
.S (m_atarget_enc),
.A (mi_awready),
.O (mi_awready_mux),
.OE (mi_awvalid_en)
);
// Receive ARREADY from targeted MI.
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (P_NUM_MASTER_SLOTS_DE),
.C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG),
.C_DATA_WIDTH (1)
) mi_arready_mux_inst
(
.S (m_atarget_enc),
.A (mi_arready),
.O (mi_arready_mux),
.OE (mi_arvalid_en)
);
assign mi_awvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{mi_awvalid_en}}; // Assert AWVALID on targeted MI.
assign mi_arvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{mi_arvalid_en}}; // Assert ARVALID on targeted MI.
assign M_AXI_AWVALID = mi_awvalid[0+:C_NUM_MASTER_SLOTS]; // Propagate to MI slots.
assign M_AXI_ARVALID = mi_arvalid[0+:C_NUM_MASTER_SLOTS]; // Propagate to MI slots.
assign mi_awready[0+:C_NUM_MASTER_SLOTS] = M_AXI_AWREADY; // Copy from MI slots.
assign mi_arready[0+:C_NUM_MASTER_SLOTS] = M_AXI_ARREADY; // Copy from MI slots.
// Receive WREADY from targeted MI.
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (P_NUM_MASTER_SLOTS_DE),
.C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG),
.C_DATA_WIDTH (1)
) mi_wready_mux_inst
(
.S (m_atarget_enc),
.A (mi_wready),
.O (aa_wready),
.OE (w_transfer_en)
);
assign mi_wvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_wvalid}}; // Assert WVALID on targeted MI.
assign si_wready = aa_grant_hot & {C_NUM_SLAVE_SLOTS{aa_wready}}; // Assert WREADY on granted SI.
assign S_AXI_WREADY = si_wready;
assign w_complete_mux = aa_wready & aa_wvalid & mi_wlast; // W burst complete on on designated SI/MI.
// Receive RREADY from granted SI.
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_SLAVE_SLOTS),
.C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG),
.C_DATA_WIDTH (1)
) si_rready_mux_inst
(
.S (aa_grant_enc),
.A (S_AXI_RREADY),
.O (si_rready),
.OE (r_transfer_en)
);
assign sr_rready = si_rready & r_transfer_en;
assign mi_rready = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_rready}}; // Assert RREADY on targeted MI.
assign si_rvalid = aa_grant_hot & {C_NUM_SLAVE_SLOTS{sr_rvalid}}; // Assert RVALID on granted SI.
assign S_AXI_RVALID = si_rvalid;
assign r_complete_mux = sr_rready & sr_rvalid & si_rlast; // R burst complete on on designated SI/MI.
// Receive BREADY from granted SI.
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_SLAVE_SLOTS),
.C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG),
.C_DATA_WIDTH (1)
) si_bready_mux_inst
(
.S (aa_grant_enc),
.A (S_AXI_BREADY),
.O (si_bready),
.OE (b_transfer_en)
);
assign aa_bready = si_bready & b_transfer_en;
assign mi_bready = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_bready}}; // Assert BREADY on targeted MI.
assign si_bvalid = aa_grant_hot & {C_NUM_SLAVE_SLOTS{aa_bvalid}}; // Assert BVALID on granted SI.
assign S_AXI_BVALID = si_bvalid;
assign b_complete_mux = aa_bready & aa_bvalid; // B transfer complete on on designated SI/MI.
for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_si_amesg
assign si_armesg[gen_si_slot*P_AMESG_WIDTH +: P_AMESG_WIDTH] = { // Concatenate from MSB to LSB
4'b0000,
// S_AXI_ARREGION[gen_si_slot*4+:4],
S_AXI_ARUSER[gen_si_slot*C_AXI_ARUSER_WIDTH +: C_AXI_ARUSER_WIDTH],
S_AXI_ARQOS[gen_si_slot*4+:4],
S_AXI_ARCACHE[gen_si_slot*4+:4],
S_AXI_ARBURST[gen_si_slot*2+:2],
S_AXI_ARPROT[gen_si_slot*3+:3],
S_AXI_ARLOCK[gen_si_slot*2+:2],
S_AXI_ARSIZE[gen_si_slot*3+:3],
S_AXI_ARLEN[gen_si_slot*8+:8],
S_AXI_ARADDR[gen_si_slot*C_AXI_ADDR_WIDTH +: C_AXI_ADDR_WIDTH],
f_extend_ID(S_AXI_ARID[gen_si_slot*C_AXI_ID_WIDTH +: C_AXI_ID_WIDTH], gen_si_slot)
};
assign si_awmesg[gen_si_slot*P_AMESG_WIDTH +: P_AMESG_WIDTH] = { // Concatenate from MSB to LSB
4'b0000,
// S_AXI_AWREGION[gen_si_slot*4+:4],
S_AXI_AWUSER[gen_si_slot*C_AXI_AWUSER_WIDTH +: C_AXI_AWUSER_WIDTH],
S_AXI_AWQOS[gen_si_slot*4+:4],
S_AXI_AWCACHE[gen_si_slot*4+:4],
S_AXI_AWBURST[gen_si_slot*2+:2],
S_AXI_AWPROT[gen_si_slot*3+:3],
S_AXI_AWLOCK[gen_si_slot*2+:2],
S_AXI_AWSIZE[gen_si_slot*3+:3],
S_AXI_AWLEN[gen_si_slot*8+:8],
S_AXI_AWADDR[gen_si_slot*C_AXI_ADDR_WIDTH +: C_AXI_ADDR_WIDTH],
f_extend_ID(S_AXI_AWID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)
};
end // gen_si_amesg
assign mi_aid = aa_amesg[0 +: C_AXI_ID_WIDTH];
assign mi_aaddr = aa_amesg[C_AXI_ID_WIDTH +: C_AXI_ADDR_WIDTH];
assign mi_alen = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +: 8];
assign mi_asize = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +: 3];
assign mi_alock = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +: 2];
assign mi_aprot = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +: 3];
assign mi_aburst = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +: 2];
assign mi_acache = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2 +: 4];
assign mi_aqos = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4 +: 4];
assign mi_auser = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4+4 +: P_AXI_AUSER_WIDTH];
assign mi_aregion = (C_ADDR_DECODE != 0) ? target_region : aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4+4+P_AXI_AUSER_WIDTH +: 4];
// Broadcast AW transfer payload to all MI-slots
assign M_AXI_AWID = {C_NUM_MASTER_SLOTS{mi_aid}};
assign M_AXI_AWADDR = {C_NUM_MASTER_SLOTS{mi_aaddr}};
assign M_AXI_AWLEN = {C_NUM_MASTER_SLOTS{mi_alen }};
assign M_AXI_AWSIZE = {C_NUM_MASTER_SLOTS{mi_asize}};
assign M_AXI_AWLOCK = {C_NUM_MASTER_SLOTS{mi_alock}};
assign M_AXI_AWPROT = {C_NUM_MASTER_SLOTS{mi_aprot}};
assign M_AXI_AWREGION = {C_NUM_MASTER_SLOTS{mi_aregion}};
assign M_AXI_AWBURST = {C_NUM_MASTER_SLOTS{mi_aburst}};
assign M_AXI_AWCACHE = {C_NUM_MASTER_SLOTS{mi_acache}};
assign M_AXI_AWQOS = {C_NUM_MASTER_SLOTS{mi_aqos }};
assign M_AXI_AWUSER = {C_NUM_MASTER_SLOTS{mi_auser[0+:C_AXI_AWUSER_WIDTH] }};
// Broadcast AR transfer payload to all MI-slots
assign M_AXI_ARID = {C_NUM_MASTER_SLOTS{mi_aid}};
assign M_AXI_ARADDR = {C_NUM_MASTER_SLOTS{mi_aaddr}};
assign M_AXI_ARLEN = {C_NUM_MASTER_SLOTS{mi_alen }};
assign M_AXI_ARSIZE = {C_NUM_MASTER_SLOTS{mi_asize}};
assign M_AXI_ARLOCK = {C_NUM_MASTER_SLOTS{mi_alock}};
assign M_AXI_ARPROT = {C_NUM_MASTER_SLOTS{mi_aprot}};
assign M_AXI_ARREGION = {C_NUM_MASTER_SLOTS{mi_aregion}};
assign M_AXI_ARBURST = {C_NUM_MASTER_SLOTS{mi_aburst}};
assign M_AXI_ARCACHE = {C_NUM_MASTER_SLOTS{mi_acache}};
assign M_AXI_ARQOS = {C_NUM_MASTER_SLOTS{mi_aqos }};
assign M_AXI_ARUSER = {C_NUM_MASTER_SLOTS{mi_auser[0+:C_AXI_ARUSER_WIDTH] }};
// W-channel MI handshakes
assign M_AXI_WVALID = mi_wvalid[0+:C_NUM_MASTER_SLOTS];
assign mi_wready[0+:C_NUM_MASTER_SLOTS] = M_AXI_WREADY;
// Broadcast W transfer payload to all MI-slots
assign M_AXI_WLAST = {C_NUM_MASTER_SLOTS{mi_wlast}};
assign M_AXI_WUSER = {C_NUM_MASTER_SLOTS{mi_wuser}};
assign M_AXI_WDATA = {C_NUM_MASTER_SLOTS{mi_wdata}};
assign M_AXI_WSTRB = {C_NUM_MASTER_SLOTS{mi_wstrb}};
assign M_AXI_WID = {C_NUM_MASTER_SLOTS{mi_wid}};
// Broadcast R transfer payload to all SI-slots
assign S_AXI_RLAST = {C_NUM_SLAVE_SLOTS{si_rlast}};
assign S_AXI_RRESP = {C_NUM_SLAVE_SLOTS{si_rresp}};
assign S_AXI_RUSER = {C_NUM_SLAVE_SLOTS{si_ruser}};
assign S_AXI_RDATA = {C_NUM_SLAVE_SLOTS{si_rdata}};
assign S_AXI_RID = {C_NUM_SLAVE_SLOTS{mi_aid}};
// Broadcast B transfer payload to all SI-slots
assign S_AXI_BRESP = {C_NUM_SLAVE_SLOTS{si_bresp}};
assign S_AXI_BUSER = {C_NUM_SLAVE_SLOTS{si_buser}};
assign S_AXI_BID = {C_NUM_SLAVE_SLOTS{mi_aid}};
if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux
// SI WVALID mux.
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_SLAVE_SLOTS),
.C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG),
.C_DATA_WIDTH (1)
) si_w_valid_mux_inst
(
.S (aa_grant_enc),
.A (S_AXI_WVALID),
.O (aa_wvalid),
.OE (w_transfer_en)
);
// SI W-channel payload mux
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_SLAVE_SLOTS),
.C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG),
.C_DATA_WIDTH (P_WMESG_WIDTH)
) si_w_payload_mux_inst
(
.S (aa_grant_enc),
.A (si_wmesg),
.O (mi_wmesg),
.OE (1'b1)
);
for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_wmesg
assign si_wmesg[gen_si_slot*P_WMESG_WIDTH+:P_WMESG_WIDTH] = { // Concatenate from MSB to LSB
((C_AXI_PROTOCOL == P_AXI3) ? f_extend_ID(S_AXI_WID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) : 1'b0),
S_AXI_WUSER[gen_si_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH],
S_AXI_WSTRB[gen_si_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8],
S_AXI_WDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH],
S_AXI_WLAST[gen_si_slot*1+:1]
};
end // gen_wmesg
assign mi_wlast = mi_wmesg[0];
assign mi_wdata = mi_wmesg[1 +: C_AXI_DATA_WIDTH];
assign mi_wstrb = mi_wmesg[1+C_AXI_DATA_WIDTH +: C_AXI_DATA_WIDTH/8];
assign mi_wuser = mi_wmesg[1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8 +: C_AXI_WUSER_WIDTH];
assign mi_wid = mi_wmesg[1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8+C_AXI_WUSER_WIDTH +: P_AXI_WID_WIDTH];
end else begin : gen_no_wmux
assign aa_wvalid = w_transfer_en & S_AXI_WVALID;
assign mi_wlast = S_AXI_WLAST;
assign mi_wdata = S_AXI_WDATA;
assign mi_wstrb = S_AXI_WSTRB;
assign mi_wuser = S_AXI_WUSER;
assign mi_wid = S_AXI_WID;
end // gen_wmux
// Receive RVALID from targeted MI.
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (P_NUM_MASTER_SLOTS_DE),
.C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG),
.C_DATA_WIDTH (1)
) mi_rvalid_mux_inst
(
.S (m_atarget_enc),
.A (mi_rvalid),
.O (aa_rvalid),
.OE (r_transfer_en)
);
// MI R-channel payload mux
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (P_NUM_MASTER_SLOTS_DE),
.C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG),
.C_DATA_WIDTH (P_RMESG_WIDTH)
) mi_rmesg_mux_inst
(
.S (m_atarget_enc),
.A (mi_rmesg),
.O (aa_rmesg),
.OE (1'b1)
);
axi_register_slice_v2_1_axic_register_slice #
(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (P_RMESG_WIDTH),
.C_REG_CONFIG (P_R_REG_CONFIG)
)
reg_slice_r
(
// System Signals
.ACLK(ACLK),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(aa_rmesg),
.S_VALID(aa_rvalid),
.S_READY(aa_rready),
// Master side
.M_PAYLOAD_DATA(sr_rmesg),
.M_VALID(sr_rvalid),
.M_READY(sr_rready)
);
assign mi_rvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_RVALID;
assign mi_rlast[0+:C_NUM_MASTER_SLOTS] = M_AXI_RLAST;
assign mi_rresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_RRESP;
assign mi_ruser[0+:C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH] = M_AXI_RUSER;
assign mi_rdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH] = M_AXI_RDATA;
assign M_AXI_RREADY = mi_rready[0+:C_NUM_MASTER_SLOTS];
for (gen_mi_slot=0; gen_mi_slot<P_NUM_MASTER_SLOTS_DE; gen_mi_slot=gen_mi_slot+1) begin : gen_rmesg
assign mi_rmesg[gen_mi_slot*P_RMESG_WIDTH+:P_RMESG_WIDTH] = { // Concatenate from MSB to LSB
mi_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH],
mi_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH],
mi_rresp[gen_mi_slot*2+:2],
mi_rlast[gen_mi_slot*1+:1]
};
end // gen_rmesg
assign si_rlast = sr_rmesg[0];
assign si_rresp = sr_rmesg[1 +: 2];
assign si_rdata = sr_rmesg[1+2 +: C_AXI_DATA_WIDTH];
assign si_ruser = sr_rmesg[1+2+C_AXI_DATA_WIDTH +: C_AXI_RUSER_WIDTH];
// Receive BVALID from targeted MI.
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (P_NUM_MASTER_SLOTS_DE),
.C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG),
.C_DATA_WIDTH (1)
) mi_bvalid_mux_inst
(
.S (m_atarget_enc),
.A (mi_bvalid),
.O (aa_bvalid),
.OE (b_transfer_en)
);
// MI B-channel payload mux
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (P_NUM_MASTER_SLOTS_DE),
.C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG),
.C_DATA_WIDTH (P_BMESG_WIDTH)
) mi_bmesg_mux_inst
(
.S (m_atarget_enc),
.A (mi_bmesg),
.O (si_bmesg),
.OE (1'b1)
);
assign mi_bvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_BVALID;
assign mi_bresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_BRESP;
assign mi_buser[0+:C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH] = M_AXI_BUSER;
assign M_AXI_BREADY = mi_bready[0+:C_NUM_MASTER_SLOTS];
for (gen_mi_slot=0; gen_mi_slot<P_NUM_MASTER_SLOTS_DE; gen_mi_slot=gen_mi_slot+1) begin : gen_bmesg
assign mi_bmesg[gen_mi_slot*P_BMESG_WIDTH+:P_BMESG_WIDTH] = { // Concatenate from MSB to LSB
mi_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH],
mi_bresp[gen_mi_slot*2+:2]
};
end // gen_bmesg
assign si_bresp = si_bmesg[0 +: 2];
assign si_buser = si_bmesg[2 +: C_AXI_BUSER_WIDTH];
if (C_DEBUG) begin : gen_debug_trans_seq
// DEBUG WRITE TRANSACTION SEQUENCE COUNTER
always @(posedge ACLK) begin
if (reset) begin
debug_aw_trans_seq_i <= 1;
end else begin
if (aa_awvalid && aa_awready) begin
debug_aw_trans_seq_i <= debug_aw_trans_seq_i + 1;
end
end
end
// DEBUG READ TRANSACTION SEQUENCE COUNTER
always @(posedge ACLK) begin
if (reset) begin
debug_ar_trans_seq_i <= 1;
end else begin
if (aa_arvalid && aa_arready) begin
debug_ar_trans_seq_i <= debug_ar_trans_seq_i + 1;
end
end
end
// DEBUG WRITE BEAT COUNTER
always @(posedge ACLK) begin
if (reset) begin
debug_w_beat_cnt_i <= 0;
end else if (aa_wready & aa_wvalid) begin
if (mi_wlast) begin
debug_w_beat_cnt_i <= 0;
end else begin
debug_w_beat_cnt_i <= debug_w_beat_cnt_i + 1;
end
end
end // Clocked process
// DEBUG READ BEAT COUNTER
always @(posedge ACLK) begin
if (reset) begin
debug_r_beat_cnt_i <= 0;
end else if (sr_rready & sr_rvalid) begin
if (si_rlast) begin
debug_r_beat_cnt_i <= 0;
end else begin
debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
end
end
end // Clocked process
end // gen_debug_trans_seq
if (C_RANGE_CHECK) begin : gen_decerr
// Highest MI-slot (index C_NUM_MASTER_SLOTS) is the error handler
axi_crossbar_v2_1_decerr_slave #
(
.C_AXI_ID_WIDTH (1),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_RESP (P_DECERR)
)
decerr_slave_inst
(
.S_AXI_ACLK (ACLK),
.S_AXI_ARESET (reset),
.S_AXI_AWID (1'b0),
.S_AXI_AWVALID (mi_awvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_AWREADY (mi_awready[C_NUM_MASTER_SLOTS]),
.S_AXI_WLAST (mi_wlast),
.S_AXI_WVALID (mi_wvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_WREADY (mi_wready[C_NUM_MASTER_SLOTS]),
.S_AXI_BID (),
.S_AXI_BRESP (mi_bresp[C_NUM_MASTER_SLOTS*2+:2]),
.S_AXI_BUSER (mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]),
.S_AXI_BVALID (mi_bvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_BREADY (mi_bready[C_NUM_MASTER_SLOTS]),
.S_AXI_ARID (1'b0),
.S_AXI_ARLEN (mi_alen),
.S_AXI_ARVALID (mi_arvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_ARREADY (mi_arready[C_NUM_MASTER_SLOTS]),
.S_AXI_RID (),
.S_AXI_RDATA (mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),
.S_AXI_RRESP (mi_rresp[C_NUM_MASTER_SLOTS*2+:2]),
.S_AXI_RUSER (mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]),
.S_AXI_RLAST (mi_rlast[C_NUM_MASTER_SLOTS]),
.S_AXI_RVALID (mi_rvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_RREADY (mi_rready[C_NUM_MASTER_SLOTS])
);
end // gen_decerr
endgenerate
endmodule
`default_nettype wire
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_ln1px_s5 (
enable, resetn,
clock,
dataa,
result);
input enable, resetn;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_ln1px_s5 inst ( .clk(clock),
.areset(1'b0),
.en(enable),
.a(dataa),
.q(sub_wire0));
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
// ghrd_10as066n2_ocm_0.v
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module ghrd_10as066n2_ocm_0 (
input wire clk, // clk1.clk
input wire reset, // reset1.reset
input wire reset_req, // .reset_req
input wire [17:0] address, // s1.address
input wire clken, // .clken
input wire chipselect, // .chipselect
input wire write, // .write
output wire [7:0] readdata, // .readdata
input wire [7:0] writedata // .writedata
);
ghrd_10as066n2_ocm_0_altera_avalon_onchip_memory2_171_ehvj5ii ocm_0 (
.clk (clk), // input, width = 1, clk1.clk
.address (address), // input, width = 18, s1.address
.clken (clken), // input, width = 1, .clken
.chipselect (chipselect), // input, width = 1, .chipselect
.write (write), // input, width = 1, .write
.readdata (readdata), // output, width = 8, .readdata
.writedata (writedata), // input, width = 8, .writedata
.reset (reset), // input, width = 1, reset1.reset
.reset_req (reset_req), // input, width = 1, .reset_req
.freeze (1'b0) // (terminated),
);
endmodule
|
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : user_logic.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 13, 2008 ** //
// ** Description : Newton Core ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : newton.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 13, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ** File : newton.v ** //
// ** Revision : 2 ** //
// ** Author : kaylangu ** //
// ** Date : August 19, 2008 ** //
// ** FileName : ** //
// ** Notes : 1. Remove temp signal ** //
// ** 2. Bit ReOrdering function change to for loop ** //
// ** 3. Modify IP2Bus_Data_int mux logic ** //
// ** 4. Modify IP2Bus_WrAck to include WrAck from BRAM ** //
// ** ** //
// ** File : user_logic.v ** //
// ** Revision : 3 ** //
// ** Author : kaylangu ** //
// ** Date : August 21, 2008 ** //
// ** FileName : ** //
// ** Notes : 1. Changed file name to user_logic.v to match EDK ** //
// ** ** //
// ** File : user_logic.v ** //
// ** Revision : 4 ** //
// ** Author : kaylangu ** //
// ** Date : August 23, 2008 ** //
// ** FileName : ** //
// ** Notes : 1. changed the six 16-bit BRAM to three 32-bit wide BRAM ** //
// ** ** //
// ** File : user_logic.v ** //
// ** Revision : 5 ** //
// ** Author : kaylangu ** //
// ** Date : September 2, 2008 ** //
// ** FileName : ** //
// ** Notes : 1. Un-ReOrder the bits ** //
// ** 2. Change address of BRAM to Bus2IP_Addr[20:29] ** //
// ** 3. Fix ordering of input and output signals to match EDK ** //
// ** 4. RAM2IP_RdAck changed to one clock pulse ** //
// ** 5. Delay CS signal to output data when RdAck is high ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module user_logic
(Bus2IP_Clk,
Bus2IP_Reset,
Bus2IP_Addr,
Bus2IP_CS,
Bus2IP_RNW,
Bus2IP_Data,
Bus2IP_BE,
Bus2IP_RdCE,
Bus2IP_WrCE,
IP2Bus_Data,
IP2Bus_RdAck,
IP2Bus_WrAck,
IP2Bus_Error,
IP2Bus_IntrEvent,
IP2WFIFO_RdReq,
IP2WFIFO_RdMark, // IP to WFIFO : mark beginning of packet being read
IP2WFIFO_RdRelease, // IP to WFIFO : return WFIFO to normal FIFO operation
IP2WFIFO_RdRestore, // IP to WFIFO : restore the WFIFO to the last packet mark
WFIFO2IP_Data,
WFIFO2IP_RdAck,
WFIFO2IP_AlmostEmpty,
WFIFO2IP_Empty,
WFIFO2IP_Occupancy // WFIFO to IP : WFIFO occupancy
);
//**************************************************************************//
//* Declarations *//
//**************************************************************************//
// DATA TYPE - PARAMETERS
parameter C_SLV_AWIDTH = 32;
parameter C_SLV_DWIDTH = 32;
parameter C_NUM_REG = 4;
parameter C_NUM_MEM = 3;
parameter C_NUM_INTR = 1;
// DATA TYPE - INPUTS AND OUTPUTS
input Bus2IP_Clk; // Bus to IP clock
input Bus2IP_Reset; // Bus to IP reset
input [0 : C_SLV_AWIDTH-1] Bus2IP_Addr; // Bus to IP address bus
input [0 : C_NUM_MEM-1] Bus2IP_CS; // Bus to IP chip select for user logic memory selection
input Bus2IP_RNW; // Bus to IP read/not write
input [0 : C_SLV_DWIDTH-1] Bus2IP_Data; // Bus to IP data bus
input [0 : C_SLV_DWIDTH/8-1] Bus2IP_BE; // Bus to IP byte enables
input [0 : C_NUM_REG-1] Bus2IP_RdCE; // Bus to IP read chip enable
input [0 : C_NUM_REG-1] Bus2IP_WrCE; // Bus to IP write chip enable
output [0 : C_SLV_DWIDTH-1] IP2Bus_Data; // IP to Bus data bus
output IP2Bus_RdAck; // IP to Bus read transfer acknowledgement
output IP2Bus_WrAck; // IP to Bus write transfer acknowledgement
output IP2Bus_Error; // IP to Bus error response
output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent; // IP to Bus interrupt event
output IP2WFIFO_RdReq; // IP to WFIFO : IP read request
output IP2WFIFO_RdMark;
output IP2WFIFO_RdRelease;
output IP2WFIFO_RdRestore;
input [0 : C_SLV_DWIDTH-1] WFIFO2IP_Data; // WFIFO to IP : WFIFO read data
input WFIFO2IP_RdAck; // WFIFO to IP : WFIFO read acknowledge
input WFIFO2IP_AlmostEmpty; // WFIFO to IP : WFIFO almost empty
input WFIFO2IP_Empty; // WFIFO to IP : WFIFO empty
input [0 : 9] WFIFO2IP_Occupancy;
// DATA TYPE - WIRES
wire [9:0] CPTR; // Pointer to BRAM Address
wire SYNC;
wire [15:0] RealOut1;
wire [15:0] ImagOut1;
wire [15:0] RealOut2;
wire [15:0] ImagOut2;
wire [15:0] RealOut3;
wire [15:0] ImagOut3;
wire FIR_WE;
wire [0:C_NUM_MEM-1] RAM_WE;
wire iReg2IP_RdAck;
wire iReg2IP_WrAck;
wire RAM2IP_WrAck;
wire [10:0] CPTR_1;
// For bit reordering
wire [31:0] Bus2IP_Data_int;
wire [31:0] WFIFO2IP_Data_int;
wire [31:0] iReg2IP_Data_int;
wire [0:31] iReg2IP_Data;
wire [31:0] RAM2IP_Data_int; // Data from BRAM
wire [31:0] RAM2IP_Data_int0; // Data from BRAM0
wire [31:0] RAM2IP_Data_int1; // Data from BRAM1
wire [31:0] RAM2IP_Data_int2; // Data from BRAM2
// DATA TYPE - REG
wire RAM2IP_RdAck_int;
reg RAM2IP_RdAck_dly1;
wire RAM2IP_RdAck;
reg [31:0] IP2Bus_Data_int;
reg [0:3] Bus2IP_CS_dly1;
//**************************************************************************//
//* Bit ReOrdering *//
//**************************************************************************//
assign Bus2IP_Data_int[31:0] = fnBitReordering031to310(Bus2IP_Data[0:31]);
assign WFIFO2IP_Data_int[31:0] = fnBitReordering031to310(WFIFO2IP_Data[0:31]);
assign iReg2IP_Data_int[31:0] = fnBitReordering031to310(iReg2IP_Data[0:31]);
assign IP2Bus_Data[0:31] = fnBitReordering310to031(IP2Bus_Data_int[31:0]);
//**************************************************************************//
//* BRAM Logic *//
//**************************************************************************//
// WRITE
assign RAM_WE[0:C_NUM_MEM-1] = Bus2IP_CS[0:C_NUM_MEM-1]&{(C_NUM_MEM){~Bus2IP_RNW}};
// READ
// always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
// if (Bus2IP_Reset !== 1'b0)
// RAM2IP_RdAck <= 1'b0;
// else
assign RAM2IP_RdAck_int = |Bus2IP_CS[0:C_NUM_MEM-1] & Bus2IP_RNW;
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 0)
RAM2IP_RdAck_dly1 <= 1'b0;
else
RAM2IP_RdAck_dly1 <= RAM2IP_RdAck_int;
assign RAM2IP_RdAck = RAM2IP_RdAck_int & RAM2IP_RdAck_dly1;
assign RAM2IP_WrAck = |RAM_WE[0:C_NUM_MEM-1];
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
Bus2IP_CS_dly1[0:2] <= 3'b000;
else
Bus2IP_CS_dly1[0:2] <= Bus2IP_CS[0:2];
assign RAM2IP_Data_int[31:0] = RAM2IP_Data_int0[31:0] & {(32){Bus2IP_CS_dly1[0]}} |
RAM2IP_Data_int1[31:0] & {(32){Bus2IP_CS_dly1[1]}} |
RAM2IP_Data_int2[31:0] & {(32){Bus2IP_CS_dly1[2]}} ;
//**************************************************************************//
//* Outputs *//
//**************************************************************************//
assign IP2WFIFO_RdReq = ~WFIFO2IP_Empty;
assign CPTR[9:0] = CPTR_1[9:0]; // Choosing bits 9:0 to output to BRAM
always @ (/*AS*/RAM2IP_Data_int or RAM2IP_RdAck or iReg2IP_Data_int
or iReg2IP_RdAck)
begin
if (RAM2IP_RdAck)
IP2Bus_Data_int[31:0] = RAM2IP_Data_int[31:0];
else if (iReg2IP_RdAck)
IP2Bus_Data_int[31:0] = iReg2IP_Data_int[31:0];
else
IP2Bus_Data_int[31:0] = 32'd0;
end
assign IP2Bus_RdAck = RAM2IP_RdAck | iReg2IP_RdAck;
assign IP2Bus_WrAck = RAM2IP_WrAck | iReg2IP_WrAck;
assign IP2Bus_Error = iReg2IP_RdAck & RAM2IP_RdAck;
//**************************************************************************//
//* Submodules *//
//**************************************************************************//
iReg iReg
(//Inputs
.Bus2IP_Clk (Bus2IP_Clk),
.Bus2IP_Reset (Bus2IP_Reset),
.Bus2IP_RdCE (Bus2IP_RdCE[0:3]),
.Bus2IP_WrCE (Bus2IP_WrCE[0:3]),
.Bus2IP_Data (Bus2IP_Data[0:C_SLV_DWIDTH-1]),
.WFIFO_WE (WFIFO2IP_RdAck),
.FIR_WE (FIR_WE),
//Outputs
.iReg_intr (IP2Bus_IntrEvent),
.iReg2IP_RdAck (iReg2IP_RdAck),
.IP2Bus_WrAck (iReg2IP_WrAck),
.IP2Bus_Data (iReg2IP_Data[0:C_SLV_DWIDTH-1]),
.CPTR (CPTR_1[10:0]),
.SYNC (SYNC)
);
QM_FIR QM_FIR
(//Inputs
.CLK (Bus2IP_Clk),
.ARST (Bus2IP_Reset),
.Constant (WFIFO2IP_Data_int[15:0]), //using lower 16 bits
.InputValid (WFIFO2IP_RdAck),
.Sync (SYNC),
//Outputs
.RealOut1 (RealOut1[15:0]),
.ImagOut1 (ImagOut1[15:0]),
.RealOut2 (RealOut2[15:0]),
.ImagOut2 (ImagOut2[15:0]),
.RealOut3 (RealOut3[15:0]),
.ImagOut3 (ImagOut3[15:0]),
.DataValid_R (FIR_WE)
);
BRAM BRAM0
(//Inputs
.clka (Bus2IP_Clk),
.addra (CPTR[9:0]),
.dina ({ImagOut1[15:0],RealOut1[15:0]}),
.wea (FIR_WE),
.clkb (Bus2IP_Clk),
.addrb (Bus2IP_Addr[20:29]), //Original 32-bit
.dinb (Bus2IP_Data_int[31:0]),
.web (RAM_WE[0]),
//Outputs
.doutb (RAM2IP_Data_int0[31:0])
);
BRAM BRAM1
(//Inputs
.clka (Bus2IP_Clk),
.addra (CPTR[9:0]),
.dina ({ImagOut2[15:0],RealOut2[15:0]}),
.wea (FIR_WE),
.clkb (Bus2IP_Clk),
.addrb (Bus2IP_Addr[20:29]), //Original 32-bit
.dinb (Bus2IP_Data_int[31:0]),
.web (RAM_WE[1]),
//Outputs
.doutb (RAM2IP_Data_int1[31:0])
);
BRAM BRAM2
(//Inputs
.clka (Bus2IP_Clk),
.addra (CPTR[9:0]),
.dina ({ImagOut3[15:0],RealOut3[15:0]}),
.wea (FIR_WE),
.clkb (Bus2IP_Clk),
.addrb (Bus2IP_Addr[20:29]),
.dinb (Bus2IP_Data_int[31:0]),
.web (RAM_WE[2]),
//Outputs
.doutb (RAM2IP_Data_int2[31:0])
);
//**************************************************************************//
//* Bit ReOrddering Functions *//
//**************************************************************************//
function [31:0] fnBitReordering031to310; // From [0:31] to [31:0]
input [0:31] Data1;
integer i;
begin
for (i=0;i<32;i=i+1)
fnBitReordering031to310[i] = Data1[31-i];
end
endfunction // fnBitReordering031to310
function [0:31] fnBitReordering310to031; // From [31:0] to [0:31]
input [31:0] Data1;
integer i;
begin
for (i=0;i<32;i=i+1)
fnBitReordering310to031[i] = Data1[31-i];
end
endfunction // fnBitReordering310to031
endmodule // user_logic
// Copyright(C) 2004 by Xilinx, Inc. All rights reserved.
// This text/file contains proprietary, confidential
// information of Xilinx, Inc., is distributed under license
// from Xilinx, Inc., and may be used, copied and/or
// disclosed only pursuant to the terms of a valid license
// agreement with Xilinx, Inc. Xilinx hereby grants you
// a license to use this text/file solely for design, simulation,
// implementation and creation of design files limited
// to Xilinx devices or technologies. Use with non-Xilinx
// devices or technologies is expressly prohibited and
// immediately terminates your license unless covered by
// a separate agreement.
//
// Xilinx is providing this design, code, or information
// "as is" solely for use in developing programs and
// solutions for Xilinx devices. By providing this design,
// code, or information as one possible implementation of
// this feature, application or standard, Xilinx is making no
// representation that this implementation is free from any
// claims of infringement. You are responsible for
// obtaining any rights you may require for your implementation.
// Xilinx expressly disclaims any warranty whatsoever with
// respect to the adequacy of the implementation, including
// but not limited to any warranties or representations that this
// implementation is free from claims of infringement, implied
// warranties of merchantability or fitness for a particular
// purpose.
//
// Xilinx products are not intended for use in life support
// appliances, devices, or systems. Use in such applications are
// expressly prohibited.
//
// This copyright and support notice must be retained as part
// of this text at all times. (c) Copyright 1995-2004 Xilinx, Inc.
// All rights reserved.
/**************************************************************************
* $RCSfile: BLKMEMDP_V6_3.v,v $ $Revision: 1.1.2.1 $ $Date: 2005/08/01 18:40:58 $
**************************************************************************
* Dual Port Block Memory - Verilog Behavioral Model
* ************************************************************************
*
*
*************************************************************************
* Filename: BLKMEMDP_V6_3.v
*
* Description: The Verilog behavioral model for the Dual Port Block Memory
*
* ***********************************************************************
*/
`timescale 1ns/10ps
`celldefine
`define c_dp_rom 4
`define c_dp_ram 2
`define c_write_first 0
`define c_read_first 1
`define c_no_change 2
module BLKMEMDP_V6_3(DOUTA, DOUTB, ADDRA, CLKA, DINA, ENA, SINITA, WEA, NDA, RFDA, RDYA, ADDRB, CLKB, DINB, ENB, SINITB, WEB,NDB, RFDB, RDYB);
parameter c_addra_width = 11 ;
parameter c_addrb_width = 9 ;
parameter c_default_data = "0"; // indicates string of hex characters used to initialize memory
parameter c_depth_a = 2048 ;
parameter c_depth_b = 512 ;
parameter c_enable_rlocs = 0 ; // core includes placement constraints
parameter c_has_default_data = 1;
parameter c_has_dina = 1 ; // indicate port A has data input pins
parameter c_has_dinb = 1 ; // indicate port B has data input pins
parameter c_has_douta = 1 ; // indicates port A has output
parameter c_has_doutb = 1 ; // indicates port B has output
parameter c_has_ena = 1 ; // indicates port A has a ENA pin
parameter c_has_enb = 1 ; // indicates port B has a ENB pin
parameter c_has_limit_data_pitch = 1 ;
parameter c_has_nda = 0 ; // Port A has a new data pin
parameter c_has_ndb = 0 ; // Port B has a new data pin
parameter c_has_rdya = 0 ; // Port A has result ready pin
parameter c_has_rdyb = 0 ; // Port B has result ready pin
parameter c_has_rfda = 0 ; // Port A has ready for data pin
parameter c_has_rfdb = 0 ; // Port B has ready for data pin
parameter c_has_sinita = 1 ; // indicates port A has a SINITA pin
parameter c_has_sinitb = 1 ; // indicates port B has a SINITB pin
parameter c_has_wea = 1 ; // indicates port A has a WEA pin
parameter c_has_web = 1 ; // indicates port B has a WEB pin
parameter c_limit_data_pitch = 16 ;
parameter c_mem_init_file = "null.mif"; // controls which .mif file used to initialize memory
parameter c_pipe_stages_a = 0 ; // indicates the number of pipe stages needed in port A
parameter c_pipe_stages_b = 0 ; // indicates the number of pipe stages needed in port B
parameter c_reg_inputsa = 0 ; // indicates we, addr, and din of port A are registered
parameter c_reg_inputsb = 0 ; // indicates we, addr, and din of port B are registered
parameter c_sim_collision_check = "NONE";
parameter c_sinita_value = "0000"; // indicates string of hex used to initialize A output registers
parameter c_sinitb_value = "0000"; // indicates string of hex used to initialize B output resisters
parameter c_width_a = 8 ;
parameter c_width_b = 32 ;
parameter c_write_modea = 2; // controls which write modes shall be used
parameter c_write_modeb = 2; // controls which write modes shall be used
// New Generics for Primitive Selection and Pin Polarity
parameter c_ybottom_addr = "1024";
parameter c_yclka_is_rising = 1; // controls the active edge of the CLKA Pin
parameter c_yclkb_is_rising = 1; // controls the active edge of the CLKB Pin
parameter c_yena_is_high = 1; // controls the polarity of the ENA Pin
parameter c_yenb_is_high = 1; // controls the polarity of the ENB Pin
parameter c_yhierarchy = "hierarchy1";
parameter c_ymake_bmm = 0;
parameter c_yprimitive_type = "4kx4"; // Indicates which primitive should be used to build the
// memory if c_yuse_single_primitive=1
parameter c_ysinita_is_high = 1; // controls the polarity of the SINITA Pin
parameter c_ysinitb_is_high = 1; // controls the polarity of the SINITB Pin
parameter c_ytop_addr = "0";
parameter c_yuse_single_primitive = 0; // controls whether the Memory is build out of a
// user selected primitive or is built from multiple
// primitives with the "optimize for area" algorithm used
parameter c_ywea_is_high = 1; // controls the polarity of the WEA Pin
parameter c_yweb_is_high = 1; // controls the polarity of the WEB Pin
parameter c_yydisable_warnings = 1; //1=no warnings, 0=print warnings
// IO ports
output [c_width_a-1:0] DOUTA;
input [c_addra_width-1:0] ADDRA;
input [c_width_a-1:0] DINA;
input ENA, CLKA, WEA, SINITA, NDA;
output RFDA, RDYA;
output [c_width_b-1:0] DOUTB;
input [c_addrb_width-1:0] ADDRB;
input [c_width_b-1:0] DINB;
input ENB, CLKB, WEB, SINITB, NDB;
output RFDB, RDYB;
// internal signals
reg [c_width_a-1:0] douta_mux_out ; // output of multiplexer --
wire [c_width_a-1:0] DOUTA = douta_mux_out;
reg RFDA, RDYA ;
reg [c_width_b-1:0] doutb_mux_out ; // output of multiplexer --
wire [c_width_b-1:0] DOUTB = doutb_mux_out;
reg RFDB, RDYB;
reg [c_width_a-1:0] douta_out_q; // registered output of douta_out
reg [c_width_a-1:0] doa_out; // output of Port A RAM
reg [c_width_a-1:0] douta_out; // output of pipeline mux for port A
reg [c_width_b-1:0] doutb_out_q ; // registered output for doutb_out
reg [c_width_b-1:0] dob_out; // output of Port B RAM
reg [c_width_b-1:0] doutb_out ; // output of pipeline mux for port B
reg [c_depth_a*c_width_a-1 : 0] mem;
reg [24:0] count ;
reg [1:0] wr_mode_a, wr_mode_b;
reg [(c_width_a-1) : 0] pipelinea [0 : c_pipe_stages_a];
reg [(c_width_b-1) : 0] pipelineb [0 : c_pipe_stages_b];
reg sub_rdy_a[0 : c_pipe_stages_a];
reg sub_rdy_b[0 : c_pipe_stages_b];
reg [10:0] ci, cj;
reg [10:0] dmi, dmj, dni, dnj, doi, doj, dai, daj, dbi, dbj, dci, dcj, ddi, ddj;
reg [10:0] pmi, pmj, pni, pnj, poi, poj, pai, paj, pbi, pbj, pci, pcj, pdi, pdj;
integer ai, aj, ak, al, am, an, ap ;
integer bi, bj, bk, bl, bm, bn, bp ;
integer i, j, k, l, m, n, p;
wire [c_addra_width-1:0] addra_i = ADDRA;
reg [c_width_a-1:0] dia_int ;
reg [c_width_a-1:0] dia_q ;
wire [c_width_a-1:0] dia_i ;
wire ena_int ;
reg ena_q ;
wire clka_int ;
reg wea_int ;
wire wea_i ;
reg wea_q ;
wire ssra_int ;
wire nda_int ;
wire nda_i ;
reg rfda_int ;
reg rdya_int ;
reg nda_q ;
reg new_data_a ;
reg new_data_a_q ;
reg [c_addra_width-1:0] addra_q;
reg [c_addra_width-1:0] addra_int;
reg [c_width_a-1:0] sinita_value ; // initialization value for output registers of Port A
wire [c_addrb_width-1:0] addrb_i = ADDRB;
reg [c_width_b-1:0] dib_int ;
reg [c_width_b-1:0] dib_q ;
wire [c_width_b-1:0] dib_i ;
wire enb_int ;
reg enb_q ;
wire clkb_int ;
reg web_int ;
wire web_i ;
reg web_q ;
wire ssrb_int ;
wire ndb_int ;
wire ndb_i ;
reg rfdb_int ;
reg rdyb_int ;
reg ndb_q ;
reg new_data_b ;
reg new_data_b_q ;
reg [c_addrb_width-1:0] addrb_q ;
reg [c_addrb_width-1:0] addrb_int ;
reg [c_width_b-1:0] sinitb_value ; // initialization value for output registers of Port B
// variables used to initialize memory contents to default values.
reg [c_width_a-1:0] bitval ;
reg [c_width_a-1:0] ram_temp [0:c_depth_a-1] ;
reg [c_width_a-1:0] default_data ;
// variables used to detect address collision on dual port Rams
reg recovery_a, recovery_b;
reg address_collision;
wire clka_enable_pp = ena_int && wea_int && enb_int && address_collision
&& c_yclka_is_rising && c_yclkb_is_rising;
wire clkb_enable_pp = enb_int && web_int && ena_int && address_collision
&& c_yclka_is_rising && c_yclkb_is_rising;
wire collision_posa_posb = clka_enable_pp || clkb_enable_pp;
// For posedge clka and negedge clkb
wire clka_enable_pn = ena_int && wea_int && enb_int && address_collision
&& c_yclka_is_rising && (!c_yclkb_is_rising);
wire clkb_enable_pn = enb_int && web_int && ena_int && address_collision
&& c_yclka_is_rising && (!c_yclkb_is_rising);
wire collision_posa_negb = clka_enable_pn || clkb_enable_pn;
// For negedge clka and posedge clkb
wire clka_enable_np = ena_int && wea_int && enb_int && address_collision
&& (!c_yclka_is_rising) && c_yclkb_is_rising;
wire clkb_enable_np = enb_int && web_int && ena_int && address_collision
&& (!c_yclka_is_rising) && c_yclkb_is_rising;
wire collision_nega_posb = clka_enable_np || clkb_enable_np;
// For negedge clka and clkb
wire clka_enable_nn = ena_int && wea_int && enb_int && address_collision
&& (!c_yclka_is_rising) && (!c_yclkb_is_rising);
wire clkb_enable_nn = enb_int && web_int && ena_int && address_collision
&& (!c_yclka_is_rising) && (!c_yclkb_is_rising);
wire collision_nega_negb = clka_enable_nn || clkb_enable_nn;
// tri0 GSR = glbl.GSR;
assign dia_i = (c_has_dina === 1)?DINA:'b0;
assign ena_int = defval(ENA, c_has_ena, 1, c_yena_is_high);
assign ssra_int = defval(SINITA, c_has_sinita, 0, c_ysinita_is_high);
assign nda_i = defval(NDA, c_has_nda, 1, 1);
assign clka_int = defval(CLKA, 1, 1, c_yclka_is_rising);
assign dib_i = (c_has_dinb === 1)?DINB:'b0;
assign enb_int = defval(ENB, c_has_enb, 1, c_yenb_is_high);
assign ssrb_int = defval(SINITB, c_has_sinitb, 0, c_ysinitb_is_high);
assign ndb_i = defval(NDB, c_has_ndb, 1, 1);
assign clkb_int = defval(CLKB, 1, 1, c_yclkb_is_rising);
// RAM/ROM functionality
assign wea_i = defval(WEA, c_has_wea, 0, c_ywea_is_high);
assign web_i = defval(WEB, c_has_web, 0, c_yweb_is_high);
function defval;
input i;
input hassig;
input val;
input active_high;
begin
if(hassig == 1)
begin
if (active_high == 1)
defval = i;
else
defval = ~i;
end
else
defval = val;
end
endfunction
function max;
input a;
input b;
begin
max = (a > b) ? a : b;
end
endfunction
function a_is_X;
input [c_width_a-1 : 0] i;
integer j ;
begin
a_is_X = 1'b0;
for(j = 0; j < c_width_a; j = j + 1)
begin
if(i[j] === 1'bx)
a_is_X = 1'b1;
end // loop
end
endfunction
function b_is_X;
input [c_width_b-1 : 0] i;
integer j ;
begin
b_is_X = 1'b0;
for(j = 0; j < c_width_b; j = j + 1)
begin
if(i[j] === 1'bx)
b_is_X = 1'b1;
end // loop
end
endfunction
function [c_width_a-1:0] hexstr_conv;
input [(c_width_a*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=c_width_a-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
if (c_yydisable_warnings == 0) begin
$display("ERROR in %m at time %t: NOT A HEX CHARACTER",$time);
end
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < c_width_a)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
function [c_width_b-1:0] hexstr_conv_b;
input [(c_width_b*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv_b = 'b0;
for( i=c_width_b-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
if (c_yydisable_warnings == 0) begin
$display("ERROR in %m at time %t: NOT A HEX CHARACTER",$time);
end
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < c_width_b)
begin
hexstr_conv_b[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
// Initialize memory contents to 0 for now .
initial begin
sinita_value = 'b0 ;
sinitb_value = 'b0 ;
default_data = hexstr_conv(c_default_data);
if (c_has_sinita == 1 )
sinita_value = hexstr_conv(c_sinita_value);
if (c_has_sinitb == 1 )
sinitb_value = hexstr_conv_b(c_sinitb_value);
for(i = 0; i < c_depth_a; i = i + 1)
ram_temp[i] = default_data;
if (c_has_default_data == 0)
$readmemb(c_mem_init_file, ram_temp) ;
for(i = 0; i < c_depth_a; i = i + 1)
for(j = 0; j < c_width_a; j = j + 1)
begin
bitval = (1'b1 << j);
mem[(i*c_width_a) + j] = (ram_temp[i] & bitval) >> j;
end
recovery_a = 0;
recovery_b = 0;
for (k = 0; k <= c_pipe_stages_a; k = k + 1)
pipelinea[k] = sinita_value ;
for (l = 0; l <= c_pipe_stages_b; l = l + 1)
pipelineb[l] = sinitb_value ;
for (m = 0; m <= c_pipe_stages_a; m = m + 1)
sub_rdy_a[m] = 0 ;
for (n = 0; n <= c_pipe_stages_b; n = n + 1)
sub_rdy_b[n] = 0 ;
doa_out = sinita_value ;
dob_out = sinitb_value ;
nda_q = 0;
ndb_q = 0;
new_data_a_q = 0 ;
new_data_b_q = 0 ;
dia_q = 0;
dib_q = 0;
addra_q = 0;
addrb_q = 0;
wea_q = 0;
web_q = 0;
#1 douta_out = sinita_value;
#1 doutb_out = sinitb_value;
#1 rdya_int = 0;
#1 rdyb_int = 0;
end
always @(addra_int or addrb_int) begin // check address collision
address_collision <= 1'b0;
for (ci = 0; ci < c_width_a; ci = ci + 1) begin // absolute address A
for (cj = 0; cj < c_width_b; cj = cj + 1) begin // absolute address B
if ((addra_int * c_width_a + ci) == (addrb_int * c_width_b + cj)) begin
address_collision <= 1'b1;
end
end
end
end
/***********************************************************************************************************
* The following 3 always blocks handle memory inputs for the case of an address collision on ADDRA and ADDRB
***********************************************************************************************************/
always @(posedge recovery_a or posedge recovery_b) begin
if (((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01)) ||
((wr_mode_a != 2'b01) && (wr_mode_b != 2'b01))) begin
if (wea_int == 1 && web_int == 1) begin
if (addra_int < c_depth_a)
for (dmi = 0; dmi < c_width_a; dmi = dmi + 1) begin
for (dmj = 0; dmj < c_width_b; dmj = dmj + 1) begin
if ((addra_int * c_width_a + dmi) == (addrb_int * c_width_b + dmj)) begin
//Fixed read-first collision
// mem[addra_int * c_width_a + dmi] <= 1'bX;
if ((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01))
begin
doa_out[dmi] <= 1'bX;
dob_out[dmj] <= 1'bX;
end
else
mem[addra_int * c_width_a + dmi] <= 1'bX;
end
end
end
else begin
//Warning Condition:
//Write Mode PortA is "Read First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range
//or
//Write Mode PortA is not "Read First" and Write Mode PortB is not "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #1: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1);
end
doa_out <= {c_width_a{1'bX}}; // assign data bus to X
end
end
end
recovery_a <= 0;
recovery_b <= 0;
end
always @(posedge recovery_a or posedge recovery_b) begin
if ((wr_mode_a == 2'b01) && (wr_mode_b != 2'b01)) begin
if (wea_int == 1 && web_int == 1) begin
if (addra_int < c_depth_a)
for (dni = 0; dni < c_width_a; dni = dni + 1) begin
for (dnj = 0; dnj < c_width_b; dnj = dnj + 1) begin
if ((addra_int * c_width_a + dni) == (addrb_int * c_width_b + dnj)) begin
mem[addra_int * c_width_a + dni] <= dia_int[dni];
end
end
end
else begin
//Warning Condition:
//Write Mode PortA is "Read First" and Write Mode PortB is not "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #2: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1);
end
doa_out <= {c_width_a{1'bX}}; // assign data bus to X
end
end
end
end
always @(posedge recovery_a or posedge recovery_b) begin
if ((wr_mode_a != 2'b01) && (wr_mode_b == 2'b01)) begin
if (wea_int == 1 && web_int == 1) begin
if (addrb_int < c_depth_b)
for (doi = 0; doi < c_width_a; doi = doi + 1) begin
for (doj = 0; doj < c_width_b; doj = doj + 1) begin
if ((addra_int * c_width_a + doi) == (addrb_int * c_width_b + doj)) begin
mem[addrb_int * c_width_b + doj] <= dib_int[doj];
end
end
end
else begin
//Warning Condition:
//Write Mode PortA is not "Read First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and ADDRB out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #3: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1);
end
dob_out <= {c_width_b{1'bX}}; // assign data bus to X
end
end
end
end
/***********************************************************************************************************
*The following 4 always blocks handle memory outputs for the case of an address collision on ADDRA and ADDRB
***********************************************************************************************************/
always @(posedge recovery_a or posedge recovery_b) begin
if ((wr_mode_b == 2'b00) || (wr_mode_b == 2'b10)) begin
if ((wea_int == 0) && (web_int == 1) && (ssra_int == 0)) begin
if (addra_int < c_depth_a)
for (dai = 0; dai < c_width_a; dai = dai + 1) begin
for (daj = 0; daj < c_width_b; daj = daj + 1) begin
if ((addra_int * c_width_a + dai) == (addrb_int * c_width_b + daj)) begin
doa_out[dai] <= 1'bX;
end
end
end
else begin
//Warning Condition:
//Write Mode PortB is "Write First" and WEA = 0 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range
//or
//Write Mode PortB is "No Change" and WEA = 0 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #4: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1);
end
doa_out <= {c_width_a{1'bX}}; // assign data bus to X
end
end
end
end
always @(posedge recovery_a or posedge recovery_b) begin
if ((wr_mode_a == 2'b00) || (wr_mode_a == 2'b10)) begin
if ((wea_int == 1) && (web_int == 0) && (ssrb_int == 0)) begin
if (addrb_int < c_depth_b)
for (dbi = 0; dbi < c_width_a; dbi = dbi + 1) begin
for (dbj = 0; dbj < c_width_b; dbj = dbj + 1) begin
if ((addra_int * c_width_a + dbi) == (addrb_int * c_width_b + dbj)) begin
dob_out[dbj] <= 1'bX;
end
end
end
else begin
//Warning Condition:
//Write Mode PortA is "Write First" and WEA = 1 and WEB = 0 and SINITB = 0 and ADDRB out of the valid range
//or
//Write Mode PortA is "No Change" and WEA = 1 and WEB = 0 and SINITB = 0 and ADDRB out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #5: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1);
end
dob_out <= {c_width_b{1'bX}}; // assign data bus to X
end
end
end
end
always @(posedge recovery_a or posedge recovery_b) begin
if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
((wr_mode_a != 2'b10) && (wr_mode_b == 2'b10)) ||
((wr_mode_a == 2'b01) && (wr_mode_b == 2'b00))) begin
if ((wea_int == 1) && (web_int == 1) && (ssra_int == 0)) begin
if (addra_int < c_depth_a)
for (dci = 0; dci < c_width_a; dci = dci + 1) begin
for (dcj = 0; dcj < c_width_b; dcj = dcj + 1) begin
if ((addra_int * c_width_a + dci) == (addrb_int * c_width_b + dcj)) begin
doa_out[dci] <= 1'bX;
end
end
end
else begin
//Warning Condition:
//Write Mode PortA is "Write First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range
//or
//Write Mode PortA is not "No Change" and Write Mode PortB is "No Change" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range
//or
//Write Mode PortA is "Read First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #6: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1);
end
doa_out <= {c_width_a{1'bX}}; // assign data bus to X
end
end
end
end
always @(posedge recovery_a or posedge recovery_b) begin
if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
((wr_mode_a == 2'b10) && (wr_mode_b != 2'b10)) ||
((wr_mode_a == 2'b00) && (wr_mode_b == 2'b01))) begin
if ((wea_int == 1) && (web_int == 1) && (ssrb_int == 0)) begin
if (addrb_int < c_depth_b)
for (ddi = 0; ddi < c_width_a; ddi = ddi + 1) begin
for (ddj = 0; ddj < c_width_b; ddj = ddj + 1) begin
if ((addra_int * c_width_a + ddi) == (addrb_int * c_width_b + ddj)) begin
dob_out[ddj] <= 1'bX;
end
end
end
else begin
//Warning Condition:
//Write Mode PortA is "Write First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range
//or
//Write Mode PortA is "No Change" and Write Mode PortB is not "No Change" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range
//or
//Write Mode PortA is "Write First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #7: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1);
end
dob_out <= {c_width_b{1'bX}}; // assign data bus to X
end
end
end
end
// Parity Section is deleted
initial begin
case (c_write_modea)
`c_write_first : wr_mode_a <= 2'b00;
`c_read_first : wr_mode_a <= 2'b01;
`c_no_change : wr_mode_a <= 2'b10;
default : begin
if (c_yydisable_warnings == 0) begin
$display("Error in %m at time %t: c_write_modea = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time, c_write_modea);
end
$finish;
end
endcase
end
initial begin
case (c_write_modeb)
`c_write_first : wr_mode_b <= 2'b00;
`c_read_first : wr_mode_b <= 2'b01;
`c_no_change : wr_mode_b <= 2'b10;
default : begin
if (c_yydisable_warnings == 0) begin
$display("Error in %m at time %t: c_write_modeb = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time, c_write_modeb);
end
$finish;
end
endcase
end
// Port A
// Generate ouput control signals for Port A: RFDA and RDYA
always @ (rfda_int or rdya_int)
begin
if (c_has_rfda == 1)
RFDA = rfda_int ;
else
RFDA = 1'b0 ;
if ((c_has_rdya == 1) && (c_has_nda == 1) && (c_has_rfda == 1) )
RDYA = rdya_int;
else
RDYA = 1'b0 ;
end
always @ (ena_int )
begin
if (ena_int == 1'b1)
rfda_int <= 1'b1 ;
else
rfda_int <= 1'b0 ;
end
// Gate nd signal with en
assign nda_int = ena_int && nda_i ;
// Register hanshaking signals for port A
always @ (posedge clka_int)
begin
if (ena_int == 1'b1)
begin
if (ssra_int == 1'b1)
nda_q <= 1'b0 ;
else
nda_q <= nda_int ;
end
else
nda_q <= nda_q ;
end
// Register data/ address / we inputs for port A
always @ (posedge clka_int)
begin
if (ena_int == 1'b1)
begin
dia_q <= dia_i ;
addra_q <= addra_i ;
wea_q <= wea_i ;
end
end
// Select registered or non-registered write enable for Port A
always @ ( wea_i or wea_q )
begin
if (c_reg_inputsa == 1)
wea_int = wea_q ;
else
wea_int = wea_i ;
end
// Select registered or non-registered data/address/nd inputs for Port A
always @ ( dia_i or dia_q )
begin
if ( c_reg_inputsa == 1)
dia_int = dia_q;
else
dia_int = dia_i;
end
always @ ( addra_i or addra_q or nda_q or nda_int )
begin
if ( c_reg_inputsa == 1)
begin
addra_int = addra_q ;
if ((wea_q == 1'b1) && (c_write_modea == 2))
new_data_a = 1'b0 ;
else
new_data_a = nda_q ;
end
else
begin
addra_int = addra_i;
if ((wea_i == 1'b1) && (c_write_modea == 2))
new_data_a = 1'b0 ;
else
new_data_a = nda_int ;
end
end
// Register the new_data signal for Port A to track the synchronous RAM output
always @(posedge clka_int)
begin
if (ena_int == 1'b1)
begin
if (ssra_int == 1'b1)
new_data_a_q <= 1'b0 ;
else
// Do not update RDYA if write mode is no_change and wea=1
//if (!(c_write_modea == 2 && wea_int == 1)) begin
// rii1 : 10/20 Make dual port behavior the same as single port
new_data_a_q <= new_data_a ;
//end
end
end
// Generate data outputs for Port A
/***************************************************************
*The following always block assigns the value for the DOUTA bus
***************************************************************/
always @(posedge clka_int) begin
if (ena_int == 1'b1) begin
if (ssra_int == 1'b1) begin
// for ( ai = 0; ai < c_width_a; ai = ai + 1)
// doa_out[ai] <= sinita_value[ai];
doa_out <= sinita_value;
end
else begin
//The following IF block assigns the output for a write operation
if (wea_int == 1'b1) begin
if (wr_mode_a == 2'b00) begin
if (addra_int < c_depth_a)
// for ( aj = 0; aj < c_width_a; aj = aj + 1)
// doa_out[aj] <= dia_int[aj] ;
doa_out <= dia_int ;
else begin
//Warning Condition (Error occurs on rising edge of CLKA):
//Write Mode PortA is "Write First" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #8: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1);
end
doa_out <= {c_width_a{1'bX}}; // assign data bus to X
end
end
else if (wr_mode_a == 2'b01) begin
if (addra_int < c_depth_a)
// for ( ak = 0; ak < c_width_a; ak = ak + 1)
// doa_out[ak] <= mem[(addra_int*c_width_a) + ak];
doa_out <= mem >> (addra_int*c_width_a);
else begin
//Warning Condition (Error occurs on rising edge of CLKA):
//Write Mode PortA is "Read First" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #9: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1);
end
doa_out <= {c_width_a{1'bX}}; //assign data bus to X
end
end
else begin
if (addra_int < c_depth_a)
doa_out <= doa_out;
else begin
//Warning Condition (Error occurs on rising edge of CLKA):
//Write Mode PortA is "No Change" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #10: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1);
end
doa_out <= {c_width_a{1'bX}}; //assign data bus to X
end
end
end
//The following ELSE block assigns the output for a read operation
else begin
if (addra_int < c_depth_a)
// for ( al = 0; al < c_width_a; al = al + 1)
// doa_out[al] <= mem[(addra_int*c_width_a) + al];
doa_out <= mem >> (addra_int*c_width_a);
else begin
if (c_has_douta == 1)//New IF statement to remove read errors when port is write only
begin
//Warning Condition (Error occurs on rising edge of CLKA):
//ENA = 1 and SINITA = 0 and WEA = 0 and ADDRA out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #11: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1);
end
doa_out <= {c_width_a{1'bX}}; //assign data bus to X
end
end
end
end
end
end
/***************************************************************************************
*The following always block assigns the DINA bus to the memory during a write operation
***************************************************************************************/
always @(posedge clka_int) begin
if (ena_int == 1'b1 && wea_int == 1'b1) begin
if (addra_int < c_depth_a)
for ( am = 0; am < c_width_a; am = am + 1)
mem[(addra_int*c_width_a) + am] <= dia_int[am];
else begin
//Warning Condition (Error occurs on rising edge of CLKA):
//ENA = 1 and WEA = 1 and ADDRA out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #12: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1);
end
doa_out <= {c_width_a{1'bX}}; //assign data bus to X
end
end
end
// output pipelines for Port A
always @(posedge clka_int) begin
if (ena_int == 1'b1 && c_pipe_stages_a > 0)
begin
for (i = c_pipe_stages_a; i >= 1; i = i -1 )
begin
if (ssra_int == 1'b1 && ena_int == 1'b1 )
begin
pipelinea[i] <= sinita_value ;
sub_rdy_a[i] <= 0 ;
end
else
begin
// Do not change output when no_change and web=1
// if (!(c_write_modea == 2 && wea_int == 1)) begin
if (i==1)
pipelinea[i] <= doa_out ;
else
pipelinea[i] <= pipelinea[i-1] ;
// end // if (!(c_write_modea == 2 && wea_int == 1))
if (i==1)
sub_rdy_a[i] <= new_data_a_q ;
else
sub_rdy_a[i] <= sub_rdy_a[i-1] ;
end
end
end
end
// Select pipeline output if c_pipe_stages_a > 0
always @( pipelinea[c_pipe_stages_a] or sub_rdy_a[c_pipe_stages_a] or new_data_a_q or doa_out ) begin
if (c_pipe_stages_a == 0 )
begin
douta_out = doa_out ;
rdya_int = new_data_a_q;
end
else
begin
douta_out = pipelinea[c_pipe_stages_a];
rdya_int = sub_rdy_a[c_pipe_stages_a];
end
end
// Select Port A data outputs based on c_has_douta parameter
always @( douta_out ) begin
if ( c_has_douta == 1)
douta_mux_out = douta_out ;
else
douta_mux_out = 0 ;
end
// Port B
// Generate output control signals for Port B: RFDB and RDYB
always @ (rfdb_int or rdyb_int)
begin
if (c_has_rfdb == 1)
RFDB = rfdb_int ;
else
RFDB = 1'b0 ;
if ((c_has_rdyb == 1) && (c_has_ndb == 1) && (c_has_rfdb == 1) )
RDYB = rdyb_int;
else
RDYB = 1'b0 ;
end
always @ (enb_int )
begin
if ( enb_int == 1'b1 )
rfdb_int = 1'b1 ;
else
rfdb_int = 1'b0 ;
end
// Gate nd signal with en
assign ndb_int = enb_int && ndb_i ;
// Register hanshaking signals for port B
always @ (posedge clkb_int)
begin
if (enb_int == 1'b1)
begin
if (ssrb_int == 1'b1)
ndb_q <= 1'b0 ;
else
ndb_q <= ndb_int ;
end
else
ndb_q <= ndb_q;
end
// Register data / address / we inputs for port B
always @ (posedge clkb_int)
begin
if (enb_int == 1'b1)
begin
dib_q <= dib_i ;
addrb_q <= addrb_i ;
web_q <= web_i ;
end
end
// Select registered or non-registered write enable for port B
always @ (web_i or web_q )
begin
if (c_reg_inputsb == 1)
web_int = web_q ;
else
web_int = web_i ;
end
// Select registered or non-registered data/address/nd inputs for Port B
always @ ( dib_i or dib_q )
begin
if ( c_reg_inputsb == 1)
dib_int = dib_q;
else
dib_int = dib_i;
end
always @ ( addrb_i or addrb_q or ndb_q or ndb_int or web_q or web_i)
begin
if ( c_reg_inputsb == 1)
begin
addrb_int = addrb_q ;
if ((web_q == 1'b1) && (c_write_modeb == 2))
new_data_b = 1'b0 ;
else
new_data_b = ndb_q ;
end
else
begin
addrb_int = addrb_i;
if ((web_i == 1'b1) && (c_write_modeb == 2))
new_data_b = 1'b0 ;
else
new_data_b = ndb_int ;
end
end
// Register the new_data signal for Port B to track the synchronous RAM output
always @(posedge clkb_int)
begin
if (enb_int == 1'b1 )
begin
if (ssrb_int == 1'b1)
new_data_b_q <= 1'b0 ;
else
// Do not update RDYB if write mode is no_change and web=1
//if (!(c_write_modeb == 2 && web_int == 1)) begin
// rii1 : 10/20 Make dual port behavior the same as single port
new_data_b_q <= new_data_b ;
//end
end
end
// Generate data outputs for Port B
/***************************************************************
*The following always block assigns the value for the DOUTB bus
***************************************************************/
always @(posedge clkb_int) begin
if (enb_int == 1'b1) begin
if (ssrb_int == 1'b1) begin
// for (bi = 0; bi < c_width_b; bi = bi + 1)
// dob_out[bi] <= sinitb_value[bi];
dob_out <= sinitb_value;
end
else begin
//The following IF block assigns the output for a write operation
if (web_int == 1'b1) begin
if (wr_mode_b == 2'b00) begin
if (addrb_int < c_depth_b)
// for (bj = 0; bj < c_width_b; bj = bj + 1)
// dob_out[bj] <= dib_int[bj];
dob_out <= dib_int;
else begin
//Warning Condition (Error occurs on rising edge of CLKB):
//Write Mode PortB is "Write First" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #13: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1);
end
dob_out <= {c_width_b{1'bX}}; //assign data bus to X
end
end
else if (wr_mode_b == 2'b01) begin
if (addrb_int < c_depth_b)
// for (bk = 0; bk < c_width_b; bk = bk + 1)
// dob_out[bk] <= mem[(addrb_int*c_width_b) + bk];
dob_out <= mem >> (addrb_int*c_width_b);
else begin
//Warning Condition (Error occurs on rising edge of CLKB):
//Write Mode PortB is "Read First" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #14: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1);
end
dob_out <= {c_width_b{1'bX}}; //assign data bus to X
end
end
else begin
if (addrb_int < c_depth_b)
dob_out <= dob_out ;
else begin
//Warning Condition (Error occurs on rising edge of CLKB):
//Write Mode PortB is "No Change" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #15: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1);
end
dob_out <= {c_width_b{1'bX}}; //assign data bus to X
end
end
end
//The following ELSE block assigns the output for a read operation
else begin
if (addrb_int < c_depth_b)
// for (bl = 0; bl < c_width_b; bl = bl + 1)
// dob_out[bl] <= mem[(addrb_int*c_width_b) + bl];
dob_out <= mem >> (addrb_int*c_width_b);
else begin
if (c_has_doutb == 1)//New IF statement to remove read errors when port is write only
begin
//Warning Condition (Error occurs on rising edge of CLKB):
//ENB = 1 and SINITB = 0 and WEB = 0 and ADDRB out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #16: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1);
end
dob_out <= {c_width_b{1'bX}}; //assign data bus to X
end
end
end
end
end
end
/***************************************************************************************
*The following always block assigns the DINA bus to the memory during a write operation
***************************************************************************************/
always @(posedge clkb_int) begin
if (enb_int == 1'b1 && web_int == 1'b1) begin
if (addrb_int < c_depth_b)
for (bm = 0; bm < c_width_b; bm = bm + 1)
mem[(addrb_int*c_width_b) + bm] <= dib_int[bm];
else begin
//Warning Condition (Error occurs on rising edge of CLKB):
//ENB = 1 and WEB = 1 and ADDRB out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #17: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1);
end
dob_out <= {c_width_b{1'bX}}; // assign data bus to X
end
end
end
// output pipelines for Port B
always @(posedge clkb_int) begin
if (enb_int == 1'b1 && c_pipe_stages_b > 0)
begin
for (j = c_pipe_stages_b; j >= 1; j = j -1 )
begin
if (ssrb_int == 1'b1 && enb_int == 1'b1 )
begin
pipelineb[j] <= sinitb_value ;
sub_rdy_b[j] <= 0 ;
end
else
begin
// Do not change output when no_change and web=1
// if (!(c_write_modeb == 2 && web_int == 1)) begin
if (j==1)
pipelineb[j] <= dob_out ;
else
pipelineb[j] <= pipelineb[j-1] ;
// end
if (j==1)
sub_rdy_b[j] <= new_data_b_q ;
else
sub_rdy_b[j] <= sub_rdy_b[j-1] ;
end
end
end
end
// Select pipeline for B if c_pipe_stages_b > 0
always @(pipelineb[c_pipe_stages_b] or sub_rdy_b[c_pipe_stages_b] or new_data_b_q or dob_out) begin
if ( c_pipe_stages_b == 0 )
begin
doutb_out = dob_out ;
rdyb_int = new_data_b_q;
end
else
begin
rdyb_int = sub_rdy_b[c_pipe_stages_b];
doutb_out = pipelineb[c_pipe_stages_b];
end
end
// Select Port B data outputs based on c_has_doutb parameter
always @( doutb_out) begin
if ( c_has_doutb == 1)
doutb_mux_out = doutb_out ;
else
doutb_mux_out = 0 ;
end
specify
// when both CLKA and CLKB are active on the positive edge
$recovery (posedge CLKB, posedge CLKA &&& collision_posa_posb, 1, recovery_b);
$recovery (posedge CLKA, posedge CLKB &&& collision_posa_posb, 1, recovery_a);
// when both CLKA active on positive edge and CLKB are active on the negative edge
$recovery (negedge CLKB, posedge CLKA &&& collision_posa_negb, 1, recovery_b);
$recovery (posedge CLKA, negedge CLKB &&& collision_posa_negb, 1, recovery_a);
// when both CLKA active on negative edge and CLKB are active on the positive edge
$recovery (posedge CLKB, negedge CLKA &&& collision_nega_posb, 1, recovery_b);
$recovery (negedge CLKA, posedge CLKB &&& collision_nega_posb, 1, recovery_a);
// when both CLKA and CLKB are active on the negative edge
$recovery (negedge CLKB, negedge CLKA &&& collision_nega_negb, 1, recovery_b);
$recovery (negedge CLKA, negedge CLKB &&& collision_nega_negb, 1, recovery_a);
endspecify
endmodule // BLKMEMDP_V6_3
//*********************************************************************************//
// ** General Information ** //
// ******************************************************************************* //
// ** Module : LkupTbl1.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Date : 2008-08-08 ** //
// ** Description: This is the sine/cosine lookup table for Channel 1. ** //
// ** Center Frequency: 12.5MHz ** //
// ** Sampling Frequency: 60MHz ** //
// ** Python file: LUT.py ** //
//*********************************************************************************//
`timescale 1 ns / 100 ps
module LkupTbl1
(//Outputs
cosine,
sine,
//Input
CLK,
ARST,
cntr
);
//******************************************************************************//
//* Declarations *//
//******************************************************************************//
// DATA TYPE - INPUTS AND OUTPUTS
output reg [15:0] sine ;
output reg [15:0] cosine ;
input CLK ;
input ARST ;
input [4:0] cntr ;
//******************************************************************************//
//* Look-Up Table *//
//******************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
sine = 'b0000000000000000; // Reset to 0
cosine = 'b0000000000000000; // Reset to 0
end
else
begin
case (cntr)
0: // theta=0.0000
begin
sine = 'b0000000000000000; // 0.0000
cosine = 'b0100000000000000; // 1.0000
end
1: // theta=1.3090
begin
sine = 'b0011110111010001; // 0.9659
cosine = 'b0001000010010000; // 0.2588
end
2: // theta=2.6180
begin
sine = 'b0001111111111111; // 0.5000
cosine = 'b1100100010010100; // -0.8660
end
3: // theta=3.9270
begin
sine = 'b1101001010111111; // -0.7071
cosine = 'b1101001010111111; // -0.7071
end
4: // theta=5.2360
begin
sine = 'b1100100010010100; // -0.8660
cosine = 'b0010000000000000; // 0.5000
end
5: // theta=0.2618
begin
sine = 'b0001000010010000; // 0.2588
cosine = 'b0011110111010001; // 0.9659
end
6: // theta=1.5708
begin
sine = 'b0100000000000000; // 1.0000
cosine = 'b0000000000000000; // 0.0000
end
7: // theta=2.8798
begin
sine = 'b0001000010010000; // 0.2588
cosine = 'b1100001000101111; // -0.9659
end
8: // theta=4.1888
begin
sine = 'b1100100010010100; // -0.8660
cosine = 'b1110000000000001; // -0.5000
end
9: // theta=5.4978
begin
sine = 'b1101001010111111; // -0.7071
cosine = 'b0010110101000001; // 0.7071
end
10: // theta=0.5236
begin
sine = 'b0001111111111111; // 0.5000
cosine = 'b0011011101101100; // 0.8660
end
11: // theta=1.8326
begin
sine = 'b0011110111010001; // 0.9659
cosine = 'b1110111101110000; // -0.2588
end
12: // theta=3.1416
begin
sine = 'b0000000000000000; // 0.0000
cosine = 'b1100000000000000; // -1.0000
end
13: // theta=4.4506
begin
sine = 'b1100001000101111; // -0.9659
cosine = 'b1110111101110000; // -0.2588
end
14: // theta=5.7596
begin
sine = 'b1110000000000000; // -0.5000
cosine = 'b0011011101101100; // 0.8660
end
15: // theta=0.7854
begin
sine = 'b0010110101000001; // 0.7071
cosine = 'b0010110101000001; // 0.7071
end
16: // theta=2.0944
begin
sine = 'b0011011101101100; // 0.8660
cosine = 'b1110000000000000; // -0.5000
end
17: // theta=3.4034
begin
sine = 'b1110111101110000; // -0.2588
cosine = 'b1100001000101111; // -0.9659
end
18: // theta=4.7124
begin
sine = 'b1100000000000000; // -1.0000
cosine = 'b0000000000000000; // -0.0000
end
19: // theta=6.0214
begin
sine = 'b1110111101110000; // -0.2588
cosine = 'b0011110111010001; // 0.9659
end
20: // theta=1.0472
begin
sine = 'b0011011101101100; // 0.8660
cosine = 'b0010000000000000; // 0.5000
end
21: // theta=2.3562
begin
sine = 'b0010110101000001; // 0.7071
cosine = 'b1101001010111111; // -0.7071
end
22: // theta=3.6652
begin
sine = 'b1110000000000001; // -0.5000
cosine = 'b1100100010010100; // -0.8660
end
23: // theta=4.9742
begin
sine = 'b1100001000101111; // -0.9659
cosine = 'b0001000010010000; // 0.2588
end
default:
begin
sine = 'b0000000000000000; // 0
cosine = 'b0000000000000000; // 0
end
endcase
end
endmodule
//*********************************************************************************//
// ** General Information ** //
// ******************************************************************************* //
// ** Module : LkupTbl2.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Date : 2008-08-08 ** //
// ** Description: This is the sine/cosine lookup table for noise channel ** //
// ** Center Frequency: 15MHz ** //
// ** Sampling Frequency: 60MHz ** //
// ** Python file: LUT.py ** //
//*********************************************************************************//
`timescale 1 ns / 100 ps
module LkupTbl2
(//Outputs
cosine,
sine,
//Input
CLK,
ARST,
cntr
);
//******************************************************************************//
//* Declarations *//
//******************************************************************************//
// DATA TYPE - INPUTS AND OUTPUTS
output reg [15:0] sine ;
output reg [15:0] cosine ;
input CLK ;
input ARST ;
input [1:0] cntr ;
//******************************************************************************//
//* Look-Up Table *//
//******************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
sine = 'b0000000000000000; // Reset to 0
cosine = 'b0000000000000000; // Reset to 0
end
else
begin
case (cntr)
0: // theta=0.0000
begin
sine = 'b0000000000000000; // 0.0000
cosine = 'b0100000000000000; // 1.0000
end
1: // theta=1.5708
begin
sine = 'b0100000000000000; // 1.0000
cosine = 'b0000000000000000; // 0.0000
end
2: // theta=3.1416
begin
sine = 'b0000000000000000; // 0.0000
cosine = 'b1100000000000000; // -1.0000
end
3: // theta=4.7124
begin
sine = 'b1100000000000000; // -1.0000
cosine = 'b0000000000000000; // -0.0000
end
default:
begin
sine = 'b0000000000000000; // 0
cosine = 'b0000000000000000; // 0
end
endcase
end
endmodule
//*********************************************************************************//
// ** General Information ** //
// ******************************************************************************* //
// ** Module : LkupTbl3.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Date : 2008-08-08 ** //
// ** Description: This is the sine/cosine lookup table for Channel 2. ** //
// ** Center Frequency: 17.5MHz ** //
// ** Sampling Frequency: 60MHz ** //
// ** Python file: LUT.py ** //
//*********************************************************************************//
`timescale 1 ns / 100 ps
module LkupTbl3
(//Outputs
cosine,
sine,
//Input
CLK,
ARST,
cntr
);
//******************************************************************************//
//* Declarations *//
//******************************************************************************//
// DATA TYPE - INPUTS AND OUTPUTS
output reg [15:0] sine ;
output reg [15:0] cosine ;
input CLK ;
input ARST ;
input [4:0] cntr ;
//******************************************************************************//
//* Look-Up Table *//
//******************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
sine = 'b0000000000000000; // Reset to 0
cosine = 'b0000000000000000; // Reset to 0
end
else
begin
case (cntr)
0: // theta=0.0000
begin
sine = 'b0000000000000000; // 0.0000
cosine = 'b0100000000000000; // 1.0000
end
1: // theta=1.8326
begin
sine = 'b0011110111010001; // 0.9659
cosine = 'b1110111101110000; // -0.2588
end
2: // theta=3.6652
begin
sine = 'b1110000000000001; // -0.5000
cosine = 'b1100100010010100; // -0.8660
end
3: // theta=5.4978
begin
sine = 'b1101001010111111; // -0.7071
cosine = 'b0010110101000001; // 0.7071
end
4: // theta=1.0472
begin
sine = 'b0011011101101100; // 0.8660
cosine = 'b0010000000000000; // 0.5000
end
5: // theta=2.8798
begin
sine = 'b0001000010010000; // 0.2588
cosine = 'b1100001000101111; // -0.9659
end
6: // theta=4.7124
begin
sine = 'b1100000000000000; // -1.0000
cosine = 'b0000000000000000; // -0.0000
end
7: // theta=0.2618
begin
sine = 'b0001000010010000; // 0.2588
cosine = 'b0011110111010001; // 0.9659
end
8: // theta=2.0944
begin
sine = 'b0011011101101100; // 0.8660
cosine = 'b1110000000000001; // -0.5000
end
9: // theta=3.9270
begin
sine = 'b1101001010111111; // -0.7071
cosine = 'b1101001010111111; // -0.7071
end
10: // theta=5.7596
begin
sine = 'b1110000000000000; // -0.5000
cosine = 'b0011011101101100; // 0.8660
end
11: // theta=1.3090
begin
sine = 'b0011110111010001; // 0.9659
cosine = 'b0001000010010000; // 0.2588
end
12: // theta=3.1416
begin
sine = 'b0000000000000000; // 0.0000
cosine = 'b1100000000000000; // -1.0000
end
13: // theta=4.9742
begin
sine = 'b1100001000101111; // -0.9659
cosine = 'b0001000010010000; // 0.2588
end
14: // theta=0.5236
begin
sine = 'b0001111111111111; // 0.5000
cosine = 'b0011011101101100; // 0.8660
end
15: // theta=2.3562
begin
sine = 'b0010110101000001; // 0.7071
cosine = 'b1101001010111111; // -0.7071
end
16: // theta=4.1888
begin
sine = 'b1100100010010100; // -0.8660
cosine = 'b1110000000000000; // -0.5000
end
17: // theta=6.0214
begin
sine = 'b1110111101110000; // -0.2588
cosine = 'b0011110111010001; // 0.9659
end
18: // theta=1.5708
begin
sine = 'b0100000000000000; // 1.0000
cosine = 'b0000000000000000; // -0.0000
end
19: // theta=3.4034
begin
sine = 'b1110111101110000; // -0.2588
cosine = 'b1100001000101111; // -0.9659
end
20: // theta=5.2360
begin
sine = 'b1100100010010100; // -0.8660
cosine = 'b0001111111111111; // 0.5000
end
21: // theta=0.7854
begin
sine = 'b0010110101000001; // 0.7071
cosine = 'b0010110101000001; // 0.7071
end
22: // theta=2.6180
begin
sine = 'b0010000000000000; // 0.5000
cosine = 'b1100100010010100; // -0.8660
end
23: // theta=4.4506
begin
sine = 'b1100001000101111; // -0.9659
cosine = 'b1110111101110000; // -0.2588
end
default:
begin
sine = 'b0000000000000000; // 0
cosine = 'b0000000000000000; // 0
end
endcase
end
endmodule
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : MAC1.v ** //
// ** Project : ISAAC Newton ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 13, 2008 ** //
// ** Description : Multiplier-Accumulator Module ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : MAC1.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 13, 2008 ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module MAC1
(// Inputs
CLK , // Clock
ARST , // Reset
filterCoef , // Filter Coeficients
InData , // Input Data
input_Valid , // Input Valid
initialize , // Initialize
// Outputs
OutData , // Output Data
output_Valid // Output Valid
);
//**************************************************************************//
//* Declarations *//
//**************************************************************************//
// DATA TYPE - PARAMETERS
parameter IWIDTH = 16; // Input bit width
parameter OWIDTH = 32; // Output bit width
parameter AWIDTH = 32; // Internal bit width
parameter NTAPS = 15; // Total number of taps including zeros
parameter NTAPSr = 15; // Real number of taps in the filter
parameter CNTWIDTH = 4 ; // Count bit width, depends on number of taps
parameter NMULT = 1 ; // Number of clocks it takes for multiplier
// to generate an answer
// DATA TYPE - INPUTS AND OUTPUTS
input CLK ; // 60MHz Clock
input ARST ;
input input_Valid ;
input initialize ;
input signed [(IWIDTH-1):0] InData, filterCoef ;
output signed [(OWIDTH-1):0] OutData ;
output output_Valid ;
// DATA TYPE - REGISTERS
reg signed [(AWIDTH-1):0] mult, accum ;
reg input_Valid0 ;
reg initialize1 ;
reg output_Valid_1 ;
wire output_Valid ;
reg [CNTWIDTH-1:0] count ;
// DATA TYPE - WIRES
wire signed [(AWIDTH-1):0] accum_tmp ;
wire [CNTWIDTH-1:0] taps ;
assign taps = (NTAPS == NTAPSr) ? 0: (NTAPS - NTAPS + NTAPSr) ;
//**************************************************************************//
//* Input Buffers *//
//**************************************************************************//
always @(posedge CLK or posedge ARST)
if (ARST) input_Valid0 <= 1'b0 ;
else input_Valid0 <= input_Valid ;
always @(posedge CLK or posedge ARST)
if (ARST) initialize1 <= 1'b0 ;
else initialize1 <= initialize ;
//**************************************************************************//
//* Multiply-Accumulate *//
//**************************************************************************//
// Multiplier
always @(posedge CLK or posedge ARST)
if (ARST) mult[(AWIDTH-1):0] <= {(AWIDTH-1){1'b0}} ;
else mult[(AWIDTH-1):0] <= filterCoef*InData ;
assign accum_tmp[(AWIDTH-1):0] = mult[(AWIDTH-1):0] + accum[(AWIDTH-1):0];
// Accumulator
always @(posedge CLK or posedge ARST)// or initialize)
if (ARST) accum[(OWIDTH-1):0] <= {(OWIDTH){1'b0}} ;
else accum[(OWIDTH-1):0] <= (initialize1) ?
mult[(AWIDTH-1):0] :
(input_Valid0 ? accum_tmp[(AWIDTH-1):0]
: accum[(AWIDTH-1):0]) ;
//**************************************************************************//
//* Counters *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST) count[CNTWIDTH-1:0] <= {(CNTWIDTH){1'b0}} ;
else count[CNTWIDTH-1:0] <= initialize ?
0 :
input_Valid0 + count[CNTWIDTH-1:0] ;
//**************************************************************************//
//* Output Buffers *//
//**************************************************************************//
always @(posedge CLK or posedge ARST)
if (ARST) output_Valid_1 <= 1'b0 ;
else output_Valid_1 <= (count[CNTWIDTH-1:0]==(NTAPSr-1+NMULT-1)) ;
assign output_Valid = output_Valid_1 & (count[CNTWIDTH-1:0]==taps) ;
assign OutData[(OWIDTH-1):0] = accum[(OWIDTH-1):0] ;
endmodule //MAC1// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : QM.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 13, 2008 ** //
// ** Description : Quadrature Modulation. ** //
// ** Using sin/cos look up table. ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : QM.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 13, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module QM
(// Inputs
CLK ,
ARST ,
Sync ,
Constant ,
InputValid ,
//Outputs
Real1 ,
Imag1 ,
Real2 ,
Imag2 ,
Real3 ,
Imag3 ,
OutputValid
// tp_1 //To print out QM output, use this as the DataValid
);
//**************************************************************************//
//* Declarations *//
//**************************************************************************//
// DATA TYPE - PARAMETERS
parameter OWIDTH = 16 ; // output bit width
parameter IWIDTH = 16 ; // input bit width
parameter MAXCNT1 = 23 ; // Counter up to repeating for ch1&2
parameter MAXCNT2 = 3 ; // Counter up to repeating for ch3
parameter CNTWIDTH1 = 5 ; // counter bit width for ch1 & ch2
parameter CNTWIDTH2 = 2 ; // counter bit width for ch3 (noise)
// DATA TYPE - INPUTS AND OUTPUTS
input signed [IWIDTH-1:0] Constant ;
input CLK ;
input ARST ;
input InputValid ;
input Sync ;
output reg signed [OWIDTH-1:0] Real1 ;
output reg signed [OWIDTH-1:0] Real2 ;
output reg signed [OWIDTH-1:0] Real3 ;
output reg signed [OWIDTH-1:0] Imag1 ;
output reg signed [OWIDTH-1:0] Imag2 ;
output reg signed [OWIDTH-1:0] Imag3 ;
output reg OutputValid ;
// output tp_1 ; // only used to print results from
// test bench
// DATA TYPE - REGISTERS
reg [CNTWIDTH1-1:0] counter1 ;
reg [CNTWIDTH2-1:0] counter2 ;
reg signed [IWIDTH-1:0] Constant1 ;
reg OutputValid1;
// DATA TYPE - WIRES
wire signed [31:0] Real_1 ;
wire signed [31:0] Real_2 ;
wire signed [31:0] Real_3 ;
wire signed [31:0] Imag_1 ;
wire signed [31:0] Imag_2 ;
wire signed [31:0] Imag_3 ;
wire signed [15:0] Cosine1 ;
wire signed [15:0] Cosine2 ;
wire signed [15:0] Cosine3 ;
wire signed [15:0] Sine1 ;
wire signed [15:0] Sine2 ;
wire signed [15:0] Sine3 ;
//**************************************************************************//
//* Counters *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
counter1[CNTWIDTH1-1:0] <= {(CNTWIDTH1){1'b0}};
counter2[CNTWIDTH2-1:0] <= {(CNTWIDTH2){1'b0}};
end
else if (Sync)
begin
counter1[CNTWIDTH1-1:0] <= {(CNTWIDTH1){1'b0}};
counter2[CNTWIDTH2-1:0] <= {(CNTWIDTH2){1'b0}};
end
else
begin
counter1[CNTWIDTH1-1:0] <= InputValid ?
(counter1[CNTWIDTH1-1:0] == MAXCNT1) ? 0
: (counter1[CNTWIDTH1-1:0] + 1)
: counter1[CNTWIDTH1-1:0];
counter2[CNTWIDTH2-1:0] <= InputValid ?
(counter2[CNTWIDTH2-1:0] == MAXCNT2) ? 0
: (counter2[CNTWIDTH2-1:0] + 1)
: counter2[CNTWIDTH2-1:0];
end
//**************************************************************************//
//* Output Buffers *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
OutputValid <= 1'b0 ;
OutputValid1 <= 1'b0 ;
Constant1[15:0] <= 16'sb0000_0000_0000_0000 ;
end
else
begin
OutputValid <= OutputValid1 ;
OutputValid1 <= InputValid ;
Constant1[15:0] <= Constant[15:0] ;
end
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
Real1[15:0] <= {(16){1'b0}} ;
Imag1[15:0] <= {(16){1'b0}} ;
Real2[15:0] <= {(16){1'b0}} ;
Imag2[15:0] <= {(16){1'b0}} ;
Real3[15:0] <= {(16){1'b0}} ;
Imag3[15:0] <= {(16){1'b0}} ;
end
else
begin
Real1[15:0] <= Real_1[29:14];
Imag1[15:0] <= Imag_1[29:14];
Real2[15:0] <= Real_2[29:14];
Imag2[15:0] <= Imag_2[29:14];
Real3[15:0] <= Real_3[29:14];
Imag3[15:0] <= Imag_3[29:14];
end
assign Real_1[31:0] = Cosine1 * Constant1 ;
assign Imag_1[31:0] = Sine1 * Constant1 ;
assign Real_2[31:0] = Cosine2 * Constant1 ;
assign Imag_2[31:0] = Sine2 * Constant1 ;
assign Real_3[31:0] = Cosine3 * Constant1 ;
assign Imag_3[31:0] = Sine3 * Constant1 ;
assign tp_1 = OutputValid1 ;
//**************************************************************************//
//* Submodules *//
//**************************************************************************//
LkupTbl1 LkupTbl1 // Channel1 Sin/Cos Table Lookup
(.cntr (counter1), // Bus [9 : 0]
.CLK (CLK),
.ARST (ARST),
.sine (Sine1), // Bus [15 : 0]
.cosine (Cosine1) // Bus [15:0]
);
LkupTbl2 LkupTbl2 // Noise Sin/Cos Table Lookup
(.cntr (counter2), // Bus [9 : 0]
.CLK (CLK),
.ARST (ARST),
.sine (Sine2), // Bus [15 : 0]
.cosine (Cosine2) // Bus [15:0]
);
LkupTbl3 LkupTbl3 // Channel2 Sin/Cos Table Lookup
(.cntr (counter1), // Bus [9 : 0]
.CLK (CLK),
.ARST (ARST),
.sine (Sine3), // Bus [15 : 0]
.cosine (Cosine3) // Bus [15:0]
);
endmodule // QM
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : QM_FIR.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Original Author : Kayla Nguyen ** //
// ** First Release Date : August 13, 2008 ** //
// ** Description : Quadrature Modulation and Polyphase Decimation. ** //
// ** This module gives both the real part and the ** //
// ** ofimaginary part the along with their polyphase ** //
// ** decimation. ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : QM_FIR.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 13, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module QM_FIR
(//Inputs
CLK ,
ARST ,
Sync ,
Constant ,
InputValid ,
//Ouputs
RealOut1 ,
ImagOut1 ,
RealOut2 ,
ImagOut2 ,
RealOut3 ,
ImagOut3 ,
DataValid_R,
DataValid_I
);
//*****************************************************************************//
//* Declarations *//
//*****************************************************************************//
// DATA TYPE - INPUTS AND OUTPUTS
output signed [15:0] RealOut1, RealOut2, RealOut3;
output signed [15:0] ImagOut1, ImagOut2, ImagOut3;
output DataValid_R;
output DataValid_I;
input signed [15:0] Constant;
input CLK;
input ARST;
input Sync;
input InputValid;
// DATA TYPE - WIRES
wire OutputValid_QM;
wire signed [15:0] Real1, Real2, Real3;
wire signed [15:0] Imag1, Imag2, Imag3;
//*****************************************************************************//
//* Submodules *//
//*****************************************************************************//
//Quadrature Modulation
QM QM
(//Inputs
.CLK (CLK),
.ARST (ARST),
.Sync (Sync),
.Constant (Constant),
.InputValid (InputValid),
//Outputs
.Real1 (Real1), // Channel1 Real
.Imag1 (Imag1), // Channel1 Imag
.Real2 (Real2), // Noise Channel Real
.Imag2 (Imag2), // Noise Channel Imag
.Real3 (Real3), // Channel2 Real
.Imag3 (Imag3), // Channel2 Imag
.OutputValid (OutputValid_QM)
//.tp_1(tp_1) // To print out QM output, use this as the DataValid
);
//Firdecim 1st channel Real Filter
firdecim firdecimR1
(//Inputs
.CLK (CLK),
.ARST (ARST),
.Sync (Sync),
.InputValid (OutputValid_QM),
.SigIn (Real1),
//Outputs
.SigOut (RealOut1),
.DataValid (DataValid_R)
);
//Firdecim 1st channel Imaginary Filter
firdecim firdecimI1
(//Inputs
.CLK (CLK),
.ARST (ARST),
.Sync (Sync),
.InputValid (OutputValid_QM),
.SigIn (Imag1),
//Outputs
.SigOut (ImagOut1),
.DataValid (DataValid_I)
);
//Firdecim noise channel Real Filter
firdecim firdecimR2
(//Inputs
.CLK (CLK),
.ARST (ARST),
.Sync (Sync),
.InputValid (OutputValid_QM),
.SigIn (Real2),
//Outputs
.SigOut (RealOut2)
//.DataValid (DataValid_R)
);
//Firdecim noise channel Imaginary Filter
firdecim firdecimI2
(//Inputs
.CLK (CLK),
.ARST (ARST),
.Sync (Sync),
.InputValid (OutputValid_QM),
.SigIn (Imag2),
//Outputs
.SigOut (ImagOut2)
//.DataValid (DataValid_I)
);
//Firdecim 2nd channel Real Filter
firdecim firdecimR3
(//Inputs
.CLK (CLK),
.ARST (ARST),
.Sync (Sync),
.InputValid (OutputValid_QM),
.SigIn (Real3),
//Outputs
.SigOut (RealOut3)
//.DataValid (DataValid_R)
);
//Firdecim 2nd channel Imaginary Filter
firdecim firdecimI3
(//Inputs
.CLK (CLK),
.ARST (ARST),
.Sync (Sync),
.InputValid (OutputValid_QM),
.SigIn (Imag3),
//Outputs
.SigOut (ImagOut3)
//.DataValid (DataValid_I)
);
endmodule // QM_FIR
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : firdecim.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 13, 2008 ** //
// ** Description : Polyphase Decimation Filter: 3 stages. ** //
// ** FIRDECIM1: M = 5, L = 15 ** //
// ** FIRDECIM1: M = 5, L = 20 ** //
// ** FIRDECIM1: M = 2, L = 50 ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : firdecim.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 13, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module firdecim
(//Outputs
SigOut, // Third Stage Output
DataValid,// Third Stage DataValid
//Inputs
CLK,
ARST,
InputValid,
Sync,
SigIn
);
//******************************************************************************//
//* Declarations *//
//******************************************************************************//
//DATA TYPE - INPUTS AND OUTPUTS
output signed [15:0] SigOut ;
output DataValid;
input CLK;
input ARST;
input Sync;
input InputValid;
input signed [15:0] SigIn;
// DATA TYPE - WIRES
wire signed [31:0] SigOut1, SigOut_tmp, SigOut2;
//******************************************************************************//
//* Output Buffers *//
//******************************************************************************//
assign SigOut[15:0] = SigOut_tmp[29:14];
//******************************************************************************//
//* Submodules *//
//******************************************************************************//
// First firdecim filter
firdecim_m5_n15 firdecim1
(//Inputs
.CLK (CLK),
.ARST (ARST),
.Sync (Sync),
.InputValid (InputValid),
.SigIn (SigIn),
//Outputs
.DataValid (DataValid1),
.SigOut (SigOut1)
);
// Second firdecim filter
firdecim_m5_n20 firdecim2
(// Inputs
.CLK (CLK),
.ARST (ARST),
.Sync (Sync),
.InputValid (DataValid1),
.SigIn (SigOut1[29:14]),
// Outputs
.DataValid (DataValid2),
.SigOut (SigOut2[31:0])
);
// Third firdecim filter
firdecim_m2_n50 firdecim3
(// Inputs
.CLK (CLK),
.ARST (ARST),
.Sync (Sync),
.InputValid (DataValid2),
.SigIn (SigOut2[29:14]),
// Outputs
.DataValid (DataValid),
.SigOut (SigOut_tmp[31:0])
);
endmodule // firdecim
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : firdecim_m2_n50.v ** //
// ** Project : ISAAC Newton ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 13, 2008 ** //
// ** Description : Polyphase Decimation Filter ** //
// ** M = 2, L = 50 ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : firdecim_m2_n50.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 13, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module firdecim_m2_n50
(// Input
CLK,
ARST,
Sync,
InputValid,
SigIn,
// Output
DataValid,
SigOut
);
//**************************************************************************//
//* Declarations *//
//**************************************************************************//
// DATA TYPE - PARAMETERS
parameter e49 = 16'sb0000_0000_0010_1001;
parameter e48 = 16'sb0000_0000_0001_0010;
parameter e47 = 16'sb1111_1111_1010_0000;
parameter e46 = 16'sb1111_1111_0011_1100;
parameter e45 = 16'sb1111_1111_1000_1011;
parameter e44 = 16'sb0000_0000_0100_1010;
parameter e43 = 16'sb0000_0000_0110_1011;
parameter e42 = 16'sb1111_1111_1010_1110;
parameter e41 = 16'sb1111_1111_0100_1101;
parameter e40 = 16'sb0000_0000_0010_0000;
parameter e39 = 16'sb0000_0000_1110_1110;
parameter e38 = 16'sb0000_0000_0010_1101;
parameter e37 = 16'sb1111_1110_1101_1101;
parameter e36 = 16'sb1111_1111_0101_1000;
parameter e35 = 16'sb0000_0001_0011_1100;
parameter e34 = 16'sb0000_0001_0101_0100;
parameter e33 = 16'sb1111_1110_1101_1011;
parameter e32 = 16'sb1111_1101_1100_0101;
parameter e31 = 16'sb0000_0000_1011_1100;
parameter e30 = 16'sb0000_0011_0111_1011;
parameter e29 = 16'sb0000_0000_0100_1000;
parameter e28 = 16'sb1111_1010_0111_0101;
parameter e27 = 16'sb1111_1100_1111_1001;
parameter e26 = 16'sb0000_1011_1000_1111;
parameter e25 = 16'sb0001_1010_0110_0111;
parameter e24 = 16'sb0001_1010_0110_0111;
parameter e23 = 16'sb0000_1011_1000_1111;
parameter e22 = 16'sb1111_1100_1111_1001;
parameter e21 = 16'sb1111_1010_0111_0101;
parameter e20 = 16'sb0000_0000_0100_1000;
parameter e19 = 16'sb0000_0011_0111_1011;
parameter e18 = 16'sb0000_0000_1011_1100;
parameter e17 = 16'sb1111_1101_1100_0101;
parameter e16 = 16'sb1111_1110_1101_1011;
parameter e15 = 16'sb0000_0001_0101_0100;
parameter e14 = 16'sb0000_0001_0011_1100;
parameter e13 = 16'sb1111_1111_0101_1000;
parameter e12 = 16'sb1111_1110_1101_1101;
parameter e11 = 16'sb0000_0000_0010_1101;
parameter e10 = 16'sb0000_0000_1110_1110;
parameter e9 = 16'sb0000_0000_0010_0000;
parameter e8 = 16'sb1111_1111_0100_1101;
parameter e7 = 16'sb1111_1111_1010_1110;
parameter e6 = 16'sb0000_0000_0110_1011;
parameter e5 = 16'sb0000_0000_0100_1010;
parameter e4 = 16'sb1111_1111_1000_1011;
parameter e3 = 16'sb1111_1111_0011_1100;
parameter e2 = 16'sb1111_1111_1010_0000;
parameter e1 = 16'sb0000_0000_0001_0010;
parameter e0 = 16'sb0000_0000_0010_1001;
parameter OWIDTH = 32 ; // output bit width
parameter IWIDTH = 16 ; // input bit width
parameter AWIDTH = 32 ; // internal bit width
parameter NTAPS = 50 ; // number of filter taps
parameter ACCUMCNTWIDTH = 5 ; // accumulator count bit width
parameter CNTWIDTH = 6 ; // counter bit width
parameter NACCUM = 25 ; // numbers of accumulators
// DATA TYPE - INPUTS AND OUTPUTS
output reg signed [OWIDTH-1:0] SigOut ;
output reg DataValid ;
input CLK ; // 60MHz Clock
input ARST ;
input InputValid ;
input signed [IWIDTH-1:0] SigIn ;
input Sync ;
// DATA TYPE - REGISTERS
reg signed [IWIDTH-1:0] coe49 ;
reg signed [IWIDTH-1:0] coe48 ;
reg signed [IWIDTH-1:0] coe47 ;
reg signed [IWIDTH-1:0] coe46 ;
reg signed [IWIDTH-1:0] coe45 ;
reg signed [IWIDTH-1:0] coe44 ;
reg signed [IWIDTH-1:0] coe43 ;
reg signed [IWIDTH-1:0] coe42 ;
reg signed [IWIDTH-1:0] coe41 ;
reg signed [IWIDTH-1:0] coe40 ;
reg signed [IWIDTH-1:0] coe39 ;
reg signed [IWIDTH-1:0] coe38 ;
reg signed [IWIDTH-1:0] coe37 ;
reg signed [IWIDTH-1:0] coe36 ;
reg signed [IWIDTH-1:0] coe35 ;
reg signed [IWIDTH-1:0] coe34 ;
reg signed [IWIDTH-1:0] coe33 ;
reg signed [IWIDTH-1:0] coe32 ;
reg signed [IWIDTH-1:0] coe31 ;
reg signed [IWIDTH-1:0] coe30 ;
reg signed [IWIDTH-1:0] coe29 ;
reg signed [IWIDTH-1:0] coe28 ;
reg signed [IWIDTH-1:0] coe27 ;
reg signed [IWIDTH-1:0] coe26 ;
reg signed [IWIDTH-1:0] coe25 ;
reg signed [IWIDTH-1:0] coe24 ;
reg signed [IWIDTH-1:0] coe23 ;
reg signed [IWIDTH-1:0] coe22 ;
reg signed [IWIDTH-1:0] coe21 ;
reg signed [IWIDTH-1:0] coe20 ;
reg signed [IWIDTH-1:0] coe19 ;
reg signed [IWIDTH-1:0] coe18 ;
reg signed [IWIDTH-1:0] coe17 ;
reg signed [IWIDTH-1:0] coe16 ;
reg signed [IWIDTH-1:0] coe15 ;
reg signed [IWIDTH-1:0] coe14 ;
reg signed [IWIDTH-1:0] coe13 ;
reg signed [IWIDTH-1:0] coe12 ;
reg signed [IWIDTH-1:0] coe11 ;
reg signed [IWIDTH-1:0] coe10 ;
reg signed [IWIDTH-1:0] coe9 ;
reg signed [IWIDTH-1:0] coe8 ;
reg signed [IWIDTH-1:0] coe7 ;
reg signed [IWIDTH-1:0] coe6 ;
reg signed [IWIDTH-1:0] coe5 ;
reg signed [IWIDTH-1:0] coe4 ;
reg signed [IWIDTH-1:0] coe3 ;
reg signed [IWIDTH-1:0] coe2 ;
reg signed [IWIDTH-1:0] coe1 ;
reg signed [IWIDTH-1:0] coe0 ;
reg [CNTWIDTH-1:0] count ;
reg [CNTWIDTH-1:0] count1 ;
reg [ACCUMCNTWIDTH-1:0] accum_cnt ; //Counter to keep track of which
//accumulator is being accessed.
reg InputValid0 ;
reg InputValid1;
reg signed [IWIDTH-1:0] SigIn1 ;
reg signed [IWIDTH-1:0] SigIn2 ;
reg signed [AWIDTH-1:0] mult ;
reg signed [AWIDTH-1:0] accum1 ; //First accumulator
reg signed [AWIDTH-1:0] accum2 ; //Second accumulator
reg signed [AWIDTH-1:0] accum3 ; //Rhird accumulator
reg signed [AWIDTH-1:0] accum4 ; //Fourth accumulator
reg signed [AWIDTH-1:0] accum5 ; //Fifth accumulator
reg signed [AWIDTH-1:0] accum6 ; //Sixth accumulator
reg signed [AWIDTH-1:0] accum7 ; //Seventh accumulator
reg signed [AWIDTH-1:0] accum8 ; //Eigth accumulator
reg signed [AWIDTH-1:0] accum9 ; //Ninth accumulator
reg signed [AWIDTH-1:0] accum10 ; //Tenth accumulator
reg signed [AWIDTH-1:0] accum11 ; //Eleventh accumulator
reg signed [AWIDTH-1:0] accum12 ; //Twelve accumulator
reg signed [AWIDTH-1:0] accum13 ; //Thirteenth accumulator
reg signed [AWIDTH-1:0] accum14 ; //Fourteenth accumulator
reg signed [AWIDTH-1:0] accum15 ; //Fifteenth accumulator
reg signed [AWIDTH-1:0] accum16 ; //Sixteenth accumulator
reg signed [AWIDTH-1:0] accum17 ; //Seventeenth accumulator
reg signed [AWIDTH-1:0] accum18 ; //Eighteenth accumulator
reg signed [AWIDTH-1:0] accum19 ; //Ninteenth accumulator
reg signed [AWIDTH-1:0] accum20 ; //20th accumulator
reg signed [AWIDTH-1:0] accum21 ; //21st accumulator
reg signed [AWIDTH-1:0] accum22 ; //22nd accumulator
reg signed [AWIDTH-1:0] accum23 ; //23rd accumulator
reg signed [AWIDTH-1:0] accum24 ; //24th accumulator
reg signed [AWIDTH-1:0] accum25 ; //25th accumulator
reg signed [IWIDTH-1:0] coef1 ;
reg signed [IWIDTH-1:0] coef2 ;
reg signed [IWIDTH-1:0] coef3 ;
reg signed [IWIDTH-1:0] coef4 ;
reg signed [IWIDTH-1:0] coef ;
reg [ACCUMCNTWIDTH-1:0] accum_cnt1 ;
// DATA TYPE - WIRES
wire valid ;
wire valid1 ;
wire valid2 ;
wire valid3 ;
wire valid4 ;
wire valid5 ;
wire valid6 ;
wire valid7 ;
wire valid8 ;
wire valid9 ;
wire valid10 ;
wire valid11 ;
wire valid12 ;
wire valid13 ;
wire valid14 ;
wire valid15 ;
wire valid16 ;
wire valid17 ;
wire valid18 ;
wire valid19 ;
wire valid20 ;
wire valid21 ;
wire valid22 ;
wire valid23 ;
wire valid24 ;
wire valid25 ;
//**************************************************************************//
//* Input Buffers *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
InputValid0 <= 1'b0 ;
InputValid1 <= 1'b0 ;
end
else
begin
InputValid0 <= InputValid1;
InputValid1 <= InputValid ;
end
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
SigIn1[IWIDTH-1:0] <= {(IWIDTH){1'b0}} ;
SigIn2[IWIDTH-1:0] <= {(IWIDTH){1'b0}};
end
else
begin
SigIn2[IWIDTH-1:0] <= SigIn[IWIDTH-1:0];
SigIn1[IWIDTH-1:0] <= SigIn2[IWIDTH-1:0];
end
//**************************************************************************//
//* Coefficient Rotation / Selector *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
coef1[IWIDTH-1:0] <= {(IWIDTH){1'b0}} ;
else
case (accum_cnt[2:0])
3'b000: coef1[IWIDTH-1:0] <= coe0[IWIDTH-1:0];
3'b001: coef1[IWIDTH-1:0] <= coe2[IWIDTH-1:0];
3'b010: coef1[IWIDTH-1:0] <= coe4[IWIDTH-1:0];
3'b011: coef1[IWIDTH-1:0] <= coe6[IWIDTH-1:0];
3'b100: coef1[IWIDTH-1:0] <= coe8[IWIDTH-1:0];
3'b101: coef1[IWIDTH-1:0] <= coe10[IWIDTH-1:0];
3'b110: coef1[IWIDTH-1:0] <= coe12[IWIDTH-1:0];
3'b111: coef1[IWIDTH-1:0] <= coe14[IWIDTH-1:0];
endcase // case (accum_cnt[2:0])
always @ (posedge CLK or posedge ARST)
if (ARST)
coef2[IWIDTH-1:0] <= {(IWIDTH){1'b0}};
else
case (accum_cnt[2:0])
3'b000: coef2[IWIDTH-1:0] <= coe16[IWIDTH-1:0];
3'b001: coef2[IWIDTH-1:0] <= coe18[IWIDTH-1:0];
3'b010: coef2[IWIDTH-1:0] <= coe20[IWIDTH-1:0];
3'b011: coef2[IWIDTH-1:0] <= coe22[IWIDTH-1:0];
3'b100: coef2[IWIDTH-1:0] <= coe24[IWIDTH-1:0];
3'b101: coef2[IWIDTH-1:0] <= coe26[IWIDTH-1:0];
3'b110: coef2[IWIDTH-1:0] <= coe28[IWIDTH-1:0];
3'b111: coef2[IWIDTH-1:0] <= coe30[IWIDTH-1:0];
endcase // case (accumt_cnt[2:0])
always @ (posedge CLK or posedge ARST)
if (ARST)
coef3[IWIDTH-1:0] <= {(IWIDTH){1'b0}};
else
case (accum_cnt[2:0])
3'b000: coef3[IWIDTH-1:0] <= coe32[IWIDTH-1:0];
3'b001: coef3[IWIDTH-1:0] <= coe34[IWIDTH-1:0];
3'b010: coef3[IWIDTH-1:0] <= coe36[IWIDTH-1:0];
3'b011: coef3[IWIDTH-1:0] <= coe38[IWIDTH-1:0];
3'b100: coef3[IWIDTH-1:0] <= coe40[IWIDTH-1:0];
3'b101: coef3[IWIDTH-1:0] <= coe42[IWIDTH-1:0];
3'b110: coef3[IWIDTH-1:0] <= coe44[IWIDTH-1:0];
3'b111: coef3[IWIDTH-1:0] <= coe46[IWIDTH-1:0];
endcase // case (accumt_cnt[2:0])
always @ (posedge CLK or posedge ARST)
if (ARST) coef4[IWIDTH-1:0] <= {(IWIDTH){1'b0}} ;
else coef4[IWIDTH-1:0] <= coe48[IWIDTH-1:0] ;
always @ (accum_cnt1 or coef1 or coef2 or coef3 or coef4)
begin
case (accum_cnt1[4:3])
2'b00: coef[IWIDTH-1:0] = coef1[IWIDTH-1:0];
2'b01: coef[IWIDTH-1:0] = coef2[IWIDTH-1:0];
2'b10: coef[IWIDTH-1:0] = coef3[IWIDTH-1:0];
2'b11: coef[IWIDTH-1:0] = coef4[IWIDTH-1:0];
default: coef[IWIDTH-1:0] = coef4[IWIDTH-1:0];
endcase // case (accum_cnt[4:3])
end
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
coe49[IWIDTH-1:0] <= e48 ;
coe48[IWIDTH-1:0] <= e47 ;
coe47[IWIDTH-1:0] <= e46 ;
coe46[IWIDTH-1:0] <= e45 ;
coe45[IWIDTH-1:0] <= e44 ;
coe44[IWIDTH-1:0] <= e43 ;
coe43[IWIDTH-1:0] <= e42 ;
coe42[IWIDTH-1:0] <= e41 ;
coe41[IWIDTH-1:0] <= e40 ;
coe40[IWIDTH-1:0] <= e39 ;
coe39[IWIDTH-1:0] <= e38 ;
coe38[IWIDTH-1:0] <= e37 ;
coe37[IWIDTH-1:0] <= e36 ;
coe36[IWIDTH-1:0] <= e35 ;
coe35[IWIDTH-1:0] <= e34 ;
coe34[IWIDTH-1:0] <= e33 ;
coe33[IWIDTH-1:0] <= e32 ;
coe32[IWIDTH-1:0] <= e31 ;
coe31[IWIDTH-1:0] <= e30 ;
coe30[IWIDTH-1:0] <= e29 ;
coe29[IWIDTH-1:0] <= e28 ;
coe28[IWIDTH-1:0] <= e27 ;
coe27[IWIDTH-1:0] <= e26 ;
coe26[IWIDTH-1:0] <= e25 ;
coe25[IWIDTH-1:0] <= e24 ;
coe24[IWIDTH-1:0] <= e23 ;
coe23[IWIDTH-1:0] <= e22 ;
coe22[IWIDTH-1:0] <= e21 ;
coe21[IWIDTH-1:0] <= e20 ;
coe20[IWIDTH-1:0] <= e19 ;
coe19[IWIDTH-1:0] <= e18 ;
coe18[IWIDTH-1:0] <= e17 ;
coe17[IWIDTH-1:0] <= e16 ;
coe16[IWIDTH-1:0] <= e15 ;
coe15[IWIDTH-1:0] <= e14 ;
coe14[IWIDTH-1:0] <= e13 ;
coe13[IWIDTH-1:0] <= e12 ;
coe12[IWIDTH-1:0] <= e11 ;
coe11[IWIDTH-1:0] <= e10 ;
coe10[IWIDTH-1:0] <= e9 ;
coe9[IWIDTH-1:0] <= e8 ;
coe8[IWIDTH-1:0] <= e7 ;
coe7[IWIDTH-1:0] <= e6 ;
coe6[IWIDTH-1:0] <= e5 ;
coe5[IWIDTH-1:0] <= e4 ;
coe4[IWIDTH-1:0] <= e3 ;
coe3[IWIDTH-1:0] <= e2 ;
coe2[IWIDTH-1:0] <= e1 ;
coe1[IWIDTH-1:0] <= e0 ;
coe0[IWIDTH-1:0] <= e49 ;
end // if (ARST)
else if (Sync)
begin
coe49[IWIDTH-1:0] <= e48 ;
coe48[IWIDTH-1:0] <= e47 ;
coe47[IWIDTH-1:0] <= e46 ;
coe46[IWIDTH-1:0] <= e45 ;
coe45[IWIDTH-1:0] <= e44 ;
coe44[IWIDTH-1:0] <= e43 ;
coe43[IWIDTH-1:0] <= e42 ;
coe42[IWIDTH-1:0] <= e41 ;
coe41[IWIDTH-1:0] <= e40 ;
coe40[IWIDTH-1:0] <= e39 ;
coe39[IWIDTH-1:0] <= e38 ;
coe38[IWIDTH-1:0] <= e37 ;
coe37[IWIDTH-1:0] <= e36 ;
coe36[IWIDTH-1:0] <= e35 ;
coe35[IWIDTH-1:0] <= e34 ;
coe34[IWIDTH-1:0] <= e33 ;
coe33[IWIDTH-1:0] <= e32 ;
coe32[IWIDTH-1:0] <= e31 ;
coe31[IWIDTH-1:0] <= e30 ;
coe30[IWIDTH-1:0] <= e29 ;
coe29[IWIDTH-1:0] <= e28 ;
coe28[IWIDTH-1:0] <= e27 ;
coe27[IWIDTH-1:0] <= e26 ;
coe26[IWIDTH-1:0] <= e25 ;
coe25[IWIDTH-1:0] <= e24 ;
coe24[IWIDTH-1:0] <= e23 ;
coe23[IWIDTH-1:0] <= e22 ;
coe22[IWIDTH-1:0] <= e21 ;
coe21[IWIDTH-1:0] <= e20 ;
coe20[IWIDTH-1:0] <= e19 ;
coe19[IWIDTH-1:0] <= e18 ;
coe18[IWIDTH-1:0] <= e17 ;
coe17[IWIDTH-1:0] <= e16 ;
coe16[IWIDTH-1:0] <= e15 ;
coe15[IWIDTH-1:0] <= e14 ;
coe14[IWIDTH-1:0] <= e13 ;
coe13[IWIDTH-1:0] <= e12 ;
coe12[IWIDTH-1:0] <= e11 ;
coe11[IWIDTH-1:0] <= e10 ;
coe10[IWIDTH-1:0] <= e9 ;
coe9[IWIDTH-1:0] <= e8 ;
coe8[IWIDTH-1:0] <= e7 ;
coe7[IWIDTH-1:0] <= e6 ;
coe6[IWIDTH-1:0] <= e5 ;
coe5[IWIDTH-1:0] <= e4 ;
coe4[IWIDTH-1:0] <= e3 ;
coe3[IWIDTH-1:0] <= e2 ;
coe2[IWIDTH-1:0] <= e1 ;
coe1[IWIDTH-1:0] <= e0 ;
coe0[IWIDTH-1:0] <= e49 ;
end
else if (InputValid)
begin
coe49[IWIDTH-1:0] <= coe0[IWIDTH-1:0];
coe48[IWIDTH-1:0] <= coe49[IWIDTH-1:0] ;
coe47[IWIDTH-1:0] <= coe48[IWIDTH-1:0] ;
coe46[IWIDTH-1:0] <= coe47[IWIDTH-1:0] ;
coe45[IWIDTH-1:0] <= coe46[IWIDTH-1:0] ;
coe44[IWIDTH-1:0] <= coe45[IWIDTH-1:0] ;
coe43[IWIDTH-1:0] <= coe44[IWIDTH-1:0] ;
coe42[IWIDTH-1:0] <= coe43[IWIDTH-1:0] ;
coe41[IWIDTH-1:0] <= coe42[IWIDTH-1:0] ;
coe40[IWIDTH-1:0] <= coe41[IWIDTH-1:0] ;
coe39[IWIDTH-1:0] <= coe40[IWIDTH-1:0] ;
coe38[IWIDTH-1:0] <= coe39[IWIDTH-1:0] ;
coe37[IWIDTH-1:0] <= coe38[IWIDTH-1:0] ;
coe36[IWIDTH-1:0] <= coe37[IWIDTH-1:0] ;
coe35[IWIDTH-1:0] <= coe36[IWIDTH-1:0] ;
coe34[IWIDTH-1:0] <= coe35[IWIDTH-1:0] ;
coe33[IWIDTH-1:0] <= coe34[IWIDTH-1:0] ;
coe32[IWIDTH-1:0] <= coe33[IWIDTH-1:0] ;
coe31[IWIDTH-1:0] <= coe32[IWIDTH-1:0] ;
coe30[IWIDTH-1:0] <= coe31[IWIDTH-1:0] ;
coe29[IWIDTH-1:0] <= coe30[IWIDTH-1:0] ;
coe28[IWIDTH-1:0] <= coe29[IWIDTH-1:0] ;
coe27[IWIDTH-1:0] <= coe28[IWIDTH-1:0] ;
coe26[IWIDTH-1:0] <= coe27[IWIDTH-1:0] ;
coe25[IWIDTH-1:0] <= coe26[IWIDTH-1:0] ;
coe24[IWIDTH-1:0] <= coe25[IWIDTH-1:0] ;
coe23[IWIDTH-1:0] <= coe24[IWIDTH-1:0] ;
coe22[IWIDTH-1:0] <= coe23[IWIDTH-1:0] ;
coe21[IWIDTH-1:0] <= coe22[IWIDTH-1:0] ;
coe20[IWIDTH-1:0] <= coe21[IWIDTH-1:0] ;
coe19[IWIDTH-1:0] <= coe20[IWIDTH-1:0] ;
coe18[IWIDTH-1:0] <= coe19[IWIDTH-1:0] ;
coe17[IWIDTH-1:0] <= coe18[IWIDTH-1:0] ;
coe16[IWIDTH-1:0] <= coe17[IWIDTH-1:0] ;
coe15[IWIDTH-1:0] <= coe16[IWIDTH-1:0] ;
coe14[IWIDTH-1:0] <= coe15[IWIDTH-1:0] ;
coe13[IWIDTH-1:0] <= coe14[IWIDTH-1:0] ;
coe12[IWIDTH-1:0] <= coe13[IWIDTH-1:0] ;
coe11[IWIDTH-1:0] <= coe12[IWIDTH-1:0] ;
coe10[IWIDTH-1:0] <= coe11[IWIDTH-1:0] ;
coe9[IWIDTH-1:0] <= coe10[IWIDTH-1:0] ;
coe8[IWIDTH-1:0] <= coe9[IWIDTH-1:0] ;
coe7[IWIDTH-1:0] <= coe8[IWIDTH-1:0] ;
coe6[IWIDTH-1:0] <= coe7[IWIDTH-1:0] ;
coe5[IWIDTH-1:0] <= coe6[IWIDTH-1:0] ;
coe4[IWIDTH-1:0] <= coe5[IWIDTH-1:0] ;
coe3[IWIDTH-1:0] <= coe4[IWIDTH-1:0] ;
coe2[IWIDTH-1:0] <= coe3[IWIDTH-1:0] ;
coe1[IWIDTH-1:0] <= coe2[IWIDTH-1:0] ;
coe0[IWIDTH-1:0] <= coe1[IWIDTH-1:0] ;
end // else: !if(ARST)
//**************************************************************************//
//* Counters *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
accum_cnt[ACCUMCNTWIDTH-1:0] <= {(ACCUMCNTWIDTH){1'b0}} ;
else
accum_cnt[ACCUMCNTWIDTH-1:0] <= (InputValid & ~InputValid0) ?
0:
(accum_cnt == NACCUM+1) ? (NACCUM+1)
: accum_cnt[ACCUMCNTWIDTH-1:0] + 1 ;
always @ (posedge CLK or posedge ARST)
if (ARST)
count1[CNTWIDTH-1:0] <= {(CNTWIDTH){1'b0}} ;
else if (InputValid & ~InputValid1)
count1[CNTWIDTH-1:0] <= (count[CNTWIDTH-1:0] == NTAPS-1) ? 0
: count[CNTWIDTH-1:0] + 1 ;
always @ (posedge CLK or posedge ARST)
if (ARST) accum_cnt1[ACCUMCNTWIDTH-1:0] <= {(ACCUMCNTWIDTH){1'b0}} ;
else accum_cnt1[ACCUMCNTWIDTH-1:0] <= accum_cnt[ACCUMCNTWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST) count[CNTWIDTH-1:0] <= {(CNTWIDTH){1'b0}} ;
else count[CNTWIDTH-1:0] <= count1[CNTWIDTH-1:0] ;
//**************************************************************************//
//* Coefficient Rotation / Selector *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST) mult[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else mult[AWIDTH-1:0] <= coef * SigIn1 ; // Signed multiplication
always @ (posedge CLK or posedge ARST)
if (ARST)
accum1[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 1)
accum1[AWIDTH-1:0] <= (count == 1) ? mult
: mult[AWIDTH-1:0] + accum1[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum2[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 2)
accum2[AWIDTH-1:0] <= (count == 49) ? mult
: mult[AWIDTH-1:0] + accum2[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum3[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 3)
accum3[AWIDTH-1:0] <= (count == 47) ? mult
: mult[AWIDTH-1:0] + accum3[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum4[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 4)
accum4[AWIDTH-1:0] <= (count == 45) ? mult
: mult[AWIDTH-1:0] + accum4[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum5[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 5)
accum5[AWIDTH-1:0] <= (count == 43) ? mult
: mult[AWIDTH-1:0] + accum5[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum6[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 6)
accum6[AWIDTH-1:0] <= (count == 41) ? mult
: mult[AWIDTH-1:0] + accum6[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum7[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 7)
accum7[AWIDTH-1:0] <= (count == 39) ? mult
: mult[AWIDTH-1:0] + accum7[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum8[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 8)
accum8[AWIDTH-1:0] <= (count == 37) ? mult
: mult[AWIDTH-1:0] + accum8[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum9[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] ==9)
accum9[AWIDTH-1:0] <= (count == 35) ? mult
: mult[AWIDTH-1:0] + accum9[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum10[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] ==10)
accum10[AWIDTH-1:0] <= (count == 33) ? mult
: mult[AWIDTH-1:0] + accum10[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum11[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 11)
accum11[AWIDTH-1:0] <= (count == 31) ? mult
: mult[AWIDTH-1:0] + accum11[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum12[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 12)
accum12[AWIDTH-1:0] <= (count == 29) ? mult
: mult[AWIDTH-1:0] + accum12[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum13[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 13)
accum13[AWIDTH-1:0] <= (count == 27) ? mult
: mult[AWIDTH-1:0] + accum13[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum14[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 14)
accum14[AWIDTH-1:0] <= (count == 25) ? mult
: mult[AWIDTH-1:0] + accum14[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum15[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 15)
accum15[AWIDTH-1:0] <= (count == 23) ? mult
: mult[AWIDTH-1:0] + accum15[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum16[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 16)
accum16[AWIDTH-1:0] <= (count == 21) ? mult
: mult[AWIDTH-1:0] + accum16[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum17[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 17)
accum17[AWIDTH-1:0] <= (count == 19) ? mult
: mult[AWIDTH-1:0] + accum17[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum18[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] ==18)
accum18[AWIDTH-1:0] <= (count == 17) ? mult
: mult[AWIDTH-1:0] + accum18[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum19[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 19)
accum19[AWIDTH-1:0] <= (count == 15) ? mult
: mult[AWIDTH-1:0] + accum19[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum20[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 20)
accum20[AWIDTH-1:0] <= (count == 13) ? mult
: mult[AWIDTH-1:0] + accum20[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum21[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 21)
accum21[AWIDTH-1:0] <= (count == 11) ? mult
: mult[AWIDTH-1:0] + accum21[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum22[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 22)
accum22[AWIDTH-1:0] <= (count == 9) ? mult
: mult[AWIDTH-1:0] + accum22[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum23[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 23)
accum23[AWIDTH-1:0] <= (count == 7) ? mult
: mult[AWIDTH-1:0] + accum23[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum24[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 24)
accum24[AWIDTH-1:0] <= (count == 5) ? mult
: mult[AWIDTH-1:0] + accum24[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum25[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 0)
accum25[AWIDTH-1:0] <= (count == 4) ? mult
: mult[AWIDTH-1:0] + accum25[AWIDTH-1:0] ;
//**************************************************************************//
//* Output Buffers *//
//**************************************************************************//
assign valid1 = (count[CNTWIDTH-1:0] == 1) & (accum_cnt1 == 1) ;
assign valid2 = (count[CNTWIDTH-1:0] == 49) & (accum_cnt1 == 1) ;
assign valid3 = (count[CNTWIDTH-1:0] == 47) & (accum_cnt1 == 1) ;
assign valid4 = (count[CNTWIDTH-1:0] == 45) & (accum_cnt1 == 1) ;
assign valid5 = (count[CNTWIDTH-1:0] == 43) & (accum_cnt1 == 1) ;
assign valid6 = (count[CNTWIDTH-1:0] == 41) & (accum_cnt1 == 1) ;
assign valid7 = (count[CNTWIDTH-1:0] == 39) & (accum_cnt1 == 1) ;
assign valid8 = (count[CNTWIDTH-1:0] == 37) & (accum_cnt1 == 1) ;
assign valid9 = (count[CNTWIDTH-1:0] == 35) & (accum_cnt1 == 1) ;
assign valid10 = (count[CNTWIDTH-1:0] == 33) & (accum_cnt1 == 1) ;
assign valid11 = (count[CNTWIDTH-1:0] == 31) & (accum_cnt1 == 1) ;
assign valid12 = (count[CNTWIDTH-1:0] == 29) & (accum_cnt1 == 1) ;
assign valid13 = (count[CNTWIDTH-1:0] == 27) & (accum_cnt1 == 1) ;
assign valid14 = (count[CNTWIDTH-1:0] == 25) & (accum_cnt1 == 1) ;
assign valid15 = (count[CNTWIDTH-1:0] == 23) & (accum_cnt1 == 1) ;
assign valid16 = (count[CNTWIDTH-1:0] == 21) & (accum_cnt1 == 1) ;
assign valid17 = (count[CNTWIDTH-1:0] == 19) & (accum_cnt1 == 1) ;
assign valid18 = (count[CNTWIDTH-1:0] == 17) & (accum_cnt1 == 1) ;
assign valid19 = (count[CNTWIDTH-1:0] == 15) & (accum_cnt1 == 1) ;
assign valid20 = (count[CNTWIDTH-1:0] == 13) & (accum_cnt1 == 1) ;
assign valid21 = (count[CNTWIDTH-1:0] == 11) & (accum_cnt1 == 1) ;
assign valid22 = (count[CNTWIDTH-1:0] == 9) & (accum_cnt1 == 1) ;
assign valid23 = (count[CNTWIDTH-1:0] == 7) & (accum_cnt1 == 1) ;
assign valid24 = (count[CNTWIDTH-1:0] == 5) & (accum_cnt1 == 1) ;
assign valid25 = (count[CNTWIDTH-1:0] == 3) & (accum_cnt1 == 1) ;
assign valid = valid1 | valid2 | valid3 | valid4 | valid5 | valid6 |
valid7 | valid8 | valid9 | valid10 | valid11 | valid12 |
valid13 | valid14 | valid15 | valid16 | valid17 | valid18 |
valid19 | valid20 | valid21 | valid22 | valid23 | valid24 |
valid25;
always @ (posedge CLK or posedge ARST)
if (ARST)
SigOut[OWIDTH-1:0] <= {(OWIDTH){1'b0}} ;
else if (valid)
SigOut[OWIDTH-1:0] <= (accum1[AWIDTH-1:0] & {(AWIDTH){ valid1 }}) |
(accum2[AWIDTH-1:0] & {(AWIDTH){ valid2 }}) |
(accum3[AWIDTH-1:0] & {(AWIDTH){ valid3 }}) |
(accum4[AWIDTH-1:0] & {(AWIDTH){ valid4 }}) |
(accum5[AWIDTH-1:0] & {(AWIDTH){ valid5 }}) |
(accum6[AWIDTH-1:0] & {(AWIDTH){ valid6 }}) |
(accum7[AWIDTH-1:0] & {(AWIDTH){ valid7 }}) |
(accum8[AWIDTH-1:0] & {(AWIDTH){ valid8 }}) |
(accum9[AWIDTH-1:0] & {(AWIDTH){ valid9 }}) |
(accum10[AWIDTH-1:0] & {(AWIDTH){ valid10 }}) |
(accum11[AWIDTH-1:0] & {(AWIDTH){ valid11 }}) |
(accum12[AWIDTH-1:0] & {(AWIDTH){ valid12 }}) |
(accum13[AWIDTH-1:0] & {(AWIDTH){ valid13 }}) |
(accum14[AWIDTH-1:0] & {(AWIDTH){ valid14 }}) |
(accum15[AWIDTH-1:0] & {(AWIDTH){ valid15 }}) |
(accum16[AWIDTH-1:0] & {(AWIDTH){ valid16 }}) |
(accum17[AWIDTH-1:0] & {(AWIDTH){ valid17 }}) |
(accum18[AWIDTH-1:0] & {(AWIDTH){ valid18 }}) |
(accum19[AWIDTH-1:0] & {(AWIDTH){ valid19 }}) |
(accum20[AWIDTH-1:0] & {(AWIDTH){ valid20 }}) |
(accum21[AWIDTH-1:0] & {(AWIDTH){ valid21 }}) |
(accum22[AWIDTH-1:0] & {(AWIDTH){ valid22 }}) |
(accum23[AWIDTH-1:0] & {(AWIDTH){ valid23 }}) |
(accum24[AWIDTH-1:0] & {(AWIDTH){ valid24 }}) |
(accum25[AWIDTH-1:0] & {(AWIDTH){ valid25 }}) ;
always @ (posedge CLK or posedge ARST)
if (ARST) DataValid <= 1'b0 ;
else DataValid <= valid;
endmodule //firdecim_m2_n50// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : firdecim_m5_n15.v ** //
// ** Project : ISAAC Newton ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 13, 2008 ** //
// ** Description : Polyphase Decimation Filter ** //
// ** M = 5, L = 15 ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : firdecim_m5_n15.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 13, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module firdecim_m5_n15
(// Outputs
SigOut, DataValid,
// Inputs
CLK, ARST, InputValid, SigIn, Sync
);
//**************************************************************************//
//* Declarations *//
//**************************************************************************//
// DATA TYPE - PARAMETERS
parameter e14 = 16'sb0000_0000_0001_1111;
parameter e13 = 16'sb0000_0000_1000_1101;
parameter e12 = 16'sb0000_0001_1000_0010;
parameter e11 = 16'sb0000_0011_0001_1110;
parameter e10 = 16'sb0000_0101_0011_1111;
parameter e9 = 16'sb0000_0111_0111_1000;
parameter e8 = 16'sb0000_1001_0010_1011;
parameter e7 = 16'sb0000_1001_1100_1111;
parameter e6 = 16'sb0000_1001_0010_1011;
parameter e5 = 16'sb0000_0111_0111_1000;
parameter e4 = 16'sb0000_0101_0011_1111;
parameter e3 = 16'sb0000_0011_0001_1110;
parameter e2 = 16'sb0000_0001_1000_0010;
parameter e1 = 16'sb0000_0000_1000_1101;
parameter e0 = 16'sb0000_0000_0001_1111;
parameter OWIDTH = 32 ; // output bit width
parameter IWIDTH = 16 ; // input bit width
parameter NTAPS = 15 ; // number of taps in the filter
parameter CNTWIDTH = 4 ; // counter bit width
// DATA TYPE - INPUTS AND OUTPUTS
output reg signed [OWIDTH-1:0] SigOut ;
output reg DataValid ;
input CLK ; // 60MHz Clock
input ARST ;
input InputValid ;
input signed [IWIDTH-1:0] SigIn ;
input Sync ;
// DATA TYPE - REGISTERS
reg signed [IWIDTH-1:0] coe14 ;
reg signed [IWIDTH-1:0] coe13 ;
reg signed [IWIDTH-1:0] coe12 ;
reg signed [IWIDTH-1:0] coe11 ;
reg signed [IWIDTH-1:0] coe10 ;
reg signed [IWIDTH-1:0] coe9 ;
reg signed [IWIDTH-1:0] coe8 ;
reg signed [IWIDTH-1:0] coe7 ;
reg signed [IWIDTH-1:0] coe6 ;
reg signed [IWIDTH-1:0] coe5 ;
reg signed [IWIDTH-1:0] coe4 ;
reg signed [IWIDTH-1:0] coe3 ;
reg signed [IWIDTH-1:0] coe2 ;
reg signed [IWIDTH-1:0] coe1 ;
reg signed [IWIDTH-1:0] coe0 ;
reg [CNTWIDTH-1:0] count ;
// DATA TYPE - WIRES
wire signed [OWIDTH-1:0] SigOut1 ;
wire signed [OWIDTH-1:0] SigOut2 ;
wire signed [OWIDTH-1:0] SigOut3 ;
wire initialize1 ;
wire initialize2 ;
wire initialize3 ;
wire DataValid1 ;
wire DataValid2 ;
wire DataValid3 ;
//**************************************************************************//
//* Coefficient Rotation *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
coe14[IWIDTH-1:0] <= e14 ;
coe13[IWIDTH-1:0] <= e13 ;
coe12[IWIDTH-1:0] <= e12 ;
coe11[IWIDTH-1:0] <= e11 ;
coe10[IWIDTH-1:0] <= e10 ;
coe9[IWIDTH-1:0] <= e9 ;
coe8[IWIDTH-1:0] <= e8 ;
coe7[IWIDTH-1:0] <= e7 ;
coe6[IWIDTH-1:0] <= e6 ;
coe5[IWIDTH-1:0] <= e5 ;
coe4[IWIDTH-1:0] <= e4 ;
coe3[IWIDTH-1:0] <= e3 ;
coe2[IWIDTH-1:0] <= e2 ;
coe1[IWIDTH-1:0] <= e1 ;
coe0[IWIDTH-1:0] <= e0 ;
end // if (ARST)
else if (Sync)
begin
coe14[IWIDTH-1:0] <= e14 ;
coe13[IWIDTH-1:0] <= e13 ;
coe12[IWIDTH-1:0] <= e12 ;
coe11[IWIDTH-1:0] <= e11 ;
coe10[IWIDTH-1:0] <= e10 ;
coe9[IWIDTH-1:0] <= e9 ;
coe8[IWIDTH-1:0] <= e8 ;
coe7[IWIDTH-1:0] <= e7 ;
coe6[IWIDTH-1:0] <= e6 ;
coe5[IWIDTH-1:0] <= e5 ;
coe4[IWIDTH-1:0] <= e4 ;
coe3[IWIDTH-1:0] <= e3 ;
coe2[IWIDTH-1:0] <= e2 ;
coe1[IWIDTH-1:0] <= e1 ;
coe0[IWIDTH-1:0] <= e0 ;
end
else if (InputValid)
begin
coe14[IWIDTH-1:0] <= coe0[IWIDTH-1:0] ;
coe13[IWIDTH-1:0] <= coe14[IWIDTH-1:0] ;
coe12[IWIDTH-1:0] <= coe13[IWIDTH-1:0] ;
coe11[IWIDTH-1:0] <= coe12[IWIDTH-1:0] ;
coe10[IWIDTH-1:0] <= coe11[IWIDTH-1:0] ;
coe9[IWIDTH-1:0] <= coe10[IWIDTH-1:0] ;
coe8[IWIDTH-1:0] <= coe9[IWIDTH-1:0] ;
coe7[IWIDTH-1:0] <= coe8[IWIDTH-1:0] ;
coe6[IWIDTH-1:0] <= coe7[IWIDTH-1:0] ;
coe5[IWIDTH-1:0] <= coe6[IWIDTH-1:0] ;
coe4[IWIDTH-1:0] <= coe5[IWIDTH-1:0] ;
coe3[IWIDTH-1:0] <= coe4[IWIDTH-1:0] ;
coe2[IWIDTH-1:0] <= coe3[IWIDTH-1:0] ;
coe1[IWIDTH-1:0] <= coe2[IWIDTH-1:0] ;
coe0[IWIDTH-1:0] <= coe1[IWIDTH-1:0] ;
end
//**************************************************************************//
//* Counter *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
count[CNTWIDTH-1:0] <= {(CNTWIDTH){1'b0}} ;
else if (InputValid)
count[CNTWIDTH-1:0] <= (count[CNTWIDTH-1:0] == (NTAPS-1)) ? 0 :
count[CNTWIDTH-1:0] + 1 ;
//**************************************************************************//
//* Reset each MAC *//
//**************************************************************************//
assign initialize1 = (count == 0) ;
assign initialize2 = (count == 5) ;
assign initialize3 = (count == 10) ;
//**************************************************************************//
//* Output Buffers *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
SigOut[OWIDTH-1:0] <= {(OWIDTH){1'b0}};
else if (DataValid1 | DataValid2 | DataValid3)
SigOut[OWIDTH-1:0] <= {(OWIDTH){DataValid1}} & SigOut1 |
{(OWIDTH){DataValid2}} & SigOut2 |
{(OWIDTH){DataValid3}} & SigOut3 ;
always @ (posedge CLK or posedge ARST)
if (ARST) DataValid <= 1'b0 ;
else DataValid <= (DataValid1 | DataValid2 | DataValid3) ;
//**************************************************************************//
//* Submodules *//
//**************************************************************************//
//First MAC
MAC1 MAC1_a
(// Inputs
.CLK (CLK), // CLK
.ARST (ARST), // ARST
.filterCoef (coe0), // Filter Coeficients
.InData (SigIn), // Input Data
.input_Valid (InputValid), // Input Valid
.initialize (initialize1), // Initialize
//Outputs
.OutData (SigOut1), // Output Data
.output_Valid (DataValid1) // Output Valid
);
// Second MAC
MAC1 MAC1_b
(// Inputs
.CLK (CLK), // CLK
.ARST (ARST), // ARST
.filterCoef (coe10), // Filter Coeficients
.InData (SigIn), // Input Data
.input_Valid (InputValid), // Input Valid
.initialize (initialize2), // Initialize
//Outputs
.OutData (SigOut2), // Output Data
.output_Valid (DataValid2) // Output Valid
);
// Third MAC
MAC1 MAC1_c
(// Inputs
.CLK (CLK), // CLK
.ARST (ARST), // ARST
.filterCoef (coe5), // Filter Coeficients
.InData (SigIn), // Input Data
.input_Valid (InputValid), // Input Valid
.initialize (initialize3), // Initialize
//Outputs
.OutData (SigOut3), // Output Data
.output_Valid (DataValid3) // Output Valid
);
endmodule // firdecim_m5_n15
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : firdecim_m5_n20.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 13, 2008 ** //
// ** Description : Polyphase Decimation Filter ** //
// ** M = 5, L = 20 ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : firdecim_m5_n20.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 13, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module firdecim_m5_n20
(// Input
CLK,
ARST,
Sync,
InputValid,
SigIn,
// Ouput
DataValid,
SigOut
);
//****************************************************************************//
//* Declarations *//
//****************************************************************************//
// DATA TYPE - PARAMETERS
parameter e19 = 16'sb1111_1111_1011_1000;
parameter e18 = 16'sb1111_1111_1000_0110;
parameter e17 = 16'sb1111_1111_0110_1110;
parameter e16 = 16'sb1111_1111_1011_1110;
parameter e15 = 16'sb0000_0000_1011_0011;
parameter e14 = 16'sb0000_0010_0110_1101;
parameter e13 = 16'sb0000_0100_1100_0101;
parameter e12 = 16'sb0000_0111_0101_0101;
parameter e11 = 16'sb0000_1001_1000_0111;
parameter e10 = 16'sb0000_1010_1100_1101;
parameter e9 = 16'sb0000_1010_1100_1101;
parameter e8 = 16'sb0000_1001_1000_0111;
parameter e7 = 16'sb0000_0111_0101_0101;
parameter e6 = 16'sb0000_0100_1100_0101;
parameter e5 = 16'sb0000_0010_0110_1101;
parameter e4 = 16'sb0000_0000_1011_0011;
parameter e3 = 16'sb1111_1111_1011_1110;
parameter e2 = 16'sb1111_1111_0110_1110;
parameter e1 = 16'sb1111_1111_1000_0110;
parameter e0 = 16'sb1111_1111_1011_1000;
parameter OWIDTH = 32 ; // output bit width
parameter IWIDTH = 16 ; // input bit width
parameter AWIDTH = 32 ; // internal bit width
parameter NTAPS = 20 ; // number of filter taps
parameter ACCUMCNTWIDTH = 3 ; // accumulator count bit width
parameter CNTWIDTH = 5 ; // counter bit width
parameter NACCUM = 4 ; // numbers of accumulators
// DATA TYPE - INPUTS AND OUTPUTS
output reg signed [OWIDTH-1:0] SigOut ;
output reg DataValid ;
input CLK ; // 60MHz Clock
input ARST ;
input InputValid ;
input Sync ;
input signed [IWIDTH-1:0] SigIn ;
// DATA TYPE - REGISTERS
reg signed [IWIDTH-1:0] coe19 ;
reg signed [IWIDTH-1:0] coe18 ;
reg signed [IWIDTH-1:0] coe17 ;
reg signed [IWIDTH-1:0] coe16 ;
reg signed [IWIDTH-1:0] coe15 ;
reg signed [IWIDTH-1:0] coe14 ;
reg signed [IWIDTH-1:0] coe13 ;
reg signed [IWIDTH-1:0] coe12 ;
reg signed [IWIDTH-1:0] coe11 ;
reg signed [IWIDTH-1:0] coe10 ;
reg signed [IWIDTH-1:0] coe9 ;
reg signed [IWIDTH-1:0] coe8 ;
reg signed [IWIDTH-1:0] coe7 ;
reg signed [IWIDTH-1:0] coe6 ;
reg signed [IWIDTH-1:0] coe5 ;
reg signed [IWIDTH-1:0] coe4 ;
reg signed [IWIDTH-1:0] coe3 ;
reg signed [IWIDTH-1:0] coe2 ;
reg signed [IWIDTH-1:0] coe1 ;
reg signed [IWIDTH-1:0] coe0 ;
reg [CNTWIDTH-1:0] count ;
reg [ACCUMCNTWIDTH-1:0] accum_cnt ; //Counter to keep track of which
//accumulator is being accessed.
reg signed [IWIDTH-1:0] SigIn1 ;
reg InputValid0 ;
reg signed [AWIDTH-1:0] mult ;
reg signed [AWIDTH-1:0] accum1 ; //First accumulator
reg signed [AWIDTH-1:0] accum2 ; //Second accumulator
reg signed [AWIDTH-1:0] accum3 ; //Third accumulator
reg signed [AWIDTH-1:0] accum4 ; //Fourth accumulator
// DATA TYPE - NETS
wire signed [IWIDTH-1:0] coef ; //Coefficient to be used in the
//multiplier.
wire valid ;
wire valid1 ;
wire valid2 ;
wire valid3 ;
wire valid4 ;
//****************************************************************************//
//* Input Buffers *//
//****************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST) InputValid0 <= 1'b0 ;
else InputValid0 <= InputValid ;
always @ (posedge CLK or posedge ARST)
if (ARST) SigIn1[IWIDTH-1:0] <= {(IWIDTH){1'b0}} ;
else SigIn1[IWIDTH-1:0] <= SigIn[IWIDTH-1:0];
//****************************************************************************//
//* Coefficient Rotation / Selector *//
//****************************************************************************//
assign coef[IWIDTH-1:0] = (accum_cnt[ACCUMCNTWIDTH-1:0] == 0) ? coe0[IWIDTH-1:0] :
((accum_cnt[ACCUMCNTWIDTH-1:0] == 1) ? coe5[IWIDTH-1:0] :
((accum_cnt[ACCUMCNTWIDTH-1:0] == 2) ? coe10[IWIDTH-1:0]
: coe15[IWIDTH-1:0])) ;
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
coe19[IWIDTH-1:0] <= e18 ;
coe18[IWIDTH-1:0] <= e17 ;
coe17[IWIDTH-1:0] <= e16 ;
coe16[IWIDTH-1:0] <= e15 ;
coe15[IWIDTH-1:0] <= e14 ;
coe14[IWIDTH-1:0] <= e13 ;
coe13[IWIDTH-1:0] <= e12 ;
coe12[IWIDTH-1:0] <= e11 ;
coe11[IWIDTH-1:0] <= e10 ;
coe10[IWIDTH-1:0] <= e9 ;
coe9[IWIDTH-1:0] <= e8 ;
coe8[IWIDTH-1:0] <= e7 ;
coe7[IWIDTH-1:0] <= e6 ;
coe6[IWIDTH-1:0] <= e5 ;
coe5[IWIDTH-1:0] <= e4 ;
coe4[IWIDTH-1:0] <= e3 ;
coe3[IWIDTH-1:0] <= e2 ;
coe2[IWIDTH-1:0] <= e1 ;
coe1[IWIDTH-1:0] <= e0 ;
coe0[IWIDTH-1:0] <= e19 ;
end // if (ARST)
else if (Sync)
begin
coe19[IWIDTH-1:0] <= e18 ;
coe18[IWIDTH-1:0] <= e17 ;
coe17[IWIDTH-1:0] <= e16 ;
coe16[IWIDTH-1:0] <= e15 ;
coe15[IWIDTH-1:0] <= e14 ;
coe14[IWIDTH-1:0] <= e13 ;
coe13[IWIDTH-1:0] <= e12 ;
coe12[IWIDTH-1:0] <= e11 ;
coe11[IWIDTH-1:0] <= e10 ;
coe10[IWIDTH-1:0] <= e9 ;
coe9[IWIDTH-1:0] <= e8 ;
coe8[IWIDTH-1:0] <= e7 ;
coe7[IWIDTH-1:0] <= e6 ;
coe6[IWIDTH-1:0] <= e5 ;
coe5[IWIDTH-1:0] <= e4 ;
coe4[IWIDTH-1:0] <= e3 ;
coe3[IWIDTH-1:0] <= e2 ;
coe2[IWIDTH-1:0] <= e1 ;
coe1[IWIDTH-1:0] <= e0 ;
coe0[IWIDTH-1:0] <= e19 ;
end
else if (InputValid)
begin
coe19[IWIDTH-1:0] <= coe0[IWIDTH-1:0] ;
coe18[IWIDTH-1:0] <= coe19[IWIDTH-1:0] ;
coe17[IWIDTH-1:0] <= coe18[IWIDTH-1:0] ;
coe16[IWIDTH-1:0] <= coe17[IWIDTH-1:0] ;
coe15[IWIDTH-1:0] <= coe16[IWIDTH-1:0] ;
coe14[IWIDTH-1:0] <= coe15[IWIDTH-1:0] ;
coe13[IWIDTH-1:0] <= coe14[IWIDTH-1:0] ;
coe12[IWIDTH-1:0] <= coe13[IWIDTH-1:0] ;
coe11[IWIDTH-1:0] <= coe12[IWIDTH-1:0] ;
coe10[IWIDTH-1:0] <= coe11[IWIDTH-1:0] ;
coe9[IWIDTH-1:0] <= coe10[IWIDTH-1:0] ;
coe8[IWIDTH-1:0] <= coe9[IWIDTH-1:0] ;
coe7[IWIDTH-1:0] <= coe8[IWIDTH-1:0] ;
coe6[IWIDTH-1:0] <= coe7[IWIDTH-1:0] ;
coe5[IWIDTH-1:0] <= coe6[IWIDTH-1:0] ;
coe4[IWIDTH-1:0] <= coe5[IWIDTH-1:0] ;
coe3[IWIDTH-1:0] <= coe4[IWIDTH-1:0] ;
coe2[IWIDTH-1:0] <= coe3[IWIDTH-1:0] ;
coe1[IWIDTH-1:0] <= coe2[IWIDTH-1:0] ;
coe0[IWIDTH-1:0] <= coe1[IWIDTH-1:0] ;
end // else: !if(ARST)
//****************************************************************************//
//* Counters *//
//****************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
accum_cnt[ACCUMCNTWIDTH-1:0] <= {(ACCUMCNTWIDTH){1'b0}} ;
else
accum_cnt[ACCUMCNTWIDTH-1:0] <= (InputValid & ~InputValid0) ?
0:
(accum_cnt == NACCUM+1) ? (NACCUM+1)
: accum_cnt[ACCUMCNTWIDTH-1:0] + 1 ;
always @ (posedge CLK or posedge ARST)
if (ARST)
count[CNTWIDTH-1:0] <= {(CNTWIDTH){1'b0}} ;
else if (InputValid & ~InputValid0)
count[CNTWIDTH-1:0] <= (count[CNTWIDTH-1:0] == NTAPS-1) ? 0
: count[CNTWIDTH-1:0] + 1 ;
//****************************************************************************//
//* Multiplier - Accumulator *//
//****************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST) mult[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else mult[AWIDTH-1:0] <= coef* SigIn1 ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum1[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt[ACCUMCNTWIDTH-1:0] == 1)
accum1[AWIDTH-1:0] <= (count == 1) ? mult
: mult[AWIDTH-1:0] + accum1[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum2[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt[ACCUMCNTWIDTH-1:0] == 2)
accum2[AWIDTH-1:0] <= (count == 16) ? mult
: mult[AWIDTH-1:0] + accum2[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum3[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt[ACCUMCNTWIDTH-1:0] == 3)
accum3[AWIDTH-1:0] <= (count == 11) ? mult
: mult[AWIDTH-1:0] + accum3[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum4[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt[ACCUMCNTWIDTH-1:0] == 4)
accum4[AWIDTH-1:0] <= (count == 6) ? mult
: mult[AWIDTH-1:0] + accum4[AWIDTH-1:0] ;
//****************************************************************************//
//* Output Buffers *//
//****************************************************************************//
assign valid1 = (count[CNTWIDTH-1:0] == 1) & (accum_cnt == 0) ;
assign valid2 = (count[CNTWIDTH-1:0] == 16) & (accum_cnt == 0) ;
assign valid3 = (count[CNTWIDTH-1:0] == 11) & (accum_cnt == 0) ;
assign valid4 = (count[CNTWIDTH-1:0] == 6) & (accum_cnt == 0) ;
assign valid = valid1 | valid2 | valid3 | valid4 ;
always @ (posedge CLK or posedge ARST)
if (ARST)
SigOut[OWIDTH-1:0] <= {(OWIDTH){1'b0}} ;
else if (valid)
SigOut[OWIDTH-1:0] <= (accum1[AWIDTH-1:0] & {(AWIDTH){ valid1 }}) |
(accum2[AWIDTH-1:0] & {(AWIDTH){ valid2 }}) |
(accum3[AWIDTH-1:0] & {(AWIDTH){ valid3 }}) |
(accum4[AWIDTH-1:0] & {(AWIDTH){ valid4 }}) ;
always @ (posedge CLK or posedge ARST)
if (ARST) DataValid <= 1'b0 ;
else DataValid <= valid;
endmodule // firdecim_m5_n20
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : iReg.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 5, 2008 ** //
// ** Description : Internal Register for Newton core ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : iReg.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 5, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ** File : iReg.v ** //
// ** Revision : 2 ** //
// ** Author : kaylangu ** //
// ** Date : August 19, 2008 ** //
// ** FileName : ** //
// ** Notes : 1. Register 0 functional modification ** //
// ** 2. Bit ReOrdering function change to for loop ** //
// ** 3. Register 1 and Register 2 counter modify to use ** //
// ** Write Enable bits ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module iReg
(// Outputs
iReg_intr, iReg2IP_RdAck, IP2Bus_WrAck, CPTR, IP2Bus_Data, SYNC,
// Inputs
Bus2IP_Clk, Bus2IP_Reset, Bus2IP_RdCE, Bus2IP_WrCE, Bus2IP_Data,
WFIFO_WE, FIR_WE
);
//**************************************************************************//
//* Declarations *//
//**************************************************************************//
// DATA TYPE - PARAMETERS
parameter r0setclr = 31; // Register 0 set/clr bit
parameter initWM = 16'hFFFF;
parameter ModuleVersion = 2;
// DATA TYPE - INPUTS AND OUTPUTS
input Bus2IP_Clk; // 100MHz Clock from BUS
input Bus2IP_Reset; // Asynchronous Reset (positive logic)
input [0:3] Bus2IP_RdCE; // Register Read Enable (from Bus)
input [0:3] Bus2IP_WrCE; // Register Write Enable (from Bus)
input [0:31] Bus2IP_Data; // Data from Bus to IP
input WFIFO_WE; // Write Enable Signal from FIFO
input FIR_WE; // Write Signal from QM_FIR
output reg iReg_intr; // Interrupt Signal
output iReg2IP_RdAck;// Read Acknowledgement
output IP2Bus_WrAck; // Write Acknowledgement
output reg [10:0] CPTR; // Data from IP to bus
output [0:31] IP2Bus_Data; // Pointer to BRAM
output reg SYNC; // Resets QM counter to zero and Reset FIR coef registers
// to initial values
// DATA TYPE - INTERNAL REG
reg OVFL_MSK; // Overflow Mask
reg WMI_MSK; // WMI Mask
reg OVFL; // Overflow for CPTR
reg WMI; // Watermark Interrupt
reg [9:0] SPTR; // Load to CPTR when SYNC is asserted
reg [31:0] ICNT; // Counts the numbers of inputs
reg [15:0] OCNT_WM; // Output counter watermark
reg [15:0] OCNT_int; // Counts the numbers of outputs
reg [7:0] VERSION; // Current Module version number
reg [31:0] IP2Bus_Data_int; // Internal IP2Bus_Data
reg FIR_WE_dly1;
// DATA TYPE - INTERNAL WIRES
wire [31:0] ESCR;
wire [31:0] WPTR;
wire [31:0] OCNT;
wire [31:0] Bus2IP_Data_int; // Internal Bus2IP_Data_int
wire setclr;
//**************************************************************************//
//* Reversing Bit ReOrdering *//
//**************************************************************************//
assign Bus2IP_Data_int[31:0] = fnBitReordering031to310(Bus2IP_Data[0:31]);
assign IP2Bus_Data[0:31] = fnBitReordering310to031(IP2Bus_Data_int[31:0]);
//**************************************************************************//
//* REG 0 *//
//**************************************************************************//
assign setclr = Bus2IP_WrCE[0] & Bus2IP_Data_int[r0setclr];
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
OVFL_MSK <= 1'b0;
else if (Bus2IP_WrCE[0] & Bus2IP_Data_int[18])
OVFL_MSK <= Bus2IP_Data_int[r0setclr];
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
WMI_MSK <= 1'b0;
else if (Bus2IP_WrCE[0] & Bus2IP_Data_int[17])
WMI_MSK <= Bus2IP_Data_int[r0setclr];
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
OVFL <= 1'b0;
else if (CPTR[10] == 1'b1) // BRAM pointer overflows
OVFL <= 1'b1;
else if (Bus2IP_WrCE[0] & Bus2IP_Data_int[2])
OVFL <= Bus2IP_Data_int[r0setclr];
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
FIR_WE_dly1 <= 1'b0;
else
FIR_WE_dly1 <= FIR_WE;
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
WMI <= 1'b0;
else if (FIR_WE_dly1 & (OCNT_int[15:0] == OCNT_WM[15:0])) // Output counter overflows
WMI <= 1'b1;
else if (Bus2IP_WrCE[0] & Bus2IP_Data_int[1])
WMI <= Bus2IP_Data_int[r0setclr];
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
SYNC <= 1'b0;
else
SYNC <= setclr & Bus2IP_Data_int[0];
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0 )
VERSION[7:0] <= 8'd0;
else
VERSION[7:0] <= ModuleVersion;
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
iReg_intr <= 1'b0;
else
iReg_intr <= (WMI & ~WMI_MSK) | (OVFL & ~OVFL_MSK);
// Read out
assign ESCR[31:0] = {setclr, 12'd0, OVFL_MSK, WMI_MSK, 1'b0,
VERSION[7:0], 5'd0, OVFL, WMI, 1'b0};
//**************************************************************************//
//* REG 1 *//
//**************************************************************************//
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
SPTR[9:0] <= 10'd0;
else if (Bus2IP_WrCE[1])
SPTR[9:0] <= Bus2IP_Data_int[25:16];
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
CPTR[10:0] <= 11'd0;
else if (SYNC == 1'b1)
begin
CPTR[9:0] <= SPTR[9:0];
CPTR[10] <= 1'b0;
end
else if (OVFL == 1'b1)
CPTR[10] <= 1'b0;
else
CPTR[10:0] <= CPTR[10:0] + FIR_WE; //Pointer to BRAM address
// Readout
assign WPTR[31:0] = {6'd0, SPTR[9:0], 6'd0, CPTR[9:0]};
//**************************************************************************//
//* REG 2 *//
//**************************************************************************//
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
ICNT[31:0] <= 32'd0;
else if (Bus2IP_WrCE[2])
ICNT[31:0] <= Bus2IP_Data_int[31:0];
else
ICNT[31:0] <= ICNT[31:0] + WFIFO_WE;
//**************************************************************************//
//* REG 3 *//
//**************************************************************************//
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
OCNT_WM[15:0] <= initWM;
else if (Bus2IP_WrCE[3])
OCNT_WM[15:0] <= Bus2IP_Data_int[31:16];
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
OCNT_int[15:0] <= 16'd0;
else if (Bus2IP_WrCE[3])
OCNT_int[15:0] <= Bus2IP_Data_int[15:0];
else
OCNT_int[15:0] <= OCNT_int[15:0] + FIR_WE;
// Read out
assign OCNT[31:0] = {OCNT_WM[15:0], OCNT_int[15:0]};
//**************************************************************************//
//* Read Out *//
//**************************************************************************//
always @ (/*AS*/Bus2IP_RdCE or ESCR or ICNT or OCNT or WPTR)
begin
IP2Bus_Data_int[31:0] = 32'b0;
case (1'b1)
Bus2IP_RdCE[0] : IP2Bus_Data_int[31:0] = ESCR[31:0];
Bus2IP_RdCE[1] : IP2Bus_Data_int[31:0] = WPTR[31:0];
Bus2IP_RdCE[2] : IP2Bus_Data_int[31:0] = ICNT[31:0];
Bus2IP_RdCE[3] : IP2Bus_Data_int[31:0] = OCNT[31:0];
endcase // case (1'b1)
end
assign iReg2IP_RdAck = |Bus2IP_RdCE[0:3];
assign IP2Bus_WrAck = |Bus2IP_WrCE[0:3];
//**************************************************************************//
//* Bit ReOrdering Functions *//
//**************************************************************************//
function [31:0] fnBitReordering031to310; // From [0:31] to [31:0]
input [0:31] Data1;
integer i;
begin
for (i=0;i<32;i=i+1)
fnBitReordering031to310[i] = Data1[31-i];
end
endfunction // fnBitReordering031to310
function [0:31] fnBitReordering310to031; // From [31:0] to [0:31]
input [31:0] Data1;
integer i;
begin
for (i=0;i<32;i=i+1)
fnBitReordering310to031[i] = Data1[31-i];
end
endfunction // fnBitReordering310to031
endmodule // iReg
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: test_stub_scan.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// ____________________________________________________________________________
//
// test_stub_bist - Test Stub with Scan Support
// ____________________________________________________________________________
//
// Description: DBB interface for test signal generation
// ____________________________________________________________________________
module test_stub_scan (/*AUTOARG*/
// Outputs
mux_drive_disable, mem_write_disable, sehold, se, testmode_l,
mem_bypass, so_0, so_1, so_2,
// Inputs
ctu_tst_pre_grst_l, arst_l, global_shift_enable,
ctu_tst_scan_disable, ctu_tst_scanmode, ctu_tst_macrotest,
ctu_tst_short_chain, long_chain_so_0, short_chain_so_0,
long_chain_so_1, short_chain_so_1, long_chain_so_2, short_chain_so_2
);
input ctu_tst_pre_grst_l;
input arst_l; // no longer used
input global_shift_enable;
input ctu_tst_scan_disable; // redefined as pin_based_scan
input ctu_tst_scanmode;
input ctu_tst_macrotest;
input ctu_tst_short_chain;
input long_chain_so_0;
input short_chain_so_0;
input long_chain_so_1;
input short_chain_so_1;
input long_chain_so_2;
input short_chain_so_2;
output mux_drive_disable;
output mem_write_disable;
output sehold;
output se;
output testmode_l;
output mem_bypass;
output so_0;
output so_1;
output so_2;
wire pin_based_scan;
wire short_chain_en;
wire short_chain_select;
// INTERNAL CLUSTER CONNECTIONS
//
// Scan Chain Hookup
// =================
//
// Scan chains have two configurations: long and short.
// The short chain is typically the first tenth of the
// long chain. The short chain should contain memory
// collar flops for deep arrays. The CTU determines
// which configuration is selected. Up to three chains
// are supported.
//
// The scanout connections from the long and short
// chains connect to the following inputs:
//
// long_chain_so_0, short_chain_so_0 (mandatory)
// long_chain_so_1, short_chain_so_1 (optional)
// long_chain_so_2, short_chain_so_2 (optional)
//
// The test stub outputs should connect directly to the
// scanout port(s) of the cluster:
//
// so_0 (mandatory), so_1 (optional), so_2 (optional)
//
//
// Static Output Signals
// =====================
//
// testmode_l
//
// Local testmode control for overriding gated
// clocks, asynchronous resets, etc. Asserted
// for all shift-based test modes.
//
// mem_bypass
//
// Memory bypass control for arrays without output
// flops. Allows testing of shadow logic. Asserted
// for scan test; de-asserted for macrotest.
//
//
// Dynamic Output Signals
// ======================
//
// sehold
//
// The sehold signal needs to be set for macrotest
// to allow holding flops in the array collars
// to retain their shifted data during capture.
// Inverted version of scan enable during macrotest.
//
// mux_drive_disable (for mux/long chain protection)
//
// Activate one-hot mux protection circuitry during
// scan shift and reset. Formerly known as rst_tri_en.
// Also used by long chain memories with embedded
// control.
//
// mem_write_disable (for short chain protection)
//
// Protects contents of short chain memories during
// shift and POR.
//
// se
assign mux_drive_disable = ~ctu_tst_pre_grst_l | short_chain_select | se;
assign mem_write_disable = ~ctu_tst_pre_grst_l | se;
assign sehold = ctu_tst_macrotest & ~se;
assign se = global_shift_enable;
assign testmode_l = ~ctu_tst_scanmode;
assign mem_bypass = ~ctu_tst_macrotest & ~testmode_l;
assign pin_based_scan = ctu_tst_scan_disable;
assign short_chain_en = ~(pin_based_scan & se);
assign short_chain_select = ctu_tst_short_chain & ~testmode_l & short_chain_en;
assign so_0 = short_chain_select ? short_chain_so_0 : long_chain_so_0;
assign so_1 = short_chain_select ? short_chain_so_1 : long_chain_so_1;
assign so_2 = short_chain_select ? short_chain_so_2 : long_chain_so_2;
endmodule // test_stub_scan
|
`timescale 1 ns / 1 ps
`default_nettype none
`define WIDTH 32
module j1b(input wire clk,
input wire resetq,
output wire uart0_wr,
output wire uart0_rd,
output wire [7:0] uart_w,
input wire uart0_valid,
input wire [7:0] uart0_data
);
wire io_rd, io_wr;
wire [15:0] mem_addr;
wire mem_wr;
reg [31:0] mem_din;
wire [31:0] dout;
wire [31:0] io_din;
wire [12:0] code_addr;
wire [15:0] insn;
wire [12:0] codeaddr = {1'b0, code_addr[12:1]};
reg [31:0] ram[0:8191] /* verilator public_flat */;
always @(posedge clk) begin
// $display("pc=%x", code_addr * 2);
insn <= code_addr[0] ? ram[codeaddr][31:16] : ram[codeaddr][15:0];
if (mem_wr)
ram[mem_addr[14:2]] <= dout;
mem_din <= ram[mem_addr[14:2]];
end
j1 _j1(
.clk(clk),
.resetq(resetq),
.io_rd(io_rd),
.io_wr(io_wr),
.mem_wr(mem_wr),
.dout(dout),
.mem_din(mem_din),
.io_din(io_din),
.mem_addr(mem_addr),
.code_addr(code_addr),
.insn(insn));
// ###### IO SIGNALS ####################################
reg io_wr_, io_rd_;
/* verilator lint_off UNUSED */
reg [31:0] dout_;
reg [15:0] io_addr_;
/* verilator lint_on UNUSED */
always @(posedge clk) begin
{io_rd_, io_wr_, dout_} <= {io_rd, io_wr, dout};
if (io_rd | io_wr)
io_addr_ <= mem_addr;
end
// ###### UART ##########################################
wire uart0_wr = io_wr_ & io_addr_[12];
wire uart0_rd = io_rd_ & io_addr_[12];
assign uart_w = dout_[7:0];
// always @(posedge clk) begin
// if (uart0_wr)
// $display("--- out %x %c", uart_w, uart_w);
// if (uart0_rd)
// $display("--- in %x %c", uart0_data, uart0_data);
// end
// ###### IO PORTS ######################################
/* bit READ WRITE
1000 12 UART RX UART TX
2000 13 misc.in
*/
assign io_din =
(io_addr_[12] ? {24'd0, uart0_data} : 32'd0) |
(io_addr_[13] ? {28'd0, 1'b0, 1'b0, uart0_valid, 1'b1} : 32'd0);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: data_prbs_gen.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:19 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module is used LFSR to generate random data for memory
// data write or memory data read comparison.The first data is
// seeded by the input prbs_seed_i which is connected to memory address.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_0_data_prbs_gen #
(
parameter TCQ = 100,
parameter EYE_TEST = "FALSE",
parameter PRBS_WIDTH = 32, // "SEQUENTIAL_BUrst_i"
parameter SEED_WIDTH = 32
)
(
input clk_i,
input clk_en,
input rst_i,
input prbs_seed_init, // when high the prbs_x_seed will be loaded
input [PRBS_WIDTH - 1:0] prbs_seed_i,
output [PRBS_WIDTH - 1:0] prbs_o // generated address
);
reg [PRBS_WIDTH - 1 :0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
integer i;
always @ (posedge clk_i)
begin
if (prbs_seed_init && EYE_TEST == "FALSE" || rst_i ) //reset it to a known good state to prevent it locks up
// if (rst_i ) //reset it to a known good state to prevent it locks up
begin
lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5;
// lfsr_q[PRBS_WIDTH-1:4] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ;
lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ;
end
else if (clk_en) begin
lfsr_q[32:9] <= #TCQ lfsr_q[31:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
always @ (lfsr_q[PRBS_WIDTH:1]) begin
prbs = lfsr_q[PRBS_WIDTH:1];
end
assign prbs_o = prbs;
endmodule
|
`define WIDTH_P 3
`define ELS_P 4
`define SEED_P 10000
/**************************** TEST RATIONALE *******************************
1. STATE SPACE
Since the memory is synchronous, we can either write or read but not do both
at the same time. The memory is tested in two passes. In the first pass, a
random number is written to a memory location and is immediately read in the
next clock cycle. This process is repeated sequentially for every location thus
testing the memory exhaustively. In the second pass, v_i input is made low and
approximately half of the memory is tested.
2. PARAMETERIZATION
The synthesis of the design is not much influenced by data width WIDTH_P.
But the parameter ELS_P must be varied to include different cases, powers of 2
and non power of 2 for example. SEED_P may be varied to generated different
streams of random numbers that are written to the test memory. So a minimum
set of tests might be WIDTH_P=1,4,5 and ELS_P=1,2,3,4,5,8.
***************************************************************************/
module test_bsg;
#(
parameter width_p = `WIDTH_P,
parameter els_p = `ELS_P,
parameter addr_width_p = `BSG_SAFE_CLOG2(`ELS_P),
parameter cycle_time_p = 20,
parameter seed_p = `SEED_P,
parameter reset_cycles_lo_p=1,
parameter reset_cycles_hi_p=5
);
// clock and reset generation
wire clk;
wire reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(reset_cycles_lo_p)
, .reset_cycles_hi_p(reset_cycles_hi_p)
) reset_gen
( .clk_i (clk)
, .async_reset_o(reset)
);
initial
begin
/*$monitor( "@%0t: count:%d", $time, count
, " test_input_data:%b test_input_addr:%b test_input_w:%b test_input_v:%b"
, test_input_data, test_input_addr, test_input_w, test_input_v
, " test_input_data_r:%b test_output_data:%b"
, test_input_data_r, test_output_data
);*/
$display("\n\n\n");
$display("===========================================================");
$display("testing bsg_mem_1rw_sync with ...");
$display("WIDTH_P: %0d", width_p);
$display("ELS_P : %0d\n", els_p);
end
logic [width_p-1:0] test_input_data, test_input_data_r
, test_output_data, test_output_data_r;
logic [addr_width_p-1:0] test_input_addr;
logic test_input_w, test_input_v;
logic [`BSG_SAFE_CLOG2(3*els_p):0] count;
bsg_cycle_counter #( .width_p (`BSG_SAFE_CLOG2(3*els_p)+1)
, .init_val_p()
) cycle_counter
( .clk_i (clk)
, .reset_i(reset)
, .ctr_r_o(count)
);
// random test data generation;
// generates a new random number after every +ve clock edge
bsg_nonsynth_random_gen #( .width_p(width_p)
, .seed_p (seed_p)
) random_gen
( .clk_i (clk)
, .reset_i(reset)
, .yumi_i (1'b1)
, .data_o (test_input_data)
);
always_ff @(posedge clk)
begin
test_output_data_r <= test_output_data;
if(test_input_w)
test_input_data_r <= test_input_data;
if(reset)
begin
test_input_addr <= addr_width_p'(0);
test_input_w <= 1'b1;
test_input_v <= 1'b1;
end
else
begin
test_input_w <= !(test_input_w);
test_input_addr <= test_input_addr + !(test_input_w);
if(count < 2*els_p-1) // first pass
test_input_v <= 1'b1;
else if(count < 3*els_p) // second pass, covers only a portion of mem.
test_input_v <= 1'b0;
else
begin
$display("=======================================================\n");
$finish;
end
end
end
logic new_read; // is set if newly written value is read in first pass
always_ff @(posedge clk)
begin
if(reset)
new_read <= 1'b0; // initializing new_read
else
begin
// if w_i is low and v_i is high a new mem. location is read
if(count <= 2*els_p-1)
begin
if((!test_input_w) && test_input_v)
new_read <= 1'b1;
else
new_read <= 1'b0;
end
else
new_read <= 1'b0;
if(count >= 2)
begin
if(count <= 2*els_lp && new_read) // new read in first pass
assert(test_output_data == test_input_data_r)
else $error("output=%b expected_output:%b\n"
, test_output_data, test_input_data_r);
else
assert(test_output_data == test_output_data_r)
else $error("output=%b expected_output:%b\n"
, test_output_data, test_output_data_r);
end
end
end
bsg_mem_1rw_sync #( .width_p(width_p)
, .els_p (els_p)
) DUT
( .clk_i (clk)
, .reset_i(reset)
, .data_i (test_input_data)
, .addr_i (test_input_addr)
, .v_i (test_input_v)
, .w_i (test_input_w)
, .data_o (test_output_data)
);
endmodule
|
// megafunction wizard: %ALTECC%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altecc_decoder
// ============================================================
// File Name: alt_ddrx_decoder_72.v
// Megafunction Name(s):
// altecc_decoder
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Internal Build 157 07/06/2009 PN Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altecc_decoder CBX_AUTO_BLACKBOX="ALL" device_family="Stratix" lpm_pipeline=1 width_codeword=72 width_dataword=64 clock data err_corrected err_detected err_fatal q
//VERSION_BEGIN 9.1 cbx_altecc_decoder 2009:06:09:13:32:57:PN cbx_cycloneii 2008:05:20:01:57:37:PN cbx_lpm_add_sub 2009:05:05:06:30:25:PN cbx_lpm_compare 2009:02:26:09:32:14:PN cbx_lpm_decode 2009:02:26:09:32:14:PN cbx_mgl 2009:07:03:02:47:54:PN cbx_stratix 2009:07:02:14:27:13:PN cbx_stratixii 2009:05:21:05:59:50:PN VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = lpm_decode 1 lut 67 mux21 64
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_ddrx_decoder_72_altecc_decoder_e8f
(
clock,
data,
err_corrected,
err_detected,
err_fatal,
q) ;
input clock;
input [71:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output [63:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] err_corrected_pipeline0c;
reg [0:0] err_detected_pipeline0c;
reg [0:0] err_fatal_pipeline0c;
reg [63:0] output_pipeline0c;
wire [127:0] wire_error_bit_decoder_eq;
wire wire_mux21_0_dataout;
wire wire_mux21_1_dataout;
wire wire_mux21_10_dataout;
wire wire_mux21_11_dataout;
wire wire_mux21_12_dataout;
wire wire_mux21_13_dataout;
wire wire_mux21_14_dataout;
wire wire_mux21_15_dataout;
wire wire_mux21_16_dataout;
wire wire_mux21_17_dataout;
wire wire_mux21_18_dataout;
wire wire_mux21_19_dataout;
wire wire_mux21_2_dataout;
wire wire_mux21_20_dataout;
wire wire_mux21_21_dataout;
wire wire_mux21_22_dataout;
wire wire_mux21_23_dataout;
wire wire_mux21_24_dataout;
wire wire_mux21_25_dataout;
wire wire_mux21_26_dataout;
wire wire_mux21_27_dataout;
wire wire_mux21_28_dataout;
wire wire_mux21_29_dataout;
wire wire_mux21_3_dataout;
wire wire_mux21_30_dataout;
wire wire_mux21_31_dataout;
wire wire_mux21_32_dataout;
wire wire_mux21_33_dataout;
wire wire_mux21_34_dataout;
wire wire_mux21_35_dataout;
wire wire_mux21_36_dataout;
wire wire_mux21_37_dataout;
wire wire_mux21_38_dataout;
wire wire_mux21_39_dataout;
wire wire_mux21_4_dataout;
wire wire_mux21_40_dataout;
wire wire_mux21_41_dataout;
wire wire_mux21_42_dataout;
wire wire_mux21_43_dataout;
wire wire_mux21_44_dataout;
wire wire_mux21_45_dataout;
wire wire_mux21_46_dataout;
wire wire_mux21_47_dataout;
wire wire_mux21_48_dataout;
wire wire_mux21_49_dataout;
wire wire_mux21_5_dataout;
wire wire_mux21_50_dataout;
wire wire_mux21_51_dataout;
wire wire_mux21_52_dataout;
wire wire_mux21_53_dataout;
wire wire_mux21_54_dataout;
wire wire_mux21_55_dataout;
wire wire_mux21_56_dataout;
wire wire_mux21_57_dataout;
wire wire_mux21_58_dataout;
wire wire_mux21_59_dataout;
wire wire_mux21_6_dataout;
wire wire_mux21_60_dataout;
wire wire_mux21_61_dataout;
wire wire_mux21_62_dataout;
wire wire_mux21_63_dataout;
wire wire_mux21_7_dataout;
wire wire_mux21_8_dataout;
wire wire_mux21_9_dataout;
wire aclr;
wire clocken;
wire data_bit;
wire [63:0] data_t;
wire [71:0] data_wire;
wire [127:0] decode_output;
wire err_corrected_wire;
wire err_detected_wire;
wire err_fatal_wire;
wire [35:0] parity_01_wire;
wire [17:0] parity_02_wire;
wire [8:0] parity_03_wire;
wire [3:0] parity_04_wire;
wire [1:0] parity_05_wire;
wire [30:0] parity_06_wire;
wire [6:0] parity_07_wire;
wire parity_bit;
wire [70:0] parity_final_wire;
wire [6:0] parity_t;
wire [63:0] q_wire;
wire syn_bit;
wire syn_e;
wire [5:0] syn_t;
wire [7:0] syndrome;
// synopsys translate_off
initial
err_corrected_pipeline0c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) err_corrected_pipeline0c <= 1'b0;
else if (clocken == 1'b1) err_corrected_pipeline0c <= err_corrected_wire;
// synopsys translate_off
initial
err_detected_pipeline0c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) err_detected_pipeline0c <= 1'b0;
else if (clocken == 1'b1) err_detected_pipeline0c <= err_detected_wire;
// synopsys translate_off
initial
err_fatal_pipeline0c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) err_fatal_pipeline0c <= 1'b0;
else if (clocken == 1'b1) err_fatal_pipeline0c <= err_fatal_wire;
// synopsys translate_off
initial
output_pipeline0c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) output_pipeline0c <= 64'b0;
else if (clocken == 1'b1) output_pipeline0c <= q_wire;
lpm_decode error_bit_decoder
(
.data(syndrome[6:0]),
.eq(wire_error_bit_decoder_eq)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0),
.enable(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
error_bit_decoder.lpm_decodes = 128,
error_bit_decoder.lpm_width = 7,
error_bit_decoder.lpm_type = "lpm_decode";
assign wire_mux21_0_dataout = (syndrome[7] === 1'b1) ? (decode_output[3] ^ data_wire[0]) : data_wire[0];
assign wire_mux21_1_dataout = (syndrome[7] === 1'b1) ? (decode_output[5] ^ data_wire[1]) : data_wire[1];
assign wire_mux21_10_dataout = (syndrome[7] === 1'b1) ? (decode_output[15] ^ data_wire[10]) : data_wire[10];
assign wire_mux21_11_dataout = (syndrome[7] === 1'b1) ? (decode_output[17] ^ data_wire[11]) : data_wire[11];
assign wire_mux21_12_dataout = (syndrome[7] === 1'b1) ? (decode_output[18] ^ data_wire[12]) : data_wire[12];
assign wire_mux21_13_dataout = (syndrome[7] === 1'b1) ? (decode_output[19] ^ data_wire[13]) : data_wire[13];
assign wire_mux21_14_dataout = (syndrome[7] === 1'b1) ? (decode_output[20] ^ data_wire[14]) : data_wire[14];
assign wire_mux21_15_dataout = (syndrome[7] === 1'b1) ? (decode_output[21] ^ data_wire[15]) : data_wire[15];
assign wire_mux21_16_dataout = (syndrome[7] === 1'b1) ? (decode_output[22] ^ data_wire[16]) : data_wire[16];
assign wire_mux21_17_dataout = (syndrome[7] === 1'b1) ? (decode_output[23] ^ data_wire[17]) : data_wire[17];
assign wire_mux21_18_dataout = (syndrome[7] === 1'b1) ? (decode_output[24] ^ data_wire[18]) : data_wire[18];
assign wire_mux21_19_dataout = (syndrome[7] === 1'b1) ? (decode_output[25] ^ data_wire[19]) : data_wire[19];
assign wire_mux21_2_dataout = (syndrome[7] === 1'b1) ? (decode_output[6] ^ data_wire[2]) : data_wire[2];
assign wire_mux21_20_dataout = (syndrome[7] === 1'b1) ? (decode_output[26] ^ data_wire[20]) : data_wire[20];
assign wire_mux21_21_dataout = (syndrome[7] === 1'b1) ? (decode_output[27] ^ data_wire[21]) : data_wire[21];
assign wire_mux21_22_dataout = (syndrome[7] === 1'b1) ? (decode_output[28] ^ data_wire[22]) : data_wire[22];
assign wire_mux21_23_dataout = (syndrome[7] === 1'b1) ? (decode_output[29] ^ data_wire[23]) : data_wire[23];
assign wire_mux21_24_dataout = (syndrome[7] === 1'b1) ? (decode_output[30] ^ data_wire[24]) : data_wire[24];
assign wire_mux21_25_dataout = (syndrome[7] === 1'b1) ? (decode_output[31] ^ data_wire[25]) : data_wire[25];
assign wire_mux21_26_dataout = (syndrome[7] === 1'b1) ? (decode_output[33] ^ data_wire[26]) : data_wire[26];
assign wire_mux21_27_dataout = (syndrome[7] === 1'b1) ? (decode_output[34] ^ data_wire[27]) : data_wire[27];
assign wire_mux21_28_dataout = (syndrome[7] === 1'b1) ? (decode_output[35] ^ data_wire[28]) : data_wire[28];
assign wire_mux21_29_dataout = (syndrome[7] === 1'b1) ? (decode_output[36] ^ data_wire[29]) : data_wire[29];
assign wire_mux21_3_dataout = (syndrome[7] === 1'b1) ? (decode_output[7] ^ data_wire[3]) : data_wire[3];
assign wire_mux21_30_dataout = (syndrome[7] === 1'b1) ? (decode_output[37] ^ data_wire[30]) : data_wire[30];
assign wire_mux21_31_dataout = (syndrome[7] === 1'b1) ? (decode_output[38] ^ data_wire[31]) : data_wire[31];
assign wire_mux21_32_dataout = (syndrome[7] === 1'b1) ? (decode_output[39] ^ data_wire[32]) : data_wire[32];
assign wire_mux21_33_dataout = (syndrome[7] === 1'b1) ? (decode_output[40] ^ data_wire[33]) : data_wire[33];
assign wire_mux21_34_dataout = (syndrome[7] === 1'b1) ? (decode_output[41] ^ data_wire[34]) : data_wire[34];
assign wire_mux21_35_dataout = (syndrome[7] === 1'b1) ? (decode_output[42] ^ data_wire[35]) : data_wire[35];
assign wire_mux21_36_dataout = (syndrome[7] === 1'b1) ? (decode_output[43] ^ data_wire[36]) : data_wire[36];
assign wire_mux21_37_dataout = (syndrome[7] === 1'b1) ? (decode_output[44] ^ data_wire[37]) : data_wire[37];
assign wire_mux21_38_dataout = (syndrome[7] === 1'b1) ? (decode_output[45] ^ data_wire[38]) : data_wire[38];
assign wire_mux21_39_dataout = (syndrome[7] === 1'b1) ? (decode_output[46] ^ data_wire[39]) : data_wire[39];
assign wire_mux21_4_dataout = (syndrome[7] === 1'b1) ? (decode_output[9] ^ data_wire[4]) : data_wire[4];
assign wire_mux21_40_dataout = (syndrome[7] === 1'b1) ? (decode_output[47] ^ data_wire[40]) : data_wire[40];
assign wire_mux21_41_dataout = (syndrome[7] === 1'b1) ? (decode_output[48] ^ data_wire[41]) : data_wire[41];
assign wire_mux21_42_dataout = (syndrome[7] === 1'b1) ? (decode_output[49] ^ data_wire[42]) : data_wire[42];
assign wire_mux21_43_dataout = (syndrome[7] === 1'b1) ? (decode_output[50] ^ data_wire[43]) : data_wire[43];
assign wire_mux21_44_dataout = (syndrome[7] === 1'b1) ? (decode_output[51] ^ data_wire[44]) : data_wire[44];
assign wire_mux21_45_dataout = (syndrome[7] === 1'b1) ? (decode_output[52] ^ data_wire[45]) : data_wire[45];
assign wire_mux21_46_dataout = (syndrome[7] === 1'b1) ? (decode_output[53] ^ data_wire[46]) : data_wire[46];
assign wire_mux21_47_dataout = (syndrome[7] === 1'b1) ? (decode_output[54] ^ data_wire[47]) : data_wire[47];
assign wire_mux21_48_dataout = (syndrome[7] === 1'b1) ? (decode_output[55] ^ data_wire[48]) : data_wire[48];
assign wire_mux21_49_dataout = (syndrome[7] === 1'b1) ? (decode_output[56] ^ data_wire[49]) : data_wire[49];
assign wire_mux21_5_dataout = (syndrome[7] === 1'b1) ? (decode_output[10] ^ data_wire[5]) : data_wire[5];
assign wire_mux21_50_dataout = (syndrome[7] === 1'b1) ? (decode_output[57] ^ data_wire[50]) : data_wire[50];
assign wire_mux21_51_dataout = (syndrome[7] === 1'b1) ? (decode_output[58] ^ data_wire[51]) : data_wire[51];
assign wire_mux21_52_dataout = (syndrome[7] === 1'b1) ? (decode_output[59] ^ data_wire[52]) : data_wire[52];
assign wire_mux21_53_dataout = (syndrome[7] === 1'b1) ? (decode_output[60] ^ data_wire[53]) : data_wire[53];
assign wire_mux21_54_dataout = (syndrome[7] === 1'b1) ? (decode_output[61] ^ data_wire[54]) : data_wire[54];
assign wire_mux21_55_dataout = (syndrome[7] === 1'b1) ? (decode_output[62] ^ data_wire[55]) : data_wire[55];
assign wire_mux21_56_dataout = (syndrome[7] === 1'b1) ? (decode_output[63] ^ data_wire[56]) : data_wire[56];
assign wire_mux21_57_dataout = (syndrome[7] === 1'b1) ? (decode_output[65] ^ data_wire[57]) : data_wire[57];
assign wire_mux21_58_dataout = (syndrome[7] === 1'b1) ? (decode_output[66] ^ data_wire[58]) : data_wire[58];
assign wire_mux21_59_dataout = (syndrome[7] === 1'b1) ? (decode_output[67] ^ data_wire[59]) : data_wire[59];
assign wire_mux21_6_dataout = (syndrome[7] === 1'b1) ? (decode_output[11] ^ data_wire[6]) : data_wire[6];
assign wire_mux21_60_dataout = (syndrome[7] === 1'b1) ? (decode_output[68] ^ data_wire[60]) : data_wire[60];
assign wire_mux21_61_dataout = (syndrome[7] === 1'b1) ? (decode_output[69] ^ data_wire[61]) : data_wire[61];
assign wire_mux21_62_dataout = (syndrome[7] === 1'b1) ? (decode_output[70] ^ data_wire[62]) : data_wire[62];
assign wire_mux21_63_dataout = (syndrome[7] === 1'b1) ? (decode_output[71] ^ data_wire[63]) : data_wire[63];
assign wire_mux21_7_dataout = (syndrome[7] === 1'b1) ? (decode_output[12] ^ data_wire[7]) : data_wire[7];
assign wire_mux21_8_dataout = (syndrome[7] === 1'b1) ? (decode_output[13] ^ data_wire[8]) : data_wire[8];
assign wire_mux21_9_dataout = (syndrome[7] === 1'b1) ? (decode_output[14] ^ data_wire[9]) : data_wire[9];
assign
aclr = 1'b0,
clocken = 1'b1,
data_bit = data_t[63],
data_t = {(data_t[62] | decode_output[71]), (data_t[61] | decode_output[70]), (data_t[60] | decode_output[69]), (data_t[59] | decode_output[68]), (data_t[58] | decode_output[67]), (data_t[57] | decode_output[66]), (data_t[56] | decode_output[65]), (data_t[55] | decode_output[63]), (data_t[54] | decode_output[62]), (data_t[53] | decode_output[61]), (data_t[52] | decode_output[60]), (data_t[51] | decode_output[59]), (data_t[50] | decode_output[58]), (data_t[49] | decode_output[57]), (data_t[48] | decode_output[56]), (data_t[47] | decode_output[55]), (data_t[46] | decode_output[54]), (data_t[45] | decode_output[53]), (data_t[44] | decode_output[52]), (data_t[43] | decode_output[51]), (data_t[42] | decode_output[50]), (data_t[41] | decode_output[49]), (data_t[40] | decode_output[48]), (data_t[39] | decode_output[47]), (data_t[38] | decode_output[46]), (data_t[37] | decode_output[45]), (data_t[36] | decode_output[44]), (data_t[35] | decode_output[43]), (data_t[34] | decode_output[42]), (data_t[33] | decode_output[41]), (data_t[32] | decode_output[40]), (data_t[31] | decode_output[39]), (data_t[30] | decode_output[38]), (data_t[29] | decode_output[37]), (data_t[28] | decode_output[36]), (data_t[27] | decode_output[35]), (data_t[26] | decode_output[34]), (data_t[25] | decode_output[33]), (data_t[24] | decode_output[31]), (data_t[23] | decode_output[30]), (data_t[22] | decode_output[29]), (data_t[21] | decode_output[28]), (data_t[20] | decode_output[27]), (data_t[19] | decode_output[26]), (data_t[18] | decode_output[25]), (data_t[17] | decode_output[24]), (data_t[16] | decode_output[23]), (data_t[15] | decode_output[22]), (data_t[14] | decode_output[21]), (data_t[13] | decode_output[20]), (data_t[12] | decode_output[19]), (data_t[11] | decode_output[18]), (data_t[10] | decode_output[17]), (data_t[9] | decode_output[15]), (data_t[8] | decode_output[14]), (data_t[7] | decode_output[13]), (data_t[6] | decode_output[12]), (data_t[5] | decode_output[11]), (data_t[4] | decode_output[10]), (data_t[3] | decode_output[9]), (data_t[2]
| decode_output[7]), (data_t[1] | decode_output[6]), (data_t[0] | decode_output[5]), decode_output[3]},
data_wire = data,
decode_output = wire_error_bit_decoder_eq,
err_corrected = err_corrected_pipeline0c,
err_corrected_wire = ((syn_bit & syn_e) & data_bit),
err_detected = err_detected_pipeline0c,
err_detected_wire = (syn_bit & (~ (syn_e & parity_bit))),
err_fatal = err_fatal_pipeline0c,
err_fatal_wire = (err_detected_wire & (~ err_corrected_wire)),
parity_01_wire = {(data_wire[63] ^ parity_01_wire[34]), (data_wire[61] ^ parity_01_wire[33]), (data_wire[59] ^ parity_01_wire[32]), (data_wire[57] ^ parity_01_wire[31]), (data_wire[56] ^ parity_01_wire[30]), (data_wire[54] ^ parity_01_wire[29]), (data_wire[52] ^ parity_01_wire[28]), (data_wire[50] ^ parity_01_wire[27]), (data_wire[48] ^ parity_01_wire[26]), (data_wire[46] ^ parity_01_wire[25]), (data_wire[44] ^ parity_01_wire[24]), (data_wire[42] ^ parity_01_wire[23]), (data_wire[40] ^ parity_01_wire[22]), (data_wire[38] ^ parity_01_wire[21]), (data_wire[36] ^ parity_01_wire[20]), (data_wire[34] ^ parity_01_wire[19]), (data_wire[32] ^ parity_01_wire[18]), (data_wire[30] ^ parity_01_wire[17]), (data_wire[28] ^ parity_01_wire[16]), (data_wire[26] ^ parity_01_wire[15]), (data_wire[25] ^ parity_01_wire[14]), (data_wire[23] ^ parity_01_wire[13]), (data_wire[21] ^ parity_01_wire[12]), (data_wire[19] ^ parity_01_wire[11]), (data_wire[17] ^ parity_01_wire[10]), (data_wire[15] ^ parity_01_wire[9]), (data_wire[13] ^ parity_01_wire[8]), (data_wire[11] ^ parity_01_wire[7]), (data_wire[10] ^ parity_01_wire[6]), (data_wire[8] ^ parity_01_wire[5]), (data_wire[6] ^ parity_01_wire[4]), (data_wire[4] ^ parity_01_wire[3]), (data_wire[3] ^ parity_01_wire[2]), (data_wire[1] ^ parity_01_wire[1]), (data_wire[0] ^ parity_01_wire[0]), data_wire[64]},
parity_02_wire = {((data_wire[62] ^ data_wire[63]) ^ parity_02_wire[16]), ((data_wire[58] ^ data_wire[59]) ^ parity_02_wire[15]), ((data_wire[55] ^ data_wire[56]) ^ parity_02_wire[14]), ((data_wire[51] ^ data_wire[52]) ^ parity_02_wire[13]), ((data_wire[47] ^ data_wire[48]) ^ parity_02_wire[12]), ((data_wire[43] ^ data_wire[44]) ^ parity_02_wire[11]), ((data_wire[39] ^ data_wire[40]) ^ parity_02_wire[10]), ((data_wire[35] ^ data_wire[36]) ^ parity_02_wire[9]), ((data_wire[31] ^ data_wire[32]) ^ parity_02_wire[8]), ((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]), ((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]), ((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]), ((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]), ((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]), ((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]), ((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]), ((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]), (data_wire[65] ^ data_wire[0])},
parity_03_wire = {((((data_wire[60] ^ data_wire[61]) ^ data_wire[62]) ^ data_wire[63]) ^ parity_03_wire[7]), ((((data_wire[53] ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_03_wire[6]), ((((data_wire[45] ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ parity_03_wire[5]), ((((data_wire[37] ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_03_wire[4]), ((((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ data_wire[32]) ^ parity_03_wire[3]), ((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]), ((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]), ((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]), (((data_wire[66] ^ data_wire[1]) ^ data_wire[2]) ^ data_wire[3])},
parity_04_wire = {((((((((data_wire[49] ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_04_wire[2]), ((((((((data_wire[33] ^ data_wire[34]) ^ data_wire[35]) ^ data_wire[36]) ^ data_wire[37]) ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_04_wire[1]), ((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]), (((((((data_wire[67] ^ data_wire[4]) ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])},
parity_05_wire = {((((((((((((((((data_wire[41] ^ data_wire[42]) ^ data_wire[43]) ^ data_wire[44]) ^ data_wire[45]) ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ data_wire[49]) ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_05_wire[0]), (((((((((((((((data_wire[68] ^ data_wire[11]) ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])},
parity_06_wire = {(data_wire[56] ^ parity_06_wire[29]), (data_wire[55] ^ parity_06_wire[28]), (data_wire[54] ^ parity_06_wire[27]), (data_wire[53] ^ parity_06_wire[26]), (data_wire[52] ^ parity_06_wire[25]), (data_wire[51] ^ parity_06_wire[24]), (data_wire[50] ^ parity_06_wire[23]), (data_wire[49] ^ parity_06_wire[22]), (data_wire[48] ^ parity_06_wire[21]), (data_wire[47] ^ parity_06_wire[20]), (data_wire[46] ^ parity_06_wire[19]), (data_wire[45] ^ parity_06_wire[18]), (data_wire[44] ^ parity_06_wire[17]), (data_wire[43] ^ parity_06_wire[16]), (data_wire[42] ^ parity_06_wire[15]), (data_wire[41] ^ parity_06_wire[14]), (data_wire[40] ^ parity_06_wire[13]), (data_wire[39] ^ parity_06_wire[12]), (data_wire[38] ^ parity_06_wire[11]), (data_wire[37] ^ parity_06_wire[10]), (data_wire[36] ^ parity_06_wire[9]), (data_wire[35] ^ parity_06_wire[8]), (data_wire[34] ^ parity_06_wire[7]), (data_wire[33] ^ parity_06_wire[6]), (data_wire[32] ^ parity_06_wire[5]), (data_wire[31] ^ parity_06_wire[4]), (data_wire[30] ^ parity_06_wire[3]), (data_wire[29] ^ parity_06_wire[2]), (data_wire[28] ^ parity_06_wire[1]), (data_wire[27] ^ parity_06_wire[0]), (data_wire[69] ^ data_wire[26])},
parity_07_wire = {(data_wire[63] ^ parity_07_wire[5]), (data_wire[62] ^ parity_07_wire[4]), (data_wire[61] ^ parity_07_wire[3]), (data_wire[60] ^ parity_07_wire[2]), (data_wire[59] ^ parity_07_wire[1]), (data_wire[58] ^ parity_07_wire[0]), (data_wire[70] ^ data_wire[57])},
parity_bit = parity_t[6],
parity_final_wire = {(data_wire[70] ^ parity_final_wire[69]), (data_wire[69] ^ parity_final_wire[68]), (data_wire[68] ^ parity_final_wire[67]), (data_wire[67] ^ parity_final_wire[66]), (data_wire[66] ^ parity_final_wire[65]), (data_wire[65] ^ parity_final_wire[64]), (data_wire[64] ^ parity_final_wire[63]), (data_wire[63] ^ parity_final_wire[62]), (data_wire[62] ^ parity_final_wire[61]), (data_wire[61] ^ parity_final_wire[60]), (data_wire[60] ^ parity_final_wire[59]), (data_wire[59] ^ parity_final_wire[58]), (data_wire[58] ^ parity_final_wire[57]), (data_wire[57] ^ parity_final_wire[56]), (data_wire[56] ^ parity_final_wire[55]), (data_wire[55] ^ parity_final_wire[54]), (data_wire[54] ^ parity_final_wire[53]), (data_wire[53] ^ parity_final_wire[52]), (data_wire[52] ^ parity_final_wire[51]), (data_wire[51] ^ parity_final_wire[50]), (data_wire[50] ^ parity_final_wire[49]), (data_wire[49] ^ parity_final_wire[48]), (data_wire[48] ^ parity_final_wire[47]), (data_wire[47] ^ parity_final_wire[46]), (data_wire[46] ^ parity_final_wire[45]), (data_wire[45] ^ parity_final_wire[44]), (data_wire[44] ^ parity_final_wire[43]), (data_wire[43] ^ parity_final_wire[42]), (data_wire[42] ^ parity_final_wire[41]), (data_wire[41] ^ parity_final_wire[40]), (data_wire[40] ^ parity_final_wire[39]), (data_wire[39] ^ parity_final_wire[38]), (data_wire[38] ^ parity_final_wire[37]), (data_wire[37] ^ parity_final_wire[36]), (data_wire[36] ^ parity_final_wire[35]), (data_wire[35] ^ parity_final_wire[34]), (data_wire[34] ^ parity_final_wire[33]), (data_wire[33] ^ parity_final_wire[32]), (data_wire[32] ^ parity_final_wire[31]), (data_wire[31] ^ parity_final_wire[30]), (data_wire[30] ^ parity_final_wire[29]), (data_wire[29] ^ parity_final_wire[28]), (data_wire[28] ^ parity_final_wire[27]), (data_wire[27] ^ parity_final_wire[26]), (data_wire[26] ^ parity_final_wire[25]), (data_wire[25] ^ parity_final_wire[24]), (data_wire[24] ^ parity_final_wire[23]), (data_wire[23] ^ parity_final_wire[22]), (data_wire[22] ^ parity_final_wire[21]), (data_wire[21] ^
parity_final_wire[20]), (data_wire[20] ^ parity_final_wire[19]), (data_wire[19] ^ parity_final_wire[18]), (data_wire[18] ^ parity_final_wire[17]), (data_wire[17] ^ parity_final_wire[16]), (data_wire[16] ^ parity_final_wire[15]), (data_wire[15] ^ parity_final_wire[14]), (data_wire[14] ^ parity_final_wire[13]), (data_wire[13] ^ parity_final_wire[12]), (data_wire[12] ^ parity_final_wire[11]), (data_wire[11] ^ parity_final_wire[10]), (data_wire[10] ^ parity_final_wire[9]), (data_wire[9] ^ parity_final_wire[8]), (data_wire[8] ^ parity_final_wire[7]), (data_wire[7] ^ parity_final_wire[6]), (data_wire[6] ^ parity_final_wire[5]), (data_wire[5] ^ parity_final_wire[4]), (data_wire[4] ^ parity_final_wire[3]), (data_wire[3] ^ parity_final_wire[2]), (data_wire[2] ^ parity_final_wire[1]), (data_wire[1] ^ parity_final_wire[0]), (data_wire[71] ^ data_wire[0])},
parity_t = {(parity_t[5] | decode_output[64]), (parity_t[4] | decode_output[32]), (parity_t[3] | decode_output[16]), (parity_t[2] | decode_output[8]), (parity_t[1] | decode_output[4]), (parity_t[0] | decode_output[2]), decode_output[1]},
q = output_pipeline0c,
q_wire = {wire_mux21_63_dataout, wire_mux21_62_dataout, wire_mux21_61_dataout, wire_mux21_60_dataout, wire_mux21_59_dataout, wire_mux21_58_dataout, wire_mux21_57_dataout, wire_mux21_56_dataout, wire_mux21_55_dataout, wire_mux21_54_dataout, wire_mux21_53_dataout, wire_mux21_52_dataout, wire_mux21_51_dataout, wire_mux21_50_dataout, wire_mux21_49_dataout, wire_mux21_48_dataout, wire_mux21_47_dataout, wire_mux21_46_dataout, wire_mux21_45_dataout, wire_mux21_44_dataout, wire_mux21_43_dataout, wire_mux21_42_dataout, wire_mux21_41_dataout, wire_mux21_40_dataout, wire_mux21_39_dataout, wire_mux21_38_dataout, wire_mux21_37_dataout, wire_mux21_36_dataout, wire_mux21_35_dataout, wire_mux21_34_dataout, wire_mux21_33_dataout, wire_mux21_32_dataout, wire_mux21_31_dataout, wire_mux21_30_dataout, wire_mux21_29_dataout, wire_mux21_28_dataout, wire_mux21_27_dataout, wire_mux21_26_dataout, wire_mux21_25_dataout, wire_mux21_24_dataout, wire_mux21_23_dataout, wire_mux21_22_dataout, wire_mux21_21_dataout, wire_mux21_20_dataout, wire_mux21_19_dataout, wire_mux21_18_dataout, wire_mux21_17_dataout, wire_mux21_16_dataout, wire_mux21_15_dataout, wire_mux21_14_dataout, wire_mux21_13_dataout, wire_mux21_12_dataout, wire_mux21_11_dataout, wire_mux21_10_dataout, wire_mux21_9_dataout, wire_mux21_8_dataout, wire_mux21_7_dataout, wire_mux21_6_dataout, wire_mux21_5_dataout, wire_mux21_4_dataout, wire_mux21_3_dataout, wire_mux21_2_dataout, wire_mux21_1_dataout, wire_mux21_0_dataout},
syn_bit = syn_t[5],
syn_e = syndrome[7],
syn_t = {(syn_t[4] | syndrome[6]), (syn_t[3] | syndrome[5]), (syn_t[2] | syndrome[4]), (syn_t[1] | syndrome[3]), (syn_t[0] | syndrome[2]), (syndrome[0] | syndrome[1])},
syndrome = {parity_final_wire[70], parity_07_wire[6], parity_06_wire[30], parity_05_wire[1], parity_04_wire[3], parity_03_wire[8], parity_02_wire[17], parity_01_wire[35]};
endmodule //alt_ddrx_decoder_72_altecc_decoder_e8f
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_ddrx_decoder_72 (
clock,
data,
err_corrected,
err_detected,
err_fatal,
q);
input clock;
input [71:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output [63:0] q;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [63:0] sub_wire3;
wire err_fatal = sub_wire0;
wire err_corrected = sub_wire1;
wire err_detected = sub_wire2;
wire [63:0] q = sub_wire3[63:0];
alt_ddrx_decoder_72_altecc_decoder_e8f alt_ddrx_decoder_72_altecc_decoder_e8f_component (
.clock (clock),
.data (data),
.err_fatal (sub_wire0),
.err_corrected (sub_wire1),
.err_detected (sub_wire2),
.q (sub_wire3));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix"
// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "1"
// Retrieval info: CONSTANT: width_codeword NUMERIC "72"
// Retrieval info: CONSTANT: width_dataword NUMERIC "64"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 72 0 INPUT NODEFVAL "data[71..0]"
// Retrieval info: USED_PORT: err_corrected 0 0 0 0 OUTPUT NODEFVAL "err_corrected"
// Retrieval info: USED_PORT: err_detected 0 0 0 0 OUTPUT NODEFVAL "err_detected"
// Retrieval info: USED_PORT: err_fatal 0 0 0 0 OUTPUT NODEFVAL "err_fatal"
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
// Retrieval info: CONNECT: @data 0 0 72 0 data 0 0 72 0
// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
// Retrieval info: CONNECT: err_fatal 0 0 0 0 @err_fatal 0 0 0 0
// Retrieval info: CONNECT: err_detected 0 0 0 0 @err_detected 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: err_corrected 0 0 0 0 @err_corrected 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_decoder_72.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_decoder_72.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_decoder_72.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_decoder_72.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_decoder_72_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_decoder_72_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
//////////////////////////////////////////////////////////////////////////////
/// Copyright (c) 2014, Ajit Mathew <[email protected]>
/// All rights reserved.
///
// Redistribution and use in source and binary forms, with or without modification,
/// are permitted provided that the following conditions are met:
///
/// * Redistributions of source code must retain the above copyright notice,
/// this list of conditions and the following disclaimer.
/// * Redistributions in binary form must reproduce the above copyright notice,
/// this list of conditions and the following disclaimer in the documentation and/or
/// other materials provided with the distribution.
///
/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
/// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
/// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
/// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
/// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
/// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
/// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
/// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
/// POSSIBILITY OF SUCH DAMAGE.
///
///
/// * http://opensource.org/licenses/MIT
/// * http://copyfree.org/licenses/mit/license.txt
///
//////////////////////////////////////////////////////////////////////////////
module uart
#(
parameter Data_Bits = 8,
StopBits_tick = 16,
DIVISOR = 326, // divider circuit = 50M/(16*baud rate)
DVSR_BIT = 9, // # bits of divider circuit
FIFO_Add_Bit = 4
)
(
input wire clk, reset,
input wire rd_uart, wr_uart, rx,
input wire [7:0] w_data,
output wire tx_empty, rx_empty, tx,
output wire [7:0] r_data
);
wire tck, rx_done_tck, tx_done_tck;
wire tx_full, tx_fifo_not_empty;
wire [7:0] tx_fifo_out, rx_data_out;
assign clkout=clk;
//body
counter #(.M(DIVISOR), .N(DVSR_BIT)) baud_gen_unit
(.clk(clkout), .reset(reset), .q(), .max_tck(tck));
uart_rx #(.DBIT(Data_Bits), .SB_tck(StopBits_tick)) uart_rx_unit
(.clk(clkout), .reset(reset), .rx(rx), .s_tck(tck),
.rx_done_tck(rx_done_tck), .dout(rx_data_out));
fifo #(.B(Data_Bits), .W(FIFO_Add_Bit )) fifo_rx_unit
(.clk(clkout), .reset(reset), .rd(rd_uart),
.wr(rx_done_tck), .w_data(rx_data_out),
.empty(rx_empty), .full(), .r_data(r_data));
fifo #(.B(Data_Bits), .W(FIFO_Add_Bit )) fifo_tx_unit
(.clk(clkout), .reset(reset), .rd(tx_done_tck),
.wr(wr_uart), .w_data(w_data), .empty(tx_empty),
.full(tx_full), .r_data(tx_fifo_out));
uart_tx #(.DBIT(Data_Bits), .SB_tck(StopBits_tick)) uart_tx_unit
(.clk(clkout), .reset(reset), .tx_start(tx_fifo_not_empty),
.s_tck(tck), .din(tx_fifo_out),
.tx_done_tck(tx_done_tck), .tx(tx));
assign tx_fifo_not_empty = ~tx_empty;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:37:00 11/09/2016
// Design Name:
// Module Name: button_painter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module button_painter(
input wire [1:0] row,
input wire [2:0] column,
input wire [3:0] in_row,
output reg [11:0] code
);
wire [4:0] d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, ds, dr, dm, dd, dmod, dsig, di;
reg [4:0] number;
reg [4:0] data;
num_0 n0 (
.in_row({in_row-2'b11}[2:0]),
.out_code(d0)
);
num_1 n1 (
.in_row({in_row-2'b11}[2:0]),
.out_code(d1)
);
num_2 n2 (
.in_row({in_row-2'b11}[2:0]),
.out_code(d2)
);
num_3 n3 (
.in_row({in_row-2'b11}[2:0]),
.out_code(d3)
);
num_4 n4 (
.in_row({in_row-2'b11}[2:0]),
.out_code(d4)
);
num_5 n5 (
.in_row({in_row-2'b11}[2:0]),
.out_code(d5)
);
num_6 n6 (
.in_row({in_row-2'b11}[2:0]),
.out_code(d6)
);
num_7 n7 (
.in_row({in_row-2'b11}[2:0]),
.out_code(d7)
);
num_8 n8 (
.in_row({in_row-2'b11}[2:0]),
.out_code(d8)
);
num_9 n9 (
.in_row({in_row-2'b11}[2:0]),
.out_code(d9)
);
bsuma bsum (
.in_row({in_row-2'b11}[2:0]),
.out_code(ds)
);
bresta bres (
.in_row({in_row-2'b11}[2:0]),
.out_code(dr)
);
bmultip bmul (
.in_row({in_row-2'b11}[2:0]),
.out_code(dm)
);
bdiv bd (
.in_row({in_row-2'b11}[2:0]),
.out_code(dd)
);
bmod bm (
.in_row({in_row-2'b11}[2:0]),
.out_code(dmod)
);
bigual bi (
.in_row({in_row-2'b11}[2:0]),
.out_code(di)
);
bsigno bsig (
.in_row({in_row-2'b11}[2:0]),
.out_code(dsig)
);
always @ *
begin
number = {(row * 6) + column}[4:0];
case (number)
5'b00000: data = d0;
5'b00001: data = d1;
5'b00010: data = d2;
5'b00011: data = d3;
5'b00100: data = d4;
5'b00101: data = d5;
5'b00110: data = d6;
5'b00111: data = d7;
5'b01000: data = d8;
5'b01001: data = d9;
5'b01010: data = ds;
5'b01011: data = dr;
5'b01100: data = dm;
5'b01101: data = dd;
5'b01110: data = dmod;
5'b01111: data = di;
5'b10000: data = dsig;
default: data = 5'b0;
endcase
code = 12'b0;
if((in_row > 2) && (in_row < 11))
code[8:4] = data;
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_drp_cntrl (
// drp interface
drp_clk,
drp_rst,
drp_sel,
drp_wr,
drp_addr,
drp_wdata,
drp_rdata,
drp_ready,
drp_locked,
// processor interface
up_rstn,
up_clk,
up_drp_sel_t,
up_drp_rwn,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_status,
up_drp_locked);
// drp interface
input drp_clk;
input drp_rst;
output drp_sel;
output drp_wr;
output [11:0] drp_addr;
output [15:0] drp_wdata;
input [15:0] drp_rdata;
input drp_ready;
input drp_locked;
// processor interface
input up_rstn;
input up_clk;
input up_drp_sel_t;
input up_drp_rwn;
input [11:0] up_drp_addr;
input [15:0] up_drp_wdata;
output [15:0] up_drp_rdata;
output up_drp_status;
output up_drp_locked;
// internal registers
reg drp_sel_t_m1 = 'd0;
reg drp_sel_t_m2 = 'd0;
reg drp_sel_t_m3 = 'd0;
reg drp_sel = 'd0;
reg drp_wr = 'd0;
reg [11:0] drp_addr = 'd0;
reg [15:0] drp_wdata = 'd0;
reg drp_ready_int = 'd0;
reg [15:0] drp_rdata_int = 'd0;
reg drp_ack_t = 'd0;
reg up_drp_locked_m1 = 'd0;
reg up_drp_locked = 'd0;
reg up_drp_ack_t_m1 = 'd0;
reg up_drp_ack_t_m2 = 'd0;
reg up_drp_ack_t_m3 = 'd0;
reg up_drp_sel_t_d = 'd0;
reg up_drp_status = 'd0;
reg [15:0] up_drp_rdata = 'd0;
// internal signals
wire drp_sel_t_s;
wire up_drp_ack_t_s;
wire up_drp_sel_t_s;
// drp control and status
assign drp_sel_t_s = drp_sel_t_m2 ^ drp_sel_t_m3;
always @(posedge drp_clk) begin
if (drp_rst == 1'b1) begin
drp_sel_t_m1 <= 'd0;
drp_sel_t_m2 <= 'd0;
drp_sel_t_m3 <= 'd0;
end else begin
drp_sel_t_m1 <= up_drp_sel_t;
drp_sel_t_m2 <= drp_sel_t_m1;
drp_sel_t_m3 <= drp_sel_t_m2;
end
end
always @(posedge drp_clk) begin
if (drp_sel_t_s == 1'b1) begin
drp_sel <= 1'b1;
drp_wr <= ~up_drp_rwn;
drp_addr <= up_drp_addr;
drp_wdata <= up_drp_wdata;
end else begin
drp_sel <= 1'b0;
drp_wr <= 1'b0;
drp_addr <= 12'd0;
drp_wdata <= 16'd0;
end
end
always @(posedge drp_clk) begin
drp_ready_int <= drp_ready;
if ((drp_ready_int == 1'b0) && (drp_ready == 1'b1)) begin
drp_rdata_int <= drp_rdata;
drp_ack_t <= ~drp_ack_t;
end
end
// drp status transfer
assign up_drp_ack_t_s = up_drp_ack_t_m3 ^ up_drp_ack_t_m2;
assign up_drp_sel_t_s = up_drp_sel_t ^ up_drp_sel_t_d;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_drp_locked_m1 <= 'd0;
up_drp_locked <= 'd0;
up_drp_ack_t_m1 <= 'd0;
up_drp_ack_t_m2 <= 'd0;
up_drp_ack_t_m3 <= 'd0;
up_drp_sel_t_d <= 'd0;
up_drp_status <= 'd0;
up_drp_rdata <= 'd0;
end else begin
up_drp_locked_m1 <= drp_locked;
up_drp_locked <= up_drp_locked_m1;
up_drp_ack_t_m1 <= drp_ack_t;
up_drp_ack_t_m2 <= up_drp_ack_t_m1;
up_drp_ack_t_m3 <= up_drp_ack_t_m2;
up_drp_sel_t_d <= up_drp_sel_t;
if (up_drp_ack_t_s == 1'b1) begin
up_drp_status <= 1'b0;
end else if (up_drp_sel_t_s == 1'b1) begin
up_drp_status <= 1'b1;
end
if (up_drp_ack_t_s == 1'b1) begin
up_drp_rdata <= drp_rdata_int;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// Three basic tests in here:
// 1. byte must be initialised before any initial or always block
// 2. assignments to (unsigned) bytes with random numbers
// 3. assignments to (unsigned) bytes with random values including X and Z
module ibyte_test;
parameter TRIALS = 100;
parameter MAX = 'h7fff;
reg [15:0] ar; // should it be "reg unsigned [7:0] aw"?
reg [15:0] ar_xz; // same as above here?
reg [15:0] ar_expected; // and here
shortint unsigned bu;
shortint unsigned bu_xz;
integer i;
assign bu = ar;
assign bu_xz = ar_xz;
// all test
initial begin
// time 0 checkings (Section 6.4 of IEEE 1850 LRM)
if (bu !== 16'b0 | bu_xz != 16'b0)
begin
$display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz);
$finish;
end
// random numbers
for (i = 0; i< TRIALS; i = i+1)
begin
#1;
ar = {$random} % MAX;
#1;
if (bu !== ar)
begin
$display ("FAILED - incorrect assigment to byte: %b", bu);
$finish;
end
end
# 1;
// with 'x injections (Section 4.3.2 of IEEE 1850 LRM)
for (i = 0; i< TRIALS; i = i+1)
begin
#1;
ar = {$random} % MAX;
ar_xz = xz_inject (ar);
ar_expected = xz_expected (ar_xz);
#1;
if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0
begin
$display ("FAILED - incorrect assigment to byte (when 'x): %b", bu);
$finish;
end
end
# 1;
$display("PASSED");
end
// this returns X and Z states into bit random positions for a value
function [7:0] xz_inject (input [7:0] value); // should it be "input unsigned [7:0]" instead?
integer i, temp;
begin
temp = {$random} % MAX;
for (i=0; i<16; i=i+1)
begin
if (temp[i] == 1'b1)
begin
temp = $random % MAX;
if (temp <= 0)
value[i] = 1'bx; // 'x noise
else
value[i] = 1'bz; // 'z noise
end
end
xz_inject = value;
end
endfunction
// this function returns bit positions with either X or Z to 0 for an input value
function [15:0] xz_expected (input [15:0] value_xz); // should it be "input unsigned [7:0] instead?
integer i;
begin
for (i=0; i<16; i=i+1)
begin
if (value_xz[i] === 1'bx || value_xz[i] === 1'bz )
value_xz[i] = 1'b0; // forced to zero
end
xz_expected = value_xz;
end
endfunction
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_embedded_workgroup_issuer_fifo #(
parameter unsigned MAX_SIMULTANEOUS_WORKGROUPS = 2, // >0
parameter unsigned MAX_WORKGROUP_SIZE = 2147483648, // >0
parameter unsigned WG_SIZE_BITS = $clog2({1'b0, MAX_WORKGROUP_SIZE} + 1),
parameter unsigned LLID_BITS = (MAX_WORKGROUP_SIZE > 1 ? $clog2(MAX_WORKGROUP_SIZE) : 1),
parameter unsigned WG_ID_BITS = (MAX_SIMULTANEOUS_WORKGROUPS > 1 ? $clog2(MAX_SIMULTANEOUS_WORKGROUPS) : 1)
)
(
input logic clock,
input logic resetn,
// Handshake for item entry into function.
input logic valid_in,
output logic stall_out,
// Handshake with entry basic block
output logic valid_entry,
input logic stall_entry,
// Observe threads exiting the function .
// This is asserted when items are ready to be retired from the workgroup.
input logic valid_exit,
// This is asserted when downstream is not ready to retire an item from
// the workgroup.
input logic stall_exit,
// Need workgroup_size to know when one workgroup ends
// and another begins.
input logic [WG_SIZE_BITS - 1:0] workgroup_size,
// Linearized local id. In range of [0, workgroup_size - 1].
output logic [LLID_BITS - 1:0] linear_local_id_out,
// Hardware work-group id. In range of [0, MAX_SIMULTANEOUS_WORKGROUPS - 1].
output logic [WG_ID_BITS - 1:0] hw_wg_id_out,
// The hardware work-group id of the work-group that is exiting.
input logic [WG_ID_BITS - 1:0] done_hw_wg_id_in,
// Pass though global_id, local_id and group_id.
input logic [31:0] global_id_in[2:0],
input logic [31:0] local_id_in[2:0],
input logic [31:0] group_id_in[2:0],
output logic [31:0] global_id_out[2:0],
output logic [31:0] local_id_out[2:0],
output logic [31:0] group_id_out[2:0]
);
// Entry: 1 cycle latency
// Exit: 1 cycle latency
acl_work_group_limiter #(
.WG_LIMIT(MAX_SIMULTANEOUS_WORKGROUPS),
.KERNEL_WG_LIMIT(MAX_SIMULTANEOUS_WORKGROUPS),
.MAX_WG_SIZE(MAX_WORKGROUP_SIZE),
.WG_FIFO_ORDER(1),
.IMPL("kernel") // this parameter is very important to get the right implementation
)
limiter(
.clock(clock),
.resetn(resetn),
.wg_size(workgroup_size),
.entry_valid_in(valid_in),
.entry_k_wgid(),
.entry_stall_out(stall_out),
.entry_valid_out(valid_entry),
.entry_l_wgid(hw_wg_id_out),
.entry_stall_in(stall_entry),
.exit_valid_in(valid_exit & ~stall_exit),
.exit_l_wgid(done_hw_wg_id_in),
.exit_stall_out(),
.exit_valid_out(),
.exit_stall_in(1'b0)
);
// Pass through ids (global, local, group).
// Match the latency of the work-group limiter, which is one cycle.
always @(posedge clock)
if( ~stall_entry )
begin
global_id_out <= global_id_in;
local_id_out <= local_id_in;
group_id_out <= group_id_in;
end
// local id 3 generator
always @(posedge clock or negedge resetn)
if( ~resetn )
linear_local_id_out <= '0;
else if( valid_entry & ~stall_entry )
begin
if( linear_local_id_out == workgroup_size - 'd1 )
linear_local_id_out <= '0;
else
linear_local_id_out <= linear_local_id_out + 'd1;
end
endmodule
// vim:set filetype=verilog_systemverilog:
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_mask_rows_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_mask_rows_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_mask_rows_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_mask_rows_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
module lsu_bursting_read
(
clk, clk2x, reset, flush, i_nop, o_stall, i_valid, i_address, i_stall, o_valid, o_readdata,
o_active, //Debugging signal
avm_address, avm_read, avm_readdata, avm_waitrequest, avm_byteenable,
avm_readdatavalid,
avm_burstcount,
// Profiling
extra_unaligned_reqs,
req_cache_hit_count
);
/*************
* Parameters *
*************/
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter WIDTH_BYTES=8; // Width of the memory access (bytes)
parameter MWIDTH_BYTES=64; // Width of the global memory bus (bytes)
parameter ALIGNMENT_ABITS=$clog2(WIDTH_BYTES); // Request address alignment (address bits)
parameter DEVICE = "Stratix V"; // DEVICE
parameter BURSTCOUNT_WIDTH=5; // MAX BURST = 2**(BURSTCOUNT_WIDTH-1)
parameter KERNEL_SIDE_MEM_LATENCY=1; // Effective Latency in cycles as seen by the kernel pipeline
parameter MEMORY_SIDE_MEM_LATENCY = 1; // Latency in cycles between LSU and memory
parameter MAX_THREADS=64; // Maximum # of threads to group into a burst request
parameter TIME_OUT=8; // Time out counter max
parameter USECACHING = 0; // Enable internal cache
parameter CACHE_SIZE_N=1024; // Cache depth (width = WIDTH_BYTES)
parameter ACL_PROFILE = 0; // Profiler
parameter HIGH_FMAX = 1; // Add pipeline to io if set to 1
parameter UNALIGNED = 0; // Output word unaligned
/*****************
* Local Parameters *
*****************/
localparam MAX_BURST = 2**(BURSTCOUNT_WIDTH-1);
localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam A_BYTES = 2**ALIGNMENT_ABITS;
localparam WORD_BYTES = (WIDTH_BYTES >= A_BYTES & (UNALIGNED == 0))? WIDTH_BYTES : A_BYTES;
localparam NUM_WORD = MWIDTH_BYTES / WORD_BYTES;
localparam MB_W=$clog2(MWIDTH_BYTES);
localparam OB_W = $clog2(WIDTH_BYTES);
localparam PAGE_ADDR_WIDTH = AWIDTH - MB_W;
localparam OFFSET_WIDTH = $clog2(NUM_WORD);
localparam CACHE_ADDR_W=$clog2(CACHE_SIZE_N);
localparam CACHE_BASE_ADDR_W = AWIDTH-MB_W-CACHE_ADDR_W;
localparam UNALIGNED_DIV_ALIGN = WIDTH_BYTES / A_BYTES;
localparam UNALIGNED_SELECTION_BITS=$clog2(UNALIGNED_DIV_ALIGN);
// Standard global signals
input clk;
input clk2x;
input reset;
input flush;
input i_nop;
// Upstream interface
output logic o_stall;
input i_valid;
input [AWIDTH-1:0] i_address;
// Downstream interface
input i_stall;
output o_valid;
output [WIDTH-1:0] o_readdata;
output o_active;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output avm_read;
input [MWIDTH-1:0] avm_readdata;
input avm_waitrequest;
output [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_readdatavalid;
output [BURSTCOUNT_WIDTH-1:0] avm_burstcount;
// Profiling
output logic extra_unaligned_reqs;
output logic req_cache_hit_count;
// internal signals
logic stall_pre;
wire reg_valid;
wire reg_nop;
wire [AWIDTH-1:0] reg_address;
// registed to help P&R
logic R_valid, R_nop;
wire [AWIDTH-1:0] addr_next_wire;
logic [AWIDTH-1:0] R_addr, R_addr_next, R_addr_next_hold;
// cache status
reg [CACHE_BASE_ADDR_W:0] cache [CACHE_SIZE_N] /* synthesis ramstyle = "M20K" */;
wire [1:0] in_cache_pre;
logic [CACHE_BASE_ADDR_W-1:0] cached_tag [2];
wire [CACHE_BASE_ADDR_W-1:0] R_tag [2];
wire [CACHE_ADDR_W-1:0] rd_c_index [2];
wire [CACHE_ADDR_W-1:0] wr_c_index;
logic cached_tag_valid [2];
wire tag_match [2];
wire consecutive;
reg cache_ready;
logic [1:0] in_cache;
wire [MB_W-1:0] byte_offset;
reg include_2nd_part;
logic update_cache;
logic [CACHE_BASE_ADDR_W-1:0] new_tag;
logic issue_2nd_word;
reg issue_2nd_hold;
logic need_2_page;
wire stall_int;
wire need_2_cc;
wire [UNALIGNED_SELECTION_BITS-1:0] shift;
logic [AWIDTH-1:0] lsu_i_address;
reg p_valid;
reg [AWIDTH-1:0] p_addr;
reg [1:0] R_consecutive;
reg [63:0] non_align_hit_cache;
// coalesced addr
wire [BURSTCOUNT_WIDTH-1:0]c_burstcount;
wire [PAGE_ADDR_WIDTH-1:0] c_page_addr;
wire c_req_valid;
wire c_new_page;
logic [OFFSET_WIDTH-1 : 0] p_offset, c_word_offset;
logic p_offset_valid;
reg [CACHE_ADDR_W-1:0] R_cache_addr;
// fifo
reg fifo_din_en;
reg [1:0] fi_in_cache;
reg [CACHE_ADDR_W-1:0] fi_cached_addr;
reg [UNALIGNED_SELECTION_BITS-1:0] fi_shift;
reg fi_second, fi_2nd_valid;
reg [UNALIGNED_SELECTION_BITS-1:0] R_shift;
reg [MB_W-1:0] fi_byte_offset;
wire p_ae;
generate
if(HIGH_FMAX) begin: GEN_PIPE_INPUT
acl_io_pipeline #(
.WIDTH(1+AWIDTH)
) in_pipeline (
.clk(clk),
.reset(reset),
.i_stall(stall_pre),
.i_valid(i_valid),
.i_data({i_nop, i_address}),
.o_stall(o_stall),
.o_valid(reg_valid),
.o_data({reg_nop, reg_address})
);
end
else begin : GEN_FAST_INPUT
assign {reg_valid, reg_nop, reg_address} = {i_valid, i_nop, i_address};
end
if(USECACHING) begin : GEN_ENABLE_CACHE
reg R_flush;
reg [CACHE_ADDR_W:0] flush_cnt;
reg cache_status_ready;
assign rd_c_index[0] = R_addr[CACHE_ADDR_W-1+MB_W:MB_W];
assign rd_c_index[1] = R_addr_next[CACHE_ADDR_W-1+MB_W:MB_W];
assign {cached_tag_valid[0], cached_tag[0]} = cache[rd_c_index[0]];
assign {cached_tag_valid[1], cached_tag[1]} = cache[rd_c_index[1]];
assign wr_c_index = lsu_i_address[CACHE_ADDR_W-1+MB_W:MB_W];
assign R_tag[0] = R_addr[AWIDTH-1:MB_W+CACHE_ADDR_W];
assign R_tag[1] = R_addr_next[AWIDTH-1:MB_W+CACHE_ADDR_W];
assign tag_match[0] = cached_tag[0] == R_tag[0] & cached_tag_valid[0] === 1'b1;
assign tag_match[1] = cached_tag[1] == R_tag[1] & cached_tag_valid[1] === 1'b1;
assign in_cache_pre[0] = tag_match[0] & !issue_2nd_word & cache_ready;
assign in_cache_pre[1] = tag_match[1] & !issue_2nd_word & cache_ready;
assign new_tag = lsu_i_address[AWIDTH-1:MB_W+CACHE_ADDR_W];
assign update_cache = R_valid & !R_nop | issue_2nd_word;
always @(posedge clk or posedge reset) begin
if(reset) cache_status_ready <= 1'b0;
else cache_status_ready <= flush_cnt[CACHE_ADDR_W];
end
always @ (posedge clk) begin
R_flush <= flush;
if(flush & !R_flush) flush_cnt <= '0;
else if(!flush_cnt[CACHE_ADDR_W]) flush_cnt <= flush_cnt + 1'b1;
cache_ready <= flush_cnt[CACHE_ADDR_W];
if(!flush_cnt[CACHE_ADDR_W]) cache[flush_cnt] <= '0;
else if(update_cache) cache[wr_c_index] <= {1'b1, new_tag};
in_cache[0] <= R_valid & (in_cache_pre[0] | R_nop) & !issue_2nd_word;
in_cache[1] <= UNALIGNED? R_valid & (in_cache_pre[1] | R_nop) & !issue_2nd_word & need_2_page : 1'b0;
include_2nd_part <= issue_2nd_word | in_cache_pre[1] & need_2_page;
p_valid <= issue_2nd_word | R_valid & !in_cache_pre[0] & !R_nop; // not include nop
p_offset_valid <= issue_2nd_word | R_valid;
p_addr <= lsu_i_address;
R_cache_addr <= lsu_i_address[MB_W+CACHE_ADDR_W-1:MB_W];
end
if(OFFSET_WIDTH > 0) begin
always @ (posedge clk) begin
p_offset <= R_addr[MB_W-1:MB_W-OFFSET_WIDTH];
end
end
if(ACL_PROFILE == 1) begin
assign req_cache_hit_count = ((|fi_in_cache) & fifo_din_en);
end
else
begin
assign req_cache_hit_count = 1'b0;
end
end // end GEN_ENABLE_CACHE
else begin : GEN_DISABLE_CACHE
assign req_cache_hit_count = 1'b0;
assign in_cache_pre = 2'b0;
assign in_cache = 2'b0;
assign include_2nd_part = issue_2nd_word;
assign p_valid = issue_2nd_word | R_valid & !R_nop; // not include nop
assign p_offset_valid = issue_2nd_word | R_valid;
assign p_addr = lsu_i_address;
if(OFFSET_WIDTH > 0) begin
assign p_offset = R_addr[MB_W-1:MB_W-OFFSET_WIDTH];
end
end // end GEN_DISABLE_CACHE
if (UNALIGNED) begin : GEN_UNALIGN
assign addr_next_wire[AWIDTH-1:AWIDTH-PAGE_ADDR_WIDTH] = reg_address[AWIDTH-1:AWIDTH-PAGE_ADDR_WIDTH]+1'b1;
assign addr_next_wire[AWIDTH-PAGE_ADDR_WIDTH-1:0] = '0;
// Look at the higher bits to determine how much we need to shift the two aligned accesses
wire [UNALIGNED_SELECTION_BITS-1:0] temp = NUM_WORD - R_addr[AWIDTH-1:ALIGNMENT_ABITS];
assign shift = UNALIGNED_DIV_ALIGN - temp;
assign consecutive = reg_nop | reg_address[AWIDTH-1:AWIDTH-PAGE_ADDR_WIDTH] == R_addr_next[AWIDTH-1:AWIDTH-PAGE_ADDR_WIDTH];
// When do we need to issue the 2nd word ?
// The previous address needed a 2nd page and
// [1] the current requested address isn't in the (previous+1)th page and
// [2] The second page is not in the cache
assign need_2_cc = need_2_page & !in_cache_pre[1] & R_valid & (!issue_2nd_word | R_consecutive[0]); // need 2 clock cycles to combine segments from 2 pages
// simulation only
assign byte_offset = stall_pre? R_addr[MB_W-1:0] : reg_address[MB_W-1:0];
always @(posedge clk or posedge reset) begin
if(reset) begin
issue_2nd_word <= 1'b0;
R_consecutive <= 'x;
stall_pre <= 1'b0;
issue_2nd_hold <= 'x;
end
else begin
issue_2nd_word <= need_2_cc;
if(!stall_pre | issue_2nd_word) issue_2nd_hold <= need_2_cc;
R_consecutive[0] <= reg_valid & !stall_int & consecutive & need_2_cc;
R_consecutive[1] <= R_consecutive[0];
stall_pre <= (stall_int | need_2_cc & reg_valid & !consecutive);
end
end
always @(posedge clk) begin
if(reg_valid & !stall_pre) need_2_page <= !reg_nop & (reg_address[MB_W-1:0] + WIDTH_BYTES) > MWIDTH_BYTES;
if(reg_valid & !stall_pre & !reg_nop) begin
R_addr <= reg_address;
R_addr_next <= addr_next_wire;
end
R_addr_next_hold <= R_addr_next;
if(!issue_2nd_word | !stall_pre) begin
R_valid <= reg_valid & !stall_pre;
R_nop <= reg_nop;
end
end
if(ACL_PROFILE == 1) begin
assign extra_unaligned_reqs = need_2_cc & reg_valid & !consecutive;
always @(posedge clk or posedge reset) begin
if(reset) begin
non_align_hit_cache <= '0;
end
else begin
non_align_hit_cache <= non_align_hit_cache + (need_2_page & in_cache_pre[1] & R_valid & (!issue_2nd_word | R_consecutive[0]) & reg_valid & !consecutive);
end
end
end // end ACL_PROFILE == 1
end // end GEN_UNALIGN
else begin : GEN_ALIGN
assign issue_2nd_word = 1'b0;
assign need_2_page = 1'b0;
assign R_addr = reg_address;
assign R_valid = reg_valid & !stall_int;
assign R_nop = reg_nop;
assign stall_pre = stall_int;
end // end GEN_ALIGN
endgenerate
assign lsu_i_address = issue_2nd_word ? R_addr_next_hold : R_addr;
always @(posedge clk) begin
c_word_offset <= p_offset;
R_shift <= need_2_page? shift : '0;
fifo_din_en <= (|in_cache) | p_offset_valid;
{fi_in_cache, fi_cached_addr, fi_second} <= {in_cache, R_cache_addr, include_2nd_part};
if(!include_2nd_part) fi_byte_offset <= p_addr[MB_W-1:0];
fi_shift <= USECACHING? R_shift : (need_2_page? shift : '0);
fi_2nd_valid <= USECACHING? R_consecutive[1] : R_consecutive[0];
end
acl_stall_free_coalescer #(
.AW(AWIDTH),
.PAGE_AW(PAGE_ADDR_WIDTH),
.MAX_BURST(MAX_BURST),
.TIME_OUT(TIME_OUT),
.CACHE_LAST(USECACHING),
.MAX_THREAD(MAX_THREADS),
.DISABLE_COALESCE(0)
) coalescer(
.clk(clk),
.reset(reset),
.i_valid(p_valid),
.i_addr(p_addr),
.i_empty(p_ae),
.o_page_addr(c_page_addr),
.o_page_addr_valid(c_req_valid),
.o_num_burst(c_burstcount),
.o_new_page(c_new_page)
);
lsu_bursting_pipelined_read #(
.INPUT_AW(PAGE_ADDR_WIDTH),
.AWIDTH(AWIDTH),
.WIDTH(WIDTH),
.MWIDTH(MWIDTH),
.MEMORY_SIDE_MEM_LATENCY(MEMORY_SIDE_MEM_LATENCY),
.DEVICE(DEVICE),
.CACHE_SIZE_N(CACHE_SIZE_N),
.USECACHING(USECACHING),
.UNALIGNED(UNALIGNED),
.UNALIGNED_SHIFT_WIDTH(UNALIGNED_SELECTION_BITS),
.MAX_BURST(MAX_BURST),
.INCLUDE_BYTE_OFFSET(0), // sim-only
.ALIGNMENT_ABITS(ALIGNMENT_ABITS)
) pipelined_read(
.clk (clk),
.reset (reset),
.i_address (c_page_addr),
.i_addr_valid (c_req_valid),
.i_burst_count (c_burstcount),
.i_new_page (c_new_page),
.i_word_offset (c_word_offset),
.i_byte_offset (fi_byte_offset),
.i_in_cache (fi_in_cache),
.i_cache_addr (fi_cached_addr),
.i_shift (fi_shift),
.i_second (fi_second),
.i_2nd_valid (fi_2nd_valid), // has two segments' info in one cc
.i_word_offset_valid(fifo_din_en),
.i_stall (i_stall),
.o_ae (p_ae),
.o_empty (p_empty),
.o_readdata (o_readdata),
.o_valid (o_valid),
.o_stall (stall_int),
.avm_address (avm_address),
.avm_read (avm_read),
.avm_readdata (avm_readdata),
.avm_waitrequest (avm_waitrequest),
.avm_byteenable (avm_byteenable),
.avm_readdatavalid(avm_readdatavalid),
.avm_burstcount (avm_burstcount)
);
endmodule
module acl_io_pipeline #(
parameter WIDTH = 1
)(
input clk,
input reset,
input i_stall,
input i_valid,
input [WIDTH-1:0] i_data,
output o_stall,
output reg o_valid,
output reg [WIDTH-1:0] o_data
);
reg R_valid;
assign o_stall = i_stall & R_valid;
always@(posedge clk) begin
if(!o_stall) {o_valid, o_data} <= {i_valid, i_data};
end
always@(posedge clk or posedge reset)begin
if(reset) R_valid <= 1'b0;
else if(!o_stall) R_valid <= i_valid;
end
endmodule
module lsu_bursting_pipelined_read
(
clk, reset,
i_in_cache,
i_cache_addr,
i_addr_valid,
i_address,
i_burst_count,
i_word_offset,
i_byte_offset,
i_shift,
i_second,
i_2nd_valid,
i_word_offset_valid,
i_new_page,
o_readdata,
o_valid,
i_stall,
o_stall,
o_empty,
o_ae,
avm_address,
avm_read,
avm_readdata,
avm_waitrequest,
avm_byteenable,
avm_burstcount,
avm_readdatavalid
);
parameter INPUT_AW = 32;
parameter AWIDTH=32;
parameter WIDTH=32;
parameter MWIDTH=512;
parameter MAX_BURST = 16;
parameter ALIGNMENT_ABITS=2;
parameter DEVICE = "Stratix V";
parameter MEMORY_SIDE_MEM_LATENCY=160;
parameter USECACHING = 0;
parameter CACHE_SIZE_N = 1024;
parameter UNALIGNED = 0;
parameter UNALIGNED_SHIFT_WIDTH = 0;
parameter INCLUDE_BYTE_OFFSET = 0; // testing purpose
localparam ALIGNMENT_WIDTH = 2**ALIGNMENT_ABITS * 8;
localparam BYTE_SELECT_BITS=$clog2(MWIDTH/8);
localparam WORD_WIDTH = (WIDTH >= ALIGNMENT_WIDTH & (UNALIGNED == 0))? WIDTH : ALIGNMENT_WIDTH;
localparam NUM_WORD = MWIDTH / WORD_WIDTH;
localparam OFFSET_WIDTH = (NUM_WORD==1)? 1 : $clog2(NUM_WORD);
localparam WIDE_FIFO_DEPTH = (MEMORY_SIDE_MEM_LATENCY < 256)? 256 : MEMORY_SIDE_MEM_LATENCY;
localparam OFFSET_FIFO_DEPTH = (MEMORY_SIDE_MEM_LATENCY <= 246)? 256 : MEMORY_SIDE_MEM_LATENCY + 10;
localparam REQUEST_FIFO_DEPTH = OFFSET_FIFO_DEPTH;
localparam WIDE_FIFO_DEPTH_THRESH = MEMORY_SIDE_MEM_LATENCY;
localparam WIDE_FIFO_AW = $clog2(WIDE_FIFO_DEPTH);
localparam BURST_CNT_WIDTH = (MAX_BURST == 1)? 1 : $clog2(MAX_BURST + 1);
localparam REQUEST_FIFO_AW = $clog2(REQUEST_FIFO_DEPTH);
localparam OFFSET_FIFO_AW = $clog2(OFFSET_FIFO_DEPTH);
localparam REQUEST_FIFO_WIDTH = INPUT_AW + BURST_CNT_WIDTH;
localparam CACHE_SIZE_LOG2N=$clog2(CACHE_SIZE_N);
localparam CACHE_ADDR_W=$clog2(CACHE_SIZE_N);
localparam OFFSET_FIFO_WIDTH = 1 + ((NUM_WORD > 1)? OFFSET_WIDTH : 0) + (USECACHING? 1 + CACHE_ADDR_W : 0) + (UNALIGNED? UNALIGNED_SHIFT_WIDTH + 3 : 0) + (INCLUDE_BYTE_OFFSET? BYTE_SELECT_BITS : 0);
// I/O
input clk, reset;
input [UNALIGNED:0] i_in_cache;
input [CACHE_ADDR_W-1:0] i_cache_addr;
input [INPUT_AW-1:0] i_address;
input [BURST_CNT_WIDTH-1:0] i_burst_count;
input [OFFSET_WIDTH-1:0] i_word_offset;
input [BYTE_SELECT_BITS-1:0] i_byte_offset; // simulation
input [UNALIGNED_SHIFT_WIDTH-1:0] i_shift; // used only when UNALIGNED = 1
input i_second; // used only when UNALIGNED = 1
input i_2nd_valid; // used only when UNALIGNED = 1
input i_word_offset_valid;
input i_new_page;
input i_addr_valid;
input i_stall;
output logic [WIDTH-1:0] o_readdata;
output logic o_valid;
output reg o_stall;
output reg o_empty;
output o_ae;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output reg avm_read;
input [MWIDTH-1:0] avm_readdata;
input avm_waitrequest;
output [MWIDTH/8-1:0] avm_byteenable;
input avm_readdatavalid;
output [BURST_CNT_WIDTH-1:0] avm_burstcount;
// offset fifo
wire [OFFSET_FIFO_WIDTH-1:0] offset_fifo_din;
wire [OFFSET_FIFO_WIDTH-1:0] offset_fifo_dout;
// req FIFO
wire rd_req_en;
wire req_fifo_ae, req_fifo_af, req_overflow, offset_overflow, rd_req_empty; // FIFO status
// end req FIFO
// output FIFO
wire rd_data_fifo;
reg R_rd_data;
wire rd_data_empty;
wire rd_offset;
wire offset_fifo_empty;
wire offset_af;
wire [UNALIGNED:0] d_in_cache;
wire rd_next_page;
wire [CACHE_ADDR_W-1:0] d_cache_addr;
wire [BYTE_SELECT_BITS-1:0] d_byte_offset; // for simulation
reg R_in_cache;
wire d_second, d_2nd_valid;
wire unalign_stall_offset, unalign_stall_data;
wire [UNALIGNED_SHIFT_WIDTH-1:0] d_shift;
wire [OFFSET_WIDTH-1 : 0] d_offset;
reg [OFFSET_WIDTH-1 : 0] R_offset;
reg [MWIDTH-1:0] R_avm_rd_data;
wire [MWIDTH-1:0] rd_data;
// end output FIFO
assign avm_address[AWIDTH - INPUT_AW - 1 : 0] = 0;
assign avm_byteenable = {(MWIDTH/8){1'b1}};
assign o_ae = req_fifo_ae;
assign rd_req_en = !avm_read | !avm_waitrequest;
always @(posedge clk or posedge reset) begin
if(reset) begin
o_empty = 1'b0;
avm_read <= 1'b0;
o_stall <= 1'b0;
end
else begin
o_empty <= rd_req_empty;
o_stall <= offset_af;
if(rd_req_en) avm_read <= !rd_req_empty;
end
end
generate
if(NUM_WORD > 1) begin : GEN_WORD_OFFSET_FIFO
scfifo #(
.add_ram_output_register ( "ON"),
.intended_device_family ( DEVICE),
.lpm_numwords (OFFSET_FIFO_DEPTH),
.lpm_showahead ( "OFF"),
.lpm_type ( "scfifo"),
.lpm_width (OFFSET_FIFO_WIDTH),
.lpm_widthu (OFFSET_FIFO_AW),
.overflow_checking ( "OFF"),
.underflow_checking ( "ON"),
.use_eab ( "ON"),
.almost_full_value(OFFSET_FIFO_DEPTH - 10)
) offset_fifo (
.clock (clk),
.data (offset_fifo_din),
.wrreq (i_word_offset_valid),
.rdreq (rd_offset),
.usedw (offset_flv),
.empty (offset_fifo_empty),
.full (offset_overflow),
.q (offset_fifo_dout),
.almost_empty (),
.almost_full (offset_af),
.aclr (reset)
);
end
else begin : GEN_SINGLE_WORD_RD_NEXT
scfifo #(
.add_ram_output_register ( "ON"),
.intended_device_family ( DEVICE),
.lpm_numwords (OFFSET_FIFO_DEPTH),
.lpm_showahead ( "OFF"),
.lpm_type ( "scfifo"),
.lpm_width (OFFSET_FIFO_WIDTH),
.lpm_widthu (OFFSET_FIFO_AW),
.overflow_checking ( "OFF"),
.underflow_checking ( "ON"),
.use_eab ( "OFF"), // not instantiate block ram
.almost_full_value(OFFSET_FIFO_DEPTH - 10)
) offset_fifo (
.clock (clk),
.data (offset_fifo_din),
.wrreq (i_word_offset_valid),
.rdreq (rd_offset),
.usedw (offset_flv),
.empty (offset_fifo_empty),
.full (offset_overflow),
.q (offset_fifo_dout),
.almost_empty (),
.almost_full (offset_af),
.aclr (reset)
);
end
endgenerate
scfifo #(
.add_ram_output_register ( "ON"),
.intended_device_family ( DEVICE),
.lpm_numwords (REQUEST_FIFO_DEPTH),
.lpm_showahead ( "OFF"),
.lpm_type ( "scfifo"),
.lpm_width (REQUEST_FIFO_WIDTH),
.lpm_widthu (REQUEST_FIFO_AW),
.overflow_checking ( "OFF"),
.underflow_checking ( "ON"),
.use_eab ( "ON"),
.almost_full_value(20),
.almost_empty_value(3)
) rd_request_fifo (
.clock (clk),
.data ({i_address, i_burst_count}),
.wrreq (i_addr_valid),
.rdreq (rd_req_en),
.usedw (),
.empty (rd_req_empty),
.full (req_overflow),
.q ({avm_address[AWIDTH - 1: AWIDTH - INPUT_AW], avm_burstcount}),
.almost_empty (req_fifo_ae),
.almost_full (req_fifo_af),
.aclr (reset)
);
/*------------------------------
Generate output data
--------------------------------*/
reg offset_valid;
reg [1:0] o_valid_pre;
wire rd_next_page_en, downstream_stall, wait_data, offset_stall, data_stall, valid_hold;
generate
if(USECACHING) begin : ENABLE_CACHE
reg [MWIDTH-1:0] cache [CACHE_SIZE_N] /* synthesis ramstyle = "no_rw_check, M20K" */;
logic [MWIDTH-1:0] reused_data[2] ;
reg [CACHE_ADDR_W-1:0] R_cache_addr, R_cache_next;
if(NUM_WORD == 1) begin
assign offset_fifo_din[OFFSET_FIFO_WIDTH-1:0] = {i_2nd_valid, i_shift, i_second, i_cache_addr, i_in_cache, i_new_page};
assign {d_2nd_valid, d_shift, d_second, d_cache_addr, d_in_cache, rd_next_page} = offset_fifo_dout[OFFSET_FIFO_WIDTH-1:0];
end
else begin
assign offset_fifo_din[OFFSET_FIFO_WIDTH-1:0] = {i_byte_offset, i_2nd_valid, i_shift, i_second, i_word_offset, i_cache_addr, i_in_cache, i_new_page};
assign {d_byte_offset, d_2nd_valid, d_shift, d_second, d_offset, d_cache_addr, d_in_cache, rd_next_page} = offset_fifo_dout[OFFSET_FIFO_WIDTH-1:0];
end
if(UNALIGNED) begin : GEN_UNALIGNED
wire need_2nd_page;
reg [UNALIGNED_SHIFT_WIDTH-1:0] R_shift [3];
reg hold_dout;
reg R_second;
reg R_need_2nd_page;
reg [WIDTH*2-ALIGNMENT_WIDTH-1:0] data_int;
reg [WIDTH-1:0] R_o_readdata;
reg [1:0] R_2nd_valid;
reg second_part_in_cache;
wire [WIDTH-1:0] c0_data_h, rd_data_h, c0_data_mux, rd_data_mux;
wire [WIDTH-ALIGNMENT_WIDTH-1:0] c1_data_l, rd_data_l;
wire get_new_offset, offset_backpressure_stall ;
wire [CACHE_ADDR_W-1:0] caddr_next;
wire [1:0] rw_wire;
reg [1:0] rw;
reg [WIDTH-ALIGNMENT_WIDTH-1:0] R_c1_data_l;
assign need_2nd_page = |d_shift;
assign valid_hold = |o_valid_pre;
assign rw_wire[0] = d_cache_addr == R_cache_addr & R_rd_data;
assign rw_wire[1] = caddr_next == R_cache_addr & R_rd_data;
assign c0_data_h = rw[0]? rd_data[MWIDTH-1:MWIDTH-WIDTH] : reused_data[0][MWIDTH-1:MWIDTH-WIDTH];
assign c1_data_l = rw[1]? R_c1_data_l : reused_data[1][WIDTH-ALIGNMENT_WIDTH-1:0];
assign rd_data_h = rd_data[MWIDTH-1:MWIDTH-WIDTH];
assign rd_data_l = rd_data[WIDTH-ALIGNMENT_WIDTH-1:0];
assign c0_data_mux = rw[0]? rd_data >> R_offset*ALIGNMENT_WIDTH : reused_data[0] >> R_offset*ALIGNMENT_WIDTH ;
assign rd_data_mux = rd_data >> R_offset*ALIGNMENT_WIDTH;
assign caddr_next = d_cache_addr+1;
assign unalign_stall_offset = d_2nd_valid & !offset_backpressure_stall & !R_2nd_valid[0]; //it is a one-cc pulse
assign unalign_stall_data = R_2nd_valid[0];
assign get_new_offset = rd_offset | unalign_stall_offset;
assign offset_backpressure_stall = wait_data | downstream_stall & offset_valid;
assign offset_stall = offset_backpressure_stall | unalign_stall_offset;
assign data_stall = downstream_stall | unalign_stall_data;
assign wait_data = rd_next_page_en & rd_data_empty & !R_2nd_valid[0];
assign o_readdata = hold_dout? R_o_readdata : data_int[R_shift[2]*ALIGNMENT_WIDTH +: WIDTH];
always@(posedge clk or posedge reset)begin
if(reset) begin
o_valid_pre <= 2'b0;
o_valid <= 1'b0;
end
else begin
o_valid_pre[0] <= offset_valid & get_new_offset & (!need_2nd_page | !R_2nd_valid[0] & d_second);
if(i_stall & o_valid & o_valid_pre[0]) o_valid_pre[1] <= 1'b1;
else if(!i_stall) o_valid_pre[1] <= 1'b0;
if(o_valid_pre[0]) o_valid <= 1'b1;
else if(!i_stall) o_valid <= valid_hold;
end
end
always @(posedge clk) begin
if(R_rd_data) cache[R_cache_addr] <= rd_data;
if(get_new_offset) begin
{R_in_cache, R_offset, R_shift[0], R_second} <= {|d_in_cache, d_offset, d_shift, d_second};
R_cache_addr <= d_cache_addr;
R_cache_next <= caddr_next;
R_shift[1] <= R_shift[0];
R_need_2nd_page <= need_2nd_page;
second_part_in_cache <= !d_in_cache[0] & d_in_cache[1];
R_2nd_valid[1] <= R_2nd_valid[0];
`ifdef SIM_ONLY
if(d_in_cache[0]) reused_data[0] <= rw_wire[0]? 'x : cache[d_cache_addr];
reused_data[1] <= rw_wire[1]? 'x : cache[caddr_next];
`else
if(d_in_cache[0]) reused_data[0] <= cache[d_cache_addr];
reused_data[1] <= cache[caddr_next];
`endif
if(d_in_cache[1]) R_c1_data_l <= rd_data[WIDTH-ALIGNMENT_WIDTH-1:0];
end
// work-around to deal with read-during-write
if(!downstream_stall & (|d_in_cache)) rw <= rw_wire & d_in_cache;
if(!offset_backpressure_stall) R_2nd_valid[0] <= d_2nd_valid & !R_2nd_valid[0];
R_o_readdata <= o_readdata;
hold_dout <= i_stall & o_valid;
if(R_in_cache) begin
data_int[WIDTH*2-ALIGNMENT_WIDTH-1:WIDTH] <= c1_data_l;
data_int[WIDTH-1:0] <= second_part_in_cache? rd_data_h : R_need_2nd_page? c0_data_h : c0_data_mux;
end
else begin
if(R_second) data_int[WIDTH*2-ALIGNMENT_WIDTH-1:WIDTH] <= rd_data_l;
if(!R_second | R_2nd_valid[1]) data_int[WIDTH-1:0] <= R_need_2nd_page? rd_data_h : rd_data_mux;
end
R_shift[2] <= (R_in_cache | !R_second | R_2nd_valid[1])? R_shift[0] : R_shift[1];
end
end // end UNALIGNED
else begin : GEN_ALIGNED
reg [MWIDTH-1:0] cache [CACHE_SIZE_N] /* synthesis ramstyle = "no_rw_check, M20K" */;
assign valid_hold = o_valid;
assign offset_stall = wait_data | downstream_stall & offset_valid;
assign data_stall = downstream_stall;
assign wait_data = rd_next_page_en & rd_data_empty; // there is a valid offset, need data to demux
if(NUM_WORD == 1) assign o_readdata = R_in_cache? reused_data[0][WIDTH-1:0] : rd_data[WIDTH-1:0];
else assign o_readdata = R_in_cache? reused_data[0] >> R_offset*WORD_WIDTH: rd_data >> R_offset*WORD_WIDTH;
always @(posedge clk) begin
if(rd_offset) begin
R_cache_addr <= d_cache_addr;
R_in_cache <= d_in_cache & !(R_rd_data & R_cache_addr == d_cache_addr);
R_offset <= d_offset;
// registered cache input and output to infer megafunction RAM
`ifdef SIM_ONLY // for simulation accuracy
reused_data[0] <= (d_cache_addr == R_cache_addr & R_rd_data)? 'x : cache[d_cache_addr]; // read during write
`else
reused_data[0] <= cache[d_cache_addr];
`endif
end
else if(R_rd_data & R_cache_addr == d_cache_addr) R_in_cache <= 1'b0; // read during write
if(R_rd_data) cache[R_cache_addr] <= rd_data; // update cache
end
always@(posedge clk or posedge reset)begin
if(reset) o_valid <= 1'b0;
else if(!i_stall | !o_valid) o_valid <= rd_offset & offset_valid;
end
end // end ALIGNED
end // end USECACHING
else begin : DISABLE_CACHE
if(NUM_WORD == 1) begin
assign offset_fifo_din[OFFSET_FIFO_WIDTH-1:0] = {i_2nd_valid, i_shift, i_second, i_new_page};
assign {d_2nd_valid, d_shift, d_second, rd_next_page} = offset_fifo_dout[OFFSET_FIFO_WIDTH-1:0];
end
else begin
assign offset_fifo_din[OFFSET_FIFO_WIDTH-1:0] = {i_byte_offset, i_2nd_valid, i_shift, i_second, i_word_offset, i_new_page};
assign {d_byte_offset, d_2nd_valid, d_shift, d_second, d_offset, rd_next_page} = offset_fifo_dout[OFFSET_FIFO_WIDTH-1:0];
end
if(UNALIGNED) begin : GEN_UNALIGNED
wire need_2nd_page;
reg [UNALIGNED_SHIFT_WIDTH-1:0] R_shift [3];
reg hold_dout;
reg R_second;
reg R_need_2nd_page;
reg [WIDTH*2-ALIGNMENT_WIDTH-1:0] data_int;
reg [WIDTH-1:0] R_o_readdata;
reg [1:0] R_2nd_valid;
wire [WIDTH-1:0] rd_data_h, rd_data_mux;
wire [WIDTH-ALIGNMENT_WIDTH-1:0] rd_data_l;
wire get_new_offset, offset_backpressure_stall;
assign need_2nd_page = |d_shift;
assign valid_hold = |o_valid_pre;
assign rd_data_h = rd_data[MWIDTH-1:MWIDTH-WIDTH];
assign rd_data_l = rd_data[WIDTH-ALIGNMENT_WIDTH-1:0];
assign rd_data_mux = rd_data >> R_offset*ALIGNMENT_WIDTH;
assign unalign_stall_offset = d_2nd_valid & !offset_backpressure_stall & !R_2nd_valid[0]; //it is a one-cc pulse
assign unalign_stall_data = R_2nd_valid[0];
assign get_new_offset = rd_offset | unalign_stall_offset;
assign offset_backpressure_stall = wait_data | downstream_stall & offset_valid;
assign offset_stall = offset_backpressure_stall | unalign_stall_offset;
assign data_stall = downstream_stall | unalign_stall_data;
assign wait_data = rd_next_page_en & rd_data_empty & !R_2nd_valid[0];
assign o_readdata = hold_dout? R_o_readdata : data_int >> R_shift[2]*ALIGNMENT_WIDTH;
always@(posedge clk or posedge reset)begin
if(reset) begin
o_valid_pre <= 2'b0;
o_valid <= 1'b0;
end
else begin
o_valid_pre[0] <= offset_valid & get_new_offset & (!need_2nd_page | !R_2nd_valid[0] & d_second);
if(i_stall & o_valid & o_valid_pre[0]) o_valid_pre[1] <= 1'b1;
else if(!i_stall) o_valid_pre[1] <= 1'b0;
if(o_valid_pre[0]) o_valid <= 1'b1;
else if(!i_stall) o_valid <= valid_hold;
end
end
always @(posedge clk) begin
if(get_new_offset) begin
{R_offset, R_shift[0], R_second} <= {d_offset, d_shift, d_second};
R_shift[1] <= R_shift[0];
R_need_2nd_page <= need_2nd_page;
R_2nd_valid[1] <= R_2nd_valid[0];
end
if(!offset_backpressure_stall) R_2nd_valid[0] <= d_2nd_valid & !R_2nd_valid[0];
R_o_readdata <= o_readdata;
hold_dout <= i_stall & o_valid;
if(R_second) data_int[WIDTH*2-ALIGNMENT_WIDTH-1:WIDTH] <= rd_data_l;
if(!R_second | R_2nd_valid[1]) data_int[WIDTH-1:0] <= R_need_2nd_page? rd_data_h : rd_data_mux;
R_shift[2] <= (!R_second | R_2nd_valid[1])? R_shift[0] : R_shift[1];
end
end // end GEN_UNALIGNED
else begin : GEN_ALIGNED
assign valid_hold = o_valid;
assign offset_stall = wait_data | downstream_stall & offset_valid;
assign data_stall = downstream_stall;
assign wait_data = rd_next_page_en & rd_data_empty; // there is a valid offset, need data to demux
if(NUM_WORD == 1) assign o_readdata = rd_data[WIDTH-1:0];
else assign o_readdata = rd_data >> R_offset*WORD_WIDTH;
always @(posedge clk) begin
if(rd_offset) R_offset <= d_offset;
end
always@(posedge clk or posedge reset)begin
if(reset) o_valid <= 1'b0;
else if(!i_stall | !o_valid) o_valid <= rd_offset & offset_valid;
end
end // end GEN_ALIGNED
end // end DISABLE_CACHE
endgenerate
assign downstream_stall = i_stall & valid_hold;
assign rd_next_page_en = offset_valid & rd_next_page;
assign rd_offset = !offset_stall;
assign rd_data_fifo = rd_next_page_en & !data_stall;
always@(posedge clk or posedge reset)begin
if(reset) begin
offset_valid <= 1'b0;
R_rd_data <= 1'b0;
end
else begin
if(rd_offset) offset_valid <= !offset_fifo_empty;
R_rd_data <= rd_data_fifo & !rd_data_empty;
end
end
scfifo #(
.add_ram_output_register ( "ON"),
.intended_device_family ( DEVICE),
.lpm_numwords (WIDE_FIFO_DEPTH),
.almost_full_value(WIDE_FIFO_DEPTH_THRESH),
.lpm_showahead ( "OFF"),
.lpm_type ( "scfifo"),
.lpm_width (MWIDTH),
.lpm_widthu (WIDE_FIFO_AW),
.overflow_checking ( "OFF"),
.underflow_checking ( "ON"),
.use_eab ( "ON")
) rd_back_wfifo (
.clock (clk),
.data (avm_readdata),
.wrreq (avm_readdatavalid),
.rdreq (rd_data_fifo),
.usedw (),
.empty (rd_data_empty),
.full (),
.q (rd_data),
.almost_empty (),
.almost_full (),
.aclr (reset)
);
endmodule
module acl_stall_free_coalescer (
clk, // clock
reset, // reset
i_valid, // valid address
i_empty, // request FIFO is empty
i_addr, // input address
o_page_addr, // output page address
o_page_addr_valid, // page address valid
o_num_burst, // number of burst
o_new_page
);
parameter AW = 1,
PAGE_AW = 1,
MAX_BURST = 1,
TIME_OUT = 1,
MAX_THREAD = 1,
CACHE_LAST = 0,
DISABLE_COALESCE = 0;
localparam BURST_CNT_WIDTH = $clog2(MAX_BURST+1);
localparam TIME_OUT_W = $clog2(TIME_OUT+1);
localparam THREAD_W = $clog2(MAX_THREAD+1);
input clk;
input reset;
input i_valid;
input i_empty;
input [AW-1:0] i_addr;
// all output signals are registered to help P&R
output reg [PAGE_AW-1:0] o_page_addr;
output reg o_page_addr_valid;
output reg [BURST_CNT_WIDTH-1:0] o_num_burst;
output reg o_new_page;
logic init;
wire match_current_wire, match_next_wire, reset_cnt;
reg [BURST_CNT_WIDTH-1:0] num_burst;
reg valid_burst;
wire [PAGE_AW-1:0] page_addr;
reg [PAGE_AW-1:0] R_page_addr = 0;
reg [PAGE_AW-1:0] R_page_addr_next = 0;
reg [PAGE_AW-1:0] addr_hold = 0;
reg [3:0] delay_cnt; // it takes 5 clock cycles from o_page_addr_valid to being read out from FIFO (if avm_stall = 0), assuming 3 extra clock cycles to reach global mem
reg [TIME_OUT_W-1:0] time_out_cnt = 0;
reg [THREAD_W-1:0] thread_cnt = 0;
wire time_out;
wire max_thread;
assign page_addr = i_addr[AW-1:AW-PAGE_AW]; // page address
assign match_current_wire = page_addr == R_page_addr;
assign max_thread = thread_cnt[THREAD_W-1] & i_empty;
assign time_out = time_out_cnt[TIME_OUT_W-1] & i_empty;
assign reset_cnt = valid_burst & (
num_burst[BURST_CNT_WIDTH-1] // reach max burst
| time_out
| max_thread
| !match_current_wire & !match_next_wire & !init & i_valid ); // new burst
generate
if(MAX_BURST == 1) begin : BURST_ONE
assign match_next_wire = 1'b0;
end
else begin : BURST_N
assign match_next_wire = page_addr == R_page_addr_next & !init & i_valid & (|page_addr[BURST_CNT_WIDTH-2:0]);
end
if(DISABLE_COALESCE) begin : GEN_DISABLE_COALESCE
always@(*) begin
o_page_addr = page_addr;
o_page_addr_valid = i_valid;
o_num_burst = 1;
o_new_page = 1'b1;
end
end
else begin : ENABLE_COALESCE
always@(posedge clk) begin
if(i_valid) begin
R_page_addr <= page_addr;
R_page_addr_next <= page_addr + 1'b1;
end
o_num_burst <= num_burst;
o_page_addr <= addr_hold;
if(i_valid | reset_cnt) time_out_cnt <= 0; // nop is valid thread, should reset time_out counter too
else if(!time_out_cnt[TIME_OUT_W-1] & valid_burst) time_out_cnt <= time_out_cnt + 1;
if(reset_cnt) thread_cnt <= i_valid;
else if(i_valid & !thread_cnt[THREAD_W-1]) thread_cnt <= thread_cnt + 1;
if(o_page_addr_valid) delay_cnt <= 1;
else if(!delay_cnt[3]) delay_cnt <= delay_cnt + 1;
if(reset_cnt) begin
num_burst <= i_valid & !match_current_wire;
addr_hold <= page_addr;
end
else if(i_valid) begin
num_burst <= (!valid_burst & !match_current_wire | init)? 1 : num_burst + match_next_wire;
if(!valid_burst | init) addr_hold <= page_addr;
end
o_new_page <= (!match_current_wire| init) & i_valid;
end
always@(posedge clk or posedge reset) begin
if(reset) begin
o_page_addr_valid <= 1'b0;
valid_burst <= 1'b0;
end
else begin
if(reset_cnt) valid_burst <= i_valid & !match_current_wire;
else if(i_valid) begin
if(!valid_burst & !match_current_wire | init) valid_burst <= 1'b1;
else if(match_next_wire) valid_burst <= 1'b1;
end
o_page_addr_valid <= reset_cnt;
end
end
end
if(CACHE_LAST) begin : GEN_ENABLE_CACHE
always@(posedge clk or posedge reset) begin
if(reset) init <= 1'b1;
else begin
if(!valid_burst & !o_page_addr_valid & (!i_valid | match_current_wire & !init)) init <= 1'b1; // set init to 1 when the previous request is read out
else if(i_valid) init <= 1'b0;
end
end
end
else begin : GEN_DISABLE_CACHE
always@(posedge clk or posedge reset) begin
if(reset) init <= 1'b1;
else begin
if(!valid_burst & delay_cnt[3] & !o_page_addr_valid & i_empty & (!i_valid | match_current_wire & !init)) init <= 1'b1; // set init to 1 when the previous request is read out
else if(i_valid) init <= 1'b0;
end
end
end
endgenerate
endmodule
module lsu_bursting_write
(
clk, clk2x, reset, o_stall, i_valid, i_nop, i_address, i_writedata, i_stall, o_valid,
i_2nd_offset,
i_2nd_data,
i_2nd_byte_en,
i_2nd_en,
i_thread_valid,
o_active, //Debugging signal
avm_address, avm_write, avm_writeack, avm_writedata, avm_byteenable, avm_waitrequest,
avm_burstcount,
i_byteenable
);
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter WIDTH_BYTES=4; // Width of the memory access (bytes)
parameter MWIDTH_BYTES=32; // Width of the global memory bus (bytes)
parameter ALIGNMENT_ABITS=2; // Request address alignment (address bits)
parameter KERNEL_SIDE_MEM_LATENCY=32; // The max number of live threads
parameter MEMORY_SIDE_MEM_LATENCY=32; // The latency to get to the iface (no response needed from DDR, we generate writeack right before the iface).
parameter BURSTCOUNT_WIDTH=6; // Size of Avalon burst count port
parameter USE_WRITE_ACK=0; // Wait till the write has actually made it to global memory
parameter HIGH_FMAX=1;
parameter USE_BYTE_EN=0;
parameter UNALIGN=0;
localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam BYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
localparam ALIGNMENT_ABYTES=2**ALIGNMENT_ABITS;
/********
* Ports *
********/
// Standard global signals
input clk;
input clk2x;
input reset;
// Upstream interface
output o_stall;
input i_valid;
input i_nop;
input [AWIDTH-1:0] i_address;
input [WIDTH-1:0] i_writedata;
// used for unaligned
input [BYTE_SELECT_BITS-1-ALIGNMENT_ABITS:0] i_2nd_offset;
input [WIDTH-1:0] i_2nd_data;
input [WIDTH_BYTES-1:0] i_2nd_byte_en;
input i_2nd_en;
input i_thread_valid;
// Downstream interface
input i_stall;
output o_valid;
output reg o_active;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output avm_write;
input avm_writeack;
output [MWIDTH-1:0] avm_writedata;
output [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_waitrequest;
output [BURSTCOUNT_WIDTH-1:0] avm_burstcount;
input [WIDTH_BYTES-1:0] i_byteenable;
// Byte enable control
reg reg_lsu_i_valid, reg_lsu_i_thread_valid;
reg [AWIDTH-1:0] reg_lsu_i_address;
reg [WIDTH-1:0] reg_lsu_i_writedata;
reg [WIDTH_BYTES-1:0] reg_lsu_i_byte_enable;
reg reg_common_burst, reg_lsu_i_2nd_en;
reg reg_i_nop;
reg [BYTE_SELECT_BITS-1-ALIGNMENT_ABITS:0] reg_lsu_i_2nd_offset;
reg [WIDTH-1:0]reg_lsu_i_2nd_data;
reg [WIDTH_BYTES-1:0] reg_lsu_i_2nd_byte_en;
wire stall_signal_directly_from_lsu;
assign o_stall = reg_lsu_i_valid & stall_signal_directly_from_lsu;
// --------------- Pipeline stage : Burst Checking --------------------
always@(posedge clk or posedge reset)
begin
if (reset)
begin
reg_lsu_i_valid <= 1'b0;
reg_lsu_i_thread_valid <= 1'b0;
end
else
begin
if (~o_stall) begin
reg_lsu_i_valid <= i_valid;
reg_lsu_i_thread_valid <= i_thread_valid;
end
end
end
always@(posedge clk) begin
if (~o_stall & i_valid & ~i_nop) reg_lsu_i_address <= i_address;
if (~o_stall) begin
reg_i_nop <= i_nop;
reg_lsu_i_writedata <= i_writedata;
reg_lsu_i_byte_enable <= i_byteenable;
reg_lsu_i_2nd_offset <= i_2nd_offset;
reg_lsu_i_2nd_en <= i_2nd_en;
reg_lsu_i_2nd_data <= i_2nd_data;
reg_lsu_i_2nd_byte_en <= i_2nd_byte_en;
reg_common_burst <= i_nop | (reg_lsu_i_address[AWIDTH-1:BYTE_SELECT_BITS+BURSTCOUNT_WIDTH-1] == i_address[AWIDTH-1:BYTE_SELECT_BITS+BURSTCOUNT_WIDTH-1]);
end
end
// -------------------------------------------------------------------
lsu_bursting_write_internal #(
.KERNEL_SIDE_MEM_LATENCY(KERNEL_SIDE_MEM_LATENCY),
.MEMORY_SIDE_MEM_LATENCY(MEMORY_SIDE_MEM_LATENCY),
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.MWIDTH_BYTES(MWIDTH_BYTES),
.BURSTCOUNT_WIDTH(BURSTCOUNT_WIDTH),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS),
.USE_WRITE_ACK(USE_WRITE_ACK),
.USE_BYTE_EN(USE_BYTE_EN),
.UNALIGN(UNALIGN),
.HIGH_FMAX(HIGH_FMAX)
) bursting_write (
.clk(clk),
.clk2x(clk2x),
.reset(reset),
.i_nop(reg_i_nop),
.o_stall(stall_signal_directly_from_lsu),
.i_valid(reg_lsu_i_valid),
.i_thread_valid(reg_lsu_i_thread_valid),
.i_address(reg_lsu_i_address),
.i_writedata(reg_lsu_i_writedata),
.i_2nd_offset(reg_lsu_i_2nd_offset),
.i_2nd_data(reg_lsu_i_2nd_data),
.i_2nd_byte_en(reg_lsu_i_2nd_byte_en),
.i_2nd_en(reg_lsu_i_2nd_en),
.i_stall(i_stall),
.o_valid(o_valid),
.o_active(o_active),
.i_byteenable(reg_lsu_i_byte_enable),
.avm_address(avm_address),
.avm_write(avm_write),
.avm_writeack(avm_writeack),
.avm_writedata(avm_writedata),
.avm_byteenable(avm_byteenable),
.avm_burstcount(avm_burstcount),
.avm_waitrequest(avm_waitrequest),
.common_burst(reg_common_burst)
);
endmodule
//
// Burst coalesced write module
// Again, top level comments later
//
module lsu_bursting_write_internal
(
clk, clk2x, reset, o_stall, i_valid, i_nop, i_address, i_writedata, i_stall, o_valid,
o_active, //Debugging signal
i_2nd_offset,
i_2nd_data,
i_2nd_byte_en,
i_2nd_en,
i_thread_valid,
avm_address, avm_write, avm_writeack, avm_writedata, avm_byteenable, avm_waitrequest,
avm_burstcount,
i_byteenable,
common_burst
);
/*************
* Parameters *
*************/
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter WIDTH_BYTES=4; // Width of the memory access (bytes)
parameter MWIDTH_BYTES=32; // Width of the global memory bus (bytes)
parameter ALIGNMENT_ABITS=2; // Request address alignment (address bits)
parameter KERNEL_SIDE_MEM_LATENCY=32; // Memory latency in cycles
parameter MEMORY_SIDE_MEM_LATENCY=32; // Memory latency in cycles
parameter BURSTCOUNT_WIDTH=6; // Size of Avalon burst count port
parameter USE_WRITE_ACK=0; // Wait till the write has actually made it to global memory
parameter HIGH_FMAX=1;
parameter USE_BYTE_EN=0;
parameter UNALIGN=0;
// WARNING: Kernels will hang if InstrDataDep claims that a store
// has more capacity than this number
//
parameter MAX_CAPACITY=128; // Must be a power-of-2 to keep things simple
// Derived parameters
localparam MAX_BURST=2**(BURSTCOUNT_WIDTH-1);
//
// Notice that in the non write ack case, the number of threads seems to be twice the sensible number
// This is because MAX_THREADS is usually the limiter on the counter width. Once one request is assemembled,
// we want to be able to start piplining another burst. Thus the factor of 2.
// The MEMORY_SIDE_MEM_LATENCY will further increase this depth if the compiler
// thinks the lsu will see a lot of contention on the Avalon side.
//
localparam __WRITE_FIFO_DEPTH = (WIDTH_BYTES==MWIDTH_BYTES) ? 3*MAX_BURST : 2*MAX_BURST;
// No reason this should need more than max MLAB depth
localparam _WRITE_FIFO_DEPTH = ( __WRITE_FIFO_DEPTH < 64 ) ? __WRITE_FIFO_DEPTH : 64;
// Need at least 4 to account for fifo push-to-pop latency
localparam WRITE_FIFO_DEPTH = ( _WRITE_FIFO_DEPTH > 8 ) ? _WRITE_FIFO_DEPTH : 8;
// If writeack, make this equal to
localparam MAX_THREADS=(USE_WRITE_ACK ? KERNEL_SIDE_MEM_LATENCY - MEMORY_SIDE_MEM_LATENCY : (2*MWIDTH_BYTES/WIDTH_BYTES*MAX_BURST)); // Maximum # of threads to group into a burst request
//
localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam BYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
localparam SEGMENT_SELECT_BITS=BYTE_SELECT_BITS-ALIGNMENT_ABITS;
localparam PAGE_SELECT_BITS=AWIDTH-BYTE_SELECT_BITS;
localparam NUM_SEGMENTS=2**SEGMENT_SELECT_BITS;
localparam SEGMENT_WIDTH_BYTES=(2**ALIGNMENT_ABITS);
localparam SEGMENT_WIDTH=8*SEGMENT_WIDTH_BYTES;
localparam NUM_WORD = MWIDTH_BYTES/SEGMENT_WIDTH_BYTES;
localparam UNALIGN_BITS = $clog2(WIDTH_BYTES)-ALIGNMENT_ABITS;
// Constants
localparam COUNTER_WIDTH=(($clog2(MAX_THREADS)+1 < $clog2(MAX_CAPACITY+1)) ?
$clog2(MAX_CAPACITY+1) : ($clog2(MAX_THREADS)+1)); // Determines the max writes 'in-flight'
/********
* Ports *
********/
// Standard global signals
input clk;
input clk2x;
input reset;
// Upstream interface
output o_stall;
input i_valid;
input i_nop;
input [AWIDTH-1:0] i_address;
input [WIDTH-1:0] i_writedata;
// used for unaligned
input [BYTE_SELECT_BITS-1-ALIGNMENT_ABITS:0] i_2nd_offset;
input [WIDTH-1:0] i_2nd_data;
input [WIDTH_BYTES-1:0] i_2nd_byte_en;
input i_2nd_en;
input i_thread_valid;
// Downstream interface
input i_stall;
output o_valid;
output reg o_active;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output avm_write;
input avm_writeack;
output [MWIDTH-1:0] avm_writedata;
output [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_waitrequest;
output [BURSTCOUNT_WIDTH-1:0] avm_burstcount;
// Byte enable control
input [WIDTH_BYTES-1:0] i_byteenable;
// Help from outside
input common_burst;
/***************
* Architecture *
***************/
wire [WIDTH_BYTES-1:0] word_byte_enable;
wire [WIDTH-1:0] word_bit_enable, word2_bit_enable;
wire input_accepted;
wire output_acknowledged;
wire write_accepted;
wire [PAGE_SELECT_BITS-1:0] page_addr;
wire c_new_page;
wire c_page_done;
wire c_nop;
wire [PAGE_SELECT_BITS-1:0] c_req_addr;
wire c_req_valid;
wire c_stall;
reg [COUNTER_WIDTH-1:0] occ_counter;
// Replicated version of the occ and stores counters that decrement instead of increment
// This allows me to check the topmost bit to determine if the counter is non-empty
reg [COUNTER_WIDTH-1:0] nop_cnt;
reg [COUNTER_WIDTH-1:0] occ_counter_neg;
reg [COUNTER_WIDTH-1:0] ack_counter_neg;
reg [COUNTER_WIDTH-1:0] ack_counter;
reg [COUNTER_WIDTH-1:0] next_counter;
reg [MWIDTH-1:0] wm_writedata;
reg [MWIDTH_BYTES-1:0] wm_byteenable;
reg [MWIDTH-1:0] wm_wide_wdata;
reg [MWIDTH_BYTES-1:0] wm_wide_be;
reg [MWIDTH-1:0] wm_wide_bite;
wire w_fifo_full;
wire [BURSTCOUNT_WIDTH-1:0] c_burstcount;
// Track the current item in the write burst since we issue c_burstcount burst reqs
reg [BURSTCOUNT_WIDTH-1:0] burstcounter;
// The address components
assign page_addr = i_address[AWIDTH-1:BYTE_SELECT_BITS];
assign word_byte_enable = i_nop? '0: (USE_BYTE_EN ? i_byteenable :{WIDTH_BYTES{1'b1}}) ;
generate
genvar byte_num;
for( byte_num = 0; byte_num < WIDTH_BYTES; byte_num++)
begin : biten
assign word_bit_enable[(byte_num+1)*8-1: byte_num*8] = {8{word_byte_enable[byte_num]}};
assign word2_bit_enable[(byte_num+1)*8-1: byte_num*8] = {8{i_2nd_byte_en[byte_num]}};
end
endgenerate
wire oc_full;
wire cnt_valid;
wire coalescer_active;
// Coalescer - Groups subsequent requests together if they are compatible
// and the output register stage is stalled
bursting_coalescer #(
.PAGE_ADDR_WIDTH(PAGE_SELECT_BITS),
.TIMEOUT(16),
.BURSTCOUNT_WIDTH(BURSTCOUNT_WIDTH),
.MAXBURSTCOUNT(MAX_BURST),
.MAX_THREADS(MAX_THREADS)
) coalescer (
.clk(clk),
.reset(reset),
.i_page_addr(page_addr),
.i_valid(i_valid && !oc_full && !w_fifo_full),
.i_nop(i_nop),
.o_stall(c_stall),
.o_start_nop(c_nop), // new burst starts with nop
.o_new_page(c_new_page),
.o_page_done(c_page_done),
.o_req_addr(c_req_addr),
.o_req_valid(c_req_valid),
.i_stall(w_fifo_full),
.o_burstcount(c_burstcount),
.common_burst(common_burst),
.o_active(coalescer_active)
);
// Writedata MUX
generate if( SEGMENT_SELECT_BITS > 0 )
begin
wire [SEGMENT_SELECT_BITS-1:0] segment_select;
assign segment_select = i_address[BYTE_SELECT_BITS-1:ALIGNMENT_ABITS];
if(UNALIGN) begin : GEN_UNALIGN
assign cnt_valid = i_thread_valid;
always@(*) begin
wm_wide_wdata = {MWIDTH{1'bx}};
wm_wide_be = {MWIDTH_BYTES{1'b0}};
wm_wide_bite = {MWIDTH{1'b0}};
if(i_2nd_en) begin
wm_wide_wdata[WIDTH-1:0] = i_2nd_data;
wm_wide_wdata = wm_wide_wdata << (i_2nd_offset*SEGMENT_WIDTH);
wm_wide_wdata[WIDTH-1:0] = i_writedata;
wm_wide_be[WIDTH_BYTES-1:0] = i_2nd_byte_en;
wm_wide_be = wm_wide_be << (i_2nd_offset*SEGMENT_WIDTH_BYTES);
wm_wide_be[WIDTH_BYTES-1:0] = word_byte_enable;
wm_wide_bite[WIDTH-1:0] = word2_bit_enable;
wm_wide_bite = wm_wide_bite << (i_2nd_offset*SEGMENT_WIDTH);
wm_wide_bite[WIDTH-1:0] = word_bit_enable;
end
else begin
wm_wide_wdata[WIDTH-1:0] = i_writedata;
wm_wide_wdata = wm_wide_wdata << (segment_select*SEGMENT_WIDTH);
wm_wide_be[WIDTH_BYTES-1:0] = word_byte_enable;
wm_wide_be = wm_wide_be << (segment_select*SEGMENT_WIDTH_BYTES);
wm_wide_bite[WIDTH-1:0] = word_bit_enable;
wm_wide_bite = wm_wide_bite << (segment_select*SEGMENT_WIDTH);
end
end
end // end GEN_UNALIGN
else begin: GEN_ALIGN
assign cnt_valid = i_valid;
always@(*) begin
wm_wide_wdata = {MWIDTH{1'bx}};
wm_wide_wdata[WIDTH-1:0] = i_writedata;
wm_wide_wdata = wm_wide_wdata << (segment_select*SEGMENT_WIDTH);
wm_wide_be = {MWIDTH_BYTES{1'b0}};
wm_wide_be[WIDTH_BYTES-1:0] = word_byte_enable;
wm_wide_be = wm_wide_be << (segment_select*SEGMENT_WIDTH_BYTES);
wm_wide_bite = {MWIDTH{1'b0}};
wm_wide_bite[WIDTH-1:0] = word_bit_enable;
wm_wide_bite = wm_wide_bite << (segment_select*SEGMENT_WIDTH);
end
end
end
else
begin
assign cnt_valid = i_valid;
always@(*)
begin
wm_wide_wdata = {MWIDTH{1'bx}};
wm_wide_wdata[0 +: WIDTH] = i_writedata;
wm_wide_be = {MWIDTH_BYTES{1'b0}};
wm_wide_be[0 +: WIDTH_BYTES] = word_byte_enable;
wm_wide_bite = {MWIDTH{1'b0}};
wm_wide_bite[0 +: WIDTH] = word_bit_enable;
end
end
endgenerate
// Track the current write burst data - coalesce writes together until the
// output registers are ready for a new request.
always@(posedge clk or posedge reset)
begin
if(reset)
begin
wm_writedata <= {MWIDTH{1'b0}};
wm_byteenable <= {MWIDTH_BYTES{1'b0}};
end
else
begin
if(c_new_page)
begin
wm_writedata <= wm_wide_wdata;
wm_byteenable <= wm_wide_be;
end
else if(input_accepted)
begin
wm_writedata <= (wm_wide_wdata & wm_wide_bite) | (wm_writedata & ~wm_wide_bite);
wm_byteenable <= wm_wide_be | wm_byteenable;
end
end
end
wire [COUNTER_WIDTH-1:0] num_threads_written;
// This FIFO stores the actual data to be written
//
//
wire w_data_fifo_full, req_fifo_empty;
wire wr_page = c_page_done & !w_fifo_full;
acl_data_fifo #(
.DATA_WIDTH(COUNTER_WIDTH+MWIDTH+MWIDTH_BYTES),
.DEPTH(WRITE_FIFO_DEPTH),
.IMPL(HIGH_FMAX ? "ram_plus_reg" : "ram")
) req_fifo (
.clock(clk),
.resetn(~reset),
.data_in( {wm_writedata,wm_byteenable} ),
.valid_in( wr_page ),
.data_out( {avm_writedata,avm_byteenable} ),
.stall_in( ~write_accepted ),
.stall_out( w_data_fifo_full ),
.empty(req_fifo_empty)
);
// This FIFO stores the number of valid's to release with each writeack
//
wire w_ack_fifo_full;
acl_data_fifo #(
.DATA_WIDTH(COUNTER_WIDTH),
.DEPTH(2*WRITE_FIFO_DEPTH),
.IMPL(HIGH_FMAX ? "ram_plus_reg" : "ram")
) ack_fifo (
.clock(clk),
.resetn(~reset),
.data_in( next_counter),
.valid_in( wr_page ),
.data_out( num_threads_written ),
.stall_in( !avm_writeack),
.stall_out( w_ack_fifo_full )
);
// This FIFO hold the request information { address & burstcount }
//
wire w_fifo_stall_in;
assign w_fifo_stall_in = !(write_accepted && (burstcounter == avm_burstcount));
wire w_request_fifo_full;
acl_data_fifo #(
.DATA_WIDTH(PAGE_SELECT_BITS+BURSTCOUNT_WIDTH),
.DEPTH(WRITE_FIFO_DEPTH),
.IMPL(HIGH_FMAX ? "ram_plus_reg" : "ram")
) req_fifo2 (
.clock(clk),
.resetn(~reset),
.data_in( {c_req_addr,c_burstcount} ),
.valid_in( c_req_valid & !w_fifo_full ), // The basical coalescer stalls on w_fifo_full holding c_req_valid high
.data_out( {avm_address[AWIDTH-1: BYTE_SELECT_BITS],avm_burstcount} ),
.valid_out( avm_write ),
.stall_in( w_fifo_stall_in ),
.stall_out( w_request_fifo_full )
);
assign avm_address[BYTE_SELECT_BITS-1:0] = '0;
// The w_fifo_full is the OR of the data or request fifo's being full
assign w_fifo_full = w_data_fifo_full | w_request_fifo_full | w_ack_fifo_full;
// Occupancy counter - track the number of successfully transmitted writes
// and the number of writes pending in the next request.
// occ_counter - the total occupancy (in threads) of the unit
// next_counter - the number of threads coalesced into the next transfer
// ack_counter - the number of pending threads with write completion acknowledged
reg pending_nop;
wire pending_cc = nop_cnt != occ_counter;
wire burst_start_nop = cnt_valid & c_nop & !o_stall;
wire start_with_nop = !pending_cc && i_nop && cnt_valid && !o_stall; // nop starts when there are no pending writes
wire normal_cc_valid = cnt_valid && !o_stall && !i_nop;
wire clear_nop_cnt = normal_cc_valid || !pending_cc;
assign input_accepted = cnt_valid && !o_stall && !(c_nop || start_with_nop);
assign write_accepted = avm_write && !avm_waitrequest;
assign output_acknowledged = o_valid && !i_stall;
wire [8:0] ack_pending = {1'b1, {COUNTER_WIDTH{1'b0}}} - ack_counter;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
occ_counter <= {COUNTER_WIDTH{1'b0}};
occ_counter_neg <= {COUNTER_WIDTH{1'b0}};
ack_counter <= {COUNTER_WIDTH{1'b0}};
next_counter <= {COUNTER_WIDTH{1'b0}};
ack_counter_neg <= '0;
nop_cnt <= '0;
burstcounter <= 6'b000001;
o_active <= 1'b0;
pending_nop <= 1'b0;
end
else
begin
if(clear_nop_cnt) begin
nop_cnt <= '0;
pending_nop <= 1'b0;
end
else if(!start_with_nop) begin
nop_cnt <= nop_cnt + burst_start_nop;
if(burst_start_nop) pending_nop <= 1'b1;
end
occ_counter <= occ_counter + (cnt_valid && !o_stall) - output_acknowledged;
occ_counter_neg <= occ_counter_neg - (cnt_valid && !o_stall) + output_acknowledged;
next_counter <= input_accepted + (c_page_done ? {COUNTER_WIDTH{1'b0}} : next_counter) + (normal_cc_valid? nop_cnt : 0);
if(USE_WRITE_ACK) begin
ack_counter <= ack_counter
- (avm_writeack? num_threads_written : 0)
- ( (!pending_cc & !normal_cc_valid)? nop_cnt : 0)
- start_with_nop
+ output_acknowledged;
o_active <= occ_counter_neg[COUNTER_WIDTH-1];
end
else begin
ack_counter <= ack_counter - (cnt_valid && !o_stall) + output_acknowledged;
ack_counter_neg <= ack_counter_neg - wr_page + avm_writeack;
o_active <= occ_counter_neg[COUNTER_WIDTH-1] | ack_counter_neg[COUNTER_WIDTH-1] | coalescer_active; // do not use num_threads_written, because it takes extra resource
end
burstcounter <= write_accepted ? ((burstcounter == avm_burstcount) ? 6'b000001 : burstcounter+1) : burstcounter;
end
end
assign oc_full = occ_counter[COUNTER_WIDTH-1];
// Pipeline control signals
assign o_stall = oc_full || c_stall || w_fifo_full;
assign o_valid = ack_counter[COUNTER_WIDTH-1];
endmodule
// BURST COALESCING MODULE
//
// Similar to the basic coalescer but supports checking if accesses are in consecutive DRAM "pages"
// Supports the ad-hocly discovered protocols for bursting efficiently with avalaon
// - Don't burst from an ODD address
// - If not on a burst boundary, then just burst up to the next burst bondary
//
// Yes, I know, this could be incorporated into the basic coalescer. But that's really not my "thing"
//
module bursting_coalescer
(
clk, reset, i_page_addr, i_nop, i_valid, o_stall, o_new_page, o_page_done, o_req_addr, o_burstcount,
o_req_valid, i_stall, o_start_nop,
common_burst,
// For the purposes of maintaining latency correctly, we need to know if total # of threads
// accepted by the caching LSU
i_input_accepted_from_wrapper_lsu,
i_reset_timeout,
o_active
);
parameter PAGE_ADDR_WIDTH=32;
parameter TIMEOUT=8;
parameter BURSTCOUNT_WIDTH=6; // Size of Avalon burst count port
parameter MAXBURSTCOUNT=32; // This isn't the max supported by Avalon, but the max that the instantiating module needs
parameter MAX_THREADS=64; // Must be a power of 2
parameter USECACHING=0;
localparam SLAVE_MAX_BURST=2**(BURSTCOUNT_WIDTH-1);
localparam THREAD_COUNTER_WIDTH=$clog2(MAX_THREADS+1);
input clk;
input reset;
input [PAGE_ADDR_WIDTH-1:0] i_page_addr;
input i_nop;
input i_valid;
output o_stall;
output o_new_page;
output o_page_done;
output o_start_nop;
output [PAGE_ADDR_WIDTH-1:0] o_req_addr;
output o_req_valid;
output [BURSTCOUNT_WIDTH-1:0] o_burstcount;
input i_stall;
input common_burst;
input i_input_accepted_from_wrapper_lsu;
input i_reset_timeout;
output o_active;
reg [PAGE_ADDR_WIDTH-1:0] page_addr;
reg [PAGE_ADDR_WIDTH-1:0] last_page_addr;
reg [PAGE_ADDR_WIDTH-1:0] last_page_addr_p1;
reg [BURSTCOUNT_WIDTH-1:0] burstcount;
reg valid;
wire ready;
wire waiting;
wire match;
wire timeout;
reg [$clog2(TIMEOUT):0] timeout_counter;
reg [THREAD_COUNTER_WIDTH-1:0] thread_counter;
generate if(USECACHING)
begin
assign timeout = timeout_counter[$clog2(TIMEOUT)] | thread_counter[THREAD_COUNTER_WIDTH-1];
end
else
begin
assign timeout = timeout_counter[$clog2(TIMEOUT)];
end
endgenerate
// Internal signal logic
wire match_burst_address;
wire match_next_page;
wire match_current_page;
generate
if ( BURSTCOUNT_WIDTH > 1 )
begin
assign match_next_page = (i_page_addr[BURSTCOUNT_WIDTH-2:0] === last_page_addr_p1[BURSTCOUNT_WIDTH-2:0]) && (|last_page_addr_p1[BURSTCOUNT_WIDTH-2:0]);
assign match_current_page = (i_page_addr[BURSTCOUNT_WIDTH-2:0] === last_page_addr[BURSTCOUNT_WIDTH-2:0]);
end
else
begin
assign match_next_page = 1'b0;
assign match_current_page = 1'b1;
end
endgenerate
assign match_burst_address = common_burst;//(i_page_addr[PAGE_ADDR_WIDTH-1:BURSTCOUNT_WIDTH-1] == last_page_addr[PAGE_ADDR_WIDTH-1:BURSTCOUNT_WIDTH-1]);
assign match = (match_burst_address && (match_current_page || match_next_page)) && !thread_counter[THREAD_COUNTER_WIDTH-1];
assign ready = !valid || !(i_stall || waiting);
assign waiting = !timeout && (!i_valid || match);
wire input_accepted = i_valid && !o_stall;
assign o_start_nop = i_nop & ready;
assign o_active = valid;
always@(posedge clk or posedge reset)
begin
if(reset)
begin
page_addr <= {PAGE_ADDR_WIDTH{1'b0}};
last_page_addr <= {PAGE_ADDR_WIDTH{1'b0}};
last_page_addr_p1 <= {PAGE_ADDR_WIDTH{1'b0}};
burstcount <= 1;
valid <= 1'b0;
timeout_counter <= 0;
thread_counter <= {THREAD_COUNTER_WIDTH{1'b0}};
end
else
begin
page_addr <= ready ? i_page_addr : page_addr;
last_page_addr <= ready ? i_page_addr : (input_accepted && match_next_page ? i_page_addr : last_page_addr );
last_page_addr_p1 <= ready ? i_page_addr+1 : (input_accepted && match_next_page ? i_page_addr+1 : last_page_addr_p1 );
valid <= ready ? i_valid & !i_nop : valid; // burst should not start with nop thread
burstcount <= ready ? 6'b000001 : (input_accepted && match_next_page ? burstcount+1 : burstcount );
thread_counter <= ready ? 1 : (USECACHING ?
(i_input_accepted_from_wrapper_lsu && !thread_counter[THREAD_COUNTER_WIDTH-1] ? thread_counter+1 : thread_counter ) :
(input_accepted ? thread_counter+1 : thread_counter));
if( USECACHING && i_reset_timeout || !USECACHING && i_valid )
timeout_counter <= 'd1;
else if( valid && !timeout )
timeout_counter <= timeout_counter + 'd1;
end
end
// Outputs
assign o_stall = !match && !ready && i_valid;
// We're starting a new page (used by loads)
assign o_new_page = ready || i_valid && match_burst_address && !thread_counter[THREAD_COUNTER_WIDTH-1] && match_next_page;
assign o_req_addr = page_addr;
assign o_burstcount = burstcount;
assign o_req_valid = valid && !waiting;
// We're just finished with a page (used by stores)
assign o_page_done = valid && !waiting && !i_stall || !ready && i_valid && match_burst_address && !thread_counter[THREAD_COUNTER_WIDTH-1] && match_next_page;
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_be_i
//
// Generated
// by: wig
// on: Sat Mar 3 11:02:57 2007
// cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../udc.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_be_i.v,v 1.1 2007/03/03 11:17:34 wig Exp $
// $Date: 2007/03/03 11:17:34 $
// $Log: inst_be_i.v,v $
// Revision 1.1 2007/03/03 11:17:34 wig
// Extended ::udc: language dependent %AINS% and %PINS%: e.g. <VHDL>...</VHDL>
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
//
// Generator: mix_0.pl Revision: 1.47 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
udc: Verilog HEAD HOOK inst_bc2_i
//
//
// Start of Generated Module rtl of inst_be_i
//
// No user `defines in this module
module inst_be_i
//
// Generated Module inst_be_i
//
(
);
udc: Verilog PARA HOOK inst_bc2_i
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
udc: Verilog BODY HOOK inst_bc2_i
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_be_i
//
udc: Verilog FOOT HOOK two lines inst_bc2_i
second line inst_bc2_i, config here inst_be_i_rtl_conf and description no verilog udc here
//
//!End of Module/s
// --------------------------------------------------------------
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 26.06.2017 22:52:37
// Design Name:
// Module Name: show_one_char2
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module show_one_char2(
input clk,
input rst,
input [10:0]hc_visible,
input [10:0]vc_visible,
input [7:0] the_char,
output in_square,
output reg in_character
);
localparam n = 3; //numero de bits necesario para contar los pixeles definidos por ancho_pixel
localparam ancho_pixel = 'd1; //ancho y alto de cada pixel que compone a un caracter.
parameter MENU_X_LOCATION = 11'd70;
parameter MENU_Y_LOCATION = 11'd150;
localparam CHARACTER_WIDTH = 8'd5;
localparam CHARACTER_HEIGHT = 8'd8;
localparam MAX_CHARACTER_LINE = 1; //habran 1 caracteres por linea
localparam MAX_NUMBER_LINES = 1; //numero de lineas
localparam MENU_WIDTH = ( CHARACTER_WIDTH + 8'd1 ) * MAX_CHARACTER_LINE * ancho_pixel;
localparam MENU_HEIGHT = (CHARACTER_HEIGHT) * MAX_NUMBER_LINES * ancho_pixel;
localparam MENU_X_TOP = MENU_X_LOCATION + MENU_WIDTH;
localparam MENU_Y_TOP = MENU_Y_LOCATION + MENU_HEIGHT;
reg [5:0]menu_character_position_x; //indica la posicion x del caracter dentro del cuadro
reg [5:0]menu_character_position_y; //indica la posicion y del caracter dentro del cuadro
reg [5:0]menu_character_position_x_next;
reg [5:0]menu_character_position_y_next;
reg [7:0]push_menu_minimat_x; //se incremente a incrementos de ancho de caracter
reg [7:0]push_menu_minimat_y; //se incremente a incrementos de largo de caracter
reg [7:0]push_menu_minimat_x_next;
reg [7:0]push_menu_minimat_y_next;
reg [2:0]pixel_x_to_show; //indica la coordenada x del pixel que se debe dibujar
reg [2:0]pixel_y_to_show; //indica la coordenada y del pixel que se debe dibujar
reg [2:0]pixel_x_to_show_next;
reg [2:0]pixel_y_to_show_next;
wire [10:0]hc_visible_menu; //para fijar la posicion x en la que aparecera el cuadro de texto
wire [10:0]vc_visible_menu; //para fijar la posicion y en la que aparecera el cuadro de texto
assign in_square=(hc_visible_menu>0)&&(vc_visible_menu>0);
assign hc_visible_menu=( (hc_visible >= MENU_X_LOCATION) && (hc_visible <= MENU_X_TOP) )? hc_visible - MENU_X_LOCATION:11'd0;
assign vc_visible_menu=( (vc_visible >= MENU_Y_LOCATION) && (vc_visible <= MENU_Y_TOP) )? vc_visible - MENU_Y_LOCATION:11'd0;
reg [n-1:0]contador_pixels_horizontales; //este registro cuenta de 0 a 2
reg [n-1:0]contador_pixels_verticales; //este registro cuenta de 0 a 2
reg [n-1:0]contador_pixels_horizontales_next;
reg [n-1:0]contador_pixels_verticales_next;
//1 pixel por pixel de letra
//contando cada 3 pixeles
always@(*)
if(in_square)
if(contador_pixels_horizontales == (ancho_pixel - 'd1))
contador_pixels_horizontales_next = 2'd0;
else
contador_pixels_horizontales_next = contador_pixels_horizontales + 'd1;
else
contador_pixels_horizontales_next = 'd0;
always@(posedge clk or posedge rst)
if(rst)
contador_pixels_horizontales <= 'd0;
else
contador_pixels_horizontales <= contador_pixels_horizontales_next;
//////////////////////////////////////////////////////////////////////////////
//contando cada tres pixeles verticales
always@(*)
if(vc_visible_menu > 0)
if(hc_visible_menu == MENU_WIDTH)
if(contador_pixels_verticales == (ancho_pixel - 'd1))
contador_pixels_verticales_next = 'd0;
else
contador_pixels_verticales_next = contador_pixels_verticales + 'd1;
else
contador_pixels_verticales_next = contador_pixels_verticales;
else
contador_pixels_verticales_next = 'd0;
always@(posedge clk or posedge rst)
if(rst)
contador_pixels_verticales <= 'd0;
else
contador_pixels_verticales <= contador_pixels_verticales_next;
/////////////////////////////////////////////////////////////////////////////
//Calculando en que caracter est?? el haz y qu?? pixel hay que dibujar
wire pixel_limit_h = contador_pixels_horizontales == (ancho_pixel - 'd1);//cuando se lleg?? al m??ximo.
wire hor_limit_char = push_menu_minimat_x == ((CHARACTER_WIDTH + 8'd1) - 8'd1);//se debe agregar el espacio de separaci??n
always@(*)
begin
case({in_square, pixel_limit_h, hor_limit_char})
3'b111: push_menu_minimat_x_next = 8'd0;
3'b110: push_menu_minimat_x_next = push_menu_minimat_x + 8'd1;
3'b100, 3'b101: push_menu_minimat_x_next = push_menu_minimat_x;
default: push_menu_minimat_x_next = 8'd0;
endcase
case({in_square,pixel_limit_h,hor_limit_char})
3'b111: menu_character_position_x_next = menu_character_position_x + 6'd1;
3'b110: menu_character_position_x_next = menu_character_position_x;
3'b100,3'b101: menu_character_position_x_next = menu_character_position_x;
default:menu_character_position_x_next = 6'd0;
endcase
case({in_square,pixel_limit_h,hor_limit_char})
3'b111:pixel_x_to_show_next = 3'd0;
3'b110:pixel_x_to_show_next = pixel_x_to_show + 3'd1;
3'b100,3'b101:pixel_x_to_show_next = pixel_x_to_show;
default:pixel_x_to_show_next = 3'd0;
endcase
end
always@(posedge clk)
begin
push_menu_minimat_x <= push_menu_minimat_x_next;
menu_character_position_x <= menu_character_position_x_next;
pixel_x_to_show <= pixel_x_to_show_next;
end
wire pixel_limit_v = (contador_pixels_verticales == (ancho_pixel - 'd1) && (hc_visible_menu == MENU_WIDTH)); //cuando se llega al maximo.
//wire pixel_limit_v = (contador_pixels_verticales == (ancho_pixel - 2'd1) && (hc_visible == 32'd0));//cuando se llega al maximo.
wire ver_limit_char = push_menu_minimat_y == (CHARACTER_HEIGHT - 8'd1);
always @(*)
begin
case({vc_visible_menu > 0, pixel_limit_v, ver_limit_char})
3'b111:push_menu_minimat_y_next = 8'd0;
3'b110:push_menu_minimat_y_next = push_menu_minimat_y + 8'd1;
3'b100,3'b101:push_menu_minimat_y_next = push_menu_minimat_y;
default:push_menu_minimat_y_next = 8'd0;
endcase
case({vc_visible_menu > 0, pixel_limit_v, ver_limit_char})
3'b111:menu_character_position_y_next = menu_character_position_y + 6'd1;
3'b110:menu_character_position_y_next = menu_character_position_y;
3'b100,3'b101:menu_character_position_y_next = menu_character_position_y;
default:menu_character_position_y_next = 6'd0;
endcase
case({vc_visible_menu > 0, pixel_limit_v, ver_limit_char})
3'b111:pixel_y_to_show_next = 3'd0;
3'b110:pixel_y_to_show_next = pixel_y_to_show + 3'd1;
3'b100,3'b101:pixel_y_to_show_next = pixel_y_to_show;
default:pixel_y_to_show_next = 3'd0;
endcase
end
always@(posedge clk)
begin
push_menu_minimat_y <= push_menu_minimat_y_next;
menu_character_position_y <= menu_character_position_y_next;
pixel_y_to_show <= pixel_y_to_show_next;
end
wire [4:0]character_to_show[0:7];
wire [39:0]char_vect_to_show;
wire [8 * MAX_CHARACTER_LINE - 1:0] tex_row_tmp;
wire [7:0]select;
assign tex_row_tmp = the_char;
assign select = tex_row_tmp[7:0];
characters m_ch(select, char_vect_to_show);
assign { character_to_show[7], character_to_show[6], character_to_show[5], character_to_show[4],
character_to_show[3], character_to_show[2], character_to_show[1], character_to_show[0] } =
char_vect_to_show;
wire [5:0]pixel_row; //agregamos un cero para que se espaceen las letras
assign pixel_row = {1'b0, character_to_show[pixel_y_to_show]};
always@(*)
if(in_square)
in_character = ( pixel_row[pixel_x_to_show] );
else
in_character = 1'd0;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
logic [7:0] arr [7:0];
logic [7:0] arri [7:0];
has_array am1 (.clk(clk), .arri(arr), .arro(arri));
integer cyc; initial cyc = 0;
initial begin
for (int i = 0; i < 8; i++) begin
arr[i] = 0;
end
end
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5 && arri[1] != 8) begin
$stop;
end
for (int i = 0; i < 7; ++i) begin
arr[i+1] <= arr[i];
end
arr[0] <= arr[0] + 1;
end
endmodule : t
module has_array (
input clk,
input logic [7:0] arri [7:0],
output logic [7:0] arro [7:0]
);
integer cyc; initial cyc = 0;
always @(posedge clk) begin
cyc <= cyc + 1;
if (arri[0] == 10 && cyc == 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge clk) begin
for (integer i = 0; i < 7; ++i) begin
arro[i+1] <= arro[i];
end
arro[0] = arro[0] + 2;
end
endmodule : has_array
|
`timescale 1ns/1ps
`default_nettype none
module inout_iv(SIM_RST, SIM_CLK, p4VSW, GND, GOJAM, T06_n, SB0_n, SB1_n, SB2, SB2_n, F04A, F05A_n, F05B_n, F06B, FS07A, FS07_n, F07B, F09B_n, FS10, F10A_n, F10B, BR1, BR1_n, CCHG_n, CSG, POUT_n, MOUT_n, ZOUT_n, OVF_n, WOVR_n, SHINC_n, CAURST, T6ON_n, BLKUPL_n, UPL0, UPL1, XLNK0, XLNK1, GTONE, GTSET, GTSET_n, GATEX_n, GATEY_n, GATEZ_n, SIGNX, SIGNY, SIGNZ, BMGXP, BMGXM, BMGYP, BMGYM, BMGZP, BMGZM, C45R, XB3_n, XB5_n, XB6_n, XB7_n, XT3_n, CXB0_n, CXB7_n, CA2_n, CA4_n, CA5_n, CA6_n, CHWL01_n, CHWL02_n, CHWL03_n, CHWL04_n, CHWL05_n, CHWL06_n, CHWL07_n, CHWL08_n, CHWL09_n, CHWL10_n, CHWL11_n, CHWL12_n, CCH11, CCH13, CCH14, RCH11_n, RCH13_n, RCH14_n, RCH33_n, WCH11_n, WCH13_n, WCH14_n, F5ASB0_n, F5ASB2, F5ASB2_n, F5BSB2_n, ERRST, T1P, T2P, T3P, T4P, T5P, T6P, ALTM, BMAGXP, BMAGXM, BMAGYP, BMAGYM, BMAGZP, BMAGZM, EMSD, GYROD, UPRUPT, INLNKP, INLNKM, OTLNKM, THRSTD, CCH33, CH1305, CH1306, CH1308, CH1309, CH1401, CH1402, CH1403, CH1404, CH1405, CH1406, CH1407, CH1408, CH1409, CH1410, CH3310, CH3311, CH1109, CH1110, CH1111, CH1112);
input wire SIM_RST;
input wire SIM_CLK;
input wire p4VSW;
input wire GND;
output wire ALTM;
input wire BLKUPL_n;
output wire BMAGXM;
output wire BMAGXP;
output wire BMAGYM;
output wire BMAGYP;
output wire BMAGZM;
output wire BMAGZP;
input wire BMGXM;
input wire BMGXP;
input wire BMGYM;
input wire BMGYP;
input wire BMGZM;
input wire BMGZP;
input wire BR1;
input wire BR1_n;
input wire C45R;
input wire CA2_n;
input wire CA4_n;
input wire CA5_n;
input wire CA6_n;
input wire CAURST;
input wire CCH11;
input wire CCH13;
input wire CCH14;
output wire CCH33;
input wire CCHG_n;
output wire CH1109;
output wire CH1110;
output wire CH1111;
output wire CH1112;
output wire CH1305;
output wire CH1306;
output wire CH1308;
output wire CH1309;
output wire CH1401;
output wire CH1402;
output wire CH1403;
output wire CH1404;
output wire CH1405;
output wire CH1406;
output wire CH1407;
output wire CH1408;
output wire CH1409;
output wire CH1410;
output wire CH3310;
output wire CH3311;
input wire CHWL01_n;
input wire CHWL02_n;
input wire CHWL03_n;
input wire CHWL04_n;
input wire CHWL05_n;
input wire CHWL06_n;
input wire CHWL07_n;
input wire CHWL08_n;
input wire CHWL09_n;
input wire CHWL10_n;
input wire CHWL11_n;
input wire CHWL12_n;
input wire CSG;
input wire CXB0_n;
input wire CXB7_n;
output wire EMSD;
output wire ERRST;
input wire F04A;
input wire F05A_n;
input wire F05B_n;
input wire F06B;
input wire F07B;
input wire F09B_n;
input wire F10A_n;
input wire F10B;
output wire F5ASB0_n;
output wire F5ASB2;
output wire F5ASB2_n;
output wire F5BSB2_n;
input wire FS07A;
input wire FS07_n;
input wire FS10;
input wire GATEX_n;
input wire GATEY_n;
input wire GATEZ_n;
input wire GOJAM;
input wire GTONE;
input wire GTSET;
input wire GTSET_n;
output wire GYROD;
output wire INLNKM;
output wire INLNKP;
input wire MOUT_n;
output wire OTLNKM;
input wire OVF_n;
input wire POUT_n;
input wire RCH11_n;
input wire RCH13_n;
input wire RCH14_n;
input wire RCH33_n;
input wire SB0_n;
input wire SB1_n;
input wire SB2;
input wire SB2_n;
input wire SHINC_n;
input wire SIGNX;
input wire SIGNY;
input wire SIGNZ;
input wire T06_n;
output wire T1P;
output wire T2P;
output wire T3P;
output wire T4P;
output wire T5P;
input wire T6ON_n;
output wire T6P;
output wire THRSTD;
input wire UPL0;
input wire UPL1;
output wire UPRUPT;
input wire WCH11_n;
input wire WCH13_n;
input wire WCH14_n;
input wire WOVR_n;
input wire XB3_n;
input wire XB5_n;
input wire XB6_n;
input wire XB7_n;
input wire XLNK0;
input wire XLNK1;
input wire XT3_n;
input wire ZOUT_n;
wire __A19_1__ALRT0;
wire __A19_1__ALRT1;
wire __A19_1__ALT0;
wire __A19_1__ALT1;
wire __A19_1__ALTSNC;
wire __A19_1__BLKUPL;
wire __A19_1__C45R_n;
wire __A19_1__EMSm;
wire __A19_1__EMSp;
wire __A19_1__F5ASB0;
wire __A19_1__F5BSB2;
wire __A19_1__OTLNK0;
wire __A19_1__OTLNK1;
wire __A19_1__SH3MS_n;
wire __A19_1__THRSTm;
wire __A19_1__THRSTp;
wire __A19_1__UPL0_n;
wire __A19_1__UPL1_n;
wire __A19_1__XLNK0_n;
wire __A19_1__XLNK1_n;
wire __A19_2__CNTRSB_n;
wire __A19_2__F06B_n;
wire __A19_2__F07C_n;
wire __A19_2__F07D_n;
wire __A19_2__F10B_n;
wire __A19_2__F7CSB1_n;
wire __A19_2__FF1109_n;
wire __A19_2__FF1110_n;
wire __A19_2__FF1111_n;
wire __A19_2__FF1112_n;
wire __A19_2__GYENAB;
wire __A19_2__GYRRST;
wire __A19_2__GYRSET;
wire __A19_2__GYXM;
wire __A19_2__GYXP;
wire __A19_2__GYYM;
wire __A19_2__GYYP;
wire __A19_2__GYZM;
wire __A19_2__GYZP;
wire __A19_2__O44;
wire __A19_2__OT1110;
wire __A19_2__OT1111;
wire __A19_2__OT1112;
wire __A19_2__OUTCOM;
wire __A19_2__RHCGO;
wire net_U19001_Pad1;
wire net_U19001_Pad13;
wire net_U19001_Pad4;
wire net_U19002_Pad11;
wire net_U19002_Pad2;
wire net_U19002_Pad3;
wire net_U19002_Pad4;
wire net_U19002_Pad5;
wire net_U19002_Pad8;
wire net_U19002_Pad9;
wire net_U19003_Pad11;
wire net_U19003_Pad6;
wire net_U19003_Pad8;
wire net_U19003_Pad9;
wire net_U19004_Pad1;
wire net_U19004_Pad10;
wire net_U19004_Pad12;
wire net_U19005_Pad12;
wire net_U19006_Pad13;
wire net_U19006_Pad3;
wire net_U19006_Pad4;
wire net_U19007_Pad10;
wire net_U19007_Pad12;
wire net_U19007_Pad6;
wire net_U19008_Pad3;
wire net_U19008_Pad9;
wire net_U19009_Pad10;
wire net_U19010_Pad1;
wire net_U19010_Pad10;
wire net_U19010_Pad12;
wire net_U19010_Pad13;
wire net_U19010_Pad4;
wire net_U19010_Pad6;
wire net_U19011_Pad13;
wire net_U19011_Pad9;
wire net_U19012_Pad1;
wire net_U19012_Pad13;
wire net_U19013_Pad6;
wire net_U19014_Pad8;
wire net_U19014_Pad9;
wire net_U19015_Pad10;
wire net_U19015_Pad12;
wire net_U19015_Pad13;
wire net_U19016_Pad10;
wire net_U19016_Pad11;
wire net_U19016_Pad8;
wire net_U19016_Pad9;
wire net_U19017_Pad10;
wire net_U19017_Pad11;
wire net_U19017_Pad12;
wire net_U19017_Pad3;
wire net_U19017_Pad9;
wire net_U19018_Pad10;
wire net_U19018_Pad12;
wire net_U19018_Pad13;
wire net_U19019_Pad1;
wire net_U19020_Pad13;
wire net_U19021_Pad1;
wire net_U19021_Pad13;
wire net_U19021_Pad3;
wire net_U19022_Pad13;
wire net_U19023_Pad1;
wire net_U19024_Pad10;
wire net_U19024_Pad8;
wire net_U19024_Pad9;
wire net_U19025_Pad1;
wire net_U19025_Pad11;
wire net_U19025_Pad4;
wire net_U19026_Pad12;
wire net_U19026_Pad13;
wire net_U19027_Pad10;
wire net_U19027_Pad4;
wire net_U19028_Pad10;
wire net_U19028_Pad13;
wire net_U19029_Pad1;
wire net_U19029_Pad10;
wire net_U19029_Pad4;
wire net_U19029_Pad9;
wire net_U19030_Pad10;
wire net_U19030_Pad11;
wire net_U19030_Pad3;
wire net_U19030_Pad4;
wire net_U19030_Pad6;
wire net_U19030_Pad8;
wire net_U19031_Pad10;
wire net_U19031_Pad12;
wire net_U19031_Pad13;
wire net_U19031_Pad4;
wire net_U19032_Pad13;
wire net_U19033_Pad13;
wire net_U19034_Pad13;
wire net_U19034_Pad3;
wire net_U19035_Pad3;
wire net_U19036_Pad10;
wire net_U19036_Pad11;
wire net_U19036_Pad12;
wire net_U19036_Pad13;
wire net_U19036_Pad8;
wire net_U19037_Pad1;
wire net_U19037_Pad10;
wire net_U19038_Pad1;
wire net_U19038_Pad10;
wire net_U19039_Pad1;
wire net_U19039_Pad13;
wire net_U19040_Pad1;
wire net_U19040_Pad13;
wire net_U19040_Pad3;
wire net_U19041_Pad1;
wire net_U19041_Pad13;
wire net_U19042_Pad13;
wire net_U19042_Pad3;
wire net_U19043_Pad1;
wire net_U19043_Pad3;
wire net_U19044_Pad10;
wire net_U19044_Pad11;
wire net_U19044_Pad8;
wire net_U19044_Pad9;
wire net_U19046_Pad13;
wire net_U19047_Pad11;
wire net_U19047_Pad13;
wire net_U19047_Pad2;
wire net_U19047_Pad3;
wire net_U19047_Pad9;
wire net_U19049_Pad10;
wire net_U19049_Pad13;
wire net_U19050_Pad10;
wire net_U19050_Pad12;
wire net_U19050_Pad13;
wire net_U19051_Pad1;
wire net_U19051_Pad10;
wire net_U19051_Pad2;
wire net_U19051_Pad3;
wire net_U19052_Pad10;
wire net_U19052_Pad13;
wire net_U19053_Pad8;
wire net_U19053_Pad9;
wire net_U19055_Pad6;
wire net_U19055_Pad8;
wire net_U19056_Pad10;
wire net_U19056_Pad12;
wire net_U19056_Pad13;
wire net_U19056_Pad4;
wire net_U19057_Pad10;
wire net_U19057_Pad12;
wire net_U19057_Pad13;
wire net_U19057_Pad4;
wire net_U19057_Pad6;
wire net_U19057_Pad9;
wire net_U19059_Pad12;
wire net_U19059_Pad6;
wire net_U19059_Pad8;
wire net_U19060_Pad1;
wire net_U19060_Pad10;
wire net_U19060_Pad4;
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U19001(net_U19001_Pad1, CA6_n, CXB0_n, net_U19001_Pad4, SHINC_n, T06_n, GND, net_U19001_Pad4, net_U19001_Pad13, __A19_1__SH3MS_n, __A19_1__SH3MS_n, CSG, net_U19001_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1) U19002(net_U19001_Pad1, net_U19002_Pad2, net_U19002_Pad3, net_U19002_Pad4, net_U19002_Pad5, __A19_1__ALTSNC, GND, net_U19002_Pad8, net_U19002_Pad9, __A19_1__OTLNK0, net_U19002_Pad11, F5ASB0_n, __A19_1__F5ASB0, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U19003(BR1, __A19_1__SH3MS_n, net_U19002_Pad2, __A19_1__SH3MS_n, BR1_n, net_U19003_Pad6, GND, net_U19003_Pad8, net_U19003_Pad9, CCH14, net_U19003_Pad11, net_U19002_Pad3, net_U19002_Pad2, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U19004(net_U19004_Pad1, CHWL02_n, WCH14_n, net_U19004_Pad12, net_U19004_Pad1, net_U19004_Pad10, GND, net_U19004_Pad12, CCH14, net_U19004_Pad10, RCH14_n, net_U19004_Pad12, CH1402, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U19005(__A19_1__ALT0, net_U19002_Pad4, net_U19004_Pad10, __A19_1__ALT1, net_U19004_Pad10, net_U19005_Pad12, GND, net_U19002_Pad4, net_U19004_Pad12, __A19_1__ALRT0, net_U19004_Pad12, net_U19005_Pad12, __A19_1__ALRT1, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U19006(net_U19005_Pad12, net_U19003_Pad6, net_U19006_Pad3, net_U19006_Pad4, WCH14_n, CHWL03_n, GND, net_U19006_Pad4, net_U19003_Pad8, net_U19003_Pad9, net_U19003_Pad8, net_U19003_Pad11, net_U19006_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U19007(CH1403, RCH14_n, net_U19006_Pad13, net_U19007_Pad12, net_U19007_Pad10, net_U19007_Pad6, GND, net_U19003_Pad9, GTSET_n, net_U19007_Pad10, F5ASB2_n, net_U19007_Pad12, net_U19006_Pad3, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U19008(net_U19007_Pad12, GOJAM, net_U19008_Pad3, GTSET, GOJAM, net_U19003_Pad11, GND, net_U19002_Pad5, net_U19008_Pad9, net_U19003_Pad11, net_U19007_Pad6, net_U19007_Pad6, GTONE, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U19009(net_U19008_Pad3, net_U19006_Pad3, net_U19003_Pad11, ALTM, F5ASB0_n, net_U19008_Pad3, GND, net_U19003_Pad11, net_U19008_Pad9, net_U19009_Pad10, net_U19009_Pad10, GTONE, net_U19008_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U19010(net_U19010_Pad1, CHWL01_n, WCH14_n, net_U19010_Pad4, net_U19010_Pad1, net_U19010_Pad6, GND, GTSET_n, net_U19010_Pad4, net_U19010_Pad10, net_U19010_Pad10, net_U19010_Pad12, net_U19010_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U19011(net_U19010_Pad4, CCH14, net_U19010_Pad13, GTONE, GOJAM, net_U19010_Pad12, GND, net_U19011_Pad13, net_U19011_Pad9, GTSET, GOJAM, net_U19010_Pad6, net_U19011_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U19012(net_U19012_Pad1, F5ASB2_n, net_U19010_Pad13, net_U19011_Pad9, net_U19012_Pad1, net_U19011_Pad13, GND, F5ASB0_n, net_U19011_Pad9, OTLNKM, net_U19010_Pad6, net_U19011_Pad13, net_U19012_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U19013(CH1401, net_U19012_Pad13, RCH14_n, net_U19002_Pad11, net_U19012_Pad1, net_U19013_Pad6, GND, CA5_n, CXB7_n, net_U19002_Pad9, SB0_n, F05A_n, __A19_1__F5ASB0, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U19014(BR1_n, __A19_1__SH3MS_n, net_U19002_Pad8, __A19_1__SH3MS_n, BR1, __A19_1__OTLNK1, GND, net_U19014_Pad8, net_U19014_Pad9, __A19_1__UPL0_n, __A19_1__BLKUPL, net_U19013_Pad6, net_U19002_Pad8, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U19015(F5ASB2, F05A_n, SB2_n, __A19_1__F5BSB2, SB2_n, F05B_n, GND, __A19_1__XLNK0_n, net_U19015_Pad12, net_U19015_Pad10, __A19_1__XLNK1_n, net_U19015_Pad12, net_U19015_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 1'b1) U19016(F5ASB2, F5ASB2_n, __A19_1__F5BSB2, F5BSB2_n, C45R, __A19_1__C45R_n, GND, net_U19016_Pad8, net_U19016_Pad9, net_U19016_Pad10, net_U19016_Pad11, __A19_1__UPL0_n, UPL0, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U19017(__A19_1__BLKUPL, net_U19014_Pad9, net_U19017_Pad3, net_U19017_Pad10, net_U19017_Pad11, INLNKM, GND, INLNKP, net_U19017_Pad9, net_U19017_Pad10, net_U19017_Pad11, net_U19017_Pad12, __A19_1__UPL1_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b1, 1'b0, 1'b0) U19018(net_U19017_Pad3, net_U19014_Pad8, net_U19015_Pad10, net_U19017_Pad9, net_U19017_Pad12, net_U19015_Pad13, GND, __A19_1__C45R_n, net_U19018_Pad13, net_U19018_Pad10, net_U19018_Pad10, net_U19018_Pad12, net_U19018_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 #(1'b1, 1'b0) U19019(net_U19019_Pad1, net_U19014_Pad8, net_U19017_Pad12, net_U19015_Pad10, net_U19015_Pad13, , GND, , CA2_n, XB5_n, WOVR_n, OVF_n, T2P, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U19020(net_U19018_Pad12, net_U19018_Pad10, net_U19017_Pad11, net_U19017_Pad11, net_U19018_Pad12, F04A, GND, BR1_n, __A19_1__C45R_n, UPRUPT, net_U19018_Pad12, net_U19019_Pad1, net_U19020_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U19021(net_U19021_Pad1, net_U19020_Pad13, net_U19021_Pad3, CH3311, net_U19021_Pad3, RCH33_n, GND, RCH33_n, __A19_1__BLKUPL, CH3310, CHWL05_n, WCH13_n, net_U19021_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U19022(net_U19015_Pad12, net_U19021_Pad13, net_U19014_Pad9, net_U19014_Pad9, net_U19015_Pad12, CCH13, GND, net_U19015_Pad12, RCH13_n, CH1305, WCH13_n, CHWL06_n, net_U19022_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U19023(net_U19023_Pad1, net_U19022_Pad13, net_U19017_Pad10, net_U19017_Pad10, net_U19023_Pad1, CCH13, GND, net_U19023_Pad1, RCH13_n, CH1306, CA5_n, XB5_n, net_U19016_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U19024(net_U19021_Pad1, CCH33, CCHG_n, XT3_n, XB3_n, CCH33, GND, net_U19024_Pad8, net_U19024_Pad9, net_U19024_Pad10, CCH14, net_U19021_Pad3, GOJAM, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b0, 1'b1) U19025(net_U19025_Pad1, net_U19016_Pad8, POUT_n, net_U19025_Pad4, net_U19016_Pad8, MOUT_n, GND, net_U19016_Pad8, ZOUT_n, net_U19024_Pad10, net_U19025_Pad11, net_U19024_Pad8, net_U19024_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b0, 1'b1) U19026(net_U19025_Pad11, WCH14_n, CHWL04_n, CH1404, RCH14_n, net_U19024_Pad9, GND, net_U19024_Pad9, F5ASB2_n, THRSTD, net_U19025_Pad1, net_U19026_Pad12, net_U19026_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U19027(net_U19026_Pad12, net_U19026_Pad13, net_U19024_Pad9, net_U19027_Pad4, net_U19025_Pad4, net_U19027_Pad10, GND, net_U19027_Pad4, net_U19024_Pad9, net_U19027_Pad10, net_U19026_Pad13, F5ASB0_n, __A19_1__THRSTp, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U19028(__A19_1__THRSTm, net_U19027_Pad4, F5ASB0_n, net_U19016_Pad11, CA5_n, XB6_n, GND, net_U19016_Pad10, POUT_n, net_U19028_Pad10, WCH14_n, CHWL05_n, net_U19028_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U19029(net_U19029_Pad1, net_U19016_Pad10, MOUT_n, net_U19029_Pad4, net_U19016_Pad10, ZOUT_n, GND, net_U19028_Pad13, net_U19029_Pad9, net_U19029_Pad10, RCH14_n, net_U19029_Pad10, CH1405, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U19030(net_U19029_Pad10, net_U19029_Pad4, net_U19030_Pad3, net_U19030_Pad4, CCH14, net_U19030_Pad6, GND, net_U19030_Pad8, SB1_n, net_U19030_Pad10, net_U19030_Pad11, net_U19029_Pad9, CCH14, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U19031(EMSD, net_U19029_Pad10, F5ASB2_n, net_U19031_Pad4, net_U19028_Pad10, net_U19031_Pad10, GND, net_U19031_Pad4, net_U19029_Pad10, net_U19031_Pad10, net_U19029_Pad1, net_U19031_Pad12, net_U19031_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U19032(net_U19031_Pad12, net_U19031_Pad13, net_U19029_Pad10, __A19_1__EMSp, net_U19031_Pad4, F5ASB0_n, GND, net_U19031_Pad13, F5ASB0_n, __A19_1__EMSm, CHWL09_n, WCH11_n, net_U19032_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b1, 1'b1, 1'b1, 1'b0, 1'b0) U19033(BLKUPL_n, __A19_1__BLKUPL, UPL1, __A19_1__UPL1_n, XLNK0, __A19_1__XLNK0_n, GND, __A19_1__XLNK1_n, XLNK1, __A19_2__OUTCOM, __A19_2__FF1109_n, ERRST, net_U19033_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U19034(__A19_2__FF1109_n, net_U19032_Pad13, net_U19034_Pad3, net_U19034_Pad3, __A19_2__FF1109_n, CCH11, GND, RCH11_n, __A19_2__FF1109_n, CH1109, CHWL10_n, WCH11_n, net_U19034_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U19035(__A19_2__FF1110_n, net_U19034_Pad13, net_U19035_Pad3, net_U19035_Pad3, __A19_2__FF1110_n, CCH11, GND, CAURST, net_U19034_Pad13, net_U19033_Pad13, RCH11_n, __A19_2__FF1110_n, CH1110, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U19036(__A19_2__FF1110_n, __A19_2__OT1110, __A19_2__FF1111_n, __A19_2__OT1111, __A19_2__FF1112_n, __A19_2__OT1112, GND, net_U19036_Pad8, net_U19030_Pad8, net_U19036_Pad10, net_U19036_Pad11, net_U19036_Pad12, net_U19036_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U19037(net_U19037_Pad1, CHWL11_n, WCH11_n, __A19_2__FF1111_n, net_U19037_Pad1, net_U19037_Pad10, GND, __A19_2__FF1111_n, CCH11, net_U19037_Pad10, RCH11_n, __A19_2__FF1111_n, CH1111, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U19038(net_U19038_Pad1, CHWL12_n, WCH11_n, __A19_2__FF1112_n, net_U19038_Pad1, net_U19038_Pad10, GND, __A19_2__FF1112_n, CCH11, net_U19038_Pad10, RCH11_n, __A19_2__FF1112_n, CH1112, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U19039(net_U19039_Pad1, CHWL10_n, WCH14_n, net_U19030_Pad3, net_U19039_Pad1, net_U19030_Pad6, GND, RCH14_n, net_U19030_Pad3, CH1410, CHWL09_n, WCH14_n, net_U19039_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U19040(net_U19040_Pad1, net_U19039_Pad13, net_U19040_Pad3, net_U19040_Pad3, net_U19040_Pad1, CCH14, GND, RCH14_n, net_U19040_Pad1, CH1409, CHWL08_n, WCH14_n, net_U19040_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U19041(net_U19041_Pad1, net_U19040_Pad13, net_U19030_Pad10, net_U19030_Pad10, net_U19041_Pad1, CCH14, GND, RCH14_n, net_U19041_Pad1, CH1408, CHWL07_n, WCH14_n, net_U19041_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U19042(net_U19030_Pad11, net_U19041_Pad13, net_U19042_Pad3, net_U19042_Pad3, net_U19030_Pad11, CCH14, GND, RCH14_n, net_U19030_Pad11, CH1407, CHWL06_n, WCH14_n, net_U19042_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U19043(net_U19043_Pad1, net_U19042_Pad13, net_U19043_Pad3, net_U19043_Pad3, net_U19043_Pad1, CCH14, GND, RCH14_n, net_U19043_Pad1, CH1406, net_U19030_Pad3, F5ASB2_n, GYROD, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U19044(SB1_n, net_U19042_Pad3, SB1_n, net_U19041_Pad1, net_U19030_Pad11, net_U19036_Pad13, GND, net_U19044_Pad8, net_U19044_Pad9, net_U19044_Pad10, net_U19044_Pad11, net_U19036_Pad11, net_U19041_Pad1, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U19045(__A19_2__GYENAB, SB1_n, net_U19043_Pad1, __A19_2__GYXP, net_U19040_Pad3, net_U19036_Pad8, GND, net_U19036_Pad8, net_U19040_Pad1, __A19_2__GYXM, net_U19040_Pad3, net_U19036_Pad10, __A19_2__GYYP, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U19046(__A19_2__GYYM, net_U19036_Pad10, net_U19040_Pad1, __A19_2__GYZP, net_U19040_Pad3, net_U19036_Pad12, GND, net_U19036_Pad12, net_U19040_Pad1, __A19_2__GYZM, CA4_n, XB7_n, net_U19046_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b1, 1'b0, 1'b1, 1'b1, 1'b0) U19047(net_U19046_Pad13, net_U19047_Pad2, net_U19047_Pad3, __A19_2__O44, F06B, __A19_2__F06B_n, GND, __A19_2__F07D_n, net_U19047_Pad9, __A19_2__F07C_n, net_U19047_Pad11, __A19_2__F7CSB1_n, net_U19047_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b0, 1'b1) U19048(net_U19044_Pad10, POUT_n, net_U19047_Pad2, net_U19044_Pad11, MOUT_n, net_U19047_Pad2, GND, ZOUT_n, net_U19047_Pad2, net_U19030_Pad4, net_U19030_Pad3, net_U19044_Pad8, net_U19044_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b0, 1'b1) U19049(__A19_2__GYRRST, F5ASB2_n, net_U19044_Pad9, __A19_2__GYRSET, F5ASB2_n, net_U19044_Pad8, GND, CHWL08_n, WCH13_n, net_U19049_Pad10, net_U19049_Pad10, net_U19047_Pad3, net_U19049_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b0, 1'b1) U19050(net_U19047_Pad3, net_U19049_Pad13, CCH13, CH1308, RCH13_n, net_U19049_Pad13, GND, WCH13_n, CHWL09_n, net_U19050_Pad10, net_U19050_Pad10, net_U19050_Pad12, net_U19050_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U19051(net_U19051_Pad1, net_U19051_Pad2, net_U19051_Pad3, CH1309, RCH13_n, net_U19050_Pad13, GND, net_U19050_Pad13, __A19_2__F07D_n, net_U19051_Pad10, FS07_n, __A19_2__F06B_n, net_U19047_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U19052(net_U19047_Pad11, __A19_2__F06B_n, FS07A, net_U19047_Pad13, __A19_2__F07C_n, SB1_n, GND, net_U19051_Pad10, net_U19052_Pad13, net_U19052_Pad10, net_U19052_Pad10, F07B, net_U19052_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U19053(SB2_n, net_U19052_Pad10, net_U19050_Pad13, CCH13, __A19_2__RHCGO, net_U19050_Pad12, GND, net_U19053_Pad8, net_U19053_Pad9, __A19_2__F07C_n, SB0_n, __A19_2__RHCGO, __A19_2__F07C_n, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0) U19054(net_U19052_Pad13, net_U19053_Pad9, SB2, __A19_2__CNTRSB_n, F10B, __A19_2__F10B_n, GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC27 U19055(SIGNX, net_U19053_Pad9, SIGNY, net_U19053_Pad9, __A19_2__F7CSB1_n, net_U19055_Pad6, GND, net_U19055_Pad8, SIGNZ, net_U19053_Pad9, __A19_2__F7CSB1_n, net_U19051_Pad2, __A19_2__F7CSB1_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U19056(net_U19051_Pad3, net_U19051_Pad1, net_U19053_Pad8, net_U19056_Pad4, net_U19055_Pad6, net_U19056_Pad10, GND, net_U19056_Pad4, net_U19053_Pad8, net_U19056_Pad10, net_U19055_Pad8, net_U19056_Pad12, net_U19056_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U19057(net_U19056_Pad12, net_U19056_Pad13, net_U19053_Pad8, net_U19057_Pad4, BMGXP, net_U19057_Pad6, GND, BMGXM, net_U19057_Pad9, net_U19057_Pad10, BMGYP, net_U19057_Pad12, net_U19057_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U19058(F5ASB2_n, net_U19051_Pad1, F5ASB2_n, net_U19051_Pad3, GATEX_n, net_U19057_Pad9, GND, net_U19057_Pad12, F5ASB2_n, net_U19056_Pad4, GATEY_n, net_U19057_Pad6, GATEX_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U19059(F5ASB2_n, net_U19056_Pad10, F5ASB2_n, net_U19056_Pad13, GATEZ_n, net_U19059_Pad6, GND, net_U19059_Pad8, F5ASB2_n, net_U19056_Pad12, GATEZ_n, net_U19059_Pad12, GATEY_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U19060(net_U19060_Pad1, BMGYM, net_U19059_Pad12, net_U19060_Pad4, BMGZP, net_U19059_Pad6, GND, BMGZM, net_U19059_Pad8, net_U19060_Pad10, __A19_2__O44, net_U19057_Pad4, BMAGXP, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U19061(BMAGXM, __A19_2__O44, net_U19057_Pad10, BMAGYP, __A19_2__O44, net_U19057_Pad13, GND, __A19_2__O44, net_U19060_Pad1, BMAGYM, __A19_2__O44, net_U19060_Pad4, BMAGZP, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U19062(BMAGZM, __A19_2__O44, net_U19060_Pad10, T1P, __A19_2__CNTRSB_n, __A19_2__F10B_n, GND, __A19_2__F10B_n, __A19_2__CNTRSB_n, T3P, F10A_n, __A19_2__CNTRSB_n, T5P, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U19063(FS10, F09B_n, __A19_2__F06B_n, T6ON_n, __A19_2__CNTRSB_n, T6P, GND, , , , , T4P, __A19_2__CNTRSB_n, p4VSW, SIM_RST, SIM_CLK);
endmodule |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// This module defines the LDEXP function, which multiplies a floating point number by 2^(shift_in).
// The result is a valid floating point number within single-precision range, +/- INF or 0.
// If a denormalized number is supplied as input, the result will be zero (until we add denormalized
// number support).
//
module acl_fp_ldexp(clock, resetn, dataa, datab, enable, result);
input clock, resetn;
input [31:0] dataa;
input [31:0] datab;
input enable;
output [31:0] result;
// Cycle 1: Test inputs and compute resulting exponents.
wire [7:0] exponent_in = dataa[30:23];
wire [22:0] mantissa_in = dataa[22:0];
wire sign_in = dataa[31];
wire [31:0] shift_in = datab;
wire [31:0] intermediate_exp = shift_in + exponent_in;
reg [7:0] exp_stage_1;
reg [22:0] man_stage_1;
reg sign_stage_1;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
exp_stage_1 <= 8'dx;
man_stage_1 <= 23'dx;
sign_stage_1 <= 1'bx;
end
else if (enable)
begin
sign_stage_1 <= sign_in;
if (exponent_in == 8'hff)
begin
// NaN / Inf input, so produce an NaN / Inf output.
man_stage_1 <= mantissa_in;
exp_stage_1 <= exponent_in;
end
else
if (intermediate_exp[31] | (exponent_in == 8'd0))
begin
man_stage_1 <= 23'd0;
exp_stage_1 <= 8'd0;
end
else if ({1'b0, intermediate_exp[30:0]} >= 255)
begin
// infinity
man_stage_1 <= 23'd0;
exp_stage_1 <= 8'hff;
end
else if (intermediate_exp[7:0] == 8'd0)
begin
// zero
man_stage_1 <= 23'd0;
exp_stage_1 <= 8'h00;
end
else
begin
man_stage_1 <= mantissa_in;
exp_stage_1 <= intermediate_exp[7:0];
end
end
end
assign result = {sign_stage_1, exp_stage_1, man_stage_1};
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/29/2016 05:57:16 AM
// Design Name:
// Module Name: Testbench_FPU_Add_Subt
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Testbench_FPU();
parameter PERIOD = 10;
`ifdef SINGLE
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR = 26;
parameter EWR = 5;//
`endif
`ifdef DOUBLE
parameter W = 64;
parameter EW = 11;
parameter SW = 52;
parameter SWR = 55;
parameter EWR = 6;
`endif
reg clk;
//INPUT signals
reg rst;
reg beg_FSM;
reg ack_FSM;
//Oper_Start_in signals
reg [W-1:0] Data_X;
reg [W-1:0] Data_Y;
reg add_subt;
//Round signals signals
reg [1:0] r_mode;
//OUTPUT SIGNALS
wire overflow_flag;
wire underflow_flag;
wire ready;
wire [W-1:0] final_result_ieee;
FPU_Add_Subtract_Function #(
.W(W),
.EW(EW),
.SW(SW),
.SWR(SWR),
.EWR(EWR)
) FPADDSUB (
.clk (clk),
.rst (rst),
.beg_FSM (beg_FSM),
.ack_FSM (ack_FSM),
.Data_X (Data_X),
.Data_Y (Data_Y),
.add_subt (add_subt),
.r_mode (r_mode),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.ready (ready),
.final_result_ieee (final_result_ieee)
);
reg [W-1:0] Array_IN_1 [0:((2**PERIOD)-1)];
reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
beg_FSM = 0;
ack_FSM = 0;
Data_X = 0;
Data_Y = 0;
r_mode = 2'b00;
//Abre el archivo testbench
// FileSaveData = $fopen("vector/add_single/ResultadoXilinxFLM.txt","w");
// $readmemh("vector/add_single/Hexadecimal_A.txt", Array_IN_1);
// $readmemh("vector/add_single/Hexadecimal_B.txt", Array_IN_2);
add_subt = 0;
FileSaveData = $fopen("ResultadoXilinxFLM_SUMA.txt","w");
$readmemh("Hexadecimal_A.txt", Array_IN_1);
$readmemh("Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
add_subt = 1;
FileSaveData = $fopen("ResultadoXilinxFLM_RESTA.txt","w");
$readmemh("Hexadecimal_A.txt", Array_IN_1);
$readmemh("Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
#100 rst = 0;
$finish;
//Add stimulus here
end
//******************************* Se ejecuta el CLK ************************
initial forever #5 clk = ~clk;
task run_Arch2;
input integer FDataO;
input integer Vector_size;
begin
rst = 0;
#15 rst = 1;
#15 rst = 0;
beg_FSM = 0;
ack_FSM = 0;
contador = 0;
repeat(Vector_size) @(negedge clk) begin
//input the new values inside the operator
Data_X = Array_IN_1[contador];
Data_Y = Array_IN_2[contador];
#(PERIOD/4) beg_FSM = 1;
//Wait for the operation ready
@(posedge ready) begin
#(PERIOD+2);
ack_FSM = 1;
#4;
$fwrite(FDataO,"%h\n",final_result_ieee);
end
@(negedge clk) begin
ack_FSM = 0;
end
contador = contador + 1;
end
$fclose(FDataO);
end
endtask
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_mask_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// testbench_9.v
////////////////////////////////////////////////////////////////////////////////
// CPU testbench using the suggested program of lab 9
////////////////////////////////////////////////////////////////////////////////
// Dimitrios Paraschas ([email protected])
////////////////////////////////////////////////////////////////////////////////
// inf.uth.gr
// ce232 Computer Organization and Design
////////////////////////////////////////////////////////////////////////////////
// lab 9
// implementation of a subset of MIPS instruction five stages pipeline CPU
////////////////////////////////////////////////////////////////////////////////
`include "constants.h"
`timescale 1ns/1ps
// modules
////////////////////////////////////////////////////////////////////////////////
module cpu_tb;
// unchangeable parameters
// http://www.edaboard.com/thread194570.html
localparam N_REGISTERS = 32;
localparam IMS = 64;
localparam DMS = 32;
reg clock, reset; // clock and reset signals
integer i;
integer tests_passed;
// CPU (clock, reset);
// module with multiple parameters
// http://www.asic-world.com/verilog/para_modules1.html
CPU #(
.INSTR_MEM_SIZE(IMS),
.DATA_MEM_SIZE(DMS)
) CPU_0 (
.clock(clock),
.reset(reset)
);
always begin
#5;
clock = ~clock;
end
initial begin
// specify a VCD dump file and variables
// http://verilog.renerta.com/source/vrg00056.htm
$dumpfile("dumpfile_9.vcd");
$dumpvars(0, cpu_tb);
for (i = 0; i < N_REGISTERS; i = i + 1)
$dumpvars(1, CPU_0.Registers_0.data[i]);
for (i = 0; i < IMS; i = i + 1)
$dumpvars(1, CPU_0.InstructionMemory_0.data[i]);
for (i = 0; i < DMS; i = i + 1)
$dumpvars(1, CPU_0.DataMemory_0.data[i]);
// clock and reset signals
clock = 1;
reset = 0;
// initialize the data memory
for (i = 0; i < DMS; i = i + 1)
CPU_0.DataMemory_0.data[i] = i;
// load the program to the instruction memory
//$readmemh("program_9.mhex", CPU_0.InstructionMemory_0.data);
$readmemb("program_9.mbin", CPU_0.InstructionMemory_0.data);
$display("\n");
$display("Program 9 loaded and running.\n");
// TODO
// zero waiting time is preferred
//#0;
#5;
reset = 1;
// initialize the registers
for (i = 0; i < N_REGISTERS; i = i + 1)
CPU_0.Registers_0.data[i] = i;
#65;
#65;
#5;
#30;
#10;
#20;
tests_passed = 0;
// verify that the registers have the correct values
$display("\n");
if ((CPU_0.Registers_0.data[1] == 1) &&
(CPU_0.Registers_0.data[2] == 28) &&
(CPU_0.Registers_0.data[3] == 3) &&
(CPU_0.Registers_0.data[4] == 30) &&
(CPU_0.Registers_0.data[5] == 5) &&
(CPU_0.Registers_0.data[6] == 6) &&
(CPU_0.Registers_0.data[7] == 7) &&
(CPU_0.Registers_0.data[8] == 24) &&
(CPU_0.Registers_0.data[9] == 58) &&
(CPU_0.Registers_0.data[10] == 10) &&
(CPU_0.Registers_0.data[11] == 11) &&
(CPU_0.Registers_0.data[12] == 12) &&
(CPU_0.Registers_0.data[13] == 31) &&
(CPU_0.Registers_0.data[14] == 31) &&
(CPU_0.Registers_0.data[15] == 15) &&
(CPU_0.Registers_0.data[16] == 16) &&
(CPU_0.Registers_0.data[17] == 17) &&
(CPU_0.Registers_0.data[18] == 18) &&
(CPU_0.Registers_0.data[19] == 16) &&
(CPU_0.Registers_0.data[20] == 20) &&
(CPU_0.Registers_0.data[21] == 21) &&
(CPU_0.Registers_0.data[22] == 22) &&
(CPU_0.Registers_0.data[23] == 23) &&
(CPU_0.Registers_0.data[24] == 24) &&
(CPU_0.Registers_0.data[25] == 25) &&
(CPU_0.Registers_0.data[26] == 26) &&
(CPU_0.Registers_0.data[27] == 27) &&
(CPU_0.Registers_0.data[28] == 28) &&
(CPU_0.Registers_0.data[29] == 1) &&
(CPU_0.Registers_0.data[30] == 30) &&
(CPU_0.Registers_0.data[31] == 31)) begin
tests_passed = tests_passed + 1;
$display("Registers OK. All values are correct.");
end // if
else begin
$display("Registers mismatch. Wrong values.");
end // else
$display("\n");
// verify that the memory locations have the correct values
if ((CPU_0.DataMemory_0.data[0] == 0) &&
(CPU_0.DataMemory_0.data[1] == 1) &&
(CPU_0.DataMemory_0.data[2] == 2) &&
(CPU_0.DataMemory_0.data[3] == 3) &&
(CPU_0.DataMemory_0.data[4] == 4) &&
(CPU_0.DataMemory_0.data[5] == 5) &&
(CPU_0.DataMemory_0.data[6] == 6) &&
(CPU_0.DataMemory_0.data[7] == 7) &&
(CPU_0.DataMemory_0.data[8] == 28) &&
(CPU_0.DataMemory_0.data[9] == 9) &&
(CPU_0.DataMemory_0.data[10] == 10) &&
(CPU_0.DataMemory_0.data[11] == 11) &&
(CPU_0.DataMemory_0.data[12] == 31) &&
(CPU_0.DataMemory_0.data[13] == 13) &&
(CPU_0.DataMemory_0.data[14] == 14) &&
(CPU_0.DataMemory_0.data[15] == 15) &&
(CPU_0.DataMemory_0.data[16] == 16) &&
(CPU_0.DataMemory_0.data[17] == 17) &&
(CPU_0.DataMemory_0.data[18] == 18) &&
(CPU_0.DataMemory_0.data[19] == 19) &&
(CPU_0.DataMemory_0.data[20] == 20) &&
(CPU_0.DataMemory_0.data[21] == 21) &&
(CPU_0.DataMemory_0.data[22] == 22) &&
(CPU_0.DataMemory_0.data[23] == 23) &&
(CPU_0.DataMemory_0.data[24] == 24) &&
(CPU_0.DataMemory_0.data[25] == 25) &&
(CPU_0.DataMemory_0.data[26] == 26) &&
(CPU_0.DataMemory_0.data[27] == 27) &&
(CPU_0.DataMemory_0.data[28] == 28) &&
(CPU_0.DataMemory_0.data[29] == 29) &&
(CPU_0.DataMemory_0.data[30] == 30) &&
(CPU_0.DataMemory_0.data[31] == 31)) begin
tests_passed = tests_passed + 1;
$display("DataMemory OK. All values are correct.");
end // if
else begin
$display("DataMemory mismatch. Wrong values.");
end // else
$display("\n");
if (tests_passed == 2)
$display("Program 9 successfully run.");
else
$display("Program 9 has failed.");
$display("\n");
$finish;
end // initial
endmodule
////////////////////////////////////////////////////////////////////////////////
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:09:17 06/06/2009
// Design Name:
// Module Name: RCB_FRL_COUNT_TO_64
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RCB_FRL_COUNT_TO_64(
input clk,
input rst,
input count,
input ud,
output reg [5:0] counter_value /*synthesis syn_noprune = 1*/
);
//This module counts up/down between 0 to 63
wire [5:0] counter_value_preserver;
// reg [5:0] counter_value/*synthesis syn_noprune = 1*/;
always@(posedge clk or posedge rst) begin
if(rst == 1'b1)
counter_value = 6'h00;
else begin
case({count,ud})
2'b00: counter_value = counter_value_preserver;
2'b01: counter_value = counter_value_preserver;
2'b10: counter_value = counter_value_preserver - 1;
2'b11: counter_value = counter_value_preserver + 1;
default: counter_value = 6'h00;
endcase
end
end
assign counter_value_preserver = counter_value;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Wojtek Gumua
//
// Create Date: 21:20:55 05/11/2015
// Design Name:
// Module Name: circle
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module circle #
(
parameter [9:0] IMG_W = 720,
parameter [9:0] IMG_H = 576
)
(
input clk,
input ce,
input rst,
input de,
input hsync,
input vsync,
input mask,
output [9:0] x,
output [9:0] y,
output inside_circle,
output [9:0] c_h,
output [9:0] c_w
);
//implementacja licznikow
reg [9:0] curr_w = 0;
reg [9:0] curr_h = 0;
wire eof;
wire p_vsync;
delay #
(
.DELAY(1),
.N(1)
)
delay_vsync
(
.d(vsync),
.ce(1'b1),
.clk(clk),
.q(p_vsync)
);
always @(posedge clk)
begin
if (vsync == 0) begin
curr_w <= 0;
curr_h <= 0;
end
else if(de == 1) begin
curr_w <= curr_w + 1;
if (curr_w == IMG_W - 1) begin
curr_w <= 0;
curr_h <= curr_h + 1;
if (curr_h == IMG_H - 1) begin
curr_h <= 0;
end
end
end
end
assign eof = (p_vsync == 1'b1 && vsync == 1'b0) ? 1'b1 : 1'b0;
//wyliczanie m00
reg [27:0] count_m00 = 0;
wire [27:0] count_m10;
wire [27:0] count_m01;
always @(posedge clk)
begin
if(eof) count_m00 <= 0;
else count_m00 <= count_m00 + ((mask && de) ? 28'd1 : 2'd0);
end
wire d_mask;
wire d_eof;
delay #
(
.DELAY(1),
.N(1)
)
delay_mask
(
.d(mask),
.ce(1'b1),
.clk(clk),
.q(d_mask)
);
delay #
(
.DELAY(1),
.N(1)
)
delay_eof
(
.d(eof),
.ce(1'b1),
.clk(clk),
.q(d_eof)
);
summator sum_m10
(
.A(curr_w),
.clk(clk),
.ce((mask && de)),
.rst(eof),
.Y(count_m10)
);
summator sum_m01
(
.A(curr_h),
.clk(clk),
.ce((mask && de)),
.rst(eof),
.Y(count_m01)
);
wire [27:0] d_x;
wire [27:0] d_y;
wire qv_x;
wire qv_y;
divider_28_20 div_x
(
.clk(clk),
.start(eof),
.dividend({count_m10}),
.divisor({count_m00}),
.quotient(d_x),
.qv(qv_x)
);
divider_28_20 div_y
(
.clk(clk),
.start(eof),
.dividend({count_m01}),
.divisor({count_m00}),
.quotient(d_y),
.qv(qv_y)
);
reg [9:0] x_latch = 0;
reg [9:0] y_latch = 0;
always @(posedge clk)
begin
if(qv_x) x_latch = d_x[9:0];
if(qv_y) y_latch = d_y[9:0];
end
//wyznacz czy wewnatrz kola
assign inside_circle = (((x_latch - curr_w) * (x_latch - curr_w) + (y_latch - curr_h) * (y_latch - curr_h)) < 50) ? 1'b1 : 1'b0;
assign x = x_latch;
assign y = y_latch;
assign c_h = curr_h;
assign c_w = curr_w;
endmodule
|
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=2 clk0_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=pll100M" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 11.1 cbx_altclkbuf 2011:10:31:21:11:05:SJ cbx_altiobuf_bidir 2011:10:31:21:11:05:SJ cbx_altiobuf_in 2011:10:31:21:11:05:SJ cbx_altiobuf_out 2011:10:31:21:11:05:SJ cbx_altpll 2011:10:31:21:11:05:SJ cbx_cycloneii 2011:10:31:21:11:05:SJ cbx_lpm_add_sub 2011:10:31:21:11:05:SJ cbx_lpm_compare 2011:10:31:21:11:05:SJ cbx_lpm_decode 2011:10:31:21:11:05:SJ cbx_lpm_mux 2011:10:31:21:11:05:SJ cbx_mgl 2011:10:31:21:12:31:SJ cbx_stratix 2011:10:31:21:11:05:SJ cbx_stratixii 2011:10:31:21:11:05:SJ cbx_stratixiii 2011:10:31:21:11:05:SJ cbx_stratixv 2011:10:31:21:11:05:SJ cbx_util_mgl 2011:10:31:21:11:05:SJ VERSION_END
//CBXI_INSTANCE_NAME="dds_gen_pll100M_gen_100MHz_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = cycloneive_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module pll100M_altpll
(
clk,
inclk) /* synthesis synthesis_clearbox=1 */;
output [4:0] clk;
input [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
cycloneive_pll pll1
(
.activeclock(),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 1,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 2,
pll1.clk0_phase_shift = "0",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]};
endmodule //pll100M_altpll
//VALID FILE
|
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_convert_to_ieee_double(clock, resetn, mantissa, exponent, sign, result, valid_in, valid_out, stall_in, stall_out, enable);
input clock, resetn;
input [55:0] mantissa;
input [11:0] exponent;
input sign;
output [63:0] result;
input valid_in, stall_in, enable;
output valid_out, stall_out;
parameter FINITE_MATH_ONLY = 1;
assign valid_out = valid_in;
assign stall_out = stall_in;
generate
if (FINITE_MATH_ONLY == 0)
assign result = {sign, {11{exponent[11]}} | exponent[10:0], mantissa[54:3]};
else
assign result = {sign, exponent[10:0], mantissa[54:3]};
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Baud Generator Core
// Paul Mumby 2012
// Originally derived from code examples at:
// http://www.fpga4fun.com
//////////////////////////////////////////////////////////////////////////////////
module uart_baudgenerator(
clk,
baudtick
);
//Parameters:
//================================================
parameter CLOCK = 25000000; // 25MHz
parameter BAUD = 9600;
parameter ACCWIDTH = 16;
parameter ROUNDBITS = 5;
parameter INC = ((BAUD<<(ACCWIDTH-(ROUNDBITS-1)))+(CLOCK>>ROUNDBITS))/(CLOCK>>(ROUNDBITS-1));
//IO Definitions:
//================================================
input clk;
output baudtick;
//Register/Wire Definitions:
//================================================
reg [ACCWIDTH:0] accumulator = 0;
//BUFG Instatiation:
//================================================
//Module Instantiation:
//================================================
//Assignments:
//================================================
assign baudtick = accumulator[ACCWIDTH];
//Toplevel Logic:
//================================================
always @(posedge clk)
accumulator <= accumulator[ACCWIDTH-1:0] + INC;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: read_data_path.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This is top level of read path and also consist of comparison logic
// for read data.
//Reference:
//Revision History: 11/18 /2011 Fixed a localparam ER_WIDTH bug for QDR2+ case.
// 03/15/2012 Registered error_byte, error_bit to avoid false
// comparison when data_valid_i is deasserted.
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_read_data_path #(
parameter TCQ = 100,
parameter START_ADDR = 32'h00000000,
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
parameter MEM_TYPE = "DDR3",
parameter FAMILY = "VIRTEX6",
parameter BL_WIDTH = 6,
parameter MEM_BURST_LEN = 8,
parameter ADDR_WIDTH = 32,
parameter CMP_DATA_PIPE_STAGES = 3,
parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 8,
parameter DWIDTH = nCK_PER_CLK * 2 * NUM_DQ_PINS,
parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
parameter MEM_COL_WIDTH = 10,
parameter SIMULATION = "FALSE"
)
(
input clk_i,
input [9:0] rst_i,
input manual_clear_error,
output cmd_rdy_o,
input cmd_valid_i,
input memc_cmd_full_i,
input [31:0] prbs_fseed_i,
input mode_load_i,
input [3:0] vio_instr_mode_value,
input [3:0] data_mode_i,
input [2:0] cmd_sent,
input [5:0] bl_sent ,
input cmd_en_i ,
// input [31:0] m_addr_i,
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
input [31:0] fixed_data_i,
input [31:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
output data_rdy_o,
input data_valid_i,
input [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_i,
output data_error_o, //data_error on user data bus side
output [DWIDTH-1:0] cmp_data_o,
output [DWIDTH-1:0] rd_mdata_o ,
output cmp_data_valid,
output [31:0] cmp_addr_o,
output [5 :0] cmp_bl_o,
output [NUM_DQ_PINS/8 - 1:0] dq_error_bytelane_cmp, // V6: real time compare error byte lane
output [NUM_DQ_PINS/8 - 1:0] cumlative_dq_lane_error_r, // V6: latched error byte lane that occure on
// first error
output reg [NUM_DQ_PINS - 1:0] cumlative_dq_r0_bit_error_r ,
output reg [NUM_DQ_PINS - 1:0] cumlative_dq_f0_bit_error_r ,
output reg [NUM_DQ_PINS - 1:0] cumlative_dq_r1_bit_error_r ,
output reg [NUM_DQ_PINS - 1:0] cumlative_dq_f1_bit_error_r ,
output reg [NUM_DQ_PINS-1:0] dq_r0_bit_error_r,
output reg [NUM_DQ_PINS-1:0] dq_f0_bit_error_r,
output reg [NUM_DQ_PINS-1:0] dq_r1_bit_error_r,
output reg [NUM_DQ_PINS-1:0] dq_f1_bit_error_r,
output reg [NUM_DQ_PINS - 1:0] dq_r0_read_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_f0_read_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_r1_read_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_f1_read_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_r0_expect_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_f0_expect_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_r1_expect_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_f1_expect_bit_r,
output [31:0] error_addr_o
);
wire gen_rdy;
wire gen_valid;
wire [31:0] gen_addr;
wire [BL_WIDTH-1:0] gen_bl;
wire cmp_rdy;
wire cmp_valid;
wire [31:0] cmp_addr;
wire [5:0] cmp_bl;
reg data_error;
wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] cmp_data;
wire [31:0] tg_st_addr_o;
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] cmp_data_r1,cmp_data_r2;
reg last_word_rd;
reg [5:0] bl_counter;
wire cmd_rdy;
wire user_bl_cnt_is_1;
wire data_rdy;
reg [DWIDTH:0] delayed_data;
wire rd_mdata_en;
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] rd_data_r1;
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] rd_data_r2;
reg force_wrcmd_gen;
reg wait_bl_end;
reg wait_bl_end_r1;
reg l_data_error ;
reg u_data_error;
reg v6_data_cmp_valid;
wire [DWIDTH -1 :0] rd_v6_mdata;
reg [DWIDTH -1 :0] cmpdata_r;
wire [DWIDTH -1 :0] rd_mdata;
reg cmp_data_en;
localparam ER_WIDTH = ( MEM_TYPE == "QDR2PLUS" && nCK_PER_CLK == 2) ? (NUM_DQ_PINS*MEM_BURST_LEN)/9 :
( MEM_TYPE != "QDR2PLUS" && nCK_PER_CLK == 2) ? NUM_DQ_PINS/2 : NUM_DQ_PINS;
reg [ER_WIDTH - 1:0] error_byte;
reg [ER_WIDTH - 1:0] error_byte_r1;
reg [NUM_DQ_PINS*nCK_PER_CLK*2 - 1:0] error_bit;
reg [NUM_DQ_PINS*nCK_PER_CLK*2 -1:0] error_bit_r1;
wire [NUM_DQ_PINS-1:0] dq_bit_error;
wire [NUM_DQ_PINS-1:0] cumlative_dq_bit_error_c;
wire [ NUM_DQ_PINS/8-1:0] dq_lane_error;
reg [ NUM_DQ_PINS/8-1:0] dq_lane_error_r1;
reg [ NUM_DQ_PINS/8-1:0] dq_lane_error_r2;
reg [NUM_DQ_PINS-1:0] dq_bit_error_r1;
wire [NUM_DQ_PINS-1:0] cumlative_dq_r0_bit_error_c;
wire [NUM_DQ_PINS-1:0] cumlative_dq_f0_bit_error_c;
wire [NUM_DQ_PINS-1:0] cumlative_dq_r1_bit_error_c;
wire [NUM_DQ_PINS-1:0] cumlative_dq_f1_bit_error_c;
wire [ NUM_DQ_PINS/8-1:0] cum_dq_lane_error_mask;
wire [ NUM_DQ_PINS/8-1:0] cumlative_dq_lane_error_c;
reg [ NUM_DQ_PINS/8-1:0] cumlative_dq_lane_error_reg;
reg [NUM_DQ_PINS - 1:0] dq_r0_read_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_f0_read_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_r1_read_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_f1_read_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_r0_expect_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_f0_expect_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_r1_expect_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_f1_expect_bit_rdlay1;
wire [NUM_DQ_PINS-1:0] dq_r0_bit_error ;
wire [NUM_DQ_PINS-1:0] dq_f0_bit_error ;
wire [NUM_DQ_PINS-1:0] dq_r1_bit_error ;
wire [NUM_DQ_PINS-1:0] dq_f1_bit_error ;
reg [31:0] error_addr_r1;
reg [31:0] error_addr_r2;
reg [31:0] error_addr_r3;
reg data_valid_r1;
reg data_valid_r2;
wire cmd_start_i;
always @ (posedge clk_i) begin
wait_bl_end_r1 <= #TCQ wait_bl_end;
rd_data_r1 <= #TCQ data_i;
rd_data_r2 <= #TCQ rd_data_r1;
end
reg [7:0] force_wrcmd_timeout_cnts ;
always @ (posedge clk_i) begin
if (rst_i[0])
force_wrcmd_gen <= #TCQ 1'b0;
else if ((wait_bl_end == 1'b0 && wait_bl_end_r1 == 1'b1) || force_wrcmd_timeout_cnts == 8'b11111111)
force_wrcmd_gen <= #TCQ 1'b0;
else if ((cmd_valid_i && bl_i > 16) || wait_bl_end )
force_wrcmd_gen <= #TCQ 1'b1;
end
always @ (posedge clk_i) begin
if (rst_i[0])
force_wrcmd_timeout_cnts <= #TCQ 'b0;
else if (wait_bl_end == 1'b0 && wait_bl_end_r1 == 1'b1)
force_wrcmd_timeout_cnts <= #TCQ 'b0;
else if (force_wrcmd_gen)
force_wrcmd_timeout_cnts <= #TCQ force_wrcmd_timeout_cnts + 1'b1;
end
always @ (posedge clk_i)
if (rst_i[0])
wait_bl_end <= #TCQ 1'b0;
else if (force_wrcmd_timeout_cnts == 8'b11111111)
wait_bl_end <= #TCQ 1'b0;
else if (gen_rdy && gen_valid && gen_bl > 16)
wait_bl_end <= #TCQ 1'b1;
else if (wait_bl_end && user_bl_cnt_is_1)
wait_bl_end <= #TCQ 1'b0;
assign cmd_rdy_o = cmd_rdy;
mig_7series_v1_9_read_posted_fifo #
(
.TCQ (TCQ),
.FAMILY (FAMILY),
.nCK_PER_CLK (nCK_PER_CLK),
.MEM_BURST_LEN (MEM_BURST_LEN),
.ADDR_WIDTH (32),
.BL_WIDTH (BL_WIDTH)
)
read_postedfifo(
.clk_i (clk_i),
.rst_i (rst_i[0]),
.cmd_rdy_o (cmd_rdy ),
.cmd_valid_i (cmd_valid_i ),
.data_valid_i (data_rdy ), // input to
.addr_i (addr_i ),
.bl_i (bl_i ),
.cmd_start_i (cmd_start),
.cmd_sent (cmd_sent),
.bl_sent (bl_sent ),
.cmd_en_i (cmd_en_i),
.memc_cmd_full_i (memc_cmd_full_i),
.gen_valid_o (gen_valid ),
.gen_addr_o (gen_addr ),
.gen_bl_o (gen_bl ),
.rd_mdata_en (rd_mdata_en)
);
mig_7series_v1_9_rd_data_gen #
(
.TCQ (TCQ),
.FAMILY (FAMILY),
.MEM_TYPE (MEM_TYPE),
.BL_WIDTH (BL_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.MEM_BURST_LEN (MEM_BURST_LEN),
.NUM_DQ_PINS (NUM_DQ_PINS),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.START_ADDR (START_ADDR),
.DATA_PATTERN (DATA_PATTERN),
.DWIDTH(DWIDTH),
.COLUMN_WIDTH (MEM_COL_WIDTH)
)
rd_datagen(
.clk_i (clk_i ),
.rst_i (rst_i[4:0]),
.prbs_fseed_i (prbs_fseed_i),
.data_mode_i (data_mode_i ),
.vio_instr_mode_value (vio_instr_mode_value),
.cmd_rdy_o (gen_rdy ),
.cmd_valid_i (gen_valid ),
.mode_load_i (mode_load_i),
.cmd_start_o (cmd_start),
// .m_addr_i (m_addr_i ),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.fixed_data_i (fixed_data_i),
.addr_i (gen_addr ),
.bl_i (gen_bl ),
.user_bl_cnt_is_1_o (user_bl_cnt_is_1),
.data_rdy_i (data_valid_i ), // input to
.data_valid_o (cmp_valid ),
.tg_st_addr_o (tg_st_addr_o),
.data_o (cmp_data )
);
mig_7series_v1_9_afifo #
(
.TCQ (TCQ),
.DSIZE (DWIDTH),
.FIFO_DEPTH (32),
.ASIZE (4),
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
)
rd_mdata_fifo
(
.wr_clk (clk_i),
.rst (rst_i[0]),
.wr_en (data_valid_i),
.wr_data (data_i),
.rd_en (rd_mdata_en),
.rd_clk (clk_i),
.rd_data (rd_v6_mdata),
.full (),
.empty (),
.almost_full ()
);
always @ (posedge clk_i)
begin
// delayed_data <= #TCQ {cmp_valid & data_valid_i,cmp_data};
cmp_data_r1 <= #TCQ cmp_data;
cmp_data_r2 <= #TCQ cmp_data_r1;
end
assign rd_mdata_o = rd_mdata;
assign rd_mdata = (FAMILY == "SPARTAN6") ? rd_data_r1:
(FAMILY == "VIRTEX6" && MEM_BURST_LEN == 4)? rd_v6_mdata:
rd_data_r2;
assign cmp_data_valid = (FAMILY == "SPARTAN6") ? cmp_data_en :
(FAMILY == "VIRTEX6" && MEM_BURST_LEN == 4)? v6_data_cmp_valid :data_valid_i;
assign cmp_data_o = cmp_data_r2;
assign cmp_addr_o = tg_st_addr_o;//gen_addr;
assign cmp_bl_o = gen_bl[5:0];
assign data_rdy_o = data_rdy;
assign data_rdy = cmp_valid & data_valid_i;
always @ (posedge clk_i)
v6_data_cmp_valid <= #TCQ rd_mdata_en;
always @ (posedge clk_i)
cmp_data_en <= #TCQ data_rdy;
genvar i;
generate
if (FAMILY == "SPARTAN6")
begin: gen_error_sp6
always @ (posedge clk_i)
begin
if (cmp_data_en)
l_data_error <= #TCQ (rd_data_r1[DWIDTH/2-1:0] != cmp_data_r1[DWIDTH/2-1:0]);
else
l_data_error <= #TCQ 1'b0;
if (cmp_data_en)
u_data_error <= #TCQ (rd_data_r1[DWIDTH-1:DWIDTH/2] != cmp_data_r1[DWIDTH-1:DWIDTH/2]);
else
u_data_error <= #TCQ 1'b0;
data_error <= #TCQ l_data_error | u_data_error;
//synthesis translate_off
if (data_error)
$display ("ERROR at time %t" , $time);
//synthesis translate_on
end
end
else
// if (FAMILY == "VIRTEX6" )
begin: gen_error_v7
if (nCK_PER_CLK == 2)
begin
if (MEM_TYPE == "QDR2PLUS")
begin: qdr_design
for (i = 0; i < (NUM_DQ_PINS*MEM_BURST_LEN)/9; i = i + 1)
begin: gen_cmp_2
always @ (posedge clk_i)
//synthesis translate_off
if (data_valid_i & (SIMULATION=="TRUE"))
error_byte[i] <= (data_i[9*(i+1)-1:9*i] !== cmp_data[9*(i+1)-1:9*i]) ;
else
//synthesis translate_on
if (data_valid_i)
error_byte[i] <= (data_i[9*(i+1)-1:9*i] != cmp_data[9*(i+1)-1:9*i]) ;
else
error_byte[i] <= 1'b0;
end
for (i = 0; i < NUM_DQ_PINS*MEM_BURST_LEN; i = i + 1)
begin: gen_cmp_bit_2
always @ (posedge clk_i)
//synthesis translate_off
if (data_valid_i & (SIMULATION=="TRUE"))
error_bit[i] <= (data_i[i] !== cmp_data[i]) ;
else
//synthesis translate_on
if (data_valid_i)
error_bit[i] <= (data_i[i] != cmp_data[i]) ;
else
error_bit[i] <= 1'b0;
end
end
else
begin: ddr_design
for (i = 0; i < NUM_DQ_PINS/2; i = i + 1)
begin: gen_cmp_2
always @ (posedge clk_i)
//synthesis translate_off
if (data_valid_i & (SIMULATION=="TRUE"))
error_byte[i] <= (data_i[8*(i+1)-1:8*i] !== cmp_data[8*(i+1)-1:8*i]) ;
else
//synthesis translate_on
if (data_valid_i)
error_byte[i] <= (data_i[8*(i+1)-1:8*i] != cmp_data[8*(i+1)-1:8*i]) ;
else
error_byte[i] <= 1'b0;
end
for (i = 0; i < NUM_DQ_PINS*4; i = i + 1)
begin: gen_cmp_bit_2
always @ (posedge clk_i)
//synthesis translate_off
if (data_valid_i & (SIMULATION=="TRUE"))
error_bit[i] <= ( (data_i[i] !== cmp_data[i]) ) ;
else
//synthesis translate_on
if (data_valid_i)
error_bit[i] <= ( (data_i[i] != cmp_data[i]) ) ;
else
error_bit[i] <= 1'b0;
end
end
end
else //nCK_PER_CLK == 4
begin
for (i = 0; i < NUM_DQ_PINS; i = i + 1)
begin: gen_cmp_4
always @ (posedge clk_i)
//synthesis translate_off
if (data_valid_i & (SIMULATION=="TRUE"))
error_byte[i] <= (data_i[8*(i+1)-1:8*i] !== cmp_data[8*(i+1)-1:8*i]) ;
else
//synthesis translate_on
if (data_valid_i)
error_byte[i] <= (data_i[8*(i+1)-1:8*i] != cmp_data[8*(i+1)-1:8*i]) ;
else
error_byte[i] <= 1'b0;
end
for (i = 0; i < NUM_DQ_PINS*8; i = i + 1)
begin: gen_cmp_bit_4
always @ (posedge clk_i)
//synthesis translate_off
if (data_valid_i & (SIMULATION=="TRUE"))
error_bit[i] <= (data_i[i] !== cmp_data[i]) ;
else
//synthesis translate_on
if (data_valid_i)
error_bit[i] <= (data_i[i] != cmp_data[i]) ;
else
error_bit[i] <= 1'b0;
end
end
always @ (posedge clk_i)
begin
dq_r0_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*1 - 1:0];
dq_f0_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*2 - 1:NUM_DQ_PINS*1];
dq_r1_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*3 - 1:NUM_DQ_PINS*2];
dq_f1_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*4 - 1:NUM_DQ_PINS*3];
dq_r0_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*1 - 1:0];
dq_f0_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*2 - 1:NUM_DQ_PINS*1];
dq_r1_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*3 - 1:NUM_DQ_PINS*2];
dq_f1_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*4 - 1:NUM_DQ_PINS*3];
dq_r0_read_bit_r <= #TCQ dq_r0_read_bit_rdlay1 ;
dq_f0_read_bit_r <= #TCQ dq_f0_read_bit_rdlay1 ;
dq_r1_read_bit_r <= #TCQ dq_r1_read_bit_rdlay1 ;
dq_f1_read_bit_r <= #TCQ dq_f1_read_bit_rdlay1 ;
dq_r0_expect_bit_r <= #TCQ dq_r0_expect_bit_rdlay1;
dq_f0_expect_bit_r <= #TCQ dq_f0_expect_bit_rdlay1;
dq_r1_expect_bit_r <= #TCQ dq_r1_expect_bit_rdlay1;
dq_f1_expect_bit_r <= #TCQ dq_f1_expect_bit_rdlay1;
end
always @ (posedge clk_i)
begin
if (rst_i[1] || manual_clear_error) begin
error_byte_r1 <= #TCQ 'b0;
error_bit_r1 <= #TCQ 'b0;
end
else if (data_valid_r1) begin
error_byte_r1 <= #TCQ error_byte;
error_bit_r1 <= #TCQ error_bit;
end
else
begin
error_byte_r1 <= #TCQ 'b0;
error_bit_r1 <= #TCQ 'b0;
end
end
always @ (posedge clk_i)
begin
if (rst_i[1] || manual_clear_error)
data_error <= #TCQ 1'b0;
else if (data_valid_r2)
data_error <= #TCQ | error_byte_r1;
else
data_error <= #TCQ 1'b0;
//synthesis translate_off
if (data_error)
$display ("ERROR: Expected data=%h, Received data=%h @ %t" ,cmp_data_r2, rd_data_r2, $time);
//synthesis translate_on
end
localparam NUM_OF_DQS = (MEM_TYPE == "QDR2PLUS") ? 9 : 8 ;
if (MEM_TYPE == "QDR2PLUS") begin: qdr_design_error_calc
if (MEM_BURST_LEN == 4) begin: bl4_design
for ( i = 0; i < NUM_DQ_PINS/NUM_OF_DQS; i = i+1) begin: gen_dq_error_map
assign dq_lane_error[i] = (error_byte_r1[i] |
error_byte_r1[i + (NUM_DQ_PINS/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*2/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*3/NUM_OF_DQS)] ) ? 1'b1 : 1'b0 ;
assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i];
end
end else begin: bl2_design
for ( i = 0; i < NUM_DQ_PINS/NUM_OF_DQS; i = i+1) begin: gen_dq_error_map
assign dq_lane_error[i] = (error_byte_r1[i] |
error_byte_r1[i + (NUM_DQ_PINS/NUM_OF_DQS)] ) ? 1'b1 : 1'b0 ;
assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i];
end
end
end else begin: ddr_design_error_calc
if (nCK_PER_CLK == 4) begin: ck_4to1_design
for ( i = 0; i < NUM_DQ_PINS/NUM_OF_DQS; i = i+1) begin: gen_dq_error_map
assign dq_lane_error[i] = (error_byte_r1[i] |
error_byte_r1[i + (NUM_DQ_PINS/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*2/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*3/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*4/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*5/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*6/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*7/NUM_OF_DQS)] ) ? 1'b1 : 1'b0 ;
assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i];
end
end else if (nCK_PER_CLK == 2) begin: ck_2to1_design
for ( i = 0; i < NUM_DQ_PINS/NUM_OF_DQS; i = i+1) begin: gen_dq_error_map
assign dq_lane_error[i] = (error_byte_r1[i] |
error_byte_r1[i + (NUM_DQ_PINS/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*2/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*3/NUM_OF_DQS)] ) ? 1'b1 : 1'b0 ;
assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i];
end
end
end
// mapped the user bits error to dq bits error
// mapper the error to rising 0
for ( i = 0; i < NUM_DQ_PINS; i = i+1)
begin: gen_dq_r0_error_mapbit
assign dq_r0_bit_error[i] = (error_bit_r1[i]);
assign cumlative_dq_r0_bit_error_c[i] = cumlative_dq_r0_bit_error_r[i] | dq_r0_bit_error[i];
end
// mapper the error to falling 0
for ( i = 0; i < NUM_DQ_PINS; i = i+1)
begin: gen_dq_f0_error_mapbit
assign dq_f0_bit_error[i] = (error_bit_r1[i+NUM_DQ_PINS*1] );
assign cumlative_dq_f0_bit_error_c[i] = cumlative_dq_f0_bit_error_r[i] | dq_f0_bit_error[i];
end
// mapper the error to rising 1
for ( i = 0; i < NUM_DQ_PINS; i = i+1)
begin: gen_dq_r1_error_mapbit
assign dq_r1_bit_error[i] = (error_bit_r1[i+ (NUM_DQ_PINS*2)]);
assign cumlative_dq_r1_bit_error_c[i] = cumlative_dq_r1_bit_error_r[i] | dq_r1_bit_error[i];
end
// mapper the error to falling 1
for ( i = 0; i < NUM_DQ_PINS; i = i+1)
begin: gen_dq_f1_error_mapbit
assign dq_f1_bit_error[i] = ( error_bit_r1[i+ (NUM_DQ_PINS*3)]);
assign cumlative_dq_f1_bit_error_c[i] = cumlative_dq_f1_bit_error_r[i] | dq_f1_bit_error[i];
end
reg COuta;
always @ (posedge clk_i)
begin
if (rst_i[1] || manual_clear_error) begin
dq_bit_error_r1 <= #TCQ 'b0;
dq_lane_error_r1 <= #TCQ 'b0;
dq_lane_error_r2 <= #TCQ 'b0;
data_valid_r1 <= #TCQ 1'b0;
data_valid_r2 <= #TCQ 1'b0;
dq_r0_bit_error_r <= #TCQ 'b0;
dq_f0_bit_error_r <= #TCQ 'b0;
dq_r1_bit_error_r <= #TCQ 'b0;
dq_f1_bit_error_r <= #TCQ 'b0;
cumlative_dq_lane_error_reg <= #TCQ 'b0;
cumlative_dq_r0_bit_error_r <= #TCQ 'b0;
cumlative_dq_f0_bit_error_r <= #TCQ 'b0;
cumlative_dq_r1_bit_error_r <= #TCQ 'b0;
cumlative_dq_f1_bit_error_r <= #TCQ 'b0;
error_addr_r1 <= #TCQ 'b0;
error_addr_r2 <= #TCQ 'b0;
error_addr_r3 <= #TCQ 'b0;
end
else begin
data_valid_r1 <= #TCQ data_valid_i;
data_valid_r2 <= #TCQ data_valid_r1;
dq_lane_error_r1 <= #TCQ dq_lane_error;
dq_bit_error_r1 <= #TCQ dq_bit_error;
cumlative_dq_lane_error_reg <= #TCQ cumlative_dq_lane_error_c;
cumlative_dq_r0_bit_error_r <= #TCQ cumlative_dq_r0_bit_error_c;
cumlative_dq_f0_bit_error_r <= #TCQ cumlative_dq_f0_bit_error_c;
cumlative_dq_r1_bit_error_r <= #TCQ cumlative_dq_r1_bit_error_c;
cumlative_dq_f1_bit_error_r <= #TCQ cumlative_dq_f1_bit_error_c;
dq_r0_bit_error_r <= #TCQ dq_r0_bit_error;
dq_f0_bit_error_r <= #TCQ dq_f0_bit_error;
dq_r1_bit_error_r <= #TCQ dq_r1_bit_error;
dq_f1_bit_error_r <= #TCQ dq_f1_bit_error;
error_addr_r2 <= #TCQ error_addr_r1;
error_addr_r3 <= #TCQ error_addr_r2;
if (rd_mdata_en)
error_addr_r1 <= #TCQ gen_addr;
else if (data_valid_i)
{COuta,error_addr_r1} <= #TCQ error_addr_r1 + 4;
end
end
end
endgenerate
assign cumlative_dq_lane_error_r = cumlative_dq_lane_error_reg;
assign dq_error_bytelane_cmp = dq_lane_error_r1;
assign data_error_o = data_error;
assign error_addr_o = error_addr_r3;
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/15.0/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2015/02/08 $
// $Author: swbranch $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21BO_1_V
`define SKY130_FD_SC_MS__A21BO_1_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21bo with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a21bo.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a21bo_1 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a21bo_1 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21BO_1_V
|
/*
########################################################################
########################################################################
*/
module ecfg_if (/*AUTOARG*/
// Outputs
mi_mmu_en, mi_dma_en, mi_cfg_en, mi_we, mi_addr, mi_din,
access_out, packet_out,
// Inputs
clk, reset, access_in, packet_in, mi_dout0, mi_dout1, mi_dout2,
mi_dout3, wait_in
);
parameter RX = 0; //0,1
parameter PW = 104;
parameter AW = 32;
parameter DW = 32;
parameter ID = 12'h810;
/********************************/
/*Clocks/reset */
/********************************/
input clk;
input reset;
/********************************/
/*Incoming Packet */
/********************************/
input access_in;
input [PW-1:0] packet_in;
/********************************/
/* Register Interface */
/********************************/
output mi_mmu_en;
output mi_dma_en;
output mi_cfg_en;
output mi_we;
output [14:0] mi_addr;
output [63:0] mi_din;
input [63:0] mi_dout0;
input [63:0] mi_dout1;
input [63:0] mi_dout2;
input [63:0] mi_dout3;
/********************************/
/* Outgoing Packet */
/********************************/
output access_out;
output [PW-1:0] packet_out;
input wait_in; //incoming wait
//wires
wire [31:0] dstaddr;
wire [31:0] data;
wire [31:0] srcaddr;
wire [1:0] datamode;
wire [3:0] ctrlmode;
wire [63:0] mi_dout_mux;
wire mi_rd;
wire access_forward;
wire rxsel;
wire mi_en;
//regs;
reg access_out;
reg [31:0] dstaddr_reg;
reg [31:0] srcaddr_reg;
reg [1:0] datamode_reg;
reg [3:0] ctrlmode_reg;
reg write_reg;
reg readback_reg;
reg [31:0] data_reg;
wire [31:0] data_out;
//parameter didn't seem to work
assign rxsel = RX;
//splicing packet
packet2emesh p2e (.access_out (),
.write_out (write),
.datamode_out (datamode[1:0] ),
.ctrlmode_out (ctrlmode[3:0]),
.dstaddr_out (dstaddr[31:0]),
.data_out (data[31:0]),
.srcaddr_out (srcaddr[31:0]),
.packet_in (packet_in[PW-1:0])
);
//ENABLE SIGNALS
assign mi_match = access_in & (dstaddr[31:20]==ID);
//config select (group 2 and 3)
assign mi_cfg_en = mi_match &
(dstaddr[19:16]==4'hF) &
(dstaddr[10:8]=={2'b01,rxsel});
//dma select (group 5)
assign mi_dma_en = mi_match &
(dstaddr[19:16]==4'hF) &
(dstaddr[10:8]==3'h5) &
(dstaddr[5]==rxsel);
//mmu select
assign mi_mmu_en = mi_match &
(dstaddr[19:16]==4'hE) &
(dstaddr[15]==rxsel);
//read/write indicator
assign mi_en = (mi_mmu_en | mi_cfg_en | mi_dma_en);
assign mi_rd = ~write & mi_en;
assign mi_we = write & mi_en;
//signal to carry transaction from ETX to ERX block through fifo_cdc
assign mi_rx_en = mi_match &
((dstaddr[19:16]==4'hE) | (dstaddr[19:16]==4'hF)) &
~mi_en;
//ADDR
assign mi_addr[14:0] = dstaddr[14:0];
//DIN
assign mi_din[63:0] = {srcaddr[31:0], data[31:0]};
//READBACK MUX (inputs should be zero if not used)
assign mi_dout_mux[63:0] = mi_dout0[63:0] |
mi_dout1[63:0] |
mi_dout2[63:0] |
mi_dout3[63:0];
//Access out packet
assign access_forward = (mi_rx_en | mi_rd);
always @ (posedge clk)
if(reset)
access_out <= 1'b0;
else if(~wait_in)
access_out <= access_forward;
always @ (posedge clk)
if(~wait_in)
begin
readback_reg <= mi_rd;
write_reg <= (mi_rx_en & write) | mi_rd;
datamode_reg[1:0] <= datamode[1:0];
ctrlmode_reg[3:0] <= ctrlmode[3:0];
dstaddr_reg[31:0] <= mi_rx_en ? dstaddr[31:0] : srcaddr[31:0];
data_reg[31:0] <= data[31:0];
srcaddr_reg[31:0] <= mi_rx_en ? srcaddr[31:0] : mi_dout_mux[63:32];
end
assign data_out[31:0] = readback_reg ? mi_dout_mux[31:0] : data_reg[31:0];
//Create packet
emesh2packet e2p (.packet_out (packet_out[PW-1:0]),
.access_in (1'b1),
.write_in (write_reg),
.datamode_in (datamode_reg[1:0]),
.ctrlmode_in (ctrlmode_reg[3:0]),
.dstaddr_in (dstaddr_reg[AW-1:0]),
.data_in (data_out[31:0]),
.srcaddr_in (srcaddr_reg[AW-1:0])
);
endmodule // ecfg_if
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_rst (
// clock reset
preset,
clk,
rst);
// clock reset
input preset;
input clk;
output rst;
// internal registers
reg rst_p = 'd0;
reg rst = 'd0;
// simple reset gen
always @(posedge clk or posedge preset) begin
if (preset == 1'b1) begin
rst_p <= 1'd1;
rst <= 1'd1;
end else begin
rst_p <= 1'b0;
rst <= rst_p;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_sel #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = V;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
//sf_camera_controller.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`include "sf_camera_defines.v"
module sf_camera_controller (
input clk,
input rst,
//Physical Interface
output o_cam_rst,
output o_flash,
input i_flash_strobe,
output o_cam_in_clk,
//Configuration Registers
input i_auto_flash,
input i_manual_flash_on,
input i_enable,
input i_camera_reset,
output o_clk_locked,
//Core Controller
output o_enable_dma,
output o_enable_reader,
output o_enable_interrupt
);
//Local Parameters
//Registers/Wires
//Submodules
//20MHz Clock Genertors
sf_camera_clk_gen clk_gen(
.clk (clk ),
.rst (rst ),
.locked (o_clk_locked ),
.phy_out_clk (o_cam_in_clk )
);
//Asynchronous Logic
assign o_flash = (i_auto_flash) ? i_flash_strobe:
i_manual_flash_on;
assign o_cam_rst = i_camera_reset;
//Synchronous Logic
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: flop_rptrs_xc6.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module flop_rptrs_xc6(/*AUTOARG*/
// Outputs
sparc_out, so, jbussync2_out, jbussync1_out, grst_out,
gdbginit_out, ddrsync2_out, ddrsync1_out, cken_out,
// Inputs
spare_in, se, sd, jbussync2_in, jbussync1_in, grst_in,
gdbginit_in, gclk, ddrsync2_in, ddrsync1_in, cken_in, agrst_l,
adbginit_l
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [25:0] cken_out; // From cken_ff_25_ of bw_u1_soffasr_2x.v, ...
output ddrsync1_out; // From ddrsync1_ff of bw_u1_soffasr_2x.v
output ddrsync2_out; // From ddrsync2_ff of bw_u1_soffasr_2x.v
output gdbginit_out; // From gdbginit_ff of bw_u1_soffasr_2x.v
output grst_out; // From gclk_ff of bw_u1_soffasr_2x.v
output jbussync1_out; // From jbussync1_ff of bw_u1_soffasr_2x.v
output jbussync2_out; // From jbussync2_ff of bw_u1_soffasr_2x.v
output so; // From scanout_latch of bw_u1_scanlg_2x.v
output [5:0] sparc_out; // From spare_ff_5_ of bw_u1_soffasr_2x.v, ...
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input adbginit_l; // To gdbginit_ff of bw_u1_soffasr_2x.v
input agrst_l; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
input [25:0] cken_in; // To cken_ff_25_ of bw_u1_soffasr_2x.v, ...
input ddrsync1_in; // To ddrsync1_ff of bw_u1_soffasr_2x.v
input ddrsync2_in; // To ddrsync2_ff of bw_u1_soffasr_2x.v
input gclk; // To I73 of bw_u1_ckbuf_33x.v
input gdbginit_in; // To gdbginit_ff of bw_u1_soffasr_2x.v
input grst_in; // To gclk_ff of bw_u1_soffasr_2x.v
input jbussync1_in; // To jbussync1_ff of bw_u1_soffasr_2x.v
input jbussync2_in; // To jbussync2_ff of bw_u1_soffasr_2x.v
input sd; // To spare_ff_5_ of bw_u1_soffasr_2x.v
input se; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
input [5:0] spare_in; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire clk; // From I73 of bw_u1_ckbuf_33x.v
wire scan_data_0; // From spare_ff_5_ of bw_u1_soffasr_2x.v
wire scan_data_1; // From spare_ff_4_ of bw_u1_soffasr_2x.v
wire scan_data_10; // From gdbginit_ff of bw_u1_soffasr_2x.v
wire scan_data_11; // From gclk_ff of bw_u1_soffasr_2x.v
wire scan_data_2; // From spare_ff_3_ of bw_u1_soffasr_2x.v
wire scan_data_3; // From spare_ff_2_ of bw_u1_soffasr_2x.v
wire scan_data_4; // From spare_ff_1_ of bw_u1_soffasr_2x.v
wire scan_data_5; // From spare_ff_0_ of bw_u1_soffasr_2x.v
wire scan_data_6; // From jbussync2_ff of bw_u1_soffasr_2x.v
wire scan_data_7; // From jbussync1_ff of bw_u1_soffasr_2x.v
wire scan_data_8; // From ddrsync2_ff of bw_u1_soffasr_2x.v
wire scan_data_9; // From ddrsync1_ff of bw_u1_soffasr_2x.v
// End of automatics
/* bw_u1_ckbuf_33x AUTO_TEMPLATE (
.clk (clk ),
.rclk (gclk ) ); */
bw_u1_ckbuf_33x I73
(/*AUTOINST*/
// Outputs
.clk (clk ), // Templated
// Inputs
.rclk (gclk )); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.q (sparc_out[@]),
.d (spare_in[@]),
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.sd (scan_data_@"(- 4 @)" ),
.so (scan_data_@"(- 5 @)" ),
); */
bw_u1_soffasr_2x spare_ff_5_
(
// Inputs
.sd (sd ),
/*AUTOINST*/
// Outputs
.q (sparc_out[5]), // Templated
.so (scan_data_0 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[5]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se));
bw_u1_soffasr_2x spare_ff_4_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[4]), // Templated
.so (scan_data_1 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[4]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_0 )); // Templated
bw_u1_soffasr_2x spare_ff_3_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[3]), // Templated
.so (scan_data_2 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[3]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_1 )); // Templated
bw_u1_soffasr_2x spare_ff_2_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[2]), // Templated
.so (scan_data_3 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[2]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_2 )); // Templated
bw_u1_soffasr_2x spare_ff_1_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[1]), // Templated
.so (scan_data_4 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[1]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_3 )); // Templated
bw_u1_soffasr_2x spare_ff_0_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[0]), // Templated
.so (scan_data_5 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[0]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_4 )); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.q (cken_out[@] ),
.d (cken_in[@] ),
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.se (1'b0),
.sd (1'b0),
.so (),
); */
bw_u1_soffasr_2x cken_ff_25_
( /*AUTOINST*/
// Outputs
.q (cken_out[25] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[25] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_24_
( /*AUTOINST*/
// Outputs
.q (cken_out[24] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[24] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_23_
( /*AUTOINST*/
// Outputs
.q (cken_out[23] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[23] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_22_
( /*AUTOINST*/
// Outputs
.q (cken_out[22] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[22] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_21_
( /*AUTOINST*/
// Outputs
.q (cken_out[21] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[21] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_20_
( /*AUTOINST*/
// Outputs
.q (cken_out[20] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[20] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_19_
( /*AUTOINST*/
// Outputs
.q (cken_out[19] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[19] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_18_
( /*AUTOINST*/
// Outputs
.q (cken_out[18] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[18] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_17_
( /*AUTOINST*/
// Outputs
.q (cken_out[17] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[17] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_16_
( /*AUTOINST*/
// Outputs
.q (cken_out[16] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[16] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_15_
( /*AUTOINST*/
// Outputs
.q (cken_out[15] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[15] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_14_
( /*AUTOINST*/
// Outputs
.q (cken_out[14] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[14] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_13_
( /*AUTOINST*/
// Outputs
.q (cken_out[13] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[13] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_12_
( /*AUTOINST*/
// Outputs
.q (cken_out[12] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[12] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_11_
( /*AUTOINST*/
// Outputs
.q (cken_out[11] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[11] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_10_
( /*AUTOINST*/
// Outputs
.q (cken_out[10] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[10] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_9_
( /*AUTOINST*/
// Outputs
.q (cken_out[9] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[9] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_8_
( /*AUTOINST*/
// Outputs
.q (cken_out[8] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[8] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_7_
( /*AUTOINST*/
// Outputs
.q (cken_out[7] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[7] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_6_
( /*AUTOINST*/
// Outputs
.q (cken_out[6] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[6] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_5_
( /*AUTOINST*/
// Outputs
.q (cken_out[5] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[5] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_4_
( /*AUTOINST*/
// Outputs
.q (cken_out[4] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[4] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_3_
( /*AUTOINST*/
// Outputs
.q (cken_out[3] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[3] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_2_
( /*AUTOINST*/
// Outputs
.q (cken_out[2] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[2] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_1_
( /*AUTOINST*/
// Outputs
.q (cken_out[1] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[1] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_0_
( /*AUTOINST*/
// Outputs
.q (cken_out[0] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[0] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.se (se ),
); */
bw_u1_soffasr_2x ddrsync1_ff
(
// Outputs
.q (ddrsync1_out ),
.so (scan_data_9 ),
// Inputs
.d (ddrsync1_in ),
.sd (scan_data_8 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x ddrsync2_ff
(
// Outputs
.q (ddrsync2_out ),
.so (scan_data_8 ),
// Inputs
.d (ddrsync2_in ),
.sd (scan_data_7 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x jbussync1_ff
(
// Outputs
.q (jbussync1_out ),
.so (scan_data_7 ),
// Inputs
.d (jbussync1_in ),
.sd (scan_data_6 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x jbussync2_ff
(
// Outputs
.q (jbussync2_out ),
.so (scan_data_6 ),
// Inputs
.d (jbussync2_in ),
.sd (scan_data_5 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x gdbginit_ff
(
// Outputs
.q (gdbginit_out ),
.so (scan_data_10 ),
// Inputs
.d (gdbginit_in ),
.sd (scan_data_9 ),
.r_l (adbginit_l),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x gclk_ff
(
// Outputs
.q (grst_out ),
.so (scan_data_11 ),
// Inputs
.d (grst_in ),
.sd (scan_data_10 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
/* bw_u1_scanlg_2x AUTO_TEMPLATE (
.sd (scan_data_11 ),
.ck (clk ),
); */
bw_u1_scanlg_2x scanout_latch
( /*AUTOINST*/
// Outputs
.so (so),
// Inputs
.sd (scan_data_11 ), // Templated
.ck (clk ), // Templated
.se (1'b1));
endmodule
// Local Variables:
// verilog-library-files:("../../../common/rtl/u1.behV" )
// End:
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:11:35 03/19/2015
// Design Name: fsm2
// Module Name: /home/lsriw/SR/Wojciech Gumula/repo/fsm2/tb_fsm2.v
// Project Name: fsm2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: fsm2
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module load_file
(
output [7:0] out,
output send
);
integer file;
reg [7:0] c;
reg s;
reg [7:0] i = 0;
initial
begin
file=$fopen("data/input.data", "r");
for(i = 0; i < 16; i = i + 1)
begin
c=$fgetc(file);
s = 1;
#4;
s = 0;
#44;
end
$fclose(file);
end
assign out = c;
assign send = s;
endmodule
module save_file
(
input [7:0] c,
input received
);
integer file;
initial
begin
file=$fopen("data/output.ise", "wb");
repeat (16) begin
@(posedge received);
$fwrite(file, "%c", c);
end
$fwrite(file, "\n");
$fclose(file);
end
endmodule
module tb_fsm2;
// Inputs
reg clk;
reg rst; //reset jest wspólny dla uproszczenia układu
// Outputs
wire rxd;
wire [7:0] data;
wire [7:0] data_out;
wire received;
// Instantiate the Unit Under Test (UUT)
fsm2 uut (
.clk(clk),
.rst(rst),
.rxd(rxd),
.data(data_out),
.received(received)
);
fsm serial (
.clk(clk),
.send(send),
.data(data),
.txd(rxd),
.rst(rst)
);
load_file load (
.out(data),
.send(send)
);
save_file save (
.c(data_out),
.received(received)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
// Wait 100 ns for global reset to finish
#100;
end
always #2 clk = ~clk;
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The gltch free clock mux
//
// ====================================================================
`include "e203_defines.v"
module e203_subsys_gfcm(
input test_mode,
input clk0_rst_n,
input clk1_rst_n,
input sel1 ,
input clk0 ,
input clk1 ,
output clkout
);
wire clk0_sel = ~sel1;
wire clk1_sel = sel1;
localparam SYNC_LEVEL = 3;
wire clk0_sync_in;
reg [SYNC_LEVEL-1:0] clk0_sync_r;
always @(posedge clk0 or negedge clk0_rst_n)
begin:clk0_sync_PROC
if(clk0_rst_n == 1'b0)
begin
clk0_sync_r[SYNC_LEVEL-1:0] <= {SYNC_LEVEL{1'b0}};
end
else
begin
clk0_sync_r[SYNC_LEVEL-1:0] <= {clk0_sync_r[SYNC_LEVEL-2:0],clk0_sync_in};
end
end
wire clk1_sync_in;
reg [SYNC_LEVEL-1:0] clk1_sync_r;
always @(posedge clk1 or negedge clk1_rst_n)
begin:clk1_sync_PROC
if(clk1_rst_n == 1'b0)
begin
clk1_sync_r[SYNC_LEVEL-1:0] <= {SYNC_LEVEL{1'b0}};
end
else
begin
clk1_sync_r[SYNC_LEVEL-1:0] <= {clk1_sync_r[SYNC_LEVEL-2:0],clk1_sync_in};
end
end
assign clk0_sync_in = (~clk1_sync_r[SYNC_LEVEL-1]) & clk0_sel;
assign clk1_sync_in = (~clk0_sync_r[SYNC_LEVEL-1]) & clk1_sel;
wire clk0_gated;
wire clk1_gated;
wire clk0_gate_en = clk0_sync_r[1];
e203_clkgate u_clk0_clkgate(
.clk_in (clk0 ),
.test_mode(test_mode ),
.clock_en (clk0_gate_en),
.clk_out (clk0_gated)
);
wire clk1_gate_en = clk1_sync_r[1];
e203_clkgate u_clk1_clkgate(
.clk_in (clk1 ),
.test_mode(test_mode ),
.clock_en (clk1_gate_en),
.clk_out (clk1_gated)
);
assign clkout = clk0_gated | clk1_gated;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVGND_PP_SYMBOL_V
`define SKY130_FD_SC_HS__TAPVGND_PP_SYMBOL_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__tapvgnd (
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVGND_PP_SYMBOL_V
|
// synthesis translate_off
// synthesis translate_on
// synthesis verilog_input_version verilog_2001
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//-----------------------------------------------------------------------------
// Title : PCI Express Reference Design Example Application
// Project : PCI Express MegaCore function
//-----------------------------------------------------------------------------
// File : altpcierd_cdma_ecrc_check_64.v
// Author : Altera Corporation
//-----------------------------------------------------------------------------
// Description :
// This module performs PCIE Ecrc checking on the 64 bit Avalon-ST RX data stream
//-----------------------------------------------------------------------------
// Copyright (c) 2009 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
module altpcierd_cdma_ecrc_check_64 (
input clk_in,
input srst,
input[139:0] rxdata,
input[15:0] rxdata_be,
input rx_stream_valid0,
output rx_stream_ready0_ecrc,
output reg [139:0] rxdata_ecrc,
output reg [15:0] rxdata_be_ecrc,
output reg rx_stream_valid0_ecrc,
input rx_stream_ready0,
output reg rx_ecrc_check_valid,
output reg [15:0] ecrc_bad_cnt
);
localparam RAM_DATA_WIDTH = 140;
localparam RAM_ADDR_WIDTH = 8;
localparam PIPELINE_DEPTH =4;
// Bits in rxdata
localparam SOP_BIT = 139;
localparam EOP_BIT = 138;
localparam EMPTY_BIT = 137;
wire rx_sop;
reg rx_sop_crc_in;
reg rx_sop_last;
reg rx_eop_last;
wire rx_eop;
reg rx_eop_reg;
wire rx_eop_crc_in;
wire [2:0] rx_empty;
wire [31:0] crc_32;
wire crcbad;
wire crcvalid;
// Set TLP length
reg [9:0] ctrlrx_cnt_len_dw;
reg [9:0] ctrlrx_cnt_len_dw_reg;
// Set when TLP is 3 DW header
wire ctrlrx_payload;
reg ctrlrx_payload_reg;
// Set when TLP is 3 DW header
wire ctrlrx_3dw;
reg ctrlrx_3dw_reg;
// Set when TLP are qword aligned
wire ctrlrx_qword_aligned;
reg ctrlrx_qword_aligned_reg;
// Set when the TD digest bit is set in the descriptor
wire ctrlrx_digest;
reg ctrlrx_digest_reg;
reg [PIPELINE_DEPTH-1:0] ctrlrx_digest_pipe;
reg[139:0] rxdata_pipeline [PIPELINE_DEPTH-1:0];
reg[15:0] rxdata_be_pipeline [PIPELINE_DEPTH-1:0];
reg[PIPELINE_DEPTH-1:0] rx_stream_valid_pipeline;
wire ctrlrx_3dw_aligned;
reg ctrlrx_3dw_aligned_reg;
wire ctrlrx_4dw_non_aligned;
wire ctrlrx_4dw_aligned;
wire ctrlrx_4dw_nopayload;
wire ctrlrx_3dw_nopayload;
wire ctrlrx_3dw_nonaligned;
reg ctrlrx_4dw_non_aligned_reg;
reg ctrlrx_4dw_aligned_reg;
reg ctrlrx_4dw_nopayload_reg;
reg ctrlrx_3dw_nopayload_reg;
reg ctrlrx_3dw_nonaligned_reg;
integer i;
reg [127:0] rxdata_crc_reg ;
reg rx_valid_crc_in ;
wire [127:0] rxdata_byte_swap ;
wire [127:0] rxdata_crc_in ;
reg rx_sop_crc_in_last;
reg rx_eop_crc_in_last;
reg rx_valid_crc_pending;
// xhdl
wire[31:0] zeros_32; assign zeros_32 = 32'h0;
wire ctrlrx_single_cycle;
reg [10:0] rx_payld_remain_dw;
reg [10:0] rx_payld_len;
reg has_payld;
reg debug_ctrlrx_4dw_aligned;
reg debug_ctrlrx_4dw_non_aligned;
reg debug_ctrlrx_3dw_aligned;
reg debug_ctrlrx_3dw_nonaligned;
reg debug_ctrlrx_4dw_aligned_nopayld;
reg debug_ctrlrx_4dw_non_aligned_nopayld;
reg debug_ctrlrx_3dw_aligned_nopayld;
reg debug_ctrlrx_3dw_nonaligned_nopayld;
wire[11:0] zeros12; assign zeros12 = 12'h0;
wire[7:0] zeros8; assign zeros8 = 8'h0;
wire[15:0] rxdata_be_15_12; assign rxdata_be_15_12 = {rxdata_be[15:12], zeros12};
wire[15:0] rxdata_be_15_8; assign rxdata_be_15_8 = {rxdata_be[15:8], zeros8};
////////////////////////////////////////////////////////////////////////////
//
// Drop ECRC field from the data stream/rx_be.
// Regenerate rx_st_eop.
// Set TD bit to 0.
//
always @ (posedge clk_in ) begin
if (srst==1'b1) begin
rxdata_ecrc <= 140'h0;
rxdata_be_ecrc <= 16'h0;
rx_payld_remain_dw <= 11'h0;
rx_stream_valid0_ecrc <= 1'b0;
rx_payld_len <= 11'h0;
has_payld <= 1'b0;
end
else begin
rxdata_ecrc[138] <= 1'b0;
rx_stream_valid0_ecrc <= 1'b0; // default
/////////////////////////
// TLP has Digest
//
if (ctrlrx_digest==1'b1) begin
// 1st phase of descriptor
if ((rx_sop==1'b1) & (rx_stream_valid0==1'b1)) begin
rxdata_ecrc[111] <= 1'b0;
rxdata_ecrc[135:112] <= rxdata[135:112];
rxdata_ecrc[110:0] <= rxdata[110:0];
rxdata_ecrc[SOP_BIT] <= 1'b1;
rxdata_ecrc[EOP_BIT] <= 1'b0;
rxdata_ecrc[EMPTY_BIT] <= 1'b0;
rxdata_be_ecrc <= rxdata_be;
has_payld <= rxdata[126];
if (rxdata[126]==1'b1)
rx_payld_len <= (rxdata[105:96] == 0) ? 11'h400 : {1'b0, rxdata[105:96]}; // account for 1024DW
else
rx_payld_len <= 0;
rx_stream_valid0_ecrc <= 1'b1;
end
// 2nd phase of descriptor
else if ((rx_sop_last==1'b1) & (rx_stream_valid0==1'b1)) begin
rxdata_ecrc[127:0] <= rxdata[127:0];
rxdata_ecrc[SOP_BIT] <= 1'b0;
rxdata_ecrc[EOP_BIT] <= (has_payld==1'b0) | ((ctrlrx_3dw==1'b1) & (ctrlrx_qword_aligned==1'b0) & (rx_payld_len==1));
rxdata_ecrc[EMPTY_BIT] <= 1'b0;
rxdata_be_ecrc <= rxdata_be;
rx_stream_valid0_ecrc <= 1'b1;
// Load the # of payld DWs remaining in next cycles
if (has_payld==1'b1) begin // if there is payload
if ((ctrlrx_3dw==1'b1) & (ctrlrx_qword_aligned==1'b0)) begin
rx_payld_remain_dw <= rx_payld_len - 1;
end
else if ((ctrlrx_3dw==1'b0) & (ctrlrx_qword_aligned==1'b0)) begin
rx_payld_remain_dw <= rx_payld_len + 1;
end
else begin
rx_payld_remain_dw <= rx_payld_len;
end
end
else begin
rx_payld_remain_dw <= 11'h0;
end
end
else if (rx_stream_valid0==1'b1) begin
rxdata_ecrc[SOP_BIT] <= 1'b0;
rxdata_ecrc[EMPTY_BIT] <= 1'b0;
rxdata_ecrc[127:0] <= rxdata[127:0];
case (rx_payld_remain_dw)
11'h1: begin
rxdata_ecrc[EOP_BIT] <= 1'b1;
rxdata_be_ecrc <= rxdata_be_15_12;
end
11'h2: begin
rxdata_ecrc[EOP_BIT] <= 1'b1;
rxdata_be_ecrc <= rxdata_be_15_8;
end
default: begin
rxdata_ecrc[EOP_BIT] <= 1'b0;
rxdata_be_ecrc <= rxdata_be[15:0];
end
endcase
rx_stream_valid0_ecrc <= (rx_payld_remain_dw > 11'h0) ? 1'b1 : 1'b0;
// Decrement payld count as payld is received
rx_payld_remain_dw <= (rx_payld_remain_dw < 2) ? 11'h0 : rx_payld_remain_dw - 11'h2;
end
end
///////////////
// No Digest
//
else begin
rxdata_ecrc <= rxdata;
rxdata_be_ecrc <= rxdata_be;
rx_stream_valid0_ecrc <= rx_stream_valid0;
end
end
end
////////////////////////////////////////////////////////////////////////////
//
// RX Avalon-ST input delayed of PIPELINE_DEPTH to RX Avalon-ST output
//
assign rx_stream_ready0_ecrc = rx_stream_ready0;
/*
assign rxdata_ecrc = rxdata_pipeline[PIPELINE_DEPTH-1];
assign rxdata_be_ecrc = rxdata_be_pipeline[PIPELINE_DEPTH-1];
always @(posedge clk_in) begin
rxdata_pipeline[0] <= rxdata;
rxdata_be_pipeline[0] <= rxdata_be;
for(i=1;i <PIPELINE_DEPTH;i=i+1) begin
rxdata_pipeline[i] <= rxdata_pipeline[i-1];
rxdata_be_pipeline[i] <= rxdata_be_pipeline[i-1];
end
end
assign rx_stream_valid0_ecrc = rx_stream_valid_pipeline[PIPELINE_DEPTH-1];
always @(posedge clk_in) begin
rx_stream_valid_pipeline[0] <= rx_stream_valid0;
for(i=1;i <PIPELINE_DEPTH;i=i+1)
rx_stream_valid_pipeline[i] <= rx_stream_valid_pipeline[i-1];
end
*/
////////////////////////////////////////////////////////////////////////////
//
// CRC MegaCore instanciation
//
altpcierd_rx_ecrc_64 rx_ecrc_64 (
.reset_n (~srst),
.clk (clk_in),
.data (rxdata_crc_in[127:64]),
// .datavalid ( ((rx_sop_crc_in | rx_valid_crc_pending) & rx_stream_valid0) | (rx_valid_crc_pending&rx_eop_crc_in)),
.datavalid (ctrlrx_digest_reg & (((rx_sop_crc_in | rx_valid_crc_pending) & rx_stream_valid0) | (rx_valid_crc_pending&rx_eop_crc_in))),
.startofpacket (rx_sop_crc_in),
.endofpacket (rx_eop_crc_in),
.empty (rx_empty),
.crcbad (crcbad),
.crcvalid (crcvalid));
// Inputs to the MegaCore
always @(posedge clk_in) begin
if (ctrlrx_digest ==1'b0)
rx_valid_crc_in <= 1'b0;
else if ((rx_sop_crc_in==1'b0) && (rx_sop_crc_in_last==1'b0) && (rx_eop==1'b1) &&
(ctrlrx_cnt_len_dw_reg<2)) // rxdata is only 1 DW of payld -- CRC appended
rx_valid_crc_in <= 1'b0;
else
rx_valid_crc_in <= rx_stream_valid0;
if (rx_sop_crc_in & rx_stream_valid0)
rx_valid_crc_pending <= 1'b1;
else if (rx_eop_crc_in)
rx_valid_crc_pending <= 1'b0;
end
always @(posedge clk_in) begin
if (srst==1'b1) begin
debug_ctrlrx_4dw_aligned <= 1'b0;
debug_ctrlrx_4dw_non_aligned <= 1'b0;
debug_ctrlrx_3dw_aligned <= 1'b0;
debug_ctrlrx_3dw_nonaligned <= 1'b0;
debug_ctrlrx_4dw_aligned_nopayld <= 1'b0;
debug_ctrlrx_4dw_non_aligned_nopayld <= 1'b0;
debug_ctrlrx_3dw_aligned_nopayld <= 1'b0;
debug_ctrlrx_3dw_nonaligned_nopayld <= 1'b0;
end
else begin
if (rx_stream_valid0==1'b1) begin
debug_ctrlrx_4dw_aligned <= (rx_sop==1'b1) ? ctrlrx_4dw_aligned : debug_ctrlrx_4dw_aligned;
debug_ctrlrx_4dw_non_aligned <= (rx_sop==1'b1) ? ctrlrx_4dw_non_aligned : debug_ctrlrx_4dw_non_aligned;
debug_ctrlrx_3dw_aligned <= (rx_sop==1'b1) ? ctrlrx_3dw_aligned : debug_ctrlrx_3dw_aligned;
debug_ctrlrx_3dw_nonaligned <= (rx_sop==1'b1) ? ctrlrx_3dw_nonaligned : debug_ctrlrx_3dw_nonaligned;
debug_ctrlrx_4dw_aligned_nopayld <= ((rx_sop==1'b1) & (rxdata[126]==1'b0)) ? ctrlrx_4dw_aligned : debug_ctrlrx_4dw_aligned_nopayld ;
debug_ctrlrx_4dw_non_aligned_nopayld <= ((rx_sop==1'b1) & (rxdata[126]==1'b0)) ? ctrlrx_4dw_non_aligned : debug_ctrlrx_4dw_non_aligned_nopayld ;
debug_ctrlrx_3dw_aligned_nopayld <= ((rx_sop==1'b1) & (rxdata[126]==1'b0)) ? ctrlrx_3dw_aligned : debug_ctrlrx_3dw_aligned_nopayld ;
debug_ctrlrx_3dw_nonaligned_nopayld <= ((rx_sop==1'b1) & (rxdata[126]==1'b0)) ? ctrlrx_3dw_nonaligned : debug_ctrlrx_3dw_nonaligned_nopayld ;
end
end
end
always @(posedge clk_in) begin
if (srst==1'b1) begin
rx_sop_crc_in <= 1'b0;
rx_sop_crc_in_last <= 1'b0;
rx_eop_crc_in_last <= 1'b0;
ctrlrx_3dw_aligned_reg <= 1'b0;
rx_eop_reg <= 1'b0;
end
else if (rx_stream_valid0) begin
rx_sop_crc_in <= rx_sop;
rx_sop_crc_in_last <= rx_sop_last;
rx_eop_crc_in_last <= rx_eop_crc_in;
ctrlrx_3dw_aligned_reg <= ctrlrx_3dw_aligned;
if ((rx_sop_crc_in==1'b0) && (rx_sop_crc_in_last==1'b0) && (rx_eop==1'b1) &&
(ctrlrx_cnt_len_dw_reg<2)) // rxdata is only 1 DW of payld -- CRC appended
rx_eop_reg <= 1'b0;
else
rx_eop_reg <= rx_eop;
end
end
assign rx_eop_crc_in = ( (rx_sop_crc_in==1'b0)&& (rx_sop_crc_in_last==1'b0) &&
(rx_eop==1'b1)&& (rx_stream_valid0==1'b1) &&
(ctrlrx_cnt_len_dw_reg<2)) ||
((rx_sop_crc_in_last==1'b1) & (rx_eop==1'b1) & (ctrlrx_3dw_nopayload_reg==1'b1) )?1'b1:rx_eop_reg;
// rxdata_byte_swap is :
// - Set variant bit to 1 The EP field is variant
// - Byte swap the data and not the header
// - The header is already byte order ready for the CRC (lower byte first) such as :
// | H0 byte 0,1,2,3
// rxdata[127:0] | H1 byte 4,5,6,7
// | H2 byte 8,9,10,11
// | H3 byte 12,13,14,15
// - The Data requires byte swaping
// rxdata
//
always @(posedge clk_in) begin
if (srst==1'b1) begin
rx_sop_last <= rx_sop;
rx_eop_last <= rx_eop;
end
else if (rx_stream_valid0==1'b1) begin
rx_sop_last <= rx_sop;
rx_eop_last <= rx_eop;
end
//////////////////////////////////////////////////////////
// Reformat the incoming data so that
// - the left-most byte corresponds to the first
// byte on the PCIE line.
// - 'gaps' between the Avalon-ST desc/data boundaries are removed
// so that all bytes going into the CRC checker are contiguous
// (e.g. for 3DW aligned, 4DW non-aligned packets).
// - EP and Type[0] bits are set to '1' for ECRC calc
//
// Headers are already formatted. Data needs to be byte flipped
// within each DW.
if (rx_stream_valid0==1'b1) begin
if (ctrlrx_3dw_aligned==1'b1) begin // 3DW aligned
if (rx_sop==1'b1) begin
rxdata_crc_reg[127:121] <= rxdata[127:121];
rxdata_crc_reg[120] <= 1'b1;
rxdata_crc_reg[119:111] <= rxdata[119:111];
rxdata_crc_reg[110] <= 1'b1;
rxdata_crc_reg[109:0] <= rxdata[109:0];
end
else if (rx_sop_last==1'b1) begin
rxdata_crc_reg[127:0] <= rxdata[127:0]; // 2nd descriptor phase
end
else begin
rxdata_crc_reg[127:0] <= { rxdata[71:64 ], rxdata[79 : 72], rxdata[87 : 80], rxdata[95 : 88],
rxdata[39:32 ], rxdata[47 : 40], rxdata[55 : 48], rxdata[63 : 56],
rxdata[7:0 ], rxdata[15 : 8], rxdata[23 : 16], rxdata[31 : 24],
zeros_32};
end
end
else if (ctrlrx_3dw_nonaligned==1'b1) begin // 3DW non-aligned
if (rx_sop==1'b1) begin
rxdata_crc_reg[127:121] <= rxdata[127:121];
rxdata_crc_reg[120] <= 1'b1;
rxdata_crc_reg[119:111] <= rxdata[119:111];
rxdata_crc_reg[110] <= 1'b1;
rxdata_crc_reg[109:0] <= rxdata[109:0];
end
else if (rx_sop_last==1'b1) begin // 2nd descriptor phase
rxdata_crc_reg[127:96] <= rxdata[127:96]; // descriptor bits
rxdata_crc_reg[95:64] <= {rxdata[71 :64], rxdata[79 :72 ], rxdata[87 :80 ], rxdata[95 : 88]}; // data bits
end
else begin
rxdata_crc_reg[127:0] <= { rxdata[103:96], rxdata[111:104], rxdata[119:112], rxdata[127:120],
rxdata[71 :64], rxdata[79 :72 ], rxdata[87 :80 ], rxdata[95 : 88],
rxdata[39 :32], rxdata[47 :40 ], rxdata[55 :48 ], rxdata[63 : 56],
rxdata[7 :0 ], rxdata[15 : 8 ], rxdata[23 :16 ], rxdata[31 : 24]};
end
end
else if (ctrlrx_4dw_non_aligned == 1'b1) begin // 4DW non-aligned
if (rx_sop==1'b1) begin
rxdata_crc_reg[127:121] <= rxdata[127:121];
rxdata_crc_reg[120] <= 1'b1;
rxdata_crc_reg[119:111] <= rxdata[119:111];
rxdata_crc_reg[110] <= 1'b1;
rxdata_crc_reg[109:0] <= rxdata[109:0];
end
else if (rx_sop_last==1'b1) begin // 2nd descriptor phase
rxdata_crc_reg[127:64] <= rxdata[127:64];
end
else begin // data phase
rxdata_crc_reg[127:0] <= { rxdata[71 :64], rxdata[79 :72 ], rxdata[87 :80 ], rxdata[95 : 88],
rxdata[39 :32], rxdata[47 :40 ], rxdata[55 :48 ], rxdata[63 : 56],
rxdata[7 :0 ], rxdata[15 : 8 ], rxdata[23 :16 ], rxdata[31 : 24],
zeros_32};
end
end
else begin // 4DW Aligned
if (rx_sop==1'b1) begin
rxdata_crc_reg[127:121] <= rxdata[127:121];
rxdata_crc_reg[120] <= 1'b1;
rxdata_crc_reg[119:111] <= rxdata[119:111];
rxdata_crc_reg[110] <= 1'b1;
rxdata_crc_reg[109:0] <= rxdata[109:0];
end
else if (rx_sop_last==1'b1) begin // 2nd descriptor phase
rxdata_crc_reg[127:64] <= rxdata[127:64];
end
else begin // data phase
rxdata_crc_reg[127:0] <= { rxdata[103:96], rxdata[111:104], rxdata[119:112], rxdata[127:120],
rxdata[71 :64], rxdata[79 :72 ], rxdata[87 :80 ], rxdata[95 : 88],
rxdata[39 :32], rxdata[47 :40 ], rxdata[55 :48 ], rxdata[63 : 56],
rxdata[7 :0 ], rxdata[15 : 8 ], rxdata[23 :16 ], rxdata[31 : 24]};
end
end
end
end
assign rxdata_crc_in[127:64] = ((ctrlrx_3dw_nonaligned_reg==1'b1) || (ctrlrx_4dw_aligned_reg==1'b1) || (rx_sop_crc_in==1'b1) ||
((rx_sop_crc_in_last==1'b1) & (ctrlrx_4dw_non_aligned_reg==1'b1)) )? rxdata_crc_reg[127:64]: // SOP, or all data for 3DW non-aligned, 4DW aligned,
{rxdata_crc_reg[127:96], // 3DW aligned, 4DW non-aligned
rxdata[103:96 ],
rxdata[111:104],
rxdata[119:112],
rxdata[127:120]};
//////////////////////////////////////////////////////////////////////////
//
// BAD ECRC Counter output (ecrc_bad_cnt
//
always @(posedge clk_in) begin
if (srst==1'b1) begin
rx_ecrc_check_valid <= 1'b1;
ecrc_bad_cnt <= 0;
end
else if ((crcvalid==1'b1) && (crcbad==1'b1)) begin
if (ecrc_bad_cnt<16'hFFFF)
ecrc_bad_cnt <= ecrc_bad_cnt+1;
if (rx_ecrc_check_valid==1'b1)
rx_ecrc_check_valid <= 1'b0;
end
end
////////////////////////////////////////////////////////////////////////////
//
// Misc. Avalon-ST control signals
//
assign rx_sop = (rx_stream_valid0==1'b1) ? ((rxdata[139]==1'b1)?1'b1:1'b0) : rx_sop_last;
assign rx_eop = (rx_stream_valid0==1'b1) ? ((rxdata[138]==1'b1)?1'b1:1'b0) : rx_eop_last;
assign ctrlrx_single_cycle = ((rx_sop==1'b1)&&(rx_eop==1'b1))?1'b1:1'b0;
// ctrlrx_payload is set when the TLP has payload
assign ctrlrx_payload = (rx_sop==1'b1)? ( (rxdata[126]==1'b1)?1'b1:1'b0) : ctrlrx_payload_reg;
always @(posedge clk_in) begin
if (srst==1'b1)
ctrlrx_payload_reg <=1'b0;
else
ctrlrx_payload_reg <=ctrlrx_payload;
end
// ctrlrx_3dw is set when the TLP has 3 DWORD header
assign ctrlrx_3dw = (rx_sop==1'b1) ? ((rxdata[125]==1'b0) ? 1'b1:1'b0) : ctrlrx_3dw_reg;
always @(posedge clk_in) begin
if (srst==1'b1)
ctrlrx_3dw_reg <= 1'b0;
else
ctrlrx_3dw_reg <= ctrlrx_3dw;
end
// ctrlrx_qword_aligned is set when the data are address aligned
assign ctrlrx_qword_aligned = (rx_sop_last==1'b1) ? (( ((ctrlrx_3dw==1'b1) && (rxdata[98]==0)) ||
((ctrlrx_3dw==1'b0) && (rxdata[66]==0))) ? 1'b1 : 1'b0) : ctrlrx_qword_aligned_reg;
always @(posedge clk_in) begin
if (srst==1'b1)
ctrlrx_qword_aligned_reg <=1'b0;
else
ctrlrx_qword_aligned_reg <= ctrlrx_qword_aligned;
end
assign ctrlrx_digest = (rx_sop==1'b1) ? ((rxdata[111]==1'b1)?1'b1:1'b0) : ctrlrx_digest_reg;
always @(posedge clk_in) begin
if (srst==1'b1)
ctrlrx_digest_reg <=1'b0;
else
ctrlrx_digest_reg <=ctrlrx_digest;
end
assign ctrlrx_3dw_aligned = (//(ctrlrx_payload==1'b1) &&
(ctrlrx_3dw==1'b1) &&
(ctrlrx_qword_aligned==1'b1))?1'b1:1'b0;
assign ctrlrx_3dw_nonaligned = (//(ctrlrx_payload==1'b1) &&
(ctrlrx_3dw==1'b1) &&
(ctrlrx_qword_aligned==1'b0))?1'b1:1'b0;
assign ctrlrx_4dw_non_aligned = (//(ctrlrx_payload==1'b1) &&
(ctrlrx_3dw==1'b0) &&
(ctrlrx_qword_aligned==1'b0))?1'b1:1'b0;
assign ctrlrx_4dw_aligned = (//(ctrlrx_payload==1'b1) &&
(ctrlrx_3dw==1'b0) &&
(ctrlrx_qword_aligned==1'b1))?1'b1:1'b0;
assign ctrlrx_4dw_nopayload = (ctrlrx_payload==1'b0) && (ctrlrx_3dw==1'b0);
assign ctrlrx_3dw_nopayload = (ctrlrx_payload==1'b0) && (ctrlrx_3dw==1'b1);
always @(posedge clk_in) begin
if (srst==1'b1) begin
ctrlrx_4dw_non_aligned_reg <= 1'b0;
ctrlrx_4dw_aligned_reg <= 1'b0;
ctrlrx_4dw_nopayload_reg <= 1'b0;
ctrlrx_3dw_nopayload_reg <= 1'b0;
ctrlrx_3dw_nonaligned_reg <= 1'b0;
end
else if (rx_stream_valid0==1'b1) begin
ctrlrx_4dw_non_aligned_reg <= ctrlrx_4dw_non_aligned;
ctrlrx_4dw_aligned_reg <= ctrlrx_4dw_aligned;
ctrlrx_4dw_nopayload_reg <= ctrlrx_4dw_nopayload;
ctrlrx_3dw_nopayload_reg <= ctrlrx_3dw_nopayload;
ctrlrx_3dw_nonaligned_reg <= ctrlrx_3dw_nonaligned;
end
end
always @(posedge clk_in) begin
// ctrlrx_cnt_len_dw counts the number remaining
// number of DWORD in rxdata_crc_reg
if (rx_stream_valid0==1'b1) begin
if (ctrlrx_payload==1'b1)
ctrlrx_cnt_len_dw_reg <= ctrlrx_cnt_len_dw;
else
ctrlrx_cnt_len_dw_reg <= 0; // no payload
end
if (srst==1'b1)
ctrlrx_cnt_len_dw <= 0;
else if ((rx_sop==1'b1) & (rx_stream_valid0==1'b1))begin
if (ctrlrx_3dw==1'b0)
ctrlrx_cnt_len_dw <= rxdata[105:96];
else
ctrlrx_cnt_len_dw <= rxdata[105:96]-1;
end
else if ((rx_sop_last==1'b0) & (rx_stream_valid0==1'b1)) begin // decrement in data phase
if (ctrlrx_cnt_len_dw>1)
ctrlrx_cnt_len_dw <= ctrlrx_cnt_len_dw-2;
else if (ctrlrx_cnt_len_dw>0)
ctrlrx_cnt_len_dw <= ctrlrx_cnt_len_dw-1;
end
end
assign rx_empty = (rx_eop_crc_in==1'b0)? 0:
(ctrlrx_3dw_nopayload_reg==1'b1) ? 3'h0 : // ECRC appended to 3DW header (3DW dataless)
(ctrlrx_cnt_len_dw_reg[1:0]==0)?3'h4: // sending ECRC field only (4 bytes)
(ctrlrx_cnt_len_dw_reg[1:0]==1)?3'h0: // sending 1 DW payld + ECRC (8 bytes)
(ctrlrx_cnt_len_dw_reg[1:0]==2)?3'h0:3'h0; // sending 2 DW (8 bytes) paylod + ECRC (4 bytes)
// for internal monitoring
assign crc_32 = (rx_eop_crc_in==1'b0)?0:
(ctrlrx_cnt_len_dw_reg[1:0]==0)? rxdata_crc_in[127:96]:
(ctrlrx_cnt_len_dw_reg[1:0]==1)? rxdata_crc_in[95:64]:
(ctrlrx_cnt_len_dw_reg[1:0]==2)? rxdata_crc_in[63:32]:
rxdata_crc_in[31:0];
endmodule
|
/*
Instruction Word
15: 0, First Word
31:16, Second Word
*/
`include "CoreDefs.v"
`include "DecOp4_XE.v"
module DecOp4(
/* verilator lint_off UNUSED */
clk,
istrWord,
regCsFl,
idRegN,
idRegS,
idRegT,
idImm,
idStepPc,
idStepPc2,
idUCmd
);
parameter decEnable64 = 0; //Enable BJX1-64 ISA
parameter decEnable64A = 0; //Enable BJX1-64A ISA
parameter decEnableBJX1 = 1; //Enable BJX1 extensions
input clk; //clock
input[47:0] istrWord; //source instruction word
input[15:0] regCsFl; //current SR/FPSCR
output[6:0] idRegN;
output[6:0] idRegS;
output[6:0] idRegT;
output[31:0] idImm;
output[3:0] idStepPc;
output[3:0] idStepPc2;
output[7:0] idUCmd;
reg isOp32; //opcode is 32-bit
reg isOp8E; //8Ezz_zzzz
reg isOpCE; //CEzz_zzzz
reg isOpXE; //8Ezz_zzzz || CEzz_zzzz
reg opPsDQ;
reg opPwDQ;
reg opPlDQ;
reg opJQ;
reg opUseBase16; //op uses basic 16-bit decoder
reg[15:0] opCmdWord;
reg[6:0] opRegN;
reg[6:0] opRegS;
reg[6:0] opRegT; //Index for mem ops
reg[31:0] opImm; //Disp for mem ops
reg[7:0] opUCmd;
reg[3:0] opStepPc;
reg[3:0] opStepPc2;
reg[3:0] opStepPc2A;
reg[3:0] opStepPc2B;
assign idRegN = opRegN;
assign idRegS = opRegS;
assign idRegT = opRegT;
assign idImm = opImm;
assign idUCmd = opUCmd;
assign idStepPc = opStepPc;
assign idStepPc2 = opStepPc2;
reg[4:0] tOpDecXfrm;
reg[2:0] tOpDecXfrmZx;
// reg[7:0] tOpW2;
reg[6:0] opRegN_Dfl;
reg[6:0] opRegM_Dfl;
reg[6:0] opRegO_Dfl;
reg[6:0] opRegM_CR;
reg[6:0] opRegM_SR;
reg[6:0] opRegN_FR;
reg[6:0] opRegM_FR;
reg[6:0] opRegO_FR;
reg[6:0] opRegS_FR;
reg[6:0] opRegT_FR;
reg[6:0] opRegN_N3;
reg[6:0] opRegM_N3;
reg[31:0] opImm_Zx4;
reg[31:0] opImm_Zx8;
reg[31:0] opImm_Sx8;
reg[31:0] opImm_Sx12;
//reg opIsRegN_FR;
//reg opIsRegM_FR;
reg opIsRegM_CR;
reg opIsRegM_SR;
// reg opIsXe;
wire[6:0] opRegXeN;
wire[6:0] opRegXeS;
wire[6:0] opRegXeT;
wire[31:0] opImmXe;
wire[7:0] opUCmdXe;
DecOp4_XE decXe(istrWord[31:0],
opRegXeN, opRegXeS, opRegXeT,
opImmXe, opUCmdXe);
always @*
begin
opStepPc = 2;
// opPfxImm=0;
// opCmdWord=0;
opCmdWord=0;
opUCmd=UCMD_UDBRK;
opImm=0;
isOp32=0;
isOp8E=0; isOpCE=0; isOpXE=0;
// isOpCC0=0; isOpCC3=0; opCCe=0;
opUseBase16=1;
// opIsXe = 0;
opRegN=UREG_ZZR;
opRegS=UREG_ZZR;
opRegT=UREG_ZZR;
// opIsRegN_FR=0; opIsRegM_FR=0;
// opIsRegS_FR=0; opIsRegT_FR=0;
// opIsRegM_CR=0; opIsRegM_SR=0;
tOpDecXfrm=UXFORM_INVALID;
tOpDecXfrmZx=UXFORMZX_SX;
if(decEnable64 && regCsFl[5])
begin
opJQ=1; opPsDQ=regCsFl[6];
opPwDQ=opPsDQ; opPlDQ=0;
end else begin
opJQ=0; opPsDQ=0;
opPwDQ=0; opPlDQ=0;
end
opCmdWord=istrWord[15:0];
// tOpW2=istrWord[31:24];
opStepPc2 = 2;
opStepPc2A=2;
opStepPc2B=2;
if(decEnableBJX1)
begin
if(istrWord[47:44]==4'h8)
begin
if( (istrWord[43:40]==4'hA) ||
(istrWord[43:40]==4'hC) ||
(istrWord[43:40]==4'hE))
opStepPc2A=4;
end
if(istrWord[31:28]==4'h8)
begin
if( (istrWord[27:24]==4'hA) ||
(istrWord[27:24]==4'hC) ||
(istrWord[27:24]==4'hE))
opStepPc2B=4;
end
end
casez(opCmdWord[15:12])
4'h0: case(opCmdWord[3:0])
4'h2: begin //0xx2, STC
opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARIC_NS;
tOpDecXfrmZx=UXFORMZX_CR;
end
4'h4: begin //0xx4
opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_NSO;
end
4'h5: begin //0xx5
opUCmd = opPwDQ ? UCMD_MOVQ_RM : UCMD_MOVW_RM;
tOpDecXfrm=UXFORM_MOV_NSO;
end
4'h6: begin //0xx6
opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM;
tOpDecXfrm=UXFORM_MOV_NSO;
end
4'h7: begin //0xx7
opUCmd=UCMD_ALU_DMULS; tOpDecXfrm=UXFORM_ARI_ST;
end
4'h8: case(opCmdWord[7:4])
4'h0: begin //0x08
opUCmd=UCMD_ALU_SPOP;
opImm[7:0]=UCMDP_ALU_CLRT;
tOpDecXfrm=UXFORM_CST;
end
4'h1: begin //0x18
opUCmd=UCMD_ALU_SPOP;
opImm[7:0]=UCMDP_ALU_SETT;
tOpDecXfrm=UXFORM_CST;
end
4'h2: begin //0x28
opUCmd=UCMD_ALU_SPOP;
opImm[7:0]=UCMDP_ALU_CLRMAC;
tOpDecXfrm=UXFORM_CST;
end
4'h3: begin //0x38
opUCmd=UCMD_ALU_SPOP;
opImm[7:0]=UCMDP_ALU_LDTLB;
tOpDecXfrm=UXFORM_CST;
end
4'h4: begin //0x48
opUCmd=UCMD_ALU_SPOP;
opImm[7:0]=UCMDP_ALU_CLRS;
tOpDecXfrm=UXFORM_CST;
end
4'h5: begin //0x58
opUCmd=UCMD_ALU_SPOP;
opImm[7:0]=UCMDP_ALU_SETS;
tOpDecXfrm=UXFORM_CST;
end
4'h6: begin //0x68
opUCmd=UCMD_ALU_SPOP;
opImm[7:0]=UCMDP_ALU_NOTT;
tOpDecXfrm=UXFORM_CST;
end
default: begin end
endcase
4'h9: case(opCmdWord[7:4])
4'h0: begin //0x09
opUCmd=UCMD_NONE; tOpDecXfrm=UXFORM_Z;
end
4'h1: begin //0x19
opUCmd=UCMD_ALU_SPOP;
opImm[7:0]=UCMDP_ALU_DIV0U;
tOpDecXfrm=UXFORM_CST;
end
4'h2: begin //0x29
opUCmd=UCMD_ALU_MOVT; tOpDecXfrm=UXFORM_N;
end
4'h3: begin //0x39
opUCmd=UCMD_ALU_MOVRT; tOpDecXfrm=UXFORM_N;
end
default: begin end
endcase
4'hA: begin //0xxA
opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARIC_NS;
tOpDecXfrmZx=UXFORMZX_SR;
end
4'hB: case(opCmdWord[7:4])
4'h0: begin //0z0B
opUCmd=UCMD_RTS; tOpDecXfrm=UXFORM_Z;
end
4'h1: begin //0x1B
opUCmd=UCMD_ALU_SPOP;
opImm[7:0]=UCMDP_ALU_SLEEP;
tOpDecXfrm=UXFORM_CST;
end
4'h2: begin //0z2B
opUCmd=UCMD_RTE; tOpDecXfrm=UXFORM_Z;
end
4'h3: begin //0z3B
opUCmd=UCMD_UDBRK; tOpDecXfrm=UXFORM_Z;
opImm=1;
if(opCmdWord[11:8]==4'hF)
begin
opUCmd=UCMD_NONE;
opStepPc=0;
end
end
4'h6: begin //0z6B
opUCmd=UCMD_RTSN; tOpDecXfrm=UXFORM_Z;
end
default: begin end
endcase
4'hC: begin //0xxC
opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_NSO;
end
4'hD: begin //0xxD
opUCmd = opPwDQ ? UCMD_MOVQ_MR : UCMD_MOVW_MR;
tOpDecXfrm=UXFORM_MOV_NSO;
end
4'hE: begin //0xxE
opUCmd = UCMD_MOVL_MR;
tOpDecXfrm=UXFORM_MOV_NSO;
end
default: begin end
endcase
4'h1: begin //1nmd, MOV.L Rm, @(Rn, disp4)
opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM;
tOpDecXfrm=UXFORM_MOV_NSJ;
end
4'h2: case(opCmdWord[3:0])
4'h0: begin //2xx0, MOV.B Rm, @Rn
opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_NS;
end
4'h1: begin //2xx1, MOV.W Rm, @Rn
opUCmd = opPwDQ ? UCMD_MOVQ_RM : UCMD_MOVW_RM;
tOpDecXfrm=UXFORM_MOV_NS;
end
4'h2: begin //2xx2, MOV.L Rm, @Rn
opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM;
tOpDecXfrm=UXFORM_MOV_NS;
end
4'h3: begin //2xx3, CAS.L Rm, Rn, @R0
opUCmd=UCMD_CASL; tOpDecXfrm=UXFORM_MOV_NSO;
end
4'h4: begin //2xx4, MOV.B @Rm, Rn
opUCmd=UCMD_MOVB_RM; tOpDecXfrm=UXFORM_MOV_NSDEC;
tOpDecXfrmZx=UXFORMZX_PDEC;
end
4'h5: begin //2xx5, MOV.W @Rm, Rn
opUCmd = opPwDQ ? UCMD_MOVQ_RM : UCMD_MOVW_RM;
tOpDecXfrm=UXFORM_MOV_NSDEC;
tOpDecXfrmZx=UXFORMZX_PDEC;
end
4'h6: begin //2xx6, MOV.L @Rm, Rn
opUCmd = opPlDQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM;
tOpDecXfrm=UXFORM_MOV_NSDEC;
tOpDecXfrmZx=UXFORMZX_PDEC;
end
4'h7: begin //2xx7, DIV0S Rm, Rn
opUCmd=UCMD_ALU_DIV0S; tOpDecXfrm=UXFORM_ARI_ST;
end
4'h8: begin //2xx8, TST Rm, Rn
opUCmd=UCMD_CMP_TST; tOpDecXfrm=UXFORM_CMP_ST;
tOpDecXfrmZx=UXFORMZX_ZX;
end
4'h9: begin //2xx9, AND Rm, Rn
opUCmd=UCMD_ALU_AND; tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_ZX;
end
4'hA: begin //2xxA, XOR Rm, Rn
opUCmd=UCMD_ALU_XOR; tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_ZX;
end
4'hB: begin //2xxB, OR Rm, Rn
opUCmd=UCMD_ALU_OR; tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_ZX;
end
4'hC: begin //2xxC, CMPSTR Rm, Rn
opUCmd=UCMD_ALU_CMPSTR; tOpDecXfrm=UXFORM_ARI_NST;
end
4'hD: begin //2xxD, XTRCT Rm, Rn
opUCmd=UCMD_ALU_XTRCT; tOpDecXfrm=UXFORM_ARI_NST;
end
4'hE: begin //2xxE, MULU.W Rm, Rn
opUCmd=UCMD_ALU_MULUW; tOpDecXfrm=UXFORM_ARI_ST;
end
4'hF: begin //2xxF, MULS.W Rm, Rn
opUCmd=UCMD_ALU_MULSW; tOpDecXfrm=UXFORM_ARI_ST;
end
default: begin end
endcase
4'h3: case(opCmdWord[3:0])
4'h0: begin //3xx0, CMP/EQ Rm, Rn
opUCmd=opPsDQ ? UCMD_CMPQ_EQ : UCMD_CMP_EQ;
tOpDecXfrm=UXFORM_CMP_ST;
end
4'h2: begin //3xx2, CMP/HS Rm, Rn
opUCmd=opPsDQ ? UCMD_CMPQ_HS : UCMD_CMP_HS;
tOpDecXfrm=UXFORM_CMP_ST;
end
4'h3: begin //3xx3, CMP/GE Rm, Rn
opUCmd=opPsDQ ? UCMD_CMPQ_GE : UCMD_CMP_GE;
tOpDecXfrm=UXFORM_CMP_ST;
end
4'h4: begin //3xx4, DIV1 Rm, Rn
opUCmd=UCMD_ALU_DIV1; tOpDecXfrm=UXFORM_ARI_NST;
end
4'h5: begin //3xx5, DMULU.L Rm, Rn
opUCmd=UCMD_ALU_DMULU; tOpDecXfrm=UXFORM_ARI_ST;
end
4'h6: begin //3xx6, CMP/HI Rm, Rn
opUCmd=opPsDQ ? UCMD_CMPQ_HI : UCMD_CMP_HI;
tOpDecXfrm=UXFORM_CMP_ST;
end
4'h7: begin //3xx7, CMP/GT Rm, Rn
opUCmd=opPsDQ ? UCMD_CMPQ_GT : UCMD_CMP_GT;
tOpDecXfrm=UXFORM_CMP_ST;
end
4'h8: begin //3xx8, SUB Rm, Rn
opUCmd=UCMD_ALU_SUB; tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_ZX;
end
4'hA: begin //3xxA, SUBC Rm, Rn
opUCmd=UCMD_ALU_SUBC; tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_ZX;
end
4'hB: begin //3xxB, SUBV Rm, Rn
opUCmd=UCMD_ALU_SUBV; tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_ZX;
end
4'hC: begin //3xxC, ADD Rm, Rn
opUCmd=UCMD_ALU_ADD; tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_ZX;
end
4'hD: begin //3xxD, DMULS.L Rm, Rn
opUCmd=UCMD_ALU_DMULS; tOpDecXfrm=UXFORM_ARI_ST;
end
4'hE: begin //3xxE, ADDC Rm, Rn
opUCmd=UCMD_ALU_ADDC; tOpDecXfrm=UXFORM_ARI_NST;
end
4'hF: begin //3xxF, ADDV Rm, Rn
opUCmd=UCMD_ALU_ADDV; tOpDecXfrm=UXFORM_ARI_NST;
end
default: begin end
endcase
4'h4: case(opCmdWord[3:0])
4'h0: case(opCmdWord[7:4])
4'h0: begin //4x00
opUCmd=UCMD_ALU_SHLL; tOpDecXfrm=UXFORM_N;
end
4'h1: begin //4x10
opUCmd=UCMD_ALU_DT; tOpDecXfrm=UXFORM_N;
end
4'h2: begin //4x20
opUCmd=UCMD_ALU_SHAL; tOpDecXfrm=UXFORM_N;
end
default: begin end
endcase
4'h1: case(opCmdWord[7:4])
4'h0: begin //4x01
opUCmd=UCMD_ALU_SHLR; tOpDecXfrm=UXFORM_N;
end
4'h1: begin //4x11
opUCmd=opPsDQ ? UCMD_CMPQ_GE : UCMD_CMP_GE;
tOpDecXfrm=UXFORM_M;
end
4'h2: begin //4x21
opUCmd=UCMD_ALU_SHAR; tOpDecXfrm=UXFORM_N;
end
default: begin end
endcase
4'h2: begin //4xx2
opUCmd = opJQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM;
tOpDecXfrm=UXFORM_MOVC_NSDEC;
tOpDecXfrmZx=UXFORMZX_SR;
end
4'h3: begin //4xx3
opUCmd = opJQ ? UCMD_MOVQ_RM : UCMD_MOVL_RM;
tOpDecXfrm=UXFORM_MOVC_NSDEC;
tOpDecXfrmZx=UXFORMZX_CR;
end
4'h4: case(opCmdWord[7:4])
4'h0: begin //4x00
opUCmd=UCMD_ALU_ROTL; tOpDecXfrm=UXFORM_N;
end
// 4'h1: begin //4x10
// opUCmd=UCMD_ALU_DT; tOpDecXfrm=UXFORM_N;
// end
4'h2: begin //4x20
opUCmd=UCMD_ALU_ROTCL; tOpDecXfrm=UXFORM_N;
end
default: begin end
endcase
4'h5: case(opCmdWord[7:4])
4'h0: begin //4x01
opUCmd=UCMD_ALU_ROTR; tOpDecXfrm=UXFORM_N;
end
4'h1: begin //4x11
opUCmd=opPsDQ ? UCMD_CMPQ_GT : UCMD_CMP_GT;
tOpDecXfrm=UXFORM_M;
end
4'h2: begin //4x21
opUCmd=UCMD_ALU_ROTCR; tOpDecXfrm=UXFORM_N;
end
default: begin end
endcase
4'h6: begin //4xx6
opUCmd = opJQ ? UCMD_MOVQ_MR : UCMD_MOVL_MR;
tOpDecXfrm=UXFORM_MOVC_NSDEC;
tOpDecXfrmZx=UXFORMZX_RS;
end
4'h7: begin //4xx7
opUCmd = opJQ ? UCMD_MOVQ_RM : UCMD_MOVL_MR;
tOpDecXfrm=UXFORM_MOVC_NSDEC;
tOpDecXfrmZx=UXFORMZX_RC;
end
4'h8: case(opCmdWord[7:4])
4'h0: begin //4x08
opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C;
opImm=2;
end
4'h1: begin //4x18
opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C;
opImm=8;
end
4'h2: begin //4x28
opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C;
opImm=16;
end
default: begin end
endcase
4'h9: case(opCmdWord[7:4])
4'h0: begin //4x09
opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C;
opImm=-2;
end
4'h1: begin //4x19
opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C;
opImm=-8;
end
4'h2: begin //4x29
opUCmd=UCMD_ALU_SHLD; tOpDecXfrm=UXFORM_N_C;
opImm=-16;
end
default: begin end
endcase
4'hA: begin //4xxA, LDS
opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARIC_NS;
tOpDecXfrmZx=UXFORMZX_RS;
end
4'hB: case(opCmdWord[7:4])
4'h0: begin
opUCmd=UCMD_JSR; tOpDecXfrm=UXFORM_M;
end
4'h2: begin
opUCmd=UCMD_JMP; tOpDecXfrm=UXFORM_M;
end
4'h3: begin
end
4'h4: begin
opUCmd=UCMD_JSRN; tOpDecXfrm=UXFORM_M;
end
default: begin end
endcase
4'hC: begin //4xxC
opUCmd=opPsDQ ? UCMD_ALU_SHADQ : UCMD_ALU_SHAD;
tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_SX;
end
4'hD: begin //4xxD
opUCmd=opPsDQ ? UCMD_ALU_SHLDQ : UCMD_ALU_SHLD;
tOpDecXfrm=UXFORM_ARI_NST;
tOpDecXfrmZx=UXFORMZX_SX;
end
4'hE: begin //4xxE, LDC
opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARIC_NS;
tOpDecXfrmZx=UXFORMZX_RC;
end
default: begin end
endcase
4'h5: begin //5xxx
opUCmd = UCMD_MOVL_MR;
tOpDecXfrm=UXFORM_MOV_NSJ;
end
4'h6: case(opCmdWord[3:0])
4'h0: begin //6xx0
opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_NS;
end
4'h1: begin //6xx1
opUCmd = opPwDQ ? UCMD_MOVQ_MR : UCMD_MOVW_MR;
tOpDecXfrm=UXFORM_MOV_NS;
end
4'h2: begin //6xx2
opUCmd = UCMD_MOVL_MR;
tOpDecXfrm=UXFORM_MOV_NS;
end
4'h3: begin //6xx3
opUCmd=UCMD_MOV_RR; tOpDecXfrm=UXFORM_ARI_NS;
end
4'h4: begin //6xx4
opUCmd=UCMD_MOVB_MR; tOpDecXfrm=UXFORM_MOV_NSDEC;
tOpDecXfrmZx=UXFORMZX_PINC;
end
4'h5: begin //6xx5
opUCmd = opPwDQ ? UCMD_MOVQ_MR : UCMD_MOVW_MR;
tOpDecXfrm=UXFORM_MOV_NSDEC;
tOpDecXfrmZx=UXFORMZX_PINC;
end
4'h6: begin //6xx6
opUCmd = UCMD_MOVL_MR;
tOpDecXfrm=UXFORM_MOV_NSDEC;
tOpDecXfrmZx=UXFORMZX_PINC;
end
4'h7: begin
opUCmd=UCMD_ALU_NOT; tOpDecXfrm=UXFORM_ARI_NS;
end
4'h8: begin
opUCmd=UCMD_ALU_SWAPB; tOpDecXfrm=UXFORM_ARI_NS;
end
4'h9: begin
opUCmd=UCMD_ALU_SWAPW; tOpDecXfrm=UXFORM_ARI_NS;
end
4'hA: begin
opUCmd=UCMD_ALU_NEGC; tOpDecXfrm=UXFORM_ARI_NS;
end
4'hB: begin
opUCmd=UCMD_ALU_NEG; tOpDecXfrm=UXFORM_ARI_NS;
end
4'hC: begin
opUCmd=UCMD_ALU_EXTUB; tOpDecXfrm=UXFORM_ARI_NS;
end
4'hD: begin
opUCmd=UCMD_ALU_EXTUW; tOpDecXfrm=UXFORM_ARI_NS;
end
4'hE: begin
opUCmd=UCMD_ALU_EXTSB; tOpDecXfrm=UXFORM_ARI_NS;
end
4'hF: begin
opUCmd=UCMD_ALU_EXTSW; tOpDecXfrm=UXFORM_ARI_NS;
end
default: begin end
endcase
4'h7: begin //7xxx
opUCmd=UCMD_ALU_ADD; tOpDecXfrm=UXFORM_ARI_NNI;
end
4'h8: case(opCmdWord[11:8])
4'h0: begin //80xx
opUCmd=UCMD_MOVB_RM;
tOpDecXfrm=UXFORM_MOV_SP4RN;
tOpDecXfrmZx=UXFORMZX_RM0;
end
4'h1: begin //81xx
opUCmd=UCMD_MOVW_RM;
tOpDecXfrm=UXFORM_MOV_SP4RN;
tOpDecXfrmZx=UXFORMZX_RM0;
end
4'h2: begin //82xx
opUCmd=UCMD_BRAN; tOpDecXfrm=UXFORM_BR_D8;
end
4'h3: begin //83xx
tOpDecXfrm=UXFORM_MOV_SP4RN;
if(opCmdWord[7])
begin
opUCmd=UCMD_MOVL_MR;
tOpDecXfrmZx=UXFORMZX_MR3;
end else begin
opUCmd=UCMD_MOVL_RM;
tOpDecXfrmZx=UXFORMZX_RM3;
end
end
4'h4: begin //84xx
opUCmd=UCMD_MOVB_MR;
tOpDecXfrm=UXFORM_MOV_SP4RN;
tOpDecXfrmZx=UXFORMZX_MR0;
end
4'h5: begin //85xx
opUCmd=UCMD_MOVW_MR;
tOpDecXfrm=UXFORM_MOV_SP4RN;
tOpDecXfrmZx=UXFORMZX_MR0;
end
4'h6: begin //86xx
tOpDecXfrm=UXFORM_MOV_SP4RN;
if(opCmdWord[7])
begin
opUCmd=UCMD_MOVL_MR;
tOpDecXfrmZx=UXFORMZX_MF3;
end else begin
opUCmd=UCMD_MOVL_RM;
tOpDecXfrmZx=UXFORMZX_FM3;
end
end
4'h7: begin //87xx
end
4'h8: begin //88xx
opUCmd=UCMD_CMP_EQ;
tOpDecXfrm=UXFORM_ARI_I8R0;
end
4'h9: begin //89xx
opUCmd=UCMD_BT; tOpDecXfrm=UXFORM_BR_D8;
end
4'hA: begin //8Axx-xxxx
if(decEnableBJX1)
begin
opRegN=UREG_R0;
opUCmd=UCMD_MOV_RI;
opImm={istrWord[7] ? 8'hFF : 8'h00,
istrWord[7:0], istrWord[31:16]};
tOpDecXfrm=UXFORM_CST;
end
end
4'hB: begin //8Bxx, BF disp
opUCmd=UCMD_BF; tOpDecXfrm=UXFORM_BR_D8;
end
4'hC: begin //8Cxx
/* Escape */
end
4'hD: begin //8Dxx, BTS disp
opUCmd=UCMD_BTS; tOpDecXfrm=UXFORM_BR_D8;
end
4'hE: begin //8Exx
/* Escape */
if(decEnableBJX1)
begin
isOpXE = 1;
opStepPc = 4;
end
end
4'hF: begin //8Fxx, BFS disp
opUCmd=UCMD_BFS; tOpDecXfrm=UXFORM_BR_D8;
end
default: begin end
endcase
4'h9: begin //9xxx
opRegN[3:0]=opCmdWord[11:8];
opRegS=UREG_PCW;
opRegT=UREG_ZZR;
opImm[7:0]=opCmdWord[ 7:0];
opUCmd=UCMD_MOVW_MR;
tOpDecXfrm=UXFORM_CST;
end
4'hA: begin //Axxx
opUCmd=UCMD_BRA; tOpDecXfrm=UXFORM_BR_D12;
end
4'hB: begin //Bxxx
opUCmd=UCMD_BSR; tOpDecXfrm=UXFORM_BR_D12;
end
4'hC: case(opCmdWord[11:8])
4'h0: begin
if(opJQ)
begin
opUCmd=UCMD_MOVQ_RM;
tOpDecXfrm=UXFORM_MOV_SP4RN;
tOpDecXfrmZx=UXFORMZX_RM;
end else begin
opUCmd=UCMD_MOVB_RM;
tOpDecXfrm=UXFORM_MOV_GD8R0;
tOpDecXfrmZx=UXFORMZX_RM;
end
end
4'h1: begin
if(opJQ)
begin
end else begin
opUCmd=UCMD_MOVW_RM;
tOpDecXfrm=UXFORM_MOV_GD8R0;
tOpDecXfrmZx=UXFORMZX_RM;
end
end
4'h2: begin
if(opJQ)
begin
end else begin
opUCmd=UCMD_MOVL_RM;
tOpDecXfrm=UXFORM_MOV_GD8R0;
tOpDecXfrmZx=UXFORMZX_RM;
end
end
4'h4: begin
if(opJQ)
begin
opUCmd=UCMD_MOVQ_MR;
tOpDecXfrm=UXFORM_MOV_SP4RN;
tOpDecXfrmZx=UXFORMZX_MR;
end else begin
opUCmd=UCMD_MOVB_MR;
tOpDecXfrm=UXFORM_MOV_GD8R0;
tOpDecXfrmZx=UXFORMZX_MR;
end
end
4'h5: begin
if(opJQ)
begin
end else begin
opUCmd=UCMD_MOVW_MR;
tOpDecXfrm=UXFORM_MOV_GD8R0;
tOpDecXfrmZx=UXFORMZX_MR;
end
end
4'h6: begin
if(opJQ)
begin
end else begin
opUCmd=UCMD_MOVL_MR;
tOpDecXfrm=UXFORM_MOV_GD8R0;
tOpDecXfrmZx=UXFORMZX_MR;
end
end
4'h8: begin //CMP/EQ #imm, R0
opUCmd=opPsDQ ? UCMD_CMPQ_TST : UCMD_CMP_TST;
tOpDecXfrm=UXFORM_CMP_I8R0;
end
4'h9: begin //AND #imm, R0
opUCmd=UCMD_ALU_AND; tOpDecXfrm=UXFORM_ARI_I8R0;
end
4'hA: begin //XOR #imm, R0
opUCmd=UCMD_ALU_XOR; tOpDecXfrm=UXFORM_ARI_I8R0;
end
4'hB: begin //OR #imm, R0
opUCmd=UCMD_ALU_OR; tOpDecXfrm=UXFORM_ARI_I8R0;
end
default: begin end
endcase
4'hD: begin //Dxxx, MOV @(PC,disp), Rn
opRegN[3:0]=opCmdWord[11:8];
opRegS=UREG_PCL;
opRegT=UREG_ZZR;
opImm[7:0]=opCmdWord[ 7:0];
opUCmd=UCMD_MOVL_MR;
tOpDecXfrm=UXFORM_CST;
end
4'hE: begin //Exxx, MOV #imm, Rn
opUCmd=UCMD_MOV_RI;
tOpDecXfrm=UXFORM_ARI_NNI;
end
4'hF: case(opCmdWord[3:0])
4'h0: begin
opUCmd=UCMD_FPU_ADD;
tOpDecXfrm=UXFORM_FPARI_NS;
end
4'h1: begin
opUCmd=UCMD_FPU_SUB;
tOpDecXfrm=UXFORM_FPARI_NS;
end
4'h2: begin
opUCmd=UCMD_FPU_MUL;
tOpDecXfrm=UXFORM_FPARI_NS;
end
4'h4: begin
opUCmd=UCMD_FPU_CMPEQ;
tOpDecXfrm=UXFORM_FPARI_NS;
end
4'h5: begin
opUCmd=UCMD_FPU_CMPGT;
tOpDecXfrm=UXFORM_FPARI_NS;
end
4'h6: begin
opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSO;
tOpDecXfrmZx=UXFORMZX_RF;
end
4'h7: begin
opUCmd=UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSO;
tOpDecXfrmZx=UXFORMZX_FR;
end
4'h8: begin
opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NS;
tOpDecXfrmZx=UXFORMZX_RF;
end
4'h9: begin
opUCmd=UCMD_MOVL_MR; tOpDecXfrm=UXFORM_MOV_NSDEC;
tOpDecXfrmZx=UXFORMZX_RFI;
end
4'hA: begin
opUCmd=UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NS;
tOpDecXfrmZx=UXFORMZX_FR;
end
// 4'hB: begin
// opUCmd=UCMD_MOVL_RM; tOpDecXfrm=UXFORM_MOV_NSDEC;
// opIsRegM_FR=1;
// tOpDecXfrmZx=UXFORMZX_FRD;
// end
default: begin end
endcase
default: begin end
endcase
opRegN_Dfl = {3'b000, opCmdWord[11:8]};
opRegM_Dfl = {3'b000, opCmdWord[ 7:4]};
opRegO_Dfl = {3'b000, opCmdWord[ 3:0]};
if(opCmdWord[11]) //RmB
opRegM_CR={3'h2, 1'b0, opCmdWord[6:4]};
else
opRegM_CR={3'h7, opCmdWord[7:4]};
opRegM_SR={3'h6, opCmdWord[7:4]};
opRegN_FR = {3'h4, opCmdWord[11:8]};
opRegM_FR = {3'h4, opCmdWord[ 7:4]};
opRegO_FR = {3'h4, opCmdWord[ 3:0]};
opRegN_N3 = (opCmdWord[6:4]==3'b111) ? UREG_R0 :
{3'h0, 1'b1, opCmdWord[6:4]};
opRegM_N3 = (opCmdWord[2:0]==3'b111) ? UREG_R0 :
{3'h0, 1'b1, opCmdWord[2:0]};
opImm_Zx4 = {28'h0, opCmdWord[ 3:0]};
opImm_Zx8 = {24'h0, opCmdWord[ 7:0]};
opImm_Sx8 = {opCmdWord[ 7] ? 24'hFFFFFF : 24'h000000, opCmdWord [ 7:0]};
opImm_Sx12 = {opCmdWord[11] ? 20'hFFFFF : 20'h00000 , opCmdWord [11:0]};
// /*
case(tOpDecXfrm)
UXFORM_CST: begin
end
UXFORM_N: begin
opRegN=opRegN_Dfl;
opRegS=opRegN;
end
UXFORM_MOV_NS: begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
end
UXFORM_MOV_NSO: begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
opRegT=UREG_R0; opImm=0;
end
UXFORM_MOV_NSJ: begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
opImm = opImm_Zx4;
end
UXFORM_MOV_NSDEC: begin
case(tOpDecXfrmZx)
UXFORMZX_PDEC: begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
opRegT=UREG_MR_MEMDEC;
end
UXFORMZX_PINC: begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
opRegT=UREG_MR_MEMINC;
end
UXFORMZX_FRD: begin
opRegN=opRegN_Dfl; opRegS=opRegM_FR;
opRegT=UREG_MR_MEMDEC;
end
UXFORMZX_RFI: begin
opRegN=opRegN_FR; opRegS=opRegM_Dfl;
opRegT=UREG_MR_MEMINC;
end
default: begin
opRegN=UREG_XX; opRegS=UREG_XX;
opRegT=UREG_XX; opImm=32'hXXXXXXXX;
end
endcase
end
UXFORM_MOVC_NSDEC: begin
case(tOpDecXfrmZx)
UXFORMZX_RS: begin
opRegN=opRegM_SR; opRegS=opRegN_Dfl;
opRegT=UREG_MR_MEMINC;
end
UXFORMZX_RC: begin
opRegN=opRegM_CR; opRegS=opRegN_Dfl;
opRegT=UREG_MR_MEMINC;
end
UXFORMZX_SR: begin
opRegN=opRegN_Dfl; opRegS=opRegM_SR;
opRegT=UREG_MR_MEMDEC;
end
UXFORMZX_CR: begin
opRegN=opRegN_Dfl; opRegS=opRegM_CR;
opRegT=UREG_MR_MEMDEC;
end
default: begin
opRegN=UREG_XX; opRegS=UREG_XX;
opRegT=UREG_XX; opImm=32'hXXXXXXXX;
end
endcase
end
UXFORM_FPARI_NS: begin
opRegN=opRegN_FR;
opRegS=opRegM_FR;
end
UXFORM_ARI_NS: begin
case(tOpDecXfrmZx)
UXFORMZX_RR: begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
end
UXFORMZX_FF: begin
opRegN=opRegN_FR; opRegS=opRegM_FR;
end
default: begin
opRegN=UREG_XX; opRegS=UREG_XX;
opRegT=UREG_XX; opImm=32'hXXXXXXXX;
end
endcase
end
UXFORM_ARIC_NS: begin
case(tOpDecXfrmZx)
UXFORMZX_RS: begin
opRegN=opRegM_SR; opRegS=opRegN_Dfl;
end
UXFORMZX_RC: begin
opRegN=opRegM_CR; opRegS=opRegN_Dfl;
end
UXFORMZX_SR: begin
opRegN=opRegN_Dfl; opRegS=opRegM_SR;
end
UXFORMZX_CR: begin
opRegN=opRegN_Dfl; opRegS=opRegM_CR;
end
default: begin
opRegN=UREG_XX; opRegS=UREG_XX;
opRegT=UREG_XX; opImm=32'hXXXXXXXX;
end
endcase
end
UXFORM_ARI_NST: begin
opRegN=opRegN_Dfl; opRegS=opRegN_Dfl; opRegT=opRegM_Dfl;
end
UXFORM_CMP_ST: begin
opRegS=opRegN_Dfl; opRegT=opRegM_Dfl;
end
UXFORM_ARI_ST: begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
end
UXFORM_ARI_NNI: begin
opRegN=opRegN_Dfl; opRegS=opRegN_Dfl;
opRegT=UREG_MR_IMM; opImm=opImm_Sx8;
end
UXFORM_BR_D8: begin
opImm = opImm_Sx8;
end
UXFORM_BR_D12: begin
opImm = opImm_Sx12;
end
UXFORM_ARI_I8R0: begin
opRegN=UREG_R0; opRegS=UREG_R0;
opRegT=UREG_MR_IMM; opImm=opImm_Zx8;
end
UXFORM_N_C: begin
opRegN=opRegN_Dfl; opRegS=opRegN_Dfl;
opRegT=UREG_MR_IMM;
end
UXFORM_MOV_GD8R0: begin
case(tOpDecXfrmZx)
UXFORMZX_RM: begin
opRegN=UREG_GBR; opRegS=UREG_R0;
opRegT=UREG_MR_IMM; opImm=opImm_Zx8;
end
UXFORMZX_MR: begin
opRegN=UREG_R0; opRegS=UREG_GBR;
opRegT=UREG_MR_IMM; opImm=opImm_Zx8;
end
default: begin
opRegN=UREG_XX; opRegS=UREG_XX;
opRegT=UREG_XX; opImm=32'hXXXXXXXX;
end
endcase
end
UXFORM_MOV_SP4RN: begin
case(tOpDecXfrmZx)
UXFORMZX_RM: begin
opRegN=UREG_R15; opRegS=opRegM_Dfl;
opRegT=UREG_MR_IMM; opImm=opImm_Zx4;
end
UXFORMZX_MR: begin
opRegN=opRegM_Dfl; opRegS=UREG_R15;
opRegT=UREG_MR_IMM; opImm=opImm_Zx4;
end
UXFORMZX_RM3: begin
opRegN=UREG_R15; opRegS=opRegN_N3;
opRegT=UREG_MR_IMM;
opImm[3:0]=opCmdWord[3:0];
opImm[31:4]=1;
end
UXFORMZX_MR3: begin
opRegN=opRegN_N3; opRegS=UREG_R15;
opRegT=UREG_MR_IMM;
opImm[3:0]=opCmdWord[3:0];
opImm[31:4]=1;
end
UXFORMZX_FM3: begin
opRegN=UREG_R15;
opRegS={3'h4, 1'b1, opCmdWord[6:4]};
opRegT=UREG_MR_IMM; opImm=opImm_Zx4;
end
UXFORMZX_MF3: begin
opRegN={3'h4, 1'b1, opCmdWord[6:4]};
opRegS=UREG_R15;
opRegT=UREG_MR_IMM; opImm=opImm_Zx4;
end
UXFORMZX_RM0: begin
opRegN=opRegM_Dfl; opRegS=UREG_R0;
opRegT=UREG_MR_IMM; opImm=opImm_Zx4;
end
UXFORMZX_MR0: begin
opRegN=UREG_R0; opRegS=opRegM_Dfl;
opRegT=UREG_MR_IMM; opImm=opImm_Zx4;
end
default: begin
opRegN=UREG_XX; opRegS=UREG_XX;
opRegT=UREG_XX; opImm=32'hXXXXXXXX;
end
endcase
end
UXFORM_INVALID: begin
opRegN=UREG_XX; opRegS=UREG_XX;
opRegT=UREG_XX; opImm=32'hXXXXXXXX;
end
default: begin
opRegN=UREG_XX; opRegS=UREG_XX;
opRegT=UREG_XX; opImm=32'hXXXXXXXX;
end
endcase
// */
/*
casez({tOpDecXfrm, tOpDecXfrmZx})
{UXFORM_CST, UXFORMZX_X}: begin
end
{UXFORM_N, UXFORMZX_X}: begin
opRegN=opRegN_Dfl;
opRegS=opRegN;
end
{UXFORM_MOV_NS, UXFORMZX_X}: begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
end
{UXFORM_MOV_NSO, UXFORMZX_X}: begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
opRegT=UREG_R0; opImm=0;
end
{UXFORM_MOV_NSJ, UXFORMZX_X}: begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
opImm = opImm_Zx4;
end
{UXFORM_MOV_NSDEC, UXFORMZX_PDEC}: begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
opRegT=UREG_MR_MEMDEC;
end
{UXFORM_MOV_NSDEC, UXFORMZX_PINC}: begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
opRegT=UREG_MR_MEMINC;
end
{UXFORM_MOV_NSDEC, UXFORMZX_FRD}: begin
opRegN=opRegN_Dfl; opRegS=opRegM_FR;
opRegT=UREG_MR_MEMDEC;
end
{UXFORM_MOV_NSDEC, UXFORMZX_RFI}: begin
opRegN=opRegN_FR; opRegS=opRegM_Dfl;
opRegT=UREG_MR_MEMINC;
end
{UXFORM_MOVC_NSDEC, UXFORMZX_RS}: begin
opRegN=opRegM_SR; opRegS=opRegN_Dfl;
opRegT=UREG_MR_MEMINC;
end
{UXFORM_MOVC_NSDEC, UXFORMZX_RC}: begin
opRegN=opRegM_CR; opRegS=opRegN_Dfl;
opRegT=UREG_MR_MEMINC;
end
{UXFORM_MOVC_NSDEC, UXFORMZX_SR}: begin
opRegN=opRegN_Dfl; opRegS=opRegM_SR;
opRegT=UREG_MR_MEMDEC;
end
{UXFORM_MOVC_NSDEC, UXFORMZX_CR}: begin
opRegN=opRegN_Dfl; opRegS=opRegM_CR;
opRegT=UREG_MR_MEMDEC;
end
{UXFORM_FPARI_NS, UXFORMZX_X}: begin
opRegN=opRegN_FR; opRegS=opRegM_FR;
end
{UXFORM_ARI_NS, UXFORMZX_RR}: begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
end
{UXFORM_ARI_NS, UXFORMZX_FF}: begin
opRegN=opRegN_FR; opRegS=opRegM_FR;
end
{UXFORM_ARIC_NS, UXFORMZX_RS}: begin
opRegN=opRegM_SR; opRegS=opRegN_Dfl;
end
{UXFORM_ARIC_NS, UXFORMZX_RC}: begin
opRegN=opRegM_CR; opRegS=opRegN_Dfl;
end
{UXFORM_ARIC_NS, UXFORMZX_SR}: begin
opRegN=opRegN_Dfl; opRegS=opRegM_SR;
end
{UXFORM_ARIC_NS, UXFORMZX_CR}: begin
opRegN=opRegN_Dfl; opRegS=opRegM_CR;
end
{UXFORM_ARI_NST, UXFORMZX_X}: begin
opRegN=opRegN_Dfl; opRegS=opRegN_Dfl; opRegT=opRegM_Dfl;
end
{UXFORM_CMP_ST, UXFORMZX_X}: begin
opRegS=opRegN_Dfl; opRegT=opRegM_Dfl;
end
{UXFORM_ARI_ST, UXFORMZX_X}: begin
opRegN=opRegN_Dfl; opRegS=opRegM_Dfl;
end
{UXFORM_ARI_NNI, UXFORMZX_X}: begin
opRegN=opRegN_Dfl; opRegS=opRegN_Dfl;
opRegT=UREG_MR_IMM; opImm=opImm_Sx8;
end
{UXFORM_BR_D8, UXFORMZX_X}: begin
opImm = opImm_Sx8;
end
{UXFORM_BR_D12, UXFORMZX_X}: begin
opImm = opImm_Sx12;
end
{UXFORM_ARI_I8R0, UXFORMZX_X}: begin
opRegN=UREG_R0; opRegS=UREG_R0;
opRegT=UREG_MR_IMM; opImm=opImm_Zx8;
end
{UXFORM_N_C, UXFORMZX_X}: begin
opRegN=opRegN_Dfl; opRegS=opRegN_Dfl;
opRegT=UREG_MR_IMM;
end
{UXFORM_MOV_GD8R0, UXFORMZX_RM}: begin
opRegN=UREG_GBR; opRegS=UREG_R0;
opRegT=UREG_MR_IMM; opImm=opImm_Zx8;
end
{UXFORM_MOV_GD8R0, UXFORMZX_MR}: begin
opRegN=UREG_R0; opRegS=UREG_GBR;
opRegT=UREG_MR_IMM; opImm=opImm_Zx8;
end
{UXFORM_MOV_SP4RN, UXFORMZX_RM}: begin
opRegN=UREG_R15; opRegS=opRegM_Dfl;
opRegT=UREG_MR_IMM; opImm=opImm_Zx4;
end
{UXFORM_MOV_SP4RN, UXFORMZX_MR}: begin
opRegN=opRegM_Dfl; opRegS=UREG_R15;
opRegT=UREG_MR_IMM; opImm=opImm_Zx4;
end
{UXFORM_MOV_SP4RN, UXFORMZX_RM3}: begin
opRegN=UREG_R15; opRegS=opRegN_N3;
opRegT=UREG_MR_IMM;
opImm[3:0]=opCmdWord[3:0];
opImm[31:4]=1;
end
{UXFORM_MOV_SP4RN, UXFORMZX_MR3}: begin
opRegN=opRegN_N3; opRegS=UREG_R15;
opRegT=UREG_MR_IMM;
opImm[3:0]=opCmdWord[3:0];
opImm[31:4]=1;
end
{UXFORM_MOV_SP4RN, UXFORMZX_FM3}: begin
opRegN=UREG_R15;
opRegS={3'h4, 1'b1, opCmdWord[6:4]};
opRegT=UREG_MR_IMM; opImm=opImm_Zx4;
end
{UXFORM_MOV_SP4RN, UXFORMZX_MF3}: begin
opRegN={3'h4, 1'b1, opCmdWord[6:4]};
opRegS=UREG_R15;
opRegT=UREG_MR_IMM; opImm=opImm_Zx4;
end
{UXFORM_MOV_SP4RN, UXFORMZX_RM0}: begin
opRegN=opRegM_Dfl; opRegS=UREG_R0;
opRegT=UREG_MR_IMM; opImm=opImm_Zx4;
end
{UXFORM_MOV_SP4RN, UXFORMZX_MR0}: begin
opRegN=UREG_R0; opRegS=opRegM_Dfl;
opRegT=UREG_MR_IMM; opImm=opImm_Zx4;
end
{UXFORM_INVALID, UXFORMZX_X}: begin
opRegN=UREG_XX; opRegS=UREG_XX;
opRegT=UREG_XX; opImm=32'hXXXXXXXX;
end
default: begin
opRegN=UREG_XX; opRegS=UREG_XX;
opRegT=UREG_XX; opImm=32'hXXXXXXXX;
end
endcase
*/
// if(isOpXE)
if(0)
begin
opRegN=opRegXeN; opRegS=opRegXeS;
opRegT=opRegXeT; opImm=opImmXe;
opUCmd=opUCmdXe;
opStepPc2=opStepPc2A;
end
else
begin
opStepPc2=opStepPc2B;
end
end
endmodule
|
/*
* Copyright (c) 2001 Uwe Bonnes
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
`define ADC_DATA_OFFSET 5
`define ADC_CHANELS 8*48
//`define ADC_CHANELS 348
module mymod (out1,out2,state,reset);
input [8:0] state;
input reset;
output out1,out2;
assign out1 = (state > `ADC_DATA_OFFSET) ? 1 : 0;
assign out2 = (state > `ADC_CHANELS + `ADC_DATA_OFFSET +1)|| (reset);
endmodule // mymod
module t;
reg [8:0] state;
reg reset;
wire out1,out2;
mymod m1 (out1,out2,state,reset);
initial
begin
//$timeformat(-9,0,"ns",5);
$display(" TIME:state:out1:out2");
$monitor("%7t:%5d:%3d:%3d",$time,state,out1,out2);
state =0;
reset = 0;
#10
reset=1;
#20
reset=0;
#5110
$finish(0);
end
always
begin
#10
if (reset)
state = 0;
else
state=state+1;
end
endmodule // t
|
(** * ProofObjects: Working with Explicit Evidence in Coq *)
Require Export MoreLogic.
(* ##################################################### *)
(** We have seen that Coq has mechanisms both for _programming_,
using inductive data types (like [nat] or [list]) and functions
over these types, and for _proving_ properties of these programs,
using inductive propositions (like [ev] or [eq]), implication, and
universal quantification. So far, we have treated these mechanisms
as if they were quite separate, and for many purposes this is
a good way to think. But we have also seen hints that Coq's programming and
proving facilities are closely related. For example, the
keyword [Inductive] is used to declare both data types and
propositions, and [->] is used both to describe the type of
functions on data and logical implication. This is not just a
syntactic accident! In fact, programs and proofs in Coq are almost
the same thing. In this chapter we will study how this works.
We have already seen the fundamental idea: provability in Coq is
represented by concrete _evidence_. When we construct the proof
of a basic proposition, we are actually building a tree of evidence,
which can be thought of as a data structure. If the proposition
is an implication like [A -> B], then its proof will be an
evidence _transformer_: a recipe for converting evidence for
A into evidence for B. So at a fundamental level, proofs are simply
programs that manipulate evidence.
*)
(**
Q. If evidence is data, what are propositions themselves?
A. They are types!
Look again at the formal definition of the [beautiful] property. *)
Print beautiful.
(* ==>
Inductive beautiful : nat -> Prop :=
b_0 : beautiful 0
| b_3 : beautiful 3
| b_5 : beautiful 5
| b_sum : forall n m : nat, beautiful n -> beautiful m -> beautiful (n + m)
*)
(** *** *)
(** The trick is to introduce an alternative pronunciation of "[:]".
Instead of "has type," we can also say "is a proof of." For
example, the second line in the definition of [beautiful] declares
that [b_0 : beautiful 0]. Instead of "[b_0] has type
[beautiful 0]," we can say that "[b_0] is a proof of [beautiful 0]."
Similarly for [b_3] and [b_5]. *)
(** *** *)
(** This pun between types and propositions (between [:] as "has type"
and [:] as "is a proof of" or "is evidence for") is called the
_Curry-Howard correspondence_. It proposes a deep connection
between the world of logic and the world of computation.
<<
propositions ~ types
proofs ~ data values
>>
Many useful insights follow from this connection. To begin with, it
gives us a natural interpretation of the type of [b_sum] constructor: *)
Check b_sum.
(* ===> b_sum : forall n m,
beautiful n ->
beautiful m ->
beautiful (n+m) *)
(** This can be read "[b_sum] is a constructor that takes four
arguments -- two numbers, [n] and [m], and two pieces of evidence,
for the propositions [beautiful n] and [beautiful m], respectively --
and yields evidence for the proposition [beautiful (n+m)]." *)
(** Now let's look again at a previous proof involving [beautiful]. *)
Theorem eight_is_beautiful: beautiful 8.
Proof.
apply b_sum with (n := 3) (m := 5).
apply b_3.
apply b_5. Qed.
(** Just as with ordinary data values and functions, we can use the [Print]
command to see the _proof object_ that results from this proof script. *)
Print eight_is_beautiful.
(* ===> eight_is_beautiful = b_sum 3 5 b_3 b_5
: beautiful 8 *)
(** In view of this, we might wonder whether we can write such
an expression ourselves. Indeed, we can: *)
Check (b_sum 3 5 b_3 b_5).
(* ===> beautiful (3 + 5) *)
(** The expression [b_sum 3 5 b_3 b_5] can be thought of as
instantiating the parameterized constructor [b_sum] with the
specific arguments [3] [5] and the corresponding proof objects for
its premises [beautiful 3] and [beautiful 5] (Coq is smart enough
to figure out that 3+5=8). Alternatively, we can think of [b_sum]
as a primitive "evidence constructor" that, when applied to two
particular numbers, wants to be further applied to evidence that
those two numbers are beautiful; its type,
forall n m, beautiful n -> beautiful m -> beautiful (n+m),
expresses this functionality, in the same way that the polymorphic
type [forall X, list X] in the previous chapter expressed the fact
that the constructor [nil] can be thought of as a function from
types to empty lists with elements of that type. *)
(** This gives us an alternative way to write the proof that [8] is
beautiful: *)
Theorem eight_is_beautiful': beautiful 8.
Proof.
apply (b_sum 3 5 b_3 b_5).
Qed.
(** Notice that we're using [apply] here in a new way: instead of just
supplying the _name_ of a hypothesis or previously proved theorem
whose type matches the current goal, we are supplying an
_expression_ that directly builds evidence with the required
type. *)
(* ##################################################### *)
(** * Proof Scripts and Proof Objects *)
(** These proof objects lie at the core of how Coq operates.
When Coq is following a proof script, what is happening internally
is that it is gradually constructing a proof object -- a term
whose type is the proposition being proved. The tactics between
the [Proof] command and the [Qed] instruct Coq how to build up a
term of the required type. To see this process in action, let's
use the [Show Proof] command to display the current state of the
proof tree at various points in the following tactic proof. *)
Theorem eight_is_beautiful'': beautiful 8.
Proof.
Show Proof.
apply b_sum with (n:=3) (m:=5).
Show Proof.
apply b_3.
Show Proof.
apply b_5.
Show Proof.
Qed.
(** At any given moment, Coq has constructed a term with some
"holes" (indicated by [?1], [?2], and so on), and it knows what
type of evidence is needed at each hole. *)
(**
Each of the holes corresponds to a subgoal, and the proof is
finished when there are no more subgoals. At this point, the
[Theorem] command gives a name to the evidence we've built and
stores it in the global context. *)
(** Tactic proofs are useful and convenient, but they are not
essential: in principle, we can always construct the required
evidence by hand, as shown above. Then we can use [Definition]
(rather than [Theorem]) to give a global name directly to a
piece of evidence. *)
Definition eight_is_beautiful''' : beautiful 8 :=
b_sum 3 5 b_3 b_5.
(** All these different ways of building the proof lead to exactly the
same evidence being saved in the global environment. *)
Print eight_is_beautiful.
(* ===> eight_is_beautiful = b_sum 3 5 b_3 b_5 : beautiful 8 *)
Print eight_is_beautiful'.
(* ===> eight_is_beautiful' = b_sum 3 5 b_3 b_5 : beautiful 8 *)
Print eight_is_beautiful''.
(* ===> eight_is_beautiful'' = b_sum 3 5 b_3 b_5 : beautiful 8 *)
Print eight_is_beautiful'''.
(* ===> eight_is_beautiful''' = b_sum 3 5 b_3 b_5 : beautiful 8 *)
(** **** Exercise: 1 star (six_is_beautiful) *)
(** Give a tactic proof and a proof object showing that [6] is [beautiful]. *)
Theorem six_is_beautiful :
beautiful 6.
Proof.
(* FILL IN HERE *) Admitted.
Definition six_is_beautiful' : beautiful 6 :=
(* FILL IN HERE *) admit.
(** [] *)
(** **** Exercise: 1 star (nine_is_beautiful) *)
(** Give a tactic proof and a proof object showing that [9] is [beautiful]. *)
Theorem nine_is_beautiful :
beautiful 9.
Proof.
(* FILL IN HERE *) Admitted.
Definition nine_is_beautiful' : beautiful 9 :=
(* FILL IN HERE *) admit.
(** [] *)
(* ##################################################### *)
(** * Quantification, Implications and Functions *)
(** In Coq's computational universe (where we've mostly been living
until this chapter), there are two sorts of values with arrows in
their types: _constructors_ introduced by [Inductive]-ly defined
data types, and _functions_.
Similarly, in Coq's logical universe, there are two ways of giving
evidence for an implication: constructors introduced by
[Inductive]-ly defined propositions, and... functions!
For example, consider this statement: *)
Theorem b_plus3: forall n, beautiful n -> beautiful (3+n).
Proof.
intros n H.
apply b_sum.
apply b_3.
apply H.
Qed.
(** What is the proof object corresponding to [b_plus3]?
We're looking for an expression whose _type_ is [forall n,
beautiful n -> beautiful (3+n)] -- that is, a _function_ that
takes two arguments (one number and a piece of evidence) and
returns a piece of evidence! Here it is: *)
Definition b_plus3' : forall n, beautiful n -> beautiful (3+n) :=
fun (n : nat) => fun (H : beautiful n) =>
b_sum 3 n b_3 H.
Check b_plus3'.
(* ===> b_plus3' : forall n : nat, beautiful n -> beautiful (3+n) *)
(** Recall that [fun n => blah] means "the function that, given [n],
yields [blah]." Another equivalent way to write this definition is: *)
Definition b_plus3'' (n : nat) (H : beautiful n) : beautiful (3+n) :=
b_sum 3 n b_3 H.
Check b_plus3''.
(* ===> b_plus3'' : forall n, beautiful n -> beautiful (3+n) *)
(** When we view the proposition being proved by [b_plus3] as a function type,
one aspect of it may seem a little unusual. The second argument's
type, [beautiful n], mentions the _value_ of the first argument, [n].
While such _dependent types_ are not commonly found in programming
languages, even functional ones like ML or Haskell, they can
be useful there too.
Notice that both implication ([->]) and quantification ([forall])
correspond to functions on evidence. In fact, they are really the
same thing: [->] is just a shorthand for a degenerate use of
[forall] where there is no dependency, i.e., no need to give a name
to the type on the LHS of the arrow. *)
(** For example, consider this proposition: *)
Definition beautiful_plus3 : Prop :=
forall n, forall (E : beautiful n), beautiful (n+3).
(** A proof term inhabiting this proposition would be a function
with two arguments: a number [n] and some evidence [E] that [n] is
beautiful. But the name [E] for this evidence is not used in the
rest of the statement of [funny_prop1], so it's a bit silly to
bother making up a name for it. We could write it like this
instead, using the dummy identifier [_] in place of a real
name: *)
Definition beautiful_plus3' : Prop :=
forall n, forall (_ : beautiful n), beautiful (n+3).
(** Or, equivalently, we can write it in more familiar notation: *)
Definition beatiful_plus3'' : Prop :=
forall n, beautiful n -> beautiful (n+3).
(** In general, "[P -> Q]" is just syntactic sugar for
"[forall (_:P), Q]". *)
(** **** Exercise: 2 stars b_times2 *)
(** Give a proof object corresponding to the theorem [b_times2] from Prop.v *)
Definition b_times2': forall n, beautiful n -> beautiful (2*n) :=
(* FILL IN HERE *) admit.
(** [] *)
(** **** Exercise: 2 stars, optional (gorgeous_plus13_po) *)
(** Give a proof object corresponding to the theorem [gorgeous_plus13] from Prop.v *)
Definition gorgeous_plus13_po: forall n, gorgeous n -> gorgeous (13+n):=
(* FILL IN HERE *) admit.
(** [] *)
(** It is particularly revealing to look at proof objects involving the
logical connectives that we defined with inductive propositions in Logic.v. *)
Theorem and_example :
(beautiful 0) /\ (beautiful 3).
Proof.
apply conj.
(* Case "left". *) apply b_0.
(* Case "right". *) apply b_3. Qed.
(** Let's take a look at the proof object for the above theorem. *)
Print and_example.
(* ===> conj (beautiful 0) (beautiful 3) b_0 b_3
: beautiful 0 /\ beautiful 3 *)
(** Note that the proof is of the form
conj (beautiful 0) (beautiful 3)
(...pf of beautiful 3...) (...pf of beautiful 3...)
as you'd expect, given the type of [conj]. *)
(** **** Exercise: 1 star, optional (case_proof_objects) *)
(** The [Case] tactics were commented out in the proof of
[and_example] to avoid cluttering the proof object. What would
you guess the proof object will look like if we uncomment them?
Try it and see. *)
(** [] *)
Theorem and_commut : forall P Q : Prop,
P /\ Q -> Q /\ P.
Proof.
intros P Q H.
inversion H as [HP HQ].
split.
(* Case "left". *) apply HQ.
(* Case "right". *) apply HP. Qed.
(** Once again, we have commented out the [Case] tactics to make the
proof object for this theorem easier to understand. It is still
a little complicated, but after performing some simple reduction
steps, we can see that all that is really happening is taking apart
a record containing evidence for [P] and [Q] and rebuilding it in the
opposite order: *)
Print and_commut.
(* ===>
and_commut =
fun (P Q : Prop) (H : P /\ Q) =>
(fun H0 : Q /\ P => H0)
match H with
| conj HP HQ => (fun (HP0 : P) (HQ0 : Q) => conj Q P HQ0 HP0) HP HQ
end
: forall P Q : Prop, P /\ Q -> Q /\ P *)
(** After simplifying some direct application of [fun] expressions to arguments,
we get: *)
(* ===>
and_commut =
fun (P Q : Prop) (H : P /\ Q) =>
match H with
| conj HP HQ => conj Q P HQ HP
end
: forall P Q : Prop, P /\ Q -> Q /\ P *)
(** **** Exercise: 2 stars, optional (conj_fact) *)
(** Construct a proof object demonstrating the following proposition. *)
Definition conj_fact : forall P Q R, P /\ Q -> Q /\ R -> P /\ R :=
(* FILL IN HERE *) admit.
(** [] *)
(** **** Exercise: 2 stars, advanced, optional (beautiful_iff_gorgeous) *)
(** We have seen that the families of propositions [beautiful] and
[gorgeous] actually characterize the same set of numbers.
Prove that [beautiful n <-> gorgeous n] for all [n]. Just for
fun, write your proof as an explicit proof object, rather than
using tactics. (_Hint_: if you make use of previously defined
theorems, you should only need a single line!) *)
Definition beautiful_iff_gorgeous :
forall n, beautiful n <-> gorgeous n :=
(* FILL IN HERE *) admit.
(** [] *)
(** **** Exercise: 2 stars, optional (or_commut'') *)
(** Try to write down an explicit proof object for [or_commut] (without
using [Print] to peek at the ones we already defined!). *)
(* FILL IN HERE *)
(** [] *)
(** Recall that we model an existential for a property as a pair consisting of
a witness value and a proof that the witness obeys that property.
We can choose to construct the proof explicitly.
For example, consider this existentially quantified proposition: *)
Check ex.
Definition some_nat_is_even : Prop :=
ex _ ev.
(** To prove this proposition, we need to choose a particular number
as witness -- say, 4 -- and give some evidence that that number is
even. *)
Definition snie : some_nat_is_even :=
ex_intro _ ev 4 (ev_SS 2 (ev_SS 0 ev_0)).
(** **** Exercise: 2 stars, optional (ex_beautiful_Sn) *)
(** Complete the definition of the following proof object: *)
Definition p : ex _ (fun n => beautiful (S n)) :=
(* FILL IN HERE *) admit.
(** [] *)
(* ##################################################### *)
(** * Giving Explicit Arguments to Lemmas and Hypotheses *)
(** Even when we are using tactic-based proof, it can be very useful to
understand the underlying functional nature of implications and quantification.
For example, it is often convenient to [apply] or [rewrite]
using a lemma or hypothesis with one or more quantifiers or
assumptions already instantiated in order to direct what
happens. For example: *)
Check plus_comm.
(* ==>
plus_comm
: forall n m : nat, n + m = m + n *)
Lemma plus_comm_r : forall a b c, c + (b + a) = c + (a + b).
Proof.
intros a b c.
(* rewrite plus_comm. *)
(* rewrites in the first possible spot; not what we want *)
rewrite (plus_comm b a). (* directs rewriting to the right spot *)
reflexivity. Qed.
(** In this case, giving just one argument would be sufficient. *)
Lemma plus_comm_r' : forall a b c, c + (b + a) = c + (a + b).
Proof.
intros a b c.
rewrite (plus_comm b).
reflexivity. Qed.
(** Arguments must be given in order, but wildcards (_)
may be used to skip arguments that Coq can infer. *)
Lemma plus_comm_r'' : forall a b c, c + (b + a) = c + (a + b).
Proof.
intros a b c.
rewrite (plus_comm _ a).
reflexivity. Qed.
(** The author of a lemma can choose to declare easily inferable arguments
to be implicit, just as with functions and constructors.
The [with] clauses we've already seen is really just a way of
specifying selected arguments by name rather than position: *)
Lemma plus_comm_r''' : forall a b c, c + (b + a) = c + (a + b).
Proof.
intros a b c.
rewrite plus_comm with (n := b).
reflexivity. Qed.
(** **** Exercise: 2 stars (trans_eq_example_redux) *)
(** Redo the proof of the following theorem (from MoreCoq.v) using
an [apply] of [trans_eq] but _not_ using a [with] clause. *)
Example trans_eq_example' : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ##################################################### *)
(** * Programming with Tactics (Advanced) *)
(** If we can build proofs with explicit terms rather than tactics,
you may be wondering if we can build programs using tactics rather
than explicit terms. Sure! *)
Definition add1 : nat -> nat.
intro n.
Show Proof.
apply S.
Show Proof.
apply n. Defined.
Print add1.
(* ==>
add1 = fun n : nat => S n
: nat -> nat
*)
Eval compute in add1 2.
(* ==> 3 : nat *)
(** Notice that we terminate the [Definition] with a [.] rather than with
[:=] followed by a term. This tells Coq to enter proof scripting mode
to build an object of type [nat -> nat]. Also, we terminate the proof
with [Defined] rather than [Qed]; this makes the definition _transparent_
so that it can be used in computation like a normally-defined function.
This feature is mainly useful for writing functions with dependent types,
which we won't explore much further in this book.
But it does illustrate the uniformity and orthogonality of the basic ideas in Coq. *)
(** $Date: 2014-12-31 15:31:47 -0500 (Wed, 31 Dec 2014) $ *)
|
// Computer_System_mm_interconnect_2.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module Computer_System_mm_interconnect_2 (
input wire System_PLL_sys_clk_clk, // System_PLL_sys_clk.clk
input wire Pixel_DMA_Addr_Translation_reset_reset_bridge_in_reset_reset, // Pixel_DMA_Addr_Translation_reset_reset_bridge_in_reset.reset
input wire VGA_Subsystem_sys_reset_reset_bridge_in_reset_reset, // VGA_Subsystem_sys_reset_reset_bridge_in_reset.reset
input wire [1:0] Pixel_DMA_Addr_Translation_master_address, // Pixel_DMA_Addr_Translation_master.address
output wire Pixel_DMA_Addr_Translation_master_waitrequest, // .waitrequest
input wire [3:0] Pixel_DMA_Addr_Translation_master_byteenable, // .byteenable
input wire Pixel_DMA_Addr_Translation_master_read, // .read
output wire [31:0] Pixel_DMA_Addr_Translation_master_readdata, // .readdata
input wire Pixel_DMA_Addr_Translation_master_write, // .write
input wire [31:0] Pixel_DMA_Addr_Translation_master_writedata, // .writedata
output wire [1:0] VGA_Subsystem_pixel_dma_control_slave_address, // VGA_Subsystem_pixel_dma_control_slave.address
output wire VGA_Subsystem_pixel_dma_control_slave_write, // .write
output wire VGA_Subsystem_pixel_dma_control_slave_read, // .read
input wire [31:0] VGA_Subsystem_pixel_dma_control_slave_readdata, // .readdata
output wire [31:0] VGA_Subsystem_pixel_dma_control_slave_writedata, // .writedata
output wire [3:0] VGA_Subsystem_pixel_dma_control_slave_byteenable // .byteenable
);
wire pixel_dma_addr_translation_master_translator_avalon_universal_master_0_waitrequest; // VGA_Subsystem_pixel_dma_control_slave_translator:uav_waitrequest -> Pixel_DMA_Addr_Translation_master_translator:uav_waitrequest
wire [31:0] pixel_dma_addr_translation_master_translator_avalon_universal_master_0_readdata; // VGA_Subsystem_pixel_dma_control_slave_translator:uav_readdata -> Pixel_DMA_Addr_Translation_master_translator:uav_readdata
wire pixel_dma_addr_translation_master_translator_avalon_universal_master_0_debugaccess; // Pixel_DMA_Addr_Translation_master_translator:uav_debugaccess -> VGA_Subsystem_pixel_dma_control_slave_translator:uav_debugaccess
wire [3:0] pixel_dma_addr_translation_master_translator_avalon_universal_master_0_address; // Pixel_DMA_Addr_Translation_master_translator:uav_address -> VGA_Subsystem_pixel_dma_control_slave_translator:uav_address
wire pixel_dma_addr_translation_master_translator_avalon_universal_master_0_read; // Pixel_DMA_Addr_Translation_master_translator:uav_read -> VGA_Subsystem_pixel_dma_control_slave_translator:uav_read
wire [3:0] pixel_dma_addr_translation_master_translator_avalon_universal_master_0_byteenable; // Pixel_DMA_Addr_Translation_master_translator:uav_byteenable -> VGA_Subsystem_pixel_dma_control_slave_translator:uav_byteenable
wire pixel_dma_addr_translation_master_translator_avalon_universal_master_0_readdatavalid; // VGA_Subsystem_pixel_dma_control_slave_translator:uav_readdatavalid -> Pixel_DMA_Addr_Translation_master_translator:uav_readdatavalid
wire pixel_dma_addr_translation_master_translator_avalon_universal_master_0_lock; // Pixel_DMA_Addr_Translation_master_translator:uav_lock -> VGA_Subsystem_pixel_dma_control_slave_translator:uav_lock
wire pixel_dma_addr_translation_master_translator_avalon_universal_master_0_write; // Pixel_DMA_Addr_Translation_master_translator:uav_write -> VGA_Subsystem_pixel_dma_control_slave_translator:uav_write
wire [31:0] pixel_dma_addr_translation_master_translator_avalon_universal_master_0_writedata; // Pixel_DMA_Addr_Translation_master_translator:uav_writedata -> VGA_Subsystem_pixel_dma_control_slave_translator:uav_writedata
wire [2:0] pixel_dma_addr_translation_master_translator_avalon_universal_master_0_burstcount; // Pixel_DMA_Addr_Translation_master_translator:uav_burstcount -> VGA_Subsystem_pixel_dma_control_slave_translator:uav_burstcount
altera_merlin_master_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (4),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) pixel_dma_addr_translation_master_translator (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Pixel_DMA_Addr_Translation_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (pixel_dma_addr_translation_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (pixel_dma_addr_translation_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (pixel_dma_addr_translation_master_translator_avalon_universal_master_0_read), // .read
.uav_write (pixel_dma_addr_translation_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (pixel_dma_addr_translation_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (pixel_dma_addr_translation_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (pixel_dma_addr_translation_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (pixel_dma_addr_translation_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (pixel_dma_addr_translation_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (pixel_dma_addr_translation_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (pixel_dma_addr_translation_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (Pixel_DMA_Addr_Translation_master_address), // avalon_anti_master_0.address
.av_waitrequest (Pixel_DMA_Addr_Translation_master_waitrequest), // .waitrequest
.av_byteenable (Pixel_DMA_Addr_Translation_master_byteenable), // .byteenable
.av_read (Pixel_DMA_Addr_Translation_master_read), // .read
.av_readdata (Pixel_DMA_Addr_Translation_master_readdata), // .readdata
.av_write (Pixel_DMA_Addr_Translation_master_write), // .write
.av_writedata (Pixel_DMA_Addr_Translation_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (4),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) vga_subsystem_pixel_dma_control_slave_translator (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Pixel_DMA_Addr_Translation_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (pixel_dma_addr_translation_master_translator_avalon_universal_master_0_address), // avalon_universal_slave_0.address
.uav_burstcount (pixel_dma_addr_translation_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (pixel_dma_addr_translation_master_translator_avalon_universal_master_0_read), // .read
.uav_write (pixel_dma_addr_translation_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (pixel_dma_addr_translation_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (pixel_dma_addr_translation_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (pixel_dma_addr_translation_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (pixel_dma_addr_translation_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (pixel_dma_addr_translation_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (pixel_dma_addr_translation_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (pixel_dma_addr_translation_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (VGA_Subsystem_pixel_dma_control_slave_address), // avalon_anti_slave_0.address
.av_write (VGA_Subsystem_pixel_dma_control_slave_write), // .write
.av_read (VGA_Subsystem_pixel_dma_control_slave_read), // .read
.av_readdata (VGA_Subsystem_pixel_dma_control_slave_readdata), // .readdata
.av_writedata (VGA_Subsystem_pixel_dma_control_slave_writedata), // .writedata
.av_byteenable (VGA_Subsystem_pixel_dma_control_slave_byteenable), // .byteenable
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 08:49:35 2016
/////////////////////////////////////////////////////////////
module FPU_Add_Subtract_Function_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_FSM,
ack_FSM, Data_X, Data_Y, add_subt, r_mode, overflow_flag,
underflow_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
input [1:0] r_mode;
output [63:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM, add_subt;
output overflow_flag, underflow_flag, ready;
wire FSM_selector_C, add_overflow_flag, FSM_selector_D, intAS,
sign_final_result, n1104, n1105, n1106, n1107, n1108, n1109, n1110,
n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120,
n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130,
n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140,
n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150,
n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160,
n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170,
n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180,
n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190,
n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200,
n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210,
n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220,
n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230,
n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240,
n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250,
n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260,
n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270,
n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280,
n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290,
n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300,
n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310,
n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320,
n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330,
n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340,
n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350,
n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360,
n1361, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511,
n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521,
n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531,
n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541,
n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551,
n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561,
n1562, n1563, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580,
n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590,
n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600,
n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610,
n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620,
n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630,
n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640,
n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650,
n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660,
n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670,
n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680,
n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690,
n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700,
n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710,
n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720,
n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730,
n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740,
n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750,
n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760,
n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770,
n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780,
n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790,
n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800,
n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810,
n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820,
n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830,
n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840,
n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850,
n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860,
n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870,
n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880,
n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890,
n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900,
n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910,
n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920,
n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930,
n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940,
n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950,
n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960,
n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970,
n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980,
n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990,
n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000,
n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010,
n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020,
n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030,
n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040,
n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050,
n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060,
n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070,
n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080,
n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090,
n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100,
n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110,
n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120,
n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130,
n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140,
n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150,
n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160,
n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170,
n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180,
n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190,
n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200,
n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210,
n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220,
n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230,
n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240,
n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250,
n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260,
n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270,
n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280,
n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290,
n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300,
n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310,
n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320,
n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330,
n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340,
n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350,
n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360,
n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370,
n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380,
n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390,
n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400,
n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410,
n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420,
n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430,
n2431, n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440,
n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450,
n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460,
n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470,
n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480,
n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490,
n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500,
n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510,
n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520,
n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530,
n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540,
n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550,
n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560,
n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570,
n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580,
n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590,
n2591, n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600,
n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610,
n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620,
n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630,
n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640,
n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650,
n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660,
n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670,
n2671, n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680,
n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690,
n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700,
n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710,
n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720,
n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730,
n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740,
n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750,
n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760,
n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770,
n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780,
n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790,
n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800,
n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810,
n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820,
n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830,
n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840,
n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850,
n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860,
n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870,
n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880,
n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890,
n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900,
n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910,
n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920,
n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930,
n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940,
n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950,
n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960,
n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970,
n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980,
n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990,
n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000,
n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010,
n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020,
n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030,
n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040,
n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050,
n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060,
n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070,
n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080,
n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090,
n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100,
n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110,
n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120,
n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130,
n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140,
n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150,
n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160,
n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170,
n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180,
n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190,
n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200,
n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210,
n3211, n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220,
n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230,
n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240,
n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250,
n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260,
n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270,
n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280,
n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290,
n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300,
n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310,
n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320,
n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330,
n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340,
n3341, n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350,
n3351, n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360,
n3361, n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370,
n3371, n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380,
n3381, n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390,
n3391, n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400,
n3401, n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410,
n3411, n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420,
n3421, n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430,
n3431, n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440,
n3441, n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450,
n3451, n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460,
n3461, n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470,
n3471, n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480,
n3481, n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490,
n3491, n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500,
n3501, n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510,
n3511, n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520,
n3521, n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530,
n3531, n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540,
n3541, n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550,
n3551, n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560,
n3561, n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570,
n3571, n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580,
n3581, n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590,
n3591, n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600,
n3601, n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610,
n3611, n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620,
n3621, n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630,
n3631, n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640,
n3641, n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650,
n3651, n3652, n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660,
n3661, n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670,
n3671, n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680,
n3681, n3682, n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690,
n3691, n3692, n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700,
n3701, n3702, n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710,
n3711, n3712, n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720,
n3721, n3722, n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730,
n3731, n3732, n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740,
n3741, n3742, n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750,
n3751, n3752, n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760,
n3761, n3762, n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770,
n3771, n3772, n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780,
n3781, n3782, n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790,
n3791, n3792, n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800,
n3801, n3802, n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810,
n3811, n3812, n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820,
n3821, n3822, n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830,
n3831, n3832, n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840,
n3841, n3842, n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850,
n3851, n3852, n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860,
n3861, n3862, n3863, n3864, n3866, n3867, n3868;
wire [1:0] FSM_selector_B;
wire [63:0] intDX;
wire [63:0] intDY;
wire [62:0] DMP;
wire [62:0] DmP;
wire [10:0] exp_oper_result;
wire [5:0] LZA_output;
wire [54:0] Add_Subt_result;
wire [54:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [109:0] Barrel_Shifter_module_Mux_Array_Data_array;
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1442), .CK(clk),
.RN(n3834), .Q(Sgf_normalized_result[0]), .QN(n3766) );
DFFRX4TS FS_Module_state_reg_reg_0_ ( .D(n1560), .CK(clk), .RN(n3833), .Q(
FS_Module_state_reg[0]), .QN(n3688) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_52_ ( .D(n1555), .CK(clk),
.RN(n3850), .Q(Add_Subt_result[52]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_51_ ( .D(n1554), .CK(clk),
.RN(n3850), .Q(Add_Subt_result[51]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_50_ ( .D(n1553), .CK(clk),
.RN(n3850), .Q(Add_Subt_result[50]), .QN(n3808) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_49_ ( .D(n1552), .CK(clk),
.RN(n3851), .Q(Add_Subt_result[49]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_47_ ( .D(n1550), .CK(clk),
.RN(n3851), .Q(Add_Subt_result[47]), .QN(n3810) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_45_ ( .D(n1548), .CK(clk),
.RN(n3851), .Q(Add_Subt_result[45]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_43_ ( .D(n1546), .CK(clk),
.RN(n3851), .Q(Add_Subt_result[43]), .QN(n3812) );
DFFRX4TS FS_Module_state_reg_reg_3_ ( .D(n1561), .CK(clk), .RN(n3833), .Q(
FS_Module_state_reg[3]), .QN(n3728) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ ( .D(n1501), .CK(
clk), .RN(n3845), .Q(LZA_output[2]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_3_ ( .D(n1500), .CK(
clk), .RN(n3846), .Q(LZA_output[3]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ ( .D(n1499), .CK(
clk), .RN(n3830), .Q(LZA_output[0]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ ( .D(n1498), .CK(
clk), .RN(n3845), .Q(LZA_output[1]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ ( .D(n1497), .CK(
clk), .RN(n3845), .Q(LZA_output[4]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[7]), .CK(clk), .RN(n3818),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[62]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[6]), .CK(clk), .RN(n3818),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[61]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[5]), .CK(clk), .RN(n3818),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[60]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[4]), .CK(clk), .RN(n3818),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[59]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[3]), .CK(clk), .RN(n3818),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[58]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[2]), .CK(clk), .RN(n3818),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[57]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[1]), .CK(clk), .RN(n3818),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[56]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[0]), .CK(clk), .RN(n3818),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[55]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1453), .CK(clk),
.RN(n3836), .Q(Sgf_normalized_result[11]), .QN(n3776) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1464), .CK(clk),
.RN(n3838), .Q(Sgf_normalized_result[22]), .QN(n3767) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1449), .CK(clk),
.RN(n3835), .Q(Sgf_normalized_result[7]), .QN(n1619) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1458), .CK(clk),
.RN(n3837), .Q(Sgf_normalized_result[16]), .QN(n3773) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1448), .CK(clk),
.RN(n3835), .Q(Sgf_normalized_result[6]), .QN(n1612) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1459), .CK(clk),
.RN(n3837), .Q(Sgf_normalized_result[17]), .QN(n3772) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1447), .CK(clk),
.RN(n3834), .Q(Sgf_normalized_result[5]), .QN(n1618) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1460), .CK(clk),
.RN(n3837), .Q(Sgf_normalized_result[18]), .QN(n3771) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1446), .CK(clk),
.RN(n3834), .Q(Sgf_normalized_result[4]), .QN(n1614) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1461), .CK(clk),
.RN(n3837), .Q(Sgf_normalized_result[19]), .QN(n3770) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1445), .CK(clk),
.RN(n3834), .Q(Sgf_normalized_result[3]), .QN(n1617) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1462), .CK(clk),
.RN(n3837), .Q(Sgf_normalized_result[20]), .QN(n3769) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1463), .CK(clk),
.RN(n3838), .Q(Sgf_normalized_result[21]), .QN(n3768) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1443), .CK(clk),
.RN(n3834), .Q(Sgf_normalized_result[1]), .QN(n3765) );
DFFRX4TS Sel_D_Q_reg_0_ ( .D(n1441), .CK(clk), .RN(n1360), .Q(FSM_selector_D), .QN(n3733) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_60_ ( .D(n1229), .CK(clk),
.RN(n3833), .Q(DMP[60]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_59_ ( .D(n1228), .CK(clk),
.RN(n3832), .Q(DMP[59]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_58_ ( .D(n1227), .CK(clk),
.RN(n3832), .Q(DMP[58]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_57_ ( .D(n1226), .CK(clk),
.RN(n3832), .Q(DMP[57]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_56_ ( .D(n1225), .CK(clk),
.RN(n3832), .Q(DMP[56]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_54_ ( .D(n1223), .CK(clk),
.RN(n3832), .Q(DMP[54]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_51_ ( .D(n1220), .CK(clk),
.RN(n3845), .Q(DMP[51]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_50_ ( .D(n1219), .CK(clk),
.RN(n3844), .Q(DMP[50]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_45_ ( .D(n1214), .CK(clk),
.RN(n3843), .Q(DMP[45]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_44_ ( .D(n1213), .CK(clk),
.RN(n3843), .Q(DMP[44]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_42_ ( .D(n1211), .CK(clk),
.RN(n3842), .Q(DMP[42]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_41_ ( .D(n1210), .CK(clk),
.RN(n3842), .Q(DMP[41]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_40_ ( .D(n1209), .CK(clk),
.RN(n3842), .Q(DMP[40]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_39_ ( .D(n1208), .CK(clk),
.RN(n3842), .Q(DMP[39]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_38_ ( .D(n1207), .CK(clk),
.RN(n3842), .Q(DMP[38]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_37_ ( .D(n1206), .CK(clk),
.RN(n3841), .Q(DMP[37]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_36_ ( .D(n1205), .CK(clk),
.RN(n3841), .Q(DMP[36]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_35_ ( .D(n1204), .CK(clk),
.RN(n3841), .Q(DMP[35]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_34_ ( .D(n1203), .CK(clk),
.RN(n3841), .Q(DMP[34]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_33_ ( .D(n1202), .CK(clk),
.RN(n3841), .Q(DMP[33]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_32_ ( .D(n1201), .CK(clk),
.RN(n3840), .Q(DMP[32]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_31_ ( .D(n1200), .CK(clk),
.RN(n3840), .Q(DMP[31]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(n1199), .CK(clk),
.RN(n3840), .Q(DMP[30]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(n1198), .CK(clk),
.RN(n3840), .Q(DMP[29]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(n1197), .CK(clk),
.RN(n3840), .Q(DMP[28]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(n1196), .CK(clk),
.RN(n3839), .Q(DMP[27]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(n1195), .CK(clk),
.RN(n3839), .Q(DMP[26]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(n1194), .CK(clk),
.RN(n3839), .Q(DMP[25]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(n1193), .CK(clk),
.RN(n3839), .Q(DMP[24]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(n1192), .CK(clk),
.RN(n3839), .Q(DMP[23]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(n1191), .CK(clk),
.RN(n3838), .Q(DMP[22]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(n1189), .CK(clk),
.RN(n3838), .Q(DMP[20]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(n1188), .CK(clk),
.RN(n3838), .Q(DMP[19]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(n1187), .CK(clk),
.RN(n3838), .Q(DMP[18]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(n1186), .CK(clk),
.RN(n3837), .Q(DMP[17]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(n1185), .CK(clk),
.RN(n3837), .Q(DMP[16]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(n1184), .CK(clk),
.RN(n3837), .Q(DMP[15]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(n1183), .CK(clk),
.RN(n3837), .Q(DMP[14]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(n1181), .CK(clk),
.RN(n3836), .Q(DMP[12]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(n1180), .CK(clk),
.RN(n3836), .Q(DMP[11]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(n1179), .CK(clk),
.RN(n3836), .Q(DMP[10]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(n1178), .CK(clk), .RN(
n3836), .Q(DMP[9]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(n1177), .CK(clk), .RN(
n3836), .Q(DMP[8]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(n1175), .CK(clk), .RN(
n3835), .Q(DMP[6]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(n1174), .CK(clk), .RN(
n3835), .Q(DMP[5]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(n1173), .CK(clk), .RN(
n3835), .Q(DMP[4]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(n1172), .CK(clk), .RN(
n3835), .Q(DMP[3]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(n1171), .CK(clk), .RN(
n3834), .Q(DMP[2]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(n1170), .CK(clk), .RN(
n3834), .Q(DMP[1]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(n1169), .CK(clk), .RN(
n3834), .Q(DMP[0]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_61_ ( .D(n1166), .CK(clk),
.RN(n3831), .Q(DmP[61]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_60_ ( .D(n1165), .CK(clk),
.RN(n3831), .Q(DmP[60]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_59_ ( .D(n1164), .CK(clk),
.RN(n3831), .Q(DmP[59]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_58_ ( .D(n1163), .CK(clk),
.RN(n3831), .Q(DmP[58]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_57_ ( .D(n1162), .CK(clk),
.RN(n3831), .Q(DmP[57]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_56_ ( .D(n1161), .CK(clk),
.RN(n3831), .Q(DmP[56]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_55_ ( .D(n1160), .CK(clk),
.RN(n3831), .Q(DmP[55]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_54_ ( .D(n1159), .CK(clk),
.RN(n3831), .Q(DmP[54]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_53_ ( .D(n1158), .CK(clk),
.RN(n3831), .Q(DmP[53]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_52_ ( .D(n1157), .CK(clk),
.RN(n3830), .Q(DmP[52]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_62_ ( .D(n1104), .CK(clk),
.RN(n3831), .Q(DmP[62]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(n1505), .CK(clk),
.RN(n3846), .Q(Add_Subt_result[2]), .QN(n3790) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(n1507), .CK(clk),
.RN(n3846), .Q(Add_Subt_result[4]), .QN(n3788) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(n1509), .CK(clk),
.RN(n3847), .Q(Add_Subt_result[6]), .QN(n3784) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(n1513), .CK(clk),
.RN(n3847), .Q(Add_Subt_result[10]), .QN(n3783) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(n1508), .CK(clk),
.RN(n3846), .Q(Add_Subt_result[5]), .QN(n3781) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(n1517), .CK(clk),
.RN(n3847), .Q(Add_Subt_result[14]), .QN(n3779) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_16_ ( .D(n1519), .CK(clk),
.RN(n3847), .Q(Add_Subt_result[16]), .QN(n3778) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_22_ ( .D(n1525), .CK(clk),
.RN(n3848), .Q(Add_Subt_result[22]), .QN(n3777) );
DFFRX2TS XRegister_Q_reg_8_ ( .D(n1305), .CK(clk), .RN(n3859), .Q(intDX[8]),
.QN(n3764) );
DFFRX2TS XRegister_Q_reg_18_ ( .D(n1315), .CK(clk), .RN(n3860), .Q(intDX[18]), .QN(n3763) );
DFFRX2TS XRegister_Q_reg_26_ ( .D(n1323), .CK(clk), .RN(n3860), .Q(intDX[26]), .QN(n3762) );
DFFRX2TS XRegister_Q_reg_50_ ( .D(n1347), .CK(clk), .RN(n3863), .Q(intDX[50]), .QN(n3761) );
DFFRX2TS XRegister_Q_reg_55_ ( .D(n1352), .CK(clk), .RN(n3863), .Q(intDX[55]), .QN(n3760) );
DFFRX2TS XRegister_Q_reg_53_ ( .D(n1350), .CK(clk), .RN(n3863), .Q(intDX[53]), .QN(n3759) );
DFFRX2TS XRegister_Q_reg_3_ ( .D(n1300), .CK(clk), .RN(n3858), .Q(intDX[3]),
.QN(n3757) );
DFFRX2TS XRegister_Q_reg_23_ ( .D(n1320), .CK(clk), .RN(n3860), .Q(intDX[23]), .QN(n3755) );
DFFRX2TS XRegister_Q_reg_31_ ( .D(n1328), .CK(clk), .RN(n3861), .Q(intDX[31]), .QN(n3754) );
DFFRX2TS XRegister_Q_reg_11_ ( .D(n1308), .CK(clk), .RN(n3859), .Q(intDX[11]), .QN(n3753) );
DFFRX2TS XRegister_Q_reg_17_ ( .D(n1314), .CK(clk), .RN(n3860), .Q(intDX[17]), .QN(n3752) );
DFFRX2TS XRegister_Q_reg_25_ ( .D(n1322), .CK(clk), .RN(n3860), .Q(intDX[25]), .QN(n3751) );
DFFRX2TS XRegister_Q_reg_49_ ( .D(n1346), .CK(clk), .RN(n3863), .Q(intDX[49]), .QN(n3750) );
DFFRX2TS XRegister_Q_reg_36_ ( .D(n1333), .CK(clk), .RN(n3861), .Q(intDX[36]), .QN(n3749) );
DFFRX2TS XRegister_Q_reg_33_ ( .D(n1330), .CK(clk), .RN(n3861), .Q(intDX[33]), .QN(n3748) );
DFFRX2TS XRegister_Q_reg_35_ ( .D(n1332), .CK(clk), .RN(n3861), .Q(intDX[35]), .QN(n3747) );
DFFRX2TS XRegister_Q_reg_43_ ( .D(n1340), .CK(clk), .RN(n3862), .Q(intDX[43]), .QN(n3746) );
DFFRX2TS XRegister_Q_reg_45_ ( .D(n1342), .CK(clk), .RN(n3862), .Q(intDX[45]), .QN(n3745) );
DFFRX2TS XRegister_Q_reg_41_ ( .D(n1338), .CK(clk), .RN(n3862), .Q(intDX[41]), .QN(n3741) );
DFFRX2TS XRegister_Q_reg_21_ ( .D(n1318), .CK(clk), .RN(n3860), .Q(intDX[21]), .QN(n3735) );
DFFRX2TS XRegister_Q_reg_29_ ( .D(n1326), .CK(clk), .RN(n3861), .Q(intDX[29]), .QN(n3734) );
DFFRX2TS YRegister_Q_reg_6_ ( .D(n1238), .CK(clk), .RN(n3852), .Q(intDY[6]),
.QN(n3732) );
DFFRX2TS YRegister_Q_reg_16_ ( .D(n1248), .CK(clk), .RN(n3853), .Q(intDY[16]), .QN(n3731) );
DFFRX2TS XRegister_Q_reg_7_ ( .D(n1304), .CK(clk), .RN(n3859), .Q(intDX[7]),
.QN(n3713) );
DFFRX2TS YRegister_Q_reg_5_ ( .D(n1237), .CK(clk), .RN(n3852), .Q(intDY[5]),
.QN(n3712) );
DFFRX2TS YRegister_Q_reg_38_ ( .D(n1270), .CK(clk), .RN(n3855), .Q(intDY[38]), .QN(n3711) );
DFFRX2TS YRegister_Q_reg_52_ ( .D(n1284), .CK(clk), .RN(n3857), .Q(intDY[52]), .QN(n3710) );
DFFRX2TS YRegister_Q_reg_10_ ( .D(n1242), .CK(clk), .RN(n3853), .Q(intDY[10]), .QN(n3709) );
DFFRX2TS YRegister_Q_reg_44_ ( .D(n1276), .CK(clk), .RN(n3856), .Q(intDY[44]), .QN(n3708) );
DFFRX2TS YRegister_Q_reg_48_ ( .D(n1280), .CK(clk), .RN(n3856), .Q(intDY[48]), .QN(n3707) );
DFFRX2TS YRegister_Q_reg_1_ ( .D(n1233), .CK(clk), .RN(n3852), .Q(intDY[1]),
.QN(n3705) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_33_ ( .D(n1536), .CK(clk),
.RN(n3849), .Q(Add_Subt_result[33]), .QN(n3702) );
DFFRX2TS XRegister_Q_reg_1_ ( .D(n1298), .CK(clk), .RN(n3858), .Q(intDX[1]),
.QN(n3699) );
DFFRX2TS XRegister_Q_reg_5_ ( .D(n1302), .CK(clk), .RN(n3858), .Q(intDX[5]),
.QN(n3681) );
DFFRX2TS YRegister_Q_reg_7_ ( .D(n1239), .CK(clk), .RN(n3852), .Q(intDY[7]),
.QN(n3680) );
DFFRX2TS YRegister_Q_reg_4_ ( .D(n1236), .CK(clk), .RN(n3852), .Q(intDY[4]),
.QN(n3679) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(n1512), .CK(clk),
.RN(n3847), .Q(Add_Subt_result[9]), .QN(n3678) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_63_ ( .D(n1361),
.CK(clk), .RN(n3824), .Q(final_result_ieee[63]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n1414),
.CK(clk), .RN(n3830), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n1413),
.CK(clk), .RN(n3830), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n1412),
.CK(clk), .RN(n3830), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n1411),
.CK(clk), .RN(n3830), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n1410),
.CK(clk), .RN(n3830), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n1409),
.CK(clk), .RN(n3829), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n1408),
.CK(clk), .RN(n3829), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n1407),
.CK(clk), .RN(n3829), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n1406),
.CK(clk), .RN(n3829), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n1405),
.CK(clk), .RN(n3829), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n1404),
.CK(clk), .RN(n3829), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n1403),
.CK(clk), .RN(n3829), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n1402),
.CK(clk), .RN(n3829), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n1401),
.CK(clk), .RN(n3829), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n1400),
.CK(clk), .RN(n3829), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n1399),
.CK(clk), .RN(n3828), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n1398),
.CK(clk), .RN(n3828), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n1397),
.CK(clk), .RN(n3828), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n1396),
.CK(clk), .RN(n3828), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n1395),
.CK(clk), .RN(n3828), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n1394),
.CK(clk), .RN(n3828), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n1393),
.CK(clk), .RN(n3828), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n1392),
.CK(clk), .RN(n3828), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n1391),
.CK(clk), .RN(n3828), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n1390),
.CK(clk), .RN(n3828), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n1389),
.CK(clk), .RN(n3827), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n1388),
.CK(clk), .RN(n3827), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n1387),
.CK(clk), .RN(n3827), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n1386),
.CK(clk), .RN(n3827), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n1385),
.CK(clk), .RN(n3827), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n1384),
.CK(clk), .RN(n3827), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n1383),
.CK(clk), .RN(n3827), .Q(final_result_ieee[31]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_32_ ( .D(n1382),
.CK(clk), .RN(n3827), .Q(final_result_ieee[32]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_33_ ( .D(n1381),
.CK(clk), .RN(n3827), .Q(final_result_ieee[33]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_34_ ( .D(n1380),
.CK(clk), .RN(n3827), .Q(final_result_ieee[34]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_35_ ( .D(n1379),
.CK(clk), .RN(n3826), .Q(final_result_ieee[35]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_36_ ( .D(n1378),
.CK(clk), .RN(n3826), .Q(final_result_ieee[36]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_37_ ( .D(n1377),
.CK(clk), .RN(n3826), .Q(final_result_ieee[37]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_38_ ( .D(n1376),
.CK(clk), .RN(n3826), .Q(final_result_ieee[38]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_39_ ( .D(n1375),
.CK(clk), .RN(n3826), .Q(final_result_ieee[39]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_40_ ( .D(n1374),
.CK(clk), .RN(n3826), .Q(final_result_ieee[40]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_41_ ( .D(n1373),
.CK(clk), .RN(n3826), .Q(final_result_ieee[41]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_42_ ( .D(n1372),
.CK(clk), .RN(n3826), .Q(final_result_ieee[42]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_43_ ( .D(n1371),
.CK(clk), .RN(n3826), .Q(final_result_ieee[43]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_44_ ( .D(n1370),
.CK(clk), .RN(n3826), .Q(final_result_ieee[44]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_45_ ( .D(n1369),
.CK(clk), .RN(n3825), .Q(final_result_ieee[45]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_46_ ( .D(n1368),
.CK(clk), .RN(n3825), .Q(final_result_ieee[46]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_47_ ( .D(n1367),
.CK(clk), .RN(n3825), .Q(final_result_ieee[47]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_48_ ( .D(n1366),
.CK(clk), .RN(n3825), .Q(final_result_ieee[48]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_49_ ( .D(n1365),
.CK(clk), .RN(n3825), .Q(final_result_ieee[49]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_50_ ( .D(n1364),
.CK(clk), .RN(n3825), .Q(final_result_ieee[50]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_51_ ( .D(n1363),
.CK(clk), .RN(n3825), .Q(final_result_ieee[51]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_52_ ( .D(n1425),
.CK(clk), .RN(n3825), .Q(final_result_ieee[52]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_53_ ( .D(n1424),
.CK(clk), .RN(n3825), .Q(final_result_ieee[53]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_54_ ( .D(n1423),
.CK(clk), .RN(n3825), .Q(final_result_ieee[54]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_55_ ( .D(n1422),
.CK(clk), .RN(n3824), .Q(final_result_ieee[55]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_56_ ( .D(n1421),
.CK(clk), .RN(n3824), .Q(final_result_ieee[56]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_57_ ( .D(n1420),
.CK(clk), .RN(n3824), .Q(final_result_ieee[57]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_58_ ( .D(n1419),
.CK(clk), .RN(n3824), .Q(final_result_ieee[58]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_59_ ( .D(n1418),
.CK(clk), .RN(n3824), .Q(final_result_ieee[59]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_60_ ( .D(n1417),
.CK(clk), .RN(n3824), .Q(final_result_ieee[60]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_61_ ( .D(n1416),
.CK(clk), .RN(n3824), .Q(final_result_ieee[61]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_62_ ( .D(n1415),
.CK(clk), .RN(n3824), .Q(final_result_ieee[62]) );
DFFRXLTS Exp_Operation_Module_Overflow_Q_reg_0_ ( .D(n1427), .CK(clk), .RN(
n3830), .Q(overflow_flag), .QN(n3813) );
DFFRX2TS XRegister_Q_reg_13_ ( .D(n1310), .CK(clk), .RN(n3859), .Q(intDX[13]), .QN(n3720) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_26_ ( .D(n1529), .CK(clk),
.RN(n3849), .Q(Add_Subt_result[26]), .QN(n3792) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_28_ ( .D(n1531), .CK(clk),
.RN(n3849), .Q(Add_Subt_result[28]), .QN(n3786) );
DFFRX2TS XRegister_Q_reg_15_ ( .D(n1312), .CK(clk), .RN(n3859), .Q(intDX[15]), .QN(n3756) );
DFFRX2TS YRegister_Q_reg_3_ ( .D(n1235), .CK(clk), .RN(n3852), .Q(intDY[3])
);
DFFRX2TS YRegister_Q_reg_39_ ( .D(n1271), .CK(clk), .RN(n3855), .Q(intDY[39]) );
DFFRX2TS YRegister_Q_reg_41_ ( .D(n1273), .CK(clk), .RN(n3856), .Q(intDY[41]) );
DFFRX2TS YRegister_Q_reg_15_ ( .D(n1247), .CK(clk), .RN(n3853), .Q(intDY[15]) );
DFFRX4TS Sel_C_Q_reg_0_ ( .D(n1557), .CK(clk), .RN(n1360), .Q(FSM_selector_C), .QN(n3677) );
DFFRX2TS XRegister_Q_reg_60_ ( .D(n1357), .CK(clk), .RN(n3864), .Q(intDX[60]), .QN(n3866) );
DFFRX2TS XRegister_Q_reg_58_ ( .D(n1355), .CK(clk), .RN(n3864), .Q(intDX[58]), .QN(n3867) );
DFFRX2TS XRegister_Q_reg_57_ ( .D(n1354), .CK(clk), .RN(n3864), .Q(intDX[57]), .QN(n3868) );
DFFRX2TS XRegister_Q_reg_38_ ( .D(n1335), .CK(clk), .RN(n3862), .Q(intDX[38]), .QN(n3696) );
DFFRX2TS XRegister_Q_reg_4_ ( .D(n1301), .CK(clk), .RN(n3858), .Q(intDX[4]),
.QN(n3718) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_36_ ( .D(n1539), .CK(clk),
.RN(n3849), .Q(Add_Subt_result[36]), .QN(n3793) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_39_ ( .D(n1542), .CK(clk),
.RN(n3850), .Q(Add_Subt_result[39]) );
DFFRX1TS YRegister_Q_reg_63_ ( .D(n1231), .CK(clk), .RN(n3864), .Q(intDY[63]) );
DFFRX1TS XRegister_Q_reg_9_ ( .D(n1306), .CK(clk), .RN(n3859), .Q(intDX[9]),
.QN(n3722) );
DFFRX1TS XRegister_Q_reg_30_ ( .D(n1327), .CK(clk), .RN(n3861), .Q(intDX[30]), .QN(n3685) );
DFFRX1TS XRegister_Q_reg_56_ ( .D(n1353), .CK(clk), .RN(n3863), .Q(intDX[56]), .QN(n3726) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(n1510), .CK(clk),
.RN(n3847), .Q(Add_Subt_result[7]), .QN(n3797) );
DFFRX2TS YRegister_Q_reg_33_ ( .D(n1265), .CK(clk), .RN(n3855), .Q(intDY[33]) );
DFFRX2TS YRegister_Q_reg_53_ ( .D(n1285), .CK(clk), .RN(n3857), .Q(intDY[53]) );
DFFRX2TS YRegister_Q_reg_31_ ( .D(n1263), .CK(clk), .RN(n3855), .Q(intDY[31]) );
DFFRX2TS YRegister_Q_reg_35_ ( .D(n1267), .CK(clk), .RN(n3855), .Q(intDY[35]) );
DFFRX2TS YRegister_Q_reg_43_ ( .D(n1275), .CK(clk), .RN(n3856), .Q(intDY[43]) );
DFFRX2TS YRegister_Q_reg_55_ ( .D(n1287), .CK(clk), .RN(n3857), .Q(intDY[55]) );
DFFRX2TS YRegister_Q_reg_23_ ( .D(n1255), .CK(clk), .RN(n3854), .Q(intDY[23]) );
DFFRX2TS YRegister_Q_reg_29_ ( .D(n1261), .CK(clk), .RN(n3854), .Q(intDY[29]) );
DFFRX2TS YRegister_Q_reg_13_ ( .D(n1245), .CK(clk), .RN(n3853), .Q(intDY[13]) );
DFFRX2TS YRegister_Q_reg_21_ ( .D(n1253), .CK(clk), .RN(n3854), .Q(intDY[21]) );
DFFRX2TS YRegister_Q_reg_11_ ( .D(n1243), .CK(clk), .RN(n3853), .Q(intDY[11]) );
DFFRX2TS YRegister_Q_reg_57_ ( .D(n1289), .CK(clk), .RN(n3857), .Q(intDY[57]) );
DFFRX2TS YRegister_Q_reg_17_ ( .D(n1249), .CK(clk), .RN(n3853), .Q(intDY[17]) );
DFFRX2TS YRegister_Q_reg_25_ ( .D(n1257), .CK(clk), .RN(n3854), .Q(intDY[25]) );
DFFRX2TS YRegister_Q_reg_46_ ( .D(n1278), .CK(clk), .RN(n3856), .Q(intDY[46]) );
DFFRX2TS YRegister_Q_reg_60_ ( .D(n1292), .CK(clk), .RN(n3858), .Q(intDY[60]) );
DFFRX2TS YRegister_Q_reg_42_ ( .D(n1274), .CK(clk), .RN(n3856), .Q(intDY[42]) );
DFFRX2TS YRegister_Q_reg_49_ ( .D(n1281), .CK(clk), .RN(n3856), .Q(intDY[49]) );
DFFRX2TS YRegister_Q_reg_8_ ( .D(n1240), .CK(clk), .RN(n3852), .Q(intDY[8])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_27_ ( .D(n1530), .CK(clk),
.RN(n3849), .Q(Add_Subt_result[27]) );
DFFRX2TS YRegister_Q_reg_40_ ( .D(n1272), .CK(clk), .RN(n3856), .Q(intDY[40]) );
DFFRX2TS YRegister_Q_reg_51_ ( .D(n1283), .CK(clk), .RN(n3857), .Q(intDY[51]) );
DFFRX2TS YRegister_Q_reg_9_ ( .D(n1241), .CK(clk), .RN(n3852), .Q(intDY[9])
);
DFFRX2TS YRegister_Q_reg_47_ ( .D(n1279), .CK(clk), .RN(n3856), .Q(intDY[47]) );
DFFRX2TS YRegister_Q_reg_2_ ( .D(n1234), .CK(clk), .RN(n3852), .Q(intDY[2])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_21_ ( .D(n1524), .CK(clk),
.RN(n3848), .Q(Add_Subt_result[21]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_34_ ( .D(n1537), .CK(clk),
.RN(n3849), .Q(Add_Subt_result[34]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_32_ ( .D(n1535), .CK(clk),
.RN(n3848), .Q(Add_Subt_result[32]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_18_ ( .D(n1521), .CK(clk),
.RN(n3848), .Q(Add_Subt_result[18]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(n1511), .CK(clk),
.RN(n3847), .Q(Add_Subt_result[8]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_41_ ( .D(n1544), .CK(clk),
.RN(n3850), .Q(Add_Subt_result[41]) );
DFFRX2TS YRegister_Q_reg_37_ ( .D(n1269), .CK(clk), .RN(n3855), .Q(intDY[37]), .QN(n1611) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_13_ ( .D(n1516), .CK(clk),
.RN(n3847), .Q(Add_Subt_result[13]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_30_ ( .D(n1533), .CK(clk),
.RN(n3849), .Q(Add_Subt_result[30]), .QN(n3780) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_11_ ( .D(n1514), .CK(clk),
.RN(n3847), .Q(Add_Subt_result[11]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(n1504), .CK(clk),
.RN(n3846), .Q(Add_Subt_result[1]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(n1506), .CK(clk),
.RN(n3846), .Q(Add_Subt_result[3]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(n1518), .CK(clk),
.RN(n3851), .Q(Add_Subt_result[15]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_4_ ( .D(n1434), .CK(clk),
.RN(n3845), .Q(exp_oper_result[4]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(n1435), .CK(clk),
.RN(n3846), .Q(exp_oper_result[3]) );
DFFRX2TS Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(n1438), .CK(clk),
.RN(n3830), .Q(exp_oper_result[0]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[25]), .CK(clk), .RN(n3816),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[80]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_26_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[26]), .CK(clk), .RN(n3816),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[81]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_27_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[27]), .CK(clk), .RN(n3816),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[82]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_28_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[28]), .CK(clk), .RN(n3815),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[83]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_29_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[29]), .CK(clk), .RN(n3815),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[84]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_30_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[30]), .CK(clk), .RN(n3815),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[85]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_35_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[35]), .CK(clk), .RN(n3815),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[90]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_31_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[31]), .CK(clk), .RN(n3815),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[86]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_33_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[33]), .CK(clk), .RN(n3815),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[88]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_34_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .CK(clk), .RN(n3815),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[89]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_36_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .CK(clk), .RN(n3815),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[91]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_37_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .CK(clk), .RN(n3815),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[92]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[24]), .CK(clk), .RN(n3816),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[79]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_32_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[32]), .CK(clk), .RN(n3815),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[87]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_5_ ( .D(n1433), .CK(clk),
.RN(n3846), .Q(exp_oper_result[5]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(n1436), .CK(clk),
.RN(n3845), .Q(exp_oper_result[2]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(n1437), .CK(clk),
.RN(n3845), .Q(exp_oper_result[1]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_38_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .CK(clk), .RN(n3814),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[93]) );
DFFRX1TS Exp_Operation_Module_Underflow_Q_reg_0_ ( .D(n1426), .CK(clk), .RN(
n3830), .Q(underflow_flag) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1444), .CK(clk),
.RN(n3834), .Q(Sgf_normalized_result[2]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_30_ ( .D(n1472), .CK(clk),
.RN(n3839), .Q(Sgf_normalized_result[30]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n1467), .CK(clk),
.RN(n3838), .Q(Sgf_normalized_result[25]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_29_ ( .D(n1471), .CK(clk),
.RN(n3839), .Q(Sgf_normalized_result[29]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_26_ ( .D(n1468), .CK(clk),
.RN(n3839), .Q(Sgf_normalized_result[26]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_28_ ( .D(n1470), .CK(clk),
.RN(n3839), .Q(Sgf_normalized_result[28]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_33_ ( .D(n1475), .CK(clk),
.RN(n3840), .Q(Sgf_normalized_result[33]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_34_ ( .D(n1476), .CK(clk),
.RN(n3840), .Q(Sgf_normalized_result[34]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_35_ ( .D(n1477), .CK(clk),
.RN(n3840), .Q(Sgf_normalized_result[35]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_36_ ( .D(n1478), .CK(clk),
.RN(n3841), .Q(Sgf_normalized_result[36]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_37_ ( .D(n1479), .CK(clk),
.RN(n3841), .Q(Sgf_normalized_result[37]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_38_ ( .D(n1480), .CK(clk),
.RN(n3841), .Q(Sgf_normalized_result[38]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_41_ ( .D(n1483), .CK(clk),
.RN(n3842), .Q(Sgf_normalized_result[41]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_42_ ( .D(n1484), .CK(clk),
.RN(n3842), .Q(Sgf_normalized_result[42]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1457), .CK(clk),
.RN(n3836), .Q(Sgf_normalized_result[15]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_31_ ( .D(n1473), .CK(clk),
.RN(n3840), .Q(Sgf_normalized_result[31]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1456), .CK(clk),
.RN(n3836), .Q(Sgf_normalized_result[14]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_46_ ( .D(n1488), .CK(clk),
.RN(n3843), .Q(Sgf_normalized_result[46]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1451), .CK(clk),
.RN(n3835), .Q(Sgf_normalized_result[9]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_45_ ( .D(n1487), .CK(clk),
.RN(n3842), .Q(Sgf_normalized_result[45]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1452), .CK(clk),
.RN(n3835), .Q(Sgf_normalized_result[10]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_44_ ( .D(n1486), .CK(clk),
.RN(n3842), .Q(Sgf_normalized_result[44]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_43_ ( .D(n1485), .CK(clk),
.RN(n3842), .Q(Sgf_normalized_result[43]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_53_ ( .D(n1495), .CK(clk),
.RN(n3844), .Q(Sgf_normalized_result[53]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_52_ ( .D(n1494), .CK(clk),
.RN(n3844), .Q(Sgf_normalized_result[52]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_51_ ( .D(n1493), .CK(clk),
.RN(n3844), .Q(Sgf_normalized_result[51]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_50_ ( .D(n1492), .CK(clk),
.RN(n3844), .Q(Sgf_normalized_result[50]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_49_ ( .D(n1491), .CK(clk),
.RN(n3843), .Q(Sgf_normalized_result[49]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_48_ ( .D(n1490), .CK(clk),
.RN(n3843), .Q(Sgf_normalized_result[48]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_47_ ( .D(n1489), .CK(clk),
.RN(n3843), .Q(Sgf_normalized_result[47]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_40_ ( .D(n1482), .CK(clk),
.RN(n3841), .Q(Sgf_normalized_result[40]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n1466), .CK(clk),
.RN(n3838), .Q(Sgf_normalized_result[24]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_10_ ( .D(n1428), .CK(clk),
.RN(n3833), .Q(exp_oper_result[10]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_9_ ( .D(n1429), .CK(clk),
.RN(n3833), .Q(exp_oper_result[9]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_8_ ( .D(n1430), .CK(clk),
.RN(n3833), .Q(exp_oper_result[8]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_7_ ( .D(n1431), .CK(clk),
.RN(n3832), .Q(exp_oper_result[7]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_6_ ( .D(n1432), .CK(clk),
.RN(n3832), .Q(exp_oper_result[6]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_54_ ( .D(n1563), .CK(clk),
.RN(n3845), .Q(Sgf_normalized_result[54]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_37_ ( .D(n1540), .CK(clk),
.RN(n3850), .Q(Add_Subt_result[37]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_42_ ( .D(n1545), .CK(clk),
.RN(n3851), .Q(Add_Subt_result[42]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_43_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .CK(clk), .RN(n3814),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[98]), .QN(n1575) );
DFFRX2TS Sel_B_Q_reg_0_ ( .D(n1440), .CK(clk), .RN(n1360), .Q(
FSM_selector_B[0]), .QN(n3727) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n1439), .CK(clk), .RN(n1360), .Q(
FSM_selector_B[1]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(n1105), .CK(clk), .RN(
n3824), .Q(DmP[0]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(n1106), .CK(clk), .RN(
n3823), .Q(DmP[1]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_3_ ( .D(n1108), .CK(clk), .RN(
n3823), .Q(DmP[3]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(n1109), .CK(clk), .RN(
n3823), .Q(DmP[4]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(n1110), .CK(clk), .RN(
n3823), .Q(DmP[5]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(n1111), .CK(clk), .RN(
n3823), .Q(DmP[6]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(n1112), .CK(clk), .RN(
n3823), .Q(DmP[7]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(n1117), .CK(clk),
.RN(n3822), .Q(DmP[12]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(n1119), .CK(clk),
.RN(n3822), .Q(DmP[14]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(n1121), .CK(clk),
.RN(n3822), .Q(DmP[16]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(n1124), .CK(clk),
.RN(n3822), .Q(DmP[19]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(n1131), .CK(clk),
.RN(n3821), .Q(DmP[26]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(n1132), .CK(clk),
.RN(n3821), .Q(DmP[27]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(n1135), .CK(clk),
.RN(n3821), .Q(DmP[30]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_32_ ( .D(n1137), .CK(clk),
.RN(n3820), .Q(DmP[32]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_36_ ( .D(n1141), .CK(clk),
.RN(n3820), .Q(DmP[36]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_38_ ( .D(n1143), .CK(clk),
.RN(n3820), .Q(DmP[38]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_45_ ( .D(n1150), .CK(clk),
.RN(n3819), .Q(DmP[45]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_48_ ( .D(n1153), .CK(clk),
.RN(n3819), .Q(DmP[48]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_50_ ( .D(n1155), .CK(clk),
.RN(n3819), .Q(DmP[50]) );
DFFRX2TS YRegister_Q_reg_58_ ( .D(n1290), .CK(clk), .RN(n3857), .Q(intDY[58]) );
DFFRX2TS YRegister_Q_reg_26_ ( .D(n1258), .CK(clk), .RN(n3854), .Q(intDY[26]) );
DFFRX2TS YRegister_Q_reg_45_ ( .D(n1277), .CK(clk), .RN(n3856), .Q(intDY[45]) );
DFFRX2TS YRegister_Q_reg_24_ ( .D(n1256), .CK(clk), .RN(n3854), .Q(intDY[24]) );
DFFRX2TS YRegister_Q_reg_56_ ( .D(n1288), .CK(clk), .RN(n3857), .Q(intDY[56]) );
DFFRX2TS YRegister_Q_reg_36_ ( .D(n1268), .CK(clk), .RN(n3855), .Q(intDY[36]) );
DFFRX2TS YRegister_Q_reg_54_ ( .D(n1286), .CK(clk), .RN(n3857), .Q(intDY[54]) );
DFFRX2TS YRegister_Q_reg_50_ ( .D(n1282), .CK(clk), .RN(n3857), .Q(intDY[50]) );
DFFRX2TS YRegister_Q_reg_18_ ( .D(n1250), .CK(clk), .RN(n3853), .Q(intDY[18]) );
DFFRX2TS YRegister_Q_reg_14_ ( .D(n1246), .CK(clk), .RN(n3853), .Q(intDY[14]) );
DFFRX2TS YRegister_Q_reg_12_ ( .D(n1244), .CK(clk), .RN(n3853), .Q(intDY[12]) );
DFFRX2TS YRegister_Q_reg_27_ ( .D(n1259), .CK(clk), .RN(n3854), .Q(intDY[27]) );
DFFRX2TS YRegister_Q_reg_22_ ( .D(n1254), .CK(clk), .RN(n3854), .Q(intDY[22]) );
DFFRX2TS YRegister_Q_reg_59_ ( .D(n1291), .CK(clk), .RN(n3857), .Q(intDY[59]) );
DFFRX2TS YRegister_Q_reg_32_ ( .D(n1264), .CK(clk), .RN(n3855), .Q(intDY[32]) );
DFFRX2TS YRegister_Q_reg_34_ ( .D(n1266), .CK(clk), .RN(n3855), .Q(intDY[34]) );
DFFRX2TS YRegister_Q_reg_19_ ( .D(n1251), .CK(clk), .RN(n3853), .Q(intDY[19]) );
DFFRX2TS YRegister_Q_reg_30_ ( .D(n1262), .CK(clk), .RN(n3855), .Q(intDY[30]) );
DFFRX2TS YRegister_Q_reg_0_ ( .D(n1232), .CK(clk), .RN(n3852), .Q(intDY[0])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_19_ ( .D(n1522), .CK(clk),
.RN(n3848), .Q(Add_Subt_result[19]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_29_ ( .D(n1532), .CK(clk),
.RN(n3849), .Q(Add_Subt_result[29]), .QN(n3782) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_17_ ( .D(n1520), .CK(clk),
.RN(n3848), .Q(Add_Subt_result[17]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_39_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .CK(clk), .RN(n3814),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[94]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_40_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .CK(clk), .RN(n3814),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[95]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_42_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .CK(clk), .RN(n3814),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[97]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_41_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .CK(clk), .RN(n3814),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[96]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_46_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .CK(clk), .RN(n3814),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[101]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_45_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .CK(clk), .RN(n3814),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[100]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_44_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .CK(clk), .RN(n3814),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[99]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[23]), .CK(clk), .RN(n3816),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[78]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[22]), .CK(clk), .RN(n3816),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[77]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[21]), .CK(clk), .RN(n3816),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[76]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[20]), .CK(clk), .RN(n3816),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[75]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[19]), .CK(clk), .RN(n3816),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[74]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[18]), .CK(clk), .RN(n3816),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[73]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[17]), .CK(clk), .RN(n3817),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[72]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[16]), .CK(clk), .RN(n3817),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[71]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_61_ ( .D(n1230), .CK(clk),
.RN(n3833), .Q(DMP[61]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_55_ ( .D(n1224), .CK(clk),
.RN(n3832), .Q(DMP[55]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_53_ ( .D(n1222), .CK(clk),
.RN(n3832), .Q(DMP[53]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_52_ ( .D(n1221), .CK(clk),
.RN(n3832), .Q(DMP[52]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_49_ ( .D(n1218), .CK(clk),
.RN(n3844), .Q(DMP[49]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_48_ ( .D(n1217), .CK(clk),
.RN(n3844), .Q(DMP[48]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_47_ ( .D(n1216), .CK(clk),
.RN(n3843), .Q(DMP[47]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_46_ ( .D(n1215), .CK(clk),
.RN(n3843), .Q(DMP[46]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_43_ ( .D(n1212), .CK(clk),
.RN(n3843), .Q(DMP[43]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(n1190), .CK(clk),
.RN(n3838), .Q(DMP[21]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(n1182), .CK(clk),
.RN(n3837), .Q(DMP[13]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(n1176), .CK(clk), .RN(
n3835), .Q(DMP[7]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_62_ ( .D(n1168), .CK(clk),
.RN(n3833), .Q(DMP[62]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[15]), .CK(clk), .RN(n3817),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[70]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[14]), .CK(clk), .RN(n3817),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[69]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[13]), .CK(clk), .RN(n3817),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[68]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[12]), .CK(clk), .RN(n3817),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[67]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[11]), .CK(clk), .RN(n3817),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[66]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[10]), .CK(clk), .RN(n3817),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[65]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[9]), .CK(clk), .RN(n3817),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[64]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[8]), .CK(clk), .RN(n3817),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[63]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(n1130), .CK(clk),
.RN(n3821), .Q(DmP[25]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_51_ ( .D(n1156), .CK(clk),
.RN(n3818), .Q(DmP[51]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_49_ ( .D(n1154), .CK(clk),
.RN(n3819), .Q(DmP[49]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_47_ ( .D(n1152), .CK(clk),
.RN(n3819), .Q(DmP[47]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_46_ ( .D(n1151), .CK(clk),
.RN(n3819), .Q(DmP[46]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_44_ ( .D(n1149), .CK(clk),
.RN(n3819), .Q(DmP[44]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_43_ ( .D(n1148), .CK(clk),
.RN(n3819), .Q(DmP[43]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_42_ ( .D(n1147), .CK(clk),
.RN(n3819), .Q(DmP[42]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_41_ ( .D(n1146), .CK(clk),
.RN(n3819), .Q(DmP[41]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_40_ ( .D(n1145), .CK(clk),
.RN(n3820), .Q(DmP[40]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_39_ ( .D(n1144), .CK(clk),
.RN(n3820), .Q(DmP[39]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_37_ ( .D(n1142), .CK(clk),
.RN(n3820), .Q(DmP[37]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_35_ ( .D(n1140), .CK(clk),
.RN(n3820), .Q(DmP[35]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_34_ ( .D(n1139), .CK(clk),
.RN(n3820), .Q(DmP[34]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_33_ ( .D(n1138), .CK(clk),
.RN(n3820), .Q(DmP[33]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_31_ ( .D(n1136), .CK(clk),
.RN(n3820), .Q(DmP[31]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(n1134), .CK(clk),
.RN(n3821), .Q(DmP[29]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(n1133), .CK(clk),
.RN(n3821), .Q(DmP[28]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(n1129), .CK(clk),
.RN(n3821), .Q(DmP[24]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(n1128), .CK(clk),
.RN(n3821), .Q(DmP[23]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(n1127), .CK(clk),
.RN(n3821), .Q(DmP[22]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(n1126), .CK(clk),
.RN(n3821), .Q(DmP[21]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(n1125), .CK(clk),
.RN(n3822), .Q(DmP[20]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(n1123), .CK(clk),
.RN(n3822), .Q(DmP[18]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(n1122), .CK(clk),
.RN(n3822), .Q(DmP[17]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(n1120), .CK(clk),
.RN(n3822), .Q(DmP[15]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(n1118), .CK(clk),
.RN(n3822), .Q(DmP[13]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(n1116), .CK(clk),
.RN(n3822), .Q(DmP[11]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(n1115), .CK(clk),
.RN(n3823), .Q(DmP[10]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(n1114), .CK(clk), .RN(
n3823), .Q(DmP[9]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(n1113), .CK(clk), .RN(
n3823), .Q(DmP[8]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(n1107), .CK(clk), .RN(
n3823), .Q(DmP[2]) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n1558), .CK(clk), .RN(n3864), .Q(
FS_Module_state_reg[2]), .QN(n3706) );
DFFRX1TS Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ ( .D(n1562), .CK(
clk), .RN(n3834), .Q(add_overflow_flag), .QN(n3714) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_48_ ( .D(n1551), .CK(clk),
.RN(n3851), .Q(Add_Subt_result[48]), .QN(n3729) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_46_ ( .D(n1549), .CK(clk),
.RN(n3851), .Q(Add_Subt_result[46]), .QN(n3715) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_54_ ( .D(n1502), .CK(clk),
.RN(n3850), .Q(Add_Subt_result[54]), .QN(n3811) );
DFFRX1TS XRegister_Q_reg_63_ ( .D(n1296), .CK(clk), .RN(n3864), .Q(intDX[63]), .QN(n3730) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_38_ ( .D(n1541), .CK(clk),
.RN(n3850), .Q(Add_Subt_result[38]), .QN(n3807) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_40_ ( .D(n1543), .CK(clk),
.RN(n3850), .Q(Add_Subt_result[40]), .QN(n3796) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_20_ ( .D(n1523), .CK(clk),
.RN(n3848), .Q(Add_Subt_result[20]), .QN(n3794) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_24_ ( .D(n1527), .CK(clk),
.RN(n3848), .Q(Add_Subt_result[24]), .QN(n3787) );
DFFRX1TS XRegister_Q_reg_0_ ( .D(n1297), .CK(clk), .RN(n3858), .Q(intDX[0]),
.QN(n3758) );
DFFRX1TS XRegister_Q_reg_61_ ( .D(n1358), .CK(clk), .RN(n3864), .Q(intDX[61]), .QN(n3743) );
DFFRX2TS XRegister_Q_reg_62_ ( .D(n1359), .CK(clk), .RN(n3833), .Q(intDX[62]), .QN(n3737) );
DFFRX2TS YRegister_Q_reg_61_ ( .D(n1293), .CK(clk), .RN(n3858), .Q(intDY[61]), .QN(n3704) );
DFFRX1TS XRegister_Q_reg_59_ ( .D(n1356), .CK(clk), .RN(n3864), .Q(intDX[59]), .QN(n3697) );
DFFRX2TS YRegister_Q_reg_62_ ( .D(n1294), .CK(clk), .RN(n3858), .Q(intDY[62]), .QN(n3689) );
DFFRX1TS XRegister_Q_reg_39_ ( .D(n1336), .CK(clk), .RN(n3862), .Q(intDX[39]), .QN(n3744) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_44_ ( .D(n1547), .CK(clk),
.RN(n3851), .Q(Add_Subt_result[44]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1465), .CK(clk),
.RN(n3838), .Q(Sgf_normalized_result[23]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_39_ ( .D(n1481), .CK(clk),
.RN(n3841), .Q(Sgf_normalized_result[39]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_53_ ( .D(n1556), .CK(clk),
.RN(n3850), .Q(Add_Subt_result[53]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1450), .CK(clk),
.RN(n3835), .Q(Sgf_normalized_result[8]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_32_ ( .D(n1474), .CK(clk),
.RN(n3840), .Q(Sgf_normalized_result[32]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(n1503), .CK(clk),
.RN(n3846), .Q(Add_Subt_result[0]), .QN(n3795) );
DFFRX1TS XRegister_Q_reg_34_ ( .D(n1331), .CK(clk), .RN(n3861), .Q(intDX[34]), .QN(n3701) );
DFFRX1TS XRegister_Q_reg_32_ ( .D(n1329), .CK(clk), .RN(n3861), .Q(intDX[32]), .QN(n3721) );
DFFRX1TS XRegister_Q_reg_28_ ( .D(n1325), .CK(clk), .RN(n3861), .Q(intDX[28]), .QN(n3724) );
DFFRX1TS XRegister_Q_reg_27_ ( .D(n1324), .CK(clk), .RN(n3861), .Q(intDX[27]), .QN(n3692) );
DFFRX1TS XRegister_Q_reg_24_ ( .D(n1321), .CK(clk), .RN(n3860), .Q(intDX[24]), .QN(n3723) );
DFFRX1TS XRegister_Q_reg_22_ ( .D(n1319), .CK(clk), .RN(n3860), .Q(intDX[22]), .QN(n3686) );
DFFRX1TS XRegister_Q_reg_20_ ( .D(n1317), .CK(clk), .RN(n3860), .Q(intDX[20]), .QN(n3736) );
DFFRX1TS XRegister_Q_reg_19_ ( .D(n1316), .CK(clk), .RN(n3860), .Q(intDX[19]), .QN(n3693) );
DFFRX1TS XRegister_Q_reg_16_ ( .D(n1313), .CK(clk), .RN(n3859), .Q(intDX[16]), .QN(n3716) );
DFFRX1TS XRegister_Q_reg_14_ ( .D(n1311), .CK(clk), .RN(n3859), .Q(intDX[14]), .QN(n3687) );
DFFRX1TS XRegister_Q_reg_12_ ( .D(n1309), .CK(clk), .RN(n3859), .Q(intDX[12]), .QN(n3725) );
DFFRX1TS XRegister_Q_reg_10_ ( .D(n1307), .CK(clk), .RN(n3859), .Q(intDX[10]), .QN(n3682) );
DFFRX1TS XRegister_Q_reg_6_ ( .D(n1303), .CK(clk), .RN(n3858), .Q(intDX[6]),
.QN(n3717) );
DFFRX1TS XRegister_Q_reg_54_ ( .D(n1351), .CK(clk), .RN(n3863), .Q(intDX[54]), .QN(n3684) );
DFFRX1TS XRegister_Q_reg_52_ ( .D(n1349), .CK(clk), .RN(n3863), .Q(intDX[52]), .QN(n3719) );
DFFRX1TS XRegister_Q_reg_51_ ( .D(n1348), .CK(clk), .RN(n3863), .Q(intDX[51]), .QN(n3694) );
DFFRX1TS XRegister_Q_reg_48_ ( .D(n1345), .CK(clk), .RN(n3863), .Q(intDX[48]), .QN(n3695) );
DFFRX1TS XRegister_Q_reg_47_ ( .D(n1344), .CK(clk), .RN(n3863), .Q(intDX[47]), .QN(n3740) );
DFFRX1TS XRegister_Q_reg_46_ ( .D(n1343), .CK(clk), .RN(n3862), .Q(intDX[46]), .QN(n3742) );
DFFRX1TS XRegister_Q_reg_44_ ( .D(n1341), .CK(clk), .RN(n3862), .Q(intDX[44]), .QN(n3738) );
DFFRX1TS XRegister_Q_reg_42_ ( .D(n1339), .CK(clk), .RN(n3862), .Q(intDX[42]), .QN(n3700) );
DFFRX1TS XRegister_Q_reg_40_ ( .D(n1337), .CK(clk), .RN(n3862), .Q(intDX[40]), .QN(n3698) );
DFFRX1TS XRegister_Q_reg_37_ ( .D(n1334), .CK(clk), .RN(n3862), .Q(intDX[37]), .QN(n3739) );
DFFRX1TS XRegister_Q_reg_2_ ( .D(n1299), .CK(clk), .RN(n3858), .Q(intDX[2]),
.QN(n3683) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_48_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[48]), .CK(clk), .RN(n3818),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[103]), .QN(n3798) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1455), .CK(clk),
.RN(n3836), .Q(Sgf_normalized_result[13]), .QN(n3774) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1454), .CK(clk),
.RN(n3836), .Q(Sgf_normalized_result[12]), .QN(n3775) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_31_ ( .D(n1534), .CK(clk),
.RN(n3848), .Q(Add_Subt_result[31]), .QN(n3789) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_27_ ( .D(n1469), .CK(clk),
.RN(n3839), .Q(Sgf_normalized_result[27]), .QN(n3809) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_54_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[54]), .CK(clk), .RN(n3845),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[109]), .QN(n3801) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_51_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .CK(clk), .RN(n3844),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[106]), .QN(n3806) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_52_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[52]), .CK(clk), .RN(n3844),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[107]), .QN(n3805) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_49_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[49]), .CK(clk), .RN(n3843),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[104]), .QN(n3802) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_47_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .CK(clk), .RN(n3814),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[102]), .QN(n3799) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_50_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .CK(clk), .RN(n3844),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[105]), .QN(n3804) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_53_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[53]), .CK(clk), .RN(n3845),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[108]), .QN(n3803) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_23_ ( .D(n1526), .CK(clk),
.RN(n3848), .Q(Add_Subt_result[23]), .QN(n3791) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_35_ ( .D(n1538), .CK(clk),
.RN(n3849), .Q(Add_Subt_result[35]), .QN(n3690) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(n1515), .CK(clk),
.RN(n3847), .Q(Add_Subt_result[12]), .QN(n3800) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_25_ ( .D(n1528), .CK(clk),
.RN(n3849), .Q(Add_Subt_result[25]), .QN(n3691) );
DFFRX1TS Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(n1167), .CK(clk),
.RN(n3851), .Q(sign_final_result), .QN(n3703) );
DFFRX2TS YRegister_Q_reg_20_ ( .D(n1252), .CK(clk), .RN(n3854), .Q(intDY[20]) );
DFFRX2TS YRegister_Q_reg_28_ ( .D(n1260), .CK(clk), .RN(n3854), .Q(intDY[28]) );
DFFRX1TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_5_ ( .D(n1496), .CK(
clk), .RN(n3846), .Q(LZA_output[5]) );
DFFRX4TS FS_Module_state_reg_reg_1_ ( .D(n1559), .CK(clk), .RN(n3833), .Q(
FS_Module_state_reg[1]), .QN(n3785) );
DFFRX2TS ASRegister_Q_reg_0_ ( .D(n1295), .CK(clk), .RN(n3864), .Q(intAS) );
AOI222X1TS U1759 ( .A0(n2579), .A1(DMP[0]), .B0(n2588), .B1(intDX[0]), .C0(
intDY[0]), .C1(n2587), .Y(n2568) );
AOI222X1TS U1760 ( .A0(n2573), .A1(DMP[2]), .B0(n2588), .B1(intDX[2]), .C0(
intDY[2]), .C1(n2587), .Y(n2561) );
AOI222X1TS U1761 ( .A0(n2573), .A1(DMP[9]), .B0(n2578), .B1(intDX[9]), .C0(
intDY[9]), .C1(n1585), .Y(n2528) );
AOI222X1TS U1762 ( .A0(n2541), .A1(DMP[1]), .B0(n2588), .B1(intDX[1]), .C0(
intDY[1]), .C1(n2587), .Y(n2590) );
AOI222X1TS U1763 ( .A0(n2585), .A1(DMP[3]), .B0(n2578), .B1(intDX[3]), .C0(
intDY[3]), .C1(n2587), .Y(n2559) );
AOI222X1TS U1764 ( .A0(n2541), .A1(DMP[14]), .B0(n2592), .B1(intDX[14]),
.C0(intDY[14]), .C1(n1585), .Y(n2535) );
AOI222X1TS U1765 ( .A0(n2593), .A1(DMP[11]), .B0(n2578), .B1(intDX[11]),
.C0(intDY[11]), .C1(n1585), .Y(n2538) );
AOI222X1TS U1766 ( .A0(n2585), .A1(DMP[17]), .B0(n2592), .B1(intDX[17]),
.C0(intDY[17]), .C1(n2591), .Y(n2567) );
AOI222X1TS U1767 ( .A0(n2573), .A1(DMP[23]), .B0(n2592), .B1(intDX[23]),
.C0(intDY[23]), .C1(n2591), .Y(n2577) );
AOI222X1TS U1768 ( .A0(n2573), .A1(DMP[15]), .B0(n2592), .B1(intDX[15]),
.C0(intDY[15]), .C1(n2591), .Y(n2594) );
AOI222X1TS U1769 ( .A0(n2593), .A1(DMP[30]), .B0(n2547), .B1(intDX[30]),
.C0(intDY[30]), .C1(n2543), .Y(n2582) );
AOI222X1TS U1770 ( .A0(n2541), .A1(DMP[4]), .B0(n2578), .B1(intDX[4]), .C0(
intDY[4]), .C1(n2587), .Y(n2580) );
AOI222X1TS U1771 ( .A0(n2593), .A1(DMP[59]), .B0(n2588), .B1(intDX[59]),
.C0(intDY[59]), .C1(n2587), .Y(n2555) );
AOI222X1TS U1772 ( .A0(n2573), .A1(DMP[58]), .B0(n2588), .B1(intDX[58]),
.C0(intDY[58]), .C1(n2587), .Y(n2551) );
AOI222X1TS U1773 ( .A0(n2585), .A1(DMP[60]), .B0(n2588), .B1(intDX[60]),
.C0(intDY[60]), .C1(n2587), .Y(n2556) );
AOI222X1TS U1774 ( .A0(n2579), .A1(DMP[56]), .B0(n2588), .B1(intDX[56]),
.C0(intDY[56]), .C1(n2543), .Y(n2540) );
AOI222X1TS U1775 ( .A0(n2593), .A1(DMP[57]), .B0(n2588), .B1(intDX[57]),
.C0(intDY[57]), .C1(n2543), .Y(n2544) );
AOI222X1TS U1776 ( .A0(n2541), .A1(DMP[32]), .B0(n2524), .B1(intDX[32]),
.C0(intDY[32]), .C1(n2543), .Y(n2548) );
AOI222X1TS U1777 ( .A0(n2585), .A1(DMP[27]), .B0(n2524), .B1(intDX[27]),
.C0(intDY[27]), .C1(n2543), .Y(n2562) );
AOI222X1TS U1778 ( .A0(n2579), .A1(DMP[26]), .B0(n2524), .B1(intDX[26]),
.C0(intDY[26]), .C1(n2543), .Y(n2563) );
AOI222X1TS U1779 ( .A0(n2570), .A1(DMP[34]), .B0(n2553), .B1(intDX[34]),
.C0(intDY[34]), .C1(n2523), .Y(n2530) );
AOI222X1TS U1780 ( .A0(n2593), .A1(DMP[45]), .B0(n2524), .B1(intDX[45]),
.C0(intDY[45]), .C1(n2523), .Y(n2519) );
AOI222X1TS U1781 ( .A0(n2579), .A1(DMP[50]), .B0(n2516), .B1(intDX[50]),
.C0(intDY[50]), .C1(n2523), .Y(n2483) );
AOI222X1TS U1782 ( .A0(n2541), .A1(DMP[12]), .B0(n2578), .B1(intDX[12]),
.C0(intDY[12]), .C1(n1585), .Y(n2566) );
AOI222X1TS U1783 ( .A0(n2573), .A1(DMP[10]), .B0(n2578), .B1(intDX[10]),
.C0(intDY[10]), .C1(n1585), .Y(n2527) );
AOI222X1TS U1784 ( .A0(n2541), .A1(DMP[6]), .B0(n2578), .B1(intDX[6]), .C0(
intDY[6]), .C1(n1585), .Y(n2526) );
AOI222X1TS U1785 ( .A0(n2585), .A1(DMP[5]), .B0(n2578), .B1(intDX[5]), .C0(
intDY[5]), .C1(n1585), .Y(n2537) );
AOI222X1TS U1786 ( .A0(n2579), .A1(DMP[8]), .B0(n2578), .B1(intDX[8]), .C0(
intDY[8]), .C1(n1585), .Y(n2533) );
AOI222X1TS U1787 ( .A0(n2573), .A1(DMP[22]), .B0(n2592), .B1(intDX[22]),
.C0(intDY[22]), .C1(n2591), .Y(n2583) );
AOI222X1TS U1788 ( .A0(n2585), .A1(DMP[19]), .B0(n2592), .B1(intDX[19]),
.C0(intDY[19]), .C1(n2591), .Y(n2584) );
AOI222X1TS U1789 ( .A0(n2579), .A1(DMP[18]), .B0(n2592), .B1(intDX[18]),
.C0(intDY[18]), .C1(n2591), .Y(n2575) );
AOI222X1TS U1790 ( .A0(n2593), .A1(DMP[16]), .B0(n2592), .B1(intDX[16]),
.C0(intDY[16]), .C1(n2591), .Y(n2560) );
AOI222X1TS U1791 ( .A0(n2570), .A1(DMP[38]), .B0(n2553), .B1(intDX[38]),
.C0(intDY[38]), .C1(n2552), .Y(n2554) );
AOI222X1TS U1792 ( .A0(n2570), .A1(DMP[36]), .B0(n2553), .B1(intDX[36]),
.C0(intDY[36]), .C1(n2552), .Y(n2545) );
AOI222X1TS U1793 ( .A0(n2570), .A1(DMP[41]), .B0(n2553), .B1(intDX[41]),
.C0(intDY[41]), .C1(n2552), .Y(n2534) );
AOI222X1TS U1794 ( .A0(n2570), .A1(DMP[37]), .B0(n2553), .B1(intDX[37]),
.C0(intDY[37]), .C1(n2552), .Y(n2532) );
AOI222X1TS U1795 ( .A0(n2570), .A1(DMP[40]), .B0(n2553), .B1(intDX[40]),
.C0(intDY[40]), .C1(n2552), .Y(n2531) );
AOI222X1TS U1796 ( .A0(n2579), .A1(DMP[20]), .B0(n2592), .B1(intDX[20]),
.C0(intDY[20]), .C1(n2591), .Y(n2574) );
AOI222X1TS U1797 ( .A0(n1590), .A1(DMP[42]), .B0(n2553), .B1(intDX[42]),
.C0(intDY[42]), .C1(n2552), .Y(n2549) );
AOI222X1TS U1798 ( .A0(n2570), .A1(DMP[35]), .B0(n2553), .B1(intDX[35]),
.C0(intDY[35]), .C1(n2552), .Y(n2539) );
AOI222X1TS U1799 ( .A0(n2593), .A1(DMP[54]), .B0(n2516), .B1(intDX[54]),
.C0(intDY[54]), .C1(n2543), .Y(n2486) );
AOI222X1TS U1800 ( .A0(n2573), .A1(DMP[44]), .B0(n2524), .B1(intDX[44]),
.C0(intDY[44]), .C1(n2552), .Y(n2522) );
AOI222X1TS U1801 ( .A0(n2573), .A1(DMP[24]), .B0(n2524), .B1(intDX[24]),
.C0(intDY[24]), .C1(n2591), .Y(n2572) );
INVX2TS U1802 ( .A(n3457), .Y(n3455) );
OA21XLTS U1803 ( .A0(n3306), .A1(n3305), .B0(n3304), .Y(n3338) );
BUFX4TS U1804 ( .A(n2448), .Y(n2547) );
INVX2TS U1805 ( .A(n2449), .Y(n2472) );
CLKBUFX2TS U1806 ( .A(n3461), .Y(n3458) );
NAND2X1TS U1807 ( .A(n3329), .B(n3782), .Y(n3316) );
AND2X2TS U1808 ( .A(n1920), .B(n1927), .Y(n3461) );
CMPR32X2TS U1809 ( .A(n1884), .B(n1883), .C(n1882), .CO(n1906), .S(n3420) );
NAND2X1TS U1810 ( .A(n3412), .B(n2426), .Y(n2424) );
CLKBUFX2TS U1811 ( .A(n3520), .Y(n3511) );
INVX4TS U1812 ( .A(n2793), .Y(n3180) );
BUFX3TS U1813 ( .A(n1957), .Y(n2595) );
OR2X2TS U1814 ( .A(n3633), .B(n3624), .Y(n1615) );
BUFX3TS U1815 ( .A(n3530), .Y(n3633) );
NAND2X1TS U1816 ( .A(n1925), .B(n1924), .Y(n1940) );
AND2X2TS U1817 ( .A(n1927), .B(n1926), .Y(n3530) );
OAI2BB2XLTS U1818 ( .B0(n1709), .B1(n1708), .A0N(n1707), .A1N(n1706), .Y(
n1710) );
NAND3X1TS U1819 ( .A(n1750), .B(n1759), .C(n1692), .Y(n1767) );
AND2X2TS U1820 ( .A(n1962), .B(n1961), .Y(n1976) );
NAND2X2TS U1821 ( .A(n1671), .B(n1670), .Y(n1674) );
NOR2X1TS U1822 ( .A(n3189), .B(n2720), .Y(n2722) );
ADDFHX2TS U1823 ( .A(n1873), .B(n1872), .CI(n1871), .CO(n1874), .S(n3373) );
NAND2X1TS U1824 ( .A(n2995), .B(n2823), .Y(n2825) );
NAND2X1TS U1825 ( .A(n3190), .B(n2718), .Y(n2720) );
NAND2X1TS U1826 ( .A(n3041), .B(n2813), .Y(n2994) );
NAND2X1TS U1827 ( .A(n2850), .B(n2854), .Y(n2865) );
OAI21X1TS U1828 ( .A0(n3015), .A1(n3022), .B0(n3016), .Y(n2855) );
NOR2X1TS U1829 ( .A(n3100), .B(n3093), .Y(n2786) );
NOR2X1TS U1830 ( .A(n3260), .B(n3254), .Y(n2686) );
NOR2X1TS U1831 ( .A(n3085), .B(n3059), .Y(n3091) );
NOR2X1TS U1832 ( .A(n3194), .B(n3196), .Y(n2718) );
NOR2X1TS U1833 ( .A(n2729), .B(n3181), .Y(n3163) );
INVX2TS U1834 ( .A(n1616), .Y(n1963) );
NAND2X1TS U1835 ( .A(n2725), .B(n2724), .Y(n3177) );
AOI222X1TS U1836 ( .A0(intDX[4]), .A1(n3679), .B0(intDX[5]), .B1(n3712),
.C0(n1627), .C1(n1626), .Y(n1629) );
XOR2X1TS U1837 ( .A(n2690), .B(n2689), .Y(n2700) );
XOR2X1TS U1838 ( .A(n2731), .B(n2692), .Y(n2704) );
XOR2X1TS U1839 ( .A(n2742), .B(n2741), .Y(n2778) );
INVX4TS U1840 ( .A(n3403), .Y(n2882) );
NOR2BX1TS U1841 ( .AN(Sgf_normalized_result[9]), .B(n2743), .Y(n2692) );
NAND2X1TS U1842 ( .A(n1927), .B(n1847), .Y(n1918) );
NOR2X4TS U1843 ( .A(n3706), .B(FS_Module_state_reg[1]), .Y(n1927) );
OAI21XLTS U1844 ( .A0(intDY[23]), .A1(n3755), .B0(intDY[22]), .Y(n1665) );
NOR2XLTS U1845 ( .A(n1697), .B(intDX[56]), .Y(n1698) );
OAI21XLTS U1846 ( .A0(intDY[43]), .A1(n3746), .B0(intDY[42]), .Y(n1719) );
OAI21XLTS U1847 ( .A0(intDY[53]), .A1(n3759), .B0(intDY[52]), .Y(n1747) );
OAI211XLTS U1848 ( .A0(intDX[61]), .A1(n3704), .B0(n1705), .C0(n1704), .Y(
n1706) );
OAI21XLTS U1849 ( .A0(n3093), .A1(n3101), .B0(n3094), .Y(n2785) );
AOI21X1TS U1850 ( .A0(intDX[38]), .A1(n3711), .B0(n1742), .Y(n1741) );
OAI21XLTS U1851 ( .A0(n3143), .A1(n3140), .B0(n3144), .Y(n2763) );
NOR2XLTS U1852 ( .A(n1749), .B(n1748), .Y(n1762) );
NOR2XLTS U1853 ( .A(n2966), .B(n3770), .Y(n2733) );
OR2X1TS U1854 ( .A(FSM_selector_B[1]), .B(FSM_selector_B[0]), .Y(n1616) );
NOR2XLTS U1855 ( .A(n2696), .B(n3774), .Y(n2697) );
NAND2X2TS U1856 ( .A(n3320), .B(n3783), .Y(n1832) );
OAI21XLTS U1857 ( .A0(n3316), .A1(n3315), .B0(n3362), .Y(n3317) );
NOR2BX2TS U1858 ( .AN(n1769), .B(n1768), .Y(n2436) );
OR2X1TS U1859 ( .A(n3519), .B(n2110), .Y(n1947) );
INVX2TS U1860 ( .A(n2424), .Y(n2449) );
BUFX3TS U1861 ( .A(n1615), .Y(n2108) );
AOI31XLTS U1862 ( .A0(n3319), .A1(n3678), .A2(n1826), .B0(n1825), .Y(n1827)
);
OAI21XLTS U1863 ( .A0(n3155), .A1(n3154), .B0(n3153), .Y(n3160) );
NOR2XLTS U1864 ( .A(n2236), .B(n2343), .Y(n2237) );
NOR2XLTS U1865 ( .A(n2220), .B(n2256), .Y(n2218) );
INVX2TS U1866 ( .A(n3014), .Y(n3025) );
OAI21XLTS U1867 ( .A0(n3077), .A1(n3073), .B0(n3074), .Y(n3071) );
OAI21XLTS U1868 ( .A0(n3264), .A1(n3260), .B0(n3261), .Y(n3258) );
OAI2BB1X1TS U1869 ( .A0N(Add_Subt_result[3]), .A1N(n3635), .B0(n3625), .Y(
n3670) );
CLKINVX3TS U1870 ( .A(n1987), .Y(n2128) );
OAI211XLTS U1871 ( .A0(n2351), .A1(n1600), .B0(n1978), .C0(n1582), .Y(n1979)
);
OAI31X1TS U1872 ( .A0(n3520), .A1(n3519), .A2(n3518), .B0(n3517), .Y(n3523)
);
CLKINVX3TS U1873 ( .A(n3511), .Y(n2178) );
ADDFHX2TS U1874 ( .A(n1908), .B(n1907), .CI(n1906), .CO(n1903), .S(n3419) );
INVX2TS U1875 ( .A(n3458), .Y(n3445) );
CLKINVX3TS U1876 ( .A(n2523), .Y(n2480) );
OAI211XLTS U1877 ( .A0(n3467), .A1(n3469), .B0(n3380), .C0(n2107), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[53]) );
OAI211XLTS U1878 ( .A0(n3380), .A1(n2128), .B0(n2127), .C0(n2126), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[50]) );
OAI211XLTS U1879 ( .A0(n2607), .A1(n2343), .B0(n2320), .C0(n1583), .Y(n1474)
);
OAI21XLTS U1880 ( .A0(n3683), .A1(n1584), .B0(n2499), .Y(n1107) );
OAI21XLTS U1881 ( .A0(n3752), .A1(n2475), .B0(n2452), .Y(n1122) );
OAI21XLTS U1882 ( .A0(n3754), .A1(n2502), .B0(n1775), .Y(n1136) );
OAI21XLTS U1883 ( .A0(n3751), .A1(n2502), .B0(n2454), .Y(n1130) );
OAI211XLTS U1884 ( .A0(n2153), .A1(n3503), .B0(n2123), .C0(n2122), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[23]) );
OAI21XLTS U1885 ( .A0(n3761), .A1(n2511), .B0(n2510), .Y(n1155) );
OAI21XLTS U1886 ( .A0(n2223), .A1(n2256), .B0(n2222), .Y(n1466) );
OAI211XLTS U1887 ( .A0(n2601), .A1(n1600), .B0(n2298), .C0(n1583), .Y(n1485)
);
OAI211XLTS U1888 ( .A0(n2603), .A1(n2343), .B0(n2315), .C0(n1583), .Y(n1476)
);
OAI211XLTS U1889 ( .A0(n3520), .A1(n2117), .B0(n2116), .C0(n2115), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[24]) );
OAI21XLTS U1890 ( .A0(n2511), .A1(n3719), .B0(n2446), .Y(n1157) );
INVX2TS U1891 ( .A(n2550), .Y(n1584) );
AND4X2TS U1892 ( .A(n2432), .B(n2431), .C(n3328), .D(n3294), .Y(n2434) );
OAI21X1TS U1893 ( .A0(n3762), .A1(n2502), .B0(n2453), .Y(n1131) );
OAI21X1TS U1894 ( .A0(n2480), .A1(n3737), .B0(n2442), .Y(n1104) );
OAI21X1TS U1895 ( .A0(n3721), .A1(n2502), .B0(n2501), .Y(n1137) );
OAI21X1TS U1896 ( .A0(n2480), .A1(n3760), .B0(n2476), .Y(n1160) );
OAI21X1TS U1897 ( .A0(n3685), .A1(n2502), .B0(n2460), .Y(n1135) );
OAI21X1TS U1898 ( .A0(n2480), .A1(n3759), .B0(n2477), .Y(n1158) );
OAI21X1TS U1899 ( .A0(n3734), .A1(n2502), .B0(n1773), .Y(n1134) );
OAI21X1TS U1900 ( .A0(n3724), .A1(n2502), .B0(n2473), .Y(n1133) );
OAI21X1TS U1901 ( .A0(n2480), .A1(n3866), .B0(n2458), .Y(n1165) );
OAI21X1TS U1902 ( .A0(n3723), .A1(n2502), .B0(n2450), .Y(n1129) );
OAI21X1TS U1903 ( .A0(n3755), .A1(n2502), .B0(n2465), .Y(n1128) );
OAI21X1TS U1904 ( .A0(n2480), .A1(n3743), .B0(n2443), .Y(n1166) );
OAI21X1TS U1905 ( .A0(n3692), .A1(n2502), .B0(n2468), .Y(n1132) );
OAI21X1TS U1906 ( .A0(n2480), .A1(n3684), .B0(n2479), .Y(n1159) );
OAI21X1TS U1907 ( .A0(n2239), .A1(n2256), .B0(n2238), .Y(n1470) );
INVX4TS U1908 ( .A(n1772), .Y(n2529) );
AOI211X1TS U1909 ( .A0(n2302), .A1(Sgf_normalized_result[28]), .B0(n2237),
.C0(n1581), .Y(n2238) );
NAND4X1TS U1910 ( .A(n3500), .B(n3499), .C(n3498), .D(n3497), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[46]) );
OAI21X1TS U1911 ( .A0(n3347), .A1(n3333), .B0(n3332), .Y(n3334) );
NAND4X1TS U1912 ( .A(n3529), .B(n3528), .C(n3527), .D(n3526), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[18]) );
NAND4X1TS U1913 ( .A(n3536), .B(n3535), .C(n3534), .D(n3533), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[17]) );
NAND4X1TS U1914 ( .A(n3655), .B(n3654), .C(n3653), .D(n3652), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[1]) );
NAND4X1TS U1915 ( .A(n3541), .B(n3540), .C(n3539), .D(n3538), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[16]) );
OAI21X1TS U1916 ( .A0(n3347), .A1(n3786), .B0(n3346), .Y(n3348) );
NAND4X1TS U1917 ( .A(n3676), .B(n3675), .C(n3674), .D(n3673), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[0]) );
NAND4X1TS U1918 ( .A(n3547), .B(n3546), .C(n3545), .D(n3544), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[15]) );
NAND4X1TS U1919 ( .A(n3554), .B(n3553), .C(n3552), .D(n3551), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[14]) );
INVX4TS U1920 ( .A(n3118), .Y(n3129) );
NAND4X1TS U1921 ( .A(n3568), .B(n3567), .C(n3566), .D(n3565), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[12]) );
NAND4X1TS U1922 ( .A(n3576), .B(n3575), .C(n3574), .D(n3573), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[11]) );
NAND4X1TS U1923 ( .A(n3582), .B(n3581), .C(n3580), .D(n3579), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[10]) );
NAND4X1TS U1924 ( .A(n3589), .B(n3588), .C(n3587), .D(n3586), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[9]) );
NAND4X1TS U1925 ( .A(n3561), .B(n3560), .C(n3559), .D(n3558), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[13]) );
NAND4X1TS U1926 ( .A(n3602), .B(n3601), .C(n3600), .D(n3599), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[7]) );
NAND4X1TS U1927 ( .A(n3486), .B(n3485), .C(n3484), .D(n3483), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[47]) );
NAND4X1TS U1928 ( .A(n3595), .B(n3594), .C(n3593), .D(n3592), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[8]) );
OAI21X1TS U1929 ( .A0(n3299), .A1(n1822), .B0(n1799), .Y(n1800) );
NAND4X1TS U1930 ( .A(n3386), .B(n3385), .C(n3384), .D(n3383), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[49]) );
NAND4X1TS U1931 ( .A(n3609), .B(n3608), .C(n3607), .D(n3606), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[6]) );
OAI31XLTS U1932 ( .A0(n3511), .A1(n3519), .A2(n3510), .B0(n3509), .Y(n3515)
);
NAND4X1TS U1933 ( .A(n3508), .B(n3507), .C(n3506), .D(n3505), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[22]) );
NAND2X2TS U1934 ( .A(n3054), .B(n2790), .Y(n2792) );
INVX4TS U1935 ( .A(n2346), .Y(n1594) );
INVX4TS U1936 ( .A(n2346), .Y(n1593) );
NOR2X2TS U1937 ( .A(n2865), .B(n2876), .Y(n2879) );
AO22XLTS U1938 ( .A0(n3657), .A1(Add_Subt_result[1]), .B0(n3656), .B1(
Add_Subt_result[53]), .Y(n3668) );
INVX4TS U1939 ( .A(n3398), .Y(n2596) );
INVX2TS U1940 ( .A(n3455), .Y(n3456) );
NOR2X4TS U1941 ( .A(n1969), .B(n1968), .Y(n1970) );
BUFX8TS U1942 ( .A(n1853), .Y(n1889) );
AOI211X1TS U1943 ( .A0(intDX[16]), .A1(n3731), .B0(n1658), .C0(n1664), .Y(
n1653) );
NAND3X1TS U1944 ( .A(n1803), .B(n3780), .C(n3702), .Y(n1793) );
AOI2BB2X1TS U1945 ( .B0(intDY[53]), .B1(n3759), .A0N(intDX[52]), .A1N(n1747),
.Y(n1749) );
NOR2X1TS U1946 ( .A(Add_Subt_result[16]), .B(Add_Subt_result[22]), .Y(n1788)
);
INVX4TS U1947 ( .A(n3733), .Y(n2696) );
NOR2X1TS U1948 ( .A(Add_Subt_result[27]), .B(Add_Subt_result[33]), .Y(n1781)
);
NOR2X1TS U1949 ( .A(Add_Subt_result[26]), .B(Add_Subt_result[28]), .Y(n1780)
);
NOR2X1TS U1950 ( .A(Add_Subt_result[30]), .B(Add_Subt_result[29]), .Y(n1782)
);
INVX3TS U1951 ( .A(n3733), .Y(n2802) );
INVX3TS U1952 ( .A(n3733), .Y(n2925) );
NAND2BX1TS U1953 ( .AN(r_mode[0]), .B(sign_final_result), .Y(n1916) );
OAI21X1TS U1954 ( .A0(n1602), .A1(n3813), .B0(n2435), .Y(n1427) );
OAI21X1TS U1955 ( .A0(n3441), .A1(n3440), .B0(n3439), .Y(n3442) );
OAI211X2TS U1956 ( .A0(n1802), .A1(n3311), .B0(n1820), .C0(n1801), .Y(n3370)
);
OAI21X1TS U1957 ( .A0(n3740), .A1(n2511), .B0(n2498), .Y(n1152) );
OAI21X1TS U1958 ( .A0(n3713), .A1(n2515), .B0(n2493), .Y(n1112) );
CLKAND2X2TS U1959 ( .A(n3438), .B(n1820), .Y(n1836) );
OAI21X1TS U1960 ( .A0(n3757), .A1(n2515), .B0(n1841), .Y(n1108) );
OAI21X1TS U1961 ( .A0(n3763), .A1(n2475), .B0(n2451), .Y(n1123) );
OAI21X1TS U1962 ( .A0(n3716), .A1(n2475), .B0(n2444), .Y(n1121) );
OAI21X1TS U1963 ( .A0(n3718), .A1(n2515), .B0(n2496), .Y(n1109) );
OAI21X1TS U1964 ( .A0(n3745), .A1(n2511), .B0(n1770), .Y(n1150) );
OAI21X1TS U1965 ( .A0(n3736), .A1(n2475), .B0(n2474), .Y(n1125) );
OAI21X1TS U1966 ( .A0(n3681), .A1(n2515), .B0(n2495), .Y(n1110) );
OAI21X1TS U1967 ( .A0(n3717), .A1(n2515), .B0(n2491), .Y(n1111) );
OAI21X1TS U1968 ( .A0(n3695), .A1(n2511), .B0(n2492), .Y(n1153) );
OAI21X1TS U1969 ( .A0(n3735), .A1(n2475), .B0(n2463), .Y(n1126) );
OAI21X1TS U1970 ( .A0(n3748), .A1(n1584), .B0(n1840), .Y(n1138) );
OAI21X1TS U1971 ( .A0(n3747), .A1(n1584), .B0(n1839), .Y(n1140) );
OAI21X1TS U1972 ( .A0(n3741), .A1(n1584), .B0(n1776), .Y(n1146) );
OAI21X1TS U1973 ( .A0(n3701), .A1(n1584), .B0(n1843), .Y(n1139) );
OAI21X1TS U1974 ( .A0(n3699), .A1(n1584), .B0(n2489), .Y(n1106) );
OAI21X1TS U1975 ( .A0(n2480), .A1(n3726), .B0(n2459), .Y(n1161) );
OAI21X1TS U1976 ( .A0(n2480), .A1(n3868), .B0(n2456), .Y(n1162) );
OAI21X1TS U1977 ( .A0(n2480), .A1(n3867), .B0(n2457), .Y(n1163) );
OAI21X1TS U1978 ( .A0(n2480), .A1(n3697), .B0(n2447), .Y(n1164) );
OAI21X1TS U1979 ( .A0(n3758), .A1(n1584), .B0(n2482), .Y(n1105) );
OAI21XLTS U1980 ( .A0(Add_Subt_result[6]), .A1(Add_Subt_result[4]), .B0(
n3295), .Y(n3298) );
OAI21X1TS U1981 ( .A0(n2243), .A1(n2256), .B0(n2242), .Y(n1471) );
OAI21X1TS U1982 ( .A0(n2239), .A1(n2343), .B0(n2235), .Y(n1468) );
OAI21X1TS U1983 ( .A0(n2243), .A1(n2343), .B0(n2229), .Y(n1467) );
OAI211X1TS U1984 ( .A0(intDX[63]), .A1(n2440), .B0(n2439), .C0(n2640), .Y(
n2441) );
OAI21X2TS U1985 ( .A0(n1824), .A1(n3351), .B0(n3435), .Y(n1825) );
AOI211X1TS U1986 ( .A0(n2344), .A1(Sgf_normalized_result[24]), .B0(n2221),
.C0(n1586), .Y(n2222) );
OAI21X1TS U1987 ( .A0(n3084), .A1(n3085), .B0(n3086), .Y(n3063) );
AOI211X1TS U1988 ( .A0(n1576), .A1(Sgf_normalized_result[25]), .B0(n2228),
.C0(n1586), .Y(n2229) );
AOI211X1TS U1989 ( .A0(n2288), .A1(Sgf_normalized_result[30]), .B0(n2218),
.C0(n1581), .Y(n2219) );
AOI211X1TS U1990 ( .A0(n2288), .A1(Sgf_normalized_result[29]), .B0(n2241),
.C0(n1586), .Y(n2242) );
AOI211X1TS U1991 ( .A0(n2344), .A1(Sgf_normalized_result[26]), .B0(n2234),
.C0(n1586), .Y(n2235) );
OAI211X1TS U1992 ( .A0(n2145), .A1(n2178), .B0(n2144), .C0(n2143), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[44]) );
OAI222X1TS U1993 ( .A0(n3771), .A1(n1957), .B0(n1594), .B1(n2614), .C0(n2596), .C1(n2613), .Y(n1460) );
OAI222X1TS U1994 ( .A0(n2623), .A1(n1594), .B0(n2635), .B1(n2622), .C0(n2639), .C1(n1612), .Y(n1448) );
OAI222X1TS U1995 ( .A0(n3773), .A1(n2639), .B0(n1593), .B1(n2638), .C0(n2596), .C1(n2637), .Y(n1458) );
NOR2X1TS U1996 ( .A(n2236), .B(n2256), .Y(n2234) );
NOR2X1TS U1997 ( .A(n2240), .B(n2256), .Y(n2228) );
OAI21X1TS U1998 ( .A0(n2181), .A1(n2256), .B0(n2159), .Y(n1450) );
NOR2X1TS U1999 ( .A(n2220), .B(n1599), .Y(n2221) );
OAI211X1TS U2000 ( .A0(n2611), .A1(n2343), .B0(n2311), .C0(n1583), .Y(n1479)
);
OAI222X1TS U2001 ( .A0(n2620), .A1(n1594), .B0(n2635), .B1(n2619), .C0(n2639), .C1(n1614), .Y(n1446) );
OAI222X1TS U2002 ( .A0(n2632), .A1(n1594), .B0(n2635), .B1(n2631), .C0(n2639), .C1(n1617), .Y(n1445) );
OAI222X1TS U2003 ( .A0(n2636), .A1(n1594), .B0(n2635), .B1(n2634), .C0(n1957), .C1(n3765), .Y(n1443) );
OAI21X1TS U2004 ( .A0(n2247), .A1(n1593), .B0(n2188), .Y(n1457) );
OAI21X1TS U2005 ( .A0(n2260), .A1(n1593), .B0(n2212), .Y(n1456) );
OAI211X1TS U2006 ( .A0(n2181), .A1(n2343), .B0(n2180), .C0(n1583), .Y(n1488)
);
OAI21X1TS U2007 ( .A0(n2301), .A1(n2256), .B0(n2251), .Y(n1451) );
OAI211X1TS U2008 ( .A0(n2301), .A1(n1600), .B0(n2300), .C0(n1582), .Y(n1487)
);
OAI222X1TS U2009 ( .A0(n3776), .A1(n2639), .B0(n1593), .B1(n2602), .C0(n2635), .C1(n2601), .Y(n1453) );
OAI222X1TS U2010 ( .A0(n2626), .A1(n1594), .B0(n2635), .B1(n2625), .C0(n2639), .C1(n1618), .Y(n1447) );
OAI211X1TS U2011 ( .A0(n2626), .A1(n1592), .B0(n2202), .C0(n2201), .Y(n1491)
);
OAI211X1TS U2012 ( .A0(n1591), .A1(n2617), .B0(n2192), .C0(n2191), .Y(n1489)
);
OAI211X1TS U2013 ( .A0(n2306), .A1(n2343), .B0(n2305), .C0(n1583), .Y(n1486)
);
OAI222X1TS U2014 ( .A0(n3767), .A1(n2595), .B0(n1593), .B1(n2608), .C0(n2596), .C1(n2607), .Y(n1464) );
OAI211X1TS U2015 ( .A0(n3395), .A1(n1592), .B0(n2267), .C0(n2266), .Y(n1494)
);
OAI222X1TS U2016 ( .A0(n2629), .A1(n1594), .B0(n2635), .B1(n2628), .C0(n1957), .C1(n3766), .Y(n1442) );
OAI21X1TS U2017 ( .A0(n2306), .A1(n2256), .B0(n2255), .Y(n1452) );
OAI211X1TS U2018 ( .A0(n2623), .A1(n1592), .B0(n2207), .C0(n2206), .Y(n1490)
);
OAI211X1TS U2019 ( .A0(n2260), .A1(n1592), .B0(n2259), .C0(n2258), .Y(n1482)
);
OAI211X1TS U2020 ( .A0(n2636), .A1(n1592), .B0(n2290), .C0(n2289), .Y(n1495)
);
OAI211X1TS U2021 ( .A0(n2085), .A1(n2178), .B0(n2084), .C0(n2083), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[42]) );
NAND3BX1TS U2022 ( .AN(n3515), .B(n3514), .C(n3513), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[21]) );
OAI211X1TS U2023 ( .A0(n2597), .A1(n1600), .B0(n2165), .C0(n1582), .Y(n1483)
);
NAND3BX1TS U2024 ( .AN(n3523), .B(n3522), .C(n3521), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[20]) );
OAI21X1TS U2025 ( .A0(n3116), .A1(n2920), .B0(n2918), .Y(n2887) );
OAI211X1TS U2026 ( .A0(n2351), .A1(n2596), .B0(n2350), .C0(n2349), .Y(n1473)
);
OAI21X1TS U2027 ( .A0(n3116), .A1(n3112), .B0(n3113), .Y(n3110) );
OAI211X1TS U2028 ( .A0(n2599), .A1(n2343), .B0(n2172), .C0(n1583), .Y(n1484)
);
OAI21X1TS U2029 ( .A0(n3170), .A1(n3169), .B0(n3168), .Y(n3175) );
NOR2X6TS U2030 ( .A(n2924), .B(n2923), .Y(n2934) );
OAI211X1TS U2031 ( .A0(n2179), .A1(n2178), .B0(n2177), .C0(n2176), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[43]) );
NOR2BX2TS U2032 ( .AN(n1823), .B(n3423), .Y(n3368) );
INVX4TS U2033 ( .A(n2922), .Y(n3116) );
OAI21X1TS U2034 ( .A0(n3801), .A1(n2263), .B0(n2216), .Y(n2217) );
OAI21X1TS U2035 ( .A0(n3390), .A1(n3802), .B0(n2226), .Y(n2227) );
NAND3X1TS U2036 ( .A(n3380), .B(n3379), .C(n3378), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[51]) );
OAI211X1TS U2037 ( .A0(n3520), .A1(n2102), .B0(n2101), .C0(n2100), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[25]) );
NAND3X1TS U2038 ( .A(n3380), .B(n3377), .C(n3376), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[52]) );
OAI211X1TS U2039 ( .A0(n2136), .A1(n2132), .B0(n2131), .C0(n2130), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[26]) );
NOR2X4TS U2040 ( .A(n1812), .B(n1789), .Y(n3349) );
INVX3TS U2041 ( .A(n3487), .Y(n3646) );
INVX3TS U2042 ( .A(n3487), .Y(n3661) );
OAI211X1TS U2043 ( .A0(n3520), .A1(n2139), .B0(n2138), .C0(n2137), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[27]) );
OAI21X1TS U2044 ( .A0(n3244), .A1(n3240), .B0(n3241), .Y(n3238) );
AOI21X2TS U2045 ( .A0(n2880), .A1(n2879), .B0(n2878), .Y(n2918) );
INVX3TS U2046 ( .A(n2124), .Y(n3649) );
NAND2X2TS U2047 ( .A(n2866), .B(n2879), .Y(n2920) );
NAND2X6TS U2048 ( .A(n3331), .B(n1785), .Y(n1812) );
INVX3TS U2049 ( .A(n3466), .Y(n3583) );
INVX3TS U2050 ( .A(n2124), .Y(n3563) );
INVX3TS U2051 ( .A(n3466), .Y(n3667) );
INVX3TS U2052 ( .A(n2124), .Y(n3639) );
INVX3TS U2053 ( .A(n3466), .Y(n3637) );
INVX2TS U2054 ( .A(n2124), .Y(n3496) );
INVX3TS U2055 ( .A(n3469), .Y(n3669) );
AOI222X1TS U2056 ( .A0(n2129), .A1(n2121), .B0(n2099), .B1(n2128), .C0(n2067), .C1(n3374), .Y(n2075) );
AND2X2TS U2057 ( .A(n2105), .B(n2104), .Y(n3482) );
OAI21X1TS U2058 ( .A0(n3056), .A1(n2788), .B0(n2787), .Y(n2789) );
INVX3TS U2059 ( .A(n3475), .Y(n3651) );
INVX3TS U2060 ( .A(n3475), .Y(n3671) );
INVX3TS U2061 ( .A(n3475), .Y(n3641) );
NOR2X1TS U2062 ( .A(n3283), .B(n3282), .Y(n3288) );
INVX2TS U2063 ( .A(n3475), .Y(n3572) );
AO22XLTS U2064 ( .A0(n3556), .A1(Add_Subt_result[0]), .B0(
Add_Subt_result[54]), .B1(n3656), .Y(n3658) );
OAI21X1TS U2065 ( .A0(n2292), .A1(n3803), .B0(n2291), .Y(n2160) );
OAI21X1TS U2066 ( .A0(n2292), .A1(n3805), .B0(n2291), .Y(n2166) );
NAND2X6TS U2067 ( .A(n3434), .B(n3690), .Y(n3343) );
OAI21X1TS U2068 ( .A0(n2292), .A1(n3801), .B0(n2291), .Y(n2158) );
AND2X2TS U2069 ( .A(n2054), .B(n2178), .Y(n2082) );
OAI21X2TS U2070 ( .A0(n3119), .A1(n3126), .B0(n3120), .Y(n3065) );
OAI21X1TS U2071 ( .A0(n3196), .A1(n3202), .B0(n3197), .Y(n2717) );
NAND3X1TS U2072 ( .A(n3416), .B(n3415), .C(n3414), .Y(n1561) );
OAI21X1TS U2073 ( .A0(n3254), .A1(n3261), .B0(n3255), .Y(n2685) );
INVX2TS U2074 ( .A(n3177), .Y(n3178) );
INVX3TS U2075 ( .A(n2595), .Y(n2288) );
XOR2X1TS U2076 ( .A(n2882), .B(n2828), .Y(n2831) );
OAI21X1TS U2077 ( .A0(n1726), .A1(n1725), .B0(n1724), .Y(n1728) );
AND2X2TS U2078 ( .A(n3519), .B(n2112), .Y(n2043) );
INVX2TS U2079 ( .A(n2546), .Y(n2589) );
INVX4TS U2080 ( .A(n3403), .Y(n2969) );
AND2X2TS U2081 ( .A(n1959), .B(n1958), .Y(n1968) );
INVX3TS U2082 ( .A(n2546), .Y(n2585) );
INVX3TS U2083 ( .A(n2546), .Y(n2593) );
INVX3TS U2084 ( .A(n2546), .Y(n2573) );
INVX3TS U2085 ( .A(n2546), .Y(n2579) );
NAND2BX1TS U2086 ( .AN(ack_FSM), .B(ready), .Y(n2645) );
INVX2TS U2087 ( .A(n3166), .Y(n3232) );
NAND2BX1TS U2088 ( .AN(n3411), .B(n3410), .Y(n1986) );
INVX2TS U2089 ( .A(n3166), .Y(n3265) );
INVX2TS U2090 ( .A(n3166), .Y(n3020) );
INVX3TS U2091 ( .A(n3166), .Y(n3098) );
CLKAND2X2TS U2092 ( .A(n3426), .B(n1808), .Y(n1779) );
INVX3TS U2093 ( .A(n2962), .Y(n1886) );
NOR2X1TS U2094 ( .A(n2696), .B(n1618), .Y(n2675) );
NAND2XLTS U2095 ( .A(n3412), .B(FS_Module_state_reg[0]), .Y(n1911) );
NAND3XLTS U2096 ( .A(n3313), .B(n3312), .C(n3792), .Y(n3315) );
NAND2BX1TS U2097 ( .AN(Sgf_normalized_result[54]), .B(n2966), .Y(n3399) );
NOR2X1TS U2098 ( .A(n2696), .B(n3776), .Y(n2694) );
OAI211X1TS U2099 ( .A0(n3748), .A1(intDY[33]), .B0(n1695), .C0(n1736), .Y(
n1696) );
OAI211X2TS U2100 ( .A0(intDY[28]), .A1(n3724), .B0(n1687), .C0(n1672), .Y(
n1681) );
NOR2X1TS U2101 ( .A(n2966), .B(n3775), .Y(n2695) );
NAND3X1TS U2102 ( .A(n3866), .B(n1703), .C(intDY[60]), .Y(n1704) );
NOR2X1TS U2103 ( .A(n2696), .B(n1619), .Y(n2689) );
AOI211X2TS U2104 ( .A0(intDX[52]), .A1(n3710), .B0(n1690), .C0(n1748), .Y(
n1750) );
OAI211X2TS U2105 ( .A0(intDY[20]), .A1(n3736), .B0(n1669), .C0(n1652), .Y(
n1663) );
INVX3TS U2106 ( .A(n3733), .Y(n2967) );
NAND2BX1TS U2107 ( .AN(intDY[51]), .B(intDX[51]), .Y(n1753) );
NAND2BX1TS U2108 ( .AN(intDY[59]), .B(intDX[59]), .Y(n1699) );
NAND2BX1TS U2109 ( .AN(intDY[62]), .B(intDX[62]), .Y(n1707) );
NOR2X1TS U2110 ( .A(n3759), .B(intDY[53]), .Y(n1690) );
NAND2BX1TS U2111 ( .AN(intDY[47]), .B(intDX[47]), .Y(n1715) );
NAND2BX1TS U2112 ( .AN(intDY[40]), .B(intDX[40]), .Y(n1693) );
NAND2BX1TS U2113 ( .AN(intDY[41]), .B(intDX[41]), .Y(n1694) );
OAI21X1TS U2114 ( .A0(intDY[55]), .A1(n3760), .B0(intDY[54]), .Y(n1758) );
NAND2BX1TS U2115 ( .AN(intDX[62]), .B(intDY[62]), .Y(n1705) );
NAND2BX1TS U2116 ( .AN(intDY[32]), .B(intDX[32]), .Y(n1695) );
NAND2BX1TS U2117 ( .AN(intDY[27]), .B(intDX[27]), .Y(n1678) );
NAND2BX1TS U2118 ( .AN(intDY[29]), .B(intDX[29]), .Y(n1672) );
OAI21X1TS U2119 ( .A0(intDY[31]), .A1(n3754), .B0(intDY[30]), .Y(n1683) );
NAND2BX1TS U2120 ( .AN(intDY[19]), .B(intDX[19]), .Y(n1660) );
NAND2BX1TS U2121 ( .AN(intDY[21]), .B(intDX[21]), .Y(n1652) );
INVX3TS U2122 ( .A(n3733), .Y(n2743) );
AO21X2TS U2123 ( .A0(n1974), .A1(underflow_flag), .B0(n1910), .Y(n1426) );
INVX4TS U2124 ( .A(n1584), .Y(n1585) );
NOR4BX2TS U2125 ( .AN(n1898), .B(n2431), .C(n3328), .D(n3294), .Y(n1909) );
INVX4TS U2126 ( .A(n3403), .Y(n2841) );
AOI21X2TS U2127 ( .A0(n3180), .A1(n3054), .B0(n3053), .Y(n3118) );
OAI21X1TS U2128 ( .A0(n3390), .A1(n3804), .B0(n2232), .Y(n2233) );
NAND2X2TS U2129 ( .A(n3361), .B(n3359), .Y(n3340) );
NOR2X2TS U2130 ( .A(Add_Subt_result[54]), .B(Add_Subt_result[53]), .Y(n3359)
);
OAI2BB1X2TS U2131 ( .A0N(n1836), .A1N(n1835), .B0(n3439), .Y(n1837) );
AOI21X2TS U2132 ( .A0(n2855), .A1(n2854), .B0(n2853), .Y(n2877) );
AOI22X4TS U2133 ( .A0(n1902), .A1(n1888), .B0(n1899), .B1(n1900), .Y(n1891)
);
OAI21X2TS U2134 ( .A0(n3402), .A1(n3401), .B0(n3400), .Y(n3404) );
NOR2X8TS U2135 ( .A(n3343), .B(Add_Subt_result[34]), .Y(n3331) );
AOI21X4TS U2136 ( .A0(n3129), .A1(n3058), .B0(n3057), .Y(n3084) );
NOR2XLTS U2137 ( .A(n1920), .B(FS_Module_state_reg[2]), .Y(n1851) );
MX2X1TS U2138 ( .A(DMP[60]), .B(exp_oper_result[8]), .S0(n1886), .Y(n1907)
);
CLKAND2X2TS U2139 ( .A(n1963), .B(DmP[60]), .Y(n1881) );
NAND2BXLTS U2140 ( .AN(intDY[13]), .B(intDX[13]), .Y(n1632) );
AOI211X2TS U2141 ( .A0(intDX[44]), .A1(n3708), .B0(n1716), .C0(n1725), .Y(
n1723) );
MX2X1TS U2142 ( .A(DMP[45]), .B(Sgf_normalized_result[47]), .S0(n1886), .Y(
n2883) );
OAI211X1TS U2143 ( .A0(n1606), .A1(n2604), .B0(n2265), .C0(n2264), .Y(n3397)
);
MX2X1TS U2144 ( .A(DMP[54]), .B(exp_oper_result[2]), .S0(n2796), .Y(n1875)
);
MX2X1TS U2145 ( .A(DMP[61]), .B(exp_oper_result[9]), .S0(n2796), .Y(n1904)
);
CLKAND2X2TS U2146 ( .A(n1960), .B(DmP[61]), .Y(n1880) );
MX2X1TS U2147 ( .A(DMP[57]), .B(exp_oper_result[5]), .S0(n1588), .Y(n1896)
);
NAND4XLTS U2148 ( .A(n3322), .B(n1814), .C(n1813), .D(n3301), .Y(n1815) );
AOI31XLTS U2149 ( .A0(n3335), .A1(Add_Subt_result[11]), .A2(n3800), .B0(
n3334), .Y(n3337) );
NOR2BX1TS U2150 ( .AN(n1634), .B(n1633), .Y(n1635) );
OAI211XLTS U2151 ( .A0(intDY[8]), .A1(n3764), .B0(n1640), .C0(n1643), .Y(
n1633) );
INVX2TS U2152 ( .A(n1645), .Y(n1634) );
AOI21X1TS U2153 ( .A0(n1642), .A1(n1641), .B0(n1645), .Y(n1644) );
NOR2XLTS U2154 ( .A(n1638), .B(intDX[10]), .Y(n1639) );
AOI211X1TS U2155 ( .A0(n1687), .A1(n1686), .B0(n1685), .C0(n1684), .Y(n1688)
);
OAI2BB2XLTS U2156 ( .B0(intDX[30]), .B1(n1683), .A0N(intDY[31]), .A1N(n3754),
.Y(n1684) );
OAI2BB2XLTS U2157 ( .B0(intDX[28]), .B1(n1675), .A0N(intDY[29]), .A1N(n3734),
.Y(n1686) );
OA21XLTS U2158 ( .A0(n1702), .A1(n1701), .B0(n1700), .Y(n1708) );
NOR2XLTS U2159 ( .A(n1716), .B(intDX[44]), .Y(n1717) );
INVX2TS U2160 ( .A(n1732), .Y(n1738) );
OAI21XLTS U2161 ( .A0(intDX[37]), .A1(n1611), .B0(n1731), .Y(n1740) );
NAND3XLTS U2162 ( .A(n3749), .B(n1730), .C(intDY[36]), .Y(n1731) );
NOR2BX1TS U2163 ( .AN(intDX[39]), .B(intDY[39]), .Y(n1742) );
NAND2X1TS U2164 ( .A(n1862), .B(n1861), .Y(n1932) );
CLKINVX6TS U2165 ( .A(n3403), .Y(n2731) );
MX2X1TS U2166 ( .A(DMP[40]), .B(Sgf_normalized_result[42]), .S0(n1587), .Y(
n2843) );
MX2X1TS U2167 ( .A(DMP[13]), .B(Sgf_normalized_result[15]), .S0(n1587), .Y(
n2724) );
MX2X1TS U2168 ( .A(DMP[1]), .B(Sgf_normalized_result[3]), .S0(n2967), .Y(
n2677) );
MX2X1TS U2169 ( .A(DMP[27]), .B(Sgf_normalized_result[29]), .S0(
FSM_selector_D), .Y(n2781) );
MX2X1TS U2170 ( .A(DMP[28]), .B(Sgf_normalized_result[30]), .S0(
FSM_selector_D), .Y(n2783) );
MX2X1TS U2171 ( .A(DMP[39]), .B(Sgf_normalized_result[41]), .S0(n2958), .Y(
n2837) );
MX2X1TS U2172 ( .A(DMP[6]), .B(Sgf_normalized_result[8]), .S0(FSM_selector_D), .Y(n2701) );
MX2X1TS U2173 ( .A(DMP[32]), .B(Sgf_normalized_result[34]), .S0(n2796), .Y(
n2810) );
MX2X1TS U2174 ( .A(DMP[29]), .B(Sgf_normalized_result[31]), .S0(n1588), .Y(
n2804) );
MX2X1TS U2175 ( .A(DMP[26]), .B(Sgf_normalized_result[28]), .S0(n2796), .Y(
n2779) );
MX2X1TS U2176 ( .A(DMP[62]), .B(exp_oper_result[10]), .S0(n2842), .Y(n1899)
);
CLKAND2X2TS U2177 ( .A(n1963), .B(DmP[62]), .Y(n1885) );
MX2X1TS U2178 ( .A(DMP[7]), .B(Sgf_normalized_result[9]), .S0(n1587), .Y(
n2703) );
MX2X1TS U2179 ( .A(DMP[31]), .B(Sgf_normalized_result[33]), .S0(n1587), .Y(
n2808) );
MX2X1TS U2180 ( .A(DMP[8]), .B(Sgf_normalized_result[10]), .S0(
FSM_selector_D), .Y(n2705) );
MX2X1TS U2181 ( .A(DMP[4]), .B(Sgf_normalized_result[6]), .S0(FSM_selector_D), .Y(n2683) );
MX2X1TS U2182 ( .A(DMP[22]), .B(Sgf_normalized_result[24]), .S0(n1587), .Y(
n2769) );
MX2X1TS U2183 ( .A(DMP[2]), .B(Sgf_normalized_result[4]), .S0(n1587), .Y(
n2679) );
MX2X1TS U2184 ( .A(DMP[0]), .B(Sgf_normalized_result[2]), .S0(n2967), .Y(
n2669) );
MX2X1TS U2185 ( .A(DMP[38]), .B(Sgf_normalized_result[40]), .S0(n2842), .Y(
n2832) );
MX2X1TS U2186 ( .A(DMP[36]), .B(Sgf_normalized_result[38]), .S0(n1588), .Y(
n2820) );
INVX2TS U2187 ( .A(n2280), .Y(n2292) );
NAND2X4TS U2188 ( .A(n3356), .B(n1779), .Y(n1796) );
NAND2X4TS U2189 ( .A(n3295), .B(n3784), .Y(n3306) );
MX2X1TS U2190 ( .A(DMP[41]), .B(Sgf_normalized_result[43]), .S0(n1587), .Y(
n2857) );
MX2X1TS U2191 ( .A(DMP[43]), .B(Sgf_normalized_result[45]), .S0(n1588), .Y(
n2869) );
MX2X1TS U2192 ( .A(DMP[44]), .B(Sgf_normalized_result[46]), .S0(n1588), .Y(
n2871) );
MX2X1TS U2193 ( .A(DMP[46]), .B(Sgf_normalized_result[48]), .S0(n2796), .Y(
n2927) );
NAND3X2TS U2194 ( .A(n1819), .B(n1795), .C(Add_Subt_result[0]), .Y(n1820) );
AOI222X1TS U2195 ( .A0(n3532), .A1(n1597), .B0(n1603), .B1(n2120), .C0(n3525), .C1(n2119), .Y(n2153) );
AND3X1TS U2196 ( .A(n2047), .B(n2046), .C(n2045), .Y(n2145) );
BUFX3TS U2197 ( .A(n2547), .Y(n2505) );
INVX2TS U2198 ( .A(n2550), .Y(n2475) );
INVX2TS U2199 ( .A(n2550), .Y(n2515) );
BUFX3TS U2200 ( .A(n2547), .Y(n2513) );
OAI21XLTS U2201 ( .A0(n3390), .A1(n3803), .B0(n2224), .Y(n2225) );
OAI21XLTS U2202 ( .A0(n3798), .A1(n3390), .B0(n2213), .Y(n2214) );
AND3X1TS U2203 ( .A(n1990), .B(n1989), .C(n1988), .Y(n2085) );
MX2X1TS U2204 ( .A(DMP[53]), .B(exp_oper_result[1]), .S0(n2796), .Y(n1872)
);
AOI21X1TS U2205 ( .A0(n3092), .A1(n3091), .B0(n3090), .Y(n3104) );
OAI221X1TS U2206 ( .A0(n1767), .A1(n1766), .B0(n1765), .B1(n1764), .C0(n1763), .Y(n1768) );
INVX2TS U2207 ( .A(n1714), .Y(n1769) );
AND3X1TS U2208 ( .A(n2170), .B(n2169), .C(n2168), .Y(n2599) );
AND3X1TS U2209 ( .A(n2163), .B(n2162), .C(n2161), .Y(n2597) );
INVX2TS U2210 ( .A(n3623), .Y(n3487) );
CLKAND2X2TS U2211 ( .A(n2967), .B(Sgf_normalized_result[0]), .Y(n2667) );
OR2X1TS U2212 ( .A(n2964), .B(n2963), .Y(n2973) );
OAI211X1TS U2213 ( .A0(n1607), .A1(n2617), .B0(n2187), .C0(n2186), .Y(n2244)
);
CLKAND2X2TS U2214 ( .A(n1970), .B(
Barrel_Shifter_module_Mux_Array_Data_array[94]), .Y(n2345) );
MX2X1TS U2215 ( .A(DMP[56]), .B(exp_oper_result[4]), .S0(n1588), .Y(n1893)
);
MX2X1TS U2216 ( .A(DMP[59]), .B(exp_oper_result[7]), .S0(FSM_selector_D),
.Y(n1883) );
CLKAND2X2TS U2217 ( .A(n1960), .B(DmP[59]), .Y(n1864) );
CLKAND2X2TS U2218 ( .A(n2967), .B(Sgf_normalized_result[1]), .Y(n2663) );
INVX2TS U2219 ( .A(n2550), .Y(n2511) );
BUFX3TS U2220 ( .A(n2448), .Y(n2516) );
AO22XLTS U2221 ( .A0(n1970), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[104]), .B0(n2280), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[96]), .Y(n2281) );
AO22XLTS U2222 ( .A0(n1970), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[105]), .B0(n2280), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[97]), .Y(n2261) );
AO22XLTS U2223 ( .A0(n1970), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[106]), .B0(n2280), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[98]), .Y(n2273) );
AO22XLTS U2224 ( .A0(n1970), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[107]), .B0(n2280), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[99]), .Y(n2193) );
AO22XLTS U2225 ( .A0(n1970), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[108]), .B0(n2280), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[100]), .Y(n2198) );
AO22XLTS U2226 ( .A0(n2262), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[93]), .B0(n2280), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[101]), .Y(n2203) );
OAI211X1TS U2227 ( .A0(n1607), .A1(n2623), .B0(n2339), .C0(n2338), .Y(n2340)
);
OAI211X1TS U2228 ( .A0(n1605), .A1(n2602), .B0(n2295), .C0(n2294), .Y(n2296)
);
INVX2TS U2229 ( .A(n3473), .Y(n3648) );
OAI211XLTS U2230 ( .A0(Add_Subt_result[54]), .A1(n3431), .B0(n3430), .C0(
n3429), .Y(n3432) );
NAND3XLTS U2231 ( .A(n3428), .B(Add_Subt_result[45]), .C(n3715), .Y(n3429)
);
NAND4XLTS U2232 ( .A(n3427), .B(n3426), .C(Add_Subt_result[37]), .D(n3807),
.Y(n3430) );
NAND3XLTS U2233 ( .A(n1803), .B(Add_Subt_result[30]), .C(n3702), .Y(n1804)
);
OAI21XLTS U2234 ( .A0(n3311), .A1(n3787), .B0(n3310), .Y(n3323) );
NAND3XLTS U2235 ( .A(n3428), .B(n3810), .C(n3307), .Y(n3308) );
NAND4XLTS U2236 ( .A(n1823), .B(n1788), .C(n1787), .D(n1786), .Y(n1789) );
AOI2BB2XLTS U2237 ( .B0(r_mode[1]), .B1(r_mode[0]), .A0N(
Sgf_normalized_result[1]), .A1N(Sgf_normalized_result[0]), .Y(n1915)
);
OR2X1TS U2238 ( .A(n2955), .B(n2954), .Y(n2978) );
XNOR2X1TS U2239 ( .A(n2969), .B(n2968), .Y(n3400) );
NOR2X2TS U2240 ( .A(FS_Module_state_reg[3]), .B(FS_Module_state_reg[0]), .Y(
n2426) );
CLKAND2X2TS U2241 ( .A(n1920), .B(n1848), .Y(n3410) );
NOR2XLTS U2242 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[1]), .Y(
n1848) );
NAND4XLTS U2243 ( .A(n2375), .B(n2374), .C(n2373), .D(n2372), .Y(n2422) );
NAND4XLTS U2244 ( .A(n2383), .B(n2382), .C(n2381), .D(n2380), .Y(n2421) );
NAND4XLTS U2245 ( .A(n2367), .B(n2366), .C(n2365), .D(n2364), .Y(n2423) );
AND3X1TS U2246 ( .A(n2175), .B(n2174), .C(n2173), .Y(n2176) );
MX2X1TS U2247 ( .A(Add_Subt_result[12]), .B(n3220), .S0(n3232), .Y(n1515) );
MX2X1TS U2248 ( .A(Add_Subt_result[35]), .B(n3040), .S0(n3020), .Y(n1538) );
MX2X1TS U2249 ( .A(Add_Subt_result[14]), .B(n3201), .S0(n3232), .Y(n1517) );
NAND2BXLTS U2250 ( .AN(intDY[2]), .B(intDX[2]), .Y(n1624) );
NAND2BXLTS U2251 ( .AN(intDY[9]), .B(intDX[9]), .Y(n1640) );
NAND3XLTS U2252 ( .A(n3764), .B(n1640), .C(intDY[8]), .Y(n1642) );
NAND2BXLTS U2253 ( .AN(intDX[9]), .B(intDY[9]), .Y(n1641) );
NOR2XLTS U2254 ( .A(n1658), .B(intDX[16]), .Y(n1659) );
NOR2BX1TS U2255 ( .AN(n1653), .B(n1663), .Y(n1654) );
NAND2BX2TS U2256 ( .AN(n1636), .B(n1635), .Y(n1656) );
NOR2XLTS U2257 ( .A(n1676), .B(intDX[24]), .Y(n1677) );
NOR2BX1TS U2258 ( .AN(n3677), .B(n1912), .Y(n1849) );
NOR2XLTS U2259 ( .A(n1751), .B(intDX[48]), .Y(n1752) );
NOR2X1TS U2260 ( .A(n3045), .B(n3047), .Y(n2813) );
NOR2X1TS U2261 ( .A(n3073), .B(n3067), .Y(n2776) );
INVX2TS U2262 ( .A(n2962), .Y(n2958) );
NOR2X1TS U2263 ( .A(n3141), .B(n3143), .Y(n2764) );
NOR2X1TS U2264 ( .A(n3169), .B(n3171), .Y(n2754) );
NOR2X1TS U2265 ( .A(n2999), .B(n3001), .Y(n2823) );
NOR2X1TS U2266 ( .A(n2849), .B(n2852), .Y(n2854) );
NAND2X1TS U2267 ( .A(n3091), .B(n2786), .Y(n2788) );
MX2X1TS U2268 ( .A(DmP[25]), .B(Add_Subt_result[27]), .S0(FSM_selector_C),
.Y(n2111) );
MX2X1TS U2269 ( .A(DMP[52]), .B(exp_oper_result[0]), .S0(n1587), .Y(n1878)
);
XOR2X1TS U2270 ( .A(n1604), .B(n1863), .Y(n1877) );
AO21XLTS U2271 ( .A0(DmP[52]), .A1(n3727), .B0(n1932), .Y(n1863) );
OAI2BB1X2TS U2272 ( .A0N(n1713), .A1N(n1712), .B0(n1711), .Y(n1714) );
INVX2TS U2273 ( .A(n1710), .Y(n1711) );
NAND2X1TS U2274 ( .A(n1689), .B(n1688), .Y(n1713) );
OAI2BB1X1TS U2275 ( .A0N(n1741), .A1N(n1740), .B0(n1739), .Y(n1746) );
NAND4X1TS U2276 ( .A(n1723), .B(n1721), .C(n1694), .D(n1693), .Y(n1765) );
NAND2X1TS U2277 ( .A(n3221), .B(n2708), .Y(n3189) );
MX2X1TS U2278 ( .A(DMP[10]), .B(Sgf_normalized_result[12]), .S0(n2958), .Y(
n2711) );
MX2X1TS U2279 ( .A(DMP[33]), .B(Sgf_normalized_result[35]), .S0(n2958), .Y(
n2814) );
MX2X1TS U2280 ( .A(DMP[51]), .B(Sgf_normalized_result[53]), .S0(n1588), .Y(
n2963) );
MX2X1TS U2281 ( .A(DMP[24]), .B(Sgf_normalized_result[26]), .S0(n1587), .Y(
n2773) );
MX2X1TS U2282 ( .A(DMP[12]), .B(Sgf_normalized_result[14]), .S0(n2796), .Y(
n2715) );
NAND2X1TS U2283 ( .A(n3163), .B(n2754), .Y(n3131) );
NOR2X1TS U2284 ( .A(n3027), .B(n3030), .Y(n2995) );
BUFX3TS U2285 ( .A(n3677), .Y(n3624) );
INVX2TS U2286 ( .A(n1803), .Y(n1798) );
INVX2TS U2287 ( .A(n3425), .Y(n3427) );
OAI21XLTS U2288 ( .A0(Add_Subt_result[24]), .A1(n3791), .B0(n3691), .Y(n3313) );
CLKAND2X2TS U2289 ( .A(n3428), .B(n3296), .Y(n3314) );
NOR2X2TS U2290 ( .A(n1832), .B(n1791), .Y(n3295) );
NOR2X1TS U2291 ( .A(n2862), .B(n2911), .Y(n2889) );
NOR2X1TS U2292 ( .A(n2894), .B(n2896), .Y(n2874) );
NAND2X1TS U2293 ( .A(n2889), .B(n2874), .Y(n2876) );
MX2X1TS U2294 ( .A(DMP[47]), .B(Sgf_normalized_result[49]), .S0(n1588), .Y(
n2936) );
MX2X1TS U2295 ( .A(DMP[48]), .B(Sgf_normalized_result[50]), .S0(n1588), .Y(
n2945) );
MX2X1TS U2296 ( .A(DMP[49]), .B(Sgf_normalized_result[51]), .S0(
FSM_selector_D), .Y(n2954) );
MX2X1TS U2297 ( .A(DMP[50]), .B(Sgf_normalized_result[52]), .S0(n1588), .Y(
n2959) );
NAND4XLTS U2298 ( .A(n2419), .B(n2418), .C(n2417), .D(n2416), .Y(n2420) );
OAI211XLTS U2299 ( .A0(n1832), .A1(n3678), .B0(n1831), .C0(n3336), .Y(n1833)
);
AOI2BB2XLTS U2300 ( .B0(n3335), .B1(Add_Subt_result[10]), .A0N(n3423), .A1N(
n1830), .Y(n1831) );
AND3X1TS U2301 ( .A(n2017), .B(n2016), .C(n2015), .Y(n2179) );
OAI211X1TS U2302 ( .A0(n1605), .A1(n2600), .B0(n2253), .C0(n2252), .Y(n2254)
);
OAI211X1TS U2303 ( .A0(n1607), .A1(n2598), .B0(n2249), .C0(n2248), .Y(n2250)
);
OAI211X1TS U2304 ( .A0(n1605), .A1(n2211), .B0(n2210), .C0(n2209), .Y(n2257)
);
AND3X1TS U2305 ( .A(n2061), .B(n2060), .C(n2059), .Y(n2070) );
AND3X1TS U2306 ( .A(n2053), .B(n2052), .C(n2051), .Y(n2065) );
AND3X1TS U2307 ( .A(n2000), .B(n1999), .C(n1998), .Y(n2042) );
AND3X1TS U2308 ( .A(n2022), .B(n2021), .C(n2020), .Y(n2038) );
AND3X1TS U2309 ( .A(n2004), .B(n2003), .C(n2002), .Y(n2019) );
AND3X1TS U2310 ( .A(n2013), .B(n2012), .C(n2011), .Y(n2032) );
CLKAND2X2TS U2311 ( .A(n2429), .B(n1602), .Y(n3444) );
ADDFHX2TS U2312 ( .A(n1870), .B(n1869), .CI(n1868), .CO(n1892), .S(n3327) );
MX2X1TS U2313 ( .A(DMP[55]), .B(exp_oper_result[3]), .S0(FSM_selector_D),
.Y(n1869) );
OAI211X1TS U2314 ( .A0(n2260), .A1(n1606), .B0(n2156), .C0(n2155), .Y(n2157)
);
ADDFHX2TS U2315 ( .A(n1867), .B(n1866), .CI(n1865), .CO(n1882), .S(n3422) );
MX2X1TS U2316 ( .A(DMP[58]), .B(exp_oper_result[6]), .S0(n2842), .Y(n1866)
);
CLKAND2X2TS U2317 ( .A(n1963), .B(DmP[58]), .Y(n1854) );
INVX2TS U2318 ( .A(n1889), .Y(n1890) );
NAND2BXLTS U2319 ( .AN(n1900), .B(n1887), .Y(n1888) );
BUFX3TS U2320 ( .A(n2547), .Y(n2578) );
BUFX3TS U2321 ( .A(n2547), .Y(n2592) );
BUFX3TS U2322 ( .A(n2529), .Y(n2591) );
BUFX3TS U2323 ( .A(n2547), .Y(n2553) );
BUFX3TS U2324 ( .A(n2529), .Y(n2552) );
BUFX3TS U2325 ( .A(n2547), .Y(n2588) );
BUFX3TS U2326 ( .A(n2550), .Y(n2587) );
OAI211X1TS U2327 ( .A0(n1605), .A1(n2610), .B0(n2287), .C0(n2286), .Y(n2633)
);
OAI211X1TS U2328 ( .A0(n1607), .A1(n2606), .B0(n2275), .C0(n2274), .Y(n2630)
);
OAI211X1TS U2329 ( .A0(n1606), .A1(n2614), .B0(n2195), .C0(n2194), .Y(n2618)
);
OAI211X1TS U2330 ( .A0(n1607), .A1(n2612), .B0(n2200), .C0(n2199), .Y(n2624)
);
OAI211X1TS U2331 ( .A0(n2247), .A1(n1606), .B0(n2190), .C0(n2189), .Y(n2615)
);
AO22XLTS U2332 ( .A0(n2262), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[87]), .B0(n2280), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[95]), .Y(n2268) );
OAI211XLTS U2333 ( .A0(n3364), .A1(n3426), .B0(n3363), .C0(n3362), .Y(n3365)
);
INVX2TS U2334 ( .A(n3356), .Y(n3364) );
OAI2BB1X1TS U2335 ( .A0N(LZA_output[5]), .A1N(n3443), .B0(n1837), .Y(n1496)
);
NOR3BXLTS U2336 ( .AN(n1834), .B(n3371), .C(n1833), .Y(n1835) );
AO22XLTS U2337 ( .A0(n3564), .A1(n3659), .B0(n3512), .B1(n3572), .Y(n2150)
);
AND3X1TS U2338 ( .A(n2142), .B(n2141), .C(n2140), .Y(n2143) );
MX2X1TS U2339 ( .A(Add_Subt_result[17]), .B(n3167), .S0(n3405), .Y(n1520) );
MX2X1TS U2340 ( .A(Add_Subt_result[29]), .B(n3105), .S0(n3265), .Y(n1532) );
MX2X1TS U2341 ( .A(Add_Subt_result[19]), .B(n3152), .S0(n3020), .Y(n1522) );
MX2X1TS U2342 ( .A(intDY[0]), .B(Data_Y[0]), .S0(n2660), .Y(n1232) );
MX2X1TS U2343 ( .A(intDY[30]), .B(Data_Y[30]), .S0(n2656), .Y(n1262) );
MX2X1TS U2344 ( .A(intDY[19]), .B(Data_Y[19]), .S0(n2657), .Y(n1251) );
MX2X1TS U2345 ( .A(intDY[34]), .B(Data_Y[34]), .S0(n2656), .Y(n1266) );
MX2X1TS U2346 ( .A(intDY[32]), .B(Data_Y[32]), .S0(n2656), .Y(n1264) );
MX2X1TS U2347 ( .A(intDY[59]), .B(Data_Y[59]), .S0(n3417), .Y(n1291) );
MX2X1TS U2348 ( .A(intDY[22]), .B(Data_Y[22]), .S0(n2657), .Y(n1254) );
MX2X1TS U2349 ( .A(intDY[27]), .B(Data_Y[27]), .S0(n2657), .Y(n1259) );
MX2X1TS U2350 ( .A(intDY[12]), .B(Data_Y[12]), .S0(n2659), .Y(n1244) );
MX2X1TS U2351 ( .A(intDY[14]), .B(Data_Y[14]), .S0(n2659), .Y(n1246) );
MX2X1TS U2352 ( .A(intDY[18]), .B(Data_Y[18]), .S0(n2659), .Y(n1250) );
MX2X1TS U2353 ( .A(intDY[50]), .B(Data_Y[50]), .S0(n2654), .Y(n1282) );
MX2X1TS U2354 ( .A(intDY[54]), .B(Data_Y[54]), .S0(n2654), .Y(n1286) );
MX2X1TS U2355 ( .A(intDY[36]), .B(Data_Y[36]), .S0(n2656), .Y(n1268) );
MX2X1TS U2356 ( .A(intDY[56]), .B(Data_Y[56]), .S0(n2654), .Y(n1288) );
MX2X1TS U2357 ( .A(intDY[24]), .B(Data_Y[24]), .S0(n2657), .Y(n1256) );
MX2X1TS U2358 ( .A(intDY[45]), .B(Data_Y[45]), .S0(n2655), .Y(n1277) );
MX2X1TS U2359 ( .A(intDY[26]), .B(Data_Y[26]), .S0(n2657), .Y(n1258) );
MX2X1TS U2360 ( .A(intDY[58]), .B(Data_Y[58]), .S0(n2654), .Y(n1290) );
OAI21XLTS U2361 ( .A0(n3696), .A1(n1772), .B0(n2490), .Y(n1143) );
OAI21XLTS U2362 ( .A0(n3749), .A1(n1772), .B0(n1771), .Y(n1141) );
OAI21XLTS U2363 ( .A0(n3693), .A1(n2475), .B0(n2469), .Y(n1124) );
OAI21XLTS U2364 ( .A0(n3687), .A1(n2475), .B0(n2461), .Y(n1119) );
OAI21XLTS U2365 ( .A0(n3725), .A1(n2515), .B0(n2471), .Y(n1117) );
OAI21XLTS U2366 ( .A0(n3714), .A1(n3443), .B0(n2076), .Y(n1439) );
MX2X1TS U2367 ( .A(Add_Subt_result[42]), .B(n2848), .S0(n3409), .Y(n1545) );
MX2X1TS U2368 ( .A(Add_Subt_result[37]), .B(n3011), .S0(n1580), .Y(n1540) );
MX2X1TS U2369 ( .A(exp_oper_result[6]), .B(n3422), .S0(n3421), .Y(n1432) );
MX2X1TS U2370 ( .A(exp_oper_result[7]), .B(n3420), .S0(n3421), .Y(n1431) );
MX2X1TS U2371 ( .A(exp_oper_result[8]), .B(n3419), .S0(n3421), .Y(n1430) );
MX2X1TS U2372 ( .A(exp_oper_result[9]), .B(n3418), .S0(n3421), .Y(n1429) );
MX2X1TS U2373 ( .A(exp_oper_result[10]), .B(n2433), .S0(n1913), .Y(n1428) );
INVX2TS U2374 ( .A(n2602), .Y(n2297) );
AOI2BB2XLTS U2375 ( .B0(n2288), .B1(Sgf_normalized_result[42]), .A0N(n1591),
.A1N(n2600), .Y(n2172) );
AOI2BB2XLTS U2376 ( .B0(n2302), .B1(Sgf_normalized_result[41]), .A0N(n1591),
.A1N(n2598), .Y(n2165) );
AOI2BB2XLTS U2377 ( .B0(n1577), .B1(Sgf_normalized_result[38]), .A0N(n2638),
.A1N(n1591), .Y(n2342) );
AOI2BB2XLTS U2378 ( .B0(n1577), .B1(Sgf_normalized_result[37]), .A0N(n2612),
.A1N(n1591), .Y(n2311) );
AOI2BB2XLTS U2379 ( .B0(n2302), .B1(Sgf_normalized_result[36]), .A0N(n2614),
.A1N(n1591), .Y(n2334) );
AOI2BB2XLTS U2380 ( .B0(n2302), .B1(Sgf_normalized_result[35]), .A0N(n2606),
.A1N(n1591), .Y(n2324) );
AOI2BB2XLTS U2381 ( .B0(n1577), .B1(Sgf_normalized_result[34]), .A0N(n2604),
.A1N(n1591), .Y(n2315) );
AOI2BB2XLTS U2382 ( .B0(n2288), .B1(Sgf_normalized_result[33]), .A0N(n2610),
.A1N(n1591), .Y(n2329) );
NOR2XLTS U2383 ( .A(n2240), .B(n1600), .Y(n2241) );
AOI2BB2XLTS U2384 ( .B0(n1577), .B1(Sgf_normalized_result[2]), .A0N(n3395),
.A1N(n1593), .Y(n3396) );
MX2X1TS U2385 ( .A(exp_oper_result[1]), .B(n3373), .S0(n3421), .Y(n1437) );
MX2X1TS U2386 ( .A(exp_oper_result[2]), .B(n3355), .S0(n3421), .Y(n1436) );
MX2X1TS U2387 ( .A(exp_oper_result[5]), .B(n3294), .S0(n3421), .Y(n1433) );
AOI2BB2XLTS U2388 ( .B0(n2114), .B1(n3525), .A0N(n3518), .A1N(n2113), .Y(
n2115) );
AOI2BB2XLTS U2389 ( .B0(n3641), .B1(n2099), .A0N(n3510), .A1N(n2113), .Y(
n2100) );
AO21XLTS U2390 ( .A0(n1601), .A1(exp_oper_result[0]), .B0(n3444), .Y(n1438)
);
MX2X1TS U2391 ( .A(exp_oper_result[3]), .B(n3327), .S0(n3421), .Y(n1435) );
MX2X1TS U2392 ( .A(exp_oper_result[4]), .B(n3328), .S0(n1913), .Y(n1434) );
MX2X1TS U2393 ( .A(Add_Subt_result[15]), .B(n2727), .S0(n3265), .Y(n1518) );
MX2X1TS U2394 ( .A(Add_Subt_result[3]), .B(n3279), .S0(n3405), .Y(n1506) );
MX2X1TS U2395 ( .A(Add_Subt_result[1]), .B(n3281), .S0(n1580), .Y(n1504) );
MX2X1TS U2396 ( .A(Add_Subt_result[11]), .B(n3210), .S0(n3265), .Y(n1514) );
MX2X1TS U2397 ( .A(Add_Subt_result[30]), .B(n3099), .S0(n3020), .Y(n1533) );
MX2X1TS U2398 ( .A(Add_Subt_result[13]), .B(n3206), .S0(n3098), .Y(n1516) );
MX2X1TS U2399 ( .A(intDY[37]), .B(Data_Y[37]), .S0(n2656), .Y(n1269) );
MX2X1TS U2400 ( .A(Add_Subt_result[41]), .B(n2992), .S0(n1580), .Y(n1544) );
MX2X1TS U2401 ( .A(Add_Subt_result[8]), .B(n3239), .S0(n3098), .Y(n1511) );
MX2X1TS U2402 ( .A(Add_Subt_result[18]), .B(n3176), .S0(n3020), .Y(n1521) );
MX2X1TS U2403 ( .A(Add_Subt_result[32]), .B(n3111), .S0(n3232), .Y(n1535) );
MX2X1TS U2404 ( .A(Add_Subt_result[34]), .B(n3052), .S0(n3265), .Y(n1537) );
MX2X1TS U2405 ( .A(Add_Subt_result[21]), .B(n3139), .S0(n3232), .Y(n1524) );
MX2X1TS U2406 ( .A(intDY[2]), .B(Data_Y[2]), .S0(n2660), .Y(n1234) );
MX2X1TS U2407 ( .A(intDY[47]), .B(Data_Y[47]), .S0(n2655), .Y(n1279) );
MX2X1TS U2408 ( .A(intDY[9]), .B(Data_Y[9]), .S0(n2659), .Y(n1241) );
MX2X1TS U2409 ( .A(intDY[51]), .B(Data_Y[51]), .S0(n2654), .Y(n1283) );
MX2X1TS U2410 ( .A(intDY[40]), .B(Data_Y[40]), .S0(n2655), .Y(n1272) );
MX2X1TS U2411 ( .A(Add_Subt_result[27]), .B(n3089), .S0(n3098), .Y(n1530) );
MX2X1TS U2412 ( .A(intDY[28]), .B(Data_Y[28]), .S0(n2657), .Y(n1260) );
MX2X1TS U2413 ( .A(intDY[20]), .B(Data_Y[20]), .S0(n2657), .Y(n1252) );
MX2X1TS U2414 ( .A(intDY[8]), .B(Data_Y[8]), .S0(n2660), .Y(n1240) );
MX2X1TS U2415 ( .A(intDY[49]), .B(Data_Y[49]), .S0(n2654), .Y(n1281) );
MX2X1TS U2416 ( .A(intDY[42]), .B(Data_Y[42]), .S0(n2655), .Y(n1274) );
MX2X1TS U2417 ( .A(intDY[60]), .B(Data_Y[60]), .S0(n3417), .Y(n1292) );
MX2X1TS U2418 ( .A(intDY[46]), .B(Data_Y[46]), .S0(n2655), .Y(n1278) );
MX2X1TS U2419 ( .A(intDY[25]), .B(Data_Y[25]), .S0(n2657), .Y(n1257) );
MX2X1TS U2420 ( .A(intDY[17]), .B(Data_Y[17]), .S0(n2659), .Y(n1249) );
MX2X1TS U2421 ( .A(intDY[57]), .B(Data_Y[57]), .S0(n2654), .Y(n1289) );
MX2X1TS U2422 ( .A(intDY[11]), .B(Data_Y[11]), .S0(n2659), .Y(n1243) );
MX2X1TS U2423 ( .A(intDY[21]), .B(Data_Y[21]), .S0(n2657), .Y(n1253) );
MX2X1TS U2424 ( .A(intDY[13]), .B(Data_Y[13]), .S0(n2659), .Y(n1245) );
MX2X1TS U2425 ( .A(intDY[29]), .B(Data_Y[29]), .S0(n2656), .Y(n1261) );
MX2X1TS U2426 ( .A(intDY[23]), .B(Data_Y[23]), .S0(n2657), .Y(n1255) );
MX2X1TS U2427 ( .A(intDY[55]), .B(Data_Y[55]), .S0(n2654), .Y(n1287) );
MX2X1TS U2428 ( .A(intDY[43]), .B(Data_Y[43]), .S0(n2655), .Y(n1275) );
MX2X1TS U2429 ( .A(intDY[35]), .B(Data_Y[35]), .S0(n2656), .Y(n1267) );
MX2X1TS U2430 ( .A(intDY[31]), .B(Data_Y[31]), .S0(n2656), .Y(n1263) );
MX2X1TS U2431 ( .A(intDY[53]), .B(Data_Y[53]), .S0(n2654), .Y(n1285) );
MX2X1TS U2432 ( .A(intDY[33]), .B(Data_Y[33]), .S0(n2656), .Y(n1265) );
MX2X1TS U2433 ( .A(Add_Subt_result[7]), .B(n3245), .S0(n1580), .Y(n1510) );
MX2X1TS U2434 ( .A(intDX[56]), .B(Data_X[56]), .S0(n2647), .Y(n1353) );
MX2X1TS U2435 ( .A(intDX[30]), .B(Data_X[30]), .S0(n2650), .Y(n1327) );
MX2X1TS U2436 ( .A(intDX[9]), .B(Data_X[9]), .S0(n2652), .Y(n1306) );
MX2X1TS U2437 ( .A(intDY[63]), .B(Data_Y[63]), .S0(n2647), .Y(n1231) );
MX2X1TS U2438 ( .A(intAS), .B(add_subt), .S0(n2647), .Y(n1295) );
MX2X1TS U2439 ( .A(Add_Subt_result[39]), .B(n3026), .S0(n3232), .Y(n1542) );
OAI21XLTS U2440 ( .A0(n2640), .A1(n3703), .B0(n2441), .Y(n1167) );
MX2X1TS U2441 ( .A(Add_Subt_result[25]), .B(n3078), .S0(n3265), .Y(n1528) );
MX2X1TS U2442 ( .A(Add_Subt_result[36]), .B(n3035), .S0(n3098), .Y(n1539) );
MX2X1TS U2443 ( .A(Add_Subt_result[23]), .B(n3130), .S0(n3265), .Y(n1526) );
OAI21XLTS U2444 ( .A0(n3390), .A1(n3806), .B0(n3389), .Y(n3392) );
MX2X1TS U2445 ( .A(Add_Subt_result[31]), .B(n3117), .S0(n3098), .Y(n1534) );
MX2X1TS U2446 ( .A(intDX[2]), .B(Data_X[2]), .S0(n3417), .Y(n1299) );
MX2X1TS U2447 ( .A(intDX[4]), .B(Data_X[4]), .S0(n3417), .Y(n1301) );
MX2X1TS U2448 ( .A(intDX[37]), .B(Data_X[37]), .S0(n2649), .Y(n1334) );
MX2X1TS U2449 ( .A(intDX[38]), .B(Data_X[38]), .S0(n2649), .Y(n1335) );
MX2X1TS U2450 ( .A(intDX[40]), .B(Data_X[40]), .S0(n2649), .Y(n1337) );
MX2X1TS U2451 ( .A(intDX[42]), .B(Data_X[42]), .S0(n2649), .Y(n1339) );
MX2X1TS U2452 ( .A(intDX[44]), .B(Data_X[44]), .S0(n2649), .Y(n1341) );
MX2X1TS U2453 ( .A(intDX[46]), .B(Data_X[46]), .S0(n2648), .Y(n1343) );
MX2X1TS U2454 ( .A(intDX[47]), .B(Data_X[47]), .S0(n2648), .Y(n1344) );
MX2X1TS U2455 ( .A(intDX[48]), .B(Data_X[48]), .S0(n2648), .Y(n1345) );
MX2X1TS U2456 ( .A(intDX[51]), .B(Data_X[51]), .S0(n2648), .Y(n1348) );
MX2X1TS U2457 ( .A(intDX[52]), .B(Data_X[52]), .S0(n2648), .Y(n1349) );
MX2X1TS U2458 ( .A(intDX[54]), .B(Data_X[54]), .S0(n2648), .Y(n1351) );
MX2X1TS U2459 ( .A(intDX[57]), .B(Data_X[57]), .S0(n2647), .Y(n1354) );
MX2X1TS U2460 ( .A(intDX[58]), .B(Data_X[58]), .S0(n2647), .Y(n1355) );
MX2X1TS U2461 ( .A(intDX[60]), .B(Data_X[60]), .S0(n2647), .Y(n1357) );
MX2X1TS U2462 ( .A(intDX[6]), .B(Data_X[6]), .S0(n2652), .Y(n1303) );
MX2X1TS U2463 ( .A(intDX[10]), .B(Data_X[10]), .S0(n2652), .Y(n1307) );
MX2X1TS U2464 ( .A(intDX[12]), .B(Data_X[12]), .S0(n2652), .Y(n1309) );
MX2X1TS U2465 ( .A(intDX[14]), .B(Data_X[14]), .S0(n2652), .Y(n1311) );
MX2X1TS U2466 ( .A(intDX[16]), .B(Data_X[16]), .S0(n2651), .Y(n1313) );
MX2X1TS U2467 ( .A(intDX[19]), .B(Data_X[19]), .S0(n2651), .Y(n1316) );
MX2X1TS U2468 ( .A(intDX[20]), .B(Data_X[20]), .S0(n2651), .Y(n1317) );
MX2X1TS U2469 ( .A(intDX[22]), .B(Data_X[22]), .S0(n2651), .Y(n1319) );
MX2X1TS U2470 ( .A(intDX[24]), .B(Data_X[24]), .S0(n2651), .Y(n1321) );
MX2X1TS U2471 ( .A(intDX[27]), .B(Data_X[27]), .S0(n2650), .Y(n1324) );
MX2X1TS U2472 ( .A(intDX[28]), .B(Data_X[28]), .S0(n2650), .Y(n1325) );
MX2X1TS U2473 ( .A(intDX[32]), .B(Data_X[32]), .S0(n2650), .Y(n1329) );
MX2X1TS U2474 ( .A(intDX[34]), .B(Data_X[34]), .S0(n2650), .Y(n1331) );
MX2X1TS U2475 ( .A(Add_Subt_result[0]), .B(n3292), .S0(n3020), .Y(n1503) );
AOI2BB2XLTS U2476 ( .B0(n1577), .B1(Sgf_normalized_result[32]), .A0N(n2608),
.A1N(n1592), .Y(n2320) );
MX2X1TS U2477 ( .A(intDY[15]), .B(Data_Y[15]), .S0(n2659), .Y(n1247) );
MX2X1TS U2478 ( .A(intDY[41]), .B(Data_Y[41]), .S0(n2655), .Y(n1273) );
MX2X1TS U2479 ( .A(intDY[39]), .B(Data_Y[39]), .S0(n2655), .Y(n1271) );
MX2X1TS U2480 ( .A(Add_Subt_result[53]), .B(n2976), .S0(n3409), .Y(n1556) );
OAI211XLTS U2481 ( .A0(n2247), .A1(n1592), .B0(n2246), .C0(n2245), .Y(n1481)
);
AO21XLTS U2482 ( .A0(n3398), .A1(n2348), .B0(n1979), .Y(n1465) );
MX2X1TS U2483 ( .A(Add_Subt_result[44]), .B(n2916), .S0(n3409), .Y(n1547) );
MX2X1TS U2484 ( .A(intDY[3]), .B(Data_Y[3]), .S0(n2660), .Y(n1235) );
MX2X1TS U2485 ( .A(intDX[15]), .B(Data_X[15]), .S0(n2651), .Y(n1312) );
MX2X1TS U2486 ( .A(intDX[39]), .B(Data_X[39]), .S0(n2649), .Y(n1336) );
MX2X1TS U2487 ( .A(Add_Subt_result[28]), .B(n3064), .S0(n3232), .Y(n1531) );
MX2X1TS U2488 ( .A(intDX[13]), .B(Data_X[13]), .S0(n2652), .Y(n1310) );
AO22XLTS U2489 ( .A0(n3456), .A1(Sgf_normalized_result[53]), .B0(
final_result_ieee[51]), .B1(n3463), .Y(n1363) );
AO22XLTS U2490 ( .A0(n3456), .A1(Sgf_normalized_result[52]), .B0(
final_result_ieee[50]), .B1(n3463), .Y(n1364) );
AO22XLTS U2491 ( .A0(n3454), .A1(Sgf_normalized_result[51]), .B0(
final_result_ieee[49]), .B1(n3463), .Y(n1365) );
AO22XLTS U2492 ( .A0(n3454), .A1(Sgf_normalized_result[50]), .B0(
final_result_ieee[48]), .B1(n3453), .Y(n1366) );
AO22XLTS U2493 ( .A0(n3454), .A1(Sgf_normalized_result[49]), .B0(
final_result_ieee[47]), .B1(n3453), .Y(n1367) );
AO22XLTS U2494 ( .A0(n3454), .A1(Sgf_normalized_result[48]), .B0(
final_result_ieee[46]), .B1(n3453), .Y(n1368) );
AO22XLTS U2495 ( .A0(n3454), .A1(Sgf_normalized_result[47]), .B0(
final_result_ieee[45]), .B1(n3453), .Y(n1369) );
AO22XLTS U2496 ( .A0(n3454), .A1(Sgf_normalized_result[46]), .B0(
final_result_ieee[44]), .B1(n3453), .Y(n1370) );
AO22XLTS U2497 ( .A0(n3454), .A1(Sgf_normalized_result[45]), .B0(
final_result_ieee[43]), .B1(n3453), .Y(n1371) );
AO22XLTS U2498 ( .A0(n3454), .A1(Sgf_normalized_result[44]), .B0(
final_result_ieee[42]), .B1(n3453), .Y(n1372) );
AO22XLTS U2499 ( .A0(n3454), .A1(Sgf_normalized_result[43]), .B0(
final_result_ieee[41]), .B1(n3453), .Y(n1373) );
AO22XLTS U2500 ( .A0(n3454), .A1(Sgf_normalized_result[42]), .B0(
final_result_ieee[40]), .B1(n3453), .Y(n1374) );
AO22XLTS U2501 ( .A0(n3452), .A1(Sgf_normalized_result[41]), .B0(
final_result_ieee[39]), .B1(n3453), .Y(n1375) );
AO22XLTS U2502 ( .A0(n3452), .A1(Sgf_normalized_result[40]), .B0(
final_result_ieee[38]), .B1(n3451), .Y(n1376) );
AO22XLTS U2503 ( .A0(n3452), .A1(Sgf_normalized_result[39]), .B0(
final_result_ieee[37]), .B1(n3451), .Y(n1377) );
AO22XLTS U2504 ( .A0(n3452), .A1(Sgf_normalized_result[38]), .B0(
final_result_ieee[36]), .B1(n3451), .Y(n1378) );
AO22XLTS U2505 ( .A0(n3452), .A1(Sgf_normalized_result[37]), .B0(
final_result_ieee[35]), .B1(n3451), .Y(n1379) );
AO22XLTS U2506 ( .A0(n3452), .A1(Sgf_normalized_result[36]), .B0(
final_result_ieee[34]), .B1(n3451), .Y(n1380) );
AO22XLTS U2507 ( .A0(n3452), .A1(Sgf_normalized_result[35]), .B0(
final_result_ieee[33]), .B1(n3451), .Y(n1381) );
AO22XLTS U2508 ( .A0(n3452), .A1(Sgf_normalized_result[34]), .B0(
final_result_ieee[32]), .B1(n3451), .Y(n1382) );
AO22XLTS U2509 ( .A0(n3452), .A1(Sgf_normalized_result[33]), .B0(
final_result_ieee[31]), .B1(n3451), .Y(n1383) );
AO22XLTS U2510 ( .A0(n3452), .A1(Sgf_normalized_result[32]), .B0(
final_result_ieee[30]), .B1(n3451), .Y(n1384) );
AO22XLTS U2511 ( .A0(n3450), .A1(Sgf_normalized_result[31]), .B0(
final_result_ieee[29]), .B1(n3451), .Y(n1385) );
AO22XLTS U2512 ( .A0(n3450), .A1(Sgf_normalized_result[30]), .B0(
final_result_ieee[28]), .B1(n3449), .Y(n1386) );
AO22XLTS U2513 ( .A0(n3450), .A1(Sgf_normalized_result[29]), .B0(
final_result_ieee[27]), .B1(n3449), .Y(n1387) );
AO22XLTS U2514 ( .A0(n3450), .A1(Sgf_normalized_result[28]), .B0(
final_result_ieee[26]), .B1(n3449), .Y(n1388) );
AO22XLTS U2515 ( .A0(n3450), .A1(Sgf_normalized_result[27]), .B0(
final_result_ieee[25]), .B1(n3449), .Y(n1389) );
AO22XLTS U2516 ( .A0(n3450), .A1(Sgf_normalized_result[26]), .B0(
final_result_ieee[24]), .B1(n3449), .Y(n1390) );
AO22XLTS U2517 ( .A0(n3450), .A1(Sgf_normalized_result[25]), .B0(
final_result_ieee[23]), .B1(n3449), .Y(n1391) );
AO22XLTS U2518 ( .A0(n3450), .A1(Sgf_normalized_result[24]), .B0(
final_result_ieee[22]), .B1(n3449), .Y(n1392) );
AO22XLTS U2519 ( .A0(n3450), .A1(Sgf_normalized_result[23]), .B0(
final_result_ieee[21]), .B1(n3449), .Y(n1393) );
AO22XLTS U2520 ( .A0(n3450), .A1(Sgf_normalized_result[22]), .B0(
final_result_ieee[20]), .B1(n3449), .Y(n1394) );
AO22XLTS U2521 ( .A0(n3448), .A1(Sgf_normalized_result[21]), .B0(
final_result_ieee[19]), .B1(n3449), .Y(n1395) );
AO22XLTS U2522 ( .A0(n3448), .A1(Sgf_normalized_result[20]), .B0(
final_result_ieee[18]), .B1(n3447), .Y(n1396) );
AO22XLTS U2523 ( .A0(n3448), .A1(Sgf_normalized_result[19]), .B0(
final_result_ieee[17]), .B1(n3447), .Y(n1397) );
AO22XLTS U2524 ( .A0(n3448), .A1(Sgf_normalized_result[18]), .B0(
final_result_ieee[16]), .B1(n3447), .Y(n1398) );
AO22XLTS U2525 ( .A0(n3448), .A1(Sgf_normalized_result[17]), .B0(
final_result_ieee[15]), .B1(n3447), .Y(n1399) );
AO22XLTS U2526 ( .A0(n3448), .A1(Sgf_normalized_result[16]), .B0(
final_result_ieee[14]), .B1(n3447), .Y(n1400) );
AO22XLTS U2527 ( .A0(n3448), .A1(Sgf_normalized_result[15]), .B0(
final_result_ieee[13]), .B1(n3447), .Y(n1401) );
AO22XLTS U2528 ( .A0(n3448), .A1(Sgf_normalized_result[14]), .B0(
final_result_ieee[12]), .B1(n3447), .Y(n1402) );
AO22XLTS U2529 ( .A0(n3448), .A1(Sgf_normalized_result[13]), .B0(
final_result_ieee[11]), .B1(n3447), .Y(n1403) );
AO22XLTS U2530 ( .A0(n3448), .A1(Sgf_normalized_result[12]), .B0(
final_result_ieee[10]), .B1(n3447), .Y(n1404) );
AO22XLTS U2531 ( .A0(n3446), .A1(Sgf_normalized_result[11]), .B0(
final_result_ieee[9]), .B1(n3447), .Y(n1405) );
AO22XLTS U2532 ( .A0(n3446), .A1(Sgf_normalized_result[10]), .B0(
final_result_ieee[8]), .B1(n3445), .Y(n1406) );
AO22XLTS U2533 ( .A0(n3446), .A1(Sgf_normalized_result[9]), .B0(
final_result_ieee[7]), .B1(n3445), .Y(n1407) );
AO22XLTS U2534 ( .A0(n3446), .A1(Sgf_normalized_result[8]), .B0(
final_result_ieee[6]), .B1(n3445), .Y(n1408) );
AO22XLTS U2535 ( .A0(n3446), .A1(Sgf_normalized_result[7]), .B0(
final_result_ieee[5]), .B1(n3445), .Y(n1409) );
AO22XLTS U2536 ( .A0(n3446), .A1(Sgf_normalized_result[6]), .B0(
final_result_ieee[4]), .B1(n3445), .Y(n1410) );
AO22XLTS U2537 ( .A0(n3446), .A1(Sgf_normalized_result[5]), .B0(
final_result_ieee[3]), .B1(n3445), .Y(n1411) );
AO22XLTS U2538 ( .A0(n3446), .A1(Sgf_normalized_result[4]), .B0(
final_result_ieee[2]), .B1(n3445), .Y(n1412) );
AO22XLTS U2539 ( .A0(n3446), .A1(Sgf_normalized_result[3]), .B0(
final_result_ieee[1]), .B1(n3445), .Y(n1413) );
AO22XLTS U2540 ( .A0(n3446), .A1(Sgf_normalized_result[2]), .B0(
final_result_ieee[0]), .B1(n3445), .Y(n1414) );
MX2X1TS U2541 ( .A(Add_Subt_result[9]), .B(n3250), .S0(n3232), .Y(n1512) );
MX2X1TS U2542 ( .A(intDY[4]), .B(Data_Y[4]), .S0(n2660), .Y(n1236) );
MX2X1TS U2543 ( .A(intDY[7]), .B(Data_Y[7]), .S0(n2660), .Y(n1239) );
MX2X1TS U2544 ( .A(intDX[5]), .B(Data_X[5]), .S0(n2652), .Y(n1302) );
MX2X1TS U2545 ( .A(intDY[62]), .B(Data_Y[62]), .S0(n3417), .Y(n1294) );
MX2X1TS U2546 ( .A(intDX[59]), .B(Data_X[59]), .S0(n2647), .Y(n1356) );
MX2X1TS U2547 ( .A(intDX[1]), .B(Data_X[1]), .S0(n3417), .Y(n1298) );
MX2X1TS U2548 ( .A(Add_Subt_result[33]), .B(n3083), .S0(n3232), .Y(n1536) );
MX2X1TS U2549 ( .A(intDY[61]), .B(Data_Y[61]), .S0(n3417), .Y(n1293) );
MX2X1TS U2550 ( .A(intDY[1]), .B(Data_Y[1]), .S0(n2660), .Y(n1233) );
MX2X1TS U2551 ( .A(intDY[48]), .B(Data_Y[48]), .S0(n2655), .Y(n1280) );
MX2X1TS U2552 ( .A(intDY[44]), .B(Data_Y[44]), .S0(n2655), .Y(n1276) );
MX2X1TS U2553 ( .A(intDY[10]), .B(Data_Y[10]), .S0(n2659), .Y(n1242) );
MX2X1TS U2554 ( .A(intDY[52]), .B(Data_Y[52]), .S0(n2654), .Y(n1284) );
MX2X1TS U2555 ( .A(intDY[38]), .B(Data_Y[38]), .S0(n2656), .Y(n1270) );
MX2X1TS U2556 ( .A(intDY[5]), .B(Data_Y[5]), .S0(n2660), .Y(n1237) );
MX2X1TS U2557 ( .A(intDX[7]), .B(Data_X[7]), .S0(n2652), .Y(n1304) );
MX2X1TS U2558 ( .A(intDY[16]), .B(Data_Y[16]), .S0(n2659), .Y(n1248) );
MX2X1TS U2559 ( .A(intDY[6]), .B(Data_Y[6]), .S0(n2660), .Y(n1238) );
MX2X1TS U2560 ( .A(intDX[29]), .B(Data_X[29]), .S0(n2650), .Y(n1326) );
MX2X1TS U2561 ( .A(intDX[21]), .B(Data_X[21]), .S0(n2651), .Y(n1318) );
MX2X1TS U2562 ( .A(intDX[62]), .B(Data_X[62]), .S0(n3417), .Y(n1359) );
MX2X1TS U2563 ( .A(intDX[41]), .B(Data_X[41]), .S0(n2649), .Y(n1338) );
MX2X1TS U2564 ( .A(intDX[61]), .B(Data_X[61]), .S0(n2647), .Y(n1358) );
MX2X1TS U2565 ( .A(intDX[45]), .B(Data_X[45]), .S0(n2648), .Y(n1342) );
MX2X1TS U2566 ( .A(intDX[43]), .B(Data_X[43]), .S0(n2649), .Y(n1340) );
MX2X1TS U2567 ( .A(intDX[35]), .B(Data_X[35]), .S0(n2649), .Y(n1332) );
MX2X1TS U2568 ( .A(intDX[33]), .B(Data_X[33]), .S0(n2650), .Y(n1330) );
MX2X1TS U2569 ( .A(intDX[36]), .B(Data_X[36]), .S0(n2649), .Y(n1333) );
MX2X1TS U2570 ( .A(intDX[49]), .B(Data_X[49]), .S0(n2648), .Y(n1346) );
MX2X1TS U2571 ( .A(intDX[25]), .B(Data_X[25]), .S0(n2650), .Y(n1322) );
MX2X1TS U2572 ( .A(intDX[17]), .B(Data_X[17]), .S0(n2651), .Y(n1314) );
MX2X1TS U2573 ( .A(intDX[11]), .B(Data_X[11]), .S0(n2652), .Y(n1308) );
MX2X1TS U2574 ( .A(intDX[31]), .B(Data_X[31]), .S0(n2650), .Y(n1328) );
MX2X1TS U2575 ( .A(intDX[23]), .B(Data_X[23]), .S0(n2651), .Y(n1320) );
MX2X1TS U2576 ( .A(intDX[3]), .B(Data_X[3]), .S0(n3417), .Y(n1300) );
MX2X1TS U2577 ( .A(intDX[0]), .B(Data_X[0]), .S0(n3417), .Y(n1297) );
MX2X1TS U2578 ( .A(intDX[53]), .B(Data_X[53]), .S0(n2648), .Y(n1350) );
MX2X1TS U2579 ( .A(intDX[55]), .B(Data_X[55]), .S0(n2647), .Y(n1352) );
MX2X1TS U2580 ( .A(intDX[50]), .B(Data_X[50]), .S0(n2648), .Y(n1347) );
MX2X1TS U2581 ( .A(intDX[26]), .B(Data_X[26]), .S0(n2650), .Y(n1323) );
MX2X1TS U2582 ( .A(intDX[18]), .B(Data_X[18]), .S0(n2651), .Y(n1315) );
MX2X1TS U2583 ( .A(intDX[8]), .B(Data_X[8]), .S0(n2652), .Y(n1305) );
MX2X1TS U2584 ( .A(Add_Subt_result[22]), .B(n3148), .S0(n3098), .Y(n1525) );
MX2X1TS U2585 ( .A(Add_Subt_result[16]), .B(n3186), .S0(n3265), .Y(n1519) );
MX2X1TS U2586 ( .A(Add_Subt_result[5]), .B(n3266), .S0(n3020), .Y(n1508) );
MX2X1TS U2587 ( .A(Add_Subt_result[10]), .B(n3233), .S0(n3265), .Y(n1513) );
MX2X1TS U2588 ( .A(Add_Subt_result[6]), .B(n3259), .S0(n3098), .Y(n1509) );
MX2X1TS U2589 ( .A(Add_Subt_result[24]), .B(n3124), .S0(n3020), .Y(n1527) );
OAI21XLTS U2590 ( .A0(n3118), .A1(n3125), .B0(n3126), .Y(n3123) );
MX2X1TS U2591 ( .A(Add_Subt_result[4]), .B(n3274), .S0(n3405), .Y(n1507) );
MX2X1TS U2592 ( .A(Add_Subt_result[2]), .B(n3289), .S0(n3405), .Y(n1505) );
MX2X1TS U2593 ( .A(Add_Subt_result[20]), .B(n3161), .S0(n3020), .Y(n1523) );
MX2X1TS U2594 ( .A(Add_Subt_result[40]), .B(n3021), .S0(n3409), .Y(n1543) );
MX2X1TS U2595 ( .A(Add_Subt_result[38]), .B(n3006), .S0(n1580), .Y(n1541) );
MX2X1TS U2596 ( .A(intDX[63]), .B(Data_X[63]), .S0(n2660), .Y(n1296) );
NAND4XLTS U2597 ( .A(n3645), .B(n3644), .C(n3643), .D(n3642), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[2]) );
NAND4XLTS U2598 ( .A(n3630), .B(n3629), .C(n3628), .D(n3627), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[3]) );
NAND4XLTS U2599 ( .A(n3622), .B(n3621), .C(n3620), .D(n3619), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[4]) );
NAND4XLTS U2600 ( .A(n3615), .B(n3614), .C(n3613), .D(n3612), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[5]) );
OAI21X1TS U2601 ( .A0(n1818), .A1(n3443), .B0(n1817), .Y(n1497) );
NAND4BXLTS U2602 ( .AN(n3323), .B(n3437), .C(n3322), .D(n3321), .Y(n3324) );
OAI21XLTS U2603 ( .A0(n3351), .A1(n3800), .B0(n3350), .Y(n3352) );
MX2X1TS U2604 ( .A(Add_Subt_result[54]), .B(n2971), .S0(n3232), .Y(n1502) );
MX2X1TS U2605 ( .A(Add_Subt_result[43]), .B(n2860), .S0(n3409), .Y(n1546) );
MX2X1TS U2606 ( .A(Add_Subt_result[45]), .B(n2906), .S0(n3405), .Y(n1548) );
MX2X1TS U2607 ( .A(Add_Subt_result[46]), .B(n2901), .S0(n1580), .Y(n1549) );
MX2X1TS U2608 ( .A(Add_Subt_result[47]), .B(n2888), .S0(n3409), .Y(n1550) );
MX2X1TS U2609 ( .A(Add_Subt_result[48]), .B(n2931), .S0(n3405), .Y(n1551) );
MX2X1TS U2610 ( .A(Add_Subt_result[49]), .B(n2939), .S0(n3020), .Y(n1552) );
MX2X1TS U2611 ( .A(Add_Subt_result[50]), .B(n2949), .S0(n3265), .Y(n1553) );
MX2X1TS U2612 ( .A(Add_Subt_result[51]), .B(n2981), .S0(n3098), .Y(n1554) );
MX2X1TS U2613 ( .A(Add_Subt_result[52]), .B(n2987), .S0(n1580), .Y(n1555) );
MX2X1TS U2614 ( .A(add_overflow_flag), .B(n3406), .S0(n3405), .Y(n1562) );
XNOR2X1TS U2615 ( .A(n3404), .B(n3403), .Y(n3406) );
AO21XLTS U2616 ( .A0(n2641), .A1(n2661), .B0(n2589), .Y(n2428) );
NAND4XLTS U2617 ( .A(n3415), .B(n1601), .C(n2646), .D(n2645), .Y(n1558) );
NAND4X2TS U2618 ( .A(n2434), .B(n2433), .C(n3418), .D(n3419), .Y(n2435) );
NAND2X1TS U2619 ( .A(n3391), .B(n3398), .Y(n2341) );
OA21XLTS U2620 ( .A0(n2292), .A1(n3806), .B0(n2291), .Y(n1573) );
NOR2X4TS U2621 ( .A(n2438), .B(n2472), .Y(n2448) );
AND2X4TS U2622 ( .A(n3519), .B(n2110), .Y(n2121) );
INVX2TS U2623 ( .A(n2595), .Y(n2302) );
OR2X2TS U2624 ( .A(n1917), .B(FS_Module_state_reg[3]), .Y(n3166) );
NAND2X4TS U2625 ( .A(n2438), .B(n2640), .Y(n1772) );
OA21XLTS U2626 ( .A0(n2108), .A1(n3791), .B0(n2118), .Y(n1574) );
INVX4TS U2627 ( .A(n2962), .Y(n1587) );
BUFX3TS U2628 ( .A(n1966), .Y(n2167) );
INVX2TS U2629 ( .A(n1772), .Y(n2550) );
BUFX3TS U2630 ( .A(n2550), .Y(n2543) );
BUFX3TS U2631 ( .A(n2529), .Y(n2523) );
INVX2TS U2632 ( .A(n2343), .Y(n1598) );
NAND2X4TS U2633 ( .A(n2595), .B(n3633), .Y(n2343) );
INVX2TS U2634 ( .A(n2449), .Y(n2507) );
INVX2TS U2635 ( .A(n3166), .Y(n3405) );
NOR2X2TS U2636 ( .A(Add_Subt_result[51]), .B(Add_Subt_result[52]), .Y(n3361)
);
NOR2X2TS U2637 ( .A(n3293), .B(n3785), .Y(n2425) );
INVX2TS U2638 ( .A(n2595), .Y(n1576) );
INVX2TS U2639 ( .A(n1957), .Y(n1577) );
INVX2TS U2640 ( .A(n3469), .Y(n1578) );
INVX2TS U2641 ( .A(n3469), .Y(n1579) );
INVX2TS U2642 ( .A(n3166), .Y(n1580) );
INVX2TS U2643 ( .A(n2341), .Y(n1581) );
INVX2TS U2644 ( .A(n1581), .Y(n1582) );
INVX2TS U2645 ( .A(n1581), .Y(n1583) );
INVX2TS U2646 ( .A(n2341), .Y(n1586) );
INVX4TS U2647 ( .A(n2962), .Y(n1588) );
INVX2TS U2648 ( .A(n2546), .Y(n1589) );
INVX2TS U2649 ( .A(n2546), .Y(n1590) );
INVX2TS U2650 ( .A(n2303), .Y(n1591) );
INVX2TS U2651 ( .A(n2303), .Y(n1592) );
INVX2TS U2652 ( .A(n2121), .Y(n1595) );
INVX2TS U2653 ( .A(n1595), .Y(n1596) );
INVX2TS U2654 ( .A(n1595), .Y(n1597) );
INVX2TS U2655 ( .A(n1598), .Y(n1599) );
INVX2TS U2656 ( .A(n1598), .Y(n1600) );
AOI21X1TS U2657 ( .A0(n3222), .A1(n2708), .B0(n2707), .Y(n3188) );
OAI21XLTS U2658 ( .A0(n3764), .A1(n2515), .B0(n2508), .Y(n1113) );
OAI21XLTS U2659 ( .A0(n3722), .A1(n2515), .B0(n2503), .Y(n1114) );
OAI21XLTS U2660 ( .A0(n3682), .A1(n2515), .B0(n2445), .Y(n1115) );
OAI21XLTS U2661 ( .A0(n3753), .A1(n2515), .B0(n2514), .Y(n1116) );
OAI21XLTS U2662 ( .A0(n3720), .A1(n2475), .B0(n2464), .Y(n1118) );
OAI21XLTS U2663 ( .A0(n3756), .A1(n2475), .B0(n2466), .Y(n1120) );
OAI21XLTS U2664 ( .A0(n3686), .A1(n2475), .B0(n2462), .Y(n1127) );
OAI21XLTS U2665 ( .A0(n3739), .A1(n1772), .B0(n2497), .Y(n1142) );
OAI21XLTS U2666 ( .A0(n3744), .A1(n1772), .B0(n1774), .Y(n1144) );
OAI21XLTS U2667 ( .A0(n3698), .A1(n1772), .B0(n2506), .Y(n1145) );
OAI21XLTS U2668 ( .A0(n3700), .A1(n1772), .B0(n1842), .Y(n1147) );
OAI21XLTS U2669 ( .A0(n3746), .A1(n2511), .B0(n1838), .Y(n1148) );
OAI21XLTS U2670 ( .A0(n3738), .A1(n2511), .B0(n2494), .Y(n1149) );
OAI21XLTS U2671 ( .A0(n3742), .A1(n2511), .B0(n1844), .Y(n1151) );
OAI21XLTS U2672 ( .A0(n3750), .A1(n2511), .B0(n2455), .Y(n1154) );
OAI21XLTS U2673 ( .A0(n3694), .A1(n2511), .B0(n2467), .Y(n1156) );
NAND2X1TS U2674 ( .A(n1674), .B(n1613), .Y(n1689) );
NAND2X4TS U2675 ( .A(n3375), .B(n1975), .Y(n2291) );
OAI211X1TS U2676 ( .A0(n1607), .A1(n3395), .B0(n2313), .C0(n2312), .Y(n2314)
);
OAI21X2TS U2677 ( .A0(n2279), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[107]), .B0(n2278), .Y(n3395) );
OAI21X2TS U2678 ( .A0(n2279), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[102]), .B0(n2278), .Y(n2617) );
NAND2X4TS U2679 ( .A(n2185), .B(n2184), .Y(n2278) );
OAI211X1TS U2680 ( .A0(n1606), .A1(n2620), .B0(n2332), .C0(n2331), .Y(n2333)
);
OAI21X2TS U2681 ( .A0(n2279), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[105]), .B0(n2278), .Y(n2620) );
OAI211X1TS U2682 ( .A0(n1606), .A1(n2626), .B0(n2309), .C0(n2308), .Y(n2310)
);
OAI21X2TS U2683 ( .A0(n2279), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[104]), .B0(n2278), .Y(n2626) );
OAI211X1TS U2684 ( .A0(n1605), .A1(n2632), .B0(n2322), .C0(n2321), .Y(n2323)
);
OAI21X2TS U2685 ( .A0(n2279), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[106]), .B0(n2278), .Y(n2632) );
OAI211X1TS U2686 ( .A0(n1605), .A1(n2636), .B0(n2327), .C0(n2326), .Y(n2328)
);
OAI21X2TS U2687 ( .A0(n2279), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[108]), .B0(n2278), .Y(n2636) );
OAI211X1TS U2688 ( .A0(n1607), .A1(n2629), .B0(n2318), .C0(n2317), .Y(n2319)
);
OAI21X2TS U2689 ( .A0(n2279), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[109]), .B0(n2278), .Y(n2629) );
AOI22X2TS U2690 ( .A0(n1845), .A1(FSM_selector_C), .B0(n1920), .B1(n3412),
.Y(n1974) );
INVX2TS U2691 ( .A(n1912), .Y(n1845) );
NOR2X4TS U2692 ( .A(n2256), .B(n2167), .Y(n2303) );
OAI211X1TS U2693 ( .A0(n1605), .A1(n2638), .B0(n2205), .C0(n2204), .Y(n2621)
);
AOI211X2TS U2694 ( .A0(n1970), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[109]), .B0(n2282), .C0(
n2203), .Y(n2638) );
OAI211X1TS U2695 ( .A0(n1606), .A1(n2608), .B0(n2270), .C0(n2269), .Y(n2627)
);
AOI211X2TS U2696 ( .A0(n1970), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[103]), .B0(n2282), .C0(
n2268), .Y(n2608) );
AOI222X1TS U2697 ( .A0(n2099), .A1(n1597), .B0(n2073), .B1(n2120), .C0(n2129), .C1(n2054), .Y(n2139) );
OAI2BB1X2TS U2698 ( .A0N(Add_Subt_result[33]), .A1N(n3556), .B0(n2028), .Y(
n2129) );
INVX2TS U2699 ( .A(n3421), .Y(n1601) );
INVX2TS U2700 ( .A(n1601), .Y(n1602) );
INVX2TS U2701 ( .A(n1574), .Y(n1603) );
OAI21X4TS U2702 ( .A0(n1615), .A1(n3787), .B0(n2109), .Y(n3532) );
AOI22X2TS U2703 ( .A0(n2112), .A1(n2111), .B0(n3502), .B1(n2110), .Y(n3510)
);
AOI222X1TS U2704 ( .A0(n3501), .A1(n2121), .B0(n3502), .B1(n2128), .C0(n2073), .C1(n3374), .Y(n2117) );
OAI21X2TS U2705 ( .A0(n2108), .A1(n3786), .B0(n2072), .Y(n3502) );
NOR2X4TS U2706 ( .A(n1599), .B(n2167), .Y(n2346) );
OAI21XLTS U2707 ( .A0(n2096), .A1(n3503), .B0(n2095), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[45]) );
AOI21X2TS U2708 ( .A0(n2183), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[96]), .B0(n2164), .Y(n2598)
);
AOI21X2TS U2709 ( .A0(n2183), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[97]), .B0(n2171), .Y(n2600)
);
AOI21X2TS U2710 ( .A0(n2183), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[95]), .B0(n2154), .Y(n2260)
);
AOI21X2TS U2711 ( .A0(n2183), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[94]), .B0(n2182), .Y(n2247)
);
NOR2X1TS U2712 ( .A(Add_Subt_result[17]), .B(Add_Subt_result[18]), .Y(n1823)
);
NOR4X1TS U2713 ( .A(Add_Subt_result[17]), .B(Add_Subt_result[18]), .C(
Add_Subt_result[14]), .D(Add_Subt_result[16]), .Y(n1830) );
OAI21XLTS U2714 ( .A0(Add_Subt_result[29]), .A1(n1811), .B0(n3329), .Y(n1813) );
AOI31XLTS U2715 ( .A0(n3303), .A1(Add_Subt_result[19]), .A2(n3794), .B0(
n3302), .Y(n3304) );
OAI221X1TS U2716 ( .A0(n3683), .A1(intDY[2]), .B0(n3758), .B1(intDY[0]),
.C0(n2402), .Y(n2405) );
OAI221X1TS U2717 ( .A0(n3734), .A1(intDY[29]), .B0(n3685), .B1(intDY[30]),
.C0(n2392), .Y(n2399) );
AOI32X1TS U2718 ( .A0(n3763), .A1(n1660), .A2(intDY[18]), .B0(intDY[19]),
.B1(n3693), .Y(n1661) );
OAI221XLTS U2719 ( .A0(n3693), .A1(intDY[19]), .B0(n3736), .B1(intDY[20]),
.C0(n2387), .Y(n2388) );
AOI221X1TS U2720 ( .A0(n3701), .A1(intDY[34]), .B0(intDY[33]), .B1(n3748),
.C0(n2370), .Y(n2373) );
OAI221XLTS U2721 ( .A0(n3754), .A1(intDY[31]), .B0(n3721), .B1(intDY[32]),
.C0(n2393), .Y(n2398) );
AOI32X1TS U2722 ( .A0(n3867), .A1(n1699), .A2(intDY[58]), .B0(intDY[59]),
.B1(n3697), .Y(n1700) );
AOI221X1TS U2723 ( .A0(n3866), .A1(intDY[60]), .B0(intDY[59]), .B1(n3697),
.C0(n2355), .Y(n2365) );
OAI221X1TS U2724 ( .A0(n3735), .A1(intDY[21]), .B0(n3686), .B1(intDY[22]),
.C0(n2384), .Y(n2391) );
AOI32X1TS U2725 ( .A0(n3762), .A1(n1678), .A2(intDY[26]), .B0(intDY[27]),
.B1(n3692), .Y(n1679) );
OAI221XLTS U2726 ( .A0(n3692), .A1(intDY[27]), .B0(n3724), .B1(intDY[28]),
.C0(n2395), .Y(n2396) );
OAI221XLTS U2727 ( .A0(n3753), .A1(intDY[11]), .B0(n3725), .B1(intDY[12]),
.C0(n2411), .Y(n2412) );
OA22X1TS U2728 ( .A0(n3687), .A1(intDY[14]), .B0(n3756), .B1(intDY[15]), .Y(
n1651) );
OAI21XLTS U2729 ( .A0(intDY[15]), .A1(n3756), .B0(intDY[14]), .Y(n1647) );
OAI221X1TS U2730 ( .A0(n3720), .A1(intDY[13]), .B0(n3687), .B1(intDY[14]),
.C0(n2408), .Y(n2415) );
OAI221X1TS U2731 ( .A0(n3752), .A1(intDY[17]), .B0(n3763), .B1(intDY[18]),
.C0(n2386), .Y(n2389) );
AOI32X1TS U2732 ( .A0(n3761), .A1(n1753), .A2(intDY[50]), .B0(intDY[51]),
.B1(n3694), .Y(n1754) );
OAI221X1TS U2733 ( .A0(n3750), .A1(intDY[49]), .B0(n3761), .B1(intDY[50]),
.C0(n2358), .Y(n2361) );
OAI221X1TS U2734 ( .A0(n3759), .A1(intDY[53]), .B0(n3684), .B1(intDY[54]),
.C0(n2356), .Y(n2363) );
AOI221X1TS U2735 ( .A0(n3749), .A1(intDY[36]), .B0(intDY[35]), .B1(n3747),
.C0(n2371), .Y(n2372) );
OAI221XLTS U2736 ( .A0(n3760), .A1(intDY[55]), .B0(n3726), .B1(intDY[56]),
.C0(n2357), .Y(n2362) );
OAI221XLTS U2737 ( .A0(n3755), .A1(intDY[23]), .B0(n3723), .B1(intDY[24]),
.C0(n2385), .Y(n2390) );
AOI221X1TS U2738 ( .A0(n3742), .A1(intDY[46]), .B0(intDY[45]), .B1(n3745),
.C0(n2376), .Y(n2383) );
OAI221X1TS U2739 ( .A0(n3751), .A1(intDY[25]), .B0(n3762), .B1(intDY[26]),
.C0(n2394), .Y(n2397) );
AOI221X1TS U2740 ( .A0(n3867), .A1(intDY[58]), .B0(intDY[57]), .B1(n3868),
.C0(n2354), .Y(n2366) );
BUFX12TS U2741 ( .A(n1853), .Y(n1604) );
OAI221X1TS U2742 ( .A0(n3681), .A1(intDY[5]), .B0(n3717), .B1(intDY[6]),
.C0(n2400), .Y(n2407) );
OAI21X1TS U2743 ( .A0(n2877), .A1(n2876), .B0(n2875), .Y(n2878) );
OAI21X2TS U2744 ( .A0(n3025), .A1(n2865), .B0(n2877), .Y(n2910) );
AOI222X4TS U2745 ( .A0(n2134), .A1(n2121), .B0(n2129), .B1(n2120), .C0(n2067), .C1(n2119), .Y(n2037) );
OAI211XLTS U2746 ( .A0(n3520), .A1(n2153), .B0(n2152), .C0(n2151), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[19]) );
NOR2X2TS U2747 ( .A(n2807), .B(n2806), .Y(n3106) );
NOR2X2TS U2748 ( .A(n2702), .B(n2701), .Y(n3234) );
CLKINVX3TS U2749 ( .A(rst), .Y(n1980) );
INVX2TS U2750 ( .A(n2167), .Y(n1605) );
INVX2TS U2751 ( .A(n2167), .Y(n1606) );
INVX2TS U2752 ( .A(n1966), .Y(n1607) );
NOR2X4TS U2753 ( .A(n3727), .B(FSM_selector_B[1]), .Y(n1860) );
OAI21X2TS U2754 ( .A0(n2279), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[103]), .B0(n2278), .Y(n2623) );
NAND2X1TS U2755 ( .A(n1608), .B(n1609), .Y(n2602) );
NAND2X1TS U2756 ( .A(n1573), .B(n1575), .Y(n1608) );
NAND2X1TS U2757 ( .A(n1573), .B(n2184), .Y(n1609) );
OAI21XLTS U2758 ( .A0(n3413), .A1(n3412), .B0(FS_Module_state_reg[3]), .Y(
n3414) );
OAI21X2TS U2759 ( .A0(beg_FSM), .A1(n1360), .B0(n2645), .Y(n3413) );
AOI31XLTS U2760 ( .A0(n2428), .A1(n3407), .A2(n2427), .B0(n3413), .Y(n1560)
);
AOI21X2TS U2761 ( .A0(FSM_selector_C), .A1(n1973), .B0(n2643), .Y(n3407) );
OAI211XLTS U2762 ( .A0(Add_Subt_result[42]), .A1(Add_Subt_result[40]), .B0(
n3314), .C0(n3812), .Y(n3297) );
NOR2X4TS U2763 ( .A(n3293), .B(FS_Module_state_reg[1]), .Y(n3439) );
AOI222X4TS U2764 ( .A0(n2570), .A1(DMP[39]), .B0(n2553), .B1(intDX[39]),
.C0(intDY[39]), .C1(n2552), .Y(n2536) );
AOI22X2TS U2765 ( .A0(n2112), .A1(n3512), .B0(n2111), .B1(n2110), .Y(n3518)
);
OAI2BB1X2TS U2766 ( .A0N(Add_Subt_result[26]), .A1N(n3556), .B0(n2098), .Y(
n3512) );
CLKXOR2X2TS U2767 ( .A(n1889), .B(n1885), .Y(n1900) );
OAI2BB1X2TS U2768 ( .A0N(Add_Subt_result[4]), .A1N(n3635), .B0(n3616), .Y(
n3662) );
OAI211XLTS U2769 ( .A0(n2629), .A1(n1592), .B0(n2272), .C0(n2271), .Y(n1563)
);
OAI21X2TS U2770 ( .A0(n2108), .A1(n3789), .B0(n2027), .Y(n2073) );
OAI211XLTS U2771 ( .A0(n2620), .A1(n1592), .B0(n2197), .C0(n2196), .Y(n1492)
);
OAI211XLTS U2772 ( .A0(n2632), .A1(n1592), .B0(n2277), .C0(n2276), .Y(n1493)
);
OAI211XLTS U2773 ( .A0(n2613), .A1(n1600), .B0(n2334), .C0(n1582), .Y(n1478)
);
OAI211XLTS U2774 ( .A0(n2609), .A1(n1600), .B0(n2329), .C0(n1582), .Y(n1475)
);
OAI21XLTS U2775 ( .A0(n2223), .A1(n1600), .B0(n2219), .Y(n1472) );
NOR3X2TS U2776 ( .A(n3445), .B(overflow_flag), .C(underflow_flag), .Y(n3457)
);
AOI211X2TS U2777 ( .A0(n2262), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[92]), .B0(n2282), .C0(n2198), .Y(n2612) );
AOI211X2TS U2778 ( .A0(n2262), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[91]), .B0(n2282), .C0(n2193), .Y(n2614) );
AOI211X2TS U2779 ( .A0(n2262), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[89]), .B0(n2282), .C0(n2261), .Y(n2604) );
AOI211X2TS U2780 ( .A0(n2262), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[88]), .B0(n2282), .C0(n2281), .Y(n2610) );
AOI211X2TS U2781 ( .A0(n2262), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[90]), .B0(n2282), .C0(n2273), .Y(n2606) );
AOI21X4TS U2782 ( .A0(exp_oper_result[0]), .A1(n3727), .B0(n1932), .Y(n2112)
);
NAND2X1TS U2783 ( .A(n1960), .B(exp_oper_result[3]), .Y(n1961) );
NAND2X1TS U2784 ( .A(n1963), .B(exp_oper_result[4]), .Y(n1958) );
OR2X2TS U2785 ( .A(n1829), .B(Add_Subt_result[13]), .Y(n3351) );
NOR2X2TS U2786 ( .A(n3425), .B(Add_Subt_result[41]), .Y(n3356) );
OAI2BB1X2TS U2787 ( .A0N(Add_Subt_result[32]), .A1N(n3657), .B0(n2026), .Y(
n2099) );
OAI21XLTS U2788 ( .A0(n3789), .A1(Add_Subt_result[32]), .B0(n3702), .Y(n3330) );
NOR2XLTS U2789 ( .A(Add_Subt_result[34]), .B(Add_Subt_result[32]), .Y(n3342)
);
NOR3X2TS U2790 ( .A(n1812), .B(Add_Subt_result[21]), .C(Add_Subt_result[22]),
.Y(n3303) );
OAI221X1TS U2791 ( .A0(n3722), .A1(intDY[9]), .B0(n3682), .B1(intDY[10]),
.C0(n2410), .Y(n2413) );
OAI221XLTS U2792 ( .A0(n3694), .A1(intDY[51]), .B0(n3719), .B1(intDY[52]),
.C0(n2359), .Y(n2360) );
AOI222X4TS U2793 ( .A0(n2573), .A1(DMP[51]), .B0(n2523), .B1(intDY[51]),
.C0(n2516), .C1(intDX[51]), .Y(n2484) );
AOI222X4TS U2794 ( .A0(n2541), .A1(DMP[28]), .B0(n2547), .B1(intDX[28]),
.C0(intDY[28]), .C1(n2529), .Y(n2557) );
OAI221XLTS U2795 ( .A0(n3713), .A1(intDY[7]), .B0(n3764), .B1(intDY[8]),
.C0(n2401), .Y(n2406) );
NOR2X1TS U2796 ( .A(n3751), .B(intDY[25]), .Y(n1676) );
AOI222X4TS U2797 ( .A0(n2585), .A1(DMP[25]), .B0(n2448), .B1(intDX[25]),
.C0(intDY[25]), .C1(n2529), .Y(n2564) );
NOR2X1TS U2798 ( .A(n3752), .B(intDY[17]), .Y(n1658) );
NOR2X1TS U2799 ( .A(n3868), .B(intDY[57]), .Y(n1697) );
NOR2X1TS U2800 ( .A(n3753), .B(intDY[11]), .Y(n1638) );
OAI21XLTS U2801 ( .A0(intDY[21]), .A1(n3735), .B0(intDY[20]), .Y(n1657) );
OAI21XLTS U2802 ( .A0(intDY[13]), .A1(n3720), .B0(intDY[12]), .Y(n1637) );
OAI21XLTS U2803 ( .A0(intDY[29]), .A1(n3734), .B0(intDY[28]), .Y(n1675) );
AOI222X4TS U2804 ( .A0(n2579), .A1(DMP[29]), .B0(n2448), .B1(intDX[29]),
.C0(intDY[29]), .C1(n2529), .Y(n2586) );
OA22X1TS U2805 ( .A0(n3686), .A1(intDY[22]), .B0(n3755), .B1(intDY[23]), .Y(
n1669) );
OA22X1TS U2806 ( .A0(n3700), .A1(intDY[42]), .B0(n3746), .B1(intDY[43]), .Y(
n1721) );
AOI221X1TS U2807 ( .A0(n3738), .A1(intDY[44]), .B0(intDY[43]), .B1(n3746),
.C0(n2379), .Y(n2380) );
OA22X1TS U2808 ( .A0(n3701), .A1(intDY[34]), .B0(n3747), .B1(intDY[35]), .Y(
n1736) );
OA22X1TS U2809 ( .A0(n3685), .A1(intDY[30]), .B0(n3754), .B1(intDY[31]), .Y(
n1687) );
AOI222X4TS U2810 ( .A0(n2593), .A1(DMP[31]), .B0(n2448), .B1(intDX[31]),
.C0(intDY[31]), .C1(n2529), .Y(n2581) );
OAI21XLTS U2811 ( .A0(intDY[33]), .A1(n3748), .B0(intDY[32]), .Y(n1733) );
AOI222X4TS U2812 ( .A0(n2570), .A1(DMP[33]), .B0(n2448), .B1(intDX[33]),
.C0(intDY[33]), .C1(n2529), .Y(n2571) );
OR3X1TS U2813 ( .A(Add_Subt_result[42]), .B(Add_Subt_result[43]), .C(
Add_Subt_result[47]), .Y(n1610) );
NOR4X1TS U2814 ( .A(n1682), .B(n1681), .C(n1673), .D(n1676), .Y(n1613) );
OR2X2TS U2815 ( .A(n2643), .B(n1973), .Y(n1957) );
INVX2TS U2816 ( .A(n2262), .Y(n2184) );
OAI21XLTS U2817 ( .A0(intDX[1]), .A1(n3705), .B0(intDX[0]), .Y(n1622) );
OAI21XLTS U2818 ( .A0(intDY[3]), .A1(n3757), .B0(intDY[2]), .Y(n1625) );
OAI21XLTS U2819 ( .A0(intDY[35]), .A1(n3747), .B0(intDY[34]), .Y(n1734) );
OAI21XLTS U2820 ( .A0(intDY[41]), .A1(n3741), .B0(intDY[40]), .Y(n1718) );
NOR2X1TS U2821 ( .A(n3745), .B(intDY[45]), .Y(n1716) );
NOR2XLTS U2822 ( .A(Add_Subt_result[20]), .B(Add_Subt_result[15]), .Y(n1786)
);
NAND2X1TS U2823 ( .A(n3136), .B(n2764), .Y(n2766) );
NOR2XLTS U2824 ( .A(n3307), .B(Add_Subt_result[47]), .Y(n3296) );
NOR2X1TS U2825 ( .A(n3225), .B(n3227), .Y(n2708) );
NAND2X1TS U2826 ( .A(n3066), .B(n2776), .Y(n3055) );
NOR2XLTS U2827 ( .A(n2696), .B(n3765), .Y(n2662) );
INVX2TS U2828 ( .A(n3196), .Y(n3198) );
NAND2X1TS U2829 ( .A(n1927), .B(n2426), .Y(n1912) );
OR2X1TS U2830 ( .A(n2937), .B(n2936), .Y(n2942) );
BUFX3TS U2831 ( .A(n2547), .Y(n2509) );
BUFX3TS U2832 ( .A(n2547), .Y(n2524) );
OAI21XLTS U2833 ( .A0(n3390), .A1(n3805), .B0(n2230), .Y(n2231) );
AND2X2TS U2834 ( .A(n1931), .B(n1930), .Y(n3519) );
XNOR2X1TS U2835 ( .A(n3097), .B(n3096), .Y(n3099) );
INVX2TS U2836 ( .A(n1940), .Y(n3520) );
AND3X1TS U2837 ( .A(n1950), .B(n1949), .C(n1948), .Y(n2025) );
AND3X1TS U2838 ( .A(n1939), .B(n1938), .C(n1937), .Y(n2096) );
OAI211XLTS U2839 ( .A0(n2605), .A1(n1600), .B0(n2324), .C0(n1582), .Y(n1477)
);
OAI211XLTS U2840 ( .A0(n2637), .A1(n1600), .B0(n2342), .C0(n1582), .Y(n1480)
);
OAI2BB1X1TS U2841 ( .A0N(n3712), .A1N(intDX[5]), .B0(intDY[4]), .Y(n1620) );
OAI22X1TS U2842 ( .A0(intDX[4]), .A1(n1620), .B0(n3712), .B1(intDX[5]), .Y(
n1631) );
OAI2BB1X1TS U2843 ( .A0N(n3680), .A1N(intDX[7]), .B0(intDY[6]), .Y(n1621) );
OAI22X1TS U2844 ( .A0(intDX[6]), .A1(n1621), .B0(n3680), .B1(intDX[7]), .Y(
n1630) );
AOI2BB2X1TS U2845 ( .B0(intDX[1]), .B1(n3705), .A0N(intDY[0]), .A1N(n1622),
.Y(n1623) );
OAI211X1TS U2846 ( .A0(n3757), .A1(intDY[3]), .B0(n1624), .C0(n1623), .Y(
n1627) );
AOI2BB2X2TS U2847 ( .B0(intDY[3]), .B1(n3757), .A0N(intDX[2]), .A1N(n1625),
.Y(n1626) );
AOI22X1TS U2848 ( .A0(intDX[7]), .A1(n3680), .B0(intDX[6]), .B1(n3732), .Y(
n1628) );
OAI32X1TS U2849 ( .A0(n1631), .A1(n1630), .A2(n1629), .B0(n1628), .B1(n1630),
.Y(n1636) );
OAI211X4TS U2850 ( .A0(intDY[12]), .A1(n3725), .B0(n1651), .C0(n1632), .Y(
n1645) );
AOI21X1TS U2851 ( .A0(intDX[10]), .A1(n3709), .B0(n1638), .Y(n1643) );
OAI2BB2XLTS U2852 ( .B0(intDX[12]), .B1(n1637), .A0N(intDY[13]), .A1N(n3720),
.Y(n1650) );
AOI22X1TS U2853 ( .A0(intDY[11]), .A1(n3753), .B0(intDY[10]), .B1(n1639),
.Y(n1646) );
OAI2BB2X1TS U2854 ( .B0(n1646), .B1(n1645), .A0N(n1644), .A1N(n1643), .Y(
n1649) );
OAI2BB2XLTS U2855 ( .B0(intDX[14]), .B1(n1647), .A0N(intDY[15]), .A1N(n3756),
.Y(n1648) );
AOI211X1TS U2856 ( .A0(n1651), .A1(n1650), .B0(n1649), .C0(n1648), .Y(n1655)
);
OAI21X1TS U2857 ( .A0(intDY[18]), .A1(n3763), .B0(n1660), .Y(n1664) );
OAI2BB1X4TS U2858 ( .A0N(n1656), .A1N(n1655), .B0(n1654), .Y(n1671) );
OAI2BB2XLTS U2859 ( .B0(intDX[20]), .B1(n1657), .A0N(intDY[21]), .A1N(n3735),
.Y(n1668) );
AOI22X1TS U2860 ( .A0(n1659), .A1(intDY[16]), .B0(intDY[17]), .B1(n3752),
.Y(n1662) );
OAI32X1TS U2861 ( .A0(n1664), .A1(n1663), .A2(n1662), .B0(n1661), .B1(n1663),
.Y(n1667) );
OAI2BB2XLTS U2862 ( .B0(intDX[22]), .B1(n1665), .A0N(intDY[23]), .A1N(n3755),
.Y(n1666) );
AOI211X1TS U2863 ( .A0(n1669), .A1(n1668), .B0(n1667), .C0(n1666), .Y(n1670)
);
OAI21X1TS U2864 ( .A0(intDY[26]), .A1(n3762), .B0(n1678), .Y(n1682) );
NOR2BX1TS U2865 ( .AN(intDX[24]), .B(intDY[24]), .Y(n1673) );
AOI22X1TS U2866 ( .A0(n1677), .A1(intDY[24]), .B0(intDY[25]), .B1(n3751),
.Y(n1680) );
OAI32X1TS U2867 ( .A0(n1682), .A1(n1681), .A2(n1680), .B0(n1679), .B1(n1681),
.Y(n1685) );
OAI22X1TS U2868 ( .A0(n3760), .A1(intDY[55]), .B0(intDY[54]), .B1(n3684),
.Y(n1748) );
NOR2BX1TS U2869 ( .AN(intDX[56]), .B(intDY[56]), .Y(n1691) );
NAND2X1TS U2870 ( .A(n3704), .B(intDX[61]), .Y(n1703) );
OAI211X1TS U2871 ( .A0(intDY[60]), .A1(n3866), .B0(n1707), .C0(n1703), .Y(
n1709) );
OAI21X1TS U2872 ( .A0(intDY[58]), .A1(n3867), .B0(n1699), .Y(n1701) );
NOR4X2TS U2873 ( .A(n1691), .B(n1697), .C(n1709), .D(n1701), .Y(n1759) );
NOR2X1TS U2874 ( .A(n3750), .B(intDY[49]), .Y(n1751) );
OAI21X1TS U2875 ( .A0(intDY[50]), .A1(n3761), .B0(n1753), .Y(n1757) );
AOI211X1TS U2876 ( .A0(intDX[48]), .A1(n3707), .B0(n1751), .C0(n1757), .Y(
n1692) );
NAND2X1TS U2877 ( .A(n1611), .B(intDX[37]), .Y(n1730) );
OAI211X1TS U2878 ( .A0(intDY[36]), .A1(n3749), .B0(n1741), .C0(n1730), .Y(
n1732) );
OAI21X1TS U2879 ( .A0(intDY[46]), .A1(n3742), .B0(n1715), .Y(n1725) );
NOR4X1TS U2880 ( .A(n1767), .B(n1732), .C(n1765), .D(n1696), .Y(n1712) );
AOI22X1TS U2881 ( .A0(intDY[57]), .A1(n3868), .B0(intDY[56]), .B1(n1698),
.Y(n1702) );
NOR2BX1TS U2882 ( .AN(n1715), .B(intDX[46]), .Y(n1729) );
AOI22X1TS U2883 ( .A0(intDY[45]), .A1(n3745), .B0(intDY[44]), .B1(n1717),
.Y(n1726) );
OAI2BB2XLTS U2884 ( .B0(intDX[40]), .B1(n1718), .A0N(intDY[41]), .A1N(n3741),
.Y(n1722) );
OAI2BB2XLTS U2885 ( .B0(intDX[42]), .B1(n1719), .A0N(intDY[43]), .A1N(n3746),
.Y(n1720) );
AOI32X1TS U2886 ( .A0(n1723), .A1(n1722), .A2(n1721), .B0(n1720), .B1(n1723),
.Y(n1724) );
NOR2BX1TS U2887 ( .AN(intDY[47]), .B(intDX[47]), .Y(n1727) );
AOI211X1TS U2888 ( .A0(intDY[46]), .A1(n1729), .B0(n1728), .C0(n1727), .Y(
n1766) );
OAI2BB2XLTS U2889 ( .B0(intDX[32]), .B1(n1733), .A0N(intDY[33]), .A1N(n3748),
.Y(n1737) );
OAI2BB2XLTS U2890 ( .B0(intDX[34]), .B1(n1734), .A0N(intDY[35]), .A1N(n3747),
.Y(n1735) );
AOI32X1TS U2891 ( .A0(n1738), .A1(n1737), .A2(n1736), .B0(n1735), .B1(n1738),
.Y(n1739) );
NOR2BX1TS U2892 ( .AN(intDY[39]), .B(intDX[39]), .Y(n1745) );
NOR3X1TS U2893 ( .A(n3711), .B(n1742), .C(intDX[38]), .Y(n1744) );
INVX2TS U2894 ( .A(n1767), .Y(n1743) );
OAI31X1TS U2895 ( .A0(n1746), .A1(n1745), .A2(n1744), .B0(n1743), .Y(n1764)
);
INVX2TS U2896 ( .A(n1750), .Y(n1756) );
AOI22X1TS U2897 ( .A0(intDY[49]), .A1(n3750), .B0(intDY[48]), .B1(n1752),
.Y(n1755) );
OAI32X1TS U2898 ( .A0(n1757), .A1(n1756), .A2(n1755), .B0(n1754), .B1(n1756),
.Y(n1761) );
OAI2BB2XLTS U2899 ( .B0(intDX[54]), .B1(n1758), .A0N(intDY[55]), .A1N(n3760),
.Y(n1760) );
OAI31X1TS U2900 ( .A0(n1762), .A1(n1761), .A2(n1760), .B0(n1759), .Y(n1763)
);
INVX6TS U2901 ( .A(n2436), .Y(n2438) );
NOR2X2TS U2902 ( .A(n3785), .B(FS_Module_state_reg[2]), .Y(n3412) );
INVX2TS U2903 ( .A(n2424), .Y(n2640) );
INVX2TS U2904 ( .A(n2449), .Y(n2504) );
AOI22X1TS U2905 ( .A0(n2509), .A1(intDY[45]), .B0(DmP[45]), .B1(n1590), .Y(
n1770) );
INVX2TS U2906 ( .A(n2449), .Y(n2500) );
AOI22X1TS U2907 ( .A0(n2505), .A1(intDY[36]), .B0(DmP[36]), .B1(n2500), .Y(
n1771) );
INVX4TS U2908 ( .A(n2523), .Y(n2502) );
AOI22X1TS U2909 ( .A0(n2505), .A1(intDY[29]), .B0(DmP[29]), .B1(n1589), .Y(
n1773) );
AOI22X1TS U2910 ( .A0(n2509), .A1(intDY[39]), .B0(DmP[39]), .B1(n2512), .Y(
n1774) );
AOI22X1TS U2911 ( .A0(n2505), .A1(intDY[31]), .B0(DmP[31]), .B1(n1589), .Y(
n1775) );
AOI22X1TS U2912 ( .A0(n2509), .A1(intDY[41]), .B0(DmP[41]), .B1(n1589), .Y(
n1776) );
NOR2X1TS U2913 ( .A(Add_Subt_result[45]), .B(Add_Subt_result[44]), .Y(n1777)
);
NAND2X2TS U2914 ( .A(n3715), .B(n1777), .Y(n3307) );
NOR2X1TS U2915 ( .A(n1610), .B(n3307), .Y(n1778) );
NOR2X2TS U2916 ( .A(Add_Subt_result[50]), .B(Add_Subt_result[49]), .Y(n3357)
);
NAND2X2TS U2917 ( .A(n3729), .B(n3357), .Y(n3339) );
NOR2X4TS U2918 ( .A(n3340), .B(n3339), .Y(n3428) );
NAND2X4TS U2919 ( .A(n1778), .B(n3428), .Y(n3425) );
NOR2X2TS U2920 ( .A(Add_Subt_result[40]), .B(Add_Subt_result[39]), .Y(n3426)
);
NOR2X1TS U2921 ( .A(Add_Subt_result[38]), .B(Add_Subt_result[37]), .Y(n1808)
);
NOR2X4TS U2922 ( .A(n1796), .B(Add_Subt_result[36]), .Y(n3434) );
NOR2X2TS U2923 ( .A(Add_Subt_result[32]), .B(Add_Subt_result[31]), .Y(n1803)
);
NOR2X1TS U2924 ( .A(Add_Subt_result[24]), .B(Add_Subt_result[23]), .Y(n1802)
);
NAND2X1TS U2925 ( .A(n1803), .B(n1802), .Y(n1784) );
NAND2X1TS U2926 ( .A(n3691), .B(n1780), .Y(n1811) );
NAND2X1TS U2927 ( .A(n1782), .B(n1781), .Y(n1783) );
NOR3X1TS U2928 ( .A(n1784), .B(n1811), .C(n1783), .Y(n1785) );
NOR2XLTS U2929 ( .A(Add_Subt_result[21]), .B(Add_Subt_result[19]), .Y(n1787)
);
NAND2X2TS U2930 ( .A(n3349), .B(n3779), .Y(n1829) );
NOR2X1TS U2931 ( .A(Add_Subt_result[12]), .B(Add_Subt_result[11]), .Y(n1824)
);
INVX2TS U2932 ( .A(n1824), .Y(n1790) );
NOR2X4TS U2933 ( .A(n3351), .B(n1790), .Y(n3320) );
NOR2X1TS U2934 ( .A(Add_Subt_result[8]), .B(Add_Subt_result[7]), .Y(n1821)
);
NAND2X1TS U2935 ( .A(n3678), .B(n1821), .Y(n1791) );
NOR2X1TS U2936 ( .A(Add_Subt_result[4]), .B(Add_Subt_result[3]), .Y(n1828)
);
NAND2X1TS U2937 ( .A(n1828), .B(n3781), .Y(n1792) );
NOR2X2TS U2938 ( .A(n3306), .B(n1792), .Y(n1819) );
NOR2X1TS U2939 ( .A(Add_Subt_result[2]), .B(Add_Subt_result[1]), .Y(n1795)
);
INVX2TS U2940 ( .A(n1795), .Y(n1816) );
INVX2TS U2941 ( .A(n3331), .Y(n1805) );
NOR2X2TS U2942 ( .A(n1805), .B(n1793), .Y(n3329) );
OR2X1TS U2943 ( .A(n1811), .B(Add_Subt_result[27]), .Y(n1794) );
OR2X2TS U2944 ( .A(n3316), .B(n1794), .Y(n3311) );
INVX2TS U2945 ( .A(n3316), .Y(n3366) );
INVX2TS U2946 ( .A(n3303), .Y(n3299) );
NOR2X1TS U2947 ( .A(Add_Subt_result[19]), .B(Add_Subt_result[20]), .Y(n1822)
);
AOI21X1TS U2948 ( .A0(n3793), .A1(n3690), .B0(n1796), .Y(n1797) );
AOI31XLTS U2949 ( .A0(n3331), .A1(n3702), .A2(n1798), .B0(n1797), .Y(n1799)
);
AOI21X1TS U2950 ( .A0(n3366), .A1(Add_Subt_result[27]), .B0(n1800), .Y(n1801) );
INVX2TS U2951 ( .A(n3311), .Y(n1806) );
AOI2BB2X1TS U2952 ( .B0(n1806), .B1(Add_Subt_result[22]), .A0N(n1805), .A1N(
n1804), .Y(n3322) );
NOR2BX1TS U2953 ( .AN(Add_Subt_result[33]), .B(n3343), .Y(n1810) );
INVX2TS U2954 ( .A(n3426), .Y(n1807) );
NOR3BX1TS U2955 ( .AN(n3356), .B(n1808), .C(n1807), .Y(n1809) );
AOI211X1TS U2956 ( .A0(n3434), .A1(Add_Subt_result[34]), .B0(n1810), .C0(
n1809), .Y(n1814) );
INVX2TS U2957 ( .A(n1812), .Y(n3345) );
NAND2X1TS U2958 ( .A(n3345), .B(Add_Subt_result[21]), .Y(n3301) );
AOI211X1TS U2959 ( .A0(n1819), .A1(n1816), .B0(n3370), .C0(n1815), .Y(n1818)
);
NOR2X1TS U2960 ( .A(n3728), .B(FS_Module_state_reg[2]), .Y(n2644) );
NAND2X1TS U2961 ( .A(n2644), .B(n3688), .Y(n3293) );
INVX2TS U2962 ( .A(n3439), .Y(n3443) );
NAND2X1TS U2963 ( .A(n3443), .B(LZA_output[4]), .Y(n1817) );
NAND3X1TS U2964 ( .A(n1819), .B(Add_Subt_result[1]), .C(n3790), .Y(n3438) );
OAI31X1TS U2965 ( .A0(Add_Subt_result[5]), .A1(Add_Subt_result[6]), .A2(
Add_Subt_result[2]), .B0(n3295), .Y(n1834) );
INVX2TS U2966 ( .A(n1832), .Y(n3319) );
INVX2TS U2967 ( .A(n1821), .Y(n1826) );
NAND2X1TS U2968 ( .A(n3303), .B(n1822), .Y(n3423) );
NAND3X1TS U2969 ( .A(n3368), .B(Add_Subt_result[15]), .C(n3778), .Y(n3435)
);
OAI31X1TS U2970 ( .A0(Add_Subt_result[5]), .A1(n1828), .A2(n3306), .B0(n1827), .Y(n3371) );
INVX2TS U2971 ( .A(n1829), .Y(n3335) );
NAND2X1TS U2972 ( .A(n3335), .B(Add_Subt_result[13]), .Y(n3336) );
AOI22X1TS U2973 ( .A0(n2509), .A1(intDY[43]), .B0(DmP[43]), .B1(n2504), .Y(
n1838) );
AOI22X1TS U2974 ( .A0(n2505), .A1(intDY[35]), .B0(DmP[35]), .B1(n2500), .Y(
n1839) );
AOI22X1TS U2975 ( .A0(n2505), .A1(intDY[33]), .B0(DmP[33]), .B1(n2504), .Y(
n1840) );
AOI22X1TS U2976 ( .A0(n2513), .A1(intDY[3]), .B0(DmP[3]), .B1(n2512), .Y(
n1841) );
AOI22X1TS U2977 ( .A0(n2509), .A1(intDY[42]), .B0(DmP[42]), .B1(n2507), .Y(
n1842) );
AOI22X1TS U2978 ( .A0(n2505), .A1(intDY[34]), .B0(DmP[34]), .B1(n2504), .Y(
n1843) );
AOI22X1TS U2979 ( .A0(n2509), .A1(intDY[46]), .B0(DmP[46]), .B1(n2500), .Y(
n1844) );
NOR2X2TS U2980 ( .A(n3728), .B(n3688), .Y(n1920) );
INVX2TS U2981 ( .A(n1927), .Y(n1846) );
NAND2X1TS U2982 ( .A(n3688), .B(FS_Module_state_reg[3]), .Y(n1914) );
NOR2X2TS U2983 ( .A(n1846), .B(n1914), .Y(n2643) );
NOR2X1TS U2984 ( .A(n3688), .B(FS_Module_state_reg[3]), .Y(n1847) );
INVX2TS U2985 ( .A(n1918), .Y(n1973) );
NOR2X1TS U2986 ( .A(n3410), .B(n1849), .Y(n1850) );
NOR2X1TS U2987 ( .A(n1851), .B(n3714), .Y(n1852) );
NAND3BX4TS U2988 ( .AN(n1957), .B(n1850), .C(n1852), .Y(n1853) );
XOR2X1TS U2989 ( .A(n1604), .B(n1854), .Y(n1867) );
INVX2TS U2990 ( .A(FSM_selector_D), .Y(n2962) );
INVX2TS U2991 ( .A(n1616), .Y(n1960) );
NAND2X1TS U2992 ( .A(n1860), .B(LZA_output[5]), .Y(n1965) );
OAI2BB1X1TS U2993 ( .A0N(DmP[57]), .A1N(n1960), .B0(n1965), .Y(n1855) );
XOR2X1TS U2994 ( .A(n1889), .B(n1855), .Y(n1897) );
NAND2X1TS U2995 ( .A(n1860), .B(LZA_output[4]), .Y(n1959) );
OAI2BB1X1TS U2996 ( .A0N(DmP[56]), .A1N(n1963), .B0(n1959), .Y(n1856) );
XOR2X1TS U2997 ( .A(n1604), .B(n1856), .Y(n1894) );
NAND2X1TS U2998 ( .A(n1860), .B(LZA_output[3]), .Y(n1962) );
OAI2BB1X1TS U2999 ( .A0N(DmP[55]), .A1N(n1960), .B0(n1962), .Y(n1857) );
XOR2X1TS U3000 ( .A(n1889), .B(n1857), .Y(n1870) );
NAND2X1TS U3001 ( .A(n1860), .B(LZA_output[2]), .Y(n1925) );
OAI2BB1X1TS U3002 ( .A0N(DmP[54]), .A1N(n1963), .B0(n1925), .Y(n1858) );
XOR2X1TS U3003 ( .A(n1604), .B(n1858), .Y(n1876) );
NAND2X1TS U3004 ( .A(n1860), .B(LZA_output[1]), .Y(n1931) );
OAI2BB1X1TS U3005 ( .A0N(DmP[53]), .A1N(n1960), .B0(n1931), .Y(n1859) );
XOR2X1TS U3006 ( .A(n1889), .B(n1859), .Y(n1873) );
NAND2X1TS U3007 ( .A(n1860), .B(LZA_output[0]), .Y(n1862) );
NAND2X1TS U3008 ( .A(n3727), .B(FSM_selector_B[1]), .Y(n1861) );
XOR2X1TS U3009 ( .A(n1889), .B(n1864), .Y(n1884) );
ADDFHX4TS U3010 ( .A(n1876), .B(n1875), .CI(n1874), .CO(n1868), .S(n3355) );
ADDFHX2TS U3011 ( .A(n1889), .B(n1878), .CI(n1877), .CO(n1871), .S(n2429) );
OR4X2TS U3012 ( .A(n3373), .B(n3355), .C(n2429), .D(n1974), .Y(n1879) );
NOR4X1TS U3013 ( .A(n3422), .B(n3420), .C(n3327), .D(n1879), .Y(n1898) );
XOR2X1TS U3014 ( .A(n1604), .B(n1880), .Y(n1905) );
XOR2X1TS U3015 ( .A(n1604), .B(n1881), .Y(n1908) );
INVX2TS U3016 ( .A(n1899), .Y(n1887) );
XOR2X4TS U3017 ( .A(n1891), .B(n1890), .Y(n2431) );
ADDFHX4TS U3018 ( .A(n1894), .B(n1893), .CI(n1892), .CO(n1895), .S(n3328) );
ADDFHX4TS U3019 ( .A(n1897), .B(n1896), .CI(n1895), .CO(n1865), .S(n3294) );
XOR2X1TS U3020 ( .A(n1900), .B(n1899), .Y(n1901) );
CLKXOR2X2TS U3021 ( .A(n1902), .B(n1901), .Y(n2433) );
ADDFHX4TS U3022 ( .A(n1905), .B(n1904), .CI(n1903), .CO(n1902), .S(n3418) );
NOR4BX4TS U3023 ( .AN(n1909), .B(n2433), .C(n3418), .D(n3419), .Y(n1910) );
NAND2X1TS U3024 ( .A(n1912), .B(n1911), .Y(n1913) );
BUFX3TS U3025 ( .A(n1913), .Y(n3421) );
NOR3X1TS U3026 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[1]), .C(
FS_Module_state_reg[3]), .Y(n1919) );
NAND2X2TS U3027 ( .A(n1919), .B(n3688), .Y(n1360) );
NAND2X1TS U3028 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[1]),
.Y(n1917) );
NOR2X1TS U3029 ( .A(n1914), .B(n1917), .Y(ready) );
INVX2TS U3030 ( .A(n3413), .Y(n1923) );
OAI211X1TS U3031 ( .A0(sign_final_result), .A1(r_mode[1]), .B0(n1916), .C0(
n1915), .Y(n3411) );
INVX2TS U3032 ( .A(n3166), .Y(n3409) );
NOR2X1TS U3033 ( .A(n1918), .B(FSM_selector_C), .Y(n2642) );
AND2X2TS U3034 ( .A(n1919), .B(FS_Module_state_reg[0]), .Y(n2658) );
CLKBUFX2TS U3035 ( .A(n2658), .Y(n2653) );
BUFX3TS U3036 ( .A(n2653), .Y(n2647) );
AOI211XLTS U3037 ( .A0(n3409), .A1(FS_Module_state_reg[0]), .B0(n2642), .C0(
n2647), .Y(n1921) );
NOR4BX1TS U3038 ( .AN(n1921), .B(n2640), .C(n2425), .D(n3458), .Y(n1922) );
OAI211XLTS U3039 ( .A0(n1923), .A1(n3785), .B0(n1986), .C0(n1922), .Y(n1559)
);
NAND2X1TS U3040 ( .A(n1963), .B(exp_oper_result[2]), .Y(n1924) );
INVX2TS U3041 ( .A(n1940), .Y(n2066) );
NOR3X1TS U3042 ( .A(add_overflow_flag), .B(n3624), .C(FS_Module_state_reg[3]), .Y(n1926) );
INVX2TS U3043 ( .A(n2108), .Y(n2103) );
NAND2X1TS U3044 ( .A(n2087), .B(Add_Subt_result[45]), .Y(n1929) );
BUFX3TS U3045 ( .A(n3530), .Y(n1995) );
BUFX3TS U3046 ( .A(n3677), .Y(n2088) );
AOI22X1TS U3047 ( .A0(n1995), .A1(Add_Subt_result[9]), .B0(DmP[43]), .B1(
n2088), .Y(n1928) );
NAND2X2TS U3048 ( .A(n1929), .B(n1928), .Y(n2077) );
NAND2X1TS U3049 ( .A(n1963), .B(exp_oper_result[1]), .Y(n1930) );
NAND2X1TS U3050 ( .A(n2077), .B(n2043), .Y(n1939) );
NAND2X1TS U3051 ( .A(n2087), .B(Add_Subt_result[46]), .Y(n1934) );
AOI22X1TS U3052 ( .A0(n1995), .A1(Add_Subt_result[8]), .B0(DmP[44]), .B1(
n2088), .Y(n1933) );
NAND2X2TS U3053 ( .A(n1934), .B(n1933), .Y(n3492) );
INVX2TS U3054 ( .A(n2112), .Y(n2110) );
NAND2X1TS U3055 ( .A(n3492), .B(n1597), .Y(n1938) );
NAND2X1TS U3056 ( .A(n3657), .B(Add_Subt_result[47]), .Y(n1936) );
AOI22X1TS U3057 ( .A0(n1995), .A1(Add_Subt_result[7]), .B0(DmP[45]), .B1(
n2088), .Y(n1935) );
NAND2X2TS U3058 ( .A(n1936), .B(n1935), .Y(n3491) );
INVX2TS U3059 ( .A(n1947), .Y(n2054) );
NAND2X1TS U3060 ( .A(n3491), .B(n2054), .Y(n1937) );
INVX2TS U3061 ( .A(n3511), .Y(n3503) );
INVX2TS U3062 ( .A(n2108), .Y(n3657) );
NAND2X1TS U3063 ( .A(n2103), .B(Add_Subt_result[41]), .Y(n1942) );
AOI22X1TS U3064 ( .A0(n1995), .A1(Add_Subt_result[13]), .B0(DmP[39]), .B1(
n2088), .Y(n1941) );
NAND2X2TS U3065 ( .A(n1942), .B(n1941), .Y(n2050) );
INVX2TS U3066 ( .A(n2043), .Y(n1987) );
NAND2X1TS U3067 ( .A(n2050), .B(n2128), .Y(n1950) );
NAND2X1TS U3068 ( .A(n2103), .B(Add_Subt_result[42]), .Y(n1944) );
AOI22X1TS U3069 ( .A0(n1995), .A1(Add_Subt_result[12]), .B0(DmP[40]), .B1(
n2088), .Y(n1943) );
NAND2X2TS U3070 ( .A(n1944), .B(n1943), .Y(n2062) );
NAND2X1TS U3071 ( .A(n2062), .B(n1596), .Y(n1949) );
NAND2X1TS U3072 ( .A(n2103), .B(Add_Subt_result[43]), .Y(n1946) );
AOI22X1TS U3073 ( .A0(n1995), .A1(Add_Subt_result[11]), .B0(DmP[41]), .B1(
n2088), .Y(n1945) );
NAND2X1TS U3074 ( .A(n1946), .B(n1945), .Y(n2049) );
INVX2TS U3075 ( .A(n1947), .Y(n2119) );
NAND2X1TS U3076 ( .A(n2049), .B(n2119), .Y(n1948) );
NOR2X4TS U3077 ( .A(n3519), .B(n2112), .Y(n3374) );
NAND2X2TS U3078 ( .A(n3374), .B(n2178), .Y(n3475) );
NAND2X1TS U3079 ( .A(n2087), .B(Add_Subt_result[48]), .Y(n1952) );
CLKBUFX2TS U3080 ( .A(n3530), .Y(n3656) );
AOI22X1TS U3081 ( .A0(n3656), .A1(Add_Subt_result[6]), .B0(DmP[46]), .B1(
n2088), .Y(n1951) );
NAND2X2TS U3082 ( .A(n1952), .B(n1951), .Y(n3493) );
INVX2TS U3083 ( .A(n3374), .Y(n1953) );
NOR2X2TS U3084 ( .A(n1953), .B(n2178), .Y(n2023) );
NAND2X1TS U3085 ( .A(n3657), .B(Add_Subt_result[44]), .Y(n1955) );
AOI22X1TS U3086 ( .A0(n1995), .A1(Add_Subt_result[10]), .B0(DmP[42]), .B1(
n2088), .Y(n1954) );
NAND2X2TS U3087 ( .A(n1955), .B(n1954), .Y(n2044) );
AOI22X1TS U3088 ( .A0(n3641), .A1(n3493), .B0(n3496), .B1(n2044), .Y(n1956)
);
OAI221XLTS U3089 ( .A0(n2066), .A1(n2096), .B0(n3503), .B1(n2025), .C0(n1956), .Y(Barrel_Shifter_module_Mux_Array_Data_array[41]) );
NOR2X4TS U3090 ( .A(n2344), .B(n3633), .Y(n3398) );
NAND2X1TS U3091 ( .A(n1963), .B(exp_oper_result[5]), .Y(n1964) );
NAND2X1TS U3092 ( .A(n1965), .B(n1964), .Y(n1966) );
OR3X2TS U3093 ( .A(n1968), .B(n1976), .C(n2167), .Y(n3390) );
AND2X4TS U3094 ( .A(n1976), .B(n1968), .Y(n2262) );
NOR2X4TS U3095 ( .A(n2167), .B(n2184), .Y(n2285) );
BUFX3TS U3096 ( .A(n2285), .Y(n2325) );
INVX2TS U3097 ( .A(n1968), .Y(n1975) );
NOR2X4TS U3098 ( .A(n1976), .B(n1975), .Y(n2280) );
NOR2X2TS U3099 ( .A(n2167), .B(n2292), .Y(n3393) );
BUFX3TS U3100 ( .A(n3393), .Y(n2335) );
AOI22X1TS U3101 ( .A0(n2325), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .B0(n2335), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[86]), .Y(n1967) );
OAI21X1TS U3102 ( .A0(n3390), .A1(n3799), .B0(n1967), .Y(n2348) );
INVX2TS U3103 ( .A(n1976), .Y(n1969) );
INVX2TS U3104 ( .A(n1970), .Y(n1971) );
NOR2X2TS U3105 ( .A(n1971), .B(n2167), .Y(n2215) );
AOI22X1TS U3106 ( .A0(n2325), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[86]), .B0(n2335), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[94]), .Y(n1972) );
OAI2BB1X1TS U3107 ( .A0N(n2215), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[102]), .B0(n1972), .Y(n1977) );
AOI21X2TS U3108 ( .A0(n3407), .A1(n1974), .B0(n3714), .Y(n3375) );
INVX2TS U3109 ( .A(n3375), .Y(n3476) );
NOR2X2TS U3110 ( .A(n3476), .B(n1605), .Y(n3391) );
NOR2X4TS U3111 ( .A(n1976), .B(n2291), .Y(n2282) );
NOR3X1TS U3112 ( .A(n1977), .B(n3391), .C(n2282), .Y(n2351) );
BUFX3TS U3113 ( .A(n2596), .Y(n2256) );
INVX2TS U3114 ( .A(n2595), .Y(n2344) );
AOI22X1TS U3115 ( .A0(n2303), .A1(n2345), .B0(n2344), .B1(
Sgf_normalized_result[23]), .Y(n1978) );
CLKBUFX3TS U3116 ( .A(n1980), .Y(n1983) );
BUFX3TS U3117 ( .A(n1983), .Y(n3854) );
BUFX3TS U3118 ( .A(n1980), .Y(n3819) );
BUFX3TS U3119 ( .A(n1980), .Y(n3820) );
CLKBUFX3TS U3120 ( .A(n1980), .Y(n1984) );
BUFX3TS U3121 ( .A(n1984), .Y(n3821) );
CLKBUFX3TS U3122 ( .A(n1980), .Y(n1981) );
BUFX3TS U3123 ( .A(n1981), .Y(n3822) );
CLKBUFX3TS U3124 ( .A(n1980), .Y(n1982) );
BUFX3TS U3125 ( .A(n1982), .Y(n3823) );
BUFX3TS U3126 ( .A(n1982), .Y(n3831) );
BUFX3TS U3127 ( .A(n1983), .Y(n3814) );
BUFX3TS U3128 ( .A(n1984), .Y(n3815) );
BUFX3TS U3129 ( .A(n1984), .Y(n3816) );
BUFX3TS U3130 ( .A(n1984), .Y(n3817) );
CLKBUFX3TS U3131 ( .A(n1980), .Y(n1985) );
BUFX3TS U3132 ( .A(n1985), .Y(n3818) );
BUFX3TS U3133 ( .A(n1981), .Y(n3832) );
BUFX3TS U3134 ( .A(n1981), .Y(n3839) );
BUFX3TS U3135 ( .A(n1981), .Y(n3842) );
BUFX3TS U3136 ( .A(n1982), .Y(n3845) );
BUFX3TS U3137 ( .A(n1982), .Y(n3843) );
BUFX3TS U3138 ( .A(n1981), .Y(n3841) );
BUFX3TS U3139 ( .A(n1981), .Y(n3837) );
BUFX3TS U3140 ( .A(n1981), .Y(n3840) );
BUFX3TS U3141 ( .A(n1981), .Y(n3838) );
BUFX3TS U3142 ( .A(n1984), .Y(n3834) );
BUFX3TS U3143 ( .A(n1985), .Y(n3835) );
BUFX3TS U3144 ( .A(n1980), .Y(n3833) );
BUFX3TS U3145 ( .A(n1985), .Y(n3855) );
BUFX3TS U3146 ( .A(n1985), .Y(n3857) );
BUFX3TS U3147 ( .A(n1985), .Y(n3856) );
BUFX3TS U3148 ( .A(n1983), .Y(n3851) );
BUFX3TS U3149 ( .A(n1983), .Y(n3852) );
BUFX3TS U3150 ( .A(n1984), .Y(n3861) );
BUFX3TS U3151 ( .A(n1982), .Y(n3844) );
BUFX3TS U3152 ( .A(n1985), .Y(n3858) );
BUFX3TS U3153 ( .A(n1980), .Y(n3829) );
CLKBUFX3TS U3154 ( .A(n1984), .Y(n3864) );
BUFX3TS U3155 ( .A(n1983), .Y(n3850) );
BUFX3TS U3156 ( .A(n1984), .Y(n3862) );
BUFX3TS U3157 ( .A(n1980), .Y(n3830) );
BUFX3TS U3158 ( .A(n1983), .Y(n3849) );
BUFX3TS U3159 ( .A(n1981), .Y(n3824) );
BUFX3TS U3160 ( .A(n1983), .Y(n3825) );
BUFX3TS U3161 ( .A(n1984), .Y(n3863) );
BUFX3TS U3162 ( .A(n1982), .Y(n3848) );
BUFX3TS U3163 ( .A(n1982), .Y(n3846) );
BUFX3TS U3164 ( .A(n1982), .Y(n3826) );
BUFX3TS U3165 ( .A(n1982), .Y(n3847) );
BUFX3TS U3166 ( .A(n1985), .Y(n3860) );
BUFX3TS U3167 ( .A(n1983), .Y(n3853) );
BUFX3TS U3168 ( .A(n1983), .Y(n3836) );
BUFX3TS U3169 ( .A(n1984), .Y(n3827) );
BUFX3TS U3170 ( .A(n1985), .Y(n3859) );
BUFX3TS U3171 ( .A(n1985), .Y(n3828) );
OAI21XLTS U3172 ( .A0(n3166), .A1(FS_Module_state_reg[0]), .B0(n3677), .Y(
n1557) );
NAND2X1TS U3173 ( .A(n1986), .B(n3733), .Y(n1441) );
INVX2TS U3174 ( .A(n3455), .Y(n3448) );
INVX2TS U3175 ( .A(n3458), .Y(n3449) );
INVX2TS U3176 ( .A(n3455), .Y(n3450) );
INVX2TS U3177 ( .A(n3458), .Y(n3447) );
NAND2X1TS U3178 ( .A(n2044), .B(n2054), .Y(n1990) );
NAND2X1TS U3179 ( .A(n2049), .B(n2121), .Y(n1989) );
INVX2TS U3180 ( .A(n1987), .Y(n2120) );
NAND2X1TS U3181 ( .A(n2062), .B(n2120), .Y(n1988) );
INVX2TS U3182 ( .A(n3511), .Y(n2064) );
NAND2X1TS U3183 ( .A(n2103), .B(Add_Subt_result[40]), .Y(n1992) );
BUFX3TS U3184 ( .A(n3677), .Y(n2029) );
AOI22X1TS U3185 ( .A0(n1995), .A1(Add_Subt_result[14]), .B0(DmP[38]), .B1(
n2029), .Y(n1991) );
NAND2X2TS U3186 ( .A(n1992), .B(n1991), .Y(n2048) );
NAND2X1TS U3187 ( .A(n2048), .B(n2119), .Y(n2000) );
NAND2X1TS U3188 ( .A(n3657), .B(Add_Subt_result[39]), .Y(n1994) );
AOI22X1TS U3189 ( .A0(n1995), .A1(Add_Subt_result[15]), .B0(DmP[37]), .B1(
n2029), .Y(n1993) );
NAND2X1TS U3190 ( .A(n1994), .B(n1993), .Y(n2057) );
NAND2X1TS U3191 ( .A(n2057), .B(n2121), .Y(n1999) );
NAND2X1TS U3192 ( .A(n3657), .B(Add_Subt_result[38]), .Y(n1997) );
AOI22X1TS U3193 ( .A0(n1995), .A1(Add_Subt_result[16]), .B0(DmP[36]), .B1(
n2029), .Y(n1996) );
NAND2X2TS U3194 ( .A(n1997), .B(n1996), .Y(n2068) );
NAND2X1TS U3195 ( .A(n2068), .B(n2128), .Y(n1998) );
AOI22X1TS U3196 ( .A0(n3649), .A1(n2050), .B0(n3572), .B1(n2077), .Y(n2001)
);
OAI221XLTS U3197 ( .A0(n2066), .A1(n2085), .B0(n2064), .B1(n2042), .C0(n2001), .Y(Barrel_Shifter_module_Mux_Array_Data_array[38]) );
NAND2X1TS U3198 ( .A(n2048), .B(n1597), .Y(n2004) );
NAND2X1TS U3199 ( .A(n2050), .B(n2054), .Y(n2003) );
NAND2X1TS U3200 ( .A(n2057), .B(n2120), .Y(n2002) );
NAND2X1TS U3201 ( .A(n3556), .B(Add_Subt_result[35]), .Y(n2006) );
BUFX3TS U3202 ( .A(n3530), .Y(n2071) );
AOI22X1TS U3203 ( .A0(n2071), .A1(Add_Subt_result[19]), .B0(DmP[33]), .B1(
n2029), .Y(n2005) );
NAND2X1TS U3204 ( .A(n2006), .B(n2005), .Y(n2067) );
NAND2X1TS U3205 ( .A(n2067), .B(n2120), .Y(n2013) );
NAND2X1TS U3206 ( .A(n3657), .B(Add_Subt_result[36]), .Y(n2008) );
AOI22X1TS U3207 ( .A0(n2071), .A1(Add_Subt_result[18]), .B0(DmP[34]), .B1(
n2029), .Y(n2007) );
NAND2X2TS U3208 ( .A(n2008), .B(n2007), .Y(n2056) );
NAND2X1TS U3209 ( .A(n2056), .B(n2121), .Y(n2012) );
NAND2X1TS U3210 ( .A(n2103), .B(Add_Subt_result[37]), .Y(n2010) );
AOI22X1TS U3211 ( .A0(n2071), .A1(Add_Subt_result[17]), .B0(DmP[35]), .B1(
n2029), .Y(n2009) );
NAND2X2TS U3212 ( .A(n2010), .B(n2009), .Y(n2058) );
NAND2X1TS U3213 ( .A(n2058), .B(n2119), .Y(n2011) );
AOI22X1TS U3214 ( .A0(n3563), .A1(n2068), .B0(n3572), .B1(n2062), .Y(n2014)
);
OAI221XLTS U3215 ( .A0(n2066), .A1(n2019), .B0(n2064), .B1(n2032), .C0(n2014), .Y(Barrel_Shifter_module_Mux_Array_Data_array[35]) );
NAND2X1TS U3216 ( .A(n2044), .B(n2121), .Y(n2017) );
NAND2X1TS U3217 ( .A(n2077), .B(n2054), .Y(n2016) );
NAND2X1TS U3218 ( .A(n2049), .B(n2043), .Y(n2015) );
AOI22X1TS U3219 ( .A0(n3639), .A1(n2062), .B0(n3572), .B1(n3492), .Y(n2018)
);
OAI221XLTS U3220 ( .A0(n2066), .A1(n2179), .B0(n2064), .B1(n2019), .C0(n2018), .Y(Barrel_Shifter_module_Mux_Array_Data_array[39]) );
NAND2X1TS U3221 ( .A(n2058), .B(n2120), .Y(n2022) );
NAND2X1TS U3222 ( .A(n2068), .B(n1597), .Y(n2021) );
NAND2X1TS U3223 ( .A(n2057), .B(n2054), .Y(n2020) );
INVX2TS U3224 ( .A(n2023), .Y(n2124) );
AOI22X1TS U3225 ( .A0(n3651), .A1(n2044), .B0(n3496), .B1(n2048), .Y(n2024)
);
OAI221XLTS U3226 ( .A0(n2066), .A1(n2025), .B0(n2064), .B1(n2038), .C0(n2024), .Y(Barrel_Shifter_module_Mux_Array_Data_array[37]) );
BUFX3TS U3227 ( .A(n2066), .Y(n2136) );
INVX2TS U3228 ( .A(n2108), .Y(n2087) );
AOI22X1TS U3229 ( .A0(n2071), .A1(Add_Subt_result[22]), .B0(DmP[30]), .B1(
n2029), .Y(n2026) );
AOI22X1TS U3230 ( .A0(n2071), .A1(Add_Subt_result[23]), .B0(DmP[29]), .B1(
n2029), .Y(n2027) );
AOI22X1TS U3231 ( .A0(n2071), .A1(Add_Subt_result[21]), .B0(DmP[31]), .B1(
n2029), .Y(n2028) );
AOI22X1TS U3232 ( .A0(n2071), .A1(Add_Subt_result[20]), .B0(DmP[32]), .B1(
n2029), .Y(n2030) );
OAI2BB1X2TS U3233 ( .A0N(Add_Subt_result[34]), .A1N(n2103), .B0(n2030), .Y(
n2134) );
AOI22X1TS U3234 ( .A0(n3563), .A1(n2134), .B0(n3651), .B1(n2068), .Y(n2031)
);
OAI221XLTS U3235 ( .A0(n2136), .A1(n2032), .B0(n3503), .B1(n2139), .C0(n2031), .Y(Barrel_Shifter_module_Mux_Array_Data_array[31]) );
BUFX3TS U3236 ( .A(n3677), .Y(n3632) );
AOI22X1TS U3237 ( .A0(n2071), .A1(Add_Subt_result[24]), .B0(DmP[28]), .B1(
n3632), .Y(n2033) );
OAI2BB1X2TS U3238 ( .A0N(Add_Subt_result[30]), .A1N(n2087), .B0(n2033), .Y(
n2133) );
INVX2TS U3239 ( .A(n2108), .Y(n3556) );
AOI22X1TS U3240 ( .A0(n2071), .A1(Add_Subt_result[25]), .B0(DmP[27]), .B1(
n3632), .Y(n2034) );
OAI2BB1X2TS U3241 ( .A0N(Add_Subt_result[29]), .A1N(n3657), .B0(n2034), .Y(
n3501) );
AOI222X1TS U3242 ( .A0(n2133), .A1(n1597), .B0(n3501), .B1(n2120), .C0(n2073), .C1(n2054), .Y(n2102) );
AOI22X1TS U3243 ( .A0(n3671), .A1(n2056), .B0(n3496), .B1(n2099), .Y(n2035)
);
OAI221XLTS U3244 ( .A0(n2136), .A1(n2037), .B0(n3503), .B1(n2102), .C0(n2035), .Y(Barrel_Shifter_module_Mux_Array_Data_array[29]) );
AOI22X1TS U3245 ( .A0(n3671), .A1(n2048), .B0(n3496), .B1(n2056), .Y(n2036)
);
OAI221XLTS U3246 ( .A0(n2136), .A1(n2038), .B0(n2064), .B1(n2037), .C0(n2036), .Y(Barrel_Shifter_module_Mux_Array_Data_array[33]) );
AOI222X1TS U3247 ( .A0(n2067), .A1(n2121), .B0(n2134), .B1(n2128), .C0(n2056), .C1(n2054), .Y(n2041) );
AOI222X1TS U3248 ( .A0(n2073), .A1(n1597), .B0(n2133), .B1(n2128), .C0(n2099), .C1(n2119), .Y(n2132) );
AOI22X1TS U3249 ( .A0(n3563), .A1(n2129), .B0(n3572), .B1(n2058), .Y(n2039)
);
OAI221XLTS U3250 ( .A0(n2136), .A1(n2041), .B0(n3503), .B1(n2132), .C0(n2039), .Y(Barrel_Shifter_module_Mux_Array_Data_array[30]) );
AOI22X1TS U3251 ( .A0(n3649), .A1(n2058), .B0(n3572), .B1(n2050), .Y(n2040)
);
OAI221XLTS U3252 ( .A0(n2066), .A1(n2042), .B0(n2064), .B1(n2041), .C0(n2040), .Y(Barrel_Shifter_module_Mux_Array_Data_array[34]) );
NAND2X1TS U3253 ( .A(n2044), .B(n2043), .Y(n2047) );
NAND2X1TS U3254 ( .A(n3491), .B(n3374), .Y(n2046) );
NAND2X1TS U3255 ( .A(n2077), .B(n1597), .Y(n2045) );
NAND2X1TS U3256 ( .A(n2048), .B(n2128), .Y(n2053) );
NAND2X1TS U3257 ( .A(n2049), .B(n3374), .Y(n2052) );
NAND2X1TS U3258 ( .A(n2050), .B(n1597), .Y(n2051) );
OR2X2TS U3259 ( .A(n1947), .B(n2178), .Y(n3473) );
INVX2TS U3260 ( .A(n2082), .Y(n3466) );
AOI22X1TS U3261 ( .A0(n3665), .A1(n2062), .B0(n3637), .B1(n3492), .Y(n2055)
);
OAI221XLTS U3262 ( .A0(n2066), .A1(n2145), .B0(n2064), .B1(n2065), .C0(n2055), .Y(Barrel_Shifter_module_Mux_Array_Data_array[40]) );
NAND2X1TS U3263 ( .A(n2056), .B(n2128), .Y(n2061) );
NAND2X1TS U3264 ( .A(n2057), .B(n3374), .Y(n2060) );
NAND2X1TS U3265 ( .A(n2058), .B(n2121), .Y(n2059) );
AOI22X1TS U3266 ( .A0(n3638), .A1(n2068), .B0(n3637), .B1(n2062), .Y(n2063)
);
OAI221XLTS U3267 ( .A0(n2066), .A1(n2065), .B0(n2064), .B1(n2070), .C0(n2063), .Y(Barrel_Shifter_module_Mux_Array_Data_array[36]) );
AOI22X1TS U3268 ( .A0(n3516), .A1(n2134), .B0(n3637), .B1(n2068), .Y(n2069)
);
OAI221XLTS U3269 ( .A0(n2136), .A1(n2070), .B0(n3503), .B1(n2075), .C0(n2069), .Y(Barrel_Shifter_module_Mux_Array_Data_array[32]) );
AOI22X1TS U3270 ( .A0(n2071), .A1(Add_Subt_result[26]), .B0(DmP[26]), .B1(
n3632), .Y(n2072) );
INVX2TS U3271 ( .A(n3473), .Y(n3638) );
AOI22X1TS U3272 ( .A0(n3637), .A1(n2134), .B0(n3648), .B1(n2133), .Y(n2074)
);
OAI221XLTS U3273 ( .A0(n2136), .A1(n2075), .B0(n3503), .B1(n2117), .C0(n2074), .Y(Barrel_Shifter_module_Mux_Array_Data_array[28]) );
AOI21X1TS U3274 ( .A0(n3443), .A1(FSM_selector_B[1]), .B0(n2425), .Y(n2076)
);
AND2X2TS U3275 ( .A(n1596), .B(n2178), .Y(n3623) );
AOI22X1TS U3276 ( .A0(n3649), .A1(n2077), .B0(n3623), .B1(n3491), .Y(n2084)
);
INVX2TS U3277 ( .A(n3492), .Y(n2080) );
NAND2X2TS U3278 ( .A(n2120), .B(n2178), .Y(n3481) );
NAND2X1TS U3279 ( .A(n2087), .B(Add_Subt_result[49]), .Y(n2079) );
AOI22X1TS U3280 ( .A0(n3656), .A1(Add_Subt_result[5]), .B0(DmP[47]), .B1(
n2088), .Y(n2078) );
NAND2X2TS U3281 ( .A(n2079), .B(n2078), .Y(n3495) );
INVX2TS U3282 ( .A(n3495), .Y(n3468) );
OAI22X1TS U3283 ( .A0(n2080), .A1(n3481), .B0(n3475), .B1(n3468), .Y(n2081)
);
AOI21X1TS U3284 ( .A0(n2082), .A1(n3493), .B0(n2081), .Y(n2083) );
INVX2TS U3285 ( .A(n3481), .Y(n3663) );
INVX2TS U3286 ( .A(n3493), .Y(n3471) );
AOI22X1TS U3287 ( .A0(n3656), .A1(Add_Subt_result[2]), .B0(DmP[50]), .B1(
n3677), .Y(n2086) );
OAI2BB1X2TS U3288 ( .A0N(Add_Subt_result[52]), .A1N(n2087), .B0(n2086), .Y(
n3490) );
INVX2TS U3289 ( .A(n3490), .Y(n3464) );
OAI22X1TS U3290 ( .A0(n2124), .A1(n3471), .B0(n3464), .B1(n3475), .Y(n2094)
);
NAND2X1TS U3291 ( .A(n3556), .B(Add_Subt_result[50]), .Y(n2090) );
AOI22X1TS U3292 ( .A0(n3656), .A1(Add_Subt_result[4]), .B0(DmP[48]), .B1(
n2088), .Y(n2089) );
NAND2X2TS U3293 ( .A(n2090), .B(n2089), .Y(n3489) );
INVX2TS U3294 ( .A(n3489), .Y(n3472) );
NAND2X1TS U3295 ( .A(n3556), .B(Add_Subt_result[51]), .Y(n2092) );
AOI22X1TS U3296 ( .A0(n3656), .A1(Add_Subt_result[3]), .B0(DmP[49]), .B1(
n3677), .Y(n2091) );
NAND2X2TS U3297 ( .A(n2092), .B(n2091), .Y(n3488) );
INVX2TS U3298 ( .A(n3488), .Y(n3474) );
OAI22X1TS U3299 ( .A0(n3472), .A1(n3487), .B0(n3466), .B1(n3474), .Y(n2093)
);
AOI211X1TS U3300 ( .A0(n3663), .A1(n3495), .B0(n2094), .C0(n2093), .Y(n2095)
);
AND2X2TS U3301 ( .A(n2128), .B(n3511), .Y(n3617) );
INVX2TS U3302 ( .A(n3617), .Y(n3470) );
INVX2TS U3303 ( .A(n3470), .Y(n3636) );
BUFX3TS U3304 ( .A(n3530), .Y(n3548) );
AOI22X1TS U3305 ( .A0(n3548), .A1(Add_Subt_result[29]), .B0(DmP[23]), .B1(
n3632), .Y(n2097) );
OAI2BB1X2TS U3306 ( .A0N(Add_Subt_result[25]), .A1N(n2103), .B0(n2097), .Y(
n3525) );
NOR2X2TS U3307 ( .A(n1595), .B(n2178), .Y(n2114) );
INVX2TS U3308 ( .A(n2114), .Y(n3469) );
AOI22X1TS U3309 ( .A0(n3548), .A1(Add_Subt_result[28]), .B0(DmP[24]), .B1(
n3632), .Y(n2098) );
AOI22X1TS U3310 ( .A0(n3604), .A1(n3525), .B0(n2114), .B1(n3512), .Y(n2101)
);
INVX2TS U3311 ( .A(n3519), .Y(n3381) );
NAND2X1TS U3312 ( .A(n2136), .B(n3381), .Y(n2113) );
NAND2X1TS U3313 ( .A(n3556), .B(n3811), .Y(n2105) );
NAND2X1TS U3314 ( .A(n3633), .B(n3795), .Y(n2104) );
INVX2TS U3315 ( .A(n3482), .Y(n3467) );
NOR2X1TS U3316 ( .A(n3476), .B(n3520), .Y(n3382) );
INVX2TS U3317 ( .A(n3382), .Y(n3380) );
INVX2TS U3318 ( .A(n3470), .Y(n3659) );
INVX2TS U3319 ( .A(n1615), .Y(n3635) );
AOI22X1TS U3320 ( .A0(n3633), .A1(Add_Subt_result[1]), .B0(DmP[51]), .B1(
n3677), .Y(n2106) );
OAI2BB1X2TS U3321 ( .A0N(Add_Subt_result[53]), .A1N(n3635), .B0(n2106), .Y(
n3494) );
AOI22X1TS U3322 ( .A0(n3375), .A1(n3381), .B0(n3604), .B1(n3494), .Y(n2107)
);
INVX2TS U3323 ( .A(n3470), .Y(n3604) );
AOI22X1TS U3324 ( .A0(n3548), .A1(Add_Subt_result[30]), .B0(DmP[22]), .B1(
n3632), .Y(n2109) );
AOI22X1TS U3325 ( .A0(n3637), .A1(n2133), .B0(n3636), .B1(n3532), .Y(n2116)
);
AOI22X1TS U3326 ( .A0(n3548), .A1(Add_Subt_result[31]), .B0(DmP[21]), .B1(
n3632), .Y(n2118) );
AOI22X1TS U3327 ( .A0(n3563), .A1(n3512), .B0(n3637), .B1(n3501), .Y(n2123)
);
NOR2X1TS U3328 ( .A(n3381), .B(n3510), .Y(n2135) );
AOI22X1TS U3329 ( .A0(n3651), .A1(n2133), .B0(n2135), .B1(n3503), .Y(n2122)
);
INVX2TS U3330 ( .A(n3494), .Y(n3465) );
OAI22X1TS U3331 ( .A0(n2124), .A1(n3465), .B0(n3481), .B1(n3467), .Y(n2125)
);
AOI21X1TS U3332 ( .A0(n1579), .A1(n3488), .B0(n2125), .Y(n2127) );
INVX2TS U3333 ( .A(n3473), .Y(n3665) );
AOI22X1TS U3334 ( .A0(n3648), .A1(n3490), .B0(n3659), .B1(n3489), .Y(n2126)
);
INVX2TS U3335 ( .A(n3473), .Y(n3516) );
AOI22X1TS U3336 ( .A0(n2023), .A1(n3501), .B0(n3648), .B1(n3502), .Y(n2131)
);
NOR2X1TS U3337 ( .A(n3381), .B(n3518), .Y(n3504) );
AOI22X1TS U3338 ( .A0(n2136), .A1(n3504), .B0(n3641), .B1(n2129), .Y(n2130)
);
AOI22X1TS U3339 ( .A0(n2023), .A1(n2133), .B0(n3665), .B1(n3501), .Y(n2138)
);
AOI22X1TS U3340 ( .A0(n2136), .A1(n2135), .B0(n3572), .B1(n2134), .Y(n2137)
);
AOI22X1TS U3341 ( .A0(n3648), .A1(n3492), .B0(n3637), .B1(n3489), .Y(n2144)
);
INVX2TS U3342 ( .A(n3481), .Y(n3631) );
NAND2X1TS U3343 ( .A(n3647), .B(n3493), .Y(n2142) );
NAND2X1TS U3344 ( .A(n3661), .B(n3495), .Y(n2141) );
NAND2X1TS U3345 ( .A(n3572), .B(n3488), .Y(n2140) );
AOI22X1TS U3346 ( .A0(n3548), .A1(Add_Subt_result[32]), .B0(DmP[20]), .B1(
n3632), .Y(n2146) );
OAI21X4TS U3347 ( .A0(n1615), .A1(n3777), .B0(n2146), .Y(n3543) );
BUFX3TS U3348 ( .A(n3677), .Y(n3569) );
AOI22X1TS U3349 ( .A0(n3548), .A1(Add_Subt_result[34]), .B0(DmP[18]), .B1(
n3569), .Y(n2147) );
OAI21X4TS U3350 ( .A0(n1615), .A1(n3794), .B0(n2147), .Y(n3557) );
AOI22X1TS U3351 ( .A0(n3649), .A1(n3543), .B0(n2114), .B1(n3557), .Y(n2152)
);
AOI22X1TS U3352 ( .A0(n3548), .A1(Add_Subt_result[33]), .B0(DmP[19]), .B1(
n3632), .Y(n2148) );
OAI2BB1X2TS U3353 ( .A0N(Add_Subt_result[21]), .A1N(n2087), .B0(n2148), .Y(
n3550) );
AOI22X1TS U3354 ( .A0(n3548), .A1(Add_Subt_result[35]), .B0(DmP[17]), .B1(
n3569), .Y(n2149) );
OAI2BB1X2TS U3355 ( .A0N(Add_Subt_result[19]), .A1N(n3556), .B0(n2149), .Y(
n3564) );
AOI21X1TS U3356 ( .A0(n3638), .A1(n3550), .B0(n2150), .Y(n2151) );
INVX2TS U3357 ( .A(n2184), .Y(n2183) );
OAI21X1TS U3358 ( .A0(n2292), .A1(n3798), .B0(n2291), .Y(n2154) );
CLKBUFX2TS U3359 ( .A(n3390), .Y(n2263) );
INVX2TS U3360 ( .A(n2263), .Y(n2336) );
AOI22X1TS U3361 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[87]), .A1(
n2283), .B0(Barrel_Shifter_module_Mux_Array_Data_array[71]), .B1(n3393), .Y(n2156) );
CLKBUFX2TS U3362 ( .A(n2285), .Y(n2337) );
BUFX3TS U3363 ( .A(n2215), .Y(n2307) );
AOI22X1TS U3364 ( .A0(n2337), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[63]), .B0(n2307), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[79]), .Y(n2155) );
INVX2TS U3365 ( .A(n2157), .Y(n2181) );
AO21X1TS U3366 ( .A0(n2262), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[101]), .B0(n2158), .Y(n2208) );
AOI22X1TS U3367 ( .A0(n2208), .A1(n2346), .B0(n2288), .B1(
Sgf_normalized_result[8]), .Y(n2159) );
BUFX3TS U3368 ( .A(n3393), .Y(n2293) );
INVX2TS U3369 ( .A(n2263), .Y(n2316) );
AOI22X1TS U3370 ( .A0(n2293), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[76]), .B0(n2316), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[92]), .Y(n2163) );
BUFX3TS U3371 ( .A(n2285), .Y(n3388) );
AOI22X1TS U3372 ( .A0(n3388), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[68]), .B0(n2307), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .Y(n2162) );
AO21X1TS U3373 ( .A0(n2183), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[100]), .B0(n2160), .Y(n2299) );
NAND2X1TS U3374 ( .A(n2299), .B(n2167), .Y(n2161) );
OAI21X1TS U3375 ( .A0(n2292), .A1(n3802), .B0(n2291), .Y(n2164) );
AOI22X1TS U3376 ( .A0(n2293), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[75]), .B0(n2283), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[91]), .Y(n2170) );
AOI22X1TS U3377 ( .A0(n3388), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[67]), .B0(n2307), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .Y(n2169) );
AO21X1TS U3378 ( .A0(n2262), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[99]), .B0(n2166), .Y(n2304)
);
NAND2X1TS U3379 ( .A(n2304), .B(n2167), .Y(n2168) );
OAI21X1TS U3380 ( .A0(n2292), .A1(n3804), .B0(n2291), .Y(n2171) );
AOI22X1TS U3381 ( .A0(n3649), .A1(n3492), .B0(n3623), .B1(n3493), .Y(n2177)
);
NAND2X1TS U3382 ( .A(n3631), .B(n3491), .Y(n2175) );
NAND2X1TS U3383 ( .A(n3637), .B(n3495), .Y(n2174) );
NAND2X1TS U3384 ( .A(n3572), .B(n3489), .Y(n2173) );
AOI22X1TS U3385 ( .A0(n2208), .A1(n2303), .B0(n2344), .B1(
Sgf_normalized_result[46]), .Y(n2180) );
OAI21X1TS U3386 ( .A0(n2292), .A1(n3799), .B0(n2291), .Y(n2182) );
NOR2X4TS U3387 ( .A(n3476), .B(n2183), .Y(n2279) );
INVX2TS U3388 ( .A(n2279), .Y(n2185) );
AOI22X1TS U3389 ( .A0(n2335), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .B0(n2336), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[94]), .Y(n2187) );
AOI22X1TS U3390 ( .A0(n3388), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[70]), .B0(n2307), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[86]), .Y(n2186) );
AOI22X1TS U3391 ( .A0(n2244), .A1(n3398), .B0(n1576), .B1(
Sgf_normalized_result[15]), .Y(n2188) );
AOI22X1TS U3392 ( .A0(n2293), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[70]), .B0(n2316), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[86]), .Y(n2190) );
BUFX3TS U3393 ( .A(n2215), .Y(n3387) );
AOI22X1TS U3394 ( .A0(n2285), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[62]), .B0(n3387), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .Y(n2189) );
INVX2TS U3395 ( .A(n1599), .Y(n2347) );
NAND2X1TS U3396 ( .A(n2615), .B(n2347), .Y(n2192) );
AOI21X1TS U3397 ( .A0(n2288), .A1(Sgf_normalized_result[47]), .B0(n1586),
.Y(n2191) );
AOI22X1TS U3398 ( .A0(n2293), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[67]), .B0(n2283), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .Y(n2195) );
AOI22X1TS U3399 ( .A0(n2337), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[59]), .B0(n3387), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[75]), .Y(n2194) );
NAND2X1TS U3400 ( .A(n2618), .B(n2347), .Y(n2197) );
AOI21X1TS U3401 ( .A0(n2302), .A1(Sgf_normalized_result[50]), .B0(n1581),
.Y(n2196) );
AOI22X1TS U3402 ( .A0(n2293), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[68]), .B0(n2336), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .Y(n2200) );
AOI22X1TS U3403 ( .A0(n2285), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[60]), .B0(n3387), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[76]), .Y(n2199) );
NAND2X1TS U3404 ( .A(n2624), .B(n2347), .Y(n2202) );
AOI21X1TS U3405 ( .A0(n2302), .A1(Sgf_normalized_result[49]), .B0(n1581),
.Y(n2201) );
AOI22X1TS U3406 ( .A0(n2293), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[69]), .B0(n2336), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(n2205) );
AOI22X1TS U3407 ( .A0(n2285), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[61]), .B0(n3387), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[77]), .Y(n2204) );
NAND2X1TS U3408 ( .A(n2621), .B(n2347), .Y(n2207) );
AOI21X1TS U3409 ( .A0(n1576), .A1(Sgf_normalized_result[48]), .B0(n1586),
.Y(n2206) );
INVX2TS U3410 ( .A(n2208), .Y(n2211) );
AOI22X1TS U3411 ( .A0(n2293), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[77]), .B0(n2336), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[93]), .Y(n2210) );
AOI22X1TS U3412 ( .A0(n3388), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[69]), .B0(n2307), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(n2209) );
AOI22X1TS U3413 ( .A0(n2257), .A1(n3398), .B0(n2302), .B1(
Sgf_normalized_result[14]), .Y(n2212) );
BUFX3TS U3414 ( .A(n3393), .Y(n2284) );
AOI22X1TS U3415 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[95]), .A1(
n3387), .B0(n2337), .B1(Barrel_Shifter_module_Mux_Array_Data_array[79]), .Y(n2213) );
AOI21X1TS U3416 ( .A0(n2284), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[87]), .B0(n2214), .Y(n2223)
);
BUFX3TS U3417 ( .A(n2215), .Y(n2330) );
AOI22X1TS U3418 ( .A0(n2325), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .B0(n2330), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[101]), .Y(n2216) );
AOI21X1TS U3419 ( .A0(n2284), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[93]), .B0(n2217), .Y(n2220)
);
AOI22X1TS U3420 ( .A0(n2325), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .B0(n2330), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[100]), .Y(n2224) );
AOI21X1TS U3421 ( .A0(n2284), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[92]), .B0(n2225), .Y(n2243)
);
AOI22X1TS U3422 ( .A0(n2325), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .B0(n2330), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[96]), .Y(n2226) );
AOI21X1TS U3423 ( .A0(n2284), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[88]), .B0(n2227), .Y(n2240)
);
AOI22X1TS U3424 ( .A0(n2325), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .B0(n2330), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[99]), .Y(n2230) );
AOI21X1TS U3425 ( .A0(n2284), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[91]), .B0(n2231), .Y(n2239)
);
AOI22X1TS U3426 ( .A0(n2325), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .B0(n2330), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[97]), .Y(n2232) );
AOI21X1TS U3427 ( .A0(n2284), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[89]), .B0(n2233), .Y(n2236)
);
AOI21X1TS U3428 ( .A0(n1576), .A1(Sgf_normalized_result[39]), .B0(n1581),
.Y(n2246) );
NAND2X1TS U3429 ( .A(n2244), .B(n2347), .Y(n2245) );
AOI22X1TS U3430 ( .A0(n2293), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[72]), .B0(n2283), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[88]), .Y(n2249) );
AOI22X1TS U3431 ( .A0(n3388), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[64]), .B0(n2307), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .Y(n2248) );
INVX2TS U3432 ( .A(n2250), .Y(n2301) );
AOI22X1TS U3433 ( .A0(n2299), .A1(n2346), .B0(n2288), .B1(
Sgf_normalized_result[9]), .Y(n2251) );
AOI22X1TS U3434 ( .A0(n2293), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .B0(n2336), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[89]), .Y(n2253) );
AOI22X1TS U3435 ( .A0(n2337), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[65]), .B0(n2307), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .Y(n2252) );
INVX2TS U3436 ( .A(n2254), .Y(n2306) );
AOI22X1TS U3437 ( .A0(n2304), .A1(n2346), .B0(n1577), .B1(
Sgf_normalized_result[10]), .Y(n2255) );
AOI21X1TS U3438 ( .A0(n2288), .A1(Sgf_normalized_result[40]), .B0(n1586),
.Y(n2259) );
NAND2X1TS U3439 ( .A(n2257), .B(n2347), .Y(n2258) );
INVX2TS U3440 ( .A(n2263), .Y(n2283) );
AOI22X1TS U3441 ( .A0(n2284), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[65]), .B0(n2316), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .Y(n2265) );
AOI22X1TS U3442 ( .A0(n2285), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[57]), .B0(n3387), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .Y(n2264) );
NAND2X1TS U3443 ( .A(n3397), .B(n2347), .Y(n2267) );
AOI21X1TS U3444 ( .A0(n1576), .A1(Sgf_normalized_result[52]), .B0(n1581),
.Y(n2266) );
AOI22X1TS U3445 ( .A0(n2284), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[63]), .B0(n2316), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[79]), .Y(n2270) );
AOI22X1TS U3446 ( .A0(n2325), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[55]), .B0(n2307), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[71]), .Y(n2269) );
NAND2X1TS U3447 ( .A(n2627), .B(n2347), .Y(n2272) );
AOI21X1TS U3448 ( .A0(n2302), .A1(Sgf_normalized_result[54]), .B0(n1586),
.Y(n2271) );
AOI22X1TS U3449 ( .A0(n2284), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[66]), .B0(n2283), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .Y(n2275) );
AOI22X1TS U3450 ( .A0(n2285), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[58]), .B0(n3387), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[74]), .Y(n2274) );
NAND2X1TS U3451 ( .A(n2630), .B(n1598), .Y(n2277) );
AOI21X1TS U3452 ( .A0(n2302), .A1(Sgf_normalized_result[51]), .B0(n1586),
.Y(n2276) );
AOI22X1TS U3453 ( .A0(n2284), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[64]), .B0(n2336), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .Y(n2287) );
AOI22X1TS U3454 ( .A0(n2285), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[56]), .B0(n3387), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[72]), .Y(n2286) );
NAND2X1TS U3455 ( .A(n2633), .B(n1598), .Y(n2290) );
AOI21X1TS U3456 ( .A0(n2288), .A1(Sgf_normalized_result[53]), .B0(n1581),
.Y(n2289) );
AOI22X1TS U3457 ( .A0(n2293), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[74]), .B0(n2316), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[90]), .Y(n2295) );
AOI22X1TS U3458 ( .A0(n2337), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[66]), .B0(n2307), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .Y(n2294) );
INVX2TS U3459 ( .A(n2296), .Y(n2601) );
AOI22X1TS U3460 ( .A0(n2297), .A1(n2303), .B0(n2344), .B1(
Sgf_normalized_result[43]), .Y(n2298) );
AOI22X1TS U3461 ( .A0(n2299), .A1(n2303), .B0(n2344), .B1(
Sgf_normalized_result[45]), .Y(n2300) );
AOI22X1TS U3462 ( .A0(n2304), .A1(n2303), .B0(n1576), .B1(
Sgf_normalized_result[44]), .Y(n2305) );
AOI22X1TS U3463 ( .A0(n2335), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .B0(n2283), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[96]), .Y(n2309) );
AOI22X1TS U3464 ( .A0(n3388), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[72]), .B0(n2307), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[88]), .Y(n2308) );
INVX2TS U3465 ( .A(n2310), .Y(n2611) );
AOI22X1TS U3466 ( .A0(n2335), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .B0(n2336), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[99]), .Y(n2313) );
AOI22X1TS U3467 ( .A0(n3388), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[75]), .B0(n2330), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[91]), .Y(n2312) );
INVX2TS U3468 ( .A(n2314), .Y(n2603) );
AOI22X1TS U3469 ( .A0(n2335), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .B0(n2316), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[101]), .Y(n2318) );
AOI22X1TS U3470 ( .A0(n2325), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[77]), .B0(n2330), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[93]), .Y(n2317) );
INVX2TS U3471 ( .A(n2319), .Y(n2607) );
AOI22X1TS U3472 ( .A0(n2335), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .B0(n2283), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[98]), .Y(n2322) );
AOI22X1TS U3473 ( .A0(n3388), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[74]), .B0(n2330), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[90]), .Y(n2321) );
INVX2TS U3474 ( .A(n2323), .Y(n2605) );
AOI22X1TS U3475 ( .A0(n2335), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .B0(n2336), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[100]), .Y(n2327) );
AOI22X1TS U3476 ( .A0(n2325), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[76]), .B0(n2330), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[92]), .Y(n2326) );
INVX2TS U3477 ( .A(n2328), .Y(n2609) );
AOI22X1TS U3478 ( .A0(n2335), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .B0(n2316), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[97]), .Y(n2332) );
AOI22X1TS U3479 ( .A0(n3388), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .B0(n2330), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[89]), .Y(n2331) );
INVX2TS U3480 ( .A(n2333), .Y(n2613) );
AOI22X1TS U3481 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[95]), .A1(
n2316), .B0(n2335), .B1(Barrel_Shifter_module_Mux_Array_Data_array[79]), .Y(n2339) );
AOI22X1TS U3482 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[87]), .A1(
n3387), .B0(n2337), .B1(Barrel_Shifter_module_Mux_Array_Data_array[71]), .Y(n2338) );
INVX2TS U3483 ( .A(n2340), .Y(n2637) );
AOI22X1TS U3484 ( .A0(n2346), .A1(n2345), .B0(n2344), .B1(
Sgf_normalized_result[31]), .Y(n2350) );
NAND2X1TS U3485 ( .A(n2348), .B(n2347), .Y(n2349) );
AOI22X1TS U3486 ( .A0(n3699), .A1(intDY[1]), .B0(n3743), .B1(intDY[61]), .Y(
n2352) );
OAI221XLTS U3487 ( .A0(n3699), .A1(intDY[1]), .B0(n3743), .B1(intDY[61]),
.C0(n2352), .Y(n2353) );
AOI221X1TS U3488 ( .A0(intDX[62]), .A1(n3689), .B0(n3737), .B1(intDY[62]),
.C0(n2353), .Y(n2367) );
OAI22X1TS U3489 ( .A0(n3867), .A1(intDY[58]), .B0(n3868), .B1(intDY[57]),
.Y(n2354) );
OAI22X1TS U3490 ( .A0(n3866), .A1(intDY[60]), .B0(n3697), .B1(intDY[59]),
.Y(n2355) );
AOI22X1TS U3491 ( .A0(n3759), .A1(intDY[53]), .B0(n3684), .B1(intDY[54]),
.Y(n2356) );
AOI22X1TS U3492 ( .A0(n3760), .A1(intDY[55]), .B0(n3726), .B1(intDY[56]),
.Y(n2357) );
AOI22X1TS U3493 ( .A0(n3750), .A1(intDY[49]), .B0(n3761), .B1(intDY[50]),
.Y(n2358) );
AOI22X1TS U3494 ( .A0(n3694), .A1(intDY[51]), .B0(n3719), .B1(intDY[52]),
.Y(n2359) );
NOR4X1TS U3495 ( .A(n2363), .B(n2362), .C(n2361), .D(n2360), .Y(n2364) );
OAI22X1TS U3496 ( .A0(n3696), .A1(intDY[38]), .B0(n3739), .B1(intDY[37]),
.Y(n2368) );
AOI221X1TS U3497 ( .A0(n3696), .A1(intDY[38]), .B0(intDY[37]), .B1(n3739),
.C0(n2368), .Y(n2375) );
OAI22X1TS U3498 ( .A0(n3698), .A1(intDY[40]), .B0(n3744), .B1(intDY[39]),
.Y(n2369) );
AOI221X1TS U3499 ( .A0(n3698), .A1(intDY[40]), .B0(intDY[39]), .B1(n3744),
.C0(n2369), .Y(n2374) );
OAI22X1TS U3500 ( .A0(n3701), .A1(intDY[34]), .B0(n3748), .B1(intDY[33]),
.Y(n2370) );
OAI22X1TS U3501 ( .A0(n3749), .A1(intDY[36]), .B0(n3747), .B1(intDY[35]),
.Y(n2371) );
OAI22X1TS U3502 ( .A0(n3742), .A1(intDY[46]), .B0(n3745), .B1(intDY[45]),
.Y(n2376) );
OAI22X1TS U3503 ( .A0(n3695), .A1(intDY[48]), .B0(n3740), .B1(intDY[47]),
.Y(n2377) );
AOI221X1TS U3504 ( .A0(n3695), .A1(intDY[48]), .B0(intDY[47]), .B1(n3740),
.C0(n2377), .Y(n2382) );
OAI22X1TS U3505 ( .A0(n3700), .A1(intDY[42]), .B0(n3741), .B1(intDY[41]),
.Y(n2378) );
AOI221X1TS U3506 ( .A0(n3700), .A1(intDY[42]), .B0(intDY[41]), .B1(n3741),
.C0(n2378), .Y(n2381) );
OAI22X1TS U3507 ( .A0(n3738), .A1(intDY[44]), .B0(n3746), .B1(intDY[43]),
.Y(n2379) );
AOI22X1TS U3508 ( .A0(n3735), .A1(intDY[21]), .B0(n3686), .B1(intDY[22]),
.Y(n2384) );
AOI22X1TS U3509 ( .A0(n3755), .A1(intDY[23]), .B0(n3723), .B1(intDY[24]),
.Y(n2385) );
AOI22X1TS U3510 ( .A0(n3752), .A1(intDY[17]), .B0(n3763), .B1(intDY[18]),
.Y(n2386) );
AOI22X1TS U3511 ( .A0(n3693), .A1(intDY[19]), .B0(n3736), .B1(intDY[20]),
.Y(n2387) );
NOR4X1TS U3512 ( .A(n2391), .B(n2390), .C(n2389), .D(n2388), .Y(n2419) );
AOI22X1TS U3513 ( .A0(n3734), .A1(intDY[29]), .B0(n3685), .B1(intDY[30]),
.Y(n2392) );
AOI22X1TS U3514 ( .A0(n3754), .A1(intDY[31]), .B0(n3721), .B1(intDY[32]),
.Y(n2393) );
AOI22X1TS U3515 ( .A0(n3751), .A1(intDY[25]), .B0(n3762), .B1(intDY[26]),
.Y(n2394) );
AOI22X1TS U3516 ( .A0(n3692), .A1(intDY[27]), .B0(n3724), .B1(intDY[28]),
.Y(n2395) );
NOR4X1TS U3517 ( .A(n2399), .B(n2398), .C(n2397), .D(n2396), .Y(n2418) );
AOI22X1TS U3518 ( .A0(n3681), .A1(intDY[5]), .B0(n3717), .B1(intDY[6]), .Y(
n2400) );
AOI22X1TS U3519 ( .A0(n3713), .A1(intDY[7]), .B0(n3764), .B1(intDY[8]), .Y(
n2401) );
AOI22X1TS U3520 ( .A0(n3683), .A1(intDY[2]), .B0(n3758), .B1(intDY[0]), .Y(
n2402) );
AOI22X1TS U3521 ( .A0(n3757), .A1(intDY[3]), .B0(n3718), .B1(intDY[4]), .Y(
n2403) );
OAI221XLTS U3522 ( .A0(n3757), .A1(intDY[3]), .B0(n3718), .B1(intDY[4]),
.C0(n2403), .Y(n2404) );
NOR4X1TS U3523 ( .A(n2407), .B(n2406), .C(n2405), .D(n2404), .Y(n2417) );
AOI22X1TS U3524 ( .A0(n3720), .A1(intDY[13]), .B0(n3687), .B1(intDY[14]),
.Y(n2408) );
AOI22X1TS U3525 ( .A0(n3756), .A1(intDY[15]), .B0(n3716), .B1(intDY[16]),
.Y(n2409) );
OAI221XLTS U3526 ( .A0(n3756), .A1(intDY[15]), .B0(n3716), .B1(intDY[16]),
.C0(n2409), .Y(n2414) );
AOI22X1TS U3527 ( .A0(n3722), .A1(intDY[9]), .B0(n3682), .B1(intDY[10]), .Y(
n2410) );
AOI22X1TS U3528 ( .A0(n3753), .A1(intDY[11]), .B0(n3725), .B1(intDY[12]),
.Y(n2411) );
NOR4X1TS U3529 ( .A(n2415), .B(n2414), .C(n2413), .D(n2412), .Y(n2416) );
NOR4X2TS U3530 ( .A(n2423), .B(n2422), .C(n2421), .D(n2420), .Y(n2641) );
XNOR2X4TS U3531 ( .A(intDY[63]), .B(intAS), .Y(n2437) );
XOR2X4TS U3532 ( .A(n2437), .B(n3730), .Y(n2661) );
INVX2TS U3533 ( .A(n2424), .Y(n2546) );
AOI211X1TS U3534 ( .A0(n2426), .A1(n3785), .B0(n2425), .C0(n3410), .Y(n2427)
);
AND4X1TS U3535 ( .A(n3327), .B(n3373), .C(n3355), .D(n3444), .Y(n2430) );
AND3X2TS U3536 ( .A(n3422), .B(n3420), .C(n2430), .Y(n2432) );
NOR2XLTS U3537 ( .A(n2436), .B(n2641), .Y(n2440) );
NAND2X1TS U3538 ( .A(n2438), .B(n2437), .Y(n2439) );
AOI22X1TS U3539 ( .A0(n2516), .A1(intDY[62]), .B0(DmP[62]), .B1(n2589), .Y(
n2442) );
AOI22X1TS U3540 ( .A0(n2516), .A1(intDY[61]), .B0(DmP[61]), .B1(n2589), .Y(
n2443) );
BUFX3TS U3541 ( .A(n2448), .Y(n2470) );
INVX2TS U3542 ( .A(n2449), .Y(n2512) );
AOI22X1TS U3543 ( .A0(n2470), .A1(intDY[16]), .B0(DmP[16]), .B1(n2512), .Y(
n2444) );
AOI22X1TS U3544 ( .A0(n2470), .A1(intDY[10]), .B0(DmP[10]), .B1(n1590), .Y(
n2445) );
BUFX3TS U3545 ( .A(n2448), .Y(n2478) );
AOI22X1TS U3546 ( .A0(n2478), .A1(intDY[52]), .B0(DmP[52]), .B1(n2500), .Y(
n2446) );
AOI22X1TS U3547 ( .A0(n2516), .A1(intDY[59]), .B0(DmP[59]), .B1(n2589), .Y(
n2447) );
BUFX3TS U3548 ( .A(n2448), .Y(n2481) );
AOI22X1TS U3549 ( .A0(n2481), .A1(intDY[24]), .B0(DmP[24]), .B1(n2472), .Y(
n2450) );
AOI22X1TS U3550 ( .A0(n2470), .A1(intDY[18]), .B0(DmP[18]), .B1(n1589), .Y(
n2451) );
AOI22X1TS U3551 ( .A0(n2470), .A1(intDY[17]), .B0(DmP[17]), .B1(n1589), .Y(
n2452) );
AOI22X1TS U3552 ( .A0(n2481), .A1(intDY[26]), .B0(DmP[26]), .B1(n2500), .Y(
n2453) );
AOI22X1TS U3553 ( .A0(n2481), .A1(intDY[25]), .B0(DmP[25]), .B1(n2472), .Y(
n2454) );
AOI22X1TS U3554 ( .A0(n2478), .A1(intDY[49]), .B0(DmP[49]), .B1(n2512), .Y(
n2455) );
AOI22X1TS U3555 ( .A0(n2478), .A1(intDY[57]), .B0(DmP[57]), .B1(n2589), .Y(
n2456) );
AOI22X1TS U3556 ( .A0(n2478), .A1(intDY[58]), .B0(DmP[58]), .B1(n2507), .Y(
n2457) );
AOI22X1TS U3557 ( .A0(n2478), .A1(intDY[60]), .B0(DmP[60]), .B1(n2504), .Y(
n2458) );
AOI22X1TS U3558 ( .A0(n2478), .A1(intDY[56]), .B0(DmP[56]), .B1(n2512), .Y(
n2459) );
AOI22X1TS U3559 ( .A0(n2481), .A1(intDY[30]), .B0(DmP[30]), .B1(n2512), .Y(
n2460) );
AOI22X1TS U3560 ( .A0(n2470), .A1(intDY[14]), .B0(DmP[14]), .B1(n2504), .Y(
n2461) );
AOI22X1TS U3561 ( .A0(n2481), .A1(intDY[22]), .B0(DmP[22]), .B1(n2472), .Y(
n2462) );
AOI22X1TS U3562 ( .A0(n2470), .A1(intDY[21]), .B0(DmP[21]), .B1(n2472), .Y(
n2463) );
AOI22X1TS U3563 ( .A0(n2470), .A1(intDY[13]), .B0(DmP[13]), .B1(n1589), .Y(
n2464) );
AOI22X1TS U3564 ( .A0(n2481), .A1(intDY[23]), .B0(DmP[23]), .B1(n1589), .Y(
n2465) );
AOI22X1TS U3565 ( .A0(n2470), .A1(intDY[15]), .B0(DmP[15]), .B1(n2512), .Y(
n2466) );
AOI22X1TS U3566 ( .A0(n2478), .A1(intDY[51]), .B0(DmP[51]), .B1(n1589), .Y(
n2467) );
AOI22X1TS U3567 ( .A0(n2481), .A1(intDY[27]), .B0(DmP[27]), .B1(n2504), .Y(
n2468) );
AOI22X1TS U3568 ( .A0(n2470), .A1(intDY[19]), .B0(DmP[19]), .B1(n2507), .Y(
n2469) );
AOI22X1TS U3569 ( .A0(n2470), .A1(intDY[12]), .B0(DmP[12]), .B1(n2507), .Y(
n2471) );
AOI22X1TS U3570 ( .A0(n2481), .A1(intDY[28]), .B0(DmP[28]), .B1(n1590), .Y(
n2473) );
AOI22X1TS U3571 ( .A0(n2481), .A1(intDY[20]), .B0(DmP[20]), .B1(n1590), .Y(
n2474) );
AOI22X1TS U3572 ( .A0(n2478), .A1(intDY[55]), .B0(DmP[55]), .B1(n2504), .Y(
n2476) );
AOI22X1TS U3573 ( .A0(n2478), .A1(intDY[53]), .B0(DmP[53]), .B1(n2507), .Y(
n2477) );
AOI22X1TS U3574 ( .A0(n2478), .A1(intDY[54]), .B0(DmP[54]), .B1(n2500), .Y(
n2479) );
AOI22X1TS U3575 ( .A0(n2481), .A1(intDY[0]), .B0(DmP[0]), .B1(n2472), .Y(
n2482) );
INVX2TS U3576 ( .A(n2546), .Y(n2541) );
INVX2TS U3577 ( .A(n2483), .Y(n1219) );
INVX2TS U3578 ( .A(n2484), .Y(n1220) );
AOI222X1TS U3579 ( .A0(n2579), .A1(DMP[52]), .B0(n2516), .B1(intDX[52]),
.C0(intDY[52]), .C1(n2543), .Y(n2485) );
INVX2TS U3580 ( .A(n2485), .Y(n1221) );
INVX2TS U3581 ( .A(n2486), .Y(n1223) );
AOI222X1TS U3582 ( .A0(n2589), .A1(DMP[55]), .B0(n2516), .B1(intDX[55]),
.C0(intDY[55]), .C1(n2543), .Y(n2487) );
INVX2TS U3583 ( .A(n2487), .Y(n1224) );
AOI222X1TS U3584 ( .A0(n2593), .A1(DMP[53]), .B0(n2516), .B1(intDX[53]),
.C0(intDY[53]), .C1(n2543), .Y(n2488) );
INVX2TS U3585 ( .A(n2488), .Y(n1222) );
AOI22X1TS U3586 ( .A0(n2513), .A1(intDY[1]), .B0(DmP[1]), .B1(n2472), .Y(
n2489) );
AOI22X1TS U3587 ( .A0(n2505), .A1(intDY[38]), .B0(DmP[38]), .B1(n2512), .Y(
n2490) );
AOI22X1TS U3588 ( .A0(n2513), .A1(intDY[6]), .B0(DmP[6]), .B1(n2504), .Y(
n2491) );
AOI22X1TS U3589 ( .A0(n2509), .A1(intDY[48]), .B0(DmP[48]), .B1(n1590), .Y(
n2492) );
AOI22X1TS U3590 ( .A0(n2513), .A1(intDY[7]), .B0(DmP[7]), .B1(n2507), .Y(
n2493) );
AOI22X1TS U3591 ( .A0(n2509), .A1(intDY[44]), .B0(DmP[44]), .B1(n2507), .Y(
n2494) );
AOI22X1TS U3592 ( .A0(n2513), .A1(intDY[5]), .B0(DmP[5]), .B1(n2500), .Y(
n2495) );
AOI22X1TS U3593 ( .A0(n2513), .A1(intDY[4]), .B0(DmP[4]), .B1(n1590), .Y(
n2496) );
AOI22X1TS U3594 ( .A0(n2505), .A1(intDY[37]), .B0(DmP[37]), .B1(n2500), .Y(
n2497) );
AOI22X1TS U3595 ( .A0(n2509), .A1(intDY[47]), .B0(DmP[47]), .B1(n2504), .Y(
n2498) );
AOI22X1TS U3596 ( .A0(n2513), .A1(intDY[2]), .B0(DmP[2]), .B1(n2472), .Y(
n2499) );
AOI22X1TS U3597 ( .A0(n2505), .A1(intDY[32]), .B0(DmP[32]), .B1(n1590), .Y(
n2501) );
AOI22X1TS U3598 ( .A0(n2513), .A1(intDY[9]), .B0(DmP[9]), .B1(n2512), .Y(
n2503) );
AOI22X1TS U3599 ( .A0(n2505), .A1(intDY[40]), .B0(DmP[40]), .B1(n2500), .Y(
n2506) );
AOI22X1TS U3600 ( .A0(n2513), .A1(intDY[8]), .B0(DmP[8]), .B1(n1589), .Y(
n2508) );
AOI22X1TS U3601 ( .A0(n2509), .A1(intDY[50]), .B0(DmP[50]), .B1(n1590), .Y(
n2510) );
AOI22X1TS U3602 ( .A0(n2513), .A1(intDY[11]), .B0(DmP[11]), .B1(n2507), .Y(
n2514) );
AOI222X1TS U3603 ( .A0(n2589), .A1(DMP[21]), .B0(n2516), .B1(intDX[21]),
.C0(intDY[21]), .C1(n2591), .Y(n2517) );
INVX2TS U3604 ( .A(n2517), .Y(n1190) );
AOI222X1TS U3605 ( .A0(n2579), .A1(DMP[49]), .B0(n2524), .B1(intDX[49]),
.C0(intDY[49]), .C1(n2523), .Y(n2518) );
INVX2TS U3606 ( .A(n2518), .Y(n1218) );
INVX2TS U3607 ( .A(n2519), .Y(n1214) );
AOI222X1TS U3608 ( .A0(n2585), .A1(DMP[46]), .B0(n2524), .B1(intDX[46]),
.C0(intDY[46]), .C1(n2523), .Y(n2520) );
INVX2TS U3609 ( .A(n2520), .Y(n1215) );
AOI222X1TS U3610 ( .A0(n2593), .A1(DMP[47]), .B0(n2524), .B1(intDX[47]),
.C0(intDY[47]), .C1(n2523), .Y(n2521) );
INVX2TS U3611 ( .A(n2521), .Y(n1216) );
INVX2TS U3612 ( .A(n2522), .Y(n1213) );
AOI222X1TS U3613 ( .A0(n2541), .A1(DMP[48]), .B0(n2524), .B1(intDX[48]),
.C0(intDY[48]), .C1(n2523), .Y(n2525) );
INVX2TS U3614 ( .A(n2525), .Y(n1217) );
INVX2TS U3615 ( .A(n2526), .Y(n1175) );
INVX2TS U3616 ( .A(n2527), .Y(n1179) );
INVX2TS U3617 ( .A(n2528), .Y(n1178) );
INVX2TS U3618 ( .A(n2640), .Y(n2570) );
INVX2TS U3619 ( .A(n2530), .Y(n1203) );
INVX2TS U3620 ( .A(n2531), .Y(n1209) );
INVX2TS U3621 ( .A(n2532), .Y(n1206) );
INVX2TS U3622 ( .A(n2533), .Y(n1177) );
INVX2TS U3623 ( .A(n2534), .Y(n1210) );
INVX2TS U3624 ( .A(n2535), .Y(n1183) );
INVX2TS U3625 ( .A(n2536), .Y(n1208) );
INVX2TS U3626 ( .A(n2537), .Y(n1174) );
INVX2TS U3627 ( .A(n2538), .Y(n1180) );
INVX2TS U3628 ( .A(n2539), .Y(n1204) );
INVX2TS U3629 ( .A(n2540), .Y(n1225) );
AOI222X1TS U3630 ( .A0(n2585), .A1(DMP[43]), .B0(n2553), .B1(intDX[43]),
.C0(intDY[43]), .C1(n2552), .Y(n2542) );
INVX2TS U3631 ( .A(n2542), .Y(n1212) );
INVX2TS U3632 ( .A(n2544), .Y(n1226) );
INVX2TS U3633 ( .A(n2545), .Y(n1205) );
INVX2TS U3634 ( .A(n2548), .Y(n1201) );
INVX2TS U3635 ( .A(n2549), .Y(n1211) );
INVX2TS U3636 ( .A(n2551), .Y(n1227) );
INVX2TS U3637 ( .A(n2554), .Y(n1207) );
INVX2TS U3638 ( .A(n2555), .Y(n1228) );
INVX2TS U3639 ( .A(n2556), .Y(n1229) );
INVX2TS U3640 ( .A(n2557), .Y(n1197) );
AOI222X1TS U3641 ( .A0(n2589), .A1(DMP[61]), .B0(n2588), .B1(intDX[61]),
.C0(intDY[61]), .C1(n2587), .Y(n2558) );
INVX2TS U3642 ( .A(n2558), .Y(n1230) );
INVX2TS U3643 ( .A(n2559), .Y(n1172) );
INVX2TS U3644 ( .A(n2560), .Y(n1185) );
INVX2TS U3645 ( .A(n2561), .Y(n1171) );
INVX2TS U3646 ( .A(n2562), .Y(n1196) );
INVX2TS U3647 ( .A(n2563), .Y(n1195) );
INVX2TS U3648 ( .A(n2564), .Y(n1194) );
AOI222X1TS U3649 ( .A0(n2541), .A1(DMP[7]), .B0(n2578), .B1(intDX[7]), .C0(
intDY[7]), .C1(n1585), .Y(n2565) );
INVX2TS U3650 ( .A(n2565), .Y(n1176) );
INVX2TS U3651 ( .A(n2566), .Y(n1181) );
INVX2TS U3652 ( .A(n2567), .Y(n1186) );
INVX2TS U3653 ( .A(n2568), .Y(n1169) );
AOI222X1TS U3654 ( .A0(n2585), .A1(DMP[13]), .B0(n2592), .B1(intDX[13]),
.C0(intDY[13]), .C1(n1585), .Y(n2569) );
INVX2TS U3655 ( .A(n2569), .Y(n1182) );
INVX2TS U3656 ( .A(n2571), .Y(n1202) );
INVX2TS U3657 ( .A(n2572), .Y(n1193) );
INVX2TS U3658 ( .A(n2574), .Y(n1189) );
INVX2TS U3659 ( .A(n2575), .Y(n1187) );
AOI222X1TS U3660 ( .A0(n2589), .A1(DMP[62]), .B0(n2588), .B1(intDX[62]),
.C0(intDY[62]), .C1(n2587), .Y(n2576) );
INVX2TS U3661 ( .A(n2576), .Y(n1168) );
INVX2TS U3662 ( .A(n2577), .Y(n1192) );
INVX2TS U3663 ( .A(n2580), .Y(n1173) );
INVX2TS U3664 ( .A(n2581), .Y(n1200) );
INVX2TS U3665 ( .A(n2582), .Y(n1199) );
INVX2TS U3666 ( .A(n2583), .Y(n1191) );
INVX2TS U3667 ( .A(n2584), .Y(n1188) );
INVX2TS U3668 ( .A(n2586), .Y(n1198) );
INVX2TS U3669 ( .A(n2590), .Y(n1170) );
INVX2TS U3670 ( .A(n2594), .Y(n1184) );
BUFX3TS U3671 ( .A(n2595), .Y(n2639) );
BUFX3TS U3672 ( .A(n2596), .Y(n2635) );
OAI222X1TS U3673 ( .A0(n3774), .A1(n2639), .B0(n1593), .B1(n2598), .C0(n2635), .C1(n2597), .Y(n1455) );
OAI222X1TS U3674 ( .A0(n3775), .A1(n2639), .B0(n1593), .B1(n2600), .C0(n2635), .C1(n2599), .Y(n1454) );
OAI222X1TS U3675 ( .A0(n3769), .A1(n2595), .B0(n1593), .B1(n2604), .C0(n2596), .C1(n2603), .Y(n1462) );
OAI222X1TS U3676 ( .A0(n3770), .A1(n2595), .B0(n1593), .B1(n2606), .C0(n2596), .C1(n2605), .Y(n1461) );
OAI222X1TS U3677 ( .A0(n3768), .A1(n2595), .B0(n1594), .B1(n2610), .C0(n2596), .C1(n2609), .Y(n1463) );
OAI222X1TS U3678 ( .A0(n3772), .A1(n2639), .B0(n1594), .B1(n2612), .C0(n2596), .C1(n2611), .Y(n1459) );
INVX2TS U3679 ( .A(n2615), .Y(n2616) );
OAI222X1TS U3680 ( .A0(n2617), .A1(n1594), .B0(n2635), .B1(n2616), .C0(n2639), .C1(n1619), .Y(n1449) );
INVX2TS U3681 ( .A(n2618), .Y(n2619) );
INVX2TS U3682 ( .A(n2621), .Y(n2622) );
INVX2TS U3683 ( .A(n2624), .Y(n2625) );
INVX2TS U3684 ( .A(n2627), .Y(n2628) );
INVX2TS U3685 ( .A(n2630), .Y(n2631) );
INVX2TS U3686 ( .A(n2633), .Y(n2634) );
BUFX3TS U3687 ( .A(n2653), .Y(n2660) );
CLKBUFX2TS U3688 ( .A(n3461), .Y(n3459) );
AOI31X1TS U3689 ( .A0(n2641), .A1(n2661), .A2(n2640), .B0(n3459), .Y(n3415)
);
AOI211X1TS U3690 ( .A0(n2644), .A1(n3785), .B0(n2643), .C0(n2642), .Y(n2646)
);
BUFX3TS U3691 ( .A(n2653), .Y(n2648) );
BUFX3TS U3692 ( .A(n2653), .Y(n2649) );
BUFX3TS U3693 ( .A(n2658), .Y(n2650) );
BUFX3TS U3694 ( .A(n2658), .Y(n2651) );
BUFX3TS U3695 ( .A(n2658), .Y(n2652) );
BUFX3TS U3696 ( .A(n2653), .Y(n3417) );
BUFX3TS U3697 ( .A(n2658), .Y(n2654) );
BUFX3TS U3698 ( .A(n2658), .Y(n2655) );
BUFX3TS U3699 ( .A(n2658), .Y(n2656) );
BUFX3TS U3700 ( .A(n2658), .Y(n2657) );
BUFX3TS U3701 ( .A(n2658), .Y(n2659) );
NAND2X8TS U3702 ( .A(n2661), .B(n3733), .Y(n3403) );
INVX4TS U3703 ( .A(n3403), .Y(n2690) );
XOR2X1TS U3704 ( .A(n2690), .B(n2662), .Y(n2664) );
NOR2X2TS U3705 ( .A(n2664), .B(n2663), .Y(n3282) );
OR2X1TS U3706 ( .A(n2696), .B(Sgf_normalized_result[2]), .Y(n2665) );
XOR2X1TS U3707 ( .A(n2690), .B(n2665), .Y(n2670) );
NOR2X1TS U3708 ( .A(n2670), .B(n2669), .Y(n3284) );
NOR2X1TS U3709 ( .A(n3282), .B(n3284), .Y(n2672) );
NOR2X1TS U3710 ( .A(n2696), .B(n3766), .Y(n2666) );
XOR2X1TS U3711 ( .A(n2969), .B(n2666), .Y(n3290) );
INVX2TS U3712 ( .A(n3290), .Y(n2668) );
NOR2X1TS U3713 ( .A(n2969), .B(n2667), .Y(n3291) );
NOR2X1TS U3714 ( .A(n2668), .B(n3291), .Y(n3280) );
NAND2X1TS U3715 ( .A(n2670), .B(n2669), .Y(n3285) );
INVX2TS U3716 ( .A(n3285), .Y(n2671) );
AOI21X1TS U3717 ( .A0(n2672), .A1(n3280), .B0(n2671), .Y(n3251) );
NOR2X1TS U3718 ( .A(n2696), .B(n1617), .Y(n2673) );
XOR2X1TS U3719 ( .A(n2690), .B(n2673), .Y(n2678) );
NOR2X1TS U3720 ( .A(n2678), .B(n2677), .Y(n3267) );
NOR2X1TS U3721 ( .A(n2696), .B(n1614), .Y(n2674) );
XOR2X1TS U3722 ( .A(n2690), .B(n2674), .Y(n2680) );
NOR2X2TS U3723 ( .A(n2680), .B(n2679), .Y(n3269) );
NOR2X1TS U3724 ( .A(n3267), .B(n3269), .Y(n3253) );
XOR2X1TS U3725 ( .A(n2690), .B(n2675), .Y(n2682) );
CLKMX2X2TS U3726 ( .A(DMP[3]), .B(Sgf_normalized_result[5]), .S0(n1886), .Y(
n2681) );
NOR2X2TS U3727 ( .A(n2682), .B(n2681), .Y(n3260) );
NOR2X1TS U3728 ( .A(n2696), .B(n1612), .Y(n2676) );
XOR2X1TS U3729 ( .A(n2690), .B(n2676), .Y(n2684) );
NOR2X2TS U3730 ( .A(n2684), .B(n2683), .Y(n3254) );
NAND2X1TS U3731 ( .A(n3253), .B(n2686), .Y(n2688) );
NAND2X1TS U3732 ( .A(n2678), .B(n2677), .Y(n3275) );
NAND2X1TS U3733 ( .A(n2680), .B(n2679), .Y(n3270) );
OAI21X1TS U3734 ( .A0(n3269), .A1(n3275), .B0(n3270), .Y(n3252) );
NAND2X1TS U3735 ( .A(n2682), .B(n2681), .Y(n3261) );
NAND2X1TS U3736 ( .A(n2684), .B(n2683), .Y(n3255) );
AOI21X1TS U3737 ( .A0(n3252), .A1(n2686), .B0(n2685), .Y(n2687) );
OAI21X2TS U3738 ( .A0(n3251), .A1(n2688), .B0(n2687), .Y(n3187) );
CLKMX2X2TS U3739 ( .A(DMP[5]), .B(Sgf_normalized_result[7]), .S0(n1587), .Y(
n2699) );
NOR2X2TS U3740 ( .A(n2700), .B(n2699), .Y(n3240) );
INVX4TS U3741 ( .A(n3733), .Y(n2966) );
NOR2BX1TS U3742 ( .AN(Sgf_normalized_result[8]), .B(n2966), .Y(n2691) );
XOR2X1TS U3743 ( .A(n2731), .B(n2691), .Y(n2702) );
NOR2X1TS U3744 ( .A(n3240), .B(n3234), .Y(n3221) );
NOR2X1TS U3745 ( .A(n2704), .B(n2703), .Y(n3225) );
NOR2BX1TS U3746 ( .AN(Sgf_normalized_result[10]), .B(n2743), .Y(n2693) );
XOR2X1TS U3747 ( .A(n2731), .B(n2693), .Y(n2706) );
NOR2X2TS U3748 ( .A(n2706), .B(n2705), .Y(n3227) );
XOR2X1TS U3749 ( .A(n2731), .B(n2694), .Y(n2710) );
CLKMX2X2TS U3750 ( .A(DMP[9]), .B(Sgf_normalized_result[11]), .S0(n2958),
.Y(n2709) );
NOR2X1TS U3751 ( .A(n2710), .B(n2709), .Y(n3207) );
XOR2X1TS U3752 ( .A(n2731), .B(n2695), .Y(n2712) );
NOR2X2TS U3753 ( .A(n2712), .B(n2711), .Y(n3215) );
NOR2X1TS U3754 ( .A(n3207), .B(n3215), .Y(n3190) );
XOR2X1TS U3755 ( .A(n2731), .B(n2697), .Y(n2714) );
CLKMX2X2TS U3756 ( .A(DMP[11]), .B(Sgf_normalized_result[13]), .S0(n1886),
.Y(n2713) );
NOR2X1TS U3757 ( .A(n2714), .B(n2713), .Y(n3194) );
NOR2BX1TS U3758 ( .AN(Sgf_normalized_result[14]), .B(n2743), .Y(n2698) );
XOR2X1TS U3759 ( .A(n2731), .B(n2698), .Y(n2716) );
NOR2X2TS U3760 ( .A(n2716), .B(n2715), .Y(n3196) );
NAND2X2TS U3761 ( .A(n2700), .B(n2699), .Y(n3241) );
NAND2X1TS U3762 ( .A(n2702), .B(n2701), .Y(n3235) );
OAI21X1TS U3763 ( .A0(n3234), .A1(n3241), .B0(n3235), .Y(n3222) );
NAND2X1TS U3764 ( .A(n2704), .B(n2703), .Y(n3246) );
NAND2X1TS U3765 ( .A(n2706), .B(n2705), .Y(n3228) );
OAI21X1TS U3766 ( .A0(n3227), .A1(n3246), .B0(n3228), .Y(n2707) );
NAND2X1TS U3767 ( .A(n2710), .B(n2709), .Y(n3211) );
NAND2X1TS U3768 ( .A(n2712), .B(n2711), .Y(n3216) );
OAI21X1TS U3769 ( .A0(n3215), .A1(n3211), .B0(n3216), .Y(n3191) );
NAND2X1TS U3770 ( .A(n2714), .B(n2713), .Y(n3202) );
NAND2X1TS U3771 ( .A(n2716), .B(n2715), .Y(n3197) );
AOI21X1TS U3772 ( .A0(n3191), .A1(n2718), .B0(n2717), .Y(n2719) );
OAI21X1TS U3773 ( .A0(n3188), .A1(n2720), .B0(n2719), .Y(n2721) );
AOI21X4TS U3774 ( .A0(n3187), .A1(n2722), .B0(n2721), .Y(n2793) );
NOR2BX1TS U3775 ( .AN(Sgf_normalized_result[15]), .B(n2743), .Y(n2723) );
XOR2X1TS U3776 ( .A(n2731), .B(n2723), .Y(n2725) );
NOR2X1TS U3777 ( .A(n2725), .B(n2724), .Y(n2729) );
INVX2TS U3778 ( .A(n2729), .Y(n3179) );
NAND2X1TS U3779 ( .A(n3179), .B(n3177), .Y(n2726) );
XNOR2X1TS U3780 ( .A(n3180), .B(n2726), .Y(n2727) );
NOR2X1TS U3781 ( .A(n2966), .B(n3773), .Y(n2728) );
XOR2X1TS U3782 ( .A(n2731), .B(n2728), .Y(n2748) );
CLKMX2X2TS U3783 ( .A(DMP[14]), .B(Sgf_normalized_result[16]), .S0(n1886),
.Y(n2747) );
NOR2X2TS U3784 ( .A(n2748), .B(n2747), .Y(n3181) );
NOR2X1TS U3785 ( .A(n2966), .B(n3772), .Y(n2730) );
XOR2X1TS U3786 ( .A(n2731), .B(n2730), .Y(n2750) );
CLKMX2X2TS U3787 ( .A(DMP[15]), .B(Sgf_normalized_result[17]), .S0(n1886),
.Y(n2749) );
NOR2X2TS U3788 ( .A(n2750), .B(n2749), .Y(n3169) );
INVX4TS U3789 ( .A(n3403), .Y(n2742) );
NOR2X1TS U3790 ( .A(n2966), .B(n3771), .Y(n2732) );
XOR2X1TS U3791 ( .A(n2742), .B(n2732), .Y(n2752) );
CLKMX2X2TS U3792 ( .A(DMP[16]), .B(Sgf_normalized_result[18]), .S0(n2842),
.Y(n2751) );
NOR2X2TS U3793 ( .A(n2752), .B(n2751), .Y(n3171) );
XOR2X1TS U3794 ( .A(n2742), .B(n2733), .Y(n2756) );
CLKMX2X2TS U3795 ( .A(DMP[17]), .B(Sgf_normalized_result[19]), .S0(n2842),
.Y(n2755) );
NOR2X2TS U3796 ( .A(n2756), .B(n2755), .Y(n3154) );
NOR2X1TS U3797 ( .A(n2966), .B(n3769), .Y(n2734) );
XOR2X1TS U3798 ( .A(n2742), .B(n2734), .Y(n2758) );
CLKMX2X2TS U3799 ( .A(DMP[18]), .B(Sgf_normalized_result[20]), .S0(n2842),
.Y(n2757) );
NOR2X2TS U3800 ( .A(n2758), .B(n2757), .Y(n3156) );
NOR2X1TS U3801 ( .A(n3154), .B(n3156), .Y(n3136) );
NOR2X1TS U3802 ( .A(n2966), .B(n3768), .Y(n2735) );
XOR2X1TS U3803 ( .A(n2742), .B(n2735), .Y(n2760) );
CLKMX2X2TS U3804 ( .A(DMP[19]), .B(Sgf_normalized_result[21]), .S0(n2842),
.Y(n2759) );
NOR2X2TS U3805 ( .A(n2760), .B(n2759), .Y(n3141) );
NOR2X1TS U3806 ( .A(n2966), .B(n3767), .Y(n2736) );
XOR2X1TS U3807 ( .A(n2742), .B(n2736), .Y(n2762) );
CLKMX2X2TS U3808 ( .A(DMP[20]), .B(Sgf_normalized_result[22]), .S0(n1886),
.Y(n2761) );
NOR2X2TS U3809 ( .A(n2762), .B(n2761), .Y(n3143) );
NOR2X2TS U3810 ( .A(n3131), .B(n2766), .Y(n3054) );
NOR2BX1TS U3811 ( .AN(Sgf_normalized_result[23]), .B(n2743), .Y(n2737) );
XOR2X1TS U3812 ( .A(n2742), .B(n2737), .Y(n2768) );
INVX2TS U3813 ( .A(n2962), .Y(n2796) );
CLKMX2X2TS U3814 ( .A(DMP[21]), .B(Sgf_normalized_result[23]), .S0(n2958),
.Y(n2767) );
NOR2X2TS U3815 ( .A(n2768), .B(n2767), .Y(n3125) );
NOR2BX1TS U3816 ( .AN(Sgf_normalized_result[24]), .B(n2743), .Y(n2738) );
XOR2X1TS U3817 ( .A(n2742), .B(n2738), .Y(n2770) );
NOR2X2TS U3818 ( .A(n2770), .B(n2769), .Y(n3119) );
NOR2X1TS U3819 ( .A(n3125), .B(n3119), .Y(n3066) );
NOR2BX1TS U3820 ( .AN(Sgf_normalized_result[25]), .B(n2743), .Y(n2739) );
XOR2X1TS U3821 ( .A(n2742), .B(n2739), .Y(n2772) );
CLKMX2X2TS U3822 ( .A(DMP[23]), .B(Sgf_normalized_result[25]), .S0(n2958),
.Y(n2771) );
NOR2X2TS U3823 ( .A(n2772), .B(n2771), .Y(n3073) );
NOR2BX1TS U3824 ( .AN(Sgf_normalized_result[26]), .B(n2743), .Y(n2740) );
XOR2X1TS U3825 ( .A(n2742), .B(n2740), .Y(n2774) );
NOR2X2TS U3826 ( .A(n2774), .B(n2773), .Y(n3067) );
NOR2BX1TS U3827 ( .AN(Sgf_normalized_result[27]), .B(n2743), .Y(n2741) );
CLKMX2X2TS U3828 ( .A(DMP[25]), .B(Sgf_normalized_result[27]), .S0(n2958),
.Y(n2777) );
NOR2X2TS U3829 ( .A(n2778), .B(n2777), .Y(n3085) );
NOR2BX1TS U3830 ( .AN(Sgf_normalized_result[28]), .B(n2743), .Y(n2744) );
XOR2X1TS U3831 ( .A(n2841), .B(n2744), .Y(n2780) );
NOR2X2TS U3832 ( .A(n2780), .B(n2779), .Y(n3059) );
NOR2BX1TS U3833 ( .AN(Sgf_normalized_result[29]), .B(n2802), .Y(n2745) );
XOR2X1TS U3834 ( .A(n2841), .B(n2745), .Y(n2782) );
NOR2X2TS U3835 ( .A(n2782), .B(n2781), .Y(n3100) );
NOR2BX1TS U3836 ( .AN(Sgf_normalized_result[30]), .B(n2802), .Y(n2746) );
XOR2X1TS U3837 ( .A(n2841), .B(n2746), .Y(n2784) );
NOR2X2TS U3838 ( .A(n2784), .B(n2783), .Y(n3093) );
NOR2X2TS U3839 ( .A(n3055), .B(n2788), .Y(n2790) );
NAND2X1TS U3840 ( .A(n2748), .B(n2747), .Y(n3182) );
OAI21X1TS U3841 ( .A0(n3181), .A1(n3177), .B0(n3182), .Y(n3162) );
NAND2X1TS U3842 ( .A(n2750), .B(n2749), .Y(n3168) );
NAND2X1TS U3843 ( .A(n2752), .B(n2751), .Y(n3172) );
OAI21X1TS U3844 ( .A0(n3171), .A1(n3168), .B0(n3172), .Y(n2753) );
AOI21X2TS U3845 ( .A0(n3162), .A1(n2754), .B0(n2753), .Y(n3132) );
NAND2X1TS U3846 ( .A(n2756), .B(n2755), .Y(n3153) );
NAND2X1TS U3847 ( .A(n2758), .B(n2757), .Y(n3157) );
OAI21X1TS U3848 ( .A0(n3156), .A1(n3153), .B0(n3157), .Y(n3135) );
NAND2X1TS U3849 ( .A(n2760), .B(n2759), .Y(n3140) );
NAND2X1TS U3850 ( .A(n2762), .B(n2761), .Y(n3144) );
AOI21X1TS U3851 ( .A0(n3135), .A1(n2764), .B0(n2763), .Y(n2765) );
OAI21X2TS U3852 ( .A0(n3132), .A1(n2766), .B0(n2765), .Y(n3053) );
NAND2X1TS U3853 ( .A(n2768), .B(n2767), .Y(n3126) );
NAND2X1TS U3854 ( .A(n2770), .B(n2769), .Y(n3120) );
NAND2X1TS U3855 ( .A(n2772), .B(n2771), .Y(n3074) );
NAND2X1TS U3856 ( .A(n2774), .B(n2773), .Y(n3068) );
OAI21X1TS U3857 ( .A0(n3067), .A1(n3074), .B0(n3068), .Y(n2775) );
AOI21X1TS U3858 ( .A0(n3065), .A1(n2776), .B0(n2775), .Y(n3056) );
NAND2X1TS U3859 ( .A(n2778), .B(n2777), .Y(n3086) );
NAND2X1TS U3860 ( .A(n2780), .B(n2779), .Y(n3060) );
OAI21X1TS U3861 ( .A0(n3059), .A1(n3086), .B0(n3060), .Y(n3090) );
NAND2X1TS U3862 ( .A(n2782), .B(n2781), .Y(n3101) );
NAND2X1TS U3863 ( .A(n2784), .B(n2783), .Y(n3094) );
AOI21X1TS U3864 ( .A0(n3090), .A1(n2786), .B0(n2785), .Y(n2787) );
AOI21X2TS U3865 ( .A0(n3053), .A1(n2790), .B0(n2789), .Y(n2791) );
OAI21X4TS U3866 ( .A0(n2793), .A1(n2792), .B0(n2791), .Y(n2922) );
NOR2BX1TS U3867 ( .AN(Sgf_normalized_result[31]), .B(n2802), .Y(n2794) );
XOR2X1TS U3868 ( .A(n2841), .B(n2794), .Y(n2805) );
NOR2X2TS U3869 ( .A(n2805), .B(n2804), .Y(n3112) );
NOR2BX1TS U3870 ( .AN(Sgf_normalized_result[32]), .B(n2802), .Y(n2795) );
XOR2X1TS U3871 ( .A(n2841), .B(n2795), .Y(n2807) );
CLKMX2X2TS U3872 ( .A(DMP[30]), .B(Sgf_normalized_result[32]), .S0(n1886),
.Y(n2806) );
NOR2X1TS U3873 ( .A(n3112), .B(n3106), .Y(n3041) );
NOR2BX1TS U3874 ( .AN(Sgf_normalized_result[33]), .B(n2802), .Y(n2797) );
XOR2X1TS U3875 ( .A(n2841), .B(n2797), .Y(n2809) );
INVX2TS U3876 ( .A(n2962), .Y(n2842) );
NOR2X1TS U3877 ( .A(n2809), .B(n2808), .Y(n3045) );
NOR2BX1TS U3878 ( .AN(Sgf_normalized_result[34]), .B(n2802), .Y(n2798) );
XOR2X1TS U3879 ( .A(n2841), .B(n2798), .Y(n2811) );
NOR2X2TS U3880 ( .A(n2811), .B(n2810), .Y(n3047) );
NOR2BX1TS U3881 ( .AN(Sgf_normalized_result[35]), .B(n2802), .Y(n2799) );
XOR2X1TS U3882 ( .A(n2841), .B(n2799), .Y(n2815) );
NOR2X1TS U3883 ( .A(n2815), .B(n2814), .Y(n3027) );
NOR2BX1TS U3884 ( .AN(Sgf_normalized_result[36]), .B(n2802), .Y(n2800) );
XOR2X1TS U3885 ( .A(n2841), .B(n2800), .Y(n2817) );
CLKMX2X2TS U3886 ( .A(DMP[34]), .B(Sgf_normalized_result[36]), .S0(n2796),
.Y(n2816) );
NOR2X2TS U3887 ( .A(n2817), .B(n2816), .Y(n3030) );
NOR2BX1TS U3888 ( .AN(Sgf_normalized_result[37]), .B(n2802), .Y(n2801) );
XOR2X1TS U3889 ( .A(n2882), .B(n2801), .Y(n2819) );
CLKMX2X2TS U3890 ( .A(DMP[35]), .B(Sgf_normalized_result[37]), .S0(n2842),
.Y(n2818) );
NOR2X1TS U3891 ( .A(n2819), .B(n2818), .Y(n2999) );
NOR2BX1TS U3892 ( .AN(Sgf_normalized_result[38]), .B(n2802), .Y(n2803) );
XOR2X1TS U3893 ( .A(n2882), .B(n2803), .Y(n2821) );
NOR2X2TS U3894 ( .A(n2821), .B(n2820), .Y(n3001) );
NOR2X2TS U3895 ( .A(n2994), .B(n2825), .Y(n2866) );
INVX2TS U3896 ( .A(n2866), .Y(n2827) );
NAND2X2TS U3897 ( .A(n2805), .B(n2804), .Y(n3113) );
NAND2X1TS U3898 ( .A(n2807), .B(n2806), .Y(n3107) );
OAI21X1TS U3899 ( .A0(n3106), .A1(n3113), .B0(n3107), .Y(n3042) );
NAND2X1TS U3900 ( .A(n2809), .B(n2808), .Y(n3079) );
NAND2X1TS U3901 ( .A(n2811), .B(n2810), .Y(n3048) );
OAI21X1TS U3902 ( .A0(n3047), .A1(n3079), .B0(n3048), .Y(n2812) );
AOI21X2TS U3903 ( .A0(n3042), .A1(n2813), .B0(n2812), .Y(n2993) );
NAND2X1TS U3904 ( .A(n2815), .B(n2814), .Y(n3036) );
NAND2X1TS U3905 ( .A(n2817), .B(n2816), .Y(n3031) );
OAI21X1TS U3906 ( .A0(n3030), .A1(n3036), .B0(n3031), .Y(n2996) );
NAND2X1TS U3907 ( .A(n2819), .B(n2818), .Y(n3007) );
NAND2X1TS U3908 ( .A(n2821), .B(n2820), .Y(n3002) );
OAI21X1TS U3909 ( .A0(n3001), .A1(n3007), .B0(n3002), .Y(n2822) );
AOI21X1TS U3910 ( .A0(n2996), .A1(n2823), .B0(n2822), .Y(n2824) );
OAI21X2TS U3911 ( .A0(n2993), .A1(n2825), .B0(n2824), .Y(n2880) );
INVX2TS U3912 ( .A(n2880), .Y(n2826) );
OAI21X4TS U3913 ( .A0(n3116), .A1(n2827), .B0(n2826), .Y(n3014) );
NOR2BX1TS U3914 ( .AN(Sgf_normalized_result[39]), .B(n2925), .Y(n2828) );
CLKMX2X2TS U3915 ( .A(DMP[37]), .B(Sgf_normalized_result[39]), .S0(n2958),
.Y(n2830) );
NOR2X1TS U3916 ( .A(n2831), .B(n2830), .Y(n3012) );
NOR2BX1TS U3917 ( .AN(Sgf_normalized_result[40]), .B(n2925), .Y(n2829) );
XOR2X1TS U3918 ( .A(n2882), .B(n2829), .Y(n2833) );
NOR2X2TS U3919 ( .A(n2833), .B(n2832), .Y(n3015) );
NOR2X1TS U3920 ( .A(n3012), .B(n3015), .Y(n2850) );
INVX2TS U3921 ( .A(n2850), .Y(n2835) );
NAND2X1TS U3922 ( .A(n2831), .B(n2830), .Y(n3022) );
NAND2X1TS U3923 ( .A(n2833), .B(n2832), .Y(n3016) );
INVX2TS U3924 ( .A(n2855), .Y(n2834) );
OAI21X1TS U3925 ( .A0(n3025), .A1(n2835), .B0(n2834), .Y(n2991) );
NOR2BX1TS U3926 ( .AN(Sgf_normalized_result[41]), .B(n2925), .Y(n2836) );
XOR2X1TS U3927 ( .A(n2882), .B(n2836), .Y(n2838) );
NOR2X1TS U3928 ( .A(n2838), .B(n2837), .Y(n2849) );
INVX2TS U3929 ( .A(n2849), .Y(n2989) );
NAND2X1TS U3930 ( .A(n2838), .B(n2837), .Y(n2988) );
INVX2TS U3931 ( .A(n2988), .Y(n2839) );
AOI21X1TS U3932 ( .A0(n2991), .A1(n2989), .B0(n2839), .Y(n2847) );
NOR2BX1TS U3933 ( .AN(Sgf_normalized_result[42]), .B(n2925), .Y(n2840) );
XOR2X1TS U3934 ( .A(n2841), .B(n2840), .Y(n2844) );
NOR2X2TS U3935 ( .A(n2844), .B(n2843), .Y(n2852) );
INVX2TS U3936 ( .A(n2852), .Y(n2845) );
NAND2X1TS U3937 ( .A(n2844), .B(n2843), .Y(n2851) );
NAND2X1TS U3938 ( .A(n2845), .B(n2851), .Y(n2846) );
XOR2X1TS U3939 ( .A(n2847), .B(n2846), .Y(n2848) );
OAI21X1TS U3940 ( .A0(n2852), .A1(n2988), .B0(n2851), .Y(n2853) );
INVX2TS U3941 ( .A(n2910), .Y(n2893) );
NOR2BX1TS U3942 ( .AN(Sgf_normalized_result[43]), .B(n2925), .Y(n2856) );
XOR2X1TS U3943 ( .A(n2882), .B(n2856), .Y(n2858) );
NOR2X1TS U3944 ( .A(n2858), .B(n2857), .Y(n2862) );
INVX2TS U3945 ( .A(n2862), .Y(n2909) );
NAND2X1TS U3946 ( .A(n2858), .B(n2857), .Y(n2907) );
NAND2X1TS U3947 ( .A(n2909), .B(n2907), .Y(n2859) );
XOR2X1TS U3948 ( .A(n2893), .B(n2859), .Y(n2860) );
NOR2BX1TS U3949 ( .AN(Sgf_normalized_result[44]), .B(n2925), .Y(n2861) );
XOR2X1TS U3950 ( .A(n2882), .B(n2861), .Y(n2868) );
CLKMX2X2TS U3951 ( .A(DMP[42]), .B(Sgf_normalized_result[44]), .S0(n1886),
.Y(n2867) );
NOR2X2TS U3952 ( .A(n2868), .B(n2867), .Y(n2911) );
NOR2BX1TS U3953 ( .AN(Sgf_normalized_result[45]), .B(n2925), .Y(n2863) );
XOR2X1TS U3954 ( .A(n2882), .B(n2863), .Y(n2870) );
NOR2X1TS U3955 ( .A(n2870), .B(n2869), .Y(n2894) );
NOR2BX1TS U3956 ( .AN(Sgf_normalized_result[46]), .B(n2925), .Y(n2864) );
XOR2X1TS U3957 ( .A(n2882), .B(n2864), .Y(n2872) );
NOR2X2TS U3958 ( .A(n2872), .B(n2871), .Y(n2896) );
NAND2X1TS U3959 ( .A(n2868), .B(n2867), .Y(n2912) );
OAI21X1TS U3960 ( .A0(n2911), .A1(n2907), .B0(n2912), .Y(n2890) );
NAND2X1TS U3961 ( .A(n2870), .B(n2869), .Y(n2902) );
NAND2X1TS U3962 ( .A(n2872), .B(n2871), .Y(n2897) );
OAI21X1TS U3963 ( .A0(n2896), .A1(n2902), .B0(n2897), .Y(n2873) );
AOI21X1TS U3964 ( .A0(n2890), .A1(n2874), .B0(n2873), .Y(n2875) );
NOR2BX1TS U3965 ( .AN(Sgf_normalized_result[47]), .B(n2925), .Y(n2881) );
XOR2X1TS U3966 ( .A(n2882), .B(n2881), .Y(n2884) );
NOR2X2TS U3967 ( .A(n2884), .B(n2883), .Y(n2919) );
INVX2TS U3968 ( .A(n2919), .Y(n2885) );
NAND2X1TS U3969 ( .A(n2884), .B(n2883), .Y(n2917) );
NAND2X1TS U3970 ( .A(n2885), .B(n2917), .Y(n2886) );
XNOR2X1TS U3971 ( .A(n2887), .B(n2886), .Y(n2888) );
INVX2TS U3972 ( .A(n2889), .Y(n2892) );
INVX2TS U3973 ( .A(n2890), .Y(n2891) );
OAI21X4TS U3974 ( .A0(n2893), .A1(n2892), .B0(n2891), .Y(n2905) );
INVX2TS U3975 ( .A(n2894), .Y(n2903) );
INVX2TS U3976 ( .A(n2902), .Y(n2895) );
AOI21X1TS U3977 ( .A0(n2905), .A1(n2903), .B0(n2895), .Y(n2900) );
INVX2TS U3978 ( .A(n2896), .Y(n2898) );
NAND2X1TS U3979 ( .A(n2898), .B(n2897), .Y(n2899) );
XOR2X1TS U3980 ( .A(n2900), .B(n2899), .Y(n2901) );
NAND2X1TS U3981 ( .A(n2903), .B(n2902), .Y(n2904) );
XNOR2X1TS U3982 ( .A(n2905), .B(n2904), .Y(n2906) );
INVX2TS U3983 ( .A(n2907), .Y(n2908) );
AOI21X1TS U3984 ( .A0(n2910), .A1(n2909), .B0(n2908), .Y(n2915) );
INVX2TS U3985 ( .A(n2911), .Y(n2913) );
NAND2X1TS U3986 ( .A(n2913), .B(n2912), .Y(n2914) );
XOR2X1TS U3987 ( .A(n2915), .B(n2914), .Y(n2916) );
OAI21X4TS U3988 ( .A0(n2918), .A1(n2919), .B0(n2917), .Y(n2924) );
NOR2X2TS U3989 ( .A(n2920), .B(n2919), .Y(n2921) );
AND2X8TS U3990 ( .A(n2922), .B(n2921), .Y(n2923) );
NOR2BX1TS U3991 ( .AN(Sgf_normalized_result[48]), .B(n2925), .Y(n2926) );
XOR2X1TS U3992 ( .A(n2969), .B(n2926), .Y(n2928) );
NOR2X1TS U3993 ( .A(n2928), .B(n2927), .Y(n2933) );
INVX2TS U3994 ( .A(n2933), .Y(n2929) );
NAND2X1TS U3995 ( .A(n2928), .B(n2927), .Y(n2932) );
NAND2X1TS U3996 ( .A(n2929), .B(n2932), .Y(n2930) );
XOR2X1TS U3997 ( .A(n2934), .B(n2930), .Y(n2931) );
OAI21X4TS U3998 ( .A0(n2934), .A1(n2933), .B0(n2932), .Y(n2943) );
NOR2BX1TS U3999 ( .AN(Sgf_normalized_result[49]), .B(n2967), .Y(n2935) );
XOR2X1TS U4000 ( .A(n2969), .B(n2935), .Y(n2937) );
NAND2X1TS U4001 ( .A(n2937), .B(n2936), .Y(n2940) );
NAND2X1TS U4002 ( .A(n2942), .B(n2940), .Y(n2938) );
XNOR2X1TS U4003 ( .A(n2943), .B(n2938), .Y(n2939) );
INVX2TS U4004 ( .A(n2940), .Y(n2941) );
AOI21X4TS U4005 ( .A0(n2943), .A1(n2942), .B0(n2941), .Y(n2952) );
NOR2BX1TS U4006 ( .AN(Sgf_normalized_result[50]), .B(n2967), .Y(n2944) );
XOR2X1TS U4007 ( .A(n2969), .B(n2944), .Y(n2946) );
NOR2X1TS U4008 ( .A(n2946), .B(n2945), .Y(n2951) );
INVX2TS U4009 ( .A(n2951), .Y(n2947) );
NAND2X1TS U4010 ( .A(n2946), .B(n2945), .Y(n2950) );
NAND2X1TS U4011 ( .A(n2947), .B(n2950), .Y(n2948) );
XOR2X1TS U4012 ( .A(n2952), .B(n2948), .Y(n2949) );
OAI21X4TS U4013 ( .A0(n2952), .A1(n2951), .B0(n2950), .Y(n2980) );
NOR2BX1TS U4014 ( .AN(Sgf_normalized_result[51]), .B(n2967), .Y(n2953) );
XOR2X1TS U4015 ( .A(n2969), .B(n2953), .Y(n2955) );
NAND2X1TS U4016 ( .A(n2955), .B(n2954), .Y(n2977) );
INVX2TS U4017 ( .A(n2977), .Y(n2956) );
AOI21X4TS U4018 ( .A0(n2980), .A1(n2978), .B0(n2956), .Y(n2986) );
NOR2BX1TS U4019 ( .AN(Sgf_normalized_result[52]), .B(n2967), .Y(n2957) );
XOR2X1TS U4020 ( .A(n2969), .B(n2957), .Y(n2960) );
NOR2X1TS U4021 ( .A(n2960), .B(n2959), .Y(n2982) );
NAND2X1TS U4022 ( .A(n2960), .B(n2959), .Y(n2983) );
OAI21X4TS U4023 ( .A0(n2986), .A1(n2982), .B0(n2983), .Y(n2975) );
NOR2BX1TS U4024 ( .AN(Sgf_normalized_result[53]), .B(n2967), .Y(n2961) );
XOR2X1TS U4025 ( .A(n2969), .B(n2961), .Y(n2964) );
NAND2X1TS U4026 ( .A(n2964), .B(n2963), .Y(n2972) );
INVX2TS U4027 ( .A(n2972), .Y(n2965) );
AOI21X4TS U4028 ( .A0(n2975), .A1(n2973), .B0(n2965), .Y(n3402) );
NOR2BX1TS U4029 ( .AN(Sgf_normalized_result[54]), .B(n2967), .Y(n2968) );
NAND2X1TS U4030 ( .A(n3399), .B(n3400), .Y(n2970) );
XOR2X1TS U4031 ( .A(n3402), .B(n2970), .Y(n2971) );
NAND2X1TS U4032 ( .A(n2973), .B(n2972), .Y(n2974) );
XNOR2X1TS U4033 ( .A(n2975), .B(n2974), .Y(n2976) );
NAND2X1TS U4034 ( .A(n2978), .B(n2977), .Y(n2979) );
XNOR2X1TS U4035 ( .A(n2980), .B(n2979), .Y(n2981) );
INVX2TS U4036 ( .A(n2982), .Y(n2984) );
NAND2X1TS U4037 ( .A(n2984), .B(n2983), .Y(n2985) );
XOR2X1TS U4038 ( .A(n2986), .B(n2985), .Y(n2987) );
NAND2X1TS U4039 ( .A(n2989), .B(n2988), .Y(n2990) );
XNOR2X1TS U4040 ( .A(n2991), .B(n2990), .Y(n2992) );
OAI21X2TS U4041 ( .A0(n3116), .A1(n2994), .B0(n2993), .Y(n3029) );
INVX2TS U4042 ( .A(n3029), .Y(n3039) );
INVX2TS U4043 ( .A(n2995), .Y(n2998) );
INVX2TS U4044 ( .A(n2996), .Y(n2997) );
OAI21X1TS U4045 ( .A0(n3039), .A1(n2998), .B0(n2997), .Y(n3010) );
INVX2TS U4046 ( .A(n2999), .Y(n3008) );
INVX2TS U4047 ( .A(n3007), .Y(n3000) );
AOI21X1TS U4048 ( .A0(n3010), .A1(n3008), .B0(n3000), .Y(n3005) );
INVX2TS U4049 ( .A(n3001), .Y(n3003) );
NAND2X1TS U4050 ( .A(n3003), .B(n3002), .Y(n3004) );
XOR2X1TS U4051 ( .A(n3005), .B(n3004), .Y(n3006) );
NAND2X1TS U4052 ( .A(n3008), .B(n3007), .Y(n3009) );
XNOR2X1TS U4053 ( .A(n3010), .B(n3009), .Y(n3011) );
INVX2TS U4054 ( .A(n3012), .Y(n3023) );
INVX2TS U4055 ( .A(n3022), .Y(n3013) );
AOI21X1TS U4056 ( .A0(n3014), .A1(n3023), .B0(n3013), .Y(n3019) );
INVX2TS U4057 ( .A(n3015), .Y(n3017) );
NAND2X1TS U4058 ( .A(n3017), .B(n3016), .Y(n3018) );
XOR2X1TS U4059 ( .A(n3019), .B(n3018), .Y(n3021) );
NAND2X1TS U4060 ( .A(n3023), .B(n3022), .Y(n3024) );
XOR2X1TS U4061 ( .A(n3025), .B(n3024), .Y(n3026) );
INVX2TS U4062 ( .A(n3027), .Y(n3037) );
INVX2TS U4063 ( .A(n3036), .Y(n3028) );
AOI21X1TS U4064 ( .A0(n3029), .A1(n3037), .B0(n3028), .Y(n3034) );
INVX2TS U4065 ( .A(n3030), .Y(n3032) );
NAND2X1TS U4066 ( .A(n3032), .B(n3031), .Y(n3033) );
XOR2X1TS U4067 ( .A(n3034), .B(n3033), .Y(n3035) );
NAND2X1TS U4068 ( .A(n3037), .B(n3036), .Y(n3038) );
XOR2X1TS U4069 ( .A(n3039), .B(n3038), .Y(n3040) );
INVX2TS U4070 ( .A(n3041), .Y(n3044) );
INVX2TS U4071 ( .A(n3042), .Y(n3043) );
OAI21X1TS U4072 ( .A0(n3116), .A1(n3044), .B0(n3043), .Y(n3082) );
INVX2TS U4073 ( .A(n3045), .Y(n3080) );
INVX2TS U4074 ( .A(n3079), .Y(n3046) );
AOI21X1TS U4075 ( .A0(n3082), .A1(n3080), .B0(n3046), .Y(n3051) );
INVX2TS U4076 ( .A(n3047), .Y(n3049) );
NAND2X1TS U4077 ( .A(n3049), .B(n3048), .Y(n3050) );
XOR2X1TS U4078 ( .A(n3051), .B(n3050), .Y(n3052) );
INVX2TS U4079 ( .A(n3055), .Y(n3058) );
INVX2TS U4080 ( .A(n3056), .Y(n3057) );
INVX2TS U4081 ( .A(n3059), .Y(n3061) );
NAND2X1TS U4082 ( .A(n3061), .B(n3060), .Y(n3062) );
XNOR2X1TS U4083 ( .A(n3063), .B(n3062), .Y(n3064) );
AOI21X1TS U4084 ( .A0(n3129), .A1(n3066), .B0(n3065), .Y(n3077) );
INVX2TS U4085 ( .A(n3067), .Y(n3069) );
NAND2X1TS U4086 ( .A(n3069), .B(n3068), .Y(n3070) );
XNOR2X1TS U4087 ( .A(n3071), .B(n3070), .Y(n3072) );
CLKMX2X2TS U4088 ( .A(Add_Subt_result[26]), .B(n3072), .S0(n3098), .Y(n1529)
);
INVX2TS U4089 ( .A(n3073), .Y(n3075) );
NAND2X1TS U4090 ( .A(n3075), .B(n3074), .Y(n3076) );
XOR2X1TS U4091 ( .A(n3077), .B(n3076), .Y(n3078) );
NAND2X1TS U4092 ( .A(n3080), .B(n3079), .Y(n3081) );
XNOR2X1TS U4093 ( .A(n3082), .B(n3081), .Y(n3083) );
INVX2TS U4094 ( .A(n3084), .Y(n3092) );
INVX2TS U4095 ( .A(n3085), .Y(n3087) );
NAND2X1TS U4096 ( .A(n3087), .B(n3086), .Y(n3088) );
XNOR2X1TS U4097 ( .A(n3092), .B(n3088), .Y(n3089) );
OAI21X1TS U4098 ( .A0(n3104), .A1(n3100), .B0(n3101), .Y(n3097) );
INVX2TS U4099 ( .A(n3093), .Y(n3095) );
NAND2X1TS U4100 ( .A(n3095), .B(n3094), .Y(n3096) );
INVX2TS U4101 ( .A(n3100), .Y(n3102) );
NAND2X1TS U4102 ( .A(n3102), .B(n3101), .Y(n3103) );
XOR2X1TS U4103 ( .A(n3104), .B(n3103), .Y(n3105) );
INVX2TS U4104 ( .A(n3106), .Y(n3108) );
NAND2X1TS U4105 ( .A(n3108), .B(n3107), .Y(n3109) );
XNOR2X1TS U4106 ( .A(n3110), .B(n3109), .Y(n3111) );
INVX2TS U4107 ( .A(n3112), .Y(n3114) );
NAND2X1TS U4108 ( .A(n3114), .B(n3113), .Y(n3115) );
XOR2X1TS U4109 ( .A(n3116), .B(n3115), .Y(n3117) );
INVX2TS U4110 ( .A(n3119), .Y(n3121) );
NAND2X1TS U4111 ( .A(n3121), .B(n3120), .Y(n3122) );
XNOR2X1TS U4112 ( .A(n3123), .B(n3122), .Y(n3124) );
INVX2TS U4113 ( .A(n3125), .Y(n3127) );
NAND2X1TS U4114 ( .A(n3127), .B(n3126), .Y(n3128) );
XNOR2X1TS U4115 ( .A(n3129), .B(n3128), .Y(n3130) );
INVX2TS U4116 ( .A(n3131), .Y(n3134) );
INVX2TS U4117 ( .A(n3132), .Y(n3133) );
AOI21X1TS U4118 ( .A0(n3180), .A1(n3134), .B0(n3133), .Y(n3155) );
INVX2TS U4119 ( .A(n3155), .Y(n3151) );
AOI21X1TS U4120 ( .A0(n3151), .A1(n3136), .B0(n3135), .Y(n3142) );
INVX2TS U4121 ( .A(n3141), .Y(n3137) );
NAND2X1TS U4122 ( .A(n3137), .B(n3140), .Y(n3138) );
XOR2X1TS U4123 ( .A(n3142), .B(n3138), .Y(n3139) );
OAI21X1TS U4124 ( .A0(n3142), .A1(n3141), .B0(n3140), .Y(n3147) );
INVX2TS U4125 ( .A(n3143), .Y(n3145) );
NAND2X1TS U4126 ( .A(n3145), .B(n3144), .Y(n3146) );
XNOR2X1TS U4127 ( .A(n3147), .B(n3146), .Y(n3148) );
INVX2TS U4128 ( .A(n3154), .Y(n3149) );
NAND2X1TS U4129 ( .A(n3149), .B(n3153), .Y(n3150) );
XNOR2X1TS U4130 ( .A(n3151), .B(n3150), .Y(n3152) );
INVX2TS U4131 ( .A(n3156), .Y(n3158) );
NAND2X1TS U4132 ( .A(n3158), .B(n3157), .Y(n3159) );
XNOR2X1TS U4133 ( .A(n3160), .B(n3159), .Y(n3161) );
AOI21X1TS U4134 ( .A0(n3180), .A1(n3163), .B0(n3162), .Y(n3170) );
INVX2TS U4135 ( .A(n3169), .Y(n3164) );
NAND2X1TS U4136 ( .A(n3164), .B(n3168), .Y(n3165) );
XOR2X1TS U4137 ( .A(n3170), .B(n3165), .Y(n3167) );
INVX2TS U4138 ( .A(n3171), .Y(n3173) );
NAND2X1TS U4139 ( .A(n3173), .B(n3172), .Y(n3174) );
XNOR2X1TS U4140 ( .A(n3175), .B(n3174), .Y(n3176) );
AOI21X1TS U4141 ( .A0(n3180), .A1(n3179), .B0(n3178), .Y(n3185) );
INVX2TS U4142 ( .A(n3181), .Y(n3183) );
NAND2X1TS U4143 ( .A(n3183), .B(n3182), .Y(n3184) );
XOR2X1TS U4144 ( .A(n3185), .B(n3184), .Y(n3186) );
INVX2TS U4145 ( .A(n3187), .Y(n3244) );
OAI21X1TS U4146 ( .A0(n3244), .A1(n3189), .B0(n3188), .Y(n3214) );
INVX2TS U4147 ( .A(n3214), .Y(n3209) );
INVX2TS U4148 ( .A(n3190), .Y(n3193) );
INVX2TS U4149 ( .A(n3191), .Y(n3192) );
OAI21X1TS U4150 ( .A0(n3209), .A1(n3193), .B0(n3192), .Y(n3205) );
INVX2TS U4151 ( .A(n3194), .Y(n3203) );
INVX2TS U4152 ( .A(n3202), .Y(n3195) );
AOI21X1TS U4153 ( .A0(n3205), .A1(n3203), .B0(n3195), .Y(n3200) );
NAND2X1TS U4154 ( .A(n3198), .B(n3197), .Y(n3199) );
XOR2X1TS U4155 ( .A(n3200), .B(n3199), .Y(n3201) );
NAND2X1TS U4156 ( .A(n3203), .B(n3202), .Y(n3204) );
XNOR2X1TS U4157 ( .A(n3205), .B(n3204), .Y(n3206) );
INVX2TS U4158 ( .A(n3207), .Y(n3213) );
NAND2X1TS U4159 ( .A(n3213), .B(n3211), .Y(n3208) );
XOR2X1TS U4160 ( .A(n3209), .B(n3208), .Y(n3210) );
INVX2TS U4161 ( .A(n3211), .Y(n3212) );
AOI21X1TS U4162 ( .A0(n3214), .A1(n3213), .B0(n3212), .Y(n3219) );
INVX2TS U4163 ( .A(n3215), .Y(n3217) );
NAND2X1TS U4164 ( .A(n3217), .B(n3216), .Y(n3218) );
XOR2X1TS U4165 ( .A(n3219), .B(n3218), .Y(n3220) );
INVX2TS U4166 ( .A(n3221), .Y(n3224) );
INVX2TS U4167 ( .A(n3222), .Y(n3223) );
OAI21X1TS U4168 ( .A0(n3244), .A1(n3224), .B0(n3223), .Y(n3249) );
INVX2TS U4169 ( .A(n3225), .Y(n3247) );
INVX2TS U4170 ( .A(n3246), .Y(n3226) );
AOI21X1TS U4171 ( .A0(n3249), .A1(n3247), .B0(n3226), .Y(n3231) );
INVX2TS U4172 ( .A(n3227), .Y(n3229) );
NAND2X1TS U4173 ( .A(n3229), .B(n3228), .Y(n3230) );
XOR2X1TS U4174 ( .A(n3231), .B(n3230), .Y(n3233) );
INVX2TS U4175 ( .A(n3234), .Y(n3236) );
NAND2X1TS U4176 ( .A(n3236), .B(n3235), .Y(n3237) );
XNOR2X1TS U4177 ( .A(n3238), .B(n3237), .Y(n3239) );
INVX2TS U4178 ( .A(n3240), .Y(n3242) );
NAND2X1TS U4179 ( .A(n3242), .B(n3241), .Y(n3243) );
XOR2X1TS U4180 ( .A(n3244), .B(n3243), .Y(n3245) );
NAND2X1TS U4181 ( .A(n3247), .B(n3246), .Y(n3248) );
XNOR2X1TS U4182 ( .A(n3249), .B(n3248), .Y(n3250) );
INVX2TS U4183 ( .A(n3251), .Y(n3278) );
AOI21X1TS U4184 ( .A0(n3278), .A1(n3253), .B0(n3252), .Y(n3264) );
INVX2TS U4185 ( .A(n3254), .Y(n3256) );
NAND2X1TS U4186 ( .A(n3256), .B(n3255), .Y(n3257) );
XNOR2X1TS U4187 ( .A(n3258), .B(n3257), .Y(n3259) );
INVX2TS U4188 ( .A(n3260), .Y(n3262) );
NAND2X1TS U4189 ( .A(n3262), .B(n3261), .Y(n3263) );
XOR2X1TS U4190 ( .A(n3264), .B(n3263), .Y(n3266) );
INVX2TS U4191 ( .A(n3267), .Y(n3276) );
INVX2TS U4192 ( .A(n3275), .Y(n3268) );
AOI21X1TS U4193 ( .A0(n3278), .A1(n3276), .B0(n3268), .Y(n3273) );
INVX2TS U4194 ( .A(n3269), .Y(n3271) );
NAND2X1TS U4195 ( .A(n3271), .B(n3270), .Y(n3272) );
XOR2X1TS U4196 ( .A(n3273), .B(n3272), .Y(n3274) );
NAND2X1TS U4197 ( .A(n3276), .B(n3275), .Y(n3277) );
XNOR2X1TS U4198 ( .A(n3278), .B(n3277), .Y(n3279) );
INVX2TS U4199 ( .A(n3280), .Y(n3283) );
XOR2X1TS U4200 ( .A(n3282), .B(n3283), .Y(n3281) );
INVX2TS U4201 ( .A(n3284), .Y(n3286) );
NAND2X1TS U4202 ( .A(n3286), .B(n3285), .Y(n3287) );
XNOR2X1TS U4203 ( .A(n3288), .B(n3287), .Y(n3289) );
XNOR2X1TS U4204 ( .A(n3291), .B(n3290), .Y(n3292) );
MXI2X1TS U4205 ( .A(add_overflow_flag), .B(n3727), .S0(n3293), .Y(n1440) );
OAI211X1TS U4206 ( .A0(n3299), .A1(n3794), .B0(n3298), .C0(n3297), .Y(n3353)
);
AOI21X1TS U4207 ( .A0(n3788), .A1(Add_Subt_result[3]), .B0(
Add_Subt_result[5]), .Y(n3305) );
AOI21X1TS U4208 ( .A0(n3796), .A1(Add_Subt_result[39]), .B0(
Add_Subt_result[41]), .Y(n3300) );
OAI22X1TS U4209 ( .A0(n3301), .A1(Add_Subt_result[22]), .B0(n3300), .B1(
n3425), .Y(n3302) );
INVX2TS U4210 ( .A(n3338), .Y(n3325) );
NOR2X1TS U4211 ( .A(Add_Subt_result[27]), .B(Add_Subt_result[28]), .Y(n3312)
);
NAND2X1TS U4212 ( .A(n3312), .B(Add_Subt_result[26]), .Y(n3309) );
OA21XLTS U4213 ( .A0(n3316), .A1(n3309), .B0(n3308), .Y(n3310) );
OAI21XLTS U4214 ( .A0(Add_Subt_result[8]), .A1(n3797), .B0(n3678), .Y(n3318)
);
NAND2X1TS U4215 ( .A(n3314), .B(Add_Subt_result[43]), .Y(n3362) );
AOI21X1TS U4216 ( .A0(n3319), .A1(n3318), .B0(n3317), .Y(n3437) );
OAI21XLTS U4217 ( .A0(Add_Subt_result[10]), .A1(Add_Subt_result[8]), .B0(
n3320), .Y(n3321) );
OAI31X1TS U4218 ( .A0(n3353), .A1(n3325), .A2(n3324), .B0(n3439), .Y(n3326)
);
OAI2BB1X1TS U4219 ( .A0N(LZA_output[3]), .A1N(n3443), .B0(n3326), .Y(n1500)
);
INVX2TS U4220 ( .A(n3329), .Y(n3347) );
AOI21X1TS U4221 ( .A0(n3786), .A1(Add_Subt_result[27]), .B0(
Add_Subt_result[29]), .Y(n3333) );
AOI22X1TS U4222 ( .A0(n3331), .A1(n3330), .B0(n3428), .B1(
Add_Subt_result[47]), .Y(n3332) );
NAND3X1TS U4223 ( .A(n3338), .B(n3337), .C(n3336), .Y(n3440) );
INVX2TS U4224 ( .A(n3339), .Y(n3341) );
OAI22X1TS U4225 ( .A0(n3343), .A1(n3342), .B0(n3341), .B1(n3340), .Y(n3344)
);
AOI21X1TS U4226 ( .A0(n3345), .A1(Add_Subt_result[22]), .B0(n3344), .Y(n3346) );
AOI21X1TS U4227 ( .A0(n3349), .A1(Add_Subt_result[14]), .B0(n3348), .Y(n3350) );
OAI31X1TS U4228 ( .A0(n3353), .A1(n3440), .A2(n3352), .B0(n3439), .Y(n3354)
);
OAI2BB1X1TS U4229 ( .A0N(LZA_output[2]), .A1N(n3443), .B0(n3354), .Y(n1501)
);
NOR3BX1TS U4230 ( .AN(Add_Subt_result[44]), .B(Add_Subt_result[46]), .C(
Add_Subt_result[45]), .Y(n3358) );
OAI31X1TS U4231 ( .A0(n3358), .A1(Add_Subt_result[47]), .A2(
Add_Subt_result[48]), .B0(n3357), .Y(n3360) );
OAI2BB1X1TS U4232 ( .A0N(n3361), .A1N(n3360), .B0(n3359), .Y(n3363) );
AOI21X1TS U4233 ( .A0(n3366), .A1(Add_Subt_result[28]), .B0(n3365), .Y(n3367) );
OAI2BB1X1TS U4234 ( .A0N(Add_Subt_result[16]), .A1N(n3368), .B0(n3367), .Y(
n3369) );
OAI31X1TS U4235 ( .A0(n3371), .A1(n3370), .A2(n3369), .B0(n3439), .Y(n3372)
);
OAI2BB1X1TS U4236 ( .A0N(LZA_output[1]), .A1N(n3443), .B0(n3372), .Y(n1498)
);
MXI2X1TS U4237 ( .A(n3476), .B(n3467), .S0(n3604), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[54]) );
AOI22X1TS U4238 ( .A0(n3482), .A1(n3638), .B0(n1578), .B1(n3494), .Y(n3377)
);
AOI22X1TS U4239 ( .A0(n3375), .A1(n3374), .B0(n3659), .B1(n3490), .Y(n3376)
);
AOI22X1TS U4240 ( .A0(n3516), .A1(n3494), .B0(n3636), .B1(n3488), .Y(n3379)
);
AOI22X1TS U4241 ( .A0(n3669), .A1(n3490), .B0(n3639), .B1(n3482), .Y(n3378)
);
NAND2X1TS U4242 ( .A(n3382), .B(n3381), .Y(n3386) );
AOI22X1TS U4243 ( .A0(n3482), .A1(n3661), .B0(n3636), .B1(n3495), .Y(n3385)
);
AOI22X1TS U4244 ( .A0(n3639), .A1(n3490), .B0(n3647), .B1(n3494), .Y(n3384)
);
AOI22X1TS U4245 ( .A0(n3638), .A1(n3488), .B0(n2114), .B1(n3489), .Y(n3383)
);
AOI22X1TS U4246 ( .A0(n3388), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .B0(n3387), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[98]), .Y(n3389) );
AOI211X1TS U4247 ( .A0(n3393), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[90]), .B0(n3392), .C0(n3391), .Y(n3394) );
MXI2X1TS U4248 ( .A(n3394), .B(n3809), .S0(n2288), .Y(n1469) );
OAI2BB1X1TS U4249 ( .A0N(n3398), .A1N(n3397), .B0(n3396), .Y(n1444) );
INVX2TS U4250 ( .A(n3399), .Y(n3401) );
INVX2TS U4251 ( .A(n3407), .Y(n3408) );
AOI211X1TS U4252 ( .A0(n3411), .A1(n3410), .B0(n3409), .C0(n3408), .Y(n3416)
);
NOR3BX1TS U4253 ( .AN(Add_Subt_result[17]), .B(n3423), .C(
Add_Subt_result[18]), .Y(n3433) );
AOI21X1TS U4254 ( .A0(n3808), .A1(Add_Subt_result[49]), .B0(
Add_Subt_result[51]), .Y(n3424) );
AOI2BB1XLTS U4255 ( .A0N(n3424), .A1N(Add_Subt_result[52]), .B0(
Add_Subt_result[53]), .Y(n3431) );
AOI211X1TS U4256 ( .A0(n3434), .A1(Add_Subt_result[35]), .B0(n3433), .C0(
n3432), .Y(n3436) );
NAND4X1TS U4257 ( .A(n3438), .B(n3437), .C(n3436), .D(n3435), .Y(n3441) );
OAI2BB1X1TS U4258 ( .A0N(LZA_output[0]), .A1N(n3443), .B0(n3442), .Y(n1499)
);
INVX2TS U4259 ( .A(n3455), .Y(n3446) );
INVX2TS U4260 ( .A(n3461), .Y(n3451) );
INVX2TS U4261 ( .A(n3455), .Y(n3452) );
INVX2TS U4262 ( .A(n3458), .Y(n3453) );
INVX2TS U4263 ( .A(n3455), .Y(n3454) );
INVX2TS U4264 ( .A(n3461), .Y(n3463) );
INVX2TS U4265 ( .A(n3457), .Y(n3460) );
OA22X1TS U4266 ( .A0(n3460), .A1(exp_oper_result[0]), .B0(n3459), .B1(
final_result_ieee[52]), .Y(n1425) );
OA22X1TS U4267 ( .A0(n3460), .A1(exp_oper_result[1]), .B0(n3459), .B1(
final_result_ieee[53]), .Y(n1424) );
OA22X1TS U4268 ( .A0(n3460), .A1(exp_oper_result[2]), .B0(n3459), .B1(
final_result_ieee[54]), .Y(n1423) );
OA22X1TS U4269 ( .A0(n3460), .A1(exp_oper_result[3]), .B0(n3459), .B1(
final_result_ieee[55]), .Y(n1422) );
OA22X1TS U4270 ( .A0(n3455), .A1(exp_oper_result[4]), .B0(n3458), .B1(
final_result_ieee[56]), .Y(n1421) );
OA22X1TS U4271 ( .A0(n3460), .A1(exp_oper_result[5]), .B0(n3459), .B1(
final_result_ieee[57]), .Y(n1420) );
OA22X1TS U4272 ( .A0(n3460), .A1(exp_oper_result[6]), .B0(n3461), .B1(
final_result_ieee[58]), .Y(n1419) );
OA22X1TS U4273 ( .A0(n3460), .A1(exp_oper_result[7]), .B0(n3459), .B1(
final_result_ieee[59]), .Y(n1418) );
OA22X1TS U4274 ( .A0(n3460), .A1(exp_oper_result[8]), .B0(n3461), .B1(
final_result_ieee[60]), .Y(n1417) );
OA22X1TS U4275 ( .A0(n3460), .A1(exp_oper_result[9]), .B0(n3461), .B1(
final_result_ieee[61]), .Y(n1416) );
OA22X1TS U4276 ( .A0(n3460), .A1(exp_oper_result[10]), .B0(n3461), .B1(
final_result_ieee[62]), .Y(n1415) );
OAI211XLTS U4277 ( .A0(underflow_flag), .A1(sign_final_result), .B0(n3461),
.C0(n3813), .Y(n3462) );
OAI2BB1X1TS U4278 ( .A0N(final_result_ieee[63]), .A1N(n3463), .B0(n3462),
.Y(n1361) );
OAI22X1TS U4279 ( .A0(n3465), .A1(n3487), .B0(n3464), .B1(n3481), .Y(n3480)
);
OAI22X1TS U4280 ( .A0(n3469), .A1(n3468), .B0(n3467), .B1(n3466), .Y(n3479)
);
OAI22X1TS U4281 ( .A0(n3473), .A1(n3472), .B0(n3471), .B1(n3470), .Y(n3478)
);
OAI22X1TS U4282 ( .A0(n3476), .A1(n3475), .B0(n3474), .B1(n2124), .Y(n3477)
);
OR4X2TS U4283 ( .A(n3480), .B(n3479), .C(n3478), .D(n3477), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[48]) );
INVX2TS U4284 ( .A(n3481), .Y(n3647) );
AOI22X1TS U4285 ( .A0(n3661), .A1(n3490), .B0(n3631), .B1(n3488), .Y(n3486)
);
AOI22X1TS U4286 ( .A0(n1578), .A1(n3493), .B0(n3667), .B1(n3494), .Y(n3485)
);
AOI22X1TS U4287 ( .A0(n3516), .A1(n3495), .B0(n3659), .B1(n3491), .Y(n3484)
);
AOI22X1TS U4288 ( .A0(n3639), .A1(n3489), .B0(n3482), .B1(n3671), .Y(n3483)
);
AOI22X1TS U4289 ( .A0(n3663), .A1(n3489), .B0(n3646), .B1(n3488), .Y(n3500)
);
AOI22X1TS U4290 ( .A0(n3669), .A1(n3491), .B0(n3583), .B1(n3490), .Y(n3499)
);
AOI22X1TS U4291 ( .A0(n3648), .A1(n3493), .B0(n3659), .B1(n3492), .Y(n3498)
);
AOI22X1TS U4292 ( .A0(n3639), .A1(n3495), .B0(n3641), .B1(n3494), .Y(n3497)
);
AOI22X1TS U4293 ( .A0(n3563), .A1(n3525), .B0(n3665), .B1(n3532), .Y(n3508)
);
AOI22X1TS U4294 ( .A0(n3651), .A1(n3501), .B0(n1578), .B1(n1603), .Y(n3507)
);
AOI22X1TS U4295 ( .A0(n3667), .A1(n3502), .B0(n3617), .B1(n3543), .Y(n3506)
);
NAND2X1TS U4296 ( .A(n3504), .B(n3503), .Y(n3505) );
AOI22X1TS U4297 ( .A0(n3496), .A1(n3532), .B0(n3638), .B1(n1603), .Y(n3509)
);
AOI22X1TS U4298 ( .A0(n3647), .A1(n3525), .B0(n3623), .B1(n3512), .Y(n3514)
);
AOI22X1TS U4299 ( .A0(n3669), .A1(n3543), .B0(n3636), .B1(n3550), .Y(n3513)
);
AOI22X1TS U4300 ( .A0(n3496), .A1(n1603), .B0(n3516), .B1(n3543), .Y(n3517)
);
AOI22X1TS U4301 ( .A0(n3663), .A1(n3532), .B0(n3646), .B1(n3525), .Y(n3522)
);
AOI22X1TS U4302 ( .A0(n1579), .A1(n3550), .B0(n3659), .B1(n3557), .Y(n3521)
);
AOI22X1TS U4303 ( .A0(n3631), .A1(n3543), .B0(n3646), .B1(n1603), .Y(n3529)
);
AOI22X1TS U4304 ( .A0(n3583), .A1(n3532), .B0(n1579), .B1(n3564), .Y(n3528)
);
AOI22X1TS U4305 ( .A0(n3548), .A1(Add_Subt_result[36]), .B0(DmP[16]), .B1(
n3569), .Y(n3524) );
OAI2BB1X2TS U4306 ( .A0N(Add_Subt_result[18]), .A1N(n2103), .B0(n3524), .Y(
n3571) );
AOI22X1TS U4307 ( .A0(n3516), .A1(n3557), .B0(n3617), .B1(n3571), .Y(n3527)
);
AOI22X1TS U4308 ( .A0(n3641), .A1(n3525), .B0(n3639), .B1(n3550), .Y(n3526)
);
AOI22X1TS U4309 ( .A0(n3663), .A1(n3550), .B0(n3646), .B1(n3543), .Y(n3536)
);
AOI22X1TS U4310 ( .A0(n3667), .A1(n1603), .B0(n1578), .B1(n3571), .Y(n3535)
);
BUFX3TS U4311 ( .A(n3530), .Y(n3596) );
AOI22X1TS U4312 ( .A0(n3596), .A1(Add_Subt_result[37]), .B0(DmP[15]), .B1(
n3569), .Y(n3531) );
OAI2BB1X2TS U4313 ( .A0N(Add_Subt_result[17]), .A1N(n3556), .B0(n3531), .Y(
n3578) );
AOI22X1TS U4314 ( .A0(n3648), .A1(n3564), .B0(n3659), .B1(n3578), .Y(n3534)
);
AOI22X1TS U4315 ( .A0(n3641), .A1(n3532), .B0(n3649), .B1(n3557), .Y(n3533)
);
AOI22X1TS U4316 ( .A0(n3647), .A1(n3557), .B0(n3646), .B1(n3550), .Y(n3541)
);
AOI22X1TS U4317 ( .A0(n3543), .A1(n3583), .B0(n1579), .B1(n3578), .Y(n3540)
);
AOI22X1TS U4318 ( .A0(n3596), .A1(Add_Subt_result[38]), .B0(DmP[14]), .B1(
n3569), .Y(n3537) );
OAI2BB1X2TS U4319 ( .A0N(Add_Subt_result[16]), .A1N(n3657), .B0(n3537), .Y(
n3585) );
AOI22X1TS U4320 ( .A0(n3638), .A1(n3571), .B0(n3617), .B1(n3585), .Y(n3539)
);
AOI22X1TS U4321 ( .A0(n3671), .A1(n1603), .B0(n3639), .B1(n3564), .Y(n3538)
);
AOI22X1TS U4322 ( .A0(n3631), .A1(n3564), .B0(n3646), .B1(n3557), .Y(n3547)
);
AOI22X1TS U4323 ( .A0(n3583), .A1(n3550), .B0(n3669), .B1(n3585), .Y(n3546)
);
AOI22X1TS U4324 ( .A0(n3596), .A1(Add_Subt_result[39]), .B0(DmP[13]), .B1(
n3569), .Y(n3542) );
OAI2BB1X2TS U4325 ( .A0N(Add_Subt_result[15]), .A1N(n2103), .B0(n3542), .Y(
n3591) );
AOI22X1TS U4326 ( .A0(n3638), .A1(n3578), .B0(n3636), .B1(n3591), .Y(n3545)
);
AOI22X1TS U4327 ( .A0(n3651), .A1(n3543), .B0(n3563), .B1(n3571), .Y(n3544)
);
AOI22X1TS U4328 ( .A0(n3647), .A1(n3571), .B0(n3646), .B1(n3564), .Y(n3554)
);
AOI22X1TS U4329 ( .A0(n3667), .A1(n3557), .B0(n3669), .B1(n3591), .Y(n3553)
);
AOI22X1TS U4330 ( .A0(n3548), .A1(Add_Subt_result[40]), .B0(DmP[12]), .B1(
n3569), .Y(n3549) );
OAI2BB1X2TS U4331 ( .A0N(Add_Subt_result[14]), .A1N(n3635), .B0(n3549), .Y(
n3598) );
AOI22X1TS U4332 ( .A0(n3638), .A1(n3585), .B0(n3617), .B1(n3598), .Y(n3552)
);
AOI22X1TS U4333 ( .A0(n3649), .A1(n3578), .B0(n3671), .B1(n3550), .Y(n3551)
);
AOI22X1TS U4334 ( .A0(n3661), .A1(n3571), .B0(n3663), .B1(n3578), .Y(n3561)
);
AOI22X1TS U4335 ( .A0(n3583), .A1(n3564), .B0(n1578), .B1(n3598), .Y(n3560)
);
AOI22X1TS U4336 ( .A0(n3596), .A1(Add_Subt_result[41]), .B0(DmP[11]), .B1(
n3569), .Y(n3555) );
OAI2BB1X2TS U4337 ( .A0N(Add_Subt_result[13]), .A1N(n2087), .B0(n3555), .Y(
n3605) );
AOI22X1TS U4338 ( .A0(n3516), .A1(n3591), .B0(n3636), .B1(n3605), .Y(n3559)
);
AOI22X1TS U4339 ( .A0(n3651), .A1(n3557), .B0(n3563), .B1(n3585), .Y(n3558)
);
AOI22X1TS U4340 ( .A0(n3647), .A1(n3585), .B0(n3661), .B1(n3578), .Y(n3568)
);
AOI22X1TS U4341 ( .A0(n1578), .A1(n3605), .B0(n3667), .B1(n3571), .Y(n3567)
);
AOI22X1TS U4342 ( .A0(n3596), .A1(Add_Subt_result[42]), .B0(DmP[10]), .B1(
n3569), .Y(n3562) );
OAI21X4TS U4343 ( .A0(n1615), .A1(n3800), .B0(n3562), .Y(n3611) );
AOI22X1TS U4344 ( .A0(n3516), .A1(n3598), .B0(n3617), .B1(n3611), .Y(n3566)
);
AOI22X1TS U4345 ( .A0(n3641), .A1(n3564), .B0(n3649), .B1(n3591), .Y(n3565)
);
AOI22X1TS U4346 ( .A0(n3631), .A1(n3591), .B0(n3646), .B1(n3585), .Y(n3576)
);
AOI22X1TS U4347 ( .A0(n3611), .A1(n1579), .B0(n3583), .B1(n3578), .Y(n3575)
);
AOI22X1TS U4348 ( .A0(n3596), .A1(Add_Subt_result[43]), .B0(DmP[9]), .B1(
n3569), .Y(n3570) );
OAI2BB1X2TS U4349 ( .A0N(Add_Subt_result[11]), .A1N(n3635), .B0(n3570), .Y(
n3618) );
AOI22X1TS U4350 ( .A0(n3648), .A1(n3605), .B0(n3659), .B1(n3618), .Y(n3574)
);
AOI22X1TS U4351 ( .A0(n3671), .A1(n3571), .B0(n3563), .B1(n3598), .Y(n3573)
);
AOI22X1TS U4352 ( .A0(n3663), .A1(n3598), .B0(n3646), .B1(n3591), .Y(n3582)
);
AOI22X1TS U4353 ( .A0(n1578), .A1(n3618), .B0(n3637), .B1(n3585), .Y(n3581)
);
AOI22X1TS U4354 ( .A0(n3596), .A1(Add_Subt_result[44]), .B0(DmP[8]), .B1(
n3624), .Y(n3577) );
OAI2BB1X2TS U4355 ( .A0N(Add_Subt_result[10]), .A1N(n3635), .B0(n3577), .Y(
n3626) );
AOI22X1TS U4356 ( .A0(n3648), .A1(n3611), .B0(n3659), .B1(n3626), .Y(n3580)
);
AOI22X1TS U4357 ( .A0(n3563), .A1(n3605), .B0(n3671), .B1(n3578), .Y(n3579)
);
AOI22X1TS U4358 ( .A0(n3661), .A1(n3598), .B0(n3647), .B1(n3605), .Y(n3589)
);
AOI22X1TS U4359 ( .A0(n3583), .A1(n3591), .B0(n3669), .B1(n3626), .Y(n3588)
);
AOI22X1TS U4360 ( .A0(n3596), .A1(Add_Subt_result[45]), .B0(DmP[7]), .B1(
n3624), .Y(n3584) );
OAI21X4TS U4361 ( .A0(n2108), .A1(n3678), .B0(n3584), .Y(n3640) );
AOI22X1TS U4362 ( .A0(n3640), .A1(n3604), .B0(n3665), .B1(n3618), .Y(n3587)
);
AOI22X1TS U4363 ( .A0(n3651), .A1(n3585), .B0(n3639), .B1(n3611), .Y(n3586)
);
AOI22X1TS U4364 ( .A0(n3611), .A1(n3647), .B0(n3661), .B1(n3605), .Y(n3595)
);
AOI22X1TS U4365 ( .A0(n3583), .A1(n3598), .B0(n1579), .B1(n3640), .Y(n3594)
);
AOI22X1TS U4366 ( .A0(n3596), .A1(Add_Subt_result[46]), .B0(DmP[6]), .B1(
n3624), .Y(n3590) );
OAI2BB1X2TS U4367 ( .A0N(Add_Subt_result[8]), .A1N(n3635), .B0(n3590), .Y(
n3650) );
AOI22X1TS U4368 ( .A0(n3516), .A1(n3626), .B0(n3617), .B1(n3650), .Y(n3593)
);
AOI22X1TS U4369 ( .A0(n2023), .A1(n3618), .B0(n3641), .B1(n3591), .Y(n3592)
);
AOI22X1TS U4370 ( .A0(n3611), .A1(n3661), .B0(n3631), .B1(n3618), .Y(n3602)
);
AOI22X1TS U4371 ( .A0(n3669), .A1(n3650), .B0(n3637), .B1(n3605), .Y(n3601)
);
AOI22X1TS U4372 ( .A0(n3596), .A1(Add_Subt_result[47]), .B0(DmP[5]), .B1(
n3624), .Y(n3597) );
OAI21X4TS U4373 ( .A0(n2108), .A1(n3797), .B0(n3597), .Y(n3672) );
AOI22X1TS U4374 ( .A0(n3516), .A1(n3640), .B0(n3672), .B1(n3604), .Y(n3600)
);
AOI22X1TS U4375 ( .A0(n3641), .A1(n3598), .B0(n3496), .B1(n3626), .Y(n3599)
);
AOI22X1TS U4376 ( .A0(n3631), .A1(n3626), .B0(n3623), .B1(n3618), .Y(n3609)
);
AOI22X1TS U4377 ( .A0(n3667), .A1(n3611), .B0(n3672), .B1(n3669), .Y(n3608)
);
AOI22X1TS U4378 ( .A0(n3633), .A1(Add_Subt_result[48]), .B0(DmP[4]), .B1(
n3624), .Y(n3603) );
OAI2BB1X2TS U4379 ( .A0N(Add_Subt_result[6]), .A1N(n3635), .B0(n3603), .Y(
n3666) );
AOI22X1TS U4380 ( .A0(n3665), .A1(n3650), .B0(n3604), .B1(n3666), .Y(n3607)
);
AOI22X1TS U4381 ( .A0(n3640), .A1(n3649), .B0(n3641), .B1(n3605), .Y(n3606)
);
AOI22X1TS U4382 ( .A0(n3647), .A1(n3640), .B0(n3623), .B1(n3626), .Y(n3615)
);
AOI22X1TS U4383 ( .A0(n3669), .A1(n3666), .B0(n3667), .B1(n3618), .Y(n3614)
);
AOI22X1TS U4384 ( .A0(n3633), .A1(Add_Subt_result[49]), .B0(DmP[3]), .B1(
n3624), .Y(n3610) );
OAI2BB1X2TS U4385 ( .A0N(Add_Subt_result[5]), .A1N(n3635), .B0(n3610), .Y(
n3660) );
AOI22X1TS U4386 ( .A0(n3672), .A1(n3665), .B0(n3604), .B1(n3660), .Y(n3613)
);
AOI22X1TS U4387 ( .A0(n3671), .A1(n3611), .B0(n3496), .B1(n3650), .Y(n3612)
);
AOI22X1TS U4388 ( .A0(n3631), .A1(n3650), .B0(n3623), .B1(n3640), .Y(n3622)
);
AOI22X1TS U4389 ( .A0(n3667), .A1(n3626), .B0(n1578), .B1(n3660), .Y(n3621)
);
AOI22X1TS U4390 ( .A0(n3633), .A1(Add_Subt_result[50]), .B0(DmP[2]), .B1(
n3624), .Y(n3616) );
AOI22X1TS U4391 ( .A0(n3638), .A1(n3666), .B0(n3617), .B1(n3662), .Y(n3620)
);
AOI22X1TS U4392 ( .A0(n3672), .A1(n3639), .B0(n3651), .B1(n3618), .Y(n3619)
);
AOI22X1TS U4393 ( .A0(n3672), .A1(n3631), .B0(n3623), .B1(n3650), .Y(n3630)
);
AOI22X1TS U4394 ( .A0(n3667), .A1(n3640), .B0(n3669), .B1(n3662), .Y(n3629)
);
AOI22X1TS U4395 ( .A0(n3633), .A1(Add_Subt_result[51]), .B0(DmP[1]), .B1(
n3624), .Y(n3625) );
AOI22X1TS U4396 ( .A0(n3665), .A1(n3660), .B0(n3636), .B1(n3670), .Y(n3628)
);
AOI22X1TS U4397 ( .A0(n3671), .A1(n3626), .B0(n3639), .B1(n3666), .Y(n3627)
);
AOI22X1TS U4398 ( .A0(n3672), .A1(n3661), .B0(n3663), .B1(n3666), .Y(n3645)
);
AOI22X1TS U4399 ( .A0(n3633), .A1(Add_Subt_result[52]), .B0(DmP[0]), .B1(
n3632), .Y(n3634) );
OAI2BB1X1TS U4400 ( .A0N(Add_Subt_result[2]), .A1N(n3635), .B0(n3634), .Y(
n3664) );
AOI22X1TS U4401 ( .A0(n3667), .A1(n3650), .B0(n3604), .B1(n3664), .Y(n3644)
);
AOI22X1TS U4402 ( .A0(n3648), .A1(n3662), .B0(n1579), .B1(n3670), .Y(n3643)
);
AOI22X1TS U4403 ( .A0(n3651), .A1(n3640), .B0(n3563), .B1(n3660), .Y(n3642)
);
AOI22X1TS U4404 ( .A0(n3663), .A1(n3660), .B0(n3646), .B1(n3666), .Y(n3655)
);
AOI22X1TS U4405 ( .A0(n3583), .A1(n3672), .B0(n1579), .B1(n3664), .Y(n3654)
);
AOI22X1TS U4406 ( .A0(n3665), .A1(n3670), .B0(n3604), .B1(n3668), .Y(n3653)
);
AOI22X1TS U4407 ( .A0(n3671), .A1(n3650), .B0(n3649), .B1(n3662), .Y(n3652)
);
AOI22X1TS U4408 ( .A0(n3661), .A1(n3660), .B0(n3636), .B1(n3658), .Y(n3676)
);
AOI22X1TS U4409 ( .A0(n3665), .A1(n3664), .B0(n3663), .B1(n3662), .Y(n3675)
);
AOI22X1TS U4410 ( .A0(n1578), .A1(n3668), .B0(n3583), .B1(n3666), .Y(n3674)
);
AOI22X1TS U4411 ( .A0(n3672), .A1(n3651), .B0(n3496), .B1(n3670), .Y(n3673)
);
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk10.tcl_syn.sdf");
endmodule
|
`timescale 1ns/1ps
`include "global.v"
module ExpRegisterFile(clk_in, reset_in, writeEnableR0_in, writeEnableR1_in, writeValueR0_in, writeValueR1_in,
readSelectA_in, readSelectB_in, readResultA_out, readResultB_out);
//default register width
parameter REGISTER_WIDTH = 'd9;
//default constant register contents
parameter CONST0_VALUE = 9'd0; //zero
parameter CONST1_VALUE = 9'd1; //one
parameter CONST2_VALUE = 9'd31; //radix point position
parameter CONST3_VALUE = 9'd158; //exponent const used by int2fp
parameter CONST4_VALUE = 9'd127; //BIAS
parameter CONST5_VALUE = 9'd511; //all ones
//PORTS
input clk_in, reset_in;
input writeEnableR0_in, writeEnableR1_in;
input [REGISTER_WIDTH-1:0] writeValueR0_in, writeValueR1_in;
input [2:0] readSelectA_in, readSelectB_in;
output reg [REGISTER_WIDTH-1:0] readResultA_out, readResultB_out;
//INTERNAL REGISTERS
//GPR
reg [REGISTER_WIDTH-1:0] reg0, reg1;
always @(readSelectA_in, readSelectB_in, reg0, reg1) begin
case (readSelectA_in)
3'b000: readResultA_out = reg0;
3'b001: readResultA_out = reg1;
3'b010: readResultA_out = CONST0_VALUE;
3'b011: readResultA_out = CONST1_VALUE;
3'b100: readResultA_out = CONST2_VALUE;
3'b101: readResultA_out = CONST3_VALUE;
3'b110: readResultA_out = CONST4_VALUE;
3'b111: readResultA_out = CONST5_VALUE;
endcase
case (readSelectB_in)
3'b000: readResultB_out = reg0;
3'b001: readResultB_out = reg1;
3'b010: readResultB_out = CONST0_VALUE;
3'b011: readResultB_out = CONST1_VALUE;
3'b100: readResultB_out = CONST2_VALUE;
3'b101: readResultB_out = CONST3_VALUE;
3'b110: readResultB_out = CONST4_VALUE;
3'b111: readResultB_out = CONST5_VALUE;
endcase
end
always @(posedge clk_in) begin
if (reset_in) begin // reset registers?
reg0 <= 0;
reg1 <= 0;
end else begin
//update reg0?
if (writeEnableR0_in) reg0 <= writeValueR0_in;
//update reg1?
if (writeEnableR1_in) reg1 <= writeValueR1_in;
end
end
endmodule
|
// DESCRIPTION: Verilator: Simple test of CLkDATA
//
// Trigger the CLKDATA detection
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Jie Xu.
localparam ID_MSB = 1;
module t (/*AUTOARG*/
// Inputs
clk,
res,
res8,
res16
);
input clk;
output res;
output [7:0] res8;
output [15:0] res16;
wire [7:0] clkSet;
wire clk_1;
wire [2:0] clk_3;
wire [3:0] clk_4;
wire clk_final;
reg [7:0] count;
assign clkSet = {8{clk}};
assign clk_4 = clkSet[7:4];
assign clk_1 = clk_4[0];;
// arraysel
assign clk_3 = {3{clk_1}};
assign clk_final = clk_3[0];
// the following two assignment triggers the CLKDATA warning
// because on LHS there are a mix of signals both CLOCK and
// DATA
/* verilator lint_off CLKDATA */
assign res8 = {clk_3, 1'b0, clk_4};
assign res16 = {count, clk_3, clk_1, clk_4};
/* verilator lint_on CLKDATA */
initial
count = 0;
always @(posedge clk_final or negedge clk_final) begin
count = count + 1;
// the following assignment should trigger the CLKDATA warning
// because CLOCK signal is used as DATA in sequential block
/* verilator lint_off CLKDATA */
res <= clk_final;
/* verilator lint_on CLKDATA */
if ( count == 8'hf) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_sel_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
assign v_local = V;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) |
( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : DDR2 controller ODT block
//
// File : alt_ddrx_ddr2_odt_gen.v
//
// Abstract : DDR2 ODT signal generator block
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_ddrx_ddr2_odt_gen
# (parameter
DWIDTH_RATIO = 2,
MEMORY_BURSTLENGTH = 8,
ADD_LAT_BUS_WIDTH = 3,
CTL_OUTPUT_REGD = 0,
TCL_BUS_WIDTH = 4
)
(
ctl_clk,
ctl_reset_n,
mem_tcl,
mem_add_lat,
do_write,
do_read,
int_odt_l,
int_odt_h
);
input ctl_clk;
input ctl_reset_n;
input [TCL_BUS_WIDTH-1:0] mem_tcl;
input [ADD_LAT_BUS_WIDTH-1:0] mem_add_lat;
input do_write;
input do_read;
output int_odt_l;
output int_odt_h;
localparam TCL_PIPE_LENGTH = 2**TCL_BUS_WIDTH; // okay to size this to 4 since max latency in DDR2 is 7+6=13
localparam TAOND = 2;
localparam TAOFD = 2.5;
wire do_write;
wire do_read;
wire [1:0] regd_output;
wire [TCL_BUS_WIDTH-1:0] int_tcwl_unreg;
reg [TCL_BUS_WIDTH-1:0] int_tcwl;
wire int_odt_l;
wire int_odt_h;
reg reg_odt_l;
reg reg_odt_h;
reg combi_odt_l;
reg combi_odt_h;
reg [1:0] offset_code;
reg start_odt_write;
reg start_odt_read;
reg [TCL_PIPE_LENGTH-1:0] do_write_pipe;
reg [TCL_PIPE_LENGTH-1:0] do_read_pipe;
assign int_odt_l = combi_odt_l | reg_odt_l;
assign int_odt_h = combi_odt_h | reg_odt_h;
assign regd_output = (DWIDTH_RATIO == 2) ? (CTL_OUTPUT_REGD ? 2'd1 : 2'd0) : (CTL_OUTPUT_REGD ? 2'd2 : 2'd0);
assign int_tcwl_unreg = (mem_tcl + mem_add_lat + regd_output - 1'b1);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_tcwl <= 0;
else
int_tcwl <= int_tcwl_unreg;
end
always @(*)
begin
if (DWIDTH_RATIO == 2)
begin
if (int_tcwl < 4)
start_odt_write <= do_write;
else
start_odt_write <= do_write_pipe[int_tcwl - 4];
end
else // half rate
begin
if (int_tcwl < 4)
start_odt_write <= do_write;
else
start_odt_write <= do_write_pipe[(int_tcwl - 4)/2];
end
end
always @(*)
begin
if (DWIDTH_RATIO == 2)
begin
if (int_tcwl < 3)
start_odt_read <= do_read;
else
start_odt_read <= do_read_pipe[int_tcwl - 3];
end
else // half rate
begin
if (int_tcwl < 3)
start_odt_read <= do_read;
else
start_odt_read <= do_read_pipe[(int_tcwl - 3)/2];
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
do_write_pipe <= 0;
else
if (do_write)
do_write_pipe <= {do_write_pipe[TCL_PIPE_LENGTH-2:0],do_write};
else
do_write_pipe <= {do_write_pipe[TCL_PIPE_LENGTH-2:0],1'b0};
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
do_read_pipe <= 0;
else
if (do_read)
do_read_pipe <= {do_read_pipe[TCL_PIPE_LENGTH-2:0],do_read};
else
do_read_pipe <= {do_read_pipe[TCL_PIPE_LENGTH-2:0],1'b0};
end
// these blocks already assumes burstlength 8 in half rate and BL4 in full rate
always @(*)
begin
if (DWIDTH_RATIO == 2)
begin
if (start_odt_write || start_odt_read)
combi_odt_l <= 1'b1;
else
combi_odt_l <= 1'b0;
end
else // half rate
begin
if (int_tcwl % 2 == 0) //even
begin
if (start_odt_write)
begin
combi_odt_l <= 1'b1;
combi_odt_h <= 1'b1;
end
else if (start_odt_read)
begin
combi_odt_l <= 1'b0;
combi_odt_h <= 1'b1;
end
else
begin
combi_odt_l <= 1'b0;
combi_odt_h <= 1'b0;
end
end
else
begin
if (start_odt_read)
begin
combi_odt_l <= 1'b1;
combi_odt_h <= 1'b1;
end
else if (start_odt_write)
begin
combi_odt_l <= 1'b0;
combi_odt_h <= 1'b1;
end
else
begin
combi_odt_l <= 1'b0;
combi_odt_h <= 1'b0;
end
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
reg_odt_l <= 1'b0;
reg_odt_h <= 1'b0;
offset_code <= 0;
end
else
if (DWIDTH_RATIO == 2)
begin
reg_odt_h <= 1'b0;
if (start_odt_write || start_odt_read)
begin
reg_odt_l <= 1'b1;
offset_code <= 2;
end
else if (offset_code == 2)
offset_code <= 3;
else if (offset_code == 3)
begin
offset_code <= 0;
reg_odt_l <= 1'b0;
end
end
else
begin
if (int_tcwl % 2 == 0) //even
begin
if (start_odt_write)
begin
reg_odt_l <= 1'b1;
reg_odt_h <= 1'b1;
offset_code <= 3;
end
else if (start_odt_read)
begin
reg_odt_l <= 1'b1;
reg_odt_h <= 1'b1;
offset_code <= 0;
end
else if (reg_odt_h && reg_odt_l && offset_code == 0)
offset_code <= 1;
else if (reg_odt_h && reg_odt_l && offset_code == 1)
begin
reg_odt_l <= 1'b0;
reg_odt_h <= 1'b0;
offset_code <= 0;
end
else if (reg_odt_h && reg_odt_l && offset_code == 3)
begin
reg_odt_h <= 1'b0;
offset_code <= 0;
end
else if (!reg_odt_h && reg_odt_l)
begin
reg_odt_l <= 1'b0;
offset_code <= 0;
end
end
else
begin
if (start_odt_read)
begin
reg_odt_l <= 1'b1;
reg_odt_h <= 1'b1;
offset_code <= 3;
end
else if (start_odt_write)
begin
reg_odt_l <= 1'b1;
reg_odt_h <= 1'b1;
offset_code <= 0;
end
else if (reg_odt_h && reg_odt_l && offset_code == 0)
offset_code <= 1;
else if (reg_odt_h && reg_odt_l && offset_code == 1)
begin
reg_odt_l <= 1'b0;
reg_odt_h <= 1'b0;
offset_code <= 0;
end
else if (reg_odt_h && reg_odt_l && offset_code == 3)
begin
reg_odt_h <= 1'b0;
offset_code <= 0;
end
else if (!reg_odt_h && reg_odt_l)
begin
reg_odt_l <= 1'b0;
offset_code <= 0;
end
end
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : PIO_64_TX_ENGINE.v
//--
//-- Description: 64 bit Local-Link Transmit Unit.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
`define PIO_64_CPLD_FMT_TYPE 7'b10_01010
`define PIO_64_CPL_FMT_TYPE 7'b00_01010
`define PIO_64_TX_RST_STATE 2'b00
`define PIO_64_TX_CPLD_QW1 2'b01
`define PIO_64_TX_CPL_QW1 2'b10
module PIO_64_TX_ENGINE (
clk,
rst_n,
trn_td,
trn_trem_n,
trn_tsof_n,
trn_teof_n,
trn_tsrc_rdy_n,
trn_tsrc_dsc_n,
trn_tdst_rdy_n,
trn_tdst_dsc_n,
req_compl_i,
req_compl_with_data_i,
compl_done_o,
req_tc_i,
req_td_i,
req_ep_i,
req_attr_i,
req_len_i,
req_rid_i,
req_tag_i,
req_be_i,
req_addr_i,
// Read Access
rd_addr_o,
rd_be_o,
rd_data_i,
completer_id_i,
cfg_bus_mstr_enable_i
);
input clk;
input rst_n;
output [63:0] trn_td;
output [7:0] trn_trem_n;
output trn_tsof_n;
output trn_teof_n;
output trn_tsrc_rdy_n;
output trn_tsrc_dsc_n;
input trn_tdst_rdy_n;
input trn_tdst_dsc_n;
input req_compl_i;
input req_compl_with_data_i; // asserted indicates to generate a completion WITH data
// otherwise a completion WITHOUT data will be generated
output compl_done_o;
input [2:0] req_tc_i;
input req_td_i;
input req_ep_i;
input [1:0] req_attr_i;
input [9:0] req_len_i;
input [15:0] req_rid_i;
input [7:0] req_tag_i;
input [7:0] req_be_i;
input [12:0] req_addr_i;
output [10:0] rd_addr_o;
output [3:0] rd_be_o;
input [31:0] rd_data_i;
input [15:0] completer_id_i;
input cfg_bus_mstr_enable_i;
// Local registers
reg [63:0] trn_td;
reg [7:0] trn_trem_n;
reg trn_tsof_n;
reg trn_teof_n;
reg trn_tsrc_rdy_n;
reg trn_tsrc_dsc_n;
reg [11:0] byte_count;
reg [06:0] lower_addr;
reg compl_done_o;
reg req_compl_q;
reg req_compl_with_data_q;
reg [1:0] state;
// Local wires
/*
* Present address and byte enable to memory module
*/
assign rd_addr_o = req_addr_i[12:2];
assign rd_be_o = req_be_i[3:0];
/*
* Calculate byte count based on byte enable
*/
always @ (rd_be_o) begin
casex (rd_be_o[3:0])
4'b1xx1 : byte_count = 12'h004;
4'b01x1 : byte_count = 12'h003;
4'b1x10 : byte_count = 12'h003;
4'b0011 : byte_count = 12'h002;
4'b0110 : byte_count = 12'h002;
4'b1100 : byte_count = 12'h002;
4'b0001 : byte_count = 12'h001;
4'b0010 : byte_count = 12'h001;
4'b0100 : byte_count = 12'h001;
4'b1000 : byte_count = 12'h001;
4'b0000 : byte_count = 12'h001;
endcase
end
/*
* Calculate lower address based on byte enable
*/
always @ (rd_be_o or req_addr_i) begin
casex (rd_be_o[3:0])
4'b0000 : lower_addr = {req_addr_i[6:2], 2'b00};
4'bxxx1 : lower_addr = {req_addr_i[6:2], 2'b00};
4'bxx10 : lower_addr = {req_addr_i[6:2], 2'b01};
4'bx100 : lower_addr = {req_addr_i[6:2], 2'b10};
4'b1000 : lower_addr = {req_addr_i[6:2], 2'b11};
endcase
end
always @ ( posedge clk or negedge rst_n ) begin
if (!rst_n ) begin
req_compl_q <= 1'b0;
req_compl_with_data_q <= 1'b1;
end else begin
req_compl_q <= req_compl_i;
req_compl_with_data_q <= req_compl_with_data_i;
end
end
/*
* Generate Completion with 1 DW Payload or Completion with no data
*/
always @ ( posedge clk or negedge rst_n ) begin
if (!rst_n ) begin
trn_tsof_n <= 1'b1;
trn_teof_n <= 1'b1;
trn_tsrc_rdy_n <= 1'b1;
trn_tsrc_dsc_n <= 1'b1;
trn_td <= 64'b0;
trn_trem_n <= 8'b0;
compl_done_o <= 1'b0;
state <= `PIO_64_TX_RST_STATE;
end else begin
case ( state )
`PIO_64_TX_RST_STATE : begin
if (req_compl_q && req_compl_with_data_q &&
trn_tdst_dsc_n) begin
trn_tsof_n <= 1'b0;
trn_teof_n <= 1'b1;
trn_tsrc_rdy_n <= 1'b0;
trn_td <= { {1'b0},
`PIO_64_CPLD_FMT_TYPE,
{1'b0},
req_tc_i,
{4'b0},
req_td_i,
req_ep_i,
req_attr_i,
{2'b0},
req_len_i,
completer_id_i,
{3'b0},
{1'b0},
byte_count };
trn_trem_n <= 8'b0;
state <= `PIO_64_TX_CPLD_QW1;
end else if (req_compl_q && (!req_compl_with_data_q) &&
trn_tdst_dsc_n) begin
trn_tsof_n <= 1'b0;
trn_teof_n <= 1'b1;
trn_tsrc_rdy_n <= 1'b0;
trn_td <= { {1'b0},
`PIO_64_CPL_FMT_TYPE,
{1'b0},
req_tc_i,
{4'b0},
req_td_i,
req_ep_i,
req_attr_i,
{2'b0},
req_len_i,
completer_id_i,
{3'b0},
{1'b0},
byte_count };
trn_trem_n <= 8'b0;
state <= `PIO_64_TX_CPL_QW1;
end else begin
trn_tsof_n <= 1'b1;
trn_teof_n <= 1'b1;
trn_tsrc_rdy_n <= 1'b1;
trn_tsrc_dsc_n <= 1'b1;
trn_td <= 64'b0;
trn_trem_n <= 8'b0;
compl_done_o <= 1'b0;
state <= `PIO_64_TX_RST_STATE;
end
end
`PIO_64_TX_CPLD_QW1 : begin
if ((!trn_tdst_rdy_n) && (trn_tdst_dsc_n)) begin
trn_tsof_n <= 1'b1;
trn_teof_n <= 1'b0;
trn_tsrc_rdy_n <= 1'b0;
trn_td <= { req_rid_i,
req_tag_i,
{1'b0},
lower_addr,
rd_data_i };
trn_trem_n <= 8'h00;
compl_done_o <= 1'b1;
state <= `PIO_64_TX_RST_STATE;
end else if (!trn_tdst_dsc_n) begin
state <= `PIO_64_TX_RST_STATE;
trn_tsrc_dsc_n <= 1'b0;
end else
state <= `PIO_64_TX_CPLD_QW1;
end
`PIO_64_TX_CPL_QW1 : begin
if ((!trn_tdst_rdy_n) && (trn_tdst_dsc_n)) begin
trn_tsof_n <= 1'b1;
trn_teof_n <= 1'b0;
trn_tsrc_rdy_n <= 1'b0;
trn_td <= { req_rid_i,
req_tag_i,
{1'b0},
lower_addr,
32'h00000000 };
trn_trem_n <= 8'h0F;
compl_done_o <= 1'b1;
state <= `PIO_64_TX_RST_STATE;
end else if (!trn_tdst_dsc_n) begin
state <= `PIO_64_TX_RST_STATE;
trn_tsrc_dsc_n <= 1'b0;
end else
state <= `PIO_64_TX_CPL_QW1;
end
endcase
end
end
endmodule // PIO_64_TX_ENGINE
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 21:06:44 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_clock_splitter_0_0/system_clock_splitter_0_0_stub.v
// Design : system_clock_splitter_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "clock_splitter,Vivado 2016.4" *)
module system_clock_splitter_0_0(clk_in, latch_edge, clk_out)
/* synthesis syn_black_box black_box_pad_pin="clk_in,latch_edge,clk_out" */;
input clk_in;
input latch_edge;
output clk_out;
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_arb_wr_4.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 4 write requests from 4 ports.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_arb_wr_4(
rstn,
sw_clk,
qos1,
qos2,
qos3,
qos4,
prt_dv1,
prt_dv2,
prt_dv3,
prt_dv4,
prt_data1,
prt_data2,
prt_data3,
prt_data4,
prt_addr1,
prt_addr2,
prt_addr3,
prt_addr4,
prt_bytes1,
prt_bytes2,
prt_bytes3,
prt_bytes4,
prt_ack1,
prt_ack2,
prt_ack3,
prt_ack4,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_ack
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
input [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
input prt_dv1, prt_dv2,prt_dv3, prt_dv4, prt_ack;
output reg prt_ack1,prt_ack2,prt_ack3,prt_ack4,prt_req;
output reg [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 4'b100,wait_ack_low = 3'b101;
reg [2:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
prt_req = 0;
if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
serv_req1:begin
state = serv_req1;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack1 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv2) begin
state = serv_req2;
prt_qos = qos2;
prt_req = 1;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
end
serv_req2:begin
state = serv_req2;
prt_ack1 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack2 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv3) begin
state = serv_req3;
prt_qos = qos3;
prt_req = 1;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
state = serv_req4;
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_dv1) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req3:begin
state = serv_req3;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack3 = 1'b1;
// state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv4) begin
state = serv_req4;
prt_qos = qos4;
prt_req = 1;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end
end
end
serv_req4:begin
state = serv_req4;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
if(prt_ack)begin
prt_ack4 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
state = serv_req3;
end
end
end
wait_ack_low:begin
state = wait_ack_low;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(!prt_ack)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2010 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=1;
counter_io c1_data();
counter_io c2_data();
//counter_io c3_data; // IEEE illegal, and VCS doesn't allow non-() as it does with cells
counter_io c3_data();
counter_ansi c1 (.clkm(clk),
.c_data(c1_data),
.i_value(4'h1));
counter_ansi c2 (.clkm(clk),
.c_data(c2_data),
.i_value(4'h2));
`ifdef VERILATOR counter_ansi `else counter_nansi `endif
/**/ c3 (.clkm(clk),
.c_data(c3_data),
.i_value(4'h3));
initial begin
c1_data.value = 4'h4;
c2_data.value = 4'h5;
c3_data.value = 4'h6;
end
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc<2) begin
c1_data.reset <= 1;
c2_data.reset <= 1;
c3_data.reset <= 1;
end
if (cyc==2) begin
c1_data.reset <= 0;
c2_data.reset <= 0;
c3_data.reset <= 0;
end
if (cyc==3) begin
if (c1_data.get_lcl() != 12345) $stop;
end
if (cyc==20) begin
$write("[%0t] c1 cyc%0d: c1 %0x %0x c2 %0x %0x c3 %0x %0x\n", $time, cyc,
c1_data.value, c1_data.reset,
c2_data.value, c2_data.reset,
c3_data.value, c3_data.reset);
if (c1_data.value != 2) $stop;
if (c2_data.value != 3) $stop;
if (c3_data.value != 4) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
interface counter_io;
logic [3:0] value;
logic reset;
integer lcl;
task set_lcl (input integer a); lcl=a; endtask
function integer get_lcl (); return lcl; endfunction
endinterface
interface ifunused;
logic unused;
endinterface
module counter_ansi
(
input clkm,
counter_io c_data,
input logic [3:0] i_value
);
initial begin
c_data.set_lcl(12345);
end
always @ (posedge clkm) begin
c_data.value <= c_data.reset ? i_value : c_data.value + 1;
end
endmodule : counter_ansi
`ifndef VERILATOR
// non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too.
module counter_nansi(clkm, c_data, i_value);
input clkm;
counter_io c_data;
input logic [3:0] i_value;
always @ (posedge clkm) begin
c_data.value <= c_data.reset ? i_value : c_data.value + 1;
end
endmodule : counter_nansi
`endif
// Test uses Verilator --top-module, which means this isn't in the hierarchy
// Other simulators will see it, and is illegal to have unconnected interface
`ifdef VERILATOR
module modunused (ifunused ifinunused);
ifunused ifunused();
endmodule
`endif
|
/* -*- verilog -*-
*
* USRP - Universal Software Radio Peripheral
*
* Copyright (C) 2005 Matt Ettus
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
*/
/*
* This implements a 31-tap halfband filter that decimates by two.
* The coefficients are symmetric, and with the exception of the middle tap,
* every other coefficient is zero. The middle section of taps looks like this:
*
* ..., -1468, 0, 2950, 0, -6158, 0, 20585, 32768, 20585, 0, -6158, 0, 2950, 0, -1468, ...
* |
* middle tap -------+
*
* See coeff_rom.v for the full set. The taps are scaled relative to 32768,
* thus the middle tap equals 1.0. Not counting the middle tap, there are 8
* non-zero taps on each side, and they are symmetric. A naive implementation
* requires a mulitply for each non-zero tap. Because of symmetry, we can
* replace 2 multiplies with 1 add and 1 multiply. Thus, to compute each output
* sample, we need to perform 8 multiplications. Since the middle tap is 1.0,
* we just add the corresponding delay line value.
*
* About timing: We implement this with a single multiplier, so it takes
* 8 cycles to compute a single output. However, since we're decimating by two
* we can accept a new input value every 4 cycles. strobe_in is asserted when
* there's a new input sample available. Depending on the overall decimation
* rate, strobe_in may be asserted less frequently than once every 4 clocks.
* On the output side, we assert strobe_out when output contains a new sample.
*
* Implementation: Every time strobe_in is asserted we store the new data into
* the delay line. We split the delay line into two components, one for the
* even samples, and one for the odd samples. ram16_odd is the delay line for
* the odd samples. This ram is written on each odd assertion of strobe_in, and
* is read on each clock when we're computing the dot product. ram16_even is
* similar, although because it holds the even samples we must be able to read
* two samples from different addresses at the same time, while writing the incoming
* even samples. Thus it's "triple-ported".
*/
module halfband_decim
(input clock, input reset, input enable, input strobe_in, output wire strobe_out,
input wire [15:0] data_in, output reg [15:0] data_out,output wire [15:0] debugctrl);
reg [3:0] rd_addr1;
reg [3:0] rd_addr2;
reg [3:0] phase;
reg [3:0] base_addr;
wire signed [15:0] mac_out,middle_data, sum, coeff;
wire signed [30:0] product;
wire signed [33:0] sum_even;
wire clear;
reg store_odd;
always @(posedge clock)
if(reset)
store_odd <= #1 1'b0;
else
if(strobe_in)
store_odd <= #1 ~store_odd;
wire start = strobe_in & store_odd;
always @(posedge clock)
if(reset)
base_addr <= #1 4'd0;
else if(start)
base_addr <= #1 base_addr + 4'd1;
always @(posedge clock)
if(reset)
phase <= #1 4'd8;
else if (start)
phase <= #1 4'd0;
else if(phase != 4'd8)
phase <= #1 phase + 4'd1;
reg start_d1,start_d2,start_d3,start_d4,start_d5,start_d6,start_d7,start_d8,start_d9,start_dA,start_dB,start_dC,start_dD;
always @(posedge clock)
begin
start_d1 <= #1 start;
start_d2 <= #1 start_d1;
start_d3 <= #1 start_d2;
start_d4 <= #1 start_d3;
start_d5 <= #1 start_d4;
start_d6 <= #1 start_d5;
start_d7 <= #1 start_d6;
start_d8 <= #1 start_d7;
start_d9 <= #1 start_d8;
start_dA <= #1 start_d9;
start_dB <= #1 start_dA;
start_dC <= #1 start_dB;
start_dD <= #1 start_dC;
end // always @ (posedge clock)
reg mult_en, mult_en_pre;
always @(posedge clock)
begin
mult_en_pre <= #1 phase!=8;
mult_en <= #1 mult_en_pre;
end
assign clear = start_d4; // was dC
wire latch_result = start_d4; // was dC
assign strobe_out = start_d5; // was dD
wire acc_en;
always @*
case(phase[2:0])
3'd0 : begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end
3'd1 : begin rd_addr1 = base_addr + 4'd1; rd_addr2 = base_addr + 4'd14; end
3'd2 : begin rd_addr1 = base_addr + 4'd2; rd_addr2 = base_addr + 4'd13; end
3'd3 : begin rd_addr1 = base_addr + 4'd3; rd_addr2 = base_addr + 4'd12; end
3'd4 : begin rd_addr1 = base_addr + 4'd4; rd_addr2 = base_addr + 4'd11; end
3'd5 : begin rd_addr1 = base_addr + 4'd5; rd_addr2 = base_addr + 4'd10; end
3'd6 : begin rd_addr1 = base_addr + 4'd6; rd_addr2 = base_addr + 4'd9; end
3'd7 : begin rd_addr1 = base_addr + 4'd7; rd_addr2 = base_addr + 4'd8; end
default: begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end
endcase // case(phase)
coeff_rom coeff_rom (.clock(clock),.addr(phase[2:0]-3'd1),.data(coeff));
ram16_2sum ram16_even (.clock(clock),.write(strobe_in & ~store_odd),
.wr_addr(base_addr),.wr_data(data_in),
.rd_addr1(rd_addr1),.rd_addr2(rd_addr2),
.sum(sum));
ram16 ram16_odd (.clock(clock),.write(strobe_in & store_odd), // Holds middle items
.wr_addr(base_addr),.wr_data(data_in),
//.rd_addr(base_addr+4'd7),.rd_data(middle_data));
.rd_addr(base_addr+4'd6),.rd_data(middle_data));
mult mult(.clock(clock),.x(coeff),.y(sum),.product(product),.enable_in(mult_en),.enable_out(acc_en));
acc acc(.clock(clock),.reset(reset),.enable_in(acc_en),.enable_out(),
.clear(clear),.addend(product),.sum(sum_even));
wire signed [33:0] dout = sum_even + {{4{middle_data[15]}},middle_data,14'b0}; // We already divided product by 2!!!!
always @(posedge clock)
if(reset)
data_out <= #1 16'd0;
else if(latch_result)
data_out <= #1 dout[30:15] + (dout[33]& |dout[14:0]);
assign debugctrl = { clock,reset,acc_en,mult_en,clear,latch_result,store_odd,strobe_in,strobe_out,phase};
endmodule // halfband_decim
|
// test_intermout_always_comb_1_test.v
module f1_test(a, b, c, d, z);
input a, b, c, d;
output z;
reg z, temp1, temp2;
always @(a or b or c or d)
begin
temp1 = a ^ b;
temp2 = c ^ d;
z = temp1 ^ temp2;
end
endmodule
// test_intermout_always_comb_3_test.v
module f2_test (in1, in2, out);
input in1, in2;
output reg out;
always @ ( in1 or in2)
if(in1 > in2)
out = in1;
else
out = in2;
endmodule
// test_intermout_always_comb_4_test.v
module f3_test(a, b, c);
input b, c;
output reg a;
always @(b or c) begin
a = b;
a = c;
end
endmodule
// test_intermout_always_comb_5_test.v
module f4_test(ctrl, in1, in2, out);
input ctrl;
input in1, in2;
output reg out;
always @ (ctrl or in1 or in2)
if(ctrl)
out = in1 & in2;
else
out = in1 | in2;
endmodule
// test_intermout_always_ff_3_test.v
module f5_NonBlockingEx(clk, merge, er, xmit, fddi, claim);
input clk, merge, er, xmit, fddi;
output reg claim;
reg fcr;
always @(posedge clk)
begin
fcr = er | xmit;
if(merge)
claim = fcr & fddi;
else
claim = fddi;
end
endmodule
// test_intermout_always_ff_4_test.v
module f6_FlipFlop(clk, cs, ns);
input clk;
input [31:0] cs;
output [31:0] ns;
integer is;
always @(posedge clk)
is <= cs;
assign ns = is;
endmodule
// test_intermout_always_ff_5_test.v
module f7_FlipFlop(clock, cs, ns);
input clock;
input [3:0] cs;
output reg [3:0] ns;
reg [3:0] temp;
always @(posedge clock)
begin
temp = cs;
ns = temp;
end
endmodule
// test_intermout_always_ff_6_test.v
module f8_inc(clock, counter);
input clock;
output reg [3:0] counter;
always @(posedge clock)
counter <= counter + 1;
endmodule
// test_intermout_always_ff_8_test.v
module f9_NegEdgeClock(q, d, clk, reset);
input d, clk, reset;
output reg q;
always @(negedge clk or negedge reset)
if(!reset)
q <= 1'b0;
else
q <= d;
endmodule
// test_intermout_always_ff_9_test.v
module f10_MyCounter (clock, preset, updown, presetdata, counter);
input clock, preset, updown;
input [1: 0] presetdata;
output reg [1:0] counter;
always @(posedge clock)
if(preset)
counter <= presetdata;
else
if(updown)
counter <= counter + 1;
else
counter <= counter - 1;
endmodule
// test_intermout_always_latch_1_test.v
module f11_test(en, in, out);
input en;
input [1:0] in;
output reg [2:0] out;
always @ (en or in)
if(en)
out = in + 1;
endmodule
// test_intermout_bufrm_1_test.v
module f12_test(input in, output out);
//no buffer removal
assign out = in;
endmodule
// test_intermout_bufrm_2_test.v
module f13_test(input in, output out);
//intermediate buffers should be removed
wire w1, w2;
assign w1 = in;
assign w2 = w1;
assign out = w2;
endmodule
// test_intermout_bufrm_6_test.v
module f14_test(in, out);
input in;
output out;
wire w1, w2, w3, w4;
assign w1 = in;
assign w2 = w1;
assign w4 = w3;
assign out = w4;
f14_mybuf _f14_mybuf(w2, w3);
endmodule
module f14_mybuf(in, out);
input in;
output out;
wire w1, w2, w3, w4;
assign w1 = in;
assign w2 = w1;
assign out = w2;
endmodule
// test_intermout_bufrm_7_test.v
module f15_test(in1, in2, out);
input in1, in2;
output out;
// Y with cluster of f15_mybuf instances at the junction
wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10;
assign w1 = in1;
assign w2 = w1;
assign w5 = in2;
assign w6 = w5;
assign w10 = w9;
assign out = w10;
f15_mybuf _f15_mybuf0(w2, w3);
f15_mybuf _f15_mybuf1(w3, w4);
f15_mybuf _f15_mybuf2(w6, w7);
f15_mybuf _f15_mybuf3(w7, w4);
f15_mybuf _f15_mybuf4(w4, w8);
f15_mybuf _f15_mybuf5(w8, w9);
endmodule
module f15_mybuf(in, out);
input in;
output out;
wire w1, w2, w3, w4;
assign w1 = in;
assign w2 = w1;
assign out = w2;
endmodule
// test_intermout_exprs_add_test.v
module f16_test(out, in1, in2, vin1, vin2, vout1);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 + in2;
assign vout1 = vin1 + vin2;
endmodule
// test_intermout_exprs_binlogic_test.v
module f17_test(in1, in2, vin1, vin2, out, vout, vin3, vin4, vout1 );
input in1, in2;
input [1:0] vin1;
input [3:0] vin2;
input [1:0] vin3;
input [3:0] vin4;
output vout, vout1;
output out;
assign out = in1 && in2;
assign vout = vin1 && vin2;
assign vout1 = vin3 || vin4;
endmodule
// test_intermout_exprs_bitwiseneg_test.v
module f18_test(output out, input in, output [1:0] vout, input [1:0] vin);
assign out = ~in;
assign vout = ~vin;
endmodule
// test_intermout_exprs_buffer_test.v
module f19_buffer(in, out, vin, vout);
input in;
output out;
input [1:0] vin;
output [1:0] vout;
assign out = in;
assign vout = vin;
endmodule
// test_intermout_exprs_condexpr_mux_test.v
module f20_test(in1, in2, out, vin1, vin2, vin3, vin4, vout1, vout2, en1, ven1, ven2);
input in1, in2, en1, ven1;
input [1:0] ven2;
output out;
input [1:0] vin1, vin2, vin3, vin4;
output [1:0] vout1, vout2;
assign out = en1 ? in1 : in2;
assign vout1 = ven1 ? vin1 : vin2;
assign vout2 = ven2 ? vin3 : vin4;
endmodule
// test_intermout_exprs_condexpr_tribuf_test.v
module f21_test(in, out, en, vin1, vout1, en1);
input in, en, en1;
output out;
input [1:0] vin1;
output [1:0] vout1;
assign out = en ? in : 1'bz;
assign vout1 = en1 ? vin1 : 2'bzz;
endmodule
// test_intermout_exprs_constshift_test.v
module f22_test(in, out, vin, vout, vin1, vout1, vin2, vout2);
input in;
input [3:0] vin, vin1, vin2;
output [3:0] vout, vout1, vout2;
output out;
assign out = in << 1;
assign vout = vin << 2;
assign vout1 = vin1 >> 2;
assign vout2 = vin2 >>> 2;
endmodule
// test_intermout_exprs_const_test.v
module f23_test (out, vout);
output out;
output [7:0] vout;
assign out = 1'b1;
assign vout = 9;
endmodule
// test_intermout_exprs_div_test.v
module f24_test(out, in1, in2, vin1, vin2, vout1);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 / in2;
assign vout1 = vin1 / vin2;
endmodule
// test_intermout_exprs_logicneg_test.v
module f25_test(out, vout, in, vin);
output out, vout;
input in;
input [3:0] vin;
assign out = !in;
assign vout = !vin;
endmodule
// test_intermout_exprs_mod_test.v
module f26_test(out, in1, in2, vin1, vin2, vout1);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 % in2;
assign vout1 = vin1 % vin2;
endmodule
// test_intermout_exprs_mul_test.v
module f27_test(out, in1, in2, vin1, vin2, vout1);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 * in2;
assign vout1 = vin1 * vin2;
endmodule
// test_intermout_exprs_redand_test.v
module f28_test(output out, input [1:0] vin, output out1, input [3:0] vin1);
assign out = &vin;
assign out1 = &vin1;
endmodule
// test_intermout_exprs_redop_test.v
module f29_Reduction (A1, A2, A3, A4, A5, A6, Y1, Y2, Y3, Y4, Y5, Y6);
input [1:0] A1;
input [1:0] A2;
input [1:0] A3;
input [1:0] A4;
input [1:0] A5;
input [1:0] A6;
output Y1, Y2, Y3, Y4, Y5, Y6;
//reg Y1, Y2, Y3, Y4, Y5, Y6;
assign Y1=&A1; //reduction AND
assign Y2=|A2; //reduction OR
assign Y3=~&A3; //reduction NAND
assign Y4=~|A4; //reduction NOR
assign Y5=^A5; //reduction XOR
assign Y6=~^A6; //reduction XNOR
endmodule
// test_intermout_exprs_sub_test.v
module f30_test(out, in1, in2, vin1, vin2, vout1);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 - in2;
assign vout1 = vin1 - vin2;
endmodule
// test_intermout_exprs_unaryminus_test.v
module f31_test(output out, input in, output [31:0] vout, input [31:0] vin);
assign out = -in;
assign vout = -vin;
endmodule
// test_intermout_exprs_unaryplus_test.v
module f32_test(output out, input in);
assign out = +in;
endmodule
// test_intermout_exprs_varshift_test.v
module f33_test(vin0, vout0);
input [2:0] vin0;
output reg [7:0] vout0;
wire [7:0] myreg0, myreg1, myreg2;
integer i;
assign myreg0 = vout0 << vin0;
assign myreg1 = myreg2 >> i;
endmodule
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