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/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module vgafb #(
parameter csr_addr = 4'h0,
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
/* Configuration interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
/* Framebuffer FML 4x64 interface */
output [fml_depth-1:0] fml_adr,
output fml_stb,
input fml_ack,
input [63:0] fml_di,
/* Direct Cache Bus */
output dcb_stb,
output [fml_depth-1:0] dcb_adr,
input [63:0] dcb_dat,
input dcb_hit,
/* VGA pixel clock */
input vga_clk,
/* VGA signal pads */
output vga_psave_n,
output reg vga_hsync_n,
output reg vga_vsync_n,
output vga_sync_n,
output vga_blank_n,
output reg [7:0] vga_r,
output reg [7:0] vga_g,
output reg [7:0] vga_b,
inout vga_sda,
output vga_sdc,
output [1:0] clksel
);
/*
* Control interface
*/
wire vga_rst;
wire [10:0] hres;
wire [10:0] hsync_start;
wire [10:0] hsync_end;
wire [10:0] hscan;
wire [10:0] vres;
wire [10:0] vsync_start;
wire [10:0] vsync_end;
wire [10:0] vscan;
wire [fml_depth-1:0] baseaddress;
wire baseaddress_ack;
wire [17:0] nbursts;
vgafb_ctlif #(
.csr_addr(csr_addr),
.fml_depth(fml_depth)
) ctlif (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.vga_rst(vga_rst),
.hres(hres),
.hsync_start(hsync_start),
.hsync_end(hsync_end),
.hscan(hscan),
.vres(vres),
.vsync_start(vsync_start),
.vsync_end(vsync_end),
.vscan(vscan),
.baseaddress(baseaddress),
.baseaddress_ack(baseaddress_ack),
.nbursts(nbursts),
.vga_sda(vga_sda),
.vga_sdc(vga_sdc),
.clksel(clksel)
);
/*
* Generate signal data
*/
reg hsync_n;
reg vsync_n;
wire pixel_valid;
wire [15:0] pixel_fb;
wire pixel_ack;
wire [15:0] pixel;
wire fifo_full;
reg hactive;
reg vactive;
wire active = hactive & vactive;
assign pixel = active ? pixel_fb : 16'h0000;
wire generate_en;
reg [10:0] hcounter;
reg [10:0] vcounter;
always @(posedge sys_clk) begin
if(vga_rst) begin
hcounter <= 10'd0;
vcounter <= 10'd0;
hactive <= 1'b0;
hsync_n <= 1'b1;
vactive <= 1'b0;
vsync_n <= 1'b1;
end else begin
if(generate_en) begin
hcounter <= hcounter + 10'd1;
if(hcounter == 10'd0) hactive <= 1'b1;
if(hcounter == hres) hactive <= 1'b0;
if(hcounter == hsync_start) hsync_n <= 1'b0;
if(hcounter == hsync_end) hsync_n <= 1'b1;
if(hcounter == hscan) begin
hcounter <= 10'd0;
if(vcounter == vscan)
vcounter <= 10'd0;
else
vcounter <= vcounter + 10'd1;
end
if(vcounter == 10'd0) vactive <= 1'b1;
if(vcounter == vres) vactive <= 1'b0;
if(vcounter == vsync_start) vsync_n <= 1'b0;
if(vcounter == vsync_end) vsync_n <= 1'b1;
end
end
end
assign generate_en = ~fifo_full & (~active | pixel_valid);
assign pixel_ack = ~fifo_full & active & pixel_valid;
vgafb_pixelfeed #(
.fml_depth(fml_depth)
) pixelfeed (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.vga_rst(vga_rst),
.nbursts(nbursts),
.baseaddress(baseaddress),
.baseaddress_ack(baseaddress_ack),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_ack(fml_ack),
.fml_di(fml_di),
.dcb_stb(dcb_stb),
.dcb_adr(dcb_adr),
.dcb_dat(dcb_dat),
.dcb_hit(dcb_hit),
.pixel_valid(pixel_valid),
.pixel(pixel_fb),
.pixel_ack(pixel_ack)
);
/*
* System clock to VGA clock domain crossing is
* acheived by an asynchronous FIFO.
*
* Bits 0-15 are RGB565 pixel data
* Bit 16 is negated Horizontal Sync
* Bit 17 is negated Verical Sync
*/
wire [17:0] fifo_do;
asfifo #(
.data_width(18),
.address_width(10)
) fifo (
.data_out(fifo_do),
.empty(),
.read_en(1'b1),
.clk_read(vga_clk),
.data_in({vsync_n, hsync_n, pixel}),
.full(fifo_full),
.write_en(generate_en),
.clk_write(sys_clk),
.rst(vga_rst)
);
/*
* Drive the VGA pads.
* RGB565 -> RGB888 color space conversion is also performed here
* by bit shifting and replicating the most significant bits of
* the input into the least significant bits of the output left
* undefined by the shifting.
*/
assign vga_sync_n = 1'b0; /* Sync-on-Green is not implemented */
assign vga_psave_n = 1'b1;
assign vga_blank_n = 1'b1;
always @(posedge vga_clk) begin
vga_vsync_n <= fifo_do[17];
vga_hsync_n <= fifo_do[16];
vga_r <= {fifo_do[15:11], fifo_do[15:13]};
vga_g <= {fifo_do[10:5], fifo_do[10:9]};
vga_b <= {fifo_do[4:0], fifo_do[4:2]};
end
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 5
(* X_CORE_INFO = "axi_crossbar_v2_1_axi_crossbar,Vivado 2014.4.1" *)
(* CHECK_LICENSE_TYPE = "OpenSSD2_xbar_1,axi_crossbar_v2_1_axi_crossbar,{}" *)
(* CORE_GENERATION_INFO = "OpenSSD2_xbar_1,axi_crossbar_v2_1_axi_crossbar,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=2,C_NUM_MASTER_SLOTS=1,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_PROTOCOL=0,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x0000000000000000,C_M_AXI_ADDR_WIDTH=0x0000001e,C_S_AXI_BASE_ID=0x0000000100000000,C_S_AXI_THREAD_ID_WIDTH=0x0000000000000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x00000003,C_M_AXI_READ_CONNECTIVITY=0x00000003,C_R_REGISTER=0,C_S_AXI_SINGLE_THREAD=0x0000000000000000,C_S_AXI_WRITE_ACCEPTANCE=0x0000000400000004,C_S_AXI_READ_ACCEPTANCE=0x0000000400000004,C_M_AXI_WRITE_ISSUING=0x00000008,C_M_AXI_READ_ISSUING=0x00000008,C_S_AXI_ARB_PRIORITY=0x0000000000000000,C_M_AXI_SECURE=0x00000000,C_CONNECTIVITY_MODE=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module OpenSSD2_xbar_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [31:0] [63:32]" *)
input wire [63 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8]" *)
input wire [15 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3]" *)
input wire [5 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2]" *)
input wire [3 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4]" *)
input wire [7 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3]" *)
input wire [5 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4]" *)
input wire [7 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [63:0] [127:64]" *)
input wire [127 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [7:0] [15:8]" *)
input wire [15 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1]" *)
input wire [1 : 0] s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2]" *)
output wire [3 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1]" *)
input wire [1 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [31:0] [63:32]" *)
input wire [63 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8]" *)
input wire [15 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3]" *)
input wire [5 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2]" *)
input wire [3 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4]" *)
input wire [7 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3]" *)
input wire [5 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4]" *)
input wire [7 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [63:0] [127:64]" *)
output wire [127 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2]" *)
output wire [3 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1]" *)
input wire [1 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID" *)
output wire [0 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID" *)
output wire [0 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY" *)
input wire [0 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST" *)
output wire [0 : 0] m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID" *)
output wire [0 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY" *)
input wire [0 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID" *)
input wire [0 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID" *)
input wire [0 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY" *)
output wire [0 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID" *)
output wire [0 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID" *)
output wire [0 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY" *)
input wire [0 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID" *)
input wire [0 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST" *)
input wire [0 : 0] m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID" *)
input wire [0 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY" *)
output wire [0 : 0] m_axi_rready;
axi_crossbar_v2_1_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(2),
.C_NUM_MASTER_SLOTS(1),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_PROTOCOL(0),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(64'H0000000000000000),
.C_M_AXI_ADDR_WIDTH(32'H0000001e),
.C_S_AXI_BASE_ID(64'H0000000100000000),
.C_S_AXI_THREAD_ID_WIDTH(64'H0000000000000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(32'H00000003),
.C_M_AXI_READ_CONNECTIVITY(32'H00000003),
.C_R_REGISTER(0),
.C_S_AXI_SINGLE_THREAD(64'H0000000000000000),
.C_S_AXI_WRITE_ACCEPTANCE(64'H0000000400000004),
.C_S_AXI_READ_ACCEPTANCE(64'H0000000400000004),
.C_M_AXI_WRITE_ISSUING(32'H00000008),
.C_M_AXI_READ_ISSUING(32'H00000008),
.C_S_AXI_ARB_PRIORITY(64'H0000000000000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(2'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(2'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(2'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(2'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_intr_rd_mem.v
*
* Date : 2012-11
*
* Description : Mimics interconnect for Reads between AFI and DDRC/OCM
*
*****************************************************************************/
module processing_system7_bfm_v2_0_intr_rd_mem(
sw_clk,
rstn,
full,
empty,
req,
invalid_rd_req,
rd_info,
RD_DATA_OCM,
RD_DATA_DDR,
RD_DATA_VALID_OCM,
RD_DATA_VALID_DDR
);
`include "processing_system7_bfm_v2_0_local_params.v"
input sw_clk, rstn;
output full, empty;
input RD_DATA_VALID_DDR, RD_DATA_VALID_OCM;
input [max_burst_bits-1:0] RD_DATA_DDR, RD_DATA_OCM;
input req, invalid_rd_req;
input [rd_info_bits-1:0] rd_info;
reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0;
reg [rd_afi_fifo_bits-1:0] rd_fifo [0:intr_max_outstanding-1]; // Data, addr, size, burst, len, RID, RRESP, valid bytes
wire full, empty;
assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0;
assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0;
/* read from the fifo */
task read_mem;
output [rd_afi_fifo_bits-1:0] data;
begin
data = rd_fifo[rd_ptr[intr_cnt_width-1:0]];
if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1)
rd_ptr[intr_cnt_width-2:0] = 0;
else
rd_ptr = rd_ptr + 1;
end
endtask
reg state;
reg invalid_rd;
/* write in the fifo */
always@(negedge rstn or posedge sw_clk)
begin
if(!rstn) begin
wr_ptr <= 0;
rd_ptr <= 0;
state <= 0;
invalid_rd <= 0;
end else begin
case (state)
0 : begin
state <= 0;
invalid_rd <= 0;
if(req)begin
state <= 1;
invalid_rd <= invalid_rd_req;
end
end
1 : begin
state <= 1;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd) begin
if(RD_DATA_VALID_DDR)
rd_fifo[wr_ptr[intr_cnt_width-2:0]] <= {RD_DATA_DDR,rd_info};
else if(RD_DATA_VALID_OCM)
rd_fifo[wr_ptr[intr_cnt_width-2:0]] <= {RD_DATA_OCM,rd_info};
else
rd_fifo[wr_ptr[intr_cnt_width-2:0]] <= rd_info;
if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1)
wr_ptr[intr_cnt_width-2:0] <= 0;
else
wr_ptr <= wr_ptr + 1;
state <= 0;
invalid_rd <= 0;
end
end
endcase
end
end
endmodule
|
// -- (c) Copyright 2011-2014 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: axi_crossbar.v
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_axi_crossbar # (
parameter C_FAMILY = "rtl",
// FPGA Base Family. Current version: virtex6 or spartan6.
parameter integer C_NUM_SLAVE_SLOTS = 1,
// Number of Slave Interface (SI) slots for connecting
// to master IP. Range: 1-16.
parameter integer C_NUM_MASTER_SLOTS = 2,
// Number of Master Interface (MI) slots for connecting
// to slave IP. Range: 1-16.
parameter integer C_AXI_ID_WIDTH = 1,
// Width of ID signals propagated by the Interconnect.
// Width of ID signals produced on all MI slots.
// Range: 1-32.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and
// m_axi_araddr for all SI/MI slots.
// Range: 1-64.
parameter integer C_AXI_DATA_WIDTH = 32,
// Data width of the internal interconnect write and read
// data paths.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_AXI_PROTOCOL = 0,
// 0 = "AXI4",
// 1 = "AXI3",
// 2 = "AXI4LITE"
// Propagate WID only when C_AXI_PROTOCOL = 1.
parameter integer C_NUM_ADDR_RANGES = 1,
// Number of BASE/HIGH_ADDR pairs per MI slot.
// Range: 1-16.
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = 128'h00000000001000000000000000000000,
// Base address of each range of each MI slot.
// For unused ranges, set C_M_AXI_BASE_ADDR[mm*aa*64 +: C_AXI_ADDR_WIDTH] = {C_AXI_ADDR_WIDTH{1'b1}}.
// (Bit positions above C_AXI_ADDR_WIDTH are ignored.)
// Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit64}}.
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*32-1:0] C_M_AXI_ADDR_WIDTH = 64'H0000000c0000000c,
// Number of low-order address bits that are used to select locations within each address range of each MI slot.
// The High address of each range is derived as BASE_ADDR + 2**C_M_AXI_ADDR_WIDTH -1.
// For used address ranges, C_M_AXI_ADDR_WIDTH must be > 0.
// For unused ranges, set C_M_AXI_ADDR_WIDTH to 32'h00000000.
// Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit32}}.
// Range: 0 - C_AXI_ADDR_WIDTH.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_BASE_ID = 32'h00000000,
// Base ID of each SI slot.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0 to 2**C_AXI_ID_WIDTH-1.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = 32'h00000000,
// Number of low-order ID bits a connected master may vary to select a transaction thread.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0 - C_AXI_ID_WIDTH.
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
// 1 = Propagate all USER signals, 0 = Dont propagate.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of BUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF,
// Multi-pathway write connectivity from each SI slot (N) to each
// MI slot (M):
// 0 = no pathway required; 1 = pathway required. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF,
// Multi-pathway read connectivity from each SI slot (N) to each
// MI slot (M):
// 0 = no pathway required; 1 = pathway required. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
parameter integer C_R_REGISTER = 0,
// Insert register slice on R channel in the crossbar. (Valid only for SASD)
// Range: Reg-slice type (0-8).
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD = 32'h00000000,
// 0 = Implement separate command queues per ID thread.
// 1 = Force corresponding SI slot to be single-threaded. (Valid only for SAMD)
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0, 1
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE = 32'H00000002,
// Maximum number of active write transactions that each SI
// slot can accept. (Valid only for SAMD)
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE = 32'H00000002,
// Maximum number of active read transactions that each SI
// slot can accept. (Valid only for SAMD)
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING = 64'H0000000400000004,
// Maximum number of data-active write transactions that
// each MI slot can generate at any one time. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING = 64'H0000000400000004,
// Maximum number of active read transactions that
// each MI slot can generate at any one time. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY = 32'h00000000,
// Arbitration priority among each SI slot.
// Higher values indicate higher priority.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0-15.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE = 32'h00000000,
// Indicates whether each MI slot connects to a secure slave
// (allows only TrustZone secure access).
// Format: C_NUM_MASTER_SLOTS{Bit32}.
// Range: 0, 1
parameter integer C_CONNECTIVITY_MODE = 1
// 0 = Shared-Address Shared-Data (SASD).
// 1 = Shared-Address Multi-Data (SAMD).
// Default 1 (on) for simulation; default 0 (off) for implementation.
)
(
// Global Signals
input wire aclk,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_awsize,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_awburst,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awcache,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_awprot,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awregion,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awqos,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wlast,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_bresp,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bvalid,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_arsize,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_arburst,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arcache,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_arprot,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arregion,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arqos,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_rresp,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rlast,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rvalid,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rready,
// Master Interface Write Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_awsize,
output wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_awburst,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awcache,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_awprot,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awregion,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awqos,
output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awready,
// Master Interface Write Data Ports
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wlast,
output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wready,
// Master Interface Write Response Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_bresp,
input wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bvalid,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bready,
// Master Interface Read Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_arsize,
output wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_arburst,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arcache,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_arprot,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arregion,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arqos,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arready,
// Master Interface Read Data Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_rresp,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rlast,
input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rvalid,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rready
);
localparam [64:0] P_ONES = {65{1'b1}};
localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_BASE_ID = f_base_id(0);
localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_HIGH_ID = f_high_id(0);
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
localparam [2:0] P_AXILITE_SIZE = 3'b010;
localparam [1:0] P_INCR = 2'b01;
localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_WRITE = f_m_supports_write(0);
localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_READ = f_m_supports_read(0);
localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_WRITE = f_s_supports_write(0);
localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_READ = f_s_supports_read(0);
localparam integer C_DEBUG = 1;
localparam integer P_RANGE_CHECK = 1;
// 1 (non-zero) = Detect and issue DECERR on the following conditions:
// a. address range mismatch (no valid MI slot)
// b. Burst or >32-bit transfer to AxiLite slave
// c. TrustZone access violation
// d. R/W direction unsupported by target
// 0 = Pass all transactions (no DECERR):
// a. Omit DECERR detection and response logic
// b. Omit address decoder and propagate s_axi_a*REGION to m_axi_a*REGION
// when C_NUM_MASTER_SLOTS=1 and C_NUM_ADDR_RANGES=1.
// c. Unpredictable target MI-slot if address mismatch and >1 MI-slot
// d. Transaction corruption if any burst or >32-bit transfer to AxiLite slave
// Illegal combination: P_RANGE_CHECK = 0 && C_M_AXI_SECURE != 0.
localparam integer P_ADDR_DECODE = ((P_RANGE_CHECK == 1) || (C_NUM_MASTER_SLOTS > 1) || (C_NUM_ADDR_RANGES > 1)) ? 1 : 0; // Always 1
localparam [C_NUM_MASTER_SLOTS*32-1:0] P_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}};
// Transaction error detection (per MI-slot)
// 0 = None; 1 = AXI4Lite burst violation
// Format: C_NUM_MASTER_SLOTS{Bit32};
localparam integer P_LEN = (C_AXI_PROTOCOL == P_AXI3) ? 4 : 8;
localparam integer P_LOCK = (C_AXI_PROTOCOL == P_AXI3) ? 2 : 1;
localparam P_FAMILY = ((C_FAMILY == "virtex7") || (C_FAMILY == "kintex7") || (C_FAMILY == "artix7") || (C_FAMILY == "zynq")) ? C_FAMILY : "rtl";
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// Widths of all write issuance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_write_issue_width_vec
(input null_arg);
integer mi;
reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result;
begin
result = 0;
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_WRITE_ISSUING[mi*32+:32]);
end
result[C_NUM_MASTER_SLOTS*32+:32] = 32'h0;
f_write_issue_width_vec = result;
end
endfunction
// Widths of all read issuance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_read_issue_width_vec
(input null_arg);
integer mi;
reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result;
begin
result = 0;
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_READ_ISSUING[mi*32+:32]);
end
result[C_NUM_MASTER_SLOTS*32+:32] = 32'h0;
f_read_issue_width_vec = result;
end
endfunction
// Widths of all write acceptance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [C_NUM_SLAVE_SLOTS*32-1:0] f_write_accept_width_vec
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*32-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_WRITE_ACCEPTANCE[si*32+:32]);
end
f_write_accept_width_vec = result;
end
endfunction
// Widths of all read acceptance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [C_NUM_SLAVE_SLOTS*32-1:0] f_read_accept_width_vec
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*32-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_READ_ACCEPTANCE[si*32+:32]);
end
f_read_accept_width_vec = result;
end
endfunction
// Convert C_S_AXI_BASE_ID vector from Bit32 to Bit64 format
function [C_NUM_SLAVE_SLOTS*64-1:0] f_base_id
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*64-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*64+:C_AXI_ID_WIDTH] = C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH];
end
f_base_id = result;
end
endfunction
// Construct P_S_HIGH_ID vector
function [C_NUM_SLAVE_SLOTS*64-1:0] f_high_id
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*64-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*64+:C_AXI_ID_WIDTH] = (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] :
({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} :
(C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}));
end
f_high_id = result;
end
endfunction
// Construct P_M_HIGH_ADDR vector
function [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] f_high_addr
(input null_arg);
integer ar;
reg [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] result;
begin
result = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}};
for (ar=0; ar<C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES; ar=ar+1) begin
result[ar*64+:C_AXI_ADDR_WIDTH] = (C_M_AXI_ADDR_WIDTH[ar*32+:32] == 0) ? 64'h00000000_00000000 :
({1'b0, C_M_AXI_ADDR_WIDTH[ar*32+:31]} >= C_AXI_ADDR_WIDTH) ? {C_AXI_ADDR_WIDTH{1'b1}} :
(C_M_AXI_BASE_ADDR[ar*64+:C_AXI_ADDR_WIDTH] | ~(P_ONES << {1'b0, C_M_AXI_ADDR_WIDTH[ar*32+:7]}));
end
f_high_addr = result;
end
endfunction
// Generate a mask of valid ID bits for a given SI slot.
function [C_AXI_ID_WIDTH-1:0] f_thread_id_mask
(input integer si);
begin
f_thread_id_mask =
(C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? {C_AXI_ID_WIDTH{1'b0}} :
({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} :
({C_AXI_ID_WIDTH{1'b0}} | ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}));
end
endfunction
// Isolate thread bits of input S_ID and add to BASE_ID to form MI-side ID value
// only for end-point SI-slots
function [C_AXI_ID_WIDTH-1:0] f_extend_ID (
input [C_AXI_ID_WIDTH-1:0] s_id,
input integer si
);
begin
f_extend_ID =
(C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] :
({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? s_id :
(C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | (s_id & ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]})));
end
endfunction
// Bit vector of SI slots with at least one write connection.
function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_write
(input null_arg);
integer mi;
reg [C_NUM_SLAVE_SLOTS-1:0] result;
begin
result = {C_NUM_SLAVE_SLOTS{1'b0}};
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result = result | C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS];
end
f_s_supports_write = result;
end
endfunction
// Bit vector of SI slots with at least one read connection.
function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_read
(input null_arg);
integer mi;
reg [C_NUM_SLAVE_SLOTS-1:0] result;
begin
result = {C_NUM_SLAVE_SLOTS{1'b0}};
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result = result | C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS];
end
f_s_supports_read = result;
end
endfunction
// Bit vector of MI slots with at least one write connection.
function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_write
(input null_arg);
integer mi;
begin
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
f_m_supports_write[mi] = (|C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]);
end
end
endfunction
// Bit vector of MI slots with at least one read connection.
function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_read
(input null_arg);
integer mi;
begin
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
f_m_supports_read[mi] = (|C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]);
end
end
endfunction
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_awid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] si_cb_awaddr ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] si_cb_awlen ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_awsize ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_awburst ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_awlock ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awcache ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_awprot ;
// wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awregion ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awqos ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] si_cb_awuser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_wid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] si_cb_wdata ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] si_cb_wstrb ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wlast ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] si_cb_wuser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_bid ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_bresp ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] si_cb_buser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_arid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] si_cb_araddr ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] si_cb_arlen ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_arsize ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_arburst ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_arlock ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arcache ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_arprot ;
// wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arregion ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arqos ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] si_cb_aruser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_rid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] si_cb_rdata ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_rresp ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rlast ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] si_cb_ruser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_awid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] cb_mi_awaddr ;
wire [C_NUM_MASTER_SLOTS*8-1:0] cb_mi_awlen ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_awsize ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_awburst ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_awlock ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awcache ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_awprot ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awregion ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awqos ;
wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] cb_mi_awuser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_wid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] cb_mi_wdata ;
wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] cb_mi_wstrb ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wlast ;
wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] cb_mi_wuser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_bid ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_bresp ;
wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] cb_mi_buser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_arid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] cb_mi_araddr ;
wire [C_NUM_MASTER_SLOTS*8-1:0] cb_mi_arlen ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_arsize ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_arburst ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_arlock ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arcache ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_arprot ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arregion ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arqos ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] cb_mi_aruser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_rid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] cb_mi_rdata ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_rresp ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rlast ;
wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] cb_mi_ruser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rready ;
genvar slot;
generate
for (slot=0;slot<C_NUM_SLAVE_SLOTS;slot=slot+1) begin : gen_si_tieoff
assign si_cb_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign si_cb_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign si_cb_awlen[slot*8+:8] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awlen[slot*P_LEN+:P_LEN] : 0 ;
assign si_cb_awsize[slot*3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awsize[slot*3+:3] : P_AXILITE_SIZE ;
assign si_cb_awburst[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awburst[slot*2+:2] : P_INCR ;
assign si_cb_awlock[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1'b0, s_axi_awlock[slot*P_LOCK+:1]} : 0 ;
assign si_cb_awcache[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awcache[slot*4+:4] : 0 ;
assign si_cb_awprot[slot*3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awprot[slot*3+:3] : 0 ;
assign si_cb_awqos[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awqos[slot*4+:4] : 0 ;
// assign si_cb_awregion[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_awregion[slot*4+:4] : 0 ;
assign si_cb_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ;
assign si_cb_awvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awvalid[slot*1+:1] : 0 ;
assign si_cb_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI3) ) ? (s_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign si_cb_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign si_cb_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ;
assign si_cb_wlast[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_wlast[slot*1+:1] : 1'b1 ;
assign si_cb_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ;
assign si_cb_wvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wvalid[slot*1+:1] : 0 ;
assign si_cb_bready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_bready[slot*1+:1] : 0 ;
assign si_cb_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign si_cb_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign si_cb_arlen[slot*8+:8] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arlen[slot*P_LEN+:P_LEN] : 0 ;
assign si_cb_arsize[slot*3+:3] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arsize[slot*3+:3] : P_AXILITE_SIZE ;
assign si_cb_arburst[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arburst[slot*2+:2] : P_INCR ;
assign si_cb_arlock[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1'b0, s_axi_arlock[slot*P_LOCK+:1]} : 0 ;
assign si_cb_arcache[slot*4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arcache[slot*4+:4] : 0 ;
assign si_cb_arprot[slot*3+:3] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arprot[slot*3+:3] : 0 ;
assign si_cb_arqos[slot*4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arqos[slot*4+:4] : 0 ;
// assign si_cb_arregion[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_arregion[slot*4+:4] : 0 ;
assign si_cb_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ;
assign si_cb_arvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arvalid[slot*1+:1] : 0 ;
assign si_cb_rready[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_rready[slot*1+:1] : 0 ;
assign s_axi_awready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_awready[slot*1+:1] : 0 ;
assign s_axi_wready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_wready[slot*1+:1] : 0 ;
assign s_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign s_axi_bresp[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bresp[slot*2+:2] : 0 ;
assign s_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ;
assign s_axi_bvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bvalid[slot*1+:1] : 0 ;
assign s_axi_arready[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_arready[slot*1+:1] : 0 ;
assign s_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign s_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign s_axi_rresp[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rresp[slot*2+:2] : 0 ;
assign s_axi_rlast[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cb_rlast[slot*1+:1] : 0 ;
assign s_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ;
assign s_axi_rvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rvalid[slot*1+:1] : 0 ;
end // gen_si_tieoff
for (slot=0;slot<C_NUM_MASTER_SLOTS;slot=slot+1) begin : gen_mi_tieoff
assign m_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign m_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign m_axi_awlen[slot*P_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_WRITE[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_awlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_awlen[slot*8+:4] : 0 ;
assign m_axi_awsize[slot*3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awsize[slot*3+:3] : 0 ;
assign m_axi_awburst[slot*2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awburst[slot*2+:2] : 0 ;
assign m_axi_awlock[slot*P_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awlock[slot*2+:1] : 0 ;
assign m_axi_awcache[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awcache[slot*4+:4] : 0 ;
assign m_axi_awprot[slot*3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awprot[slot*3+:3] : 0 ;
assign m_axi_awregion[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_awregion[slot*4+:4] : 0 ;
assign m_axi_awqos[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awqos[slot*4+:4] : 0 ;
assign m_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ;
assign m_axi_awvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awvalid[slot*1+:1] : 0 ;
assign m_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign m_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign m_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ;
assign m_axi_wlast[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wlast[slot*1+:1] : 0 ;
assign m_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ;
assign m_axi_wvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wvalid[slot*1+:1] : 0 ;
assign m_axi_bready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_bready[slot*1+:1] : 0 ;
assign m_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign m_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign m_axi_arlen[slot*P_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_READ[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_arlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_arlen[slot*8+:4] : 0 ;
assign m_axi_arsize[slot*3+:3] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arsize[slot*3+:3] : 0 ;
assign m_axi_arburst[slot*2+:2] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arburst[slot*2+:2] : 0 ;
assign m_axi_arlock[slot*P_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arlock[slot*2+:1] : 0 ;
assign m_axi_arcache[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arcache[slot*4+:4] : 0 ;
assign m_axi_arprot[slot*3+:3] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arprot[slot*3+:3] : 0 ;
assign m_axi_arregion[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_arregion[slot*4+:4] : 0 ;
assign m_axi_arqos[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arqos[slot*4+:4] : 0 ;
assign m_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ;
assign m_axi_arvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arvalid[slot*1+:1] : 0 ;
assign m_axi_rready[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_rready[slot*1+:1] : 0 ;
assign cb_mi_awready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_awready[slot*1+:1] : 0 ;
assign cb_mi_wready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_wready[slot*1+:1] : 0 ;
assign cb_mi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign cb_mi_bresp[slot*2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bresp[slot*2+:2] : 0 ;
assign cb_mi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ;
assign cb_mi_bvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bvalid[slot*1+:1] : 0 ;
assign cb_mi_arready[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_arready[slot*1+:1] : 0 ;
assign cb_mi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign cb_mi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign cb_mi_rresp[slot*2+:2] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rresp[slot*2+:2] : 0 ;
assign cb_mi_rlast[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rlast[slot*1+:1] : 1'b1 ;
assign cb_mi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ;
assign cb_mi_rvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rvalid[slot*1+:1] : 0 ;
end // gen_mi_tieoff
if ((C_CONNECTIVITY_MODE==0) || (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_sasd
axi_crossbar_v2_1_crossbar_sasd #
(
.C_FAMILY (P_FAMILY),
.C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS),
.C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS),
.C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_M_AXI_HIGH_ADDR (f_high_addr(0)),
.C_S_AXI_BASE_ID (P_S_AXI_BASE_ID),
.C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE),
.C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ),
.C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE),
.C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ),
.C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY),
.C_M_AXI_SECURE (C_M_AXI_SECURE),
.C_R_REGISTER (C_R_REGISTER),
.C_RANGE_CHECK (P_RANGE_CHECK),
.C_ADDR_DECODE (P_ADDR_DECODE),
.C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE),
.C_DEBUG (C_DEBUG)
)
crossbar_sasd_0
(
.ACLK (aclk),
.ARESETN (aresetn),
.S_AXI_AWID (si_cb_awid ),
.S_AXI_AWADDR (si_cb_awaddr ),
.S_AXI_AWLEN (si_cb_awlen ),
.S_AXI_AWSIZE (si_cb_awsize ),
.S_AXI_AWBURST (si_cb_awburst ),
.S_AXI_AWLOCK (si_cb_awlock ),
.S_AXI_AWCACHE (si_cb_awcache ),
.S_AXI_AWPROT (si_cb_awprot ),
// .S_AXI_AWREGION (si_cb_awregion ),
.S_AXI_AWQOS (si_cb_awqos ),
.S_AXI_AWUSER (si_cb_awuser ),
.S_AXI_AWVALID (si_cb_awvalid ),
.S_AXI_AWREADY (si_cb_awready ),
.S_AXI_WID (si_cb_wid ),
.S_AXI_WDATA (si_cb_wdata ),
.S_AXI_WSTRB (si_cb_wstrb ),
.S_AXI_WLAST (si_cb_wlast ),
.S_AXI_WUSER (si_cb_wuser ),
.S_AXI_WVALID (si_cb_wvalid ),
.S_AXI_WREADY (si_cb_wready ),
.S_AXI_BID (si_cb_bid ),
.S_AXI_BRESP (si_cb_bresp ),
.S_AXI_BUSER (si_cb_buser ),
.S_AXI_BVALID (si_cb_bvalid ),
.S_AXI_BREADY (si_cb_bready ),
.S_AXI_ARID (si_cb_arid ),
.S_AXI_ARADDR (si_cb_araddr ),
.S_AXI_ARLEN (si_cb_arlen ),
.S_AXI_ARSIZE (si_cb_arsize ),
.S_AXI_ARBURST (si_cb_arburst ),
.S_AXI_ARLOCK (si_cb_arlock ),
.S_AXI_ARCACHE (si_cb_arcache ),
.S_AXI_ARPROT (si_cb_arprot ),
// .S_AXI_ARREGION (si_cb_arregion ),
.S_AXI_ARQOS (si_cb_arqos ),
.S_AXI_ARUSER (si_cb_aruser ),
.S_AXI_ARVALID (si_cb_arvalid ),
.S_AXI_ARREADY (si_cb_arready ),
.S_AXI_RID (si_cb_rid ),
.S_AXI_RDATA (si_cb_rdata ),
.S_AXI_RRESP (si_cb_rresp ),
.S_AXI_RLAST (si_cb_rlast ),
.S_AXI_RUSER (si_cb_ruser ),
.S_AXI_RVALID (si_cb_rvalid ),
.S_AXI_RREADY (si_cb_rready ),
.M_AXI_AWID (cb_mi_awid ),
.M_AXI_AWADDR (cb_mi_awaddr ),
.M_AXI_AWLEN (cb_mi_awlen ),
.M_AXI_AWSIZE (cb_mi_awsize ),
.M_AXI_AWBURST (cb_mi_awburst ),
.M_AXI_AWLOCK (cb_mi_awlock ),
.M_AXI_AWCACHE (cb_mi_awcache ),
.M_AXI_AWPROT (cb_mi_awprot ),
.M_AXI_AWREGION (cb_mi_awregion ),
.M_AXI_AWQOS (cb_mi_awqos ),
.M_AXI_AWUSER (cb_mi_awuser ),
.M_AXI_AWVALID (cb_mi_awvalid ),
.M_AXI_AWREADY (cb_mi_awready ),
.M_AXI_WID (cb_mi_wid ),
.M_AXI_WDATA (cb_mi_wdata ),
.M_AXI_WSTRB (cb_mi_wstrb ),
.M_AXI_WLAST (cb_mi_wlast ),
.M_AXI_WUSER (cb_mi_wuser ),
.M_AXI_WVALID (cb_mi_wvalid ),
.M_AXI_WREADY (cb_mi_wready ),
.M_AXI_BID (cb_mi_bid ),
.M_AXI_BRESP (cb_mi_bresp ),
.M_AXI_BUSER (cb_mi_buser ),
.M_AXI_BVALID (cb_mi_bvalid ),
.M_AXI_BREADY (cb_mi_bready ),
.M_AXI_ARID (cb_mi_arid ),
.M_AXI_ARADDR (cb_mi_araddr ),
.M_AXI_ARLEN (cb_mi_arlen ),
.M_AXI_ARSIZE (cb_mi_arsize ),
.M_AXI_ARBURST (cb_mi_arburst ),
.M_AXI_ARLOCK (cb_mi_arlock ),
.M_AXI_ARCACHE (cb_mi_arcache ),
.M_AXI_ARPROT (cb_mi_arprot ),
.M_AXI_ARREGION (cb_mi_arregion ),
.M_AXI_ARQOS (cb_mi_arqos ),
.M_AXI_ARUSER (cb_mi_aruser ),
.M_AXI_ARVALID (cb_mi_arvalid ),
.M_AXI_ARREADY (cb_mi_arready ),
.M_AXI_RID (cb_mi_rid ),
.M_AXI_RDATA (cb_mi_rdata ),
.M_AXI_RRESP (cb_mi_rresp ),
.M_AXI_RLAST (cb_mi_rlast ),
.M_AXI_RUSER (cb_mi_ruser ),
.M_AXI_RVALID (cb_mi_rvalid ),
.M_AXI_RREADY (cb_mi_rready )
);
end else begin : gen_samd
axi_crossbar_v2_1_crossbar #
(
.C_FAMILY (P_FAMILY),
.C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS),
.C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS),
.C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_S_AXI_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_M_AXI_HIGH_ADDR (f_high_addr(0)),
.C_S_AXI_BASE_ID (P_S_AXI_BASE_ID),
.C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE),
.C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ),
.C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE),
.C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ),
.C_M_AXI_WRITE_CONNECTIVITY (C_M_AXI_WRITE_CONNECTIVITY),
.C_M_AXI_READ_CONNECTIVITY (C_M_AXI_READ_CONNECTIVITY),
.C_S_AXI_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD),
.C_S_AXI_WRITE_ACCEPTANCE (C_S_AXI_WRITE_ACCEPTANCE),
.C_S_AXI_READ_ACCEPTANCE (C_S_AXI_READ_ACCEPTANCE),
.C_M_AXI_WRITE_ISSUING (C_M_AXI_WRITE_ISSUING),
.C_M_AXI_READ_ISSUING (C_M_AXI_READ_ISSUING),
.C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY),
.C_M_AXI_SECURE (C_M_AXI_SECURE),
.C_RANGE_CHECK (P_RANGE_CHECK),
.C_ADDR_DECODE (P_ADDR_DECODE),
.C_W_ISSUE_WIDTH (f_write_issue_width_vec(0) ),
.C_R_ISSUE_WIDTH (f_read_issue_width_vec(0) ),
.C_W_ACCEPT_WIDTH (f_write_accept_width_vec(0)),
.C_R_ACCEPT_WIDTH (f_read_accept_width_vec(0)),
.C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE),
.C_DEBUG (C_DEBUG)
)
crossbar_samd
(
.ACLK (aclk),
.ARESETN (aresetn),
.S_AXI_AWID (si_cb_awid ),
.S_AXI_AWADDR (si_cb_awaddr ),
.S_AXI_AWLEN (si_cb_awlen ),
.S_AXI_AWSIZE (si_cb_awsize ),
.S_AXI_AWBURST (si_cb_awburst ),
.S_AXI_AWLOCK (si_cb_awlock ),
.S_AXI_AWCACHE (si_cb_awcache ),
.S_AXI_AWPROT (si_cb_awprot ),
// .S_AXI_AWREGION (si_cb_awregion ),
.S_AXI_AWQOS (si_cb_awqos ),
.S_AXI_AWUSER (si_cb_awuser ),
.S_AXI_AWVALID (si_cb_awvalid ),
.S_AXI_AWREADY (si_cb_awready ),
.S_AXI_WID (si_cb_wid ),
.S_AXI_WDATA (si_cb_wdata ),
.S_AXI_WSTRB (si_cb_wstrb ),
.S_AXI_WLAST (si_cb_wlast ),
.S_AXI_WUSER (si_cb_wuser ),
.S_AXI_WVALID (si_cb_wvalid ),
.S_AXI_WREADY (si_cb_wready ),
.S_AXI_BID (si_cb_bid ),
.S_AXI_BRESP (si_cb_bresp ),
.S_AXI_BUSER (si_cb_buser ),
.S_AXI_BVALID (si_cb_bvalid ),
.S_AXI_BREADY (si_cb_bready ),
.S_AXI_ARID (si_cb_arid ),
.S_AXI_ARADDR (si_cb_araddr ),
.S_AXI_ARLEN (si_cb_arlen ),
.S_AXI_ARSIZE (si_cb_arsize ),
.S_AXI_ARBURST (si_cb_arburst ),
.S_AXI_ARLOCK (si_cb_arlock ),
.S_AXI_ARCACHE (si_cb_arcache ),
.S_AXI_ARPROT (si_cb_arprot ),
// .S_AXI_ARREGION (si_cb_arregion ),
.S_AXI_ARQOS (si_cb_arqos ),
.S_AXI_ARUSER (si_cb_aruser ),
.S_AXI_ARVALID (si_cb_arvalid ),
.S_AXI_ARREADY (si_cb_arready ),
.S_AXI_RID (si_cb_rid ),
.S_AXI_RDATA (si_cb_rdata ),
.S_AXI_RRESP (si_cb_rresp ),
.S_AXI_RLAST (si_cb_rlast ),
.S_AXI_RUSER (si_cb_ruser ),
.S_AXI_RVALID (si_cb_rvalid ),
.S_AXI_RREADY (si_cb_rready ),
.M_AXI_AWID (cb_mi_awid ),
.M_AXI_AWADDR (cb_mi_awaddr ),
.M_AXI_AWLEN (cb_mi_awlen ),
.M_AXI_AWSIZE (cb_mi_awsize ),
.M_AXI_AWBURST (cb_mi_awburst ),
.M_AXI_AWLOCK (cb_mi_awlock ),
.M_AXI_AWCACHE (cb_mi_awcache ),
.M_AXI_AWPROT (cb_mi_awprot ),
.M_AXI_AWREGION (cb_mi_awregion ),
.M_AXI_AWQOS (cb_mi_awqos ),
.M_AXI_AWUSER (cb_mi_awuser ),
.M_AXI_AWVALID (cb_mi_awvalid ),
.M_AXI_AWREADY (cb_mi_awready ),
.M_AXI_WID (cb_mi_wid ),
.M_AXI_WDATA (cb_mi_wdata ),
.M_AXI_WSTRB (cb_mi_wstrb ),
.M_AXI_WLAST (cb_mi_wlast ),
.M_AXI_WUSER (cb_mi_wuser ),
.M_AXI_WVALID (cb_mi_wvalid ),
.M_AXI_WREADY (cb_mi_wready ),
.M_AXI_BID (cb_mi_bid ),
.M_AXI_BRESP (cb_mi_bresp ),
.M_AXI_BUSER (cb_mi_buser ),
.M_AXI_BVALID (cb_mi_bvalid ),
.M_AXI_BREADY (cb_mi_bready ),
.M_AXI_ARID (cb_mi_arid ),
.M_AXI_ARADDR (cb_mi_araddr ),
.M_AXI_ARLEN (cb_mi_arlen ),
.M_AXI_ARSIZE (cb_mi_arsize ),
.M_AXI_ARBURST (cb_mi_arburst ),
.M_AXI_ARLOCK (cb_mi_arlock ),
.M_AXI_ARCACHE (cb_mi_arcache ),
.M_AXI_ARPROT (cb_mi_arprot ),
.M_AXI_ARREGION (cb_mi_arregion ),
.M_AXI_ARQOS (cb_mi_arqos ),
.M_AXI_ARUSER (cb_mi_aruser ),
.M_AXI_ARVALID (cb_mi_arvalid ),
.M_AXI_ARREADY (cb_mi_arready ),
.M_AXI_RID (cb_mi_rid ),
.M_AXI_RDATA (cb_mi_rdata ),
.M_AXI_RRESP (cb_mi_rresp ),
.M_AXI_RLAST (cb_mi_rlast ),
.M_AXI_RUSER (cb_mi_ruser ),
.M_AXI_RVALID (cb_mi_rvalid ),
.M_AXI_RREADY (cb_mi_rready )
);
end // gen_samd
// end // gen_crossbar
endgenerate
endmodule
`default_nettype wire
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate unary or ^~(value)
//
module main;
reg [3:0] vect;
reg error;
wire result;
assign result = ^~(vect);
initial
begin
error = 0;
for(vect=4'b0001;vect<4'b0000;vect = vect << 1)
begin
#1;
if(result !== 1'b0)
begin
$display("FAILED - Unary xnor ^~(%b)=%b",vect,result);
error = 1'b1;
end
end
#1;
for(vect=4'b0011;vect<4'b0000;vect = vect << 1)
begin
#1;
if(result !== 1'b0)
begin
$display("FAILED - Unary xnor ^~(%b)=%b",vect,result);
error = 1'b1;
end
end
#1;
vect = 4'b0000;
#1;
if(result !== 1'b1)
begin
$display("FAILED - Unary xnor ^~(%b)=%b",vect,result);
error = 1'b1;
end
if(error === 0 )
$display("PASSED");
end
endmodule // main
|
//////////////////////////////////////////////////////////////////////////////
//
// Xilinx, Inc. 2008 www.xilinx.com
//
//////////////////////////////////////////////////////////////////////////////
//
// File name : serdes_n_to_1.v
//
// Description : 1-bit generic n:1 transmitter module
// Takes in n bits of data and serialises this to 1 bit
// data is transmitted LSB first
// 0, 1, 2 ......
//
// Date - revision : August 1st 2008 - v 1.0
//
// Author : NJS
//
// Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
// provided to you "as is". Xilinx and its licensors make and you
// receive no warranties or conditions, express, implied,
// statutory or otherwise, and Xilinx specifically disclaims any
// implied warranties of merchantability, non-infringement,or
// fitness for a particular purpose. Xilinx does not warrant that
// the functions contained in these designs will meet your
// requirements, or that the operation of these designs will be
// uninterrupted or error free, or that defects in the Designs
// will be corrected. Furthermore, Xilinx does not warrantor
// make any representations regarding use or the results of the
// use of the designs in terms of correctness, accuracy,
// reliability, or otherwise.
//
// LIMITATION OF LIABILITY. In no event will Xilinx or its
// licensors be liable for any loss of data, lost profits,cost
// or procurement of substitute goods or services, or for any
// special, incidental, consequential, or indirect damages
// arising from the use or operation of the designs or
// accompanying documentation, however caused and on any theory
// of liability. This limitation will apply even if Xilinx
// has been advised of the possibility of such damage. This
// limitation shall apply not-withstanding the failure of the
// essential purpose of any limited remedies herein.
//
// Copyright © 2008 Xilinx, Inc.
// All rights reserved
//
//////////////////////////////////////////////////////////////////////////////
//
`timescale 1ps/1ps
module serdes_n_to_1 (ioclk, serdesstrobe, reset, gclk, datain, iob_data_out) ;
parameter integer SF = 8 ; // Parameter to set the serdes factor 1..8
input ioclk ; // IO Clock network
input serdesstrobe ; // Parallel data capture strobe
input reset ; // Reset
input gclk ; // Global clock
input [SF-1 : 0] datain ; // Data for output
output iob_data_out ; // output data
wire cascade_di ; //
wire cascade_do ; //
wire cascade_ti ; //
wire cascade_to ; //
wire [8:0] mdatain ; //
genvar i ; // Pad out the input data bus with 0's to 8 bits to avoid errors
generate
for (i = 0 ; i <= (SF - 1) ; i = i + 1)
begin : loop0
assign mdatain[i] = datain[i] ;
end
endgenerate
generate
for (i = (SF) ; i <= 8 ; i = i + 1)
begin : loop1
assign mdatain[i] = 1'b0 ;
end
endgenerate
OSERDES2 #(
.DATA_WIDTH (SF), // SERDES word width. This should match the setting is BUFPLL
.DATA_RATE_OQ ("SDR"), // <SDR>, DDR
.DATA_RATE_OT ("SDR"), // <SDR>, DDR
.SERDES_MODE ("MASTER"), // <DEFAULT>, MASTER, SLAVE
.OUTPUT_MODE ("DIFFERENTIAL"))
oserdes_m (
.OQ (iob_data_out),
.OCE (1'b1),
.CLK0 (ioclk),
.CLK1 (1'b0),
.IOCE (serdesstrobe),
.RST (reset),
.CLKDIV (gclk),
.D4 (mdatain[7]),
.D3 (mdatain[6]),
.D2 (mdatain[5]),
.D1 (mdatain[4]),
.TQ (),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TRAIN (1'b0),
.TCE (1'b1),
.SHIFTIN1 (1'b1), // Dummy input in Master
.SHIFTIN2 (1'b1), // Dummy input in Master
.SHIFTIN3 (cascade_do), // Cascade output D data from slave
.SHIFTIN4 (cascade_to), // Cascade output T data from slave
.SHIFTOUT1 (cascade_di), // Cascade input D data to slave
.SHIFTOUT2 (cascade_ti), // Cascade input T data to slave
.SHIFTOUT3 (), // Dummy output in Master
.SHIFTOUT4 ()) ; // Dummy output in Master
OSERDES2 #(
.DATA_WIDTH (SF), // SERDES word width. This should match the setting is BUFPLL
.DATA_RATE_OQ ("SDR"), // <SDR>, DDR
.DATA_RATE_OT ("SDR"), // <SDR>, DDR
.SERDES_MODE ("SLAVE"), // <DEFAULT>, MASTER, SLAVE
.OUTPUT_MODE ("DIFFERENTIAL"))
oserdes_s (
.OQ (),
.OCE (1'b1),
.CLK0 (ioclk),
.CLK1 (1'b0),
.IOCE (serdesstrobe),
.RST (reset),
.CLKDIV (gclk),
.D4 (mdatain[3]),
.D3 (mdatain[2]),
.D2 (mdatain[1]),
.D1 (mdatain[0]),
.TQ (),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TRAIN (1'b0),
.TCE (1'b1),
.SHIFTIN1 (cascade_di), // Cascade input D from Master
.SHIFTIN2 (cascade_ti), // Cascade input T from Master
.SHIFTIN3 (1'b1), // Dummy input in Slave
.SHIFTIN4 (1'b1), // Dummy input in Slave
.SHIFTOUT1 (), // Dummy output in Slave
.SHIFTOUT2 (), // Dummy output in Slave
.SHIFTOUT3 (cascade_do), // Cascade output D data to Master
.SHIFTOUT4 (cascade_to)) ; // Cascade output T data to Master
endmodule
|
/* Generated by Yosys 0.3.0+ (git sha1 3b52121) */
(* src = "../../verilog/bytemuxquad.v:1" *)
module ByteMuxQuad(A_i, B_i, C_i, D_i, SAB_i, SC_i, SD_i, Y_o);
(* src = "../../verilog/bytemuxquad.v:20" *)
wire [7:0] AB;
(* src = "../../verilog/bytemuxquad.v:21" *)
wire [7:0] ABC;
(* intersynth_conntype = "Byte" *)
(* src = "../../verilog/bytemuxquad.v:3" *)
input [7:0] A_i;
(* intersynth_conntype = "Byte" *)
(* src = "../../verilog/bytemuxquad.v:5" *)
input [7:0] B_i;
(* intersynth_conntype = "Byte" *)
(* src = "../../verilog/bytemuxquad.v:7" *)
input [7:0] C_i;
(* intersynth_conntype = "Byte" *)
(* src = "../../verilog/bytemuxquad.v:9" *)
input [7:0] D_i;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/bytemuxquad.v:11" *)
input SAB_i;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/bytemuxquad.v:13" *)
input SC_i;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/bytemuxquad.v:15" *)
input SD_i;
(* intersynth_conntype = "Byte" *)
(* src = "../../verilog/bytemuxquad.v:17" *)
output [7:0] Y_o;
(* src = "../../verilog/bytemuxquad.v:20" *)
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$ternary$../../verilog/bytemuxquad.v:20$1 (
.A(A_i),
.B(B_i),
.S(SAB_i),
.Y(AB)
);
(* src = "../../verilog/bytemuxquad.v:21" *)
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$ternary$../../verilog/bytemuxquad.v:21$2 (
.A(AB),
.B(C_i),
.S(SC_i),
.Y(ABC)
);
(* src = "../../verilog/bytemuxquad.v:22" *)
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$ternary$../../verilog/bytemuxquad.v:22$3 (
.A(ABC),
.B(D_i),
.S(SD_i),
.Y(Y_o)
);
endmodule
|
module de0_cv
(
input CLOCK2_50,
input CLOCK3_50,
inout CLOCK4_50,
input CLOCK_50,
input RESET_N,
input [ 3:0] KEY,
input [ 9:0] SW,
output [ 9:0] LEDR,
output [ 6:0] HEX0,
output [ 6:0] HEX1,
output [ 6:0] HEX2,
output [ 6:0] HEX3,
output [ 6:0] HEX4,
output [ 6:0] HEX5,
output [12:0] DRAM_ADDR,
output [ 1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
output [ 3:0] VGA_B,
output [ 3:0] VGA_G,
output VGA_HS,
output [ 3:0] VGA_R,
output VGA_VS,
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
output SD_CLK,
inout SD_CMD,
inout [ 3:0] SD_DATA,
inout [35:0] GPIO_0,
inout [35:0] GPIO_1
);
// wires & inputs
wire clk;
wire clkIn = CLOCK_50;
wire rst_n = KEY[0] & RESET_N;
wire clkEnable = SW [9] | ~KEY[1];
wire [ 3:0 ] clkDevide = SW [8:5];
wire [ 4:0 ] regAddr = SW [4:0];
wire [ 31:0 ] regData;
//cores
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( clkDevide ),
.clkEnable ( clkEnable ),
.clk ( clk ),
.regAddr ( regAddr ),
.regData ( regData )
);
//outputs
assign LEDR[0] = clk;
assign LEDR[9:1] = regData[8:0];
wire [ 31:0 ] h7segment = regData;
sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );
sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );
sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );
sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );
sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//===----------------------------------------------------------------------===//
//
// C backend 'pop' primitive
//
//===----------------------------------------------------------------------===//
module acl_pop (
clock,
resetn,
// input stream from kernel pipeline
dir,
valid_in,
data_in,
stall_out,
predicate,
// downstream, to kernel pipeline
valid_out,
stall_in,
data_out,
// feedback downstream, from feedback acl_push
feedback_in,
feedback_valid_in,
feedback_stall_out
);
parameter DATA_WIDTH = 32;
parameter string STYLE = "REGULAR"; // REGULAR vs COALESCE
// this will pop garbage off of the feedback
localparam POP_GARBAGE = STYLE == "COALESCE" ? 1 : 0;
input clock, resetn, stall_in, valid_in, feedback_valid_in;
output stall_out, valid_out, feedback_stall_out;
input [DATA_WIDTH-1:0] data_in;
input dir;
input predicate;
output [DATA_WIDTH-1:0] data_out;
input [DATA_WIDTH-1:0] feedback_in;
wire feedback_downstream, data_downstream;
reg pop_garbage;
reg last_dir;
always @(posedge clock or negedge resetn)
begin
if ( !resetn ) begin
pop_garbage = 0;
end
else if ( valid_in && ~dir && last_dir ) begin
pop_garbage = POP_GARBAGE;
end
end
always @(posedge clock or negedge resetn)
begin
if ( !resetn ) begin
last_dir = 0;
end
else if ( valid_in ) begin
last_dir = dir;
end
end
assign feedback_downstream = valid_in & ~dir & feedback_valid_in;
assign data_downstream = valid_in & dir;
assign valid_out = feedback_downstream | ( data_downstream & (~pop_garbage | feedback_valid_in ) ) ;
assign data_out = ~dir ? feedback_in : data_in;
//assign stall_out = stall_in;
//assign stall_out = valid_in & ~((feedback_downstream | data_downstream) & ~stall_in);
// assign stall_out = ~((feedback_downstream | data_downstream) & ~stall_in);
// stall upstream if
// downstream is stalling (stall_in)
// I'm waiting for data from feedback (valid_in&~dir&~feedback_valiid_in)
assign stall_out = ( valid_in & ( ( ~dir & ~feedback_valid_in ) | ( dir & ~feedback_valid_in & pop_garbage ) ) ) | stall_in;
// don't accept data if:
// downstream cannot accept data (stall_in)
// data from upstream is selected (data_downstream)
// no thread exists to read data (~valid_in)
// predicate is high
assign feedback_stall_out = stall_in | (data_downstream & ~pop_garbage) | ~valid_in | predicate;
endmodule
|
module MUX8_1(Sel,S0,S1,S2,S3,S4,S5,S6,S7,out);
input [2:0] Sel;
input [7:0] S0,S1,S2,S3,S4,S5,S6,S7;
output [7:0]out;
assign out = (Sel[2])? (Sel[1]?(Sel[0]?S7:S6) : (Sel[0]?S5:S4)) : (Sel[1]?(Sel[0]?S3:S2) : (Sel[0]?S1:S0));
endmodule
module MUX4_1(Sel,S0,S1,S2,S3,out);
input [1:0] Sel;
input [7:0] S0,S1,S2,S3;
output [7:0]out;
assign out = (Sel[1]?(Sel[0]?S3:S2) : (Sel[0]?S1:S0));
endmodule
module Memory_ShiftOutput(
input [31:0] Mem_data_out,
input [1:0] Mem_addr_in,
input [31:26] IR,
output [31:0] Mem_data_shift
);
wire [2:0] MEM_data_shift_ctr;
wire [31:0]Mem_d_l,Mem_d_r;
assign MEM_data_shift_ctr[2] = (IR[31])&(!IR[30])&(!IR[29])&(((!IR[28])&(IR[27])) | ((IR[27])&(!IR[26])) );
assign MEM_data_shift_ctr[1] = (IR[31])&(!IR[30])&(!IR[29])&(((!IR[27])&(IR[26])) | ((IR[28])&(IR[27])&(!IR[26])));
assign MEM_data_shift_ctr[0] = (IR[31])&(!IR[30])&(!IR[29])&(((IR[28])&(!IR[27])) | ((!IR[28])&(IR[27])&(!IR[26])));
MUX4_1 mux4_1_10(Mem_addr_in[1:0],Mem_data_out[31:24],Mem_data_out[23:16],Mem_data_out[15:8],Mem_data_out[7:0],Mem_d_l[31:24]);
MUX4_1 mux4_1_11(Mem_addr_in[1:0],Mem_data_out[23:16],Mem_data_out[15:8],Mem_data_out[7:0],8'b0,Mem_d_l[23:16]);
MUX4_1 mux4_1_12(Mem_addr_in[1:0],Mem_data_out[15:8],Mem_data_out[7:0],8'b0,8'b0,Mem_d_l[15:8]);
MUX4_1 mux4_1_13(Mem_addr_in[1:0],Mem_data_out[7:0],8'b0,8'b0,8'b0,Mem_d_l[7:0]);
MUX4_1 mux4_1_14(Mem_addr_in[1:0],8'b0,8'b0,8'b0,Mem_data_out[31:24],Mem_d_r[31:24]);
MUX4_1 mux4_1_15(Mem_addr_in[1:0],8'b0,8'b0,Mem_data_out[31:24],Mem_data_out[23:16],Mem_d_r[23:16]);
MUX4_1 mux4_1_16(Mem_addr_in[1:0],8'b0,Mem_data_out[31:24],Mem_data_out[23:16],Mem_data_out[15:8],Mem_d_r[15:8]);
MUX4_1 mux4_1_17(Mem_addr_in[1:0],Mem_data_out[31:24],Mem_data_out[23:16],Mem_data_out[15:8],Mem_data_out[7:0],Mem_d_r[7:0]);
MUX8_1 mux8_1_10(MEM_data_shift_ctr[2:0],{8{Mem_d_l[31]}},8'b0,{8{Mem_d_l[31]}},8'b0,Mem_d_l[31:24],Mem_d_l[31:24],Mem_d_r[31:24],8'b0,Mem_data_shift[31:24]);
MUX8_1 mux8_1_11(MEM_data_shift_ctr[2:0],{8{Mem_d_l[31]}},8'b0,{8{Mem_d_l[31]}},8'b0,Mem_d_l[23:16],Mem_d_l[23:16],Mem_d_r[23:16],8'b0,Mem_data_shift[23:16]);
MUX8_1 mux8_1_12(MEM_data_shift_ctr[2:0],{8{Mem_d_l[31]}},8'b0,Mem_d_l[31:24],Mem_d_l[31:24],Mem_d_l[15:8],Mem_d_l[15:8],Mem_d_r[15:8],8'b0,Mem_data_shift[15:8]);
MUX8_1 mux8_1_13(MEM_data_shift_ctr[2:0],Mem_d_l[31:24],Mem_d_l[31:24],Mem_d_l[23:16],Mem_d_l[23:16],Mem_d_l[7:0],Mem_d_l[7:0],Mem_d_r[7:0],8'b0,Mem_data_shift[7:0]);
endmodule |
module ex;
/* autoinst_paramover_sub AUTO_TEMPLATE "u_\(.*\)" (
.a(inA_@[]),
.b(outA_@[]),
);*/
autoinst_paramover_sub u_foo(/*AUTOINST*/
// Inouts
.a (inA_foo[bitsa:0]), // Templated
.b (outA_foo[bitsb:0])); // Templated
autoinst_paramover_sub u_bar(/*AUTOINST*/
// Inouts
.a (inA_bar[bitsa:0]), // Templated
.b (outA_bar[bitsb:0])); // Templated
autoinst_paramover_sub u_baz(/*AUTOINST*/
// Inouts
.a (inA_baz[bitsa:0]), // Templated
.b (outA_baz[bitsb:0])); // Templated
/* autoinst_paramover_sub AUTO_TEMPLATE (
.a(inN_@[]),
.b(outN_@[]),
);*/
autoinst_paramover_sub u_0_2(/*AUTOINST*/
// Inouts
.a (inN_0[bitsa:0]), // Templated
.b (outN_0[bitsb:0])); // Templated
autoinst_paramover_sub u_1_3(/*AUTOINST*/
// Inouts
.a (inN_1[bitsa:0]), // Templated
.b (outN_1[bitsb:0])); // Templated
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_pipe_drp.v
// Version : 3.2
//------------------------------------------------------------------------------
// Filename : pipe_drp.v
// Description : PIPE DRP Module for 7 Series Transceiver
// Version : 20.0
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE DRP Module ---------------------------------------------------
module PCIeGen2x8If128_pipe_drp #
(
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_AUX_CDR_GEN3_EN = "TRUE", // PCIe AUX CDR Gen3 enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
parameter LOAD_CNT_MAX = 2'd1, // Load max count
parameter INDEX_MAX = 5'd21 // Index max count
)
(
//---------- Input -------------------------------------
input DRP_CLK,
input DRP_RST_N,
input DRP_GTXRESET,
input [ 1:0] DRP_RATE,
input DRP_X16X20_MODE,
input DRP_X16,
input DRP_START,
input [15:0] DRP_DO,
input DRP_RDY,
//---------- Output ------------------------------------
output [ 8:0] DRP_ADDR,
output DRP_EN,
output [15:0] DRP_DI,
output DRP_WE,
output DRP_DONE,
output [ 2:0] DRP_FSM
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gtxreset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16x20_mode_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gtxreset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16x20_mode_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2;
//---------- Internal Signals --------------------------
reg [ 1:0] load_cnt = 2'd0;
reg [ 4:0] index = 5'd0;
reg mode = 1'd0;
reg [ 8:0] addr_reg = 9'd0;
reg [15:0] di_reg = 16'd0;
//---------- Output Registers --------------------------
reg done = 1'd0;
reg [ 2:0] fsm = 0;
//---------- DRP Address -------------------------------
// DRP access for *RXCDR_EIDLE includes
// - [11] RXCDR_HOLD_DURING_EIDLE
// - [12] RXCDR_FR_RESET_ON_EIDLE
// - [13] RXCDR_PH_RESET_ON_EIDLE
//------------------------------------------------------
localparam ADDR_PCS_RSVD_ATTR = 9'h06F;
localparam ADDR_TXOUT_DIV = 9'h088;
localparam ADDR_RXOUT_DIV = 9'h088;
localparam ADDR_TX_DATA_WIDTH = 9'h06B;
localparam ADDR_TX_INT_DATAWIDTH = 9'h06B;
localparam ADDR_RX_DATA_WIDTH = 9'h011;
localparam ADDR_RX_INT_DATAWIDTH = 9'h011;
localparam ADDR_TXBUF_EN = 9'h01C;
localparam ADDR_RXBUF_EN = 9'h09D;
localparam ADDR_TX_XCLK_SEL = 9'h059;
localparam ADDR_RX_XCLK_SEL = 9'h059;
localparam ADDR_CLK_CORRECT_USE = 9'h044;
localparam ADDR_TX_DRIVE_MODE = 9'h019;
localparam ADDR_RXCDR_EIDLE = 9'h0A7;
localparam ADDR_RX_DFE_LPM_EIDLE = 9'h01E;
localparam ADDR_PMA_RSV_A = 9'h099;
localparam ADDR_PMA_RSV_B = 9'h09A;
localparam ADDR_RXCDR_CFG_A = 9'h0A8;
localparam ADDR_RXCDR_CFG_B = 9'h0A9;
localparam ADDR_RXCDR_CFG_C = 9'h0AA;
localparam ADDR_RXCDR_CFG_D = 9'h0AB;
localparam ADDR_RXCDR_CFG_E = 9'h0AC;
localparam ADDR_RXCDR_CFG_F = 9'h0AD; // GTH only
//---------- DRP Mask ----------------------------------
localparam MASK_PCS_RSVD_ATTR = 16'b1111111111111001; // Unmask bit [ 2: 1]
localparam MASK_TXOUT_DIV = 16'b1111111110001111; // Unmask bit [ 6: 4]
localparam MASK_RXOUT_DIV = 16'b1111111111111000; // Unmask bit [ 2: 0]
localparam MASK_TX_DATA_WIDTH = 16'b1111111111111000; // Unmask bit [ 2: 0]
localparam MASK_TX_INT_DATAWIDTH = 16'b1111111111101111; // Unmask bit [ 4]
localparam MASK_RX_DATA_WIDTH = 16'b1100011111111111; // Unmask bit [13:11]
localparam MASK_X16X20_RX_DATA_WIDTH = 16'b1111011111111111; // Unmask bit [ 11] // for x16 or x20 mode only
localparam MASK_RX_INT_DATAWIDTH = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_TXBUF_EN = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_RXBUF_EN = 16'b1111111111111101; // Unmask bit [ 1]
localparam MASK_TX_XCLK_SEL = 16'b1111111101111111; // Unmask bit [ 7]
localparam MASK_RX_XCLK_SEL = 16'b1111111110111111; // Unmask bit [ 6]
localparam MASK_CLK_CORRECT_USE = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_TX_DRIVE_MODE = 16'b1111111111100000; // Unmask bit [ 4:0]
localparam MASK_RXCDR_EIDLE = 16'b1111011111111111; // Unmask bit [ 11]
localparam MASK_RX_DFE_LPM_EIDLE = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_PMA_RSV_A = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_PMA_RSV_B = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_A = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_B = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_C = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_D = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_E_GTX = 16'b1111111100000000; // Unmask bit [ 7: 0]
localparam MASK_RXCDR_CFG_E_GTH = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_F_GTX = 16'b1111111111111111; // Unmask bit [ ]
localparam MASK_RXCDR_CFG_F_GTH = 16'b1111111111111000; // Unmask bit [ 2: 0]
//---------- DRP Data for PCIe Gen1 and Gen2 -----------
localparam GEN12_TXOUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000100000 : 16'b0000000000010000; // Divide by 4 or 2
localparam GEN12_RXOUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000000010 : 16'b0000000000000001; // Divide by 4 or 2
localparam GEN12_TX_DATA_WIDTH = 16'b0000000000000011; // 2-byte (16-bit) external data width
localparam GEN12_TX_INT_DATAWIDTH = 16'b0000000000000000; // 2-byte (20-bit) internal data width
localparam GEN12_RX_DATA_WIDTH = 16'b0001100000000000; // 2-byte (16-bit) external data width
localparam GEN12_RX_INT_DATAWIDTH = 16'b0000000000000000; // 2-byte (20-bit) internal data width
localparam GEN12_TXBUF_EN = 16'b0100000000000000; // Use TX buffer if PCIE_TXBUF_EN == "TRUE"
localparam GEN12_RXBUF_EN = 16'b0000000000000010; // Use RX buffer
localparam GEN12_TX_XCLK_SEL = 16'b0000000000000000; // Use TXOUT if PCIE_TXBUF_EN == "TRUE"
localparam GEN12_RX_XCLK_SEL = 16'b0000000000000000; // Use RXREC
localparam GEN12_CLK_CORRECT_USE = 16'b0100000000000000; // Use clock correction
localparam GEN12_TX_DRIVE_MODE = 16'b0000000000000001; // Use PIPE Gen1 and Gen2 mode
localparam GEN12_RXCDR_EIDLE = 16'b0000100000000000; // Hold RXCDR during electrical idle
localparam GEN12_RX_DFE_LPM_EIDLE = 16'b0100000000000000; // Hold RX DFE or LPM during electrical idle
localparam GEN12_PMA_RSV_A_GTX = 16'b1000010010000000; // 16'h8480
localparam GEN12_PMA_RSV_B_GTX = 16'b0000000000000001; // 16'h0001
localparam GEN12_PMA_RSV_A_GTH = 16'b0000000000001000; // 16'h0008
localparam GEN12_PMA_RSV_B_GTH = 16'b0000000000000000; // 16'h0000
//----------
localparam GEN12_RXCDR_CFG_A_GTX = 16'h0020; // 16'h0020
localparam GEN12_RXCDR_CFG_B_GTX = 16'h1020; // 16'h1020
localparam GEN12_RXCDR_CFG_C_GTX = 16'h23FF; // 16'h23FF
localparam GEN12_RXCDR_CFG_D_GTX_S = 16'h0000; // 16'h0000 Sync
localparam GEN12_RXCDR_CFG_D_GTX_A = 16'h8000; // 16'h8000 Async
localparam GEN12_RXCDR_CFG_E_GTX = 16'h0003; // 16'h0003
localparam GEN12_RXCDR_CFG_F_GTX = 16'h0000; // 16'h0000
//----------
localparam GEN12_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync
localparam GEN12_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async
localparam GEN12_RXCDR_CFG_B_GTH = 16'hC208; // 16'hC208
localparam GEN12_RXCDR_CFG_C_GTH = 16'h2000; // 16'h2000
localparam GEN12_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE
localparam GEN12_RXCDR_CFG_E_GTH = 16'h0020; // 16'h0020
localparam GEN12_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000
//---------- DRP Data for PCIe Gen3 --------------------
localparam GEN3_TXOUT_DIV = 16'b0000000000000000; // Divide by 1
localparam GEN3_RXOUT_DIV = 16'b0000000000000000; // Divide by 1
localparam GEN3_TX_DATA_WIDTH = 16'b0000000000000100; // 4-byte (32-bit) external data width
localparam GEN3_TX_INT_DATAWIDTH = 16'b0000000000010000; // 4-byte (32-bit) internal data width
localparam GEN3_RX_DATA_WIDTH = 16'b0010000000000000; // 4-byte (32-bit) external data width
localparam GEN3_RX_INT_DATAWIDTH = 16'b0100000000000000; // 4-byte (32-bit) internal data width
localparam GEN3_TXBUF_EN = 16'b0000000000000000; // Bypass TX buffer
localparam GEN3_RXBUF_EN = 16'b0000000000000000; // Bypass RX buffer
localparam GEN3_TX_XCLK_SEL = 16'b0000000010000000; // Use TXUSR
localparam GEN3_RX_XCLK_SEL = 16'b0000000001000000; // Use RXUSR
localparam GEN3_CLK_CORRECT_USE = 16'b0000000000000000; // Bypass clock correction
localparam GEN3_TX_DRIVE_MODE = 16'b0000000000000010; // Use PIPE Gen3 mode
localparam GEN3_RXCDR_EIDLE = 16'b0000000000000000; // Disable Hold RXCDR during electrical idle
localparam GEN3_RX_DFE_LPM_EIDLE = 16'b0000000000000000; // Disable RX DFE or LPM during electrical idle
localparam GEN3_PMA_RSV_A_GTX = 16'b0111000010000000; // 16'h7080
localparam GEN3_PMA_RSV_B_GTX = 16'b0000000000011110; // 16'h001E
localparam GEN3_PMA_RSV_A_GTH = 16'b0000000000001000; // 16'h0008
localparam GEN3_PMA_RSV_B_GTH = 16'b0000000000000000; // 16'h0000
//----------
localparam GEN3_RXCDR_CFG_A_GTX = 16'h0080; // 16'h0080
localparam GEN3_RXCDR_CFG_B_GTX = 16'h1010; // 16'h1010
localparam GEN3_RXCDR_CFG_C_GTX = 16'h0BFF; // 16'h0BFF
localparam GEN3_RXCDR_CFG_D_GTX_S = 16'h0000; // 16'h0000 Sync
localparam GEN3_RXCDR_CFG_D_GTX_A = 16'h8000; // 16'h8000 Async
localparam GEN3_RXCDR_CFG_E_GTX = 16'h000B; // 16'h000B
localparam GEN3_RXCDR_CFG_F_GTX = 16'h0000; // 16'h0000
//----------
//localparam GEN3_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync
//localparam GEN3_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async
//localparam GEN3_RXCDR_CFG_B_GTH = 16'hC208; // 16'hC848
//localparam GEN3_RXCDR_CFG_C_GTH = 16'h2000; // 16'h1000
//localparam GEN3_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE v1.0 silicon
//localparam GEN3_RXCDR_CFG_D_GTH_AUX = 16'h0FFE; // 16'h07FE v2.0 silicon, [62:59] AUX CDR configuration
//localparam GEN3_RXCDR_CFG_E_GTH = 16'h0020; // 16'h0010
//localparam GEN3_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000 v1.0 silicon
//localparam GEN3_RXCDR_CFG_F_GTH_AUX = 16'h0002; // 16'h0000 v2.0 silicon, [81] AUX CDR enable
//----------
localparam GEN3_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync
localparam GEN3_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async
localparam GEN3_RXCDR_CFG_B_GTH = 16'hC848; // 16'hC848
localparam GEN3_RXCDR_CFG_C_GTH = 16'h1000; // 16'h1000
localparam GEN3_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE v1.0 silicon
localparam GEN3_RXCDR_CFG_D_GTH_AUX = 16'h0FFE; // 16'h07FE v2.0 silicon, [62:59] AUX CDR configuration
localparam GEN3_RXCDR_CFG_E_GTH = 16'h0010; // 16'h0010
localparam GEN3_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000 v1.0 silicon
localparam GEN3_RXCDR_CFG_F_GTH_AUX = 16'h0002; // 16'h0000 v2.0 silicon, [81] AUX CDR enable
//---------- DRP Data for PCIe Gen1, Gen2 and Gen3 -----
localparam GEN123_PCS_RSVD_ATTR_A = 16'b0000000000000000; // Auto TX and RX sync mode
localparam GEN123_PCS_RSVD_ATTR_M_TX = 16'b0000000000000010; // Manual TX sync mode
localparam GEN123_PCS_RSVD_ATTR_M_RX = 16'b0000000000000100; // Manual RX sync mode
//---------- DRP Data for x16 --------------------------
localparam X16_RX_DATAWIDTH = 16'b0000000000000000; // 2-byte (16-bit) internal data width
//---------- DRP Data for x20 --------------------------
localparam X20_RX_DATAWIDTH = 16'b0000100000000000; // 2-byte (20-bit) internal data width
//---------- DRP Data ----------------------------------
wire [15:0] data_txout_div;
wire [15:0] data_rxout_div;
wire [15:0] data_tx_data_width;
wire [15:0] data_tx_int_datawidth;
wire [15:0] data_rx_data_width;
wire [15:0] data_rx_int_datawidth;
wire [15:0] data_txbuf_en;
wire [15:0] data_rxbuf_en;
wire [15:0] data_tx_xclk_sel;
wire [15:0] data_rx_xclk_sel;
wire [15:0] data_clk_correction_use;
wire [15:0] data_tx_drive_mode;
wire [15:0] data_rxcdr_eidle;
wire [15:0] data_rx_dfe_lpm_eidle;
wire [15:0] data_pma_rsv_a;
wire [15:0] data_pma_rsv_b;
wire [15:0] data_rxcdr_cfg_a;
wire [15:0] data_rxcdr_cfg_b;
wire [15:0] data_rxcdr_cfg_c;
wire [15:0] data_rxcdr_cfg_d;
wire [15:0] data_rxcdr_cfg_e;
wire [15:0] data_rxcdr_cfg_f;
wire [15:0] data_pcs_rsvd_attr_a;
wire [15:0] data_pcs_rsvd_attr_m_tx;
wire [15:0] data_pcs_rsvd_attr_m_rx;
wire [15:0] data_pcs_rsvd_attr_m;
wire [15:0] data_x16x20_rx_datawidth;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 0;
localparam FSM_LOAD = 1;
localparam FSM_READ = 2;
localparam FSM_RRDY = 3;
localparam FSM_WRITE = 4;
localparam FSM_WRDY = 5;
localparam FSM_DONE = 6;
//---------- Input FF ----------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
//---------- 1st Stage FF --------------------------
gtxreset_reg1 <= 1'd0;
rate_reg1 <= 2'd0;
x16x20_mode_reg1 <= 1'd0;
x16_reg1 <= 1'd0;
do_reg1 <= 16'd0;
rdy_reg1 <= 1'd0;
start_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
gtxreset_reg2 <= 1'd0;
rate_reg2 <= 2'd0;
x16x20_mode_reg2 <= 1'd0;
x16_reg2 <= 1'd0;
do_reg2 <= 16'd0;
rdy_reg2 <= 1'd0;
start_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
gtxreset_reg1 <= DRP_GTXRESET;
rate_reg1 <= DRP_RATE;
x16x20_mode_reg1 <= DRP_X16X20_MODE;
x16_reg1 <= DRP_X16;
do_reg1 <= DRP_DO;
rdy_reg1 <= DRP_RDY;
start_reg1 <= DRP_START;
//---------- 2nd Stage FF --------------------------
gtxreset_reg2 <= gtxreset_reg1;
rate_reg2 <= rate_reg1;
x16x20_mode_reg2 <= x16x20_mode_reg1;
x16_reg2 <= x16_reg1;
do_reg2 <= do_reg1;
rdy_reg2 <= rdy_reg1;
start_reg2 <= start_reg1;
end
end
//---------- Select DRP Data ---------------------------------------------------
assign data_txout_div = (rate_reg2 == 2'd2) ? GEN3_TXOUT_DIV : GEN12_TXOUT_DIV;
assign data_rxout_div = (rate_reg2 == 2'd2) ? GEN3_RXOUT_DIV : GEN12_RXOUT_DIV;
assign data_tx_data_width = (rate_reg2 == 2'd2) ? GEN3_TX_DATA_WIDTH : GEN12_TX_DATA_WIDTH;
assign data_tx_int_datawidth = (rate_reg2 == 2'd2) ? GEN3_TX_INT_DATAWIDTH : GEN12_TX_INT_DATAWIDTH;
assign data_rx_data_width = (rate_reg2 == 2'd2) ? GEN3_RX_DATA_WIDTH : GEN12_RX_DATA_WIDTH;
assign data_rx_int_datawidth = (rate_reg2 == 2'd2) ? GEN3_RX_INT_DATAWIDTH : GEN12_RX_INT_DATAWIDTH;
assign data_txbuf_en = ((rate_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? GEN3_TXBUF_EN : GEN12_TXBUF_EN;
assign data_rxbuf_en = ((rate_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE")) ? GEN3_RXBUF_EN : GEN12_RXBUF_EN;
assign data_tx_xclk_sel = ((rate_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? GEN3_TX_XCLK_SEL : GEN12_TX_XCLK_SEL;
assign data_rx_xclk_sel = ((rate_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE")) ? GEN3_RX_XCLK_SEL : GEN12_RX_XCLK_SEL;
assign data_clk_correction_use = (rate_reg2 == 2'd2) ? GEN3_CLK_CORRECT_USE : GEN12_CLK_CORRECT_USE;
assign data_tx_drive_mode = (rate_reg2 == 2'd2) ? GEN3_TX_DRIVE_MODE : GEN12_TX_DRIVE_MODE;
assign data_rxcdr_eidle = (rate_reg2 == 2'd2) ? GEN3_RXCDR_EIDLE : GEN12_RXCDR_EIDLE;
assign data_rx_dfe_lpm_eidle = (rate_reg2 == 2'd2) ? GEN3_RX_DFE_LPM_EIDLE : GEN12_RX_DFE_LPM_EIDLE;
assign data_pma_rsv_a = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_PMA_RSV_A_GTH : GEN3_PMA_RSV_A_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_PMA_RSV_A_GTH : GEN12_PMA_RSV_A_GTX);
assign data_pma_rsv_b = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_PMA_RSV_B_GTH : GEN3_PMA_RSV_B_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_PMA_RSV_B_GTH : GEN12_PMA_RSV_B_GTX);
assign data_rxcdr_cfg_a = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_A_GTH_A : GEN3_RXCDR_CFG_A_GTH_S) : GEN3_RXCDR_CFG_A_GTX) :
((PCIE_GT_DEVICE == "GTH") ? ((PCIE_ASYNC_EN == "TRUE") ? GEN12_RXCDR_CFG_A_GTH_A : GEN12_RXCDR_CFG_A_GTH_S) : GEN12_RXCDR_CFG_A_GTX);
assign data_rxcdr_cfg_b = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_B_GTH : GEN3_RXCDR_CFG_B_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_B_GTH : GEN12_RXCDR_CFG_B_GTX);
assign data_rxcdr_cfg_c = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_C_GTH : GEN3_RXCDR_CFG_C_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_C_GTH : GEN12_RXCDR_CFG_C_GTX);
assign data_rxcdr_cfg_d = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_AUX_CDR_GEN3_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTH_AUX : GEN3_RXCDR_CFG_D_GTH) : ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTX_A : GEN3_RXCDR_CFG_D_GTX_S)) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_D_GTH : ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTX_A : GEN3_RXCDR_CFG_D_GTX_S));
assign data_rxcdr_cfg_e = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_E_GTH : GEN3_RXCDR_CFG_E_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_E_GTH : GEN12_RXCDR_CFG_E_GTX);
assign data_rxcdr_cfg_f = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_AUX_CDR_GEN3_EN == "TRUE") ? GEN3_RXCDR_CFG_F_GTH_AUX : GEN3_RXCDR_CFG_F_GTH) : GEN3_RXCDR_CFG_F_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_F_GTH : GEN12_RXCDR_CFG_F_GTX);
assign data_pcs_rsvd_attr_a = GEN123_PCS_RSVD_ATTR_A;
assign data_pcs_rsvd_attr_m_tx = PCIE_TXSYNC_MODE ? GEN123_PCS_RSVD_ATTR_A : GEN123_PCS_RSVD_ATTR_M_TX;
assign data_pcs_rsvd_attr_m_rx = PCIE_RXSYNC_MODE ? GEN123_PCS_RSVD_ATTR_A : GEN123_PCS_RSVD_ATTR_M_RX;
assign data_pcs_rsvd_attr_m = data_pcs_rsvd_attr_m_tx | data_pcs_rsvd_attr_m_rx;
assign data_x16x20_rx_datawidth = x16_reg2 ? X16_RX_DATAWIDTH : X20_RX_DATAWIDTH;
//---------- Load Counter ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
load_cnt <= 2'd0;
else
//---------- Increment Load Counter ----------------
if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX))
load_cnt <= load_cnt + 2'd1;
//---------- Hold Load Counter ---------------------
else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX))
load_cnt <= load_cnt;
//---------- Reset Load Counter --------------------
else
load_cnt <= 2'd0;
end
//---------- Update DRP Address and Data ---------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
addr_reg <= 9'd0;
di_reg <= 16'd0;
end
else
begin
case (index)
//--------------------------------------------------
5'd0:
begin
addr_reg <= mode ? ADDR_PCS_RSVD_ATTR :
x16x20_mode_reg2 ? ADDR_RX_DATA_WIDTH : ADDR_TXOUT_DIV;
di_reg <= mode ? ((do_reg2 & MASK_PCS_RSVD_ATTR) | data_pcs_rsvd_attr_a) :
x16x20_mode_reg2 ? ((do_reg2 & MASK_X16X20_RX_DATA_WIDTH) | data_x16x20_rx_datawidth) :
((do_reg2 & MASK_TXOUT_DIV) | data_txout_div);
end
//--------------------------------------------------
5'd1:
begin
addr_reg <= mode ? ADDR_PCS_RSVD_ATTR : ADDR_RXOUT_DIV;
di_reg <= mode ? ((do_reg2 & MASK_PCS_RSVD_ATTR) | data_pcs_rsvd_attr_m) :
((do_reg2 & MASK_RXOUT_DIV) | data_rxout_div);
end
//--------------------------------------------------
5'd2 :
begin
addr_reg <= ADDR_TX_DATA_WIDTH;
di_reg <= (do_reg2 & MASK_TX_DATA_WIDTH) | data_tx_data_width;
end
//--------------------------------------------------
5'd3 :
begin
addr_reg <= ADDR_TX_INT_DATAWIDTH;
di_reg <= (do_reg2 & MASK_TX_INT_DATAWIDTH) | data_tx_int_datawidth;
end
//--------------------------------------------------
5'd4 :
begin
addr_reg <= ADDR_RX_DATA_WIDTH;
di_reg <= (do_reg2 & MASK_RX_DATA_WIDTH) | data_rx_data_width;
end
//--------------------------------------------------
5'd5 :
begin
addr_reg <= ADDR_RX_INT_DATAWIDTH;
di_reg <= (do_reg2 & MASK_RX_INT_DATAWIDTH) | data_rx_int_datawidth;
end
//--------------------------------------------------
5'd6 :
begin
addr_reg <= ADDR_TXBUF_EN;
di_reg <= (do_reg2 & MASK_TXBUF_EN) | data_txbuf_en;
end
//--------------------------------------------------
5'd7 :
begin
addr_reg <= ADDR_RXBUF_EN;
di_reg <= (do_reg2 & MASK_RXBUF_EN) | data_rxbuf_en;
end
//--------------------------------------------------
5'd8 :
begin
addr_reg <= ADDR_TX_XCLK_SEL;
di_reg <= (do_reg2 & MASK_TX_XCLK_SEL) | data_tx_xclk_sel;
end
//--------------------------------------------------
5'd9 :
begin
addr_reg <= ADDR_RX_XCLK_SEL;
di_reg <= (do_reg2 & MASK_RX_XCLK_SEL) | data_rx_xclk_sel;
end
//--------------------------------------------------
5'd10 :
begin
addr_reg <= ADDR_CLK_CORRECT_USE;
di_reg <= (do_reg2 & MASK_CLK_CORRECT_USE) | data_clk_correction_use;
end
//--------------------------------------------------
5'd11 :
begin
addr_reg <= ADDR_TX_DRIVE_MODE;
di_reg <= (do_reg2 & MASK_TX_DRIVE_MODE) | data_tx_drive_mode;
end
//--------------------------------------------------
5'd12 :
begin
addr_reg <= ADDR_RXCDR_EIDLE;
di_reg <= (do_reg2 & MASK_RXCDR_EIDLE) | data_rxcdr_eidle;
end
//--------------------------------------------------
5'd13 :
begin
addr_reg <= ADDR_RX_DFE_LPM_EIDLE;
di_reg <= (do_reg2 & MASK_RX_DFE_LPM_EIDLE) | data_rx_dfe_lpm_eidle;
end
//--------------------------------------------------
5'd14 :
begin
addr_reg <= ADDR_PMA_RSV_A;
di_reg <= (do_reg2 & MASK_PMA_RSV_A) | data_pma_rsv_a;
end
//--------------------------------------------------
5'd15 :
begin
addr_reg <= ADDR_PMA_RSV_B;
di_reg <= (do_reg2 & MASK_PMA_RSV_B) | data_pma_rsv_b;
end
//--------------------------------------------------
5'd16 :
begin
addr_reg <= ADDR_RXCDR_CFG_A;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_A) | data_rxcdr_cfg_a;
end
//--------------------------------------------------
5'd17 :
begin
addr_reg <= ADDR_RXCDR_CFG_B;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_B) | data_rxcdr_cfg_b;
end
//--------------------------------------------------
5'd18 :
begin
addr_reg <= ADDR_RXCDR_CFG_C;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_C) | data_rxcdr_cfg_c;
end
//--------------------------------------------------
5'd19 :
begin
addr_reg <= ADDR_RXCDR_CFG_D;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_D) | data_rxcdr_cfg_d;
end
//--------------------------------------------------
5'd20 :
begin
addr_reg <= ADDR_RXCDR_CFG_E;
di_reg <= (do_reg2 & ((PCIE_GT_DEVICE == "GTH") ? MASK_RXCDR_CFG_E_GTH : MASK_RXCDR_CFG_E_GTX)) | data_rxcdr_cfg_e;
end
//--------------------------------------------------
5'd21 :
begin
addr_reg <= ADDR_RXCDR_CFG_F;
di_reg <= (do_reg2 & ((PCIE_GT_DEVICE == "GTH") ? MASK_RXCDR_CFG_F_GTH : MASK_RXCDR_CFG_F_GTX)) | data_rxcdr_cfg_f;
end
//--------------------------------------------------
default :
begin
addr_reg <= 9'd0;
di_reg <= 16'd0;
end
endcase
end
end
//---------- PIPE DRP FSM ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
//---------- Reset or Rate Change --------------
if (start_reg2)
begin
fsm <= FSM_LOAD;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
//---------- GTXRESET --------------------------
else if ((gtxreset_reg2 && !gtxreset_reg1) && ((PCIE_TXSYNC_MODE == 0) || (PCIE_RXSYNC_MODE == 0)) && (PCIE_USE_MODE == "1.0"))
begin
fsm <= FSM_LOAD;
index <= 5'd0;
mode <= 1'd1;
done <= 1'd0;
end
//---------- Idle ------------------------------
else
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd1;
end
end
//---------- Load DRP Address ---------------------
FSM_LOAD :
begin
fsm <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Read DRP ------------------------------
FSM_READ :
begin
fsm <= FSM_RRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Read DRP Ready ------------------------
FSM_RRDY :
begin
fsm <= rdy_reg2 ? FSM_WRITE : FSM_RRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Write DRP -----------------------------
FSM_WRITE :
begin
fsm <= FSM_WRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Write DRP Ready -----------------------
FSM_WRDY :
begin
fsm <= rdy_reg2 ? FSM_DONE : FSM_WRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- DRP Done ------------------------------
FSM_DONE :
begin
if ((index == INDEX_MAX) || (mode && (index == 5'd1)) || (x16x20_mode_reg2 && (index == 5'd0)))
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
else
begin
fsm <= FSM_LOAD;
index <= index + 5'd1;
mode <= mode;
done <= 1'd0;
end
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
endcase
end
end
//---------- PIPE DRP Output ---------------------------------------------------
assign DRP_ADDR = addr_reg;
assign DRP_EN = (fsm == FSM_READ) || (fsm == FSM_WRITE);
assign DRP_DI = di_reg;
assign DRP_WE = (fsm == FSM_WRITE);
assign DRP_DONE = done;
assign DRP_FSM = fsm;
endmodule
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
module test_aes_256;
// Inputs
reg clk;
reg [127:0] state;
reg [255:0] key;
// Outputs
wire [127:0] out;
// Instantiate the Unit Under Test (UUT)
aes_256 uut (
.clk(clk),
.state(state),
.key(key),
.out(out)
);
initial begin
clk = 0;
state = 0;
key = 0;
#100;
/*
* TIMEGRP "key" OFFSET = IN 6.4 ns VALID 6 ns AFTER "clk" HIGH;
* TIMEGRP "state" OFFSET = IN 6.4 ns VALID 6 ns AFTER "clk" HIGH;
* TIMEGRP "out" OFFSET = OUT 2.2 ns BEFORE "clk" HIGH;
*/
@ (negedge clk);
#2;
state = 128'h3243f6a8885a308d313198a2e0370734;
key = 256'h2b7e151628aed2a6abf7158809cf4f3c_762e7160f38b4da56a784d9045190cfe;
#10;
state = 128'h00112233445566778899aabbccddeeff;
key = 256'h000102030405060708090a0b0c0d0e0f_101112131415161718191a1b1c1d1e1f;
#10;
state = 128'h0;
key = 256'h0;
#270;
if (out !== 128'h1a6e6c2c_662e7da6_501ffb62_bc9e93f3)
begin $display("E"); $finish; end
#10;
if (out !== 128'h8ea2b7ca_516745bf_eafc4990_4b496089)
begin $display("E"); $finish; end
$display("Good.");
$finish;
end
always #5 clk = ~clk;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// allows conversions between the dac (or similar) interface to the dma (or similar).
// * asymmetric bus widths in the range allowed by the fifo
// * frequency -- dma can run slower at reduced channels
// * drop or add channels -- pre processing samples
// * interface axis -- allows axi-stream interface
//
// in all cases bandwidth requirements must be met (read <= write).
//
// axis-interface support
// * connect dma_rd as axis_ready, make sure data is present (use dma_rd as
// enable for the data pipe line). leave axis_valid open!
// * make sure read bandwidth <= write bandwidth (or interpolate samples)
//
// the fifo is external- connect all the fifo_* signals to a fifo generator IP.
// configure the IP to match the buswidths & clocks.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_rfifo (
// dac interface
dac_clk,
dac_rd,
dac_rdata,
dac_runf,
// dma interface
dma_clk,
dma_rd,
dma_rdata,
dma_runf,
// fifo interface
fifo_rst,
fifo_rstn,
fifo_wr,
fifo_wdata,
fifo_wfull,
fifo_rd,
fifo_rdata,
fifo_rempty,
fifo_runf);
// parameters
parameter DAC_DATA_WIDTH = 32;
parameter DMA_DATA_WIDTH = 64;
// dac interface
input dac_clk;
input dac_rd;
output [DAC_DATA_WIDTH-1:0] dac_rdata;
output dac_runf;
// dma interface
input dma_clk;
output dma_rd;
input [DMA_DATA_WIDTH-1:0] dma_rdata;
input dma_runf;
// fifo interface
output fifo_rst;
output fifo_rstn;
output fifo_wr;
output [DMA_DATA_WIDTH-1:0] fifo_wdata;
input fifo_wfull;
output fifo_rd;
input [DAC_DATA_WIDTH-1:0] fifo_rdata;
input fifo_rempty;
input fifo_runf;
// internal registers
reg [ 1:0] dac_runf_m = 'd0;
reg dac_runf = 'd0;
reg dma_rd = 'd0;
// dac underflow
always @(posedge dac_clk) begin
dac_runf_m[0] <= dma_runf | fifo_runf;
dac_runf_m[1] <= dac_runf_m[0];
dac_runf <= dac_runf_m[1];
end
// dma read
always @(posedge dma_clk) begin
dma_rd <= ~fifo_wfull;
end
// write
assign fifo_wr = dma_rd;
genvar s;
generate
for (s = 0; s < DMA_DATA_WIDTH; s = s + 1) begin: g_wdata
assign fifo_wdata[s] = dma_rdata[(DMA_DATA_WIDTH-1)-s];
end
endgenerate
// read
assign fifo_rd = ~fifo_rempty & dac_rd;
genvar m;
generate
for (m = 0; m < DAC_DATA_WIDTH; m = m + 1) begin: g_rdata
assign dac_rdata[m] = fifo_rdata[(DAC_DATA_WIDTH-1)-m];
end
endgenerate
// reset & resetn
assign fifo_rst = 1'b0;
assign fifo_rstn = 1'b1;
endmodule
// ***************************************************************************
// ***************************************************************************
|
(** * MoreStlc: More on the Simply Typed Lambda-Calculus *)
Require Export Stlc.
(* ###################################################################### *)
(** * Simple Extensions to STLC *)
(** The simply typed lambda-calculus has enough structure to make its
theoretical properties interesting, but it is not much of a
programming language. In this chapter, we begin to close the gap
with real-world languages by introducing a number of familiar
features that have straightforward treatments at the level of
typing. *)
(** ** Numbers *)
(** Adding types, constants, and primitive operations for numbers is
easy -- just a matter of combining the [Types] and [Stlc]
chapters. *)
(** ** [let]-bindings *)
(** When writing a complex expression, it is often useful to give
names to some of its subexpressions: this avoids repetition and
often increases readability. Most languages provide one or more
ways of doing this. In OCaml (and Coq), for example, we can write
[let x=t1 in t2] to mean ``evaluate the expression [t1] and bind
the name [x] to the resulting value while evaluating [t2].''
Our [let]-binder follows OCaml's in choosing a call-by-value
evaluation order, where the [let]-bound term must be fully
evaluated before evaluation of the [let]-body can begin. The
typing rule [T_Let] tells us that the type of a [let] can be
calculated by calculating the type of the [let]-bound term,
extending the context with a binding with this type, and in this
enriched context calculating the type of the body, which is then
the type of the whole [let] expression.
At this point in the course, it's probably easier simply to look
at the rules defining this new feature as to wade through a lot of
english text conveying the same information. Here they are: *)
(** Syntax:
<<
t ::= Terms
| ... (other terms same as before)
| let x=t in t let-binding
>>
*)
(**
Reduction:
t1 ==> t1'
---------------------------------- (ST_Let1)
let x=t1 in t2 ==> let x=t1' in t2
---------------------------- (ST_LetValue)
let x=v1 in t2 ==> [x:=v1]t2
Typing:
Gamma |- t1 : T1 Gamma , x:T1 |- t2 : T2
-------------------------------------------- (T_Let)
Gamma |- let x=t1 in t2 : T2
*)
(** ** Pairs *)
(** Our functional programming examples in Coq have made
frequent use of _pairs_ of values. The type of such pairs is
called a _product type_.
The formalization of pairs is almost too simple to be worth
discussing. However, let's look briefly at the various parts of
the definition to emphasize the common pattern. *)
(** In Coq, the primitive way of extracting the components of a pair
is _pattern matching_. An alternative style is to take [fst] and
[snd] -- the first- and second-projection operators -- as
primitives. Just for fun, let's do our products this way. For
example, here's how we'd write a function that takes a pair of
numbers and returns the pair of their sum and difference:
<<
\x:Nat*Nat.
let sum = x.fst + x.snd in
let diff = x.fst - x.snd in
(sum,diff)
>>
*)
(** Adding pairs to the simply typed lambda-calculus, then, involves
adding two new forms of term -- pairing, written [(t1,t2)], and
projection, written [t.fst] for the first projection from [t] and
[t.snd] for the second projection -- plus one new type constructor,
[T1*T2], called the _product_ of [T1] and [T2]. *)
(** Syntax:
<<
t ::= Terms
| ...
| (t,t) pair
| t.fst first projection
| t.snd second projection
v ::= Values
| ...
| (v,v) pair value
T ::= Types
| ...
| T * T product type
>>
*)
(** For evaluation, we need several new rules specifying how pairs and
projection behave.
t1 ==> t1'
-------------------- (ST_Pair1)
(t1,t2) ==> (t1',t2)
t2 ==> t2'
-------------------- (ST_Pair2)
(v1,t2) ==> (v1,t2')
t1 ==> t1'
------------------ (ST_Fst1)
t1.fst ==> t1'.fst
------------------ (ST_FstPair)
(v1,v2).fst ==> v1
t1 ==> t1'
------------------ (ST_Snd1)
t1.snd ==> t1'.snd
------------------ (ST_SndPair)
(v1,v2).snd ==> v2
*)
(**
Rules [ST_FstPair] and [ST_SndPair] specify that, when a fully
evaluated pair meets a first or second projection, the result is
the appropriate component. The congruence rules [ST_Fst1] and
[ST_Snd1] allow reduction to proceed under projections, when the
term being projected from has not yet been fully evaluated.
[ST_Pair1] and [ST_Pair2] evaluate the parts of pairs: first the
left part, and then -- when a value appears on the left -- the right
part. The ordering arising from the use of the metavariables [v]
and [t] in these rules enforces a left-to-right evaluation
strategy for pairs. (Note the implicit convention that
metavariables like [v] and [v1] can only denote values.) We've
also added a clause to the definition of values, above, specifying
that [(v1,v2)] is a value. The fact that the components of a pair
value must themselves be values ensures that a pair passed as an
argument to a function will be fully evaluated before the function
body starts executing. *)
(** The typing rules for pairs and projections are straightforward.
Gamma |- t1 : T1 Gamma |- t2 : T2
--------------------------------------- (T_Pair)
Gamma |- (t1,t2) : T1*T2
Gamma |- t1 : T11*T12
--------------------- (T_Fst)
Gamma |- t1.fst : T11
Gamma |- t1 : T11*T12
--------------------- (T_Snd)
Gamma |- t1.snd : T12
*)
(** The rule [T_Pair] says that [(t1,t2)] has type [T1*T2] if [t1] has
type [T1] and [t2] has type [T2]. Conversely, the rules [T_Fst]
and [T_Snd] tell us that, if [t1] has a product type
[T11*T12] (i.e., if it will evaluate to a pair), then the types of
the projections from this pair are [T11] and [T12]. *)
(** ** Unit *)
(** Another handy base type, found especially in languages in
the ML family, is the singleton type [Unit]. *)
(** It has a single element -- the term constant [unit] (with a small
[u]) -- and a typing rule making [unit] an element of [Unit]. We
also add [unit] to the set of possible result values of
computations -- indeed, [unit] is the _only_ possible result of
evaluating an expression of type [Unit]. *)
(** Syntax:
<<
t ::= Terms
| ...
| unit unit value
v ::= Values
| ...
| unit unit
T ::= Types
| ...
| Unit Unit type
>>
Typing:
-------------------- (T_Unit)
Gamma |- unit : Unit
*)
(** It may seem a little strange to bother defining a type that
has just one element -- after all, wouldn't every computation
living in such a type be trivial?
This is a fair question, and indeed in the STLC the [Unit] type is
not especially critical (though we'll see two uses for it below).
Where [Unit] really comes in handy is in richer languages with
various sorts of _side effects_ -- e.g., assignment statements
that mutate variables or pointers, exceptions and other sorts of
nonlocal control structures, etc. In such languages, it is
convenient to have a type for the (trivial) result of an
expression that is evaluated only for its effect. *)
(** ** Sums *)
(** Many programs need to deal with values that can take two distinct
forms. For example, we might identify employees in an accounting
application using using _either_ their name _or_ their id number.
A search function might return _either_ a matching value _or_ an
error code.
These are specific examples of a binary _sum type_,
which describes a set of values drawn from exactly two given types, e.g.
<<
Nat + Bool
>>
*)
(** We create elements of these types by _tagging_ elements of
the component types. For example, if [n] is a [Nat] then [inl v]
is an element of [Nat+Bool]; similarly, if [b] is a [Bool] then
[inr b] is a [Nat+Bool]. The names of the tags [inl] and [inr]
arise from thinking of them as functions
<<
inl : Nat -> Nat + Bool
inr : Bool -> Nat + Bool
>>
that "inject" elements of [Nat] or [Bool] into the left and right
components of the sum type [Nat+Bool]. (But note that we don't
actually treat them as functions in the way we formalize them:
[inl] and [inr] are keywords, and [inl t] and [inr t] are primitive
syntactic forms, not function applications. This allows us to give
them their own special typing rules.) *)
(** In general, the elements of a type [T1 + T2] consist of the
elements of [T1] tagged with the token [inl], plus the elements of
[T2] tagged with [inr]. *)
(** One important usage of sums is signaling errors:
<<
div : Nat -> Nat -> (Nat + Unit) =
div =
\x:Nat. \y:Nat.
if iszero y then
inr unit
else
inl ...
>>
The type [Nat + Unit] above is in fact isomorphic to [option nat]
in Coq, and we've already seen how to signal errors with options. *)
(** To _use_ elements of sum types, we introduce a [case]
construct (a very simplified form of Coq's [match]) to destruct
them. For example, the following procedure converts a [Nat+Bool]
into a [Nat]: *)
(**
<<
getNat =
\x:Nat+Bool.
case x of
inl n => n
| inr b => if b then 1 else 0
>>
*)
(** More formally... *)
(** Syntax:
<<
t ::= Terms
| ...
| inl T t tagging (left)
| inr T t tagging (right)
| case t of case
inl x => t
| inr x => t
v ::= Values
| ...
| inl T v tagged value (left)
| inr T v tagged value (right)
T ::= Types
| ...
| T + T sum type
>>
*)
(** Evaluation:
t1 ==> t1'
---------------------- (ST_Inl)
inl T t1 ==> inl T t1'
t1 ==> t1'
---------------------- (ST_Inr)
inr T t1 ==> inr T t1'
t0 ==> t0'
------------------------------------------- (ST_Case)
case t0 of inl x1 => t1 | inr x2 => t2 ==>
case t0' of inl x1 => t1 | inr x2 => t2
---------------------------------------------- (ST_CaseInl)
case (inl T v0) of inl x1 => t1 | inr x2 => t2
==> [x1:=v0]t1
---------------------------------------------- (ST_CaseInr)
case (inr T v0) of inl x1 => t1 | inr x2 => t2
==> [x2:=v0]t2
*)
(** Typing:
Gamma |- t1 : T1
---------------------------- (T_Inl)
Gamma |- inl T2 t1 : T1 + T2
Gamma |- t1 : T2
---------------------------- (T_Inr)
Gamma |- inr T1 t1 : T1 + T2
Gamma |- t0 : T1+T2
Gamma , x1:T1 |- t1 : T
Gamma , x2:T2 |- t2 : T
--------------------------------------------------- (T_Case)
Gamma |- case t0 of inl x1 => t1 | inr x2 => t2 : T
We use the type annotation in [inl] and [inr] to make the typing
simpler, similarly to what we did for functions. *)
(** Without this extra
information, the typing rule [T_Inl], for example, would have to
say that, once we have shown that [t1] is an element of type [T1],
we can derive that [inl t1] is an element of [T1 + T2] for _any_
type T2. For example, we could derive both [inl 5 : Nat + Nat]
and [inl 5 : Nat + Bool] (and infinitely many other types).
This failure of uniqueness of types would mean that we cannot
build a typechecking algorithm simply by "reading the rules from
bottom to top" as we could for all the other features seen so far.
There are various ways to deal with this difficulty. One simple
one -- which we've adopted here -- forces the programmer to
explicitly annotate the "other side" of a sum type when performing
an injection. This is rather heavyweight for programmers (and so
real languages adopt other solutions), but it is easy to
understand and formalize. *)
(** ** Lists *)
(** The typing features we have seen can be classified into _base
types_ like [Bool], and _type constructors_ like [->] and [*] that
build new types from old ones. Another useful type constructor is
[List]. For every type [T], the type [List T] describes
finite-length lists whose elements are drawn from [T].
In principle, we could encode lists using pairs, sums and
_recursive_ types. But giving semantics to recursive types is
non-trivial. Instead, we'll just discuss the special case of lists
directly.
Below we give the syntax, semantics, and typing rules for lists.
Except for the fact that explicit type annotations are mandatory
on [nil] and cannot appear on [cons], these lists are essentially
identical to those we built in Coq. We use [lcase] to destruct
lists, to avoid dealing with questions like "what is the [head] of
the empty list?" *)
(** For example, here is a function that calculates the sum of
the first two elements of a list of numbers:
<<
\x:List Nat.
lcase x of nil -> 0
| a::x' -> lcase x' of nil -> a
| b::x'' -> a+b
>>
*)
(**
Syntax:
<<
t ::= Terms
| ...
| nil T
| cons t t
| lcase t of nil -> t | x::x -> t
v ::= Values
| ...
| nil T nil value
| cons v v cons value
T ::= Types
| ...
| List T list of Ts
>>
*)
(** Reduction:
t1 ==> t1'
-------------------------- (ST_Cons1)
cons t1 t2 ==> cons t1' t2
t2 ==> t2'
-------------------------- (ST_Cons2)
cons v1 t2 ==> cons v1 t2'
t1 ==> t1'
---------------------------------------- (ST_Lcase1)
(lcase t1 of nil -> t2 | xh::xt -> t3) ==>
(lcase t1' of nil -> t2 | xh::xt -> t3)
----------------------------------------- (ST_LcaseNil)
(lcase nil T of nil -> t2 | xh::xt -> t3)
==> t2
----------------------------------------------- (ST_LcaseCons)
(lcase (cons vh vt) of nil -> t2 | xh::xt -> t3)
==> [xh:=vh,xt:=vt]t3
*)
(** Typing:
----------------------- (T_Nil)
Gamma |- nil T : List T
Gamma |- t1 : T Gamma |- t2 : List T
----------------------------------------- (T_Cons)
Gamma |- cons t1 t2: List T
Gamma |- t1 : List T1
Gamma |- t2 : T
Gamma , h:T1, t:List T1 |- t3 : T
------------------------------------------------- (T_Lcase)
Gamma |- (lcase t1 of nil -> t2 | h::t -> t3) : T
*)
(** ** General Recursion *)
(** Another facility found in most programming languages (including
Coq) is the ability to define recursive functions. For example,
we might like to be able to define the factorial function like
this:
<<
fact = \x:Nat.
if x=0 then 1 else x * (fact (pred x)))
>>
But this would require quite a bit of work to formalize: we'd have
to introduce a notion of "function definitions" and carry around an
"environment" of such definitions in the definition of the [step]
relation. *)
(** Here is another way that is straightforward to formalize: instead
of writing recursive definitions where the right-hand side can
contain the identifier being defined, we can define a _fixed-point
operator_ that performs the "unfolding" of the recursive definition
in the right-hand side lazily during reduction.
<<
fact =
fix
(\f:Nat->Nat.
\x:Nat.
if x=0 then 1 else x * (f (pred x)))
>>
*)
(** The intuition is that the higher-order function [f] passed
to [fix] is a _generator_ for the [fact] function: if [fact] is
applied to a function that approximates the desired behavior of
[fact] up to some number [n] (that is, a function that returns
correct results on inputs less than or equal to [n]), then it
returns a better approximation to [fact] -- a function that returns
correct results for inputs up to [n+1]. Applying [fix] to this
generator returns its _fixed point_ -- a function that gives the
desired behavior for all inputs [n].
(The term "fixed point" has exactly the same sense as in ordinary
mathematics, where a fixed point of a function [f] is an input [x]
such that [f(x) = x]. Here, a fixed point of a function [F] of
type (say) [(Nat->Nat)->(Nat->Nat)] is a function [f] such that [F
f] is behaviorally equivalent to [f].) *)
(** Syntax:
<<
t ::= Terms
| ...
| fix t fixed-point operator
>>
Reduction:
t1 ==> t1'
------------------ (ST_Fix1)
fix t1 ==> fix t1'
F = \xf:T1.t2
----------------------- (ST_FixAbs)
fix F ==> [xf:=fix F]t2
Typing:
Gamma |- t1 : T1->T1
-------------------- (T_Fix)
Gamma |- fix t1 : T1
*)
(** Let's see how [ST_FixAbs] works by reducing [fact 3 = fix F 3],
where [F = (\f. \x. if x=0 then 1 else x * (f (pred x)))] (we are
omitting type annotations for brevity here).
<<
fix F 3
>>
[==>] [ST_FixAbs]
<<
(\x. if x=0 then 1 else x * (fix F (pred x))) 3
>>
[==>] [ST_AppAbs]
<<
if 3=0 then 1 else 3 * (fix F (pred 3))
>>
[==>] [ST_If0_Nonzero]
<<
3 * (fix F (pred 3))
>>
[==>] [ST_FixAbs + ST_Mult2]
<<
3 * ((\x. if x=0 then 1 else x * (fix F (pred x))) (pred 3))
>>
[==>] [ST_PredNat + ST_Mult2 + ST_App2]
<<
3 * ((\x. if x=0 then 1 else x * (fix F (pred x))) 2)
>>
[==>] [ST_AppAbs + ST_Mult2]
<<
3 * (if 2=0 then 1 else 2 * (fix F (pred 2)))
>>
[==>] [ST_If0_Nonzero + ST_Mult2]
<<
3 * (2 * (fix F (pred 2)))
>>
[==>] [ST_FixAbs + 2 x ST_Mult2]
<<
3 * (2 * ((\x. if x=0 then 1 else x * (fix F (pred x))) (pred 2)))
>>
[==>] [ST_PredNat + 2 x ST_Mult2 + ST_App2]
<<
3 * (2 * ((\x. if x=0 then 1 else x * (fix F (pred x))) 1))
>>
[==>] [ST_AppAbs + 2 x ST_Mult2]
<<
3 * (2 * (if 1=0 then 1 else 1 * (fix F (pred 1))))
>>
[==>] [ST_If0_Nonzero + 2 x ST_Mult2]
<<
3 * (2 * (1 * (fix F (pred 1))))
>>
[==>] [ST_FixAbs + 3 x ST_Mult2]
<<
3 * (2 * (1 * ((\x. if x=0 then 1 else x * (fix F (pred x))) (pred 1))))
>>
[==>] [ST_PredNat + 3 x ST_Mult2 + ST_App2]
<<
3 * (2 * (1 * ((\x. if x=0 then 1 else x * (fix F (pred x))) 0)))
>>
[==>] [ST_AppAbs + 3 x ST_Mult2]
<<
3 * (2 * (1 * (if 0=0 then 1 else 0 * (fix F (pred 0)))))
>>
[==>] [ST_If0Zero + 3 x ST_Mult2]
<<
3 * (2 * (1 * 1))
>>
[==>] [ST_MultNats + 2 x ST_Mult2]
<<
3 * (2 * 1)
>>
[==>] [ST_MultNats + ST_Mult2]
<<
3 * 2
>>
[==>] [ST_MultNats]
<<
6
>>
*)
(** **** Exercise: 1 star (halve_fix) *)
(** Translate this informal recursive definition into one using [fix]:
<<
halve =
\x:Nat.
if x=0 then 0
else if (pred x)=0 then 0
else 1 + (halve (pred (pred x))))
>>
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 1 star (fact_steps) *)
(** Write down the sequence of steps that the term [fact 1] goes
through to reduce to a normal form (assuming the usual reduction
rules for arithmetic operations).
(* FILL IN HERE *)
[]
*)
(** The ability to form the fixed point of a function of type [T->T]
for any [T] has some surprising consequences. In particular, it
implies that _every_ type is inhabited by some term. To see this,
observe that, for every type [T], we can define the term
fix (\x:T.x)
By [T_Fix] and [T_Abs], this term has type [T]. By [ST_FixAbs]
it reduces to itself, over and over again. Thus it is an
_undefined element_ of [T].
More usefully, here's an example using [fix] to define a
two-argument recursive function:
<<
equal =
fix
(\eq:Nat->Nat->Bool.
\m:Nat. \n:Nat.
if m=0 then iszero n
else if n=0 then false
else eq (pred m) (pred n))
>>
And finally, here is an example where [fix] is used to define a
_pair_ of recursive functions (illustrating the fact that the type
[T1] in the rule [T_Fix] need not be a function type):
<<
evenodd =
fix
(\eo: (Nat->Bool * Nat->Bool).
let e = \n:Nat. if n=0 then true else eo.snd (pred n) in
let o = \n:Nat. if n=0 then false else eo.fst (pred n) in
(e,o))
even = evenodd.fst
odd = evenodd.snd
>>
*)
(* ###################################################################### *)
(** ** Records *)
(** As a final example of a basic extension of the STLC, let's
look briefly at how to define _records_ and their types.
Intuitively, records can be obtained from pairs by two kinds of
generalization: they are n-ary products (rather than just binary)
and their fields are accessed by _label_ (rather than position).
Conceptually, this extension is a straightforward generalization
of pairs and product types, but notationally it becomes a little
heavier; for this reason, we postpone its formal treatment to a
separate chapter ([Records]). *)
(** Records are not included in the extended exercise below, but
they will be useful to motivate the [Sub] chapter. *)
(** Syntax:
<<
t ::= Terms
| ...
| {i1=t1, ..., in=tn} record
| t.i projection
v ::= Values
| ...
| {i1=v1, ..., in=vn} record value
T ::= Types
| ...
| {i1:T1, ..., in:Tn} record type
>>
Intuitively, the generalization is pretty obvious. But it's worth
noticing that what we've actually written is rather informal: in
particular, we've written "[...]" in several places to mean "any
number of these," and we've omitted explicit mention of the usual
side-condition that the labels of a record should not contain
repetitions. *)
(* It is possible to devise informal notations that are
more precise, but these tend to be quite heavy and to obscure the
main points of the definitions. So we'll leave these a bit loose
here (they are informal anyway, after all) and do the work of
tightening things up elsewhere (in chapter [Records]). *)
(**
Reduction:
ti ==> ti'
------------------------------------ (ST_Rcd)
{i1=v1, ..., im=vm, in=ti, ...}
==> {i1=v1, ..., im=vm, in=ti', ...}
t1 ==> t1'
-------------- (ST_Proj1)
t1.i ==> t1'.i
------------------------- (ST_ProjRcd)
{..., i=vi, ...}.i ==> vi
Again, these rules are a bit informal. For example, the first rule
is intended to be read "if [ti] is the leftmost field that is not a
value and if [ti] steps to [ti'], then the whole record steps..."
In the last rule, the intention is that there should only be one
field called i, and that all the other fields must contain values. *)
(**
Typing:
Gamma |- t1 : T1 ... Gamma |- tn : Tn
-------------------------------------------------- (T_Rcd)
Gamma |- {i1=t1, ..., in=tn} : {i1:T1, ..., in:Tn}
Gamma |- t : {..., i:Ti, ...}
----------------------------- (T_Proj)
Gamma |- t.i : Ti
*)
(* ###################################################################### *)
(** *** Encoding Records (Optional) *)
(** There are several ways to make the above definitions precise.
- We can directly formalize the syntactic forms and inference
rules, staying as close as possible to the form we've given
them above. This is conceptually straightforward, and it's
probably what we'd want to do if we were building a real
compiler -- in particular, it will allow is to print error
messages in the form that programmers will find easy to
understand. But the formal versions of the rules will not be
pretty at all!
- We could look for a smoother way of presenting records -- for
example, a binary presentation with one constructor for the
empty record and another constructor for adding a single field
to an existing record, instead of a single monolithic
constructor that builds a whole record at once. This is the
right way to go if we are primarily interested in studying the
metatheory of the calculi with records, since it leads to
clean and elegant definitions and proofs. Chapter [Records]
shows how this can be done.
- Alternatively, if we like, we can avoid formalizing records
altogether, by stipulating that record notations are just
informal shorthands for more complex expressions involving
pairs and product types. We sketch this approach here.
First, observe that we can encode arbitrary-size tuples using
nested pairs and the [unit] value. To avoid overloading the pair
notation [(t1,t2)], we'll use curly braces without labels to write
down tuples, so [{}] is the empty tuple, [{5}] is a singleton
tuple, [{5,6}] is a 2-tuple (morally the same as a pair),
[{5,6,7}] is a triple, etc.
<<
{} ----> unit
{t1, t2, ..., tn} ----> (t1, trest)
where {t2, ..., tn} ----> trest
>>
Similarly, we can encode tuple types using nested product types:
<<
{} ----> Unit
{T1, T2, ..., Tn} ----> T1 * TRest
where {T2, ..., Tn} ----> TRest
>>
The operation of projecting a field from a tuple can be encoded
using a sequence of second projections followed by a first projection:
<<
t.0 ----> t.fst
t.(n+1) ----> (t.snd).n
>>
Next, suppose that there is some total ordering on record labels,
so that we can associate each label with a unique natural number.
This number is called the _position_ of the label. For example,
we might assign positions like this:
<<
LABEL POSITION
a 0
b 1
c 2
... ...
foo 1004
... ...
bar 10562
... ...
>>
We use these positions to encode record values as tuples (i.e., as
nested pairs) by sorting the fields according to their positions.
For example:
<<
{a=5, b=6} ----> {5,6}
{a=5, c=7} ----> {5,unit,7}
{c=7, a=5} ----> {5,unit,7}
{c=5, b=3} ----> {unit,3,5}
{f=8,c=5,a=7} ----> {7,unit,5,unit,unit,8}
{f=8,c=5} ----> {unit,unit,5,unit,unit,8}
>>
Note that each field appears in the position associated with its
label, that the size of the tuple is determined by the label with
the highest position, and that we fill in unused positions with
[unit].
We do exactly the same thing with record types:
<<
{a:Nat, b:Nat} ----> {Nat,Nat}
{c:Nat, a:Nat} ----> {Nat,Unit,Nat}
{f:Nat,c:Nat} ----> {Unit,Unit,Nat,Unit,Unit,Nat}
>>
Finally, record projection is encoded as a tuple projection from
the appropriate position:
<<
t.l ----> t.(position of l)
>>
It is not hard to check that all the typing rules for the original
"direct" presentation of records are validated by this
encoding. (The reduction rules are "almost validated" -- not
quite, because the encoding reorders fields.) *)
(** Of course, this encoding will not be very efficient if we
happen to use a record with label [bar]! But things are not
actually as bad as they might seem: for example, if we assume that
our compiler can see the whole program at the same time, we can
_choose_ the numbering of labels so that we assign small positions
to the most frequently used labels. Indeed, there are industrial
compilers that essentially do this! *)
(** *** Variants (Optional Reading) *)
(** Just as products can be generalized to records, sums can be
generalized to n-ary labeled types called _variants_. Instead of
[T1+T2], we can write something like [<l1:T1,l2:T2,...ln:Tn>]
where [l1],[l2],... are field labels which are used both to build
instances and as case arm labels.
These n-ary variants give us almost enough mechanism to build
arbitrary inductive data types like lists and trees from
scratch -- the only thing missing is a way to allow _recursion_ in
type definitions. We won't cover this here, but detailed
treatments can be found in many textbooks -- e.g., Types and
Programming Languages. *)
(* ###################################################################### *)
(** * Exercise: Formalizing the Extensions *)
(** **** Exercise: 4 stars, advanced (STLC_extensions) *)
(** In this problem you will formalize a couple of the extensions
described above. We've provided the necessary additions to the
syntax of terms and types, and we've included a few examples that
you can test your definitions with to make sure they are working
as expected. You'll fill in the rest of the definitions and
extend all the proofs accordingly.
To get you started, we've provided implementations for:
- numbers
- pairs and units
- sums
- lists
You need to complete the implementations for:
- let (which involves binding)
- [fix]
A good strategy is to work on the extensions one at a time, in
multiple passes, rather than trying to work through the file from
start to finish in a single pass. For each definition or proof,
begin by reading carefully through the parts that are provided for
you, referring to the text in the [Stlc] chapter for high-level
intuitions and the embedded comments for detailed mechanics.
*)
Module STLCExtended.
(* ###################################################################### *)
(** *** Syntax and Operational Semantics *)
Inductive ty : Type :=
| TArrow : ty -> ty -> ty
| TNat : ty
| TUnit : ty
| TProd : ty -> ty -> ty
| TSum : ty -> ty -> ty
| TList : ty -> ty.
Tactic Notation "T_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "TArrow" | Case_aux c "TNat"
| Case_aux c "TProd" | Case_aux c "TUnit"
| Case_aux c "TSum" | Case_aux c "TList" ].
Inductive tm : Type :=
(* pure STLC *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
(* numbers *)
| tnat : nat -> tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tmult : tm -> tm -> tm
| tif0 : tm -> tm -> tm -> tm
(* pairs *)
| tpair : tm -> tm -> tm
| tfst : tm -> tm
| tsnd : tm -> tm
(* units *)
| tunit : tm
(* let *)
| tlet : id -> tm -> tm -> tm
(* i.e., [let x = t1 in t2] *)
(* sums *)
| tinl : ty -> tm -> tm
| tinr : ty -> tm -> tm
| tcase : tm -> id -> tm -> id -> tm -> tm
(* i.e., [case t0 of inl x1 => t1 | inr x2 => t2] *)
(* lists *)
| tnil : ty -> tm
| tcons : tm -> tm -> tm
| tlcase : tm -> tm -> id -> id -> tm -> tm
(* i.e., [lcase t1 of | nil -> t2 | x::y -> t3] *)
(* fix *)
| tfix : tm -> tm.
(** Note that, for brevity, we've omitted booleans and instead
provided a single [if0] form combining a zero test and a
conditional. That is, instead of writing
<<
if x = 0 then ... else ...
>>
we'll write this:
<<
if0 x then ... else ...
>>
*)
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp" | Case_aux c "tabs"
| Case_aux c "tnat" | Case_aux c "tsucc" | Case_aux c "tpred"
| Case_aux c "tmult" | Case_aux c "tif0"
| Case_aux c "tpair" | Case_aux c "tfst" | Case_aux c "tsnd"
| Case_aux c "tunit" | Case_aux c "tlet"
| Case_aux c "tinl" | Case_aux c "tinr" | Case_aux c "tcase"
| Case_aux c "tnil" | Case_aux c "tcons" | Case_aux c "tlcase"
| Case_aux c "tfix" ].
(* ###################################################################### *)
(** *** Substitution *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar y =>
if eq_id_dec x y then s else t
| tabs y T t1 =>
tabs y T (if eq_id_dec x y then t1 else (subst x s t1))
| tapp t1 t2 =>
tapp (subst x s t1) (subst x s t2)
| tnat n =>
tnat n
| tsucc t1 =>
tsucc (subst x s t1)
| tpred t1 =>
tpred (subst x s t1)
| tmult t1 t2 =>
tmult (subst x s t1) (subst x s t2)
| tif0 t1 t2 t3 =>
tif0 (subst x s t1) (subst x s t2) (subst x s t3)
| tpair t1 t2 =>
tpair (subst x s t1) (subst x s t2)
| tfst t1 =>
tfst (subst x s t1)
| tsnd t1 =>
tsnd (subst x s t1)
| tunit => tunit
(* FILL IN HERE *)
| tinl T t1 =>
tinl T (subst x s t1)
| tinr T t1 =>
tinr T (subst x s t1)
| tcase t0 y1 t1 y2 t2 =>
tcase (subst x s t0)
y1 (if eq_id_dec x y1 then t1 else (subst x s t1))
y2 (if eq_id_dec x y2 then t2 else (subst x s t2))
| tnil T =>
tnil T
| tcons t1 t2 =>
tcons (subst x s t1) (subst x s t2)
| tlcase t1 t2 y1 y2 t3 =>
tlcase (subst x s t1) (subst x s t2) y1 y2
(if eq_id_dec x y1 then
t3
else if eq_id_dec x y2 then t3
else (subst x s t3))
(* FILL IN HERE *)
| _ => t (* ... and delete this line *)
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ###################################################################### *)
(** *** Reduction *)
(** Next we define the values of our language. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T11 t12,
value (tabs x T11 t12)
(* Numbers are values: *)
| v_nat : forall n1,
value (tnat n1)
(* A pair is a value if both components are: *)
| v_pair : forall v1 v2,
value v1 ->
value v2 ->
value (tpair v1 v2)
(* A unit is always a value *)
| v_unit : value tunit
(* A tagged value is a value: *)
| v_inl : forall v T,
value v ->
value (tinl T v)
| v_inr : forall v T,
value v ->
value (tinr T v)
(* A list is a value iff its head and tail are values: *)
| v_lnil : forall T, value (tnil T)
| v_lcons : forall v1 vl,
value v1 ->
value vl ->
value (tcons v1 vl)
.
Hint Constructors value.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T11 t12 v2,
value v2 ->
(tapp (tabs x T11 t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tapp t1 t2) ==> (tapp t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tapp v1 t2) ==> (tapp v1 t2')
(* nats *)
| ST_Succ1 : forall t1 t1',
t1 ==> t1' ->
(tsucc t1) ==> (tsucc t1')
| ST_SuccNat : forall n1,
(tsucc (tnat n1)) ==> (tnat (S n1))
| ST_Pred : forall t1 t1',
t1 ==> t1' ->
(tpred t1) ==> (tpred t1')
| ST_PredNat : forall n1,
(tpred (tnat n1)) ==> (tnat (pred n1))
| ST_Mult1 : forall t1 t1' t2,
t1 ==> t1' ->
(tmult t1 t2) ==> (tmult t1' t2)
| ST_Mult2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tmult v1 t2) ==> (tmult v1 t2')
| ST_MultNats : forall n1 n2,
(tmult (tnat n1) (tnat n2)) ==> (tnat (mult n1 n2))
| ST_If01 : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif0 t1 t2 t3) ==> (tif0 t1' t2 t3)
| ST_If0Zero : forall t2 t3,
(tif0 (tnat 0) t2 t3) ==> t2
| ST_If0Nonzero : forall n t2 t3,
(tif0 (tnat (S n)) t2 t3) ==> t3
(* pairs *)
| ST_Pair1 : forall t1 t1' t2,
t1 ==> t1' ->
(tpair t1 t2) ==> (tpair t1' t2)
| ST_Pair2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tpair v1 t2) ==> (tpair v1 t2')
| ST_Fst1 : forall t1 t1',
t1 ==> t1' ->
(tfst t1) ==> (tfst t1')
| ST_FstPair : forall v1 v2,
value v1 ->
value v2 ->
(tfst (tpair v1 v2)) ==> v1
| ST_Snd1 : forall t1 t1',
t1 ==> t1' ->
(tsnd t1) ==> (tsnd t1')
| ST_SndPair : forall v1 v2,
value v1 ->
value v2 ->
(tsnd (tpair v1 v2)) ==> v2
(* let *)
(* FILL IN HERE *)
(* sums *)
| ST_Inl : forall t1 t1' T,
t1 ==> t1' ->
(tinl T t1) ==> (tinl T t1')
| ST_Inr : forall t1 t1' T,
t1 ==> t1' ->
(tinr T t1) ==> (tinr T t1')
| ST_Case : forall t0 t0' x1 t1 x2 t2,
t0 ==> t0' ->
(tcase t0 x1 t1 x2 t2) ==> (tcase t0' x1 t1 x2 t2)
| ST_CaseInl : forall v0 x1 t1 x2 t2 T,
value v0 ->
(tcase (tinl T v0) x1 t1 x2 t2) ==> [x1:=v0]t1
| ST_CaseInr : forall v0 x1 t1 x2 t2 T,
value v0 ->
(tcase (tinr T v0) x1 t1 x2 t2) ==> [x2:=v0]t2
(* lists *)
| ST_Cons1 : forall t1 t1' t2,
t1 ==> t1' ->
(tcons t1 t2) ==> (tcons t1' t2)
| ST_Cons2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tcons v1 t2) ==> (tcons v1 t2')
| ST_Lcase1 : forall t1 t1' t2 x1 x2 t3,
t1 ==> t1' ->
(tlcase t1 t2 x1 x2 t3) ==> (tlcase t1' t2 x1 x2 t3)
| ST_LcaseNil : forall T t2 x1 x2 t3,
(tlcase (tnil T) t2 x1 x2 t3) ==> t2
| ST_LcaseCons : forall v1 vl t2 x1 x2 t3,
value v1 ->
value vl ->
(tlcase (tcons v1 vl) t2 x1 x2 t3) ==> (subst x2 vl (subst x1 v1 t3))
(* fix *)
(* FILL IN HERE *)
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1" | Case_aux c "ST_App2"
| Case_aux c "ST_Succ1" | Case_aux c "ST_SuccNat"
| Case_aux c "ST_Pred1" | Case_aux c "ST_PredNat"
| Case_aux c "ST_Mult1" | Case_aux c "ST_Mult2"
| Case_aux c "ST_MultNats" | Case_aux c "ST_If01"
| Case_aux c "ST_If0Zero" | Case_aux c "ST_If0Nonzero"
| Case_aux c "ST_Pair1" | Case_aux c "ST_Pair2"
| Case_aux c "ST_Fst1" | Case_aux c "ST_FstPair"
| Case_aux c "ST_Snd1" | Case_aux c "ST_SndPair"
(* FILL IN HERE *)
| Case_aux c "ST_Inl" | Case_aux c "ST_Inr" | Case_aux c "ST_Case"
| Case_aux c "ST_CaseInl" | Case_aux c "ST_CaseInr"
| Case_aux c "ST_Cons1" | Case_aux c "ST_Cons2" | Case_aux c "ST_Lcase1"
| Case_aux c "ST_LcaseNil" | Case_aux c "ST_LcaseCons"
(* FILL IN HERE *)
].
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Hint Constructors step.
(* ###################################################################### *)
(** *** Typing *)
Definition context := partial_map ty.
(** Next we define the typing rules. These are nearly direct
transcriptions of the inference rules shown above. *)
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
(* Typing rules for proper terms *)
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- (tvar x) \in T
| T_Abs : forall Gamma x T11 T12 t12,
(extend Gamma x T11) |- t12 \in T12 ->
Gamma |- (tabs x T11 t12) \in (TArrow T11 T12)
| T_App : forall T1 T2 Gamma t1 t2,
Gamma |- t1 \in (TArrow T1 T2) ->
Gamma |- t2 \in T1 ->
Gamma |- (tapp t1 t2) \in T2
(* nats *)
| T_Nat : forall Gamma n1,
Gamma |- (tnat n1) \in TNat
| T_Succ : forall Gamma t1,
Gamma |- t1 \in TNat ->
Gamma |- (tsucc t1) \in TNat
| T_Pred : forall Gamma t1,
Gamma |- t1 \in TNat ->
Gamma |- (tpred t1) \in TNat
| T_Mult : forall Gamma t1 t2,
Gamma |- t1 \in TNat ->
Gamma |- t2 \in TNat ->
Gamma |- (tmult t1 t2) \in TNat
| T_If0 : forall Gamma t1 t2 t3 T1,
Gamma |- t1 \in TNat ->
Gamma |- t2 \in T1 ->
Gamma |- t3 \in T1 ->
Gamma |- (tif0 t1 t2 t3) \in T1
(* pairs *)
| T_Pair : forall Gamma t1 t2 T1 T2,
Gamma |- t1 \in T1 ->
Gamma |- t2 \in T2 ->
Gamma |- (tpair t1 t2) \in (TProd T1 T2)
| T_Fst : forall Gamma t T1 T2,
Gamma |- t \in (TProd T1 T2) ->
Gamma |- (tfst t) \in T1
| T_Snd : forall Gamma t T1 T2,
Gamma |- t \in (TProd T1 T2) ->
Gamma |- (tsnd t) \in T2
(* unit *)
| T_Unit : forall Gamma,
Gamma |- tunit \in TUnit
(* let *)
(* FILL IN HERE *)
(* sums *)
| T_Inl : forall Gamma t1 T1 T2,
Gamma |- t1 \in T1 ->
Gamma |- (tinl T2 t1) \in (TSum T1 T2)
| T_Inr : forall Gamma t2 T1 T2,
Gamma |- t2 \in T2 ->
Gamma |- (tinr T1 t2) \in (TSum T1 T2)
| T_Case : forall Gamma t0 x1 T1 t1 x2 T2 t2 T,
Gamma |- t0 \in (TSum T1 T2) ->
(extend Gamma x1 T1) |- t1 \in T ->
(extend Gamma x2 T2) |- t2 \in T ->
Gamma |- (tcase t0 x1 t1 x2 t2) \in T
(* lists *)
| T_Nil : forall Gamma T,
Gamma |- (tnil T) \in (TList T)
| T_Cons : forall Gamma t1 t2 T1,
Gamma |- t1 \in T1 ->
Gamma |- t2 \in (TList T1) ->
Gamma |- (tcons t1 t2) \in (TList T1)
| T_Lcase : forall Gamma t1 T1 t2 x1 x2 t3 T2,
Gamma |- t1 \in (TList T1) ->
Gamma |- t2 \in T2 ->
(extend (extend Gamma x2 (TList T1)) x1 T1) |- t3 \in T2 ->
Gamma |- (tlcase t1 t2 x1 x2 t3) \in T2
(* fix *)
(* FILL IN HERE *)
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type.
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs" | Case_aux c "T_App"
| Case_aux c "T_Nat" | Case_aux c "T_Succ" | Case_aux c "T_Pred"
| Case_aux c "T_Mult" | Case_aux c "T_If0"
| Case_aux c "T_Pair" | Case_aux c "T_Fst" | Case_aux c "T_Snd"
| Case_aux c "T_Unit"
(* let *)
(* FILL IN HERE *)
| Case_aux c "T_Inl" | Case_aux c "T_Inr" | Case_aux c "T_Case"
| Case_aux c "T_Nil" | Case_aux c "T_Cons" | Case_aux c "T_Lcase"
(* fix *)
(* FILL IN HERE *)
].
(* ###################################################################### *)
(** ** Examples *)
(** This section presents formalized versions of the examples from
above (plus several more). The ones at the beginning focus on
specific features; you can use these to make sure your definition
of a given feature is reasonable before moving on to extending the
proofs later in the file with the cases relating to this feature.
The later examples require all the features together, so you'll
need to come back to these when you've got all the definitions
filled in. *)
Module Examples.
(** *** Preliminaries *)
(** First, let's define a few variable names: *)
Notation a := (Id 0).
Notation f := (Id 1).
Notation g := (Id 2).
Notation l := (Id 3).
Notation k := (Id 6).
Notation i1 := (Id 7).
Notation i2 := (Id 8).
Notation x := (Id 9).
Notation y := (Id 10).
Notation processSum := (Id 11).
Notation n := (Id 12).
Notation eq := (Id 13).
Notation m := (Id 14).
Notation evenodd := (Id 15).
Notation even := (Id 16).
Notation odd := (Id 17).
Notation eo := (Id 18).
(** Next, a bit of Coq hackery to automate searching for typing
derivations. You don't need to understand this bit in detail --
just have a look over it so that you'll know what to look for if
you ever find yourself needing to make custom extensions to
[auto].
The following [Hint] declarations say that, whenever [auto]
arrives at a goal of the form [(Gamma |- (tapp e1 e1) \in T)], it
should consider [eapply T_App], leaving an existential variable
for the middle type T1, and similar for [lcase]. That variable
will then be filled in during the search for type derivations for
[e1] and [e2]. We also include a hint to "try harder" when
solving equality goals; this is useful to automate uses of
[T_Var] (which includes an equality as a precondition). *)
Hint Extern 2 (has_type _ (tapp _ _) _) =>
eapply T_App; auto.
(* You'll want to uncomment the following line once
you've defined the [T_Lcase] constructor for the typing
relation: *)
(*
Hint Extern 2 (has_type _ (tlcase _ _ _ _ _) _) =>
eapply T_Lcase; auto.
*)
Hint Extern 2 (_ = _) => compute; reflexivity.
(** *** Numbers *)
Module Numtest.
(* if0 (pred (succ (pred (2 * 0))) then 5 else 6 *)
Definition test :=
tif0
(tpred
(tsucc
(tpred
(tmult
(tnat 2)
(tnat 0)))))
(tnat 5)
(tnat 6).
(** Remove the comment braces once you've implemented enough of the
definitions that you think this should work. *)
(*
Example typechecks :
(@empty ty) |- test \in TNat.
Proof.
unfold test.
(* This typing derivation is quite deep, so we need to increase the
max search depth of [auto] from the default 5 to 10. *)
auto 10.
Qed.
Example numtest_reduces :
test ==>* tnat 5.
Proof.
unfold test. normalize.
Qed.
*)
End Numtest.
(** *** Products *)
Module Prodtest.
(* ((5,6),7).fst.snd *)
Definition test :=
tsnd
(tfst
(tpair
(tpair
(tnat 5)
(tnat 6))
(tnat 7))).
(*
Example typechecks :
(@empty ty) |- test \in TNat.
Proof. unfold test. eauto 15. Qed.
Example reduces :
test ==>* tnat 6.
Proof. unfold test. normalize. Qed.
*)
End Prodtest.
(** *** [let] *)
Module LetTest.
(* let x = pred 6 in succ x *)
Definition test :=
tlet
x
(tpred (tnat 6))
(tsucc (tvar x)).
(*
Example typechecks :
(@empty ty) |- test \in TNat.
Proof. unfold test. eauto 15. Qed.
Example reduces :
test ==>* tnat 6.
Proof. unfold test. normalize. Qed.
*)
End LetTest.
(** *** Sums *)
Module Sumtest1.
(* case (inl Nat 5) of
inl x => x
| inr y => y *)
Definition test :=
tcase (tinl TNat (tnat 5))
x (tvar x)
y (tvar y).
(*
Example typechecks :
(@empty ty) |- test \in TNat.
Proof. unfold test. eauto 15. Qed.
Example reduces :
test ==>* (tnat 5).
Proof. unfold test. normalize. Qed.
*)
End Sumtest1.
Module Sumtest2.
(* let processSum =
\x:Nat+Nat.
case x of
inl n => n
inr n => if0 n then 1 else 0 in
(processSum (inl Nat 5), processSum (inr Nat 5)) *)
Definition test :=
tlet
processSum
(tabs x (TSum TNat TNat)
(tcase (tvar x)
n (tvar n)
n (tif0 (tvar n) (tnat 1) (tnat 0))))
(tpair
(tapp (tvar processSum) (tinl TNat (tnat 5)))
(tapp (tvar processSum) (tinr TNat (tnat 5)))).
(*
Example typechecks :
(@empty ty) |- test \in (TProd TNat TNat).
Proof. unfold test. eauto 15. Qed.
Example reduces :
test ==>* (tpair (tnat 5) (tnat 0)).
Proof. unfold test. normalize. Qed.
*)
End Sumtest2.
(** *** Lists *)
Module ListTest.
(* let l = cons 5 (cons 6 (nil Nat)) in
lcase l of
nil => 0
| x::y => x*x *)
Definition test :=
tlet l
(tcons (tnat 5) (tcons (tnat 6) (tnil TNat)))
(tlcase (tvar l)
(tnat 0)
x y (tmult (tvar x) (tvar x))).
(*
Example typechecks :
(@empty ty) |- test \in TNat.
Proof. unfold test. eauto 20. Qed.
Example reduces :
test ==>* (tnat 25).
Proof. unfold test. normalize. Qed.
*)
End ListTest.
(** *** [fix] *)
Module FixTest1.
(* fact := fix
(\f:nat->nat.
\a:nat.
if a=0 then 1 else a * (f (pred a))) *)
Definition fact :=
tfix
(tabs f (TArrow TNat TNat)
(tabs a TNat
(tif0
(tvar a)
(tnat 1)
(tmult
(tvar a)
(tapp (tvar f) (tpred (tvar a))))))).
(** (Warning: you may be able to typecheck [fact] but still have some
rules wrong!) *)
(*
Example fact_typechecks :
(@empty ty) |- fact \in (TArrow TNat TNat).
Proof. unfold fact. auto 10.
Qed.
*)
(*
Example fact_example:
(tapp fact (tnat 4)) ==>* (tnat 24).
Proof. unfold fact. normalize. Qed.
*)
End FixTest1.
Module FixTest2.
(* map :=
\g:nat->nat.
fix
(\f:[nat]->[nat].
\l:[nat].
case l of
| [] -> []
| x::l -> (g x)::(f l)) *)
Definition map :=
tabs g (TArrow TNat TNat)
(tfix
(tabs f (TArrow (TList TNat) (TList TNat))
(tabs l (TList TNat)
(tlcase (tvar l)
(tnil TNat)
a l (tcons (tapp (tvar g) (tvar a))
(tapp (tvar f) (tvar l))))))).
(*
(* Make sure you've uncommented the last [Hint Extern] above... *)
Example map_typechecks :
empty |- map \in
(TArrow (TArrow TNat TNat)
(TArrow (TList TNat)
(TList TNat))).
Proof. unfold map. auto 10. Qed.
Example map_example :
tapp (tapp map (tabs a TNat (tsucc (tvar a))))
(tcons (tnat 1) (tcons (tnat 2) (tnil TNat)))
==>* (tcons (tnat 2) (tcons (tnat 3) (tnil TNat))).
Proof. unfold map. normalize. Qed.
*)
End FixTest2.
Module FixTest3.
(* equal =
fix
(\eq:Nat->Nat->Bool.
\m:Nat. \n:Nat.
if0 m then (if0 n then 1 else 0)
else if0 n then 0
else eq (pred m) (pred n)) *)
Definition equal :=
tfix
(tabs eq (TArrow TNat (TArrow TNat TNat))
(tabs m TNat
(tabs n TNat
(tif0 (tvar m)
(tif0 (tvar n) (tnat 1) (tnat 0))
(tif0 (tvar n)
(tnat 0)
(tapp (tapp (tvar eq)
(tpred (tvar m)))
(tpred (tvar n)))))))).
(*
Example equal_typechecks :
(@empty ty) |- equal \in (TArrow TNat (TArrow TNat TNat)).
Proof. unfold equal. auto 10.
Qed.
*)
(*
Example equal_example1:
(tapp (tapp equal (tnat 4)) (tnat 4)) ==>* (tnat 1).
Proof. unfold equal. normalize. Qed.
*)
(*
Example equal_example2:
(tapp (tapp equal (tnat 4)) (tnat 5)) ==>* (tnat 0).
Proof. unfold equal. normalize. Qed.
*)
End FixTest3.
Module FixTest4.
(* let evenodd =
fix
(\eo: (Nat->Nat * Nat->Nat).
let e = \n:Nat. if0 n then 1 else eo.snd (pred n) in
let o = \n:Nat. if0 n then 0 else eo.fst (pred n) in
(e,o)) in
let even = evenodd.fst in
let odd = evenodd.snd in
(even 3, even 4)
*)
Definition eotest :=
tlet evenodd
(tfix
(tabs eo (TProd (TArrow TNat TNat) (TArrow TNat TNat))
(tpair
(tabs n TNat
(tif0 (tvar n)
(tnat 1)
(tapp (tsnd (tvar eo)) (tpred (tvar n)))))
(tabs n TNat
(tif0 (tvar n)
(tnat 0)
(tapp (tfst (tvar eo)) (tpred (tvar n))))))))
(tlet even (tfst (tvar evenodd))
(tlet odd (tsnd (tvar evenodd))
(tpair
(tapp (tvar even) (tnat 3))
(tapp (tvar even) (tnat 4))))).
(*
Example eotest_typechecks :
(@empty ty) |- eotest \in (TProd TNat TNat).
Proof. unfold eotest. eauto 30.
Qed.
*)
(*
Example eotest_example1:
eotest ==>* (tpair (tnat 0) (tnat 1)).
Proof. unfold eotest. normalize. Qed.
*)
End FixTest4.
End Examples.
(* ###################################################################### *)
(** ** Properties of Typing *)
(** The proofs of progress and preservation for this system are
essentially the same (though of course somewhat longer) as for the
pure simply typed lambda-calculus. *)
(* ###################################################################### *)
(** *** Progress *)
Theorem progress : forall t T,
empty |- t \in T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
(* Theorem: Suppose empty |- t : T. Then either
1. t is a value, or
2. t ==> t' for some t'.
Proof: By induction on the given typing derivation. *)
intros t T Ht.
remember (@empty ty) as Gamma.
generalize dependent HeqGamma.
has_type_cases (induction Ht) Case; intros HeqGamma; subst.
Case "T_Var".
(* The final rule in the given typing derivation cannot be [T_Var],
since it can never be the case that [empty |- x : T] (since the
context is empty). *)
inversion H.
Case "T_Abs".
(* If the [T_Abs] rule was the last used, then [t = tabs x T11 t12],
which is a value. *)
left...
Case "T_App".
(* If the last rule applied was T_App, then [t = t1 t2], and we know
from the form of the rule that
[empty |- t1 : T1 -> T2]
[empty |- t2 : T1]
By the induction hypothesis, each of t1 and t2 either is a value
or can take a step. *)
right.
destruct IHHt1; subst...
SCase "t1 is a value".
destruct IHHt2; subst...
SSCase "t2 is a value".
(* If both [t1] and [t2] are values, then we know that
[t1 = tabs x T11 t12], since abstractions are the only values
that can have an arrow type. But
[(tabs x T11 t12) t2 ==> [x:=t2]t12] by [ST_AppAbs]. *)
inversion H; subst; try (solve by inversion).
exists (subst x t2 t12)...
SSCase "t2 steps".
(* If [t1] is a value and [t2 ==> t2'], then [t1 t2 ==> t1 t2']
by [ST_App2]. *)
inversion H0 as [t2' Hstp]. exists (tapp t1 t2')...
SCase "t1 steps".
(* Finally, If [t1 ==> t1'], then [t1 t2 ==> t1' t2] by [ST_App1]. *)
inversion H as [t1' Hstp]. exists (tapp t1' t2)...
Case "T_Nat".
left...
Case "T_Succ".
right.
destruct IHHt...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
exists (tnat (S n1))...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tsucc t1')...
Case "T_Pred".
right.
destruct IHHt...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
exists (tnat (pred n1))...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tpred t1')...
Case "T_Mult".
right.
destruct IHHt1...
SCase "t1 is a value".
destruct IHHt2...
SSCase "t2 is a value".
inversion H; subst; try solve by inversion.
inversion H0; subst; try solve by inversion.
exists (tnat (mult n1 n0))...
SSCase "t2 steps".
inversion H0 as [t2' Hstp].
exists (tmult t1 t2')...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tmult t1' t2)...
Case "T_If0".
right.
destruct IHHt1...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
destruct n1 as [|n1'].
SSCase "n1=0".
exists t2...
SSCase "n1<>0".
exists t3...
SCase "t1 steps".
inversion H as [t1' H0].
exists (tif0 t1' t2 t3)...
Case "T_Pair".
destruct IHHt1...
SCase "t1 is a value".
destruct IHHt2...
SSCase "t2 steps".
right. inversion H0 as [t2' Hstp].
exists (tpair t1 t2')...
SCase "t1 steps".
right. inversion H as [t1' Hstp].
exists (tpair t1' t2)...
Case "T_Fst".
right.
destruct IHHt...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
exists v1...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tfst t1')...
Case "T_Snd".
right.
destruct IHHt...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
exists v2...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tsnd t1')...
Case "T_Unit".
left...
(* let *)
(* FILL IN HERE *)
Case "T_Inl".
destruct IHHt...
SCase "t1 steps".
right. inversion H as [t1' Hstp]...
(* exists (tinl _ t1')... *)
Case "T_Inr".
destruct IHHt...
SCase "t1 steps".
right. inversion H as [t1' Hstp]...
(* exists (tinr _ t1')... *)
Case "T_Case".
right.
destruct IHHt1...
SCase "t0 is a value".
inversion H; subst; try solve by inversion.
SSCase "t0 is inl".
exists ([x1:=v]t1)...
SSCase "t0 is inr".
exists ([x2:=v]t2)...
SCase "t0 steps".
inversion H as [t0' Hstp].
exists (tcase t0' x1 t1 x2 t2)...
Case "T_Nil".
left...
Case "T_Cons".
destruct IHHt1...
SCase "head is a value".
destruct IHHt2...
SSCase "tail steps".
right. inversion H0 as [t2' Hstp].
exists (tcons t1 t2')...
SCase "head steps".
right. inversion H as [t1' Hstp].
exists (tcons t1' t2)...
Case "T_Lcase".
right.
destruct IHHt1...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
SSCase "t1=tnil".
exists t2...
SSCase "t1=tcons v1 vl".
exists ([x2:=vl]([x1:=v1]t3))...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tlcase t1' t2 x1 x2 t3)...
(* fix *)
(* FILL IN HERE *)
Qed.
(* ###################################################################### *)
(** *** Context Invariance *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
(* nats *)
| afi_succ : forall x t,
appears_free_in x t ->
appears_free_in x (tsucc t)
| afi_pred : forall x t,
appears_free_in x t ->
appears_free_in x (tpred t)
| afi_mult1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tmult t1 t2)
| afi_mult2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tmult t1 t2)
| afi_if01 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if02 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if03 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif0 t1 t2 t3)
(* pairs *)
| afi_pair1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tpair t1 t2)
| afi_pair2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tpair t1 t2)
| afi_fst : forall x t,
appears_free_in x t ->
appears_free_in x (tfst t)
| afi_snd : forall x t,
appears_free_in x t ->
appears_free_in x (tsnd t)
(* let *)
(* FILL IN HERE *)
(* sums *)
| afi_inl : forall x t T,
appears_free_in x t ->
appears_free_in x (tinl T t)
| afi_inr : forall x t T,
appears_free_in x t ->
appears_free_in x (tinr T t)
| afi_case0 : forall x t0 x1 t1 x2 t2,
appears_free_in x t0 ->
appears_free_in x (tcase t0 x1 t1 x2 t2)
| afi_case1 : forall x t0 x1 t1 x2 t2,
x1 <> x ->
appears_free_in x t1 ->
appears_free_in x (tcase t0 x1 t1 x2 t2)
| afi_case2 : forall x t0 x1 t1 x2 t2,
x2 <> x ->
appears_free_in x t2 ->
appears_free_in x (tcase t0 x1 t1 x2 t2)
(* lists *)
| afi_cons1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tcons t1 t2)
| afi_cons2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tcons t1 t2)
| afi_lcase1 : forall x t1 t2 y1 y2 t3,
appears_free_in x t1 ->
appears_free_in x (tlcase t1 t2 y1 y2 t3)
| afi_lcase2 : forall x t1 t2 y1 y2 t3,
appears_free_in x t2 ->
appears_free_in x (tlcase t1 t2 y1 y2 t3)
| afi_lcase3 : forall x t1 t2 y1 y2 t3,
y1 <> x ->
y2 <> x ->
appears_free_in x t3 ->
appears_free_in x (tlcase t1 t2 y1 y2 t3)
(* fix *)
(* FILL IN HERE *)
.
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t S,
Gamma |- t \in S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in S.
Proof with eauto.
intros. generalize dependent Gamma'.
has_type_cases (induction H) Case;
intros Gamma' Heqv...
Case "T_Var".
apply T_Var... rewrite <- Heqv...
Case "T_Abs".
apply T_Abs... apply IHhas_type. intros y Hafi.
unfold extend.
destruct (eq_id_dec x y)...
Case "T_Mult".
apply T_Mult...
Case "T_If0".
apply T_If0...
Case "T_Pair".
apply T_Pair...
(* let *)
(* FILL IN HERE *)
Case "T_Case".
eapply T_Case...
apply IHhas_type2. intros y Hafi.
unfold extend.
destruct (eq_id_dec x1 y)...
apply IHhas_type3. intros y Hafi.
unfold extend.
destruct (eq_id_dec x2 y)...
Case "T_Cons".
apply T_Cons...
Case "T_Lcase".
eapply T_Lcase... apply IHhas_type3. intros y Hafi.
unfold extend.
destruct (eq_id_dec x1 y)...
destruct (eq_id_dec x2 y)...
Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
has_type_cases (induction Htyp) Case; inversion Hafi; subst...
Case "T_Abs".
destruct IHHtyp as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx...
(* let *)
(* FILL IN HERE *)
Case "T_Case".
SCase "left".
destruct IHHtyp2 as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx...
SCase "right".
destruct IHHtyp3 as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx...
Case "T_Lcase".
clear Htyp1 IHHtyp1 Htyp2 IHHtyp2.
destruct IHHtyp3 as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx... rewrite neq_id in Hctx...
Qed.
(* ###################################################################### *)
(** *** Substitution *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
(extend Gamma x U) |- t \in S ->
empty |- v \in U ->
Gamma |- ([x:=v]t) \in S.
Proof with eauto.
(* Theorem: If Gamma,x:U |- t : S and empty |- v : U, then
Gamma |- [x:=v]t : S. *)
intros Gamma x U v t S Htypt Htypv.
generalize dependent Gamma. generalize dependent S.
(* Proof: By induction on the term t. Most cases follow directly
from the IH, with the exception of tvar and tabs.
The former aren't automatic because we must reason about how the
variables interact. *)
t_cases (induction t) Case;
intros S Gamma Htypt; simpl; inversion Htypt; subst...
Case "tvar".
simpl. rename i into y.
(* If t = y, we know that
[empty |- v : U] and
[Gamma,x:U |- y : S]
and, by inversion, [extend Gamma x U y = Some S]. We want to
show that [Gamma |- [x:=v]y : S].
There are two cases to consider: either [x=y] or [x<>y]. *)
destruct (eq_id_dec x y).
SCase "x=y".
(* If [x = y], then we know that [U = S], and that [[x:=v]y = v].
So what we really must show is that if [empty |- v : U] then
[Gamma |- v : U]. We have already proven a more general version
of this theorem, called context invariance. *)
subst.
unfold extend in H1. rewrite eq_id in H1.
inversion H1; subst. clear H1.
eapply context_invariance...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra) as [T' HT']...
inversion HT'.
SCase "x<>y".
(* If [x <> y], then [Gamma y = Some S] and the substitution has no
effect. We can show that [Gamma |- y : S] by [T_Var]. *)
apply T_Var... unfold extend in H1. rewrite neq_id in H1...
Case "tabs".
rename i into y. rename t into T11.
(* If [t = tabs y T11 t0], then we know that
[Gamma,x:U |- tabs y T11 t0 : T11->T12]
[Gamma,x:U,y:T11 |- t0 : T12]
[empty |- v : U]
As our IH, we know that forall S Gamma,
[Gamma,x:U |- t0 : S -> Gamma |- [x:=v]t0 : S].
We can calculate that
[x:=v]t = tabs y T11 (if beq_id x y then t0 else [x:=v]t0)
And we must show that [Gamma |- [x:=v]t : T11->T12]. We know
we will do so using [T_Abs], so it remains to be shown that:
[Gamma,y:T11 |- if beq_id x y then t0 else [x:=v]t0 : T12]
We consider two cases: [x = y] and [x <> y].
*)
apply T_Abs...
destruct (eq_id_dec x y).
SCase "x=y".
(* If [x = y], then the substitution has no effect. Context
invariance shows that [Gamma,y:U,y:T11] and [Gamma,y:T11] are
equivalent. Since the former context shows that [t0 : T12], so
does the latter. *)
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
SCase "x<>y".
(* If [x <> y], then the IH and context invariance allow us to show that
[Gamma,x:U,y:T11 |- t0 : T12] =>
[Gamma,y:T11,x:U |- t0 : T12] =>
[Gamma,y:T11 |- [x:=v]t0 : T12] *)
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
(* let *)
(* FILL IN HERE *)
Case "tcase".
rename i into x1. rename i0 into x2.
eapply T_Case...
SCase "left arm".
destruct (eq_id_dec x x1).
SSCase "x = x1".
eapply context_invariance...
subst.
intros z Hafi. unfold extend.
destruct (eq_id_dec x1 z)...
SSCase "x <> x1".
apply IHt2. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec x1 z)...
subst. rewrite neq_id...
SCase "right arm".
destruct (eq_id_dec x x2).
SSCase "x = x2".
eapply context_invariance...
subst.
intros z Hafi. unfold extend.
destruct (eq_id_dec x2 z)...
SSCase "x <> x2".
apply IHt3. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec x2 z)...
subst. rewrite neq_id...
Case "tlcase".
rename i into y1. rename i0 into y2.
eapply T_Lcase...
destruct (eq_id_dec x y1).
SCase "x=y1".
simpl.
eapply context_invariance...
subst.
intros z Hafi. unfold extend.
destruct (eq_id_dec y1 z)...
SCase "x<>y1".
destruct (eq_id_dec x y2).
SSCase "x=y2".
eapply context_invariance...
subst.
intros z Hafi. unfold extend.
destruct (eq_id_dec y2 z)...
SSCase "x<>y2".
apply IHt3. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y1 z)...
subst. rewrite neq_id...
destruct (eq_id_dec y2 z)...
subst. rewrite neq_id...
Qed.
(* ###################################################################### *)
(** *** Preservation *)
Theorem preservation : forall t t' T,
empty |- t \in T ->
t ==> t' ->
empty |- t' \in T.
Proof with eauto.
intros t t' T HT.
(* Theorem: If [empty |- t : T] and [t ==> t'], then [empty |- t' : T]. *)
remember (@empty ty) as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
(* Proof: By induction on the given typing derivation. Many cases are
contradictory ([T_Var], [T_Abs]). We show just the interesting ones. *)
has_type_cases (induction HT) Case;
intros t' HeqGamma HE; subst; inversion HE; subst...
Case "T_App".
(* If the last rule used was [T_App], then [t = t1 t2], and three rules
could have been used to show [t ==> t']: [ST_App1], [ST_App2], and
[ST_AppAbs]. In the first two cases, the result follows directly from
the IH. *)
inversion HE; subst...
SCase "ST_AppAbs".
(* For the third case, suppose
[t1 = tabs x T11 t12]
and
[t2 = v2].
We must show that [empty |- [x:=v2]t12 : T2].
We know by assumption that
[empty |- tabs x T11 t12 : T1->T2]
and by inversion
[x:T1 |- t12 : T2]
We have already proven that substitution_preserves_typing and
[empty |- v2 : T1]
by assumption, so we are done. *)
apply substitution_preserves_typing with T1...
inversion HT1...
Case "T_Fst".
inversion HT...
Case "T_Snd".
inversion HT...
(* let *)
(* FILL IN HERE *)
Case "T_Case".
SCase "ST_CaseInl".
inversion HT1; subst.
eapply substitution_preserves_typing...
SCase "ST_CaseInr".
inversion HT1; subst.
eapply substitution_preserves_typing...
Case "T_Lcase".
SCase "ST_LcaseCons".
inversion HT1; subst.
apply substitution_preserves_typing with (TList T1)...
apply substitution_preserves_typing with T1...
(* fix *)
(* FILL IN HERE *)
Qed.
(** [] *)
End STLCExtended.
(* $Date: 2013-12-03 07:45:41 -0500 (Tue, 03 Dec 2013) $ *)
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
(* X_CORE_INFO = "xlconcat,Vivado 2015.2" *)
(* CHECK_LICENSE_TYPE = "design_1_microblaze_0_xlconcat_0,xlconcat,{}" *)
(* CORE_GENERATION_INFO = "design_1_microblaze_0_xlconcat_0,xlconcat,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_microblaze_0_xlconcat_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: wdata_router.v
//
// Description:
// Contains SI-side write command queue.
// Target MI-slot index is pushed onto queue when S_AVALID transfer is received.
// Queue is popped when WLAST data beat is transferred.
// W-channel input is transferred to MI-slot output selected by queue output.
//--------------------------------------------------------------------------
//
// Structure:
// wdata_router
// axic_reg_srl_fifo
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_wdata_router #
(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of all data signals
parameter integer C_NUM_MASTER_SLOTS = 1, // Number of M_* ports.
parameter integer C_SELECT_WIDTH = 1, // Width of S_ASELECT.
parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave Data Ports
input wire [C_WMESG_WIDTH-1:0] S_WMESG,
input wire S_WLAST,
input wire S_WVALID,
output wire S_WREADY,
// Master Data Ports
output wire [C_WMESG_WIDTH-1:0] M_WMESG, // Broadcast to all MI-slots
output wire M_WLAST, // Broadcast to all MI-slots
output wire [C_NUM_MASTER_SLOTS-1:0] M_WVALID, // Per MI-slot
input wire [C_NUM_MASTER_SLOTS-1:0] M_WREADY, // Per MI-slot
// Address Arbiter Ports
input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // Target MI-slot index from SI-side AW command
input wire S_AVALID,
output wire S_AREADY
);
localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32
// Decode select input to 1-hot
function [C_NUM_MASTER_SLOTS-1:0] f_decoder (
input [C_SELECT_WIDTH-1:0] sel
);
integer i;
begin
for (i=0; i<C_NUM_MASTER_SLOTS; i=i+1) begin
f_decoder[i] = (sel == i);
end
end
endfunction
//---------------------------------------------------------------------------
// Internal signal declarations
//---------------------------------------------------------------------------
wire [C_NUM_MASTER_SLOTS-1:0] m_select_hot;
wire [C_SELECT_WIDTH-1:0] m_select_enc;
wire m_avalid;
wire m_aready;
//---------------------------------------------------------------------------
// Router
//---------------------------------------------------------------------------
// SI-side write command queue
axi_data_fifo_v2_1_axic_reg_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (C_SELECT_WIDTH),
.C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG),
.C_USE_FULL (1)
)
wrouter_aw_fifo
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (S_ASELECT),
.S_VALID (S_AVALID),
.S_READY (S_AREADY),
.M_MESG (m_select_enc),
.M_VALID (m_avalid),
.M_READY (m_aready)
);
assign m_select_hot = f_decoder(m_select_enc);
// W-channel payload and LAST are broadcast to all MI-slot's W-mux
assign M_WMESG = S_WMESG;
assign M_WLAST = S_WLAST;
// Assert m_aready when last beat acknowledged by slave
assign m_aready = m_avalid & S_WVALID & S_WLAST & (|(M_WREADY & m_select_hot));
// M_WVALID is generated per MI-slot (including error handler at slot C_NUM_MASTER_SLOTS).
// The slot selected by the head of the queue (m_select_enc) is enabled.
assign M_WVALID = {C_NUM_MASTER_SLOTS{S_WVALID & m_avalid}} & m_select_hot;
// S_WREADY is muxed from the MI slot selected by the head of the queue (m_select_enc).
assign S_WREADY = m_avalid & (|(M_WREADY & m_select_hot));
endmodule
`default_nettype wire
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Parametrizable combinatorial parallel LFSR/CRC
*/
module lfsr #
(
// width of LFSR
parameter LFSR_WIDTH = 31,
// LFSR polynomial
parameter LFSR_POLY = 31'h10000001,
// LFSR configuration: "GALOIS", "FIBONACCI"
parameter LFSR_CONFIG = "FIBONACCI",
// LFSR feed forward enable
parameter LFSR_FEED_FORWARD = 0,
// bit-reverse input and output
parameter REVERSE = 0,
// width of data input
parameter DATA_WIDTH = 8,
// implementation style: "AUTO", "LOOP", "REDUCTION"
parameter STYLE = "AUTO"
)
(
input wire [DATA_WIDTH-1:0] data_in,
input wire [LFSR_WIDTH-1:0] state_in,
output wire [DATA_WIDTH-1:0] data_out,
output wire [LFSR_WIDTH-1:0] state_out
);
/*
Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR
next state computation, shifting DATA_WIDTH bits per pass through the module. Input data
is XORed with LFSR feedback path, tie data_in to zero if this is not required.
Works in two parts: statically computes a set of bit masks, then uses these bit masks to
select bits for XORing to compute the next state.
Ports:
data_in
Data bits to be shifted through the LFSR (DATA_WIDTH bits)
state_in
LFSR/CRC current state input (LFSR_WIDTH bits)
data_out
Data bits shifted out of LFSR (DATA_WIDTH bits)
state_out
LFSR/CRC next state output (LFSR_WIDTH bits)
Parameters:
LFSR_WIDTH
Specify width of LFSR/CRC register
LFSR_POLY
Specify the LFSR/CRC polynomial in hex format. For example, the polynomial
x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
would be represented as
32'h04c11db7
Note that the largest term (x^32) is suppressed. This term is generated automatically based
on LFSR_WIDTH.
LFSR_CONFIG
Specify the LFSR configuration, either Fibonacci or Galois. Fibonacci is generally used
for linear-feedback shift registers (LFSR) for pseudorandom binary sequence (PRBS) generators,
scramblers, and descrambers, while Galois is generally used for cyclic redundancy check
generators and checkers.
Fibonacci style (example for 64b66b scrambler, 0x8000000001)
DIN (LSB first)
|
V
(+)<---------------------------(+)<-----------------------------.
| ^ |
| .----. .----. .----. | .----. .----. .----. |
+->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |--'
| '----' '----' '----' '----' '----' '----'
V
DOUT
Galois style (example for CRC16, 0x8005)
,-------------------+-------------------------+----------(+)<-- DIN (MSB first)
| | | ^
| .----. .----. V .----. .----. V .----. |
`->| 0 |->| 1 |->(+)->| 2 |->...->| 14 |->(+)->| 15 |--+---> DOUT
'----' '----' '----' '----' '----'
LFSR_FEED_FORWARD
Generate feed forward instead of feed back LFSR. Enable this for PRBS checking and self-
synchronous descrambling.
Fibonacci feed-forward style (example for 64b66b descrambler, 0x8000000001)
DIN (LSB first)
|
| .----. .----. .----. .----. .----. .----.
+->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |--.
| '----' '----' '----' | '----' '----' '----' |
| V |
(+)<---------------------------(+)------------------------------'
|
V
DOUT
Galois feed-forward style
,-------------------+-------------------------+------------+--- DIN (MSB first)
| | | |
| .----. .----. V .----. .----. V .----. V
`->| 0 |->| 1 |->(+)->| 2 |->...->| 14 |->(+)->| 15 |->(+)-> DOUT
'----' '----' '----' '----' '----'
REVERSE
Bit-reverse LFSR input and output. Shifts MSB first by default, set REVERSE for LSB first.
DATA_WIDTH
Specify width of input and output data bus. The module will perform one shift per input
data bit, so if the input data bus is not required tie data_in to zero and set DATA_WIDTH
to the required number of shifts per clock cycle.
STYLE
Specify implementation style. Can be "AUTO", "LOOP", or "REDUCTION". When "AUTO"
is selected, implemenation will be "LOOP" or "REDUCTION" based on synthesis translate
directives. "REDUCTION" and "LOOP" are functionally identical, however they simulate
and synthesize differently. "REDUCTION" is implemented with a loop over a Verilog
reduction operator. "LOOP" is implemented as a doubly-nested loop with no reduction
operator. "REDUCTION" is very fast for simulation in iverilog and synthesizes well in
Quartus but synthesizes poorly in ISE, likely due to large inferred XOR gates causing
problems with the optimizer. "LOOP" synthesizes will in both ISE and Quartus. "AUTO"
will default to "REDUCTION" when simulating and "LOOP" for synthesizers that obey
synthesis translate directives.
Settings for common LFSR/CRC implementations:
Name Configuration Length Polynomial Initial value Notes
CRC16-IBM Galois, bit-reverse 16 16'h8005 16'hffff
CRC16-CCITT Galois 16 16'h1021 16'h1d0f
CRC32 Galois, bit-reverse 32 32'h04c11db7 32'hffffffff Ethernet FCS; invert final output
PRBS6 Fibonacci 6 6'h21 any
PRBS7 Fibonacci 7 7'h41 any
PRBS9 Fibonacci 9 9'h021 any ITU V.52
PRBS10 Fibonacci 10 10'h081 any ITU
PRBS11 Fibonacci 11 11'h201 any ITU O.152
PRBS15 Fibonacci, inverted 15 15'h4001 any ITU O.152
PRBS17 Fibonacci 17 17'h04001 any
PRBS20 Fibonacci 20 20'h00009 any ITU V.57
PRBS23 Fibonacci, inverted 23 23'h040001 any ITU O.151
PRBS29 Fibonacci, inverted 29 29'h08000001 any
PRBS31 Fibonacci, inverted 31 31'h10000001 any
64b66b Fibonacci, bit-reverse 58 58'h8000000001 any 10G Ethernet
128b130b Galois, bit-reverse 23 23'h210125 any PCIe gen 3
*/
reg [LFSR_WIDTH-1:0] lfsr_mask_state[LFSR_WIDTH-1:0];
reg [DATA_WIDTH-1:0] lfsr_mask_data[LFSR_WIDTH-1:0];
reg [LFSR_WIDTH-1:0] output_mask_state[DATA_WIDTH-1:0];
reg [DATA_WIDTH-1:0] output_mask_data[DATA_WIDTH-1:0];
reg [LFSR_WIDTH-1:0] state_val = 0;
reg [DATA_WIDTH-1:0] data_val = 0;
integer i, j, k;
initial begin
// init bit masks
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
lfsr_mask_state[i] = {LFSR_WIDTH{1'b0}};
lfsr_mask_state[i][i] = 1'b1;
lfsr_mask_data[i] = {DATA_WIDTH{1'b0}};
end
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
output_mask_state[i] = {LFSR_WIDTH{1'b0}};
if (i < LFSR_WIDTH) begin
output_mask_state[i][i] = 1'b1;
end
output_mask_data[i] = {DATA_WIDTH{1'b0}};
end
// simulate shift register
if (LFSR_CONFIG == "FIBONACCI") begin
// Fibonacci configuration
for (i = DATA_WIDTH-1; i >= 0; i = i - 1) begin
// determine shift in value
// current value in last FF, XOR with input data bit (MSB first)
state_val = lfsr_mask_state[LFSR_WIDTH-1];
data_val = lfsr_mask_data[LFSR_WIDTH-1];
data_val = data_val ^ (1 << i);
// add XOR inputs from correct indicies
for (j = 1; j < LFSR_WIDTH; j = j + 1) begin
if (LFSR_POLY & (1 << j)) begin
state_val = lfsr_mask_state[j-1] ^ state_val;
data_val = lfsr_mask_data[j-1] ^ data_val;
end
end
// shift
for (j = LFSR_WIDTH-1; j > 0; j = j - 1) begin
lfsr_mask_state[j] = lfsr_mask_state[j-1];
lfsr_mask_data[j] = lfsr_mask_data[j-1];
end
for (j = DATA_WIDTH-1; j > 0; j = j - 1) begin
output_mask_state[j] = output_mask_state[j-1];
output_mask_data[j] = output_mask_data[j-1];
end
output_mask_state[0] = state_val;
output_mask_data[0] = data_val;
if (LFSR_FEED_FORWARD) begin
// only shift in new input data
state_val = {LFSR_WIDTH{1'b0}};
data_val = 1 << i;
end
lfsr_mask_state[0] = state_val;
lfsr_mask_data[0] = data_val;
end
end else if (LFSR_CONFIG == "GALOIS") begin
// Galois configuration
for (i = DATA_WIDTH-1; i >= 0; i = i - 1) begin
// determine shift in value
// current value in last FF, XOR with input data bit (MSB first)
state_val = lfsr_mask_state[LFSR_WIDTH-1];
data_val = lfsr_mask_data[LFSR_WIDTH-1];
data_val = data_val ^ (1 << i);
// shift
for (j = LFSR_WIDTH-1; j > 0; j = j - 1) begin
lfsr_mask_state[j] = lfsr_mask_state[j-1];
lfsr_mask_data[j] = lfsr_mask_data[j-1];
end
for (j = DATA_WIDTH-1; j > 0; j = j - 1) begin
output_mask_state[j] = output_mask_state[j-1];
output_mask_data[j] = output_mask_data[j-1];
end
output_mask_state[0] = state_val;
output_mask_data[0] = data_val;
if (LFSR_FEED_FORWARD) begin
// only shift in new input data
state_val = {LFSR_WIDTH{1'b0}};
data_val = 1 << i;
end
lfsr_mask_state[0] = state_val;
lfsr_mask_data[0] = data_val;
// add XOR inputs at correct indicies
for (j = 1; j < LFSR_WIDTH; j = j + 1) begin
if (LFSR_POLY & (1 << j)) begin
lfsr_mask_state[j] = lfsr_mask_state[j] ^ state_val;
lfsr_mask_data[j] = lfsr_mask_data[j] ^ data_val;
end
end
end
end else begin
$error("Error: unknown configuration setting!");
$finish;
end
// reverse bits if selected
if (REVERSE) begin
// reverse order
for (i = 0; i < LFSR_WIDTH/2; i = i + 1) begin
state_val = lfsr_mask_state[i];
data_val = lfsr_mask_data[i];
lfsr_mask_state[i] = lfsr_mask_state[LFSR_WIDTH-i-1];
lfsr_mask_data[i] = lfsr_mask_data[LFSR_WIDTH-i-1];
lfsr_mask_state[LFSR_WIDTH-i-1] = state_val;
lfsr_mask_data[LFSR_WIDTH-i-1] = data_val;
end
for (i = 0; i < DATA_WIDTH/2; i = i + 1) begin
state_val = output_mask_state[i];
data_val = output_mask_data[i];
output_mask_state[i] = output_mask_state[DATA_WIDTH-i-1];
output_mask_data[i] = output_mask_data[DATA_WIDTH-i-1];
output_mask_state[DATA_WIDTH-i-1] = state_val;
output_mask_data[DATA_WIDTH-i-1] = data_val;
end
// reverse bits
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
state_val = 0;
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
state_val[j] = lfsr_mask_state[i][LFSR_WIDTH-j-1];
end
lfsr_mask_state[i] = state_val;
data_val = 0;
for (j = 0; j < DATA_WIDTH; j = j + 1) begin
data_val[j] = lfsr_mask_data[i][DATA_WIDTH-j-1];
end
lfsr_mask_data[i] = data_val;
end
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
state_val = 0;
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
state_val[j] = output_mask_state[i][LFSR_WIDTH-j-1];
end
output_mask_state[i] = state_val;
data_val = 0;
for (j = 0; j < DATA_WIDTH; j = j + 1) begin
data_val[j] = output_mask_data[i][DATA_WIDTH-j-1];
end
output_mask_data[i] = data_val;
end
end
// for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
// $display("%b %b", lfsr_mask_state[i], lfsr_mask_data[i]);
// end
end
// synthesis translate_off
`define SIMULATION
// synthesis translate_on
`ifdef SIMULATION
// "AUTO" style is "REDUCTION" for faster simulation
parameter STYLE_INT = (STYLE == "AUTO") ? "REDUCTION" : STYLE;
`else
// "AUTO" style is "LOOP" for better synthesis result
parameter STYLE_INT = (STYLE == "AUTO") ? "LOOP" : STYLE;
`endif
genvar n;
generate
if (STYLE_INT == "REDUCTION") begin
// use Verilog reduction operator
// fast in iverilog
// significantly larger than generated code with ISE (inferred wide XORs may be tripping up optimizer)
// slightly smaller than generated code with Quartus
// --> better for simulation
for (n = 0; n < LFSR_WIDTH; n = n + 1) begin : loop1
assign state_out[n] = ^{(state_in & lfsr_mask_state[n]), (data_in & lfsr_mask_data[n])};
end
for (n = 0; n < DATA_WIDTH; n = n + 1) begin : loop2
assign data_out[n] = ^{(state_in & output_mask_state[n]), (data_in & output_mask_data[n])};
end
end else if (STYLE_INT == "LOOP") begin
// use nested loops
// very slow in iverilog
// slightly smaller than generated code with ISE
// same size as generated code with Quartus
// --> better for synthesis
reg [LFSR_WIDTH-1:0] state_out_reg = 0;
reg [DATA_WIDTH-1:0] data_out_reg = 0;
assign state_out = state_out_reg;
assign data_out = data_out_reg;
always @* begin
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
state_out_reg[i] = 0;
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
if (lfsr_mask_state[i][j]) begin
state_out_reg[i] = state_out_reg[i] ^ state_in[j];
end
end
for (j = 0; j < DATA_WIDTH; j = j + 1) begin
if (lfsr_mask_data[i][j]) begin
state_out_reg[i] = state_out_reg[i] ^ data_in[j];
end
end
end
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
data_out_reg[i] = 0;
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
if (output_mask_state[i][j]) begin
data_out_reg[i] = data_out_reg[i] ^ state_in[j];
end
end
for (j = 0; j < DATA_WIDTH; j = j + 1) begin
if (output_mask_data[i][j]) begin
data_out_reg[i] = data_out_reg[i] ^ data_in[j];
end
end
end
end
end else begin
initial begin
$error("Error: unknown style setting!");
$finish;
end
end
endgenerate
endmodule
`resetall
|
`define AND 4'b0000
`define OR 4'b0001
`define ADD 4'b0010
`define SUB 4'b0110
`define SLT 4'b0111
`define NOR 4'b1100
`include "../ALU/one_bit_alu.v"
module alu (
input [3:0] op,
input signed [31:0] a, b,
output signed [31:0] z,
output zero);
wire set;
wire [30:0] carry;
one_bit_alu alu0 (.op(op), .r(z[0 ]), .a(a[0 ]), .b(b[0 ]), .cin(1'b0 ), .cout(carry[0 ]), .less(set ));
one_bit_alu alu1 (.op(op), .r(z[1 ]), .a(a[1 ]), .b(b[1 ]), .cin(carry[0 ]), .cout(carry[1 ]), .less(1'b0));
one_bit_alu alu2 (.op(op), .r(z[2 ]), .a(a[2 ]), .b(b[2 ]), .cin(carry[1 ]), .cout(carry[2 ]), .less(1'b0));
one_bit_alu alu3 (.op(op), .r(z[3 ]), .a(a[3 ]), .b(b[3 ]), .cin(carry[2 ]), .cout(carry[3 ]), .less(1'b0));
one_bit_alu alu4 (.op(op), .r(z[4 ]), .a(a[4 ]), .b(b[4 ]), .cin(carry[3 ]), .cout(carry[4 ]), .less(1'b0));
one_bit_alu alu5 (.op(op), .r(z[5 ]), .a(a[5 ]), .b(b[5 ]), .cin(carry[4 ]), .cout(carry[5 ]), .less(1'b0));
one_bit_alu alu6 (.op(op), .r(z[6 ]), .a(a[6 ]), .b(b[6 ]), .cin(carry[5 ]), .cout(carry[6 ]), .less(1'b0));
one_bit_alu alu7 (.op(op), .r(z[7 ]), .a(a[7 ]), .b(b[7 ]), .cin(carry[6 ]), .cout(carry[7 ]), .less(1'b0));
one_bit_alu alu8 (.op(op), .r(z[8 ]), .a(a[8 ]), .b(b[8 ]), .cin(carry[7 ]), .cout(carry[8 ]), .less(1'b0));
one_bit_alu alu9 (.op(op), .r(z[9 ]), .a(a[9 ]), .b(b[9 ]), .cin(carry[8 ]), .cout(carry[9 ]), .less(1'b0));
one_bit_alu alu10 (.op(op), .r(z[10]), .a(a[10]), .b(b[10]), .cin(carry[9 ]), .cout(carry[10]), .less(1'b0));
one_bit_alu alu11 (.op(op), .r(z[11]), .a(a[11]), .b(b[11]), .cin(carry[10]), .cout(carry[11]), .less(1'b0));
one_bit_alu alu12 (.op(op), .r(z[12]), .a(a[12]), .b(b[12]), .cin(carry[11]), .cout(carry[12]), .less(1'b0));
one_bit_alu alu13 (.op(op), .r(z[13]), .a(a[13]), .b(b[13]), .cin(carry[12]), .cout(carry[13]), .less(1'b0));
one_bit_alu alu14 (.op(op), .r(z[14]), .a(a[14]), .b(b[14]), .cin(carry[13]), .cout(carry[14]), .less(1'b0));
one_bit_alu alu15 (.op(op), .r(z[15]), .a(a[15]), .b(b[15]), .cin(carry[14]), .cout(carry[15]), .less(1'b0));
one_bit_alu alu16 (.op(op), .r(z[16]), .a(a[16]), .b(b[16]), .cin(carry[15]), .cout(carry[16]), .less(1'b0));
one_bit_alu alu17 (.op(op), .r(z[17]), .a(a[17]), .b(b[17]), .cin(carry[16]), .cout(carry[17]), .less(1'b0));
one_bit_alu alu18 (.op(op), .r(z[18]), .a(a[18]), .b(b[18]), .cin(carry[17]), .cout(carry[18]), .less(1'b0));
one_bit_alu alu19 (.op(op), .r(z[19]), .a(a[19]), .b(b[19]), .cin(carry[18]), .cout(carry[19]), .less(1'b0));
one_bit_alu alu20 (.op(op), .r(z[20]), .a(a[20]), .b(b[20]), .cin(carry[19]), .cout(carry[20]), .less(1'b0));
one_bit_alu alu21 (.op(op), .r(z[21]), .a(a[21]), .b(b[21]), .cin(carry[20]), .cout(carry[21]), .less(1'b0));
one_bit_alu alu22 (.op(op), .r(z[22]), .a(a[22]), .b(b[22]), .cin(carry[21]), .cout(carry[22]), .less(1'b0));
one_bit_alu alu23 (.op(op), .r(z[23]), .a(a[23]), .b(b[23]), .cin(carry[22]), .cout(carry[23]), .less(1'b0));
one_bit_alu alu24 (.op(op), .r(z[24]), .a(a[24]), .b(b[24]), .cin(carry[23]), .cout(carry[24]), .less(1'b0));
one_bit_alu alu25 (.op(op), .r(z[25]), .a(a[25]), .b(b[25]), .cin(carry[24]), .cout(carry[25]), .less(1'b0));
one_bit_alu alu26 (.op(op), .r(z[26]), .a(a[26]), .b(b[26]), .cin(carry[25]), .cout(carry[26]), .less(1'b0));
one_bit_alu alu27 (.op(op), .r(z[27]), .a(a[27]), .b(b[27]), .cin(carry[26]), .cout(carry[27]), .less(1'b0));
one_bit_alu alu28 (.op(op), .r(z[28]), .a(a[28]), .b(b[28]), .cin(carry[27]), .cout(carry[28]), .less(1'b0));
one_bit_alu alu29 (.op(op), .r(z[29]), .a(a[29]), .b(b[29]), .cin(carry[28]), .cout(carry[29]), .less(1'b0));
one_bit_alu alu30 (.op(op), .r(z[30]), .a(a[30]), .b(b[30]), .cin(carry[29]), .cout(carry[30]), .less(1'b0));
one_bit_alu alu31 (.op(op), .r(z[31]), .a(a[31]), .b(b[31]), .cin(carry[30]), .set (set ), .less(1'b0));
nor (zero, z[0 ], z[1 ], z[2 ], z[3 ], z[4 ], z[5 ], z[6 ], z[7 ], z[8 ], z[9 ],
z[10], z[11], z[12], z[13], z[14], z[15], z[16], z[17], z[18], z[19],
z[20], z[21], z[22], z[23], z[24], z[25], z[26], z[27], z[28], z[29],
z[30], z[31]);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO0P_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__LSBUFISO0P_FUNCTIONAL_PP_V
/**
* lsbufiso0p: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__lsbufiso0p (
X ,
SLEEP ,
A ,
DESTPWR,
VPWR ,
VGND ,
DESTVPB,
VPB ,
VNB
);
// Module ports
output X ;
input SLEEP ;
input A ;
input DESTPWR;
input VPWR ;
input VGND ;
input DESTVPB;
input VPB ;
input VNB ;
// Local signals
wire sleepb ;
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_sleepb;
wire and0_out_X ;
// Name Output Other arguments
not not0 (sleepb , SLEEP );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_sleepb, sleepb, DESTPWR, VGND );
and and0 (and0_out_X , pwrgood_pp1_out_sleepb, pwrgood_pp0_out_A);
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp2 (X , and0_out_X, DESTPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO0P_FUNCTIONAL_PP_V |
`default_nettype none
module prioenc #(
parameter REQ_LEN = 4,
parameter GRANT_LEN = 2
)
(
input wire [REQ_LEN-1:0] in,
output reg [GRANT_LEN-1:0] out,
output reg en
);
integer i;
always @ (*) begin
en = 0;
out = 0;
for (i = REQ_LEN-1 ; i >= 0 ; i = i - 1) begin
if (~in[i]) begin
out = i;
en = 1;
end
end
end
endmodule
module maskunit #(
parameter REQ_LEN = 4,
parameter GRANT_LEN = 2
)
(
input wire [GRANT_LEN-1:0] mask,
input wire [REQ_LEN-1:0] in,
output reg [REQ_LEN-1:0] out
);
integer i;
always @ (*) begin
out = 0;
for (i = 0 ; i < REQ_LEN ; i = i+1) begin
out[i] = (mask < i) ? 1'b0 : 1'b1;
end
end
endmodule
module allocateunit #(
parameter REQ_LEN = 4,
parameter GRANT_LEN = 2
)
(
input wire [REQ_LEN-1:0] busy,
output wire en1,
output wire en2,
output wire [GRANT_LEN-1:0] free_ent1,
output wire [GRANT_LEN-1:0] free_ent2,
input wire [1:0] reqnum,
output wire allocatable
);
wire [REQ_LEN-1:0] busy_msk;
prioenc #(REQ_LEN, GRANT_LEN) p1
(
.in(busy),
.out(free_ent1),
.en(en1)
);
maskunit #(REQ_LEN, GRANT_LEN) msku
(
.mask(free_ent1),
.in(busy),
.out(busy_msk)
);
prioenc #(REQ_LEN, GRANT_LEN) p2
(
.in(busy | busy_msk),
.out(free_ent2),
.en(en2)
);
assign allocatable = (reqnum > ({1'b0,en1}+{1'b0,en2})) ? 1'b0 : 1'b1;
endmodule
`default_nettype wire
|
//*****************************************************************************
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_calib_top.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:06 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
//Purpose:
// Top-level for memory physical layer (PHY) interface
// NOTES:
// 1. Need to support multiple copies of CS outputs
// 2. DFI_DRAM_CKE_DISABLE not supported
//
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_calib_top.v,v 1.1 2011/06/02 08:35:06 mishra Exp $
**$Date: 2011/06/02 08:35:06 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_calib_top.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_calib_top #
(
parameter TCQ = 100,
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter tCK = 2500, // DDR3 SDRAM clock period
parameter DDR3_VDD_OP_VOLT = "135", // Voltage mode used for DDR3
parameter CLK_PERIOD = 3333, // Internal clock period (in ps)
parameter N_CTL_LANES = 3, // # of control byte lanes in the PHY
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter PRBS_WIDTH = 8, // The PRBS sequence is 2^PRBS_WIDTH
parameter HIGHEST_LANE = 4,
parameter HIGHEST_BANK = 3,
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
// five fields, one per possible I/O bank, 4 bits in each field,
// 1 per lane data=1/ctl=0
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
// defines the byte lanes in I/O banks being used in the interface
// 1- Used, 0- Unused
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter CTL_BYTE_LANE = 8'hE4, // Control byte lane map
parameter CTL_BANK = 3'b000, // Bank used for control byte lanes
// Slot Conifg parameters
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
// DRAM bus widths
parameter BANK_WIDTH = 2, // # of bank bits
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter COL_WIDTH = 10, // column address width
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ROW_WIDTH = 14, // DRAM address bus width
parameter RANKS = 1, // # of memory ranks in the interface
parameter CS_WIDTH = 1, // # of CS# signals in the interface
parameter CKE_WIDTH = 1, // # of cke outputs
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter PER_BIT_DESKEW = "ON",
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter NUM_DQSFOUND_CAL = 1020, // # of iteration of DQSFOUND calib
parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
// DRAM mode settings
parameter AL = "0", // Additive Latency option
parameter TEST_AL = "0", // Additive Latency for internal use
parameter ADDR_CMD_MODE = "1T", // ADDR/CTRL timing: "2T", "1T"
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter nCL = 5, // Read CAS latency (in clk cyc)
parameter nCWL = 5, // Write CAS latency (in clk cyc)
parameter tRFC = 110000, // Refresh-to-command delay
parameter tREFI = 7800000, // pS Refresh-to-Refresh delay
parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter RTT_NOM = "60", // ODT Nominal termination value
parameter RTT_WR = "60", // ODT Write termination value
parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA
// 1 - ODT output from FPGA
parameter WRLVL = "OFF", // Enable write leveling
parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly
parameter POC_USE_METASTABLE_SAMP = "FALSE",
// Simulation /debug options
parameter SIM_INIT_OPTION = "NONE", // Performs all initialization steps
parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps
parameter CKE_ODT_AUX = "FALSE",
parameter IDELAY_ADJ = "ON",
parameter FINE_PER_BIT = "ON",
parameter CENTER_COMP_MODE = "ON",
parameter PI_VAL_ADJ = "ON",
parameter TAPSPERKCLK = 56,
parameter DEBUG_PORT = "OFF" // Enable debug port
)
(
input clk, // Internal (logic) clock
input rst, // Reset sync'ed to CLK
// Slot present inputs
input [7:0] slot_0_present,
input [7:0] slot_1_present,
// Hard PHY signals
// From PHY Ctrl Block
input phy_ctl_ready,
input phy_ctl_full,
input phy_cmd_full,
input phy_data_full,
// To PHY Ctrl Block
output write_calib,
output read_calib,
output calib_ctl_wren,
output calib_cmd_wren,
output [1:0] calib_seq,
output [3:0] calib_aux_out,
output [nCK_PER_CLK -1:0] calib_cke,
output [1:0] calib_odt,
output [2:0] calib_cmd,
output calib_wrdata_en,
output [1:0] calib_rank_cnt,
output [1:0] calib_cas_slot,
output [5:0] calib_data_offset_0,
output [5:0] calib_data_offset_1,
output [5:0] calib_data_offset_2,
output [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address,
output [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank,
output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n,
output [nCK_PER_CLK-1:0] phy_ras_n,
output [nCK_PER_CLK-1:0] phy_cas_n,
output [nCK_PER_CLK-1:0] phy_we_n,
output phy_reset_n,
// To hard PHY wrapper
output reg [5:0] calib_sel/* synthesis syn_maxfan = 10 */,
output reg calib_in_common/* synthesis syn_maxfan = 10 */,
output reg [HIGHEST_BANK-1:0] calib_zero_inputs/* synthesis syn_maxfan = 10 */,
output reg [HIGHEST_BANK-1:0] calib_zero_ctrl,
output phy_if_empty_def,
output reg phy_if_reset,
// output reg ck_addr_ctl_delay_done,
// From DQS Phaser_In
input pi_phaselocked,
input pi_phase_locked_all,
input pi_found_dqs,
input pi_dqs_found_all,
input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
input [5:0] pi_counter_read_val,
// To DQS Phaser_In
output [HIGHEST_BANK-1:0] pi_rst_stg1_cal,
output pi_en_stg2_f,
output pi_stg2_f_incdec,
output pi_stg2_load,
output [5:0] pi_stg2_reg_l,
// To DQ IDELAY
output idelay_ce,
output idelay_inc,
output idelay_ld,
// To DQS Phaser_Out
output [2:0] po_sel_stg2stg3 /* synthesis syn_maxfan = 3 */,
output [2:0] po_stg2_c_incdec /* synthesis syn_maxfan = 3 */,
output [2:0] po_en_stg2_c /* synthesis syn_maxfan = 3 */,
output [2:0] po_stg2_f_incdec /* synthesis syn_maxfan = 3 */,
output [2:0] po_en_stg2_f /* synthesis syn_maxfan = 3 */,
output po_counter_load_en,
input [8:0] po_counter_read_val,
// To command Phaser_Out
input phy_if_empty,
input [4:0] idelaye2_init_val,
input [5:0] oclkdelay_init_val,
input tg_err,
output rst_tg_mc,
// Write data to OUT_FIFO
output [2*nCK_PER_CLK*DQ_WIDTH-1:0]phy_wrdata,
// To CNTVALUEIN input of DQ IDELAYs for perbit de-skew
output [5*RANKS*DQ_WIDTH-1:0] dlyval_dq,
// IN_FIFO read enable during write leveling, write calibration,
// and read leveling
// Read data from hard PHY fans out to mc and calib logic
input[2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata,
// To MC
output [6*RANKS-1:0] calib_rd_data_offset_0,
output [6*RANKS-1:0] calib_rd_data_offset_1,
output [6*RANKS-1:0] calib_rd_data_offset_2,
output phy_rddata_valid,
output calib_writes,
(* max_fanout = 50 *) output reg init_calib_complete/* synthesis syn_maxfan = 10 */,
output init_wrcal_complete,
output pi_phase_locked_err,
output pi_dqsfound_err,
output wrcal_err,
input pd_out,
// input mmcm_ps_clk, //phase shift clock
// input oclkdelay_fb_clk, //Write DQS feedback clk
//phase shift clock control
output psen,
output psincdec,
input psdone,
input poc_sample_pd,
// Debug Port
output dbg_pi_phaselock_start,
output dbg_pi_dqsfound_start,
output dbg_pi_dqsfound_done,
output dbg_wrcal_start,
output dbg_wrcal_done,
output dbg_wrlvl_start,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output [255:0] dbg_phy_wrlvl,
output [5:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
// Write Calibration Logic
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output [99:0] dbg_phy_wrcal,
// Read leveling logic
output [1:0] dbg_rdlvl_start,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
// Delay control
input [11:0] device_temp,
input tempmon_sample_en,
input dbg_sel_pi_incdec,
input dbg_sel_po_incdec,
input [DQS_CNT_WIDTH:0] dbg_byte_sel,
input dbg_pi_f_inc,
input dbg_pi_f_dec,
input dbg_po_f_inc,
input dbg_po_f_stg23_sel,
input dbg_po_f_dec,
input dbg_idel_up_all,
input dbg_idel_down_all,
input dbg_idel_up_cpt,
input dbg_idel_down_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
input dbg_sel_all_idel_cpt,
output [255:0] dbg_phy_rdlvl, // Read leveling calibration
output [255:0] dbg_calib_top, // General PHY debug
output dbg_oclkdelay_calib_start,
output dbg_oclkdelay_calib_done,
output [255:0] dbg_phy_oclkdelay_cal,
output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data,
output [255:0] dbg_phy_init,
output [255:0] dbg_prbs_rdlvl,
output [255:0] dbg_dqs_found_cal,
output [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps,
output reg [DQS_CNT_WIDTH:0] byte_sel_cnt,
output [DRAM_WIDTH-1:0] fine_delay_incdec_pb, //fine_delay decreament per bit
output fine_delay_sel
);
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction
// Advance ODELAY of DQ by extra 0.25*tCK (quarter clock cycle) to center
// align DQ and DQS on writes. Round (up or down) value to nearest integer
// localparam integer SHIFT_TBY4_TAP
// = (CLK_PERIOD + (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*2)-1) /
// (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*4);
// Calculate number of slots in the system
localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0);
localparam OCAL_EN = ((SIM_CAL_OPTION == "FAST_CAL") || (tCK > 2500)) ? "OFF" : "ON";
// Different CTL_LANES value for DDR2. In DDR2 during DQS found all
// the add,ctl & data phaser out fine delays will be adjusted.
// In DDR3 only the add/ctrl lane delays will be adjusted
localparam DQS_FOUND_N_CTL_LANES = (DRAM_TYPE == "DDR3") ? N_CTL_LANES : 1;
localparam DQSFOUND_CAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && tCK > 2500)) ? "LEFT" : "RIGHT"; // IO Bank used for Memory I/F: "LEFT", "RIGHT"
localparam FIXED_VICTIM = (SIM_CAL_OPTION == "NONE") ? "FALSE" : "TRUE";
localparam VCCO_PAT_EN = 1; // Enable VCCO pattern during calibration
localparam VCCAUX_PAT_EN = 1; // Enable VCCAUX pattern during calibration
localparam ISI_PAT_EN = 1; // Enable VCCO pattern during calibration
//Per-bit deskew for higher freqency (>800Mhz)
//localparam FINE_DELAY = (tCK < 1250) ? "ON" : "OFF";
//BYPASS
localparam BYPASS_COMPLEX_RDLVL = (tCK > 2500) ? "TRUE": "FALSE"; //"TRUE";
localparam BYPASS_COMPLEX_OCAL = "TRUE";
//localparam BYPASS_COMPLEX_OCAL = ((DRAM_TYPE == "DDR2") || (nCK_PER_CLK == 2) || (OCAL_EN == "OFF")) ? "TRUE" : "FALSE";
// 8*tREFI in ps is divided by the fabric clock period in ps
// 270 fabric clock cycles is subtracted to account for PRECHARGE, WR, RD times
localparam REFRESH_TIMER = (SIM_CAL_OPTION == "NONE") ? (8*tREFI/(tCK*nCK_PER_CLK)) - 270 : 10795;
localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER);
wire [2*8*nCK_PER_CLK-1:0] prbs_seed;
//wire [2*8*nCK_PER_CLK-1:0] prbs_out;
wire [8*DQ_WIDTH-1:0] prbs_out;
wire [7:0] prbs_rise0;
wire [7:0] prbs_fall0;
wire [7:0] prbs_rise1;
wire [7:0] prbs_fall1;
wire [7:0] prbs_rise2;
wire [7:0] prbs_fall2;
wire [7:0] prbs_rise3;
wire [7:0] prbs_fall3;
//wire [2*8*nCK_PER_CLK-1:0] prbs_o;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o;
wire dqsfound_retry;
wire dqsfound_retry_done;
wire phy_rddata_en;
wire prech_done;
wire rdlvl_stg1_done;
reg rdlvl_stg1_done_r1;
wire pi_dqs_found_done;
wire rdlvl_stg1_err;
wire pi_dqs_found_err;
wire wrcal_pat_resume;
wire wrcal_resume_w;
wire rdlvl_prech_req;
wire rdlvl_last_byte_done;
wire rdlvl_stg1_start;
wire rdlvl_stg1_rank_done;
wire rdlvl_assrt_common;
wire pi_dqs_found_start;
wire pi_dqs_found_rank_done;
wire wl_sm_start;
wire wrcal_start;
wire wrcal_rd_wait;
wire wrcal_prech_req;
wire wrcal_pat_err;
wire wrcal_done;
wire wrlvl_done;
wire wrlvl_err;
wire wrlvl_start;
wire ck_addr_cmd_delay_done;
wire po_ck_addr_cmd_delay_done;
wire pi_calib_done;
wire detect_pi_found_dqs;
wire [5:0] rd_data_offset_0;
wire [5:0] rd_data_offset_1;
wire [5:0] rd_data_offset_2;
wire [6*RANKS-1:0] rd_data_offset_ranks_0;
wire [6*RANKS-1:0] rd_data_offset_ranks_1;
wire [6*RANKS-1:0] rd_data_offset_ranks_2;
wire [6*RANKS-1:0] rd_data_offset_ranks_mc_0;
wire [6*RANKS-1:0] rd_data_offset_ranks_mc_1;
wire [6*RANKS-1:0] rd_data_offset_ranks_mc_2;
wire cmd_po_stg2_f_incdec;
wire cmd_po_stg2_incdec_ddr2_c;
wire cmd_po_en_stg2_f;
wire cmd_po_en_stg2_ddr2_c;
wire cmd_po_stg2_c_incdec;
wire cmd_po_en_stg2_c;
wire po_stg2_ddr2_incdec;
wire po_en_stg2_ddr2;
wire dqs_po_stg2_f_incdec;
wire dqs_po_en_stg2_f;
wire dqs_wl_po_stg2_c_incdec;
wire wrcal_po_stg2_c_incdec;
wire dqs_wl_po_en_stg2_c;
wire wrcal_po_en_stg2_c;
wire [N_CTL_LANES-1:0] ctl_lane_cnt;
reg [N_CTL_LANES-1:0] ctl_lane_sel;
wire [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt;
wire [DQS_CNT_WIDTH:0] po_stg2_wl_cnt;
wire [DQS_CNT_WIDTH:0] po_stg2_ddr2_cnt;
wire [8:0] dqs_wl_po_stg2_reg_l;
wire dqs_wl_po_stg2_load;
wire [8:0] dqs_po_stg2_reg_l;
wire dqs_po_stg2_load;
wire dqs_po_dec_done;
wire pi_fine_dly_dec_done;
wire rdlvl_pi_stg2_f_incdec;
wire rdlvl_pi_stg2_f_en;
wire [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt;
//reg [DQS_CNT_WIDTH:0] byte_sel_cnt;
wire [3*DQS_WIDTH-1:0] wl_po_coarse_cnt;
wire [6*DQS_WIDTH-1:0] wl_po_fine_cnt;
wire phase_locked_err;
wire phy_ctl_rdy_dly;
wire idelay_ce_int;
wire idelay_inc_int;
reg idelay_ce_r1;
reg idelay_ce_r2;
reg idelay_inc_r1;
reg idelay_inc_r2 /* synthesis syn_maxfan = 30 */;
reg po_dly_req_r;
wire wrcal_read_req;
wire wrcal_act_req;
wire temp_wrcal_done;
wire tg_timer_done;
wire no_rst_tg_mc;
wire calib_complete;
reg reset_if_r1;
reg reset_if_r2;
reg reset_if_r3;
reg reset_if_r4;
reg reset_if_r5;
reg reset_if_r6;
reg reset_if_r7;
reg reset_if_r8;
reg reset_if_r9;
reg reset_if;
wire phy_if_reset_w;
wire pi_phaselock_start;
reg dbg_pi_f_inc_r;
reg dbg_pi_f_en_r;
reg dbg_sel_pi_incdec_r;
reg dbg_po_f_inc_r;
reg dbg_po_f_stg23_sel_r;
reg dbg_po_f_en_r;
reg dbg_sel_po_incdec_r;
reg tempmon_pi_f_inc_r;
reg tempmon_pi_f_en_r;
reg tempmon_sel_pi_incdec_r;
reg ck_addr_cmd_delay_done_r1;
reg ck_addr_cmd_delay_done_r2;
reg ck_addr_cmd_delay_done_r3;
reg ck_addr_cmd_delay_done_r4;
reg ck_addr_cmd_delay_done_r5;
reg ck_addr_cmd_delay_done_r6;
// wire oclk_init_delay_start;
wire oclk_prech_req;
wire oclk_calib_resume;
// wire oclk_init_delay_done;
wire [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
wire [DQS_CNT_WIDTH:0] complex_oclkdelay_calib_cnt;
wire oclkdelay_calib_start;
wire oclkdelay_calib_done;
wire complex_oclk_prech_req;
wire complex_oclk_calib_resume;
wire complex_oclkdelay_calib_start;
wire complex_oclkdelay_calib_done;
wire complex_ocal_num_samples_inc;
wire complex_ocal_num_samples_done_r;
wire [2:0] complex_ocal_rd_victim_sel;
wire complex_ocal_ref_req;
wire complex_ocal_ref_done;
wire [6*DQS_WIDTH-1:0] oclkdelay_left_edge_val;
wire [6*DQS_WIDTH-1:0] oclkdelay_right_edge_val;
wire wrlvl_final;
wire complex_wrlvl_final;
reg wrlvl_final_mux;
wire wrlvl_final_if_rst;
wire wrlvl_byte_redo;
wire wrlvl_byte_done;
wire early1_data;
wire early2_data;
//wire po_stg3_incdec;
//wire po_en_stg3;
wire po_stg23_sel;
wire po_stg23_incdec;
wire po_en_stg23;
wire complex_po_stg23_sel;
wire complex_po_stg23_incdec;
wire complex_po_en_stg23;
wire mpr_rdlvl_done;
wire mpr_rdlvl_start;
wire mpr_last_byte_done;
wire mpr_rnk_done;
wire mpr_end_if_reset;
wire mpr_rdlvl_err;
wire rdlvl_err;
wire prbs_rdlvl_start;
wire prbs_rdlvl_done;
reg prbs_rdlvl_done_r1;
wire prbs_last_byte_done;
wire prbs_rdlvl_prech_req;
wire prbs_pi_stg2_f_incdec;
wire prbs_pi_stg2_f_en;
wire complex_sample_cnt_inc;
wire complex_sample_cnt_inc_ocal;
wire [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt;
wire prbs_gen_clk_en;
wire prbs_gen_oclk_clk_en;
wire rd_data_offset_cal_done;
wire fine_adjust_done;
wire [N_CTL_LANES-1:0] fine_adjust_lane_cnt;
wire ck_po_stg2_f_indec;
wire ck_po_stg2_f_en;
wire dqs_found_prech_req;
wire tempmon_pi_f_inc;
wire tempmon_pi_f_dec;
wire tempmon_sel_pi_incdec;
wire wrcal_sanity_chk;
wire wrcal_sanity_chk_done;
wire wrlvl_done_w;
wire wrlvl_rank_done;
wire done_dqs_tap_inc;
wire [2:0] rd_victim_sel;
wire [2:0] victim_sel;
wire [DQS_CNT_WIDTH:0] victim_byte_cnt;
wire complex_wr_done;
wire complex_victim_inc;
wire reset_rd_addr;
wire read_pause;
wire complex_ocal_reset_rd_addr;
wire oclkdelay_center_calib_start;
wire poc_error;
wire prbs_ignore_first_byte;
wire prbs_ignore_last_bytes;
//stg3 tap values
// wire [6*DQS_WIDTH-1:0] oclkdelay_center_val;
//byte selection
// wire [DQS_CNT_WIDTH:0] oclkdelay_center_cnt;
//INC/DEC for stg3 taps
// wire ocal_ctr_po_stg23_sel;
// wire ocal_ctr_po_stg23_incdec;
// wire ocal_ctr_po_en_stg23;
//Write resume for DQS toggling
wire oclk_center_write_resume;
wire oclkdelay_center_calib_done;
//Write request to toggle DQS for limit module
wire lim2init_write_request;
wire lim_done;
// Bypass complex ocal
wire complex_oclkdelay_calib_start_w;
wire complex_oclkdelay_calib_done_w;
wire [2:0] complex_ocal_rd_victim_sel_w;
wire complex_wrlvl_final_w;
wire [255:0] dbg_ocd_lim;
//with MMCM phase detect logic
//wire mmcm_edge_detect_rdy; // ready for MMCM detect
//wire ktap_at_rightedge; // stg3 tap at right edge
//wire ktap_at_leftedge; // stg3 tap at left edge
//wire mmcm_tap_at_center; // indicate stg3 tap at center
//wire mmcm_ps_clkphase_ok; // ps clkphase is OK
//wire mmcm_edge_detect_done; // mmcm edge detect is done
//wire mmcm_lbclk_edges_aligned; // mmcm edge detect is done
//wire reset_mmcm; //mmcm detect logic reset per byte
// wire [255:0] dbg_phy_oclkdelay_center_cal;
//*****************************************************************************
// Assertions to check correctness of parameter values
//*****************************************************************************
// synthesis translate_off
initial
begin
if (RANKS == 0) begin
$display ("Error: Invalid RANKS parameter. Must be 1 or greater");
$finish;
end
if (phy_ctl_full == 1'b1) begin
$display ("Error: Incorrect phy_ctl_full input value in 2:1 or 4:1 mode");
$finish;
end
end
// synthesis translate_on
//***************************************************************************
// Debug
//***************************************************************************
assign dbg_pi_phaselock_start = pi_phaselock_start;
assign dbg_pi_dqsfound_start = pi_dqs_found_start;
assign dbg_pi_dqsfound_done = pi_dqs_found_done;
assign dbg_wrcal_start = wrcal_start;
assign dbg_wrcal_done = wrcal_done;
// Unused for now - use these as needed to bring up lower level signals
assign dbg_calib_top = dbg_ocd_lim;
// Write Level and write calibration debug observation ports
assign dbg_wrlvl_start = wrlvl_start;
assign dbg_wrlvl_done = wrlvl_done;
assign dbg_wrlvl_err = wrlvl_err;
// Read Level debug observation ports
assign dbg_rdlvl_start = {mpr_rdlvl_start, rdlvl_stg1_start};
assign dbg_rdlvl_done = {mpr_rdlvl_done, rdlvl_stg1_done};
assign dbg_rdlvl_err = {mpr_rdlvl_err, rdlvl_err};
assign dbg_oclkdelay_calib_done = oclkdelay_calib_done;
assign dbg_oclkdelay_calib_start = oclkdelay_calib_start;
//***************************************************************************
// Write leveling dependent signals
//***************************************************************************
assign wrcal_resume_w = (WRLVL == "ON") ? wrcal_pat_resume : 1'b0;
assign wrlvl_done_w = (WRLVL == "ON") ? wrlvl_done : 1'b1;
assign ck_addr_cmd_delay_done = (WRLVL == "ON") ? po_ck_addr_cmd_delay_done :
(po_ck_addr_cmd_delay_done
&& pi_fine_dly_dec_done) ;
generate
if((WRLVL == "ON") && (BYPASS_COMPLEX_OCAL=="FALSE")) begin: complex_oclk_calib
assign complex_oclkdelay_calib_start_w = complex_oclkdelay_calib_start;
assign complex_oclkdelay_calib_done_w = complex_oclkdelay_calib_done;
assign complex_ocal_rd_victim_sel_w = complex_ocal_rd_victim_sel;
assign complex_wrlvl_final_w = complex_wrlvl_final;
end else begin: bypass_complex_ocal
assign complex_oclkdelay_calib_start_w = 1'b0;
assign complex_oclkdelay_calib_done_w = prbs_rdlvl_done;
assign complex_ocal_rd_victim_sel_w = 'd0;
assign complex_wrlvl_final_w = 1'b0;
end
endgenerate
generate
genvar i;
for (i = 0; i <= 2; i = i+1) begin : bankwise_signal
assign po_sel_stg2stg3[i] = ((ck_addr_cmd_delay_done && ~oclkdelay_calib_done && mpr_rdlvl_done) ? po_stg23_sel :
(complex_oclkdelay_calib_start_w&&~complex_oclkdelay_calib_done_w? po_stg23_sel : 1'b0 )
// (~oclkdelay_center_calib_done? ocal_ctr_po_stg23_sel:1'b0))
) | dbg_po_f_stg23_sel_r;
assign po_stg2_c_incdec[i] = cmd_po_stg2_c_incdec ||
cmd_po_stg2_incdec_ddr2_c ||
dqs_wl_po_stg2_c_incdec;
assign po_en_stg2_c[i] = cmd_po_en_stg2_c ||
cmd_po_en_stg2_ddr2_c ||
dqs_wl_po_en_stg2_c;
assign po_stg2_f_incdec[i] = dqs_po_stg2_f_incdec ||
cmd_po_stg2_f_incdec ||
//po_stg3_incdec ||
ck_po_stg2_f_indec ||
po_stg23_incdec ||
// complex_po_stg23_incdec ||
// ocal_ctr_po_stg23_incdec ||
dbg_po_f_inc_r;
assign po_en_stg2_f[i] = dqs_po_en_stg2_f ||
cmd_po_en_stg2_f ||
//po_en_stg3 ||
ck_po_stg2_f_en ||
po_en_stg23 ||
// complex_po_en_stg23 ||
// ocal_ctr_po_en_stg23 ||
dbg_po_f_en_r;
end
endgenerate
assign pi_stg2_f_incdec = (dbg_pi_f_inc_r | rdlvl_pi_stg2_f_incdec | prbs_pi_stg2_f_incdec | tempmon_pi_f_inc_r);
assign pi_en_stg2_f = (dbg_pi_f_en_r | rdlvl_pi_stg2_f_en | prbs_pi_stg2_f_en | tempmon_pi_f_en_r);
assign idelay_ce = idelay_ce_r2;
assign idelay_inc = idelay_inc_r2;
assign po_counter_load_en = 1'b0;
assign complex_oclkdelay_calib_cnt = oclkdelay_calib_cnt;
assign complex_oclk_calib_resume = oclk_calib_resume;
assign complex_ocal_ref_req = oclk_prech_req;
// Added single stage flop to meet timing
always @(posedge clk)
init_calib_complete <= calib_complete;
assign calib_rd_data_offset_0 = rd_data_offset_ranks_mc_0;
assign calib_rd_data_offset_1 = rd_data_offset_ranks_mc_1;
assign calib_rd_data_offset_2 = rd_data_offset_ranks_mc_2;
//***************************************************************************
// Hard PHY signals
//***************************************************************************
assign pi_phase_locked_err = phase_locked_err;
assign pi_dqsfound_err = pi_dqs_found_err;
assign wrcal_err = wrcal_pat_err;
assign rst_tg_mc = 1'b0;
//Restart WRLVL after oclkdealy cal
always @ (posedge clk)
wrlvl_final_mux <= #TCQ complex_oclkdelay_calib_start_w? complex_wrlvl_final_w: wrlvl_final;
always @(posedge clk)
phy_if_reset <= #TCQ (phy_if_reset_w | mpr_end_if_reset |
reset_if | wrlvl_final_if_rst);
//***************************************************************************
// Phaser_IN inc dec control for debug
//***************************************************************************
always @(posedge clk) begin
if (rst) begin
dbg_pi_f_inc_r <= #TCQ 1'b0;
dbg_pi_f_en_r <= #TCQ 1'b0;
dbg_sel_pi_incdec_r <= #TCQ 1'b0;
end else begin
dbg_pi_f_inc_r <= #TCQ dbg_pi_f_inc;
dbg_pi_f_en_r <= #TCQ (dbg_pi_f_inc | dbg_pi_f_dec);
dbg_sel_pi_incdec_r <= #TCQ dbg_sel_pi_incdec;
end
end
//***************************************************************************
// Phaser_OUT inc dec control for debug
//***************************************************************************
always @(posedge clk) begin
if (rst) begin
dbg_po_f_inc_r <= #TCQ 1'b0;
dbg_po_f_stg23_sel_r<= #TCQ 1'b0;
dbg_po_f_en_r <= #TCQ 1'b0;
dbg_sel_po_incdec_r <= #TCQ 1'b0;
end else begin
dbg_po_f_inc_r <= #TCQ dbg_po_f_inc;
dbg_po_f_stg23_sel_r<= #TCQ dbg_po_f_stg23_sel;
dbg_po_f_en_r <= #TCQ (dbg_po_f_inc | dbg_po_f_dec);
dbg_sel_po_incdec_r <= #TCQ dbg_sel_po_incdec;
end
end
//***************************************************************************
// Phaser_IN inc dec control for temperature tracking
//***************************************************************************
always @(posedge clk) begin
if (rst) begin
tempmon_pi_f_inc_r <= #TCQ 1'b0;
tempmon_pi_f_en_r <= #TCQ 1'b0;
tempmon_sel_pi_incdec_r <= #TCQ 1'b0;
end else begin
tempmon_pi_f_inc_r <= #TCQ tempmon_pi_f_inc;
tempmon_pi_f_en_r <= #TCQ (tempmon_pi_f_inc | tempmon_pi_f_dec);
tempmon_sel_pi_incdec_r <= #TCQ tempmon_sel_pi_incdec;
end
end
//***************************************************************************
// OCLKDELAY calibration signals
//***************************************************************************
// Minimum of 5 'clk' cycles required between assertion of po_sel_stg2stg3
// and increment/decrement of Phaser_Out stage 3 delay
always @(posedge clk) begin
ck_addr_cmd_delay_done_r1 <= #TCQ ck_addr_cmd_delay_done;
ck_addr_cmd_delay_done_r2 <= #TCQ ck_addr_cmd_delay_done_r1;
ck_addr_cmd_delay_done_r3 <= #TCQ ck_addr_cmd_delay_done_r2;
ck_addr_cmd_delay_done_r4 <= #TCQ ck_addr_cmd_delay_done_r3;
ck_addr_cmd_delay_done_r5 <= #TCQ ck_addr_cmd_delay_done_r4;
ck_addr_cmd_delay_done_r6 <= #TCQ ck_addr_cmd_delay_done_r5;
end
//***************************************************************************
// MUX select logic to select current byte undergoing calibration
// Use DQS_CAL_MAP to determine the correlation between the physical
// byte numbering, and the byte numbering within the hard PHY
//***************************************************************************
generate
if (tCK > 2500) begin: gen_byte_sel_div2
always @(posedge clk) begin
if (rst) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ck_addr_cmd_delay_done) begin
ctl_lane_sel <= #TCQ ctl_lane_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~fine_adjust_done && rd_data_offset_cal_done) begin
if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ fine_adjust_lane_cnt;
calib_in_common <= #TCQ 1'b0;
end
end else if (~pi_calib_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~pi_dqs_found_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~wrlvl_done_w) begin
if (SIM_CAL_OPTION != "FAST_CAL") begin
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
calib_in_common <= #TCQ 1'b0;
end else begin
// Special case for FAST_CAL simulation only to ensure that
// calib_in_common isn't asserted too soon
if (!phy_ctl_rdy_dly) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else begin
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
calib_in_common <= #TCQ 1'b1;
end
end
end else if (~mpr_rdlvl_done) begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~oclkdelay_calib_done) begin
byte_sel_cnt <= #TCQ oclkdelay_calib_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~rdlvl_stg1_done && pi_calib_done) begin
if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b1;
end else begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end
end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin
byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~complex_oclkdelay_calib_done_w && prbs_rdlvl_done) begin
byte_sel_cnt <= #TCQ complex_oclkdelay_calib_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~wrcal_done) begin
byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin
byte_sel_cnt <= #TCQ dbg_byte_sel;
calib_in_common <= #TCQ 1'b0;
end else if (tempmon_sel_pi_incdec) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end
end
end else begin: gen_byte_sel_div1
always @(posedge clk) begin
if (rst) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ck_addr_cmd_delay_done) begin
ctl_lane_sel <= #TCQ ctl_lane_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~fine_adjust_done && rd_data_offset_cal_done) begin
if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ fine_adjust_lane_cnt;
calib_in_common <= #TCQ 1'b0;
end
end else if (~pi_calib_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~pi_dqs_found_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~wrlvl_done_w) begin
if (SIM_CAL_OPTION != "FAST_CAL") begin
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
calib_in_common <= #TCQ 1'b0;
end else begin
// Special case for FAST_CAL simulation only to ensure that
// calib_in_common isn't asserted too soon
if (!phy_ctl_rdy_dly) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else begin
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
calib_in_common <= #TCQ 1'b1;
end
end
end else if (~mpr_rdlvl_done) begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~oclkdelay_calib_done) begin
byte_sel_cnt <= #TCQ oclkdelay_calib_cnt;
calib_in_common <= #TCQ 1'b0;
end else if ((~wrcal_done)&& (DRAM_TYPE == "DDR3")) begin
byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~rdlvl_stg1_done && pi_calib_done) begin
if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b1;
end else begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end
end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin
byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~complex_oclkdelay_calib_done_w && prbs_rdlvl_done) begin
byte_sel_cnt <= #TCQ complex_oclkdelay_calib_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin
byte_sel_cnt <= #TCQ dbg_byte_sel;
calib_in_common <= #TCQ 1'b0;
end else if (tempmon_sel_pi_incdec) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end
end
end
endgenerate
// verilint STARC-2.2.3.3 off
always @(posedge clk) begin
if (rst || (calib_complete && ~ (dbg_sel_pi_incdec_r|dbg_sel_po_incdec_r|tempmon_sel_pi_incdec) )) begin
calib_sel <= #TCQ 6'b000100;
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
if (~dqs_po_dec_done && (WRLVL != "ON"))
//if (~dqs_po_dec_done && ((SIM_CAL_OPTION == "FAST_CAL") ||(WRLVL != "ON")))
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}};
else
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if (~ck_addr_cmd_delay_done || (~fine_adjust_done && rd_data_offset_cal_done)) begin
if(WRLVL =="ON") begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ CTL_BYTE_LANE[(ctl_lane_sel*2)+:2];
calib_sel[5:3] <= #TCQ CTL_BANK;
if (|pi_rst_stg1_cal) begin
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
end else begin
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
calib_zero_inputs[1*CTL_BANK] <= #TCQ 1'b0;
end
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else begin // if (WRLVL =="ON")
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
if(~ck_addr_cmd_delay_done)
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
else
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}};
end // else: !if(WRLVL =="ON")
end else if ((~wrlvl_done_w) && (SIM_CAL_OPTION == "FAST_CAL")) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if (~rdlvl_stg1_done && (SIM_CAL_OPTION == "FAST_CAL") &&
rdlvl_assrt_common) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if (tempmon_sel_pi_incdec) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
if (~calib_in_common) begin
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
calib_zero_inputs[(1*DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3])] <= #TCQ 1'b0;
end else
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
end
end
// verilint STARC-2.2.3.3 on
// Logic to reset IN_FIFO flags to account for the possibility that
// one or more PHASER_IN's have not correctly found the DQS preamble
// If this happens, we can still complete read leveling, but the # of
// words written into the IN_FIFO's may be an odd #, so that if the
// IN_FIFO is used in 2:1 mode ("8:4 mode"), there may be a "half" word
// of data left that can only be flushed out by reseting the IN_FIFO
always @(posedge clk) begin
rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done;
prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done;
reset_if_r1 <= #TCQ reset_if;
reset_if_r2 <= #TCQ reset_if_r1;
reset_if_r3 <= #TCQ reset_if_r2;
reset_if_r4 <= #TCQ reset_if_r3;
reset_if_r5 <= #TCQ reset_if_r4;
reset_if_r6 <= #TCQ reset_if_r5;
reset_if_r7 <= #TCQ reset_if_r6;
reset_if_r8 <= #TCQ reset_if_r7;
reset_if_r9 <= #TCQ reset_if_r8;
end
always @(posedge clk) begin
if (rst || reset_if_r9)
reset_if <= #TCQ 1'b0;
else if ((rdlvl_stg1_done && ~rdlvl_stg1_done_r1) ||
(prbs_rdlvl_done && ~prbs_rdlvl_done_r1))
reset_if <= #TCQ 1'b1;
end
assign phy_if_empty_def = 1'b0;
// DQ IDELAY tap inc and ce signals registered to control calib_in_common
// signal during read leveling in FAST_CAL mode. The calib_in_common signal
// is only asserted for IDELAY tap increments not Phaser_IN tap increments
// in FAST_CAL mode. For Phaser_IN tap increments the Phaser_IN counter load
// inputs are used.
always @(posedge clk) begin
if (rst) begin
idelay_ce_r1 <= #TCQ 1'b0;
idelay_ce_r2 <= #TCQ 1'b0;
idelay_inc_r1 <= #TCQ 1'b0;
idelay_inc_r2 <= #TCQ 1'b0;
end else begin
idelay_ce_r1 <= #TCQ idelay_ce_int;
idelay_ce_r2 <= #TCQ idelay_ce_r1;
idelay_inc_r1 <= #TCQ idelay_inc_int;
idelay_inc_r2 <= #TCQ idelay_inc_r1;
end
end
//***************************************************************************
// Delay all Outputs using Phaser_Out fine taps
//***************************************************************************
assign init_wrcal_complete = 1'b0;
//***************************************************************************
// PRBS Generator for Read Leveling Stage 1 - read window detection and
// DQS Centering
//***************************************************************************
// Assign initial seed (used for 1st data word in 8-burst sequence); use alternating 1/0 pat
assign prbs_seed = 64'h9966aa559966aa55;
// A single PRBS generator
// writes 64-bits every 4to1 fabric clock cycle and
// write 32-bits every 2to1 fabric clock cycle
// used for complex read leveling and complex oclkdealy calib
mig_7series_v2_3_ddr_prbs_gen #
(
.TCQ (TCQ),
.PRBS_WIDTH (2*8*nCK_PER_CLK),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.VCCO_PAT_EN (VCCO_PAT_EN),
.VCCAUX_PAT_EN (VCCAUX_PAT_EN),
.ISI_PAT_EN (ISI_PAT_EN),
.FIXED_VICTIM (FIXED_VICTIM)
)
u_ddr_prbs_gen
(.prbs_ignore_first_byte (prbs_ignore_first_byte),
.prbs_ignore_last_bytes (prbs_ignore_last_bytes),
.clk_i (clk),
.clk_en_i (prbs_gen_clk_en | prbs_gen_oclk_clk_en),
.rst_i (rst),
.prbs_o (prbs_out),
.prbs_seed_i (prbs_seed),
.phy_if_empty (phy_if_empty),
.prbs_rdlvl_start (prbs_rdlvl_start),
.prbs_rdlvl_done (prbs_rdlvl_done),
.complex_wr_done (complex_wr_done),
.victim_sel (victim_sel),
.byte_cnt (victim_byte_cnt),
.dbg_prbs_gen (),
.reset_rd_addr (reset_rd_addr | complex_ocal_reset_rd_addr)
);
// PRBS data slice that decides the Rise0, Fall0, Rise1, Fall1,
// Rise2, Fall2, Rise3, Fall3 data
generate
if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4
assign prbs_o = prbs_out;
/*assign prbs_rise0 = prbs_out[7:0];
assign prbs_fall0 = prbs_out[15:8];
assign prbs_rise1 = prbs_out[23:16];
assign prbs_fall1 = prbs_out[31:24];
assign prbs_rise2 = prbs_out[39:32];
assign prbs_fall2 = prbs_out[47:40];
assign prbs_rise3 = prbs_out[55:48];
assign prbs_fall3 = prbs_out[63:56];
assign prbs_o = {prbs_fall3, prbs_rise3, prbs_fall2, prbs_rise2,
prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};*/
end else begin :gen_ck_per_clk2
assign prbs_o = prbs_out[4*DQ_WIDTH-1:0];
/*assign prbs_rise0 = prbs_out[7:0];
assign prbs_fall0 = prbs_out[15:8];
assign prbs_rise1 = prbs_out[23:16];
assign prbs_fall1 = prbs_out[31:24];
assign prbs_o = {prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};*/
end
endgenerate
//***************************************************************************
// Initialization / Master PHY state logic (overall control during memory
// init, timing leveling)
//***************************************************************************
mig_7series_v2_3_ddr_phy_init #
(
.tCK (tCK),
.DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT),
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.DRAM_TYPE (DRAM_TYPE),
.PRBS_WIDTH (PRBS_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.CA_MIRROR (CA_MIRROR),
.COL_WIDTH (COL_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.CS_WIDTH (CS_WIDTH),
.RANKS (RANKS),
.CKE_WIDTH (CKE_WIDTH),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.AL (AL),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.nCL (nCL),
.nCWL (nCWL),
.tRFC (tRFC),
.REFRESH_TIMER (REFRESH_TIMER),
.REFRESH_TIMER_WIDTH (REFRESH_TIMER_WIDTH),
.OUTPUT_DRV (OUTPUT_DRV),
.REG_CTRL (REG_CTRL),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.WRLVL (WRLVL),
.USE_ODT_PORT (USE_ODT_PORT),
.DDR2_DQSN_ENABLE(DDR2_DQSN_ENABLE),
.nSLOTS (nSLOTS),
.SIM_INIT_OPTION (SIM_INIT_OPTION),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.CKE_ODT_AUX (CKE_ODT_AUX),
.PRE_REV3ES (PRE_REV3ES),
.TEST_AL (TEST_AL),
.FIXED_VICTIM (FIXED_VICTIM),
.BYPASS_COMPLEX_OCAL(BYPASS_COMPLEX_OCAL)
)
u_ddr_phy_init
(
.clk (clk),
.rst (rst),
.prbs_o (prbs_o),
.ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),
.delay_incdec_done (ck_addr_cmd_delay_done),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_phaselock_start (pi_phaselock_start),
.pi_phase_locked_err (phase_locked_err),
.pi_calib_done (pi_calib_done),
.phy_if_empty (phy_if_empty),
.phy_ctl_ready (phy_ctl_ready),
.phy_ctl_full (phy_ctl_full),
.phy_cmd_full (phy_cmd_full),
.phy_data_full (phy_data_full),
.calib_ctl_wren (calib_ctl_wren),
.calib_cmd_wren (calib_cmd_wren),
.calib_wrdata_en (calib_wrdata_en),
.calib_seq (calib_seq),
.calib_aux_out (calib_aux_out),
.calib_rank_cnt (calib_rank_cnt),
.calib_cas_slot (calib_cas_slot),
.calib_data_offset_0 (calib_data_offset_0),
.calib_data_offset_1 (calib_data_offset_1),
.calib_data_offset_2 (calib_data_offset_2),
.calib_cmd (calib_cmd),
.calib_cke (calib_cke),
.calib_odt (calib_odt),
.write_calib (write_calib),
.read_calib (read_calib),
.wrlvl_done (wrlvl_done),
.wrlvl_rank_done (wrlvl_rank_done),
.wrlvl_byte_done (wrlvl_byte_done),
.wrlvl_byte_redo (wrlvl_byte_redo),
.wrlvl_final (wrlvl_final_mux),
.wrlvl_final_if_rst (wrlvl_final_if_rst),
.oclkdelay_calib_start (oclkdelay_calib_start),
.oclkdelay_calib_done (oclkdelay_calib_done),
.oclk_prech_req (oclk_prech_req),
.oclk_calib_resume (oclk_calib_resume),
.lim_wr_req (lim2init_write_request),
.lim_done (lim_done),
.complex_oclkdelay_calib_start (complex_oclkdelay_calib_start),
.complex_oclkdelay_calib_done (complex_oclkdelay_calib_done_w),
.complex_oclk_calib_resume (complex_oclk_calib_resume),
.complex_oclkdelay_calib_cnt (complex_oclkdelay_calib_cnt),
.complex_sample_cnt_inc_ocal (complex_sample_cnt_inc_ocal),
.complex_ocal_num_samples_inc (complex_ocal_num_samples_inc),
.complex_ocal_num_samples_done_r (complex_ocal_num_samples_done_r),
.complex_ocal_reset_rd_addr (complex_ocal_reset_rd_addr),
.complex_ocal_ref_req (complex_ocal_ref_req),
.complex_ocal_ref_done (complex_ocal_ref_done),
.done_dqs_tap_inc (done_dqs_tap_inc),
.wl_sm_start (wl_sm_start),
.wr_lvl_start (wrlvl_start),
.slot_0_present (slot_0_present),
.slot_1_present (slot_1_present),
.mpr_rdlvl_done (mpr_rdlvl_done),
.mpr_rdlvl_start (mpr_rdlvl_start),
.mpr_last_byte_done (mpr_last_byte_done),
.mpr_rnk_done (mpr_rnk_done),
.mpr_end_if_reset (mpr_end_if_reset),
.rdlvl_stg1_done (rdlvl_stg1_done),
.rdlvl_stg1_rank_done (rdlvl_stg1_rank_done),
.rdlvl_stg1_start (rdlvl_stg1_start),
.rdlvl_prech_req (rdlvl_prech_req),
.rdlvl_last_byte_done (rdlvl_last_byte_done),
.prbs_rdlvl_start (prbs_rdlvl_start),
.complex_wr_done (complex_wr_done),
.prbs_rdlvl_done (prbs_rdlvl_done),
.prbs_last_byte_done (prbs_last_byte_done),
.prbs_rdlvl_prech_req (prbs_rdlvl_prech_req),
.complex_victim_inc (complex_victim_inc),
.rd_victim_sel (rd_victim_sel),
.complex_ocal_rd_victim_sel (complex_ocal_rd_victim_sel),
.pi_stg2_prbs_rdlvl_cnt(pi_stg2_prbs_rdlvl_cnt),
.victim_sel (victim_sel),
.victim_byte_cnt (victim_byte_cnt),
.prbs_gen_clk_en (prbs_gen_clk_en),
.prbs_gen_oclk_clk_en (prbs_gen_oclk_clk_en),
.complex_sample_cnt_inc(complex_sample_cnt_inc),
.pi_dqs_found_start (pi_dqs_found_start),
.dqsfound_retry (dqsfound_retry),
.dqs_found_prech_req (dqs_found_prech_req),
.pi_dqs_found_rank_done(pi_dqs_found_rank_done),
.pi_dqs_found_done (pi_dqs_found_done),
.detect_pi_found_dqs (detect_pi_found_dqs),
.rd_data_offset_0 (rd_data_offset_0),
.rd_data_offset_1 (rd_data_offset_1),
.rd_data_offset_2 (rd_data_offset_2),
.rd_data_offset_ranks_0(rd_data_offset_ranks_0),
.rd_data_offset_ranks_1(rd_data_offset_ranks_1),
.rd_data_offset_ranks_2(rd_data_offset_ranks_2),
.wrcal_start (wrcal_start),
.wrcal_rd_wait (wrcal_rd_wait),
.wrcal_prech_req (wrcal_prech_req),
.wrcal_resume (wrcal_resume_w),
.wrcal_read_req (wrcal_read_req),
.wrcal_act_req (wrcal_act_req),
.wrcal_sanity_chk (wrcal_sanity_chk),
.temp_wrcal_done (temp_wrcal_done),
.wrcal_sanity_chk_done (wrcal_sanity_chk_done),
.tg_timer_done (tg_timer_done),
.no_rst_tg_mc (no_rst_tg_mc),
.wrcal_done (wrcal_done),
.prech_done (prech_done),
.calib_writes (calib_writes),
.init_calib_complete (calib_complete),
.phy_address (phy_address),
.phy_bank (phy_bank),
.phy_cas_n (phy_cas_n),
.phy_cs_n (phy_cs_n),
.phy_ras_n (phy_ras_n),
.phy_reset_n (phy_reset_n),
.phy_we_n (phy_we_n),
.phy_wrdata (phy_wrdata),
.phy_rddata_en (phy_rddata_en),
.phy_rddata_valid (phy_rddata_valid),
.dbg_phy_init (dbg_phy_init),
.read_pause (read_pause),
.reset_rd_addr (reset_rd_addr | complex_ocal_reset_rd_addr),
.oclkdelay_center_calib_start (oclkdelay_center_calib_start),
.oclk_center_write_resume (oclk_center_write_resume),
.oclkdelay_center_calib_done (oclkdelay_center_calib_done)
);
//*****************************************************************
// Write Calibration
//*****************************************************************
mig_7series_v2_3_ddr_phy_wrcal #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.SIM_CAL_OPTION (SIM_CAL_OPTION)
)
u_ddr_phy_wrcal
(
.clk (clk),
.rst (rst),
.wrcal_start (wrcal_start),
.wrcal_rd_wait (wrcal_rd_wait),
.wrcal_sanity_chk (wrcal_sanity_chk),
.dqsfound_retry_done (pi_dqs_found_done),
.dqsfound_retry (dqsfound_retry),
.wrcal_read_req (wrcal_read_req),
.wrcal_act_req (wrcal_act_req),
.phy_rddata_en (phy_rddata_en),
.wrcal_done (wrcal_done),
.wrcal_pat_err (wrcal_pat_err),
.wrcal_prech_req (wrcal_prech_req),
.temp_wrcal_done (temp_wrcal_done),
.wrcal_sanity_chk_done (wrcal_sanity_chk_done),
.prech_done (prech_done),
.rd_data (phy_rddata),
.wrcal_pat_resume (wrcal_pat_resume),
.po_stg2_wrcal_cnt (po_stg2_wrcal_cnt),
.phy_if_reset (phy_if_reset_w),
.wl_po_coarse_cnt (wl_po_coarse_cnt),
.wl_po_fine_cnt (wl_po_fine_cnt),
.wrlvl_byte_redo (wrlvl_byte_redo),
.wrlvl_byte_done (wrlvl_byte_done),
.early1_data (early1_data),
.early2_data (early2_data),
.idelay_ld (idelay_ld),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt)
);
//***************************************************************************
// Write-leveling calibration logic
//***************************************************************************
generate
if (WRLVL == "ON") begin: mb_wrlvl_inst
mig_7series_v2_3_ddr_phy_wrlvl #
(
.TCQ (TCQ),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.RANKS (1),
.CLK_PERIOD (CLK_PERIOD),
.nCK_PER_CLK (nCK_PER_CLK),
.SIM_CAL_OPTION (SIM_CAL_OPTION)
)
u_ddr_phy_wrlvl
(
.clk (clk),
.rst (rst),
.phy_ctl_ready (phy_ctl_ready),
.wr_level_start (wrlvl_start),
.wl_sm_start (wl_sm_start),
.wrlvl_byte_redo (wrlvl_byte_redo),
.wrcal_cnt (po_stg2_wrcal_cnt),
.early1_data (early1_data),
.early2_data (early2_data),
.wrlvl_final (wrlvl_final_mux),
.oclkdelay_calib_cnt (oclkdelay_calib_cnt),
.wrlvl_byte_done (wrlvl_byte_done),
.oclkdelay_calib_done (oclkdelay_calib_done),
.rd_data_rise0 (phy_rddata[DQ_WIDTH-1:0]),
.dqs_po_dec_done (dqs_po_dec_done),
.phy_ctl_rdy_dly (phy_ctl_rdy_dly),
.wr_level_done (wrlvl_done),
.wrlvl_rank_done (wrlvl_rank_done),
.done_dqs_tap_inc (done_dqs_tap_inc),
.dqs_po_stg2_f_incdec (dqs_po_stg2_f_incdec),
.dqs_po_en_stg2_f (dqs_po_en_stg2_f),
.dqs_wl_po_stg2_c_incdec (dqs_wl_po_stg2_c_incdec),
.dqs_wl_po_en_stg2_c (dqs_wl_po_en_stg2_c),
.po_counter_read_val (po_counter_read_val),
.po_stg2_wl_cnt (po_stg2_wl_cnt),
.wrlvl_err (wrlvl_err),
.wl_po_coarse_cnt (wl_po_coarse_cnt),
.wl_po_fine_cnt (wl_po_fine_cnt),
.dbg_wl_tap_cnt (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_dqs_count (),
.dbg_wl_state (),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_phy_wrlvl (dbg_phy_wrlvl)
);
mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay #
(
.TCQ (TCQ),
.tCK (tCK),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.N_CTL_LANES (N_CTL_LANES),
.SIM_CAL_OPTION(SIM_CAL_OPTION)
)
u_ddr_phy_ck_addr_cmd_delay
(
.clk (clk),
.rst (rst),
.cmd_delay_start (dqs_po_dec_done & pi_fine_dly_dec_done),
.ctl_lane_cnt (ctl_lane_cnt),
.po_stg2_f_incdec (cmd_po_stg2_f_incdec),
.po_en_stg2_f (cmd_po_en_stg2_f),
.po_stg2_c_incdec (cmd_po_stg2_c_incdec),
.po_en_stg2_c (cmd_po_en_stg2_c),
.po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done)
);
assign cmd_po_stg2_incdec_ddr2_c = 1'b0;
assign cmd_po_en_stg2_ddr2_c = 1'b0;
end else begin: mb_wrlvl_off
mig_7series_v2_3_ddr_phy_wrlvl_off_delay #
(
.TCQ (TCQ),
.tCK (tCK),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.PO_INITIAL_DLY(60),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.N_CTL_LANES (N_CTL_LANES)
)
u_phy_wrlvl_off_delay
(
.clk (clk),
.rst (rst),
.pi_fine_dly_dec_done (pi_fine_dly_dec_done),
.cmd_delay_start (phy_ctl_ready),
.ctl_lane_cnt (ctl_lane_cnt),
.po_s2_incdec_f (cmd_po_stg2_f_incdec),
.po_en_s2_f (cmd_po_en_stg2_f),
.po_s2_incdec_c (cmd_po_stg2_incdec_ddr2_c),
.po_en_s2_c (cmd_po_en_stg2_ddr2_c),
.po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done),
.po_dec_done (dqs_po_dec_done),
.phy_ctl_rdy_dly (phy_ctl_rdy_dly)
);
assign wrlvl_byte_done = 1'b1;
assign wrlvl_rank_done = 1'b1;
assign po_stg2_wl_cnt = 'h0;
assign wl_po_coarse_cnt = 'h0;
assign wl_po_fine_cnt = 'h0;
assign dbg_tap_cnt_during_wrlvl = 'h0;
assign dbg_wl_edge_detect_valid = 'h0;
assign dbg_rd_data_edge_detect = 'h0;
assign dbg_wrlvl_fine_tap_cnt = 'h0;
assign dbg_wrlvl_coarse_tap_cnt = 'h0;
assign dbg_phy_wrlvl = 'h0;
assign wrlvl_done = 1'b1;
assign wrlvl_err = 1'b0;
assign dqs_po_stg2_f_incdec = 1'b0;
assign dqs_po_en_stg2_f = 1'b0;
assign dqs_wl_po_en_stg2_c = 1'b0;
assign cmd_po_stg2_c_incdec = 1'b0;
assign dqs_wl_po_stg2_c_incdec = 1'b0;
assign cmd_po_en_stg2_c = 1'b0;
end
endgenerate
generate
if((WRLVL == "ON") && (OCAL_EN == "ON")) begin: oclk_calib
localparam SAMPCNTRWIDTH = 17;
localparam SAMPLES = (SIM_CAL_OPTION=="NONE") ? 2048 : 4;
localparam TAPCNTRWIDTH = clogb2(TAPSPERKCLK);
localparam MMCM_SAMP_WAIT = (SIM_CAL_OPTION=="NONE") ? 256 : 10;
localparam OCAL_SIMPLE_SCAN_SAMPS = (SIM_CAL_OPTION=="NONE") ? 2048 : 1;
localparam POC_PCT_SAMPS_SOLID = 80;
localparam SCAN_PCT_SAMPS_SOLID = 95;
mig_7series_v2_3_ddr_phy_oclkdelay_cal #
(/*AUTOINSTPARAM*/
// Parameters
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
//.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
//.OCAL_EN (OCAL_EN),
.OCAL_SIMPLE_SCAN_SAMPS (OCAL_SIMPLE_SCAN_SAMPS),
.PCT_SAMPS_SOLID (POC_PCT_SAMPS_SOLID),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP),
.SCAN_PCT_SAMPS_SOLID (SCAN_PCT_SAMPS_SOLID),
.SAMPCNTRWIDTH (SAMPCNTRWIDTH),
.SAMPLES (SAMPLES),
.MMCM_SAMP_WAIT (MMCM_SAMP_WAIT),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.TAPCNTRWIDTH (TAPCNTRWIDTH),
.TAPSPERKCLK (TAPSPERKCLK),
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.BYPASS_COMPLEX_OCAL (BYPASS_COMPLEX_OCAL)
//.tCK (tCK)
)
u_ddr_phy_oclkdelay_cal
(/*AUTOINST*/
// Outputs
.prbs_ignore_first_byte (prbs_ignore_first_byte),
.prbs_ignore_last_bytes (prbs_ignore_last_bytes),
.complex_oclkdelay_calib_done (complex_oclkdelay_calib_done),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data[16*DRAM_WIDTH-1:0]),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal[255:0]),
.lim2init_write_request (lim2init_write_request),
.lim_done (lim_done),
.oclk_calib_resume (oclk_calib_resume),
//.oclk_init_delay_done (oclk_init_delay_done),
.oclk_prech_req (oclk_prech_req),
.oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]),
.oclkdelay_calib_done (oclkdelay_calib_done),
.po_en_stg23 (po_en_stg23),
//.po_en_stg3 (po_en_stg3),
.po_stg23_incdec (po_stg23_incdec),
.po_stg23_sel (po_stg23_sel),
//.po_stg3_incdec (po_stg3_incdec),
.psen (psen),
.psincdec (psincdec),
.wrlvl_final (wrlvl_final),
.rd_victim_sel (complex_ocal_rd_victim_sel),
.ocal_num_samples_done_r (complex_ocal_num_samples_done_r),
.complex_wrlvl_final (complex_wrlvl_final),
.poc_error (poc_error),
// Inputs
.clk (clk),
.complex_oclkdelay_calib_start (complex_oclkdelay_calib_start_w),
.metaQ (pd_out),
//.oclk_init_delay_start (oclk_init_delay_start),
.po_counter_read_val (po_counter_read_val),
.oclkdelay_calib_start (oclkdelay_calib_start),
.oclkdelay_init_val (oclkdelay_init_val[5:0]),
.poc_sample_pd (poc_sample_pd),
.phy_rddata (phy_rddata[2*nCK_PER_CLK*DQ_WIDTH-1:0]),
.phy_rddata_en (phy_rddata_en),
.prbs_o (prbs_o[2*nCK_PER_CLK*DQ_WIDTH-1:0]),
.prech_done (prech_done),
.psdone (psdone),
.rst (rst),
.wl_po_fine_cnt (wl_po_fine_cnt[6*DQS_WIDTH-1:0]),
.ocal_num_samples_inc (complex_ocal_num_samples_inc),
.oclkdelay_center_calib_start (oclkdelay_center_calib_start),
.oclk_center_write_resume (oclk_center_write_resume),
.oclkdelay_center_calib_done (oclkdelay_center_calib_done),
.dbg_ocd_lim (dbg_ocd_lim));
end else begin : oclk_calib_disabled
assign wrlvl_final = 'b0;
assign psen = 'b0;
assign psincdec = 'b0;
assign po_stg23_sel = 'b0;
assign po_stg23_incdec = 'b0;
assign po_en_stg23 = 'b0;
//assign oclk_init_delay_done = 1'b1;
assign oclkdelay_calib_cnt = 'b0;
assign oclk_prech_req = 'b0;
assign oclk_calib_resume = 'b0;
assign oclkdelay_calib_done = 1'b1;
assign dbg_phy_oclkdelay_cal = 'h0;
assign dbg_oclkdelay_rd_data = 'h0;
end
endgenerate
//***************************************************************************
// Read data-offset calibration required for Phaser_In
//***************************************************************************
generate
if(DQSFOUND_CAL == "RIGHT") begin: dqsfind_calib_right
mig_7series_v2_3_ddr_phy_dqs_found_cal #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.nCL (nCL),
.AL (AL),
.nCWL (nCWL),
//.RANKS (RANKS),
.RANKS (1),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.REG_CTRL (REG_CTRL),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.DRAM_TYPE (DRAM_TYPE),
.NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL),
.N_CTL_LANES (DQS_FOUND_N_CTL_LANES),
.HIGHEST_LANE (HIGHEST_LANE),
.HIGHEST_BANK (HIGHEST_BANK),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4)
)
u_ddr_phy_dqs_found_cal
(
.clk (clk),
.rst (rst),
.pi_dqs_found_start (pi_dqs_found_start),
.dqsfound_retry (dqsfound_retry),
.detect_pi_found_dqs (detect_pi_found_dqs),
.prech_done (prech_done),
.pi_dqs_found_lanes (pi_dqs_found_lanes),
.pi_rst_stg1_cal (pi_rst_stg1_cal),
.rd_data_offset_0 (rd_data_offset_0),
.rd_data_offset_1 (rd_data_offset_1),
.rd_data_offset_2 (rd_data_offset_2),
.pi_dqs_found_rank_done (pi_dqs_found_rank_done),
.pi_dqs_found_done (pi_dqs_found_done),
.dqsfound_retry_done (dqsfound_retry_done),
.dqs_found_prech_req (dqs_found_prech_req),
.pi_dqs_found_err (pi_dqs_found_err),
.rd_data_offset_ranks_0 (rd_data_offset_ranks_0),
.rd_data_offset_ranks_1 (rd_data_offset_ranks_1),
.rd_data_offset_ranks_2 (rd_data_offset_ranks_2),
.rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0),
.rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1),
.rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2),
.po_counter_read_val (po_counter_read_val),
.rd_data_offset_cal_done (rd_data_offset_cal_done),
.fine_adjust_done (fine_adjust_done),
.fine_adjust_lane_cnt (fine_adjust_lane_cnt),
.ck_po_stg2_f_indec (ck_po_stg2_f_indec),
.ck_po_stg2_f_en (ck_po_stg2_f_en),
.dbg_dqs_found_cal (dbg_dqs_found_cal)
);
end else begin: dqsfind_calib_left
mig_7series_v2_3_ddr_phy_dqs_found_cal_hr #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.nCL (nCL),
.AL (AL),
.nCWL (nCWL),
//.RANKS (RANKS),
.RANKS (1),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.REG_CTRL (REG_CTRL),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.DRAM_TYPE (DRAM_TYPE),
.NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL),
.N_CTL_LANES (DQS_FOUND_N_CTL_LANES),
.HIGHEST_LANE (HIGHEST_LANE),
.HIGHEST_BANK (HIGHEST_BANK),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4)
)
u_ddr_phy_dqs_found_cal_hr
(
.clk (clk),
.rst (rst),
.pi_dqs_found_start (pi_dqs_found_start),
.dqsfound_retry (dqsfound_retry),
.detect_pi_found_dqs (detect_pi_found_dqs),
.prech_done (prech_done),
.pi_dqs_found_lanes (pi_dqs_found_lanes),
.pi_rst_stg1_cal (pi_rst_stg1_cal),
.rd_data_offset_0 (rd_data_offset_0),
.rd_data_offset_1 (rd_data_offset_1),
.rd_data_offset_2 (rd_data_offset_2),
.pi_dqs_found_rank_done (pi_dqs_found_rank_done),
.pi_dqs_found_done (pi_dqs_found_done),
.dqsfound_retry_done (dqsfound_retry_done),
.dqs_found_prech_req (dqs_found_prech_req),
.pi_dqs_found_err (pi_dqs_found_err),
.rd_data_offset_ranks_0 (rd_data_offset_ranks_0),
.rd_data_offset_ranks_1 (rd_data_offset_ranks_1),
.rd_data_offset_ranks_2 (rd_data_offset_ranks_2),
.rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0),
.rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1),
.rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2),
.po_counter_read_val (po_counter_read_val),
.rd_data_offset_cal_done (rd_data_offset_cal_done),
.fine_adjust_done (fine_adjust_done),
.fine_adjust_lane_cnt (fine_adjust_lane_cnt),
.ck_po_stg2_f_indec (ck_po_stg2_f_indec),
.ck_po_stg2_f_en (ck_po_stg2_f_en),
.dbg_dqs_found_cal (dbg_dqs_found_cal)
);
end
endgenerate
//***************************************************************************
// Read-leveling calibration logic
//***************************************************************************
mig_7series_v2_3_ddr_phy_rdlvl #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.RANKS (1),
.PER_BIT_DESKEW (PER_BIT_DESKEW),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.DEBUG_PORT (DEBUG_PORT),
.DRAM_TYPE (DRAM_TYPE),
.OCAL_EN (OCAL_EN),
.IDELAY_ADJ (IDELAY_ADJ)
)
u_ddr_phy_rdlvl
(
.clk (clk),
.rst (rst),
.mpr_rdlvl_done (mpr_rdlvl_done),
.mpr_rdlvl_start (mpr_rdlvl_start),
.mpr_last_byte_done (mpr_last_byte_done),
.mpr_rnk_done (mpr_rnk_done),
.rdlvl_stg1_start (rdlvl_stg1_start),
.rdlvl_stg1_done (rdlvl_stg1_done),
.rdlvl_stg1_rnk_done (rdlvl_stg1_rank_done),
.rdlvl_stg1_err (rdlvl_stg1_err),
.mpr_rdlvl_err (mpr_rdlvl_err),
.rdlvl_err (rdlvl_err),
.rdlvl_prech_req (rdlvl_prech_req),
.rdlvl_last_byte_done (rdlvl_last_byte_done),
.rdlvl_assrt_common (rdlvl_assrt_common),
.prech_done (prech_done),
.phy_if_empty (phy_if_empty),
.idelaye2_init_val (idelaye2_init_val),
.rd_data (phy_rddata),
.pi_en_stg2_f (rdlvl_pi_stg2_f_en),
.pi_stg2_f_incdec (rdlvl_pi_stg2_f_incdec),
.pi_stg2_load (pi_stg2_load),
.pi_stg2_reg_l (pi_stg2_reg_l),
.dqs_po_dec_done (dqs_po_dec_done),
.pi_counter_read_val (pi_counter_read_val),
.pi_fine_dly_dec_done (pi_fine_dly_dec_done),
.idelay_ce (idelay_ce_int),
.idelay_inc (idelay_inc_int),
.idelay_ld (idelay_ld),
.wrcal_cnt (po_stg2_wrcal_cnt),
.pi_stg2_rdlvl_cnt (pi_stg2_rdlvl_cnt),
.dlyval_dq (dlyval_dq),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_phy_rdlvl (dbg_phy_rdlvl)
);
generate
if((DRAM_TYPE == "DDR3") && (nCK_PER_CLK == 4) && (BYPASS_COMPLEX_RDLVL=="FALSE")) begin:ddr_phy_prbs_rdlvl_gen
mig_7series_v2_3_ddr_phy_prbs_rdlvl #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.RANKS (1),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.PRBS_WIDTH (PRBS_WIDTH),
.FIXED_VICTIM (FIXED_VICTIM),
.FINE_PER_BIT (FINE_PER_BIT),
.CENTER_COMP_MODE (CENTER_COMP_MODE),
.PI_VAL_ADJ (PI_VAL_ADJ)
)
u_ddr_phy_prbs_rdlvl
(
.clk (clk),
.rst (rst),
.prbs_rdlvl_start (prbs_rdlvl_start),
.prbs_rdlvl_done (prbs_rdlvl_done),
.prbs_last_byte_done (prbs_last_byte_done),
.prbs_rdlvl_prech_req (prbs_rdlvl_prech_req),
.complex_sample_cnt_inc (complex_sample_cnt_inc),
.prech_done (prech_done),
.phy_if_empty (phy_if_empty),
.rd_data (phy_rddata),
.compare_data (prbs_o),
.pi_counter_read_val (pi_counter_read_val),
.pi_en_stg2_f (prbs_pi_stg2_f_en),
.pi_stg2_f_incdec (prbs_pi_stg2_f_incdec),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.pi_stg2_prbs_rdlvl_cnt (pi_stg2_prbs_rdlvl_cnt),
.prbs_final_dqs_tap_cnt_r (prbs_final_dqs_tap_cnt_r),
.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps),
.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps),
.rd_victim_sel (rd_victim_sel),
.complex_victim_inc (complex_victim_inc),
.reset_rd_addr (reset_rd_addr),
.read_pause (read_pause),
.fine_delay_incdec_pb (fine_delay_incdec_pb),
.fine_delay_sel (fine_delay_sel)
);
end else begin:ddr_phy_prbs_rdlvl_off
assign prbs_rdlvl_done = rdlvl_stg1_done ;
//assign prbs_last_byte_done = rdlvl_stg1_rank_done ;
assign prbs_last_byte_done = rdlvl_stg1_done;
assign read_pause = 1'b0;
assign reset_rd_addr = 1'b0;
assign prbs_rdlvl_prech_req = 1'b0 ;
assign prbs_pi_stg2_f_en = 1'b0 ;
assign prbs_pi_stg2_f_incdec = 1'b0 ;
assign pi_stg2_prbs_rdlvl_cnt = 'b0 ;
assign dbg_prbs_rdlvl = 'h0 ;
assign prbs_final_dqs_tap_cnt_r = {(6*DQS_WIDTH*RANKS){1'b0}};
assign dbg_prbs_first_edge_taps = {(6*DQS_WIDTH*RANKS){1'b0}};
assign dbg_prbs_second_edge_taps = {(6*DQS_WIDTH*RANKS){1'b0}};
end
endgenerate
//***************************************************************************
// Temperature induced PI tap adjustment logic
//***************************************************************************
mig_7series_v2_3_ddr_phy_tempmon #
(
.TCQ (TCQ)
)
ddr_phy_tempmon_0
(
.rst (rst),
.clk (clk),
.calib_complete (calib_complete),
.tempmon_pi_f_inc (tempmon_pi_f_inc),
.tempmon_pi_f_dec (tempmon_pi_f_dec),
.tempmon_sel_pi_incdec (tempmon_sel_pi_incdec),
.device_temp (device_temp),
.tempmon_sample_en (tempmon_sample_en)
);
endmodule
|
// Copyright (c) 2014, Segiusz 'q3k' Bazanski <[email protected]>
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
/* verilator lint_off UNUSED */
module qm_dcache(
input wire reset,
input wire clk,
// to the consumer (CPU execute stage)
output reg stall,
input wire [31:0] address,
output reg [31:0] read_data,
input wire [31:0] write_data,
input wire write_enable,
input wire enable,
// to the memory controller (no wishbone yet...)
// the cache is currently only backed in 1GBit RAM via this controller
// this RAM is mapped 0x80000000 - 0x90000000
output wire mem_cmd_clk, // we will keep this synchronous to the input clock
output reg mem_cmd_en,
output reg [2:0] mem_cmd_instr,
output reg [5:0] mem_cmd_bl,
output reg [29:0] mem_cmd_addr,
input wire mem_cmd_full,
input wire mem_cmd_empty,
output wire mem_rd_clk,
output reg mem_rd_en,
input wire [6:0] mem_rd_count,
input wire mem_rd_full,
input wire [31:0] mem_rd_data,
input wire mem_rd_empty,
output wire mem_wr_clk,
output wire mem_wr_en,
output wire mem_wr_mask,
output wire [31:0] mem_wr_data,
input wire mem_wr_empty,
input wire mem_wr_full,
input wire mem_wr_underrun,
input wire [6:0] mem_wr_count,
input wire mem_wr_data
);
// 4k cache lines -> 16kword cache
reg [145:0] lines [4095:0];
/// internal signals
// the bit used to mark valid lines (flips when we flush the cache)
reg valid_bit;
wire [11:0] index;
wire index_valid;
wire [15:0] index_tag;
wire [15:0] address_tag;
wire [1:0] address_word;
// 145 0
// - +----------------------------------------------------------+
// ^ 4k | s | v | tag | word 3 | word 2 | word 1 | word 0 |
// | lines | s | v | tag | word 3 | word 2 | word 1 | word 0 |
// | | s | v | tag | word 3 | word 2 | word 1 | word 0 | <--
// | | s | v | tag | word 3 | word 2 | word 1 | word 0 | index
// | | s | v | tag | word 3 | word 2 | word 1 | word 0 |
// | | s | v | tag | word 3 | word 2 | word 1 | word 0 |
// v | s | v | tag | word 3 | word 2 | word 1 | word 0 |
// - +----------------------------------------------------------+
//
// index - lower 16 bits of address, used to select a line
// s - synced (written back to memory, can be evicted)
// v - valid (has been read from memory, can be output to consumer)
// tag - upper 16 bits of address, to check against requested address
//
assign index = address[15:4];
assign index_synced = lines[index]145];
assign index_valid = lines[index][144];
assign index_tag = lines[index][143:128];
assign address_tag = address[31:16];
assign address_word = address[3:2];
// Be pi degrees out of phase with DRAM controller
assign mem_rd_clk = ~clk;
assign mem_wr_clk = ~clk;
assign mem_cmd_clk = ~clk;
assign mem_wr_mask = 32'b0;
// reset condition
generate
genvar i;
for (i = 0; i < 4096; i = i + 1) begin: ruchanie
always @(posedge clk) begin
if (reset) begin
lines[0] <= {146'b0};
end
end
end
endgenerate
always @(posedge clk) begin
if (reset) begin
valid_bit <= 1;
memory_read_state <= 0;
memory_write_state <= 0;
mem_cmd_en <= 0;
mem_cmd_bl <= 0;
mem_cmd_instr <= 0;
mem_cmd_addr <= 0;
mem_rd_en <= 0;
end
end
// read condition
always @(*) begin
if (enable) begin
// is this in the RAM region?
if (32'h80000000 <= address && address < 32'h90000000) begin
// do we have a hit?
if (index_valid == valid_bit && index_tag == address_tag) begin
if (address_word == 2'b00)
data = lines[index][31:0];
else if (address_word == 2'b01)
data = lines[index][63:32];
else if (address_word == 2'b10)
data = lines[index][95:64];
else
data = lines[index][127:96];
hit = 1;
stall = 0;
end else begin
hit = 0;
stall = 1;
end
end else begin
hit = 1;
stall = 0;
data = 32'h00000000;
end
end else begin
hit = 0;
stall = 0;
end
end
reg [2:0] memory_read_state;
reg [2:0] memory_write_state;
always @(posedge clk) begin
// Should we be running the read state machine?
if ((stall && !reset && enable && index_sync == 1) ||
(memory_read_state != 0 && !reset && enable)) begin
case (memory_read_state)
0: begin // assert command
mem_cmd_instr <= 1; // read
mem_cmd_bl <= 3; // four words
mem_cmd_addr <= {1'b0, address[28:0]};
mem_cmd_en <= 1;
mem_rd_en <= 1;
memory_read_state <= 1;
end
1: begin // wait for first word
mem_cmd_en <= 0;
if (!mem_rd_empty) begin
lines[index][31:0] <= mem_rd_data;
memory_read_state <= 2;
end
end
2: begin // wait for second word
if (!mem_rd_empty) begin
lines[index][63:32] <= mem_rd_data;
memory_read_state <= 3;
end
end
3: begin // wait for third word
if (!mem_rd_empty) begin
lines[index][95:64] <= mem_rd_data;
memory_read_state <= 4;
end
end
4: begin // wait for fourth word
if (!mem_rd_empty) begin
lines[index][127:96] <= mem_rd_data;
memory_read_state <= 0;
mem_rd_en <= 0;
// write tag
lines[index][143:128] <= address_tag;
// and valid bit - our cominatorial logic will now turn
// off stalling and indicate a hit to the consumer
lines[index][144] <= valid_bit;
end
end
endcase
end
// Should we be running the writeback state machine?
if ((stall && !reset && enable && index_sync == 0) ||
(memory_write_state != 0 && !reset && enable)) begin
case (memory_write_state)
0: begin
// first word to fifo
if (!mem_wr_full) begin
mem_wr_en <= 1;
mem_wr_data <= lines[index][31:0];
memory_write_state <= 1;
end
end
1: begin
// second word to fifo
if (!mem_wr_full) begin
mem_wr_data <= lines[index][63:32];
memory_write_state <= 2;
end
end
2: begin
// third word to fifo
if (!mem_wr_full) begin
mem_wr_data <= lines[index][95:64];
memory_write_state <= 3;
end
end
3: begin
// fourth word to fifo
if (!mem_wr_full) begin
mem_wr_data <= lines[index][127:96];
// also send write command
mem_cmd_en <= 1;
mem_cmd_instr <= 0; // write
mem_cmd_bl <= 3; // four words
mem_cmd_addr <= {1'b0, address[28:0]};
memory_write_state <= 4;
end
end
4: begin
mem_wr_en <= 0;
mem_cmd_en <= 0;
memory_write_state <= 0;
end
endcase
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ddr_ch.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module ddr_ch(update_dr_in ,mode_ctrl_in ,shift_dr_in ,clock_dr_in ,
hiz_n_in ,afo ,serial_in ,afi ,serial_out ,testmode_l ,test_mode ,
bypass_enable_out ,ps_select_out ,rclk ,se ,pad_clk_so ,pad_clk_si
,dram_io_data_out ,spare_ddr_pin ,spare_ddr_data , arst_l_out,
dram_io_ptr_clk_inv ,bso ,bsi ,mode_ctrl_out ,update_dr_out ,
shift_dr_out ,clock_dr_out ,hiz_n_out ,bypass_enable_in ,
ps_select_in ,strobe ,io_dram_data_in ,io_dram_ecc_in ,dram_io_addr
,dram_io_clk_enable ,dram_io_cke ,dram_io_bank ,dram_io_ras_l ,
dram_io_write_en_l ,dram_io_cas_l ,dram_io_cs_l ,dram_dq ,dram_addr
,dram_cb ,dram_dqs ,dram_cke ,dram_ba ,dram_ck_n ,dram_ck_p ,
io_dram_data_valid ,dram_ras_l ,dram_we_l ,dram_cas_l ,dram_cs_l ,
burst_length_four ,dram_io_pad_clk_inv ,dram_io_pad_enable ,
dram_io_drive_enable ,rst_l ,lpf_code ,dram_io_channel_disabled ,
dram_io_drive_data ,cbu ,vdd_h ,cbd, dram_arst_l );
output arst_l_out ;
output [143:0] afi ;
output [143:0] serial_out ;
output [255:0] io_dram_data_in ;
output [31:0] io_dram_ecc_in ;
input [143:0] afo ;
input [143:0] serial_in ;
input [287:0] dram_io_data_out ;
input [9:0] spare_ddr_data ;
input [4:0] dram_io_ptr_clk_inv ;
input [14:0] dram_io_addr ;
input [2:0] dram_io_bank ;
input [3:0] dram_io_cs_l ;
input [4:0] lpf_code ;
input [8:1] cbu ;
input [8:1] cbd ;
inout [9:0] spare_ddr_pin ;
inout [127:0] dram_dq ;
inout [14:0] dram_addr ;
inout [15:0] dram_cb ;
inout [35:0] dram_dqs ;
inout [2:0] dram_ba ;
inout [3:0] dram_ck_n ;
inout [3:0] dram_ck_p ;
inout [3:0] dram_cs_l ;
output bypass_enable_out ;
output ps_select_out ;
output pad_clk_so ;
output bso ;
output mode_ctrl_out ;
output update_dr_out ;
output shift_dr_out ;
output clock_dr_out ;
output hiz_n_out ;
output io_dram_data_valid ;
input update_dr_in ;
input mode_ctrl_in ;
input shift_dr_in ;
input clock_dr_in ;
input hiz_n_in ;
input testmode_l ;
input test_mode ;
input rclk ;
input se ;
input pad_clk_si ;
input bsi ;
input bypass_enable_in ;
input ps_select_in ;
input strobe ;
input dram_io_clk_enable ;
input dram_io_cke ;
input dram_io_ras_l ;
input dram_io_write_en_l ;
input dram_io_cas_l ;
input burst_length_four ;
input dram_io_pad_clk_inv ;
input dram_io_pad_enable ;
input dram_io_drive_enable ;
input rst_l ;
input dram_arst_l ;
input dram_io_channel_disabled ;
input dram_io_drive_data ;
input vdd_h ;
inout dram_cke ;
inout dram_ras_l ;
inout dram_we_l ;
inout dram_cas_l ;
wire [7:0] net0126 ;
wire [7:0] net0180 ;
wire [8:1] cbd_l ;
wire [7:0] net0181 ;
wire [7:0] net0189 ;
wire [8:1] cbu_l ;
wire [7:0] net0128 ;
wire [1:0] pad_pos_cnt ;
wire [1:0] pad_neg_cnt ;
wire net0173 ;
wire net0200 ;
wire net0201 ;
wire net0202 ;
wire net0300 ;
wire net0203 ;
wire net0301 ;
wire net0302 ;
wire net0204 ;
wire net0303 ;
wire net0304 ;
wire net0207 ;
wire net0305 ;
wire net0306 ;
wire bot_so_pvt_si ;
wire net0253 ;
wire net0254 ;
wire bso0_bsi1 ;
wire pad_clk_so0_plogic_si1 ;
wire se_out ;
wire net0241 ;
wire net0247 ;
wire net0249 ;
wire net0191 ;
wire net0192 ;
wire net0193 ;
wire net0212 ;
wire net0194 ;
wire net0213 ;
wire net0195 ;
wire net0196 ;
wire net0197 ;
wire net0198 ;
wire net0199 ;
wire plogic_clk_so1_pad_si2 ;
bw_io_ddr_sig_top I0 (
.spare_ddr_data ({spare_ddr_data[9:8] } ),
.vrefcode_i_l ({net0189[0] ,net0189[1] ,net0189[2] ,net0189[3] ,
net0189[4] ,net0189[5] ,net0189[6] ,net0189[7] } ),
.vrefcode_i_r ({net0189[0] ,net0189[1] ,net0189[2] ,net0189[3] ,
net0189[4] ,net0189[5] ,net0189[6] ,net0189[7] } ),
.afo ({afo[71:0] } ),
.serial_in ({serial_in[71:0] } ),
.serial_out ({serial_out[71:0] } ),
.afi ({afi[71:0] } ),
.lpf_code_i_r ({lpf_code } ),
.dram_io_ptr_clk_inv_i_r ({dram_io_ptr_clk_inv[1:0] } ),
.pad_pos_cnt_i_r ({pad_pos_cnt } ),
.pad_neg_cnt_i_r ({pad_neg_cnt } ),
.cbu_i_r ({net0180[0] ,net0180[1] ,net0180[2] ,net0180[3] ,
net0180[4] ,net0180[5] ,net0180[6] ,net0180[7] } ),
.cbd_i_r ({net0181[0] ,net0181[1] ,net0181[2] ,net0181[3] ,
net0181[4] ,net0181[5] ,net0181[6] ,net0181[7] } ),
.lpf_code_i_l ({lpf_code } ),
.dram_io_ptr_clk_inv_i_l ({dram_io_ptr_clk_inv[1:0] } ),
.cbd_i_l ({cbd_l } ),
.spare_ddr_pin ({spare_ddr_pin[9:8] } ),
.dram_ck_n ({dram_ck_n } ),
.dram_ck_p ({dram_ck_p } ),
.dram_io_bank ({dram_io_bank[2] } ),
.dram_ba ({dram_ba[2] } ),
.pad_neg_cnt_i_l ({pad_neg_cnt } ),
.cbu_i_l ({cbu_l } ),
.dram_cb ({dram_cb[7:0] } ),
.pad_pos_cnt_i_l ({pad_pos_cnt } ),
.mode_ctrl_out (net0306 ),
.update_dr_out (net0305 ),
.shift_dr_out (net0304 ),
.clock_dr_out (net0303 ),
.hiz_n_out (net0302 ),
.bypass_enable_out (net0301 ),
.ps_select_out (net0300 ),
.test_mode_i_r (test_mode ),
.strobe_i_r (strobe ),
.testmode_l_i_l (testmode_l ),
.burst_length_four_i_r (burst_length_four ),
.dram_io_pad_enable_i_r (dram_io_pad_enable ),
.dram_io_drive_enable_i_r (dram_io_drive_enable ),
.rst_l_i_r (rst_l ),
.arst_l_i_r (dram_arst_l ),
.dram_io_channel_disabled_i_r (dram_io_channel_disabled ),
.dram_io_drive_data_i_r (dram_io_drive_data ),
.se_i_r (se ),
.mode_ctrl_i_r (net0191 ),
.shift_dr_i_r (net0193 ),
.clock_dr_i_r (net0194 ),
.hiz_n_i_r (net0195 ),
.update_dr_i_r (net0192 ),
.vdd_h (vdd_h ),
.strobe_i_l (strobe ),
.bypass_enable_i_l (net0203 ),
.ps_select_i_r (net0197 ),
.ps_select_i_l (net0204 ),
.test_mode_i_l (test_mode ),
.testmode_l_i_r (testmode_l ),
.dram_io_pad_enable_i_l (dram_io_pad_enable ),
.burst_length_four_i_l (burst_length_four ),
.\dram_io_data_out[95] (dram_io_data_out[95] ),
.\dram_io_data_out[94] (dram_io_data_out[94] ),
.\dram_io_data_out[93] (dram_io_data_out[93] ),
.\dram_io_data_out[92] (dram_io_data_out[92] ),
.\dram_io_data_out[91] (dram_io_data_out[91] ),
.\dram_io_data_out[90] (dram_io_data_out[90] ),
.\dram_io_data_out[89] (dram_io_data_out[89] ),
.\dram_io_data_out[88] (dram_io_data_out[88] ),
.\dram_io_data_out[87] (dram_io_data_out[87] ),
.\dram_io_data_out[86] (dram_io_data_out[86] ),
.\dram_io_data_out[85] (dram_io_data_out[85] ),
.\dram_io_data_out[84] (dram_io_data_out[84] ),
.\dram_io_data_out[83] (dram_io_data_out[83] ),
.\dram_io_data_out[82] (dram_io_data_out[82] ),
.\dram_io_data_out[81] (dram_io_data_out[81] ),
.\dram_io_data_out[80] (dram_io_data_out[80] ),
.\dram_io_data_out[79] (dram_io_data_out[79] ),
.\dram_io_data_out[78] (dram_io_data_out[78] ),
.\dram_io_data_out[77] (dram_io_data_out[77] ),
.\dram_io_data_out[76] (dram_io_data_out[76] ),
.\dram_io_data_out[75] (dram_io_data_out[75] ),
.\dram_io_data_out[74] (dram_io_data_out[74] ),
.\dram_io_data_out[73] (dram_io_data_out[73] ),
.\dram_io_data_out[72] (dram_io_data_out[72] ),
.\dram_io_data_out[71] (dram_io_data_out[71] ),
.\dram_io_data_out[70] (dram_io_data_out[70] ),
.\dram_io_data_out[69] (dram_io_data_out[69] ),
.\dram_io_data_out[68] (dram_io_data_out[68] ),
.\dram_io_data_out[67] (dram_io_data_out[67] ),
.\dram_io_data_out[66] (dram_io_data_out[66] ),
.\dram_io_data_out[65] (dram_io_data_out[65] ),
.\dram_io_data_out[64] (dram_io_data_out[64] ),
.\dram_io_data_out[31] (dram_io_data_out[31] ),
.\dram_io_data_out[30] (dram_io_data_out[30] ),
.\dram_io_data_out[29] (dram_io_data_out[29] ),
.\dram_io_data_out[28] (dram_io_data_out[28] ),
.\dram_io_data_out[27] (dram_io_data_out[27] ),
.\dram_io_data_out[26] (dram_io_data_out[26] ),
.\dram_io_data_out[25] (dram_io_data_out[25] ),
.\dram_io_data_out[24] (dram_io_data_out[24] ),
.\dram_io_data_out[23] (dram_io_data_out[23] ),
.\dram_io_data_out[22] (dram_io_data_out[22] ),
.\dram_io_data_out[21] (dram_io_data_out[21] ),
.\dram_io_data_out[20] (dram_io_data_out[20] ),
.\dram_io_data_out[19] (dram_io_data_out[19] ),
.\dram_io_data_out[18] (dram_io_data_out[18] ),
.\dram_io_data_out[17] (dram_io_data_out[17] ),
.\dram_io_data_out[16] (dram_io_data_out[16] ),
.\dram_io_data_out[15] (dram_io_data_out[15] ),
.\dram_io_data_out[14] (dram_io_data_out[14] ),
.\dram_io_data_out[13] (dram_io_data_out[13] ),
.\dram_io_data_out[12] (dram_io_data_out[12] ),
.\dram_io_data_out[11] (dram_io_data_out[11] ),
.\dram_io_data_out[10] (dram_io_data_out[10] ),
.\dram_io_data_out[9] (dram_io_data_out[9] ),
.\dram_io_data_out[8] (dram_io_data_out[8] ),
.\dram_io_data_out[7] (dram_io_data_out[7] ),
.\dram_io_data_out[6] (dram_io_data_out[6] ),
.\dram_io_data_out[5] (dram_io_data_out[5] ),
.\dram_io_data_out[4] (dram_io_data_out[4] ),
.\dram_io_data_out[3] (dram_io_data_out[3] ),
.\dram_io_data_out[2] (dram_io_data_out[2] ),
.\dram_io_data_out[1] (dram_io_data_out[1] ),
.\dram_io_data_out[0] (dram_io_data_out[0] ),
.dram_io_channel_disabled_i_l (dram_io_channel_disabled ),
.dram_io_drive_enable_i_l (dram_io_drive_enable ),
.rclk (rclk ),
.\dram_io_data_out[175] (dram_io_data_out[175] ),
.\dram_io_data_out[174] (dram_io_data_out[174] ),
.\dram_io_data_out[173] (dram_io_data_out[173] ),
.\dram_io_data_out[172] (dram_io_data_out[172] ),
.\dram_io_data_out[171] (dram_io_data_out[171] ),
.\dram_io_data_out[170] (dram_io_data_out[170] ),
.\dram_io_data_out[169] (dram_io_data_out[169] ),
.\dram_io_data_out[168] (dram_io_data_out[168] ),
.\dram_io_data_out[167] (dram_io_data_out[167] ),
.\dram_io_data_out[166] (dram_io_data_out[166] ),
.\dram_io_data_out[165] (dram_io_data_out[165] ),
.\dram_io_data_out[164] (dram_io_data_out[164] ),
.\dram_io_data_out[163] (dram_io_data_out[163] ),
.\dram_io_data_out[162] (dram_io_data_out[162] ),
.\dram_io_data_out[161] (dram_io_data_out[161] ),
.\dram_io_data_out[160] (dram_io_data_out[160] ),
.\dram_io_data_out[159] (dram_io_data_out[159] ),
.\dram_io_data_out[158] (dram_io_data_out[158] ),
.\dram_io_data_out[157] (dram_io_data_out[157] ),
.\dram_io_data_out[156] (dram_io_data_out[156] ),
.\dram_io_data_out[155] (dram_io_data_out[155] ),
.\dram_io_data_out[154] (dram_io_data_out[154] ),
.\dram_io_data_out[153] (dram_io_data_out[153] ),
.\dram_io_data_out[152] (dram_io_data_out[152] ),
.\dram_io_data_out[151] (dram_io_data_out[151] ),
.\dram_io_data_out[150] (dram_io_data_out[150] ),
.\dram_io_data_out[149] (dram_io_data_out[149] ),
.\dram_io_data_out[148] (dram_io_data_out[148] ),
.\dram_io_data_out[147] (dram_io_data_out[147] ),
.\dram_io_data_out[146] (dram_io_data_out[146] ),
.\dram_io_data_out[145] (dram_io_data_out[145] ),
.\dram_io_data_out[144] (dram_io_data_out[144] ),
.\dram_io_data_out[279] (dram_io_data_out[279] ),
.\dram_io_data_out[278] (dram_io_data_out[278] ),
.\dram_io_data_out[277] (dram_io_data_out[277] ),
.\dram_io_data_out[276] (dram_io_data_out[276] ),
.\dram_io_data_out[275] (dram_io_data_out[275] ),
.\dram_io_data_out[274] (dram_io_data_out[274] ),
.\dram_io_data_out[273] (dram_io_data_out[273] ),
.\dram_io_data_out[272] (dram_io_data_out[272] ),
.\io_dram_data_in[223] (io_dram_data_in[223] ),
.\io_dram_data_in[222] (io_dram_data_in[222] ),
.\io_dram_data_in[221] (io_dram_data_in[221] ),
.\io_dram_data_in[220] (io_dram_data_in[220] ),
.\io_dram_data_in[219] (io_dram_data_in[219] ),
.\io_dram_data_in[218] (io_dram_data_in[218] ),
.\io_dram_data_in[217] (io_dram_data_in[217] ),
.\io_dram_data_in[216] (io_dram_data_in[216] ),
.\io_dram_data_in[215] (io_dram_data_in[215] ),
.\io_dram_data_in[214] (io_dram_data_in[214] ),
.\io_dram_data_in[213] (io_dram_data_in[213] ),
.\io_dram_data_in[212] (io_dram_data_in[212] ),
.\io_dram_data_in[211] (io_dram_data_in[211] ),
.\io_dram_data_in[210] (io_dram_data_in[210] ),
.\io_dram_data_in[209] (io_dram_data_in[209] ),
.\io_dram_data_in[208] (io_dram_data_in[208] ),
.\io_dram_data_in[207] (io_dram_data_in[207] ),
.\io_dram_data_in[206] (io_dram_data_in[206] ),
.\io_dram_data_in[205] (io_dram_data_in[205] ),
.\io_dram_data_in[204] (io_dram_data_in[204] ),
.\io_dram_data_in[203] (io_dram_data_in[203] ),
.\io_dram_data_in[202] (io_dram_data_in[202] ),
.\io_dram_data_in[201] (io_dram_data_in[201] ),
.\io_dram_data_in[200] (io_dram_data_in[200] ),
.\io_dram_data_in[199] (io_dram_data_in[199] ),
.\io_dram_data_in[198] (io_dram_data_in[198] ),
.\io_dram_data_in[197] (io_dram_data_in[197] ),
.\io_dram_data_in[196] (io_dram_data_in[196] ),
.\io_dram_data_in[195] (io_dram_data_in[195] ),
.\io_dram_data_in[194] (io_dram_data_in[194] ),
.\io_dram_data_in[193] (io_dram_data_in[193] ),
.\io_dram_data_in[192] (io_dram_data_in[192] ),
.\dram_io_data_out[135] (dram_io_data_out[135] ),
.\dram_io_data_out[134] (dram_io_data_out[134] ),
.\dram_io_data_out[133] (dram_io_data_out[133] ),
.\dram_io_data_out[132] (dram_io_data_out[132] ),
.\dram_io_data_out[131] (dram_io_data_out[131] ),
.\dram_io_data_out[130] (dram_io_data_out[130] ),
.\dram_io_data_out[129] (dram_io_data_out[129] ),
.\dram_io_data_out[128] (dram_io_data_out[128] ),
.\io_dram_ecc_in[23] (io_dram_ecc_in[23] ),
.\io_dram_ecc_in[22] (io_dram_ecc_in[22] ),
.\io_dram_ecc_in[21] (io_dram_ecc_in[21] ),
.\io_dram_ecc_in[20] (io_dram_ecc_in[20] ),
.\io_dram_ecc_in[19] (io_dram_ecc_in[19] ),
.\io_dram_ecc_in[18] (io_dram_ecc_in[18] ),
.\io_dram_ecc_in[17] (io_dram_ecc_in[17] ),
.\io_dram_ecc_in[16] (io_dram_ecc_in[16] ),
.\io_dram_ecc_in[7] (io_dram_ecc_in[7] ),
.\io_dram_ecc_in[6] (io_dram_ecc_in[6] ),
.\io_dram_ecc_in[5] (io_dram_ecc_in[5] ),
.\io_dram_ecc_in[4] (io_dram_ecc_in[4] ),
.\io_dram_ecc_in[3] (io_dram_ecc_in[3] ),
.\io_dram_ecc_in[2] (io_dram_ecc_in[2] ),
.\io_dram_ecc_in[1] (io_dram_ecc_in[1] ),
.\io_dram_ecc_in[0] (io_dram_ecc_in[0] ),
.\io_dram_data_in[159] (io_dram_data_in[159] ),
.\io_dram_data_in[158] (io_dram_data_in[158] ),
.\io_dram_data_in[157] (io_dram_data_in[157] ),
.\io_dram_data_in[156] (io_dram_data_in[156] ),
.\io_dram_data_in[155] (io_dram_data_in[155] ),
.\io_dram_data_in[154] (io_dram_data_in[154] ),
.\io_dram_data_in[153] (io_dram_data_in[153] ),
.\io_dram_data_in[152] (io_dram_data_in[152] ),
.\io_dram_data_in[151] (io_dram_data_in[151] ),
.\io_dram_data_in[150] (io_dram_data_in[150] ),
.\io_dram_data_in[149] (io_dram_data_in[149] ),
.\io_dram_data_in[148] (io_dram_data_in[148] ),
.\io_dram_data_in[147] (io_dram_data_in[147] ),
.\io_dram_data_in[146] (io_dram_data_in[146] ),
.\io_dram_data_in[145] (io_dram_data_in[145] ),
.\io_dram_data_in[144] (io_dram_data_in[144] ),
.\io_dram_data_in[143] (io_dram_data_in[143] ),
.\io_dram_data_in[142] (io_dram_data_in[142] ),
.\io_dram_data_in[141] (io_dram_data_in[141] ),
.\io_dram_data_in[140] (io_dram_data_in[140] ),
.\io_dram_data_in[139] (io_dram_data_in[139] ),
.\io_dram_data_in[138] (io_dram_data_in[138] ),
.\io_dram_data_in[137] (io_dram_data_in[137] ),
.\io_dram_data_in[136] (io_dram_data_in[136] ),
.\io_dram_data_in[135] (io_dram_data_in[135] ),
.\io_dram_data_in[134] (io_dram_data_in[134] ),
.\io_dram_data_in[133] (io_dram_data_in[133] ),
.\io_dram_data_in[132] (io_dram_data_in[132] ),
.\io_dram_data_in[131] (io_dram_data_in[131] ),
.\io_dram_data_in[130] (io_dram_data_in[130] ),
.\io_dram_data_in[129] (io_dram_data_in[129] ),
.\io_dram_data_in[128] (io_dram_data_in[128] ),
.\io_dram_data_in[31] (io_dram_data_in[31] ),
.\io_dram_data_in[30] (io_dram_data_in[30] ),
.\io_dram_data_in[29] (io_dram_data_in[29] ),
.\io_dram_data_in[28] (io_dram_data_in[28] ),
.\io_dram_data_in[27] (io_dram_data_in[27] ),
.\io_dram_data_in[26] (io_dram_data_in[26] ),
.\io_dram_data_in[25] (io_dram_data_in[25] ),
.\io_dram_data_in[24] (io_dram_data_in[24] ),
.\io_dram_data_in[23] (io_dram_data_in[23] ),
.\io_dram_data_in[22] (io_dram_data_in[22] ),
.\io_dram_data_in[21] (io_dram_data_in[21] ),
.\io_dram_data_in[20] (io_dram_data_in[20] ),
.\io_dram_data_in[19] (io_dram_data_in[19] ),
.\io_dram_data_in[18] (io_dram_data_in[18] ),
.\io_dram_data_in[17] (io_dram_data_in[17] ),
.\io_dram_data_in[16] (io_dram_data_in[16] ),
.\io_dram_data_in[15] (io_dram_data_in[15] ),
.\io_dram_data_in[14] (io_dram_data_in[14] ),
.\io_dram_data_in[13] (io_dram_data_in[13] ),
.\io_dram_data_in[12] (io_dram_data_in[12] ),
.\io_dram_data_in[11] (io_dram_data_in[11] ),
.\io_dram_data_in[10] (io_dram_data_in[10] ),
.\io_dram_data_in[9] (io_dram_data_in[9] ),
.\io_dram_data_in[8] (io_dram_data_in[8] ),
.\io_dram_data_in[7] (io_dram_data_in[7] ),
.\io_dram_data_in[6] (io_dram_data_in[6] ),
.\io_dram_data_in[5] (io_dram_data_in[5] ),
.\io_dram_data_in[4] (io_dram_data_in[4] ),
.\io_dram_data_in[3] (io_dram_data_in[3] ),
.\io_dram_data_in[2] (io_dram_data_in[2] ),
.\io_dram_data_in[1] (io_dram_data_in[1] ),
.\io_dram_data_in[0] (io_dram_data_in[0] ),
.pad_clk_so (pad_clk_so0_plogic_si1 ),
.pad_clk_si (pad_clk_si ),
.\dram_addr[9] (dram_addr[9] ),
.\dram_addr[8] (dram_addr[8] ),
.\dram_addr[7] (dram_addr[7] ),
.\dram_addr[6] (dram_addr[6] ),
.\dram_addr[5] (dram_addr[5] ),
.\dram_addr[4] (dram_addr[4] ),
.\dram_addr[3] (dram_addr[3] ),
.\dram_addr[2] (dram_addr[2] ),
.\dram_addr[1] (dram_addr[1] ),
.\dram_addr[0] (dram_addr[0] ),
.\dram_io_addr[9] (dram_io_addr[9] ),
.\dram_io_addr[8] (dram_io_addr[8] ),
.\dram_io_addr[7] (dram_io_addr[7] ),
.\dram_io_addr[6] (dram_io_addr[6] ),
.\dram_io_addr[5] (dram_io_addr[5] ),
.\dram_io_addr[4] (dram_io_addr[4] ),
.\dram_io_addr[3] (dram_io_addr[3] ),
.\dram_io_addr[2] (dram_io_addr[2] ),
.\dram_io_addr[1] (dram_io_addr[1] ),
.\dram_io_addr[0] (dram_io_addr[0] ),
.\dram_dqs[12] (dram_dqs[12] ),
.\dram_dqs[11] (dram_dqs[11] ),
.\dram_dqs[10] (dram_dqs[10] ),
.\dram_dqs[9] (dram_dqs[9] ),
.\dram_dqs[8] (dram_dqs[8] ),
.bso (bso0_bsi1 ),
.bsi (bsi ),
.dram_io_clk_enable (dram_io_clk_enable ),
.\dram_addr[14] (dram_addr[14] ),
.\dram_addr[13] (dram_addr[13] ),
.\dram_addr[12] (dram_addr[12] ),
.\dram_addr[11] (dram_addr[11] ),
.dram_cke (dram_cke ),
.dram_io_cke (dram_io_cke ),
.\dram_io_addr[14] (dram_io_addr[14] ),
.\dram_io_addr[13] (dram_io_addr[13] ),
.\dram_io_addr[12] (dram_io_addr[12] ),
.\dram_io_addr[11] (dram_io_addr[11] ),
.\dram_dq[95] (dram_dq[95] ),
.\dram_dq[94] (dram_dq[94] ),
.\dram_dq[93] (dram_dq[93] ),
.\dram_dq[92] (dram_dq[92] ),
.\dram_dq[91] (dram_dq[91] ),
.\dram_dq[90] (dram_dq[90] ),
.\dram_dq[89] (dram_dq[89] ),
.\dram_dq[88] (dram_dq[88] ),
.\dram_dq[87] (dram_dq[87] ),
.\dram_dq[86] (dram_dq[86] ),
.\dram_dq[85] (dram_dq[85] ),
.\dram_dq[84] (dram_dq[84] ),
.\dram_dq[83] (dram_dq[83] ),
.\dram_dq[82] (dram_dq[82] ),
.\dram_dq[81] (dram_dq[81] ),
.\dram_dq[80] (dram_dq[80] ),
.\dram_dq[79] (dram_dq[79] ),
.\dram_dq[78] (dram_dq[78] ),
.\dram_dq[77] (dram_dq[77] ),
.\dram_dq[76] (dram_dq[76] ),
.\dram_dq[75] (dram_dq[75] ),
.\dram_dq[74] (dram_dq[74] ),
.\dram_dq[73] (dram_dq[73] ),
.\dram_dq[72] (dram_dq[72] ),
.\dram_dq[71] (dram_dq[71] ),
.\dram_dq[70] (dram_dq[70] ),
.\dram_dq[69] (dram_dq[69] ),
.\dram_dq[68] (dram_dq[68] ),
.\dram_dq[67] (dram_dq[67] ),
.\dram_dq[66] (dram_dq[66] ),
.\dram_dq[65] (dram_dq[65] ),
.\dram_dq[64] (dram_dq[64] ),
.\dram_dq[31] (dram_dq[31] ),
.\dram_dq[30] (dram_dq[30] ),
.\dram_dq[29] (dram_dq[29] ),
.\dram_dq[28] (dram_dq[28] ),
.\dram_dq[27] (dram_dq[27] ),
.\dram_dq[26] (dram_dq[26] ),
.\dram_dq[25] (dram_dq[25] ),
.\dram_dq[24] (dram_dq[24] ),
.\dram_dq[23] (dram_dq[23] ),
.\dram_dq[22] (dram_dq[22] ),
.\dram_dq[21] (dram_dq[21] ),
.\dram_dq[20] (dram_dq[20] ),
.\dram_dq[19] (dram_dq[19] ),
.\dram_dq[18] (dram_dq[18] ),
.\dram_dq[17] (dram_dq[17] ),
.\dram_dq[16] (dram_dq[16] ),
.\dram_dq[15] (dram_dq[15] ),
.\dram_dq[14] (dram_dq[14] ),
.\dram_dq[13] (dram_dq[13] ),
.\dram_dq[12] (dram_dq[12] ),
.\dram_dq[11] (dram_dq[11] ),
.\dram_dq[10] (dram_dq[10] ),
.\dram_dq[9] (dram_dq[9] ),
.\dram_dq[8] (dram_dq[8] ),
.\dram_dq[7] (dram_dq[7] ),
.\dram_dq[6] (dram_dq[6] ),
.\dram_dq[5] (dram_dq[5] ),
.\dram_dq[4] (dram_dq[4] ),
.\dram_dq[3] (dram_dq[3] ),
.\dram_dq[2] (dram_dq[2] ),
.\dram_dq[1] (dram_dq[1] ),
.\dram_dq[0] (dram_dq[0] ),
.\dram_dqs[3] (dram_dqs[3] ),
.\dram_dqs[2] (dram_dqs[2] ),
.\dram_dqs[1] (dram_dqs[1] ),
.\dram_dqs[0] (dram_dqs[0] ),
.\dram_dqs[21] (dram_dqs[21] ),
.\dram_dqs[20] (dram_dqs[20] ),
.\dram_dqs[19] (dram_dqs[19] ),
.\dram_dqs[18] (dram_dqs[18] ),
.\dram_dqs[17] (dram_dqs[17] ),
.\dram_dqs[30] (dram_dqs[30] ),
.\dram_dqs[29] (dram_dqs[29] ),
.\dram_dqs[28] (dram_dqs[28] ),
.\dram_dqs[27] (dram_dqs[27] ),
.rst_l_i_l (rst_l ),
.arst_l_i_l (dram_arst_l ),
.bypass_enable_i_r (net0196 ),
.hiz_n_i_l (net0202 ),
.shift_dr_i_l (net0200 ),
.mode_ctrl_i_l (net0198 ),
.dram_io_drive_data_i_l (dram_io_drive_data ),
.se_i_l (se ),
.update_dr_i_l (net0199 ),
.clock_dr_i_l (net0201 ),
.\io_dram_data_in[95] (io_dram_data_in[95] ),
.\io_dram_data_in[94] (io_dram_data_in[94] ),
.\io_dram_data_in[93] (io_dram_data_in[93] ),
.\io_dram_data_in[92] (io_dram_data_in[92] ),
.\io_dram_data_in[91] (io_dram_data_in[91] ),
.\io_dram_data_in[90] (io_dram_data_in[90] ),
.\io_dram_data_in[89] (io_dram_data_in[89] ),
.\io_dram_data_in[88] (io_dram_data_in[88] ),
.\io_dram_data_in[87] (io_dram_data_in[87] ),
.\io_dram_data_in[86] (io_dram_data_in[86] ),
.\io_dram_data_in[85] (io_dram_data_in[85] ),
.\io_dram_data_in[84] (io_dram_data_in[84] ),
.\io_dram_data_in[83] (io_dram_data_in[83] ),
.\io_dram_data_in[82] (io_dram_data_in[82] ),
.\io_dram_data_in[81] (io_dram_data_in[81] ),
.\io_dram_data_in[80] (io_dram_data_in[80] ),
.\io_dram_data_in[79] (io_dram_data_in[79] ),
.\io_dram_data_in[78] (io_dram_data_in[78] ),
.\io_dram_data_in[77] (io_dram_data_in[77] ),
.\io_dram_data_in[76] (io_dram_data_in[76] ),
.\io_dram_data_in[75] (io_dram_data_in[75] ),
.\io_dram_data_in[74] (io_dram_data_in[74] ),
.\io_dram_data_in[73] (io_dram_data_in[73] ),
.\io_dram_data_in[72] (io_dram_data_in[72] ),
.\io_dram_data_in[71] (io_dram_data_in[71] ),
.\io_dram_data_in[70] (io_dram_data_in[70] ),
.\io_dram_data_in[69] (io_dram_data_in[69] ),
.\io_dram_data_in[68] (io_dram_data_in[68] ),
.\io_dram_data_in[67] (io_dram_data_in[67] ),
.\io_dram_data_in[66] (io_dram_data_in[66] ),
.\io_dram_data_in[65] (io_dram_data_in[65] ),
.\io_dram_data_in[64] (io_dram_data_in[64] ),
.\dram_io_data_out[239] (dram_io_data_out[239] ),
.\dram_io_data_out[238] (dram_io_data_out[238] ),
.\dram_io_data_out[237] (dram_io_data_out[237] ),
.\dram_io_data_out[236] (dram_io_data_out[236] ),
.\dram_io_data_out[235] (dram_io_data_out[235] ),
.\dram_io_data_out[234] (dram_io_data_out[234] ),
.\dram_io_data_out[233] (dram_io_data_out[233] ),
.\dram_io_data_out[232] (dram_io_data_out[232] ),
.\dram_io_data_out[231] (dram_io_data_out[231] ),
.\dram_io_data_out[230] (dram_io_data_out[230] ),
.\dram_io_data_out[229] (dram_io_data_out[229] ),
.\dram_io_data_out[228] (dram_io_data_out[228] ),
.\dram_io_data_out[227] (dram_io_data_out[227] ),
.\dram_io_data_out[226] (dram_io_data_out[226] ),
.\dram_io_data_out[225] (dram_io_data_out[225] ),
.\dram_io_data_out[224] (dram_io_data_out[224] ),
.\dram_io_data_out[223] (dram_io_data_out[223] ),
.\dram_io_data_out[222] (dram_io_data_out[222] ),
.\dram_io_data_out[221] (dram_io_data_out[221] ),
.\dram_io_data_out[220] (dram_io_data_out[220] ),
.\dram_io_data_out[219] (dram_io_data_out[219] ),
.\dram_io_data_out[218] (dram_io_data_out[218] ),
.\dram_io_data_out[217] (dram_io_data_out[217] ),
.\dram_io_data_out[216] (dram_io_data_out[216] ),
.\dram_io_data_out[215] (dram_io_data_out[215] ),
.\dram_io_data_out[214] (dram_io_data_out[214] ),
.\dram_io_data_out[213] (dram_io_data_out[213] ),
.\dram_io_data_out[212] (dram_io_data_out[212] ),
.\dram_io_data_out[211] (dram_io_data_out[211] ),
.\dram_io_data_out[210] (dram_io_data_out[210] ),
.\dram_io_data_out[209] (dram_io_data_out[209] ),
.\dram_io_data_out[208] (dram_io_data_out[208] ) );
bw_io_ddr_sig_bot I1 (
.arst_l_out (arst_l_out),
.cbd_o_l ({cbd_l } ),
.cbu_o_l ({cbu_l } ),
.cbu_o_r ({net0180[0] ,net0180[1] ,net0180[2] ,net0180[3] ,
net0180[4] ,net0180[5] ,net0180[6] ,net0180[7] } ),
.cbd_o_r ({net0181[0] ,net0181[1] ,net0181[2] ,net0181[3] ,
net0181[4] ,net0181[5] ,net0181[6] ,net0181[7] } ),
.cbd_i_l ({net0126[0] ,net0126[1] ,net0126[2] ,net0126[3] ,
net0126[4] ,net0126[5] ,net0126[6] ,net0126[7] } ),
.cbu_i_r ({net0128[0] ,net0128[1] ,net0128[2] ,net0128[3] ,
net0128[4] ,net0128[5] ,net0128[6] ,net0128[7] } ),
.cbd_i_r ({net0126[0] ,net0126[1] ,net0126[2] ,net0126[3] ,
net0126[4] ,net0126[5] ,net0126[6] ,net0126[7] } ),
.vrefcode_i_l ({net0189[0] ,net0189[1] ,net0189[2] ,net0189[3] ,
net0189[4] ,net0189[5] ,net0189[6] ,net0189[7] } ),
.vrefcode_i_r ({net0189[0] ,net0189[1] ,net0189[2] ,net0189[3] ,
net0189[4] ,net0189[5] ,net0189[6] ,net0189[7] } ),
.serial_in ({serial_in[143:72] } ),
.afo ({afo[143:72] } ),
.serial_out ({serial_out[143:72] } ),
.afi ({afi[143:72] } ),
.spare_ddr_data ({spare_ddr_data[7:0] } ),
.spare_ddr_pin ({spare_ddr_pin[7:0] } ),
.cbu_i_l ({net0128[0] ,net0128[1] ,net0128[2] ,net0128[3] ,
net0128[4] ,net0128[5] ,net0128[6] ,net0128[7] } ),
.dram_io_ptr_clk_inv_i_l ({dram_io_ptr_clk_inv[1:0] } ),
.lpf_code_i_l ({lpf_code } ),
.pad_pos_cnt_i_l ({pad_pos_cnt } ),
.pad_neg_cnt_i_l ({pad_neg_cnt } ),
.dram_cs_l ({dram_cs_l } ),
.dram_cb ({dram_cb[15:8] } ),
.pad_neg_cnt_i_r ({pad_neg_cnt } ),
.dram_io_bank ({dram_io_bank[1:0] } ),
.dram_addr ({dram_addr[10] } ),
.lpf_code_i_r ({lpf_code } ),
.dram_io_ptr_clk_inv_i_r ({dram_io_ptr_clk_inv[1:0] } ),
.dram_io_cs_l ({dram_io_cs_l } ),
.dram_ba ({dram_ba[1:0] } ),
.dram_io_addr ({dram_io_addr[10] } ),
.pad_pos_cnt_i_r ({pad_pos_cnt } ),
.dram_io_drive_enable_o_l (net0207 ),
.se_o_l (se_out ),
.ps_select_i_r (net0212 ),
.test_mode_i_l (test_mode ),
.testmode_l_i_r (testmode_l ),
.test_mode_i_r (test_mode ),
.bypass_enable_i_l (net0213 ),
.bypass_enable_i_r (net0213 ),
.ps_select_i_l (net0212 ),
.update_dr_o_l (net0199 ),
.shift_dr_o_l (net0200 ),
.clock_dr_o_l (net0201 ),
.hiz_n_o_l (net0202 ),
.bypass_enable_o_l (net0203 ),
.ps_select_o_r (net0197 ),
.mode_ctrl_o_r (net0191 ),
.update_dr_o_r (net0192 ),
.se_i_r (se ),
.mode_ctrl_i_r (net0249 ),
.clock_dr_i_r (net0241 ),
.mode_ctrl_o_l (net0198 ),
.hiz_n_i_r (net0247 ),
.update_dr_i_r (net0254 ),
.shift_dr_o_r (net0193 ),
.dram_io_drive_enable_i_r (dram_io_drive_enable ),
.clock_dr_o_r (net0194 ),
.hiz_n_o_r (net0195 ),
.ps_select_o_l (net0204 ),
.rclk (rclk ),
.testmode_l_i_l (testmode_l ),
.burst_length_four_i_l (burst_length_four ),
.dram_io_pad_enable_i_l (dram_io_pad_enable ),
.dram_io_drive_enable_i_l (dram_io_drive_enable ),
.rst_l_i_l (rst_l ),
.arst_l_i_l (dram_arst_l ),
.strobe_i_l (strobe ),
.dram_io_channel_disabled_i_l (dram_io_channel_disabled ),
.dram_io_drive_data_i_l (dram_io_drive_data ),
.dram_io_channel_disabled_i_r (dram_io_channel_disabled ),
.dram_io_write_en_l (dram_io_write_en_l ),
.\dram_io_data_out[63] (dram_io_data_out[63] ),
.\dram_io_data_out[62] (dram_io_data_out[62] ),
.\dram_io_data_out[61] (dram_io_data_out[61] ),
.\dram_io_data_out[60] (dram_io_data_out[60] ),
.\dram_io_data_out[59] (dram_io_data_out[59] ),
.\dram_io_data_out[58] (dram_io_data_out[58] ),
.\dram_io_data_out[57] (dram_io_data_out[57] ),
.\dram_io_data_out[56] (dram_io_data_out[56] ),
.\dram_io_data_out[55] (dram_io_data_out[55] ),
.\dram_io_data_out[54] (dram_io_data_out[54] ),
.\dram_io_data_out[53] (dram_io_data_out[53] ),
.\dram_io_data_out[52] (dram_io_data_out[52] ),
.\dram_io_data_out[51] (dram_io_data_out[51] ),
.\dram_io_data_out[50] (dram_io_data_out[50] ),
.\dram_io_data_out[49] (dram_io_data_out[49] ),
.\dram_io_data_out[48] (dram_io_data_out[48] ),
.\dram_io_data_out[47] (dram_io_data_out[47] ),
.\dram_io_data_out[46] (dram_io_data_out[46] ),
.\dram_io_data_out[45] (dram_io_data_out[45] ),
.\dram_io_data_out[44] (dram_io_data_out[44] ),
.\dram_io_data_out[43] (dram_io_data_out[43] ),
.\dram_io_data_out[42] (dram_io_data_out[42] ),
.\dram_io_data_out[41] (dram_io_data_out[41] ),
.\dram_io_data_out[40] (dram_io_data_out[40] ),
.\dram_io_data_out[39] (dram_io_data_out[39] ),
.\dram_io_data_out[38] (dram_io_data_out[38] ),
.\dram_io_data_out[37] (dram_io_data_out[37] ),
.\dram_io_data_out[36] (dram_io_data_out[36] ),
.\dram_io_data_out[35] (dram_io_data_out[35] ),
.\dram_io_data_out[34] (dram_io_data_out[34] ),
.\dram_io_data_out[33] (dram_io_data_out[33] ),
.\dram_io_data_out[32] (dram_io_data_out[32] ),
.\io_dram_data_in[255] (io_dram_data_in[255] ),
.\io_dram_data_in[254] (io_dram_data_in[254] ),
.\io_dram_data_in[253] (io_dram_data_in[253] ),
.\io_dram_data_in[252] (io_dram_data_in[252] ),
.\io_dram_data_in[251] (io_dram_data_in[251] ),
.\io_dram_data_in[250] (io_dram_data_in[250] ),
.\io_dram_data_in[249] (io_dram_data_in[249] ),
.\io_dram_data_in[248] (io_dram_data_in[248] ),
.\io_dram_data_in[247] (io_dram_data_in[247] ),
.\io_dram_data_in[246] (io_dram_data_in[246] ),
.\io_dram_data_in[245] (io_dram_data_in[245] ),
.\io_dram_data_in[244] (io_dram_data_in[244] ),
.\io_dram_data_in[243] (io_dram_data_in[243] ),
.\io_dram_data_in[242] (io_dram_data_in[242] ),
.\io_dram_data_in[241] (io_dram_data_in[241] ),
.\io_dram_data_in[240] (io_dram_data_in[240] ),
.\io_dram_data_in[239] (io_dram_data_in[239] ),
.\io_dram_data_in[238] (io_dram_data_in[238] ),
.\io_dram_data_in[237] (io_dram_data_in[237] ),
.\io_dram_data_in[236] (io_dram_data_in[236] ),
.\io_dram_data_in[235] (io_dram_data_in[235] ),
.\io_dram_data_in[234] (io_dram_data_in[234] ),
.\io_dram_data_in[233] (io_dram_data_in[233] ),
.\io_dram_data_in[232] (io_dram_data_in[232] ),
.\io_dram_data_in[231] (io_dram_data_in[231] ),
.\io_dram_data_in[230] (io_dram_data_in[230] ),
.\io_dram_data_in[229] (io_dram_data_in[229] ),
.\io_dram_data_in[228] (io_dram_data_in[228] ),
.\io_dram_data_in[227] (io_dram_data_in[227] ),
.\io_dram_data_in[226] (io_dram_data_in[226] ),
.\io_dram_data_in[225] (io_dram_data_in[225] ),
.\io_dram_data_in[224] (io_dram_data_in[224] ),
.dram_io_cas_l (dram_io_cas_l ),
.dram_we_l (dram_we_l ),
.dram_cas_l (dram_cas_l ),
.\dram_dq[127] (dram_dq[127] ),
.\dram_dq[126] (dram_dq[126] ),
.\dram_dq[125] (dram_dq[125] ),
.\dram_dq[124] (dram_dq[124] ),
.\dram_dq[123] (dram_dq[123] ),
.\dram_dq[122] (dram_dq[122] ),
.\dram_dq[121] (dram_dq[121] ),
.\dram_dq[120] (dram_dq[120] ),
.\dram_dq[119] (dram_dq[119] ),
.\dram_dq[118] (dram_dq[118] ),
.\dram_dq[117] (dram_dq[117] ),
.\dram_dq[116] (dram_dq[116] ),
.\dram_dq[115] (dram_dq[115] ),
.\dram_dq[114] (dram_dq[114] ),
.\dram_dq[113] (dram_dq[113] ),
.\dram_dq[112] (dram_dq[112] ),
.\dram_dq[111] (dram_dq[111] ),
.\dram_dq[110] (dram_dq[110] ),
.\dram_dq[109] (dram_dq[109] ),
.\dram_dq[108] (dram_dq[108] ),
.\dram_dq[107] (dram_dq[107] ),
.\dram_dq[106] (dram_dq[106] ),
.\dram_dq[105] (dram_dq[105] ),
.\dram_dq[104] (dram_dq[104] ),
.\dram_dq[103] (dram_dq[103] ),
.\dram_dq[102] (dram_dq[102] ),
.\dram_dq[101] (dram_dq[101] ),
.\dram_dq[100] (dram_dq[100] ),
.\dram_dq[99] (dram_dq[99] ),
.\dram_dq[98] (dram_dq[98] ),
.\dram_dq[97] (dram_dq[97] ),
.\dram_dq[96] (dram_dq[96] ),
.\dram_io_data_out[287] (dram_io_data_out[287] ),
.\dram_io_data_out[286] (dram_io_data_out[286] ),
.\dram_io_data_out[285] (dram_io_data_out[285] ),
.\dram_io_data_out[284] (dram_io_data_out[284] ),
.\dram_io_data_out[283] (dram_io_data_out[283] ),
.\dram_io_data_out[282] (dram_io_data_out[282] ),
.\dram_io_data_out[281] (dram_io_data_out[281] ),
.\dram_io_data_out[280] (dram_io_data_out[280] ),
.\dram_io_data_out[143] (dram_io_data_out[143] ),
.\dram_io_data_out[142] (dram_io_data_out[142] ),
.\dram_io_data_out[141] (dram_io_data_out[141] ),
.\dram_io_data_out[140] (dram_io_data_out[140] ),
.\dram_io_data_out[139] (dram_io_data_out[139] ),
.\dram_io_data_out[138] (dram_io_data_out[138] ),
.\dram_io_data_out[137] (dram_io_data_out[137] ),
.\dram_io_data_out[136] (dram_io_data_out[136] ),
.\io_dram_ecc_in[31] (io_dram_ecc_in[31] ),
.\io_dram_ecc_in[30] (io_dram_ecc_in[30] ),
.\io_dram_ecc_in[29] (io_dram_ecc_in[29] ),
.\io_dram_ecc_in[28] (io_dram_ecc_in[28] ),
.\io_dram_ecc_in[27] (io_dram_ecc_in[27] ),
.\io_dram_ecc_in[26] (io_dram_ecc_in[26] ),
.\io_dram_ecc_in[25] (io_dram_ecc_in[25] ),
.\io_dram_ecc_in[24] (io_dram_ecc_in[24] ),
.\io_dram_ecc_in[15] (io_dram_ecc_in[15] ),
.\io_dram_ecc_in[14] (io_dram_ecc_in[14] ),
.\io_dram_ecc_in[13] (io_dram_ecc_in[13] ),
.\io_dram_ecc_in[12] (io_dram_ecc_in[12] ),
.\io_dram_ecc_in[11] (io_dram_ecc_in[11] ),
.\io_dram_ecc_in[10] (io_dram_ecc_in[10] ),
.\io_dram_ecc_in[9] (io_dram_ecc_in[9] ),
.\io_dram_ecc_in[8] (io_dram_ecc_in[8] ),
.\dram_io_data_out[127] (dram_io_data_out[127] ),
.\dram_io_data_out[126] (dram_io_data_out[126] ),
.\dram_io_data_out[125] (dram_io_data_out[125] ),
.\dram_io_data_out[124] (dram_io_data_out[124] ),
.\dram_io_data_out[123] (dram_io_data_out[123] ),
.\dram_io_data_out[122] (dram_io_data_out[122] ),
.\dram_io_data_out[121] (dram_io_data_out[121] ),
.\dram_io_data_out[120] (dram_io_data_out[120] ),
.\dram_io_data_out[119] (dram_io_data_out[119] ),
.\dram_io_data_out[118] (dram_io_data_out[118] ),
.\dram_io_data_out[117] (dram_io_data_out[117] ),
.\dram_io_data_out[116] (dram_io_data_out[116] ),
.\dram_io_data_out[115] (dram_io_data_out[115] ),
.\dram_io_data_out[114] (dram_io_data_out[114] ),
.\dram_io_data_out[113] (dram_io_data_out[113] ),
.\dram_io_data_out[112] (dram_io_data_out[112] ),
.\dram_io_data_out[111] (dram_io_data_out[111] ),
.\dram_io_data_out[110] (dram_io_data_out[110] ),
.\dram_io_data_out[109] (dram_io_data_out[109] ),
.\dram_io_data_out[108] (dram_io_data_out[108] ),
.\dram_io_data_out[107] (dram_io_data_out[107] ),
.\dram_io_data_out[106] (dram_io_data_out[106] ),
.\dram_io_data_out[105] (dram_io_data_out[105] ),
.\dram_io_data_out[104] (dram_io_data_out[104] ),
.\dram_io_data_out[103] (dram_io_data_out[103] ),
.\dram_io_data_out[102] (dram_io_data_out[102] ),
.\dram_io_data_out[101] (dram_io_data_out[101] ),
.\dram_io_data_out[100] (dram_io_data_out[100] ),
.\dram_io_data_out[99] (dram_io_data_out[99] ),
.\dram_io_data_out[98] (dram_io_data_out[98] ),
.\dram_io_data_out[97] (dram_io_data_out[97] ),
.\dram_io_data_out[96] (dram_io_data_out[96] ),
.\io_dram_data_in[191] (io_dram_data_in[191] ),
.\io_dram_data_in[190] (io_dram_data_in[190] ),
.\io_dram_data_in[189] (io_dram_data_in[189] ),
.\io_dram_data_in[188] (io_dram_data_in[188] ),
.\io_dram_data_in[187] (io_dram_data_in[187] ),
.\io_dram_data_in[186] (io_dram_data_in[186] ),
.\io_dram_data_in[185] (io_dram_data_in[185] ),
.\io_dram_data_in[184] (io_dram_data_in[184] ),
.\io_dram_data_in[183] (io_dram_data_in[183] ),
.\io_dram_data_in[182] (io_dram_data_in[182] ),
.\io_dram_data_in[181] (io_dram_data_in[181] ),
.\io_dram_data_in[180] (io_dram_data_in[180] ),
.\io_dram_data_in[179] (io_dram_data_in[179] ),
.\io_dram_data_in[178] (io_dram_data_in[178] ),
.\io_dram_data_in[177] (io_dram_data_in[177] ),
.\io_dram_data_in[176] (io_dram_data_in[176] ),
.\io_dram_data_in[175] (io_dram_data_in[175] ),
.\io_dram_data_in[174] (io_dram_data_in[174] ),
.\io_dram_data_in[173] (io_dram_data_in[173] ),
.\io_dram_data_in[172] (io_dram_data_in[172] ),
.\io_dram_data_in[171] (io_dram_data_in[171] ),
.\io_dram_data_in[170] (io_dram_data_in[170] ),
.\io_dram_data_in[169] (io_dram_data_in[169] ),
.\io_dram_data_in[168] (io_dram_data_in[168] ),
.\io_dram_data_in[167] (io_dram_data_in[167] ),
.\io_dram_data_in[166] (io_dram_data_in[166] ),
.\io_dram_data_in[165] (io_dram_data_in[165] ),
.\io_dram_data_in[164] (io_dram_data_in[164] ),
.\io_dram_data_in[163] (io_dram_data_in[163] ),
.\io_dram_data_in[162] (io_dram_data_in[162] ),
.\io_dram_data_in[161] (io_dram_data_in[161] ),
.\io_dram_data_in[160] (io_dram_data_in[160] ),
.rst_l_i_r (rst_l ),
.arst_l_i_r (dram_arst_l ),
.\io_dram_data_in[127] (io_dram_data_in[127] ),
.\io_dram_data_in[126] (io_dram_data_in[126] ),
.\io_dram_data_in[125] (io_dram_data_in[125] ),
.\io_dram_data_in[124] (io_dram_data_in[124] ),
.\io_dram_data_in[123] (io_dram_data_in[123] ),
.\io_dram_data_in[122] (io_dram_data_in[122] ),
.\io_dram_data_in[121] (io_dram_data_in[121] ),
.\io_dram_data_in[120] (io_dram_data_in[120] ),
.\io_dram_data_in[119] (io_dram_data_in[119] ),
.\io_dram_data_in[118] (io_dram_data_in[118] ),
.\io_dram_data_in[117] (io_dram_data_in[117] ),
.\io_dram_data_in[116] (io_dram_data_in[116] ),
.\io_dram_data_in[115] (io_dram_data_in[115] ),
.\io_dram_data_in[114] (io_dram_data_in[114] ),
.\io_dram_data_in[113] (io_dram_data_in[113] ),
.\io_dram_data_in[112] (io_dram_data_in[112] ),
.\io_dram_data_in[111] (io_dram_data_in[111] ),
.\io_dram_data_in[110] (io_dram_data_in[110] ),
.\io_dram_data_in[109] (io_dram_data_in[109] ),
.\io_dram_data_in[108] (io_dram_data_in[108] ),
.\io_dram_data_in[107] (io_dram_data_in[107] ),
.\io_dram_data_in[106] (io_dram_data_in[106] ),
.\io_dram_data_in[105] (io_dram_data_in[105] ),
.\io_dram_data_in[104] (io_dram_data_in[104] ),
.\io_dram_data_in[103] (io_dram_data_in[103] ),
.\io_dram_data_in[102] (io_dram_data_in[102] ),
.\io_dram_data_in[101] (io_dram_data_in[101] ),
.\io_dram_data_in[100] (io_dram_data_in[100] ),
.\io_dram_data_in[99] (io_dram_data_in[99] ),
.\io_dram_data_in[98] (io_dram_data_in[98] ),
.\io_dram_data_in[97] (io_dram_data_in[97] ),
.\io_dram_data_in[96] (io_dram_data_in[96] ),
.pad_clk_si (plogic_clk_so1_pad_si2 ),
.dram_ras_l (dram_ras_l ),
.dram_io_pad_enable_i_r (dram_io_pad_enable ),
.\dram_io_data_out[271] (dram_io_data_out[271] ),
.\dram_io_data_out[270] (dram_io_data_out[270] ),
.\dram_io_data_out[269] (dram_io_data_out[269] ),
.\dram_io_data_out[268] (dram_io_data_out[268] ),
.\dram_io_data_out[267] (dram_io_data_out[267] ),
.\dram_io_data_out[266] (dram_io_data_out[266] ),
.\dram_io_data_out[265] (dram_io_data_out[265] ),
.\dram_io_data_out[264] (dram_io_data_out[264] ),
.\dram_io_data_out[263] (dram_io_data_out[263] ),
.\dram_io_data_out[262] (dram_io_data_out[262] ),
.\dram_io_data_out[261] (dram_io_data_out[261] ),
.\dram_io_data_out[260] (dram_io_data_out[260] ),
.\dram_io_data_out[259] (dram_io_data_out[259] ),
.\dram_io_data_out[258] (dram_io_data_out[258] ),
.\dram_io_data_out[257] (dram_io_data_out[257] ),
.\dram_io_data_out[256] (dram_io_data_out[256] ),
.\dram_io_data_out[255] (dram_io_data_out[255] ),
.\dram_io_data_out[254] (dram_io_data_out[254] ),
.\dram_io_data_out[253] (dram_io_data_out[253] ),
.\dram_io_data_out[252] (dram_io_data_out[252] ),
.\dram_io_data_out[251] (dram_io_data_out[251] ),
.\dram_io_data_out[250] (dram_io_data_out[250] ),
.\dram_io_data_out[249] (dram_io_data_out[249] ),
.\dram_io_data_out[248] (dram_io_data_out[248] ),
.\dram_io_data_out[247] (dram_io_data_out[247] ),
.\dram_io_data_out[246] (dram_io_data_out[246] ),
.\dram_io_data_out[245] (dram_io_data_out[245] ),
.\dram_io_data_out[244] (dram_io_data_out[244] ),
.\dram_io_data_out[243] (dram_io_data_out[243] ),
.\dram_io_data_out[242] (dram_io_data_out[242] ),
.\dram_io_data_out[241] (dram_io_data_out[241] ),
.\dram_io_data_out[240] (dram_io_data_out[240] ),
.mode_ctrl_i_l (net0249 ),
.\dram_dqs[7] (dram_dqs[7] ),
.\dram_dqs[6] (dram_dqs[6] ),
.\dram_dqs[5] (dram_dqs[5] ),
.\dram_dqs[4] (dram_dqs[4] ),
.bsi (bso0_bsi1 ),
.bso (bso_pre_latch ),
.burst_length_four_i_r (burst_length_four ),
.strobe_i_r (strobe ),
.update_dr_i_l (net0254 ),
.hiz_n_i_l (net0247 ),
.clock_dr_i_l (net0241 ),
.shift_dr_i_l (net0253 ),
.se_i_l (se ),
.pad_clk_so (bot_so_pvt_si ),
.dram_io_ras_l (dram_io_ras_l ),
.\dram_dq[63] (dram_dq[63] ),
.\dram_dq[62] (dram_dq[62] ),
.\dram_dq[61] (dram_dq[61] ),
.\dram_dq[60] (dram_dq[60] ),
.\dram_dq[59] (dram_dq[59] ),
.\dram_dq[58] (dram_dq[58] ),
.\dram_dq[57] (dram_dq[57] ),
.\dram_dq[56] (dram_dq[56] ),
.\dram_dq[55] (dram_dq[55] ),
.\dram_dq[54] (dram_dq[54] ),
.\dram_dq[53] (dram_dq[53] ),
.\dram_dq[52] (dram_dq[52] ),
.\dram_dq[51] (dram_dq[51] ),
.\dram_dq[50] (dram_dq[50] ),
.\dram_dq[49] (dram_dq[49] ),
.\dram_dq[48] (dram_dq[48] ),
.\dram_dq[47] (dram_dq[47] ),
.\dram_dq[46] (dram_dq[46] ),
.\dram_dq[45] (dram_dq[45] ),
.\dram_dq[44] (dram_dq[44] ),
.\dram_dq[43] (dram_dq[43] ),
.\dram_dq[42] (dram_dq[42] ),
.\dram_dq[41] (dram_dq[41] ),
.\dram_dq[40] (dram_dq[40] ),
.\dram_dq[39] (dram_dq[39] ),
.\dram_dq[38] (dram_dq[38] ),
.\dram_dq[37] (dram_dq[37] ),
.\dram_dq[36] (dram_dq[36] ),
.\dram_dq[35] (dram_dq[35] ),
.\dram_dq[34] (dram_dq[34] ),
.\dram_dq[33] (dram_dq[33] ),
.\dram_dq[32] (dram_dq[32] ),
.\dram_dqs[35] (dram_dqs[35] ),
.\dram_dqs[34] (dram_dqs[34] ),
.\dram_dqs[33] (dram_dqs[33] ),
.\dram_dqs[32] (dram_dqs[32] ),
.\dram_dqs[31] (dram_dqs[31] ),
.\dram_dqs[16] (dram_dqs[16] ),
.\dram_dqs[15] (dram_dqs[15] ),
.\dram_dqs[14] (dram_dqs[14] ),
.\dram_dqs[13] (dram_dqs[13] ),
.\dram_dqs[26] (dram_dqs[26] ),
.\dram_dqs[25] (dram_dqs[25] ),
.\dram_dqs[24] (dram_dqs[24] ),
.\dram_dqs[23] (dram_dqs[23] ),
.\dram_dqs[22] (dram_dqs[22] ),
.dram_io_drive_data_i_r (dram_io_drive_data ),
.shift_dr_i_r (net0253 ),
.bypass_enable_o_r (net0196 ),
.vdd_h (vdd_h ),
.\io_dram_data_in[63] (io_dram_data_in[63] ),
.\io_dram_data_in[62] (io_dram_data_in[62] ),
.\io_dram_data_in[61] (io_dram_data_in[61] ),
.\io_dram_data_in[60] (io_dram_data_in[60] ),
.\io_dram_data_in[59] (io_dram_data_in[59] ),
.\io_dram_data_in[58] (io_dram_data_in[58] ),
.\io_dram_data_in[57] (io_dram_data_in[57] ),
.\io_dram_data_in[56] (io_dram_data_in[56] ),
.\io_dram_data_in[55] (io_dram_data_in[55] ),
.\io_dram_data_in[54] (io_dram_data_in[54] ),
.\io_dram_data_in[53] (io_dram_data_in[53] ),
.\io_dram_data_in[52] (io_dram_data_in[52] ),
.\io_dram_data_in[51] (io_dram_data_in[51] ),
.\io_dram_data_in[50] (io_dram_data_in[50] ),
.\io_dram_data_in[49] (io_dram_data_in[49] ),
.\io_dram_data_in[48] (io_dram_data_in[48] ),
.\io_dram_data_in[47] (io_dram_data_in[47] ),
.\io_dram_data_in[46] (io_dram_data_in[46] ),
.\io_dram_data_in[45] (io_dram_data_in[45] ),
.\io_dram_data_in[44] (io_dram_data_in[44] ),
.\io_dram_data_in[43] (io_dram_data_in[43] ),
.\io_dram_data_in[42] (io_dram_data_in[42] ),
.\io_dram_data_in[41] (io_dram_data_in[41] ),
.\io_dram_data_in[40] (io_dram_data_in[40] ),
.\io_dram_data_in[39] (io_dram_data_in[39] ),
.\io_dram_data_in[38] (io_dram_data_in[38] ),
.\io_dram_data_in[37] (io_dram_data_in[37] ),
.\io_dram_data_in[36] (io_dram_data_in[36] ),
.\io_dram_data_in[35] (io_dram_data_in[35] ),
.\io_dram_data_in[34] (io_dram_data_in[34] ),
.\io_dram_data_in[33] (io_dram_data_in[33] ),
.\io_dram_data_in[32] (io_dram_data_in[32] ),
.\dram_io_data_out[207] (dram_io_data_out[207] ),
.\dram_io_data_out[206] (dram_io_data_out[206] ),
.\dram_io_data_out[205] (dram_io_data_out[205] ),
.\dram_io_data_out[204] (dram_io_data_out[204] ),
.\dram_io_data_out[203] (dram_io_data_out[203] ),
.\dram_io_data_out[202] (dram_io_data_out[202] ),
.\dram_io_data_out[201] (dram_io_data_out[201] ),
.\dram_io_data_out[200] (dram_io_data_out[200] ),
.\dram_io_data_out[199] (dram_io_data_out[199] ),
.\dram_io_data_out[198] (dram_io_data_out[198] ),
.\dram_io_data_out[197] (dram_io_data_out[197] ),
.\dram_io_data_out[196] (dram_io_data_out[196] ),
.\dram_io_data_out[195] (dram_io_data_out[195] ),
.\dram_io_data_out[194] (dram_io_data_out[194] ),
.\dram_io_data_out[193] (dram_io_data_out[193] ),
.\dram_io_data_out[192] (dram_io_data_out[192] ),
.\dram_io_data_out[191] (dram_io_data_out[191] ),
.\dram_io_data_out[190] (dram_io_data_out[190] ),
.\dram_io_data_out[189] (dram_io_data_out[189] ),
.\dram_io_data_out[188] (dram_io_data_out[188] ),
.\dram_io_data_out[187] (dram_io_data_out[187] ),
.\dram_io_data_out[186] (dram_io_data_out[186] ),
.\dram_io_data_out[185] (dram_io_data_out[185] ),
.\dram_io_data_out[184] (dram_io_data_out[184] ),
.\dram_io_data_out[183] (dram_io_data_out[183] ),
.\dram_io_data_out[182] (dram_io_data_out[182] ),
.\dram_io_data_out[181] (dram_io_data_out[181] ),
.\dram_io_data_out[180] (dram_io_data_out[180] ),
.\dram_io_data_out[179] (dram_io_data_out[179] ),
.\dram_io_data_out[178] (dram_io_data_out[178] ),
.\dram_io_data_out[177] (dram_io_data_out[177] ),
.\dram_io_data_out[176] (dram_io_data_out[176] ) );
dram_pad_logic I9 (
.pad_neg_cnt ({pad_neg_cnt } ),
.pad_pos_cnt ({pad_pos_cnt } ),
.testmode_l (testmode_l ),
.pad_logic_clk_se (se ),
.pad_logic_clk_si (pad_clk_so0_plogic_si1 ),
.dram_io_pad_clk_inv (dram_io_pad_clk_inv ),
.dram_io_pad_enable (dram_io_pad_enable ),
.burst_length_four (burst_length_four ),
.clk (net0173 ),
.io_dram_data_valid (io_dram_data_valid ),
.arst_l (dram_arst_l ),
.rst_l (rst_l ),
.pad_logic_clk_so (plogic_clk_so1_pad_si2 ) );
bw_u1_buf_15x I140 (
.z (net0249 ),
.a (mode_ctrl_in ) );
bw_u1_buf_15x I141 (
.z (net0254 ),
.a (update_dr_in ) );
bw_u1_buf_15x I142 (
.z (net0253 ),
.a (shift_dr_in ) );
bw_u1_buf_15x I143 (
.z (net0241 ),
.a (clock_dr_in ) );
bw_u1_buf_15x I144 (
.z (net0247 ),
.a (hiz_n_in ) );
bw_u1_buf_15x I145 (
.z (net0213 ),
.a (bypass_enable_in ) );
bw_u1_buf_15x I146 (
.z (net0212 ),
.a (ps_select_in ) );
bw_u1_buf_15x I155 (
.z (shift_dr_out ),
.a (net0304 ) );
bw_u1_buf_15x I156 (
.z (mode_ctrl_out ),
.a (net0306 ) );
bw_u1_buf_15x I157 (
.z (bypass_enable_out ),
.a (net0301 ) );
bw_u1_buf_15x I158 (
.z (clock_dr_out ),
.a (net0303 ) );
bw_u1_buf_15x I159 (
.z (update_dr_out ),
.a (net0305 ) );
bw_u1_buf_15x I160 (
.z (hiz_n_out ),
.a (net0302 ) );
bw_u1_buf_15x I161 (
.z (ps_select_out ),
.a (net0300 ) );
bw_io_ddr_vref_logic I177 (
.vrefcode ({net0189[0] ,net0189[1] ,net0189[2] ,net0189[3] ,
net0189[4] ,net0189[5] ,net0189[6] ,net0189[7] } ),
.a (dram_io_ptr_clk_inv[2] ),
.c (dram_io_ptr_clk_inv[4] ),
.b (dram_io_ptr_clk_inv[3] ),
.vdd18 (vdd_h ) );
bw_io_ddr_pvt_enable I186 (
.cbd_in ({cbd } ),
.cbu_in ({cbu } ),
.cbu_out ({net0128[0] ,net0128[1] ,net0128[2] ,net0128[3] ,
net0128[4] ,net0128[5] ,net0128[6] ,net0128[7] } ),
.cbd_out ({net0126[0] ,net0126[1] ,net0126[2] ,net0126[3] ,
net0126[4] ,net0126[5] ,net0126[6] ,net0126[7] } ),
.si (bot_so_pvt_si ),
.en (net0207 ),
.rclk (rclk ),
.se (se_out ),
.so (pad_clk_so ) );
bw_u1_ckbuf_6x I124 (
.clk (net0173 ),
.rclk (rclk ) );
bw_u1_scanl_2x lockup_latch(
.so(bso),
.sd(bso_pre_latch),
.ck(clock_dr_in));
endmodule
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axis to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_axi2vector #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
// payloads
output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload,
output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload,
input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload,
output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload,
input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_0_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;
assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;
assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;
assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;
assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];
assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;
assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;
assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];
assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize;
assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;
assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;
assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen;
assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock;
assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid;
assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos;
assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid;
end
else begin : gen_no_axi3_wid_packing
end
assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];
assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize;
assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;
assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;
assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen;
assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock;
assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid;
assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos;
assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];
assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;
assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;
end
else begin : gen_no_region_signals
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;
assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser;
assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];
assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;
assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];
end
else begin : gen_no_user_signals
assign s_axi_buser = 'b0;
assign s_axi_ruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign s_axi_bid = 'b0;
assign s_axi_buser = 'b0;
assign s_axi_rlast = 1'b1;
assign s_axi_rid = 'b0;
assign s_axi_ruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
// Copyright 2011, 2012 Frederic Requin
//
// This file is part of the MCC216 project
//
// J68 is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// J68 is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// The J68 core:
// -------------
// Simple re-implementation of the MC68000 CPU
// The core has the following characteristics:
// - Tested on a Cyclone III (90 MHz) and a Stratix II (180 MHz)
// - from 1500 (~70 MHz) to 1900 LEs (~90 MHz)
// - 2048 x 20-bit microcode ROM
// - 256 x 28-bit decode ROM
// - 2 x block RAM for the data and instruction stacks
// - stack based CPU with forth-like microcode
// - not cycle-exact : needs a frequency ~3 x higher
// - all 68000 instructions are implemented
// - all 68000 exceptions are implemented
`timescale 1 ns / 1 ns
module j68
(
// Clock and reset
input rst, // CPU reset
input clk, // CPU clock
// Bus interface
output rd_ena, // Read strobe
output wr_ena, // Write strobe
input data_ack, // Data acknowledge
output [1:0] byte_ena, // Byte enable
output [31:0] address, // Address bus
input [15:0] rd_data, // Data bus in
output [15:0] wr_data, // Data bus out
// 68000 control
output [2:0] fc, // Function code
input [2:0] ipl_n, // Interrupt level
// 68000 debug
output [3:0] dbg_reg_addr, // Register address
output [3:0] dbg_reg_wren, // Register write enable
output [15:0] dbg_reg_data, // Register write data
output [15:0] dbg_sr_reg, // Status register
output [31:0] dbg_pc_reg, // Program counter
output [31:0] dbg_usp_reg, // User stack pointer
output [31:0] dbg_ssp_reg, // Supervisor stack pointer
output [31:0] dbg_vbr_reg, // Vector base register
output [7:0] dbg_cycles, // Cycles used
output dbg_ifetch // Instruction fetch
);
// ALU operations
`define ALU_ADD 5'b00000
`define ALU_ADDC 5'b00001
`define ALU_SUB 5'b00010
`define ALU_SUBC 5'b00011
`define ALU_AND 5'b00100
`define ALU_BAND 5'b10100
`define ALU_OR 5'b00101
`define ALU_BOR 5'b10101
`define ALU_XOR 5'b00110
`define ALU_BXOR 5'b10110
`define ALU_NOT 5'b00111
`define ALU_BNOT 5'b10111
`define ALU_SHL 5'b01000
`define ALU_SHR 5'b01100
`define ALU_DIV 5'b01110
`define ALU_MUL 5'b01111
// ALU inputs
`define A_ADD_ZERO 2'b00
`define A_ADD_T 2'b10
`define A_ADD_NOT_T 2'b11
`define B_ADD_ZERO 2'b00
`define B_ADD_N 2'b10
`define B_ADD_NOT_N 2'b11
`define A_LOG_ZERO 2'b00
`define A_LOG_IMM 2'b01
`define A_LOG_T 2'b10
`define A_LOG_RAM 2'b11
`define B_LOG_ZERO 2'b00
`define B_LOG_IO 2'b01
`define B_LOG_N 2'b10
`define B_LOG_NOT_N 2'b11
reg r_rst_dly; // Delayed reset signal
wire [19:0] w_inst_in; // Internal RAM instruction read
wire w_ram_rd; // Internal RAM read
reg r_ram_rd; // Internal RAM read (delayed)
wire w_ram_wr; // Internal RAM write
wire [1:0] w_ram_bena; // Internal RAM byte enable
wire [10:0] w_ram_addr; // Internal RAM address
wire [15:0] w_ram_din; // Internal RAM data write
wire [15:0] w_ram_dout; // Internal RAM data read
wire w_ram_rdy; // RAM data ready
wire w_reg_wr; // CPU register write
wire [1:0] w_reg_bena; // CPU register byte enable
wire [10:0] w_reg_addr; // CPU register address
reg [11:0] w_alu_c; // ALU control (wire)
reg [10:0] w_flg_c; // Flags control (wire)
reg [3:0] w_cin_c; // Carry in control (wire)
reg [3:0] r_ds_ptr; // Data stack pointer (reg)
reg [3:0] w_ds_nxt; // Next data stack pointer (wire)
wire [3:0] w_ds_inc; // Data stack pointer increment (wire)
reg [15:0] r_ds[0:15]; // Data stack (regs)
reg [15:0] r_ds_T; // Data stack output T (reg)
wire [15:0] w_ds_N; // Data stack output N (wire)
wire [31:0] w_ds_R; // Data stack input : ALU result (wire)
reg w_ds_wr; // Data stack write enable (wire)
wire w_ifetch; // Fetch next instruction
wire [10:0] w_pc_inc; // PC value incremented by 1 (wire)
reg [10:0] r_pc_reg; // PC register (reg)
reg [10:0] w_pc_nxt; // Next PC value (wire)
wire [10:0] w_pc_loop; // PC value for loop (wire)
reg [3:0] r_rs_ptr; // Return stack pointer (reg)
reg [3:0] w_rs_nxt; // Next return stack pointer (wire)
reg [10:0] r_rs[0:15]; // Return stack (regs)
wire [10:0] w_rs_q; // Return stack output (wire)
reg [10:0] w_rs_d; // Return stack input (wire)
reg w_rs_wr; // Return stack write enable (wire)
reg w_rs_rd; // Return stack read enable (wire)
// Micro-instruction decode
wire w_io_op = (w_inst_in[19:17] == 3'b100) ? 1'b1 : 1'b0;
wire w_reg_op = (w_inst_in[19:17] == 3'b101) ? 1'b1 : 1'b0;
wire w_t_mode = (w_inst_in[15:12] == 4'b1111) ? 1'b1 : 1'b0;
wire w_branch;
wire [3:0] w_loop_cnt;
wire w_loop;
wire w_skip;
// ALU <-> Flags
wire [31:0] w_res;
wire [3:0] w_alu;
wire [1:0] w_size;
wire [4:0] w_c_flg;
wire [5:0] w_v_flg;
wire [10:0] w_sr;
wire [4:0] w_ccr;
wire w_c_in;
wire w_z_flg;
wire w_g_flg;
// Memory access
wire w_io_rd; // I/O register read
wire w_io_wr; // I/O register write
wire w_io_ext; // External memory access
wire w_io_rdy; // I/O data ready
wire w_io_end; // End of I/O cycle
wire [15:0] w_io_din; // I/O data input
wire [10:0] w_io_flg_c; // Flag control (for SR write)
// M68k instruction decoder
wire [15:0] w_insw; // Instruction word
wire [15:0] w_extw; // Extension word
wire [15:0] w_ea1b; // Effective address #1 bitfield
// Debug
reg [31:0] r_usp_reg;
reg [31:0] r_ssp_reg;
reg [7:0] r_cycles;
// Delayed reset
always@(posedge clk)
r_rst_dly <= rst;
// RAM access
assign w_ram_rd = w_reg_op & w_inst_in[7] & ~w_ram_rdy;
assign w_ram_addr = w_reg_addr;
assign w_ram_bena = w_reg_bena & { w_reg_wr, w_reg_wr };
assign w_ram_din = r_ds_T;
assign w_ram_rdy = (w_reg_op & w_inst_in[6]) | r_ram_rd;
always@(posedge clk)
r_ram_rd <= w_ram_rd;
// Debug
assign dbg_reg_addr = (w_reg_wr) ? w_reg_addr[4:1] : 4'b0000;
assign dbg_reg_wren[3] = w_reg_wr & w_reg_addr[5] & w_reg_addr[0] & w_reg_bena[1];
assign dbg_reg_wren[2] = w_reg_wr & w_reg_addr[5] & w_reg_addr[0] & w_reg_bena[0];
assign dbg_reg_wren[1] = w_reg_wr & w_reg_addr[5] & ~w_reg_addr[0] & w_reg_bena[1];
assign dbg_reg_wren[0] = w_reg_wr & w_reg_addr[5] & ~w_reg_addr[0] & w_reg_bena[0];
assign dbg_reg_data = (w_reg_wr) ? r_ds_T : 16'h0000;
assign dbg_sr_reg = { (w_sr & 11'b1010_0111_000) , w_ccr};
assign dbg_usp_reg = r_usp_reg;
assign dbg_ssp_reg = r_ssp_reg;
assign dbg_vbr_reg = 32'h00000000;
assign dbg_cycles = r_cycles;
always @(posedge rst or posedge clk)
begin
if (rst) begin
r_usp_reg <= 32'd0;
r_ssp_reg <= 32'd0;
r_cycles <= 8'd0;
end else begin
if (w_reg_wr) begin
// USP low word
if ((w_reg_addr[5:0] == 6'b011100) ||
((w_reg_addr[5:0] == 6'b111110) && (!w_sr[8])))
r_usp_reg[15:0] <= r_ds_T;
// USP high word
if ((w_reg_addr[5:0] == 6'b011101) ||
((w_reg_addr[5:0] == 6'b111111) && (!w_sr[8])))
r_usp_reg[31:16] <= r_ds_T;
// SSP low word
if ((w_reg_addr[5:0] == 6'b011110) ||
((w_reg_addr[5:0] == 6'b111110) && (w_sr[8])))
r_ssp_reg[15:0] <= r_ds_T;
// SSP high word
if ((w_reg_addr[5:0] == 6'b011111) ||
((w_reg_addr[5:0] == 6'b111111) && (w_sr[8])))
r_ssp_reg[31:16] <= r_ds_T;
end
if (dbg_ifetch)
r_cycles <= 8'd0;
else
r_cycles <= r_cycles + 8'd1;
end
end
// I/O access
assign w_io_wr = ~w_inst_in[8] & w_inst_in[6] & w_io_op;
assign w_io_rd = ~w_inst_in[8] & w_inst_in[7] & w_io_op & ~w_io_rdy;
assign w_io_ext = w_inst_in[8] & w_io_op & ~w_io_rdy;
assign w_io_end = w_io_rdy | w_io_wr;
// PC calculation
assign w_pc_inc = r_pc_reg + 11'd1;
always @(w_inst_in or w_skip or w_branch or w_t_mode or w_inst_in or w_pc_inc or w_loop or w_pc_loop or r_ds_T or w_rs_q)
begin
case (w_inst_in[19:17])
3'b000 : // LOOP instruction
if (w_skip)
// Null loop count
w_pc_nxt <= w_inst_in[10:0];
else
// First instruction of the loop
w_pc_nxt <= w_pc_inc;
3'b001 : // JUMP/CALL instruction
if (w_branch)
// Branch taken
w_pc_nxt <= w_inst_in[10:0] | (r_ds_T[10:0] & {11{w_t_mode}});
else
// Branch not taken
w_pc_nxt <= w_pc_inc;
default : // Rest of instruction
if (w_inst_in[16])
// With RTS
w_pc_nxt <= w_rs_q;
else
if (w_loop)
// Jump to start of loop
w_pc_nxt <= w_pc_loop;
else
// Following instruction
w_pc_nxt <= w_pc_inc;
endcase
end
assign w_ifetch = ((w_io_end | w_ram_rdy | (~w_io_op & ~w_reg_op) | r_rst_dly) & ~rst);
always @(posedge rst or posedge clk)
begin
if (rst)
r_pc_reg <= 11'b111_11111111;
else
if (w_ifetch) r_pc_reg <= w_pc_nxt;
end
// Return stack pointer calculation
always @(w_inst_in or w_ifetch or r_rs_ptr or r_pc_reg or w_pc_inc)
begin
if (w_inst_in[19:17] == 3'b001) begin
if (w_inst_in[16]) begin
// "JUMP" instruction
w_rs_nxt <= r_rs_ptr;
w_rs_d <= r_pc_reg;
w_rs_wr <= 1'b0;
w_rs_rd <= 1'b0;
end else begin
// "CALL" instruction
w_rs_nxt <= r_rs_ptr - 4'd1;
w_rs_d <= w_pc_inc;
w_rs_wr <= 1'b1;
w_rs_rd <= 1'b0;
end
end else begin
if ((w_inst_in[16]) && (w_ifetch)) begin
// Embedded "RTS"
w_rs_nxt <= r_rs_ptr + 4'd1;
w_rs_d <= r_pc_reg;
w_rs_wr <= 1'b0;
w_rs_rd <= 1'b1;
end else begin
// No "RTS"
w_rs_nxt <= r_rs_ptr;
w_rs_d <= r_pc_reg;
w_rs_wr <= 1'b0;
w_rs_rd <= 1'b0;
end
end
end
// Return stack
always @(posedge rst or posedge clk)
begin
if (rst)
r_rs_ptr <= 4'd0;
else begin
//else if ((w_io_end) || (!w_io_op)) begin
// Latch the return stack pointer
r_rs_ptr <= w_rs_nxt;
if (w_rs_wr) r_rs[w_rs_nxt] <= w_rs_d;
end
end
// Return stack output value
assign w_rs_q = r_rs[r_rs_ptr];
assign w_ds_inc = {{3{w_inst_in[13]}}, w_inst_in[12]};
// ALU parameters and data stack update
always@(w_inst_in or w_t_mode or r_ds_ptr or w_ds_inc)
begin
casez(w_inst_in[19:17])
// LOOP
3'b000 :
begin
// Generate a "DROP" or a "NOP"
w_alu_c[11:10] <= 2'b01; // Operand size
w_alu_c[9] <= 1'b0; // CCR update
w_alu_c[8:4] <= `ALU_OR; // ALU operation
// Data stack update if "LOOP T"
if (w_inst_in[11]) begin
// DROP
w_alu_c[3:2] <= `A_LOG_ZERO; // A = 0x0000
w_alu_c[1:0] <= `B_LOG_N; // B = Next on stack
w_ds_nxt <= r_ds_ptr - 4'd1;
end else begin
// NOP
w_alu_c[3:2] <= `A_LOG_T; // A = Top of stack
w_alu_c[1:0] <= `B_LOG_ZERO; // B = 0x0000
w_ds_nxt <= r_ds_ptr;
end
w_ds_wr <= 1'b0;
end
// CALL, JUMP
3'b001 :
begin
// Generate a "DROP" or a "NOP"
w_alu_c[11:10] <= 2'b01; // Operand size
w_alu_c[9] <= 1'b0; // CCR update
w_alu_c[8:4] <= `ALU_OR; // ALU operation
// Data stack update if "JUMP (T)" or "CALL (T)"
if (w_t_mode) begin
// DROP
w_alu_c[3:2] <= `A_LOG_ZERO; // A = 0x0000
w_alu_c[1:0] <= `B_LOG_N; // B = Next on stack
w_ds_nxt <= r_ds_ptr - 4'd1;
end else begin
// NOP
w_alu_c[3:2] <= `A_LOG_T; // A = Top of stack
w_alu_c[1:0] <= `B_LOG_ZERO; // B = 0x0000
w_ds_nxt <= r_ds_ptr;
end
w_ds_wr <= 1'b0;
end
// LIT
3'b010 :
begin
w_alu_c[11:10] <= 2'b01; // Operand size
w_alu_c[9] <= 1'b0; // CCR update
w_alu_c[8:4] <= `ALU_OR; // ALU operation
w_alu_c[3:2] <= `A_LOG_IMM; // A = Immediate value
w_alu_c[1:0] <= `B_LOG_ZERO; // B = 0x0000
// Data stack update
w_ds_nxt <= r_ds_ptr + 4'd1;
w_ds_wr <= 1'b1;
end
// FLAG
3'b011 :
begin
// Generate a "NOP"
w_alu_c[11:10] <= 2'b01; // Operand size
w_alu_c[9] <= 1'b0; // CCR update
w_alu_c[8:4] <= `ALU_OR; // ALU operation
w_alu_c[3:2] <= `A_LOG_T; // A = Top of stack
w_alu_c[1:0] <= `B_LOG_ZERO; // B = 0x0000
// No data stack update
w_ds_nxt <= r_ds_ptr;
w_ds_wr <= 1'b0;
end
// I/O reg. access
3'b100 :
begin
w_alu_c[11:10] <= 2'b01; // Operand size
w_alu_c[9] <= w_inst_in[9]; // CCR update
w_alu_c[8:4] <= `ALU_OR; // ALU operation
if (w_inst_in[7]) begin
if (w_ds_inc[0]) begin
// I/O register load
w_alu_c[3:2] <= `A_LOG_ZERO; // A = 0x0000
w_alu_c[1:0] <= `B_LOG_IO; // B = I/O data
end else begin
// I/O register fetch
w_alu_c[3:2] <= `A_LOG_T; // A = Top of stack
w_alu_c[1:0] <= `B_LOG_ZERO; // B = 0x0000
end
end else begin
if (w_ds_inc[0]) begin
// I/O register store
w_alu_c[3:2] <= `A_LOG_ZERO; // A = 0x0000
w_alu_c[1:0] <= `B_LOG_N; // B = Next on stack
end else begin
// I/O register write
w_alu_c[3:2] <= `A_LOG_T; // A = Top of stack
w_alu_c[1:0] <= `B_LOG_ZERO; // B = 0x0000
end
end
// Data stack update
w_ds_nxt <= r_ds_ptr + w_ds_inc;
w_ds_wr <= w_inst_in[14];
end
// M68k reg. access
3'b101 :
begin
w_alu_c[11:10] <= 2'b01; // Operand size
w_alu_c[9] <= w_inst_in[9]; // CCR update
w_alu_c[8:4] <= `ALU_OR; // ALU operation
if (w_inst_in[7]) begin
// M68k register load
w_alu_c[3:2] <= `A_LOG_RAM; // A = RAM data
w_alu_c[1:0] <= `B_LOG_ZERO; // B = 0x0000
end else begin
if (w_ds_inc[0]) begin
// M68k register store
w_alu_c[3:2] <= `A_LOG_ZERO; // A = 0x0000
w_alu_c[1:0] <= `B_LOG_N; // B = Next on stack
end else begin
// M68k register write
w_alu_c[3:2] <= `A_LOG_T; // A = Top of stack
w_alu_c[1:0] <= `B_LOG_ZERO; // B = 0x0000
end
end
// Data stack update
w_ds_nxt <= r_ds_ptr + w_ds_inc;
w_ds_wr <= w_inst_in[14];
end
// ALU operation
3'b110 :
begin
w_alu_c[11:10] <= w_inst_in[11:10]; // Operand size
w_alu_c[9] <= w_inst_in[9]; // CCR update
w_alu_c[8:4] <= w_inst_in[8:4]; // ALU operation
w_alu_c[3:2] <= w_inst_in[3:2]; // A source
w_alu_c[1:0] <= w_inst_in[1:0]; // B source
// Data stack update
w_ds_nxt <= r_ds_ptr + w_ds_inc;
w_ds_wr <= w_inst_in[14];
end
default:
begin
// Generate a "NOP"
w_alu_c[11:10] <= 2'b01; // Operand size
w_alu_c[9] <= 1'b0; // CCR update
w_alu_c[8:4] <= `ALU_OR; // ALU operation
w_alu_c[3:2] <= `A_LOG_T; // A = Top of stack
w_alu_c[1:0] <= `B_LOG_ZERO; // B = 0x0000
// No data stack update
w_ds_nxt <= r_ds_ptr;
w_ds_wr <= 1'b0;
end
endcase
end
// Data stack
always @(posedge rst or posedge clk)
begin
if (rst) begin
r_ds_ptr <= 4'd0;
r_ds_T <= 16'h0000;
end else if ((w_io_end) || (w_ram_rdy) || (!(w_io_op | w_reg_op))) begin
// Latch the data stack pointer
r_ds_ptr <= w_ds_nxt;
// Latch the data stack value T
r_ds_T <= w_ds_R[15:0];
// Latch the data stack value N
if (w_ds_wr) r_ds[w_ds_nxt] <= w_ds_R[31:16];
end
end
// Data stack output value #1 (N)
assign w_ds_N = r_ds[r_ds_ptr];
// Flags control
always@(w_inst_in or w_io_flg_c)
begin
if (w_inst_in[19:17] == 3'b011) begin
// Update flags
w_flg_c <= w_inst_in[10:0];
w_cin_c <= w_inst_in[14:11];
end else begin
// Keep flags
w_flg_c <= w_io_flg_c;
w_cin_c <= 4'b0000;
end
end
// 16/32-bit ALU
alu alu_inst
(
.rst(rst),
.clk(clk),
.size(w_alu_c[11:10]),
.cc_upd(w_alu_c[9]),
.alu_c(w_alu_c[8:4]),
.a_ctl(w_alu_c[3:2]),
.b_ctl(w_alu_c[1:0]),
.c_in(w_c_in),
.v_in(w_ccr[1]),
.a_src(r_ds_T),
.b_src(w_ds_N),
.ram_in(w_ram_dout),
.io_in(w_io_din),
.imm_in(w_inst_in[15:0]),
.result(w_ds_R),
.c_flg(w_c_flg),
.v_flg(w_v_flg[4:0]),
.l_res(w_res),
.l_alu(w_alu),
.l_size(w_size)
);
// Flags update
flags flags_inst
(
.rst(rst),
.clk(clk),
.c_flg(w_c_flg),
.v_flg(w_v_flg),
.l_res(w_res),
.l_alu(w_alu),
.l_size(w_size),
.a_src(r_ds_T),
.b_src(w_ds_N),
.flg_c(w_flg_c),
.cin_c(w_cin_c),
.cc_out(w_ccr),
.c_in(w_c_in),
.z_flg(w_z_flg),
.g_flg(w_g_flg)
);
// Conditional Jump/Call
test test_inst
(
.rst(rst),
.clk(clk),
.inst_in(w_inst_in),
.flg_in({w_g_flg, w_res[15], w_z_flg, w_c_flg[1]}),
.sr_in({w_sr, w_ccr}),
.a_src(r_ds_T),
.ea1b(w_ea1b),
.extw(w_extw),
.branch(w_branch)
);
// Hardware loop
loop loop_inst
(
.rst(rst),
.clk(clk),
.inst_in(w_inst_in),
.i_fetch(w_ifetch),
.a_src(r_ds_T[5:0]),
.pc_in(w_pc_nxt),
.pc_out(w_pc_loop),
.branch(w_loop),
.skip(w_skip),
.lcount(w_loop_cnt)
);
// Bus interface
mem_io mem_inst
(
.rst(rst),
.clk(clk),
.rd_ena(rd_ena),
.wr_ena(wr_ena),
.data_ack(data_ack),
.byte_ena(byte_ena),
.address(address),
.rd_data(rd_data),
.wr_data(wr_data),
.fc(fc),
.ipl_n(ipl_n),
.io_rd(w_io_rd),
.io_wr(w_io_wr),
.io_ext(w_io_ext),
.io_reg(w_reg_op),
.io_rdy(w_io_rdy),
.io_din(w_io_din),
.io_dout(r_ds_T),
.inst_in(w_inst_in),
.cc_upd(w_alu_c[9]),
.alu_op(w_alu_c[7:4]),
.a_src(r_ds_T),
.b_src(w_ds_N),
.v_flg(w_v_flg[5]),
.insw(w_insw),
.extw(w_extw),
.ea1b(w_ea1b),
.ccr_in(w_ccr),
.sr_out(w_sr),
.flg_c(w_io_flg_c),
.loop_cnt(w_loop_cnt),
.reg_addr(w_reg_addr[5:0]),
.reg_wr(w_reg_wr),
.reg_bena(w_reg_bena),
.dbg_pc(dbg_pc_reg),
.dbg_if(dbg_ifetch)
);
assign w_reg_addr[10:6] = 5'b11111;
// Microcode ROM : 2048 x 20-bit (5 x M9K)
dpram_2048x4 dpram_inst_0
(
.clock(clk),
.rden_a(w_ifetch),
.address_a(w_pc_nxt),
.q_a(w_inst_in[3:0]),
.wren_b(w_ram_bena[0]),
.address_b(w_ram_addr),
.data_b(w_ram_din[3:0]),
.q_b(w_ram_dout[3:0])
);
defparam
dpram_inst_0.RAM_INIT_FILE = "j68_ram_0.mif";
dpram_2048x4 dpram_inst_1
(
.clock(clk),
.rden_a(w_ifetch),
.address_a(w_pc_nxt),
.q_a(w_inst_in[7:4]),
.wren_b(w_ram_bena[0]),
.address_b(w_ram_addr),
.data_b(w_ram_din[7:4]),
.q_b(w_ram_dout[7:4])
);
defparam
dpram_inst_1.RAM_INIT_FILE = "j68_ram_1.mif";
dpram_2048x4 dpram_inst_2
(
.clock(clk),
.rden_a(w_ifetch),
.address_a(w_pc_nxt),
.q_a(w_inst_in[11:8]),
.wren_b(w_ram_bena[1]),
.address_b(w_ram_addr),
.data_b(w_ram_din[11:8]),
.q_b(w_ram_dout[11:8])
);
defparam
dpram_inst_2.RAM_INIT_FILE = "j68_ram_2.mif";
dpram_2048x4 dpram_inst_3
(
.clock(clk),
.rden_a(w_ifetch),
.address_a(w_pc_nxt),
.q_a(w_inst_in[15:12]),
.wren_b(w_ram_bena[1]),
.address_b(w_ram_addr),
.data_b(w_ram_din[15:12]),
.q_b(w_ram_dout[15:12])
);
defparam
dpram_inst_3.RAM_INIT_FILE = "j68_ram_3.mif";
dpram_2048x4 dpram_inst_4
(
.clock(clk),
.rden_a(w_ifetch),
.address_a(w_pc_nxt),
.q_a(w_inst_in[19:16]),
.wren_b(1'b0),
.address_b(w_ram_addr),
.data_b(4'b0000),
.q_b()
);
defparam
dpram_inst_4.RAM_INIT_FILE = "j68_ram_4.mif";
endmodule
module alu
(
// Clock and reset
input rst, // CPU reset
input clk, // CPU clock
// Control signals
input cc_upd, // Condition codes update
input [1:0] size, // Operand size (00 = byte, 01 = word, 1x = long)
input [4:0] alu_c, // ALU control
input [1:0] a_ctl, // A source control
input [1:0] b_ctl, // B source control
// Operands
input c_in, // Carry in
input v_in, // Overflow in
input [15:0] a_src, // A source
input [15:0] b_src, // B source
input [15:0] ram_in, // RAM read
input [15:0] io_in, // I/O read
input [15:0] imm_in, // Immediate
// Result
output reg [31:0] result, // ALU result
// Flags
output reg [4:0] c_flg, // Partial C/X flags
output reg [4:0] v_flg, // Partial V flag
output reg [31:0] l_res, // Latched result for N & Z flags
output reg [3:0] l_alu, // Latched ALU control
output reg [1:0] l_size // Latched operand size
);
reg [15:0] w_a_log; // Operand A for logic
reg [15:0] w_a_add; // Operand A for adder
reg w_a_lsb; // Operand A lsb
reg [15:0] w_b_log; // Operand B for logic
reg [15:0] w_b_add; // Operand B for adder
reg w_b_lsb; // Operand B lsb
wire [17:0] w_add_r; // Adder result
reg [15:0] w_log_r; // Logical result
reg [31:0] w_lsh_r; // Left shifter result
reg [31:0] w_rsh_r; // Right shifter result
wire [4:0] w_c_flg; // Carry flags
wire [4:0] w_v_flg; // Overflow flags
// A source for Adder (1 LUT level)
always @(a_ctl or a_src)
begin
case (a_ctl)
2'b00 : w_a_add <= 16'h0000;
2'b01 : w_a_add <= 16'hFFFF;
2'b10 : w_a_add <= a_src;
2'b11 : w_a_add <= ~a_src;
endcase
end
// B source for Adder (1 LUT level)
always @(b_ctl or b_src)
begin
case (b_ctl)
2'b00 : w_b_add <= 16'h0000;
2'b01 : w_b_add <= 16'hFFFF;
2'b10 : w_b_add <= b_src;
2'b11 : w_b_add <= ~b_src;
endcase
end
// A source for Logic (1 LUT level)
always @(a_src or a_ctl or imm_in or ram_in)
begin
case (a_ctl)
2'b00 : w_a_log <= 16'h0000;
2'b01 : w_a_log <= imm_in; // Immediate value through OR
2'b10 : w_a_log <= a_src;
2'b11 : w_a_log <= ram_in; // RAM read through OR
endcase
end
// B source for Logic (2 LUT levels)
always @(alu_c or size or b_src or b_ctl or io_in)
begin
if (alu_c[4]) begin
// Mask generation for BTST, BCHG, BCLR, BSET
case ({b_src[4]&(size[1]|size[0]), b_src[3]&(size[1]|size[0]), b_src[2:0]})
5'b00000 : w_b_log <= 16'b0000000000000001 & {16{~size[1]}} ^ {16{b_ctl[0]}};
5'b00001 : w_b_log <= 16'b0000000000000010 & {16{~size[1]}} ^ {16{b_ctl[0]}};
5'b00010 : w_b_log <= 16'b0000000000000100 & {16{~size[1]}} ^ {16{b_ctl[0]}};
5'b00011 : w_b_log <= 16'b0000000000001000 & {16{~size[1]}} ^ {16{b_ctl[0]}};
5'b00100 : w_b_log <= 16'b0000000000010000 & {16{~size[1]}} ^ {16{b_ctl[0]}};
5'b00101 : w_b_log <= 16'b0000000000100000 & {16{~size[1]}} ^ {16{b_ctl[0]}};
5'b00110 : w_b_log <= 16'b0000000001000000 & {16{~size[1]}} ^ {16{b_ctl[0]}};
5'b00111 : w_b_log <= 16'b0000000010000000 & {16{~size[1]}} ^ {16{b_ctl[0]}};
5'b01000 : w_b_log <= 16'b0000000100000000 & {16{~size[1]}} ^ {16{b_ctl[0]}};
5'b01001 : w_b_log <= 16'b0000001000000000 & {16{~size[1]}} ^ {16{b_ctl[0]}};
5'b01010 : w_b_log <= 16'b0000010000000000 & {16{~size[1]}} ^ {16{b_ctl[0]}};
5'b01011 : w_b_log <= 16'b0000100000000000 & {16{~size[1]}} ^ {16{b_ctl[0]}};
5'b01100 : w_b_log <= 16'b0001000000000000 & {16{~size[1]}} ^ {16{b_ctl[0]}};
5'b01101 : w_b_log <= 16'b0010000000000000 & {16{~size[1]}} ^ {16{b_ctl[0]}};
5'b01110 : w_b_log <= 16'b0100000000000000 & {16{~size[1]}} ^ {16{b_ctl[0]}};
5'b01111 : w_b_log <= 16'b1000000000000000 & {16{~size[1]}} ^ {16{b_ctl[0]}};
5'b10000 : w_b_log <= 16'b0000000000000001 & {16{~size[0]}} ^ {16{b_ctl[0]}};
5'b10001 : w_b_log <= 16'b0000000000000010 & {16{~size[0]}} ^ {16{b_ctl[0]}};
5'b10010 : w_b_log <= 16'b0000000000000100 & {16{~size[0]}} ^ {16{b_ctl[0]}};
5'b10011 : w_b_log <= 16'b0000000000001000 & {16{~size[0]}} ^ {16{b_ctl[0]}};
5'b10100 : w_b_log <= 16'b0000000000010000 & {16{~size[0]}} ^ {16{b_ctl[0]}};
5'b10101 : w_b_log <= 16'b0000000000100000 & {16{~size[0]}} ^ {16{b_ctl[0]}};
5'b10110 : w_b_log <= 16'b0000000001000000 & {16{~size[0]}} ^ {16{b_ctl[0]}};
5'b10111 : w_b_log <= 16'b0000000010000000 & {16{~size[0]}} ^ {16{b_ctl[0]}};
5'b11000 : w_b_log <= 16'b0000000100000000 & {16{~size[0]}} ^ {16{b_ctl[0]}};
5'b11001 : w_b_log <= 16'b0000001000000000 & {16{~size[0]}} ^ {16{b_ctl[0]}};
5'b11010 : w_b_log <= 16'b0000010000000000 & {16{~size[0]}} ^ {16{b_ctl[0]}};
5'b11011 : w_b_log <= 16'b0000100000000000 & {16{~size[0]}} ^ {16{b_ctl[0]}};
5'b11100 : w_b_log <= 16'b0001000000000000 & {16{~size[0]}} ^ {16{b_ctl[0]}};
5'b11101 : w_b_log <= 16'b0010000000000000 & {16{~size[0]}} ^ {16{b_ctl[0]}};
5'b11110 : w_b_log <= 16'b0100000000000000 & {16{~size[0]}} ^ {16{b_ctl[0]}};
5'b11111 : w_b_log <= 16'b1000000000000000 & {16{~size[0]}} ^ {16{b_ctl[0]}};
endcase
end else begin
case (b_ctl)
2'b00 : w_b_log <= 16'h0000;
2'b01 : w_b_log <= io_in; // I/O read through OR
2'b10 : w_b_log <= b_src;
2'b11 : w_b_log <= ~b_src;
endcase
end
end
// Carry input (1 LUT level)
always @(alu_c or c_in)
begin
case (alu_c[1:0])
2'b00 : begin // For: R = A + B
w_a_lsb <= 1'b0;
w_b_lsb <= 1'b0;
end
2'b01 : begin // For: R = A + B + Carry
w_a_lsb <= c_in;
w_b_lsb <= c_in;
end
2'b10 : begin // For: R = A - B
w_a_lsb <= 1'b1;
w_b_lsb <= 1'b1;
end
2'b11 : begin // For: R = B - A - Borrow
w_a_lsb <= ~c_in;
w_b_lsb <= ~c_in;
end
endcase
end
// Adder (1 LUT level + carry chain)
assign w_add_r = {1'b0, w_a_add, w_a_lsb} + {1'b0, w_b_add, w_b_lsb};
// Logical operations (2 LUT levels)
always @(alu_c or size or w_a_log or w_b_log)
begin
case (alu_c[1:0])
2'b00 : w_log_r[7:0] <= w_a_log[7:0] & w_b_log[7:0]; // AND.B
2'b01 : w_log_r[7:0] <= w_a_log[7:0] | w_b_log[7:0]; // OR.B
2'b10 : w_log_r[7:0] <= w_a_log[7:0] ^ w_b_log[7:0]; // XOR.B
2'b11 : w_log_r[7:0] <= ~w_a_log[7:0]; // NOT.B
endcase
if (size == 2'b00)
w_log_r[15:8] <= w_a_log[15:8];
else
case (alu_c[1:0])
2'b00 : w_log_r[15:8] <= w_a_log[15:8] & w_b_log[15:8]; // AND.W
2'b01 : w_log_r[15:8] <= w_a_log[15:8] | w_b_log[15:8]; // OR.W
2'b10 : w_log_r[15:8] <= w_a_log[15:8] ^ w_b_log[15:8]; // XOR.W
2'b11 : w_log_r[15:8] <= ~w_a_log[15:8]; // NOT.W
endcase
end
// Left shifter (1 LUT level)
always @(size or a_src or b_src or c_in)
begin
case (size)
2'b00 : w_lsh_r <= { b_src[15:0], a_src[15:8], a_src[6:0], c_in }; // Byte
2'b01 : w_lsh_r <= { b_src[15:0], a_src[14:0], c_in }; // Word
default : w_lsh_r <= { b_src[14:0], a_src[15:0], c_in }; // Long
endcase
end
// Right shifter (1 LUT level)
always @(size or a_src or b_src or c_in)
begin
case (size)
2'b00 : w_rsh_r <= { b_src[15:0], a_src[15:8], c_in, a_src[7:1] }; // Byte
2'b01 : w_rsh_r <= { b_src[15:0], c_in, a_src[15:1] }; // Word
default : w_rsh_r <= { c_in, b_src[15:0], a_src[15:1] }; // Long
endcase
end
// Final MUX (2 LUTs level)
always @(alu_c or a_src or w_add_r or w_log_r or w_lsh_r or w_rsh_r)
begin
case (alu_c[3:2])
2'b00 : result <= { a_src, w_add_r[16:1] }; // Adder
2'b01 : result <= { a_src, w_log_r }; // Logic
2'b10 : result <= w_lsh_r; // Left shift
2'b11 : result <= w_rsh_r; // Right shift
endcase
end
// Partial carry flags from adder
assign w_c_flg[0] = w_add_r[9] ^ w_a_add[8]
^ w_b_add[8] ^ alu_c[1]; // Byte
assign w_c_flg[1] = w_add_r[17] ^ alu_c[1]; // Word
// Partial carry flags from shifter
assign w_c_flg[2] = (a_src[0] & alu_c[2])
| (a_src[7] & ~alu_c[2]); // Byte
assign w_c_flg[3] = (a_src[0] & alu_c[2])
| (a_src[15] & ~alu_c[2]); // Word
assign w_c_flg[4] = (a_src[0] & alu_c[2])
| (b_src[15] & ~alu_c[2]); // Long
// Partial overflow flags from adder
assign w_v_flg[0] = w_add_r[9] ^ w_add_r[8]
^ w_a_add[8] ^ w_a_add[7]
^ w_b_add[8] ^ w_b_add[7]; // Byte
assign w_v_flg[1] = w_add_r[17] ^ w_add_r[16]
^ w_a_add[15] ^ w_b_add[15]; // Word
// Partial overflow flags from shifter
assign w_v_flg[2] = v_in | (a_src[7] ^ a_src[6]); // Byte
assign w_v_flg[3] = v_in | (a_src[15] ^ a_src[14]); // Word
assign w_v_flg[4] = v_in | (b_src[15] ^ b_src[14]); // Long
// Latch partial flags and result
always@(posedge rst or posedge clk)
begin
if (rst) begin
c_flg <= 5'b00000;
v_flg <= 5'b00000;
l_res <= 32'h00000000;
l_alu <= 4'b0000;
l_size <= 2'b00;
end else if (cc_upd) begin
c_flg <= w_c_flg;
v_flg <= w_v_flg;
l_res <= result;
l_alu <= alu_c[3:0];
l_size <= size;
end
end
endmodule
module flags
(
// Clock and reset
input rst, // CPU reset
input clk, // CPU clock
// Flags input
input [4:0] c_flg, // Partial C/X flags
input [5:0] v_flg, // Partial V flags
input [31:0] l_res, // Latched result for N & Z flags
input [3:0] l_alu, // Latched ALU control
input [1:0] l_size, // Latched operand size
// Operand input
input [15:0] a_src, // A operand
input [15:0] b_src, // B operand
// Flags control
input [10:0] flg_c, // Flags output control
input [3:0] cin_c, // Carry in control
// Flags output
output reg [4:0] cc_out, // XNZVC 68000 flags
output reg c_in, // Carry in for ALU
output z_flg, // Zero flag for test block
output g_flg // Greater than flag for test block
);
reg w_c_flg;
reg w_v_flg;
reg w_z_flg;
reg w_n_flg;
wire [2:0] w_zero;
reg r_z_flg;
// C/X flag computation
always@(l_alu or l_size or c_flg)
begin
case (l_alu[3:2])
2'b00 : // Adder
if (l_size == 2'b00)
w_c_flg <= c_flg[0]; // Byte
else
w_c_flg <= c_flg[1]; // Word & Long
2'b01 : // Logic
w_c_flg <= 1'b0;
default : // Shifter
case (l_size)
2'b00 : w_c_flg <= c_flg[2]; // Byte
2'b01 : w_c_flg <= c_flg[3]; // Word
default : w_c_flg <= c_flg[4]; // Long
endcase
endcase
end
// V flag computation
always@(l_alu or l_size or v_flg)
begin
case (l_alu[3:2])
2'b00 : // Adder
if (l_size == 2'b00)
w_v_flg <= v_flg[0]; // Byte
else
w_v_flg <= v_flg[1]; // Word & Long
2'b10 : // Left shifter (ASL case)
case (l_size)
2'b00 : w_v_flg <= v_flg[2]; // Byte
2'b01 : w_v_flg <= v_flg[3]; // Word
default : w_v_flg <= v_flg[4]; // Long
endcase
2'b11 : // Right shifter (DIVU/DIVS case)
w_v_flg <= v_flg[5] & l_alu[1];
default : // Logic : no overflow
w_v_flg <= 1'b0;
endcase
end
// Z flag computation
assign w_zero[0] = (l_res[7:0] == 8'h00) ? 1'b1 : 1'b0;
assign w_zero[1] = (l_res[15:8] == 8'h00) ? 1'b1 : 1'b0;
assign w_zero[2] = (l_res[31:16] == 16'h0000) ? 1'b1 : 1'b0;
always@(l_alu or l_size or w_zero or r_z_flg)
begin
if (l_alu[3]) begin
// Shifter
case (l_size)
2'b00 : w_z_flg <= w_zero[0]; // Byte
2'b01 : w_z_flg <= w_zero[0] & w_zero[1]; // Word
default : w_z_flg <= w_zero[0] & w_zero[1] & w_zero[2]; // Long
endcase
end else begin
// Adder & Logic
case (l_size)
2'b00 : w_z_flg <= w_zero[0]; // Byte
2'b01 : w_z_flg <= w_zero[0] & w_zero[1]; // Word
default : w_z_flg <= w_zero[0] & w_zero[1] & r_z_flg; // Long
endcase
end
end
// N flag computation
always@(l_alu or l_size or l_res)
begin
if (l_alu[3]) begin
// Shifter
case (l_size)
2'b00 : w_n_flg <= l_res[7]; // Byte
2'b01 : w_n_flg <= l_res[15]; // Word
default : w_n_flg <= l_res[31]; // Long
endcase
end else begin
// Adder & Logic
case (l_size)
2'b00 : w_n_flg <= l_res[7]; // Byte
2'b01 : w_n_flg <= l_res[15]; // Word
default : w_n_flg <= l_res[15]; // Long
endcase
end
end
// Flag output control
// 00 : keep (-)
// 01 : update (*)
// 10 : clear (0)
// 11 : set (1)
// 100 : update, clear only (.)
always@(posedge rst or posedge clk)
begin
if (rst) begin
cc_out <= 5'b00100;
r_z_flg <= 1'b0;
end
else begin
// C flag update
case (flg_c[1:0])
2'b00 : cc_out[0] <= cc_out[0];
2'b01 : cc_out[0] <= w_c_flg;
2'b10 : cc_out[0] <= 1'b0;
2'b11 : cc_out[0] <= 1'b1;
endcase
// V flag update
case (flg_c[3:2])
2'b00 : cc_out[1] <= cc_out[1];
2'b01 : cc_out[1] <= w_v_flg;
2'b10 : cc_out[1] <= 1'b0;
2'b11 : cc_out[1] <= 1'b1;
endcase
// Z flag update
case (flg_c[6:4])
3'b000 : cc_out[2] <= cc_out[2];
3'b001 : cc_out[2] <= w_z_flg;
3'b010 : cc_out[2] <= 1'b0;
3'b011 : cc_out[2] <= 1'b1;
3'b100 : cc_out[2] <= cc_out[2];
3'b101 : cc_out[2] <= w_z_flg & cc_out[2];
3'b110 : cc_out[2] <= 1'b0;
3'b111 : cc_out[2] <= 1'b1;
endcase
// N flag update
case (flg_c[8:7])
2'b00 : cc_out[3] <= cc_out[3];
2'b01 : cc_out[3] <= w_n_flg;
2'b10 : cc_out[3] <= 1'b0;
2'b11 : cc_out[3] <= 1'b1;
endcase
// X flag update
case (flg_c[10:9])
2'b00 : cc_out[4] <= cc_out[4];
2'b01 : cc_out[4] <= w_c_flg;
2'b10 : cc_out[4] <= 1'b0;
2'b11 : cc_out[4] <= 1'b1;
endcase
if ((!l_alu[3]) && (l_size == 2'b01))
r_z_flg <= w_zero[0] & w_zero[1];
end
end
// Zero flag from word result
assign z_flg = w_zero[0] & w_zero[1];
// Greater than from adder : not((V xor N) or Z)
assign g_flg = ~((v_flg[1] ^ l_res[15]) | (w_zero[0] & w_zero[1]));
// Carry input control
// 0000 : keep : KEEP
// 0001 : 0 : CLR
// 0010 : c_flg[1] : C_ADD
// 0011 : w_c_flg : C_FLG
// 0100 : X flag : X_SR
// 0101 : result[7] : N_B
// 0110 : result[15] : N_W
// 0111 : N flag : N_SR
// 1000 : a_src[0] : T0
// 1001 : a_src[7] : T7
// 1010 : a_src[15] : T15
// 1100 : b_src[0] : N0
// 1101 : b_src[7] : N7
// 1110 : b_src[15] : N15
always@(posedge rst or posedge clk)
begin
if (rst)
c_in <= 1'b0;
else
case (cin_c)
4'b0000 : c_in <= c_in; // Keep flag
4'b0001 : c_in <= 1'b0; // For ASL, LSL, LSR
4'b0010 : c_in <= c_flg[1]; // For ADD.L, SUB.L
4'b0011 : c_in <= w_c_flg; // For ADDX, SUBX, ROXL, ROXR
4'b0100 : c_in <= cc_out[4]; // X flag
4'b0101 : c_in <= l_res[7]; // For EXT.W
4'b0110 : c_in <= l_res[15]; // For EXT.L
4'b0111 : c_in <= cc_out[3]; // N flag
4'b1000 : c_in <= a_src[0]; // For ROR
4'b1001 : c_in <= a_src[7]; // For ASR.B, ROL.B
4'b1010 : c_in <= a_src[15]; // For ASR.W, ROL.W
4'b1100 : c_in <= b_src[0]; // For ROR.B, ROR.W
4'b1101 : c_in <= b_src[7]; // For ASR.B, ROL.B
4'b1110 : c_in <= b_src[15]; // For ASR.W, ASR.L, ROL.W, ROL.L
default : c_in <= 1'b0;
endcase
end
endmodule
module test
(
// Clock and reset
input rst, // CPU reset
input clk, // CPU clock
// Micro-instruction word
input [19:0] inst_in,
// Operand input
input [3:0] flg_in, // Partial flags
input [15:0] sr_in, // Status register
input [15:0] a_src, // A operand
input [15:0] ea1b, // EA #1 bitfield
input [15:0] extw, // Extension word
// Test output
output reg branch // Branch taken
);
always@(inst_in or flg_in or sr_in or a_src or ea1b or extw)
begin
case (inst_in[15:12])
4'b0000 : branch <= inst_in[11] ^ sr_in[12]; // Address error
4'b0001 : branch <= inst_in[11] ^ flg_in[1]; // Z_FLG : Partial zero (for CHK, Bcc and DBcc)
4'b0010 : branch <= inst_in[11] ^ flg_in[2]; // N_FLG : Partial negative (for MULS, DIVS, ABCD and SBCD)
4'b0011 : branch <= inst_in[11] ^ flg_in[3]; // G_FLG : Greater than (for CHK)
4'b0100 : branch <= inst_in[11] ^ a_src[0]; // T[0] (for MOVEM)
4'b0101 : branch <= inst_in[11] ^ ea1b[4]; // (An)+ addressing
4'b0110 : branch <= inst_in[11] ^ ea1b[7]; // Dn/An addressing
4'b0111 : branch <= inst_in[11] ^ extw[11]; // Long/Word for d8(An,Rn)
4'b1000 : branch <= inst_in[11] ^ sr_in[1]; // V flag
4'b1001 : branch <= inst_in[11] ^ sr_in[3]; // N flag
4'b1010 : branch <= inst_in[11] ^ sr_in[5]; // Branch flag (for DBcc and Bcc)
4'b1011 : branch <= inst_in[11] ^ sr_in[11]; // Interrupt flag
4'b1100 : branch <= inst_in[11] ^ sr_in[13]; // Supervisor flag
4'b1101 : branch <= inst_in[11] ^ sr_in[15]; // Trace flag
default : branch <= 1'b1; // Always
endcase
end
endmodule
module loop
(
// Clock and reset
input rst, // CPU reset
input clk, // CPU clock
// Loop control
input [19:0] inst_in,
input i_fetch, // Instruction fetch
input [5:0] a_src, // A source
input [10:0] pc_in, // PC input
output [10:0] pc_out, // PC output
output reg branch, // Loop taken
output skip, // Loop skipped
output [3:0] lcount // Loop count for MOVEM
);
reg [10:0] r_loop_st; // Loop start PC
reg [10:0] r_loop_end; // Loop end PC
reg [5:0] r_loop_cnt; // Loop count
reg r_loop_ena; // Loop enable
always @(posedge rst or posedge clk)
begin
if (rst) begin
r_loop_st <= 11'd0;
r_loop_end <= 11'd0;
r_loop_cnt <= 6'd0;
r_loop_ena <= 1'b0;
branch <= 1'b0;
end else begin
// "LOOP" instruction is executed
if (inst_in[19:17] == 3'b000) begin
// Store current PC (start of loop)
r_loop_st = pc_in;
// Store address field (end of loop)
r_loop_end = inst_in[10:0];
if (inst_in[11]) begin
// "LOOPT"
r_loop_cnt = a_src[5:0] - 6'd1;
// Skipped if T = 0
r_loop_ena = ~skip;
end else begin
// "LOOP16"
r_loop_cnt = 6'd15;
// Always executed
r_loop_ena = 1'b1;
end
end
if (r_loop_ena) begin
if (i_fetch) begin
// End of loop reached
if (r_loop_end == pc_in)
if (r_loop_cnt == 6'd0) begin
// Loop count = 0 : exit loop
branch <= 1'b0;
r_loop_ena <= 1'b0;
end else begin
// Loop count > 0 : go on
branch <= 1'b1;
r_loop_cnt <= r_loop_cnt - 6'd1;
end
else
branch <= 1'b0;
end
end else begin
branch <= 1'b0;
end
end
end
// Loop start PC value
assign pc_out = r_loop_st;
// Loop skipped when T is null and "LOOPT" instruction
assign skip = (a_src[5:0] == 6'd0) ? inst_in[11] : 1'b0;
// Loop count for MOVEM
assign lcount = r_loop_cnt[3:0];
endmodule
// RAM registers
// -------------
// 0xFFD6 - 0xFFD7 : VBR
// 0xFFD8 - 0xFFD9 : TMP1
// 0xFFDA - 0xFFDB : TMP2
// 0xFFDC - 0xFFDD : USP
// 0xFFDE - 0xFFDF : SSP
// 0xFFE0 - 0xFFEF : D0 - D7
// 0xFFF0 - 0xFFFF : A0 - A7
// I/O registers
// -------------
// 0000 : VEC_HI (R/W)
// 0001 : VEC_LO (R/W)
// 0010 : PC_HI (R/W)
// 0011 : PC_LO (R/W)
// 0100 : EA1_HI (R/W)
// 0101 : EA1_LO (R/W)
// 0110 : EA2_HI (R/W)
// 0111 : EA2_LO (R/W)
// 1000 : IMM (RO)
// 1001 : LSH (R/W)
// 1010 : ACCL (R/W)
// 1011 : ACCH (R/W)
// 1100 : DEC_JMP (RO)
// 1101 : EA1_JMP (RO)
// 1110 : EA2_JMP (RO)
// 1111 : CPU_SR (R/W)
module mem_io
(
// Clock and reset
input rst, // CPU reset
input clk, // CPU clock
// Outside bus interface
output reg rd_ena, // Read strobe
output reg wr_ena, // Write strobe
input data_ack, // Data acknowledge
output reg [1:0] byte_ena, // Byte enable
output reg [31:0] address, // Address bus
input [15:0] rd_data, // Data bus in
output reg [15:0] wr_data, // Data bus out
// 68000 control
output reg [2:0] fc, // Function code
input [2:0] ipl_n, // Interrupt level
// I/O bus
input io_rd, // I/O read strobe from J68 micro-core
input io_wr, // I/O write strobe from J68 micro-core
input io_ext, // External memory access
input io_reg, // Read/write to CPU register
output reg io_rdy, // Data ready to J68 micro-core
output reg [15:0] io_din, // Data to J68 micro-core
input [15:0] io_dout, // Data from J68 micro-core
input [19:0] inst_in, // Microcode word
// ALU interface (MUL/DIV)
input cc_upd, // Condition codes update
input [3:0] alu_op, // ALU operation
input [15:0] a_src, // A source
input [15:0] b_src, // B source
output reg v_flg, // V flag from divide
// Decoder data
output [15:0] insw, // Instruction word
output [15:0] extw, // Extension word
output [15:0] ea1b, // EA #1 bitfield
// Status register
input [4:0] ccr_in, // XNZVC 68000 flags
output [10:0] sr_out, // Status register
output reg [10:0] flg_c, // Flag output control
// Register access
input [3:0] loop_cnt, // Loop count for MOVEM
output reg [5:0] reg_addr, // Register address
output reg reg_wr, // Register write enable
output reg [1:0] reg_bena, // Register byte enable
// Debug
output [31:0] dbg_pc, // Program counter
output dbg_if // Instruction fetch
);
reg [8:0] r_vec_addr; // Vector address (reg)
reg [31:0] r_pc_addr; // Program counter (reg)
reg [31:0] r_ea1_addr; // Effective address #1 (reg)
reg [31:0] r_ea2_addr; // Effective address #2 (reg)
reg [7:0] r_cpu_sr; // Status register high byte (reg)
wire [2:0] w_int_nr; // Interrupt number (wire)
wire w_cc_jump; // Condition code jump flag (wire)
wire [31:0] w_vec_addr; // Vector address (wire)
reg [15:0] r_md_lsh; // MUL/DIV left shifter (reg)
reg [31:0] r_md_acc; // MUL/DIV accumulator (reg)
wire [31:0] w_md_val; // Multiplier/Divisor (wire)
wire [31:0] w_md_res; // MUL/DIV partial result (wire)
wire w_borrow; // Subtract borrow
reg [15:0] r_ins_word; // Instruction word
wire w_ins_rdy; // Instruction word ready
reg [15:0] r_ext_word; // Extension word
wire w_ext_rdy; // Extension word ready
reg [15:0] r_imm_word; // Immediate word
wire w_imm_rdy; // Immediate word ready
wire [15:0] w_imm_val; // Immediate value
wire [11:0] w_dec_jump; // Decoder call address
wire [3:0] w_ea1_jump; // EA #1 jump table index
wire [3:0] w_ea2_jump; // EA #2 jump table index
reg r_io_ext; // Delayed io_ext
reg r_mem_rd; // Memory read (reg)
reg r_mem_wr; // Memory write (reg)
reg r_mem_err; // Address error during data access (reg)
reg [31:0] r_err_addr; // Address that caused an address error (reg)
reg [15:0] r_err_inst; // Opcode executed during an address error (reg)
reg [4:0] r_err_cpu; // CPU state during an address error (reg)
reg [31:0] w_mem_addr; // Memory address (wire)
reg [2:0] w_mem_inc; // Memory address increment (wire)
wire w_sp_inc; // Memory increment for stack access (wire)
wire [3:0] w_loop_cnt; // Loop count for MOVEM
reg [1:0] r_ctr;
assign dbg_pc = r_pc_addr;
assign w_sp_inc = ((r_ins_word[2:0] == 3'b111) && (inst_in[1:0] == 2'b00)) // EA1 with A7
|| ((r_ins_word[11:9] == 3'b111) && (inst_in[1:0] == 2'b01)) // EA2 with A7
? 1'b1 : 1'b0;
// Address MUX and increment
always@(inst_in or w_sp_inc or r_ea1_addr or r_ea2_addr or r_pc_addr or w_vec_addr)
begin
case (inst_in[1:0]) // addr field
2'b00 : w_mem_addr <= r_ea1_addr; // Read/write EA1 data
2'b01 : w_mem_addr <= r_ea2_addr; // Read/write EA2 data
2'b10 : w_mem_addr <= r_pc_addr; // Fetch instruction
2'b11 : w_mem_addr <= w_vec_addr; // Fetch vector
endcase
case ({inst_in[10]|inst_in[11], inst_in[3:2]}) // size & incr fields
3'b000 : w_mem_inc <= 3'b000; // No increment, byte
3'b001 : if (w_sp_inc)
w_mem_inc <= 3'b010; // Post increment, word (stack)
else
w_mem_inc <= 3'b001; // Post increment, byte
3'b010 : if (w_sp_inc)
w_mem_inc <= 3'b110; // Pre decrement, word (stack)
else
w_mem_inc <= 3'b111; // Pre decrement, byte
3'b011 : if (w_sp_inc)
w_mem_inc <= 3'b010; // Pre increment, word (stack)
else
w_mem_inc <= 3'b001; // Pre increment, byte
3'b100 : w_mem_inc <= 3'b000; // No increment, word
3'b101 : w_mem_inc <= 3'b010; // Post increment, word
3'b110 : w_mem_inc <= 3'b110; // Pre decrement, word
3'b111 : w_mem_inc <= 3'b010; // Pre increment, word
endcase
end
assign w_vec_addr = { 22'd0, r_vec_addr, 1'b0 };
// Registers read
always@(posedge rst or posedge clk)
begin
if (rst) begin
r_ins_word <= 16'h0000;
r_ext_word <= 16'h0000;
r_imm_word <= 16'h0000;
io_din <= 16'h0000;
io_rdy <= 1'b0;
r_ctr <= 2'b00;
end else begin
if (io_rd) begin
case (inst_in[3:0])
// Effective address #1
4'b0000 : io_din <= r_ea1_addr[15:0];
4'b0001 : io_din <= r_ea1_addr[31:16];
// Effective address #2
4'b0010 : io_din <= r_ea2_addr[15:0];
4'b0011 : io_din <= r_ea2_addr[31:16];
// Program
4'b0100 : io_din <= r_pc_addr[15:0];
4'b0101 : io_din <= r_pc_addr[31:16];
// Vectors
4'b0110 :
begin
io_din <= { 5'b00000, r_vec_addr[3:1], 8'h00 };
r_ctr <= 2'b00;
end
// CPU state
4'b0111 :
begin
case (r_ctr)
2'b00 : io_din <= r_err_inst;
2'b01 : io_din <= r_err_addr[15:0];
2'b10 : io_din <= r_err_addr[31:16];
2'b11 : io_din <= {11'b0, r_err_cpu };
endcase
r_ctr <= r_ctr + 2'd1;
end
// Immediate value
4'b1000 : io_din <= w_imm_val;
// MUL/DIV left shifter
4'b1001 : io_din <= r_md_lsh;
// MUL/DIV accumulator
4'b1010 : io_din <= r_md_acc[15:0];
4'b1011 : io_din <= r_md_acc[31:16];
// Jump table indexes
4'b1100 : io_din <= { 4'd0, w_dec_jump };
4'b1101 : io_din <= { 12'd0, w_ea1_jump };
4'b1110 : io_din <= { 12'd0, w_ea2_jump };
// Status register : T-S--III---XNZVC
4'b1111 : io_din <= { r_cpu_sr[7], 1'b0, r_cpu_sr[5], 2'b00, r_cpu_sr[2:0], 3'b000, ccr_in };
default : io_din <= 16'h0000;
endcase
end else if ((r_mem_rd) && (data_ack)) begin
// Memory read
case ({ inst_in[11:10], address[0] })
// Byte, even addr. : --- use
3'b000 : io_din <= { rd_data[7:0], rd_data[15:8] };
// Byte, odd addr. : --- use
3'b001 : io_din <= { rd_data[15:8], rd_data[7:0] };
// Word, even addr. : use use
3'b010 : io_din <= { rd_data[15:8], rd_data[7:0] };
// Word, odd addr. : !! exception !!
3'b011 : io_din <= { rd_data[15:8], rd_data[7:0] };
// LSB, even addr. : --- use
3'b100 : io_din <= { 8'b0000_0000, rd_data[15:8] };
// LSB, odd addr. : --- use
3'b101 : io_din <= { 8'b0000_0000, rd_data[7:0] };
// MSB, even addr. : use ---
3'b110 : io_din <= { rd_data[15:8], 8'b0000_0000 };
// MSB, odd addr. : use ---
3'b111 : io_din <= { rd_data[7:0], 8'b0000_0000 };
endcase
// Instruction fetch
if (inst_in[1:0] == 2'b10)
case (inst_in[3:2])
2'b00 : r_ins_word <= rd_data; // Fetching instruction
2'b01 : r_ext_word <= rd_data; // Fetching extension word
default : r_imm_word <= rd_data; // Fetching immediate data
endcase
end else begin
io_din <= 16'h0000;
end
// Ready signal for register read, memory read and write
io_rdy <= io_rd | (r_mem_rd & data_ack) | (r_mem_wr & data_ack) | r_mem_err;
end
end
// Status bits for the test module : T-SaeIII--b
assign sr_out[10] = r_cpu_sr[7]; // Trace
assign sr_out[9] = 1'b0; // Not used
assign sr_out[8] = r_cpu_sr[5]; // Supervisor
assign sr_out[7] = r_cpu_sr[4]|r_mem_err; // Address error (internal)
assign sr_out[6] = r_cpu_sr[3]|r_cpu_sr[4]|r_mem_err; // Exception (internal)
assign sr_out[5:3] = r_cpu_sr[2:0]; // Interrupt level
assign sr_out[2:1] = 2'b00; // Not used
assign sr_out[0] = w_cc_jump; // Branch flag
// Registers writes
always@(posedge rst or posedge clk)
begin
if (rst) begin
r_vec_addr <= 9'd0;
r_pc_addr <= 32'd0;
r_ea1_addr <= 32'd0;
r_ea2_addr <= 32'd0;
r_md_lsh <= 16'd0;
r_md_acc <= 32'd0;
v_flg <= 1'b0;
r_cpu_sr <= 8'b00100111;
flg_c <= 11'b00_00_000_00_00;
end else begin
if (io_wr) begin
case (inst_in[3:0])
// Effective address #1 (and #2 for RMW cycles)
4'b0000 :
begin
r_ea1_addr[15:0] <= io_dout;
r_ea2_addr[15:0] <= io_dout;
end
4'b0001 :
begin
r_ea1_addr[31:16] <= io_dout;
r_ea2_addr[31:16] <= io_dout;
end
// Effective address #2
4'b0010 : r_ea2_addr[15:0] <= io_dout;
4'b0011 : r_ea2_addr[31:16] <= io_dout;
// Program
4'b0100 : r_pc_addr[15:0] <= io_dout;
4'b0101 : r_pc_addr[31:16] <= io_dout;
// Vectors
4'b0110 :
begin
r_vec_addr <= { io_dout[9:2], 1'b0 };
r_cpu_sr[4] <= 1'b0; // Clear address error
end
4'b0111 : ; // No VBR on 68000, vector address is 9-bit long !
// MUL/DIV left shifer
4'b1001 : r_md_lsh <= io_dout;
// MUL/DIV accumulator
4'b1010 : r_md_acc[15:0] <= io_dout;
4'b1011 : r_md_acc[31:16] <= io_dout;
// Status register
4'b1111 :
begin
// MSB (word write)
if (inst_in[10]) begin
r_cpu_sr[7] <= io_dout[15]; // Trace
r_cpu_sr[6] <= 1'b0;
r_cpu_sr[5] <= io_dout[13]; // Supervisor
r_cpu_sr[2:0] <= io_dout[10:8]; // Interrupt mask
end
// LSB
flg_c[10] <= 1'b1;
flg_c[9] <= io_dout[4]; // Extend flag
flg_c[8] <= 1'b1;
flg_c[7] <= io_dout[3]; // Negative flag
flg_c[6] <= 1'b0;
flg_c[5] <= 1'b1;
flg_c[4] <= io_dout[2]; // Zero flag
flg_c[3] <= 1'b1;
flg_c[2] <= io_dout[1]; // Overflow flag
flg_c[1] <= 1'b1;
flg_c[0] <= io_dout[0]; // Carry flag
end
default : ;
endcase
end else begin
flg_c <= 11'b00_00_000_00_00;
// Memory control
if ((io_ext) && (!r_io_ext)) begin
// Auto-increment/decrement
case (inst_in[1:0]) // addr field
2'b00 : r_ea1_addr <= r_ea1_addr + { {29{w_mem_inc[2]}}, w_mem_inc };
2'b01 : r_ea2_addr <= r_ea2_addr + { {29{w_mem_inc[2]}}, w_mem_inc };
2'b10 : r_pc_addr <= r_pc_addr + 32'd2;
2'b11 : r_vec_addr <= r_vec_addr + 9'd1;
endcase
end
// Multiply/divide step (right shift special)
if (alu_op[3:1] == 3'b111) begin
// Accumulator
if ((alu_op[0]) || (w_borrow))
r_md_acc <= w_md_res;
// Left shifter
r_md_lsh <= { r_md_lsh[14:0], w_borrow };
// V flag
if (cc_upd) v_flg <= r_md_lsh[15];
end
// Interrupts management
if (((w_int_nr > r_cpu_sr[2:0]) || (w_int_nr == 3'd7)) && (w_int_nr >= r_vec_addr[3:1]) && (r_vec_addr[8:4] == 5'b00011)) begin
r_cpu_sr[3] <= 1'b1;
r_vec_addr <= { 5'b00011, w_int_nr, 1'b0 };
end else begin
r_cpu_sr[3] <= r_cpu_sr[4] | r_cpu_sr[7]; // Address error or trace mode
end
// Latch address error flag
if (r_mem_err) r_cpu_sr[4] <= 1'b1;
end
end
end
// Interrupt number
assign w_int_nr = ~ipl_n;
// Multiply/divide step
assign w_md_val = (r_md_lsh[15]) || (!alu_op[0]) ? { b_src, a_src } : 32'd0;
addsub_32 addsub_inst
(
.add_sub(alu_op[0]),
.dataa(r_md_acc),
.datab(w_md_val),
.cout(w_borrow),
.result(w_md_res)
);
// Debug : instruction fetch signal
assign dbg_if = (inst_in[3:0] == 4'b0010) ? io_ext & ~r_io_ext : 1'b0;
// Memory access
always@(posedge rst or posedge clk)
begin
if (rst) begin
r_io_ext <= 1'b0;
address <= 32'd0;
r_mem_rd <= 1'b0;
rd_ena <= 1'b0;
r_mem_wr <= 1'b0;
wr_ena <= 1'b0;
byte_ena <= 2'b00;
r_mem_err <= 1'b0;
r_err_addr <= 32'd0;
r_err_inst <= 16'h0000;
r_err_cpu <= 5'b00000;
wr_data <= 16'h0000;
end else begin
// Delayed io_ext
r_io_ext <= io_ext;
// Memory address and data output
if ((io_ext) && (!r_io_ext) && ((!inst_in[3]) || (inst_in[1]))) begin
// No or Post increment
address <= w_mem_addr;
// Function code
fc[2] <= r_cpu_sr[5]; // 0 : User, 1 : Supervisor
case (inst_in[1:0])
2'b00 : fc[1:0] <= 2'b01; // EA1 : data
2'b01 : fc[1:0] <= 2'b01; // EA2 : data
2'b10 : fc[1:0] <= 2'b10; // PC : program
2'b11 : fc[1:0] <= 2'b11; // Vector : CPU
endcase
// Memory write
case ({ inst_in[11:10], w_mem_addr[0] })
// Byte, even addr. : --- use
3'b000 : wr_data <= { io_dout[7:0], io_dout[15:8] };
// Byte, odd addr. : --- use
3'b001 : wr_data <= { io_dout[15:8], io_dout[7:0] };
// Word, even addr. : use use
3'b010 : wr_data <= { io_dout[15:8], io_dout[7:0] };
// Word, odd addr. : !! exception !!
3'b011 : wr_data <= { io_dout[15:8], io_dout[7:0] };
// LSB, even addr. : use ---
3'b100 : wr_data <= { io_dout[7:0], io_dout[15:8] };
// LSB, odd addr. : --- use
3'b101 : wr_data <= { io_dout[15:8], io_dout[7:0] };
// MSB, even addr. : use ---
3'b110 : wr_data <= { io_dout[15:8], io_dout[7:0] };
// MSB, odd addr. : --- use
3'b111 : wr_data <= { io_dout[7:0], io_dout[15:8] };
endcase
end else if ((r_io_ext) && (inst_in[3]) && (!inst_in[1])) begin
address <= w_mem_addr; // Pre decrement/increment
// Function code
fc[2] <= r_cpu_sr[5]; // 0 : User, 1 : Supervisor
case (inst_in[1:0])
2'b00 : fc[1:0] <= 2'b01; // EA1 : data
2'b01 : fc[1:0] <= 2'b01; // EA2 : data
2'b10 : fc[1:0] <= 2'b10; // PC : program
2'b11 : fc[1:0] <= 2'b11; // Vector : CPU
endcase
// Memory write
case ({ inst_in[11:10], w_mem_addr[0] })
// Byte, even addr. : --- use
3'b000 : wr_data <= { io_dout[7:0], io_dout[15:8] };
// Byte, odd addr. : --- use
3'b001 : wr_data <= { io_dout[15:8], io_dout[7:0] };
// Word, even addr. : use use
3'b010 : wr_data <= { io_dout[15:8], io_dout[7:0] };
// Word, odd addr. : !! exception !!
3'b011 : wr_data <= { io_dout[15:8], io_dout[7:0] };
// LSB, even addr. : use ---
3'b100 : wr_data <= { io_dout[7:0], io_dout[15:8] };
// LSB, odd addr. : --- use
3'b101 : wr_data <= { io_dout[15:8], io_dout[7:0] };
// MSB, even addr. : use ---
3'b110 : wr_data <= { io_dout[15:8], io_dout[7:0] };
// MSB, odd addr. : --- use
3'b111 : wr_data <= { io_dout[7:0], io_dout[15:8] };
endcase
end
// Read, write and byte strobes
if ((io_ext) && (!r_io_ext)) begin
r_mem_rd <= inst_in[7];
r_mem_wr <= inst_in[6];
case ({ inst_in[11:10], w_mem_addr[0] })
3'b000 : byte_ena <= { ~(inst_in[3] & ~inst_in[1]), (inst_in[3] & ~inst_in[1]) };
3'b001 : byte_ena <= { (inst_in[3] & ~inst_in[1]), ~(inst_in[3] & ~inst_in[1]) };
3'b010 : byte_ena <= 2'b11;
3'b011 : // Word access at odd address !!
begin
byte_ena <= 2'b00; // No read/write
r_mem_err <= 1'b1; // Address error
r_err_addr <= w_mem_addr; // Keep EA value
r_err_inst <= r_ins_word; // Keep opcode
case (inst_in[1:0])
2'b00 : r_err_cpu[1:0] <= 2'b01; // EA1 : data
2'b01 : r_err_cpu[1:0] <= 2'b01; // EA2 : data
2'b10 : r_err_cpu[1:0] <= 2'b10; // PC : program
2'b11 : r_err_cpu[1:0] <= 2'b11; // Vector : CPU
endcase
r_err_cpu[2] <= r_cpu_sr[5]; // 0 : User, 1 : Supervisor
r_err_cpu[3] <= 1'b0; // Instruction identified
r_err_cpu[4] <= inst_in[7]; // 0 : Write, 1 : Read
end
3'b100 : byte_ena <= 2'b10;
3'b101 : byte_ena <= 2'b01;
3'b110 : byte_ena <= 2'b10;
3'b111 : byte_ena <= 2'b01;
endcase
end
// Keep PC value for address error exception
if ((io_wr) && (inst_in[3:1] == 3'b010)) begin
if (inst_in[0])
r_err_addr[31:16] <= io_dout;
else
r_err_addr[15:0] <= io_dout;
// Address error if odd address on PC
if ((!inst_in[0]) && (io_dout[0])) begin
r_mem_err <= 1'b1; // Address error
r_err_inst <= r_ins_word; // Keep opcode
r_err_cpu <= { 2'b10, r_cpu_sr[5], 2'b10 };
end
end
// End of memory cycle : acknowledge or error
if ((data_ack) || (r_mem_err)) begin
r_mem_rd <= 1'b0;
rd_ena <= 1'b0;
r_mem_wr <= 1'b0;
wr_ena <= 1'b0;
byte_ena <= 2'b00;
r_mem_err <= 1'b0;
fc <= { r_cpu_sr[5], 2'b00 }; // No access
end else begin
rd_ena <= (inst_in[7] & (~inst_in[3] | inst_in[1]) & io_ext) | r_mem_rd;
wr_ena <= (inst_in[6] & (~inst_in[3] | inst_in[1]) & io_ext) | r_mem_wr;
end
end
end
// Instruction decoder
//assign w_ins_rdy = (inst_in[3:0] == 4'b0010) ? (data_ack & r_mem_rd & r_io_ext) : 1'b0;
assign w_ins_rdy = (inst_in[3:0] == 4'b0010) ? (io_rdy & r_io_ext) : 1'b0;
assign w_ext_rdy = (inst_in[3:0] == 4'b0110) ? (io_rdy & r_io_ext) : 1'b0;
assign w_imm_rdy = (inst_in[3:0] == 4'b1010) ? (io_rdy & r_io_ext) : 1'b0;
decode decode_inst
(
.rst(rst),
.clk(clk),
.ins_rdy(w_ins_rdy),
.instr(r_ins_word),
.ext_rdy(w_ext_rdy),
.ext_wd(r_ext_word),
.imm_rdy(w_imm_rdy),
.imm_wd(r_imm_word),
.user_mode(~r_cpu_sr[5]),
.ccr_in(ccr_in[3:0]),
.dec_jmp(w_dec_jump),
.ea1_jmp(w_ea1_jump),
.ea2_jmp(w_ea2_jump),
.imm_val(w_imm_val),
.ea1_bit(ea1b),
.cc_jmp(w_cc_jump),
.ext_inst(),
.bit_inst(),
.vld_inst()
);
assign insw = r_ins_word;
assign extw = r_ext_word;
// Registers access
assign w_loop_cnt = ea1b[4] ? loop_cnt : ~loop_cnt;
always@(io_reg or inst_in or r_ins_word or r_ext_word or w_loop_cnt)
begin
case (inst_in[3:0])
4'b0000 : reg_addr <= { 2'b10, r_ins_word[2:0], inst_in[8] }; // D[EA1]
4'b0001 : reg_addr <= { 2'b11, r_ins_word[2:0], inst_in[8] }; // A[EA1]
4'b0010 : reg_addr <= { 1'b1, r_ins_word[3:0], inst_in[8] }; // R[EA1]
4'b0011 : reg_addr <= { 5'b11111, inst_in[8] }; // A7
4'b0100 : reg_addr <= { 2'b10, r_ins_word[11:9], inst_in[8] }; // D[EA2]
4'b0101 : reg_addr <= { 2'b11, r_ins_word[11:9], inst_in[8] }; // A[EA2]
4'b0110 : reg_addr <= { 1'b1, r_ins_word[6], r_ins_word[11:9], inst_in[8] }; // R[EA2]
4'b0111 : reg_addr <= { 1'b1, w_loop_cnt, inst_in[8] }; // R[CNT]
4'b1000 : reg_addr <= { 2'b10, r_ext_word[14:12], inst_in[8] }; // D[EXT]
4'b1001 : reg_addr <= { 2'b11, r_ext_word[14:12], inst_in[8] }; // A[EXT]
4'b1010 : reg_addr <= { 1'b1, r_ext_word[15:12], inst_in[8] }; // R[EXT]
default : reg_addr <= { 2'b01, inst_in[2:0], inst_in[8] }; // VBR, TMP1, TMP2, USP, SSP
endcase
reg_wr <= inst_in[6] & io_reg;
reg_bena[0] <= io_reg;
reg_bena[1] <= inst_in[10] & io_reg;
end
endmodule
module decode
(
input rst,
input clk,
input ins_rdy,
input [15:0] instr,
input ext_rdy,
input [15:0] ext_wd,
input imm_rdy,
input [15:0] imm_wd,
input user_mode,
input [3:0] ccr_in,
output [11:0] dec_jmp,
output [3:0] ea1_jmp,
output [3:0] ea2_jmp,
output reg [15:0] imm_val,
output [15:0] ea1_bit,
output reg cc_jmp,
output ext_inst,
output bit_inst,
output vld_inst
);
// $FE00 - $FEFF : Instruction decoder jump table
// $FF00 - $FF1F : Empty
// $FF20 - $FF2F : EA1 read BYTE jump table
// $FF30 - $FF3F : EA1 read WORD jump table
// $FF40 - $FF4F : EA1 read LONG jump table
// $FF50 - $FF5F : EA1 calculation jump table
// $FF60 - $FF6F : EA1 write BYTE jump table
// $FF70 - $FF7F : EA1 write WORD jump table
// $FF80 - $FF8F : EA1 write LONG jump table
// $FF90 - $FF9F : EA2 write BYTE jump table
// $FFA0 - $FFAF : EA2 write WORD jump table
// $FFB0 - $FFBF : EA2 write LONG jump table
// $FFC0 - $FFCF : Bit masks
// $FFD0 - $FFD5 : Empty
// $FFD6 - $FFD7 : VBR
// $FFD8 - $FFD9 : TMP1
// $FFDA - $FFDB : TMP2
// $FFDC - $FFDD : USP
// $FFDE - $FFDF : SSP
// $FFE0 - $FFEF : Data registers (D0 - D7)
// $FFF0 - $FFFF : Address registers (A0 - A7)
// +---------------------+-------+----------------+------------------+
// | Index | | | |
// | Decimal | Binary | Group | Description | Op-code |
// +----------+----------+-------+----------------+------------------+
// | 0..63 | 00xxxxxx | 4 | miscellaneous | 0100111001xxxxxx |
// | 64..95 | 010xxxxx | 0 | immediate | 0000xxx0xx------ |
// | 96..127 | 011xxxxx | 4 | one operand | 0100xxx0xx------ |
// | 128..143 | 1000xxxx | E | shift byte reg | 1110---x00xxx--- |
// | 144..159 | 1001xxxx | E | shift word reg | 1110---x01xxx--- |
// | 160..175 | 1010xxxx | E | shift long reg | 1110---x10xxx--- |
// | 177 | 10110001 | 1 | MOVE.B | 0001------------ |
// | 178 | 10110010 | 2 | MOVE.L | 0010------------ |
// | 179 | 10110011 | 3 | MOVE.W | 0011------------ |
// | 182 | 10110110 | 6 | Bcc | 0110------------ |
// | 183 | 10110111 | 7 | MOVEQ | 0111------------ |
// | 186 | 10111010 | A | Line A | 1010------------ |
// | 191 | 10111111 | F | Line F | 1111------------ |
// | 192..199 | 11000xxx | 8 | OR/DIVx | 1000---xxx------ |
// | 200..207 | 11001xxx | 9 | SUB | 1001---xxx------ |
// | 208..215 | 11010xxx | 5 | ADDQ/SUBQ | 0101---xxx------ |
// | 216..223 | 11011xxx | B | CMP/EOR | 1011---xxx------ |
// | 224..231 | 11100xxx | C | AND/MULx | 1100---xxx------ |
// | 232..239 | 11101xxx | D | ADD | 1101---xxx------ |
// | 240..247 | 11110xxx | E | shift memory | 1110---011xxx--- |
// | 248..251 | 111110xx | 0 | bit operation | 0000---1xx------ |
// | 252..255 | 111111xx | 4 | two operands | 0100---1xx------ |
// +----------+----------+-------+----------------+------------------+
// Trap routines addresses
`define OP_PRIVILEDGED 12'h036
`define OP_ILLEGAL 12'h038
// Instructions groups
wire [15:0] w_grp_p0;
// Effective address bitfields
wire [15:0] w_ea1b_p0; // EA #1
reg [15:0] r_ea1b_p1;
wire [9:0] w_ea2b_p0; // EA #2
// Jump table indexes
wire [3:0] w_ea1_jmp_p0; // EA #1
reg [3:0] r_ea1_jmp_p1;
//reg [3:0] r_ea1_jmp_p2;
wire [3:0] w_ea2_jmp_p0; // EA #2
reg [3:0] r_ea2_jmp_p1;
//reg [3:0] r_ea2_jmp_p2;
// Instructions sub-groups
wire w_g0_immed_p0;
wire w_g0_bitimm_p0;
wire w_g0_bitop_p0;
wire w_g4_misc_p0;
wire w_g4_oneop_p0;
wire w_g4_twoop_p0;
wire w_g5_addsub_p0;
wire w_g6_bsr_p0;
wire w_gE_shmem_p0;
wire w_gE_shreg_p0;
// NEGX, ADDX, SUBX, NBCD, ABCD, SBCD
wire w_g4_nbcd_p0;
wire w_g8_sbcd_p0;
wire w_gC_abcd_p0;
wire w_g4_negx_p0;
wire w_g9_subx_p0;
wire w_gD_addx_p0;
// Pre-decode
wire w_ill_ins_p0; // Illegal instruction
reg r_ill_ins_p1;
wire w_prv_ins_p0; // Priviledged instruction
reg r_prv_ins_p1;
wire w_ext_ins_p0; // Special Z flag treatment
reg r_ext_ins_p1;
//reg r_ext_ins_p2;
wire w_bit_ins_p0; // Bit manipulation instructions
reg r_bit_ins_p1;
//reg r_bit_ins_p2;
reg w_vld_ins_p1; // Valid instruction
reg r_vld_ins_p2;
// Call address
wire w_call1_ena_p0; // Jump table call #1 enable
wire w_call2_ena_p0; // Jump table call #2 enable
reg [1:0] r_call_en_p1;
reg [11:0] r_call_p2;
// Indexes
wire [5:0] w_idx6_5_0_p0; // 5..0
wire [5:0] w_idx5_B_6_p0; // 11..9, 7..6
wire [5:0] w_idx4_8_3_p0; // 8, 5..3
wire [5:0] w_idx4_F_C_p0; // 15..12
wire [5:0] w_idx3_8_6_p0; // 8..6
wire [5:0] w_idx3_A_8_p0; // 10..8
wire [5:0] w_idx2_7_6_p0; // 7..6
// Decoder ROM
wire [7:0] w_addr_p0; // Decoder ROM address
wire [35:0] w_data_p1; // Decoder ROM data
reg [15:0] w_ea1m_p1; // Effective address #1 mask
reg [5:0] w_incr_p1; // Call address increment
reg [11:0] w_call_p1; // Call address
// Immediate values
wire [15:0] w_imm3_i; // For ADDQ, SUBQ, Shift reg
wire [15:0] w_imm4_i; // For TRAP
wire [15:0] w_imm8_i; // For MOVEQ, Bcc.B
wire [15:0] w_imm5_e; // For BTST, BCHG, BCLR, BSET
wire [15:0] w_imm8_e; // For d8(An, Rn), d8(PC, Rn)
// Instructions groups decode
assign w_grp_p0[0] = (instr[15:12] == 4'b0000) ? 1'b1 : 1'b0; // Immed
assign w_grp_p0[1] = (instr[15:12] == 4'b0001) ? 1'b1 : 1'b0; // MOVE.B
assign w_grp_p0[2] = (instr[15:12] == 4'b0010) ? 1'b1 : 1'b0; // MOVE.L
assign w_grp_p0[3] = (instr[15:12] == 4'b0011) ? 1'b1 : 1'b0; // MOVE.W
assign w_grp_p0[4] = (instr[15:12] == 4'b0100) ? 1'b1 : 1'b0; // Misc
assign w_grp_p0[5] = (instr[15:12] == 4'b0101) ? 1'b1 : 1'b0; // ADDQ, SUBQ
assign w_grp_p0[6] = (instr[15:12] == 4'b0110) ? 1'b1 : 1'b0; // Bcc
assign w_grp_p0[7] = (instr[15:12] == 4'b0111) ? 1'b1 : 1'b0; // MOVEQ
assign w_grp_p0[8] = (instr[15:12] == 4'b1000) ? 1'b1 : 1'b0; // OR, DIV
assign w_grp_p0[9] = (instr[15:12] == 4'b1001) ? 1'b1 : 1'b0; // SUB
assign w_grp_p0[10] = (instr[15:12] == 4'b1010) ? 1'b1 : 1'b0; // Line A
assign w_grp_p0[11] = (instr[15:12] == 4'b1011) ? 1'b1 : 1'b0; // CMP, EOR
assign w_grp_p0[12] = (instr[15:12] == 4'b1100) ? 1'b1 : 1'b0; // AND, MUL
assign w_grp_p0[13] = (instr[15:12] == 4'b1101) ? 1'b1 : 1'b0; // ADD
assign w_grp_p0[14] = (instr[15:12] == 4'b1110) ? 1'b1 : 1'b0; // Shift
assign w_grp_p0[15] = (instr[15:12] == 4'b1111) ? 1'b1 : 1'b0; // Line F
// Effective addresses #1 bitfield
assign w_ea1b_p0[15] = (instr[5:0] == 6'b111111) ? 1'b1 : 1'b0; // ???
assign w_ea1b_p0[14] = (instr[5:0] == 6'b111110) ? 1'b1 : 1'b0; // ???
assign w_ea1b_p0[13] = (instr[5:0] == 6'b111101) ? 1'b1 : 1'b0; // ???
assign w_ea1b_p0[12] = (instr[5:0] == 6'b111100) ? 1'b1 : 1'b0; // #imm, CCR/SR
assign w_ea1b_p0[11] = (instr[5:0] == 6'b111011) ? 1'b1 : 1'b0; // d8(PC,Rn)
assign w_ea1b_p0[10] = (instr[5:0] == 6'b111010) ? 1'b1 : 1'b0; // d16(PC)
assign w_ea1b_p0[9] = (instr[5:0] == 6'b111001) ? 1'b1 : 1'b0; // xxxxxxxx.L
assign w_ea1b_p0[8] = (instr[5:0] == 6'b111000) ? 1'b1 : 1'b0; // xxxx.W
assign w_ea1b_p0[7] = (instr[5:4] == 2'b00) ? 1'b1 : 1'b0; // Bcc.W
assign w_ea1b_p0[6] = (instr[5:3] == 3'b110) ? 1'b1 : 1'b0; // d8(An,Rn)
assign w_ea1b_p0[5] = (instr[5:3] == 3'b101) ? 1'b1 : 1'b0; // d16(An)
assign w_ea1b_p0[4] = (instr[5:3] == 3'b100) ? 1'b1 : 1'b0; // -(An)
assign w_ea1b_p0[3] = (instr[5:3] == 3'b011) ? 1'b1 : 1'b0; // (An)+
assign w_ea1b_p0[2] = (instr[5:3] == 3'b010) ? 1'b1 : 1'b0; // (An)
assign w_ea1b_p0[1] = (instr[5:3] == 3'b001) ? 1'b1 : 1'b0; // An
assign w_ea1b_p0[0] = (instr[5:3] == 3'b000) ? 1'b1 : 1'b0; // Dn
// Effective addresses #2 bitfield
assign w_ea2b_p0[9] = (instr[8:6] == 3'b111)
&& (instr[11:10] != 2'b00) ? 1'b1 : 1'b0; // ???
assign w_ea2b_p0[8] = (instr[11:6] == 6'b001111) ? 1'b1 : 1'b0; // xxxxxxxx.L
assign w_ea2b_p0[7] = (instr[11:6] == 6'b000111) ? 1'b1 : 1'b0; // xxxx.W
assign w_ea2b_p0[6] = (instr[8:6] == 3'b110) ? 1'b1 : 1'b0; // d8(An,Rn)
assign w_ea2b_p0[5] = (instr[8:6] == 3'b101) ? 1'b1 : 1'b0; // d16(An)
assign w_ea2b_p0[4] = (instr[8:6] == 3'b100) ? 1'b1 : 1'b0; // -(An)
assign w_ea2b_p0[3] = (instr[8:6] == 3'b011) ? 1'b1 : 1'b0; // (An)+
assign w_ea2b_p0[2] = (instr[8:6] == 3'b010) ? 1'b1 : 1'b0; // (An)
assign w_ea2b_p0[1] = (instr[8:6] == 3'b001) ? 1'b1 : 1'b0; // An
assign w_ea2b_p0[0] = (instr[8:6] == 3'b000) ? 1'b1 : 1'b0; // Dn
// Effective addresses indexes (6-bit EA field -> 4-bit index)
assign w_ea1_jmp_p0[3] = (instr[5:3] == 3'b111) ? 1'b1 : 1'b0;
assign w_ea1_jmp_p0[2:0] = (instr[5:3] == 3'b111) ? instr[2:0] : instr[5:3];
assign w_ea2_jmp_p0[3] = (instr[8:6] == 3'b111) ? 1'b1 : 1'b0;
assign w_ea2_jmp_p0[2:0] = (instr[8:6] == 3'b111) ? instr[11:9] : instr[8:6];
// Instructions sub-groups decode
assign w_g0_immed_p0 = w_grp_p0[0] & ~instr[8];
assign w_g0_bitimm_p0 = (instr[15:8] == 8'b0000_1000) ? 1'b1 : 1'b0;
assign w_g0_bitop_p0 = w_grp_p0[0] & instr[8];
assign w_g4_misc_p0 = (instr[15:6] == 10'b0100_111_001) ? 1'b1 : 1'b0;
assign w_g4_oneop_p0 = w_grp_p0[4] & ~instr[8] & ~w_g4_misc_p0;
assign w_g4_twoop_p0 = w_grp_p0[4] & instr[8];
assign w_g5_addsub_p0 = w_grp_p0[5] & ~(instr[7] & instr[6]);
assign w_g6_bsr_p0 = (instr[11:8] == 4'b0001) ? 1'b1 : 1'b0;
assign w_gE_shmem_p0 = w_grp_p0[14] & instr[7] & instr[6];
assign w_gE_shreg_p0 = w_grp_p0[14] & ~(instr[7] & instr[6]);
// Special Z flag treatment for NBCD, SBCD, ABCD, NEGX, SUB, ADDX
assign w_g4_nbcd_p0 = (w_grp_p0[4]) && (instr[11:6] == 6'b100000) ? 1'b1 : 1'b0;
assign w_g8_sbcd_p0 = (w_grp_p0[8]) && (instr[8:4] == 5'b10000) ? 1'b1 : 1'b0;
assign w_gC_abcd_p0 = (w_grp_p0[12]) && (instr[8:4] == 5'b10000) ? 1'b1 : 1'b0;
assign w_g4_negx_p0 = (w_grp_p0[4]) && (instr[11:8] == 4'b0000) ? 1'b1 : 1'b0;
assign w_g9_subx_p0 = (w_grp_p0[9]) && ((instr[8:4] == 5'b10000) ||
(instr[8:4] == 5'b10100) ||
(instr[8:4] == 5'b11000)) ? 1'b1 : 1'b0;
assign w_gD_addx_p0 = (w_grp_p0[13]) && ((instr[8:4] == 5'b10000) ||
(instr[8:4] == 5'b10100) ||
(instr[8:4] == 5'b11000)) ? 1'b1 : 1'b0;
assign w_ext_ins_p0 = w_g4_negx_p0 | w_g9_subx_p0 | w_gD_addx_p0
| w_g4_nbcd_p0 | w_g8_sbcd_p0 | w_gC_abcd_p0;
// Bit manipulation instructions
assign w_bit_ins_p0 = w_g0_bitop_p0 | w_g0_bitimm_p0;
// Illegal instruction pre-decode (not present in the jump table)
assign w_ill_ins_p0 = (w_grp_p0[1] & w_ea2b_p0[1]) // MOVE.B An,<ea>
| (w_grp_p0[1] & w_ea2b_p0[9]) // MOVE.B <ea>,???
| (w_grp_p0[2] & w_ea2b_p0[9]) // MOVE.L <ea>,???
| (w_grp_p0[3] & w_ea2b_p0[9]) // MOVE.W <ea>,???
| (w_grp_p0[7] & instr[8]) // Coldfire's MVS/MVZ instr.
| (w_grp_p0[14] & instr[11] & instr[7] & instr[6]); // Empty slots in shift instr.
// Priviledged instruction pre-decode
assign w_prv_ins_p0 = ((w_grp_p0[0]) && (instr[6]) && (w_ea1b_p0[12])) // Log. immed SR
|| ((w_g4_misc_p0) && ((instr[6:4] == 2'b10) || // MOVE USP
(instr[6:0] == 6'b110000) || // RESET
(instr[6:1] == 6'b11001))) // STOP, RTE
|| ((w_grp_p0[4]) && (instr[11:6] == 6'b011011)) // MOVE <ea>,SR
? user_mode : 1'b0;
// Jump table call #1 enable
assign w_call1_ena_p0 = (w_grp_p0[0] & w_ea1b_p0[0]) // Bit op. reg
| (w_grp_p0[2] & w_ea2b_p0[1]) // MOVEA.L
| (w_grp_p0[3] & w_ea2b_p0[1]) // MOVEA.W
| (w_grp_p0[4] & ~w_g4_misc_p0 & w_ea1b_p0[0]) // SWAP, EXT
| (w_grp_p0[6] & w_g6_bsr_p0) // BSR
| (w_grp_p0[8] & w_ea1b_p0[0]) // SBCD reg
| (w_grp_p0[9] & w_ea1b_p0[0]) // SUBX reg
| (w_grp_p0[12] & w_ea1b_p0[0]) // ABCD reg, EXG
| (w_grp_p0[13] & w_ea1b_p0[0]); // ADDX reg
// Jump table call #2 enable
assign w_call2_ena_p0 = (w_grp_p0[0] & ~instr[8] & w_ea1b_p0[12]) // Log op. SR
| (w_grp_p0[0] & instr[8] & w_ea1b_p0[1]) // MOVEP
| (w_grp_p0[4] & ~w_g4_misc_p0 & w_ea1b_p0[3]) // MOVEM (An)+<list>
| (w_grp_p0[4] & ~w_g4_misc_p0 & w_ea1b_p0[4]) // MOVEM <list>,-(An)
| (w_grp_p0[5] & w_ea1b_p0[1]) // ADDQA, SUBQA, DBcc
| (w_grp_p0[8] & w_ea1b_p0[1]) // SBCD mem
| (w_grp_p0[9] & w_ea1b_p0[1]) // SUBX mem
| (w_grp_p0[11] & w_ea1b_p0[1]) // CMPM
| (w_grp_p0[12] & w_ea1b_p0[1]) // ABCD mem, EXG
| (w_grp_p0[13] & w_ea1b_p0[1]); // ADDX mem
// 6-bit indexes calculations
assign w_idx6_5_0_p0 = (w_g4_misc_p0)
? instr[5:0]
: 6'b000000;
assign w_idx5_B_6_p0 = (w_g0_immed_p0 | w_g4_oneop_p0)
? { instr[14], instr[11:9], instr[7:6] }
: 6'b000000;
assign w_idx4_8_3_p0 = (w_gE_shreg_p0)
? { instr[7:6], instr[8], instr[5:3] }
: 6'b000000;
assign w_idx4_F_C_p0 = (w_grp_p0[1] | w_grp_p0[2] | w_grp_p0[3] | w_grp_p0[6] | w_grp_p0[7] | w_grp_p0[10] | w_grp_p0[15])
? { 2'b11, instr[15:12] }
: 6'b000000;
assign w_idx3_8_6_p0 = (w_grp_p0[5] | w_grp_p0[8] | w_grp_p0[9] | w_grp_p0[11] | w_grp_p0[12] | w_grp_p0[13])
? { instr[14] ^ ~instr[15], instr[13] ^ ~instr[15], instr[12] ^ ~instr[15], instr[8:6] }
: 6'b000000;
assign w_idx3_A_8_p0 = (w_gE_shmem_p0)
? { 3'b110, instr[10:8] }
: 6'b000000;
assign w_idx2_7_6_p0 = (w_g0_bitop_p0 | w_g4_twoop_p0)
? { 3'b111, instr[14], instr[7:6] }
: 6'b000000;
// 256-entry table index (16-bit instr. -> 8-bit index)
assign w_addr_p0[7] = ((instr[12] | instr[13]) & ~instr[15]) // Groups #1,2,3,5,6,7
| instr[15] | w_g0_bitop_p0 | w_g4_twoop_p0; // Groups #8-15
assign w_addr_p0[6] = w_grp_p0[5] | w_grp_p0[8] | w_grp_p0[9]
| w_grp_p0[11] | w_grp_p0[12] | w_grp_p0[13]
| w_g0_immed_p0 | w_g0_bitop_p0 | w_g4_oneop_p0
| w_g4_twoop_p0 | w_gE_shmem_p0;
assign w_addr_p0[5:0] = w_idx6_5_0_p0 | w_idx5_B_6_p0 | w_idx4_8_3_p0
| w_idx4_F_C_p0 | w_idx3_8_6_p0 | w_idx3_A_8_p0
| w_idx2_7_6_p0;
// Jump table ROM
decode_rom rom_inst
(
.clock(clk),
.address(w_addr_p0),
.q(w_data_p1)
);
always@(w_data_p1 or r_ea1b_p1 or r_ill_ins_p1 or r_prv_ins_p1 or r_call_en_p1)
begin
// EA #1 mask
case (w_data_p1[11:8])
4'b0000 : w_ea1m_p1 = 16'b000_00000_00000000; // $0000
4'b0001 : w_ea1m_p1 = 16'b000_00011_01110101; // $01F5
4'b0010 : w_ea1m_p1 = 16'b000_00011_01111100; // $01FC
4'b0011 : w_ea1m_p1 = 16'b000_00011_01111101; // $01FD
4'b0100 : w_ea1m_p1 = 16'b000_00011_01111110; // $01FE
4'b0101 : w_ea1m_p1 = 16'b000_00011_01111111; // $01FF
4'b0110 : w_ea1m_p1 = 16'b000_01111_01001101; // $07CD
4'b0111 : w_ea1m_p1 = 16'b000_01111_01100100; // $07E4
4'b1000 : w_ea1m_p1 = 16'b000_01111_01100101; // $07E5
4'b1001 : w_ea1m_p1 = 16'b000_01111_01101100; // $07EC
4'b1010 : w_ea1m_p1 = 16'b000_01111_01111101; // $07FD
4'b1011 : w_ea1m_p1 = 16'b000_10011_01111101; // $09FD
4'b1100 : w_ea1m_p1 = 16'b000_11111_01111101; // $0FFD
4'b1101 : w_ea1m_p1 = 16'b000_11111_01111111; // $0FFF
default : w_ea1m_p1 = 16'b111_11111_01111111; // $7FFF
endcase
// Call address increment
w_incr_p1 = (w_data_p1[23:18] & {6{r_call_en_p1[0]}})
| (w_data_p1[17:12] & {6{r_call_en_p1[1]}});
// Call address
if (((w_ea1m_p1 & r_ea1b_p1) == 16'h0000) || (r_ill_ins_p1)) begin
// Illegal instruction
w_call_p1 <= `OP_ILLEGAL;
w_vld_ins_p1 <= 1'b0;
end else if (r_prv_ins_p1) begin
// Priviledge violation
w_call_p1 <= `OP_PRIVILEDGED;
w_vld_ins_p1 <= 1'b1;
end else begin
// Valid instruction
w_call_p1 <= w_data_p1[35:24] + { 6'b000000, w_incr_p1 };
w_vld_ins_p1 <= 1'b1;
end
end
// Latch the indexes and bitfields
always @(posedge rst or posedge clk)
begin
if (rst) begin
r_ea1_jmp_p1 <= 4'b0000;
r_ea2_jmp_p1 <= 4'b0000;
r_ill_ins_p1 <= 1'b0;
r_prv_ins_p1 <= 1'b0;
r_ext_ins_p1 <= 1'b0;
r_bit_ins_p1 <= 1'b0;
r_call_en_p1 <= 2'b00;
r_ea1b_p1 <= 16'b0000000_00000000;
//r_ext_ins_p2 <= 1'b0;
//r_bit_ins_p2 <= 1'b0;
r_vld_ins_p2 <= 1'b0;
//r_ea1_jmp_p2 <= 4'b0000;
//r_ea2_jmp_p2 <= 4'b0000;
r_call_p2 <= 12'h000;
end else begin
// Cycle #1
r_ea1_jmp_p1 <= w_ea1_jmp_p0;
r_ea2_jmp_p1 <= w_ea2_jmp_p0;
r_ill_ins_p1 <= w_ill_ins_p0;
r_prv_ins_p1 <= w_prv_ins_p0;
r_ext_ins_p1 <= w_ext_ins_p0;
r_bit_ins_p1 <= w_bit_ins_p0;
r_call_en_p1 <= { w_call2_ena_p0, w_call1_ena_p0 };
r_ea1b_p1 <= w_ea1b_p0;
// Cycle #2
//r_ext_ins_p2 <= r_ext_ins_p1;
//r_bit_ins_p2 <= r_bit_ins_p1;
r_vld_ins_p2 <= w_vld_ins_p1;
//r_ea1_jmp_p2 <= r_ea1_jmp_p1;
//r_ea2_jmp_p2 <= r_ea2_jmp_p1;
r_call_p2 <= w_call_p1;
end
end
assign vld_inst = r_vld_ins_p2;
assign ext_inst = r_ext_ins_p1;
assign bit_inst = r_bit_ins_p1;
assign dec_jmp = r_call_p2;
assign ea1_jmp = r_ea1_jmp_p1;
assign ea2_jmp = r_ea2_jmp_p1;
assign ea1_bit = r_ea1b_p1;
// Immediate values from instruction word
// For ADDQ, SUBQ and shift immediate
assign w_imm3_i[15:4] = 12'h000;
assign w_imm3_i[3] = (instr[11:9] == 3'b000) ? (w_g5_addsub_p0 | (w_gE_shreg_p0 & ~instr[5])) : 1'b0;
assign w_imm3_i[2:0] = (w_g5_addsub_p0 | (w_gE_shreg_p0 & ~instr[5])) ? instr[11:9] : 3'b000;
// For TRAP #x : xxx0 - xxxF -> 0080 - 00BC
assign w_imm4_i[15:8] = 8'h00;
assign w_imm4_i[7:0] = (w_g4_misc_p0) ? {2'b10, instr[3:0], 2'b00} : 8'h00;
// For MOVEQ and Bcc.B
assign w_imm8_i[15:8] = (w_grp_p0[6] | (w_grp_p0[7] & ~instr[8])) ? {8{instr[7]}} : 8'h00;
assign w_imm8_i[7:0] = (w_grp_p0[6] | (w_grp_p0[7] & ~instr[8])) ? instr[7:0] : 8'h00;
// Immediate values from extension word
// For BTST, BCHG, BCLR and BSET
assign w_imm5_e[15:5] = 11'b0;
assign w_imm5_e[4:0] = ext_wd[4:0];
// For d8(An,Rn) and d8(PC,Rn)
assign w_imm8_e[15:8] = {8{ext_wd[7]}};
assign w_imm8_e[7:0] = ext_wd[7:0];
// Latch the immediate values
always @(posedge rst or posedge clk)
begin
if (rst) begin
imm_val <= 16'h0000;
end else begin
if (ins_rdy) imm_val <= w_imm3_i | w_imm4_i | w_imm8_i;
if (ext_rdy) begin
if (w_g0_bitimm_p0)
imm_val <= w_imm5_e;
else
imm_val <= w_imm8_e;
end
if (imm_rdy) imm_val <= imm_wd;
end
end
// Jump flag from condition codes
always @(posedge rst or posedge clk)
begin
if (rst)
cc_jmp <= 1'b0;
else
case (instr[11:8])
4'b0000 : cc_jmp <= 1'b1; // T
4'b0001 : cc_jmp <= 1'b0; // F
4'b0010 : cc_jmp <= ~(ccr_in[0] | ccr_in[2]); // HI
4'b0011 : cc_jmp <= ccr_in[0] | ccr_in[2]; // LS
4'b0100 : cc_jmp <= ~ ccr_in[0]; // CC
4'b0101 : cc_jmp <= ccr_in[0]; // CS
4'b0110 : cc_jmp <= ~ ccr_in[2]; // NE
4'b0111 : cc_jmp <= ccr_in[2]; // EQ
4'b1000 : cc_jmp <= ~ ccr_in[1]; // VC
4'b1001 : cc_jmp <= ccr_in[1]; // VS
4'b1010 : cc_jmp <= ~ ccr_in[3]; // PL
4'b1011 : cc_jmp <= ccr_in[3]; // MI
4'b1100 : cc_jmp <= ~(ccr_in[1] ^ ccr_in[3]); // GE
4'b1101 : cc_jmp <= ccr_in[1] ^ ccr_in[3]; // LT
4'b1110 : cc_jmp <= ~((ccr_in[1] ^ ccr_in[3]) | ccr_in[2]); // GT
4'b1111 : cc_jmp <= (ccr_in[1] ^ ccr_in[3]) | ccr_in[2]; // LE
endcase
end
endmodule
module dpram_2048x4
(
// Clock
input clock,
// Port A : micro-instruction fetch
input rden_a,
input [10:0] address_a,
output [3:0] q_a,
// Port B : m68k registers read/write
input wren_b,
input [10:0] address_b,
input [3:0] data_b,
output [3:0] q_b
);
parameter RAM_INIT_FILE = "j68_ram.mif";
altsyncram altsyncram_component
(
.clock0(clock),
.wren_a(1'b0),
.wren_b(wren_b),
.address_a(address_a),
.address_b(address_b),
.data_a(4'b0000),
.data_b(data_b),
.q_a(q_a),
.q_b(q_b),
.aclr0(1'b0),
.aclr1(1'b0),
.addressstall_a(~rden_a),
.addressstall_b(1'b0),
.byteena_a(1'b1),
.byteena_b(1'b1),
.clock1(1'b1),
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
.eccstatus(),
.rden_a(1'b1),
.rden_b(1'b1)
);
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.byteena_reg_b = "CLOCK0",
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = RAM_INIT_FILE,
altsyncram_component.intended_device_family = "Stratix II",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.numwords_b = 2048,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "AUTO",
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
//altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_WITH_NBE_READ",
//altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_WITH_NBE_READ",
altsyncram_component.widthad_a = 11,
altsyncram_component.widthad_b = 11,
altsyncram_component.width_a = 4,
altsyncram_component.width_b = 4,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
module addsub_32
(
input add_sub,
input [31:0] dataa,
input [31:0] datab,
output cout,
output [31:0] result
);
lpm_add_sub lpm_add_sub_component
(
.add_sub(add_sub),
.dataa(dataa),
.datab(datab),
.cout(cout),
.result(result)
// synopsys translate_off
,
.aclr(),
.cin(),
.clken(),
.clock(),
.overflow()
// synopsys translate_on
);
defparam
lpm_add_sub_component.lpm_direction = "UNUSED",
lpm_add_sub_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_add_sub_component.lpm_representation = "UNSIGNED",
lpm_add_sub_component.lpm_type = "LPM_ADD_SUB",
lpm_add_sub_component.lpm_width = 32;
endmodule
module decode_rom
(
input clock,
input [7:0] address,
output [35:0] q
);
altsyncram altsyncram_component
(
.clock0 (clock),
.address_a (address),
.q_a (q),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({36{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "j68_dec.mif",
altsyncram_component.intended_device_family = "Stratix II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 36,
altsyncram_component.width_byteena_a = 1;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// //
// This file is placed into the Public Domain, for any use, without warranty. //
// 2012 by Iztok Jeras //
// //
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// //
// This testbench contains a bus source and a bus drain. The source creates //
// address and data bus values, while the drain is the final destination of //
// such pairs. All source and drain transfers are logged into memories, which //
// are used at the end of simulation to check for data transfer correctness. //
// Inside the RLT wrapper there is a multiplexer and a demultiplexer, they //
// bus transfers into a 8bit data stream and back. Both stream input and //
// output are exposed, they are connected together into a loopback. //
// //
// ----------- --------------------- //
// | bso_mem | | wrap | //
// ----------- | | //
// ----------- | | ----------- | //
// | bsi src | ------------> | -> | mux | -> | -> - sto //
// ----------- | ----------- | \ //
// | | | loopback //
// ----------- | ----------- | / //
// | bso drn | <------------ | <- | demux | <- | <- - sti //
// ----------- | | ----------- | //
// ----------- | | //
// | bso_mem | | | //
// ----------- --------------------- //
// //
// PROTOCOL: //
// //
// The 'vld' signal is driven by the source to indicate valid data is //
// available, 'rdy' is used by the drain to indicate is is ready to accept //
// valid data. A data transfer only happens if both 'vld' & 'rdy' are active. //
// //
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
// include RTL files
`include "t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv"
`include "t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv"
`include "t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv"
`include "t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv"
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
parameter SIZ = 10;
// system signals
//logic clk = 1'b1; // clock
logic rst = 1'b1; // reset
integer rst_cnt = 0;
// input bus
logic bsi_vld; // valid (chip select)
logic [31:0] bsi_adr; // address
logic [31:0] bsi_dat; // data
logic bsi_rdy; // ready (acknowledge)
logic bsi_trn; // data transfer
logic [31:0] bsi_mem [SIZ];
// output stream
logic sto_vld; // valid (chip select)
logic [7:0] sto_bus; // data bus
logic sto_rdy; // ready (acknowledge)
// input stream
logic sti_vld; // valid (chip select)
logic [7:0] sti_bus; // data bus
logic sti_rdy; // ready (acknowledge)
// output bus
logic bso_vld; // valid (chip select)
logic [31:0] bso_adr; // address
logic [31:0] bso_dat; // data
logic bso_rdy; // ready (acknowledge)
logic bso_trn; // data transfer
logic [31:0] bso_mem [SIZ];
integer bso_cnt = 0;
////////////////////////////////////////////////////////////////////////////////
// clock and reset
////////////////////////////////////////////////////////////////////////////////
// clock toggling
//always #5 clk = ~clk;
// reset is removed after a delay
always @ (posedge clk)
begin
rst_cnt <= rst_cnt + 1;
rst <= rst_cnt <= 3;
end
// reset is removed after a delay
always @ (posedge clk)
if (bso_cnt == SIZ) begin
if (bsi_mem === bso_mem) begin $write("*-* All Finished *-*\n"); $finish(); end
else begin $display ("FAILED"); $stop(); end
end
////////////////////////////////////////////////////////////////////////////////
// input data generator
////////////////////////////////////////////////////////////////////////////////
// input data transfer
assign bsi_trn = bsi_vld & bsi_rdy;
// valid (for SIZ transfers)
always @ (posedge clk, posedge rst)
if (rst) bsi_vld = 1'b0;
else bsi_vld = (bsi_adr < SIZ);
// address (increments every transfer)
always @ (posedge clk, posedge rst)
if (rst) bsi_adr <= 32'h00000000;
else if (bsi_trn) bsi_adr <= bsi_adr + 'd1;
// data (new random value generated after every transfer)
always @ (posedge clk, posedge rst)
if (rst) bsi_dat <= 32'h00000000;
else if (bsi_trn) bsi_dat <= $random();
// storing transferred data into memory for final check
always @ (posedge clk)
if (bsi_trn) bsi_mem [bsi_adr] <= bsi_dat;
////////////////////////////////////////////////////////////////////////////////
// RTL instance
////////////////////////////////////////////////////////////////////////////////
sv_bus_mux_demux_wrap wrap (
// system signals
.clk (clk),
.rst (rst),
// input bus
.bsi_vld (bsi_vld),
.bsi_adr (bsi_adr),
.bsi_dat (bsi_dat),
.bsi_rdy (bsi_rdy),
// output stream
.sto_vld (sto_vld),
.sto_bus (sto_bus),
.sto_rdy (sto_rdy),
// input stream
.sti_vld (sti_vld),
.sti_bus (sti_bus),
.sti_rdy (sti_rdy),
// output bus
.bso_vld (bso_vld),
.bso_adr (bso_adr),
.bso_dat (bso_dat),
.bso_rdy (bso_rdy)
);
// stream output from mux is looped back into stream input for demux
assign sti_vld = sto_vld;
assign sti_bus = sto_bus;
assign sto_rdy = sti_rdy;
////////////////////////////////////////////////////////////////////////////////
// output data monitor
////////////////////////////////////////////////////////////////////////////////
// input data transfer
assign bso_trn = bso_vld & bso_rdy;
// output transfer counter used to end the test
always @ (posedge clk, posedge rst)
if (rst) bso_cnt <= 0;
else if (bso_trn) bso_cnt <= bso_cnt + 1;
// storing transferred data into memory for final check
always @ (posedge clk)
if (bso_trn) bso_mem [bso_adr] <= bso_dat;
// every output transfer against expected value stored in memory
always @ (posedge clk)
if (bso_trn && (bsi_mem [bso_adr] !== bso_dat))
$display ("@%08h i:%08h o:%08h", bso_adr, bsi_mem [bso_adr], bso_dat);
// ready is active for SIZ transfers
always @ (posedge clk, posedge rst)
if (rst) bso_rdy = 1'b0;
else bso_rdy = 1'b1;
endmodule : sv_bus_mux_demux_tb
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: rx_mem_data_fsm
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Receive Memory Data State Machine module. This module takes the
// data from the width conversion fifo (data_trn_mem_fifo) and send it into the
// dma_ddr2_if block
// that passes the data off to the MIG memory controller to write to the DDR2
// memory.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// modified by Jiansong Zhang
// add TX descriptor handling here ---------------- done
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module rx_mem_data_fsm(
input wire clk,
input wire rst,
//interface to dma_ddr2_if block
output reg [127:0] ingress_data,
output reg [1:0] ingress_fifo_ctrl, //bit 1 = unused bit 0 = write_en
input wire [1:0] ingress_fifo_status, //bit 1 = full bit 0 = almostfull
output reg [2:0] ingress_xfer_size,
output reg [27:6] ingress_start_addr,
output reg ingress_data_req,
input wire ingress_data_ack,
//interface to xfer_trn_mem_fifo
input wire isDes_fifo, /// Jiansong: added for TX des
input wire [27:6] mem_dest_addr_fifo,
input wire [10:0] mem_dma_size_fifo,
input wire mem_dma_start,//start signal not used-monitor empty instead
input wire mem_trn_fifo_empty,
output reg mem_trn_fifo_rden,
//interface to data_trn_mem_fifo
input wire [127:0] data_fifo_data,
output reg data_fifo_cntrl,
input wire data_fifo_status,
///Jiansong: interface to dma control wrapper
output reg new_des_one, /// Jiansong: is one cycle ok?
output wire [31:0] SourceAddr_L,
output wire [31:0] SourceAddr_H,
output wire [31:0] DestAddr,
output wire [23:0] FrameSize,
output wire [7:0] FrameControl
);
reg [4:0] state;
reg [9:0] cnt;
reg [1:0] ingress_fifo_ctrl_pipe = 2'b00;
/// liuchang
reg [10:0] mem_dma_size_fifo_r;
reg [27:6] mem_dest_addr_fifo_r;
/// Jiansong
reg [127:0] TX_des_1;
reg [127:0] TX_des_2;
/// Jiansong: parse TX descriptor
assign SourceAddr_L[31:0] = TX_des_1[95:64];
assign SourceAddr_H[31:0] = TX_des_1[127:96];
assign DestAddr[31:0] = TX_des_2[31:0];
assign FrameSize[23:0] = TX_des_2[87:64];
assign FrameControl[7:0] = TX_des_2[95:88];
/// Jiansong: check own bit?
reg rst_reg;
always@(posedge clk) rst_reg <= rst;
// Jiansong: data fifo empty pipeline
reg data_fifo_status_r;
always@(posedge clk) data_fifo_status_r <= data_fifo_status;
localparam IDLE = 5'b00000;
localparam WREQ = 5'b00001;
localparam WDATA2 = 5'b00010;
localparam WDONE = 5'b00011;
localparam MREQ = 5'b00100;
localparam MREQ2 = 5'b00101;
localparam MREQ_WAIT = 5'b00110; /// liuchang
/// Jiansong:
localparam PARSE_TX_DES = 5'b01000;
localparam READ_TX_DES_1 = 5'b10000;
localparam READ_TX_DES_2 = 5'b11000;
//This state machine block waits for the xfer_trn_mem_fifo to go non-empty.
//It then performs the following steps:
// 1. read the transfer size and destination
// information out of the xfer_trn_mem_fifo
// 2. encode the transfer size info from DWORDS to the encoding used by
// dma_ddr2_if block
// 3. transfer the correct amount of data from the data_trn_mem_fifo to
// the dma_ddr2_if (ingress data fifo)
always @ (posedge clk)
begin
if(rst_reg)
begin
state <= IDLE;
ingress_xfer_size <= 3'b000;
ingress_start_addr <= 22'h000000;
ingress_data_req <= 1'b0;
data_fifo_cntrl <= 1'b0;
mem_trn_fifo_rden <= 1'b0;
cnt <= 10'h000;
new_des_one <= 1'b0;
TX_des_1 <= 128'h00000000_00000000_00000000_00000000;
TX_des_2 <= 128'h00000000_00000000_00000000_00000000;
mem_dma_size_fifo_r <= 11'h000; /// liuchang
mem_dest_addr_fifo_r[27:6] <= 22'h00_0000; /// liuchang
end
else
begin
case(state)
IDLE: begin
new_des_one <= 1'b0;
//wait for non-empty case and assert the read enable if so
if(~mem_trn_fifo_empty)begin
mem_trn_fifo_rden <= 1'b1;
ingress_data_req <= 1'b0;
state <= MREQ;
end else begin
state <= IDLE;
end
end
MREQ: begin //deassert the read enable
mem_trn_fifo_rden <= 1'b0;
// state <= MREQ2; /// liuchang
state <= MREQ_WAIT; /// liuchang
end
MREQ_WAIT: begin /// liuchang
mem_dma_size_fifo_r <= mem_dma_size_fifo;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo[27:6];
state <= MREQ2;
end
MREQ2:begin
if(isDes_fifo) begin /// Jiansong: parse TX des
// check whether TX descriptor data arrived in
// if (~data_fifo_status)begin
if (~data_fifo_status_r)begin
state <= PARSE_TX_DES;
data_fifo_cntrl <= 1'b1; /// read enable the 1st cycle
end else begin
state <= MREQ2;
data_fifo_cntrl <= 1'b0;
end
end else begin
state <= WREQ;
//encode the transfer size information for the dma_ddr2_if
//also load a counter with the number of 128-bit (16 byte)
//transfers it will require to fullfill the total data
/// liuchang
if(mem_dma_size_fifo_r[10]) begin
ingress_xfer_size <= 3'b110; // 4k byte
cnt <= 10'h100;
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b10000000000;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b1000000;
end else if(mem_dma_size_fifo_r[9]) begin // 2k
ingress_xfer_size <= 3'b101;
cnt <= 10'h080;
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b01000000000;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0100000;
end else if(mem_dma_size_fifo_r[8]) begin // 1k
ingress_xfer_size <= 3'b100;
cnt <= 10'h040;
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b00100000000;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0010000;
end else if(mem_dma_size_fifo_r[7]) begin // 512
ingress_xfer_size <= 3'b011;
cnt <= 10'h020;
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b00010000000;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0001000;
end else if(mem_dma_size_fifo_r[6]) begin // 256
ingress_xfer_size <= 3'b010;
cnt <= 10'h010;
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b00001000000;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0000100;
end else if(mem_dma_size_fifo_r[5]) begin // 128
ingress_xfer_size <= 3'b001;
cnt <= 10'h008;
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b00000100000;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0000010;
end else if(mem_dma_size_fifo_r[4]) begin // 64 byte
ingress_xfer_size <= 3'b000;
cnt <= 10'h004;
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b00000010000;
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0000001;
end
/// liuchang
// case(mem_dma_size_fifo)
// 11'b00000010000: begin //64 byte
// ingress_xfer_size <= 3'b000;
// //64 bytes / 16 byte/xfer = 4 xfers
// cnt <= 10'h004;
// end
// 11'b00000100000: begin //128
// ingress_xfer_size <= 3'b001;
// cnt <= 10'h008;
// end
// 11'b00001000000: begin //256
// ingress_xfer_size <= 3'b010;
// cnt <= 10'h010;
// end
// 11'b00010000000: begin //512
// ingress_xfer_size <= 3'b011;
// cnt <= 10'h020;
// end
// 11'b00100000000: begin //1k
// ingress_xfer_size <= 3'b100;
// cnt <= 10'h040;
// end
// 11'b01000000000: begin //2k
// ingress_xfer_size <= 3'b101;
// cnt <= 10'h080;
// end
// 11'b10000000000: begin //4k
// ingress_xfer_size <= 3'b110;
// cnt <= 10'h100;
// end
// endcase
ingress_start_addr[27:6] <= mem_dest_addr_fifo_r[27:6]; ///liuchang
// ingress_start_addr <= mem_dest_addr_fifo;
ingress_data_req <= 1'b1;//request access to ingress fifo
end
end
/// Jiansong: parse TX des
PARSE_TX_DES: begin
state <= READ_TX_DES_1;
data_fifo_cntrl <= 1'b1; /// read enable the 2nd cycle
end
READ_TX_DES_1: begin
state <= READ_TX_DES_2;
data_fifo_cntrl <= 1'b0;
/// read data, 1st cycle
TX_des_2[127:0] <= data_fifo_data[127:0];
new_des_one <= 1'b0;
end
READ_TX_DES_2: begin
state <= IDLE; /// Jiansong: possible timing problem here
/// read data, 2nd cycle
TX_des_2[127:0] <= data_fifo_data[127:0];
TX_des_1[127:0] <= TX_des_2[127:0];
new_des_one <= 1'b1;
end
WREQ: begin /// Jiansong: data should be already in data_trn_mem_fifo
if(ingress_data_ack)//wait for a grant from the dma_ddr2_if
begin
state <= WDATA2;
ingress_data_req <= 1'b0;
data_fifo_cntrl <= 1'b1;
end
else
begin
state <= WREQ;
end
end
WDATA2: begin
//keep data_fifo_cntrl asserted until cnt is 1 - then deassert
//and finish
if(cnt == 10'h001)begin
state <= WDONE;
data_fifo_cntrl <= 1'b0;
end else begin
cnt <= cnt - 1'b1;
data_fifo_cntrl <= 1'b1;
state <= WDATA2;
end
end
WDONE: begin
// state <= IDLE; /// liuchang
if(mem_dma_size_fifo_r[10:4] == 7'h00) /// liuchang
state <= IDLE;
else
state <= MREQ2;
end
default:begin
state <= IDLE;
ingress_xfer_size <= 3'b000;
ingress_start_addr <= 22'h000000;
ingress_data_req <= 1'b0;
data_fifo_cntrl <= 1'b0;
mem_trn_fifo_rden <= 1'b0;
cnt <= 10'h000;
mem_dma_size_fifo_r <= 11'h000; /// liuchang
mem_dest_addr_fifo_r[27:6] <= 22'h00_0000; /// liuchang
end
endcase
end
end
/// Jiansong: timing ok? all driven by the same clk
//data_fifo_cntrl is used as both a read enable to the data_trn_mem_fifo and
//a write enable to the ingress fifo (in dma_ddr2_if). The write enable
//needs to be pipelined by two clocks so that it is synched with the
//ingress_data (normally it would only need one pipeline register but since
//ingress_data is pipelined, it requires two.
always@(posedge clk)begin // Jiansong: add logic to prevent TX des write into DDR
ingress_fifo_ctrl_pipe[1:0] <= {1'b0,(data_fifo_cntrl&(~isDes_fifo))};//1st pipeline
ingress_fifo_ctrl[1:0] <= ingress_fifo_ctrl_pipe[1:0]; //2nd pipeline
ingress_data[127:0] <= data_fifo_data[127:0]; //pipelined data
end
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0);
input inclk0;
output c0;
wire [4:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_data;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (ram_data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_data;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (ram_data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_nios2_oci_debug (
// inputs:
clk,
dbrk_break,
debugreq,
hbreak_enabled,
jdo,
jrst_n,
ocireg_ers,
ocireg_mrs,
reset,
st_ready_test_idle,
take_action_ocimem_a,
take_action_ocireg,
xbrk_break,
// outputs:
debugack,
monitor_error,
monitor_go,
monitor_ready,
oci_hbreak_req,
resetlatch,
resetrequest
)
;
output debugack;
output monitor_error;
output monitor_go;
output monitor_ready;
output oci_hbreak_req;
output resetlatch;
output resetrequest;
input clk;
input dbrk_break;
input debugreq;
input hbreak_enabled;
input [ 37: 0] jdo;
input jrst_n;
input ocireg_ers;
input ocireg_mrs;
input reset;
input st_ready_test_idle;
input take_action_ocimem_a;
input take_action_ocireg;
input xbrk_break;
reg break_on_reset /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire debugack;
reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire oci_hbreak_req;
wire reset_sync;
reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire unxcomplemented_resetxx0;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (clk),
.din (reset),
.dout (reset_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
break_on_reset <= 1'b0;
resetrequest <= 1'b0;
jtag_break <= 1'b0;
end
else if (take_action_ocimem_a)
begin
resetrequest <= jdo[22];
jtag_break <= jdo[21] ? 1
: jdo[20] ? 0
: jtag_break;
break_on_reset <= jdo[19] ? 1
: jdo[18] ? 0
: break_on_reset;
resetlatch <= jdo[24] ? 0 : resetlatch;
end
else if (reset_sync)
begin
jtag_break <= break_on_reset;
resetlatch <= 1;
end
else if (debugreq & ~debugack & break_on_reset)
jtag_break <= 1'b1;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
monitor_ready <= 1'b0;
monitor_error <= 1'b0;
monitor_go <= 1'b0;
end
else
begin
if (take_action_ocimem_a && jdo[25])
monitor_ready <= 1'b0;
else if (take_action_ocireg && ocireg_mrs)
monitor_ready <= 1'b1;
if (take_action_ocimem_a && jdo[25])
monitor_error <= 1'b0;
else if (take_action_ocireg && ocireg_ers)
monitor_error <= 1'b1;
if (take_action_ocimem_a && jdo[23])
monitor_go <= 1'b1;
else if (st_ready_test_idle)
monitor_go <= 1'b0;
end
end
assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq;
assign debugack = ~hbreak_enabled;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input [ 7: 0] address;
input [ 3: 0] byteenable;
input clock;
input [ 31: 0] data;
input reset_req;
input wren;
wire clocken;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign clocken = ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clock),
.clocken0 (clocken),
.data_a (data),
.q_a (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 256,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 8;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_nios2_ocimem (
// inputs:
address,
byteenable,
clk,
debugaccess,
jdo,
jrst_n,
read,
reset_req,
take_action_ocimem_a,
take_action_ocimem_b,
take_no_action_ocimem_a,
write,
writedata,
// outputs:
MonDReg,
ociram_readdata,
waitrequest
)
;
output [ 31: 0] MonDReg;
output [ 31: 0] ociram_readdata;
output waitrequest;
input [ 8: 0] address;
input [ 3: 0] byteenable;
input clk;
input debugaccess;
input [ 37: 0] jdo;
input jrst_n;
input read;
input reset_req;
input take_action_ocimem_a;
input take_action_ocimem_b;
input take_no_action_ocimem_a;
input write;
input [ 31: 0] writedata;
reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 8: 0] MonARegAddrInc;
wire MonARegAddrIncAccessingRAM;
reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg avalon_ociram_readdata_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire avalon_ram_wr;
wire [ 31: 0] cfgrom_readdata;
reg jtag_ram_access /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_wr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 7: 0] ociram_addr;
wire [ 3: 0] ociram_byteenable;
wire [ 31: 0] ociram_readdata;
wire [ 31: 0] ociram_wr_data;
wire ociram_wr_en;
reg waitrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
jtag_rd <= 1'b0;
jtag_rd_d1 <= 1'b0;
jtag_ram_wr <= 1'b0;
jtag_ram_rd <= 1'b0;
jtag_ram_rd_d1 <= 1'b0;
jtag_ram_access <= 1'b0;
MonAReg <= 0;
MonDReg <= 0;
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
else
begin
if (take_no_action_ocimem_a)
begin
MonAReg[10 : 2] <= MonARegAddrInc;
jtag_rd <= 1'b1;
jtag_ram_rd <= MonARegAddrIncAccessingRAM;
jtag_ram_access <= MonARegAddrIncAccessingRAM;
end
else if (take_action_ocimem_a)
begin
MonAReg[10 : 2] <= { jdo[17],
jdo[33 : 26] };
jtag_rd <= 1'b1;
jtag_ram_rd <= ~jdo[17];
jtag_ram_access <= ~jdo[17];
end
else if (take_action_ocimem_b)
begin
MonAReg[10 : 2] <= MonARegAddrInc;
MonDReg <= jdo[34 : 3];
jtag_ram_wr <= MonARegAddrIncAccessingRAM;
jtag_ram_access <= MonARegAddrIncAccessingRAM;
end
else
begin
jtag_rd <= 0;
jtag_ram_wr <= 0;
jtag_ram_rd <= 0;
jtag_ram_access <= 0;
if (jtag_rd_d1)
MonDReg <= jtag_ram_rd_d1 ? ociram_readdata : cfgrom_readdata;
end
jtag_rd_d1 <= jtag_rd;
jtag_ram_rd_d1 <= jtag_ram_rd;
if (~waitrequest)
begin
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
else if (write)
waitrequest <= ~address[8] & jtag_ram_access;
else if (read)
begin
avalon_ociram_readdata_ready <= ~(~address[8] & jtag_ram_access);
waitrequest <= ~avalon_ociram_readdata_ready;
end
else
begin
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
end
end
assign MonARegAddrInc = MonAReg[10 : 2]+1;
assign MonARegAddrIncAccessingRAM = ~MonARegAddrInc[8];
assign avalon_ram_wr = write & ~address[8] & debugaccess;
assign ociram_addr = jtag_ram_access ? MonAReg[9 : 2] : address[7 : 0];
assign ociram_wr_data = jtag_ram_access ? MonDReg[31 : 0] : writedata;
assign ociram_byteenable = jtag_ram_access ? 4'b1111 : byteenable;
assign ociram_wr_en = jtag_ram_access ? jtag_ram_wr : avalon_ram_wr;
//DE0_Nano_SOPC_cpu_ociram_sp_ram, which is an nios_sp_ram
DE0_Nano_SOPC_cpu_ociram_sp_ram_module DE0_Nano_SOPC_cpu_ociram_sp_ram
(
.address (ociram_addr),
.byteenable (ociram_byteenable),
.clock (clk),
.data (ociram_wr_data),
.q (ociram_readdata),
.reset_req (reset_req),
.wren (ociram_wr_en)
);
//synthesis translate_off
`ifdef NO_PLI
defparam DE0_Nano_SOPC_cpu_ociram_sp_ram.lpm_file = "DE0_Nano_SOPC_cpu_ociram_default_contents.dat";
`else
defparam DE0_Nano_SOPC_cpu_ociram_sp_ram.lpm_file = "DE0_Nano_SOPC_cpu_ociram_default_contents.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam DE0_Nano_SOPC_cpu_ociram_sp_ram.lpm_file = "DE0_Nano_SOPC_cpu_ociram_default_contents.mif";
//synthesis read_comments_as_HDL off
assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h02000020 :
(MonAReg[4 : 2] == 3'd1)? 32'h00001b1b :
(MonAReg[4 : 2] == 3'd2)? 32'h00040000 :
(MonAReg[4 : 2] == 3'd3)? 32'h00000100 :
(MonAReg[4 : 2] == 3'd4)? 32'h20000000 :
(MonAReg[4 : 2] == 3'd5)? 32'h02000000 :
(MonAReg[4 : 2] == 3'd6)? 32'h00000000 :
32'h00000000;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
)
;
output [ 31: 0] oci_ienable;
output [ 31: 0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [ 8: 0] address;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [ 31: 0] writedata;
reg [ 31: 0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [ 31: 0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_single_step_mode <= 1'b0;
else if (take_action_ocireg)
oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_ienable <= 32'b00000000000000000000000011111111;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000000011111111);
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_nios2_oci_break (
// inputs:
clk,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
jdo,
jrst_n,
reset_n,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
xbrk_goto0,
xbrk_goto1,
// outputs:
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
trigbrktype,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3
)
;
output [ 31: 0] break_readreg;
output dbrk_hit0_latch;
output dbrk_hit1_latch;
output dbrk_hit2_latch;
output dbrk_hit3_latch;
output trigbrktype;
output trigger_state_0;
output trigger_state_1;
output [ 7: 0] xbrk_ctrl0;
output [ 7: 0] xbrk_ctrl1;
output [ 7: 0] xbrk_ctrl2;
output [ 7: 0] xbrk_ctrl3;
input clk;
input dbrk_break;
input dbrk_goto0;
input dbrk_goto1;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_break_a;
input take_action_break_b;
input take_action_break_c;
input take_no_action_break_a;
input take_no_action_break_b;
input take_no_action_break_c;
input xbrk_goto0;
input xbrk_goto1;
wire [ 3: 0] break_a_wpr;
wire [ 1: 0] break_a_wpr_high_bits;
wire [ 1: 0] break_a_wpr_low_bits;
wire [ 1: 0] break_b_rr;
wire [ 1: 0] break_c_rr;
reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire dbrk0_high_value;
wire dbrk0_low_value;
wire dbrk1_high_value;
wire dbrk1_low_value;
wire dbrk2_high_value;
wire dbrk2_low_value;
wire dbrk3_high_value;
wire dbrk3_low_value;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire take_action_any_break;
reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg trigger_state;
wire trigger_state_0;
wire trigger_state_1;
wire [ 31: 0] xbrk0_value;
wire [ 31: 0] xbrk1_value;
wire [ 31: 0] xbrk2_value;
wire [ 31: 0] xbrk3_value;
reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
assign break_a_wpr = jdo[35 : 32];
assign break_a_wpr_high_bits = break_a_wpr[3 : 2];
assign break_a_wpr_low_bits = break_a_wpr[1 : 0];
assign break_b_rr = jdo[33 : 32];
assign break_c_rr = jdo[33 : 32];
assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
xbrk_ctrl0 <= 0;
xbrk_ctrl1 <= 0;
xbrk_ctrl2 <= 0;
xbrk_ctrl3 <= 0;
trigbrktype <= 0;
end
else
begin
if (take_action_any_break)
trigbrktype <= 0;
else if (dbrk_break)
trigbrktype <= 1;
if (take_action_break_b)
begin
if ((break_b_rr == 2'b00) && (0 >= 1))
begin
xbrk_ctrl0[0] <= jdo[27];
xbrk_ctrl0[1] <= jdo[28];
xbrk_ctrl0[2] <= jdo[29];
xbrk_ctrl0[3] <= jdo[30];
xbrk_ctrl0[4] <= jdo[21];
xbrk_ctrl0[5] <= jdo[20];
xbrk_ctrl0[6] <= jdo[19];
xbrk_ctrl0[7] <= jdo[18];
end
if ((break_b_rr == 2'b01) && (0 >= 2))
begin
xbrk_ctrl1[0] <= jdo[27];
xbrk_ctrl1[1] <= jdo[28];
xbrk_ctrl1[2] <= jdo[29];
xbrk_ctrl1[3] <= jdo[30];
xbrk_ctrl1[4] <= jdo[21];
xbrk_ctrl1[5] <= jdo[20];
xbrk_ctrl1[6] <= jdo[19];
xbrk_ctrl1[7] <= jdo[18];
end
if ((break_b_rr == 2'b10) && (0 >= 3))
begin
xbrk_ctrl2[0] <= jdo[27];
xbrk_ctrl2[1] <= jdo[28];
xbrk_ctrl2[2] <= jdo[29];
xbrk_ctrl2[3] <= jdo[30];
xbrk_ctrl2[4] <= jdo[21];
xbrk_ctrl2[5] <= jdo[20];
xbrk_ctrl2[6] <= jdo[19];
xbrk_ctrl2[7] <= jdo[18];
end
if ((break_b_rr == 2'b11) && (0 >= 4))
begin
xbrk_ctrl3[0] <= jdo[27];
xbrk_ctrl3[1] <= jdo[28];
xbrk_ctrl3[2] <= jdo[29];
xbrk_ctrl3[3] <= jdo[30];
xbrk_ctrl3[4] <= jdo[21];
xbrk_ctrl3[5] <= jdo[20];
xbrk_ctrl3[6] <= jdo[19];
xbrk_ctrl3[7] <= jdo[18];
end
end
end
end
assign dbrk_hit0_latch = 1'b0;
assign dbrk0_low_value = 0;
assign dbrk0_high_value = 0;
assign dbrk_hit1_latch = 1'b0;
assign dbrk1_low_value = 0;
assign dbrk1_high_value = 0;
assign dbrk_hit2_latch = 1'b0;
assign dbrk2_low_value = 0;
assign dbrk2_high_value = 0;
assign dbrk_hit3_latch = 1'b0;
assign dbrk3_low_value = 0;
assign dbrk3_high_value = 0;
assign xbrk0_value = 32'b0;
assign xbrk1_value = 32'b0;
assign xbrk2_value = 32'b0;
assign xbrk3_value = 32'b0;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
break_readreg <= 32'b0;
else if (take_action_any_break)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_a)
case (break_a_wpr_high_bits)
2'd0: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= xbrk0_value;
end // 2'd0
2'd1: begin
break_readreg <= xbrk1_value;
end // 2'd1
2'd2: begin
break_readreg <= xbrk2_value;
end // 2'd2
2'd3: begin
break_readreg <= xbrk3_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd0
2'd1: begin
break_readreg <= 32'b0;
end // 2'd1
2'd2: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_low_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_low_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_low_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_low_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd2
2'd3: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_high_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_high_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_high_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_high_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd3
endcase // break_a_wpr_high_bits
else if (take_no_action_break_b)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_c)
break_readreg <= jdo[31 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trigger_state <= 0;
else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0))
trigger_state <= 0;
else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1))
trigger_state <= -1;
end
assign trigger_state_0 = ~trigger_state;
assign trigger_state_1 = trigger_state;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_nios2_oci_xbrk (
// inputs:
D_valid,
E_valid,
F_pc,
clk,
reset_n,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3,
// outputs:
xbrk_break,
xbrk_goto0,
xbrk_goto1,
xbrk_traceoff,
xbrk_traceon,
xbrk_trigout
)
;
output xbrk_break;
output xbrk_goto0;
output xbrk_goto1;
output xbrk_traceoff;
output xbrk_traceon;
output xbrk_trigout;
input D_valid;
input E_valid;
input [ 24: 0] F_pc;
input clk;
input reset_n;
input trigger_state_0;
input trigger_state_1;
input [ 7: 0] xbrk_ctrl0;
input [ 7: 0] xbrk_ctrl1;
input [ 7: 0] xbrk_ctrl2;
input [ 7: 0] xbrk_ctrl3;
wire D_cpu_addr_en;
wire E_cpu_addr_en;
reg E_xbrk_goto0;
reg E_xbrk_goto1;
reg E_xbrk_traceoff;
reg E_xbrk_traceon;
reg E_xbrk_trigout;
wire [ 26: 0] cpu_i_address;
wire xbrk0_armed;
wire xbrk0_break_hit;
wire xbrk0_goto0_hit;
wire xbrk0_goto1_hit;
wire xbrk0_toff_hit;
wire xbrk0_ton_hit;
wire xbrk0_tout_hit;
wire xbrk1_armed;
wire xbrk1_break_hit;
wire xbrk1_goto0_hit;
wire xbrk1_goto1_hit;
wire xbrk1_toff_hit;
wire xbrk1_ton_hit;
wire xbrk1_tout_hit;
wire xbrk2_armed;
wire xbrk2_break_hit;
wire xbrk2_goto0_hit;
wire xbrk2_goto1_hit;
wire xbrk2_toff_hit;
wire xbrk2_ton_hit;
wire xbrk2_tout_hit;
wire xbrk3_armed;
wire xbrk3_break_hit;
wire xbrk3_goto0_hit;
wire xbrk3_goto1_hit;
wire xbrk3_toff_hit;
wire xbrk3_ton_hit;
wire xbrk3_tout_hit;
reg xbrk_break;
wire xbrk_break_hit;
wire xbrk_goto0;
wire xbrk_goto0_hit;
wire xbrk_goto1;
wire xbrk_goto1_hit;
wire xbrk_toff_hit;
wire xbrk_ton_hit;
wire xbrk_tout_hit;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
assign cpu_i_address = {F_pc, 2'b00};
assign D_cpu_addr_en = D_valid;
assign E_cpu_addr_en = E_valid;
assign xbrk0_break_hit = 0;
assign xbrk0_ton_hit = 0;
assign xbrk0_toff_hit = 0;
assign xbrk0_tout_hit = 0;
assign xbrk0_goto0_hit = 0;
assign xbrk0_goto1_hit = 0;
assign xbrk1_break_hit = 0;
assign xbrk1_ton_hit = 0;
assign xbrk1_toff_hit = 0;
assign xbrk1_tout_hit = 0;
assign xbrk1_goto0_hit = 0;
assign xbrk1_goto1_hit = 0;
assign xbrk2_break_hit = 0;
assign xbrk2_ton_hit = 0;
assign xbrk2_toff_hit = 0;
assign xbrk2_tout_hit = 0;
assign xbrk2_goto0_hit = 0;
assign xbrk2_goto1_hit = 0;
assign xbrk3_break_hit = 0;
assign xbrk3_ton_hit = 0;
assign xbrk3_toff_hit = 0;
assign xbrk3_tout_hit = 0;
assign xbrk3_goto0_hit = 0;
assign xbrk3_goto1_hit = 0;
assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit);
assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit);
assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit);
assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit);
assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit);
assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
xbrk_break <= 0;
else if (E_cpu_addr_en)
xbrk_break <= xbrk_break_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceon <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceon <= xbrk_ton_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceoff <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceoff <= xbrk_toff_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_trigout <= 0;
else if (E_cpu_addr_en)
E_xbrk_trigout <= xbrk_tout_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto0 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto0 <= xbrk_goto0_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto1 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto1 <= xbrk_goto1_hit;
end
assign xbrk_traceon = 1'b0;
assign xbrk_traceoff = 1'b0;
assign xbrk_trigout = 1'b0;
assign xbrk_goto0 = 1'b0;
assign xbrk_goto1 = 1'b0;
assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) ||
(xbrk_ctrl0[5] & trigger_state_1);
assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) ||
(xbrk_ctrl1[5] & trigger_state_1);
assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) ||
(xbrk_ctrl2[5] & trigger_state_1);
assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) ||
(xbrk_ctrl3[5] & trigger_state_1);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_nios2_oci_dbrk (
// inputs:
E_st_data,
av_ld_data_aligned_filtered,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugack,
reset_n,
// outputs:
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dbrk_trigout
)
;
output [ 26: 0] cpu_d_address;
output cpu_d_read;
output [ 31: 0] cpu_d_readdata;
output cpu_d_wait;
output cpu_d_write;
output [ 31: 0] cpu_d_writedata;
output dbrk_break;
output dbrk_goto0;
output dbrk_goto1;
output dbrk_traceme;
output dbrk_traceoff;
output dbrk_traceon;
output dbrk_trigout;
input [ 31: 0] E_st_data;
input [ 31: 0] av_ld_data_aligned_filtered;
input clk;
input [ 26: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugack;
input reset_n;
wire [ 26: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk0_armed;
wire dbrk0_break_pulse;
wire dbrk0_goto0;
wire dbrk0_goto1;
wire dbrk0_traceme;
wire dbrk0_traceoff;
wire dbrk0_traceon;
wire dbrk0_trigout;
wire dbrk1_armed;
wire dbrk1_break_pulse;
wire dbrk1_goto0;
wire dbrk1_goto1;
wire dbrk1_traceme;
wire dbrk1_traceoff;
wire dbrk1_traceon;
wire dbrk1_trigout;
wire dbrk2_armed;
wire dbrk2_break_pulse;
wire dbrk2_goto0;
wire dbrk2_goto1;
wire dbrk2_traceme;
wire dbrk2_traceoff;
wire dbrk2_traceon;
wire dbrk2_trigout;
wire dbrk3_armed;
wire dbrk3_break_pulse;
wire dbrk3_goto0;
wire dbrk3_goto1;
wire dbrk3_traceme;
wire dbrk3_traceoff;
wire dbrk3_traceon;
wire dbrk3_trigout;
reg dbrk_break;
reg dbrk_break_pulse;
wire [ 31: 0] dbrk_data;
reg dbrk_goto0;
reg dbrk_goto1;
reg dbrk_traceme;
reg dbrk_traceoff;
reg dbrk_traceon;
reg dbrk_trigout;
assign cpu_d_address = d_address;
assign cpu_d_readdata = av_ld_data_aligned_filtered;
assign cpu_d_read = d_read;
assign cpu_d_writedata = E_st_data;
assign cpu_d_write = d_write;
assign cpu_d_wait = d_waitrequest;
assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbrk_break <= 0;
else
dbrk_break <= dbrk_break ? ~debugack
: dbrk_break_pulse;
end
assign dbrk0_armed = 1'b0;
assign dbrk0_trigout = 1'b0;
assign dbrk0_break_pulse = 1'b0;
assign dbrk0_traceoff = 1'b0;
assign dbrk0_traceon = 1'b0;
assign dbrk0_traceme = 1'b0;
assign dbrk0_goto0 = 1'b0;
assign dbrk0_goto1 = 1'b0;
assign dbrk1_armed = 1'b0;
assign dbrk1_trigout = 1'b0;
assign dbrk1_break_pulse = 1'b0;
assign dbrk1_traceoff = 1'b0;
assign dbrk1_traceon = 1'b0;
assign dbrk1_traceme = 1'b0;
assign dbrk1_goto0 = 1'b0;
assign dbrk1_goto1 = 1'b0;
assign dbrk2_armed = 1'b0;
assign dbrk2_trigout = 1'b0;
assign dbrk2_break_pulse = 1'b0;
assign dbrk2_traceoff = 1'b0;
assign dbrk2_traceon = 1'b0;
assign dbrk2_traceme = 1'b0;
assign dbrk2_goto0 = 1'b0;
assign dbrk2_goto1 = 1'b0;
assign dbrk3_armed = 1'b0;
assign dbrk3_trigout = 1'b0;
assign dbrk3_break_pulse = 1'b0;
assign dbrk3_traceoff = 1'b0;
assign dbrk3_traceon = 1'b0;
assign dbrk3_traceme = 1'b0;
assign dbrk3_goto0 = 1'b0;
assign dbrk3_goto1 = 1'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
dbrk_trigout <= 0;
dbrk_break_pulse <= 0;
dbrk_traceoff <= 0;
dbrk_traceon <= 0;
dbrk_traceme <= 0;
dbrk_goto0 <= 0;
dbrk_goto1 <= 0;
end
else
begin
dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout;
dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse;
dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff;
dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon;
dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme;
dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0;
dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_nios2_oci_itrace (
// inputs:
clk,
dbrk_traceoff,
dbrk_traceon,
jdo,
jrst_n,
take_action_tracectrl,
trc_enb,
xbrk_traceoff,
xbrk_traceon,
xbrk_wrap_traceoff,
// outputs:
dct_buffer,
dct_count,
itm,
trc_ctrl,
trc_on
)
;
output [ 29: 0] dct_buffer;
output [ 3: 0] dct_count;
output [ 35: 0] itm;
output [ 15: 0] trc_ctrl;
output trc_on;
input clk;
input dbrk_traceoff;
input dbrk_traceon;
input [ 15: 0] jdo;
input jrst_n;
input take_action_tracectrl;
input trc_enb;
input xbrk_traceoff;
input xbrk_traceon;
input xbrk_wrap_traceoff;
wire advanced_exc_occured;
wire curr_pid;
reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] dct_code;
reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dct_is_taken;
wire [ 31: 0] eic_addr;
wire [ 31: 0] exc_addr;
wire instr_retired;
wire is_cond_dct;
wire is_dct;
wire is_exception_no_break;
wire is_external_interrupt;
wire is_fast_tlb_miss_exception;
wire is_idct;
reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire not_in_debug_mode;
reg pending_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exc /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 31: 0] pending_exc_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 31: 0] pending_exc_handler /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exc_record_handler /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid_valid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_dct_outcome_in_sync;
wire record_itrace;
wire [ 31: 0] retired_pcb;
reg snapped_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] sync_code;
wire [ 6: 0] sync_interval;
reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 6: 0] sync_timer_next;
wire sync_timer_reached_zero;
reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire [ 15: 0] trc_ctrl;
reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire trc_on;
assign is_cond_dct = 1'b0;
assign is_dct = 1'b0;
assign dct_is_taken = 1'b0;
assign is_idct = 1'b0;
assign retired_pcb = 32'b0;
assign not_in_debug_mode = 1'b0;
assign instr_retired = 1'b0;
assign advanced_exc_occured = 1'b0;
assign is_exception_no_break = 1'b0;
assign is_external_interrupt = 1'b0;
assign is_fast_tlb_miss_exception = 1'b0;
assign curr_pid = 1'b0;
assign exc_addr = 32'b0;
assign eic_addr = 32'b0;
assign sync_code = trc_ctrl[3 : 2];
assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 };
assign sync_timer_reached_zero = sync_timer == 0;
assign record_dct_outcome_in_sync = dct_is_taken & sync_timer_reached_zero;
assign sync_timer_next = sync_timer_reached_zero ? sync_timer : (sync_timer - 1);
assign record_itrace = trc_on & trc_ctrl[4];
assign dct_code = {is_cond_dct, dct_is_taken};
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
trc_clear <= 0;
else
trc_clear <= ~trc_enb &
take_action_tracectrl & jdo[4];
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exc <= 0;
pending_exc_addr <= 0;
pending_exc_handler <= 0;
pending_exc_record_handler <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else if (trc_clear || (!0 && !0))
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exc <= 0;
pending_exc_addr <= 0;
pending_exc_handler <= 0;
pending_exc_record_handler <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else
begin
if (!prev_pid_valid)
begin
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if ((curr_pid != prev_pid) & prev_pid_valid & !snapped_pid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if (instr_retired | advanced_exc_occured)
begin
if (~record_itrace)
pending_frametype <= 4'b1010;
else if (is_exception_no_break)
begin
pending_exc <= 1;
pending_exc_addr <= exc_addr;
pending_exc_record_handler <= 0;
if (is_external_interrupt)
pending_exc_handler <= eic_addr;
else if (is_fast_tlb_miss_exception)
pending_exc_handler <= 32'h0;
else
pending_exc_handler <= 32'h2000020;
pending_frametype <= 4'b0000;
end
else if (is_idct)
pending_frametype <= 4'b1001;
else if (record_dct_outcome_in_sync)
pending_frametype <= 4'b1000;
else if (!is_dct & snapped_pid)
begin
pending_frametype <= 4'b0011;
pending_curr_pid <= snapped_curr_pid;
pending_prev_pid <= snapped_prev_pid;
snapped_pid <= 0;
end
else
pending_frametype <= 4'b0000;
if ((dct_count != 0) &
(~record_itrace |
is_exception_no_break |
is_idct |
record_dct_outcome_in_sync |
(!is_dct & snapped_pid)))
begin
itm <= {4'b0001, dct_buffer, 2'b00};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
begin
if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~advanced_exc_occured)
begin
dct_buffer <= {dct_code, dct_buffer[29 : 2]};
dct_count <= dct_count + 1;
end
if (record_itrace & (
(pending_frametype == 4'b1000) |
(pending_frametype == 4'b1010) |
(pending_frametype == 4'b1001)))
begin
itm <= {pending_frametype, retired_pcb};
sync_timer <= sync_interval;
if (0 &
((pending_frametype == 4'b1000) | (pending_frametype == 4'b1010)) &
!snapped_pid & prev_pid_valid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
end
end
else if (record_itrace &
0 & (pending_frametype == 4'b0011))
itm <= {4'b0011, 2'b00, pending_prev_pid, 2'b00, pending_curr_pid};
else if (record_itrace & is_dct)
begin
if (dct_count == 4'd15)
begin
itm <= {4'b0001, dct_code, dct_buffer};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
itm <= 4'b0000;
end
else
itm <= {4'b0000, 32'b0};
end
end
else if (record_itrace & pending_exc)
begin
if (pending_exc_record_handler)
begin
itm <= {4'b0010, pending_exc_handler[31 : 1], 1'b1};
pending_exc <= 1'b0;
pending_exc_record_handler <= 1'b0;
end
else
begin
itm <= {4'b0010, pending_exc_addr[31 : 1], 1'b0};
pending_exc_record_handler <= 1'b1;
end
end
else
itm <= {4'b0000, 32'b0};
end
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_ctrl_reg[0] <= 1'b0;
trc_ctrl_reg[1] <= 1'b0;
trc_ctrl_reg[3 : 2] <= 2'b00;
trc_ctrl_reg[4] <= 1'b0;
trc_ctrl_reg[7 : 5] <= 3'b000;
trc_ctrl_reg[8] <= 0;
trc_ctrl_reg[9] <= 1'b0;
trc_ctrl_reg[10] <= 1'b0;
end
else if (take_action_tracectrl)
begin
trc_ctrl_reg[0] <= jdo[5];
trc_ctrl_reg[1] <= jdo[6];
trc_ctrl_reg[3 : 2] <= jdo[8 : 7];
trc_ctrl_reg[4] <= jdo[9];
trc_ctrl_reg[9] <= jdo[14];
trc_ctrl_reg[10] <= jdo[2];
if (0)
trc_ctrl_reg[7 : 5] <= jdo[12 : 10];
if (0 & 0)
trc_ctrl_reg[8] <= jdo[13];
end
else if (xbrk_wrap_traceoff)
begin
trc_ctrl_reg[1] <= 0;
trc_ctrl_reg[0] <= 0;
end
else if (dbrk_traceoff | xbrk_traceoff)
trc_ctrl_reg[1] <= 0;
else if (trc_ctrl_reg[0] &
(dbrk_traceon | xbrk_traceon))
trc_ctrl_reg[1] <= 1;
end
assign trc_ctrl = (0 || 0) ? {6'b000000, trc_ctrl_reg} : 0;
assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
)
;
output [ 3: 0] td_mode;
input [ 8: 0] ctrl;
wire [ 2: 0] ctrl_bits_for_mux;
reg [ 3: 0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux)
begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
)
;
output [ 35: 0] atm;
output [ 35: 0] dtm;
input clk;
input [ 26: 0] cpu_d_address;
input cpu_d_read;
input [ 31: 0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [ 31: 0] cpu_d_writedata;
input jrst_n;
input [ 15: 0] trc_ctrl;
reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 31: 0] cpu_d_address_0_padded;
wire [ 31: 0] cpu_d_readdata_0_padded;
wire [ 31: 0] cpu_d_writedata_0_padded;
reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3: 0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//DE0_Nano_SOPC_cpu_nios2_oci_trc_ctrl_td_mode, which is an e_instance
DE0_Nano_SOPC_cpu_nios2_oci_td_mode DE0_Nano_SOPC_cpu_nios2_oci_trc_ctrl_td_mode
(
.ctrl (trc_ctrl[8 : 0]),
.td_mode (td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
atm <= 0;
dtm <= 0;
end
else if (0)
begin
if (cpu_d_write & ~cpu_d_wait & record_store_addr)
atm <= {4'b0101, cpu_d_address_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_addr)
atm <= {4'b0100, cpu_d_address_0_padded};
else
atm <= {4'b0000, cpu_d_address_0_padded};
if (cpu_d_write & ~cpu_d_wait & record_store_data)
dtm <= {4'b0111, cpu_d_writedata_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_data)
dtm <= {4'b0110, cpu_d_readdata_0_padded};
else
dtm <= {4'b0000, cpu_d_readdata_0_padded};
end
else
begin
atm <= 0;
dtm <= 0;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
)
;
output [ 1: 0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [ 1: 0] compute_input_tm_cnt;
wire [ 2: 0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux)
begin
case (switch_for_mux)
3'b000: begin
compute_input_tm_cnt = 0;
end // 3'b000
3'b001: begin
compute_input_tm_cnt = 1;
end // 3'b001
3'b010: begin
compute_input_tm_cnt = 1;
end // 3'b010
3'b011: begin
compute_input_tm_cnt = 2;
end // 3'b011
3'b100: begin
compute_input_tm_cnt = 1;
end // 3'b100
3'b101: begin
compute_input_tm_cnt = 2;
end // 3'b101
3'b110: begin
compute_input_tm_cnt = 2;
end // 3'b110
3'b111: begin
compute_input_tm_cnt = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
)
;
output [ 3: 0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [ 1: 0] input_tm_cnt;
reg [ 3: 0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or input_tm_cnt)
begin
if (ge3_free & (input_tm_cnt == 3))
fifo_wrptr_inc = 3;
else if (ge2_free & (input_tm_cnt >= 2))
fifo_wrptr_inc = 2;
else if (input_tm_cnt >= 1)
fifo_wrptr_inc = 1;
else
fifo_wrptr_inc = 0;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
)
;
output [ 4: 0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [ 1: 0] input_tm_cnt;
reg [ 4: 0] fifo_cnt_inc;
always @(empty or ge2_free or ge3_free or input_tm_cnt)
begin
if (empty)
fifo_cnt_inc = input_tm_cnt[1 : 0];
else if (ge3_free & (input_tm_cnt == 3))
fifo_cnt_inc = 2;
else if (ge2_free & (input_tm_cnt >= 2))
fifo_cnt_inc = 1;
else if (input_tm_cnt >= 1)
fifo_cnt_inc = 0;
else
fifo_cnt_inc = {5{1'b1}};
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_nios2_oci_fifo (
// inputs:
atm,
clk,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dct_buffer,
dct_count,
dtm,
itm,
jrst_n,
reset_n,
test_ending,
test_has_ended,
trc_on,
// outputs:
tw
)
;
output [ 35: 0] tw;
input [ 35: 0] atm;
input clk;
input dbrk_traceme;
input dbrk_traceoff;
input dbrk_traceon;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input [ 35: 0] dtm;
input [ 35: 0] itm;
input jrst_n;
input reset_n;
input test_ending;
input test_has_ended;
input trc_on;
wire atm_valid;
wire [ 1: 0] compute_input_tm_cnt;
wire dtm_valid;
wire empty;
reg [ 35: 0] fifo_0;
wire fifo_0_enable;
wire [ 35: 0] fifo_0_mux;
reg [ 35: 0] fifo_1;
reg [ 35: 0] fifo_10;
wire fifo_10_enable;
wire [ 35: 0] fifo_10_mux;
reg [ 35: 0] fifo_11;
wire fifo_11_enable;
wire [ 35: 0] fifo_11_mux;
reg [ 35: 0] fifo_12;
wire fifo_12_enable;
wire [ 35: 0] fifo_12_mux;
reg [ 35: 0] fifo_13;
wire fifo_13_enable;
wire [ 35: 0] fifo_13_mux;
reg [ 35: 0] fifo_14;
wire fifo_14_enable;
wire [ 35: 0] fifo_14_mux;
reg [ 35: 0] fifo_15;
wire fifo_15_enable;
wire [ 35: 0] fifo_15_mux;
wire fifo_1_enable;
wire [ 35: 0] fifo_1_mux;
reg [ 35: 0] fifo_2;
wire fifo_2_enable;
wire [ 35: 0] fifo_2_mux;
reg [ 35: 0] fifo_3;
wire fifo_3_enable;
wire [ 35: 0] fifo_3_mux;
reg [ 35: 0] fifo_4;
wire fifo_4_enable;
wire [ 35: 0] fifo_4_mux;
reg [ 35: 0] fifo_5;
wire fifo_5_enable;
wire [ 35: 0] fifo_5_mux;
reg [ 35: 0] fifo_6;
wire fifo_6_enable;
wire [ 35: 0] fifo_6_mux;
reg [ 35: 0] fifo_7;
wire fifo_7_enable;
wire [ 35: 0] fifo_7_mux;
reg [ 35: 0] fifo_8;
wire fifo_8_enable;
wire [ 35: 0] fifo_8_mux;
reg [ 35: 0] fifo_9;
wire fifo_9_enable;
wire [ 35: 0] fifo_9_mux;
reg [ 4: 0] fifo_cnt /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 4: 0] fifo_cnt_inc;
wire [ 35: 0] fifo_head;
reg [ 3: 0] fifo_rdptr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] fifo_read_mux;
reg [ 3: 0] fifo_wrptr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 3: 0] fifo_wrptr_inc;
wire [ 3: 0] fifo_wrptr_plus1;
wire [ 3: 0] fifo_wrptr_plus2;
wire ge2_free;
wire ge3_free;
wire input_ge1;
wire input_ge2;
wire input_ge3;
wire [ 1: 0] input_tm_cnt;
wire itm_valid;
reg overflow_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] overflow_pending_atm;
wire [ 35: 0] overflow_pending_dtm;
wire trc_this;
wire [ 35: 0] tw;
assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme;
assign itm_valid = |itm[35 : 32];
assign atm_valid = |atm[35 : 32] & trc_this;
assign dtm_valid = |dtm[35 : 32] & trc_this;
assign ge2_free = ~fifo_cnt[4];
assign ge3_free = ge2_free & ~&fifo_cnt[3 : 0];
assign empty = ~|fifo_cnt;
assign fifo_wrptr_plus1 = fifo_wrptr + 1;
assign fifo_wrptr_plus2 = fifo_wrptr + 2;
DE0_Nano_SOPC_cpu_nios2_oci_compute_input_tm_cnt the_DE0_Nano_SOPC_cpu_nios2_oci_compute_input_tm_cnt
(
.atm_valid (atm_valid),
.compute_input_tm_cnt (compute_input_tm_cnt),
.dtm_valid (dtm_valid),
.itm_valid (itm_valid)
);
assign input_tm_cnt = compute_input_tm_cnt;
DE0_Nano_SOPC_cpu_nios2_oci_fifo_wrptr_inc the_DE0_Nano_SOPC_cpu_nios2_oci_fifo_wrptr_inc
(
.fifo_wrptr_inc (fifo_wrptr_inc),
.ge2_free (ge2_free),
.ge3_free (ge3_free),
.input_tm_cnt (input_tm_cnt)
);
DE0_Nano_SOPC_cpu_nios2_oci_fifo_cnt_inc the_DE0_Nano_SOPC_cpu_nios2_oci_fifo_cnt_inc
(
.empty (empty),
.fifo_cnt_inc (fifo_cnt_inc),
.ge2_free (ge2_free),
.ge3_free (ge3_free),
.input_tm_cnt (input_tm_cnt)
);
DE0_Nano_SOPC_cpu_oci_test_bench the_DE0_Nano_SOPC_cpu_oci_test_bench
(
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.test_ending (test_ending),
.test_has_ended (test_has_ended)
);
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
fifo_rdptr <= 0;
fifo_wrptr <= 0;
fifo_cnt <= 0;
overflow_pending <= 1;
end
else
begin
fifo_wrptr <= fifo_wrptr + fifo_wrptr_inc;
fifo_cnt <= fifo_cnt + fifo_cnt_inc;
if (~empty)
fifo_rdptr <= fifo_rdptr + 1;
if (~trc_this || (~ge2_free & input_ge2) || (~ge3_free & input_ge3))
overflow_pending <= 1;
else if (atm_valid | dtm_valid)
overflow_pending <= 0;
end
end
assign fifo_head = fifo_read_mux;
assign tw = 0 ? { (empty ? 4'h0 : fifo_head[35 : 32]), fifo_head[31 : 0]} : itm;
assign fifo_0_enable = ((fifo_wrptr == 4'd0) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd0) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd0) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_0 <= 0;
else if (fifo_0_enable)
fifo_0 <= fifo_0_mux;
end
assign fifo_0_mux = (((fifo_wrptr == 4'd0) && itm_valid))? itm :
(((fifo_wrptr == 4'd0) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd0) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_1_enable = ((fifo_wrptr == 4'd1) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd1) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd1) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_1 <= 0;
else if (fifo_1_enable)
fifo_1 <= fifo_1_mux;
end
assign fifo_1_mux = (((fifo_wrptr == 4'd1) && itm_valid))? itm :
(((fifo_wrptr == 4'd1) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd1) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_2_enable = ((fifo_wrptr == 4'd2) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd2) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd2) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_2 <= 0;
else if (fifo_2_enable)
fifo_2 <= fifo_2_mux;
end
assign fifo_2_mux = (((fifo_wrptr == 4'd2) && itm_valid))? itm :
(((fifo_wrptr == 4'd2) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd2) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_3_enable = ((fifo_wrptr == 4'd3) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd3) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd3) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_3 <= 0;
else if (fifo_3_enable)
fifo_3 <= fifo_3_mux;
end
assign fifo_3_mux = (((fifo_wrptr == 4'd3) && itm_valid))? itm :
(((fifo_wrptr == 4'd3) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd3) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_4_enable = ((fifo_wrptr == 4'd4) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd4) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd4) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_4 <= 0;
else if (fifo_4_enable)
fifo_4 <= fifo_4_mux;
end
assign fifo_4_mux = (((fifo_wrptr == 4'd4) && itm_valid))? itm :
(((fifo_wrptr == 4'd4) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd4) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_5_enable = ((fifo_wrptr == 4'd5) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd5) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd5) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_5 <= 0;
else if (fifo_5_enable)
fifo_5 <= fifo_5_mux;
end
assign fifo_5_mux = (((fifo_wrptr == 4'd5) && itm_valid))? itm :
(((fifo_wrptr == 4'd5) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd5) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_6_enable = ((fifo_wrptr == 4'd6) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd6) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd6) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_6 <= 0;
else if (fifo_6_enable)
fifo_6 <= fifo_6_mux;
end
assign fifo_6_mux = (((fifo_wrptr == 4'd6) && itm_valid))? itm :
(((fifo_wrptr == 4'd6) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd6) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_7_enable = ((fifo_wrptr == 4'd7) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd7) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd7) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_7 <= 0;
else if (fifo_7_enable)
fifo_7 <= fifo_7_mux;
end
assign fifo_7_mux = (((fifo_wrptr == 4'd7) && itm_valid))? itm :
(((fifo_wrptr == 4'd7) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd7) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_8_enable = ((fifo_wrptr == 4'd8) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd8) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd8) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_8 <= 0;
else if (fifo_8_enable)
fifo_8 <= fifo_8_mux;
end
assign fifo_8_mux = (((fifo_wrptr == 4'd8) && itm_valid))? itm :
(((fifo_wrptr == 4'd8) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd8) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_9_enable = ((fifo_wrptr == 4'd9) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd9) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd9) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_9 <= 0;
else if (fifo_9_enable)
fifo_9 <= fifo_9_mux;
end
assign fifo_9_mux = (((fifo_wrptr == 4'd9) && itm_valid))? itm :
(((fifo_wrptr == 4'd9) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd9) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_10_enable = ((fifo_wrptr == 4'd10) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd10) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd10) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_10 <= 0;
else if (fifo_10_enable)
fifo_10 <= fifo_10_mux;
end
assign fifo_10_mux = (((fifo_wrptr == 4'd10) && itm_valid))? itm :
(((fifo_wrptr == 4'd10) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd10) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_11_enable = ((fifo_wrptr == 4'd11) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd11) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd11) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_11 <= 0;
else if (fifo_11_enable)
fifo_11 <= fifo_11_mux;
end
assign fifo_11_mux = (((fifo_wrptr == 4'd11) && itm_valid))? itm :
(((fifo_wrptr == 4'd11) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd11) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_12_enable = ((fifo_wrptr == 4'd12) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd12) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd12) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_12 <= 0;
else if (fifo_12_enable)
fifo_12 <= fifo_12_mux;
end
assign fifo_12_mux = (((fifo_wrptr == 4'd12) && itm_valid))? itm :
(((fifo_wrptr == 4'd12) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd12) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_13_enable = ((fifo_wrptr == 4'd13) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd13) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd13) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_13 <= 0;
else if (fifo_13_enable)
fifo_13 <= fifo_13_mux;
end
assign fifo_13_mux = (((fifo_wrptr == 4'd13) && itm_valid))? itm :
(((fifo_wrptr == 4'd13) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd13) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_14_enable = ((fifo_wrptr == 4'd14) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd14) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd14) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_14 <= 0;
else if (fifo_14_enable)
fifo_14 <= fifo_14_mux;
end
assign fifo_14_mux = (((fifo_wrptr == 4'd14) && itm_valid))? itm :
(((fifo_wrptr == 4'd14) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd14) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_15_enable = ((fifo_wrptr == 4'd15) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd15) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd15) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_15 <= 0;
else if (fifo_15_enable)
fifo_15 <= fifo_15_mux;
end
assign fifo_15_mux = (((fifo_wrptr == 4'd15) && itm_valid))? itm :
(((fifo_wrptr == 4'd15) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd15) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign input_ge1 = |input_tm_cnt;
assign input_ge2 = input_tm_cnt[1];
assign input_ge3 = &input_tm_cnt;
assign overflow_pending_atm = {overflow_pending, atm[34 : 0]};
assign overflow_pending_dtm = {overflow_pending, dtm[34 : 0]};
assign fifo_read_mux = (fifo_rdptr == 4'd0)? fifo_0 :
(fifo_rdptr == 4'd1)? fifo_1 :
(fifo_rdptr == 4'd2)? fifo_2 :
(fifo_rdptr == 4'd3)? fifo_3 :
(fifo_rdptr == 4'd4)? fifo_4 :
(fifo_rdptr == 4'd5)? fifo_5 :
(fifo_rdptr == 4'd6)? fifo_6 :
(fifo_rdptr == 4'd7)? fifo_7 :
(fifo_rdptr == 4'd8)? fifo_8 :
(fifo_rdptr == 4'd9)? fifo_9 :
(fifo_rdptr == 4'd10)? fifo_10 :
(fifo_rdptr == 4'd11)? fifo_11 :
(fifo_rdptr == 4'd12)? fifo_12 :
(fifo_rdptr == 4'd13)? fifo_13 :
(fifo_rdptr == 4'd14)? fifo_14 :
fifo_15;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
)
;
output tr_clk;
output [ 17: 0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [ 35: 0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 17: 0] tr_data;
reg [ 17: 0] tr_data_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
assign phase = x1^x2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
x1 <= 0;
else
x1 <= ~x1;
end
always @(posedge clkx2 or negedge jrst_n)
begin
if (jrst_n == 0)
begin
x2 <= 0;
tr_clk_reg <= 0;
tr_data_reg <= 0;
end
else
begin
x2 <= x1;
tr_clk_reg <= ~phase;
tr_data_reg <= phase ? tw[17 : 0] : tw[35 : 18];
end
end
assign tr_clk = 0 ? tr_clk_reg : 0;
assign tr_data = 0 ? tr_data_reg : 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
)
;
output tracemem_on;
output [ 35: 0] tracemem_trcdata;
output tracemem_tw;
output trc_enb;
output [ 6: 0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_tracectrl;
input take_action_tracemem_a;
input take_action_tracemem_b;
input take_no_action_tracemem_a;
input [ 15: 0] trc_ctrl;
input [ 35: 0] tw;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire trc_enb;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 35: 0] trc_im_data;
reg [ 16: 0] trc_jtag_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (!0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (take_action_tracectrl &&
(jdo[4] | jdo[3]))
begin
if (jdo[4])
trc_im_addr <= 0;
if (jdo[3])
trc_wrap <= 0;
end
else if (trc_enb & trc_on_chip & tw_valid)
begin
trc_im_addr <= trc_im_addr+1;
if (&trc_im_addr)
trc_wrap <= 1;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trc_jtag_addr <= 0;
else if (take_action_tracemem_a ||
take_no_action_tracemem_a ||
take_action_tracemem_b)
trc_jtag_addr <= take_action_tracemem_a ?
jdo[35 : 19] :
trc_jtag_addr + 1;
end
assign trc_enb = trc_ctrl[0];
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_tw = trc_wrap;
assign tracemem_on = trc_enb;
assign tracemem_trcdata = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_nios2_performance_monitors
;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu_nios2_oci (
// inputs:
D_valid,
E_st_data,
E_valid,
F_pc,
address_nxt,
av_ld_data_aligned_filtered,
byteenable_nxt,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugaccess_nxt,
hbreak_enabled,
read_nxt,
reset,
reset_n,
reset_req,
test_ending,
test_has_ended,
write_nxt,
writedata_nxt,
// outputs:
jtag_debug_module_debugaccess_to_roms,
oci_hbreak_req,
oci_ienable,
oci_single_step_mode,
readdata,
resetrequest,
waitrequest
)
;
output jtag_debug_module_debugaccess_to_roms;
output oci_hbreak_req;
output [ 31: 0] oci_ienable;
output oci_single_step_mode;
output [ 31: 0] readdata;
output resetrequest;
output waitrequest;
input D_valid;
input [ 31: 0] E_st_data;
input E_valid;
input [ 24: 0] F_pc;
input [ 8: 0] address_nxt;
input [ 31: 0] av_ld_data_aligned_filtered;
input [ 3: 0] byteenable_nxt;
input clk;
input [ 26: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugaccess_nxt;
input hbreak_enabled;
input read_nxt;
input reset;
input reset_n;
input reset_req;
input test_ending;
input test_has_ended;
input write_nxt;
input [ 31: 0] writedata_nxt;
wire [ 31: 0] MonDReg;
reg [ 8: 0] address;
wire [ 35: 0] atm;
wire [ 31: 0] break_readreg;
reg [ 3: 0] byteenable;
wire clkx2;
wire [ 26: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk_break;
wire dbrk_goto0;
wire dbrk_goto1;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire dbrk_traceme;
wire dbrk_traceoff;
wire dbrk_traceon;
wire dbrk_trigout;
wire [ 29: 0] dct_buffer;
wire [ 3: 0] dct_count;
reg debugaccess;
wire debugack;
wire debugreq;
wire [ 35: 0] dtm;
wire dummy_sink;
wire [ 35: 0] itm;
wire [ 37: 0] jdo;
wire jrst_n;
wire jtag_debug_module_debugaccess_to_roms;
wire monitor_error;
wire monitor_go;
wire monitor_ready;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire [ 31: 0] oci_reg_readdata;
wire oci_single_step_mode;
wire [ 31: 0] ociram_readdata;
wire ocireg_ers;
wire ocireg_mrs;
reg read;
reg [ 31: 0] readdata;
wire resetlatch;
wire resetrequest;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_ocireg;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire tr_clk;
wire [ 17: 0] tr_data;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire [ 15: 0] trc_ctrl;
wire trc_enb;
wire [ 6: 0] trc_im_addr;
wire trc_on;
wire trc_wrap;
wire trigbrktype;
wire trigger_state_0;
wire trigger_state_1;
wire trigout;
wire [ 35: 0] tw;
wire waitrequest;
reg write;
reg [ 31: 0] writedata;
wire xbrk_break;
wire [ 7: 0] xbrk_ctrl0;
wire [ 7: 0] xbrk_ctrl1;
wire [ 7: 0] xbrk_ctrl2;
wire [ 7: 0] xbrk_ctrl3;
wire xbrk_goto0;
wire xbrk_goto1;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
wire xbrk_wrap_traceoff;
DE0_Nano_SOPC_cpu_nios2_oci_debug the_DE0_Nano_SOPC_cpu_nios2_oci_debug
(
.clk (clk),
.dbrk_break (dbrk_break),
.debugack (debugack),
.debugreq (debugreq),
.hbreak_enabled (hbreak_enabled),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_hbreak_req (oci_hbreak_req),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset (reset),
.resetlatch (resetlatch),
.resetrequest (resetrequest),
.st_ready_test_idle (st_ready_test_idle),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocireg (take_action_ocireg),
.xbrk_break (xbrk_break)
);
DE0_Nano_SOPC_cpu_nios2_ocimem the_DE0_Nano_SOPC_cpu_nios2_ocimem
(
.MonDReg (MonDReg),
.address (address),
.byteenable (byteenable),
.clk (clk),
.debugaccess (debugaccess),
.jdo (jdo),
.jrst_n (jrst_n),
.ociram_readdata (ociram_readdata),
.read (read),
.reset_req (reset_req),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.waitrequest (waitrequest),
.write (write),
.writedata (writedata)
);
DE0_Nano_SOPC_cpu_nios2_avalon_reg the_DE0_Nano_SOPC_cpu_nios2_avalon_reg
(
.address (address),
.clk (clk),
.debugaccess (debugaccess),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_ienable (oci_ienable),
.oci_reg_readdata (oci_reg_readdata),
.oci_single_step_mode (oci_single_step_mode),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset_n (reset_n),
.take_action_ocireg (take_action_ocireg),
.write (write),
.writedata (writedata)
);
DE0_Nano_SOPC_cpu_nios2_oci_break the_DE0_Nano_SOPC_cpu_nios2_oci_break
(
.break_readreg (break_readreg),
.clk (clk),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.trigbrktype (trigbrktype),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1)
);
DE0_Nano_SOPC_cpu_nios2_oci_xbrk the_DE0_Nano_SOPC_cpu_nios2_oci_xbrk
(
.D_valid (D_valid),
.E_valid (E_valid),
.F_pc (F_pc),
.clk (clk),
.reset_n (reset_n),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_break (xbrk_break),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_trigout (xbrk_trigout)
);
DE0_Nano_SOPC_cpu_nios2_oci_dbrk the_DE0_Nano_SOPC_cpu_nios2_oci_dbrk
(
.E_st_data (E_st_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dbrk_trigout (dbrk_trigout),
.debugack (debugack),
.reset_n (reset_n)
);
DE0_Nano_SOPC_cpu_nios2_oci_itrace the_DE0_Nano_SOPC_cpu_nios2_oci_itrace
(
.clk (clk),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.itm (itm),
.jdo (jdo),
.jrst_n (jrst_n),
.take_action_tracectrl (take_action_tracectrl),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_on (trc_on),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
DE0_Nano_SOPC_cpu_nios2_oci_dtrace the_DE0_Nano_SOPC_cpu_nios2_oci_dtrace
(
.atm (atm),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.dtm (dtm),
.jrst_n (jrst_n),
.trc_ctrl (trc_ctrl)
);
DE0_Nano_SOPC_cpu_nios2_oci_fifo the_DE0_Nano_SOPC_cpu_nios2_oci_fifo
(
.atm (atm),
.clk (clk),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.dtm (dtm),
.itm (itm),
.jrst_n (jrst_n),
.reset_n (reset_n),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.trc_on (trc_on),
.tw (tw)
);
DE0_Nano_SOPC_cpu_nios2_oci_pib the_DE0_Nano_SOPC_cpu_nios2_oci_pib
(
.clk (clk),
.clkx2 (clkx2),
.jrst_n (jrst_n),
.tr_clk (tr_clk),
.tr_data (tr_data),
.tw (tw)
);
DE0_Nano_SOPC_cpu_nios2_oci_im the_DE0_Nano_SOPC_cpu_nios2_oci_im
(
.clk (clk),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_im_addr (trc_im_addr),
.trc_wrap (trc_wrap),
.tw (tw),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
assign trigout = dbrk_trigout | xbrk_trigout;
assign jtag_debug_module_debugaccess_to_roms = debugack;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
address <= 0;
else
address <= address_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
byteenable <= 0;
else
byteenable <= byteenable_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
writedata <= 0;
else
writedata <= writedata_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
debugaccess <= 0;
else
debugaccess <= debugaccess_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
read <= 0;
else
read <= read ? waitrequest : read_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
write <= 0;
else
write <= write ? waitrequest : write_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
readdata <= 0;
else
readdata <= address[8] ? oci_reg_readdata : ociram_readdata;
end
DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper the_DE0_Nano_SOPC_cpu_jtag_debug_module_wrapper
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.clk (clk),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.st_ready_test_idle (st_ready_test_idle),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1)
);
//dummy sink, which is an e_mux
assign dummy_sink = tr_clk |
tr_data |
trigout |
debugack;
assign debugreq = 0;
assign clkx2 = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_cpu (
// inputs:
clk,
d_irq,
d_readdata,
d_waitrequest,
i_readdata,
i_waitrequest,
jtag_debug_module_address,
jtag_debug_module_byteenable,
jtag_debug_module_debugaccess,
jtag_debug_module_read,
jtag_debug_module_write,
jtag_debug_module_writedata,
reset_n,
reset_req,
// outputs:
d_address,
d_byteenable,
d_read,
d_write,
d_writedata,
i_address,
i_read,
jtag_debug_module_debugaccess_to_roms,
jtag_debug_module_readdata,
jtag_debug_module_resetrequest,
jtag_debug_module_waitrequest,
no_ci_readra
)
;
output [ 26: 0] d_address;
output [ 3: 0] d_byteenable;
output d_read;
output d_write;
output [ 31: 0] d_writedata;
output [ 26: 0] i_address;
output i_read;
output jtag_debug_module_debugaccess_to_roms;
output [ 31: 0] jtag_debug_module_readdata;
output jtag_debug_module_resetrequest;
output jtag_debug_module_waitrequest;
output no_ci_readra;
input clk;
input [ 31: 0] d_irq;
input [ 31: 0] d_readdata;
input d_waitrequest;
input [ 31: 0] i_readdata;
input i_waitrequest;
input [ 8: 0] jtag_debug_module_address;
input [ 3: 0] jtag_debug_module_byteenable;
input jtag_debug_module_debugaccess;
input jtag_debug_module_read;
input jtag_debug_module_write;
input [ 31: 0] jtag_debug_module_writedata;
input reset_n;
input reset_req;
wire [ 1: 0] D_compare_op;
wire D_ctrl_alu_force_xor;
wire D_ctrl_alu_signed_comparison;
wire D_ctrl_alu_subtract;
wire D_ctrl_b_is_dst;
wire D_ctrl_br;
wire D_ctrl_br_cmp;
wire D_ctrl_br_uncond;
wire D_ctrl_break;
wire D_ctrl_crst;
wire D_ctrl_custom;
wire D_ctrl_custom_multi;
wire D_ctrl_exception;
wire D_ctrl_force_src2_zero;
wire D_ctrl_hi_imm16;
wire D_ctrl_ignore_dst;
wire D_ctrl_implicit_dst_eretaddr;
wire D_ctrl_implicit_dst_retaddr;
wire D_ctrl_jmp_direct;
wire D_ctrl_jmp_indirect;
wire D_ctrl_ld;
wire D_ctrl_ld_io;
wire D_ctrl_ld_non_io;
wire D_ctrl_ld_signed;
wire D_ctrl_logic;
wire D_ctrl_rdctl_inst;
wire D_ctrl_retaddr;
wire D_ctrl_rot_right;
wire D_ctrl_shift_logical;
wire D_ctrl_shift_right_arith;
wire D_ctrl_shift_rot;
wire D_ctrl_shift_rot_right;
wire D_ctrl_src2_choose_imm;
wire D_ctrl_st;
wire D_ctrl_uncond_cti_non_br;
wire D_ctrl_unsigned_lo_imm16;
wire D_ctrl_wrctl_inst;
wire [ 4: 0] D_dst_regnum;
wire [ 55: 0] D_inst;
reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 4: 0] D_iw_a;
wire [ 4: 0] D_iw_b;
wire [ 4: 0] D_iw_c;
wire [ 2: 0] D_iw_control_regnum;
wire [ 7: 0] D_iw_custom_n;
wire D_iw_custom_readra;
wire D_iw_custom_readrb;
wire D_iw_custom_writerc;
wire [ 15: 0] D_iw_imm16;
wire [ 25: 0] D_iw_imm26;
wire [ 4: 0] D_iw_imm5;
wire [ 1: 0] D_iw_memsz;
wire [ 5: 0] D_iw_op;
wire [ 5: 0] D_iw_opx;
wire [ 4: 0] D_iw_shift_imm5;
wire [ 4: 0] D_iw_trap_break_imm5;
wire [ 24: 0] D_jmp_direct_target_waddr;
wire [ 1: 0] D_logic_op;
wire [ 1: 0] D_logic_op_raw;
wire D_mem16;
wire D_mem32;
wire D_mem8;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_opx;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_rsv02;
wire D_op_rsv09;
wire D_op_rsv10;
wire D_op_rsv17;
wire D_op_rsv18;
wire D_op_rsv25;
wire D_op_rsv26;
wire D_op_rsv33;
wire D_op_rsv34;
wire D_op_rsv41;
wire D_op_rsv42;
wire D_op_rsv49;
wire D_op_rsv57;
wire D_op_rsv61;
wire D_op_rsv62;
wire D_op_rsv63;
wire D_op_rsvx00;
wire D_op_rsvx10;
wire D_op_rsvx15;
wire D_op_rsvx17;
wire D_op_rsvx21;
wire D_op_rsvx25;
wire D_op_rsvx33;
wire D_op_rsvx34;
wire D_op_rsvx35;
wire D_op_rsvx42;
wire D_op_rsvx43;
wire D_op_rsvx44;
wire D_op_rsvx47;
wire D_op_rsvx50;
wire D_op_rsvx51;
wire D_op_rsvx55;
wire D_op_rsvx56;
wire D_op_rsvx60;
wire D_op_rsvx63;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
reg D_valid;
wire [ 55: 0] D_vinst;
wire D_wr_dst_reg;
wire [ 31: 0] E_alu_result;
reg E_alu_sub;
wire [ 32: 0] E_arith_result;
wire [ 31: 0] E_arith_src1;
wire [ 31: 0] E_arith_src2;
wire E_ci_multi_stall;
wire [ 31: 0] E_ci_result;
wire E_cmp_result;
wire [ 31: 0] E_control_rd_data;
wire E_eq;
reg E_invert_arith_src_msb;
wire E_ld_stall;
wire [ 31: 0] E_logic_result;
wire E_logic_result_is_0;
wire E_lt;
wire [ 26: 0] E_mem_baddr;
wire [ 3: 0] E_mem_byte_en;
reg E_new_inst;
reg [ 4: 0] E_shift_rot_cnt;
wire [ 4: 0] E_shift_rot_cnt_nxt;
wire E_shift_rot_done;
wire E_shift_rot_fill_bit;
reg [ 31: 0] E_shift_rot_result;
wire [ 31: 0] E_shift_rot_result_nxt;
wire E_shift_rot_stall;
reg [ 31: 0] E_src1;
reg [ 31: 0] E_src2;
wire [ 31: 0] E_st_data;
wire E_st_stall;
wire E_stall;
reg E_valid;
wire [ 55: 0] E_vinst;
wire E_wrctl_bstatus;
wire E_wrctl_estatus;
wire E_wrctl_ienable;
wire E_wrctl_status;
wire [ 31: 0] F_av_iw;
wire [ 4: 0] F_av_iw_a;
wire [ 4: 0] F_av_iw_b;
wire [ 4: 0] F_av_iw_c;
wire [ 2: 0] F_av_iw_control_regnum;
wire [ 7: 0] F_av_iw_custom_n;
wire F_av_iw_custom_readra;
wire F_av_iw_custom_readrb;
wire F_av_iw_custom_writerc;
wire [ 15: 0] F_av_iw_imm16;
wire [ 25: 0] F_av_iw_imm26;
wire [ 4: 0] F_av_iw_imm5;
wire [ 1: 0] F_av_iw_memsz;
wire [ 5: 0] F_av_iw_op;
wire [ 5: 0] F_av_iw_opx;
wire [ 4: 0] F_av_iw_shift_imm5;
wire [ 4: 0] F_av_iw_trap_break_imm5;
wire F_av_mem16;
wire F_av_mem32;
wire F_av_mem8;
wire [ 55: 0] F_inst;
wire [ 31: 0] F_iw;
wire [ 4: 0] F_iw_a;
wire [ 4: 0] F_iw_b;
wire [ 4: 0] F_iw_c;
wire [ 2: 0] F_iw_control_regnum;
wire [ 7: 0] F_iw_custom_n;
wire F_iw_custom_readra;
wire F_iw_custom_readrb;
wire F_iw_custom_writerc;
wire [ 15: 0] F_iw_imm16;
wire [ 25: 0] F_iw_imm26;
wire [ 4: 0] F_iw_imm5;
wire [ 1: 0] F_iw_memsz;
wire [ 5: 0] F_iw_op;
wire [ 5: 0] F_iw_opx;
wire [ 4: 0] F_iw_shift_imm5;
wire [ 4: 0] F_iw_trap_break_imm5;
wire F_mem16;
wire F_mem32;
wire F_mem8;
wire F_op_add;
wire F_op_addi;
wire F_op_and;
wire F_op_andhi;
wire F_op_andi;
wire F_op_beq;
wire F_op_bge;
wire F_op_bgeu;
wire F_op_blt;
wire F_op_bltu;
wire F_op_bne;
wire F_op_br;
wire F_op_break;
wire F_op_bret;
wire F_op_call;
wire F_op_callr;
wire F_op_cmpeq;
wire F_op_cmpeqi;
wire F_op_cmpge;
wire F_op_cmpgei;
wire F_op_cmpgeu;
wire F_op_cmpgeui;
wire F_op_cmplt;
wire F_op_cmplti;
wire F_op_cmpltu;
wire F_op_cmpltui;
wire F_op_cmpne;
wire F_op_cmpnei;
wire F_op_crst;
wire F_op_custom;
wire F_op_div;
wire F_op_divu;
wire F_op_eret;
wire F_op_flushd;
wire F_op_flushda;
wire F_op_flushi;
wire F_op_flushp;
wire F_op_hbreak;
wire F_op_initd;
wire F_op_initda;
wire F_op_initi;
wire F_op_intr;
wire F_op_jmp;
wire F_op_jmpi;
wire F_op_ldb;
wire F_op_ldbio;
wire F_op_ldbu;
wire F_op_ldbuio;
wire F_op_ldh;
wire F_op_ldhio;
wire F_op_ldhu;
wire F_op_ldhuio;
wire F_op_ldl;
wire F_op_ldw;
wire F_op_ldwio;
wire F_op_mul;
wire F_op_muli;
wire F_op_mulxss;
wire F_op_mulxsu;
wire F_op_mulxuu;
wire F_op_nextpc;
wire F_op_nor;
wire F_op_opx;
wire F_op_or;
wire F_op_orhi;
wire F_op_ori;
wire F_op_rdctl;
wire F_op_rdprs;
wire F_op_ret;
wire F_op_rol;
wire F_op_roli;
wire F_op_ror;
wire F_op_rsv02;
wire F_op_rsv09;
wire F_op_rsv10;
wire F_op_rsv17;
wire F_op_rsv18;
wire F_op_rsv25;
wire F_op_rsv26;
wire F_op_rsv33;
wire F_op_rsv34;
wire F_op_rsv41;
wire F_op_rsv42;
wire F_op_rsv49;
wire F_op_rsv57;
wire F_op_rsv61;
wire F_op_rsv62;
wire F_op_rsv63;
wire F_op_rsvx00;
wire F_op_rsvx10;
wire F_op_rsvx15;
wire F_op_rsvx17;
wire F_op_rsvx21;
wire F_op_rsvx25;
wire F_op_rsvx33;
wire F_op_rsvx34;
wire F_op_rsvx35;
wire F_op_rsvx42;
wire F_op_rsvx43;
wire F_op_rsvx44;
wire F_op_rsvx47;
wire F_op_rsvx50;
wire F_op_rsvx51;
wire F_op_rsvx55;
wire F_op_rsvx56;
wire F_op_rsvx60;
wire F_op_rsvx63;
wire F_op_sll;
wire F_op_slli;
wire F_op_sra;
wire F_op_srai;
wire F_op_srl;
wire F_op_srli;
wire F_op_stb;
wire F_op_stbio;
wire F_op_stc;
wire F_op_sth;
wire F_op_sthio;
wire F_op_stw;
wire F_op_stwio;
wire F_op_sub;
wire F_op_sync;
wire F_op_trap;
wire F_op_wrctl;
wire F_op_wrprs;
wire F_op_xor;
wire F_op_xorhi;
wire F_op_xori;
reg [ 24: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire F_pc_en;
wire [ 24: 0] F_pc_no_crst_nxt;
wire [ 24: 0] F_pc_nxt;
wire [ 24: 0] F_pc_plus_one;
wire [ 1: 0] F_pc_sel_nxt;
wire [ 26: 0] F_pcb;
wire [ 26: 0] F_pcb_nxt;
wire [ 26: 0] F_pcb_plus_four;
wire F_valid;
wire [ 55: 0] F_vinst;
reg [ 1: 0] R_compare_op;
reg R_ctrl_alu_force_xor;
wire R_ctrl_alu_force_xor_nxt;
reg R_ctrl_alu_signed_comparison;
wire R_ctrl_alu_signed_comparison_nxt;
reg R_ctrl_alu_subtract;
wire R_ctrl_alu_subtract_nxt;
reg R_ctrl_b_is_dst;
wire R_ctrl_b_is_dst_nxt;
reg R_ctrl_br;
reg R_ctrl_br_cmp;
wire R_ctrl_br_cmp_nxt;
wire R_ctrl_br_nxt;
reg R_ctrl_br_uncond;
wire R_ctrl_br_uncond_nxt;
reg R_ctrl_break;
wire R_ctrl_break_nxt;
reg R_ctrl_crst;
wire R_ctrl_crst_nxt;
reg R_ctrl_custom;
reg R_ctrl_custom_multi;
wire R_ctrl_custom_multi_nxt;
wire R_ctrl_custom_nxt;
reg R_ctrl_exception;
wire R_ctrl_exception_nxt;
reg R_ctrl_force_src2_zero;
wire R_ctrl_force_src2_zero_nxt;
reg R_ctrl_hi_imm16;
wire R_ctrl_hi_imm16_nxt;
reg R_ctrl_ignore_dst;
wire R_ctrl_ignore_dst_nxt;
reg R_ctrl_implicit_dst_eretaddr;
wire R_ctrl_implicit_dst_eretaddr_nxt;
reg R_ctrl_implicit_dst_retaddr;
wire R_ctrl_implicit_dst_retaddr_nxt;
reg R_ctrl_jmp_direct;
wire R_ctrl_jmp_direct_nxt;
reg R_ctrl_jmp_indirect;
wire R_ctrl_jmp_indirect_nxt;
reg R_ctrl_ld;
reg R_ctrl_ld_io;
wire R_ctrl_ld_io_nxt;
reg R_ctrl_ld_non_io;
wire R_ctrl_ld_non_io_nxt;
wire R_ctrl_ld_nxt;
reg R_ctrl_ld_signed;
wire R_ctrl_ld_signed_nxt;
reg R_ctrl_logic;
wire R_ctrl_logic_nxt;
reg R_ctrl_rdctl_inst;
wire R_ctrl_rdctl_inst_nxt;
reg R_ctrl_retaddr;
wire R_ctrl_retaddr_nxt;
reg R_ctrl_rot_right;
wire R_ctrl_rot_right_nxt;
reg R_ctrl_shift_logical;
wire R_ctrl_shift_logical_nxt;
reg R_ctrl_shift_right_arith;
wire R_ctrl_shift_right_arith_nxt;
reg R_ctrl_shift_rot;
wire R_ctrl_shift_rot_nxt;
reg R_ctrl_shift_rot_right;
wire R_ctrl_shift_rot_right_nxt;
reg R_ctrl_src2_choose_imm;
wire R_ctrl_src2_choose_imm_nxt;
reg R_ctrl_st;
wire R_ctrl_st_nxt;
reg R_ctrl_uncond_cti_non_br;
wire R_ctrl_uncond_cti_non_br_nxt;
reg R_ctrl_unsigned_lo_imm16;
wire R_ctrl_unsigned_lo_imm16_nxt;
reg R_ctrl_wrctl_inst;
wire R_ctrl_wrctl_inst_nxt;
reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire R_en;
reg [ 1: 0] R_logic_op;
wire [ 31: 0] R_rf_a;
wire [ 31: 0] R_rf_b;
wire [ 31: 0] R_src1;
wire [ 31: 0] R_src2;
wire [ 15: 0] R_src2_hi;
wire [ 15: 0] R_src2_lo;
reg R_src2_use_imm;
wire [ 7: 0] R_stb_data;
wire [ 15: 0] R_sth_data;
reg R_valid;
wire [ 55: 0] R_vinst;
reg R_wr_dst_reg;
reg [ 31: 0] W_alu_result;
wire W_br_taken;
reg W_bstatus_reg;
wire W_bstatus_reg_inst_nxt;
wire W_bstatus_reg_nxt;
reg W_cmp_result;
reg [ 31: 0] W_control_rd_data;
wire [ 31: 0] W_cpuid_reg;
reg W_estatus_reg;
wire W_estatus_reg_inst_nxt;
wire W_estatus_reg_nxt;
reg [ 31: 0] W_ienable_reg;
wire [ 31: 0] W_ienable_reg_nxt;
reg [ 31: 0] W_ipending_reg;
wire [ 31: 0] W_ipending_reg_nxt;
wire [ 26: 0] W_mem_baddr;
wire [ 31: 0] W_rf_wr_data;
wire W_rf_wren;
wire W_status_reg;
reg W_status_reg_pie;
wire W_status_reg_pie_inst_nxt;
wire W_status_reg_pie_nxt;
reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 55: 0] W_vinst;
wire [ 31: 0] W_wr_data;
wire [ 31: 0] W_wr_data_non_zero;
wire av_fill_bit;
reg [ 1: 0] av_ld_align_cycle;
wire [ 1: 0] av_ld_align_cycle_nxt;
wire av_ld_align_one_more_cycle;
reg av_ld_aligning_data;
wire av_ld_aligning_data_nxt;
reg [ 7: 0] av_ld_byte0_data;
wire [ 7: 0] av_ld_byte0_data_nxt;
reg [ 7: 0] av_ld_byte1_data;
wire av_ld_byte1_data_en;
wire [ 7: 0] av_ld_byte1_data_nxt;
reg [ 7: 0] av_ld_byte2_data;
wire [ 7: 0] av_ld_byte2_data_nxt;
reg [ 7: 0] av_ld_byte3_data;
wire [ 7: 0] av_ld_byte3_data_nxt;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire [ 31: 0] av_ld_data_aligned_unfiltered;
wire av_ld_done;
wire av_ld_extend;
wire av_ld_getting_data;
wire av_ld_rshift8;
reg av_ld_waiting_for_data;
wire av_ld_waiting_for_data_nxt;
wire av_sign_bit;
wire [ 26: 0] d_address;
reg [ 3: 0] d_byteenable;
reg d_read;
wire d_read_nxt;
reg d_write;
wire d_write_nxt;
reg [ 31: 0] d_writedata;
reg hbreak_enabled;
reg hbreak_pending;
wire hbreak_pending_nxt;
wire hbreak_req;
wire [ 26: 0] i_address;
reg i_read;
wire i_read_nxt;
wire [ 31: 0] iactive;
wire intr_req;
wire jtag_debug_module_clk;
wire jtag_debug_module_debugaccess_to_roms;
wire [ 31: 0] jtag_debug_module_readdata;
wire jtag_debug_module_reset;
wire jtag_debug_module_resetrequest;
wire jtag_debug_module_waitrequest;
wire no_ci_readra;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire oci_single_step_mode;
wire oci_tb_hbreak_req;
wire test_ending;
wire test_has_ended;
reg wait_for_one_post_bret_inst;
//the_DE0_Nano_SOPC_cpu_test_bench, which is an e_instance
DE0_Nano_SOPC_cpu_test_bench the_DE0_Nano_SOPC_cpu_test_bench
(
.D_iw (D_iw),
.D_iw_op (D_iw_op),
.D_iw_opx (D_iw_opx),
.D_valid (D_valid),
.E_valid (E_valid),
.F_pcb (F_pcb),
.F_valid (F_valid),
.R_ctrl_ld (R_ctrl_ld),
.R_ctrl_ld_non_io (R_ctrl_ld_non_io),
.R_dst_regnum (R_dst_regnum),
.R_wr_dst_reg (R_wr_dst_reg),
.W_valid (W_valid),
.W_vinst (W_vinst),
.W_wr_data (W_wr_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered),
.clk (clk),
.d_address (d_address),
.d_byteenable (d_byteenable),
.d_read (d_read),
.d_write (d_write),
.i_address (i_address),
.i_read (i_read),
.i_readdata (i_readdata),
.i_waitrequest (i_waitrequest),
.reset_n (reset_n),
.test_has_ended (test_has_ended)
);
assign F_av_iw_a = F_av_iw[31 : 27];
assign F_av_iw_b = F_av_iw[26 : 22];
assign F_av_iw_c = F_av_iw[21 : 17];
assign F_av_iw_custom_n = F_av_iw[13 : 6];
assign F_av_iw_custom_readra = F_av_iw[16];
assign F_av_iw_custom_readrb = F_av_iw[15];
assign F_av_iw_custom_writerc = F_av_iw[14];
assign F_av_iw_opx = F_av_iw[16 : 11];
assign F_av_iw_op = F_av_iw[5 : 0];
assign F_av_iw_shift_imm5 = F_av_iw[10 : 6];
assign F_av_iw_trap_break_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm16 = F_av_iw[21 : 6];
assign F_av_iw_imm26 = F_av_iw[31 : 6];
assign F_av_iw_memsz = F_av_iw[4 : 3];
assign F_av_iw_control_regnum = F_av_iw[8 : 6];
assign F_av_mem8 = F_av_iw_memsz == 2'b00;
assign F_av_mem16 = F_av_iw_memsz == 2'b01;
assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1;
assign F_iw_a = F_iw[31 : 27];
assign F_iw_b = F_iw[26 : 22];
assign F_iw_c = F_iw[21 : 17];
assign F_iw_custom_n = F_iw[13 : 6];
assign F_iw_custom_readra = F_iw[16];
assign F_iw_custom_readrb = F_iw[15];
assign F_iw_custom_writerc = F_iw[14];
assign F_iw_opx = F_iw[16 : 11];
assign F_iw_op = F_iw[5 : 0];
assign F_iw_shift_imm5 = F_iw[10 : 6];
assign F_iw_trap_break_imm5 = F_iw[10 : 6];
assign F_iw_imm5 = F_iw[10 : 6];
assign F_iw_imm16 = F_iw[21 : 6];
assign F_iw_imm26 = F_iw[31 : 6];
assign F_iw_memsz = F_iw[4 : 3];
assign F_iw_control_regnum = F_iw[8 : 6];
assign F_mem8 = F_iw_memsz == 2'b00;
assign F_mem16 = F_iw_memsz == 2'b01;
assign F_mem32 = F_iw_memsz[1] == 1'b1;
assign D_iw_a = D_iw[31 : 27];
assign D_iw_b = D_iw[26 : 22];
assign D_iw_c = D_iw[21 : 17];
assign D_iw_custom_n = D_iw[13 : 6];
assign D_iw_custom_readra = D_iw[16];
assign D_iw_custom_readrb = D_iw[15];
assign D_iw_custom_writerc = D_iw[14];
assign D_iw_opx = D_iw[16 : 11];
assign D_iw_op = D_iw[5 : 0];
assign D_iw_shift_imm5 = D_iw[10 : 6];
assign D_iw_trap_break_imm5 = D_iw[10 : 6];
assign D_iw_imm5 = D_iw[10 : 6];
assign D_iw_imm16 = D_iw[21 : 6];
assign D_iw_imm26 = D_iw[31 : 6];
assign D_iw_memsz = D_iw[4 : 3];
assign D_iw_control_regnum = D_iw[8 : 6];
assign D_mem8 = D_iw_memsz == 2'b00;
assign D_mem16 = D_iw_memsz == 2'b01;
assign D_mem32 = D_iw_memsz[1] == 1'b1;
assign F_op_call = F_iw_op == 0;
assign F_op_jmpi = F_iw_op == 1;
assign F_op_ldbu = F_iw_op == 3;
assign F_op_addi = F_iw_op == 4;
assign F_op_stb = F_iw_op == 5;
assign F_op_br = F_iw_op == 6;
assign F_op_ldb = F_iw_op == 7;
assign F_op_cmpgei = F_iw_op == 8;
assign F_op_ldhu = F_iw_op == 11;
assign F_op_andi = F_iw_op == 12;
assign F_op_sth = F_iw_op == 13;
assign F_op_bge = F_iw_op == 14;
assign F_op_ldh = F_iw_op == 15;
assign F_op_cmplti = F_iw_op == 16;
assign F_op_initda = F_iw_op == 19;
assign F_op_ori = F_iw_op == 20;
assign F_op_stw = F_iw_op == 21;
assign F_op_blt = F_iw_op == 22;
assign F_op_ldw = F_iw_op == 23;
assign F_op_cmpnei = F_iw_op == 24;
assign F_op_flushda = F_iw_op == 27;
assign F_op_xori = F_iw_op == 28;
assign F_op_stc = F_iw_op == 29;
assign F_op_bne = F_iw_op == 30;
assign F_op_ldl = F_iw_op == 31;
assign F_op_cmpeqi = F_iw_op == 32;
assign F_op_ldbuio = F_iw_op == 35;
assign F_op_muli = F_iw_op == 36;
assign F_op_stbio = F_iw_op == 37;
assign F_op_beq = F_iw_op == 38;
assign F_op_ldbio = F_iw_op == 39;
assign F_op_cmpgeui = F_iw_op == 40;
assign F_op_ldhuio = F_iw_op == 43;
assign F_op_andhi = F_iw_op == 44;
assign F_op_sthio = F_iw_op == 45;
assign F_op_bgeu = F_iw_op == 46;
assign F_op_ldhio = F_iw_op == 47;
assign F_op_cmpltui = F_iw_op == 48;
assign F_op_initd = F_iw_op == 51;
assign F_op_orhi = F_iw_op == 52;
assign F_op_stwio = F_iw_op == 53;
assign F_op_bltu = F_iw_op == 54;
assign F_op_ldwio = F_iw_op == 55;
assign F_op_rdprs = F_iw_op == 56;
assign F_op_flushd = F_iw_op == 59;
assign F_op_xorhi = F_iw_op == 60;
assign F_op_rsv02 = F_iw_op == 2;
assign F_op_rsv09 = F_iw_op == 9;
assign F_op_rsv10 = F_iw_op == 10;
assign F_op_rsv17 = F_iw_op == 17;
assign F_op_rsv18 = F_iw_op == 18;
assign F_op_rsv25 = F_iw_op == 25;
assign F_op_rsv26 = F_iw_op == 26;
assign F_op_rsv33 = F_iw_op == 33;
assign F_op_rsv34 = F_iw_op == 34;
assign F_op_rsv41 = F_iw_op == 41;
assign F_op_rsv42 = F_iw_op == 42;
assign F_op_rsv49 = F_iw_op == 49;
assign F_op_rsv57 = F_iw_op == 57;
assign F_op_rsv61 = F_iw_op == 61;
assign F_op_rsv62 = F_iw_op == 62;
assign F_op_rsv63 = F_iw_op == 63;
assign F_op_eret = F_op_opx & (F_iw_opx == 1);
assign F_op_roli = F_op_opx & (F_iw_opx == 2);
assign F_op_rol = F_op_opx & (F_iw_opx == 3);
assign F_op_flushp = F_op_opx & (F_iw_opx == 4);
assign F_op_ret = F_op_opx & (F_iw_opx == 5);
assign F_op_nor = F_op_opx & (F_iw_opx == 6);
assign F_op_mulxuu = F_op_opx & (F_iw_opx == 7);
assign F_op_cmpge = F_op_opx & (F_iw_opx == 8);
assign F_op_bret = F_op_opx & (F_iw_opx == 9);
assign F_op_ror = F_op_opx & (F_iw_opx == 11);
assign F_op_flushi = F_op_opx & (F_iw_opx == 12);
assign F_op_jmp = F_op_opx & (F_iw_opx == 13);
assign F_op_and = F_op_opx & (F_iw_opx == 14);
assign F_op_cmplt = F_op_opx & (F_iw_opx == 16);
assign F_op_slli = F_op_opx & (F_iw_opx == 18);
assign F_op_sll = F_op_opx & (F_iw_opx == 19);
assign F_op_wrprs = F_op_opx & (F_iw_opx == 20);
assign F_op_or = F_op_opx & (F_iw_opx == 22);
assign F_op_mulxsu = F_op_opx & (F_iw_opx == 23);
assign F_op_cmpne = F_op_opx & (F_iw_opx == 24);
assign F_op_srli = F_op_opx & (F_iw_opx == 26);
assign F_op_srl = F_op_opx & (F_iw_opx == 27);
assign F_op_nextpc = F_op_opx & (F_iw_opx == 28);
assign F_op_callr = F_op_opx & (F_iw_opx == 29);
assign F_op_xor = F_op_opx & (F_iw_opx == 30);
assign F_op_mulxss = F_op_opx & (F_iw_opx == 31);
assign F_op_cmpeq = F_op_opx & (F_iw_opx == 32);
assign F_op_divu = F_op_opx & (F_iw_opx == 36);
assign F_op_div = F_op_opx & (F_iw_opx == 37);
assign F_op_rdctl = F_op_opx & (F_iw_opx == 38);
assign F_op_mul = F_op_opx & (F_iw_opx == 39);
assign F_op_cmpgeu = F_op_opx & (F_iw_opx == 40);
assign F_op_initi = F_op_opx & (F_iw_opx == 41);
assign F_op_trap = F_op_opx & (F_iw_opx == 45);
assign F_op_wrctl = F_op_opx & (F_iw_opx == 46);
assign F_op_cmpltu = F_op_opx & (F_iw_opx == 48);
assign F_op_add = F_op_opx & (F_iw_opx == 49);
assign F_op_break = F_op_opx & (F_iw_opx == 52);
assign F_op_hbreak = F_op_opx & (F_iw_opx == 53);
assign F_op_sync = F_op_opx & (F_iw_opx == 54);
assign F_op_sub = F_op_opx & (F_iw_opx == 57);
assign F_op_srai = F_op_opx & (F_iw_opx == 58);
assign F_op_sra = F_op_opx & (F_iw_opx == 59);
assign F_op_intr = F_op_opx & (F_iw_opx == 61);
assign F_op_crst = F_op_opx & (F_iw_opx == 62);
assign F_op_rsvx00 = F_op_opx & (F_iw_opx == 0);
assign F_op_rsvx10 = F_op_opx & (F_iw_opx == 10);
assign F_op_rsvx15 = F_op_opx & (F_iw_opx == 15);
assign F_op_rsvx17 = F_op_opx & (F_iw_opx == 17);
assign F_op_rsvx21 = F_op_opx & (F_iw_opx == 21);
assign F_op_rsvx25 = F_op_opx & (F_iw_opx == 25);
assign F_op_rsvx33 = F_op_opx & (F_iw_opx == 33);
assign F_op_rsvx34 = F_op_opx & (F_iw_opx == 34);
assign F_op_rsvx35 = F_op_opx & (F_iw_opx == 35);
assign F_op_rsvx42 = F_op_opx & (F_iw_opx == 42);
assign F_op_rsvx43 = F_op_opx & (F_iw_opx == 43);
assign F_op_rsvx44 = F_op_opx & (F_iw_opx == 44);
assign F_op_rsvx47 = F_op_opx & (F_iw_opx == 47);
assign F_op_rsvx50 = F_op_opx & (F_iw_opx == 50);
assign F_op_rsvx51 = F_op_opx & (F_iw_opx == 51);
assign F_op_rsvx55 = F_op_opx & (F_iw_opx == 55);
assign F_op_rsvx56 = F_op_opx & (F_iw_opx == 56);
assign F_op_rsvx60 = F_op_opx & (F_iw_opx == 60);
assign F_op_rsvx63 = F_op_opx & (F_iw_opx == 63);
assign F_op_opx = F_iw_op == 58;
assign F_op_custom = F_iw_op == 50;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_rsv02 = D_iw_op == 2;
assign D_op_rsv09 = D_iw_op == 9;
assign D_op_rsv10 = D_iw_op == 10;
assign D_op_rsv17 = D_iw_op == 17;
assign D_op_rsv18 = D_iw_op == 18;
assign D_op_rsv25 = D_iw_op == 25;
assign D_op_rsv26 = D_iw_op == 26;
assign D_op_rsv33 = D_iw_op == 33;
assign D_op_rsv34 = D_iw_op == 34;
assign D_op_rsv41 = D_iw_op == 41;
assign D_op_rsv42 = D_iw_op == 42;
assign D_op_rsv49 = D_iw_op == 49;
assign D_op_rsv57 = D_iw_op == 57;
assign D_op_rsv61 = D_iw_op == 61;
assign D_op_rsv62 = D_iw_op == 62;
assign D_op_rsv63 = D_iw_op == 63;
assign D_op_eret = D_op_opx & (D_iw_opx == 1);
assign D_op_roli = D_op_opx & (D_iw_opx == 2);
assign D_op_rol = D_op_opx & (D_iw_opx == 3);
assign D_op_flushp = D_op_opx & (D_iw_opx == 4);
assign D_op_ret = D_op_opx & (D_iw_opx == 5);
assign D_op_nor = D_op_opx & (D_iw_opx == 6);
assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7);
assign D_op_cmpge = D_op_opx & (D_iw_opx == 8);
assign D_op_bret = D_op_opx & (D_iw_opx == 9);
assign D_op_ror = D_op_opx & (D_iw_opx == 11);
assign D_op_flushi = D_op_opx & (D_iw_opx == 12);
assign D_op_jmp = D_op_opx & (D_iw_opx == 13);
assign D_op_and = D_op_opx & (D_iw_opx == 14);
assign D_op_cmplt = D_op_opx & (D_iw_opx == 16);
assign D_op_slli = D_op_opx & (D_iw_opx == 18);
assign D_op_sll = D_op_opx & (D_iw_opx == 19);
assign D_op_wrprs = D_op_opx & (D_iw_opx == 20);
assign D_op_or = D_op_opx & (D_iw_opx == 22);
assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23);
assign D_op_cmpne = D_op_opx & (D_iw_opx == 24);
assign D_op_srli = D_op_opx & (D_iw_opx == 26);
assign D_op_srl = D_op_opx & (D_iw_opx == 27);
assign D_op_nextpc = D_op_opx & (D_iw_opx == 28);
assign D_op_callr = D_op_opx & (D_iw_opx == 29);
assign D_op_xor = D_op_opx & (D_iw_opx == 30);
assign D_op_mulxss = D_op_opx & (D_iw_opx == 31);
assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32);
assign D_op_divu = D_op_opx & (D_iw_opx == 36);
assign D_op_div = D_op_opx & (D_iw_opx == 37);
assign D_op_rdctl = D_op_opx & (D_iw_opx == 38);
assign D_op_mul = D_op_opx & (D_iw_opx == 39);
assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40);
assign D_op_initi = D_op_opx & (D_iw_opx == 41);
assign D_op_trap = D_op_opx & (D_iw_opx == 45);
assign D_op_wrctl = D_op_opx & (D_iw_opx == 46);
assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48);
assign D_op_add = D_op_opx & (D_iw_opx == 49);
assign D_op_break = D_op_opx & (D_iw_opx == 52);
assign D_op_hbreak = D_op_opx & (D_iw_opx == 53);
assign D_op_sync = D_op_opx & (D_iw_opx == 54);
assign D_op_sub = D_op_opx & (D_iw_opx == 57);
assign D_op_srai = D_op_opx & (D_iw_opx == 58);
assign D_op_sra = D_op_opx & (D_iw_opx == 59);
assign D_op_intr = D_op_opx & (D_iw_opx == 61);
assign D_op_crst = D_op_opx & (D_iw_opx == 62);
assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0);
assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10);
assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15);
assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17);
assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21);
assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25);
assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33);
assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34);
assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35);
assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42);
assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43);
assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44);
assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47);
assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50);
assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51);
assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55);
assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56);
assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60);
assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63);
assign D_op_opx = D_iw_op == 58;
assign D_op_custom = D_iw_op == 50;
assign R_en = 1'b1;
assign E_ci_result = 0;
//custom_instruction_master, which is an e_custom_instruction_master
assign no_ci_readra = 1'b0;
assign E_ci_multi_stall = 1'b0;
assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000011111111;
assign F_pc_sel_nxt = R_ctrl_exception ? 2'b00 :
R_ctrl_break ? 2'b01 :
(W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 :
2'b11;
assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 8388616 :
(F_pc_sel_nxt == 2'b01)? 25166344 :
(F_pc_sel_nxt == 2'b10)? E_arith_result[26 : 2] :
F_pc_plus_one;
assign F_pc_nxt = F_pc_no_crst_nxt;
assign F_pcb_nxt = {F_pc_nxt, 2'b00};
assign F_pc_en = W_valid;
assign F_pc_plus_one = F_pc + 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
F_pc <= 8388608;
else if (F_pc_en)
F_pc <= F_pc_nxt;
end
assign F_pcb = {F_pc, 2'b00};
assign F_pcb_plus_four = {F_pc_plus_one, 2'b00};
assign F_valid = i_read & ~i_waitrequest;
assign i_read_nxt = W_valid | (i_read & i_waitrequest);
assign i_address = {F_pc, 2'b00};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
i_read <= 1'b1;
else
i_read <= i_read_nxt;
end
assign oci_tb_hbreak_req = oci_hbreak_req;
assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid);
assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled
: hbreak_req;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wait_for_one_post_bret_inst <= 1'b0;
else
wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_pending <= 1'b0;
else
hbreak_pending <= hbreak_pending_nxt;
end
assign intr_req = W_status_reg_pie & (W_ipending_reg != 0);
assign F_av_iw = i_readdata;
assign F_iw = hbreak_req ? 4040762 :
1'b0 ? 127034 :
intr_req ? 3926074 :
F_av_iw;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_iw <= 0;
else if (F_valid)
D_iw <= F_iw;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_valid <= 0;
else
D_valid <= F_valid;
end
assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 :
D_ctrl_implicit_dst_eretaddr ? 5'd29 :
D_ctrl_b_is_dst ? D_iw_b :
D_iw_c;
assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst;
assign D_logic_op_raw = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : D_logic_op_raw;
assign D_compare_op = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_jmp_direct_target_waddr = D_iw[31 : 6];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_valid <= 0;
else
R_valid <= D_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_wr_dst_reg <= 0;
else
R_wr_dst_reg <= D_wr_dst_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_dst_regnum <= 0;
else
R_dst_regnum <= D_dst_regnum;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_logic_op <= 0;
else
R_logic_op <= D_logic_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_compare_op <= 0;
else
R_compare_op <= D_compare_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_src2_use_imm <= 0;
else
R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid);
end
assign W_rf_wren = (R_wr_dst_reg & W_valid) | ~reset_n;
assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data;
//DE0_Nano_SOPC_cpu_register_bank_a, which is an nios_sdp_ram
DE0_Nano_SOPC_cpu_register_bank_a_module DE0_Nano_SOPC_cpu_register_bank_a
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_a),
.rdaddress (D_iw_a),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam DE0_Nano_SOPC_cpu_register_bank_a.lpm_file = "DE0_Nano_SOPC_cpu_rf_ram_a.dat";
`else
defparam DE0_Nano_SOPC_cpu_register_bank_a.lpm_file = "DE0_Nano_SOPC_cpu_rf_ram_a.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam DE0_Nano_SOPC_cpu_register_bank_a.lpm_file = "DE0_Nano_SOPC_cpu_rf_ram_a.mif";
//synthesis read_comments_as_HDL off
//DE0_Nano_SOPC_cpu_register_bank_b, which is an nios_sdp_ram
DE0_Nano_SOPC_cpu_register_bank_b_module DE0_Nano_SOPC_cpu_register_bank_b
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_b),
.rdaddress (D_iw_b),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam DE0_Nano_SOPC_cpu_register_bank_b.lpm_file = "DE0_Nano_SOPC_cpu_rf_ram_b.dat";
`else
defparam DE0_Nano_SOPC_cpu_register_bank_b.lpm_file = "DE0_Nano_SOPC_cpu_rf_ram_b.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam DE0_Nano_SOPC_cpu_register_bank_b.lpm_file = "DE0_Nano_SOPC_cpu_rf_ram_b.mif";
//synthesis read_comments_as_HDL off
assign R_src1 = (((R_ctrl_br & E_valid) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} :
((R_ctrl_jmp_direct & E_valid))? {D_jmp_direct_target_waddr, 2'b00} :
R_rf_a;
assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? 16'b0 :
(R_src2_use_imm)? D_iw_imm16 :
R_rf_b[15 : 0];
assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? 16'b0 :
(R_ctrl_hi_imm16)? D_iw_imm16 :
(R_src2_use_imm)? {16 {D_iw_imm16[15]}} :
R_rf_b[31 : 16];
assign R_src2 = {R_src2_hi, R_src2_lo};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_valid <= 0;
else
E_valid <= R_valid | E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_new_inst <= 0;
else
E_new_inst <= R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src1 <= 0;
else
E_src1 <= R_src1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src2 <= 0;
else
E_src2 <= R_src2;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_invert_arith_src_msb <= 0;
else
E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_alu_sub <= 0;
else
E_alu_sub <= D_ctrl_alu_subtract & R_valid;
end
assign E_stall = E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall;
assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb,
E_src1[30 : 0]};
assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb,
E_src2[30 : 0]};
assign E_arith_result = E_alu_sub ?
E_arith_src1 - E_arith_src2 :
E_arith_src1 + E_arith_src2;
assign E_mem_baddr = E_arith_result[26 : 0];
assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
(R_logic_op == 2'b01)? (E_src1 & E_src2) :
(R_logic_op == 2'b10)? (E_src1 | E_src2) :
(E_src1 ^ E_src2);
assign E_logic_result_is_0 = E_logic_result == 0;
assign E_eq = E_logic_result_is_0;
assign E_lt = E_arith_result[32];
assign E_cmp_result = (R_compare_op == 2'b00)? E_eq :
(R_compare_op == 2'b01)? ~E_lt :
(R_compare_op == 2'b10)? E_lt :
~E_eq;
assign E_shift_rot_cnt_nxt = E_new_inst ? E_src2[4 : 0] : E_shift_rot_cnt-1;
assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst;
assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done;
assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 :
(R_ctrl_rot_right ? E_shift_rot_result[0] :
E_shift_rot_result[31]);
assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 :
(R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} :
{E_shift_rot_result[30 : 0], E_shift_rot_fill_bit};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_result <= 0;
else
E_shift_rot_result <= E_shift_rot_result_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_cnt <= 0;
else
E_shift_rot_cnt <= E_shift_rot_cnt_nxt;
end
assign E_control_rd_data = (D_iw_control_regnum == 3'd0)? W_status_reg :
(D_iw_control_regnum == 3'd1)? W_estatus_reg :
(D_iw_control_regnum == 3'd2)? W_bstatus_reg :
(D_iw_control_regnum == 3'd3)? W_ienable_reg :
(D_iw_control_regnum == 3'd4)? W_ipending_reg :
W_cpuid_reg;
assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rdctl_inst))? 0 :
(R_ctrl_shift_rot)? E_shift_rot_result :
(R_ctrl_logic)? E_logic_result :
(R_ctrl_custom)? E_ci_result :
E_arith_result;
assign R_stb_data = R_rf_b[7 : 0];
assign R_sth_data = R_rf_b[15 : 0];
assign E_st_data = (D_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} :
(D_mem16)? {R_sth_data, R_sth_data} :
R_rf_b;
assign E_mem_byte_en = ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 :
4'b1111;
assign d_read_nxt = (R_ctrl_ld & E_new_inst) | (d_read & d_waitrequest);
assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst);
assign d_write_nxt = (R_ctrl_st & E_new_inst) | (d_write & d_waitrequest);
assign E_st_stall = d_write_nxt;
assign d_address = W_mem_baddr;
assign av_ld_getting_data = d_read & ~d_waitrequest;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_read <= 0;
else
d_read <= d_read_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_writedata <= 0;
else
d_writedata <= E_st_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_byteenable <= 0;
else
d_byteenable <= E_mem_byte_en;
end
assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1);
assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_mem16 ? 2 : 3);
assign av_ld_aligning_data_nxt = av_ld_aligning_data ?
~av_ld_align_one_more_cycle :
(~D_mem32 & av_ld_getting_data);
assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ?
~av_ld_getting_data :
(R_ctrl_ld & E_new_inst);
assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_mem32 | ~av_ld_aligning_data_nxt);
assign av_ld_rshift8 = av_ld_aligning_data &
(av_ld_align_cycle < (W_mem_baddr[1 : 0]));
assign av_ld_extend = av_ld_aligning_data;
assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data :
av_ld_extend ? av_ld_byte0_data :
d_readdata[7 : 0];
assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[15 : 8];
assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[23 : 16];
assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[31 : 24];
assign av_ld_byte1_data_en = ~(av_ld_extend & D_mem16 & ~av_ld_rshift8);
assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data,
av_ld_byte1_data, av_ld_byte0_data};
assign av_sign_bit = D_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7];
assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_align_cycle <= 0;
else
av_ld_align_cycle <= av_ld_align_cycle_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_waiting_for_data <= 0;
else
av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_aligning_data <= 0;
else
av_ld_aligning_data <= av_ld_aligning_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte0_data <= 0;
else
av_ld_byte0_data <= av_ld_byte0_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte1_data <= 0;
else if (av_ld_byte1_data_en)
av_ld_byte1_data <= av_ld_byte1_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte2_data <= 0;
else
av_ld_byte2_data <= av_ld_byte2_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte3_data <= 0;
else
av_ld_byte3_data <= av_ld_byte3_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid <= 0;
else
W_valid <= E_valid & ~E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_control_rd_data <= 0;
else
W_control_rd_data <= E_control_rd_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cmp_result <= 0;
else
W_cmp_result <= E_cmp_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_alu_result <= 0;
else
W_alu_result <= E_alu_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_status_reg_pie <= 0;
else
W_status_reg_pie <= W_status_reg_pie_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_estatus_reg <= 0;
else
W_estatus_reg <= W_estatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_bstatus_reg <= 0;
else
W_bstatus_reg <= W_bstatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ienable_reg <= 0;
else
W_ienable_reg <= W_ienable_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ipending_reg <= 0;
else
W_ipending_reg <= W_ipending_reg_nxt;
end
assign W_cpuid_reg = 0;
assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result :
R_ctrl_rdctl_inst ? W_control_rd_data :
W_alu_result[31 : 0];
assign W_wr_data = W_wr_data_non_zero;
assign W_br_taken = R_ctrl_br & W_cmp_result;
assign W_mem_baddr = W_alu_result[26 : 0];
assign W_status_reg = W_status_reg_pie;
assign E_wrctl_status = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd0);
assign E_wrctl_estatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd1);
assign E_wrctl_bstatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd2);
assign E_wrctl_ienable = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd3);
assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst) ? 1'b0 :
(D_op_eret) ? W_estatus_reg :
(D_op_bret) ? W_bstatus_reg :
(E_wrctl_status) ? E_src1[0] :
W_status_reg_pie;
assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie;
assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 :
(R_ctrl_exception) ? W_status_reg :
(E_wrctl_estatus) ? E_src1[0] :
W_estatus_reg;
assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg;
assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg :
(E_wrctl_bstatus) ? E_src1[0] :
W_bstatus_reg;
assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg;
assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ?
E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000011111111;
assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000011111111;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_enabled <= 1'b1;
else if (E_valid)
hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_write <= 0;
else
d_write <= d_write_nxt;
end
DE0_Nano_SOPC_cpu_nios2_oci the_DE0_Nano_SOPC_cpu_nios2_oci
(
.D_valid (D_valid),
.E_st_data (E_st_data),
.E_valid (E_valid),
.F_pc (F_pc),
.address_nxt (jtag_debug_module_address),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.byteenable_nxt (jtag_debug_module_byteenable),
.clk (jtag_debug_module_clk),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.debugaccess_nxt (jtag_debug_module_debugaccess),
.hbreak_enabled (hbreak_enabled),
.jtag_debug_module_debugaccess_to_roms (jtag_debug_module_debugaccess_to_roms),
.oci_hbreak_req (oci_hbreak_req),
.oci_ienable (oci_ienable),
.oci_single_step_mode (oci_single_step_mode),
.read_nxt (jtag_debug_module_read),
.readdata (jtag_debug_module_readdata),
.reset (jtag_debug_module_reset),
.reset_n (reset_n),
.reset_req (reset_req),
.resetrequest (jtag_debug_module_resetrequest),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.waitrequest (jtag_debug_module_waitrequest),
.write_nxt (jtag_debug_module_write),
.writedata_nxt (jtag_debug_module_writedata)
);
//jtag_debug_module, which is an e_avalon_slave
assign jtag_debug_module_clk = clk;
assign jtag_debug_module_reset = ~reset_n;
assign D_ctrl_custom = 1'b0;
assign R_ctrl_custom_nxt = D_ctrl_custom;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom <= 0;
else if (R_en)
R_ctrl_custom <= R_ctrl_custom_nxt;
end
assign D_ctrl_custom_multi = 1'b0;
assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom_multi <= 0;
else if (R_en)
R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt;
end
assign D_ctrl_jmp_indirect = D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_indirect <= 0;
else if (R_en)
R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt;
end
assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi;
assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_direct <= 0;
else if (R_en)
R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt;
end
assign D_ctrl_implicit_dst_retaddr = D_op_call|D_op_rsv02;
assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_retaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt;
end
assign D_ctrl_implicit_dst_eretaddr = D_op_div|D_op_divu|D_op_mul|D_op_muli|D_op_mulxss|D_op_mulxsu|D_op_mulxuu;
assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_eretaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt;
end
assign D_ctrl_exception = D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60;
assign R_ctrl_exception_nxt = D_ctrl_exception;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_exception <= 0;
else if (R_en)
R_ctrl_exception <= R_ctrl_exception_nxt;
end
assign D_ctrl_break = D_op_break|D_op_hbreak;
assign R_ctrl_break_nxt = D_ctrl_break;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_break <= 0;
else if (R_en)
R_ctrl_break <= R_ctrl_break_nxt;
end
assign D_ctrl_crst = D_op_crst|D_op_rsvx63;
assign R_ctrl_crst_nxt = D_ctrl_crst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_crst <= 0;
else if (R_en)
R_ctrl_crst <= R_ctrl_crst_nxt;
end
assign D_ctrl_uncond_cti_non_br = D_op_call|
D_op_jmpi|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_uncond_cti_non_br <= 0;
else if (R_en)
R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt;
end
assign D_ctrl_retaddr = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak;
assign R_ctrl_retaddr_nxt = D_ctrl_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_retaddr <= 0;
else if (R_en)
R_ctrl_retaddr <= R_ctrl_retaddr_nxt;
end
assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl;
assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_logical <= 0;
else if (R_en)
R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt;
end
assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra;
assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_right_arith <= 0;
else if (R_en)
R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt;
end
assign D_ctrl_rot_right = D_op_rsvx10|D_op_ror|D_op_rsvx42|D_op_rsvx43;
assign R_ctrl_rot_right_nxt = D_ctrl_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rot_right <= 0;
else if (R_en)
R_ctrl_rot_right <= R_ctrl_rot_right_nxt;
end
assign D_ctrl_shift_rot_right = D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot_right <= 0;
else if (R_en)
R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt;
end
assign D_ctrl_shift_rot = D_op_slli|
D_op_rsvx50|
D_op_sll|
D_op_rsvx51|
D_op_roli|
D_op_rsvx34|
D_op_rol|
D_op_rsvx35|
D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot <= 0;
else if (R_en)
R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt;
end
assign D_ctrl_logic = D_op_and|
D_op_or|
D_op_xor|
D_op_nor|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori;
assign R_ctrl_logic_nxt = D_ctrl_logic;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_logic <= 0;
else if (R_en)
R_ctrl_logic <= R_ctrl_logic_nxt;
end
assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi;
assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_hi_imm16 <= 0;
else if (R_en)
R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt;
end
assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui|
D_op_cmpltui|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_unsigned_lo_imm16 <= 0;
else if (R_en)
R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt;
end
assign D_ctrl_br_uncond = D_op_br|D_op_rsv02;
assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_uncond <= 0;
else if (R_en)
R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt;
end
assign D_ctrl_br = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62;
assign R_ctrl_br_nxt = D_ctrl_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br <= 0;
else if (R_en)
R_ctrl_br <= R_ctrl_br_nxt;
end
assign D_ctrl_alu_subtract = D_op_sub|
D_op_rsvx25|
D_op_cmplti|
D_op_cmpltui|
D_op_cmplt|
D_op_cmpltu|
D_op_blt|
D_op_bltu|
D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpge|
D_op_cmpgeu|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42;
assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_subtract <= 0;
else if (R_en)
R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt;
end
assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt;
assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_signed_comparison <= 0;
else if (R_en)
R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt;
end
assign D_ctrl_br_cmp = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_rsvx00|
D_op_cmpge|
D_op_cmplt|
D_op_cmpne|
D_op_cmpgeu|
D_op_cmpltu|
D_op_cmpeq|
D_op_rsvx56;
assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_cmp <= 0;
else if (R_en)
R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt;
end
assign D_ctrl_ld_signed = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63;
assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_signed <= 0;
else if (R_en)
R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt;
end
assign D_ctrl_ld = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio;
assign R_ctrl_ld_nxt = D_ctrl_ld;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld <= 0;
else if (R_en)
R_ctrl_ld <= R_ctrl_ld_nxt;
end
assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldl;
assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_non_io <= 0;
else if (R_en)
R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt;
end
assign D_ctrl_st = D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61;
assign R_ctrl_st_nxt = D_ctrl_st;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_st <= 0;
else if (R_en)
R_ctrl_st <= R_ctrl_st_nxt;
end
assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio|D_op_rsv63;
assign R_ctrl_ld_io_nxt = D_ctrl_ld_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_io <= 0;
else if (R_en)
R_ctrl_ld_io <= R_ctrl_ld_io_nxt;
end
assign D_ctrl_b_is_dst = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda;
assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_b_is_dst <= 0;
else if (R_en)
R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt;
end
assign D_ctrl_ignore_dst = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57;
assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ignore_dst <= 0;
else if (R_en)
R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt;
end
assign D_ctrl_src2_choose_imm = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_src2_choose_imm <= 0;
else if (R_en)
R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt;
end
assign D_ctrl_wrctl_inst = D_op_wrctl;
assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_wrctl_inst <= 0;
else if (R_en)
R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt;
end
assign D_ctrl_rdctl_inst = D_op_rdctl;
assign R_ctrl_rdctl_inst_nxt = D_ctrl_rdctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rdctl_inst <= 0;
else if (R_en)
R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt;
end
assign D_ctrl_force_src2_zero = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_jmpi;
assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_force_src2_zero <= 0;
else if (R_en)
R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt;
end
assign D_ctrl_alu_force_xor = D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpeqi|
D_op_cmpge|
D_op_cmpgeu|
D_op_cmpeq|
D_op_cmpnei|
D_op_cmpne|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42|
D_op_beq|
D_op_rsv34|
D_op_bne|
D_op_rsv62|
D_op_br|
D_op_rsv02;
assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_force_xor <= 0;
else if (R_en)
R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt;
end
//data_master, which is an e_avalon_master
//instruction_master, which is an e_avalon_master
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign F_inst = (F_op_call)? 56'h20202063616c6c :
(F_op_jmpi)? 56'h2020206a6d7069 :
(F_op_ldbu)? 56'h2020206c646275 :
(F_op_addi)? 56'h20202061646469 :
(F_op_stb)? 56'h20202020737462 :
(F_op_br)? 56'h20202020206272 :
(F_op_ldb)? 56'h202020206c6462 :
(F_op_cmpgei)? 56'h20636d70676569 :
(F_op_ldhu)? 56'h2020206c646875 :
(F_op_andi)? 56'h202020616e6469 :
(F_op_sth)? 56'h20202020737468 :
(F_op_bge)? 56'h20202020626765 :
(F_op_ldh)? 56'h202020206c6468 :
(F_op_cmplti)? 56'h20636d706c7469 :
(F_op_initda)? 56'h20696e69746461 :
(F_op_ori)? 56'h202020206f7269 :
(F_op_stw)? 56'h20202020737477 :
(F_op_blt)? 56'h20202020626c74 :
(F_op_ldw)? 56'h202020206c6477 :
(F_op_cmpnei)? 56'h20636d706e6569 :
(F_op_flushda)? 56'h666c7573686461 :
(F_op_xori)? 56'h202020786f7269 :
(F_op_bne)? 56'h20202020626e65 :
(F_op_cmpeqi)? 56'h20636d70657169 :
(F_op_ldbuio)? 56'h206c646275696f :
(F_op_muli)? 56'h2020206d756c69 :
(F_op_stbio)? 56'h2020737462696f :
(F_op_beq)? 56'h20202020626571 :
(F_op_ldbio)? 56'h20206c6462696f :
(F_op_cmpgeui)? 56'h636d7067657569 :
(F_op_ldhuio)? 56'h206c646875696f :
(F_op_andhi)? 56'h2020616e646869 :
(F_op_sthio)? 56'h2020737468696f :
(F_op_bgeu)? 56'h20202062676575 :
(F_op_ldhio)? 56'h20206c6468696f :
(F_op_cmpltui)? 56'h636d706c747569 :
(F_op_initd)? 56'h2020696e697464 :
(F_op_orhi)? 56'h2020206f726869 :
(F_op_stwio)? 56'h2020737477696f :
(F_op_bltu)? 56'h202020626c7475 :
(F_op_ldwio)? 56'h20206c6477696f :
(F_op_flushd)? 56'h20666c75736864 :
(F_op_xorhi)? 56'h2020786f726869 :
(F_op_eret)? 56'h20202065726574 :
(F_op_roli)? 56'h202020726f6c69 :
(F_op_rol)? 56'h20202020726f6c :
(F_op_flushp)? 56'h20666c75736870 :
(F_op_ret)? 56'h20202020726574 :
(F_op_nor)? 56'h202020206e6f72 :
(F_op_mulxuu)? 56'h206d756c787575 :
(F_op_cmpge)? 56'h2020636d706765 :
(F_op_bret)? 56'h20202062726574 :
(F_op_ror)? 56'h20202020726f72 :
(F_op_flushi)? 56'h20666c75736869 :
(F_op_jmp)? 56'h202020206a6d70 :
(F_op_and)? 56'h20202020616e64 :
(F_op_cmplt)? 56'h2020636d706c74 :
(F_op_slli)? 56'h202020736c6c69 :
(F_op_sll)? 56'h20202020736c6c :
(F_op_or)? 56'h20202020206f72 :
(F_op_mulxsu)? 56'h206d756c787375 :
(F_op_cmpne)? 56'h2020636d706e65 :
(F_op_srli)? 56'h20202073726c69 :
(F_op_srl)? 56'h2020202073726c :
(F_op_nextpc)? 56'h206e6578747063 :
(F_op_callr)? 56'h202063616c6c72 :
(F_op_xor)? 56'h20202020786f72 :
(F_op_mulxss)? 56'h206d756c787373 :
(F_op_cmpeq)? 56'h2020636d706571 :
(F_op_divu)? 56'h20202064697675 :
(F_op_div)? 56'h20202020646976 :
(F_op_rdctl)? 56'h2020726463746c :
(F_op_mul)? 56'h202020206d756c :
(F_op_cmpgeu)? 56'h20636d70676575 :
(F_op_initi)? 56'h2020696e697469 :
(F_op_trap)? 56'h20202074726170 :
(F_op_wrctl)? 56'h2020777263746c :
(F_op_cmpltu)? 56'h20636d706c7475 :
(F_op_add)? 56'h20202020616464 :
(F_op_break)? 56'h2020627265616b :
(F_op_hbreak)? 56'h2068627265616b :
(F_op_sync)? 56'h20202073796e63 :
(F_op_sub)? 56'h20202020737562 :
(F_op_srai)? 56'h20202073726169 :
(F_op_sra)? 56'h20202020737261 :
(F_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign D_inst = (D_op_call)? 56'h20202063616c6c :
(D_op_jmpi)? 56'h2020206a6d7069 :
(D_op_ldbu)? 56'h2020206c646275 :
(D_op_addi)? 56'h20202061646469 :
(D_op_stb)? 56'h20202020737462 :
(D_op_br)? 56'h20202020206272 :
(D_op_ldb)? 56'h202020206c6462 :
(D_op_cmpgei)? 56'h20636d70676569 :
(D_op_ldhu)? 56'h2020206c646875 :
(D_op_andi)? 56'h202020616e6469 :
(D_op_sth)? 56'h20202020737468 :
(D_op_bge)? 56'h20202020626765 :
(D_op_ldh)? 56'h202020206c6468 :
(D_op_cmplti)? 56'h20636d706c7469 :
(D_op_initda)? 56'h20696e69746461 :
(D_op_ori)? 56'h202020206f7269 :
(D_op_stw)? 56'h20202020737477 :
(D_op_blt)? 56'h20202020626c74 :
(D_op_ldw)? 56'h202020206c6477 :
(D_op_cmpnei)? 56'h20636d706e6569 :
(D_op_flushda)? 56'h666c7573686461 :
(D_op_xori)? 56'h202020786f7269 :
(D_op_bne)? 56'h20202020626e65 :
(D_op_cmpeqi)? 56'h20636d70657169 :
(D_op_ldbuio)? 56'h206c646275696f :
(D_op_muli)? 56'h2020206d756c69 :
(D_op_stbio)? 56'h2020737462696f :
(D_op_beq)? 56'h20202020626571 :
(D_op_ldbio)? 56'h20206c6462696f :
(D_op_cmpgeui)? 56'h636d7067657569 :
(D_op_ldhuio)? 56'h206c646875696f :
(D_op_andhi)? 56'h2020616e646869 :
(D_op_sthio)? 56'h2020737468696f :
(D_op_bgeu)? 56'h20202062676575 :
(D_op_ldhio)? 56'h20206c6468696f :
(D_op_cmpltui)? 56'h636d706c747569 :
(D_op_initd)? 56'h2020696e697464 :
(D_op_orhi)? 56'h2020206f726869 :
(D_op_stwio)? 56'h2020737477696f :
(D_op_bltu)? 56'h202020626c7475 :
(D_op_ldwio)? 56'h20206c6477696f :
(D_op_flushd)? 56'h20666c75736864 :
(D_op_xorhi)? 56'h2020786f726869 :
(D_op_eret)? 56'h20202065726574 :
(D_op_roli)? 56'h202020726f6c69 :
(D_op_rol)? 56'h20202020726f6c :
(D_op_flushp)? 56'h20666c75736870 :
(D_op_ret)? 56'h20202020726574 :
(D_op_nor)? 56'h202020206e6f72 :
(D_op_mulxuu)? 56'h206d756c787575 :
(D_op_cmpge)? 56'h2020636d706765 :
(D_op_bret)? 56'h20202062726574 :
(D_op_ror)? 56'h20202020726f72 :
(D_op_flushi)? 56'h20666c75736869 :
(D_op_jmp)? 56'h202020206a6d70 :
(D_op_and)? 56'h20202020616e64 :
(D_op_cmplt)? 56'h2020636d706c74 :
(D_op_slli)? 56'h202020736c6c69 :
(D_op_sll)? 56'h20202020736c6c :
(D_op_or)? 56'h20202020206f72 :
(D_op_mulxsu)? 56'h206d756c787375 :
(D_op_cmpne)? 56'h2020636d706e65 :
(D_op_srli)? 56'h20202073726c69 :
(D_op_srl)? 56'h2020202073726c :
(D_op_nextpc)? 56'h206e6578747063 :
(D_op_callr)? 56'h202063616c6c72 :
(D_op_xor)? 56'h20202020786f72 :
(D_op_mulxss)? 56'h206d756c787373 :
(D_op_cmpeq)? 56'h2020636d706571 :
(D_op_divu)? 56'h20202064697675 :
(D_op_div)? 56'h20202020646976 :
(D_op_rdctl)? 56'h2020726463746c :
(D_op_mul)? 56'h202020206d756c :
(D_op_cmpgeu)? 56'h20636d70676575 :
(D_op_initi)? 56'h2020696e697469 :
(D_op_trap)? 56'h20202074726170 :
(D_op_wrctl)? 56'h2020777263746c :
(D_op_cmpltu)? 56'h20636d706c7475 :
(D_op_add)? 56'h20202020616464 :
(D_op_break)? 56'h2020627265616b :
(D_op_hbreak)? 56'h2068627265616b :
(D_op_sync)? 56'h20202073796e63 :
(D_op_sub)? 56'h20202020737562 :
(D_op_srai)? 56'h20202073726169 :
(D_op_sra)? 56'h20202020737261 :
(D_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign F_vinst = F_valid ? F_inst : {7{8'h2d}};
assign D_vinst = D_valid ? D_inst : {7{8'h2d}};
assign R_vinst = R_valid ? D_inst : {7{8'h2d}};
assign E_vinst = E_valid ? D_inst : {7{8'h2d}};
assign W_vinst = W_valid ? D_inst : {7{8'h2d}};
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
//name : file_writer
//tag : c components
//input : input_a:16
//source_file : file_writer.c
///===========
///
///*Created by C2CHIP*
`timescale 1ns/1ps
module file_writer(input_a,input_a_stb,clk,rst,input_a_ack);
integer file_count;
integer output_file_0;
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
reg s_input_a_ack;
reg state;
reg [31:0] value;
initial
begin
output_file_0 = $fopen("resp_z");
$fclose(output_file_0);
end
always @(posedge clk)
begin
case(state)
0:
begin
s_input_a_ack <= 1'b1;
if (s_input_a_ack && input_a_stb) begin
value <= input_a;
s_input_a_ack <= 1'b0;
state <= 1;
end
end
1:
begin
output_file_0 = $fopena("resp_z");
$fdisplay(output_file_0, "%d", value);
$fclose(output_file_0);
state <= 0;
end
endcase
if (rst == 1'b1) begin
state <= 0;
s_input_a_ack <= 0;
end
end
assign input_a_ack = s_input_a_ack;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2B_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__NOR2B_PP_SYMBOL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nor2b (
//# {{data|Data Signals}}
input A ,
input B_N ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2B_PP_SYMBOL_V
|
/******************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: Data MMU implementation
Copyright (C) 2013 Stefan Kristiansson <[email protected]>
******************************************************************************/
`include "mor1kx-defines.v"
module mor1kx_dmmu
#(
parameter FEATURE_DMMU_HW_TLB_RELOAD = "NONE",
parameter OPTION_OPERAND_WIDTH = 32,
parameter OPTION_DMMU_SET_WIDTH = 6,
parameter OPTION_DMMU_WAYS = 1
)
(
input clk,
input rst,
input enable_i,
input [OPTION_OPERAND_WIDTH-1:0] virt_addr_i,
input [OPTION_OPERAND_WIDTH-1:0] virt_addr_match_i,
output reg [OPTION_OPERAND_WIDTH-1:0] phys_addr_o,
output reg cache_inhibit_o,
input op_store_i,
input op_load_i,
input supervisor_mode_i,
output reg tlb_miss_o,
output pagefault_o,
output reg tlb_reload_req_o,
output tlb_reload_busy_o,
input tlb_reload_ack_i,
output reg [OPTION_OPERAND_WIDTH-1:0] tlb_reload_addr_o,
input [OPTION_OPERAND_WIDTH-1:0] tlb_reload_data_i,
output tlb_reload_pagefault_o,
input tlb_reload_pagefault_clear_i,
// SPR interface
input [15:0] spr_bus_addr_i,
input spr_bus_we_i,
input spr_bus_stb_i,
input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_i,
output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o,
output spr_bus_ack_o
);
wire [OPTION_OPERAND_WIDTH-1:0] dtlb_match_dout[OPTION_DMMU_WAYS-1:0];
wire [OPTION_DMMU_SET_WIDTH-1:0] dtlb_match_addr;
reg [OPTION_DMMU_WAYS-1:0] dtlb_match_we;
wire [OPTION_OPERAND_WIDTH-1:0] dtlb_match_din;
wire [OPTION_OPERAND_WIDTH-1:0] dtlb_match_huge_dout[OPTION_DMMU_WAYS-1:0];
wire [OPTION_DMMU_SET_WIDTH-1:0] dtlb_match_huge_addr;
wire dtlb_match_huge_we;
wire [OPTION_OPERAND_WIDTH-1:0] dtlb_trans_dout[OPTION_DMMU_WAYS-1:0];
wire [OPTION_DMMU_SET_WIDTH-1:0] dtlb_trans_addr;
reg [OPTION_DMMU_WAYS-1:0] dtlb_trans_we;
wire [OPTION_OPERAND_WIDTH-1:0] dtlb_trans_din;
wire [OPTION_OPERAND_WIDTH-1:0] dtlb_trans_huge_dout[OPTION_DMMU_WAYS-1:0];
wire [OPTION_DMMU_SET_WIDTH-1:0] dtlb_trans_huge_addr;
wire dtlb_trans_huge_we;
reg dtlb_match_reload_we;
reg [OPTION_OPERAND_WIDTH-1:0] dtlb_match_reload_din;
reg dtlb_trans_reload_we;
reg [OPTION_OPERAND_WIDTH-1:0] dtlb_trans_reload_din;
wire dtlb_match_spr_cs;
reg dtlb_match_spr_cs_r;
wire dtlb_trans_spr_cs;
reg dtlb_trans_spr_cs_r;
wire dmmucr_spr_cs;
reg dmmucr_spr_cs_r;
reg [OPTION_OPERAND_WIDTH-1:0] dmmucr;
wire [1:0] spr_way_idx;
reg [1:0] spr_way_idx_r;
wire [OPTION_DMMU_WAYS-1:0] way_huge;
wire [OPTION_DMMU_WAYS-1:0] way_hit;
wire [OPTION_DMMU_WAYS-1:0] way_huge_hit;
reg tlb_reload_pagefault;
reg tlb_reload_huge;
// ure: user read enable
// uwe: user write enable
// sre: supervisor read enable
// swe: supervisor write enable
reg ure;
reg uwe;
reg sre;
reg swe;
reg spr_bus_ack;
genvar i;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
spr_bus_ack <= 0;
else if (spr_bus_stb_i & spr_bus_addr_i[15:11] == 5'd1)
spr_bus_ack <= 1;
else
spr_bus_ack <= 0;
assign spr_bus_ack_o = spr_bus_ack & spr_bus_stb_i &
spr_bus_addr_i[15:11] == 5'd1;
generate
for (i = 0; i < OPTION_DMMU_WAYS; i=i+1) begin : ways
assign way_huge[i] = &dtlb_match_huge_dout[i][1:0]; // huge & valid
assign way_hit[i] = (dtlb_match_dout[i][31:13] == virt_addr_match_i[31:13]) &
dtlb_match_dout[i][0]; // valid bit
assign way_huge_hit[i] = (dtlb_match_huge_dout[i][31:24] ==
virt_addr_match_i[31:24]) &
dtlb_match_huge_dout[i][0];
end
endgenerate
integer j;
always @(*) begin
tlb_miss_o = !tlb_reload_pagefault;
phys_addr_o = virt_addr_match_i[23:0];
ure = 0;
uwe = 0;
sre = 0;
swe = 0;
cache_inhibit_o = 0;
for (j = 0; j < OPTION_DMMU_WAYS; j=j+1) begin
if (way_huge[j] & way_huge_hit[j] | !way_huge[j] & way_hit[j])
tlb_miss_o = 0;
if (way_huge[j] & way_huge_hit[j]) begin
phys_addr_o = {dtlb_trans_huge_dout[j][31:24], virt_addr_match_i[23:0]};
ure = dtlb_trans_huge_dout[j][6];
uwe = dtlb_trans_huge_dout[j][7];
sre = dtlb_trans_huge_dout[j][8];
swe = dtlb_trans_huge_dout[j][9];
cache_inhibit_o = dtlb_trans_huge_dout[j][1];
end else if (!way_huge[j] & way_hit[j])begin
phys_addr_o = {dtlb_trans_dout[j][31:13], virt_addr_match_i[12:0]};
ure = dtlb_trans_dout[j][6];
uwe = dtlb_trans_dout[j][7];
sre = dtlb_trans_dout[j][8];
swe = dtlb_trans_dout[j][9];
cache_inhibit_o = dtlb_trans_dout[j][1];
end
dtlb_match_we[j] = 0;
if (dtlb_match_reload_we)
dtlb_match_we[j] = 1;
if (j == spr_way_idx)
dtlb_match_we[j] = dtlb_match_spr_cs & spr_bus_we_i;
dtlb_trans_we[j] = 0;
if (dtlb_trans_reload_we)
dtlb_trans_we[j] = 1;
if (j == spr_way_idx)
dtlb_trans_we[j] = dtlb_trans_spr_cs & spr_bus_we_i;
end
end
assign pagefault_o = (supervisor_mode_i ?
!swe & op_store_i || !sre & op_load_i :
!uwe & op_store_i || !ure & op_load_i) &
!tlb_reload_busy_o;
assign spr_way_idx = {spr_bus_addr_i[10], spr_bus_addr_i[8]};
always @(posedge clk `OR_ASYNC_RST)
if (rst) begin
dtlb_match_spr_cs_r <= 0;
dtlb_trans_spr_cs_r <= 0;
dmmucr_spr_cs_r <= 0;
spr_way_idx_r <= 0;
end else begin
dtlb_match_spr_cs_r <= dtlb_match_spr_cs;
dtlb_trans_spr_cs_r <= dtlb_trans_spr_cs;
dmmucr_spr_cs_r <= dmmucr_spr_cs;
spr_way_idx_r <= spr_way_idx;
end
generate /* verilator lint_off WIDTH */
if (FEATURE_DMMU_HW_TLB_RELOAD == "ENABLED") begin
/* verilator lint_on WIDTH */
assign dmmucr_spr_cs = spr_bus_stb_i &
spr_bus_addr_i == `OR1K_SPR_DMMUCR_ADDR;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
dmmucr <= 0;
else if (dmmucr_spr_cs & spr_bus_we_i)
dmmucr <= spr_bus_dat_i;
end else begin
assign dmmucr_spr_cs = 0;
always @(posedge clk)
dmmucr <= 0;
end
endgenerate
assign dtlb_match_spr_cs = spr_bus_stb_i & (spr_bus_addr_i[15:11] == 5'd1) &
|spr_bus_addr_i[10:9] & !spr_bus_addr_i[7];
assign dtlb_trans_spr_cs = spr_bus_stb_i & (spr_bus_addr_i[15:11] == 5'd1) &
|spr_bus_addr_i[10:9] & spr_bus_addr_i[7];
assign dtlb_match_addr = dtlb_match_spr_cs ?
spr_bus_addr_i[OPTION_DMMU_SET_WIDTH-1:0] :
virt_addr_i[13+(OPTION_DMMU_SET_WIDTH-1):13];
assign dtlb_trans_addr = dtlb_trans_spr_cs ?
spr_bus_addr_i[OPTION_DMMU_SET_WIDTH-1:0] :
virt_addr_i[13+(OPTION_DMMU_SET_WIDTH-1):13];
assign dtlb_match_din = dtlb_match_reload_we ? dtlb_match_reload_din :
spr_bus_dat_i;
assign dtlb_trans_din = dtlb_trans_reload_we ? dtlb_trans_reload_din :
spr_bus_dat_i;
assign dtlb_match_huge_addr = virt_addr_i[24+(OPTION_DMMU_SET_WIDTH-1):24];
assign dtlb_trans_huge_addr = virt_addr_i[24+(OPTION_DMMU_SET_WIDTH-1):24];
assign dtlb_match_huge_we = dtlb_match_reload_we & tlb_reload_huge;
assign dtlb_trans_huge_we = dtlb_trans_reload_we & tlb_reload_huge;
assign spr_bus_dat_o = dtlb_match_spr_cs_r ? dtlb_match_dout[spr_way_idx_r] :
dtlb_trans_spr_cs_r ? dtlb_trans_dout[spr_way_idx_r] :
dmmucr_spr_cs_r ? dmmucr : 0;
localparam TLB_IDLE = 2'd0;
localparam TLB_GET_PTE_POINTER = 2'd1;
localparam TLB_GET_PTE = 2'd2;
localparam TLB_READ = 2'd3;
generate /* verilator lint_off WIDTH */
if (FEATURE_DMMU_HW_TLB_RELOAD == "ENABLED") begin
/* verilator lint_on WIDTH */
// Hardware TLB reload
// Compliant with the suggestion outlined in this thread:
// http://lists.openrisc.net/pipermail/openrisc/2013-July/001806.html
//
// PTE layout:
// | 31 ... 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
// | PPN | Reserved |PRESENT| L | X | W | U | D | A |WOM|WBC|CI |CC |
//
// Where X/W/U maps into SWE/SRE/UWE/URE like this:
// X | W | U SWE | SRE | UWE | URE
// ---------- ---------------------
// x | 0 | 0 = 0 | 1 | 0 | 0
// x | 0 | 1 = 0 | 1 | 0 | 1
// x | 1 | 0 = 1 | 1 | 0 | 0
// x | 1 | 1 = 1 | 1 | 1 | 1
reg [1:0] tlb_reload_state = TLB_IDLE;
wire do_reload;
assign do_reload = enable_i & tlb_miss_o & (dmmucr[31:10] != 0) &
(op_load_i | op_store_i);
assign tlb_reload_busy_o = enable_i & (tlb_reload_state != TLB_IDLE) | do_reload;
assign tlb_reload_pagefault_o = tlb_reload_pagefault &
!tlb_reload_pagefault_clear_i;
always @(posedge clk) begin
if (tlb_reload_pagefault_clear_i)
tlb_reload_pagefault <= 0;
dtlb_trans_reload_we <= 0;
dtlb_trans_reload_din <= 0;
dtlb_match_reload_we <= 0;
dtlb_match_reload_din <= 0;
case (tlb_reload_state)
TLB_IDLE: begin
tlb_reload_huge <= 0;
tlb_reload_req_o <= 0;
if (do_reload) begin
tlb_reload_req_o <= 1;
tlb_reload_addr_o <= {dmmucr[31:10],
virt_addr_match_i[31:24], 2'b00};
tlb_reload_state <= TLB_GET_PTE_POINTER;
end
end
//
// Here we get the pointer to the PTE table, next is to fetch
// the actual pte from the offset in the table.
// The offset is calculated by:
// ((virt_addr_match >> PAGE_BITS) & (PTE_CNT-1)) << 2
// Where PAGE_BITS is 13 (8 kb page) and PTE_CNT is 2048
// (number of PTEs in the PTE table)
//
TLB_GET_PTE_POINTER: begin
tlb_reload_huge <= 0;
if (tlb_reload_ack_i) begin
if (tlb_reload_data_i[31:13] == 0) begin
tlb_reload_pagefault <= 1;
tlb_reload_req_o <= 0;
tlb_reload_state <= TLB_IDLE;
end else if (tlb_reload_data_i[9]) begin
tlb_reload_huge <= 1;
tlb_reload_req_o <= 0;
tlb_reload_state <= TLB_GET_PTE;
end else begin
tlb_reload_addr_o <= {tlb_reload_data_i[31:13],
virt_addr_match_i[23:13], 2'b00};
tlb_reload_state <= TLB_GET_PTE;
end
end
end
//
// Here we get the actual PTE, left to do is to translate the
// PTE data into our translate and match registers.
//
TLB_GET_PTE: begin
if (tlb_reload_ack_i) begin
tlb_reload_req_o <= 0;
// Check PRESENT bit
if (!tlb_reload_data_i[10]) begin
tlb_reload_pagefault <= 1;
tlb_reload_state <= TLB_IDLE;
end else begin
// Translate register generation.
// PPN
dtlb_trans_reload_din[31:13] <= tlb_reload_data_i[31:13];
// SWE = W
dtlb_trans_reload_din[9] <= tlb_reload_data_i[7];
// SRE = 1
dtlb_trans_reload_din[8] <= 1'b1;
// UWE = W & U
dtlb_trans_reload_din[7] <= tlb_reload_data_i[7] &
tlb_reload_data_i[6];
// URE = U
dtlb_trans_reload_din[6] <= tlb_reload_data_i[6];
// Dirty, Accessed, Weakly-Ordered-Memory, Writeback cache,
// Cache inhibit, Cache coherent
dtlb_trans_reload_din[5:0] <= tlb_reload_data_i[5:0];
dtlb_trans_reload_we <= 1;
// Match register generation.
// VPN
dtlb_match_reload_din[31:13] <= virt_addr_match_i[31:13];
// Valid
dtlb_match_reload_din[0] <= 1;
dtlb_match_reload_we <= 1;
tlb_reload_state <= TLB_READ;
end
end
end
// Let the just written values propagate out on the read ports
TLB_READ: begin
tlb_reload_state <= TLB_IDLE;
end
default:
tlb_reload_state <= TLB_IDLE;
endcase
// Abort if enable deasserts in the middle of a reload
if (!enable_i | (dmmucr[31:10] == 0))
tlb_reload_state <= TLB_IDLE;
end
end else begin // if (FEATURE_DMMU_HW_TLB_RELOAD == "ENABLED")
assign tlb_reload_pagefault_o = 0;
assign tlb_reload_busy_o = 0;
always @(posedge clk) begin
tlb_reload_req_o <= 0;
tlb_reload_addr_o <= 0;
tlb_reload_pagefault <= 0;
dtlb_trans_reload_we <= 0;
dtlb_trans_reload_din <= 0;
dtlb_match_reload_we <= 0;
dtlb_match_reload_din <= 0;
end
end
endgenerate
generate
for (i = 0; i < OPTION_DMMU_WAYS; i=i+1) begin : dtlb
// DTLB match registers
mor1kx_true_dpram_sclk
#(
.ADDR_WIDTH(OPTION_DMMU_SET_WIDTH),
.DATA_WIDTH(OPTION_OPERAND_WIDTH)
)
dtlb_match_regs
(
// Outputs
.dout_a (dtlb_match_dout[i]),
.dout_b (dtlb_match_huge_dout[i]),
// Inputs
.clk (clk),
.addr_a (dtlb_match_addr),
.we_a (dtlb_match_we[i]),
.din_a (dtlb_match_din),
.addr_b (dtlb_match_huge_addr),
.we_b (dtlb_match_huge_we),
.din_b (dtlb_match_reload_din)
);
// DTLB translate registers
mor1kx_true_dpram_sclk
#(
.ADDR_WIDTH(OPTION_DMMU_SET_WIDTH),
.DATA_WIDTH(OPTION_OPERAND_WIDTH)
)
dtlb_translate_regs
(
// Outputs
.dout_a (dtlb_trans_dout[i]),
.dout_b (dtlb_trans_huge_dout[i]),
// Inputs
.clk (clk),
.addr_a (dtlb_trans_addr),
.we_a (dtlb_trans_we[i]),
.din_a (dtlb_trans_din),
.addr_b (dtlb_trans_huge_addr),
.we_b (dtlb_trans_huge_we),
.din_b (dtlb_trans_reload_din)
);
end
endgenerate
endmodule // mor1kx_dmmu
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module ANN_ST_WandB_ram (addr0, ce0, d0, we0, q0, clk);
parameter DWIDTH = 32;
parameter AWIDTH = 13;
parameter MEM_SIZE = 6560;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./ANN_ST_WandB_ram.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module ANN_ST_WandB(
reset,
clk,
address0,
ce0,
we0,
d0,
q0);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd6560;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
ANN_ST_WandB_ram ANN_ST_WandB_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ));
endmodule
|
// DESCRIPTION: Verilator: Dedupe optimization test.
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// Contributed 2012 by Varun Koyyalagunta, Centaur Technology.
module t(res,d,clk,en);
output res;
input d,en,clk;
wire q0,q1,q2,q3;
flop_gated_latch f0(q0,d,clk,en);
flop_gated_latch f1(q1,d,clk,en);
flop_gated_flop f2(q2,d,clk,en);
flop_gated_flop f3(q3,d,clk,en);
assign res = (q0 + q1) * (q2 - q3);
endmodule
module flop_gated_latch(q,d,clk,en);
input d, clk, en;
output q;
wire gated_clock;
clock_gate_latch clock_gate(gated_clock, clk, en);
always @(posedge gated_clock) begin
q <= d;
end
endmodule
module flop_gated_flop(q,d,clk,en);
input d, clk, en;
output q;
wire gated_clock;
clock_gate_flop clock_gate(gated_clock, clk, en);
always @(posedge gated_clock) begin
q <= d;
end
endmodule
module clock_gate_latch (gated_clk, clk, clken);
output gated_clk;
input clk, clken;
reg clken_latched /*verilator clock_enable*/;
assign gated_clk = clk & clken_latched ;
wire clkb = ~clk;
always @(clkb or clken)
if(clkb) clken_latched = clken;
endmodule
module clock_gate_flop (gated_clk, clk, clken);
output gated_clk;
input clk, clken;
reg clken_r /*verilator clock_enable*/;
assign gated_clk = clk & clken_r ;
always @(negedge clk)
clken_r <= clken;
endmodule
|
module multiple_blocking_gate (clk, ctrl, din, sel, dout);
input clk;
input [4:0] ctrl;
input [1:0] din;
input [0:0] sel;
output reg [31:0] dout;
reg [5:0] a;
reg [0:0] b;
reg [2:0] c;
always @(posedge clk)
begin
a = (ctrl)+(1);
b = (sel)-(1);
c = ~(din);
dout = (dout)+(1);
case (({(a)*(b)})+(0))
0:
dout[31:0] = c;
1:
dout[31:1] = c;
2:
dout[31:2] = c;
3:
dout[31:3] = c;
4:
dout[31:4] = c;
5:
dout[31:5] = c;
6:
dout[31:6] = c;
7:
dout[31:7] = c;
8:
dout[31:8] = c;
9:
dout[31:9] = c;
10:
dout[31:10] = c;
11:
dout[31:11] = c;
12:
dout[31:12] = c;
13:
dout[31:13] = c;
14:
dout[31:14] = c;
15:
dout[31:15] = c;
16:
dout[31:16] = c;
17:
dout[31:17] = c;
18:
dout[31:18] = c;
19:
dout[31:19] = c;
20:
dout[31:20] = c;
21:
dout[31:21] = c;
22:
dout[31:22] = c;
23:
dout[31:23] = c;
24:
dout[31:24] = c;
25:
dout[31:25] = c;
26:
dout[31:26] = c;
27:
dout[31:27] = c;
28:
dout[31:28] = c;
29:
dout[31:29] = c;
30:
dout[31:30] = c;
31:
dout[31:31] = c;
endcase
end
endmodule
|
module usb_phy_ispd (
phy_tx_mode,
DataOut_i_3_,
tau_clk,
DataOut_i_1_,
DataOut_i_7_,
DataOut_i_5_,
rxd,
rst,
TxValid_i,
rxdp,
rxdn,
DataOut_i_2_,
DataOut_i_0_,
DataOut_i_4_,
DataOut_i_6_,
DataIn_o_2_,
txdn,
txdp,
LineState_o_0_,
RxValid_o,
txoe,
LineState_o_1_,
DataIn_o_7_,
DataIn_o_4_,
usb_rst,
DataIn_o_5_,
DataIn_o_3_,
RxError_o,
g1897_u0_o,
DataIn_o_1_,
TxReady_o,
DataIn_o_0_,
RxActive_o,
DataIn_o_6_);
// Start PIs
input phy_tx_mode;
input DataOut_i_3_;
input tau_clk;
input DataOut_i_1_;
input DataOut_i_7_;
input DataOut_i_5_;
input rxd;
input rst;
input TxValid_i;
input rxdp;
input rxdn;
input DataOut_i_2_;
input DataOut_i_0_;
input DataOut_i_4_;
input DataOut_i_6_;
// Start POs
output DataIn_o_2_;
output txdn;
output txdp;
output LineState_o_0_;
output RxValid_o;
output txoe;
output LineState_o_1_;
output DataIn_o_7_;
output DataIn_o_4_;
output usb_rst;
output DataIn_o_5_;
output DataIn_o_3_;
output RxError_o;
output g1897_u0_o;
output DataIn_o_1_;
output TxReady_o;
output DataIn_o_0_;
output RxActive_o;
output DataIn_o_6_;
// Start wires
wire newNet_120;
wire newNet_199;
wire n_707;
wire newNet_235;
wire newNet_110;
wire n_479;
wire g1778_db;
wire newNet_10;
wire n_990;
wire n_960;
wire i_tx_phy_bit_cnt_2_;
wire newNet_166;
wire newNet_130;
wire n_959;
wire n_980;
wire newNet_24;
wire i_tx_phy_sd_raw_o;
wire n_297;
wire newNet_79;
wire n_192;
wire i_tx_phy_hold_reg_d_11;
wire n_210;
wire newNet_117;
wire newNet_73;
wire newNet_63;
wire n_184;
wire n_61;
wire g2068_p;
wire n_232;
wire n_362;
wire newNet_193;
wire i_tx_phy_txoe_r1;
wire newNet_2;
wire newNet_25;
wire newNet_247;
wire n_331;
wire n_341;
wire n_509;
wire g1980_p;
wire i_rx_phy_bit_cnt_2_;
wire n_484;
wire g1741_p;
wire newNet_38;
wire n_353;
wire n_737;
wire newNet_292;
wire n_157;
wire g2050_p;
wire n_701;
wire n_749;
wire newNet_124;
wire i_rx_phy_dpll_state_1_;
wire newNet_149;
wire newNet_101;
wire n_125;
wire newNet_83;
wire i_tx_phy_one_cnt_2_;
wire n_323;
wire n_410;
wire newNet_189;
wire newNet_160;
wire newNet_113;
wire newNet_53;
wire n_274;
wire g1965_p;
wire n_256;
wire n_977;
wire g2108_p;
wire newNet_272;
wire n_373;
wire n_395;
wire n_318;
wire newNet_92;
wire newNet_19;
wire i_rx_phy_bit_stuff_err_reg_Q;
wire n_763;
wire n_233;
wire newNet_26;
wire FE_RN_0_0;
wire n_53;
wire newNet_297;
wire n_426;
wire newNet_46;
wire n_227;
wire n_404;
wire n_507;
wire n_629;
wire newNet_214;
wire newNet_279;
wire newNet_183;
wire newNet_201;
wire n_223;
wire newNet_157;
wire newNet_286;
wire newNet_139;
wire newNet_140;
wire newNet_256;
wire newNet_174;
wire n_231;
wire newNet_277;
wire n_332;
wire n_391;
wire newNet_99;
wire n_165;
wire n_947;
wire newNet_237;
wire i_rx_phy_one_cnt_0_;
wire n_435;
wire newNet_108;
wire g1778_da;
wire newNet_150;
wire n_937;
wire newNet_309;
wire newNet_220;
wire newNet_269;
wire newNet_268;
wire n_974;
wire newNet_226;
wire n_511;
wire RxActive_o;
wire i_rx_phy_rxd_s0;
wire g1742_p;
wire n_37;
wire n_290;
wire n_154;
wire n_300;
wire n_97;
wire rxd;
wire newNet_119;
wire g1757_p;
wire newNet_3;
wire n_958;
wire newNet_158;
wire i_rx_phy_bit_cnt_0_;
wire n_324;
wire newNet_244;
wire g1777_db;
wire n_486;
wire n_127;
wire n_141;
wire n_800;
wire newNet_234;
wire newNet_313;
wire newNet_261;
wire n_361;
wire n_748;
wire TxReady_o;
wire n_115;
wire n_70;
wire n_126;
wire newNet_188;
wire n_183;
wire n_665;
wire newNet_8;
wire newNet_29;
wire n_246;
wire n_170;
wire newNet_257;
wire newNet_116;
wire g2413_p;
wire newNet_51;
wire newNet_5;
wire n_427;
wire i_rx_phy_shift_en;
wire g1780_db;
wire n_360;
wire n_366;
wire n_447;
wire n_359;
wire newNet_74;
wire newNet_23;
wire newNet_260;
wire g2113_p;
wire n_485;
wire n_450;
wire newNet_47;
wire n_884;
wire n_222;
wire newNet_228;
wire n_796;
wire newNet_41;
wire n_991;
wire n_434;
wire n_506;
wire n_52;
wire n_166;
wire n_195;
wire n_405;
wire g1782_sb;
wire n_424;
wire newNet_271;
wire newNet_66;
wire n_273;
wire newNet_207;
wire newNet_121;
wire n_258;
wire newNet_109;
wire n_77;
wire newNet_255;
wire newNet_0;
wire n_944;
wire g2506_p;
wire newNet_50;
wire n_920;
wire g1975_p;
wire newNet_56;
wire newNet_112;
wire n_152;
wire newNet_169;
wire newNet_138;
wire i_tx_phy_hold_reg_10;
wire newNet_293;
wire n_894;
wire n_919;
wire newNet_137;
wire g2067_p;
wire n_406;
wire newNet_204;
wire n_727;
wire n_266;
wire n_976;
wire n_325;
wire n_312;
wire n_459;
wire newNet_285;
wire n_389;
wire n_69;
wire newNet_177;
wire newNet_39;
wire n_794;
wire n_296;
wire newNet_94;
wire i_rx_phy_rxdn_s_r;
wire newNet_236;
wire n_317;
wire newNet_122;
wire DataOut_i_2_;
wire newNet_267;
wire n_364;
wire n_935;
wire newNet_312;
wire newNet_181;
wire n_461;
wire g1779_db;
wire newNet_274;
wire txoe;
wire newNet_280;
wire n_161;
wire newNet_241;
wire g15_p;
wire DataIn_o_4_;
wire newNet_216;
wire newNet_197;
wire newNet_245;
wire n_299;
wire n_334;
wire newNet_65;
wire n_257;
wire newNet_48;
wire newNet_42;
wire n_58;
wire n_35;
wire n_742;
wire newNet_36;
wire n_310;
wire newNet_143;
wire g1738_p;
wire newNet_294;
wire newNet_107;
wire n_631;
wire newNet_221;
wire n_735;
wire n_878;
wire i_tx_phy_hold_reg_d_17;
wire g1777_da;
wire n_529;
wire n_764;
wire n_453;
wire newNet_52;
wire newNet_288;
wire LineState_o_1_;
wire n_431;
wire newNet_89;
wire n_972;
wire n_167;
wire n_235;
wire n_175;
wire n_351;
wire n_182;
wire g1739_p;
wire n_916;
wire n_369;
wire n_51;
wire n_225;
wire n_982;
wire newNet_258;
wire newNet_75;
wire g1776_da;
wire newNet_17;
wire newNet_205;
wire newNet_299;
wire i_rx_phy_se0_r_reg_Q;
wire g2063_sb;
wire newNet_164;
wire n_85;
wire newNet_192;
wire rst_cnt_4_;
wire rst_cnt_3_;
wire n_124;
wire g2651_p;
wire n_885;
wire n_425;
wire newNet_303;
wire newNet_93;
wire n_138;
wire n_505;
wire i_rx_phy_rxdn_s_r_reg_Q;
wire newNet_296;
wire i_tx_phy_append_eop_sync4;
wire n_490;
wire newNet_82;
wire n_759;
wire i_tx_phy_state_2_;
wire n_132;
wire n_269;
wire n_914;
wire n_708;
wire n_590;
wire g2385_p;
wire n_9;
wire i_rx_phy_rxdp_s;
wire DataIn_o_3_;
wire newNet_118;
wire newNet_106;
wire n_15;
wire n_632;
wire n_217;
wire n_130;
wire newNet_308;
wire n_330;
wire newNet_176;
wire newNet_152;
wire n_413;
wire newNet_239;
wire newNet_142;
wire n_57;
wire n_743;
wire txdp;
wire n_354;
wire newNet_167;
wire n_934;
wire n_255;
wire n_168;
wire g1881_p;
wire DataOut_i_3_;
wire newNet_198;
wire i_tx_phy_sft_done;
wire n_263;
wire n_460;
wire g11_p;
wire newNet_35;
wire n_921;
wire n_452;
wire newNet_304;
wire i_tx_phy_ld_data_reg_Q;
wire n_539;
wire g2494_p;
wire rxdp;
wire g1855_sb;
wire n_407;
wire newNet_100;
wire n_915;
wire n_758;
wire newNet_232;
wire n_176;
wire newNet_287;
wire n_888;
wire n_209;
wire n_244;
wire n_436;
wire n_191;
wire n_968;
wire newNet_128;
wire n_116;
wire newNet_240;
wire newNet_186;
wire n_322;
wire n_277;
wire n_105;
wire n_342;
wire newNet_301;
wire n_840;
wire newNet_54;
wire n_306;
wire newNet_49;
wire newNet_180;
wire n_12;
wire g1897_u0_o;
wire newNet_254;
wire n_21;
wire n_28;
wire DataOut_i_0_;
wire n_169;
wire DataIn_o_6_;
wire i_tx_phy_one_cnt_1_;
wire g1923_p;
wire newNet_295;
wire n_499;
wire n_388;
wire n_27;
wire g1779_sb;
wire n_245;
wire newNet_96;
wire i_tx_phy_tx_ip;
wire newNet_208;
wire newNet_307;
wire n_333;
wire n_788;
wire g2069_p;
wire n_567;
wire n_852;
wire newNet_22;
wire n_924;
wire newNet_141;
wire n_559;
wire g1781_db;
wire n_930;
wire n_709;
wire n_411;
wire n_540;
wire n_925;
wire n_967;
wire n_472;
wire newNet_311;
wire newNet_227;
wire n_864;
wire newNet_156;
wire newNet_87;
wire n_666;
wire newNet_59;
wire n_756;
wire i_rx_phy_sync_err;
wire i_tx_phy_sft_done_r;
wire n_700;
wire g1776_db;
wire newNet_202;
wire n_133;
wire n_446;
wire n_598;
wire newNet_187;
wire newNet_310;
wire n_224;
wire newNet_215;
wire newNet_273;
wire newNet_259;
wire n_50;
wire newNet_68;
wire n_64;
wire newNet_151;
wire n_131;
wire newNet_134;
wire n_340;
wire n_482;
wire newNet_305;
wire newNet_238;
wire n_804;
wire newNet_191;
wire n_722;
wire newNet_7;
wire n_415;
wire newNet_170;
wire DataIn_o_7_;
wire n_338;
wire newNet_178;
wire n_259;
wire n_604;
wire n_969;
wire newNet_243;
wire i_tx_phy_hold_reg_d_15;
wire n_574;
wire newNet_80;
wire newNet_223;
wire newNet_16;
wire n_444;
wire n_782;
wire g1778_sb;
wire DataOut_i_4_;
wire i_tx_phy_sd_bs_o;
wire newNet_281;
wire newNet_264;
wire g1780_sb;
wire newNet_145;
wire g2128_p;
wire rst;
wire n_948;
wire newNet_211;
wire n_292;
wire newNet_61;
wire n_952;
wire newNet_162;
wire n_951;
wire n_228;
wire n_33;
wire n_538;
wire g2674_p;
wire newNet_155;
wire n_268;
wire n_922;
wire n_471;
wire n_754;
wire n_873;
wire n_710;
wire n_941;
wire newNet_88;
wire n_439;
wire n_237;
wire i_rx_phy_byte_err;
wire n_11;
wire i_tx_phy_one_cnt_0_;
wire n_163;
wire n_400;
wire newNet_230;
wire n_573;
wire n_7;
wire n_74;
wire n_22;
wire i_rx_phy_rx_valid_r;
wire newNet_57;
wire n_120;
wire newNet_200;
wire newNet_76;
wire n_971;
wire newNet_276;
wire newNet_95;
wire n_455;
wire RxError_o;
wire i_rx_phy_rxd_s1_reg_Q;
wire n_841;
wire g1781_da;
wire n_316;
wire newNet_62;
wire n_741;
wire i_tx_phy_hold_reg_d_reg_1__Q;
wire n_420;
wire newNet_30;
wire n_699;
wire newNet_263;
wire newNet_21;
wire n_704;
wire n_368;
wire n_785;
wire n_352;
wire LineState_o_0_;
wire newNet_13;
wire n_193;
wire i_tx_phy_hold_reg_4;
wire newNet_253;
wire rxdn;
wire i_rx_phy_sd_nrzi;
wire i_rx_phy_rx_valid1;
wire n_56;
wire n_989;
wire i_tx_phy_hold_reg_6;
wire n_933;
wire n_201;
wire phy_tx_mode;
wire newNet_11;
wire i_rx_phy_se0_s;
wire n_377;
wire newNet_195;
wire n_480;
wire n_423;
wire g1884_p;
wire n_88;
wire n_71;
wire newNet_123;
wire newNet_67;
wire newNet_252;
wire g1781_sb;
wire n_387;
wire newNet_249;
wire n_926;
wire n_394;
wire newNet_222;
wire n_462;
wire i_rx_phy_rxdp_s0;
wire n_103;
wire newNet_219;
wire n_386;
wire n_293;
wire i_tx_phy_hold_reg_d_reg_5__Q;
wire g2412_p;
wire newNet_171;
wire newNet_196;
wire n_923;
wire newNet_265;
wire n_755;
wire newNet_282;
wire newNet_28;
wire n_963;
wire n_339;
wire newNet_70;
wire newNet_289;
wire newNet_144;
wire n_443;
wire newNet_185;
wire n_940;
wire g2057_p;
wire n_63;
wire newNet_270;
wire i_tx_phy_hold_reg;
wire n_304;
wire n_966;
wire i_rx_phy_one_cnt_2_;
wire n_100;
wire n_414;
wire n_283;
wire n_697;
wire i_rx_phy_dpll_state_0_;
wire n_55;
wire newNet_154;
wire n_347;
wire rst_cnt_0_;
wire newNet_251;
wire newNet_190;
wire newNet_18;
wire n_734;
wire n_949;
wire n_409;
wire g1942_p;
wire g2028_p;
wire n_783;
wire n_252;
wire newNet_15;
wire n_320;
wire newNet_77;
wire n_243;
wire newNet_210;
wire newNet_248;
wire newNet_34;
wire txdn;
wire n_970;
wire n_291;
wire newNet_90;
wire n_275;
wire newNet_12;
wire n_401;
wire n_301;
wire n_278;
wire i_tx_phy_bit_cnt_1_;
wire newNet_126;
wire newNet_14;
wire i_tx_phy_hold_reg_7;
wire newNet_242;
wire newNet_115;
wire newNet_146;
wire tau_clk;
wire n_988;
wire n_421;
wire i_tx_phy_append_eop_sync2;
wire newNet_275;
wire DataOut_i_5_;
wire newNet_233;
wire newNet_133;
wire i_rx_phy_rxd_r;
wire n_593;
wire newNet_290;
wire newNet_163;
wire n_375;
wire newNet_98;
wire newNet_302;
wire n_454;
wire newNet_206;
wire n_108;
wire newNet_165;
wire newNet_27;
wire rst_cnt_1_;
wire n_433;
wire n_932;
wire g1780_da;
wire n_267;
wire newNet_184;
wire n_913;
wire n_984;
wire n_111;
wire n_142;
wire i_rx_phy_rxdp_s_r;
wire g2063_db;
wire n_139;
wire n_121;
wire n_583;
wire n_280;
wire newNet_105;
wire newNet_31;
wire n_118;
wire n_48;
wire n_927;
wire newNet_153;
wire n_786;
wire DataOut_i_1_;
wire i_tx_phy_hold_reg_5;
wire n_767;
wire newNet_40;
wire i_tx_phy_hold_reg_d_reg_3__Q;
wire n_367;
wire n_489;
wire newNet_85;
wire n_523;
wire n_440;
wire n_957;
wire n_122;
wire n_204;
wire newNet_6;
wire newNet_262;
wire n_726;
wire n_457;
wire n_481;
wire n_198;
wire newNet_129;
wire newNet_71;
wire n_226;
wire n_962;
wire usb_rst;
wire n_385;
wire i_rx_phy_rx_en;
wire i_tx_phy_data_done;
wire n_487;
wire DataIn_o_5_;
wire g2116_p;
wire newNet_103;
wire TxValid_i;
wire newNet_225;
wire newNet_182;
wire newNet_161;
wire newNet_4;
wire newNet_32;
wire i_rx_phy_se0_r;
wire n_230;
wire newNet_172;
wire n_449;
wire i_tx_phy_hold_reg_d_reg_6__Q;
wire newNet_69;
wire g1855_db;
wire n_203;
wire n_456;
wire i_tx_phy_bit_cnt_0_;
wire n_66;
wire n_90;
wire i_rx_phy_rxd_s;
wire n_661;
wire newNet_81;
wire i_rx_phy_fs_ce_r1;
wire n_992;
wire i_rx_phy_fs_state_0_;
wire n_185;
wire newNet_1;
wire i_tx_phy_sd_nrzi_o;
wire i_tx_phy_hold_reg_d_13;
wire newNet_213;
wire g1782_db;
wire g1901_p;
wire i_rx_phy_rxd_s1;
wire n_155;
wire newNet_266;
wire n_311;
wire newNet_9;
wire n_153;
wire n_965;
wire newNet_159;
wire newNet_283;
wire newNet_250;
wire n_294;
wire DataIn_o_0_;
wire n_417;
wire newNet_55;
wire newNet_229;
wire newNet_217;
wire i_tx_phy_append_eop;
wire n_308;
wire newNet_147;
wire n_355;
wire n_428;
wire newNet_300;
wire n_265;
wire n_213;
wire FE_RN_2_0;
wire n_350;
wire n_229;
wire g1776_sb;
wire n_458;
wire n_943;
wire i_tx_phy_hold_reg_d;
wire n_254;
wire newNet_136;
wire n_392;
wire newNet_284;
wire i_tx_phy_state_1_;
wire i_tx_phy_append_eop_sync1;
wire n_288;
wire newNet_102;
wire newNet_168;
wire n_238;
wire newNet_125;
wire i_rx_phy_rxdn_s0;
wire newNet_203;
wire n_112;
wire RxValid_o;
wire n_910;
wire n_928;
wire g1779_da;
wire g1782_da;
wire newNet_127;
wire g1737_p;
wire n_706;
wire n_344;
wire newNet_246;
wire newNet_132;
wire newNet_33;
wire n_240;
wire n_882;
wire newNet_291;
wire n_276;
wire g2035_p;
wire FE_RN_1_0;
wire n_10;
wire i_tx_phy_hold_reg_8;
wire n_432;
wire n_752;
wire i_rx_phy_one_cnt_1_;
wire DataIn_o_1_;
wire newNet_20;
wire newNet_111;
wire newNet_114;
wire newNet_104;
wire n_942;
wire g2141_p;
wire n_18;
wire newNet_212;
wire g2066_p;
wire n_981;
wire n_753;
wire n_239;
wire newNet_179;
wire n_49;
wire n_660;
wire g1857_p;
wire n_483;
wire n_319;
wire newNet_135;
wire i_tx_phy_txoe_r2;
wire g2103_p;
wire n_309;
wire i_rx_phy_byte_err_reg_Q;
wire n_337;
wire newNet_86;
wire i_tx_phy_ld_data;
wire newNet_209;
wire n_251;
wire newNet_60;
wire newNet_131;
wire i_tx_phy_hold_reg_d_12;
wire i_rx_phy_rxdn_s;
wire newNet_44;
wire newNet_306;
wire n_60;
wire i_rx_phy_bit_stuff_err;
wire n_492;
wire newNet_72;
wire n_106;
wire n_164;
wire n_81;
wire newNet_97;
wire g41_p;
wire n_186;
wire n_197;
wire newNet_45;
wire newNet_37;
wire n_248;
wire n_961;
wire newNet_173;
wire n_416;
wire newNet_64;
wire n_289;
wire n_123;
wire newNet_78;
wire i_rx_phy_sync_err_reg_Q;
wire n_588;
wire g1740_p;
wire i_tx_phy_hold_reg_d_14;
wire n_370;
wire i_rx_phy_sd_r;
wire g2063_da;
wire newNet_224;
wire newNet_43;
wire n_343;
wire n_54;
wire n_307;
wire newNet_58;
wire n_945;
wire n_384;
wire newNet_91;
wire g1855_da;
wire newNet_148;
wire g1743_p;
wire n_91;
wire n_172;
wire n_703;
wire n_8;
wire DataOut_i_7_;
wire n_911;
wire n_365;
wire n_313;
wire g2130_p;
wire n_390;
wire n_150;
wire i_rx_phy_fs_state_2_;
wire newNet_84;
wire DataIn_o_2_;
wire n_493;
wire n_380;
wire newNet_194;
wire g2091_p;
wire newNet_175;
wire i_tx_phy_hold_reg_9;
wire n_929;
wire newNet_278;
wire newNet_231;
wire n_628;
wire DataOut_i_6_;
wire n_467;
wire n_378;
wire n_938;
wire i_rx_phy_fs_ce_r2;
wire g1777_sb;
wire n_241;
wire newNet_298;
wire i_rx_phy_rxdp_s_r_reg_Q;
wire newNet_218;
// Start cells
in01f80 newInst_312 ( .a(newNet_96), .o(newNet_312) );
no02f80 g2096_u0 ( .a(n_984), .b(usb_rst), .o(n_103) );
no02f80 g1950_u0 ( .a(n_210), .b(n_882), .o(n_296) );
in01f80 newInst_252 ( .a(newNet_251), .o(newNet_252) );
in01f80 g2511_u0 ( .a(n_763), .o(n_764) );
ao12f80 g1845_u0 ( .a(n_961), .b(n_157), .c(n_352), .o(n_406) );
na02f80 g2512_u0 ( .a(n_759), .b(n_885), .o(n_763) );
na02f80 g2027_u0 ( .a(n_55), .b(n_50), .o(n_182) );
in01f80 g2003_u0 ( .a(n_982), .o(n_217) );
na02f80 g2111_u0 ( .a(i_tx_phy_bit_cnt_1_), .b(n_56), .o(n_804) );
in01f80 newInst_224 ( .a(newNet_223), .o(newNet_224) );
in01f80 newInst_54 ( .a(newNet_53), .o(newNet_54) );
na02f80 g1916_u0 ( .a(n_37), .b(n_764), .o(n_331) );
in01f80 g27_u0 ( .a(n_224), .o(n_559) );
no02f80 g1896_u0 ( .a(n_132), .b(n_70), .o(n_197) );
in01f80 newInst_211 ( .a(newNet_210), .o(newNet_211) );
in01f80 newInst_305 ( .a(newNet_304), .o(newNet_305) );
ms00f80 i_tx_phy_one_cnt_reg_0__u0 ( .ck(newNet_71), .d(n_378), .o(i_tx_phy_one_cnt_0_) );
na02f80 g2000_u0 ( .a(i_rx_phy_rxd_s0), .b(n_130), .o(n_131) );
no02f80 g2057_u0 ( .a(i_rx_phy_sd_r), .b(n_243), .o(g2057_p) );
oa12f80 g1977_u0 ( .a(n_183), .b(n_185), .c(n_224), .o(n_225) );
na03f80 g1649_u0 ( .a(i_rx_phy_byte_err), .b(i_rx_phy_sync_err), .c(i_rx_phy_bit_stuff_err), .o(RxError_o) );
in01f80 newInst_3 ( .a(newNet_1), .o(newNet_3) );
ms00f80 i_rx_phy_se0_s_reg_u0 ( .ck(newNet_166), .d(n_471), .o(i_rx_phy_se0_s) );
in01f80 g2190_u0 ( .a(RxActive_o), .o(n_509) );
in01f80 newInst_217 ( .a(newNet_216), .o(newNet_217) );
in01f80 newInst_268 ( .a(newNet_267), .o(newNet_268) );
in01f80 newInst_74 ( .a(newNet_54), .o(newNet_74) );
ms00f80 i_rx_phy_rxdp_s_reg_u0 ( .ck(newNet_181), .d(n_309), .o(i_rx_phy_rxdp_s) );
in01f80 newInst_68 ( .a(newNet_42), .o(newNet_68) );
no02f80 g1961_u0 ( .a(n_233), .b(n_318), .o(n_320) );
na02f80 g2087_u0 ( .a(i_tx_phy_one_cnt_2_), .b(n_873), .o(n_163) );
in01f80 g2491_u0 ( .a(n_735), .o(n_737) );
na02f80 g2461_u0 ( .a(n_257), .b(n_929), .o(n_701) );
in01f80 newInst_204 ( .a(newNet_203), .o(newNet_204) );
na04m80 g1936_u0 ( .a(n_182), .b(n_15), .c(i_tx_phy_bit_cnt_2_), .d(n_77), .o(n_263) );
in01f80 g2092_u0 ( .a(n_111), .o(n_112) );
na02f80 g1739_u0 ( .a(n_456), .b(n_974), .o(g1739_p) );
in01f80 newInst_143 ( .a(newNet_93), .o(newNet_143) );
ms00f80 i_tx_phy_append_eop_sync2_reg_u0 ( .ck(newNet_142), .d(n_316), .o(i_tx_phy_append_eop_sync2) );
in01f80 g2152_u0 ( .a(i_rx_phy_bit_cnt_0_), .o(n_37) );
no02f80 g2626_u0 ( .a(n_224), .b(n_888), .o(n_928) );
in01f80 newInst_2 ( .a(newNet_1), .o(newNet_2) );
in01f80 i_rx_phy_bit_stuff_err_reg_u1 ( .a(i_rx_phy_bit_stuff_err_reg_Q), .o(i_rx_phy_bit_stuff_err) );
ms00f80 rst_cnt_reg_4__u0 ( .ck(newNet_5), .d(n_423), .o(rst_cnt_4_) );
no02f80 g2640_u0 ( .a(n_980), .b(n_947), .o(n_948) );
in01f80 g2440_u0 ( .a(i_rx_phy_rxdp_s), .o(n_666) );
in01f80 g2182_u0 ( .a(i_tx_phy_bit_cnt_0_), .o(n_56) );
in01f80 g2026_u0 ( .a(n_182), .o(n_210) );
in01f80 newInst_36 ( .a(newNet_26), .o(newNet_36) );
oa12f80 g2502_u0 ( .a(n_754), .b(n_944), .c(n_752), .o(n_755) );
in01f80 newInst_294 ( .a(newNet_293), .o(newNet_294) );
na03f80 g1926_u0 ( .a(n_259), .b(n_50), .c(g2674_p), .o(n_299) );
no02f80 g2068_u0 ( .a(n_353), .b(i_rx_phy_bit_cnt_0_), .o(g2068_p) );
in01f80 newInst_156 ( .a(newNet_63), .o(newNet_156) );
in01f80 g2219_u0 ( .a(i_tx_phy_one_cnt_1_), .o(n_49) );
in01f80 g2173_u0 ( .a(rst_cnt_1_), .o(n_22) );
in01f80 newInst_7 ( .a(newNet_1), .o(newNet_7) );
oa12f80 g1928_u0 ( .a(n_131), .b(n_127), .c(i_rx_phy_rxd_s1), .o(n_229) );
ms00f80 i_rx_phy_se0_r_reg_u0 ( .ck(newNet_171), .d(n_446), .o(i_rx_phy_se0_r_reg_Q) );
no02f80 g2639_u0 ( .a(n_794), .b(n_111), .o(n_945) );
ms00f80 i_tx_phy_hold_reg_reg_3__u0 ( .ck(newNet_90), .d(n_485), .o(i_tx_phy_hold_reg_6) );
in01f80 newInst_173 ( .a(newNet_172), .o(newNet_173) );
na02f80 g2627_u0 ( .a(n_930), .b(n_933), .o(n_934) );
in01f80 g2599_u0 ( .a(n_885), .o(n_882) );
na02f80 g2048_u0 ( .a(n_277), .b(i_tx_phy_sd_bs_o), .o(n_278) );
in01f80 newInst_108 ( .a(newNet_107), .o(newNet_108) );
na02f80 g1931_u0 ( .a(n_169), .b(n_296), .o(n_294) );
ao12f80 g1859_u0 ( .a(n_391), .b(n_88), .c(n_390), .o(n_421) );
no02f80 g1725_u0 ( .a(n_385), .b(n_416), .o(n_428) );
in01f80 g2149_u0 ( .a(n_306), .o(n_70) );
in01f80 i_rx_phy_rxd_s1_reg_u1 ( .a(i_rx_phy_rxd_s1_reg_Q), .o(i_rx_phy_rxd_s1) );
na02f80 g1782_u3 ( .a(g1782_da), .b(g1782_db), .o(n_452) );
na02f80 g1778_u3 ( .a(g1778_da), .b(g1778_db), .o(n_456) );
in01f80 newInst_73 ( .a(newNet_72), .o(newNet_73) );
in01f80 i_tx_phy_hold_reg_d_reg_5__u1 ( .a(i_tx_phy_hold_reg_d_reg_5__Q), .o(i_tx_phy_hold_reg_d_15) );
na02f80 g1907_u0 ( .a(n_106), .b(n_103), .o(n_268) );
na02f80 g2015_u0 ( .a(n_277), .b(n_48), .o(n_280) );
ao12f80 g1846_u0 ( .a(n_961), .b(n_354), .c(n_334), .o(n_405) );
in01f80 g2035_u1 ( .a(g2035_p), .o(n_126) );
in01f80 g1742_u1 ( .a(g1742_p), .o(n_483) );
in01f80 newInst_65 ( .a(newNet_37), .o(newNet_65) );
na02f80 g1813_u0 ( .a(n_434), .b(DataOut_i_7_), .o(n_462) );
in01f80 g1964_u0 ( .a(n_289), .o(n_290) );
in01f80 newInst_150 ( .a(newNet_149), .o(newNet_150) );
no02f80 g2130_u0 ( .a(n_884), .b(n_509), .o(g2130_p) );
in01f80 newInst_142 ( .a(newNet_141), .o(newNet_142) );
ms00f80 i_rx_phy_fs_ce_reg_u0 ( .ck(newNet_284), .d(i_rx_phy_fs_ce_r2), .o(n_885) );
ao22s80 g1879_u0 ( .a(n_225), .b(i_tx_phy_sd_nrzi_o), .c(n_873), .d(txdp), .o(n_308) );
ms00f80 i_rx_phy_hold_reg_reg_1__u0 ( .ck(newNet_272), .d(DataIn_o_2_), .o(DataIn_o_1_) );
na02f80 g2053_u0 ( .a(n_804), .b(n_168), .o(n_169) );
in01f80 g1857_u1 ( .a(g1857_p), .o(n_433) );
in01f80 g1738_u1 ( .a(g1738_p), .o(n_487) );
in01f80 newInst_12 ( .a(newNet_11), .o(newNet_12) );
na02f80 g23_u0 ( .a(n_604), .b(n_926), .o(n_938) );
in01f80 newInst_88 ( .a(newNet_87), .o(newNet_88) );
na02f80 g1958_u0 ( .a(n_574), .b(n_841), .o(n_257) );
in01f80 newInst_134 ( .a(newNet_125), .o(newNet_134) );
in01f80 newInst_287 ( .a(newNet_286), .o(newNet_287) );
in01f80 newInst_226 ( .a(newNet_225), .o(newNet_226) );
ms00f80 i_rx_phy_rx_en_reg_u0 ( .ck(newNet_233), .d(txoe), .o(i_rx_phy_rx_en) );
in01f80 newInst_17 ( .a(newNet_16), .o(newNet_17) );
no02f80 g2506_u0 ( .a(n_910), .b(n_460), .o(g2506_p) );
in01f80 newInst_232 ( .a(newNet_231), .o(newNet_232) );
in01f80 newInst_21 ( .a(newNet_20), .o(newNet_21) );
ms00f80 i_tx_phy_hold_reg_reg_2__u0 ( .ck(newNet_95), .d(n_486), .o(i_tx_phy_hold_reg_5) );
in01f80 g2050_u1 ( .a(g2050_p), .o(n_172) );
in01f80 newInst_260 ( .a(newNet_259), .o(newNet_260) );
in01f80 newInst_111 ( .a(newNet_110), .o(newNet_111) );
in01f80 newInst_49 ( .a(newNet_48), .o(newNet_49) );
in01f80 newInst_149 ( .a(newNet_148), .o(newNet_149) );
no02f80 FE_RC_1_0 ( .a(FE_RN_2_0), .b(FE_RN_1_0), .o(FE_RN_0_0) );
in01f80 newInst_231 ( .a(newNet_230), .o(newNet_231) );
in01f80 newInst_181 ( .a(newNet_180), .o(newNet_181) );
in01f80 g2637_u0 ( .a(n_794), .o(n_940) );
na02f80 g1873_u0 ( .a(n_280), .b(n_273), .o(n_338) );
in01f80 newInst_300 ( .a(newNet_105), .o(newNet_300) );
na02f80 g2030_u0 ( .a(i_tx_phy_hold_reg_d_12), .b(n_124), .o(n_97) );
ao12f80 g1986_u0 ( .a(n_241), .b(n_384), .c(n_240), .o(n_313) );
in01f80 newInst_80 ( .a(newNet_79), .o(newNet_80) );
ms00f80 i_rx_phy_one_cnt_reg_1__u0 ( .ck(newNet_242), .d(n_427), .o(i_rx_phy_one_cnt_1_) );
na02f80 g1741_u0 ( .a(n_454), .b(n_974), .o(g1741_p) );
ao12f80 g2069_u1 ( .a(g2069_p), .b(n_115), .c(i_tx_phy_one_cnt_0_), .o(n_116) );
in01f80 g1740_u1 ( .a(g1740_p), .o(n_485) );
in01f80 newInst_242 ( .a(newNet_241), .o(newNet_242) );
in01f80 newInst_214 ( .a(newNet_24), .o(newNet_214) );
in01f80 g22_u0 ( .a(n_852), .o(n_988) );
in01f80 newInst_20 ( .a(newNet_19), .o(newNet_20) );
ms00f80 i_tx_phy_TxReady_o_reg_u0 ( .ck(newNet_155), .d(n_392), .o(TxReady_o) );
oa12f80 g1745_u0 ( .a(n_252), .b(n_311), .c(n_384), .o(n_380) );
in01f80 newInst_97 ( .a(newNet_96), .o(newNet_97) );
ms00f80 i_rx_phy_rx_valid1_reg_u0 ( .ck(newNet_232), .d(n_431), .o(i_rx_phy_rx_valid1) );
na02f80 g1897_u0 ( .a(n_764), .b(i_rx_phy_shift_en), .o(g1897_u0_o) );
na03f80 g42_u0 ( .a(n_737), .b(n_593), .c(n_590), .o(n_968) );
in01f80 newInst_306 ( .a(newNet_305), .o(newNet_306) );
in01f80 newInst_165 ( .a(newNet_164), .o(newNet_165) );
in01f80 newInst_29 ( .a(newNet_28), .o(newNet_29) );
in01f80 newInst_225 ( .a(newNet_13), .o(newNet_225) );
no02f80 g11_u0 ( .a(n_980), .b(n_947), .o(g11_p) );
in01f80 g2195_u0 ( .a(rst), .o(n_318) );
na02f80 g1951_u0 ( .a(n_182), .b(n_885), .o(n_343) );
no02f80 g2465_u0 ( .a(n_318), .b(n_540), .o(n_706) );
na03f80 g1924_u0 ( .a(n_325), .b(n_53), .c(g2674_p), .o(n_352) );
ms00f80 i_rx_phy_rx_valid_r_reg_u0 ( .ck(newNet_228), .d(n_433), .o(i_rx_phy_rx_valid_r) );
ao22s80 g2062_u0 ( .a(i_tx_phy_append_eop_sync4), .b(n_852), .c(n_48), .d(g2674_p), .o(n_204) );
in01f80 g1954_u0 ( .a(n_258), .o(n_259) );
na02f80 g2063_u3 ( .a(g2063_da), .b(g2063_db), .o(n_203) );
in01f80 newInst_210 ( .a(newNet_209), .o(newNet_210) );
no02f80 g2392_u0 ( .a(n_932), .b(n_952), .o(n_590) );
in01f80 newInst_298 ( .a(newNet_297), .o(newNet_298) );
ms00f80 i_tx_phy_append_eop_sync1_reg_u0 ( .ck(newNet_145), .d(n_317), .o(i_tx_phy_append_eop_sync1) );
in01f80 g2257_u0 ( .a(rst_cnt_3_), .o(n_69) );
na02f80 g2108_u0 ( .a(i_rx_phy_rx_valid_r), .b(n_882), .o(g2108_p) );
na02f80 g2459_u0 ( .a(n_910), .b(n_980), .o(n_697) );
ms00f80 i_rx_phy_fs_ce_r2_reg_u0 ( .ck(newNet_287), .d(i_rx_phy_fs_ce_r1), .o(i_rx_phy_fs_ce_r2) );
na02f80 g1742_u0 ( .a(n_453), .b(n_974), .o(g1742_p) );
in01f80 newInst_59 ( .a(newNet_58), .o(newNet_59) );
in01f80 newInst_69 ( .a(newNet_68), .o(newNet_69) );
ms00f80 i_tx_phy_append_eop_sync3_reg_u0 ( .ck(newNet_139), .d(n_338), .o(n_224) );
na02f80 g1975_u0 ( .a(i_rx_phy_rxdp_s0), .b(LineState_o_0_), .o(g1975_p) );
in01f80 newInst_10 ( .a(newNet_9), .o(newNet_10) );
in01f80 g1776_u0 ( .a(i_tx_phy_ld_data), .o(g1776_sb) );
in01f80 newInst_255 ( .a(newNet_254), .o(newNet_255) );
in01f80 newInst_216 ( .a(newNet_215), .o(newNet_216) );
in01f80 newInst_168 ( .a(newNet_167), .o(newNet_168) );
na02f80 g2063_u2 ( .a(i_rx_phy_sd_r), .b(n_852), .o(g2063_db) );
in01f80 g1998_u0 ( .a(n_949), .o(n_782) );
in01f80 newInst_129 ( .a(newNet_53), .o(newNet_129) );
in01f80 newInst_28 ( .a(newNet_22), .o(newNet_28) );
in01f80 newInst_263 ( .a(newNet_70), .o(newNet_263) );
na02f80 g1776_u3 ( .a(g1776_da), .b(g1776_db), .o(n_458) );
ms00f80 i_rx_phy_rxd_s1_reg_u0 ( .ck(newNet_213), .d(i_rx_phy_rxd_s0), .o(i_rx_phy_rxd_s1_reg_Q) );
ao12f80 g2057_u1 ( .a(g2057_p), .b(i_rx_phy_sd_r), .c(n_243), .o(n_122) );
ms00f80 i_tx_phy_tx_ip_sync_reg_u0 ( .ck(newNet_41), .d(n_319), .o(n_238) );
ms00f80 i_rx_phy_hold_reg_reg_0__u0 ( .ck(newNet_274), .d(DataIn_o_1_), .o(DataIn_o_0_) );
in01f80 newInst_53 ( .a(newNet_52), .o(newNet_53) );
in01f80 newInst_33 ( .a(newNet_32), .o(newNet_33) );
in01f80 g2095_u0 ( .a(n_103), .o(n_384) );
in01f80 g1923_u1 ( .a(g1923_p), .o(n_390) );
na02f80 g1780_u3 ( .a(g1780_da), .b(g1780_db), .o(n_454) );
in01f80 newInst_114 ( .a(newNet_113), .o(newNet_114) );
in01f80 newInst_19 ( .a(newNet_3), .o(newNet_19) );
in01f80 g2270_u0 ( .a(n_353), .o(n_18) );
in01f80 newInst_282 ( .a(newNet_281), .o(newNet_282) );
oa12f80 g1854_u0 ( .a(n_133), .b(n_231), .c(i_tx_phy_hold_reg_d_13), .o(n_232) );
no02f80 g2122_u0 ( .a(n_52), .b(n_28), .o(n_58) );
na02f80 g2043_u0 ( .a(n_948), .b(n_794), .o(n_175) );
na02f80 g2632_u0 ( .a(n_64), .b(i_tx_phy_sft_done), .o(n_932) );
no02f80 g1981_u0 ( .a(LineState_o_0_), .b(LineState_o_1_), .o(n_191) );
ms00f80 i_rx_phy_hold_reg_reg_6__u0 ( .ck(newNet_253), .d(DataIn_o_7_), .o(DataIn_o_6_) );
na03f80 g1982_u0 ( .a(n_125), .b(i_tx_phy_hold_reg_d_17), .c(i_tx_phy_bit_cnt_2_), .o(n_133) );
na02f80 g35_u0 ( .a(n_722), .b(n_926), .o(n_741) );
na02f80 g2109_u0 ( .a(n_115), .b(n_873), .o(n_154) );
in01f80 g1975_u1 ( .a(g1975_p), .o(n_226) );
in01f80 newInst_274 ( .a(newNet_273), .o(newNet_274) );
in01f80 newInst_157 ( .a(newNet_156), .o(newNet_157) );
in01f80 newInst_197 ( .a(newNet_182), .o(newNet_197) );
na03f80 g1927_u0 ( .a(n_296), .b(i_tx_phy_sd_raw_o), .c(n_85), .o(n_297) );
in01f80 g2648_u0 ( .a(i_tx_phy_state_1_), .o(n_735) );
in01f80 g2227_u0 ( .a(n_980), .o(n_91) );
ms00f80 i_tx_phy_txdp_reg_u0 ( .ck(newNet_35), .d(n_366), .o(txdp) );
no02f80 g2069_u0 ( .a(n_115), .b(i_tx_phy_one_cnt_0_), .o(g2069_p) );
ao22s80 g1937_u0 ( .a(n_100), .b(n_885), .c(i_tx_phy_sd_nrzi_o), .d(n_873), .o(n_195) );
in01f80 newInst_122 ( .a(newNet_45), .o(newNet_122) );
in01f80 newInst_295 ( .a(newNet_294), .o(newNet_295) );
in01f80 g2604_u0 ( .a(n_929), .o(n_888) );
in01f80 g2413_u1 ( .a(g2413_p), .o(n_628) );
oa12f80 g2655_u0 ( .a(n_965), .b(n_734), .c(n_937), .o(n_966) );
ms00f80 i_tx_phy_hold_reg_d_reg_5__u0 ( .ck(newNet_106), .d(i_tx_phy_hold_reg_8), .o(i_tx_phy_hold_reg_d_reg_5__Q) );
in01f80 newInst_176 ( .a(newNet_175), .o(newNet_176) );
in01f80 newInst_109 ( .a(newNet_108), .o(newNet_109) );
ao12f80 g1726_u0 ( .a(n_384), .b(n_292), .c(n_256), .o(n_370) );
na02f80 g1697_u0 ( .a(n_490), .b(n_786), .o(n_506) );
na02f80 g2622_u0 ( .a(n_920), .b(n_921), .o(n_922) );
in01f80 newInst_125 ( .a(newNet_124), .o(newNet_125) );
ms00f80 i_rx_phy_rxdn_s0_reg_u0 ( .ck(newNet_206), .d(rxdn), .o(i_rx_phy_rxdn_s0) );
na02f80 g2431_u0 ( .a(n_749), .b(n_754), .o(n_660) );
in01f80 g2117_u0 ( .a(n_164), .o(n_108) );
ao12f80 g1983_u0 ( .a(n_167), .b(n_192), .c(i_tx_phy_hold_reg_d), .o(n_255) );
no02f80 g2024_u0 ( .a(i_rx_phy_rxd_s0), .b(n_130), .o(n_127) );
in01f80 g2272_u0 ( .a(i_tx_phy_one_cnt_2_), .o(n_33) );
in01f80 newInst_42 ( .a(newNet_25), .o(newNet_42) );
na02f80 g2635_u0 ( .a(n_938), .b(n_943), .o(n_944) );
in01f80 newInst_135 ( .a(newNet_134), .o(newNet_135) );
in01f80 newInst_4 ( .a(newNet_3), .o(newNet_4) );
ms00f80 i_tx_phy_tx_ip_reg_u0 ( .ck(newNet_45), .d(n_976), .o(i_tx_phy_tx_ip) );
in01f80 g2610_u0 ( .a(n_929), .o(n_894) );
no02f80 g1806_u0 ( .a(n_232), .b(n_300), .o(n_369) );
in01f80 g1734_u0 ( .a(n_753), .o(n_460) );
in01f80 g2091_u1 ( .a(g2091_p), .o(n_183) );
in01f80 newInst_243 ( .a(newNet_31), .o(newNet_243) );
in01f80 newInst_64 ( .a(newNet_63), .o(newNet_64) );
no02f80 g1923_u0 ( .a(n_312), .b(n_540), .o(g1923_p) );
na02f80 g1855_u1 ( .a(rst_cnt_4_), .b(g1855_sb), .o(g1855_da) );
na02f80 g1780_u2 ( .a(i_tx_phy_hold_reg_7), .b(i_tx_phy_ld_data), .o(g1780_db) );
in01f80 newInst_102 ( .a(newNet_64), .o(newNet_102) );
ao22s80 g2059_u0 ( .a(i_tx_phy_tx_ip), .b(n_885), .c(n_238), .d(n_984), .o(n_239) );
na02f80 g1914_u0 ( .a(n_296), .b(n_56), .o(n_301) );
in01f80 g1746_u0 ( .a(n_479), .o(n_505) );
na02f80 g2653_u0 ( .a(i_rx_phy_shift_en), .b(rst), .o(n_961) );
in01f80 newInst_288 ( .a(newNet_120), .o(newNet_288) );
na03f80 g26_u0 ( .a(n_443), .b(RxActive_o), .c(rst), .o(n_708) );
ms00f80 i_rx_phy_fs_state_reg_2__u0 ( .ck(newNet_276), .d(n_758), .o(i_rx_phy_fs_state_2_) );
in01f80 g2112_u0 ( .a(n_389), .o(n_81) );
in01f80 i_tx_phy_hold_reg_d_reg_3__u1 ( .a(i_tx_phy_hold_reg_d_reg_3__Q), .o(i_tx_phy_hold_reg_d_13) );
ms00f80 i_tx_phy_sd_bs_o_reg_u0 ( .ck(newNet_64), .d(n_361), .o(i_tx_phy_sd_bs_o) );
na02f80 g1868_u0 ( .a(n_116), .b(n_340), .o(n_341) );
no02f80 g1962_u0 ( .a(n_239), .b(n_318), .o(n_319) );
no02f80 g1718_u0 ( .a(n_916), .b(n_467), .o(n_783) );
in01f80 newInst_233 ( .a(newNet_7), .o(newNet_233) );
no02f80 g1967_u0 ( .a(n_235), .b(FE_RN_2_0), .o(n_316) );
na02f80 g1855_u2 ( .a(n_11), .b(n_274), .o(g1855_db) );
in01f80 newInst_81 ( .a(newNet_80), .o(newNet_81) );
ms00f80 i_rx_phy_sd_nrzi_reg_u0 ( .ck(newNet_178), .d(n_365), .o(i_rx_phy_sd_nrzi) );
in01f80 g24_u0 ( .a(n_941), .o(n_942) );
in01f80 g2103_u1 ( .a(g2103_p), .o(n_277) );
in01f80 newInst_18 ( .a(newNet_17), .o(newNet_18) );
ao12f80 g1775_u0 ( .a(n_368), .b(n_384), .c(n_306), .o(n_385) );
na02f80 g1955_u0 ( .a(n_182), .b(i_tx_phy_sd_raw_o), .o(n_258) );
na02m80 FE_RC_0_0 ( .a(FE_RN_0_0), .b(n_629), .o(n_632) );
in01f80 g1952_u0 ( .a(n_324), .o(n_325) );
na03f80 g1774_u0 ( .a(n_425), .b(n_175), .c(n_949), .o(n_440) );
ao12f80 g1870_u0 ( .a(n_343), .b(n_126), .c(n_231), .o(n_339) );
in01f80 newInst_63 ( .a(newNet_31), .o(newNet_63) );
in01f80 newInst_241 ( .a(newNet_240), .o(newNet_241) );
ao12f80 g2056_u0 ( .a(n_164), .b(n_888), .c(n_737), .o(n_165) );
na02f80 g2104_u0 ( .a(i_rx_phy_one_cnt_0_), .b(n_873), .o(n_157) );
ms00f80 i_tx_phy_hold_reg_reg_5__u0 ( .ck(newNet_81), .d(n_483), .o(i_tx_phy_hold_reg_8) );
ao22s80 g1933_u0 ( .a(n_122), .b(n_266), .c(n_150), .d(i_rx_phy_sd_nrzi), .o(n_267) );
in01f80 newInst_303 ( .a(newNet_280), .o(newNet_303) );
in01f80 newInst_50 ( .a(newNet_49), .o(newNet_50) );
in01f80 newInst_297 ( .a(newNet_296), .o(newNet_297) );
na02f80 g1762_u0 ( .a(i_rx_phy_rx_valid_r), .b(n_446), .o(n_443) );
in01f80 newInst_167 ( .a(newNet_132), .o(newNet_167) );
ms00f80 i_rx_phy_dpll_state_reg_0__u0 ( .ck(newNet_299), .d(n_449), .o(i_rx_phy_dpll_state_0_) );
in01f80 g1828_u0 ( .a(i_tx_phy_ld_data), .o(n_434) );
in01f80 g2527_u0 ( .a(n_788), .o(n_786) );
no02f80 g1811_u0 ( .a(n_377), .b(n_400), .o(n_415) );
ao12f80 g1838_u0 ( .a(n_416), .b(n_251), .c(n_268), .o(n_367) );
na02f80 g1810_u0 ( .a(n_197), .b(n_69), .o(n_256) );
in01f80 newInst_307 ( .a(newNet_72), .o(newNet_307) );
in01f80 newInst_23 ( .a(newNet_15), .o(newNet_23) );
in01f80 g2273_u0 ( .a(n_243), .o(n_130) );
na03f80 g2482_u0 ( .a(n_439), .b(n_794), .c(n_90), .o(n_726) );
in01f80 newInst_281 ( .a(newNet_119), .o(newNet_281) );
in01f80 newInst_257 ( .a(newNet_256), .o(newNet_257) );
in01f80 newInst_202 ( .a(newNet_189), .o(newNet_202) );
in01f80 g2161_u0 ( .a(i_tx_phy_append_eop_sync2), .o(n_12) );
ao12f80 g1695_u0 ( .a(FE_RN_2_0), .b(n_704), .c(n_935), .o(n_459) );
na02f80 g2088_u0 ( .a(i_tx_phy_one_cnt_0_), .b(n_873), .o(n_161) );
no02f80 g1865_u0 ( .a(n_274), .b(n_11), .o(n_275) );
na02f80 g1872_u0 ( .a(n_227), .b(i_rx_phy_rxdp_s_r), .o(n_309) );
no02f80 g2652_u0 ( .a(n_984), .b(n_324), .o(n_958) );
in01f80 newInst_121 ( .a(newNet_7), .o(newNet_121) );
na02f80 g1778_u2 ( .a(i_tx_phy_hold_reg_5), .b(i_tx_phy_ld_data), .o(g1778_db) );
in01f80 newInst_30 ( .a(newNet_29), .o(newNet_30) );
na02f80 g2114_u0 ( .a(n_852), .b(txdn), .o(n_153) );
ao22s80 g2623_u0 ( .a(n_919), .b(n_945), .c(n_722), .d(n_916), .o(n_920) );
in01f80 newInst_254 ( .a(newNet_112), .o(newNet_254) );
na02f80 g1776_u2 ( .a(i_tx_phy_hold_reg), .b(i_tx_phy_ld_data), .o(g1776_db) );
na02f80 g1922_u0 ( .a(n_71), .b(n_66), .o(n_274) );
na02f80 g2656_u0 ( .a(n_583), .b(n_737), .o(n_967) );
no02f80 g2124_u0 ( .a(i_rx_phy_dpll_state_1_), .b(i_rx_phy_dpll_state_0_), .o(n_88) );
no02f80 g2479_u0 ( .a(n_788), .b(n_697), .o(n_722) );
in01f80 g2084_u0 ( .a(i_rx_phy_rxd_r), .o(n_244) );
ms00f80 i_tx_phy_sd_nrzi_o_reg_u0 ( .ck(newNet_62), .d(n_276), .o(i_tx_phy_sd_nrzi_o) );
in01f80 newInst_71 ( .a(newNet_66), .o(newNet_71) );
in01f80 i_rx_phy_rxdn_s_r_reg_u1 ( .a(i_rx_phy_rxdn_s_r_reg_Q), .o(i_rx_phy_rxdn_s_r) );
na02f80 g2090_u0 ( .a(i_tx_phy_append_eop), .b(n_12), .o(n_63) );
na03f80 g1925_u0 ( .a(n_350), .b(n_583), .c(n_800), .o(n_351) );
ms00f80 i_tx_phy_append_eop_reg_u0 ( .ck(newNet_150), .d(n_409), .o(i_tx_phy_append_eop) );
na03f80 g58_u0 ( .a(n_788), .b(n_112), .c(n_919), .o(n_921) );
na02f80 g1777_u2 ( .a(i_tx_phy_hold_reg_4), .b(i_tx_phy_ld_data), .o(g1777_db) );
in01f80 g41_u1 ( .a(g41_p), .o(n_700) );
in01f80 newInst_248 ( .a(newNet_247), .o(newNet_248) );
ao12f80 g2501_u0 ( .a(n_318), .b(n_755), .c(n_756), .o(n_758) );
in01f80 newInst_153 ( .a(newNet_152), .o(newNet_153) );
in01f80 newInst_209 ( .a(newNet_208), .o(newNet_209) );
ms00f80 i_rx_phy_byte_err_reg_u0 ( .ck(newNet_301), .d(n_499), .o(i_rx_phy_byte_err_reg_Q) );
ao12f80 g1851_u0 ( .a(FE_RN_2_0), .b(n_267), .c(RxActive_o), .o(n_365) );
in01f80 newInst_179 ( .a(newNet_157), .o(newNet_179) );
in01f80 newInst_101 ( .a(newNet_14), .o(newNet_101) );
in01f80 newInst_62 ( .a(newNet_53), .o(newNet_62) );
in01f80 g1819_u0 ( .a(n_426), .o(n_446) );
no02f80 g2035_u0 ( .a(n_125), .b(n_124), .o(g2035_p) );
na02f80 g1724_u0 ( .a(n_919), .b(n_914), .o(n_492) );
in01f80 newInst_106 ( .a(newNet_20), .o(newNet_106) );
ao12f80 g1853_u0 ( .a(FE_RN_2_0), .b(n_153), .c(n_265), .o(n_364) );
ms00f80 i_rx_phy_rxdn_s1_reg_u0 ( .ck(newNet_201), .d(i_rx_phy_rxdn_s0), .o(LineState_o_1_) );
in01f80 newInst_1 ( .a(newNet_0), .o(newNet_1) );
ms00f80 i_tx_phy_append_eop_sync4_reg_u0 ( .ck(newNet_138), .d(n_288), .o(i_tx_phy_append_eop_sync4) );
ms00f80 i_rx_phy_rxdn_s_reg_u0 ( .ck(newNet_196), .d(n_310), .o(i_rx_phy_rxdn_s) );
in01f80 newInst_140 ( .a(newNet_66), .o(newNet_140) );
ms00f80 rst_cnt_reg_0__u0 ( .ck(newNet_18), .d(n_362), .o(rst_cnt_0_) );
in01f80 g2157_u0 ( .a(i_rx_phy_dpll_state_0_), .o(n_60) );
ao12f80 g2066_u1 ( .a(g2066_p), .b(n_105), .c(n_240), .o(n_106) );
in01f80 newInst_89 ( .a(newNet_88), .o(newNet_89) );
na02f80 g1782_u1 ( .a(DataOut_i_6_), .b(g1782_sb), .o(g1782_da) );
oa12f80 g2058_u0 ( .a(n_35), .b(i_tx_phy_sd_bs_o), .c(i_tx_phy_sd_nrzi_o), .o(n_100) );
in01f80 newInst_273 ( .a(newNet_78), .o(newNet_273) );
na02f80 g1942_u0 ( .a(i_tx_phy_data_done), .b(n_937), .o(g1942_p) );
ms00f80 i_tx_phy_sft_done_r_reg_u0 ( .ck(newNet_60), .d(i_tx_phy_sft_done), .o(i_tx_phy_sft_done_r) );
in01f80 g2385_u1 ( .a(g2385_p), .o(n_567) );
ms00f80 i_tx_phy_hold_reg_reg_4__u0 ( .ck(newNet_86), .d(n_484), .o(i_tx_phy_hold_reg_7) );
na02f80 g1681_u0 ( .a(n_493), .b(n_440), .o(n_511) );
in01f80 newInst_234 ( .a(newNet_33), .o(newNet_234) );
na02f80 g2495_u0 ( .a(n_467), .b(n_914), .o(n_742) );
no02f80 g1808_u0 ( .a(n_307), .b(n_384), .o(n_368) );
in01f80 g2020_u0 ( .a(n_759), .o(n_248) );
in01f80 newInst_272 ( .a(newNet_271), .o(newNet_272) );
ms00f80 i_rx_phy_hold_reg_reg_3__u0 ( .ck(newNet_264), .d(DataIn_o_4_), .o(DataIn_o_3_) );
in01f80 newInst_266 ( .a(newNet_265), .o(newNet_266) );
no02f80 g2139_u0 ( .a(n_50), .b(n_49), .o(n_51) );
in01f80 newInst_201 ( .a(newNet_45), .o(newNet_201) );
in01f80 newInst_51 ( .a(newNet_50), .o(newNet_51) );
in01f80 newInst_188 ( .a(newNet_158), .o(newNet_188) );
in01f80 g1830_u0 ( .a(i_rx_phy_rxdn_s), .o(n_424) );
ao12f80 g1821_u0 ( .a(FE_RN_2_0), .b(n_435), .c(n_389), .o(n_436) );
in01f80 newInst_112 ( .a(newNet_111), .o(newNet_112) );
in01f80 newInst_107 ( .a(newNet_49), .o(newNet_107) );
in01f80 g2119_u0 ( .a(n_697), .o(n_90) );
in01f80 newInst_236 ( .a(newNet_235), .o(newNet_236) );
in01f80 newInst_183 ( .a(newNet_182), .o(newNet_183) );
in01f80 newInst_139 ( .a(newNet_68), .o(newNet_139) );
in01f80 newInst_240 ( .a(newNet_51), .o(newNet_240) );
na02f80 g1778_u1 ( .a(DataOut_i_2_), .b(g1778_sb), .o(g1778_da) );
in01f80 newInst_148 ( .a(newNet_147), .o(newNet_148) );
na03f80 g2508_u0 ( .a(n_763), .b(i_rx_phy_rx_valid1), .c(rst), .o(n_767) );
in01f80 g2438_u0 ( .a(n_666), .o(n_665) );
in01f80 newInst_256 ( .a(newNet_255), .o(newNet_256) );
in01f80 newInst_22 ( .a(newNet_21), .o(newNet_22) );
in01f80 g2183_u0 ( .a(n_57), .o(n_15) );
in01f80 i_tx_phy_hold_reg_d_reg_1__u1 ( .a(i_tx_phy_hold_reg_d_reg_1__Q), .o(i_tx_phy_hold_reg_d_11) );
in01f80 g1979_u0 ( .a(n_222), .o(n_223) );
in01f80 g1935_u0 ( .a(n_263), .o(n_293) );
in01f80 newInst_133 ( .a(newNet_125), .o(newNet_133) );
in01f80 newInst_269 ( .a(newNet_268), .o(newNet_269) );
in01f80 newInst_308 ( .a(newNet_307), .o(newNet_308) );
in01f80 g1779_u0 ( .a(i_tx_phy_ld_data), .o(g1779_sb) );
in01f80 g2667_u0 ( .a(n_796), .o(n_794) );
in01f80 newInst_144 ( .a(newNet_143), .o(newNet_144) );
na02f80 g1781_u2 ( .a(i_tx_phy_hold_reg_8), .b(i_tx_phy_ld_data), .o(g1781_db) );
ms00f80 i_tx_phy_hold_reg_d_reg_4__u0 ( .ck(newNet_109), .d(i_tx_phy_hold_reg_7), .o(i_tx_phy_hold_reg_d_14) );
oa12f80 g1744_u0 ( .a(i_rx_phy_se0_r), .b(n_353), .c(i_rx_phy_bit_cnt_2_), .o(n_472) );
in01f80 newInst_195 ( .a(newNet_194), .o(newNet_195) );
in01f80 g12_u0 ( .a(i_rx_phy_rx_en), .o(n_540) );
no02f80 g2054_u0 ( .a(n_168), .b(i_tx_phy_hold_reg_d_11), .o(n_167) );
in01f80 g2258_u0 ( .a(i_rx_phy_se0_s), .o(n_9) );
ao12f80 g1837_u0 ( .a(FE_RN_2_0), .b(n_63), .c(n_968), .o(n_409) );
na03f80 g25_u0 ( .a(n_735), .b(n_952), .c(n_894), .o(n_841) );
in01f80 g2155_u0 ( .a(i_tx_phy_one_cnt_0_), .o(n_50) );
in01f80 newInst_190 ( .a(newNet_189), .o(newNet_190) );
in01f80 newInst_94 ( .a(newNet_93), .o(newNet_94) );
in01f80 newInst_203 ( .a(newNet_202), .o(newNet_203) );
no02f80 g1963_u0 ( .a(n_201), .b(n_318), .o(n_291) );
in01f80 newInst_119 ( .a(newNet_93), .o(newNet_119) );
in01f80 g61_u0 ( .a(n_942), .o(n_919) );
na03f80 g2505_u0 ( .a(n_61), .b(n_426), .c(n_9), .o(n_753) );
in01f80 g2412_u1 ( .a(g2412_p), .o(n_629) );
na02f80 g1900_u0 ( .a(n_118), .b(n_764), .o(n_334) );
na02f80 g2115_u0 ( .a(n_120), .b(n_873), .o(n_152) );
in01f80 g1767_u0 ( .a(n_941), .o(n_467) );
in01f80 newInst_35 ( .a(newNet_34), .o(newNet_35) );
in01f80 g2669_u0 ( .a(i_rx_phy_fs_state_0_), .o(n_980) );
ms00f80 i_tx_phy_hold_reg_d_reg_0__u0 ( .ck(newNet_121), .d(i_tx_phy_hold_reg), .o(i_tx_phy_hold_reg_d) );
na03f80 g1816_u0 ( .a(n_421), .b(n_435), .c(rst), .o(n_449) );
in01f80 newInst_155 ( .a(newNet_154), .o(newNet_155) );
in01f80 newInst_46 ( .a(newNet_14), .o(newNet_46) );
no02f80 g2665_u0 ( .a(n_913), .b(n_981), .o(n_982) );
in01f80 newInst_219 ( .a(newNet_218), .o(newNet_219) );
in01f80 newInst_154 ( .a(newNet_153), .o(newNet_154) );
in01f80 newInst_198 ( .a(newNet_197), .o(newNet_198) );
na02f80 g1980_u0 ( .a(i_rx_phy_rxdn_s0), .b(LineState_o_1_), .o(g1980_p) );
in01f80 newInst_200 ( .a(newNet_199), .o(newNet_200) );
in01f80 newInst_292 ( .a(newNet_291), .o(newNet_292) );
in01f80 newInst_72 ( .a(newNet_7), .o(newNet_72) );
in01f80 g2145_u0 ( .a(n_559), .o(n_48) );
in01f80 newInst_126 ( .a(newNet_125), .o(newNet_126) );
in01f80 g2127_u0 ( .a(n_400), .o(n_85) );
na02f80 g2672_u0 ( .a(n_988), .b(n_989), .o(n_990) );
no02f80 g2050_u0 ( .a(n_804), .b(n_785), .o(g2050_p) );
ao12f80 g1840_u0 ( .a(n_322), .b(n_330), .c(n_952), .o(n_538) );
na02f80 g1906_u0 ( .a(n_191), .b(rst), .o(n_416) );
na02f80 g2385_u0 ( .a(n_885), .b(n_559), .o(g2385_p) );
oa12f80 g1934_u0 ( .a(n_184), .b(n_186), .c(n_48), .o(n_265) );
in01f80 newInst_249 ( .a(newNet_129), .o(newNet_249) );
in01f80 newInst_130 ( .a(newNet_129), .o(newNet_130) );
oa12f80 g1932_u0 ( .a(n_193), .b(n_97), .c(n_804), .o(n_228) );
in01f80 newInst_100 ( .a(newNet_99), .o(newNet_100) );
in01f80 g1741_u1 ( .a(g1741_p), .o(n_484) );
in01f80 newInst_141 ( .a(newNet_140), .o(newNet_141) );
in01f80 newInst_92 ( .a(newNet_91), .o(newNet_92) );
in01f80 newInst_57 ( .a(newNet_56), .o(newNet_57) );
ao12f80 g2657_u0 ( .a(n_318), .b(n_970), .c(n_974), .o(n_976) );
in01f80 g2645_u0 ( .a(n_951), .o(n_952) );
in01f80 FE_RC_2_0 ( .a(n_631), .o(FE_RN_1_0) );
no02f80 g2413_u0 ( .a(n_753), .b(n_727), .o(g2413_p) );
in01f80 newInst_235 ( .a(newNet_234), .o(newNet_235) );
in01f80 newInst_174 ( .a(newNet_38), .o(newNet_174) );
no02f80 g2091_u0 ( .a(phy_tx_mode), .b(n_984), .o(g2091_p) );
na02f80 g1782_u2 ( .a(i_tx_phy_hold_reg_9), .b(i_tx_phy_ld_data), .o(g1782_db) );
na02f80 g2390_u0 ( .a(n_972), .b(n_894), .o(n_574) );
in01f80 newInst_261 ( .a(newNet_260), .o(newNet_261) );
ms00f80 i_rx_phy_rxdp_s_r_reg_u0 ( .ck(newNet_184), .d(n_226), .o(i_rx_phy_rxdp_s_r_reg_Q) );
ao12f80 g1882_u0 ( .a(n_230), .b(n_132), .c(n_306), .o(n_307) );
in01f80 newInst_304 ( .a(newNet_303), .o(newNet_304) );
in01f80 g56_u0 ( .a(n_916), .o(n_926) );
in01f80 g2601_u0 ( .a(n_885), .o(n_884) );
in01f80 newInst_40 ( .a(newNet_16), .o(newNet_40) );
ms00f80 i_rx_phy_rxd_s0_reg_u0 ( .ck(newNet_217), .d(rxd), .o(i_rx_phy_rxd_s0) );
no02f80 g2140_u0 ( .a(n_49), .b(n_33), .o(n_55) );
ao12f80 g1881_u1 ( .a(g1881_p), .b(i_rx_phy_bit_cnt_2_), .c(n_141), .o(n_142) );
na02f80 g1871_u0 ( .a(n_223), .b(i_rx_phy_rxdn_s_r), .o(n_310) );
in01f80 newInst_271 ( .a(newNet_270), .o(newNet_271) );
in01f80 newInst_123 ( .a(newNet_122), .o(newNet_123) );
in01f80 newInst_99 ( .a(newNet_98), .o(newNet_99) );
in01f80 g2573_u0 ( .a(g2674_p), .o(n_852) );
na02f80 g1852_u0 ( .a(n_304), .b(n_360), .o(n_392) );
in01f80 newInst_82 ( .a(newNet_22), .o(newNet_82) );
na02f80 g2513_u0 ( .a(n_58), .b(n_53), .o(n_759) );
ao12f80 g1856_u0 ( .a(n_339), .b(n_343), .c(i_tx_phy_bit_cnt_2_), .o(n_377) );
in01f80 newInst_284 ( .a(newNet_176), .o(newNet_284) );
in01f80 newInst_227 ( .a(newNet_226), .o(newNet_227) );
in01f80 newInst_91 ( .a(newNet_11), .o(newNet_91) );
in01f80 g1942_u1 ( .a(g1942_p), .o(n_350) );
in01f80 newInst_118 ( .a(newNet_117), .o(newNet_118) );
in01f80 newInst_15 ( .a(newNet_14), .o(newNet_15) );
na02f80 g64_u0 ( .a(n_754), .b(n_509), .o(n_924) );
in01f80 g2253_u0 ( .a(n_21), .o(n_240) );
in01f80 newInst_279 ( .a(newNet_278), .o(newNet_279) );
ms00f80 i_rx_phy_dpll_state_reg_1__u0 ( .ck(newNet_295), .d(n_436), .o(i_rx_phy_dpll_state_1_) );
in01f80 g2130_u1 ( .a(g2130_p), .o(n_150) );
in01f80 newInst_160 ( .a(newNet_159), .o(newNet_160) );
ms00f80 i_tx_phy_hold_reg_d_reg_7__u0 ( .ck(newNet_104), .d(i_tx_phy_hold_reg_10), .o(i_tx_phy_hold_reg_d_17) );
na02f80 g2103_u0 ( .a(rst), .b(n_882), .o(g2103_p) );
in01f80 newInst_189 ( .a(newNet_188), .o(newNet_189) );
in01f80 newInst_182 ( .a(newNet_36), .o(newNet_182) );
na03f80 g54_u0 ( .a(n_492), .b(n_217), .c(n_209), .o(n_915) );
na02f80 g2099_u0 ( .a(n_57), .b(i_tx_phy_bit_cnt_0_), .o(n_168) );
na03f80 g2660_u0 ( .a(n_972), .b(n_894), .c(TxValid_i), .o(n_974) );
na02f80 g1918_u0 ( .a(n_353), .b(n_763), .o(n_354) );
na02f80 g2138_u0 ( .a(i_tx_phy_sd_bs_o), .b(i_tx_phy_sd_nrzi_o), .o(n_35) );
in01f80 newInst_246 ( .a(newNet_245), .o(newNet_246) );
ms00f80 i_rx_phy_hold_reg_reg_7__u0 ( .ck(newNet_248), .d(i_rx_phy_sd_nrzi), .o(DataIn_o_7_) );
na02f80 g2477_u0 ( .a(n_741), .b(n_726), .o(n_727) );
in01f80 newInst_138 ( .a(newNet_137), .o(newNet_138) );
in01f80 g2028_u1 ( .a(g2028_p), .o(n_246) );
na03f80 g2464_u0 ( .a(n_706), .b(n_461), .c(n_511), .o(n_707) );
in01f80 i_rx_phy_byte_err_reg_u1 ( .a(i_rx_phy_byte_err_reg_Q), .o(i_rx_phy_byte_err) );
ms00f80 i_rx_phy_fs_state_reg_0__u0 ( .ck(newNet_283), .d(n_529), .o(i_rx_phy_fs_state_0_) );
in01f80 g1777_u0 ( .a(i_tx_phy_ld_data), .o(g1777_sb) );
no02f80 g2066_u0 ( .a(n_105), .b(n_240), .o(g2066_p) );
ms00f80 i_rx_phy_one_cnt_reg_2__u0 ( .ck(newNet_239), .d(n_962), .o(i_rx_phy_one_cnt_2_) );
in01f80 g2643_u0 ( .a(n_796), .o(n_788) );
ao12f80 g1815_u0 ( .a(n_400), .b(n_154), .c(n_341), .o(n_401) );
na04m80 g1880_u0 ( .a(n_323), .b(n_350), .c(n_737), .d(n_108), .o(n_360) );
in01f80 g2174_u0 ( .a(i_tx_phy_append_eop_sync4), .o(n_7) );
in01f80 newInst_187 ( .a(newNet_186), .o(newNet_187) );
in01f80 newInst_245 ( .a(newNet_204), .o(newNet_245) );
in01f80 newInst_32 ( .a(newNet_0), .o(newNet_32) );
in01f80 newInst_79 ( .a(newNet_60), .o(newNet_79) );
na02f80 g1719_u0 ( .a(n_926), .b(n_982), .o(n_480) );
ms00f80 rst_cnt_reg_3__u0 ( .ck(newNet_6), .d(n_417), .o(rst_cnt_3_) );
no02f80 g10_u0 ( .a(n_911), .b(n_913), .o(n_914) );
in01f80 newInst_85 ( .a(newNet_84), .o(newNet_85) );
na03f80 g32_u0 ( .a(n_743), .b(n_938), .c(n_748), .o(n_749) );
in01f80 newInst_270 ( .a(newNet_0), .o(newNet_270) );
in01f80 FE_RC_3_0 ( .a(rst), .o(FE_RN_2_0) );
ao22s80 g2061_u0 ( .a(i_tx_phy_append_eop_sync1), .b(n_885), .c(i_tx_phy_append_eop_sync2), .d(n_864), .o(n_235) );
ao12f80 g1985_u0 ( .a(n_213), .b(n_852), .c(txoe), .o(n_283) );
in01f80 newInst_116 ( .a(newNet_115), .o(newNet_116) );
in01f80 i_rx_phy_sync_err_reg_u1 ( .a(i_rx_phy_sync_err_reg_Q), .o(i_rx_phy_sync_err) );
in01f80 g2278_u0 ( .a(i_rx_phy_one_cnt_0_), .o(n_53) );
in01f80 g1780_u0 ( .a(i_tx_phy_ld_data), .o(g1780_sb) );
in01f80 newInst_60 ( .a(newNet_59), .o(newNet_60) );
in01f80 g2072_u0 ( .a(i_tx_phy_sft_done_r), .o(n_64) );
na02f80 g2389_u0 ( .a(n_840), .b(n_567), .o(n_573) );
na02f80 g2638_u0 ( .a(n_413), .b(n_424), .o(n_941) );
oa12f80 g1978_u0 ( .a(n_927), .b(n_952), .c(n_224), .o(n_539) );
in01f80 g1980_u1 ( .a(g1980_p), .o(n_222) );
in01f80 newInst_196 ( .a(newNet_195), .o(newNet_196) );
in01f80 g2159_u0 ( .a(n_52), .o(n_120) );
in01f80 newInst_186 ( .a(newNet_185), .o(newNet_186) );
in01f80 g2642_u0 ( .a(i_rx_phy_fs_state_2_), .o(n_947) );
in01f80 newInst_103 ( .a(newNet_102), .o(newNet_103) );
in01f80 newInst_218 ( .a(newNet_82), .o(newNet_218) );
in01f80 newInst_159 ( .a(newNet_129), .o(newNet_159) );
ao12f80 g1709_u0 ( .a(n_370), .b(n_384), .c(rst_cnt_3_), .o(n_386) );
no02f80 g2625_u0 ( .a(n_888), .b(n_661), .o(n_927) );
ms00f80 i_tx_phy_ld_data_reg_u0 ( .ck(newNet_73), .d(n_387), .o(i_tx_phy_ld_data_reg_Q) );
in01f80 newInst_58 ( .a(newNet_57), .o(newNet_58) );
in01f80 newInst_43 ( .a(newNet_42), .o(newNet_43) );
in01f80 newInst_26 ( .a(newNet_25), .o(newNet_26) );
ao12f80 g2068_u1 ( .a(g2068_p), .b(n_353), .c(i_rx_phy_bit_cnt_0_), .o(n_118) );
in01f80 g2042_u0 ( .a(n_175), .o(n_176) );
in01f80 newInst_16 ( .a(newNet_15), .o(newNet_16) );
na02f80 g1814_u0 ( .a(i_tx_phy_hold_reg_10), .b(i_tx_phy_ld_data), .o(n_450) );
no02f80 g2113_u0 ( .a(i_rx_phy_dpll_state_1_), .b(n_60), .o(g2113_p) );
no02f80 g1817_u0 ( .a(n_666), .b(n_540), .o(n_413) );
na03f80 g1973_u0 ( .a(i_tx_phy_hold_reg_d_14), .b(n_192), .c(i_tx_phy_bit_cnt_2_), .o(n_193) );
in01f80 g2487_u0 ( .a(n_735), .o(n_734) );
in01f80 newInst_278 ( .a(newNet_277), .o(newNet_278) );
in01f80 newInst_221 ( .a(newNet_220), .o(newNet_221) );
no02f80 g2412_u0 ( .a(n_481), .b(n_628), .o(g2412_p) );
in01f80 newInst_169 ( .a(newNet_168), .o(newNet_169) );
in01f80 newInst_131 ( .a(newNet_130), .o(newNet_131) );
ms00f80 i_tx_phy_bit_cnt_reg_1__u0 ( .ck(newNet_132), .d(n_394), .o(i_tx_phy_bit_cnt_1_) );
in01f80 newInst_13 ( .a(newNet_12), .o(newNet_13) );
in01f80 newInst_37 ( .a(newNet_36), .o(newNet_37) );
in01f80 g1739_u1 ( .a(g1739_p), .o(n_486) );
no02f80 g2040_u0 ( .a(n_384), .b(n_240), .o(n_241) );
in01f80 newInst_146 ( .a(newNet_104), .o(newNet_146) );
no02f80 g2010_u0 ( .a(n_185), .b(i_tx_phy_sd_nrzi_o), .o(n_186) );
in01f80 newInst_296 ( .a(newNet_91), .o(newNet_296) );
in01f80 g13_u0 ( .a(n_794), .o(n_913) );
in01f80 g2128_u1 ( .a(g2128_p), .o(n_400) );
in01f80 g2504_u0 ( .a(n_753), .o(n_754) );
in01f80 g1653_u0 ( .a(n_632), .o(n_529) );
no02f80 g2137_u0 ( .a(n_53), .b(n_52), .o(n_54) );
in01f80 g2676_u0 ( .a(n_885), .o(n_984) );
in01f80 g51_u0 ( .a(n_583), .o(n_588) );
ms00f80 i_tx_phy_bit_cnt_reg_2__u0 ( .ck(newNet_128), .d(n_415), .o(i_tx_phy_bit_cnt_2_) );
na02f80 g2011_u0 ( .a(n_384), .b(rst_cnt_4_), .o(n_252) );
na02f80 g2677_u0 ( .a(n_710), .b(n_509), .o(n_989) );
na02f80 g2658_u0 ( .a(n_559), .b(i_tx_phy_tx_ip), .o(n_970) );
in01f80 newInst_104 ( .a(newNet_103), .o(newNet_104) );
ms00f80 i_tx_phy_one_cnt_reg_1__u0 ( .ck(newNet_2), .d(n_401), .o(i_tx_phy_one_cnt_1_) );
no02f80 g1707_u0 ( .a(n_472), .b(n_444), .o(n_499) );
no02f80 g1968_u0 ( .a(n_204), .b(FE_RN_2_0), .o(n_288) );
na02f80 g2630_u0 ( .a(n_965), .b(n_932), .o(n_933) );
in01f80 g2661_u0 ( .a(n_971), .o(n_972) );
in01f80 newInst_207 ( .a(newNet_180), .o(newNet_207) );
in01f80 newInst_283 ( .a(newNet_282), .o(newNet_283) );
in01f80 newInst_177 ( .a(newNet_176), .o(newNet_177) );
no02f80 g2651_u0 ( .a(n_139), .b(n_54), .o(g2651_p) );
na02f80 g2668_u0 ( .a(n_980), .b(i_rx_phy_fs_state_2_), .o(n_981) );
in01f80 g1974_u0 ( .a(n_226), .o(n_227) );
in01f80 g1733_u0 ( .a(n_753), .o(n_461) );
in01f80 newInst_83 ( .a(newNet_82), .o(newNet_83) );
no02f80 g2397_u0 ( .a(n_952), .b(n_735), .o(n_598) );
ms00f80 i_tx_phy_hold_reg_reg_0__u0 ( .ck(newNet_101), .d(n_489), .o(i_tx_phy_hold_reg) );
na02f80 g2503_u0 ( .a(n_480), .b(n_742), .o(n_752) );
no02f80 g1884_u0 ( .a(i_tx_phy_one_cnt_2_), .b(n_51), .o(g1884_p) );
na02f80 g2116_u0 ( .a(n_57), .b(n_56), .o(g2116_p) );
ms00f80 i_tx_phy_sft_done_reg_u0 ( .ck(newNet_55), .d(n_293), .o(i_tx_phy_sft_done) );
na02f80 g1760_u0 ( .a(n_446), .b(RxActive_o), .o(n_444) );
na02f80 g1965_u0 ( .a(n_965), .b(n_937), .o(g1965_p) );
in01f80 newInst_124 ( .a(newNet_121), .o(newNet_124) );
no02f80 g2028_u0 ( .a(n_244), .b(n_243), .o(g2028_p) );
in01f80 newInst_259 ( .a(newNet_258), .o(newNet_259) );
na02f80 g2671_u0 ( .a(n_990), .b(n_991), .o(n_992) );
in01f80 newInst_313 ( .a(newNet_312), .o(newNet_313) );
na02f80 g2012_u0 ( .a(n_224), .b(n_183), .o(n_184) );
na02f80 g2093_u0 ( .a(n_910), .b(n_91), .o(n_111) );
ms00f80 i_tx_phy_hold_reg_reg_6__u0 ( .ck(newNet_78), .d(n_482), .o(i_tx_phy_hold_reg_9) );
ms00f80 i_rx_phy_sync_err_reg_u0 ( .ck(newNet_158), .d(n_925), .o(i_rx_phy_sync_err_reg_Q) );
in01f80 g2664_u0 ( .a(n_974), .o(n_977) );
in01f80 g1959_u0 ( .a(n_573), .o(n_322) );
ms00f80 i_tx_phy_hold_reg_d_reg_3__u0 ( .ck(newNet_114), .d(i_tx_phy_hold_reg_6), .o(i_tx_phy_hold_reg_d_reg_3__Q) );
in01f80 newInst_110 ( .a(newNet_71), .o(newNet_110) );
ms00f80 i_tx_phy_hold_reg_reg_1__u0 ( .ck(newNet_100), .d(n_487), .o(i_tx_phy_hold_reg_4) );
in01f80 g2218_u0 ( .a(n_49), .o(n_115) );
in01f80 g1965_u1 ( .a(g1965_p), .o(n_289) );
in01f80 i_tx_phy_hold_reg_d_reg_6__u1 ( .a(i_tx_phy_hold_reg_d_reg_6__Q), .o(n_785) );
na02f80 g2463_u0 ( .a(n_707), .b(n_708), .o(n_709) );
in01f80 newInst_237 ( .a(newNet_236), .o(newNet_237) );
in01f80 newInst_137 ( .a(newNet_136), .o(newNet_137) );
no02f80 g33_u0 ( .a(i_tx_phy_data_done), .b(n_929), .o(n_593) );
no02f80 g41_u0 ( .a(n_588), .b(n_888), .o(g41_p) );
na02f80 g15_u0 ( .a(n_948), .b(n_796), .o(g15_p) );
in01f80 newInst_24 ( .a(newNet_23), .o(newNet_24) );
ms00f80 i_rx_phy_hold_reg_reg_2__u0 ( .ck(newNet_269), .d(DataIn_o_3_), .o(DataIn_o_2_) );
na02f80 g1876_u0 ( .a(n_278), .b(n_297), .o(n_361) );
in01f80 newInst_291 ( .a(newNet_224), .o(newNet_291) );
in01f80 newInst_277 ( .a(newNet_271), .o(newNet_277) );
in01f80 newInst_86 ( .a(newNet_85), .o(newNet_86) );
in01f80 newInst_117 ( .a(newNet_116), .o(newNet_117) );
na02f80 g2016_u0 ( .a(n_384), .b(n_105), .o(n_251) );
in01f80 g2634_u0 ( .a(n_932), .o(n_937) );
ms00f80 i_rx_phy_bit_cnt_reg_1__u0 ( .ck(newNet_311), .d(n_405), .o(n_353) );
no02f80 g2131_u0 ( .a(n_70), .b(n_69), .o(n_71) );
na02f80 g1913_u0 ( .a(n_343), .b(i_tx_phy_bit_cnt_0_), .o(n_332) );
in01f80 newInst_48 ( .a(newNet_24), .o(newNet_48) );
na02f80 g1743_u0 ( .a(n_452), .b(n_974), .o(g1743_p) );
in01f80 g2141_u1 ( .a(g2141_p), .o(n_185) );
in01f80 newInst_171 ( .a(newNet_170), .o(newNet_171) );
ao22s80 g2624_u0 ( .a(n_927), .b(n_928), .c(n_934), .d(n_929), .o(n_935) );
no02f80 g1680_u0 ( .a(n_386), .b(n_416), .o(n_417) );
ms00f80 i_rx_phy_bit_cnt_reg_2__u0 ( .ck(newNet_306), .d(n_414), .o(i_rx_phy_bit_cnt_2_) );
in01f80 g1702_u0 ( .a(n_404), .o(n_423) );
na03f80 g40_u0 ( .a(n_559), .b(n_734), .c(n_927), .o(n_963) );
na02f80 g1902_u0 ( .a(i_rx_phy_bit_cnt_2_), .b(n_763), .o(n_359) );
in01f80 newInst_301 ( .a(newNet_300), .o(newNet_301) );
in01f80 newInst_55 ( .a(newNet_54), .o(newNet_55) );
oa12f80 g1878_u0 ( .a(n_351), .b(n_290), .c(n_583), .o(n_387) );
in01f80 newInst_213 ( .a(newNet_212), .o(newNet_213) );
in01f80 newInst_6 ( .a(newNet_2), .o(newNet_6) );
na02f80 g34_u0 ( .a(n_873), .b(n_139), .o(n_960) );
in01f80 newInst_170 ( .a(newNet_169), .o(newNet_170) );
ms00f80 i_tx_phy_data_done_reg_u0 ( .ck(newNet_123), .d(n_166), .o(i_tx_phy_data_done) );
oa12f80 g1748_u0 ( .a(n_447), .b(n_9), .c(n_885), .o(n_471) );
no02f80 g14_u0 ( .a(n_788), .b(n_981), .o(n_604) );
in01f80 newInst_162 ( .a(newNet_161), .o(newNet_162) );
in01f80 g1737_u1 ( .a(g1737_p), .o(n_489) );
ms00f80 i_rx_phy_rx_active_reg_u0 ( .ck(newNet_238), .d(n_709), .o(RxActive_o) );
ms00f80 i_tx_phy_txoe_r2_reg_u0 ( .ck(newNet_27), .d(n_291), .o(i_tx_phy_txoe_r2) );
in01f80 newInst_267 ( .a(newNet_266), .o(newNet_267) );
in01f80 g2113_u1 ( .a(g2113_p), .o(n_389) );
in01f80 newInst_96 ( .a(newNet_73), .o(newNet_96) );
ao12f80 g1843_u0 ( .a(n_400), .b(n_332), .c(n_301), .o(n_395) );
no03m80 g2644_u0 ( .a(n_929), .b(n_952), .c(n_735), .o(n_583) );
no03m80 g2014_u0 ( .a(i_tx_phy_txoe_r2), .b(i_tx_phy_txoe_r1), .c(n_864), .o(n_213) );
na02f80 g1903_u0 ( .a(n_289), .b(n_165), .o(n_304) );
ms00f80 i_rx_phy_rxd_s_reg_u0 ( .ck(newNet_211), .d(n_229), .o(i_rx_phy_rxd_s) );
ao12f80 g1884_u1 ( .a(g1884_p), .b(i_tx_phy_one_cnt_2_), .c(n_51), .o(n_138) );
no02f80 g1956_u0 ( .a(n_929), .b(n_965), .o(n_323) );
ms00f80 i_tx_phy_one_cnt_reg_2__u0 ( .ck(newNet_67), .d(n_388), .o(i_tx_phy_one_cnt_2_) );
na02f80 g1781_u3 ( .a(g1781_da), .b(g1781_db), .o(n_453) );
in01f80 newInst_132 ( .a(newNet_131), .o(newNet_132) );
in01f80 g1743_u1 ( .a(g1743_p), .o(n_482) );
no02f80 g2123_u0 ( .a(n_57), .b(n_56), .o(n_125) );
in01f80 newInst_145 ( .a(newNet_144), .o(newNet_145) );
in01f80 newInst_93 ( .a(newNet_92), .o(newNet_93) );
in01f80 newInst_289 ( .a(newNet_288), .o(newNet_289) );
in01f80 g1731_u0 ( .a(n_754), .o(n_490) );
in01f80 newInst_84 ( .a(newNet_83), .o(newNet_84) );
in01f80 g2568_u0 ( .a(n_841), .o(n_840) );
ms00f80 i_tx_phy_txdn_reg_u0 ( .ck(newNet_39), .d(n_364), .o(txdn) );
na02f80 g2118_u0 ( .a(TxValid_i), .b(rst), .o(n_164) );
na02f80 g1776_u1 ( .a(DataOut_i_0_), .b(g1776_sb), .o(g1776_da) );
ms00f80 i_rx_phy_rx_valid_reg_u0 ( .ck(newNet_224), .d(n_373), .o(RxValid_o) );
no02f80 g2100_u0 ( .a(n_878), .b(RxActive_o), .o(n_61) );
in01f80 newInst_128 ( .a(newNet_127), .o(newNet_128) );
in01f80 i_tx_phy_ld_data_reg_u1 ( .a(i_tx_phy_ld_data_reg_Q), .o(i_tx_phy_ld_data) );
in01f80 newInst_25 ( .a(newNet_24), .o(newNet_25) );
ao12f80 g1729_u0 ( .a(n_961), .b(n_359), .c(n_347), .o(n_414) );
ao22s80 g2060_u0 ( .a(i_tx_phy_append_eop), .b(g2674_p), .c(i_tx_phy_append_eop_sync1), .d(n_984), .o(n_237) );
na02f80 g1779_u1 ( .a(DataOut_i_3_), .b(g1779_sb), .o(g1779_da) );
ao12f80 g1877_u0 ( .a(n_228), .b(n_254), .c(i_tx_phy_bit_cnt_2_), .o(n_337) );
in01f80 g2108_u1 ( .a(g2108_p), .o(n_155) );
in01f80 g2106_u0 ( .a(n_598), .o(n_661) );
in01f80 newInst_208 ( .a(newNet_207), .o(newNet_208) );
in01f80 newInst_52 ( .a(newNet_38), .o(newNet_52) );
in01f80 g2116_u1 ( .a(g2116_p), .o(n_192) );
na02f80 g1757_u0 ( .a(n_969), .b(rst), .o(g1757_p) );
in01f80 g1781_u0 ( .a(i_tx_phy_ld_data), .o(g1781_sb) );
in01f80 g1782_u0 ( .a(i_tx_phy_ld_data), .o(g1782_sb) );
in01f80 newInst_105 ( .a(newNet_3), .o(newNet_105) );
in01f80 newInst_0 ( .a(tau_clk), .o(newNet_0) );
ms00f80 i_tx_phy_state_reg_0__u0 ( .ck(newNet_51), .d(n_459), .o(n_929) );
no02f80 g1921_u0 ( .a(n_255), .b(i_tx_phy_bit_cnt_2_), .o(n_300) );
in01f80 g2460_u0 ( .a(n_703), .o(n_704) );
na02f80 g1807_u0 ( .a(n_142), .b(n_764), .o(n_347) );
in01f80 newInst_70 ( .a(newNet_69), .o(newNet_70) );
na03f80 g1894_u0 ( .a(g2674_p), .b(n_170), .c(rst), .o(n_273) );
na03f80 g57_u0 ( .a(n_666), .b(i_rx_phy_rxdn_s), .c(i_rx_phy_rx_en), .o(n_916) );
na03f80 g2636_u0 ( .a(n_112), .b(n_940), .c(n_942), .o(n_943) );
ms00f80 i_rx_phy_rxdn_s_r_reg_u0 ( .ck(newNet_200), .d(n_222), .o(i_rx_phy_rxdn_s_r_reg_Q) );
in01f80 g2226_u0 ( .a(n_91), .o(n_74) );
ao12f80 g1661_u0 ( .a(FE_RN_2_0), .b(n_506), .c(n_660), .o(n_523) );
ao12f80 g1758_u0 ( .a(n_318), .b(n_538), .c(n_539), .o(n_432) );
ms00f80 i_rx_phy_hold_reg_reg_5__u0 ( .ck(newNet_257), .d(DataIn_o_6_), .o(DataIn_o_5_) );
in01f80 newInst_247 ( .a(newNet_246), .o(newNet_247) );
in01f80 g1905_u0 ( .a(n_416), .o(n_269) );
no02f80 g2128_u0 ( .a(n_27), .b(n_318), .o(g2128_p) );
in01f80 g2178_u0 ( .a(n_56), .o(n_77) );
no02f80 g2136_u0 ( .a(n_21), .b(n_22), .o(n_66) );
na02f80 g31_u0 ( .a(n_957), .b(n_958), .o(n_959) );
ms00f80 i_rx_phy_bit_cnt_reg_0__u0 ( .ck(newNet_313), .d(n_407), .o(i_rx_phy_bit_cnt_0_) );
in01f80 newInst_87 ( .a(newNet_33), .o(newNet_87) );
na02f80 g1703_u0 ( .a(n_380), .b(n_269), .o(n_404) );
na04m80 g2628_u0 ( .a(n_735), .b(n_984), .c(n_952), .d(n_929), .o(n_930) );
in01f80 newInst_76 ( .a(newNet_75), .o(newNet_76) );
ao22s80 g2065_u0 ( .a(n_238), .b(g2674_p), .c(i_tx_phy_txoe_r1), .d(n_984), .o(n_233) );
in01f80 newInst_14 ( .a(newNet_0), .o(newNet_14) );
ms00f80 i_tx_phy_hold_reg_d_reg_6__u0 ( .ck(newNet_105), .d(i_tx_phy_hold_reg_9), .o(i_tx_phy_hold_reg_d_reg_6__Q) );
in01f80 g11_u1 ( .a(g11_p), .o(n_911) );
in01f80 newInst_222 ( .a(newNet_221), .o(newNet_222) );
in01f80 newInst_265 ( .a(newNet_4), .o(newNet_265) );
in01f80 newInst_11 ( .a(newNet_0), .o(newNet_11) );
in01f80 newInst_193 ( .a(newNet_192), .o(newNet_193) );
in01f80 newInst_175 ( .a(newNet_174), .o(newNet_175) );
in01f80 newInst_45 ( .a(newNet_44), .o(newNet_45) );
in01f80 newInst_238 ( .a(newNet_237), .o(newNet_238) );
in01f80 newInst_311 ( .a(newNet_310), .o(newNet_311) );
na02f80 g1696_u0 ( .a(n_938), .b(n_480), .o(n_481) );
in01f80 newInst_215 ( .a(newNet_214), .o(newNet_215) );
na02f80 g1717_u0 ( .a(n_916), .b(n_74), .o(n_439) );
in01f80 newInst_180 ( .a(newNet_179), .o(newNet_180) );
in01f80 newInst_178 ( .a(newNet_177), .o(newNet_178) );
no02f80 g2135_u0 ( .a(n_37), .b(n_18), .o(n_141) );
na02f80 g1867_u0 ( .a(n_121), .b(n_958), .o(n_375) );
in01f80 g2162_u0 ( .a(rst_cnt_4_), .o(n_11) );
in01f80 newInst_164 ( .a(newNet_107), .o(newNet_164) );
no02f80 g1857_u0 ( .a(n_155), .b(RxValid_o), .o(g1857_p) );
in01f80 g2595_u0 ( .a(n_885), .o(n_878) );
in01f80 newInst_206 ( .a(newNet_205), .o(newNet_206) );
in01f80 newInst_172 ( .a(newNet_48), .o(newNet_172) );
ms00f80 i_tx_phy_hold_reg_d_reg_2__u0 ( .ck(newNet_118), .d(i_tx_phy_hold_reg_5), .o(i_tx_phy_hold_reg_d_12) );
no02f80 g1899_u0 ( .a(n_258), .b(n_984), .o(n_340) );
ao12f80 g39_u0 ( .a(n_977), .b(n_840), .c(n_567), .o(n_699) );
na02f80 g1915_u0 ( .a(n_343), .b(n_15), .o(n_344) );
na02f80 g1764_u0 ( .a(n_767), .b(n_410), .o(n_431) );
in01f80 g2172_u0 ( .a(n_22), .o(n_105) );
in01f80 newInst_67 ( .a(newNet_66), .o(newNet_67) );
in01f80 newInst_262 ( .a(newNet_261), .o(newNet_262) );
in01f80 newInst_290 ( .a(newNet_289), .o(newNet_290) );
ms00f80 usb_rst_reg_u0 ( .ck(newNet_70), .d(n_275), .o(usb_rst) );
na04m80 g1858_u0 ( .a(n_195), .b(n_238), .c(rst), .d(i_tx_phy_txoe_r1), .o(n_276) );
in01f80 newInst_34 ( .a(newNet_33), .o(newNet_34) );
in01f80 newInst_77 ( .a(newNet_76), .o(newNet_77) );
in01f80 g2275_u0 ( .a(i_rx_phy_rxd_s), .o(n_243) );
ms00f80 i_tx_phy_state_reg_1__u0 ( .ck(newNet_47), .d(n_420), .o(i_tx_phy_state_1_) );
in01f80 g1860_u0 ( .a(n_197), .o(n_198) );
na02f80 g1919_u0 ( .a(i_rx_phy_bit_cnt_0_), .b(n_763), .o(n_355) );
in01f80 g2593_u0 ( .a(n_885), .o(n_873) );
in01f80 newInst_285 ( .a(newNet_230), .o(newNet_285) );
ao12f80 g2052_u0 ( .a(i_tx_phy_append_eop_sync2), .b(n_7), .c(n_48), .o(n_123) );
in01f80 newInst_302 ( .a(newNet_140), .o(newNet_302) );
in01f80 newInst_276 ( .a(newNet_275), .o(newNet_276) );
in01f80 newInst_98 ( .a(newNet_97), .o(newNet_98) );
in01f80 g2584_u0 ( .a(n_885), .o(n_864) );
in01f80 newInst_27 ( .a(newNet_26), .o(newNet_27) );
in01f80 newInst_212 ( .a(newNet_147), .o(newNet_212) );
in01f80 g1991_u0 ( .a(n_66), .o(n_132) );
in01f80 newInst_113 ( .a(newNet_112), .o(newNet_113) );
no02f80 g1822_u0 ( .a(n_424), .b(n_665), .o(n_425) );
in01f80 newInst_56 ( .a(newNet_15), .o(newNet_56) );
ms00f80 i_tx_phy_hold_reg_reg_7__u0 ( .ck(newNet_74), .d(n_507), .o(i_tx_phy_hold_reg_10) );
na02f80 g1781_u1 ( .a(DataOut_i_5_), .b(g1781_sb), .o(g1781_da) );
in01f80 newInst_136 ( .a(newNet_135), .o(newNet_136) );
in01f80 newInst_39 ( .a(newNet_38), .o(newNet_39) );
na04m80 g1824_u0 ( .a(n_764), .b(i_rx_phy_bit_cnt_2_), .c(rst), .d(n_141), .o(n_410) );
na02f80 g2029_u0 ( .a(n_244), .b(n_243), .o(n_245) );
na02f80 g2662_u0 ( .a(n_735), .b(n_951), .o(n_971) );
in01f80 i_rx_phy_rxdp_s_r_reg_u1 ( .a(i_rx_phy_rxdp_s_r_reg_Q), .o(i_rx_phy_rxdp_s_r) );
no02f80 g1869_u0 ( .a(n_313), .b(n_416), .o(n_362) );
in01f80 newInst_158 ( .a(newNet_157), .o(newNet_158) );
in01f80 newInst_184 ( .a(newNet_183), .o(newNet_184) );
in01f80 newInst_90 ( .a(newNet_89), .o(newNet_90) );
in01f80 newInst_205 ( .a(newNet_204), .o(newNet_205) );
in01f80 g2224_u0 ( .a(n_28), .o(n_139) );
no02f80 g2141_u0 ( .a(n_8), .b(n_984), .o(g2141_p) );
in01f80 newInst_5 ( .a(newNet_4), .o(newNet_5) );
na02f80 g2466_u0 ( .a(n_461), .b(n_511), .o(n_710) );
na03f80 g2497_u0 ( .a(n_112), .b(n_788), .c(n_942), .o(n_748) );
in01f80 newInst_8 ( .a(newNet_7), .o(newNet_8) );
in01f80 g2160_u0 ( .a(i_rx_phy_one_cnt_1_), .o(n_52) );
na02f80 g1987_u0 ( .a(n_246), .b(n_245), .o(n_312) );
na02f80 g2036_u0 ( .a(n_125), .b(n_124), .o(n_231) );
na04m80 g1747_u0 ( .a(n_248), .b(n_266), .c(n_426), .d(i_rx_phy_sd_nrzi), .o(n_479) );
na02f80 g1780_u1 ( .a(DataOut_i_4_), .b(g1780_sb), .o(g1780_da) );
na02f80 g1820_u0 ( .a(n_424), .b(n_666), .o(n_426) );
na02f80 g20_u0 ( .a(n_852), .b(i_rx_phy_shift_en), .o(n_991) );
in01f80 newInst_151 ( .a(newNet_113), .o(newNet_151) );
no02f80 g1966_u0 ( .a(n_237), .b(n_318), .o(n_317) );
ao12f80 g1763_u0 ( .a(n_400), .b(n_163), .c(n_342), .o(n_388) );
in01f80 newInst_229 ( .a(newNet_68), .o(newNet_229) );
in01f80 g1901_u1 ( .a(g1901_p), .o(n_373) );
in01f80 newInst_163 ( .a(newNet_162), .o(newNet_163) );
in01f80 newInst_192 ( .a(newNet_118), .o(newNet_192) );
in01f80 g1855_u0 ( .a(n_274), .o(g1855_sb) );
in01f80 g2251_u0 ( .a(i_tx_phy_data_done), .o(n_10) );
in01f80 g2646_u0 ( .a(i_tx_phy_state_2_), .o(n_951) );
na02f80 g1842_u0 ( .a(n_308), .b(rst), .o(n_366) );
na02f80 g1779_u2 ( .a(i_tx_phy_hold_reg_6), .b(i_tx_phy_ld_data), .o(g1779_db) );
ms00f80 i_rx_phy_one_cnt_reg_0__u0 ( .ck(newNet_244), .d(n_406), .o(i_rx_phy_one_cnt_0_) );
in01f80 newInst_258 ( .a(newNet_163), .o(newNet_258) );
ms00f80 i_tx_phy_sd_raw_o_reg_u0 ( .ck(newNet_61), .d(n_411), .o(i_tx_phy_sd_raw_o) );
na03f80 g1875_u0 ( .a(n_390), .b(i_rx_phy_dpll_state_1_), .c(n_60), .o(n_435) );
in01f80 g2670_u0 ( .a(i_rx_phy_fs_state_2_), .o(n_910) );
in01f80 newInst_250 ( .a(newNet_249), .o(newNet_250) );
in01f80 newInst_75 ( .a(newNet_61), .o(newNet_75) );
ms00f80 i_rx_phy_rxdp_s0_reg_u0 ( .ck(newNet_191), .d(rxdp), .o(i_rx_phy_rxdp_s0) );
in01f80 g2063_u0 ( .a(n_852), .o(g2063_sb) );
in01f80 g1757_u1 ( .a(g1757_p), .o(n_420) );
in01f80 newInst_251 ( .a(newNet_250), .o(newNet_251) );
ao12f80 g1844_u0 ( .a(n_400), .b(n_344), .c(n_294), .o(n_394) );
in01f80 newInst_194 ( .a(newNet_193), .o(newNet_194) );
na04m80 g36_u0 ( .a(n_699), .b(n_700), .c(n_701), .d(n_968), .o(n_703) );
in01f80 newInst_310 ( .a(newNet_309), .o(newNet_310) );
in01f80 newInst_280 ( .a(newNet_279), .o(newNet_280) );
in01f80 newInst_286 ( .a(newNet_285), .o(newNet_286) );
in01f80 newInst_161 ( .a(newNet_160), .o(newNet_161) );
in01f80 newInst_115 ( .a(newNet_48), .o(newNet_115) );
in01f80 newInst_120 ( .a(newNet_119), .o(newNet_120) );
ms00f80 rst_cnt_reg_1__u0 ( .ck(newNet_13), .d(n_367), .o(rst_cnt_1_) );
oa12f80 g1984_u0 ( .a(n_172), .b(i_tx_phy_hold_reg_d_15), .c(n_168), .o(n_254) );
na02f80 g2063_u1 ( .a(n_130), .b(g2063_sb), .o(g2063_da) );
in01f80 g2537_u0 ( .a(n_965), .o(n_800) );
na03f80 g1711_u0 ( .a(n_782), .b(n_176), .c(n_783), .o(n_493) );
na03f80 g1728_u0 ( .a(n_974), .b(n_462), .c(n_450), .o(n_507) );
in01f80 g2186_u0 ( .a(i_tx_phy_bit_cnt_1_), .o(n_57) );
in01f80 g2254_u0 ( .a(rst_cnt_0_), .o(n_21) );
ms00f80 rst_cnt_reg_2__u0 ( .ck(newNet_10), .d(n_428), .o(n_306) );
ms00f80 i_tx_phy_txoe_r1_reg_u0 ( .ck(newNet_31), .d(n_320), .o(i_tx_phy_txoe_r1) );
ms00f80 i_rx_phy_rxd_r_reg_u0 ( .ck(newNet_222), .d(n_130), .o(i_rx_phy_rxd_r) );
ao12f80 g2067_u1 ( .a(g2067_p), .b(n_120), .c(i_rx_phy_one_cnt_0_), .o(n_121) );
ao12f80 g2651_u1 ( .a(g2651_p), .b(n_139), .c(n_54), .o(n_957) );
in01f80 newInst_223 ( .a(newNet_88), .o(newNet_223) );
in01f80 newInst_61 ( .a(newNet_2), .o(newNet_61) );
na04m80 g2654_u0 ( .a(n_963), .b(n_966), .c(n_967), .d(n_968), .o(n_969) );
na02f80 g1904_u0 ( .a(n_283), .b(rst), .o(n_333) );
in01f80 newInst_95 ( .a(newNet_94), .o(newNet_95) );
in01f80 g2225_u0 ( .a(i_rx_phy_one_cnt_2_), .o(n_28) );
in01f80 newInst_244 ( .a(newNet_243), .o(newNet_244) );
in01f80 g2194_u0 ( .a(i_tx_phy_bit_cnt_2_), .o(n_124) );
in01f80 newInst_127 ( .a(newNet_126), .o(newNet_127) );
in01f80 g2158_u0 ( .a(phy_tx_mode), .o(n_8) );
in01f80 g2506_u1 ( .a(g2506_p), .o(n_756) );
in01f80 newInst_41 ( .a(newNet_40), .o(newNet_41) );
ao22s80 g2064_u0 ( .a(i_tx_phy_txoe_r2), .b(n_852), .c(i_tx_phy_txoe_r1), .d(g2674_p), .o(n_201) );
in01f80 newInst_38 ( .a(newNet_37), .o(newNet_38) );
ms00f80 i_rx_phy_hold_reg_reg_4__u0 ( .ck(newNet_262), .d(DataIn_o_5_), .o(DataIn_o_4_) );
ms00f80 i_tx_phy_bit_cnt_reg_0__u0 ( .ck(newNet_133), .d(n_395), .o(i_tx_phy_bit_cnt_0_) );
na02f80 g2494_u0 ( .a(n_741), .b(n_742), .o(g2494_p) );
in01f80 newInst_264 ( .a(newNet_263), .o(newNet_264) );
in01f80 newInst_239 ( .a(newNet_204), .o(newNet_239) );
na02f80 g1759_u0 ( .a(n_446), .b(g2674_p), .o(n_447) );
na02f80 g1809_u0 ( .a(n_198), .b(rst_cnt_3_), .o(n_292) );
in01f80 newInst_275 ( .a(newNet_266), .o(newNet_275) );
ao12f80 g1841_u0 ( .a(n_961), .b(n_355), .c(n_331), .o(n_407) );
in01f80 i_rx_phy_se0_r_reg_u1 ( .a(i_rx_phy_se0_r_reg_Q), .o(i_rx_phy_se0_r) );
ms00f80 i_rx_phy_sd_r_reg_u0 ( .ck(newNet_173), .d(n_203), .o(i_rx_phy_sd_r) );
na02f80 g1849_u0 ( .a(n_138), .b(n_340), .o(n_342) );
ms00f80 i_tx_phy_hold_reg_d_reg_1__u0 ( .ck(newNet_120), .d(i_tx_phy_hold_reg_4), .o(i_tx_phy_hold_reg_d_reg_1__Q) );
ao12f80 g2650_u0 ( .a(n_961), .b(n_959), .c(n_960), .o(n_962) );
ms00f80 i_rx_phy_fs_state_reg_1__u0 ( .ck(newNet_280), .d(n_523), .o(n_796) );
na02f80 g1917_u0 ( .a(n_930), .b(n_841), .o(n_330) );
no02f80 g1881_u0 ( .a(i_rx_phy_bit_cnt_2_), .b(n_141), .o(g1881_p) );
in01f80 g2051_u0 ( .a(n_123), .o(n_170) );
ms00f80 i_rx_phy_rxdp_s1_reg_u0 ( .ck(newNet_187), .d(i_rx_phy_rxdp_s0), .o(LineState_o_0_) );
in01f80 g2129_u0 ( .a(n_150), .o(n_266) );
in01f80 newInst_309 ( .a(newNet_308), .o(newNet_309) );
no02f80 g1874_u0 ( .a(n_390), .b(n_389), .o(n_391) );
no02f80 g2620_u0 ( .a(n_923), .b(n_924), .o(n_925) );
in01f80 newInst_31 ( .a(newNet_30), .o(newNet_31) );
na02f80 g1737_u0 ( .a(n_458), .b(n_974), .o(g1737_p) );
ms00f80 i_rx_phy_fs_ce_r1_reg_u0 ( .ck(newNet_290), .d(n_81), .o(i_rx_phy_fs_ce_r1) );
in01f80 newInst_228 ( .a(newNet_227), .o(newNet_228) );
ms00f80 i_tx_phy_state_reg_2__u0 ( .ck(newNet_46), .d(n_432), .o(i_tx_phy_state_2_) );
in01f80 g2494_u1 ( .a(g2494_p), .o(n_743) );
in01f80 newInst_293 ( .a(newNet_292), .o(newNet_293) );
no02f80 g1908_u0 ( .a(n_132), .b(n_306), .o(n_230) );
ao12f80 g1848_u0 ( .a(n_400), .b(n_161), .c(n_299), .o(n_378) );
in01f80 newInst_166 ( .a(newNet_165), .o(newNet_166) );
in01f80 newInst_47 ( .a(newNet_21), .o(newNet_47) );
in01f80 newInst_147 ( .a(newNet_146), .o(newNet_147) );
ao12f80 g1812_u0 ( .a(n_961), .b(n_152), .c(n_375), .o(n_427) );
no02f80 g44_u0 ( .a(n_971), .b(n_894), .o(n_965) );
ao12f80 g2621_u0 ( .a(n_922), .b(n_915), .c(n_916), .o(n_923) );
in01f80 newInst_199 ( .a(newNet_198), .o(newNet_199) );
in01f80 newInst_44 ( .a(newNet_43), .o(newNet_44) );
ao12f80 g2055_u0 ( .a(n_164), .b(n_10), .c(i_tx_phy_tx_ip), .o(n_166) );
in01f80 g2674_u0 ( .a(n_984), .o(g2674_p) );
ms00f80 i_rx_phy_bit_stuff_err_reg_u0 ( .ck(newNet_302), .d(n_505), .o(i_rx_phy_bit_stuff_err_reg_Q) );
in01f80 newInst_191 ( .a(newNet_190), .o(newNet_191) );
in01f80 newInst_299 ( .a(newNet_298), .o(newNet_299) );
in01f80 newInst_253 ( .a(newNet_252), .o(newNet_253) );
in01f80 newInst_66 ( .a(newNet_65), .o(newNet_66) );
na02f80 g1953_u0 ( .a(n_759), .b(i_rx_phy_sd_nrzi), .o(n_324) );
no02f80 g2067_u0 ( .a(n_120), .b(i_rx_phy_one_cnt_0_), .o(g2067_p) );
in01f80 g15_u1 ( .a(g15_p), .o(n_949) );
na02f80 g1777_u1 ( .a(DataOut_i_1_), .b(g1777_sb), .o(g1777_da) );
in01f80 newInst_152 ( .a(newNet_151), .o(newNet_152) );
in01f80 newInst_78 ( .a(newNet_77), .o(newNet_78) );
na02f80 g2415_u0 ( .a(n_753), .b(n_74), .o(n_631) );
in01f80 g1778_u0 ( .a(i_tx_phy_ld_data), .o(g1778_sb) );
in01f80 newInst_9 ( .a(newNet_8), .o(newNet_9) );
na02f80 g1740_u0 ( .a(n_455), .b(n_974), .o(g1740_p) );
na02f80 g1855_u3 ( .a(g1855_da), .b(g1855_db), .o(n_311) );
in01f80 g2038_u0 ( .a(n_604), .o(n_209) );
in01f80 newInst_185 ( .a(newNet_87), .o(newNet_185) );
na02f80 g1777_u3 ( .a(g1777_da), .b(g1777_db), .o(n_457) );
in01f80 newInst_230 ( .a(newNet_229), .o(newNet_230) );
na02f80 g1901_u0 ( .a(n_764), .b(i_rx_phy_rx_valid1), .o(g1901_p) );
ao12f80 g1736_u0 ( .a(n_27), .b(n_369), .c(n_337), .o(n_411) );
na02f80 g1738_u0 ( .a(n_457), .b(n_974), .o(g1738_p) );
in01f80 g2164_u0 ( .a(n_238), .o(n_27) );
in01f80 newInst_220 ( .a(newNet_219), .o(newNet_220) );
ms00f80 i_rx_phy_shift_en_reg_u0 ( .ck(newNet_163), .d(n_992), .o(i_rx_phy_shift_en) );
ms00f80 i_tx_phy_txoe_reg_u0 ( .ck(newNet_22), .d(n_333), .o(txoe) );
na02f80 g1779_u3 ( .a(g1779_da), .b(g1779_db), .o(n_455) );
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2111AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__O2111AI_BEHAVIORAL_PP_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o2111ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
// Local signals
wire C1 or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, B1, D1, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2111AI_BEHAVIORAL_PP_V |
///2016/8/6
///ShaoMin Zhai
///module function: used to debug core
`include "define.v"
module top_level(
clk,
rst
);
input clk;
input rst;
wire [31:0] pc;
wire [31:0] mem_data;
wire [31:0] mem_addr;
wire [3:0] mem_head;
wire v_mem;
wire v_pc;
wire [31:0] data;
wire v_data;
wire [31:0] inst;
wire v_inst;
core core_du(//input
.clk(clk),
.rst(rst),
.v_inst(v_inst),
.inst(inst),
.v_data(v_data),
.data(data),
//output
.pc(pc),
.v_pc(v_pc),
.v_mem(v_mem),
.mem_head(mem_head),
.mem_addr(mem_addr),
.mem_data(mem_data)
);
instmem instmem_du(
.clk(clk),
.rst(rst),
.pc(pc),
.read(v_pc),
.inst(inst),
.v_inst(v_inst)
);
datamem datamem_du(
.clk(clk),
.rst(rst),
.addr(mem_addr),
.data_in(mem_data),
.r_w(mem_head[3]),
.v_cmd(v_mem),
.data_out(data),
.v_data_out(v_data)
);
endmodule |
module modexp_test_1_N();
parameter N = 8;
parameter CC = N;
reg clk;
reg rst1;
reg rst2;
reg [N-1:0] m;
reg [N-1:0] e;
reg [N-1:0] d;
reg [N-1:0] n;
wire [N-1:0] c;
reg [N-1:0] creg;
wire [N-1:0] mout;
function [N-1:0] modexp_f;
input [N-1:0] m;
input [N-1:0] e;
input [N-1:0] n;
reg [2*N-1:0] mm;
integer i, start;
begin
$display("modexp_f: m =%d e =%d n=%d", m, e, n);
start = -1;
for(i=N-1;i>=0;i=i-1)
begin
if(e[i] && start == -1)
begin
start = i;
end
end
modexp_f = m;
$display("%d", modexp_f);
for(i=start-1;i>=0;i=i-1)
begin
mm = modexp_f;
mm = mm*mm;
modexp_f = mm%n;
$display("%d", modexp_f);
if(e[i])
begin
mm = modexp_f;
mm = mm * m;
modexp_f = mm%n;
$display("* %d", modexp_f);
end
end
end
endfunction
modexp
#(
.N(N),
.CC(CC)
)
UUT1
(
.clk(clk),
.rst(rst1),
.m(m),
.e(e),
.n(n),
.c(c)
);
modexp
#(
.N(N),
.CC(CC)
)
UUT2
(
.clk(clk),
.rst(rst2),
.m(creg),
.e(d),
.n(n),
.c(mout)
);
integer i;
initial
begin
m = 'd106;
e = 'd11;
//e = 8'b1111_1111;
//e = 8'b0011_1100;
//e = 8'b1000_0001;
d = 'd35;
n = 'd221;
creg = 0;
$display("m = %d", m);
$display("e = %d", e);
$display("d = %d", d);
$display("n = %d", n);
clk = 0;
rst1 = 1;
rst2 = 1;
@(negedge clk);
rst1 = 0;
for(i=0;i<CC-1;i=i+1)
@(negedge clk);
$display("c = %d, modexp_f = %d", c, modexp_f(m,e,n));
$display("------------");
creg = c;
@(negedge clk);
@(negedge clk);
@(negedge clk);
rst1 = 1;
rst2 = 0;
for(i=0;i<CC-1;i=i+1)
@(negedge clk);
$display("mout = %d, modexp_f = %d", mout, modexp_f(creg,d,n));
if(mout == m)
$display("Correct!", mout);
else
$display("Error!", mout);
@(negedge clk);
rst2 = 1;
$stop;
end
always #5 clk=~clk;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD1_BLACKBOX_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD1_BLACKBOX_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv3sd1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD1_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04.03.2016 14:20:17
// Design Name:
// Module Name: LUT_Z
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LUT_Z#(parameter P = 32, parameter D = 5) (
input wire CLK,
input wire EN_ROM1,
input wire [D-1:0] ADRS,
output reg [P-1:0] O_D
);
always @(posedge CLK)
if (EN_ROM1)
case (ADRS)
5'b00000: O_D <= 32'b10111111100011001001111101010100;
5'b00001: O_D <= 32'b10111111000000101100010101111000;
5'b00010: O_D <= 32'b10111110100000001010110001001001;
5'b00011: O_D <= 32'b10111110000000000010101011000100;
5'b00100: O_D <= 32'b10111110000000000010101011000100;
5'b00101: O_D <= 32'b10111101100000000000101010101100;
5'b00110: O_D <= 32'b10111101000000000000001010101011;
5'b00111: O_D <= 32'b10111100100000000000000010101011;
5'b01000: O_D <= 32'b10111100000000000000000000101011;
5'b01001: O_D <= 32'b10111011010111100011010101000010;
5'b01010: O_D <= 32'b10111011000000000000000000000011;
5'b01011: O_D <= 32'b10111010100000000000000000000001;
5'b01100: O_D <= 32'b10111010000000000000000000000000;
5'b01101: O_D <= 32'b10111001100000000000000000000000;
5'b01110: O_D <= 32'b10111001100000000000000000000000;
5'b01111: O_D <= 32'b10111001000000000000000000000000;
5'b10000: O_D <= 32'b10111000100000000000000000000000;
5'b10001: O_D <= 32'b10111000000000000000000000000000;
5'b10010: O_D <= 32'b10110111100000000000000000000000;
5'b10011: O_D <= 32'b10110111000000000000000000000000;
5'b10100: O_D <= 32'b10110110100000000000000000000000;
5'b10101: O_D <= 32'b10110110000000000000000000000000;
5'b10110: O_D <= 32'b10110101100000000000000000000000;
5'b10111: O_D <= 32'b10110101000000000000000000000000;
5'b11000: O_D <= 32'b10110100100000000000000000000000;
5'b11001: O_D <= 32'b10110100000000000000000000000000;
5'b11010: O_D <= 32'b10110011100000000000000000000000;
5'b11011: O_D <= 32'b10110011000000000000000000000000;
5'b11100: O_D <= 32'b10110010100000000000000000000000;
5'b11101: O_D <= 32'b10110010000000000000000000000000;
5'b11110: O_D <= 32'b10110001100000000000000000000000;
5'b11111: O_D <= 32'b10110001000000000000000000000000;
default: O_D <= 32'b00000000000000000000000000000000;
endcase
else
O_D <= 32'b00000000000000000000000000000000;
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:36:46 09/06/2015
// Design Name:
// Module Name: FPU_Multiplication_Function
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FPU_Multiplication_Function
//SINGLE PRECISION PARAMETERS
/*# (parameter W = 32, parameter EW = 8, parameter SW = 23) // */
//DOUBLE PRECISION PARAMETERS
# (parameter W = 64, parameter EW = 11, parameter SW = 52) // */
(
input wire clk,
input wire rst,
input wire beg_FSM,
input wire ack_FSM,
input wire [W-1:0] Data_MX,
input wire [W-1:0] Data_MY,
input wire [1:0] round_mode,
output wire overflow_flag,
output wire underflow_flag,
output wire ready,
output wire [W-1:0] final_result_ieee
);
//GENERAL
wire rst_int; //**
//FSM_load_signals
wire FSM_first_phase_load; //**
wire FSM_load_first_step; /*Zero flag, Exp operation underflow, Sgf operation first reg,
sign result reg*/
wire FSM_exp_operation_load_result; //Exp operation result,
wire FSM_load_second_step; //Exp operation Overflow, Sgf operation second reg
wire FSM_barrel_shifter_load;
wire FSM_adder_round_norm_load;
wire FSM_final_result_load;
//ZERO FLAG
//Op_MX;
//Op_MY
wire zero_flag;
//FIRST PHASE
wire [W-1:0] Op_MX;
wire [W-1:0] Op_MY;
//Mux S-> exp_operation OPER_A_i//////////
wire FSM_selector_A;
//D0=Op_MX[W-2:W-EW-1]
//D1=exp_oper_result
wire [EW:0] S_Oper_A_exp;
//Mux S-> exp_operation OPER_B_i//////////
wire [1:0] FSM_selector_B;
//D0=Op_MY[W-2:W-EW-1]
//D1=LZA_output
//D2=1
wire [EW-1:0] S_Oper_B_exp;
///////////exp_operation///////////////////////////
wire FSM_exp_operation_A_S;
//oper_A= S_Oper_A_exp
//oper_B= S_Oper_B_exp
wire [EW:0] exp_oper_result;
//Sgf operation//////////////////
//Op_A={1'b1, Op_MX[SW-1:0]}
//Op_B={1'b1, Op_MY[SW-1:0]}
wire [2*SW+1:0] P_Sgf;
wire[SW:0] significand;
wire[SW:0] non_significand;
//Sign Operation
wire sign_final_result;
//barrel shifter multiplexers
wire [SW:0] S_Data_Shift;
//barrel shifter
wire [SW:0] Sgf_normalized_result;
//adder rounding
wire FSM_add_overflow_flag;
//Oper_A_i=norm result
//Oper_B_i=1
wire [SW:0] Add_result;
//round decoder
wire FSM_round_flag;
//Selecto moltiplexers
wire selector_A;
wire [1:0] selector_B;
wire load_b;
wire selector_C;
//Barrel shifter multiplexer
/////////////////////////////////////////FSM////////////////////////////////////////////
FSM_Mult_Function FS_Module (
.clk(clk), //**
.rst(rst), //**
.beg_FSM(beg_FSM), //**
.ack_FSM(ack_FSM), //**
.zero_flag_i(zero_flag),
.Mult_shift_i(P_Sgf[2*SW+1]),
.round_flag_i(FSM_round_flag),
.Add_Overflow_i(FSM_add_overflow_flag),
.load_0_o(FSM_first_phase_load),
.load_1_o(FSM_load_first_step),
.load_2_o(FSM_exp_operation_load_result),
.load_3_o(FSM_load_second_step),
.load_4_o(FSM_adder_round_norm_load),
.load_5_o(FSM_final_result_load),
.load_6_o(FSM_barrel_shifter_load),
.ctrl_select_a_o(selector_A),
.ctrl_select_b_o(load_b),
.selector_b_o(selector_B),
.ctrl_select_c_o(selector_C),
.exp_op_o(FSM_exp_operation_A_S),
.shift_value_o(FSM_Shift_Value),
.rst_int(rst_int), //
.ready(ready)
);
///////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////Selector's registers//////////////////////////////
RegisterAdd #(.W(1)) Sel_A ( //Selector_A register
.clk(clk),
.rst(rst_int),
.load(selector_A),
.D(1'b1),
.Q(FSM_selector_A)
);
RegisterAdd #(.W(1)) Sel_C ( //Selector_C register
.clk(clk),
.rst(rst_int),
.load(selector_C),
.D(1'b1),
.Q(FSM_selector_C)
);
RegisterAdd #(.W(2)) Sel_B ( //Selector_B register
.clk(clk),
.rst(rst_int),
.load(load_b),
.D(selector_B),
.Q(FSM_selector_B)
);
///////////////////////////////////////////////////////////////////////////////////////////
First_Phase_M #(.W(W)) Operands_load_reg ( //
.clk(clk), //**
.rst(rst_int), //**
.load(FSM_first_phase_load), //**
.Data_MX(Data_MX), //**
.Data_MY(Data_MY), //**
.Op_MX(Op_MX),
.Op_MY(Op_MY)
);
Zero_InfMult_Unit #(.W(W)) Zero_Result_Detect (
.clk(clk),
.rst(rst_int),
.load(FSM_load_first_step),
.Data_A(Op_MX [W-2:0]),
.Data_B(Op_MY [W-2:0]),
.zero_m_flag(zero_flag)
);
///////////Mux exp_operation OPER_A_i//////////
Multiplexer_AC #(.W(EW+1)) Exp_Oper_A_mux(
.ctrl(FSM_selector_A),
.D0 ({1'b0,Op_MX[W-2:W-EW-1]}),
.D1 (exp_oper_result),
.S (S_Oper_A_exp)
);
///////////Mux exp_operation OPER_B_i//////////
wire [EW-1:0] Exp_oper_B_D1, Exp_oper_B_D2;
Mux_3x1 #(.W(EW)) Exp_Oper_B_mux(
.ctrl(FSM_selector_B),
.D0 (Op_MY[W-2:W-EW-1]),
.D1 (Exp_oper_B_D1),
.D2 (Exp_oper_B_D2),
.S(S_Oper_B_exp)
);
generate
case(EW)
8:begin
assign Exp_oper_B_D1 = 8'd127;
assign Exp_oper_B_D2 = 8'd1;
end
default:begin
assign Exp_oper_B_D1 = 11'd1023;
assign Exp_oper_B_D2 = 11'd1;
end
endcase
endgenerate
///////////exp_operation///////////////////////////
Exp_Operation_m #(.EW(EW)) Exp_module (
.clk(clk),
.rst(rst_int),
.load_a_i(FSM_load_first_step),
.load_b_i(FSM_load_second_step),
.load_c_i(FSM_exp_operation_load_result),
.Data_A_i(S_Oper_A_exp),
.Data_B_i({1'b0,S_Oper_B_exp}),
.Add_Subt_i(FSM_exp_operation_A_S),
.Data_Result_o(exp_oper_result),
.Overflow_flag_o(overflow_flag),
.Underflow_flag_o(underflow_flag)
);
////////Sign_operation//////////////////////////////
XOR_M Sign_operation (
.Sgn_X(Op_MX[W-1]),
.Sgn_Y(Op_MY[W-1]),
.Sgn_Info(sign_final_result)
);
/////Significant_Operation//////////////////////////
Sgf_Multiplication #(.SW(SW+1)) Sgf_operation (
.clk(clk),
.rst(rst),
.load_b_i(FSM_load_second_step),
.Data_A_i({1'b1,Op_MX[SW-1:0]}),
.Data_B_i({1'b1,Op_MY[SW-1:0]}),
.sgf_result_o(P_Sgf)
);
//////////Mux Barrel shifter shift_Value/////////////////
assign significand = P_Sgf [2*SW:SW];
assign non_significand = P_Sgf [SW-1:0];
///////////Mux Barrel shifter Data_in//////
Multiplexer_AC #(.W(SW+1)) Barrel_Shifter_D_I_mux(
.ctrl(FSM_selector_C),
.D0 (significand),
.D1 (Add_result),
.S (S_Data_Shift)
);
///////////Barrel_Shifter//////////////////////////
Barrel_Shifter_M #(.SW(SW+1)) Barrel_Shifter_module (
.clk(clk),
.rst(rst_int),
.load_i(FSM_barrel_shifter_load),
.Shift_Value_i(FSM_Shift_Value),
.Shift_Data_i(S_Data_Shift),
.N_mant_o(Sgf_normalized_result)
);
////Round decoder/////////////////////////////////
Round_decoder_M #(.SW(SW)) Round_Decoder (
.Round_Bits_i(non_significand),
.Round_Mode_i(round_mode),
.Sign_Result_i(sign_final_result),
.Round_Flag_o(FSM_round_flag)
);
//rounding_adder
wire [SW:0] Add_Sgf_Oper_B;
assign Add_Sgf_Oper_B = (SW)*1'b1;
Adder_Round #(.SW(SW+1)) Adder_M (
.clk(clk),
.rst(rst_int),
.load_i(FSM_adder_round_norm_load),
.Data_A_i(Sgf_normalized_result),
.Data_B_i(Add_Sgf_Oper_B),
.Data_Result_o(Add_result),
.FSM_C_o(FSM_add_overflow_flag)
);
////Final Result///////////////////////////////
Tenth_Phase #(.W(W),.EW(EW),.SW(SW)) final_result_ieee_Module(
.clk(clk),
.rst(rst_int),
.load_i(FSM_final_result_load),
.sel_a_i(overflow_flag),
.sel_b_i(underflow_flag),
.sign_i(sign_final_result),
.exp_ieee_i(exp_oper_result[EW-1:0]),
.sgf_ieee_i(Sgf_normalized_result[SW-1:0]),
.final_result_ieee_o(final_result_ieee)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Host Bus Data Out stage
// File : hbi_dout_stage.v
// Author : Frank Bruno
// Created : 30-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// module to generates output blackbird data to the output pins & the module
// also generates parity for the data bus & the byte enables bus
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/10ps
module hbi_dout_stage
(
input hb_clk, // host bus clock
input [31:0] hb_regs_dout, // all HBI registers bus output
input [31:0] hb_rcache_dout, /* host bus data cache output
* (either data cache or WID cache
* output) */
input [31:0] hdat_out_crt_vga, // all CRT registers bus output
input [31:0] draw_engine_a_dout,// 2D cache readback
input [31:0] draw_engine_reg, // all DE registers bus output
input cs_global_regs_n, // global register is addressed.
input cs_hbi_regs_n, // HBI regsiters is been addressed.
input cs_xyw_a_n, // 2D cache accessed
input decoder_cs_windows_n, // memory windows is asserted
input hb_lached_rdwr, /* host bus read cycle in progress
* signal when asserted, it
* indicates that a host bus read
* cycle is in progress (active low)
*/
input hbi_addr_in, // host bus address bit
input [3:0] hb_byte_ens, /* HBI UNLATCHED byte enables
* directly from the PCI bus. */
input irdy_n, // host bus initiator ready signal
input sys_reset_n, // host bus system reset
input trdy_n, /* (BLACKBIRD) is ready to accept new
* data if the cycle is write, or
* target is ready to provide data
* if the cycle is read */
input [31:0] perph_rd_dbus, // read back perhpial data bus
input cs_eprom_n, /* chip select EPROM (the EPROM
* present on the graphics board) */
input cs_dac_space_n, /* chip select VGA registers in
* either I/O or MEM mode */
input cs_vga_space_n, /* chip select VGA space whenever
* BLK board has VGA on board
* (determined from the PCI class
* configuration bits) */
input [2:0] swizzler_ctrl,
input any_trdy_async, /* an "or" of all the async trdy
* sources */
input [31:0] pci_ad_out, // pci ad request data
input pci_ad_oe, // pci oe for write data
input [3:0] c_be_out,
output reg [31:0] blkbird_dout, // data output bus to the outside
output reg par32 /* even parity for the lower half of
* the data output bus */
);
reg pci_ad_oe_reg;
reg [31:0] hb_data_swizzled;
wire [31:0] hb_regblock_dout;
wire [31:0] hb_read_data;
wire [7:0] hb_dat_b3, hb_dat_b2, hb_dat_b1, hb_dat_b0;
wire [7:0] hb_dat_b7, hb_dat_b6, hb_dat_b5, hb_dat_b4;
wire be_par32;
wire bkbrd_par32;
wire lower_level_parity32;
wire be_out_par32;
wire pci_master_par32;
parameter
READ = 1'b0,
WRITE = 1'b1;
// DOUT_MUX
// Block to multiplex data from all Blackbird modules into the data bus
// OUTPUT MUX SELECTING OUTPUT DATA BETWEEN BLKBIRD MODULES
assign hb_read_data =
// PERPH
(!cs_eprom_n || !cs_dac_space_n) ? perph_rd_dbus :
// VGA & crt & video regsiters
(!cs_vga_space_n || !cs_global_regs_n) ? hdat_out_crt_vga :
// hb registers
(!cs_hbi_regs_n) ? hb_regs_dout :
// hb data cache
(!decoder_cs_windows_n) ? hb_rcache_dout :
// 2D DE cache
(!cs_xyw_a_n) ? draw_engine_a_dout :
// Drawing Engine registers
draw_engine_reg;
// SWIZZLER FOR THE READ DATA PATH
assign hb_dat_b3 =
(swizzler_ctrl[0]) ?
{hb_read_data[24], hb_read_data[25], hb_read_data[26],
hb_read_data[27], hb_read_data[28], hb_read_data[29],
hb_read_data[30], hb_read_data[31]} :
hb_read_data[31:24];
assign hb_dat_b2 =
(swizzler_ctrl[0]) ?
{hb_read_data[16], hb_read_data[17], hb_read_data[18],
hb_read_data[19], hb_read_data[20], hb_read_data[21],
hb_read_data[22], hb_read_data[23]} :
hb_read_data[23:16];
assign hb_dat_b1 =
(swizzler_ctrl[0]) ?
{hb_read_data[8], hb_read_data[9], hb_read_data[10],
hb_read_data[11], hb_read_data[12] ,hb_read_data[13],
hb_read_data[14], hb_read_data[15]} :
hb_read_data[15:8];
assign hb_dat_b0 =
(swizzler_ctrl[0]) ?
{hb_read_data[0], hb_read_data[1], hb_read_data[2],
hb_read_data[3], hb_read_data[4], hb_read_data[5],
hb_read_data[6],hb_read_data[7]} :
hb_read_data[7:0];
always @*
case (swizzler_ctrl[2:1])
2'b00:
hb_data_swizzled = { hb_dat_b3, hb_dat_b2, hb_dat_b1, hb_dat_b0};
2'b01:
hb_data_swizzled = { hb_dat_b2, hb_dat_b3, hb_dat_b0, hb_dat_b1};
2'b10:
hb_data_swizzled = { hb_dat_b1, hb_dat_b0, hb_dat_b3, hb_dat_b2};
2'b11:
hb_data_swizzled = { hb_dat_b0, hb_dat_b1, hb_dat_b2, hb_dat_b3};
endcase // case(swizzler_ctrl[2:0])
// PIPELINE THE OUTPUT DATA
always @ (posedge hb_clk) begin
//read cycle is active (in progress) thus allow data to flow through
//if (hb_lached_rdwr==READ && ((any_trdy_async && trdy_n) ||
// (!trdy_n && !irdy_n)))
if (any_trdy_async && (trdy_n || (!trdy_n && !irdy_n)))
blkbird_dout <= hb_data_swizzled;
else if (pci_ad_oe)
blkbird_dout <= pci_ad_out;
end
/*******************************************************************************
* PARITY_GENERATOR
* Block to generate EVEN PARITY for the the host bus read cycles & the
* PCI master's write cycles as required by the PCI spec.
*******************************************************************************/
always @(posedge hb_clk) pci_ad_oe_reg <= pci_ad_oe;
assign be_par32 = ^hb_byte_ens[3:0];
assign be_out_par32 = ^c_be_out[3:0]; //PCI master's CBEs
assign bkbrd_par32 = ^blkbird_dout;
assign lower_level_parity32 = bkbrd_par32 ^ be_par32;//Parity for PCI slave
assign pci_master_par32 = bkbrd_par32 ^ be_out_par32;//Parity for PCI master
//Parity is clocked at the end of every beat(and that would delay
//parity by one clock to comply with PCI spec.)
always @(posedge hb_clk or negedge sys_reset_n) begin
if (!sys_reset_n) begin
par32 <= 1'b0;
end else if (pci_ad_oe_reg) begin
par32 <= pci_master_par32;
end else if (!trdy_n && !irdy_n) begin
par32 <= lower_level_parity32; //current beat is done
end
end
endmodule // HBI_DOUT_STAGE
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: si_transactor.v
//
// Description:
// This module manages multi-threaded transactions for one SI-slot.
// The module interface consists of a 1-slave to 1-master address channel, plus a
// (M+1)-master (from M MI-slots plus error handler) to 1-slave response channel.
// The module maintains transaction thread control registers that count the
// number of outstanding transations for each thread and the target MI-slot.
// On the address channel, the module decodes addresses to select among MI-slots
// accessible to the SI-slot where it is instantiated.
// It then qualifies whether each received transaction
// should be propagated as a request to the address channel arbiter.
// Transactions are blocked while there is any outstanding transaction to a
// different slave (MI-slot) for the requested ID thread (for deadlock avoidance).
// On the response channel, the module mulitplexes transfers from each of the
// MI-slots whenever a transfer targets the ID of an active thread,
// arbitrating between MI-slots if multiple threads respond concurrently.
//
//--------------------------------------------------------------------------
//
// Structure:
// si_transactor
// addr_decoder
// comparator_static
// mux_enc
// axic_srl_fifo
// arbiter_resp
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_10_si_transactor #
(
parameter C_FAMILY = "none",
parameter integer C_SI = 0, // SI-slot number of current instance.
parameter integer C_DIR = 0, // Direction: 0 = Write; 1 = Read.
parameter integer C_NUM_ADDR_RANGES = 1,
parameter integer C_NUM_M = 2,
parameter integer C_NUM_M_LOG = 1,
parameter integer C_ACCEPTANCE = 1, // Acceptance limit of this SI-slot.
parameter integer C_ACCEPTANCE_LOG = 0, // Width of acceptance counter for this SI-slot.
parameter integer C_ID_WIDTH = 1,
parameter integer C_THREAD_ID_WIDTH = 0,
parameter integer C_ADDR_WIDTH = 32,
parameter integer C_AMESG_WIDTH = 1, // Used for AW or AR channel payload, depending on instantiation.
parameter integer C_RMESG_WIDTH = 1, // Used for B or R channel payload, depending on instantiation.
parameter [C_ID_WIDTH-1:0] C_BASE_ID = {C_ID_WIDTH{1'b0}},
parameter [C_ID_WIDTH-1:0] C_HIGH_ID = {C_ID_WIDTH{1'b0}},
parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b1}},
parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b0}},
parameter integer C_SINGLE_THREAD = 0,
parameter [C_NUM_M-1:0] C_TARGET_QUAL = {C_NUM_M{1'b1}},
parameter [C_NUM_M*32-1:0] C_M_AXI_SECURE = {C_NUM_M{32'h00000000}},
parameter integer C_RANGE_CHECK = 0,
parameter integer C_ADDR_DECODE =0,
parameter [C_NUM_M*32-1:0] C_ERR_MODE = {C_NUM_M{32'h00000000}},
parameter integer C_DEBUG = 1
)
(
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Address Channel Interface Ports
input wire [C_ID_WIDTH-1:0] S_AID,
input wire [C_ADDR_WIDTH-1:0] S_AADDR,
input wire [8-1:0] S_ALEN,
input wire [3-1:0] S_ASIZE,
input wire [2-1:0] S_ABURST,
input wire [2-1:0] S_ALOCK,
input wire [3-1:0] S_APROT,
// input wire [4-1:0] S_AREGION,
input wire [C_AMESG_WIDTH-1:0] S_AMESG,
input wire S_AVALID,
output wire S_AREADY,
// Master Address Channel Interface Ports
output wire [C_ID_WIDTH-1:0] M_AID,
output wire [C_ADDR_WIDTH-1:0] M_AADDR,
output wire [8-1:0] M_ALEN,
output wire [3-1:0] M_ASIZE,
output wire [2-1:0] M_ALOCK,
output wire [3-1:0] M_APROT,
output wire [4-1:0] M_AREGION,
output wire [C_AMESG_WIDTH-1:0] M_AMESG,
output wire [(C_NUM_M+1)-1:0] M_ATARGET_HOT,
output wire [(C_NUM_M_LOG+1)-1:0] M_ATARGET_ENC,
output wire [7:0] M_AERROR,
output wire M_AVALID_QUAL,
output wire M_AVALID,
input wire M_AREADY,
// Slave Response Channel Interface Ports
output wire [C_ID_WIDTH-1:0] S_RID,
output wire [C_RMESG_WIDTH-1:0] S_RMESG,
output wire S_RLAST,
output wire S_RVALID,
input wire S_RREADY,
// Master Response Channel Interface Ports
input wire [(C_NUM_M+1)*C_ID_WIDTH-1:0] M_RID,
input wire [(C_NUM_M+1)*C_RMESG_WIDTH-1:0] M_RMESG,
input wire [(C_NUM_M+1)-1:0] M_RLAST,
input wire [(C_NUM_M+1)-1:0] M_RVALID,
output wire [(C_NUM_M+1)-1:0] M_RREADY,
input wire [(C_NUM_M+1)-1:0] M_RTARGET, // Does response ID from each MI-slot target this SI slot?
input wire [8-1:0] DEBUG_A_TRANS_SEQ
);
localparam integer P_WRITE = 0;
localparam integer P_READ = 1;
localparam integer P_RMUX_MESG_WIDTH = C_ID_WIDTH + C_RMESG_WIDTH + 1;
localparam [31:0] P_AXILITE_ERRMODE = 32'h00000001;
localparam integer P_NONSECURE_BIT = 1;
localparam integer P_NUM_M_LOG_M1 = C_NUM_M_LOG ? C_NUM_M_LOG : 1;
localparam [C_NUM_M-1:0] P_M_AXILITE = f_m_axilite(0); // Mask of AxiLite MI-slots
localparam [1:0] P_FIXED = 2'b00;
localparam integer P_NUM_M_DE_LOG = f_ceil_log2(C_NUM_M+1);
localparam integer P_THREAD_ID_WIDTH_M1 = (C_THREAD_ID_WIDTH > 0) ? C_THREAD_ID_WIDTH : 1;
localparam integer P_NUM_ID_VAL = 2**C_THREAD_ID_WIDTH;
localparam integer P_NUM_THREADS = (P_NUM_ID_VAL < C_ACCEPTANCE) ? P_NUM_ID_VAL : C_ACCEPTANCE;
localparam [C_NUM_M-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE); // Mask of secure MI-slots
// Ceiling of log2(x)
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// AxiLite protocol flag vector
function [C_NUM_M-1:0] f_m_axilite
(
input integer null_arg
);
integer mi;
begin
for (mi=0; mi<C_NUM_M; mi=mi+1) begin
f_m_axilite[mi] = (C_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE);
end
end
endfunction
// Convert Bit32 vector of range [0,1] to Bit1 vector on MI
function [C_NUM_M-1:0] f_bit32to1_mi
(input [C_NUM_M*32-1:0] vec32);
integer mi;
begin
for (mi=0; mi<C_NUM_M; mi=mi+1) begin
f_bit32to1_mi[mi] = vec32[mi*32];
end
end
endfunction
wire [C_NUM_M-1:0] target_mi_hot;
wire [P_NUM_M_LOG_M1-1:0] target_mi_enc;
wire [(C_NUM_M+1)-1:0] m_atarget_hot_i;
wire [(P_NUM_M_DE_LOG)-1:0] m_atarget_enc_i;
wire match;
wire [3:0] target_region;
wire [3:0] m_aregion_i;
wire m_avalid_i;
wire s_aready_i;
wire any_error;
wire s_rvalid_i;
wire [C_ID_WIDTH-1:0] s_rid_i;
wire s_rlast_i;
wire [P_RMUX_MESG_WIDTH-1:0] si_rmux_mesg;
wire [(C_NUM_M+1)*P_RMUX_MESG_WIDTH-1:0] mi_rmux_mesg;
wire [(C_NUM_M+1)-1:0] m_rvalid_qual;
wire [(C_NUM_M+1)-1:0] m_rready_arb;
wire [(C_NUM_M+1)-1:0] m_rready_i;
wire target_secure;
wire target_axilite;
wire m_avalid_qual_i;
wire [7:0] m_aerror_i;
genvar gen_mi;
genvar gen_thread;
generate
if (C_ADDR_DECODE) begin : gen_addr_decoder
axi_crossbar_v2_1_10_addr_decoder #
(
.C_FAMILY (C_FAMILY),
.C_NUM_TARGETS (C_NUM_M),
.C_NUM_TARGETS_LOG (P_NUM_M_LOG_M1),
.C_NUM_RANGES (C_NUM_ADDR_RANGES),
.C_ADDR_WIDTH (C_ADDR_WIDTH),
.C_TARGET_ENC (1),
.C_TARGET_HOT (1),
.C_REGION_ENC (1),
.C_BASE_ADDR (C_BASE_ADDR),
.C_HIGH_ADDR (C_HIGH_ADDR),
.C_TARGET_QUAL (C_TARGET_QUAL),
.C_RESOLUTION (2)
)
addr_decoder_inst
(
.ADDR (S_AADDR),
.TARGET_HOT (target_mi_hot),
.TARGET_ENC (target_mi_enc),
.MATCH (match),
.REGION (target_region)
);
end else begin : gen_no_addr_decoder
assign target_mi_hot = 1;
assign target_mi_enc = 0;
assign match = 1'b1;
assign target_region = 4'b0000;
end
endgenerate
assign target_secure = |(target_mi_hot & P_M_SECURE_MASK);
assign target_axilite = |(target_mi_hot & P_M_AXILITE);
assign any_error = C_RANGE_CHECK && (m_aerror_i != 0); // DECERR if error-detection enabled and any error condition.
assign m_aerror_i[0] = ~match; // Invalid target address
assign m_aerror_i[1] = target_secure && S_APROT[P_NONSECURE_BIT]; // TrustZone violation
assign m_aerror_i[2] = target_axilite && ((S_ALEN != 0) ||
(S_ASIZE[1:0] == 2'b11) || (S_ASIZE[2] == 1'b1)); // AxiLite access violation
assign m_aerror_i[7:3] = 5'b00000; // Reserved
assign M_ATARGET_HOT = m_atarget_hot_i;
assign m_atarget_hot_i = (any_error ? {1'b1, {C_NUM_M{1'b0}}} : {1'b0, target_mi_hot});
assign m_atarget_enc_i = (any_error ? C_NUM_M : target_mi_enc);
assign M_AVALID = m_avalid_i;
assign m_avalid_i = S_AVALID;
assign M_AVALID_QUAL = m_avalid_qual_i;
assign S_AREADY = s_aready_i;
assign s_aready_i = M_AREADY;
assign M_AERROR = m_aerror_i;
assign M_ATARGET_ENC = m_atarget_enc_i;
assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : 4'b0000;
// assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : S_AREGION;
assign M_AREGION = m_aregion_i;
assign M_AID = S_AID;
assign M_AADDR = S_AADDR;
assign M_ALEN = S_ALEN;
assign M_ASIZE = S_ASIZE;
assign M_ALOCK = S_ALOCK;
assign M_APROT = S_APROT;
assign M_AMESG = S_AMESG;
assign S_RVALID = s_rvalid_i;
assign M_RREADY = m_rready_i;
assign s_rid_i = si_rmux_mesg[0+:C_ID_WIDTH];
assign S_RMESG = si_rmux_mesg[C_ID_WIDTH+:C_RMESG_WIDTH];
assign s_rlast_i = si_rmux_mesg[C_ID_WIDTH+C_RMESG_WIDTH+:1];
assign S_RID = s_rid_i;
assign S_RLAST = s_rlast_i;
assign m_rvalid_qual = M_RVALID & M_RTARGET;
assign m_rready_i = m_rready_arb & M_RTARGET;
generate
for (gen_mi=0; gen_mi<(C_NUM_M+1); gen_mi=gen_mi+1) begin : gen_rmesg_mi
// Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order.
assign mi_rmux_mesg[gen_mi*P_RMUX_MESG_WIDTH+:P_RMUX_MESG_WIDTH] = {
M_RLAST[gen_mi],
M_RMESG[gen_mi*C_RMESG_WIDTH+:C_RMESG_WIDTH],
M_RID[gen_mi*C_ID_WIDTH+:C_ID_WIDTH]
};
end // gen_rmesg_mi
if (C_ACCEPTANCE == 1) begin : gen_single_issue
wire cmd_push;
wire cmd_pop;
reg [(C_NUM_M+1)-1:0] active_target_hot;
reg [P_NUM_M_DE_LOG-1:0] active_target_enc;
reg accept_cnt;
reg [8-1:0] debug_r_beat_cnt_i;
wire [8-1:0] debug_r_trans_seq_i;
assign cmd_push = M_AREADY;
assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst
assign m_avalid_qual_i = ~accept_cnt | cmd_pop; // Ready for arbitration if no outstanding transaction or transaction being completed
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 1'b0;
active_target_enc <= 0;
active_target_hot <= 0;
end else begin
if (cmd_push) begin
active_target_enc <= m_atarget_enc_i;
active_target_hot <= m_atarget_hot_i;
accept_cnt <= 1'b1;
end else if (cmd_pop) begin
accept_cnt <= 1'b0;
end
end
end // Clocked process
assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};
assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_single_issue
(
.S (active_target_enc),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
if (C_DEBUG) begin : gen_debug_r_single_issue
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i && S_RREADY) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i <= 0;
end else begin
debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
end
end
end else begin
debug_r_beat_cnt_i <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_8_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_single_issue
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push),
.S_READY (),
.M_MESG (debug_r_trans_seq_i),
.M_VALID (),
.M_READY (cmd_pop)
);
end // gen_debug_r
end else if (C_SINGLE_THREAD || (P_NUM_ID_VAL==1)) begin : gen_single_thread
wire s_avalid_en;
wire cmd_push;
wire cmd_pop;
reg [C_ID_WIDTH-1:0] active_id;
reg [(C_NUM_M+1)-1:0] active_target_hot;
reg [P_NUM_M_DE_LOG-1:0] active_target_enc;
reg [4-1:0] active_region;
reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt;
reg [8-1:0] debug_r_beat_cnt_i;
wire [8-1:0] debug_r_trans_seq_i;
wire accept_limit ;
// Implement single-region-per-ID cyclic dependency avoidance method.
assign s_avalid_en = // This transaction is qualified to request arbitration if ...
(accept_cnt == 0) || // Either there are no outstanding transactions, or ...
(((P_NUM_ID_VAL==1) || (S_AID[P_THREAD_ID_WIDTH_M1-1:0] == active_id[P_THREAD_ID_WIDTH_M1-1:0])) && // the current transaction ID matches the previous, and ...
(active_target_enc == m_atarget_enc_i) && // all outstanding transactions are to the same target MI ...
(active_region == m_aregion_i)); // and to the same REGION.
assign cmd_push = M_AREADY;
assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst
assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~cmd_pop; // Allow next push if a transaction is currently being completed
assign m_avalid_qual_i = s_avalid_en & ~accept_limit;
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 0;
active_id <= 0;
active_target_enc <= 0;
active_target_hot <= 0;
active_region <= 0;
end else begin
if (cmd_push) begin
active_id <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];
active_target_enc <= m_atarget_enc_i;
active_target_hot <= m_atarget_hot_i;
active_region <= m_aregion_i;
if (~cmd_pop) begin
accept_cnt <= accept_cnt + 1;
end
end else begin
if (cmd_pop & (accept_cnt != 0)) begin
accept_cnt <= accept_cnt - 1;
end
end
end
end // Clocked process
assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};
assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_single_thread
(
.S (active_target_enc),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
if (C_DEBUG) begin : gen_debug_r_single_thread
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i && S_RREADY) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i <= 0;
end else begin
debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
end
end
end else begin
debug_r_beat_cnt_i <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_8_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_single_thread
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push),
.S_READY (),
.M_MESG (debug_r_trans_seq_i),
.M_VALID (),
.M_READY (cmd_pop)
);
end // gen_debug_r
end else begin : gen_multi_thread
wire [(P_NUM_M_DE_LOG)-1:0] resp_select;
reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt;
wire [P_NUM_THREADS-1:0] s_avalid_en;
wire [P_NUM_THREADS-1:0] thread_valid;
wire [P_NUM_THREADS-1:0] aid_match;
wire [P_NUM_THREADS-1:0] rid_match;
wire [P_NUM_THREADS-1:0] cmd_push;
wire [P_NUM_THREADS-1:0] cmd_pop;
wire [P_NUM_THREADS:0] accum_push;
reg [P_NUM_THREADS*C_ID_WIDTH-1:0] active_id;
reg [P_NUM_THREADS*8-1:0] active_target;
reg [P_NUM_THREADS*8-1:0] active_region;
reg [P_NUM_THREADS*8-1:0] active_cnt;
reg [P_NUM_THREADS*8-1:0] debug_r_beat_cnt_i;
wire [P_NUM_THREADS*8-1:0] debug_r_trans_seq_i;
wire any_aid_match;
wire any_rid_match;
wire accept_limit;
wire any_push;
wire any_pop;
axi_crossbar_v2_1_10_arbiter_resp # // Multi-thread response arbiter
(
.C_FAMILY (C_FAMILY),
.C_NUM_S (C_NUM_M+1),
.C_NUM_S_LOG (P_NUM_M_DE_LOG),
.C_GRANT_ENC (1),
.C_GRANT_HOT (0)
)
arbiter_resp_inst
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_VALID (m_rvalid_qual),
.S_READY (m_rready_arb),
.M_GRANT_HOT (),
.M_GRANT_ENC (resp_select),
.M_VALID (s_rvalid_i),
.M_READY (S_RREADY)
);
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_multi_thread
(
.S (resp_select),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
assign any_push = M_AREADY;
assign any_pop = s_rvalid_i & S_RREADY & s_rlast_i;
assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~any_pop; // Allow next push if a transaction is currently being completed
assign m_avalid_qual_i = (&s_avalid_en) & ~accept_limit; // The current request is qualified for arbitration when it is qualified against all outstanding transaction threads.
assign any_aid_match = |aid_match;
assign any_rid_match = |rid_match;
assign accum_push[0] = 1'b0;
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 0;
end else begin
if (any_push & ~any_pop) begin
accept_cnt <= accept_cnt + 1;
end else if (any_pop & ~any_push & (accept_cnt != 0)) begin
accept_cnt <= accept_cnt - 1;
end
end
end // Clocked process
for (gen_thread=0; gen_thread<P_NUM_THREADS; gen_thread=gen_thread+1) begin : gen_thread_loop
assign thread_valid[gen_thread] = (active_cnt[gen_thread*8 +: C_ACCEPTANCE_LOG+1] != 0);
assign aid_match[gen_thread] = // The currect thread is active for the requested transaction if
thread_valid[gen_thread] && // this thread slot is not vacant, and
((S_AID[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]); // the requested ID matches the active ID for this thread.
assign s_avalid_en[gen_thread] = // The current request is qualified against this thread slot if
(~aid_match[gen_thread]) || // This thread slot is not active for the requested ID, or
((m_atarget_enc_i == active_target[gen_thread*8+:P_NUM_M_DE_LOG]) && // this outstanding transaction was to the same target and
(m_aregion_i == active_region[gen_thread*8+:4])); // to the same region.
// cmd_push points to the position of either the active thread for the requested ID or the lowest vacant thread slot.
assign accum_push[gen_thread+1] = accum_push[gen_thread] | ~thread_valid[gen_thread];
assign cmd_push[gen_thread] = any_push & (aid_match[gen_thread] | ((~any_aid_match) & ~thread_valid[gen_thread] & ~accum_push[gen_thread]));
// cmd_pop points to the position of the active thread that matches the current RID.
assign rid_match[gen_thread] = thread_valid[gen_thread] & ((s_rid_i[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]);
assign cmd_pop[gen_thread] = any_pop & rid_match[gen_thread];
always @(posedge ACLK) begin
if (ARESET) begin
active_id[gen_thread*C_ID_WIDTH+:C_ID_WIDTH] <= 0;
active_target[gen_thread*8+:8] <= 0;
active_region[gen_thread*8+:8] <= 0;
active_cnt[gen_thread*8+:8] <= 0;
end else begin
if (cmd_push[gen_thread]) begin
active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1] <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];
active_target[gen_thread*8+:P_NUM_M_DE_LOG] <= m_atarget_enc_i;
active_region[gen_thread*8+:4] <= m_aregion_i;
if (~cmd_pop[gen_thread]) begin
active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] + 1;
end
end else if (cmd_pop[gen_thread]) begin
active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] - 1;
end
end
end // Clocked process
if (C_DEBUG) begin : gen_debug_r_multi_thread
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i & S_RREADY & rid_match[gen_thread]) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end else begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= debug_r_beat_cnt_i[gen_thread*8+:8] + 1;
end
end
end else begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_8_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_multi_thread
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push[gen_thread]),
.S_READY (),
.M_MESG (debug_r_trans_seq_i[gen_thread*8+:8]),
.M_VALID (),
.M_READY (cmd_pop[gen_thread])
);
end // gen_debug_r_multi_thread
end // Next gen_thread_loop
end // thread control
endgenerate
endmodule
`default_nettype wire
|
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
`timescale 1ns / 1ns
module U1 (OUT);
parameter VALUE = -384;
output [9:0] OUT;
assign OUT = VALUE;
endmodule
module U2 (OUT);
parameter VALUE = 96;
output [9:0] OUT;
assign OUT = VALUE;
endmodule
module main;
wire [9:0] out1, out2;
U1 u1 (out1);
U2 u2 (out2);
initial #1 begin
if (out1 !== 10'h280) begin
$display("FAILED -- out1 = %b", out1);
$finish;
end
if (out2 !== 10'h060) begin
$display("FAILED -- out2 = %b", out2);
$finish;
end
$display("PASSED");
end // initial #1
endmodule // main
|
`timescale 1ns / 1ps
module RegisterBanc(ReadData1, ReadData2, WriteData,ReadAddr1, ReadAddr2, WriteAddr, RegWrite, clk , ro);
output [31:0] ReadData1, ReadData2;
input [31:0] WriteData;
input [4:0] ReadAddr1, ReadAddr2, WriteAddr;
input [0:0] RegWrite, clk;
output [31:0] ro;
reg [31:0] Register [0:31];
initial begin
Register[0] = 32'd0;
Register[1] = 32'd0;
Register[2] = 32'd0;
Register[3] = 32'd0;
Register[4] = 32'd0;
Register[5] = 32'd0;
Register[6] = 32'd0;
Register[7] = 32'd0;
Register[8] = 32'd0;
Register[9] = 32'd0;
Register[10] = 32'd0;
Register[11] = 32'd0;
Register[12] = 32'd0;
Register[13] = 32'd0;
Register[14] = 32'd0;
Register[15] = 32'd0;
Register[16] = 32'd0;
Register[17] = 32'd0;
Register[18] = 32'd0;
Register[19] = 32'd0;
Register[20] = 32'd0;
Register[21] = 32'd0;
Register[22] = 32'd0;
Register[23] = 32'd0;
Register[24] = 32'd0;
Register[25] = 32'd0;
Register[26] = 32'd0;
Register[27] = 32'd0;
Register[28] = 32'd0;
Register[29] = 32'd0;
Register[30] = 32'd0;
Register[31] = 32'd0;
end
always @ (posedge clk) begin
if (RegWrite) begin
Register[WriteAddr] <= WriteData;
end
end
assign ReadData1 = Register[ReadAddr1];
assign ReadData2 = Register[ReadAddr2];
assign ro=Register[4'd2];
endmodule |
module speed_select(clk, rst_n, rx_enable, tx_enable, buad_clk_rx, buad_clk_tx);
input clk; // 50MHz
input rst_n; //low reset
input rx_enable; //start clk when get data
input tx_enable;
output buad_clk_rx; // buad_clk_rx high for transfer sample point
output buad_clk_tx; // buad_clk_rx high for transfer sample point
parameter bps9600 = 5208, //baud is 9600bps
bps19200 = 2603, //baud is 19200bps
bps38400 = 1301, //baud is 38400bps
bps57600 = 867, //baud is 57600bps
bps115200 = 434, //baud is 115200bps
bps256000 = 195; //baud is 115200bps
parameter bps9600_2 = 2604,
bps19200_2 = 1301,
bps38400_2 = 650,
bps57600_2 = 433,
bps115200_2 = 217,
bps256000_2 = 97;
reg[12:0] bps_para; //max divider
reg[12:0] bps_para_2; // half of the divider
//----------------------------------------------------------
reg[2:0] uart_ctrl; // uart baud selection register
//----------------------------------------------------------
always @ (posedge clk or negedge rst_n) begin
if(!rst_n)
begin
uart_ctrl <= 3'd4; //default baudrate is 115200
end
else
begin
case (uart_ctrl) //baud rate
3'd0: begin
bps_para <= bps9600;
bps_para_2 <= bps9600_2;
end
3'd1: begin
bps_para <= bps19200;
bps_para_2 <= bps19200_2;
end
3'd2: begin
bps_para <= bps38400;
bps_para_2 <= bps38400_2;
end
3'd3: begin
bps_para <= bps57600;
bps_para_2 <= bps57600_2;
end
3'd4: begin
bps_para <= bps115200;
bps_para_2 <= bps115200_2;
end
3'd5: begin
bps_para <= bps256000;
bps_para_2 <= bps256000_2;
end
default:uart_ctrl <= 3'd0;
endcase
end
end
reg[12:0] cnt_rx; // counter
reg buad_clk_rx_reg; //baud rate clk register
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
cnt_rx <= 13'd0;
else if (cnt_rx < bps_para && rx_enable)
cnt_rx <= cnt_rx + 13'd1; //start count
else
cnt_rx <= 13'd0;
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
buad_clk_rx_reg <= 1'b0;
else if (cnt_rx < bps_para_2 && rx_enable && cnt_rx > 13'd10)
buad_clk_rx_reg <= 1'b1; // buad_clk_rx_reg high enable the sampling data
else
buad_clk_rx_reg <= 1'b0;
end
assign buad_clk_rx = buad_clk_rx_reg;
reg[12:0] cnt_tx; // counter
reg buad_clk_tx_reg; //baud rate clk register
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
cnt_tx <= 13'd0;
else if (cnt_tx < bps_para && tx_enable)
cnt_tx <= cnt_tx + 13'd1; //start count
else
cnt_tx <= 13'd0;
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
buad_clk_tx_reg <= 1'b0;
else if (cnt_tx < bps_para_2 && tx_enable && cnt_tx > 13'd10)
buad_clk_tx_reg <= 1'b1; // buad_clk_tx_reg high enable the sampling data
else
buad_clk_tx_reg <= 1'b0;
end
assign buad_clk_tx = buad_clk_tx_reg;
endmodule
|
`timescale 1ns/100ps
// -----------------------------------------------------------------------------
// One-level up Hierarchical module
// -----------------------------------------------------------------------------
module a_h
// Verilog 2001 style
#(parameter M=5, N=3)
(
// Outputs
output [N-1:0] [M-1:0] a_o1 // From Ia of autoinst_sv_kulkarni_base.v
// End of automatics
// AUTOINPUT*/
);
/*AUTOWIRE*/
autoinst_sv_kulkarni_base
#(/*AUTOINSTPARAM*/
// Parameters
.M (M),
.N (N))
Ia
(/*AUTOINST*/
// Outputs
.a_o1 (a_o1/*[N-1:0][M-1:0]*/),
// Inputs
.a_i1 (a_i1/*[N-1:0][M-1:0]*/)); // <---- BUG?
endmodule
// -----------------------------------------------------------------------------
// Top-level module or Testbench
// -----------------------------------------------------------------------------
module top;
parameter M=4;
parameter N=2;
wire [N-1:0] a_o1;
logic [N-1:0][M-1:0] a_i1;
logic temp;
/*AUTOWIRE*/
// Workaround to fix multi-dimensional port problem
// a) Set "verilog-auto-inst-vector = nil"
// b) ----> a_h AUTO_TEMPLATE ( .\(.*\) (\1), ); */
a_h #(/*AUTOINSTPARAM*/
// Parameters
.M (M),
.N (N))
Ua_h
(/*AUTOINST*/
// Outputs
.a_o1 (a_o1/*[N-1:0][M-1:0]*/)); // <---- BUG?
// Stimulus
initial begin
a_i1 = { 4'h0, 4'h2 };
#5;
$display("Loop Init: a_i1 = { %h, %h } a_o1 = %h\n",
a_i1[1], a_i1[0], a_o1);
#5;
for (int i=0; i<1; i++) begin
for (int j=0; j<N; j++) begin
temp = 1'b0;
for (int k=0; k<M; k++) begin
a_i1[j][k] = temp;
temp = ~temp;
end
end
#5;
$display("Loop %0d: a_i1 = { %h, %h } a_o1 = %h\n",
i, a_i1[1], a_i1[0], a_o1);
#5;
end
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFBUF_8_V
`define SKY130_FD_SC_LP__BUFBUF_8_V
/**
* bufbuf: Double buffer.
*
* Verilog wrapper for bufbuf with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__bufbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__bufbuf_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__bufbuf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__bufbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFBUF_8_V
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_qspi_physical_1(
input clock,
input reset,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
output io_port_cs_1,
output io_port_cs_2,
output io_port_cs_3,
input [11:0] io_ctrl_sck_div,
input io_ctrl_sck_pol,
input io_ctrl_sck_pha,
input [1:0] io_ctrl_fmt_proto,
input io_ctrl_fmt_endian,
input io_ctrl_fmt_iodir,
output io_op_ready,
input io_op_valid,
input io_op_bits_fn,
input io_op_bits_stb,
input [7:0] io_op_bits_cnt,
input [7:0] io_op_bits_data,
output io_rx_valid,
output [7:0] io_rx_bits
);
reg [11:0] ctrl_sck_div;
reg [31:0] GEN_2;
reg ctrl_sck_pol;
reg [31:0] GEN_31;
reg ctrl_sck_pha;
reg [31:0] GEN_52;
reg [1:0] ctrl_fmt_proto;
reg [31:0] GEN_67;
reg ctrl_fmt_endian;
reg [31:0] GEN_68;
reg ctrl_fmt_iodir;
reg [31:0] GEN_69;
wire proto_0;
wire proto_1;
wire proto_2;
wire accept;
wire sample;
wire setup;
wire last;
reg setup_d;
reg [31:0] GEN_70;
reg T_119;
reg [31:0] GEN_71;
reg T_120;
reg [31:0] GEN_72;
reg sample_d;
reg [31:0] GEN_73;
reg T_122;
reg [31:0] GEN_74;
reg T_123;
reg [31:0] GEN_75;
reg last_d;
reg [31:0] GEN_76;
reg [7:0] scnt;
reg [31:0] GEN_77;
reg [11:0] tcnt;
reg [31:0] GEN_78;
wire stop;
wire beat;
wire [11:0] T_127;
wire [12:0] T_129;
wire [11:0] decr;
wire sched;
wire [11:0] T_130;
reg sck;
reg [31:0] GEN_79;
reg cref;
reg [31:0] GEN_80;
wire cinv;
wire [1:0] T_133;
wire [1:0] T_134;
wire [3:0] rxd;
wire samples_0;
wire [1:0] samples_1;
reg [7:0] buffer;
reg [31:0] GEN_81;
wire T_135;
wire T_136;
wire T_137;
wire T_138;
wire T_139;
wire T_140;
wire T_141;
wire T_142;
wire T_143;
wire [1:0] T_144;
wire [1:0] T_145;
wire [3:0] T_146;
wire [1:0] T_147;
wire [1:0] T_148;
wire [3:0] T_149;
wire [7:0] T_150;
wire [7:0] buffer_in;
wire T_151;
wire shift;
wire [6:0] T_152;
wire [6:0] T_153;
wire [6:0] T_154;
wire T_155;
wire T_157;
wire [7:0] T_158;
wire [5:0] T_159;
wire [5:0] T_160;
wire [5:0] T_161;
wire [1:0] T_162;
wire [1:0] T_163;
wire [7:0] T_164;
wire [3:0] T_165;
wire [3:0] T_166;
wire [3:0] T_167;
wire [3:0] T_169;
wire [7:0] T_170;
wire [7:0] T_172;
wire [7:0] T_174;
wire [7:0] T_176;
wire [7:0] T_178;
wire [7:0] T_179;
wire [7:0] T_180;
reg [3:0] txd;
reg [31:0] GEN_82;
wire [3:0] T_182;
wire [3:0] txd_in;
wire [1:0] T_184;
wire txd_sel_0;
wire txd_sel_1;
wire txd_sel_2;
wire txd_shf_0;
wire [1:0] txd_shf_1;
wire T_186;
wire [1:0] T_188;
wire [3:0] T_190;
wire [1:0] GEN_65;
wire [1:0] T_192;
wire [3:0] GEN_66;
wire [3:0] T_193;
wire [3:0] T_194;
wire [3:0] GEN_0;
wire T_195;
wire T_196;
wire txen_1;
wire txen_0;
wire T_208_0;
wire T_208_1;
wire T_208_2;
wire T_208_3;
wire T_215;
wire T_216;
wire T_217;
wire T_218;
reg done;
reg [31:0] GEN_83;
wire T_221;
wire T_222;
wire T_224;
wire T_225;
wire T_226;
wire T_227;
wire T_228;
wire T_229;
wire T_230;
wire [1:0] T_231;
wire [1:0] T_232;
wire [3:0] T_233;
wire [1:0] T_234;
wire [1:0] T_235;
wire [3:0] T_236;
wire [7:0] T_237;
wire [7:0] T_238;
reg xfr;
reg [31:0] GEN_84;
wire GEN_1;
wire T_243;
wire T_245;
wire T_246;
wire GEN_3;
wire GEN_4;
wire GEN_5;
wire [11:0] GEN_6;
wire GEN_7;
wire GEN_8;
wire GEN_9;
wire GEN_10;
wire [11:0] GEN_11;
wire GEN_12;
wire GEN_13;
wire GEN_14;
wire GEN_15;
wire [11:0] GEN_16;
wire T_252;
wire T_253;
wire T_254;
wire T_257;
wire GEN_17;
wire GEN_18;
wire GEN_19;
wire GEN_20;
wire GEN_21;
wire GEN_22;
wire GEN_23;
wire T_260;
wire [1:0] GEN_24;
wire GEN_25;
wire GEN_26;
wire T_263;
wire T_266;
wire [7:0] GEN_27;
wire GEN_28;
wire GEN_29;
wire GEN_30;
wire GEN_32;
wire [11:0] GEN_33;
wire GEN_34;
wire GEN_35;
wire GEN_36;
wire [11:0] GEN_37;
wire GEN_38;
wire GEN_39;
wire [11:0] GEN_40;
wire [1:0] GEN_41;
wire GEN_42;
wire GEN_43;
wire GEN_44;
wire [7:0] GEN_45;
wire GEN_46;
wire GEN_47;
wire GEN_48;
wire [11:0] GEN_49;
wire GEN_50;
wire GEN_51;
wire [11:0] GEN_53;
wire [1:0] GEN_54;
wire GEN_55;
wire GEN_56;
wire GEN_57;
wire [7:0] GEN_58;
wire GEN_59;
wire GEN_60;
wire GEN_61;
wire [11:0] GEN_62;
wire GEN_63;
wire GEN_64;
assign io_port_sck = sck;
assign io_port_dq_0_o = T_215;
assign io_port_dq_0_oe = txen_0;
assign io_port_dq_1_o = T_216;
assign io_port_dq_1_oe = txen_1;
assign io_port_dq_2_o = T_217;
assign io_port_dq_2_oe = T_196;
assign io_port_dq_3_o = T_218;
assign io_port_dq_3_oe = io_port_dq_2_oe;
assign io_port_cs_0 = T_208_0;
assign io_port_cs_1 = T_208_1;
assign io_port_cs_2 = T_208_2;
assign io_port_cs_3 = T_208_3;
assign io_op_ready = T_260;
assign io_rx_valid = done;
assign io_rx_bits = T_238;
assign proto_0 = 2'h0 == ctrl_fmt_proto;
assign proto_1 = 2'h1 == ctrl_fmt_proto;
assign proto_2 = 2'h2 == ctrl_fmt_proto;
assign accept = GEN_21;
assign sample = GEN_14;
assign setup = GEN_60;
assign last = GEN_20;
assign stop = scnt == 8'h0;
assign beat = tcnt == 12'h0;
assign T_127 = beat ? {{4'd0}, scnt} : tcnt;
assign T_129 = T_127 - 12'h1;
assign decr = T_129[11:0];
assign sched = GEN_1;
assign T_130 = sched ? ctrl_sck_div : decr;
assign cinv = ctrl_sck_pha ^ ctrl_sck_pol;
assign T_133 = {io_port_dq_1_i,io_port_dq_0_i};
assign T_134 = {io_port_dq_3_i,io_port_dq_2_i};
assign rxd = {T_134,T_133};
assign samples_0 = rxd[1];
assign samples_1 = rxd[1:0];
assign T_135 = io_ctrl_fmt_endian == 1'h0;
assign T_136 = io_op_bits_data[0];
assign T_137 = io_op_bits_data[1];
assign T_138 = io_op_bits_data[2];
assign T_139 = io_op_bits_data[3];
assign T_140 = io_op_bits_data[4];
assign T_141 = io_op_bits_data[5];
assign T_142 = io_op_bits_data[6];
assign T_143 = io_op_bits_data[7];
assign T_144 = {T_142,T_143};
assign T_145 = {T_140,T_141};
assign T_146 = {T_145,T_144};
assign T_147 = {T_138,T_139};
assign T_148 = {T_136,T_137};
assign T_149 = {T_148,T_147};
assign T_150 = {T_149,T_146};
assign buffer_in = T_135 ? io_op_bits_data : T_150;
assign T_151 = sample_d & stop;
assign shift = setup_d | T_151;
assign T_152 = buffer[6:0];
assign T_153 = buffer[7:1];
assign T_154 = shift ? T_152 : T_153;
assign T_155 = buffer[0];
assign T_157 = sample_d ? samples_0 : T_155;
assign T_158 = {T_154,T_157};
assign T_159 = buffer[5:0];
assign T_160 = buffer[7:2];
assign T_161 = shift ? T_159 : T_160;
assign T_162 = buffer[1:0];
assign T_163 = sample_d ? samples_1 : T_162;
assign T_164 = {T_161,T_163};
assign T_165 = buffer[3:0];
assign T_166 = buffer[7:4];
assign T_167 = shift ? T_165 : T_166;
assign T_169 = sample_d ? rxd : T_165;
assign T_170 = {T_167,T_169};
assign T_172 = proto_0 ? T_158 : 8'h0;
assign T_174 = proto_1 ? T_164 : 8'h0;
assign T_176 = proto_2 ? T_170 : 8'h0;
assign T_178 = T_172 | T_174;
assign T_179 = T_178 | T_176;
assign T_180 = T_179;
assign T_182 = buffer_in[7:4];
assign txd_in = accept ? T_182 : T_166;
assign T_184 = accept ? io_ctrl_fmt_proto : ctrl_fmt_proto;
assign txd_sel_0 = 2'h0 == T_184;
assign txd_sel_1 = 2'h1 == T_184;
assign txd_sel_2 = 2'h2 == T_184;
assign txd_shf_0 = txd_in[3];
assign txd_shf_1 = txd_in[3:2];
assign T_186 = txd_sel_0 ? txd_shf_0 : 1'h0;
assign T_188 = txd_sel_1 ? txd_shf_1 : 2'h0;
assign T_190 = txd_sel_2 ? txd_in : 4'h0;
assign GEN_65 = {{1'd0}, T_186};
assign T_192 = GEN_65 | T_188;
assign GEN_66 = {{2'd0}, T_192};
assign T_193 = GEN_66 | T_190;
assign T_194 = T_193;
assign GEN_0 = setup ? T_194 : txd;
assign T_195 = proto_1 & ctrl_fmt_iodir;
assign T_196 = proto_2 & ctrl_fmt_iodir;
assign txen_1 = T_195 | T_196;
assign txen_0 = proto_0 | txen_1;
assign T_208_0 = 1'h1;
assign T_208_1 = 1'h1;
assign T_208_2 = 1'h1;
assign T_208_3 = 1'h1;
assign T_215 = txd[0];
assign T_216 = txd[1];
assign T_217 = txd[2];
assign T_218 = txd[3];
assign T_221 = done | last_d;
assign T_222 = ctrl_fmt_endian == 1'h0;
assign T_224 = buffer[1];
assign T_225 = buffer[2];
assign T_226 = buffer[3];
assign T_227 = buffer[4];
assign T_228 = buffer[5];
assign T_229 = buffer[6];
assign T_230 = buffer[7];
assign T_231 = {T_229,T_230};
assign T_232 = {T_227,T_228};
assign T_233 = {T_232,T_231};
assign T_234 = {T_225,T_226};
assign T_235 = {T_155,T_224};
assign T_236 = {T_235,T_234};
assign T_237 = {T_236,T_233};
assign T_238 = T_222 ? buffer : T_237;
assign GEN_1 = stop ? 1'h1 : beat;
assign T_243 = stop == 1'h0;
assign T_245 = cref == 1'h0;
assign T_246 = cref ^ cinv;
assign GEN_3 = xfr ? T_246 : sck;
assign GEN_4 = xfr ? cref : 1'h0;
assign GEN_5 = xfr ? T_245 : 1'h0;
assign GEN_6 = T_245 ? decr : {{4'd0}, scnt};
assign GEN_7 = beat ? T_245 : cref;
assign GEN_8 = beat ? GEN_3 : sck;
assign GEN_9 = beat ? GEN_4 : 1'h0;
assign GEN_10 = beat ? GEN_5 : 1'h0;
assign GEN_11 = beat ? GEN_6 : {{4'd0}, scnt};
assign GEN_12 = T_243 ? GEN_7 : cref;
assign GEN_13 = T_243 ? GEN_8 : sck;
assign GEN_14 = T_243 ? GEN_9 : 1'h0;
assign GEN_15 = T_243 ? GEN_10 : 1'h0;
assign GEN_16 = T_243 ? GEN_11 : {{4'd0}, scnt};
assign T_252 = scnt == 8'h1;
assign T_253 = beat & cref;
assign T_254 = T_253 & xfr;
assign T_257 = beat & T_245;
assign GEN_17 = T_257 ? 1'h1 : stop;
assign GEN_18 = T_257 ? 1'h0 : GEN_15;
assign GEN_19 = T_257 ? ctrl_sck_pol : GEN_13;
assign GEN_20 = T_252 ? T_254 : 1'h0;
assign GEN_21 = T_252 ? GEN_17 : stop;
assign GEN_22 = T_252 ? GEN_18 : GEN_15;
assign GEN_23 = T_252 ? GEN_19 : GEN_13;
assign T_260 = accept & done;
assign GEN_24 = io_op_bits_stb ? io_ctrl_fmt_proto : ctrl_fmt_proto;
assign GEN_25 = io_op_bits_stb ? io_ctrl_fmt_endian : ctrl_fmt_endian;
assign GEN_26 = io_op_bits_stb ? io_ctrl_fmt_iodir : ctrl_fmt_iodir;
assign T_263 = 1'h0 == io_op_bits_fn;
assign T_266 = io_op_bits_cnt == 8'h0;
assign GEN_27 = T_263 ? buffer_in : T_180;
assign GEN_28 = T_263 ? cinv : GEN_23;
assign GEN_29 = T_263 ? 1'h1 : GEN_22;
assign GEN_30 = T_263 ? T_266 : T_221;
assign GEN_32 = io_op_bits_stb ? io_ctrl_sck_pol : GEN_28;
assign GEN_33 = io_op_bits_stb ? io_ctrl_sck_div : ctrl_sck_div;
assign GEN_34 = io_op_bits_stb ? io_ctrl_sck_pol : ctrl_sck_pol;
assign GEN_35 = io_op_bits_stb ? io_ctrl_sck_pha : ctrl_sck_pha;
assign GEN_36 = io_op_bits_fn ? GEN_32 : GEN_28;
assign GEN_37 = io_op_bits_fn ? GEN_33 : ctrl_sck_div;
assign GEN_38 = io_op_bits_fn ? GEN_34 : ctrl_sck_pol;
assign GEN_39 = io_op_bits_fn ? GEN_35 : ctrl_sck_pha;
assign GEN_40 = io_op_valid ? {{4'd0}, io_op_bits_cnt} : GEN_16;
assign GEN_41 = io_op_valid ? GEN_24 : ctrl_fmt_proto;
assign GEN_42 = io_op_valid ? GEN_25 : ctrl_fmt_endian;
assign GEN_43 = io_op_valid ? GEN_26 : ctrl_fmt_iodir;
assign GEN_44 = io_op_valid ? T_263 : xfr;
assign GEN_45 = io_op_valid ? GEN_27 : T_180;
assign GEN_46 = io_op_valid ? GEN_36 : GEN_23;
assign GEN_47 = io_op_valid ? GEN_29 : GEN_22;
assign GEN_48 = io_op_valid ? GEN_30 : T_221;
assign GEN_49 = io_op_valid ? GEN_37 : ctrl_sck_div;
assign GEN_50 = io_op_valid ? GEN_38 : ctrl_sck_pol;
assign GEN_51 = io_op_valid ? GEN_39 : ctrl_sck_pha;
assign GEN_53 = T_260 ? GEN_40 : GEN_16;
assign GEN_54 = T_260 ? GEN_41 : ctrl_fmt_proto;
assign GEN_55 = T_260 ? GEN_42 : ctrl_fmt_endian;
assign GEN_56 = T_260 ? GEN_43 : ctrl_fmt_iodir;
assign GEN_57 = T_260 ? GEN_44 : xfr;
assign GEN_58 = T_260 ? GEN_45 : T_180;
assign GEN_59 = T_260 ? GEN_46 : GEN_23;
assign GEN_60 = T_260 ? GEN_47 : GEN_22;
assign GEN_61 = T_260 ? GEN_48 : T_221;
assign GEN_62 = T_260 ? GEN_49 : ctrl_sck_div;
assign GEN_63 = T_260 ? GEN_50 : ctrl_sck_pol;
assign GEN_64 = T_260 ? GEN_51 : ctrl_sck_pha;
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_sck_div <= 12'b0;
ctrl_sck_pol <= 1'b0;
ctrl_sck_pha <= 1'b0;
ctrl_fmt_proto <= 2'b0;
ctrl_fmt_endian <= 1'b0;
ctrl_fmt_iodir <= 1'b0;
setup_d <= 1'b0;
tcnt <= 12'b0;
sck <= 1'b0;
buffer <= 8'b0;
xfr <= 1'b0;
end
else begin
if (T_260) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_div <= io_ctrl_sck_div;
end
end
end
end
if (T_260) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_pol <= io_ctrl_sck_pol;
end
end
end
end
if (T_260) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_pha <= io_ctrl_sck_pha;
end
end
end
end
if (T_260) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_proto <= io_ctrl_fmt_proto;
end
end
end
if (T_260) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_endian <= io_ctrl_fmt_endian;
end
end
end
if (T_260) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_iodir <= io_ctrl_fmt_iodir;
end
end
end
setup_d <= setup;
if (sched) begin
tcnt <= ctrl_sck_div;
end else begin
tcnt <= decr;
end
if (T_260) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
sck <= io_ctrl_sck_pol;
end else begin
if (T_263) begin
sck <= cinv;
end else begin
if (T_252) begin
if (T_257) begin
sck <= ctrl_sck_pol;
end else begin
if (T_243) begin
if (beat) begin
if (xfr) begin
sck <= T_246;
end
end
end
end
end else begin
if (T_243) begin
if (beat) begin
if (xfr) begin
sck <= T_246;
end
end
end
end
end
end
end else begin
if (T_263) begin
sck <= cinv;
end else begin
if (T_252) begin
if (T_257) begin
sck <= ctrl_sck_pol;
end else begin
if (T_243) begin
if (beat) begin
if (xfr) begin
sck <= T_246;
end
end
end
end
end else begin
if (T_243) begin
if (beat) begin
if (xfr) begin
sck <= T_246;
end
end
end
end
end
end
end else begin
if (T_252) begin
if (T_257) begin
sck <= ctrl_sck_pol;
end else begin
sck <= GEN_13;
end
end else begin
sck <= GEN_13;
end
end
end else begin
if (T_252) begin
if (T_257) begin
sck <= ctrl_sck_pol;
end else begin
sck <= GEN_13;
end
end else begin
sck <= GEN_13;
end
end
if (T_260) begin
if (io_op_valid) begin
if (T_263) begin
if (T_135) begin
buffer <= io_op_bits_data;
end else begin
buffer <= T_150;
end
end else begin
buffer <= T_180;
end
end else begin
buffer <= T_180;
end
end else begin
buffer <= T_180;
end
if (T_260) begin
if (io_op_valid) begin
xfr <= T_263;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
cref <= 1'h1;
end else begin
if (T_243) begin
if (beat) begin
cref <= T_245;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
txd <= 4'h0;
end else begin
if (setup) begin
txd <= T_194;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
done <= 1'h1;
end else begin
if (T_260) begin
if (io_op_valid) begin
if (T_263) begin
done <= T_266;
end else begin
done <= T_221;
end
end else begin
done <= T_221;
end
end else begin
done <= T_221;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
T_119 <= 1'h0;
end else begin
T_119 <= sample;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_120 <= 1'h0;
end else begin
T_120 <= T_119;
end
always @(posedge clock or posedge reset)
if (reset) begin
sample_d <= 1'h0;
end else begin
sample_d <= T_120;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_122 <= 1'h0;
end else begin
T_122 <= last;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_123 <= 1'h0;
end else begin
T_123 <= T_122;
end
always @(posedge clock or posedge reset)
if (reset) begin
last_d <= 1'h0;
end else begin
last_d <= T_123;
end
always @(posedge clock or posedge reset)
if (reset) begin
scnt <= 8'h0;
end else begin
scnt <= GEN_53[7:0];
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_alulogic.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
//
// Module Name: sparc_exu_alulogic
// Description: This block implements and, or, xor, xnor, nand, nor
// and pass_rs2_data. And, or, Xor and pass are muxed together
// and then xored with an inversion signal to create
// xnor, nand and nor. Both inputs are buffered before being
// used and the rs2_data signal is buffered again before going
// to the mux.
*/
module sparc_exu_alulogic (/*AUTOARG*/
// Outputs
logic_out,
// Inputs
rs1_data, rs2_data, isand, isor, isxor, pass_rs2_data, inv_logic,
ifu_exu_sethi_inst_e
);
input [63:0] rs1_data; // 1st input operand
input [63:0] rs2_data; // 2nd input operand
input isand;
input isor;
input isxor;
input pass_rs2_data;
input inv_logic;
input ifu_exu_sethi_inst_e; // zero out top half of rs2 on mov
output [63:0] logic_out; // output of logic block
wire [63:0] rs1_data_bf1; // buffered rs1_data
wire [63:0] rs2_data_bf1; // buffered rs2_data
wire [63:0] mov_data;
wire [63:0] result_and; // rs1_data & rs2_data
wire [63:0] result_or; // rs1_data | rs2_data
wire [63:0] result_xor; // rs1_data ^ rs2_data
wire [63:0] rs2_xor_invert; // output of mux between various results
// mux between various results
mux4ds #(64) logic_mux(.dout(logic_out[63:0]),
.in0(result_and[63:0]),
.in1(result_or[63:0]),
.in2(result_xor[63:0]),
.in3(mov_data[63:0]),
.sel0(isand),
.sel1(isor),
.sel2(isxor),
.sel3(pass_rs2_data));
// buffer inputs
dp_buffer #(64) rs1_data_buf(.dout(rs1_data_bf1[63:0]), .in(rs1_data[63:0]));
dp_buffer #(64) rs2_data_buf(.dout(rs2_data_bf1[63:0]), .in(rs2_data[63:0]));
// zero out top of rs2 for sethi_inst
assign mov_data[63:32] = rs2_data_bf1[63:32] & {32{~ifu_exu_sethi_inst_e}};
dp_buffer #(32) rs2_data_buf2(.dout(mov_data[31:0]), .in(rs2_data_bf1[31:0]));
// invert input2 for andn, orn, xnor
assign rs2_xor_invert[63:0] = rs2_data_bf1[63:0] ^ {64{inv_logic}};
// do boolean ops
assign result_and = rs1_data_bf1 & rs2_xor_invert;
assign result_or = rs1_data_bf1 | rs2_xor_invert;
assign result_xor = rs1_data_bf1 ^ rs2_xor_invert;
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module bt656cap_colorspace(
input vid_clk,
input stb_i,
input field_i,
input [31:0] ycc422,
output reg stb_o,
output reg field_o,
output [31:0] rgb565
);
/* Datapath */
wire signed [7:0] cb = ycc422[31:24] - 8'd128;
wire signed [7:0] y0 = ycc422[23:16] - 8'd128;
wire signed [7:0] cr = ycc422[15: 8] - 8'd128;
wire signed [7:0] y1 = ycc422[ 7: 0] - 8'd128;
reg mult_sela;
reg [1:0] mult_selb;
wire signed [7:0] mult_opa = mult_sela ? cr : cb;
reg signed [9:0] mult_opb;
always @(*) begin
case(mult_selb)
2'd0: mult_opb = 10'd359; // 1.402
2'd1: mult_opb = 10'd454; // 1.772
2'd2: mult_opb = 10'd88; // 0.344
2'd3: mult_opb = 10'd183; // 0.714
endcase
end
reg signed [17:0] mult_result;
wire signed [9:0] mult_result_t = mult_result[17:8];
always @(posedge vid_clk) mult_result <= mult_opa*mult_opb;
reg signed [9:0] int_r0;
reg signed [9:0] int_g0;
reg signed [9:0] int_b0;
reg signed [9:0] int_r1;
reg signed [9:0] int_g1;
reg signed [9:0] int_b1;
reg load_y;
reg add_r;
reg sub_g;
reg add_b;
always @(posedge vid_clk) begin
if(load_y) begin
int_r0 <= y0;
int_g0 <= y0;
int_b0 <= y0;
int_r1 <= y1;
int_g1 <= y1;
int_b1 <= y1;
end
if(add_r) begin
int_r0 <= int_r0 + mult_result_t;
int_r1 <= int_r1 + mult_result_t;
end
if(sub_g) begin
int_g0 <= int_g0 - mult_result_t;
int_g1 <= int_g1 - mult_result_t;
end
if(add_b) begin
int_b0 <= int_b0 + mult_result_t;
int_b1 <= int_b1 + mult_result_t;
end
end
/* Output generator */
reg fsm_stb;
reg fsm_field;
wire signed [9:0] fsm_r0 = int_r0;
wire signed [9:0] fsm_g0 = int_g0 - mult_result_t;
wire signed [9:0] fsm_b0 = int_b0;
wire signed [9:0] fsm_r1 = int_r1;
wire signed [9:0] fsm_g1 = int_g1 - mult_result_t;
wire signed [9:0] fsm_b1 = int_b1;
reg [7:0] out_r0;
reg [7:0] out_g0;
reg [7:0] out_b0;
reg [7:0] out_r1;
reg [7:0] out_g1;
reg [7:0] out_b1;
always @(posedge vid_clk) begin
stb_o <= 1'b0;
if(fsm_stb) begin
stb_o <= 1'b1;
field_o <= fsm_field;
out_r0 <= (fsm_r0[7:0] | {8{fsm_r0[8]}}) & {8{~fsm_r0[9]}};
out_g0 <= (fsm_g0[7:0] | {8{fsm_g0[8]}}) & {8{~fsm_g0[9]}};
out_b0 <= (fsm_b0[7:0] | {8{fsm_b0[8]}}) & {8{~fsm_b0[9]}};
out_r1 <= (fsm_r1[7:0] | {8{fsm_r1[8]}}) & {8{~fsm_r1[9]}};
out_g1 <= (fsm_g1[7:0] | {8{fsm_g1[8]}}) & {8{~fsm_g1[9]}};
out_b1 <= (fsm_b1[7:0] | {8{fsm_b1[8]}}) & {8{~fsm_b1[9]}};
end
end
assign rgb565 = {out_r0[7:3], out_g0[7:2], out_b0[7:3],
out_r1[7:3], out_g1[7:2], out_b1[7:3]};
/* Forward field */
always @(posedge vid_clk) begin
if(stb_i)
fsm_field <= field_i;
end
/* Controller */
reg [2:0] state;
reg [2:0] next_state;
parameter S1 = 3'd0;
parameter S2 = 3'd1;
parameter S3 = 3'd2;
parameter S4 = 3'd3;
parameter S5 = 3'd4;
initial state = S1;
always @(posedge vid_clk) begin
state <= next_state;
//$display("state: %d->%d (%d)", state, next_state, stb_i);
end
always @(*) begin
mult_sela = 1'bx;
mult_selb = 2'bx;
load_y = 1'b0;
add_r = 1'b0;
sub_g = 1'b0;
add_b = 1'b0;
fsm_stb = 1'b0;
next_state = state;
case(state)
S1: begin
load_y = 1'b1;
mult_sela = 1'b1; // 1.402*Cr
mult_selb = 2'd0;
if(stb_i)
next_state = S2;
end
S2: begin
add_r = 1'b1;
mult_sela = 1'b0; // 1.772*Cb
mult_selb = 2'd1;
next_state = S3;
end
S3: begin
add_b = 1'b1;
mult_sela = 1'b0; // 0.344*Cb
mult_selb = 2'd2;
next_state = S4;
end
S4: begin
sub_g = 1'b1;
mult_sela = 1'b1; // 0.714*Cr
mult_selb = 2'd3;
next_state = S5;
end
S5: begin
fsm_stb = 1'b1;
load_y = 1'b1;
mult_sela = 1'b1; // 1.402*Cr
mult_selb = 2'd0;
if(stb_i)
next_state = S2;
else
next_state = S1;
end
endcase
end
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.1
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="doHist,hls_ip_2016_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.860000,HLS_SYN_LAT=524546,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=95,HLS_SYN_LUT=210}" *)
module doHist (
ap_clk,
ap_rst_n,
inStream_TDATA,
inStream_TVALID,
inStream_TREADY,
inStream_TKEEP,
inStream_TSTRB,
inStream_TUSER,
inStream_TLAST,
inStream_TID,
inStream_TDEST,
histo_Addr_A,
histo_EN_A,
histo_WEN_A,
histo_Din_A,
histo_Dout_A,
histo_Clk_A,
histo_Rst_A,
s_axi_CTRL_BUS_AWVALID,
s_axi_CTRL_BUS_AWREADY,
s_axi_CTRL_BUS_AWADDR,
s_axi_CTRL_BUS_WVALID,
s_axi_CTRL_BUS_WREADY,
s_axi_CTRL_BUS_WDATA,
s_axi_CTRL_BUS_WSTRB,
s_axi_CTRL_BUS_ARVALID,
s_axi_CTRL_BUS_ARREADY,
s_axi_CTRL_BUS_ARADDR,
s_axi_CTRL_BUS_RVALID,
s_axi_CTRL_BUS_RREADY,
s_axi_CTRL_BUS_RDATA,
s_axi_CTRL_BUS_RRESP,
s_axi_CTRL_BUS_BVALID,
s_axi_CTRL_BUS_BREADY,
s_axi_CTRL_BUS_BRESP,
interrupt
);
parameter ap_ST_st1_fsm_0 = 4'b1;
parameter ap_ST_st2_fsm_1 = 4'b10;
parameter ap_ST_st3_fsm_2 = 4'b100;
parameter ap_ST_st4_fsm_3 = 4'b1000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv32_2 = 32'b10;
parameter C_S_AXI_CTRL_BUS_DATA_WIDTH = 32;
parameter ap_const_int64_8 = 8;
parameter C_S_AXI_CTRL_BUS_ADDR_WIDTH = 4;
parameter C_S_AXI_DATA_WIDTH = 32;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv9_0 = 9'b000000000;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv19_0 = 19'b0000000000000000000;
parameter ap_const_lv4_0 = 4'b0000;
parameter ap_const_lv4_F = 4'b1111;
parameter ap_const_lv9_100 = 9'b100000000;
parameter ap_const_lv9_1 = 9'b1;
parameter ap_const_lv19_40000 = 19'b1000000000000000000;
parameter ap_const_lv19_1 = 19'b1;
parameter C_S_AXI_CTRL_BUS_WSTRB_WIDTH = (C_S_AXI_CTRL_BUS_DATA_WIDTH / ap_const_int64_8);
parameter C_S_AXI_WSTRB_WIDTH = (C_S_AXI_DATA_WIDTH / ap_const_int64_8);
input ap_clk;
input ap_rst_n;
input [7:0] inStream_TDATA;
input inStream_TVALID;
output inStream_TREADY;
input [0:0] inStream_TKEEP;
input [0:0] inStream_TSTRB;
input [1:0] inStream_TUSER;
input [0:0] inStream_TLAST;
input [4:0] inStream_TID;
input [5:0] inStream_TDEST;
output [31:0] histo_Addr_A;
output histo_EN_A;
output [3:0] histo_WEN_A;
output [31:0] histo_Din_A;
input [31:0] histo_Dout_A;
output histo_Clk_A;
output histo_Rst_A;
input s_axi_CTRL_BUS_AWVALID;
output s_axi_CTRL_BUS_AWREADY;
input [C_S_AXI_CTRL_BUS_ADDR_WIDTH - 1 : 0] s_axi_CTRL_BUS_AWADDR;
input s_axi_CTRL_BUS_WVALID;
output s_axi_CTRL_BUS_WREADY;
input [C_S_AXI_CTRL_BUS_DATA_WIDTH - 1 : 0] s_axi_CTRL_BUS_WDATA;
input [C_S_AXI_CTRL_BUS_WSTRB_WIDTH - 1 : 0] s_axi_CTRL_BUS_WSTRB;
input s_axi_CTRL_BUS_ARVALID;
output s_axi_CTRL_BUS_ARREADY;
input [C_S_AXI_CTRL_BUS_ADDR_WIDTH - 1 : 0] s_axi_CTRL_BUS_ARADDR;
output s_axi_CTRL_BUS_RVALID;
input s_axi_CTRL_BUS_RREADY;
output [C_S_AXI_CTRL_BUS_DATA_WIDTH - 1 : 0] s_axi_CTRL_BUS_RDATA;
output [1:0] s_axi_CTRL_BUS_RRESP;
output s_axi_CTRL_BUS_BVALID;
input s_axi_CTRL_BUS_BREADY;
output [1:0] s_axi_CTRL_BUS_BRESP;
output interrupt;
reg inStream_TREADY;
reg histo_EN_A;
reg[3:0] histo_WEN_A;
reg[31:0] histo_Din_A;
reg histo_Rst_A;
reg ap_rst_n_inv;
wire ap_start;
reg ap_done;
reg ap_idle;
(* fsm_encoding = "none" *) reg [3:0] ap_CS_fsm;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_21;
reg ap_ready;
reg inStream_TDATA_blk_n;
reg ap_sig_cseq_ST_st3_fsm_2;
reg ap_sig_53;
wire [0:0] exitcond_fu_148_p2;
wire [8:0] idxHist_1_fu_137_p2;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_102;
wire [18:0] idxPixel_1_fu_154_p2;
reg [18:0] idxPixel_1_reg_187;
reg ap_sig_108;
reg [7:0] histo_addr_1_reg_192;
reg [8:0] idxHist_reg_109;
wire [0:0] exitcond2_fu_131_p2;
reg [18:0] idxPixel_reg_120;
reg ap_sig_cseq_ST_st4_fsm_3;
reg ap_sig_130;
wire [63:0] tmp_fu_143_p1;
wire [63:0] tmp_3_fu_164_p1;
reg [31:0] histo_Addr_A_orig;
wire [31:0] tmp_4_fu_169_p2;
reg [3:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 ap_CS_fsm = 4'b1;
end
doHist_CTRL_BUS_s_axi #(
.C_S_AXI_ADDR_WIDTH( C_S_AXI_CTRL_BUS_ADDR_WIDTH ),
.C_S_AXI_DATA_WIDTH( C_S_AXI_CTRL_BUS_DATA_WIDTH ))
doHist_CTRL_BUS_s_axi_U(
.AWVALID(s_axi_CTRL_BUS_AWVALID),
.AWREADY(s_axi_CTRL_BUS_AWREADY),
.AWADDR(s_axi_CTRL_BUS_AWADDR),
.WVALID(s_axi_CTRL_BUS_WVALID),
.WREADY(s_axi_CTRL_BUS_WREADY),
.WDATA(s_axi_CTRL_BUS_WDATA),
.WSTRB(s_axi_CTRL_BUS_WSTRB),
.ARVALID(s_axi_CTRL_BUS_ARVALID),
.ARREADY(s_axi_CTRL_BUS_ARREADY),
.ARADDR(s_axi_CTRL_BUS_ARADDR),
.RVALID(s_axi_CTRL_BUS_RVALID),
.RREADY(s_axi_CTRL_BUS_RREADY),
.RDATA(s_axi_CTRL_BUS_RDATA),
.RRESP(s_axi_CTRL_BUS_RRESP),
.BVALID(s_axi_CTRL_BUS_BVALID),
.BREADY(s_axi_CTRL_BUS_BREADY),
.BRESP(s_axi_CTRL_BUS_BRESP),
.ACLK(ap_clk),
.ARESET(ap_rst_n_inv),
.ACLK_EN(1'b1),
.ap_start(ap_start),
.interrupt(interrupt),
.ap_ready(ap_ready),
.ap_done(ap_done),
.ap_idle(ap_idle)
);
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) & (1'b0 == exitcond2_fu_131_p2))) begin
idxHist_reg_109 <= idxHist_1_fu_137_p2;
end else if (((1'b1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == 1'b0))) begin
idxHist_reg_109 <= ap_const_lv9_0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) & ~(1'b0 == exitcond2_fu_131_p2))) begin
idxPixel_reg_120 <= ap_const_lv19_0;
end else if ((1'b1 == ap_sig_cseq_ST_st4_fsm_3)) begin
idxPixel_reg_120 <= idxPixel_1_reg_187;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & (exitcond_fu_148_p2 == 1'b0) & ~ap_sig_108)) begin
histo_addr_1_reg_192 <= tmp_3_fu_164_p1;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_108)) begin
idxPixel_1_reg_187 <= idxPixel_1_fu_154_p2;
end
end
always @ (*) begin
if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_108 & ~(exitcond_fu_148_p2 == 1'b0))) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_108 & ~(exitcond_fu_148_p2 == 1'b0))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if (ap_sig_21) begin
ap_sig_cseq_ST_st1_fsm_0 = 1'b1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = 1'b0;
end
end
always @ (*) begin
if (ap_sig_102) begin
ap_sig_cseq_ST_st2_fsm_1 = 1'b1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = 1'b0;
end
end
always @ (*) begin
if (ap_sig_53) begin
ap_sig_cseq_ST_st3_fsm_2 = 1'b1;
end else begin
ap_sig_cseq_ST_st3_fsm_2 = 1'b0;
end
end
always @ (*) begin
if (ap_sig_130) begin
ap_sig_cseq_ST_st4_fsm_3 = 1'b1;
end else begin
ap_sig_cseq_ST_st4_fsm_3 = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_sig_cseq_ST_st4_fsm_3)) begin
histo_Addr_A_orig = histo_addr_1_reg_192;
end else if ((1'b1 == ap_sig_cseq_ST_st2_fsm_1)) begin
histo_Addr_A_orig = tmp_fu_143_p1;
end else if ((1'b1 == ap_sig_cseq_ST_st3_fsm_2)) begin
histo_Addr_A_orig = tmp_3_fu_164_p1;
end else begin
histo_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_sig_cseq_ST_st4_fsm_3)) begin
histo_Din_A = tmp_4_fu_169_p2;
end else if ((1'b1 == ap_sig_cseq_ST_st2_fsm_1)) begin
histo_Din_A = ap_const_lv32_0;
end else begin
histo_Din_A = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) | ((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_108) | (1'b1 == ap_sig_cseq_ST_st4_fsm_3))) begin
histo_EN_A = 1'b1;
end else begin
histo_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_sig_cseq_ST_st2_fsm_1) & (1'b0 == exitcond2_fu_131_p2)) | (1'b1 == ap_sig_cseq_ST_st4_fsm_3))) begin
histo_WEN_A = ap_const_lv4_F;
end else begin
histo_WEN_A = ap_const_lv4_0;
end
end
always @ (*) begin
if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & (exitcond_fu_148_p2 == 1'b0))) begin
inStream_TDATA_blk_n = inStream_TVALID;
end else begin
inStream_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & (exitcond_fu_148_p2 == 1'b0) & ~ap_sig_108)) begin
inStream_TREADY = 1'b1;
end else begin
inStream_TREADY = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 : begin
if (~(ap_start == 1'b0)) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 : begin
if ((1'b0 == exitcond2_fu_131_p2)) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end
end
ap_ST_st3_fsm_2 : begin
if ((~ap_sig_108 & ~(exitcond_fu_148_p2 == 1'b0))) begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end else if (((exitcond_fu_148_p2 == 1'b0) & ~ap_sig_108)) begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end else begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end
end
ap_ST_st4_fsm_3 : begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
always @ (*) begin
ap_rst_n_inv = ~ap_rst_n;
end
always @ (*) begin
ap_sig_102 = (1'b1 == ap_CS_fsm[ap_const_lv32_1]);
end
always @ (*) begin
ap_sig_108 = ((exitcond_fu_148_p2 == 1'b0) & (inStream_TVALID == 1'b0));
end
always @ (*) begin
ap_sig_130 = (1'b1 == ap_CS_fsm[ap_const_lv32_3]);
end
always @ (*) begin
ap_sig_21 = (ap_CS_fsm[ap_const_lv32_0] == 1'b1);
end
always @ (*) begin
ap_sig_53 = (1'b1 == ap_CS_fsm[ap_const_lv32_2]);
end
assign exitcond2_fu_131_p2 = ((idxHist_reg_109 == ap_const_lv9_100) ? 1'b1 : 1'b0);
assign exitcond_fu_148_p2 = ((idxPixel_reg_120 == ap_const_lv19_40000) ? 1'b1 : 1'b0);
assign histo_Addr_A = histo_Addr_A_orig << ap_const_lv32_2;
assign histo_Clk_A = ap_clk;
always @ (*) begin
histo_Rst_A = ~ap_rst_n;
end
assign idxHist_1_fu_137_p2 = (idxHist_reg_109 + ap_const_lv9_1);
assign idxPixel_1_fu_154_p2 = (idxPixel_reg_120 + ap_const_lv19_1);
assign tmp_3_fu_164_p1 = inStream_TDATA;
assign tmp_4_fu_169_p2 = (histo_Dout_A + ap_const_lv32_1);
assign tmp_fu_143_p1 = idxHist_reg_109;
endmodule //doHist
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: dacpll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.0 Build 33 02/05/2007 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dacpll (
areset,
inclk0,
c0);
input areset;
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.areset (areset),
.clk (sub_wire0),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b1),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbout (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0000",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 15625,
altpll_component.intended_device_family = "Cyclone",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.ppf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_inst.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_bb.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_waveforms.html TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_wave*.jpg FALSE FALSE
// Retrieval info: LIB_FILE: altera_mf
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_testbench_utilities.v ////
//// ////
//// This file is part of the "uart16550" project ////
//// http://www.opencores.org/projects/uart16550/ ////
//// ////
//// Author(s): ////
//// - [email protected] (Tadej Markovic) ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
`include "uart_defines.v"
`include "uart_testbench_defines.v"
`include "wb_model_defines.v"
module testbench_utilities;
// Basic system TASKs
//###################
// DO_RESET
task do_reset;
begin
testbench.wb_reset = 1'b1;
#1;
`UTILS_MSG("RESET signal asynchronously set.");
end
endtask // do_reset
// RELEASE_RESET
task release_reset;
begin
@(posedge testbench.wb_clk);
#1;
testbench.wb_reset = 1'b0;
`UTILS_MSG("RESET signal released synchronously to WB clk.");
end
endtask // release_reset
// DISABLE_CLK_GENERATORS
task disable_clk_generators;
input wb_clk_disable;
input rx_clk_disable;
input tx_clk_disable;
input tx_clk_divided_disable;
begin
`UTILS_MSG("Following clocks are DISABLED:");
if (wb_clk_disable)
begin
testbench.wb_clk_en = 1'b0;
`UTILS_MSG("- WB_clk");
end
if (rx_clk_disable)
begin
testbench.i_uart_device.rx_clk_en = 1'b0;
`UTILS_MSG("- RX_clk");
end
if (tx_clk_disable)
begin
testbench.i_uart_device.tx_clk_en = 1'b0;
`UTILS_MSG("- TX_clk");
end
if (tx_clk_divided_disable)
begin
testbench.i_uart_device.tx_clk_divided_en = 1'b0;
`UTILS_MSG("- TX_clk_divided");
end
if (~wb_clk_disable && ~rx_clk_disable && ~tx_clk_disable && ~tx_clk_divided_disable)
begin
`UTILS_MSG("- NO clocks DISABLED");
end
end
endtask // disable_clk_generators
// ENABLE_CLK_GENERATORS
task enable_clk_generators;
input wb_clk_enable;
input rx_clk_enable;
input tx_clk_enable;
input tx_clk_divided_enable;
begin
`UTILS_MSG("Following clocks are ENABLED:");
if (wb_clk_enable)
begin
testbench.wb_clk_en = 1'b1;
`UTILS_MSG("- WB_clk");
end
if (rx_clk_enable)
begin
testbench.i_uart_device.rx_clk_en = 1'b1;
`UTILS_MSG("- RX_clk");
end
if (tx_clk_enable)
begin
testbench.i_uart_device.tx_clk_en = 1'b1;
`UTILS_MSG("- TX_clk");
end
if (tx_clk_divided_enable)
begin
testbench.i_uart_device.tx_clk_divided_en = 1'b1;
`UTILS_MSG("- TX_clk_divided");
end
if (~wb_clk_enable && ~rx_clk_enable && ~tx_clk_enable && ~tx_clk_divided_enable)
begin
`UTILS_MSG("- NO clocks ENABLED");
end
end
endtask // enable_clk_generators
// SET_DEVICE_TX_RX_CLK_PERIOD
task set_device_tx_rx_clk_period;
input [31:0] clk_period;
begin
testbench.i_uart_device.T_clk_period = clk_period;
`UTILS_VAL1("UART DEVICE TX/RX clock period:", clk_period);
end
endtask // set_device_tx_rx_clk_period
// SET_DEVICE_TX_CLK_DELAY
task set_device_tx_clk_delay;
input [31:0] tx_clk_delay;
begin
testbench.i_uart_device.T_clk_delay = tx_clk_delay;
`UTILS_VAL1("UART DEVICE TX clock delay:", tx_clk_delay);
end
endtask // set_device_tx_clk_delay
// SET_DEVICE_TX_RX_CLK_DIVISOR
task set_device_tx_rx_clk_divisor;
input [31:0] clk_divisor;
begin
testbench.i_uart_device.T_divisor = clk_divisor;
`UTILS_VAL1("UART DEVICE TX/RX clock divisor:", clk_divisor);
end
endtask // set_device_tx_rx_clk_divisor
// SET_WB_CLK_PERIOD
task set_wb_clock_period;
input [31:0] clk_period;
begin
testbench.T_wb_clk_period = clk_period;
testbench.i_uart_device.T_clk_period = clk_period;
`UTILS_VAL1("WB & UART DEVICE TX/RX clock period:", clk_period);
end
endtask // set_wb_clock_period
// WB_CLK_FOLLOWS_DEVICE_RX_CLK
task wb_clk_follows_device_rx_clk;
input [31:0] time_delay_i;
integer time_delay;
begin
time_delay = time_delay_i;
@(posedge testbench.wb_clk);
testbench.wb_clk_en = 1'b0;
@(posedge testbench.i_uart_device.rx_clk);
#time_delay testbench.wb_clk = 1'b1;
testbench.wb_clk_en = 1'b1;
`UTILS_VAL1("WB followed UART DEVICE rising edge RX clock for time delay:", time_delay);
end
endtask // wb_clk_follows_device_rx_clk
// DEVICE_RX_CLK_FOLLOWS_WB_CLK
task device_rx_clk_follows_wb_clk;
input [31:0] time_delay_i;
integer time_delay;
begin
time_delay = time_delay_i;
@(posedge testbench.i_uart_device.rx_clk);
testbench.i_uart_device.rx_clk_en = 1'b0;
@(posedge testbench.wb_clk);
#time_delay testbench.i_uart_device.rx_clk = 1'b1;
testbench.i_uart_device.rx_clk_en = 1'b1;
`UTILS_VAL1("UART DEVICE RX followed WB rising edge clock for time delay:", time_delay);
end
endtask // device_rx_clk_follows_wb_clk
// Utility tasks
//##############
// WAIT_FOR_NUM_OF_WB_CLK
task wait_for_num_of_wb_clk;
input [31:0] num_of_clk;
integer count;
begin
count = 0;
`UTILS_VAL1("Waiting for following number of WB CLK periods:", num_of_clk);
while (count < num_of_clk)
begin
@(testbench.wb_clk);
count = count + 1'b1;
#1;
end
`UTILS_MSG("Waiting expired.");
end
endtask // wait_for_num_of_wb_clk
// WAIT_RX_FIFO_FULL_REGARDLESS_INT
task wait_rx_fifo_full_regardless_int;
integer count;
begin
count = 0;
`UTILS_MSG("Waiting for RX FIFO to get full regardless of interrupt.");
fork
begin:fifo_full_loop
while (testbench.i_uart_top.regs.receiver.fifo_rx.count <
testbench.i_uart_top.regs.receiver.fifo_rx.fifo_depth) // While RX fifo not full
begin
@(testbench.wb_clk);
end
disable counter;
`UTILS_MSG("RX FIFO got full.");
end
begin:counter
while (count < testbench.max_wait_cnt)
begin
@(testbench.wb_clk);
count = count + 1'b1;
#1;
end
disable fifo_full_loop;
`UTILS_ERROR("WAIT counter exceeded max value.");
end
join
end
endtask // wait_rx_fifo_full_regardless_int
// WAIT_RX_FIFO_FULL_UNLESS_INT
task wait_rx_fifo_full_unless_int;
integer count;
begin
count = 0;
`UTILS_MSG("Waiting for RX FIFO to get full unless interrupt occures before.");
fork
begin:fifo_full_loop
while (testbench.i_uart_top.regs.receiver.fifo_rx.count <
testbench.i_uart_top.regs.receiver.fifo_rx.fifo_depth) // While RX fifo not full
begin
@(testbench.wb_clk);
end
disable counter;
disable int_loop;
`UTILS_MSG("RX FIFO got full.");
end
begin:int_loop
if (testbench.ier_reg[3:0] == 4'h0)
begin
`UTILS_MSG("All interrupts are disabled.");
end
else
begin
`UTILS_MSG("Interrupts are enabled in IE Register.");
`UTILS_VAL1("IER:", testbench.ier_reg);
@(testbench.int_aserted);
`UTILS_MSG("Interrupt is asserted. The pending interrupt of highest priority is in II Register.");
`UTILS_VAL1("IIR:", testbench.iir_reg);
disable counter;
disable fifo_full_loop;
end
end
begin:counter
while (count < testbench.max_wait_cnt)
begin
@(testbench.wb_clk);
count = count + 1'b1;
#1;
end
disable int_loop;
disable fifo_full_loop;
`UTILS_ERROR("WAIT counter exceeded max value.");
end
join
end
endtask // wait_rx_fifo_full_unless_int
// UART Initialize TASKs
//######################
// POSSIBLE INITIALIZE TASKS - NOW FEW STEPS ARE MADE IN EACH testcase!!!
endmodule
|
// megafunction wizard: %ALTTEMP_SENSE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTTEMP_SENSE
// ============================================================
// File Name: temp_sense.v
// Megafunction Name(s):
// ALTTEMP_SENSE
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 263 08/02/2012 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//alttemp_sense CBX_AUTO_BLACKBOX="ALL" CLK_FREQUENCY="50.0" CLOCK_DIVIDER_ENABLE="on" CLOCK_DIVIDER_VALUE=80 DEVICE_FAMILY="Stratix V" NUMBER_OF_SAMPLES=128 POI_CAL_TEMPERATURE=85 SIM_TSDCALO=0 USE_WYS="on" USER_OFFSET_ENABLE="off" ce clk clr tsdcaldone tsdcalo ALTERA_INTERNAL_OPTIONS=SUPPRESS_DA_RULE_INTERNAL=C106
//VERSION_BEGIN 12.0SP2 cbx_alttemp_sense 2012:08:02:15:11:11:SJ cbx_cycloneii 2012:08:02:15:11:11:SJ cbx_lpm_add_sub 2012:08:02:15:11:11:SJ cbx_lpm_compare 2012:08:02:15:11:11:SJ cbx_lpm_counter 2012:08:02:15:11:11:SJ cbx_lpm_decode 2012:08:02:15:11:11:SJ cbx_mgl 2012:08:02:15:40:54:SJ cbx_stratix 2012:08:02:15:11:11:SJ cbx_stratixii 2012:08:02:15:11:11:SJ cbx_stratixiii 2012:08:02:15:11:11:SJ cbx_stratixv 2012:08:02:15:11:11:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = stratixv_tsdblock 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C106"} *)
module temp_sense_alttemp_sense_v8t
(
ce,
clk,
clr,
tsdcaldone,
tsdcalo) /* synthesis synthesis_clearbox=2 */;
input ce;
input clk;
input clr;
output tsdcaldone;
output [7:0] tsdcalo;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 ce;
tri0 clr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_sd1_tsdcaldone;
wire [7:0] wire_sd1_tsdcalo;
stratixv_tsdblock sd1
(
.ce(ce),
.clk(clk),
.clr(clr),
.tsdcaldone(wire_sd1_tsdcaldone),
.tsdcalo(wire_sd1_tsdcalo));
defparam
sd1.clock_divider_enable = "true",
sd1.clock_divider_value = 80,
sd1.sim_tsdcalo = 0,
sd1.lpm_type = "stratixv_tsdblock";
assign
tsdcaldone = wire_sd1_tsdcaldone,
tsdcalo = wire_sd1_tsdcalo;
endmodule //temp_sense_alttemp_sense_v8t
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module temp_sense (
ce,
clk,
clr,
tsdcaldone,
tsdcalo)/* synthesis synthesis_clearbox = 2 */;
input ce;
input clk;
input clr;
output tsdcaldone;
output [7:0] tsdcalo;
wire [7:0] sub_wire0;
wire sub_wire1;
wire [7:0] tsdcalo = sub_wire0[7:0];
wire tsdcaldone = sub_wire1;
temp_sense_alttemp_sense_v8t temp_sense_alttemp_sense_v8t_component (
.ce (ce),
.clk (clk),
.clr (clr),
.tsdcalo (sub_wire0),
.tsdcaldone (sub_wire1))/* synthesis synthesis_clearbox=2
clearbox_macroname = ALTTEMP_SENSE
clearbox_defparam = "clk_frequency=50.0;clock_divider_enable=ON;clock_divider_value=80;intended_device_family=Stratix V;lpm_hint=UNUSED;lpm_type=alttemp_sense;number_of_samples=128;poi_cal_temperature=85;sim_tsdcalo=0;user_offset_enable=off;use_wys=on;" */;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: CLK_FREQUENCY STRING "50.0"
// Retrieval info: CONSTANT: CLOCK_DIVIDER_ENABLE STRING "ON"
// Retrieval info: CONSTANT: CLOCK_DIVIDER_VALUE NUMERIC "80"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alttemp_sense"
// Retrieval info: CONSTANT: NUMBER_OF_SAMPLES NUMERIC "128"
// Retrieval info: CONSTANT: POI_CAL_TEMPERATURE NUMERIC "85"
// Retrieval info: CONSTANT: SIM_TSDCALO NUMERIC "0"
// Retrieval info: CONSTANT: USER_OFFSET_ENABLE STRING "off"
// Retrieval info: CONSTANT: USE_WYS STRING "on"
// Retrieval info: USED_PORT: ce 0 0 0 0 INPUT NODEFVAL "ce"
// Retrieval info: CONNECT: @ce 0 0 0 0 ce 0 0 0 0
// Retrieval info: USED_PORT: clk 0 0 0 0 INPUT NODEFVAL "clk"
// Retrieval info: CONNECT: @clk 0 0 0 0 clk 0 0 0 0
// Retrieval info: USED_PORT: clr 0 0 0 0 INPUT NODEFVAL "clr"
// Retrieval info: CONNECT: @clr 0 0 0 0 clr 0 0 0 0
// Retrieval info: USED_PORT: tsdcaldone 0 0 0 0 OUTPUT NODEFVAL "tsdcaldone"
// Retrieval info: CONNECT: tsdcaldone 0 0 0 0 @tsdcaldone 0 0 0 0
// Retrieval info: USED_PORT: tsdcalo 0 0 8 0 OUTPUT NODEFVAL "tsdcalo[7..0]"
// Retrieval info: CONNECT: tsdcalo 0 0 8 0 @tsdcalo 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.cmp FALSE TRUE
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_add(clock, enable, resetn, dataa, datab, result);
input clock, enable, resetn;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
// Total Latency = 12.
acl_fp_custom_add_core core(
.clock(clock),
.resetn(resetn),
.dataa(dataa),
.datab(datab),
.result(result),
.valid_in(),
.valid_out(),
.stall_in(),
.stall_out(),
.enable(enable));
defparam core.HIGH_LATENCY = 1;
defparam core.HIGH_CAPACITY = 0;
defparam core.FLUSH_DENORMS = 0;
defparam core.ROUNDING_MODE = 0;
defparam core.FINITE_MATH_ONLY = 0;
defparam core.REMOVE_STICKY = 0;
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6
// \ \ Application: MIG
// / / Filename: tg.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:24 $
// \ \ / \ Date Created: Sept 16, 2009
// \___\/\___\
//
//Device: Virtex-6, Spartan-6 and 7series
//Design Name: DDR3 SDRAM
//Purpose:
// This module generates and checks the AXI traffic
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_0_tg #(
parameter C_AXI_ADDR_WIDTH = 32, // This is AXI address width for all
// SI and MI slots
parameter C_AXI_DATA_WIDTH = 32, // Width of the AXI write and read data
parameter C_AXI_NBURST_SUPPORT = 0, // Support for narrow burst transfers
// 1-supported, 0-not supported
parameter C_BEGIN_ADDRESS = 32'h0, // Start address of the address map
parameter C_END_ADDRESS = 32'h0000_00FF, // End address of the address map
parameter C_EN_WRAP_TRANS = 0, // Should be set to 1 for wrap transactions
parameter CTL_SIG_WIDTH = 3, // Control signal width
parameter WR_STS_WIDTH = 16, // Write port status signal width
parameter RD_STS_WIDTH = 16, // Read port status signal width
parameter DBG_WR_STS_WIDTH = 40,
parameter DBG_RD_STS_WIDTH = 40,
parameter ENFORCE_RD_WR = 0,
parameter ENFORCE_RD_WR_CMD = 8'h11,
parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
parameter PRBS_SADDR_MASK_POS = 32'h00002000,
parameter ENFORCE_RD_WR_PATTERN = 3'b000
)
(
input clk, // input clock
input resetn, // Active low reset signal
// Input start signals
input init_cmptd, // Initialization completed
input init_test, // Initialize the test
input wrap_en, // Enable wrap transactions
// Control ports
input cmd_ack, // Command has been accepted
output reg cmd_en, // Command enable
output [2:0] cmd, // Command
output reg [7:0] blen, // Length of the burst
output reg [31:0] addr, // output address
output [CTL_SIG_WIDTH-1:0] ctl, // Control signal
// Write port
input wdata_rdy, // Write data ready to be accepted
output wdata_vld, // Write data valid
output reg wdata_cmptd, // Write data completed
output [C_AXI_DATA_WIDTH-1:0] wdata, // Write data
output [C_AXI_DATA_WIDTH/8-1:0] wdata_bvld, // Byte valids
input wdata_sts_vld, // Status valid
input [WR_STS_WIDTH-1:0] wdata_sts, // Write status
// Read Port
input rdata_vld, // Read data valid
input [C_AXI_DATA_WIDTH-1:0] rdata, // Write data
input [C_AXI_DATA_WIDTH/8-1:0] rdata_bvld, // Byte valids
input rdata_cmptd, // Read data completed
input [RD_STS_WIDTH-1:0] rdata_sts, // Read status
output rdata_rdy, // Read data ready
// Error status signals
output reg cmd_err, // Error during command phase
output reg data_msmatch_err, // Data mismatch
output reg write_err, // Write error occured
output reg read_err, // Read error occured
output test_cmptd, // Completed testing with all patterns
output write_cmptd, // Completed write operation
output read_cmptd, // Completed write operation
// Debug status signals
output cmp_data_en,
output [C_AXI_DATA_WIDTH-1:0] rdata_cmp, // read data
output reg dbg_wr_sts_vld, // Write debug status valid,
output [DBG_WR_STS_WIDTH-1:0] dbg_wr_sts, // Write status
output reg dbg_rd_sts_vld, // Read debug status valid
output [DBG_RD_STS_WIDTH-1:0] dbg_rd_sts // Read status
);
//*****************************************************************************
// Internal parameter declarations
//*****************************************************************************
parameter [8:0] TG_IDLE = 8'd0,
TG_GEN_PRBS = 8'd1,
TG_WR_CMD = 8'd2,
TG_WR_DATA = 8'd3,
TG_WR_DONE = 8'd4,
TG_RD_CMD = 8'd5,
TG_RD_DATA = 8'd6,
TG_UPDT_CNTR = 8'd7;
//*****************************************************************************
// Internal wire and reg declarations
//*****************************************************************************
wire [2:0] data_pattern;
wire dgen_en;
wire dgen_init;
wire [31:0] prbs_seed;
wire msmatch_err;
wire [31:0] prbs_data;
wire [31:0] prbs_blen;
wire [7:0] prbs_blen_mdfy;
wire [31:0] prbs_addr;
wire [31:0] prbs_addr_mdfy;
wire cmd_gen_csr_sig;
wire rdata_sig_vld;
wire wdata_sig_vld;
reg [7:0] rd_mismatch_wrd_cntr_r;
wire [7:0] rd_wrd_cntr;
reg [7:0] wr_wrd_cntr;
reg [7:0] rd_wrd_cntr_r;
reg [7:0] wr_wrd_cntr_r;
wire wrd_cntr_rst;
wire w_burst_4;
wire w_burst_8;
wire w_burst_16;
reg [7:0] tg_state;
reg [7:0] next_tg_state;
reg [2:0] shft_cntr;
reg [2:0] seed_cntr;
reg cmd_vld;
reg [7:0] blen_cntr;
reg wr_proc;
reg curr_wr_ptr;
reg curr_rd_ptr;
reg [31:0] curr_addr1;
reg [31:0] curr_addr2;
reg [7:0] curr_blen1;
reg [7:0] curr_blen2;
reg cmd_wr_en;
reg cmd_wr_en_r;
reg cmd_rd_en;
reg [7:0] cmd_gen_csr;
reg cmd_err_dbg;
reg data_msmatch_err_dbg;
reg write_err_dbg;
reg read_err_dbg;
reg [WR_STS_WIDTH-1:0] wdata_sts_r; // Write status registered
reg [RD_STS_WIDTH-1:0] rdata_sts_r; // Read status registered
//*****************************************************************************
// FSM Control Block
//*****************************************************************************
always @(posedge clk) begin
if (!resetn | init_test)
tg_state <= 8'h1;
else
tg_state <= next_tg_state;
end
always @(*) begin
next_tg_state = 8'h0;
case (1'b1)
tg_state[TG_IDLE]: begin // 8'h01
if (init_cmptd)
next_tg_state[TG_GEN_PRBS] = 1'b1;
else
next_tg_state[TG_IDLE] = 1'b1;
end
tg_state[TG_GEN_PRBS]: begin // 8'h02
if (cmd_vld) begin
if (cmd_gen_csr_sig)
next_tg_state[TG_WR_CMD] = 1'b1;
else
next_tg_state[TG_RD_CMD] = 1'b1;
end else
next_tg_state[TG_GEN_PRBS] = 1'b1;
end
tg_state[TG_WR_CMD]: begin // 8'h04
if (wdata_sts_vld) begin
if (&shft_cntr)
next_tg_state[TG_UPDT_CNTR] = 1'b1;
else
next_tg_state[TG_GEN_PRBS] = 1'b1;
end
else if (wdata_rdy)
next_tg_state[TG_WR_DATA] = 1'b1;
else
next_tg_state[TG_WR_CMD] = 1'b1;
end
tg_state[TG_WR_DATA]: begin // 8'h08
if (wdata_sts_vld) begin
if (&shft_cntr)
next_tg_state[TG_UPDT_CNTR] = 1'b1;
else
next_tg_state[TG_GEN_PRBS] = 1'b1;
end
else if (blen_cntr == 8'h0 & wdata_rdy)
next_tg_state[TG_WR_DONE] = 1'b1;
else
next_tg_state[TG_WR_DATA] = 1'b1;
end
tg_state[TG_WR_DONE]: begin // 8'h10
if (wdata_sts_vld) begin
if (&shft_cntr)
next_tg_state[TG_UPDT_CNTR] = 1'b1;
else
next_tg_state[TG_GEN_PRBS] = 1'b1;
end
else
next_tg_state[TG_WR_DONE] = 1'b1;
end
tg_state[TG_RD_CMD]: begin // 8'h20
if (rdata_cmptd) begin
if (&shft_cntr)
next_tg_state[TG_UPDT_CNTR] = 1'b1;
else
next_tg_state[TG_GEN_PRBS] = 1'b1;
end
else if (cmd_ack)
next_tg_state[TG_RD_DATA] = 1'b1;
else
next_tg_state[TG_RD_CMD] = 1'b1;
end
tg_state[TG_RD_DATA]: begin // 8'h040
if (rdata_cmptd & rdata_vld & rdata_rdy) begin
if (&shft_cntr)
next_tg_state[TG_UPDT_CNTR] = 1'b1;
else
next_tg_state[TG_GEN_PRBS] = 1'b1;
end
else
next_tg_state[TG_RD_DATA] = 1'b1;
end
tg_state[TG_UPDT_CNTR]: begin // 8'h80
if (&seed_cntr)
next_tg_state[TG_IDLE] = 1'b1;
else
next_tg_state[TG_GEN_PRBS] = 1'b1;
end
endcase
end
//*****************************************************************************
// Control Signals
//*****************************************************************************
always @(posedge clk) begin
if (!resetn)
cmd_wr_en <= 1'b0;
else if (next_tg_state[TG_WR_CMD] & tg_state[TG_GEN_PRBS])
cmd_wr_en <= 1'b1;
else
cmd_wr_en <= 1'b0;
end
always @(posedge clk) begin
if (!resetn)
cmd_rd_en <= 1'b0;
else if (next_tg_state[TG_RD_CMD] & tg_state[TG_GEN_PRBS])
cmd_rd_en <= 1'b1;
else
cmd_rd_en <= 1'b0;
end
always @(posedge clk) begin
if (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR])
curr_wr_ptr <= 1'b0;
else if (cmd_wr_en)
curr_wr_ptr <= ~curr_wr_ptr;
end
always @(posedge clk) begin
if (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR])
curr_rd_ptr <= 1'b0;
else if (cmd_rd_en)
curr_rd_ptr <= ~curr_rd_ptr;
end
always @(posedge clk) begin
if (!resetn)
cmd_vld <= 1'b0;
else if (tg_state[TG_WR_CMD] | tg_state[TG_RD_CMD])
cmd_vld <= 1'b0;
else if (tg_state[TG_GEN_PRBS])
cmd_vld <= 1'b1;
end
always @(posedge clk) begin
if (tg_state[TG_IDLE])
wr_proc <= 1'b0;
else if (cmd_wr_en)
wr_proc <= 1'b1;
else if (cmd_rd_en)
wr_proc <= 1'b0;
end
always @(posedge clk) begin
if (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR])
shft_cntr <= 3'b000;
else if (tg_state[TG_GEN_PRBS] & (next_tg_state[TG_WR_CMD] |
next_tg_state[TG_RD_CMD]))
shft_cntr <= shft_cntr + 3'b001;
end
always @(posedge clk)
cmd_wr_en_r <= cmd_wr_en;
assign prbs_seed = {{10{seed_cntr}}, 2'b10};
assign dgen_init = next_tg_state[TG_GEN_PRBS] & !tg_state[TG_GEN_PRBS];
assign agen_init = next_tg_state[TG_GEN_PRBS] & (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR]);
assign cgen_init = next_tg_state[TG_GEN_PRBS] & (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR]);
assign data_pattern = (ENFORCE_RD_WR == 1) ? ENFORCE_RD_WR_PATTERN :
seed_cntr;
assign dgen_en = wr_proc ? (tg_state[TG_WR_DATA] & wdata_rdy) :
(tg_state[TG_RD_DATA] & rdata_vld) ;
assign wrd_cntr_rst = tg_state[TG_GEN_PRBS] | tg_state[TG_IDLE];
//*****************************************************************************
// Data Generation, FIFO, Checker and Data Sizer block
//*****************************************************************************
mig_7series_v4_0_data_gen_chk #
(
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH)
) data_gen_chk_inst
(
.clk (clk),
.data_en (dgen_en),
.data_pattern (data_pattern),
.pattern_init (dgen_init),
.prbs_seed_i (prbs_seed),
.rdata (rdata),
.rdata_bvld (rdata_bvld),
.rdata_vld (rdata_sig_vld),
.msmatch_err (msmatch_err),
.wrd_cntr_rst (wrd_cntr_rst),
.wrd_cntr (rd_wrd_cntr),
.data_o (prbs_data)
);
assign rdata_rdy = tg_state[TG_RD_DATA];
assign rdata_sig_vld = wr_proc ? 1'b0 : (rdata_vld & tg_state[TG_RD_DATA]);
assign wdata_sig_vld = wr_proc ? (wdata_vld & tg_state[TG_WR_DATA]) : 1'b0;
//*****************************************************************************
// Command generation
//*****************************************************************************
always @(posedge clk) begin
if (tg_state[TG_IDLE])
seed_cntr <= 3'b000;
else if (next_tg_state[TG_UPDT_CNTR] &
(tg_state[TG_WR_DATA] | tg_state[TG_WR_DONE] |
tg_state[TG_WR_CMD] | tg_state[TG_RD_CMD] |
tg_state[TG_RD_DATA] ))
seed_cntr <= seed_cntr + 3'b001;
end
always @(posedge clk) begin
if (tg_state[TG_IDLE] | tg_state[TG_UPDT_CNTR]) begin
if (ENFORCE_RD_WR == 1)
cmd_gen_csr <= ENFORCE_RD_WR_CMD;
else
cmd_gen_csr <= {seed_cntr, 1'b1, seed_cntr, 1'b1};
end
else if (next_tg_state[TG_GEN_PRBS] &
(tg_state[TG_WR_CMD] | tg_state[TG_WR_DATA] |
tg_state[TG_RD_DATA] | tg_state[TG_RD_CMD] |
tg_state[TG_WR_DONE]))
cmd_gen_csr <= cmd_gen_csr >> 1;
end
assign cmd_gen_csr_sig = cmd_gen_csr[0];
//*****************************************************************************
// Burst Length generation PRBS
//*****************************************************************************
mig_7series_v4_0_cmd_prbs_gen_axi #
(
.PRBS_CMD ("BLEN"),
.PRBS_WIDTH (32), // 64,15,20
.SEED_WIDTH (32), // 32,15,4
.ADDR_WIDTH (C_AXI_ADDR_WIDTH)
) blen_gen_inst
(
.clk_i (clk),
.prbs_seed_init (cgen_init),
.clk_en (cmd_wr_en_r),
.prbs_seed_i (prbs_seed),
.prbs_o (prbs_blen)
);
assign w_burst_4 = (|prbs_blen[7:2]);
assign w_burst_8 = (|prbs_blen[7:3]);
assign w_burst_16 = (|prbs_blen[7:4]);
assign prbs_blen_mdfy = (C_EN_WRAP_TRANS == 1 && wrap_en) ? {4'h0, w_burst_16, w_burst_8,
w_burst_4, 1'b1} : prbs_blen[7:0];
always @(posedge clk) begin
if (tg_state[TG_IDLE]) begin
curr_blen1 <= 8'h0;
curr_blen2 <= 8'h0;
end
else if (cmd_wr_en) begin
if (curr_wr_ptr)
curr_blen2 <= prbs_blen_mdfy;
else
curr_blen1 <= prbs_blen_mdfy;
end
end
always @(posedge clk) begin
if (tg_state[TG_IDLE] | (next_tg_state[TG_GEN_PRBS] & !tg_state[TG_GEN_PRBS]))
blen_cntr <= 8'h00;
else if (tg_state[TG_GEN_PRBS] & next_tg_state[TG_GEN_PRBS])
blen_cntr <= prbs_blen_mdfy;
else if (tg_state[TG_WR_DATA] & wdata_rdy & (blen_cntr != 8'h00))
blen_cntr <= blen_cntr - 8'h01;
end
//*****************************************************************************
// Address generation PRBS
//*****************************************************************************
mig_7series_v4_0_cmd_prbs_gen_axi #
(
.FAMILY ("VIRTEX7"),
.ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.PRBS_CMD ("ADDRESS"), // "INSTR", "BLEN","ADDRESS"
.PRBS_WIDTH (32), // 64,15,20
.SEED_WIDTH (32), // 32,15,4
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.PRBS_SADDR_MASK_POS (PRBS_SADDR_MASK_POS),
.PRBS_EADDR (C_END_ADDRESS),
.PRBS_SADDR (C_BEGIN_ADDRESS)
) addr_gen_inst
(
.clk_i (clk),
.prbs_seed_init (agen_init),
.clk_en (cmd_wr_en_r),
.prbs_seed_i (prbs_seed),
.prbs_o (prbs_addr)
);
generate
begin: addr_axi_wr
if (C_AXI_DATA_WIDTH == 256)
assign prbs_addr_mdfy = prbs_addr[31:0] & 32'hffff_ffe0;
else if (C_AXI_DATA_WIDTH == 128)
assign prbs_addr_mdfy = prbs_addr[31:0] & 32'hffff_fff0;
else if (C_AXI_DATA_WIDTH == 64)
assign prbs_addr_mdfy = prbs_addr[31:0] & 32'hffff_fff8;
else
assign prbs_addr_mdfy = prbs_addr[31:0] & 32'hffff_fffc;
end
endgenerate
always @(posedge clk) begin
if (tg_state[TG_IDLE]) begin
curr_addr1 <= 32'h0;
curr_addr2 <= 32'h0;
end
else if (cmd_wr_en) begin
if (curr_wr_ptr)
curr_addr2 <= prbs_addr_mdfy;
else
curr_addr1 <= prbs_addr_mdfy;
end
end
//*****************************************************************************
// Control Output Signals
//*****************************************************************************
always @(posedge clk) begin
if (!resetn)
cmd_en <= 1'b0;
else if (tg_state[TG_WR_CMD] | tg_state[TG_RD_CMD])
cmd_en <= 1'b1;
else if (tg_state[TG_WR_DATA] | tg_state[TG_RD_DATA])
cmd_en <= 1'b0;
end
assign cmd = {cmd_gen_csr_sig, 1'b0, wrap_en};
always @(posedge clk) begin
if (tg_state[TG_IDLE]) begin
blen <= 8'h0;
addr <= 32'h0;
end
else if (cmd_gen_csr_sig & tg_state[TG_GEN_PRBS]) begin
blen <= prbs_blen_mdfy;
addr <= prbs_addr_mdfy;
end
else if (tg_state[TG_GEN_PRBS]) begin
case ({curr_wr_ptr, curr_rd_ptr})
2'b01: begin
blen <= curr_blen2;
addr <= curr_addr2;
end
default : begin
blen <= curr_blen1;
addr <= curr_addr1;
end
endcase
end
end
generate
begin: cntrl_sig
if (C_AXI_NBURST_SUPPORT == 1) begin
end
else begin
if (C_AXI_DATA_WIDTH == 1024)
assign ctl[2:0] = 3'b111;
else if (C_AXI_DATA_WIDTH == 512)
assign ctl[2:0] = 3'b110;
else if (C_AXI_DATA_WIDTH == 256)
assign ctl[2:0] = 3'b101;
else if (C_AXI_DATA_WIDTH == 128)
assign ctl[2:0] = 3'b100;
else if (C_AXI_DATA_WIDTH == 64)
assign ctl[2:0] = 3'b011;
else
assign ctl[2:0] = 3'b010;
end
end
endgenerate
//*****************************************************************************
// Write Output Signals
//*****************************************************************************
always @(posedge clk) begin
if (!resetn)
wdata_cmptd <= 1'b0;
else if (tg_state[TG_WR_DONE])
wdata_cmptd <= 1'b0;
else if ((tg_state[TG_WR_DATA] & wdata_rdy & blen_cntr == 8'h01) |
(next_tg_state[TG_WR_DATA] & tg_state[TG_WR_CMD] & blen_cntr == 8'h00))
wdata_cmptd <= 1'b1;
end
assign wdata_vld = tg_state[TG_WR_DATA];
assign wdata = {{C_AXI_DATA_WIDTH/32}{prbs_data}};
generate
begin: data_sig
if (C_AXI_NBURST_SUPPORT == 1) begin
end
else begin
assign wdata_bvld = {{C_AXI_DATA_WIDTH/32}{4'hF}};
end
end
endgenerate
//*****************************************************************************
// Status and Debug Signals
//*****************************************************************************
always @(posedge clk) begin
if (!resetn) begin
cmd_err_dbg <= 1'b0;
data_msmatch_err_dbg <= 1'b0;
write_err_dbg <= 1'b0;
read_err_dbg <= 1'b0;
end
else if (tg_state[TG_IDLE] & next_tg_state[TG_GEN_PRBS]) begin
cmd_err_dbg <= 1'b0;
data_msmatch_err_dbg <= 1'b0;
write_err_dbg <= 1'b0;
read_err_dbg <= 1'b0;
end
else begin
if ((next_tg_state[TG_GEN_PRBS] | next_tg_state[TG_UPDT_CNTR]) &
(tg_state[TG_RD_CMD] | tg_state[TG_WR_CMD]))
cmd_err_dbg <= 1'b0;
if (msmatch_err & tg_state[TG_RD_DATA])
data_msmatch_err_dbg <= 1'b1;
if ((next_tg_state[TG_GEN_PRBS] | next_tg_state[TG_UPDT_CNTR]) &
tg_state[TG_WR_DATA])
write_err_dbg <= 1'b1;
if (rdata_cmptd & rdata_vld & rdata_rdy)
read_err_dbg <= (rdata_sts[3:2] == 2'b01);
end
end
always @(posedge clk) begin
if (!resetn) begin
cmd_err <= 1'b0;
data_msmatch_err <= 1'b0;
write_err <= 1'b0;
read_err <= 1'b0;
end
else begin
if (cmd_err_dbg)
cmd_err <= 1'b1;
if (data_msmatch_err_dbg)
data_msmatch_err <= 1'b1;
if (write_err_dbg)
write_err <= 1'b1;
if (read_err_dbg)
read_err <= 1'b1;
end
end
always @(posedge clk) begin
if (!resetn) begin
dbg_wr_sts_vld <= 1'b0;
dbg_rd_sts_vld <= 1'b0;
end
else if (tg_state[TG_GEN_PRBS]) begin
dbg_wr_sts_vld <= 1'b0;
dbg_rd_sts_vld <= 1'b0;
end
else begin
if (wdata_sts_vld)
dbg_wr_sts_vld <= 1'b1;
if (rdata_cmptd & rdata_vld & rdata_rdy)
dbg_rd_sts_vld <= 1'b1;
end
end
always @(posedge clk) begin
if (tg_state[TG_GEN_PRBS] | tg_state[TG_IDLE]) begin
wdata_sts_r <= {WR_STS_WIDTH{1'b0}};
rdata_sts_r <= {RD_STS_WIDTH{1'b0}};
end
else begin
if (wdata_sts_vld)
wdata_sts_r <= wdata_sts;
if (rdata_cmptd & rdata_vld & rdata_rdy)
rdata_sts_r <= rdata_sts;
end
end
//*****************************************************************************
// Data count generation incremented for each burst to indicate activity
//*****************************************************************************
// Write count within a burst
always @(posedge clk)
if (wrd_cntr_rst)
wr_wrd_cntr <= 8'h00;
else if (wdata_sig_vld)
wr_wrd_cntr <= wr_wrd_cntr + 8'h01;
// Read count within a burst is implemented inside the data_gen_chk module
// Storing last burst count for read and write
always @(posedge clk)
if (!resetn)
wr_wrd_cntr_r <= 8'h00;
else if (dbg_wr_sts_vld)
wr_wrd_cntr_r <= wr_wrd_cntr;
always @(posedge clk)
if (!resetn)
rd_wrd_cntr_r <= 8'h00;
else if (dbg_rd_sts_vld)
rd_wrd_cntr_r <= rd_wrd_cntr;
// Computing the word count at which first data mismatch occured
always @(posedge clk)
if (wrd_cntr_rst)
rd_mismatch_wrd_cntr_r <= 8'h00;
else if (~data_msmatch_err_dbg)
rd_mismatch_wrd_cntr_r <= rd_wrd_cntr - 1;
assign dbg_wr_sts = {rd_wrd_cntr_r, 11'h0, data_pattern, write_err_dbg, cmd_err_dbg, wdata_sts_r};
assign dbg_rd_sts = {wr_wrd_cntr_r, 2'b00, data_pattern, rd_mismatch_wrd_cntr_r, data_msmatch_err_dbg, read_err_dbg, cmd_err_dbg, rdata_sts_r};
assign test_cmptd = tg_state[TG_UPDT_CNTR] & next_tg_state[TG_IDLE];
assign write_cmptd = (tg_state[TG_WR_DATA] | tg_state[TG_WR_DONE]) &
(next_tg_state[TG_GEN_PRBS] | next_tg_state[TG_UPDT_CNTR]);
assign read_cmptd = tg_state[TG_RD_DATA] & (next_tg_state[TG_GEN_PRBS] | next_tg_state[TG_UPDT_CNTR]);
assign cmp_data_en = dgen_en & tg_state[TG_RD_DATA];
assign rdata_cmp = rdata;
// synthesis translate_off
//*****************************************************************************
// Simulation debug signals and messages
//*****************************************************************************
always @(*) begin
if (test_cmptd) begin
$display ("[INFO] : All tests have been completed");
if (cmd_err)
$display ("[ERROR] Command error has occured");
if (data_msmatch_err)
$display ("[ERROR] Data mismatch error occured");
if (write_err)
$display ("[ERROR] Timeout occured during write transaction");
if (read_err)
$display ("[ERROR] Timeout occured during read transaction");
if (!cmd_err & !data_msmatch_err & !write_err & !read_err)
$display ("[INFO] : Tests PASSED");
$finish;
end
end
// synthesis translate_on
endmodule
|
//------------------------------------------------------------------------------
// This confidential and proprietary software may be used only as authorized by
// a licensing agreement from Altera Corporation.
//
// Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// The entire notice above must be reproduced on all authorized copies and any
// such reproduction must be pursuant to a licensing agreement from Altera.
//
// Title : Example top level testbench for ddr3_int DDR/2/3 SDRAM High Performance Controller
// Project : DDR/2/3 SDRAM High Performance Controller
//
// File : ddr3_int_example_top_tb.v
//
// Revision : V10.0
//
// Abstract:
// Automatically generated testbench for the example top level design to allow
// functional and timing simulation.
//
//------------------------------------------------------------------------------
//
// *************** This is a MegaWizard generated file ****************
//
// If you need to edit this file make sure the edits are not inside any 'MEGAWIZARD'
// text insertion areas.
// (between "<< START MEGAWIZARD INSERT" and "<< END MEGAWIZARD INSERT" comments)
//
// Any edits inside these delimiters will be overwritten by the megawizard if you
// re-run it.
//
// If you really need to make changes inside these delimiters then delete
// both 'START' and 'END' delimiters. This will stop the megawizard updating this
// section again.
//
//----------------------------------------------------------------------------------
// << START MEGAWIZARD INSERT PARAMETER_LIST
// Parameters:
//
// Device Family : arria ii gx
// local Interface Data Width : 128
// MEM_CHIPSELS : 1
// MEM_CS_PER_RANK : 1
// MEM_BANK_BITS : 3
// MEM_ROW_BITS : 14
// MEM_COL_BITS : 10
// LOCAL_DATA_BITS : 128
// NUM_CLOCK_PAIRS : 1
// CLOCK_TICK_IN_PS : 3333
// REGISTERED_DIMM : false
// TINIT_CLOCKS : 75008
// Data_Width_Ratio : 4
// << END MEGAWIZARD INSERT PARAMETER_LIST
//----------------------------------------------------------------------------------
// << MEGAWIZARD PARSE FILE DDR10.0
`timescale 1 ps/1 ps
// << START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top_tb ();
// << END MEGAWIZARD INSERT MODULE
// << START MEGAWIZARD INSERT PARAMS
parameter gMEM_CHIPSELS = 1;
parameter gMEM_CS_PER_RANK = 1;
parameter gMEM_NUM_RANKS = 1 / 1;
parameter gMEM_BANK_BITS = 3;
parameter gMEM_ROW_BITS = 14;
parameter gMEM_COL_BITS = 10;
parameter gMEM_ADDR_BITS = 14;
parameter gMEM_DQ_PER_DQS = 8;
parameter DM_DQS_WIDTH = 4;
parameter gLOCAL_DATA_BITS = 128;
parameter gLOCAL_IF_DWIDTH_AFTER_ECC = 128;
parameter gNUM_CLOCK_PAIRS = 1;
parameter RTL_ROUNDTRIP_CLOCKS = 0.0;
parameter CLOCK_TICK_IN_PS = 3333;
parameter REGISTERED_DIMM = 1'b0;
parameter BOARD_DQS_DELAY = 0;
parameter BOARD_CLK_DELAY = 0;
parameter DWIDTH_RATIO = 4;
parameter TINIT_CLOCKS = 75008;
parameter REF_CLOCK_TICK_IN_PS = 40000;
// Parameters below are for generic memory model
parameter gMEM_TQHS_PS = 300;
parameter gMEM_TAC_PS = 400;
parameter gMEM_TDQSQ_PS = 200;
parameter gMEM_IF_TRCD_NS = 15.0;
parameter gMEM_IF_TWTR_CK = 4;
parameter gMEM_TDSS_CK = 0.2;
parameter gMEM_IF_TRFC_NS = 110.0;
parameter gMEM_IF_TRP_NS = 15.0;
parameter gMEM_IF_TRCD_PS = gMEM_IF_TRCD_NS * 1000.0;
parameter gMEM_IF_TWTR_PS = gMEM_IF_TWTR_CK * CLOCK_TICK_IN_PS;
parameter gMEM_IF_TRFC_PS = gMEM_IF_TRFC_NS * 1000.0;
parameter gMEM_IF_TRP_PS = gMEM_IF_TRP_NS * 1000.0;
parameter CLOCK_TICK_IN_NS = CLOCK_TICK_IN_PS / 1000.0;
parameter gMEM_TDQSQ_NS = gMEM_TDQSQ_PS / 1000.0;
parameter gMEM_TDSS_NS = gMEM_TDSS_CK * CLOCK_TICK_IN_NS;
// << END MEGAWIZARD INSERT PARAMS
// set to zero for Gatelevel
parameter RTL_DELAYS = 1;
parameter USE_GENERIC_MEMORY_MODEL = 1'b0;
// The round trip delay is now modeled inside the datapath (<your core name>_auk_ddr_dqs_group.v/vhd) for RTL simulation.
parameter D90_DEG_DELAY = 0; //RTL only
parameter GATE_BOARD_DQS_DELAY = BOARD_DQS_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
parameter GATE_BOARD_CLK_DELAY = BOARD_CLK_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
parameter gMEM_CLK_PHASE_EN = "false";
parameter real gMEM_CLK_PHASE = 0;
parameter real MEM_CLK_RATIO = ((360.0-gMEM_CLK_PHASE)/360.0);
parameter MEM_CLK_DELAY = MEM_CLK_RATIO*CLOCK_TICK_IN_PS * ((gMEM_CLK_PHASE_EN=="true") ? 1 : 0);
wire clk_to_ram0, clk_to_ram1, clk_to_ram2;
wire cmd_bus_watcher_enabled;
reg clk;
reg clk_n;
reg reset_n;
wire mem_reset_n;
wire[gMEM_ADDR_BITS - 1:0] a;
wire[gMEM_BANK_BITS - 1:0] ba;
wire[gMEM_CHIPSELS - 1:0] cs_n;
wire[gMEM_NUM_RANKS - 1:0] cke;
wire[gMEM_NUM_RANKS - 1:0] odt; //DDR2 only
wire ras_n;
wire cas_n;
wire we_n;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs_n;
//wire stratix_dqs_ref_clk; // only used on stratix to provide external dll reference clock
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram;
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram_n;
wire #(GATE_BOARD_CLK_DELAY * 1) clk_to_ram;
wire clk_to_ram_n;
wire[gMEM_ROW_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) a_delayed;
wire[gMEM_BANK_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) ba_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cke_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) odt_delayed; //DDR2 only
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cs_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) ras_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) cas_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) we_n_delayed;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm_delayed;
// DDR3 parity only
wire ac_parity;
wire mem_err_out_n;
assign mem_err_out_n = 1'b1;
// pulldown (dm);
assign (weak1, weak0) dm = 0;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO - 1:0] mem_dq = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs_n = 100'bz;
assign (weak1, weak0) mem_dq = 0;
assign (weak1, weak0) mem_dqs = 0;
assign (weak1, weak0) mem_dqs_n = 1;
wire [gMEM_BANK_BITS - 1:0] zero_one; //"01";
assign zero_one = 1;
wire test_complete;
wire [7:0] test_status;
// counter to count the number of sucessful read and write loops
integer test_complete_count;
wire pnf;
wire [gLOCAL_IF_DWIDTH_AFTER_ECC / 8 - 1:0] pnf_per_byte;
assign cmd_bus_watcher_enabled = 1'b0;
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
assign #(MEM_CLK_DELAY/4.0) clk_to_ram2 = clk_to_sdram[0];
assign #(MEM_CLK_DELAY/4.0) clk_to_ram1 = clk_to_ram2;
assign #(MEM_CLK_DELAY/4.0) clk_to_ram0 = clk_to_ram1;
assign #((MEM_CLK_DELAY/4.0)) clk_to_ram = clk_to_ram0;
assign clk_to_ram_n = ~clk_to_ram ; // mem model ignores clk_n ?
// ddr sdram interface
// << START MEGAWIZARD INSERT ENTITY
ddr3_int_example_top dut (
// << END MEGAWIZARD INSERT ENTITY
.clock_source(clk),
.global_reset_n(reset_n),
// << START MEGAWIZARD INSERT PORT_MAP
.mem_clk(clk_to_sdram),
.mem_clk_n(clk_to_sdram_n),
.mem_odt(odt),
.mem_dqsn(mem_dqs_n),
.mem_reset_n(mem_reset_n),
.mem_cke(cke),
.mem_cs_n(cs_n),
.mem_ras_n(ras_n),
.mem_cas_n(cas_n),
.mem_we_n(we_n),
.mem_ba(ba),
.mem_addr(a),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dm(dm),
// << END MEGAWIZARD INSERT PORT_MAP
.test_complete(test_complete),
.test_status(test_status),
.pnf_per_byte(pnf_per_byte),
.pnf(pnf)
);
// << START MEGAWIZARD INSERT MEMORY_ARRAY
// This will need updating to match the memory models you are using.
// Instantiate a generated DDR memory model to match the datawidth & chipselect requirements
ddr3_int_mem_model mem (
.mem_rst_n (mem_reset_n),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.mem_addr (a_delayed),
.mem_ba (ba_delayed),
.mem_clk (clk_to_ram),
.mem_clk_n (clk_to_ram_n),
.mem_cke (cke_delayed),
.mem_cs_n (cs_n_delayed),
.mem_ras_n (ras_n_delayed),
.mem_cas_n (cas_n_delayed),
.mem_we_n (we_n_delayed),
.mem_dm (dm_delayed),
.mem_odt (odt_delayed)
);
// << END MEGAWIZARD INSERT MEMORY_ARRAY
always
begin
clk <= 1'b0 ;
clk_n <= 1'b1 ;
while (1'b1)
begin
#((REF_CLOCK_TICK_IN_PS / 2) * 1);
clk <= ~clk ;
clk_n <= ~clk_n ;
end
end
initial
begin
reset_n <= 1'b0 ;
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
reset_n <= 1'b1 ;
end
// control and data lines = 3 inches
assign a_delayed = a[gMEM_ROW_BITS - 1:0] ;
assign ba_delayed = ba ;
assign cke_delayed = cke ;
assign odt_delayed = odt ;
assign cs_n_delayed = cs_n ;
assign ras_n_delayed = ras_n ;
assign cas_n_delayed = cas_n ;
assign we_n_delayed = we_n ;
assign dm_delayed = dm ;
// ---------------------------------------------------------------
initial
begin : endit
integer count;
reg ln;
count = 0;
// Stop simulation after test_complete or TINIT + 600000 clocks
while ((count < (TINIT_CLOCKS + 600000)) & (test_complete !== 1))
begin
count = count + 1;
@(negedge clk_to_sdram[0]);
end
if (test_complete === 1)
begin
if (pnf)
begin
$write($time);
$write(" --- SIMULATION PASSED --- ");
$stop;
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED --- ");
$stop;
end
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED, DID NOT COMPLETE --- ");
$stop;
end
end
always @(clk_to_sdram[0] or reset_n)
begin
if (!reset_n)
begin
test_complete_count <= 0 ;
end
else if ((clk_to_sdram[0]))
begin
if (test_complete)
begin
test_complete_count <= test_complete_count + 1 ;
end
end
end
reg[2:0] cmd_bus;
//***********************************************************
// Watch the SDRAM command bus
always @(clk_to_ram)
begin
if (clk_to_ram)
begin
if (1'b1)
begin
cmd_bus = {ras_n_delayed, cas_n_delayed, we_n_delayed};
case (cmd_bus)
3'b000 :
begin
// LMR command
$write($time);
if (ba_delayed == zero_one)
begin
$write(" ELMR settings = ");
if (!(a_delayed[0]))
begin
$write("DLL enable");
end
end
else
begin
$write(" LMR settings = ");
case (a_delayed[1:0])
3'b00 : $write("BL = 8,");
3'b01 : $write("BL = On The Fly,");
3'b10 : $write("BL = 4,");
default : $write("BL = ??,");
endcase
case (a_delayed[6:4])
3'b001 : $write(" CL = 5.0,");
3'b010 : $write(" CL = 6.0,");
3'b011 : $write(" CL = 7.0,");
3'b100 : $write(" CL = 8.0,");
3'b101 : $write(" CL = 9.0,");
3'b110 : $write(" CL = 10.0,");
default : $write(" CL = ??,");
endcase
if ((a_delayed[8])) $write(" DLL reset");
end
$write("\n");
end
3'b001 :
begin
// ARF command
$write($time);
$write(" ARF\n");
end
3'b010 :
begin
// PCH command
$write($time);
$write(" PCH");
if ((a_delayed[10]))
begin
$write(" all banks \n");
end
else
begin
$write(" bank ");
$write("%H\n", ba_delayed);
end
end
3'b011 :
begin
// ACT command
$write($time);
$write(" ACT row address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b100 :
begin
// WR command
$write($time);
$write(" WR to col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b101 :
begin
// RD command
$write($time);
$write(" RD from col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b110 :
begin
// BT command
$write($time);
$write(" BT ");
end
3'b111 :
begin
// NOP command
end
endcase
end
else
begin
end // if enabled
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: rd_data_gen.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module has all the timing control for generating "compare data"
// to compare the read data from memory.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_rd_data_gen #
(
parameter TCQ = 100,
parameter FAMILY = "VIRTEX7", // "SPARTAN6", "VIRTEX6"
parameter MEM_TYPE = "DDR3",
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
parameter MEM_BURST_LEN = 8,
parameter START_ADDR = 32'h00000000,
parameter ADDR_WIDTH = 32,
parameter BL_WIDTH = 6,
parameter DWIDTH = 32,
parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 8,
parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
parameter COLUMN_WIDTH = 10
)
(
input clk_i, //
input [4:0] rst_i,
input [31:0] prbs_fseed_i,
input [3:0] data_mode_i, // "00" = bram;
input mode_load_i,
input [3:0] vio_instr_mode_value,
output cmd_rdy_o, // ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.
// And then it should reasserted when
// it is generating the last_word.
input cmd_valid_i, // when both cmd_valid_i and cmd_rdy_o is high, the command is valid.
output reg cmd_start_o,
// input [ADDR_WIDTH-1:0] m_addr_i, // generated address used to determine data pattern.
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
input [31:0] fixed_data_i,
input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern.
input [BL_WIDTH-1:0] bl_i, // generated burst length for control the burst data
output user_bl_cnt_is_1_o,
input data_rdy_i, // connect from mcb_wr_full when used as wr_data_gen in sp6
// connect from mcb_rd_empty when used as rd_data_gen in sp6
// connect from rd_data_valid in v6
// When both data_rdy and data_valid is asserted, the ouput data is valid.
output reg data_valid_o, // connect to wr_en or rd_en and is asserted whenever the
// pattern is available.
// output [DWIDTH-1:0] data_o // generated data pattern NUM_DQ_PINS*nCK_PER_CLK*2-1
output [31:0] tg_st_addr_o,
output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o // generated data pattern NUM_DQ_PINS*nCK_PER_CLK*2-1
);
//
wire [31:0] prbs_data;
reg cmd_start;
reg [31:0] adata;
reg [31:0] hdata;
reg [31:0] ndata;
reg [31:0] w1data;
reg [NUM_DQ_PINS*4-1:0] v6_w1data;
reg [31:0] w0data;
reg [DWIDTH-1:0] data;
reg cmd_rdy;
reg [BL_WIDTH:0]user_burst_cnt;
reg [31:0] w3data;
reg prefetch;
assign data_port_fifo_rdy = data_rdy_i;
reg user_bl_cnt_is_1;
assign user_bl_cnt_is_1_o = user_bl_cnt_is_1;
always @ (posedge clk_i)
begin
if (data_port_fifo_rdy)
if ((user_burst_cnt == 2 && FAMILY == "SPARTAN6")
|| (user_burst_cnt == 2 && FAMILY == "VIRTEX6")
)
user_bl_cnt_is_1 <= #TCQ 1'b1;
else
user_bl_cnt_is_1 <= #TCQ 1'b0;
end
//reg cmd_start_b;
always @(cmd_valid_i,data_port_fifo_rdy,cmd_rdy,user_bl_cnt_is_1,prefetch)
begin
cmd_start = cmd_valid_i & cmd_rdy & ( data_port_fifo_rdy | prefetch) ;
cmd_start_o = cmd_valid_i & cmd_rdy & ( data_port_fifo_rdy | prefetch) ;
end
// counter to count user burst length
// verilint STARC-2.2.3.3 off
always @( posedge clk_i)
begin
if ( rst_i[0] )
user_burst_cnt <= #TCQ 'd0;
else if(cmd_valid_i && cmd_rdy && ( data_port_fifo_rdy | prefetch) ) begin
// SPATAN6 has maximum of burst length of 64.
if (FAMILY == "SPARTAN6" && bl_i[5:0] == 6'b000000)
begin
user_burst_cnt[6:0] <= #TCQ 7'd64;
user_burst_cnt[BL_WIDTH:7] <= 'b0;
end
else if (FAMILY == "VIRTEX6" && bl_i[BL_WIDTH - 1:0] == {BL_WIDTH {1'b0}})
user_burst_cnt <= #TCQ {1'b1, {BL_WIDTH{1'b0}}};
else
user_burst_cnt <= #TCQ {1'b0,bl_i };
end
else if(data_port_fifo_rdy)
if (user_burst_cnt != 6'd0)
user_burst_cnt <= #TCQ user_burst_cnt - 1'b1;
else
user_burst_cnt <= #TCQ 'd0;
end
// verilint STARC-2.2.3.3 on
// cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
// is assert and reassert during the last data
//data_valid_o logic
always @( posedge clk_i)
begin
if ( rst_i[0] )
prefetch <= #TCQ 1'b1;
else if (data_port_fifo_rdy || cmd_start)
prefetch <= #TCQ 1'b0;
else if (user_burst_cnt == 0 && ~data_port_fifo_rdy)
prefetch <= #TCQ 1'b1;
end
assign cmd_rdy_o = cmd_rdy ;
always @( posedge clk_i)
begin
if ( rst_i[0] )
cmd_rdy <= #TCQ 1'b1;
else if (cmd_valid_i && cmd_rdy && (data_port_fifo_rdy || prefetch ))
cmd_rdy <= #TCQ 1'b0;
else if ((data_port_fifo_rdy && user_burst_cnt == 2 && vio_instr_mode_value != 7 ) ||
(data_port_fifo_rdy && user_burst_cnt == 1 && vio_instr_mode_value == 7 ))
cmd_rdy <= #TCQ 1'b1;
end
always @ (data_port_fifo_rdy)
if (FAMILY == "SPARTAN6")
data_valid_o = data_port_fifo_rdy;
else
data_valid_o = data_port_fifo_rdy;
/*
generate
if (FAMILY == "SPARTAN6")
begin : SP6_DGEN
s7ven_data_gen #
(
.TCQ (TCQ),
.DMODE ("READ"),
.nCK_PER_CLK (nCK_PER_CLK),
.FAMILY (FAMILY),
.ADDR_WIDTH (32 ),
.BL_WIDTH (BL_WIDTH ),
.MEM_BURST_LEN (MEM_BURST_LEN),
.DWIDTH (DWIDTH ),
.DATA_PATTERN (DATA_PATTERN ),
.NUM_DQ_PINS (NUM_DQ_PINS ),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.START_ADDR (START_ADDR),
.COLUMN_WIDTH (COLUMN_WIDTH)
)
s7ven_data_gen
(
.clk_i (clk_i ),
.rst_i (rst_i[1] ),
.data_rdy_i (data_rdy_i ),
.mem_init_done_i (1'b1),
.wr_data_mask_gen_i (1'b0),
.prbs_fseed_i (prbs_fseed_i),
.mode_load_i (mode_load_i),
.data_mode_i (data_mode_i ),
.cmd_startA (cmd_start ),
.cmd_startB (cmd_start ),
.cmd_startC (cmd_start ),
.cmd_startD (cmd_start ),
.cmd_startE (cmd_start ),
.m_addr_i (addr_i),//(m_addr_i ),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.fixed_data_i (fixed_data_i),
.addr_i (addr_i ),
.user_burst_cnt (user_burst_cnt),
.fifo_rdy_i (data_port_fifo_rdy ),
.data_o (data_o ),
.data_mask_o (),
.bram_rd_valid_o ()
);
end
endgenerate*/
//generate
//if (FAMILY == "VIRTEX6")
//begin : V_DGEN
mig_7series_v2_3_s7ven_data_gen #
(
.TCQ (TCQ),
.DMODE ("READ"),
.nCK_PER_CLK (nCK_PER_CLK),
.FAMILY (FAMILY),
.MEM_TYPE (MEM_TYPE),
.ADDR_WIDTH (32 ),
.BL_WIDTH (BL_WIDTH ),
.MEM_BURST_LEN (MEM_BURST_LEN),
.DWIDTH (DWIDTH ),
.DATA_PATTERN (DATA_PATTERN ),
.NUM_DQ_PINS (NUM_DQ_PINS ),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.START_ADDR (START_ADDR),
.COLUMN_WIDTH (COLUMN_WIDTH)
)
s7ven_data_gen
(
.clk_i (clk_i ),
.rst_i (rst_i[1] ),
.data_rdy_i (data_rdy_i ),
.mem_init_done_i (1'b1),
.wr_data_mask_gen_i (1'b0),
.prbs_fseed_i (prbs_fseed_i),
.mode_load_i (mode_load_i),
.data_mode_i (data_mode_i ),
.cmd_startA (cmd_start ),
.cmd_startB (cmd_start ),
.cmd_startC (cmd_start ),
.cmd_startD (cmd_start ),
.cmd_startE (cmd_start ),
.m_addr_i (addr_i),//(m_addr_i ),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.fixed_data_i (fixed_data_i),
.addr_i (addr_i ),
.user_burst_cnt (user_burst_cnt),
.fifo_rdy_i (data_port_fifo_rdy ),
.data_o (data_o ),
.tg_st_addr_o (tg_st_addr_o),
.data_mask_o (),
.bram_rd_valid_o ()
);
//end
//endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O311A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O311A_BEHAVIORAL_PP_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o311a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O311A_BEHAVIORAL_PP_V |
// $Id: vcr_sw_alloc_ip.v 1854 2010-03-24 03:12:03Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// input-side switch allocator logic
module vcr_sw_alloc_ip
(clk, reset, route_ivc_op, req_in_ivc, req_out_op, gnt_in_op, gnt_out_op,
gnt_out_ivc, sel_ivc, allow_update);
`include "c_constants.v"
`include "vcr_constants.v"
// number of VCs
parameter num_vcs = 2;
// number of input and output ports on router
parameter num_ports = 5;
// select implementation variant for switch allocator
parameter allocator_type = `SW_ALLOC_TYPE_SEP_IF;
// select which arbiter type to use in allocator
parameter arbiter_type = `ARBITER_TYPE_ROUND_ROBIN;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// destination port selects
input [0:num_vcs*num_ports-1] route_ivc_op;
// requests from VC controllers
input [0:num_vcs-1] req_in_ivc;
// requests to output-side arbitration stage / wavefront block
output [0:num_ports-1] req_out_op;
wire [0:num_ports-1] req_out_op;
// grants from output-side arbitration stage / wavefront block
input [0:num_ports-1] gnt_in_op;
// grants to output-side arbitration stage / crossbar
output [0:num_ports-1] gnt_out_op;
wire [0:num_ports-1] gnt_out_op;
// grants to VC controllers
output [0:num_vcs-1] gnt_out_ivc;
wire [0:num_vcs-1] gnt_out_ivc;
// VC selector for flit buffer read address generation
output [0:num_vcs-1] sel_ivc;
wire [0:num_vcs-1] sel_ivc;
// allow arbiter state updates
input allow_update;
generate
if(allocator_type == `SW_ALLOC_TYPE_SEP_IF)
begin
//-------------------------------------------------------------------
// For the input-first separable allocator, we just pick a single
// requesting VC and forward its request to the appropriate output
// port.
//-------------------------------------------------------------------
// was any output port granted to this input port?
wire gnt_in;
assign gnt_in = |gnt_in_op;
// only update priorities if we were successful in both the input
// and output stage; since output stage requests are generated
// from input stage grants, it is sufficient to check for output
// stage grants here
wire update_arb;
assign update_arb = gnt_in & allow_update;
wire [0:num_vcs-1] req_ivc;
assign req_ivc = req_in_ivc;
// select one VC among all that have pending requests
wire [0:num_vcs-1] gnt_ivc;
c_arbiter
#(.num_ports(num_vcs),
.reset_type(reset_type),
.arbiter_type(arbiter_type))
gnt_ivc_arb
(.clk(clk),
.reset(reset),
.update(update_arb),
.req(req_ivc),
.gnt(gnt_ivc));
// propagate winning VC's request to the appropriate output
c_select_1ofn
#(.width(num_ports),
.num_ports(num_vcs))
req_out_op_sel
(.select(gnt_ivc),
.data_in(route_ivc_op),
.data_out(req_out_op));
// the selected VC's request was successful if the output it had
// requested was granted to this input port; since we only
// requested one output to begin with, it is sufficient here to
// check if any output was granted
assign gnt_out_ivc = {num_vcs{gnt_in}} & gnt_ivc;
// one whose requests for forwarded; thus, we can generate the flit
// buffer read address early
assign sel_ivc = gnt_ivc;
// the output-side port grants, so just pass these through (this
// signal will be ignored at the router level anyway)
assign gnt_out_op = gnt_in_op;
end
else if((allocator_type == `SW_ALLOC_TYPE_SEP_OF) ||
((allocator_type >= `SW_ALLOC_TYPE_WF_BASE) &&
(allocator_type <= `SW_ALLOC_TYPE_WF_LIMIT)))
begin
//-------------------------------------------------------------------
// For both separable output-first and wavefront allocation, requests
// from all input VCs are combined to be propagated to the output
// side or the actual wavefront block, respectively.
//-------------------------------------------------------------------
// combine all VCs' requests
c_select_mofn
#(.width(num_ports),
.num_ports(num_vcs))
req_out_op_sel
(.select(req_in_ivc),
.data_in(route_ivc_op),
.data_out(req_out_op));
wire [0:num_ports*num_vcs-1] route_op_ivc;
c_interleaver
#(.width(num_vcs*num_ports),
.num_blocks(num_vcs))
route_op_ivc_intl
(.data_in(route_ivc_op),
.data_out(route_op_ivc));
if(allocator_type == `SW_ALLOC_TYPE_SEP_OF)
begin
//--------------------------------------------------------------
// For output-first allocation, we check which input VCs can use
// the output ports that were granted to us, and perform
// arbitration between them; another option, which would likely
// perform better if the number of VCs is greater than the
// number of ports, would be to pre-select a winning VC for each
// output port, select a single output port to use among all
// that were granted to us, and then use that to enable the VC
// that was preselected for it. Note that this is almost
// identical to what we do for the wavefront allocator, except
// for the arbitration across all outputs.
//--------------------------------------------------------------
// only update priorities if we were successful in both stages;
// since an output-side grant implies that at least one of our
// VCs actually requested the granted output, it is sufficient
// to just check for output grants here
wire update_arb;
assign update_arb = |gnt_in_op & allow_update;
// determine which of the requesting VCs can use each output
wire [0:num_ports*num_vcs-1] usable_op_ivc;
assign usable_op_ivc = route_op_ivc & {num_ports{req_in_ivc}};
// check which VCs' requests can be satisfied using the output
// port that was actually granted
wire [0:num_vcs-1] req_ivc;
c_select_mofn
#(.width(num_vcs),
.num_ports(num_ports))
req_ivc_sel
(.select(gnt_in_op),
.data_in(usable_op_ivc),
.data_out(req_ivc));
// arbitrate between all of our VCs that can use one of the
// granted outputs
wire [0:num_vcs-1] gnt_ivc;
c_arbiter
#(.num_ports(num_vcs),
.reset_type(reset_type),
.arbiter_type(arbiter_type))
gnt_ivc_arb
(.clk(clk),
.reset(reset),
.update(update_arb),
.req(req_ivc),
.gnt(gnt_ivc));
// notify winning VC
assign gnt_out_ivc = gnt_ivc;
// the flit buffer read address is determined by the winning VC
assign sel_ivc = gnt_ivc;
// since multiple ports may have been granted in the output
// stage, we must select the winning one in order to drive the
// crossbar control signals
c_select_1ofn
#(.width(num_ports),
.num_ports(num_vcs))
gnt_op_sel
(.select(gnt_ivc),
.data_in(route_ivc_op),
.data_out(gnt_out_op));
end
else if((allocator_type >= `SW_ALLOC_TYPE_WF_BASE) &&
(allocator_type <= `SW_ALLOC_TYPE_WF_LIMIT))
begin
//--------------------------------------------------------------
// A wavefront allocator will assign at most one output port to
// each input port; consequentlyl, we can pre-select a winning
// VC for each output port and then use the output port grants
// to enable the corresponding VC (if any).
//--------------------------------------------------------------
wire [0:num_ports*num_vcs-1] presel_op_ivc;
genvar op;
// pre-select winning VC for each output port
for(op = 0; op < num_ports; op = op + 1)
begin:ops
// only update arbiter if output port was actually granted
wire update_arb;
assign update_arb = gnt_in_op[op] & allow_update;
wire [0:num_vcs-1] route_ivc;
assign route_ivc
= route_op_ivc[op*num_vcs:(op+1)*num_vcs-1];
// determine VCs with requests for this output port
wire [0:num_vcs-1] req_ivc;
assign req_ivc = route_ivc & req_in_ivc;
// arbitrate between all VCs that requested this output
wire [0:num_vcs-1] gnt_ivc;
c_arbiter
#(.num_ports(num_vcs),
.reset_type(reset_type),
.arbiter_type(arbiter_type))
gnt_ivc_arb
(.clk(clk),
.reset(reset),
.update(update_arb),
.req(req_ivc),
.gnt(gnt_ivc));
assign presel_op_ivc[op*num_vcs:(op+1)*num_vcs-1]
= gnt_ivc;
end
// the preselection mask shows which output (if any) each VC was
// preselected for
wire [0:num_vcs*num_ports-1] presel_ivc_op;
c_interleaver
#(.width(num_vcs*num_ports),
.num_blocks(num_ports))
presel_ivc_op_intl
(.data_in(presel_op_ivc),
.data_out(presel_ivc_op));
// mask actual grants with pre-selected VCs, ...
wire [0:num_vcs*num_ports-1] gnt_ivc_op;
assign gnt_ivc_op = {num_vcs{gnt_in_op}} & presel_ivc_op;
// ... rearrange them by output port, ...
wire [0:num_ports*num_vcs-1] gnt_op_ivc;
c_interleaver
#(.width(num_vcs*num_ports),
.num_blocks(num_vcs))
gnt_op_ivc_intl
(.data_in(gnt_ivc_op),
.data_out(gnt_op_ivc));
// ... and generate per-VC grants
wire [0:num_vcs-1] gnt_ivc;
c_or_nto1
#(.width(num_vcs),
.num_ports(num_ports))
gnt_ivc_or
(.data_in(gnt_op_ivc),
.data_out(gnt_ivc));
// notify winning VC
assign gnt_out_ivc = gnt_ivc;
// the flit buffer read address is determined by the winning VC
assign sel_ivc = gnt_ivc;
// in the wavefront case, the final input-side port grants are
// just the output-side port grants, so just pass these through
// (this signal will be ignored at the router level anyway)
assign gnt_out_op = gnt_in_op;
end
end
endgenerate
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 06/30/2009
This block is used to communicate information back and forth between the SGDMA
and the host. When the response port is not set to streaming then this block
will be used to generate interrupts for the host. The address span of this block
differs depending on whether the enhanced features are enabled. The enhanced
features enables sequence number readback capabilties. The address map is as follows:
Enhanced features off:
Bytes Access Type Description
----- ----------- -----------
0-3 R Status(1)
4-7 R/W Control(2)
8-12 R Descriptor Watermark (write watermark[15:0],read watermark [15:0])
13-15 R Response Watermark
16-31 N/A <Reserved>
Enhanced features on:
Bytes Access Type Description
----- ----------- -----------
0-3 R Status(1)
4-7 R/W Control(2)
8-12 R Descriptor Watermark (write watermark[15:0],read watermark [15:0])
13-15 R Response Watermark
16-20 R Sequence Number (write sequence[15:0],read sequence[15:0])
21-31 N/A <Reserved>
(1) Writing to the interrupt bit of the status register clears the interrupt bit (when applicable)
(2) Writing to the software reset bit will clear the entire register (as well as all the registers for the entire SGDMA)
Status Register:
Bits Description
---- -----------
0 Busy
1 Descriptor Buffer Empty
2 Descriptor Buffer Full
3 Response Buffer Empty
4 Response Buffer Full
5 Stop State
6 Reset State
7 Stopped on Error
8 Stopped on Early Termination
9 IRQ
10-15 <Reserved>
15-31 Done count (JSF: Added 06/13/2011)
Control Register:
Bits Description
---- -----------
0 Stop (will also be set if a stop on error/early termination condition occurs)
1 Software Reset
2 Stop on Error
3 Stop on Early Termination
4 Global Interrupt Enable Mask
5 Stop descriptors (stops the dispatcher from issuing more read/write commands)
6-31 <Reserved>
Author: JCJB
Date: 08/18/2010
1.0 - Initial release
1.1 - Removed delayed reset, added set and hold sw_reset
1.2 - Updated the sw_reset register to be set when control[1] is set instead of one cycle after.
This will prevent the read or write masters from starting back up when reset while in the stop state.
1.3 - Added the stop dispatcher bit (5) to the control register
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module csr_block (
clk,
reset,
csr_writedata,
csr_write,
csr_byteenable,
csr_readdata,
csr_read,
csr_address,
csr_irq,
done_strobe,
busy,
descriptor_buffer_empty,
descriptor_buffer_full,
stop_state,
stopped_on_error,
stopped_on_early_termination,
reset_stalled,
stop,
sw_reset,
stop_on_error,
stop_on_early_termination,
stop_descriptors,
sequence_number,
descriptor_watermark,
response_watermark,
response_buffer_empty,
response_buffer_full,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
error,
early_termination
);
parameter ADDRESS_WIDTH = 3;
localparam CONTROL_REGISTER_ADDRESS = 3'b001;
input clk;
input reset;
input [31:0] csr_writedata;
input csr_write;
input [3:0] csr_byteenable;
output wire [31:0] csr_readdata;
input csr_read;
input [ADDRESS_WIDTH-1:0] csr_address;
output wire csr_irq;
input done_strobe;
input busy;
input descriptor_buffer_empty;
input descriptor_buffer_full;
input stop_state; // when the DMA runs into some error condition and you have enabled the stop on error (or when the stop control bit is written to)
input reset_stalled; // the read or write master could be in the middle of a transfer/burst so it might take a while to flush the buffers
output wire stop;
output reg stopped_on_error;
output reg stopped_on_early_termination;
output reg sw_reset;
output wire stop_on_error;
output wire stop_on_early_termination;
output wire stop_descriptors;
input [31:0] sequence_number;
input [31:0] descriptor_watermark;
input [15:0] response_watermark;
input response_buffer_empty;
input response_buffer_full;
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input [7:0] error;
input early_termination;
/* Internal wires and registers */
wire [31:0] status;
reg [31:0] control;
reg [31:0] readdata;
reg [31:0] readdata_d1;
reg irq; // writing to the status register clears the irq bit
wire set_irq;
wire clear_irq;
reg [15:0] irq_count; // writing to bit 0 clears the counter
wire clear_irq_count;
wire incr_irq_count;
wire set_stopped_on_error;
wire set_stopped_on_early_termination;
wire set_stop;
wire clear_stop;
wire global_interrupt_enable;
wire sw_reset_strobe; // this strobe will be one cycle earlier than sw_reset
wire set_sw_reset;
wire clear_sw_reset;
/********************************************** Registers ***************************************************/
// read latency is 1 cycle
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
readdata_d1 <= 0;
end
else if (csr_read == 1)
begin
readdata_d1 <= readdata;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[31:1] <= 0;
end
else
begin
if (sw_reset_strobe == 1) // reset strobe is a strobe due to this sync reset
begin
control[31:1] <= 0;
end
else
begin
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1))
begin
control[7:1] <= csr_writedata[7:1]; // stop bit will be handled seperately since it can be set by the csr slave port access or the SGDMA hitting an error condition
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[1] == 1))
begin
control[15:8] <= csr_writedata[15:8];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[2] == 1))
begin
control[23:16] <= csr_writedata[23:16];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[3] == 1))
begin
control[31:24] <= csr_writedata[31:24];
end
end
end
end
// control bit 0 (stop) is set by different sources so handling it seperately
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[0] <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
control[0] <= 0;
end
else
begin
case ({set_stop, clear_stop})
2'b00: control[0] <= control[0];
2'b01: control[0] <= 1'b0;
2'b10: control[0] <= 1'b1;
2'b11: control[0] <= 1'b1; // setting will win, this case happens control[0] is being set to 0 (resume) at the same time an error/early termination stop condition occurs
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
sw_reset <= 0;
end
else
begin
if (set_sw_reset == 1)
begin
sw_reset <= 1;
end
else if (clear_sw_reset == 1)
begin
sw_reset <= 0;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_error <= 0;
end
else
begin
case ({set_stopped_on_error, clear_stop})
2'b00: stopped_on_error <= stopped_on_error;
2'b01: stopped_on_error <= 1'b0;
2'b10: stopped_on_error <= 1'b1;
2'b11: stopped_on_error <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_early_termination <= 0;
end
else
begin
case ({set_stopped_on_early_termination, clear_stop})
2'b00: stopped_on_early_termination <= stopped_on_early_termination;
2'b01: stopped_on_early_termination <= 1'b0;
2'b10: stopped_on_early_termination <= 1'b1;
2'b11: stopped_on_early_termination <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
irq <= 0;
end
else
begin
case ({clear_irq, set_irq})
2'b00: irq <= irq;
2'b01: irq <= 1'b1;
2'b10: irq <= 1'b0;
2'b11: irq <= 1'b1; // setting will win over a clear
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq_count <= {16{1'b0}};
end
else
begin
if (sw_reset_strobe == 1)
begin
irq_count <= {16{1'b0}};
end
else
begin
case ({clear_irq_count, incr_irq_count})
2'b00: irq_count <= irq_count;
2'b01: irq_count <= irq_count + 1;
2'b10: irq_count <= {16{1'b0}};
2'b11: irq_count <= {{15{1'b0}}, 1'b1};
endcase
end
end
end
/******************************************** End Registers *************************************************/
/**************************************** Combinational Signals *********************************************/
generate
if (ADDRESS_WIDTH == 3)
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark or sequence_number)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
3'b011: readdata = response_watermark;
default: readdata = sequence_number; // all other addresses will decode to the sequence number
endcase
end
end
else
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
default: readdata = response_watermark; // all other addresses will decode to the response watermark
endcase
end
end
endgenerate
assign clear_irq = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[1] == 1) & (csr_writedata[9] == 1); // this is the IRQ bit
assign set_irq = (global_interrupt_enable == 1) & (done_strobe == 1) & // transfer ended and interrupts are enabled
((transfer_complete_IRQ_mask == 1) | // transfer ended and the transfer complete IRQ is enabled
((error & error_IRQ_mask) != 0) | // transfer ended with an error and this IRQ is enabled
((early_termination & early_termination_IRQ_mask) == 1)); // transfer ended early due to early termination and this IRQ is enabled
assign csr_irq = irq;
// Done count
assign incr_irq_count = set_irq; // Done count just counts the number of interrupts since the last reset
assign clear_irq_count = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[2] == 1) & (csr_writedata[16] == 1); // the LSB irq_count bit
assign clear_stop = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 0);
assign set_stopped_on_error = (done_strobe == 1) & (stop_on_error == 1) & (error != 0); // when clear_stop is set then the stopped_on_error register will be cleared
assign set_stopped_on_early_termination = (done_strobe == 1) & (stop_on_early_termination == 1) & (early_termination == 1); // when clear_stop is set then the stopped_on_early_termination register will be cleared
assign set_stop = ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 1)) | // host set the stop bit
(set_stopped_on_error == 1) | // SGDMA setup to stop when an error occurs from the write master
(set_stopped_on_early_termination == 1) ; // SGDMA setup to stop when the write master overflows
assign stop = control[0];
assign set_sw_reset = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[1] == 1);
assign clear_sw_reset = (sw_reset == 1) & (reset_stalled == 0);
assign sw_reset_strobe = control[1];
assign stop_on_error = control[2];
assign stop_on_early_termination = control[3];
assign global_interrupt_enable = control[4];
assign stop_descriptors = control[5];
assign csr_readdata = readdata_d1;
assign status = {irq_count, {6{1'b0}}, irq, stopped_on_early_termination, stopped_on_error, sw_reset, stop_state, response_buffer_full, response_buffer_empty, descriptor_buffer_full, descriptor_buffer_empty, busy}; // writing to the lower byte of the status register clears the irq bit
/**************************************** Combinational Signals *********************************************/
endmodule
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Wishbone wrapper for MCB interface
*/
module wb_mcb_8
(
input wire clk,
input wire rst,
/*
* Wishbone interface
*/
input wire [31:0] wb_adr_i, // ADR_I() address input
input wire [7:0] wb_dat_i, // DAT_I() data in
output wire [7:0] wb_dat_o, // DAT_O() data out
input wire wb_we_i, // WE_I write enable input
input wire wb_stb_i, // STB_I strobe input
output wire wb_ack_o, // ACK_O acknowledge output
input wire wb_cyc_i, // CYC_I cycle input
/*
* MCB interface
*/
output wire mcb_cmd_clk,
output wire mcb_cmd_en,
output wire [2:0] mcb_cmd_instr,
output wire [5:0] mcb_cmd_bl,
output wire [31:0] mcb_cmd_byte_addr,
input wire mcb_cmd_empty,
input wire mcb_cmd_full,
output wire mcb_wr_clk,
output wire mcb_wr_en,
output wire [3:0] mcb_wr_mask,
output wire [31:0] mcb_wr_data,
input wire mcb_wr_empty,
input wire mcb_wr_full,
input wire mcb_wr_underrun,
input wire [6:0] mcb_wr_count,
input wire mcb_wr_error,
output wire mcb_rd_clk,
output wire mcb_rd_en,
input wire [31:0] mcb_rd_data,
input wire mcb_rd_empty,
input wire mcb_rd_full,
input wire mcb_rd_overflow,
input wire [6:0] mcb_rd_count,
input wire mcb_rd_error
);
reg cycle_reg = 0;
reg [7:0] wb_dat_reg = 0;
reg wb_ack_reg = 0;
reg mcb_cmd_en_reg = 0;
reg mcb_cmd_instr_reg = 0;
reg mcb_wr_en_reg = 0;
reg [3:0] mcb_wr_mask_reg = 0;
assign wb_dat_o = wb_dat_reg;
assign wb_ack_o = wb_ack_reg;
assign mcb_cmd_clk = clk;
assign mcb_cmd_en = mcb_cmd_en_reg;
assign mcb_cmd_instr = mcb_cmd_instr_reg;
assign mcb_cmd_bl = 0;
assign mcb_cmd_byte_addr = wb_adr_i & 32'hFFFFFFFC;
assign mcb_wr_clk = clk;
assign mcb_wr_en = mcb_wr_en_reg;
assign mcb_wr_mask = mcb_wr_mask_reg;
assign mcb_wr_data = {wb_dat_i, wb_dat_i, wb_dat_i, wb_dat_i};
assign mcb_rd_clk = clk;
assign mcb_rd_en = 1;
always @(posedge clk) begin
if (rst) begin
cycle_reg <= 0;
mcb_cmd_en_reg <= 0;
mcb_cmd_instr_reg <= 0;
mcb_wr_en_reg <= 0;
end else begin
wb_ack_reg <= 0;
mcb_cmd_en_reg <= 0;
mcb_cmd_instr_reg <= 0;
mcb_wr_en_reg <= 0;
if (cycle_reg) begin
if (~mcb_rd_empty) begin
cycle_reg <= 0;
wb_dat_reg <= mcb_rd_data[8*(wb_adr_i & 3) +: 8];
wb_ack_reg <= 1;
end
end else if (wb_cyc_i & wb_stb_i & ~wb_ack_o) begin
if (wb_we_i) begin
mcb_cmd_instr_reg <= 3'b000;
mcb_cmd_en_reg <= 1;
mcb_wr_en_reg <= 1;
mcb_wr_mask_reg <= ~(1 << (wb_adr_i & 3));
wb_ack_reg <= 1;
end else begin
mcb_cmd_instr_reg <= 3'b001;
mcb_cmd_en_reg <= 1;
cycle_reg <= 1;
end
end
end
end
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: decerr_slave.v
//
// Description:
// Phantom slave interface used to complete W, R and B channel transfers when an
// erroneous transaction is trapped in the crossbar.
//--------------------------------------------------------------------------
//
// Structure:
// decerr_slave
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_7_decerr_slave #
(
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_RESP = 2'b11,
parameter integer C_IGNORE_ID = 0
)
(
input wire ACLK,
input wire ARESETN,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire S_AXI_WLAST,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID,
output wire [1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] S_AXI_ARLEN,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID,
output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA,
output wire [1:0] S_AXI_RRESP,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RLAST,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY
);
reg s_axi_awready_i;
reg s_axi_wready_i;
reg s_axi_bvalid_i;
reg s_axi_arready_i;
reg s_axi_rvalid_i;
localparam P_WRITE_IDLE = 2'b00;
localparam P_WRITE_DATA = 2'b01;
localparam P_WRITE_RESP = 2'b10;
localparam P_READ_IDLE = 2'b00;
localparam P_READ_START = 2'b01;
localparam P_READ_DATA = 2'b10;
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
assign S_AXI_BRESP = C_RESP;
assign S_AXI_RRESP = C_RESP;
assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}};
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
assign S_AXI_AWREADY = s_axi_awready_i;
assign S_AXI_WREADY = s_axi_wready_i;
assign S_AXI_BVALID = s_axi_bvalid_i;
assign S_AXI_ARREADY = s_axi_arready_i;
assign S_AXI_RVALID = s_axi_rvalid_i;
generate
if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite
reg s_axi_rvalid_en;
assign S_AXI_RLAST = 1'b1;
assign S_AXI_BID = 0;
assign S_AXI_RID = 0;
always @(posedge ACLK) begin
if (~ARESETN) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
end else begin
if (s_axi_bvalid_i) begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
s_axi_awready_i <= 1'b1;
end
end else if (S_AXI_WVALID & s_axi_wready_i) begin
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
end else if (S_AXI_AWVALID & s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b1;
end else begin
s_axi_awready_i <= 1'b1;
end
end
end
always @(posedge ACLK) begin
if (~ARESETN) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
s_axi_rvalid_en <= 1'b0;
end else begin
if (s_axi_rvalid_i) begin
if (S_AXI_RREADY) begin
s_axi_rvalid_i <= 1'b0;
s_axi_arready_i <= 1'b1;
end
end else if (s_axi_rvalid_en) begin
s_axi_rvalid_en <= 1'b0;
s_axi_rvalid_i <= 1'b1;
end else if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_en <= 1'b1;
end else begin
s_axi_arready_i <= 1'b1;
end
end
end
end else begin : gen_axi
reg s_axi_rlast_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i;
reg [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] read_cnt;
reg [1:0] write_cs;
reg [1:0] read_cs;
assign S_AXI_RLAST = s_axi_rlast_i;
assign S_AXI_BID = C_IGNORE_ID ? 0 : s_axi_bid_i;
assign S_AXI_RID = C_IGNORE_ID ? 0 : s_axi_rid_i;
always @(posedge ACLK) begin
if (~ARESETN) begin
write_cs <= P_WRITE_IDLE;
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
s_axi_bid_i <= 0;
end else begin
case (write_cs)
P_WRITE_IDLE:
begin
if (S_AXI_AWVALID & s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
if (C_IGNORE_ID == 0) s_axi_bid_i <= S_AXI_AWID;
s_axi_wready_i <= 1'b1;
write_cs <= P_WRITE_DATA;
end else begin
s_axi_awready_i <= 1'b1;
end
end
P_WRITE_DATA:
begin
if (S_AXI_WVALID & S_AXI_WLAST) begin
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
write_cs <= P_WRITE_RESP;
end
end
P_WRITE_RESP:
begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
s_axi_awready_i <= 1'b1;
write_cs <= P_WRITE_IDLE;
end
end
endcase
end
end
always @(posedge ACLK) begin
if (~ARESETN) begin
read_cs <= P_READ_IDLE;
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_rid_i <= 0;
read_cnt <= 0;
end else begin
case (read_cs)
P_READ_IDLE:
begin
if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
if (C_IGNORE_ID == 0) s_axi_rid_i <= S_AXI_ARID;
read_cnt <= S_AXI_ARLEN;
s_axi_rlast_i <= (S_AXI_ARLEN == 0);
read_cs <= P_READ_START;
end else begin
s_axi_arready_i <= 1'b1;
end
end
P_READ_START:
begin
s_axi_rvalid_i <= 1'b1;
read_cs <= P_READ_DATA;
end
P_READ_DATA:
begin
if (S_AXI_RREADY) begin
if (read_cnt == 0) begin
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_arready_i <= 1'b1;
read_cs <= P_READ_IDLE;
end else begin
if (read_cnt == 1) begin
s_axi_rlast_i <= 1'b1;
end
read_cnt <= read_cnt - 1;
end
end
end
endcase
end
end
end
endgenerate
endmodule
`default_nettype wire
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always reg_lvalue = @ event_identifier constant
// D: There is a dependency here between this and event keyword and ->
module main ;
reg [3:0] value1 ;
event event_ident ;
initial
begin
# 5 -> event_ident ;
end
initial
begin
if(value1 !== 4'bxxxx)
$display("FAILED - always reg_lvalue = @ event_identifier constant\n");
#10 ;
if(value1 != 4'h5)
$display("FAILED - always reg_lvalue = @ event_identifier constant\n");
else
begin
$display("PASSED\n");
$finish ;
end
end
always value1 = @ event_ident 4'h5;
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*******************************************************************
Company: UNSW
Original Author: Lingkan Gong
Project Name: XDRS
Create Date: 5/11/2010
Design Name: isolator
*******************************************************************/
`timescale 1ns/1ns
module isolator
(
//-- to/from reconfiguration-add-ons----
input rc_ackn_rr ,
output rc_ackn ,
//-- to/from producer/consumer ----
output p_prdy ,
output [31:0] p_data ,
output c_crdy ,
output c_cerr ,
input p_prdy_rr ,
input [31:0] p_data_rr ,
input c_crdy_rr ,
input c_cerr_rr ,
//-- to/from reconfiguration controller----
input is_reconfn
);
//-------------------------------------------------------------------
// Signal Declaration
//-------------------------------------------------------------------
assign rc_ackn = (~is_reconfn)? 1'b1: rc_ackn_rr;
assign p_prdy = (~is_reconfn)? 1'b0: p_prdy_rr;
assign p_data = (~is_reconfn)? 32'h0: p_data_rr;
assign c_crdy = (~is_reconfn)? 1'b0: c_crdy_rr;
// set error signal to default 1'b1 to indicate that the region
// is undergoing partial reconfiguration.
assign c_cerr = (~is_reconfn)? 1'b1: c_cerr_rr;
endmodule
|
module uartmm(input clk,
input rst,
input [7:0] uart_din,
input uart_valid,
output reg [7:0] uart_dout,
output reg uart_wr,
output [31:0] data_b,
output strobe_b,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we);
reg [7:0] uart_din_r;
reg uart_valid_r;
reg uart_ready_r;
reg uart_rd;
wire uart_busy;
wire uart_ready;
assign uart_ready = ~uart_busy;
assign uart_busy = 0;
assign strobe_b = (addr_b == 65537) | (addr_b == 65538) | (addr_b == 65539);
assign data_b = (addr_b == 65537)?uart_valid_r:
(addr_b == 65538)?uart_ready_r:
(addr_b == 65539)?uart_din_r:0;
always @(posedge clk)
if (~rst) begin
end else begin
if (uart_wr) begin
uart_wr <= 0;
end
if (uart_valid & ~uart_rd) begin
uart_rd <= 1; // TODO: read into a FIFO / raise an IRQ (when we had a support for them)
end
uart_ready_r <= uart_ready; // delay
if (uart_rd) begin
uart_rd <= 0;
uart_din_r <= uart_dout;
uart_valid_r <= 1;
end else if ((addr_b == 65539) & ~data_b_we & uart_valid_r) begin
uart_valid_r <= 0;
end else if ((addr_b == 65539) & data_b_we & uart_ready & ~uart_wr) begin
uart_dout <= data_b[7:0];
uart_wr <= 1;
end
end
endmodule
module ledwriter (input clk,
input rst,
output reg [7:0] LED,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we);
always @(posedge clk)
if (~rst) begin
LED <= 0;
end else begin
if (addr_b == 65540) begin
LED <= data_b_in[7:0];
end
end
endmodule // ledwriter
module vgadumper (input clk,
input rst,
output reg vga_dump,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we);
always @(posedge clk)
if (~rst) begin
vga_dump <= 0;
end else begin
if (vga_dump) begin
vga_dump <= 0;
end else if (addr_b == 65599 && data_b_we) begin
vga_dump <= 1;
end
end
endmodule
`ifdef RAM_REGISTERED_OUT
module socram(input clk,
input rst,
output reg [31:0] data_a,
input [31:0] addr_a,
output reg [31:0] data_b,
output reg strobe_b,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we);
parameter RAM_DEPTH = 2048;
reg [31:0] mem [0:RAM_DEPTH-1];
always @(posedge clk)
begin
if (data_b_we & (addr_b[31:16] == 0)) begin
mem[addr_b] <= data_b_in;
end
data_a <= mem[addr_a];
data_b <= mem[addr_b];
strobe_b <= (addr_b[31:16] == 0);
end
endmodule
`else // !`ifdef RAM_REGISTERED_OUT
module socram(input clk,
input rst,
output [31:0] data_a,
input [31:0] addr_a,
output [31:0] data_b,
output strobe_b,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we);
parameter RAM_DEPTH = 16384;
reg [31:0] mem [0:RAM_DEPTH-1];
assign data_a = mem[addr_a];
assign data_b = mem[addr_b];
assign strobe_b = (addr_b[31:16] == 0);
always @(posedge clk)
begin
if (data_b_we & (addr_b[31:16] == 0)) begin
mem[addr_b] <= data_b_in;
end
end
endmodule
`endif // !`ifdef RAM_REGISTERED_OUT
/*
module generic_mul ( a, b, clk, pdt);
parameter size = 32, level = 5;
input [size-1 : 0] a;
input [size-1 : 0] b;
input clk;
output [2*size-1 : 0] pdt;
reg [size-1 : 0] a_int, b_int;
reg [2*size-1 : 0] pdt_int [level-1 : 0];
integer i;
assign pdt = pdt_int [level-1];
always @ (posedge clk)
begin
a_int <= a;
b_int <= b;
pdt_int[0] <= a_int * b_int;
for(i =1;i <level;i =i +1)
pdt_int [i] <= pdt_int [i-1];
end
endmodule
module hls_Mul(input clk,
input reset,
input [31:0] p0,
input [31:0] p1,
output [31:0] out);
reg [31:0] p0t;
reg [31:0] p1t;
reg [31:0] tmp1;
reg [31:0] tmp2;
reg [31:0] tmp3;
reg [31:0] tmp4;
assign out = tmp4;
generic_mul #(.size(32),.level(3)) mul1 (.clk(clk),
.a(p0),
.b(p1),
.pdt(out));
endmodule
*/
module mul16x16 (input [15:0] a,
input [15:0] b,
output [31:0] o);
assign o = a * b;
endmodule // mul16x16
module hls_Mul(input clk,
input reset,
input [31:0] p0,
input [31:0] p1,
output [31:0] out);
wire [15:0] a = p0r[31:16];
wire [15:0] b = p0r[15:0];
wire [15:0] c = p1r[31:16];
wire [15:0] d = p1r[15:0];
wire [15:0] ad = a * d;
wire [15:0] bc = b * c;
wire [31:0] bd = b * d;
reg [15:0] adr;
reg [31:0] p0r;
reg [31:0] p1r;
reg [31:0] t1;
reg [31:0] t2;
reg [31:0] t3;
assign out = t3;
always @(posedge clk)
begin
p0r <= p0; p1r <= p1;
t1 <= bd + {bc[15:0], 16'b0}; adr <= ad[15:0];
t2 <= t1 + {adr[15:0], 16'b0};
t3 <= t2;
end
endmodule // hls_Mul
`include "../rtl/div2.v"
// 8-stage integher division pipeline
module hls_Div(input clk,
input reset,
input [31:0] p0,
input [31:0] p1,
output [31:0] out);
wire div0, ovf;
wire [31:0] rem;
div_pipelined2 #(.WIDTH(32)) d(.clk(clk),
.rst(reset),
.z(p0),
.d(p1),
.quot(out),
.rem(rem));
endmodule
// 8-stage integher division pipeline
module hls_Rem(input clk,
input reset,
input [31:0] p0,
input [31:0] p1,
output [31:0] out);
wire [31:0] quot;
div_pipelined2 #(.WIDTH(32)) d(.clk(clk),
.rst(reset),
.z(p0),
.d(p1),
.quot(quot),
.rem(out));
endmodule
`include "../rtl/mul.v"
module hls_MulFSM(input clk,
input reset,
input req,
output ack,
input [31:0] p0,
input [31:0] p1,
output [31:0] out);
mul32x32_fsm S(.clk(clk),
.rst(reset),
.req(req),
.ack(ack),
.p0(p0),
.p1(p1),
.out(out));
endmodule // hls_MulFSM
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate that an array of modules in supported.
//
module my_and (out,a,b);
input a,b;
output out;
and u0 (out,a,b);
endmodule
module main;
reg globvar;
wire [15:0] out;
reg [15:0] a,b, rslt;
reg error;
// The test gate goes HERE!
my_and foo [0:15] (out,a,b);
always @(a or b)
rslt = a & b;
initial
begin // {
error = 0;
# 1;
for(a = 16'h1; a != 16'hffff; a = (a << 1) | 1)
begin // {
for(b = 16'hffff; b !== 16'h0; b = b >> 1)
begin // {
#1 ;
if(out !== rslt)
begin // {
$display("FAILED - GA And a=%h,b=%h,expct=%h - rcvd=%h",
a,b,rslt,out);
error = 1;
end // }
end // }
end // }
if( error == 0)
$display("PASSED");
end // }
endmodule // main
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:04:47 12/01/2015
// Design Name: crc_7
// Module Name: /home/jorge/Documentos/SPI_SD/crc_7_testbench.v
// Project Name: SPI_SD
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: crc_7
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module crc_7_testbench;
// Inputs
reg start;
reg rst;
reg clk;
reg [31:0] data_in;
// Outputs
wire [7:0] data_out;
wire done;
//parameters clk
parameter PERIOD = 10; //ns
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
// Instantiate the Unit Under Test (UUT)
crc_7 uut (
.start(start),
.rst(rst),
.clk(clk),
.data_in(data_in),
.data_out(data_out),
.done(done)
);
initial begin
// Initialize Inputs
start = 0;
clk = 0;
rst = 1;
data_in = 0;
#OFFSET
// clk
forever
begin
clk = 1'b1;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b0;
#(PERIOD*DUTY_CYCLE);
end
end
initial begin
// Wait 10 ns for global reset to finish
#10;
rst=0;
start=1;
data_in=32'h00A2E015;
#10;
start=0;
@(*)begin
if (done) begin
#10
rst=1;
#10
rst=0;
end
end
end
endmodule
|
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_9_b2s_ar_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Read Address Ports
input wire [C_ID_WIDTH-1:0] s_arid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_araddr ,
input wire [7:0] s_arlen ,
input wire [2:0] s_arsize ,
input wire [1:0] s_arburst ,
input wire s_arvalid ,
output wire s_arready ,
output wire m_arvalid ,
output wire [C_AXI_ADDR_WIDTH-1:0] m_araddr ,
input wire m_arready ,
// Connections to/from axi_protocol_converter_v2_1_9_b2s_r_channel module
output wire [C_ID_WIDTH-1:0] r_arid ,
output wire r_push ,
output wire r_rlast ,
input wire r_full
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire next ;
wire next_pending ;
wire a_push;
wire incr_burst;
reg [C_ID_WIDTH-1:0] s_arid_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// Translate the AXI transaction to the MC transaction(s)
axi_protocol_converter_v2_1_9_b2s_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_axaddr ( s_araddr ) ,
.s_axlen ( s_arlen ) ,
.s_axsize ( s_arsize ) ,
.s_axburst ( s_arburst ) ,
.s_axhandshake ( s_arvalid & a_push ) ,
.incr_burst ( incr_burst ) ,
.m_axaddr ( m_araddr ) ,
.next ( next ) ,
.next_pending ( next_pending )
);
axi_protocol_converter_v2_1_9_b2s_rd_cmd_fsm ar_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_arready ( s_arready ) ,
.s_arvalid ( s_arvalid ) ,
.s_arlen ( s_arlen ) ,
.m_arvalid ( m_arvalid ) ,
.m_arready ( m_arready ) ,
.next ( next ) ,
.next_pending ( next_pending ) ,
.data_ready ( ~r_full ) ,
.a_push ( a_push ) ,
.r_push ( r_push )
);
// these signals can be moved out of this block to the top level.
assign r_arid = s_arid_r;
assign r_rlast = ~next_pending;
always @(posedge clk) begin
s_arid_r <= s_arid ;
end
endmodule
`default_nettype wire
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Addr Decoder
// Each received address is compared to base and high address pairs for each
// of a set of decode targets.
// The matching target's index (if any) is output combinatorially.
// If the decode is successful (matches any target), the MATCH output is asserted.
// For each target, a set of alternative address ranges may be specified.
// The base and high address pairs are formatted as a pair of 2-dimensional arrays,
// alternative address ranges iterate within each target.
// The alternative range which matches the address is also output as REGION.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// addr_decoder
// comparator_static
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_addr_decoder #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_TARGETS = 2, // Number of decode targets = [1:16]
parameter integer C_NUM_TARGETS_LOG = 1, // Log2(C_NUM_TARGETS)
parameter integer C_NUM_RANGES = 1, // Number of alternative ranges that
// can match each target [1:16]
parameter integer C_ADDR_WIDTH = 32, // Width of decoder operand and of
// each base and high address [2:64]
parameter integer C_TARGET_ENC = 0, // Enable encoded target output
parameter integer C_TARGET_HOT = 1, // Enable 1-hot target output
parameter integer C_REGION_ENC = 0, // Enable REGION output
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b1}},
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b0}},
parameter [C_NUM_TARGETS:0] C_TARGET_QUAL = {C_NUM_TARGETS{1'b1}},
// Indicates whether each target has connectivity.
// Format: C_NUM_TARGETS{Bit1}.
parameter integer C_RESOLUTION = 0,
// Number of low-order ADDR bits that can be ignored when decoding.
parameter integer C_COMPARATOR_THRESHOLD = 6
// Number of decoded ADDR bits above which will implement comparator_static.
)
(
input wire [C_ADDR_WIDTH-1:0] ADDR, // Decoder input operand
output wire [C_NUM_TARGETS-1:0] TARGET_HOT, // Target matching address (1-hot)
output wire [C_NUM_TARGETS_LOG-1:0] TARGET_ENC, // Target matching address (encoded)
output wire MATCH, // Decode successful
output wire [3:0] REGION // Range within target matching address (encoded)
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
genvar target_cnt;
genvar region_cnt;
/////////////////////////////////////////////////////////////////////////////
// Function to detect addrs is in the addressable range.
// Only compare 4KB page address (ignore low-order 12 bits)
function decode_address;
input [C_ADDR_WIDTH-1:0] base, high, addr;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] mask;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] addr_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] base_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] high_page;
begin
addr_page = addr[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
base_page = base[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
high_page = high[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
if (base[C_ADDR_WIDTH-1] & ~high[C_ADDR_WIDTH-1]) begin
decode_address = 1'b0;
end else begin
mask = base_page ^ high_page;
if ( (base_page & ~mask) == (addr_page & ~mask) ) begin
decode_address = 1'b1;
end else begin
decode_address = 1'b0;
end
end
end
endfunction
// Generates a binary coded from onehotone encoded
function [3:0] f_hot2enc
(
input [15:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 16'b1010101010101010);
f_hot2enc[1] = |(one_hot & 16'b1100110011001100);
f_hot2enc[2] = |(one_hot & 16'b1111000011110000);
f_hot2enc[3] = |(one_hot & 16'b1111111100000000);
end
endfunction
/////////////////////////////////////////////////////////////////////////////
// Internal signals
wire [C_NUM_TARGETS-1:0] TARGET_HOT_I; // Target matching address (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT; // For address hit (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT_REG; // For address hit (1-hot).
wire [C_NUM_RANGES-1:0] REGION_HOT; // Reginon matching address (1-hot).
wire [3:0] TARGET_ENC_I; // Internal version of encoded hit.
/////////////////////////////////////////////////////////////////////////////
// Generate detection per region per target.
generate
for (target_cnt = 0; target_cnt < C_NUM_TARGETS; target_cnt = target_cnt + 1) begin : gen_target
for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region
// Detect if this is an address hit (including used region decoding).
if ((C_ADDR_WIDTH - C_RESOLUTION) > C_COMPARATOR_THRESHOLD) begin : gen_comparator_static
if (C_TARGET_QUAL[target_cnt] &&
((C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] == 0) ||
(C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] != 0))) begin : gen_addr_range
generic_baseblocks_v2_1_comparator_static #
(
.C_FAMILY("rtl"),
.C_VALUE(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION]),
.C_DATA_WIDTH(C_ADDR_WIDTH-C_RESOLUTION)
) addr_decode_comparator
(
.CIN(1'b1),
.A(ADDR[C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] &
~(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] ^
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION])),
.COUT(ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt])
);
end else begin : gen_null_range
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = 1'b0;
end
end else begin : gen_no_comparator_static
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = C_TARGET_QUAL[target_cnt] ?
decode_address(
C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
ADDR)
: 1'b0;
end // gen_comparator_static
assign ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS+target_cnt] = ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt];
assign REGION_HOT[region_cnt] = | ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS +: C_NUM_TARGETS];
end // gen_region
// All regions are non-overlapping
// => Or all the region detections for this target to determine if it is a hit.
assign TARGET_HOT_I[target_cnt] = | ADDRESS_HIT[target_cnt*C_NUM_RANGES +: C_NUM_RANGES];
end // gen_target
endgenerate
/////////////////////////////////////////////////////////////////////////////
// All regions are non-overlapping
// => Or all the target hit detections if it is a match.
assign MATCH = | TARGET_HOT_I;
/////////////////////////////////////////////////////////////////////////////
// Assign conditional onehot target output signal.
generate
if (C_TARGET_HOT == 1) begin : USE_TARGET_ONEHOT
assign TARGET_HOT = MATCH ? TARGET_HOT_I : 1;
end else begin : NO_TARGET_ONEHOT
assign TARGET_HOT = {C_NUM_TARGETS{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded target output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_TARGET_ENCODED
assign TARGET_ENC_I = f_hot2enc(TARGET_HOT_I);
assign TARGET_ENC = TARGET_ENC_I[C_NUM_TARGETS_LOG-1:0];
end else begin : NO_TARGET_ENCODED
assign TARGET_ENC = {C_NUM_TARGETS_LOG{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded region output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_REGION_ENCODED
assign REGION = f_hot2enc(REGION_HOT);
end else begin : NO_REGION_ENCODED
assign REGION = 4'b0;
end
endgenerate
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 20 13:53:58 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_uint_to_ieee754_fp_0_1/affine_block_uint_to_ieee754_fp_0_1_stub.v
// Design : affine_block_uint_to_ieee754_fp_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "uint_to_ieee754_fp,Vivado 2016.4" *)
module affine_block_uint_to_ieee754_fp_0_1(x, y)
/* synthesis syn_black_box black_box_pad_pin="x[9:0],y[31:0]" */;
input [9:0]x;
output [31:0]y;
endmodule
|
//////////////////////////////////////////////////////////////////
// //
// 8KBytes SRAM configured with boot software //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Holds just enough software to get the system going. //
// The boot loader fits into this 8KB embedded SRAM on the //
// FPGA and enables it to load large applications via the //
// serial port (UART) into the DDR3 memory //
// //
// Author(s): //
// - Conor Santifort, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module boot_mem128 #(
parameter WB_DWIDTH = 128,
parameter WB_SWIDTH = 16,
parameter MADDR_WIDTH = 10
)(
input i_wb_clk, // WISHBONE clock
input [31:0] i_wb_adr,
input [WB_SWIDTH-1:0] i_wb_sel,
input i_wb_we,
output [WB_DWIDTH-1:0] o_wb_dat,
input [WB_DWIDTH-1:0] i_wb_dat,
input i_wb_cyc,
input i_wb_stb,
output o_wb_ack,
output o_wb_err
);
wire start_write;
wire start_read;
wire [WB_DWIDTH-1:0] read_data;
wire [WB_DWIDTH-1:0] write_data;
wire [WB_SWIDTH-1:0] byte_enable;
wire [MADDR_WIDTH-1:0] address;
`ifdef AMBER_WISHBONE_DEBUG
reg [7:0] jitter_r = 8'h0f;
reg [1:0] start_read_r = 'd0;
`else
reg start_read_r = 'd0;
`endif
// Can't start a write while a read is completing. The ack for the read cycle
// needs to be sent first
`ifdef AMBER_WISHBONE_DEBUG
assign start_write = i_wb_stb && i_wb_we && !(|start_read_r) && jitter_r[0];
`else
assign start_write = i_wb_stb && i_wb_we && !(|start_read_r);
`endif
assign start_read = i_wb_stb && !i_wb_we && !(|start_read_r);
`ifdef AMBER_WISHBONE_DEBUG
always @( posedge i_wb_clk )
jitter_r <= {jitter_r[6:0], jitter_r[7] ^ jitter_r[4] ^ jitter_r[1]};
always @( posedge i_wb_clk )
if (start_read)
start_read_r <= {3'd0, start_read};
else if (o_wb_ack)
start_read_r <= 'd0;
else
start_read_r <= {start_read_r[2:0], start_read};
`else
always @( posedge i_wb_clk )
start_read_r <= start_read;
`endif
assign o_wb_err = 1'd0;
assign write_data = i_wb_dat;
assign byte_enable = i_wb_sel;
assign o_wb_dat = read_data;
assign address = i_wb_adr[MADDR_WIDTH+3:4];
`ifdef AMBER_WISHBONE_DEBUG
assign o_wb_ack = i_wb_stb && ( start_write || start_read_r[jitter_r[1]] );
`else
assign o_wb_ack = i_wb_stb && ( start_write || start_read_r );
`endif
// ------------------------------------------------------
// Instantiate SRAMs
// ------------------------------------------------------
//
`ifdef XILINX_FPGA
xs6_sram_1024x128_byte_en
#(
// This file holds a software image used for FPGA simulations
// This pre-processor syntax works with both the simulator
// and ISE, which I couldn't get to work with giving it the
// file name as a define.
`ifdef BOOT_MEM_PARAMS_FILE
`include `BOOT_MEM_PARAMS_FILE
`else
`ifdef BOOT_LOADER_ETHMAC
`include "boot-loader-ethmac_memparams128.v"
`else
// default file
`include "boot-loader_memparams128.v"
`endif
`endif
)
`endif
`ifndef XILINX_FPGA
generic_sram_byte_en
#(
.DATA_WIDTH ( WB_DWIDTH ),
.ADDRESS_WIDTH ( MADDR_WIDTH )
)
`endif
u_mem (
.i_clk ( i_wb_clk ),
.i_write_enable ( start_write ),
.i_byte_enable ( byte_enable ),
.i_address ( address ), // 1024 words, 128 bits
.o_read_data ( read_data ),
.i_write_data ( write_data )
);
// =======================================================================================
// =======================================================================================
// =======================================================================================
// Non-synthesizable debug code
// =======================================================================================
//synopsys translate_off
`ifdef XILINX_SPARTAN6_FPGA
`ifdef BOOT_MEM_PARAMS_FILE
initial
$display("Boot mem file is %s", `BOOT_MEM_PARAMS_FILE );
`endif
`endif
//synopsys translate_on
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_writer.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Handles receiving new transaction events and data, and
// making requests to tx engine.
// for the RIFFA channel.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTWR_MAIN_IDLE 8'b0000_0001
`define S_TXPORTWR_MAIN_CHECK 8'b0000_0010
`define S_TXPORTWR_MAIN_SIG_NEW 8'b0000_0100
`define S_TXPORTWR_MAIN_NEW_ACK 8'b0000_1000
`define S_TXPORTWR_MAIN_WRITE 8'b0001_0000
`define S_TXPORTWR_MAIN_DONE 8'b0010_0000
`define S_TXPORTWR_MAIN_SIG_DONE 8'b0100_0000
`define S_TXPORTWR_MAIN_RESET 8'b1000_0000
`define S_TXPORTWR_TX_IDLE 8'b0000_0001
`define S_TXPORTWR_TX_BUF 8'b0000_0010
`define S_TXPORTWR_TX_ADJ_0 8'b0000_0100
`define S_TXPORTWR_TX_ADJ_1 8'b0000_1000
`define S_TXPORTWR_TX_ADJ_2 8'b0001_0000
`define S_TXPORTWR_TX_CHECK_DATA 8'b0010_0000
`define S_TXPORTWR_TX_WRITE 8'b0100_0000
`define S_TXPORTWR_TX_WRITE_REM 8'b1000_0000
`timescale 1ns/1ns
module tx_port_writer (
input CLK,
input RST,
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
output TXN, // Write transaction notification
input TXN_ACK, // Write transaction acknowledged
output [31:0] TXN_LEN, // Write transaction length
output [31:0] TXN_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_DONE_LEN, // Write transaction actual transfer length
output TXN_DONE, // Write transaction done
output TXN_ERR, // Write transaction encountered an error
input TXN_DONE_ACK, // Write transaction actual transfer length read
input NEW_TXN, // Transaction parameters are valid
output NEW_TXN_ACK, // Transaction parameter read, continue
input NEW_TXN_LAST, // Channel last write
input [31:0] NEW_TXN_LEN, // Channel write length (in 32 bit words)
input [30:0] NEW_TXN_OFF, // Channel write offset
input [31:0] NEW_TXN_WORDS_RECVD, // Count of data words received in transaction
input NEW_TXN_DONE, // Transaction is closed
input [63:0] SG_ELEM_ADDR, // Scatter gather element address
input [31:0] SG_ELEM_LEN, // Scatter gather element length (in words)
input SG_ELEM_RDY, // Scatter gather element ready
input SG_ELEM_EMPTY, // Scatter gather elements empty
output SG_ELEM_REN, // Scatter gather element read enable
output SG_RST, // Scatter gather data reset
input SG_ERR, // Scatter gather read encountered an error
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output TX_LAST, // Outgoing write is last request for transaction
input TX_SENT // Outgoing write complete
);
`include "functions.vh"
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [7:0] rMainState=`S_TXPORTWR_MAIN_IDLE, _rMainState=`S_TXPORTWR_MAIN_IDLE;
reg [31:0] rOffLast=0, _rOffLast=0;
reg rWordsEQ0=0, _rWordsEQ0=0;
reg rStarted=0, _rStarted=0;
reg [31:0] rDoneLen=0, _rDoneLen=0;
reg rSgErr=0, _rSgErr=0;
reg rTxErrd=0, _rTxErrd=0;
reg rTxnAck=0, _rTxnAck=0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [7:0] rTxState=`S_TXPORTWR_TX_IDLE, _rTxState=`S_TXPORTWR_TX_IDLE;
reg [31:0] rSentWords=0, _rSentWords=0;
reg [31:0] rWords=0, _rWords=0;
reg [31:0] rBufWords=0, _rBufWords=0;
reg [31:0] rBufWordsInit=0, _rBufWordsInit=0;
reg rLargeBuf=0, _rLargeBuf=0;
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg [2:0] rCarry=0, _rCarry=0;
reg rValsPropagated=0, _rValsPropagated=0;
reg [5:0] rValsProp=0, _rValsProp=0;
reg rCopyBufWords=0, _rCopyBufWords=0;
reg rUseInit=0, _rUseInit=0;
reg [10:0] rPageRem=0, _rPageRem=0;
reg rPageSpill=0, _rPageSpill=0;
reg rPageSpillInit=0, _rPageSpillInit=0;
reg [10:0] rPreLen=0, _rPreLen=0;
reg [2:0] rMaxPayloadSize=0, _rMaxPayloadSize=0;
reg [2:0] rMaxPayloadShift=0, _rMaxPayloadShift=0;
reg [9:0] rMaxPayload=0, _rMaxPayload=0;
reg rPayloadSpill=0, _rPayloadSpill=0;
reg rMaxLen=1, _rMaxLen=1;
reg [9:0] rLen=0, _rLen=0;
reg [31:0] rSendingWords=0, _rSendingWords=0;
reg rAvail=0, _rAvail=0;
reg [1:0] rTxnDone=0, _rTxnDone=0;
reg [9:0] rLastLen=0, _rLastLen=0;
reg rLastLenEQ0=0, _rLastLenEQ0=0;
reg rLenEQWords=0, _rLenEQWords=0;
reg rLenEQBufWords=0, _rLenEQBufWords=0;
reg rNotRequesting=1, _rNotRequesting=1;
reg [63:0] rReqAddr=64'd0, _rReqAddr=64'd0;
reg [9:0] rReqLen=0, _rReqLen=0;
reg rReqLast=0, _rReqLast=0;
reg rTxReqAck=0, _rTxReqAck=0;
reg rDone=0, _rDone=0;
reg [9:0] rAckCount=0, _rAckCount=0;
reg rTxSent=0, _rTxSent=0;
reg rLastDoneRead=1, _rLastDoneRead=1;
reg rTxnDoneAck=0, _rTxnDoneAck=0;
reg rReqPartialDone=0, _rReqPartialDone=0;
reg rPartialDone=0, _rPartialDone=0;
assign NEW_TXN_ACK = rMainState[1]; // S_TXPORTWR_MAIN_CHECK
assign TXN = rMainState[2]; // S_TXPORTWR_MAIN_SIG_NEW
assign TXN_DONE = (rMainState[6] | rPartialDone); // S_TXPORTWR_MAIN_SIG_DONE
assign TXN_LEN = rWords;
assign TXN_OFF_LAST = rOffLast;
assign TXN_DONE_LEN = rDoneLen;
assign TXN_ERR = rTxErrd;
assign SG_ELEM_REN = rTxState[2]; // S_TXPORTWR_TX_ADJ_0
assign SG_RST = rMainState[3]; // S_TXPORTWR_MAIN_NEW_ACK
assign TX_REQ = !rNotRequesting;
assign TX_ADDR = rReqAddr;
assign TX_LEN = rReqLen;
assign TX_LAST = rReqLast;
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rTxnAck <= #1 (RST ? 1'd0 : _rTxnAck);
rTxnDoneAck <= #1 (RST ? 1'd0 : _rTxnDoneAck);
rSgErr <= #1 (RST ? 1'd0 : _rSgErr);
rTxReqAck <= #1 (RST ? 1'd0 : _rTxReqAck);
rTxSent <= #1 (RST ? 1'd0 : _rTxSent);
end
always @ (*) begin
_rTxnAck = TXN_ACK;
_rTxnDoneAck = TXN_DONE_ACK;
_rSgErr = SG_ERR;
_rTxReqAck = TX_REQ_ACK;
_rTxSent = TX_SENT;
end
// Wait for a NEW_TXN request. Then request transfers until all the data is sent
// or until the specified length is reached. Then signal TXN_DONE.
always @ (posedge CLK) begin
rMainState <= #1 (RST ? `S_TXPORTWR_MAIN_IDLE : _rMainState);
rOffLast <= #1 _rOffLast;
rWordsEQ0 <= #1 _rWordsEQ0;
rStarted <= #1 _rStarted;
rDoneLen <= #1 (RST ? 0 : _rDoneLen);
rTxErrd <= #1 (RST ? 1'd0 : _rTxErrd);
end
always @ (*) begin
_rMainState = rMainState;
_rOffLast = rOffLast;
_rWordsEQ0 = rWordsEQ0;
_rStarted = rStarted;
_rDoneLen = rDoneLen;
_rTxErrd = rTxErrd;
case (rMainState)
`S_TXPORTWR_MAIN_IDLE: begin // Wait for channel write request
_rStarted = 0;
_rWordsEQ0 = (NEW_TXN_LEN == 0);
_rOffLast = {NEW_TXN_OFF, NEW_TXN_LAST};
if (NEW_TXN)
_rMainState = `S_TXPORTWR_MAIN_CHECK;
end
`S_TXPORTWR_MAIN_CHECK: begin // Continue with transaction?
if (rOffLast[0] | !rWordsEQ0)
_rMainState = `S_TXPORTWR_MAIN_SIG_NEW;
else
_rMainState = `S_TXPORTWR_MAIN_RESET;
end
`S_TXPORTWR_MAIN_SIG_NEW: begin // Signal new write
_rMainState = `S_TXPORTWR_MAIN_NEW_ACK;
end
`S_TXPORTWR_MAIN_NEW_ACK: begin // Wait for acknowledgement
if (rTxnAck) // ACK'd on PC read of TXN length
_rMainState = (rWordsEQ0 ? `S_TXPORTWR_MAIN_SIG_DONE : `S_TXPORTWR_MAIN_WRITE);
end
`S_TXPORTWR_MAIN_WRITE: begin // Start writing and wait for all writes to complete
_rStarted = (rStarted | rTxState[1]); // S_TXPORTWR_TX_BUF
_rTxErrd = (rTxErrd | rSgErr);
if (rTxState[0] & rStarted) // S_TXPORTWR_TX_IDLE
_rMainState = `S_TXPORTWR_MAIN_DONE;
end
`S_TXPORTWR_MAIN_DONE: begin // Wait for the last transaction to complete
if (rDone & rLastDoneRead) begin
_rDoneLen = rSentWords;
_rMainState = `S_TXPORTWR_MAIN_SIG_DONE;
end
end
`S_TXPORTWR_MAIN_SIG_DONE: begin // Signal the done port
_rTxErrd = 0;
_rMainState = `S_TXPORTWR_MAIN_RESET;
end
`S_TXPORTWR_MAIN_RESET: begin // Wait for the channel tx to drop
if (NEW_TXN_DONE)
_rMainState = `S_TXPORTWR_MAIN_IDLE;
end
default: begin
_rMainState = `S_TXPORTWR_MAIN_IDLE;
end
endcase
end
// Manage sending TX requests to the TX engine. Transfers will be limited
// by each scatter gather buffer's size, max payload size, and must not
// cross a (4KB) page boundary. The request is only made if there is sufficient
// data already written to the buffer.
wire [9:0] wLastLen = (NEW_TXN_WORDS_RECVD - rSentWords);
wire [9:0] wAddrLoInv = ~rAddr[11:2];
wire [10:0] wPageRem = (wAddrLoInv + 1'd1);
always @ (posedge CLK) begin
rTxState <= #1 (RST | rSgErr ? `S_TXPORTWR_TX_IDLE : _rTxState);
rSentWords <= #1 (rMainState[0] ? 0 : _rSentWords);
rWords <= #1 _rWords;
rBufWords <= #1 _rBufWords;
rBufWordsInit <= #1 _rBufWordsInit;
rAddr <= #1 _rAddr;
rCarry <= #1 _rCarry;
rValsPropagated <= #1 _rValsPropagated;
rValsProp <= #1 _rValsProp;
rLargeBuf <= #1 _rLargeBuf;
rPageRem <= #1 _rPageRem;
rPageSpill <= #1 _rPageSpill;
rPageSpillInit <= #1 _rPageSpillInit;
rCopyBufWords <= #1 _rCopyBufWords;
rUseInit <= #1 _rUseInit;
rPreLen <= #1 _rPreLen;
rMaxPayloadSize <= #1 _rMaxPayloadSize;
rMaxPayloadShift <= #1 _rMaxPayloadShift;
rMaxPayload <= #1 _rMaxPayload;
rPayloadSpill <= #1 _rPayloadSpill;
rMaxLen <= #1 (RST ? 1'd1 : _rMaxLen);
rLen <= #1 _rLen;
rSendingWords <= #1 _rSendingWords;
rAvail <= #1 _rAvail;
rTxnDone <= #1 _rTxnDone;
rLastLen <= #1 _rLastLen;
rLastLenEQ0 <= #1 _rLastLenEQ0;
rLenEQWords <= #1 _rLenEQWords;
rLenEQBufWords <= #1 _rLenEQBufWords;
end
always @ (*) begin
_rTxState = rTxState;
_rCopyBufWords = rCopyBufWords;
_rUseInit = rUseInit;
_rValsProp = ((rValsProp<<1) | rTxState[3]); // S_TXPORTWR_TX_ADJ_1
_rValsPropagated = (rValsProp == 6'd0);
_rLargeBuf = (SG_ELEM_LEN > rWords);
{_rCarry[0], _rAddr[15:0]} = (rTxState[1] ? SG_ELEM_ADDR[15:0] : (rAddr[15:0] + ({12{rTxState[6]}} & {rLen, 2'd0}))); // S_TXPORTWR_TX_WRITE
{_rCarry[1], _rAddr[31:16]} = (rTxState[1] ? SG_ELEM_ADDR[31:16] : (rAddr[31:16] + rCarry[0]));
{_rCarry[2], _rAddr[47:32]} = (rTxState[1] ? SG_ELEM_ADDR[47:32] : (rAddr[47:32] + rCarry[1]));
_rAddr[63:48] = (rTxState[1] ? SG_ELEM_ADDR[63:48] : (rAddr[63:48] + rCarry[2]));
_rSentWords = (rTxState[7] ? NEW_TXN_WORDS_RECVD : rSentWords) + ({10{rTxState[6]}} & rLen); // S_TXPORTWR_TX_WRITE
_rWords = (NEW_TXN_ACK ? NEW_TXN_LEN : (rWords - ({10{rTxState[6]}} & rLen))); // S_TXPORTWR_TX_WRITE
_rBufWordsInit = (rLargeBuf ? rWords : SG_ELEM_LEN);
_rBufWords = (rCopyBufWords ? rBufWordsInit : rBufWords) - ({10{rTxState[6]}} & rLen); // S_TXPORTWR_TX_WRITE
_rPageRem = wPageRem;
_rPageSpillInit = (rBufWordsInit > wPageRem);
_rPageSpill = (rBufWords > wPageRem);
_rPreLen = ((rPageSpillInit & rUseInit) | (rPageSpill & !rUseInit) ? rPageRem : rBufWords[10:0]);
_rMaxPayloadSize = CONFIG_MAX_PAYLOAD_SIZE;
_rMaxPayloadShift = (rMaxPayloadSize > 3'd4 ? 3'd4 : rMaxPayloadSize);
_rMaxPayload = (6'd32<<rMaxPayloadShift);
_rPayloadSpill = (rPreLen > rMaxPayload);
_rMaxLen = ((rMaxLen & !rValsProp[1]) | rTxState[6]); // S_TXPORTWR_TX_WRITE
_rLen = (rPayloadSpill | rMaxLen ? rMaxPayload : rPreLen[9:0]);
_rSendingWords = rSentWords + rLen;
_rAvail = (NEW_TXN_WORDS_RECVD >= rSendingWords);
_rTxnDone = ((rTxnDone<<1) | NEW_TXN_DONE);
_rLastLen = wLastLen;
_rLastLenEQ0 = (rLastLen == 10'd0);
_rLenEQWords = (rLen == rWords);
_rLenEQBufWords = (rLen == rBufWords);
case (rTxState)
`S_TXPORTWR_TX_IDLE: begin // Wait for channel write request
if (rMainState[4] & !rStarted) // S_TXPORTWR_MAIN_WRITE
_rTxState = `S_TXPORTWR_TX_BUF;
end
`S_TXPORTWR_TX_BUF: begin // Wait for buffer length and address
if (SG_ELEM_RDY)
_rTxState = `S_TXPORTWR_TX_ADJ_0;
end
`S_TXPORTWR_TX_ADJ_0: begin // Fix for large buffer
_rCopyBufWords = 1;
_rTxState = `S_TXPORTWR_TX_ADJ_1;
end
`S_TXPORTWR_TX_ADJ_1: begin // Check for page boundary crossing
_rCopyBufWords = 0;
_rUseInit = rCopyBufWords;
_rTxState = `S_TXPORTWR_TX_ADJ_2;
end
`S_TXPORTWR_TX_ADJ_2: begin // Wait for values to propagate
// Fix for page boundary crossing
// Check for max payload
// Fix for max payload
_rUseInit = 0;
if (rValsProp[2])
_rTxState = `S_TXPORTWR_TX_CHECK_DATA;
end
`S_TXPORTWR_TX_CHECK_DATA: begin // Wait for available data
if (rNotRequesting) begin
if (rAvail)
_rTxState = `S_TXPORTWR_TX_WRITE;
else if (rValsPropagated & rTxnDone[1])
_rTxState = (rLastLenEQ0 ? `S_TXPORTWR_TX_IDLE : `S_TXPORTWR_TX_WRITE_REM);
end
end
`S_TXPORTWR_TX_WRITE: begin // Send len and repeat or finish?
if (rLenEQWords)
_rTxState = `S_TXPORTWR_TX_IDLE;
else if (rLenEQBufWords)
_rTxState = `S_TXPORTWR_TX_BUF;
else
_rTxState = `S_TXPORTWR_TX_ADJ_1;
end
`S_TXPORTWR_TX_WRITE_REM: begin // Send remaining data and finish
_rTxState = `S_TXPORTWR_TX_IDLE;
end
default: begin
_rTxState = `S_TXPORTWR_TX_IDLE;
end
endcase
end
// Request TX transfers separately so that the TX FSM can continue calculating
// the next set of request parameters without having to wait for the TX_REQ_ACK.
always @ (posedge CLK) begin
rAckCount <= #1 (RST ? 10'd0 : _rAckCount);
rNotRequesting <= #1 (RST ? 1'd1 : _rNotRequesting);
rReqAddr <= #1 _rReqAddr;
rReqLen <= #1 _rReqLen;
rReqLast <= #1 _rReqLast;
rDone <= #1 _rDone;
rLastDoneRead <= #1 (RST ? 1'd1 : _rLastDoneRead);
end
always @ (*) begin
// Start signaling when the TX FSM is ready.
if (rTxState[6] | rTxState[7]) // S_TXPORTWR_TX_WRITE
_rNotRequesting = 0;
else
_rNotRequesting = (rNotRequesting | rTxReqAck);
// Pass off the rAddr & rLen when ready and wait for TX_REQ_ACK.
if (rTxState[6]) begin // S_TXPORTWR_TX_WRITE
_rReqAddr = rAddr;
_rReqLen = rLen;
_rReqLast = rLenEQWords;
end
else if (rTxState[7]) begin // S_TXPORTWR_TX_WRITE_REM
_rReqAddr = rAddr;
_rReqLen = rLastLen;
_rReqLast = 1;
end
else begin
_rReqAddr = rReqAddr;
_rReqLen = rReqLen;
_rReqLast = rReqLast;
end
// Track TX_REQ_ACK and TX_SENT to determine when the transaction is over.
_rDone = (rAckCount == 10'd0);
if (rMainState[0]) // S_TXPORTWR_MAIN_IDLE
_rAckCount = 0;
else
_rAckCount = rAckCount + rTxState[6] + rTxState[7] - rTxSent; // S_TXPORTWR_TX_WRITE, S_TXPORTWR_TX_WRITE_REM
// Track when the user reads the actual transfer amount.
_rLastDoneRead = (rMainState[6] ? 1'd0 : (rLastDoneRead | rTxnDoneAck)); // S_TXPORTWR_MAIN_SIG_DONE
end
// Facilitate sending a TXN_DONE when we receive a TXN_ACK after the transaction
// has begun sending. This will happen when the workstation detects that it has
// sent/used all its currently mapped scatter gather elements, but it's not enough
// to complete the transaction. The TXN_DONE will let the workstation know it can
// release the current scatter gather mappings and allocate new ones.
always @ (posedge CLK) begin
rPartialDone <= #1 _rPartialDone;
rReqPartialDone <= #1 (RST ? 1'd0 : _rReqPartialDone);
end
always @ (*) begin
// Signal TXN_DONE after we've recieved the (seemingly superfluous) TXN_ACK,
// we have no outstanding transfer requests, we're not currently requesting a
// transfer, and there are no more scatter gather elements.
_rPartialDone = (rReqPartialDone & rDone & rNotRequesting & SG_ELEM_EMPTY & rTxState[1]); // S_TXPORTWR_TX_BUF
// Keep track of (seemingly superfluous) TXN_ACK requests.
if ((rReqPartialDone & rDone & rNotRequesting & SG_ELEM_EMPTY & rTxState[1]) | rMainState[0]) // S_TXPORTWR_MAIN_IDLE
_rReqPartialDone = 0;
else
_rReqPartialDone = (rReqPartialDone | (rTxnAck & !rMainState[3])); // !S_TXPORTWR_MAIN_NEW_ACK
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CLK),
.CONTROL(wControl0),
.TRIG0({rTxState[6] | rTxState[7] | rTxSent, rAckCount[6:0]}),
.DATA({280'd0,
NEW_TXN_WORDS_RECVD, // 32
rSendingWords, // 32
rAvail, // 1
rNotRequesting, // 1
NEW_TXN_LAST, // 1
NEW_TXN_LEN, // 32
NEW_TXN_OFF, // 31
NEW_TXN, // 1
rAckCount, // 10
rLastDoneRead, // 1
rWords, // 32
rBufWords, // 32
rLen, // 10
rTxState, // 8
rMainState}) // 8
);
*/
endmodule
|
// ====================================================================
// Bashkiria-2M FPGA REPLICA
//
// Copyright (C) 2010 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Bashkiria-2M home computer
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Design File: k580ww55.v
//
// Parallel interface k580ww55 design file of Bashkiria-2M replica.
//
// Warning: This realization is not fully operational.
module k580ww55(
input clk, input reset, input[1:0] addr, input we_n,
input[7:0] idata, output reg[7:0] odata,
input[7:0] ipa, output reg[7:0] opa,
input[7:0] ipb, output reg[7:0] opb,
input[7:0] ipc, output reg[7:0] opc);
//reg[6:0] mode;
always begin
case (addr)
2'b00: odata = ipa;
2'b01: odata = ipb;
2'b10: odata = ipc;
2'b11: odata = 8'h00;
endcase
end
always @(posedge clk or posedge reset) begin
if (reset) begin
//mode <= 7'b0011011;
{opa,opb,opc} <= {8'hFF,8'hFF,8'hFF};
end else
if (~we_n) begin
if (addr==2'b00) opa <= idata;
if (addr==2'b01) opb <= idata;
if (addr==2'b10) opc <= idata;
//if (addr==2'b11 && idata[7]) mode <= idata[6:0];
if (addr==2'b11 && ~idata[7]) opc[idata[3:1]] <= idata[0];
end
end
endmodule
|
// wasca_mm_interconnect_0_avalon_st_adapter_005.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module wasca_mm_interconnect_0_avalon_st_adapter_005 #(
parameter inBitsPerSymbol = 10,
parameter inUsePackets = 0,
parameter inDataWidth = 10,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 10,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [9:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [9:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
wasca_mm_interconnect_0_avalon_st_adapter_005_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module is a FIFO with same clock for both reads and writes. *
* *
******************************************************************************/
module altera_up_sync_fifo (
// Inputs
clk,
reset,
write_en,
write_data,
read_en,
// Bidirectionals
// Outputs
fifo_is_empty,
fifo_is_full,
words_used,
read_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 31; // Data width
parameter DATA_DEPTH = 128;
parameter AW = 6; // Address width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input write_en;
input [DW: 0] write_data;
input read_en;
// Bidirectionals
// Outputs
output fifo_is_empty;
output fifo_is_full;
output [AW: 0] words_used;
output [DW: 0] read_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Sync_FIFO (
// Inputs
.clock (clk),
.sclr (reset),
.data (write_data),
.wrreq (write_en),
.rdreq (read_en),
// Bidirectionals
// Outputs
.empty (fifo_is_empty),
.full (fifo_is_full),
.usedw (words_used),
.q (read_data),
// Unused
// synopsys translate_off
.aclr (),
.almost_empty (),
.almost_full ()
// synopsys translate_on
);
defparam
Sync_FIFO.add_ram_output_register = "OFF",
Sync_FIFO.intended_device_family = "Cyclone II",
Sync_FIFO.lpm_numwords = DATA_DEPTH,
Sync_FIFO.lpm_showahead = "ON",
Sync_FIFO.lpm_type = "scfifo",
Sync_FIFO.lpm_width = DW + 1,
Sync_FIFO.lpm_widthu = AW + 1,
Sync_FIFO.overflow_checking = "OFF",
Sync_FIFO.underflow_checking = "OFF",
Sync_FIFO.use_eab = "ON";
endmodule
|
//==================================================================================================
// Filename : antares_idex_register.v
// Created On : Sat Sep 5 21:08:59 2015
// Last Modified : Sat Nov 07 12:09:34 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : Pipeline register: ID -> EX
//==================================================================================================
module antares_idex_register (
input clk, // Main clock
input rst, // Main reset
input [4:0] id_alu_operation, // ALU operation from ID stage
input [31:0] id_data_rs, // Data Rs (forwarded)
input [31:0] id_data_rt, // Data Rt (forwarded)
input id_gpr_we, // GPR write enable
input id_mem_to_gpr_select, // Select MEM/ALU to GPR
input id_mem_write, // write to memory
input [1:0] id_alu_port_a_select, // Select: GPR, shamt, 0x00000004
input [1:0] id_alu_port_b_select, // Select: GPR, Imm16, PCAdd4
input [1:0] id_gpr_wa_select, // Select: direccion: Rt, Rd, $31
input id_mem_byte, // byte access
input id_mem_halfword, // halfword access
input id_mem_data_sign_ext, // Zero/Sign extend
input [4:0] id_rs, // Rs
input [4:0] id_rt, // Rt
input [3:0] id_dp_hazard,
input id_imm_sign_ext, // extend the imm16
input [15:0] id_sign_imm16, // sign_ext(imm16)
input [31:0] id_cp0_data, //
input [31:0] id_exception_pc, // Current PC
input id_movn,
input id_movz,
input id_llsc,
input id_kernel_mode,
input id_is_bds,
input id_trap,
input id_trap_condition,
input id_ex_exception_source,
input id_mem_exception_source,
input id_flush, // clean
input id_stall, // Stall ID stage
input ex_stall, // Stall EX stage
output reg [4:0] ex_alu_operation, // Same signals, but on EX stage
output reg [31:0] ex_data_rs, //
output reg [31:0] ex_data_rt, //
output reg ex_gpr_we, //
output reg ex_mem_to_gpr_select, //
output reg ex_mem_write, //
output reg [1:0] ex_alu_port_a_select, //
output reg [1:0] ex_alu_port_b_select, //
output reg [1:0] ex_gpr_wa_select, //
output reg ex_mem_byte, //
output reg ex_mem_halfword, //
output reg ex_mem_data_sign_ext, //
output reg [4:0] ex_rs, //
output reg [4:0] ex_rt, //
output reg [3:0] ex_dp_hazard,
output reg [16:0] ex_sign_imm16, //
output reg [31:0] ex_cp0_data,
output reg [31:0] ex_exception_pc,
output reg ex_movn,
output reg ex_movz,
output reg ex_llsc,
output reg ex_kernel_mode,
output reg ex_is_bds,
output reg ex_trap,
output reg ex_trap_condition,
output reg ex_ex_exception_source,
output reg ex_mem_exception_source
);
// sign extend the imm16
wire [16:0] id_imm_extended = (id_imm_sign_ext) ? {id_sign_imm16[15], id_sign_imm16[15:0]} : {1'b0, id_sign_imm16};
//--------------------------------------------------------------------------
// Propagate signals
// Clear only critical signals: op, WE, MEM write and Next PC
//--------------------------------------------------------------------------
always @(posedge clk) begin
ex_alu_operation <= (rst) ? 5'b0 : ((ex_stall & ~id_flush) ? ex_alu_operation : ((id_stall | id_flush) ? 5'b0 : id_alu_operation));
ex_data_rs <= (rst) ? 32'b0 : ((ex_stall & ~id_flush) ? ex_data_rs : id_data_rs);
ex_data_rt <= (rst) ? 32'b0 : ((ex_stall & ~id_flush) ? ex_data_rt : id_data_rt);
ex_gpr_we <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_gpr_we : ((id_stall | id_flush) ? 1'b0 : id_gpr_we));
ex_mem_to_gpr_select <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_mem_to_gpr_select : ((id_stall | id_flush) ? 1'b0 : id_mem_to_gpr_select));
ex_mem_write <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_mem_write : ((id_stall | id_flush) ? 1'b0 : id_mem_write));
ex_alu_port_a_select <= (rst) ? 2'b0 : ((ex_stall & ~id_flush) ? ex_alu_port_a_select : id_alu_port_a_select);
ex_alu_port_b_select <= (rst) ? 2'b0 : ((ex_stall & ~id_flush) ? ex_alu_port_b_select : id_alu_port_b_select);
ex_gpr_wa_select <= (rst) ? 2'b0 : ((ex_stall & ~id_flush) ? ex_gpr_wa_select : id_gpr_wa_select);
ex_mem_byte <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_mem_byte : id_mem_byte);
ex_mem_halfword <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_mem_halfword : id_mem_halfword);
ex_mem_data_sign_ext <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_mem_data_sign_ext : id_mem_data_sign_ext);
ex_rs <= (rst) ? 5'b0 : ((ex_stall & ~id_flush) ? ex_rs : id_rs);
ex_rt <= (rst) ? 5'b0 : ((ex_stall & ~id_flush) ? ex_rt : id_rt);
ex_dp_hazard <= (rst) ? 4'b0 : ((ex_stall & ~id_flush) ? ex_dp_hazard : ((id_stall | id_flush) ? 4'b0 : id_dp_hazard));
ex_sign_imm16 <= (rst) ? 17'b0 : ((ex_stall & ~id_flush) ? ex_sign_imm16 : id_imm_extended);
ex_cp0_data <= (rst) ? 32'b0 : ((ex_stall & ~id_flush) ? ex_cp0_data : id_cp0_data);
ex_exception_pc <= (rst) ? 32'b0 : ((ex_stall & ~id_flush) ? ex_exception_pc : id_exception_pc);
ex_movn <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_movn : ((id_stall | id_flush) ? 1'b0 : id_movn));
ex_movz <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_movz : ((id_stall | id_flush) ? 1'b0 : id_movz));
ex_llsc <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_llsc : id_llsc);
ex_kernel_mode <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_kernel_mode : id_kernel_mode);
ex_is_bds <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_is_bds : id_is_bds);
ex_trap <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_trap : ((id_stall | id_flush) ? 1'b0 : id_trap));
ex_trap_condition <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_trap_condition : id_trap_condition);
ex_ex_exception_source <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_ex_exception_source : ((id_stall | id_flush) ? 1'b0 : id_ex_exception_source));
ex_mem_exception_source <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_mem_exception_source : ((id_stall | id_flush) ? 1'b0 : id_mem_exception_source));
end // always @ (posedge clk)
endmodule // antares_idex_register
|
// Copyright (C) 2020-2021 The SymbiFlow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier:ISC
(* blackbox *)
(* keep *)
module qlal3_left_assp_macro (
input A2F_ACK,
output [ 7:0] A2F_ADDR,
output [ 7:0] A2F_Control,
input [ 7:0] A2F_GP_IN,
output [ 7:0] A2F_GP_OUT,
input [ 7:0] A2F_RD_DATA,
output A2F_REQ,
output A2F_RWn,
input [ 6:0] A2F_Status,
output [ 7:0] A2F_WR_DATA,
input [31:0] Amult0,
input [31:0] Bmult0,
output [63:0] Cmult0,
input [ 8:0] RAM0_ADDR,
input RAM0_CLK,
input RAM0_CLKS,
output [35:0] RAM0_RD_DATA,
input RAM0_RD_EN,
input RAM0_RME_af,
input [ 3:0] RAM0_RM_af,
input RAM0_TEST1_af,
input [ 3:0] RAM0_WR_BE,
input [35:0] RAM0_WR_DATA,
input RAM0_WR_EN,
input [11:0] RAM8K_P0_ADDR,
input RAM8K_P0_CLK,
input RAM8K_P0_CLKS,
input [ 1:0] RAM8K_P0_WR_BE,
input [16:0] RAM8K_P0_WR_DATA,
input RAM8K_P0_WR_EN,
input [11:0] RAM8K_P1_ADDR,
input RAM8K_P1_CLK,
input RAM8K_P1_CLKS,
output [16:0] RAM8K_P1_RD_DATA,
input RAM8K_P1_RD_EN,
input RAM8K_P1_mux,
input RAM8K_RME_af,
input [ 3:0] RAM8K_RM_af,
input RAM8K_TEST1_af,
output RAM8K_fifo_almost_empty,
output RAM8K_fifo_almost_full,
output [ 3:0] RAM8K_fifo_empty_flag,
input RAM8K_fifo_en,
output [ 3:0] RAM8K_fifo_full_flag,
input RESET_n,
input RESET_nS,
input SEL_18_bottom,
input SEL_18_left,
input SEL_18_right,
input SEL_18_top,
input SPI_CLK,
input SPI_CLKS,
output SPI_MISO,
output SPI_MISOe,
input SPI_MOSI,
input SPI_SSn,
output SYSCLK,
output SYSCLK_x2,
input Valid_mult0,
input [ 3:0] af_burnin_mode,
input [31:0] af_dev_id,
input af_fpga_int_en,
input af_opt_0,
input af_opt_1,
input \af_plat_id[0] ,
input \af_plat_id[1] ,
input \af_plat_id[2] ,
input \af_plat_id[3] ,
input \af_plat_id[4] ,
input \af_plat_id[5] ,
input \af_plat_id[6] ,
input \af_plat_id[7] ,
input af_spi_cpha,
input af_spi_cpol,
input af_spi_lsbf,
input default_SPI_IO_mux,
input drive_io_en_0,
input drive_io_en_1,
input drive_io_en_2,
input drive_io_en_3,
input drive_io_en_4,
input drive_io_en_5,
output fast_clk_out,
input [ 7:0] int_i,
output int_o,
input osc_en,
input osc_fsel,
input [ 2:0] osc_sel,
input [ 1:0] reg_addr_int,
input reg_clk_int,
input reg_clk_intS,
output [ 7:0] reg_rd_data_int,
input reg_rd_en_int,
input [ 7:0] reg_wr_data_int,
input reg_wr_en_int
);
endmodule
(* blackbox *)
(* keep *)
module qlal3_right_assp_macro (
input [31:0] Amult1,
input [31:0] Bmult1,
output [63:0] Cmult1,
output DrivingI2cBusOut,
input [ 8:0] RAM1_ADDR,
input RAM1_CLK,
input RAM1_CLKS,
output [35:0] RAM1_RD_DATA,
input RAM1_RD_EN,
input RAM1_RME_af,
input [ 3:0] RAM1_RM_af,
input RAM1_TEST1_af,
input [ 3:0] RAM1_WR_BE,
input [35:0] RAM1_WR_DATA,
input RAM1_WR_EN,
input [ 8:0] RAM2_P0_ADDR,
input RAM2_P0_CLK,
input RAM2_P0_CLKS,
input [ 3:0] RAM2_P0_WR_BE,
input [31:0] RAM2_P0_WR_DATA,
input RAM2_P0_WR_EN,
input [ 8:0] RAM2_P1_ADDR,
input RAM2_P1_CLK,
input RAM2_P1_CLKS,
output [31:0] RAM2_P1_RD_DATA,
input RAM2_P1_RD_EN,
input RAM2_RME_af,
input [ 3:0] RAM2_RM_af,
input RAM2_TEST1_af,
input [ 8:0] RAM3_P0_ADDR,
input RAM3_P0_CLK,
input RAM3_P0_CLKS,
input [31:0] RAM3_P0_WR_DATA,
input [ 3:0] RAM3_P0_WR_EN,
input [ 8:0] RAM3_P1_ADDR,
input RAM3_P1_CLK,
input RAM3_P1_CLKS,
output [31:0] RAM3_P1_RD_DATA,
input RAM3_P1_RD_EN,
input RAM3_RME_af,
input [ 3:0] RAM3_RM_af,
input RAM3_TEST1_af,
input SCL_i,
output SCL_o,
output SCL_oen,
input SDA_i,
output SDA_o,
output SDA_oen,
input Valid_mult1,
input al_clr_i,
output al_o,
input al_stick_en_i,
input arst,
input arstS,
output i2c_busy_o,
input rxack_clr_i,
output rxack_o,
input rxack_stick_en_i,
output tip_o,
output wb_ack,
input [ 2:0] wb_adr,
input wb_clk,
input wb_clkS,
input wb_cyc,
input [ 7:0] wb_dat_i,
output [ 7:0] wb_dat_o,
output wb_inta,
input wb_rst,
input wb_rstS,
input wb_stb,
input wb_we
);
endmodule
// ============================================================================
// Cells common to ASSPL and ASSPR
(* blackbox *)
module qlal3_mult_32x32_cell (
input [31:0] Amult,
input [31:0] Bmult,
input Valid_mult,
output [63:0] Cmult
);
endmodule
(* blackbox *)
module qlal3_ram_512x36_cell (
input [ 8:0] RAM_ADDR,
input RAM_CLK,
input RAM_CLKS,
output [35:0] RAM_RD_DATA,
input RAM_RD_EN,
input RAM_RME_af,
input [ 3:0] RAM_RM_af,
input RAM_TEST1_af,
input [ 3:0] RAM_WR_BE,
input [35:0] RAM_WR_DATA,
input RAM_WR_EN
);
endmodule
(* blackbox *)
module qlal3_ram_512x32_cell (
input [ 8:0] RAM_P0_ADDR,
input RAM_P0_CLK,
input RAM_P0_CLKS,
input [ 3:0] RAM_P0_WR_BE,
input [31:0] RAM_P0_WR_DATA,
input RAM_P0_WR_EN,
input [ 8:0] RAM_P1_ADDR,
input RAM_P1_CLK,
input RAM_P1_CLKS,
output [31:0] RAM_P1_RD_DATA,
input RAM_P1_RD_EN,
input RAM_RME_af,
input [ 3:0] RAM_RM_af,
input RAM_TEST1_af,
);
endmodule
(* blackbox *)
module qlal3_ram_4096x17_cell (
input [11:0] RAM_P0_ADDR,
input RAM_P0_CLK,
input RAM_P0_CLKS,
input [ 1:0] RAM_P0_WR_BE,
input [16:0] RAM_P0_WR_DATA,
input RAM_P0_WR_EN,
input [11:0] RAM_P1_ADDR,
input RAM_P1_CLK,
input RAM_P1_CLKS,
output [16:0] RAM_P1_RD_DATA,
input RAM_P1_RD_EN,
input RAM_P1_mux,
input RAM_RME_af,
input [ 3:0] RAM_RM_af,
input RAM_TEST1_af,
output RAM_fifo_almost_empty,
output RAM_fifo_almost_full,
output [ 3:0] RAM_fifo_empty_flag,
input RAM_fifo_en,
output [ 3:0] RAM_fifo_full_flag
);
endmodule
// ============================================================================
// Cells specific to ASSPL
(* blackbox *)
module qlal3_spi_cell (
input A2F_ACK,
output [ 7:0] A2F_ADDR,
output [ 7:0] A2F_Control,
input [ 7:0] A2F_GP_IN,
output [ 7:0] A2F_GP_OUT,
input [ 7:0] A2F_RD_DATA,
output A2F_REQ,
output A2F_RWn,
input [ 6:0] A2F_Status,
output [ 7:0] A2F_WR_DATA,
input af_spi_cpha,
input af_spi_cpol,
input af_spi_lsbf,
input SPI_CLK,
input SPI_CLKS,
output SPI_MISO,
output SPI_MISOe,
input SPI_MOSI,
input SPI_SSn
);
endmodule
(* blackbox *)
module qlal3_interrupt_controller_cell (
input af_fpga_int_en,
input [ 7:0] int_i,
output int_o,
input [ 1:0] reg_addr_int,
input reg_clk_int,
input reg_clk_intS,
output [ 7:0] reg_rd_data_int,
input reg_rd_en_int,
input [ 7:0] reg_wr_data_int,
input reg_wr_en_int
);
endmodule
(* blackbox *)
module qlal3_oscillator_cell (
input osc_en,
input osc_fsel,
input [ 2:0] osc_sel,
output fast_clk_out
);
endmodule
(* blackbox *)
module qlal3_io_control_cell (
input default_SPI_IO_mux,
input drive_io_en_0,
input drive_io_en_1,
input drive_io_en_2,
input drive_io_en_3,
input drive_io_en_4,
input drive_io_en_5
);
endmodule
(* blackbox *)
module qlal3_system_cell (
input RESET_n,
input RESET_nS,
input SEL_18_bottom,
input SEL_18_left,
input SEL_18_right,
input SEL_18_top,
output SYSCLK,
output SYSCLK_x2,
input [ 3:0] af_burnin_mode,
input [31:0] af_dev_id,
input af_opt_0,
input af_opt_1,
input \af_plat_id[0] ,
input \af_plat_id[1] ,
input \af_plat_id[2] ,
input \af_plat_id[3] ,
input \af_plat_id[4] ,
input \af_plat_id[5] ,
input \af_plat_id[6] ,
input \af_plat_id[7]
);
endmodule
// ============================================================================
// Cells specific to ASSPR
(* blackbox *)
module qlal3_i2c_cell (
input arst,
input arstS,
output wb_ack,
input [ 2:0] wb_adr,
input wb_clk,
input wb_clkS,
input wb_cyc,
input [ 7:0] wb_dat_i,
output [ 7:0] wb_dat_o,
output wb_inta,
input wb_rst,
input wb_rstS,
input wb_stb,
input wb_we,
input al_clr_i,
output al_o,
input al_stick_en_i,
output i2c_busy_o,
input rxack_clr_i,
output rxack_o,
input rxack_stick_en_i,
output tip_o,
output DrivingI2cBusOut,
input SCL_i,
output SCL_o,
output SCL_oen,
input SDA_i,
output SDA_o,
output SDA_oen
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08/28/2016 01:49:26 AM
// Design Name:
// Module Name: KOA_2
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module KOA_2 //#(parameter SW = 24)
//#(parameter SW = 54)
#(parameter SW = 12)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
//wire [SW-1:0] Data_A_i;
//wire [SW-1:0] Data_B_i;
//wire [2*(SW/2)-1:0] result_left_mult;
//wire [2*(SW/2+1)-1:0] result_right_mult;
wire [SW/2+1:0] result_A_adder; /*P=SW/2+1*/
//wire [SW/2+1:0] Q_result_A_adder;
wire [SW/2+1:0] result_B_adder; /*P=SW/2+1*/
//wire [SW/2+1:0] Q_result_B_adder;
//wire [2*(SW/2+2)-1:0] result_middle_mult;
wire [SW-1:0] Q_left;
wire [SW+1:0] Q_right;
wire [SW+3:0] Q_middle; ///Modificación J: Le he agregado dos bits al largo del puerto, para acomodar los 2 cero el resultado de una multiplicacion
wire [2*(SW/2+2)-1:0] S_A;
wire [2*(SW/2+2)-1:0] S_B;
wire [4*(SW/2)+2:0] Result;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 =2'b00;
assign zero2 =4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2-3:0] leftside1;
wire [SW/2:0] rightside2;
wire fill;
wire [4*(SW/2)-1:0] sgf_r;
assign fil = 1'b0;
assign rightside1 = (SW/2) *1'b0;
assign rightside2 = (SW/2+1)*1'b0;
assign leftside1 = (SW/2-2) *1'b0;
localparam half = SW/2;
localparam full_port = SW - 1;
//localparam level1=4;
//localparam level2=5;
////////////////////////////////////
generate
case (SW%2)
0:begin
////////////////////////////////even//////////////////////////////////
//Multiplier for left side and right side
KOA_1 #(.SW(SW/2)/*,.level(level1)*/) left(
.Data_A_i(Data_A_i[full_port:half]/*P=SW/2*/),
.Data_B_i(Data_B_i[full_port:half]/*P=SW/2*/),
.sgf_result_o(Q_left) /*P=SW*//*result_left_mult*/
);
KOA_1 #(.SW(SW/2)) right( /*,.level(level1)*/
.Data_A_i(Data_A_i[half-1:0]/*P=SW/2*/),
.Data_B_i(Data_B_i[half-1:0]/*P=SW/2*/),
.sgf_result_o(Q_right[full_port:0]/*P=SW*/) /*result_right_mult[2*(SW/2)-1:0]*/
);
//Adders for middle
adder #(.W(SW/2)) A_operation (
.Data_A_i(Data_A_i[SW-1:SW/2]/*P=SW/2*/),
.Data_B_i(Data_A_i[SW/2-1:0]/*P=SW/2*/),
.Data_S_o(result_A_adder[SW/2:0]/*P=SW/2+1*/)
);
adder #(.W(SW/2)) B_operation (
.Data_A_i(Data_B_i[SW-1:SW/2]/*P=SW/2*/),
.Data_B_i(Data_B_i[SW/2-1:0]/*P=SW/2*/),
.Data_S_o(result_B_adder[SW/2:0]/*P=SW/2+1*/)
);
//multiplication for middle
//Introducimos un par de ceros, ya que esta multiplicacion es siempre impar, gracias al sumador que viene detras.
//Modificación: Le agregué otro bit al puerto de este multiplicador, para que fuera par.
KOA_1 #(.SW(SW/2+2)/* Port length = SW/2 + 2*/) middle (
.Data_A_i({fill /*P=1*/,result_A_adder[SW/2:0]/*P=SW/2+1*/}), /*Q_result_A_adder[SW/2+1:0]*/
.Data_B_i({fill /*P=1*/,result_B_adder[SW/2:0]/*P=SW/2+1*/}), /*Q_result_B_adder[SW/2+1:0]*/
.sgf_result_o(Q_middle[SW+3:0]) /*result_middle_mult[2*(SW/2)+2:0]*/
//Vamos a truncar este resultado en la siguiente etapa del puerto
);
// wire [SW-1:0] Q_left;
// wire [SW+1:0] Q_right;
// wire [SW+3:0] Q_middle;
///Subtractors for middle
substractor #(.W(SW+2)) Subtr_1 (
.Data_A_i(Q_middle[SW+1:0] /*P=SW+2*/), /*result_middle_mult//*/
.Data_B_i({zero1/*P=2*/, Q_left /*P=SW*/}), /*result_left_mult//*/
.Data_S_o(S_A[SW+1:0]/*P=SW+2*/)
);
substractor #(.W(SW+2)) Subtr_2 (
.Data_A_i(S_A[2*(SW/2)+1:0] /*P=SW+2*/),
.Data_B_i({zero1 /*P=2*/, Q_right[SW-1:0] /*P=SW*/}), /*result_right_mult//*/
.Data_S_o(S_B[2*(SW/2)+1:0]) //Port width is SW+1
);
//wire [SW-1:0] Q_left; /*P=SW*/
//wire [SW+1:0] Q_right; /*P=SW+2*/
//Final adder
adder #(.W(2*SW)) Final(
.Data_A_i({Q_left /*P=SW*/ ,Q_right[SW-1:0]/*P=SW*/}), //Port width is 2*SW /*result_left_mult,result_right_mult*/
.Data_B_i({leftside1,S_B[2*(SW/2)+1:0],rightside1}),
.Data_S_o(Result[4*(SW/2):0]/*P=2*SW+1*/)
);
//Final Register
RegisterAdd #(.W(2*SW)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin
//////////////////////////////////odd//////////////////////////////////
//Multiplier for left side and right side
KOA_1 #(.SW(SW/2)/*,.level(level2)*/) left_high(
.Data_A_i(Data_A_i[SW-1:SW/2]),
.Data_B_i(Data_B_i[SW-1:SW/2]),
.sgf_result_o(/*result_left_mult*/Q_left)
);
/*RegisterAdd #(.W(2*(SW/2))) leftreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_left_mult),
.Q(Q_left)
);//*/
KOA_1 #(.SW((SW/2)+1)/*,.level(level2)*/) right_lower(
.Data_A_i(Data_A_i[SW/2-1:0]), //Numeros pares debe de hacer un redondeo hacia abajo
.Data_B_i(Data_B_i[SW/2-1:0]),
.sgf_result_o(/*result_right_mult*/Q_right)
);
/*RegisterAdd #(.W(2*((SW/2)+1))) rightreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_right_mult),
.Q(Q_right)
);//*/
//Adders for middle
adder #(.W(SW/2+1)) A_operation (
.Data_A_i({1'b0,Data_A_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder)
);
adder #(.W(SW/2+1)) B_operation (
.Data_A_i({1'b0,Data_B_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder)
);
//segmentation registers for 64 bits
/*RegisterAdd #(.W(SW/2+2)) preAreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_A_adder),
.Q(Q_result_A_adder)
);//
RegisterAdd #(.W(SW/2+2)) preBreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_B_adder),
.Q(Q_result_B_adder)
);//*/
//multiplication for middle
KOA_1 #(.SW(SW/2+2)/*,.level(level2)*/) middle (
.Data_A_i(/*Q_result_A_adder*/result_A_adder),
.Data_B_i(/*Q_result_B_adder*/result_B_adder),
.sgf_result_o(/*result_middle_mult*/Q_middle)
);
//segmentation registers array
/*RegisterAdd #(.W(2*((SW/2)+2))) midreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_middle_mult),
.Q(Q_middle)
);//*/
///Subtractors for middle
substractor #(.W(2*(SW/2+2))) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle),
.Data_B_i({zero2, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A)
);
substractor #(.W(2*(SW/2+2))) Subtr_2 (
.Data_A_i(S_A),
.Data_B_i({zero1, /*result_right_mult//*/Q_right}),
.Data_S_o(S_B)
);
//Final adder
adder #(.W(4*(SW/2)+2)) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right}),
.Data_B_i({S_B,rightside2}),
.Data_S_o(Result[4*(SW/2)+2:0])
);
//Final Register
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_PS_TB_V
`define SKY130_FD_SC_LS__UDP_DFF_PS_TB_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__udp_dff_ps.v"
module top();
// Inputs are registered
reg D;
reg SET;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SET = 1'bX;
#20 D = 1'b0;
#40 SET = 1'b0;
#60 D = 1'b1;
#80 SET = 1'b1;
#100 D = 1'b0;
#120 SET = 1'b0;
#140 SET = 1'b1;
#160 D = 1'b1;
#180 SET = 1'bx;
#200 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__udp_dff$PS dut (.D(D), .SET(SET), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_PS_TB_V
|
module fifo # (parameter abits = 3800, dbits = 1)(
input reset, clock,
input rd, wr,
input [dbits-1:0] din,
output [dbits-1:0] dout,
output empty,
output full
//output reg ledres
);
wire db_wr, db_rd;
//reg dffw1, dffw2, dffr1, dffr2;
reg [dbits-1:0] out;
//initial ledres = 0;
//always @ (posedge clock) dffw1 <= wr;
//always @ (posedge clock) dffw2 <= dffw1;
assign db_wr = wr; //monostable multivibrator to detect only one pulse of the button
//always @ (posedge clock) dffr1 <= rd;
//always @ (posedge clock) dffr2 <= dffr1;
assign db_rd = rd; //monostable multivibrator to detect only one pulse of the button
reg [dbits-1:0] regarray[2**abits-1:0]; //number of words in fifo = 2^(number of address bits)
reg [abits-1:0] wr_reg, wr_next, wr_succ; //points to the register that needs to be written to
reg [abits-1:0] rd_reg, rd_next, rd_succ; //points to the register that needs to be read from
reg full_reg, empty_reg, full_next, empty_next;
assign wr_en = db_wr & ~full; //only write if write signal is high and fifo is not full
//always block for write operation
always @ (posedge clock)
begin
if(wr_en)
begin
regarray[wr_reg] <= din; //at wr_reg location of regarray store what is given at din
out <= regarray[rd_reg];
end
end
//always block for read operation
//always @ (posedge clock)
//begin
//if(db_rd)
//out <= regarray[rd_reg];
//end
always @ (posedge clock or posedge reset)
begin
if (reset)
begin
wr_reg <= 0;
rd_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
//ledres=0;
end
else
begin
wr_reg <= wr_next; //created the next registers to avoid the error of mixing blocking and non blocking assignment to the same signal
rd_reg <= rd_next;
full_reg <= full_next;
empty_reg <= empty_next;
//ledres=1;
end
end
always @(*)
begin
wr_succ = wr_reg + 1; //assigned to new value as wr_next cannot be tested for in same always block
rd_succ = rd_reg + 1; //assigned to new value as rd_next cannot be tested for in same always block
wr_next = wr_reg; //defaults state stays the same
rd_next = rd_reg; //defaults state stays the same
full_next = full_reg; //defaults state stays the same
empty_next = empty_reg; //defaults state stays the same
case({db_wr,db_rd})
//2'b00: do nothing LOL..
2'b01: //read
begin
if(~empty) //if fifo is not empty continue
begin
rd_next = rd_succ;
full_next = 1'b0;
if(rd_succ == wr_reg) //all data has been read
empty_next = 1'b1; //its empty again
end
end
2'b10: //write
begin
if(~full) //if fifo is not full continue
begin
wr_next = wr_succ;
empty_next = 1'b0;
if(wr_succ == (2**abits-1)) //all registers have been written to
full_next = 1'b1; //its full now
end
end
2'b11: //read and write
begin
wr_next = wr_succ;
rd_next = rd_succ;
end
//no empty or full flag will be checked for or asserted in this state since data is being written to and read from together it can not get full in this state.
endcase
end
assign full = full_reg;
assign empty = empty_reg;
assign dout = out;
endmodule
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* ---
*
* The internal logic cell simulation library.
*
* This Verilog library contains simple simulation models for the internal
* logic cells ($_NOT_ , $_AND_ , ...) that are generated by the default technology
* mapper (see "techmap.v" in this directory) and expected by the "abc" pass.
*
*/
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_BUF_ (A, Y)
//-
//- A buffer. This cell type is always optimized away by the opt_clean pass.
//-
//- Truth table: A | Y
//- ---+---
//- 0 | 0
//- 1 | 1
//-
module \$_BUF_ (A, Y);
input A;
output Y;
assign Y = A;
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_NOT_ (A, Y)
//-
//- An inverter gate.
//-
//- Truth table: A | Y
//- ---+---
//- 0 | 1
//- 1 | 0
//-
module \$_NOT_ (A, Y);
input A;
output Y;
assign Y = ~A;
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_AND_ (A, B, Y)
//-
//- A 2-input AND gate.
//-
//- Truth table: A B | Y
//- -----+---
//- 0 0 | 0
//- 0 1 | 0
//- 1 0 | 0
//- 1 1 | 1
//-
module \$_AND_ (A, B, Y);
input A, B;
output Y;
assign Y = A & B;
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_NAND_ (A, B, Y)
//-
//- A 2-input NAND gate.
//-
//- Truth table: A B | Y
//- -----+---
//- 0 0 | 1
//- 0 1 | 1
//- 1 0 | 1
//- 1 1 | 0
//-
module \$_NAND_ (A, B, Y);
input A, B;
output Y;
assign Y = ~(A & B);
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_OR_ (A, B, Y)
//-
//- A 2-input OR gate.
//-
//- Truth table: A B | Y
//- -----+---
//- 0 0 | 0
//- 0 1 | 1
//- 1 0 | 1
//- 1 1 | 1
//-
module \$_OR_ (A, B, Y);
input A, B;
output Y;
assign Y = A | B;
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_NOR_ (A, B, Y)
//-
//- A 2-input NOR gate.
//-
//- Truth table: A B | Y
//- -----+---
//- 0 0 | 1
//- 0 1 | 0
//- 1 0 | 0
//- 1 1 | 0
//-
module \$_NOR_ (A, B, Y);
input A, B;
output Y;
assign Y = ~(A | B);
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_XOR_ (A, B, Y)
//-
//- A 2-input XOR gate.
//-
//- Truth table: A B | Y
//- -----+---
//- 0 0 | 0
//- 0 1 | 1
//- 1 0 | 1
//- 1 1 | 0
//-
module \$_XOR_ (A, B, Y);
input A, B;
output Y;
assign Y = A ^ B;
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_XNOR_ (A, B, Y)
//-
//- A 2-input XNOR gate.
//-
//- Truth table: A B | Y
//- -----+---
//- 0 0 | 1
//- 0 1 | 0
//- 1 0 | 0
//- 1 1 | 1
//-
module \$_XNOR_ (A, B, Y);
input A, B;
output Y;
assign Y = ~(A ^ B);
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ANDNOT_ (A, B, Y)
//-
//- A 2-input AND-NOT gate.
//-
//- Truth table: A B | Y
//- -----+---
//- 0 0 | 0
//- 0 1 | 0
//- 1 0 | 1
//- 1 1 | 0
//-
module \$_ANDNOT_ (A, B, Y);
input A, B;
output Y;
assign Y = A & (~B);
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ORNOT_ (A, B, Y)
//-
//- A 2-input OR-NOT gate.
//-
//- Truth table: A B | Y
//- -----+---
//- 0 0 | 1
//- 0 1 | 0
//- 1 0 | 1
//- 1 1 | 1
//-
module \$_ORNOT_ (A, B, Y);
input A, B;
output Y;
assign Y = A | (~B);
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_MUX_ (A, B, S, Y)
//-
//- A 2-input MUX gate.
//-
//- Truth table: A B S | Y
//- -------+---
//- a - 0 | a
//- - b 1 | b
//-
module \$_MUX_ (A, B, S, Y);
input A, B, S;
output Y;
assign Y = S ? B : A;
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_NMUX_ (A, B, S, Y)
//-
//- A 2-input inverting MUX gate.
//-
//- Truth table: A B S | Y
//- -------+---
//- 0 - 0 | 1
//- 1 - 0 | 0
//- - 0 1 | 1
//- - 1 1 | 0
//-
module \$_NMUX_ (A, B, S, Y);
input A, B, S;
output Y;
assign Y = S ? !B : !A;
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_MUX4_ (A, B, C, D, S, T, Y)
//-
//- A 4-input MUX gate.
//-
//- Truth table: A B C D S T | Y
//- -------------+---
//- a - - - 0 0 | a
//- - b - - 1 0 | b
//- - - c - 0 1 | c
//- - - - d 1 1 | d
//-
module \$_MUX4_ (A, B, C, D, S, T, Y);
input A, B, C, D, S, T;
output Y;
assign Y = T ? (S ? D : C) :
(S ? B : A);
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y)
//-
//- An 8-input MUX gate.
//-
//- Truth table: A B C D E F G H S T U | Y
//- -----------------------+---
//- a - - - - - - - 0 0 0 | a
//- - b - - - - - - 1 0 0 | b
//- - - c - - - - - 0 1 0 | c
//- - - - d - - - - 1 1 0 | d
//- - - - - e - - - 0 0 1 | e
//- - - - - - f - - 1 0 1 | f
//- - - - - - - g - 0 1 1 | g
//- - - - - - - - h 1 1 1 | h
//-
module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
input A, B, C, D, E, F, G, H, S, T, U;
output Y;
assign Y = U ? T ? (S ? H : G) :
(S ? F : E) :
T ? (S ? D : C) :
(S ? B : A);
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y)
//-
//- A 16-input MUX gate.
//-
//- Truth table: A B C D E F G H I J K L M N O P S T U V | Y
//- -----------------------------------------+---
//- a - - - - - - - - - - - - - - - 0 0 0 0 | a
//- - b - - - - - - - - - - - - - - 1 0 0 0 | b
//- - - c - - - - - - - - - - - - - 0 1 0 0 | c
//- - - - d - - - - - - - - - - - - 1 1 0 0 | d
//- - - - - e - - - - - - - - - - - 0 0 1 0 | e
//- - - - - - f - - - - - - - - - - 1 0 1 0 | f
//- - - - - - - g - - - - - - - - - 0 1 1 0 | g
//- - - - - - - - h - - - - - - - - 1 1 1 0 | h
//- - - - - - - - - i - - - - - - - 0 0 0 1 | i
//- - - - - - - - - - j - - - - - - 1 0 0 1 | j
//- - - - - - - - - - - k - - - - - 0 1 0 1 | k
//- - - - - - - - - - - - l - - - - 1 1 0 1 | l
//- - - - - - - - - - - - - m - - - 0 0 1 1 | m
//- - - - - - - - - - - - - - n - - 1 0 1 1 | n
//- - - - - - - - - - - - - - - o - 0 1 1 1 | o
//- - - - - - - - - - - - - - - - p 1 1 1 1 | p
//-
module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
output Y;
assign Y = V ? U ? T ? (S ? P : O) :
(S ? N : M) :
T ? (S ? L : K) :
(S ? J : I) :
U ? T ? (S ? H : G) :
(S ? F : E) :
T ? (S ? D : C) :
(S ? B : A);
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_AOI3_ (A, B, C, Y)
//-
//- A 3-input And-Or-Invert gate.
//-
//- Truth table: A B C | Y
//- -------+---
//- 0 0 0 | 1
//- 0 0 1 | 0
//- 0 1 0 | 1
//- 0 1 1 | 0
//- 1 0 0 | 1
//- 1 0 1 | 0
//- 1 1 0 | 0
//- 1 1 1 | 0
//-
module \$_AOI3_ (A, B, C, Y);
input A, B, C;
output Y;
assign Y = ~((A & B) | C);
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_OAI3_ (A, B, C, Y)
//-
//- A 3-input Or-And-Invert gate.
//-
//- Truth table: A B C | Y
//- -------+---
//- 0 0 0 | 1
//- 0 0 1 | 1
//- 0 1 0 | 1
//- 0 1 1 | 0
//- 1 0 0 | 1
//- 1 0 1 | 0
//- 1 1 0 | 1
//- 1 1 1 | 0
//-
module \$_OAI3_ (A, B, C, Y);
input A, B, C;
output Y;
assign Y = ~((A | B) & C);
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_AOI4_ (A, B, C, Y)
//-
//- A 4-input And-Or-Invert gate.
//-
//- Truth table: A B C D | Y
//- ---------+---
//- 0 0 0 0 | 1
//- 0 0 0 1 | 1
//- 0 0 1 0 | 1
//- 0 0 1 1 | 0
//- 0 1 0 0 | 1
//- 0 1 0 1 | 1
//- 0 1 1 0 | 1
//- 0 1 1 1 | 0
//- 1 0 0 0 | 1
//- 1 0 0 1 | 1
//- 1 0 1 0 | 1
//- 1 0 1 1 | 0
//- 1 1 0 0 | 0
//- 1 1 0 1 | 0
//- 1 1 1 0 | 0
//- 1 1 1 1 | 0
//-
module \$_AOI4_ (A, B, C, D, Y);
input A, B, C, D;
output Y;
assign Y = ~((A & B) | (C & D));
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_OAI4_ (A, B, C, Y)
//-
//- A 4-input Or-And-Invert gate.
//-
//- Truth table: A B C D | Y
//- ---------+---
//- 0 0 0 0 | 1
//- 0 0 0 1 | 1
//- 0 0 1 0 | 1
//- 0 0 1 1 | 1
//- 0 1 0 0 | 1
//- 0 1 0 1 | 0
//- 0 1 1 0 | 0
//- 0 1 1 1 | 0
//- 1 0 0 0 | 1
//- 1 0 0 1 | 0
//- 1 0 1 0 | 0
//- 1 0 1 1 | 0
//- 1 1 0 0 | 1
//- 1 1 0 1 | 0
//- 1 1 1 0 | 0
//- 1 1 1 1 | 0
//-
module \$_OAI4_ (A, B, C, D, Y);
input A, B, C, D;
output Y;
assign Y = ~((A | B) & (C | D));
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_TBUF_ (A, E, Y)
//-
//- A tri-state buffer.
//-
//- Truth table: A E | Y
//- -----+---
//- a 1 | a
//- - 0 | z
//-
module \$_TBUF_ (A, E, Y);
input A, E;
output Y;
assign Y = E ? A : 1'bz;
endmodule
// NOTE: the following cell types are autogenerated. DO NOT EDIT them manually,
// instead edit the templates in gen_ff_types.py and rerun it.
// START AUTOGENERATED CELL TYPES
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SR_NN_ (S, R, Q)
//-
//- A set-reset latch with negative polarity SET and negative polarity RESET.
//-
//- Truth table: S R | Q
//- -----+---
//- - 0 | 0
//- 0 - | 1
//- - - | q
//-
module \$_SR_NN_ (S, R, Q);
input S, R;
output reg Q;
always @* begin
if (R == 0)
Q <= 0;
else if (S == 0)
Q <= 1;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SR_NP_ (S, R, Q)
//-
//- A set-reset latch with negative polarity SET and positive polarity RESET.
//-
//- Truth table: S R | Q
//- -----+---
//- - 1 | 0
//- 0 - | 1
//- - - | q
//-
module \$_SR_NP_ (S, R, Q);
input S, R;
output reg Q;
always @* begin
if (R == 1)
Q <= 0;
else if (S == 0)
Q <= 1;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SR_PN_ (S, R, Q)
//-
//- A set-reset latch with positive polarity SET and negative polarity RESET.
//-
//- Truth table: S R | Q
//- -----+---
//- - 0 | 0
//- 1 - | 1
//- - - | q
//-
module \$_SR_PN_ (S, R, Q);
input S, R;
output reg Q;
always @* begin
if (R == 0)
Q <= 0;
else if (S == 1)
Q <= 1;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SR_PP_ (S, R, Q)
//-
//- A set-reset latch with positive polarity SET and positive polarity RESET.
//-
//- Truth table: S R | Q
//- -----+---
//- - 1 | 0
//- 1 - | 1
//- - - | q
//-
module \$_SR_PP_ (S, R, Q);
input S, R;
output reg Q;
always @* begin
if (R == 1)
Q <= 0;
else if (S == 1)
Q <= 1;
end
endmodule
`ifdef SIMCELLS_FF
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_FF_ (D, Q)
//-
//- A D-type flip-flop that is clocked from the implicit global clock. (This cell
//- type is usually only used in netlists for formal verification.)
//-
module \$_FF_ (D, Q);
input D;
output reg Q;
always @($global_clock) begin
Q <= D;
end
endmodule
`endif
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFF_N_ (D, C, Q)
//-
//- A negative edge D-type flip-flop.
//-
//- Truth table: D C | Q
//- -----+---
//- d \ | d
//- - - | q
//-
module \$_DFF_N_ (D, C, Q);
input D, C;
output reg Q;
always @(negedge C) begin
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFF_P_ (D, C, Q)
//-
//- A positive edge D-type flip-flop.
//-
//- Truth table: D C | Q
//- -----+---
//- d / | d
//- - - | q
//-
module \$_DFF_P_ (D, C, Q);
input D, C;
output reg Q;
always @(posedge C) begin
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFE_NN_ (D, C, E, Q)
//-
//- A negative edge D-type flip-flop with negative polarity enable.
//-
//- Truth table: D C E | Q
//- -------+---
//- d \ 0 | d
//- - - - | q
//-
module \$_DFFE_NN_ (D, C, E, Q);
input D, C, E;
output reg Q;
always @(negedge C) begin
if (!E) Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFE_NP_ (D, C, E, Q)
//-
//- A negative edge D-type flip-flop with positive polarity enable.
//-
//- Truth table: D C E | Q
//- -------+---
//- d \ 1 | d
//- - - - | q
//-
module \$_DFFE_NP_ (D, C, E, Q);
input D, C, E;
output reg Q;
always @(negedge C) begin
if (E) Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFE_PN_ (D, C, E, Q)
//-
//- A positive edge D-type flip-flop with negative polarity enable.
//-
//- Truth table: D C E | Q
//- -------+---
//- d / 0 | d
//- - - - | q
//-
module \$_DFFE_PN_ (D, C, E, Q);
input D, C, E;
output reg Q;
always @(posedge C) begin
if (!E) Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFE_PP_ (D, C, E, Q)
//-
//- A positive edge D-type flip-flop with positive polarity enable.
//-
//- Truth table: D C E | Q
//- -------+---
//- d / 1 | d
//- - - - | q
//-
module \$_DFFE_PP_ (D, C, E, Q);
input D, C, E;
output reg Q;
always @(posedge C) begin
if (E) Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFF_NN0_ (D, C, R, Q)
//-
//- A negative edge D-type flip-flop with negative polarity reset.
//-
//- Truth table: D C R | Q
//- -------+---
//- - - 0 | 0
//- d \ - | d
//- - - - | q
//-
module \$_DFF_NN0_ (D, C, R, Q);
input D, C, R;
output reg Q;
always @(negedge C or negedge R) begin
if (R == 0)
Q <= 0;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFF_NN1_ (D, C, R, Q)
//-
//- A negative edge D-type flip-flop with negative polarity set.
//-
//- Truth table: D C R | Q
//- -------+---
//- - - 0 | 1
//- d \ - | d
//- - - - | q
//-
module \$_DFF_NN1_ (D, C, R, Q);
input D, C, R;
output reg Q;
always @(negedge C or negedge R) begin
if (R == 0)
Q <= 1;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFF_NP0_ (D, C, R, Q)
//-
//- A negative edge D-type flip-flop with positive polarity reset.
//-
//- Truth table: D C R | Q
//- -------+---
//- - - 1 | 0
//- d \ - | d
//- - - - | q
//-
module \$_DFF_NP0_ (D, C, R, Q);
input D, C, R;
output reg Q;
always @(negedge C or posedge R) begin
if (R == 1)
Q <= 0;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFF_NP1_ (D, C, R, Q)
//-
//- A negative edge D-type flip-flop with positive polarity set.
//-
//- Truth table: D C R | Q
//- -------+---
//- - - 1 | 1
//- d \ - | d
//- - - - | q
//-
module \$_DFF_NP1_ (D, C, R, Q);
input D, C, R;
output reg Q;
always @(negedge C or posedge R) begin
if (R == 1)
Q <= 1;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFF_PN0_ (D, C, R, Q)
//-
//- A positive edge D-type flip-flop with negative polarity reset.
//-
//- Truth table: D C R | Q
//- -------+---
//- - - 0 | 0
//- d / - | d
//- - - - | q
//-
module \$_DFF_PN0_ (D, C, R, Q);
input D, C, R;
output reg Q;
always @(posedge C or negedge R) begin
if (R == 0)
Q <= 0;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFF_PN1_ (D, C, R, Q)
//-
//- A positive edge D-type flip-flop with negative polarity set.
//-
//- Truth table: D C R | Q
//- -------+---
//- - - 0 | 1
//- d / - | d
//- - - - | q
//-
module \$_DFF_PN1_ (D, C, R, Q);
input D, C, R;
output reg Q;
always @(posedge C or negedge R) begin
if (R == 0)
Q <= 1;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFF_PP0_ (D, C, R, Q)
//-
//- A positive edge D-type flip-flop with positive polarity reset.
//-
//- Truth table: D C R | Q
//- -------+---
//- - - 1 | 0
//- d / - | d
//- - - - | q
//-
module \$_DFF_PP0_ (D, C, R, Q);
input D, C, R;
output reg Q;
always @(posedge C or posedge R) begin
if (R == 1)
Q <= 0;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFF_PP1_ (D, C, R, Q)
//-
//- A positive edge D-type flip-flop with positive polarity set.
//-
//- Truth table: D C R | Q
//- -------+---
//- - - 1 | 1
//- d / - | d
//- - - - | q
//-
module \$_DFF_PP1_ (D, C, R, Q);
input D, C, R;
output reg Q;
always @(posedge C or posedge R) begin
if (R == 1)
Q <= 1;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFE_NN0N_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with negative polarity reset and negative
//- polarity clock enable.
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - - 0 - | 0
//- d \ - 0 | d
//- - - - - | q
//-
module \$_DFFE_NN0N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C or negedge R) begin
if (R == 0)
Q <= 0;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFE_NN0P_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with negative polarity reset and positive
//- polarity clock enable.
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - - 0 - | 0
//- d \ - 1 | d
//- - - - - | q
//-
module \$_DFFE_NN0P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C or negedge R) begin
if (R == 0)
Q <= 0;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFE_NN1N_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with negative polarity set and negative
//- polarity clock enable.
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - - 0 - | 1
//- d \ - 0 | d
//- - - - - | q
//-
module \$_DFFE_NN1N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C or negedge R) begin
if (R == 0)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFE_NN1P_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with negative polarity set and positive
//- polarity clock enable.
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - - 0 - | 1
//- d \ - 1 | d
//- - - - - | q
//-
module \$_DFFE_NN1P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C or negedge R) begin
if (R == 0)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFE_NP0N_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with positive polarity reset and negative
//- polarity clock enable.
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - - 1 - | 0
//- d \ - 0 | d
//- - - - - | q
//-
module \$_DFFE_NP0N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C or posedge R) begin
if (R == 1)
Q <= 0;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFE_NP0P_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with positive polarity reset and positive
//- polarity clock enable.
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - - 1 - | 0
//- d \ - 1 | d
//- - - - - | q
//-
module \$_DFFE_NP0P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C or posedge R) begin
if (R == 1)
Q <= 0;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFE_NP1N_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with positive polarity set and negative
//- polarity clock enable.
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - - 1 - | 1
//- d \ - 0 | d
//- - - - - | q
//-
module \$_DFFE_NP1N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C or posedge R) begin
if (R == 1)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFE_NP1P_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with positive polarity set and positive
//- polarity clock enable.
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - - 1 - | 1
//- d \ - 1 | d
//- - - - - | q
//-
module \$_DFFE_NP1P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C or posedge R) begin
if (R == 1)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFE_PN0N_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with negative polarity reset and negative
//- polarity clock enable.
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - - 0 - | 0
//- d / - 0 | d
//- - - - - | q
//-
module \$_DFFE_PN0N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C or negedge R) begin
if (R == 0)
Q <= 0;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFE_PN0P_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with negative polarity reset and positive
//- polarity clock enable.
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - - 0 - | 0
//- d / - 1 | d
//- - - - - | q
//-
module \$_DFFE_PN0P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C or negedge R) begin
if (R == 0)
Q <= 0;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFE_PN1N_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with negative polarity set and negative
//- polarity clock enable.
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - - 0 - | 1
//- d / - 0 | d
//- - - - - | q
//-
module \$_DFFE_PN1N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C or negedge R) begin
if (R == 0)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFE_PN1P_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with negative polarity set and positive
//- polarity clock enable.
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - - 0 - | 1
//- d / - 1 | d
//- - - - - | q
//-
module \$_DFFE_PN1P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C or negedge R) begin
if (R == 0)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFE_PP0N_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with positive polarity reset and negative
//- polarity clock enable.
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - - 1 - | 0
//- d / - 0 | d
//- - - - - | q
//-
module \$_DFFE_PP0N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C or posedge R) begin
if (R == 1)
Q <= 0;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFE_PP0P_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with positive polarity reset and positive
//- polarity clock enable.
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - - 1 - | 0
//- d / - 1 | d
//- - - - - | q
//-
module \$_DFFE_PP0P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C or posedge R) begin
if (R == 1)
Q <= 0;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFE_PP1N_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with positive polarity set and negative
//- polarity clock enable.
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - - 1 - | 1
//- d / - 0 | d
//- - - - - | q
//-
module \$_DFFE_PP1N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C or posedge R) begin
if (R == 1)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFE_PP1P_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with positive polarity set and positive
//- polarity clock enable.
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - - 1 - | 1
//- d / - 1 | d
//- - - - - | q
//-
module \$_DFFE_PP1P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C or posedge R) begin
if (R == 1)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFF_NN_ (D, C, L, AD, Q)
//-
//- A negative edge D-type flip-flop with negative polarity async load.
//-
//- Truth table: D C L AD | Q
//- ----------+---
//- - - 0 a | a
//- d \ - - | d
//- - - - - | q
//-
module \$_ALDFF_NN_ (D, C, L, AD, Q);
input D, C, L, AD;
output reg Q;
always @(negedge C or negedge L) begin
if (L == 0)
Q <= AD;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFF_NP_ (D, C, L, AD, Q)
//-
//- A negative edge D-type flip-flop with positive polarity async load.
//-
//- Truth table: D C L AD | Q
//- ----------+---
//- - - 1 a | a
//- d \ - - | d
//- - - - - | q
//-
module \$_ALDFF_NP_ (D, C, L, AD, Q);
input D, C, L, AD;
output reg Q;
always @(negedge C or posedge L) begin
if (L == 1)
Q <= AD;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFF_PN_ (D, C, L, AD, Q)
//-
//- A positive edge D-type flip-flop with negative polarity async load.
//-
//- Truth table: D C L AD | Q
//- ----------+---
//- - - 0 a | a
//- d / - - | d
//- - - - - | q
//-
module \$_ALDFF_PN_ (D, C, L, AD, Q);
input D, C, L, AD;
output reg Q;
always @(posedge C or negedge L) begin
if (L == 0)
Q <= AD;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFF_PP_ (D, C, L, AD, Q)
//-
//- A positive edge D-type flip-flop with positive polarity async load.
//-
//- Truth table: D C L AD | Q
//- ----------+---
//- - - 1 a | a
//- d / - - | d
//- - - - - | q
//-
module \$_ALDFF_PP_ (D, C, L, AD, Q);
input D, C, L, AD;
output reg Q;
always @(posedge C or posedge L) begin
if (L == 1)
Q <= AD;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFFE_NNN_ (D, C, L, AD, E, Q)
//-
//- A negative edge D-type flip-flop with negative polarity async load and negative
//- polarity clock enable.
//-
//- Truth table: D C L AD E | Q
//- ------------+---
//- - - 0 a - | a
//- d \ - - 0 | d
//- - - - - - | q
//-
module \$_ALDFFE_NNN_ (D, C, L, AD, E, Q);
input D, C, L, AD, E;
output reg Q;
always @(negedge C or negedge L) begin
if (L == 0)
Q <= AD;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFFE_NNP_ (D, C, L, AD, E, Q)
//-
//- A negative edge D-type flip-flop with negative polarity async load and positive
//- polarity clock enable.
//-
//- Truth table: D C L AD E | Q
//- ------------+---
//- - - 0 a - | a
//- d \ - - 1 | d
//- - - - - - | q
//-
module \$_ALDFFE_NNP_ (D, C, L, AD, E, Q);
input D, C, L, AD, E;
output reg Q;
always @(negedge C or negedge L) begin
if (L == 0)
Q <= AD;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFFE_NPN_ (D, C, L, AD, E, Q)
//-
//- A negative edge D-type flip-flop with positive polarity async load and negative
//- polarity clock enable.
//-
//- Truth table: D C L AD E | Q
//- ------------+---
//- - - 1 a - | a
//- d \ - - 0 | d
//- - - - - - | q
//-
module \$_ALDFFE_NPN_ (D, C, L, AD, E, Q);
input D, C, L, AD, E;
output reg Q;
always @(negedge C or posedge L) begin
if (L == 1)
Q <= AD;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFFE_NPP_ (D, C, L, AD, E, Q)
//-
//- A negative edge D-type flip-flop with positive polarity async load and positive
//- polarity clock enable.
//-
//- Truth table: D C L AD E | Q
//- ------------+---
//- - - 1 a - | a
//- d \ - - 1 | d
//- - - - - - | q
//-
module \$_ALDFFE_NPP_ (D, C, L, AD, E, Q);
input D, C, L, AD, E;
output reg Q;
always @(negedge C or posedge L) begin
if (L == 1)
Q <= AD;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFFE_PNN_ (D, C, L, AD, E, Q)
//-
//- A positive edge D-type flip-flop with negative polarity async load and negative
//- polarity clock enable.
//-
//- Truth table: D C L AD E | Q
//- ------------+---
//- - - 0 a - | a
//- d / - - 0 | d
//- - - - - - | q
//-
module \$_ALDFFE_PNN_ (D, C, L, AD, E, Q);
input D, C, L, AD, E;
output reg Q;
always @(posedge C or negedge L) begin
if (L == 0)
Q <= AD;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFFE_PNP_ (D, C, L, AD, E, Q)
//-
//- A positive edge D-type flip-flop with negative polarity async load and positive
//- polarity clock enable.
//-
//- Truth table: D C L AD E | Q
//- ------------+---
//- - - 0 a - | a
//- d / - - 1 | d
//- - - - - - | q
//-
module \$_ALDFFE_PNP_ (D, C, L, AD, E, Q);
input D, C, L, AD, E;
output reg Q;
always @(posedge C or negedge L) begin
if (L == 0)
Q <= AD;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFFE_PPN_ (D, C, L, AD, E, Q)
//-
//- A positive edge D-type flip-flop with positive polarity async load and negative
//- polarity clock enable.
//-
//- Truth table: D C L AD E | Q
//- ------------+---
//- - - 1 a - | a
//- d / - - 0 | d
//- - - - - - | q
//-
module \$_ALDFFE_PPN_ (D, C, L, AD, E, Q);
input D, C, L, AD, E;
output reg Q;
always @(posedge C or posedge L) begin
if (L == 1)
Q <= AD;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_ALDFFE_PPP_ (D, C, L, AD, E, Q)
//-
//- A positive edge D-type flip-flop with positive polarity async load and positive
//- polarity clock enable.
//-
//- Truth table: D C L AD E | Q
//- ------------+---
//- - - 1 a - | a
//- d / - - 1 | d
//- - - - - - | q
//-
module \$_ALDFFE_PPP_ (D, C, L, AD, E, Q);
input D, C, L, AD, E;
output reg Q;
always @(posedge C or posedge L) begin
if (L == 1)
Q <= AD;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSR_NNN_ (C, S, R, D, Q)
//-
//- A negative edge D-type flip-flop with negative polarity set and negative
//- polarity reset.
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - - 0 - | 0
//- - 0 - - | 1
//- \ - - d | d
//- - - - - | q
//-
module \$_DFFSR_NNN_ (C, S, R, D, Q);
input C, S, R, D;
output reg Q;
always @(negedge C, negedge S, negedge R) begin
if (R == 0)
Q <= 0;
else if (S == 0)
Q <= 1;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSR_NNP_ (C, S, R, D, Q)
//-
//- A negative edge D-type flip-flop with negative polarity set and positive
//- polarity reset.
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - - 1 - | 0
//- - 0 - - | 1
//- \ - - d | d
//- - - - - | q
//-
module \$_DFFSR_NNP_ (C, S, R, D, Q);
input C, S, R, D;
output reg Q;
always @(negedge C, negedge S, posedge R) begin
if (R == 1)
Q <= 0;
else if (S == 0)
Q <= 1;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSR_NPN_ (C, S, R, D, Q)
//-
//- A negative edge D-type flip-flop with positive polarity set and negative
//- polarity reset.
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - - 0 - | 0
//- - 1 - - | 1
//- \ - - d | d
//- - - - - | q
//-
module \$_DFFSR_NPN_ (C, S, R, D, Q);
input C, S, R, D;
output reg Q;
always @(negedge C, posedge S, negedge R) begin
if (R == 0)
Q <= 0;
else if (S == 1)
Q <= 1;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSR_NPP_ (C, S, R, D, Q)
//-
//- A negative edge D-type flip-flop with positive polarity set and positive
//- polarity reset.
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - - 1 - | 0
//- - 1 - - | 1
//- \ - - d | d
//- - - - - | q
//-
module \$_DFFSR_NPP_ (C, S, R, D, Q);
input C, S, R, D;
output reg Q;
always @(negedge C, posedge S, posedge R) begin
if (R == 1)
Q <= 0;
else if (S == 1)
Q <= 1;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSR_PNN_ (C, S, R, D, Q)
//-
//- A positive edge D-type flip-flop with negative polarity set and negative
//- polarity reset.
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - - 0 - | 0
//- - 0 - - | 1
//- / - - d | d
//- - - - - | q
//-
module \$_DFFSR_PNN_ (C, S, R, D, Q);
input C, S, R, D;
output reg Q;
always @(posedge C, negedge S, negedge R) begin
if (R == 0)
Q <= 0;
else if (S == 0)
Q <= 1;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSR_PNP_ (C, S, R, D, Q)
//-
//- A positive edge D-type flip-flop with negative polarity set and positive
//- polarity reset.
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - - 1 - | 0
//- - 0 - - | 1
//- / - - d | d
//- - - - - | q
//-
module \$_DFFSR_PNP_ (C, S, R, D, Q);
input C, S, R, D;
output reg Q;
always @(posedge C, negedge S, posedge R) begin
if (R == 1)
Q <= 0;
else if (S == 0)
Q <= 1;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSR_PPN_ (C, S, R, D, Q)
//-
//- A positive edge D-type flip-flop with positive polarity set and negative
//- polarity reset.
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - - 0 - | 0
//- - 1 - - | 1
//- / - - d | d
//- - - - - | q
//-
module \$_DFFSR_PPN_ (C, S, R, D, Q);
input C, S, R, D;
output reg Q;
always @(posedge C, posedge S, negedge R) begin
if (R == 0)
Q <= 0;
else if (S == 1)
Q <= 1;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSR_PPP_ (C, S, R, D, Q)
//-
//- A positive edge D-type flip-flop with positive polarity set and positive
//- polarity reset.
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - - 1 - | 0
//- - 1 - - | 1
//- / - - d | d
//- - - - - | q
//-
module \$_DFFSR_PPP_ (C, S, R, D, Q);
input C, S, R, D;
output reg Q;
always @(posedge C, posedge S, posedge R) begin
if (R == 1)
Q <= 0;
else if (S == 1)
Q <= 1;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSRE_NNNN_ (C, S, R, E, D, Q)
//-
//- A negative edge D-type flip-flop with negative polarity set, negative
//- polarity reset and negative polarity clock enable.
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - - 0 - - | 0
//- - 0 - - - | 1
//- \ - - 0 d | d
//- - - - - - | q
//-
module \$_DFFSRE_NNNN_ (C, S, R, E, D, Q);
input C, S, R, E, D;
output reg Q;
always @(negedge C, negedge S, negedge R) begin
if (R == 0)
Q <= 0;
else if (S == 0)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSRE_NNNP_ (C, S, R, E, D, Q)
//-
//- A negative edge D-type flip-flop with negative polarity set, negative
//- polarity reset and positive polarity clock enable.
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - - 0 - - | 0
//- - 0 - - - | 1
//- \ - - 1 d | d
//- - - - - - | q
//-
module \$_DFFSRE_NNNP_ (C, S, R, E, D, Q);
input C, S, R, E, D;
output reg Q;
always @(negedge C, negedge S, negedge R) begin
if (R == 0)
Q <= 0;
else if (S == 0)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSRE_NNPN_ (C, S, R, E, D, Q)
//-
//- A negative edge D-type flip-flop with negative polarity set, positive
//- polarity reset and negative polarity clock enable.
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - - 1 - - | 0
//- - 0 - - - | 1
//- \ - - 0 d | d
//- - - - - - | q
//-
module \$_DFFSRE_NNPN_ (C, S, R, E, D, Q);
input C, S, R, E, D;
output reg Q;
always @(negedge C, negedge S, posedge R) begin
if (R == 1)
Q <= 0;
else if (S == 0)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSRE_NNPP_ (C, S, R, E, D, Q)
//-
//- A negative edge D-type flip-flop with negative polarity set, positive
//- polarity reset and positive polarity clock enable.
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - - 1 - - | 0
//- - 0 - - - | 1
//- \ - - 1 d | d
//- - - - - - | q
//-
module \$_DFFSRE_NNPP_ (C, S, R, E, D, Q);
input C, S, R, E, D;
output reg Q;
always @(negedge C, negedge S, posedge R) begin
if (R == 1)
Q <= 0;
else if (S == 0)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSRE_NPNN_ (C, S, R, E, D, Q)
//-
//- A negative edge D-type flip-flop with positive polarity set, negative
//- polarity reset and negative polarity clock enable.
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - - 0 - - | 0
//- - 1 - - - | 1
//- \ - - 0 d | d
//- - - - - - | q
//-
module \$_DFFSRE_NPNN_ (C, S, R, E, D, Q);
input C, S, R, E, D;
output reg Q;
always @(negedge C, posedge S, negedge R) begin
if (R == 0)
Q <= 0;
else if (S == 1)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSRE_NPNP_ (C, S, R, E, D, Q)
//-
//- A negative edge D-type flip-flop with positive polarity set, negative
//- polarity reset and positive polarity clock enable.
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - - 0 - - | 0
//- - 1 - - - | 1
//- \ - - 1 d | d
//- - - - - - | q
//-
module \$_DFFSRE_NPNP_ (C, S, R, E, D, Q);
input C, S, R, E, D;
output reg Q;
always @(negedge C, posedge S, negedge R) begin
if (R == 0)
Q <= 0;
else if (S == 1)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSRE_NPPN_ (C, S, R, E, D, Q)
//-
//- A negative edge D-type flip-flop with positive polarity set, positive
//- polarity reset and negative polarity clock enable.
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - - 1 - - | 0
//- - 1 - - - | 1
//- \ - - 0 d | d
//- - - - - - | q
//-
module \$_DFFSRE_NPPN_ (C, S, R, E, D, Q);
input C, S, R, E, D;
output reg Q;
always @(negedge C, posedge S, posedge R) begin
if (R == 1)
Q <= 0;
else if (S == 1)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSRE_NPPP_ (C, S, R, E, D, Q)
//-
//- A negative edge D-type flip-flop with positive polarity set, positive
//- polarity reset and positive polarity clock enable.
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - - 1 - - | 0
//- - 1 - - - | 1
//- \ - - 1 d | d
//- - - - - - | q
//-
module \$_DFFSRE_NPPP_ (C, S, R, E, D, Q);
input C, S, R, E, D;
output reg Q;
always @(negedge C, posedge S, posedge R) begin
if (R == 1)
Q <= 0;
else if (S == 1)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSRE_PNNN_ (C, S, R, E, D, Q)
//-
//- A positive edge D-type flip-flop with negative polarity set, negative
//- polarity reset and negative polarity clock enable.
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - - 0 - - | 0
//- - 0 - - - | 1
//- / - - 0 d | d
//- - - - - - | q
//-
module \$_DFFSRE_PNNN_ (C, S, R, E, D, Q);
input C, S, R, E, D;
output reg Q;
always @(posedge C, negedge S, negedge R) begin
if (R == 0)
Q <= 0;
else if (S == 0)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSRE_PNNP_ (C, S, R, E, D, Q)
//-
//- A positive edge D-type flip-flop with negative polarity set, negative
//- polarity reset and positive polarity clock enable.
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - - 0 - - | 0
//- - 0 - - - | 1
//- / - - 1 d | d
//- - - - - - | q
//-
module \$_DFFSRE_PNNP_ (C, S, R, E, D, Q);
input C, S, R, E, D;
output reg Q;
always @(posedge C, negedge S, negedge R) begin
if (R == 0)
Q <= 0;
else if (S == 0)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSRE_PNPN_ (C, S, R, E, D, Q)
//-
//- A positive edge D-type flip-flop with negative polarity set, positive
//- polarity reset and negative polarity clock enable.
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - - 1 - - | 0
//- - 0 - - - | 1
//- / - - 0 d | d
//- - - - - - | q
//-
module \$_DFFSRE_PNPN_ (C, S, R, E, D, Q);
input C, S, R, E, D;
output reg Q;
always @(posedge C, negedge S, posedge R) begin
if (R == 1)
Q <= 0;
else if (S == 0)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSRE_PNPP_ (C, S, R, E, D, Q)
//-
//- A positive edge D-type flip-flop with negative polarity set, positive
//- polarity reset and positive polarity clock enable.
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - - 1 - - | 0
//- - 0 - - - | 1
//- / - - 1 d | d
//- - - - - - | q
//-
module \$_DFFSRE_PNPP_ (C, S, R, E, D, Q);
input C, S, R, E, D;
output reg Q;
always @(posedge C, negedge S, posedge R) begin
if (R == 1)
Q <= 0;
else if (S == 0)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSRE_PPNN_ (C, S, R, E, D, Q)
//-
//- A positive edge D-type flip-flop with positive polarity set, negative
//- polarity reset and negative polarity clock enable.
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - - 0 - - | 0
//- - 1 - - - | 1
//- / - - 0 d | d
//- - - - - - | q
//-
module \$_DFFSRE_PPNN_ (C, S, R, E, D, Q);
input C, S, R, E, D;
output reg Q;
always @(posedge C, posedge S, negedge R) begin
if (R == 0)
Q <= 0;
else if (S == 1)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSRE_PPNP_ (C, S, R, E, D, Q)
//-
//- A positive edge D-type flip-flop with positive polarity set, negative
//- polarity reset and positive polarity clock enable.
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - - 0 - - | 0
//- - 1 - - - | 1
//- / - - 1 d | d
//- - - - - - | q
//-
module \$_DFFSRE_PPNP_ (C, S, R, E, D, Q);
input C, S, R, E, D;
output reg Q;
always @(posedge C, posedge S, negedge R) begin
if (R == 0)
Q <= 0;
else if (S == 1)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSRE_PPPN_ (C, S, R, E, D, Q)
//-
//- A positive edge D-type flip-flop with positive polarity set, positive
//- polarity reset and negative polarity clock enable.
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - - 1 - - | 0
//- - 1 - - - | 1
//- / - - 0 d | d
//- - - - - - | q
//-
module \$_DFFSRE_PPPN_ (C, S, R, E, D, Q);
input C, S, R, E, D;
output reg Q;
always @(posedge C, posedge S, posedge R) begin
if (R == 1)
Q <= 0;
else if (S == 1)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSRE_PPPP_ (C, S, R, E, D, Q)
//-
//- A positive edge D-type flip-flop with positive polarity set, positive
//- polarity reset and positive polarity clock enable.
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - - 1 - - | 0
//- - 1 - - - | 1
//- / - - 1 d | d
//- - - - - - | q
//-
module \$_DFFSRE_PPPP_ (C, S, R, E, D, Q);
input C, S, R, E, D;
output reg Q;
always @(posedge C, posedge S, posedge R) begin
if (R == 1)
Q <= 0;
else if (S == 1)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFF_NN0_ (D, C, R, Q)
//-
//- A negative edge D-type flip-flop with negative polarity synchronous reset.
//-
//- Truth table: D C R | Q
//- -------+---
//- - \ 0 | 0
//- d \ - | d
//- - - - | q
//-
module \$_SDFF_NN0_ (D, C, R, Q);
input D, C, R;
output reg Q;
always @(negedge C) begin
if (R == 0)
Q <= 0;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFF_NN1_ (D, C, R, Q)
//-
//- A negative edge D-type flip-flop with negative polarity synchronous set.
//-
//- Truth table: D C R | Q
//- -------+---
//- - \ 0 | 1
//- d \ - | d
//- - - - | q
//-
module \$_SDFF_NN1_ (D, C, R, Q);
input D, C, R;
output reg Q;
always @(negedge C) begin
if (R == 0)
Q <= 1;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFF_NP0_ (D, C, R, Q)
//-
//- A negative edge D-type flip-flop with positive polarity synchronous reset.
//-
//- Truth table: D C R | Q
//- -------+---
//- - \ 1 | 0
//- d \ - | d
//- - - - | q
//-
module \$_SDFF_NP0_ (D, C, R, Q);
input D, C, R;
output reg Q;
always @(negedge C) begin
if (R == 1)
Q <= 0;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFF_NP1_ (D, C, R, Q)
//-
//- A negative edge D-type flip-flop with positive polarity synchronous set.
//-
//- Truth table: D C R | Q
//- -------+---
//- - \ 1 | 1
//- d \ - | d
//- - - - | q
//-
module \$_SDFF_NP1_ (D, C, R, Q);
input D, C, R;
output reg Q;
always @(negedge C) begin
if (R == 1)
Q <= 1;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFF_PN0_ (D, C, R, Q)
//-
//- A positive edge D-type flip-flop with negative polarity synchronous reset.
//-
//- Truth table: D C R | Q
//- -------+---
//- - / 0 | 0
//- d / - | d
//- - - - | q
//-
module \$_SDFF_PN0_ (D, C, R, Q);
input D, C, R;
output reg Q;
always @(posedge C) begin
if (R == 0)
Q <= 0;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFF_PN1_ (D, C, R, Q)
//-
//- A positive edge D-type flip-flop with negative polarity synchronous set.
//-
//- Truth table: D C R | Q
//- -------+---
//- - / 0 | 1
//- d / - | d
//- - - - | q
//-
module \$_SDFF_PN1_ (D, C, R, Q);
input D, C, R;
output reg Q;
always @(posedge C) begin
if (R == 0)
Q <= 1;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFF_PP0_ (D, C, R, Q)
//-
//- A positive edge D-type flip-flop with positive polarity synchronous reset.
//-
//- Truth table: D C R | Q
//- -------+---
//- - / 1 | 0
//- d / - | d
//- - - - | q
//-
module \$_SDFF_PP0_ (D, C, R, Q);
input D, C, R;
output reg Q;
always @(posedge C) begin
if (R == 1)
Q <= 0;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFF_PP1_ (D, C, R, Q)
//-
//- A positive edge D-type flip-flop with positive polarity synchronous set.
//-
//- Truth table: D C R | Q
//- -------+---
//- - / 1 | 1
//- d / - | d
//- - - - | q
//-
module \$_SDFF_PP1_ (D, C, R, Q);
input D, C, R;
output reg Q;
always @(posedge C) begin
if (R == 1)
Q <= 1;
else
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFE_NN0N_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with negative polarity synchronous reset and negative
//- polarity clock enable (with reset having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - \ 0 - | 0
//- d \ - 0 | d
//- - - - - | q
//-
module \$_SDFFE_NN0N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C) begin
if (R == 0)
Q <= 0;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFE_NN0P_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with negative polarity synchronous reset and positive
//- polarity clock enable (with reset having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - \ 0 - | 0
//- d \ - 1 | d
//- - - - - | q
//-
module \$_SDFFE_NN0P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C) begin
if (R == 0)
Q <= 0;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFE_NN1N_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with negative polarity synchronous set and negative
//- polarity clock enable (with set having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - \ 0 - | 1
//- d \ - 0 | d
//- - - - - | q
//-
module \$_SDFFE_NN1N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C) begin
if (R == 0)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFE_NN1P_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with negative polarity synchronous set and positive
//- polarity clock enable (with set having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - \ 0 - | 1
//- d \ - 1 | d
//- - - - - | q
//-
module \$_SDFFE_NN1P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C) begin
if (R == 0)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFE_NP0N_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with positive polarity synchronous reset and negative
//- polarity clock enable (with reset having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - \ 1 - | 0
//- d \ - 0 | d
//- - - - - | q
//-
module \$_SDFFE_NP0N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C) begin
if (R == 1)
Q <= 0;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFE_NP0P_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with positive polarity synchronous reset and positive
//- polarity clock enable (with reset having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - \ 1 - | 0
//- d \ - 1 | d
//- - - - - | q
//-
module \$_SDFFE_NP0P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C) begin
if (R == 1)
Q <= 0;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFE_NP1N_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with positive polarity synchronous set and negative
//- polarity clock enable (with set having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - \ 1 - | 1
//- d \ - 0 | d
//- - - - - | q
//-
module \$_SDFFE_NP1N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C) begin
if (R == 1)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFE_NP1P_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with positive polarity synchronous set and positive
//- polarity clock enable (with set having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - \ 1 - | 1
//- d \ - 1 | d
//- - - - - | q
//-
module \$_SDFFE_NP1P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C) begin
if (R == 1)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFE_PN0N_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with negative polarity synchronous reset and negative
//- polarity clock enable (with reset having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - / 0 - | 0
//- d / - 0 | d
//- - - - - | q
//-
module \$_SDFFE_PN0N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C) begin
if (R == 0)
Q <= 0;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFE_PN0P_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with negative polarity synchronous reset and positive
//- polarity clock enable (with reset having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - / 0 - | 0
//- d / - 1 | d
//- - - - - | q
//-
module \$_SDFFE_PN0P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C) begin
if (R == 0)
Q <= 0;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFE_PN1N_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with negative polarity synchronous set and negative
//- polarity clock enable (with set having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - / 0 - | 1
//- d / - 0 | d
//- - - - - | q
//-
module \$_SDFFE_PN1N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C) begin
if (R == 0)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFE_PN1P_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with negative polarity synchronous set and positive
//- polarity clock enable (with set having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - / 0 - | 1
//- d / - 1 | d
//- - - - - | q
//-
module \$_SDFFE_PN1P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C) begin
if (R == 0)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFE_PP0N_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with positive polarity synchronous reset and negative
//- polarity clock enable (with reset having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - / 1 - | 0
//- d / - 0 | d
//- - - - - | q
//-
module \$_SDFFE_PP0N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C) begin
if (R == 1)
Q <= 0;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFE_PP0P_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with positive polarity synchronous reset and positive
//- polarity clock enable (with reset having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - / 1 - | 0
//- d / - 1 | d
//- - - - - | q
//-
module \$_SDFFE_PP0P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C) begin
if (R == 1)
Q <= 0;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFE_PP1N_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with positive polarity synchronous set and negative
//- polarity clock enable (with set having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - / 1 - | 1
//- d / - 0 | d
//- - - - - | q
//-
module \$_SDFFE_PP1N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C) begin
if (R == 1)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFE_PP1P_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with positive polarity synchronous set and positive
//- polarity clock enable (with set having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - / 1 - | 1
//- d / - 1 | d
//- - - - - | q
//-
module \$_SDFFE_PP1P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C) begin
if (R == 1)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFCE_NN0N_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with negative polarity synchronous reset and negative
//- polarity clock enable (with clock enable having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - \ 0 0 | 0
//- d \ - 0 | d
//- - - - - | q
//-
module \$_SDFFCE_NN0N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C) begin
if (E == 0) begin
if (R == 0)
Q <= 0;
else
Q <= D;
end
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFCE_NN0P_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with negative polarity synchronous reset and positive
//- polarity clock enable (with clock enable having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - \ 0 1 | 0
//- d \ - 1 | d
//- - - - - | q
//-
module \$_SDFFCE_NN0P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C) begin
if (E == 1) begin
if (R == 0)
Q <= 0;
else
Q <= D;
end
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFCE_NN1N_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with negative polarity synchronous set and negative
//- polarity clock enable (with clock enable having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - \ 0 0 | 1
//- d \ - 0 | d
//- - - - - | q
//-
module \$_SDFFCE_NN1N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C) begin
if (E == 0) begin
if (R == 0)
Q <= 1;
else
Q <= D;
end
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFCE_NN1P_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with negative polarity synchronous set and positive
//- polarity clock enable (with clock enable having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - \ 0 1 | 1
//- d \ - 1 | d
//- - - - - | q
//-
module \$_SDFFCE_NN1P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C) begin
if (E == 1) begin
if (R == 0)
Q <= 1;
else
Q <= D;
end
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFCE_NP0N_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with positive polarity synchronous reset and negative
//- polarity clock enable (with clock enable having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - \ 1 0 | 0
//- d \ - 0 | d
//- - - - - | q
//-
module \$_SDFFCE_NP0N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C) begin
if (E == 0) begin
if (R == 1)
Q <= 0;
else
Q <= D;
end
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFCE_NP0P_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with positive polarity synchronous reset and positive
//- polarity clock enable (with clock enable having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - \ 1 1 | 0
//- d \ - 1 | d
//- - - - - | q
//-
module \$_SDFFCE_NP0P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C) begin
if (E == 1) begin
if (R == 1)
Q <= 0;
else
Q <= D;
end
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFCE_NP1N_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with positive polarity synchronous set and negative
//- polarity clock enable (with clock enable having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - \ 1 0 | 1
//- d \ - 0 | d
//- - - - - | q
//-
module \$_SDFFCE_NP1N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C) begin
if (E == 0) begin
if (R == 1)
Q <= 1;
else
Q <= D;
end
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFCE_NP1P_ (D, C, R, E, Q)
//-
//- A negative edge D-type flip-flop with positive polarity synchronous set and positive
//- polarity clock enable (with clock enable having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - \ 1 1 | 1
//- d \ - 1 | d
//- - - - - | q
//-
module \$_SDFFCE_NP1P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(negedge C) begin
if (E == 1) begin
if (R == 1)
Q <= 1;
else
Q <= D;
end
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFCE_PN0N_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with negative polarity synchronous reset and negative
//- polarity clock enable (with clock enable having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - / 0 0 | 0
//- d / - 0 | d
//- - - - - | q
//-
module \$_SDFFCE_PN0N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C) begin
if (E == 0) begin
if (R == 0)
Q <= 0;
else
Q <= D;
end
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFCE_PN0P_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with negative polarity synchronous reset and positive
//- polarity clock enable (with clock enable having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - / 0 1 | 0
//- d / - 1 | d
//- - - - - | q
//-
module \$_SDFFCE_PN0P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C) begin
if (E == 1) begin
if (R == 0)
Q <= 0;
else
Q <= D;
end
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFCE_PN1N_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with negative polarity synchronous set and negative
//- polarity clock enable (with clock enable having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - / 0 0 | 1
//- d / - 0 | d
//- - - - - | q
//-
module \$_SDFFCE_PN1N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C) begin
if (E == 0) begin
if (R == 0)
Q <= 1;
else
Q <= D;
end
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFCE_PN1P_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with negative polarity synchronous set and positive
//- polarity clock enable (with clock enable having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - / 0 1 | 1
//- d / - 1 | d
//- - - - - | q
//-
module \$_SDFFCE_PN1P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C) begin
if (E == 1) begin
if (R == 0)
Q <= 1;
else
Q <= D;
end
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFCE_PP0N_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with positive polarity synchronous reset and negative
//- polarity clock enable (with clock enable having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - / 1 0 | 0
//- d / - 0 | d
//- - - - - | q
//-
module \$_SDFFCE_PP0N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C) begin
if (E == 0) begin
if (R == 1)
Q <= 0;
else
Q <= D;
end
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFCE_PP0P_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with positive polarity synchronous reset and positive
//- polarity clock enable (with clock enable having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - / 1 1 | 0
//- d / - 1 | d
//- - - - - | q
//-
module \$_SDFFCE_PP0P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C) begin
if (E == 1) begin
if (R == 1)
Q <= 0;
else
Q <= D;
end
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFCE_PP1N_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with positive polarity synchronous set and negative
//- polarity clock enable (with clock enable having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - / 1 0 | 1
//- d / - 0 | d
//- - - - - | q
//-
module \$_SDFFCE_PP1N_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C) begin
if (E == 0) begin
if (R == 1)
Q <= 1;
else
Q <= D;
end
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFCE_PP1P_ (D, C, R, E, Q)
//-
//- A positive edge D-type flip-flop with positive polarity synchronous set and positive
//- polarity clock enable (with clock enable having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - / 1 1 | 1
//- d / - 1 | d
//- - - - - | q
//-
module \$_SDFFCE_PP1P_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @(posedge C) begin
if (E == 1) begin
if (R == 1)
Q <= 1;
else
Q <= D;
end
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DLATCH_N_ (E, D, Q)
//-
//- A negative enable D-type latch.
//-
//- Truth table: E D | Q
//- -----+---
//- 0 d | d
//- - - | q
//-
module \$_DLATCH_N_ (E, D, Q);
input E, D;
output reg Q;
always @* begin
if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DLATCH_P_ (E, D, Q)
//-
//- A positive enable D-type latch.
//-
//- Truth table: E D | Q
//- -----+---
//- 1 d | d
//- - - | q
//-
module \$_DLATCH_P_ (E, D, Q);
input E, D;
output reg Q;
always @* begin
if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DLATCH_NN0_ (E, R, D, Q)
//-
//- A negative enable D-type latch with negative polarity reset.
//-
//- Truth table: E R D | Q
//- -------+---
//- - 0 - | 0
//- 0 - d | d
//- - - - | q
//-
module \$_DLATCH_NN0_ (E, R, D, Q);
input E, R, D;
output reg Q;
always @* begin
if (R == 0)
Q <= 0;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DLATCH_NN1_ (E, R, D, Q)
//-
//- A negative enable D-type latch with negative polarity set.
//-
//- Truth table: E R D | Q
//- -------+---
//- - 0 - | 1
//- 0 - d | d
//- - - - | q
//-
module \$_DLATCH_NN1_ (E, R, D, Q);
input E, R, D;
output reg Q;
always @* begin
if (R == 0)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DLATCH_NP0_ (E, R, D, Q)
//-
//- A negative enable D-type latch with positive polarity reset.
//-
//- Truth table: E R D | Q
//- -------+---
//- - 1 - | 0
//- 0 - d | d
//- - - - | q
//-
module \$_DLATCH_NP0_ (E, R, D, Q);
input E, R, D;
output reg Q;
always @* begin
if (R == 1)
Q <= 0;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DLATCH_NP1_ (E, R, D, Q)
//-
//- A negative enable D-type latch with positive polarity set.
//-
//- Truth table: E R D | Q
//- -------+---
//- - 1 - | 1
//- 0 - d | d
//- - - - | q
//-
module \$_DLATCH_NP1_ (E, R, D, Q);
input E, R, D;
output reg Q;
always @* begin
if (R == 1)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DLATCH_PN0_ (E, R, D, Q)
//-
//- A positive enable D-type latch with negative polarity reset.
//-
//- Truth table: E R D | Q
//- -------+---
//- - 0 - | 0
//- 1 - d | d
//- - - - | q
//-
module \$_DLATCH_PN0_ (E, R, D, Q);
input E, R, D;
output reg Q;
always @* begin
if (R == 0)
Q <= 0;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DLATCH_PN1_ (E, R, D, Q)
//-
//- A positive enable D-type latch with negative polarity set.
//-
//- Truth table: E R D | Q
//- -------+---
//- - 0 - | 1
//- 1 - d | d
//- - - - | q
//-
module \$_DLATCH_PN1_ (E, R, D, Q);
input E, R, D;
output reg Q;
always @* begin
if (R == 0)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DLATCH_PP0_ (E, R, D, Q)
//-
//- A positive enable D-type latch with positive polarity reset.
//-
//- Truth table: E R D | Q
//- -------+---
//- - 1 - | 0
//- 1 - d | d
//- - - - | q
//-
module \$_DLATCH_PP0_ (E, R, D, Q);
input E, R, D;
output reg Q;
always @* begin
if (R == 1)
Q <= 0;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DLATCH_PP1_ (E, R, D, Q)
//-
//- A positive enable D-type latch with positive polarity set.
//-
//- Truth table: E R D | Q
//- -------+---
//- - 1 - | 1
//- 1 - d | d
//- - - - | q
//-
module \$_DLATCH_PP1_ (E, R, D, Q);
input E, R, D;
output reg Q;
always @* begin
if (R == 1)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DLATCHSR_NNN_ (E, S, R, D, Q)
//-
//- A negative enable D-type latch with negative polarity set and negative
//- polarity reset.
//-
//- Truth table: E S R D | Q
//- ---------+---
//- - - 0 - | 0
//- - 0 - - | 1
//- 0 - - d | d
//- - - - - | q
//-
module \$_DLATCHSR_NNN_ (E, S, R, D, Q);
input E, S, R, D;
output reg Q;
always @* begin
if (R == 0)
Q <= 0;
else if (S == 0)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DLATCHSR_NNP_ (E, S, R, D, Q)
//-
//- A negative enable D-type latch with negative polarity set and positive
//- polarity reset.
//-
//- Truth table: E S R D | Q
//- ---------+---
//- - - 1 - | 0
//- - 0 - - | 1
//- 0 - - d | d
//- - - - - | q
//-
module \$_DLATCHSR_NNP_ (E, S, R, D, Q);
input E, S, R, D;
output reg Q;
always @* begin
if (R == 1)
Q <= 0;
else if (S == 0)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DLATCHSR_NPN_ (E, S, R, D, Q)
//-
//- A negative enable D-type latch with positive polarity set and negative
//- polarity reset.
//-
//- Truth table: E S R D | Q
//- ---------+---
//- - - 0 - | 0
//- - 1 - - | 1
//- 0 - - d | d
//- - - - - | q
//-
module \$_DLATCHSR_NPN_ (E, S, R, D, Q);
input E, S, R, D;
output reg Q;
always @* begin
if (R == 0)
Q <= 0;
else if (S == 1)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DLATCHSR_NPP_ (E, S, R, D, Q)
//-
//- A negative enable D-type latch with positive polarity set and positive
//- polarity reset.
//-
//- Truth table: E S R D | Q
//- ---------+---
//- - - 1 - | 0
//- - 1 - - | 1
//- 0 - - d | d
//- - - - - | q
//-
module \$_DLATCHSR_NPP_ (E, S, R, D, Q);
input E, S, R, D;
output reg Q;
always @* begin
if (R == 1)
Q <= 0;
else if (S == 1)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DLATCHSR_PNN_ (E, S, R, D, Q)
//-
//- A positive enable D-type latch with negative polarity set and negative
//- polarity reset.
//-
//- Truth table: E S R D | Q
//- ---------+---
//- - - 0 - | 0
//- - 0 - - | 1
//- 1 - - d | d
//- - - - - | q
//-
module \$_DLATCHSR_PNN_ (E, S, R, D, Q);
input E, S, R, D;
output reg Q;
always @* begin
if (R == 0)
Q <= 0;
else if (S == 0)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DLATCHSR_PNP_ (E, S, R, D, Q)
//-
//- A positive enable D-type latch with negative polarity set and positive
//- polarity reset.
//-
//- Truth table: E S R D | Q
//- ---------+---
//- - - 1 - | 0
//- - 0 - - | 1
//- 1 - - d | d
//- - - - - | q
//-
module \$_DLATCHSR_PNP_ (E, S, R, D, Q);
input E, S, R, D;
output reg Q;
always @* begin
if (R == 1)
Q <= 0;
else if (S == 0)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DLATCHSR_PPN_ (E, S, R, D, Q)
//-
//- A positive enable D-type latch with positive polarity set and negative
//- polarity reset.
//-
//- Truth table: E S R D | Q
//- ---------+---
//- - - 0 - | 0
//- - 1 - - | 1
//- 1 - - d | d
//- - - - - | q
//-
module \$_DLATCHSR_PPN_ (E, S, R, D, Q);
input E, S, R, D;
output reg Q;
always @* begin
if (R == 0)
Q <= 0;
else if (S == 1)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DLATCHSR_PPP_ (E, S, R, D, Q)
//-
//- A positive enable D-type latch with positive polarity set and positive
//- polarity reset.
//-
//- Truth table: E S R D | Q
//- ---------+---
//- - - 1 - | 0
//- - 1 - - | 1
//- 1 - - d | d
//- - - - - | q
//-
module \$_DLATCHSR_PPP_ (E, S, R, D, Q);
input E, S, R, D;
output reg Q;
always @* begin
if (R == 1)
Q <= 0;
else if (S == 1)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/23/2016 11:26:28 AM
// Design Name:
// Module Name: Sgf_Multiplication
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Sgf_Multiplication
//#(parameter SW = 24)
#(parameter SW = 54)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
//wire [SW-1:0] Data_A_i;
//wire [SW-1:0] Data_B_i;
//wire [2*(SW/2)-1:0] result_left_mult;
//wire [2*(SW/2+1)-1:0] result_right_mult;
wire [SW/2+1:0] result_A_adder;
//wire [SW/2+1:0] Q_result_A_adder;
wire [SW/2+1:0] result_B_adder;
//wire [SW/2+1:0] Q_result_B_adder;
//wire [2*(SW/2+2)-1:0] result_middle_mult;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
wire [2*(SW/2+2)-1:0] S_A;
wire [2*(SW/2+2)-1:0] S_B;
wire [4*(SW/2)+2:0] Result;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 =2'b00;
assign zero2 =4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
wire [4*(SW/2)-1:0] sgf_r;
assign rightside1 = (SW/2) *1'b0;
assign rightside2 = (SW/2+1)*1'b0;
localparam half = SW/2;
//localparam level1=4;
//localparam level2=5;
////////////////////////////////////
generate
case (SW%2)
0:begin
//////////////////////////////////even//////////////////////////////////
//Multiplier for left side and right side
multiplier #(.W(SW/2)/*,.level(level1)*/) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(/*result_left_mult*/Q_left)
);
/*RegisterAdd #(.W(SW)) leftreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_left_mult),
.Q(Q_left)
);//*/
multiplier #(.W(SW/2)/*,.level(level1)*/) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(/*result_right_mult[2*(SW/2)-1:0]*/Q_right[2*(SW/2)-1:0])
);
/*RegisterAdd #(.W(SW)) rightreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_right_mult[2*(SW/2)-1:0]),
.Q(Q_right[2*(SW/2)-1:0])
);//*/
//Adders for middle
adder #(.W(SW/2)) A_operation (
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder[SW/2:0])
);
adder #(.W(SW/2)) B_operation (
.Data_A_i(Data_B_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder[SW/2:0])
);
//segmentation registers for 64 bits
/*RegisterAdd #(.W(SW/2+1)) preAreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_A_adder[SW/2:0]),
.Q(Q_result_A_adder[SW/2:0])
);//
RegisterAdd #(.W(SW/2+1)) preBreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_B_adder[SW/2:0]),
.Q(Q_result_B_adder[SW/2:0])
);//*/
//multiplication for middle
multiplier #(.W(SW/2+1)/*,.level(level1)*/) middle (
.clk(clk),
.Data_A_i(/*Q_result_A_adder[SW/2:0]*/result_A_adder[SW/2:0]),
.Data_B_i(/*Q_result_B_adder[SW/2:0]*/result_B_adder[SW/2:0]),
.Data_S_o(/*result_middle_mult[2*(SW/2)+1:0]*/Q_middle[2*(SW/2)+1:0])
);
//segmentation registers array
/*RegisterAdd #(.W(SW+2)) midreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_middle_mult[2*(SW/2)+1:0]),
.Q(Q_middle[2*(SW/2)+1:0])
);//*/
///Subtractors for middle
substractor #(.W(SW+2)) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A[2*(SW/2)+1:0])
);
substractor #(.W(SW+2)) Subtr_2 (
.Data_A_i(S_A[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_right_mult//*/Q_right[2*(SW/2)-1:0]}),
.Data_S_o(S_B[2*(SW/2)+1:0])
);
//Final adder
adder #(.W(4*(SW/2))) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right[2*(SW/2)-1:0]}),
.Data_B_i({S_B[2*(SW/2)+1:0],rightside1}),
.Data_S_o(Result[4*(SW/2):0])
);
//Final Register
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin
//////////////////////////////////odd//////////////////////////////////
//Multiplier for left side and right side
multiplier #(.W(SW/2)/*,.level(level2)*/) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(/*result_left_mult*/Q_left)
);
/*RegisterAdd #(.W(2*(SW/2))) leftreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_left_mult),
.Q(Q_left)
);//*/
multiplier #(.W((SW/2)+1)/*,.level(level2)*/) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(/*result_right_mult*/Q_right)
);
/*RegisterAdd #(.W(2*((SW/2)+1))) rightreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_right_mult),
.Q(Q_right)
);//*/
//Adders for middle
adder #(.W(SW/2+1)) A_operation (
.Data_A_i({1'b0,Data_A_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder)
);
adder #(.W(SW/2+1)) B_operation (
.Data_A_i({1'b0,Data_B_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder)
);
//segmentation registers for 64 bits
/*RegisterAdd #(.W(SW/2+2)) preAreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_A_adder),
.Q(Q_result_A_adder)
);//
RegisterAdd #(.W(SW/2+2)) preBreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_B_adder),
.Q(Q_result_B_adder)
);//*/
//multiplication for middle
multiplier #(.W(SW/2+2)/*,.level(level2)*/) middle (
.clk(clk),
.Data_A_i(/*Q_result_A_adder*/result_A_adder),
.Data_B_i(/*Q_result_B_adder*/result_B_adder),
.Data_S_o(/*result_middle_mult*/Q_middle)
);
//segmentation registers array
/*RegisterAdd #(.W(2*((SW/2)+2))) midreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_middle_mult),
.Q(Q_middle)
);//*/
///Subtractors for middle
substractor #(.W(2*(SW/2+2))) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle),
.Data_B_i({zero2, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A)
);
substractor #(.W(2*(SW/2+2))) Subtr_2 (
.Data_A_i(S_A),
.Data_B_i({zero1, /*result_right_mult//*/Q_right}),
.Data_S_o(S_B)
);
//Final adder
adder #(.W(4*(SW/2)+2)) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right}),
.Data_B_i({S_B,rightside2}),
.Data_S_o(Result[4*(SW/2)+2:0])
);
//Final Register
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
endgenerate
endmodule
|
module top();
reg consumer_iclk;
reg producer_iclk;
wire cr;
wire [3:0] cd;
wire [3:0] pd;
reg clk;
always@(posedge clk)
begin
#10 assign consumer_iclk = ~consumer_iclk;
#5 assign producer_iclk = ~producer_iclk;
end
always
#1 assign clk = ~clk;
initial
begin
/*
consumer_iclk = 0;
producer_iclk = 0;
cr =0;
cd=0;
pd=0;
*/
#5000 $finish;
end
producer p1(
pd
);
fifo f1(
cd,
pd,
cr
);
consumer c1(
cr,
cd
);
endmodule
//------------------------------
//PRODUCER IS PRODUCING DATA
module producer (/*producer_iclk,*/producer_data);
//input producer_iclk;
output producer_data;
reg producer_iclk;
reg [3:0] producer_data;
//assign producer_data = 0;
reg [3:0] i = 4'b0000;
always @(producer_iclk)
begin
producer_data = producer_data + 1;
end
initial
begin
producer_data = 0;
producer_iclk = 0;
//$monitor("time=%t data produced = %b clk=%b",$time,producer_data,producer_iclk);
//#100 $finish;
end
//internal 5 unit clk
always
begin
#5 producer_iclk = ~(producer_iclk);
end
endmodule
//-------------------------------
module fifo(consumer_data,producer_data, consumer_req);
input consumer_req;
input producer_data;
output consumer_data;
reg [3:0] consumer_data;
reg [3:0] producer_data;
reg consumer_req;
int i;
int j;
int last;
int start;
int diff;
int last_s;
int start_s;
reg [3:0] queue [9:0];
initial
begin
assign last_s = last % 10;
assign start_s = start % 10;
assign diff = last - start;
//$monitor("producer data = %b %d",producer_data,producer_data);
//producer_data = 0;
#30for(j=0;j<10;j++)
begin
//$display("queue[%d] =%d at time =%t",j,queue[j],$time);
end
end
//add_data thingy
always @ (producer_data)
if((diff < 10))
begin
begin
queue[last_s] = producer_data;
//$display("add queue[%d] is %d",last_s,queue[last_s]);
#0 last = last +1;
end
end else begin
$finish;
end
//pop data thingy
always @(consumer_req)
begin
if(consumer_req == 1)
begin
if(diff != 0)
begin
// $display("pop queue[%d] = %d",start_s,queue[start_s]);
consumer_data = queue[start_s];
//$display("consumer data = %d",consumer_data);
#0 start = start +1;
end
/*
queue[start] = consumer_data;
#0 start = start + 1;
$display("start = %d at time = %t",start,$time);
$display("consumer data = %d",consumer_data);
*/
end
end
endmodule
//------------------------
module consumer(/*consumer_iclk,*/consumer_req,consumer_data);
//input consumer_iclk;
input consumer_data;
output consumer_req;
reg consumer_iclk;
reg [3:0] consumer_data;
reg consumer_req;
// consumer_req = 0;
always @(consumer_iclk)
begin
consumer_req = 1;
#1 consumer_req = 0;
end
initial
begin
//consumer_data = 0;
consumer_req=0;
consumer_iclk =1;
$monitor("data consumed : %d at time = %t", consumer_data,$time);
//#20 $finish;
end
//internal clk
always
begin
#10 consumer_iclk = ~consumer_iclk;
end
endmodule
|
// megafunction wizard: %CRC Compiler v11.0%
// GENERATION: XML
// ============================================================
// Megafunction Name(s):
// check_ip_altcrc
// ============================================================
// Generated by CRC Compiler 11.0 [Altera, IP Toolbench 1.3.0 Build 157]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2011 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module check_ip (
clk,
data,
datavalid,
empty,
endofpacket,
reset_n,
startofpacket,
crcbad,
crcvalid);
input clk;
input [127:0] data;
input datavalid;
input [3:0] empty;
input endofpacket;
input reset_n;
input startofpacket;
output crcbad;
output crcvalid;
check_ip_altcrc check_ip_altcrc_inst(
.clk(clk),
.data(data),
.datavalid(datavalid),
.empty(empty),
.endofpacket(endofpacket),
.reset_n(reset_n),
.startofpacket(startofpacket),
.crcbad(crcbad),
.crcvalid(crcvalid));
endmodule
// =========================================================
// CRC Compiler Wizard Data
// ===============================
// DO NOT EDIT FOLLOWING DATA
// @Altera, IP Toolbench@
// Warning: If you modify this section, CRC Compiler Wizard may not be able to reproduce your chosen configuration.
//
// Retrieval info: <?xml version="1.0"?>
// Retrieval info: <MEGACORE title="CRC Compiler" version="11.0" build="157" iptb_version="1.3.0 Build 157" format_version="120" >
// Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.MVCModel" active_core="check_ip_altcrc" >
// Retrieval info: <STATIC_SECTION>
// Retrieval info: <PRIVATES>
// Retrieval info: <NAMESPACE name = "parameterization">
// Retrieval info: <PRIVATE name = "p_wordsize" value="128" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_crccheck" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_inbuff" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_outbuff" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_lanes" value="16" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_fwdpipe" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_initvalue" value="0xFFFFFFFF" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_bckpipe" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_generator" value="1_0000_0100_1100_0001_0001_1101_1011_0111" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_lsb" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_symbol_lsb" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_true_output" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_reverse" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_start_offset" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_channels" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "g_optimize" value="speed" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "g_use_all_ones" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "g_datapath" value="128 bits" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "g_genname" value="CRC-32" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "g_negate_checksum" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_cbx_hdl_language" value="verilog" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen_enable">
// Retrieval info: <PRIVATE name = "language" value="VERILOG" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enabled" value="0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "greybox">
// Retrieval info: <PRIVATE name = "gb_enabled" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "filename" value="check_ip_syn.v" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen">
// Retrieval info: <PRIVATE name = "filename" value="check_ip.vo" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "serializer"/>
// Retrieval info: </PRIVATES>
// Retrieval info: <FILES/>
// Retrieval info: <PORTS/>
// Retrieval info: <LIBRARIES/>
// Retrieval info: </STATIC_SECTION>
// Retrieval info: </NETLIST_SECTION>
// Retrieval info: </MEGACORE>
// =========================================================
|
/*
* Integer conversion module for Zet
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_conv (
input [15:0] x,
input [ 2:0] func,
output [31:0] out,
input [ 1:0] iflags, // afi, cfi
output [ 2:0] oflags // afo, ofo, cfo
);
// Net declarations
wire afi, cfi;
wire ofo, afo, cfo;
wire [15:0] aaa, aas;
wire [ 7:0] daa, tmpdaa, das, tmpdas;
wire [15:0] cbw, cwd;
wire acond, dcond;
wire tmpcf;
// Module instances
zet_mux8_16 mux8_16 (func, cbw, aaa, aas, 16'd0,
cwd, {x[15:8], daa}, {x[15:8], das}, 16'd0, out[15:0]);
// Assignments
assign aaa = (acond ? (x + 16'h0106) : x) & 16'hff0f;
assign aas = (acond ? (x - 16'h0106) : x) & 16'hff0f;
assign tmpdaa = acond ? (x[7:0] + 8'h06) : x[7:0];
assign daa = dcond ? (tmpdaa + 8'h60) : tmpdaa;
assign tmpdas = acond ? (x[7:0] - 8'h06) : x[7:0];
assign das = dcond ? (tmpdas - 8'h60) : tmpdas;
assign cbw = { { 8{x[ 7]}}, x[7:0] };
assign { out[31:16], cwd } = { {16{x[15]}}, x };
assign acond = ((x[7:0] & 8'h0f) > 8'h09) | afi;
assign dcond = (x[7:0] > 8'h99) | cfi;
assign afi = iflags[1];
assign cfi = iflags[0];
assign afo = acond;
assign ofo = 1'b0;
assign tmpcf = (x[7:0] < 8'h06) | cfi;
assign cfo = func[2] ? (dcond ? 1'b1 : (acond & tmpcf))
: acond;
assign oflags = { afo, ofo, cfo };
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// EncWidthConverter16to32.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: Data width up converter
// Module Name: EncWidthConverter16to32
// File Name: EncWidthConverter16to32.v
//
// Version: v1.0.0
//
// Description: Data width up converting unit for encoder
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module EncWidthConverter16to32
#
(
parameter InputDataWidth = 16,
parameter OutputDataWidth = 32
)
(
iClock ,
iReset ,
iCurLoopCount ,
iCmdType ,
iSrcDataValid ,
iSrcDataLast ,
iSrcParityLast ,
iSrcData ,
oConverterReady ,
oConvertedDataValid ,
oConvertedDataLast ,
oConvertedParityLast,
oConvertedData ,
iDstReady
);
input iClock ;
input iReset ;
input iCurLoopCount ;
input [1:0] iCmdType ;
input iSrcDataValid ;
input iSrcDataLast ;
input iSrcParityLast ;
input [InputDataWidth - 1:0] iSrcData ;
output oConverterReady ;
output oConvertedDataValid ;
output oConvertedDataLast ;
output oConvertedParityLast;
output [OutputDataWidth - 1:0] oConvertedData ;
input iDstReady ;
reg [InputDataWidth - 1:0] rShiftRegister ;
reg [InputDataWidth - 1:0] rInputRegister ;
reg rConvertedDataValid ;
reg rConvertedDataLast ;
reg rConvertedParityLast;
localparam State_Idle = 5'b00001;
localparam State_Input = 5'b00010;
localparam State_Shift = 5'b00100;
localparam State_InPause = 5'b01000;
localparam State_OutPause = 5'b10000;
reg [4:0] rCurState;
reg [4:0] rNextState;
always @ (posedge iClock)
if (iReset)
rCurState <= State_Idle;
else
rCurState <= rNextState;
always @ (*)
case (rCurState)
State_Idle:
rNextState <= (iSrcDataValid) ? State_Input : State_Idle;
State_Input:
rNextState <= (iSrcDataValid) || ((iCmdType == 2'b10) && (rConvertedParityLast)) ? State_Shift : State_InPause;
State_Shift:
if (iDstReady)
begin
if (iSrcDataValid)
rNextState <= State_Input;
else
rNextState <= State_Idle;
end
else
rNextState <= State_OutPause;
State_InPause:
rNextState <= (iSrcDataValid) ? State_Shift : State_InPause;
State_OutPause:
if (iDstReady)
begin
if (iSrcDataValid)
rNextState <= State_Input;
else
rNextState <= State_Idle;
end
else
rNextState <= State_OutPause;
endcase
always @ (posedge iClock)
if (iReset)
begin
rInputRegister <= 0;
rShiftRegister <= 0;
end
else
case (rNextState)
State_Input:
begin
rInputRegister <= iSrcData;
rShiftRegister <= 0;
end
State_Shift:
begin
rInputRegister <= iSrcData;
rShiftRegister <= rInputRegister;
end
State_InPause:
begin
rInputRegister <= rInputRegister;
rShiftRegister <= rShiftRegister;
end
State_OutPause:
begin
rInputRegister <= rInputRegister;
rShiftRegister <= rShiftRegister;
end
default:
begin
rInputRegister <= 0;
rShiftRegister <= 0;
end
endcase
always @ (posedge iClock)
if (iReset)
rConvertedDataValid <= 0;
else
case (rNextState)
State_Shift:
rConvertedDataValid <= 1'b1;
State_OutPause:
rConvertedDataValid <= 1'b1;
default:
rConvertedDataValid <= 1'b0;
endcase
always @ (posedge iClock)
if (iReset)
rConvertedParityLast <= 0;
else
if (iSrcParityLast)
rConvertedParityLast <= 1'b1;
else if (rConvertedParityLast & iDstReady & oConvertedDataValid)
rConvertedParityLast <= 1'b0;
always @ (posedge iClock)
if (iReset)
rConvertedDataLast <= 0;
else
rConvertedDataLast <= iSrcDataLast;
assign oConvertedData = {rShiftRegister, rInputRegister};
assign oConvertedDataValid = rConvertedDataValid;
assign oConverterReady = !(rNextState == State_OutPause);
assign oConvertedParityLast = (iCmdType == 2'b10) ? rConvertedParityLast & iDstReady & oConvertedDataValid :
(iCurLoopCount) ? rConvertedParityLast : iSrcParityLast;
assign oConvertedDataLast = rConvertedDataLast;
endmodule |
/* lab2_part7.v
*
* Copyright (c) 2014, Artem Tovbin <arty99 at gmail dot com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module lab2_part7 (SW, LEDR, HEX1, HEX0);
input [5:0] SW;
output [0:6] HEX1, HEX0;
output [5:0] LEDR;
reg [3:0] TENS, ONES;
assign LEDR = SW;
always begin
if (SW[5:0] > 59) begin
TENS = 6;
ONES = SW[5:0] - 60;
end else if (SW[5:0] > 49) begin
TENS = 5;
ONES = SW[5:0] - 50;
end else if (SW[5:0] > 39) begin
TENS = 4;
ONES = SW[5:0] - 40;
end else if (SW[5:0] > 29) begin
TENS = 3;
ONES = SW[5:0] - 30;
end else if (SW[5:0] > 19) begin
TENS = 2;
ONES = SW[5:0] - 20;
end else if (SW[5:0] > 9) begin
TENS = 1;
ONES = SW[5:0] - 10;
end else begin
TENS = 0;
ONES = SW[5:0];
end //if
end //always
b2d_7seg H1 (TENS, HEX1);
b2d_7seg H0 (ONES, HEX0);
endmodule
module b2d_7seg (X, SSD);
input [3:0] X;
output [0:6] SSD;
assign SSD[0] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & ~X[1] & ~X[0]));
assign SSD[1] = ((~X[3] & X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & X[1] & ~X[0]));
assign SSD[2] = (~X[3] & ~X[2] & X[1] & ~X[0]);
assign SSD[3] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & ~X[1] & ~X[0]) | (~X[3] & X[2] & X[1] & X[0]) | (X[3] & ~X[2] & ~X[1] & X[0]));
assign SSD[4] = ~((~X[2] & ~X[0]) | (X[1] & ~X[0]));
assign SSD[5] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & ~X[2] & X[1] & ~X[0]) | (~X[3] & ~X[2] & X[1] & X[0]) | (~X[3] & X[2] & X[1] & X[0]));
assign SSD[6] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & ~X[2] & ~X[1] & ~X[0]) | (~X[3] & X[2] & X[1] & X[0]));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR2_BEHAVIORAL_V
`define SKY130_FD_SC_LS__XOR2_BEHAVIORAL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR2_BEHAVIORAL_V |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// FIXME need to add flow control
module serdes_tb();
reg clk, rst;
wire ser_rx_clk, ser_tx_clk;
wire ser_rklsb, ser_rkmsb, ser_tklsb, ser_tkmsb;
wire [15:0] ser_r, ser_t;
initial clk = 0;
initial rst = 1;
initial #1000 rst = 0;
always #100 clk = ~clk;
// Wishbone
reg [31:0] wb_dat_i;
wire [31:0] wb_dat_o_rx, wb_dat_o_tx;
reg wb_we, wb_en_rx, wb_en_tx;
reg [8:0] wb_adr;
// Buffer Control
reg go, clear, read, write;
reg [3:0] buf_num;
wire [31:0] ctrl_word = {buf_num,3'b0,clear,write,read,step,lastline,firstline};
reg [8:0] firstline = 0, lastline = 0;
reg [3:0] step = 1;
reg first_tx = 1, first_rx = 1; // for verif
// TX Side
reg wb_we_tx;
wire en_tx, we_tx;
wire [8:0] addr_tx;
wire [31:0] f2r_tx, r2f_tx;
wire [31:0] data_tx;
wire read_tx, done_tx, error_tx, sop_tx, eop_tx;
wire fdone_tx, ferror_tx;
reg even;
reg channel_error = 0;
serdes_tx serdes_tx
(.clk(clk),.rst(rst),
.ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
.rd_dat_i(data_tx),.rd_read_o(read_tx),.rd_done_o(done_tx),
.rd_error_o(error_tx),.rd_sop_i(sop_tx),.rd_eop_i(eop_tx) );
ram_2port #(.DWIDTH(32),.AWIDTH(9))
ram_tx(.clka(clk),.ena(wb_en_tx),.wea(wb_we_tx),.addra(wb_adr),.dia(wb_dat_i),.doa(wb_dat_o_tx),
.clkb(clk),.enb(en_tx),.web(we_tx),.addrb(addr_tx),.dib(f2r_tx),.dob(r2f_tx));
buffer_int #(.BUFF_NUM(1)) buffer_int_tx
(.clk(clk),.rst(rst),
.ctrl_word(ctrl_word),.go(go),
.done(fdone_tx),.error(ferror_tx),
.en_o(en_tx),.we_o(we_tx),.addr_o(addr_tx),.dat_to_buf(f2r_tx),.dat_from_buf(r2f_tx),
.wr_dat_i(0),.wr_write_i(0),.wr_done_i(0),
.wr_error_i(0),.wr_ready_o(),.wr_full_o(),
.rd_dat_o(data_tx),.rd_read_i(read_tx),.rd_done_i(done_tx),
.rd_error_i(error_tx),.rd_sop_o(sop_tx),.rd_eop_o(eop_tx) );
// RX Side
reg wb_we_rx;
wire en_rx, we_rx;
wire [8:0] addr_rx;
wire [31:0] f2r_rx, r2f_rx;
wire [31:0] data_rx;
wire write_rx, done_rx, error_rx, ready_rx, empty_rx;
wire fdone_rx, ferror_rx;
serdes_rx serdes_rx
(.clk(clk),.rst(rst),
.ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
.wr_dat_o(data_rx),.wr_write_o(write_rx),.wr_done_o(done_rx),
.wr_error_o(error_rx),.wr_ready_i(ready_rx),.wr_full_i(full_rx) );
ram_2port #(.DWIDTH(32),.AWIDTH(9))
ram_rx(.clka(clk),.ena(wb_en_rx),.wea(wb_we_rx),.addra(wb_adr),.dia(wb_dat_i),.doa(wb_dat_o_rx),
.clkb(clk),.enb(en_rx),.web(we_rx),.addrb(addr_rx),.dib(f2r_rx),.dob(r2f_rx) );
buffer_int #(.BUFF_NUM(0)) buffer_int_rx
(.clk(clk),.rst(rst),
.ctrl_word(ctrl_word),.go(go),
.done(fdone_rx),.error(ferror_rx),
.en_o(en_rx),.we_o(we_rx),.addr_o(addr_rx),.dat_to_buf(f2r_rx),.dat_from_buf(r2f_rx),
.wr_dat_i(data_rx),.wr_write_i(write_rx),.wr_done_i(done_rx),
.wr_error_i(error_rx),.wr_ready_o(ready_rx),.wr_full_o(full_rx),
.rd_dat_o(),.rd_read_i(0),.rd_done_i(0),
.rd_error_i(0),.rd_sop_o(),.rd_eop_o() );
// Simulate the connection
serdes_model serdes_model
(.ser_tx_clk(ser_tx_clk), .ser_tkmsb(ser_tkmsb), .ser_tklsb(ser_tklsb), .ser_t(ser_t),
.ser_rx_clk(ser_rx_clk), .ser_rkmsb(ser_rkmsb), .ser_rklsb(ser_rklsb), .ser_r(ser_r),
.even(even), .error(channel_error) );
initial begin
wb_en_rx <= 0;
wb_en_tx <=0;
wb_we_tx <= 0;
wb_we_rx <= 0;
wb_adr <= 0;
wb_dat_i <= 0;
go <= 0;
even <= 0;
@(negedge rst);
@(posedge clk);
FillTXRAM;
ClearRXRAM;
ResetBuffer(0);
ResetBuffer(1);
// receive a full buffer
ReceiveSERDES(0,10);
SendSERDES(0,10);
// Receive a partial buffer
SendSERDES(11,20);
ReceiveSERDES(11,50);
// Receive too many for buffer
SendSERDES(21,100);
ReceiveSERDES(21,30);
// Send 3 packets, then wait to receive them, so they stack up in the rx fifo
SendSERDES(31,40);
SendSERDES(41,50);
SendSERDES(51,60);
repeat (10)
@(posedge clk);
ReceiveSERDES(31,40);
ReceiveSERDES(41,50);
repeat (1000)
@(posedge clk);
ReceiveSERDES(51,60);
// Overfill the FIFO, should get an error on 3rd packet
SendSERDES(1,400);
SendSERDES(1,400);
WaitForTX;
//WaitForRX;
repeat(1000)
@(posedge clk);
ReceiveSERDES(101,500);
ReceiveSERDES(101,500);
ReadRAM(80);
$finish;
end // initial begin
always @(posedge clk)
if(write_rx)
$display("SERDES RX, FIFO WRITE %x, FIFO RDY %d, FIFO FULL %d",data_rx, ready_rx, full_rx);
always @(posedge clk)
if(read_tx)
$display("SERDES TX, FIFO READ %x, SOP %d, EOP %d",data_tx, sop_tx, eop_tx);
initial begin
$dumpfile("serdes_tb.vcd");
$dumpvars(0,serdes_tb);
end
initial #10000000 $finish;
initial #259300 channel_error <= 1;
initial #259500 channel_error <= 0;
task FillTXRAM;
begin
wb_adr <= 0;
wb_dat_i <= 32'h10802000;
wb_we_tx <= 1;
wb_en_tx <= 1;
@(posedge clk);
repeat(511) begin
wb_dat_i <= wb_dat_i + 32'h00010001;
wb_adr <= wb_adr + 1;
@(posedge clk);
end // repeat (511)
wb_we_tx <= 0;
wb_en_tx <= 0;
@(posedge clk);
$display("Done entering Data into TX RAM\n");
end
endtask // FillTXRAM
task ClearRXRAM;
begin
wb_adr <= 0;
wb_dat_i <= 0;
wb_we_rx <= 1;
wb_en_rx <= 1;
wb_dat_i <= 0;
@(posedge clk);
repeat(511) begin
wb_adr <= wb_adr + 1;
@(posedge clk);
end // repeat (511)
wb_we_rx <= 0;
wb_en_rx <= 0;
@(posedge clk);
$display("Done clearing RX RAM\n");
end
endtask // FillRAM
task ReadRAM;
input [8:0] lastline;
begin
wb_en_rx <= 1;
wb_adr <= 0;
@(posedge clk);
@(posedge clk);
repeat(lastline) begin
$display("ADDR: %h DATA %h", wb_adr, wb_dat_o_rx);
wb_adr <= wb_adr + 1;
@(posedge clk);
@(posedge clk);
end // repeat (511)
$display("ADDR: %h DATA %h", wb_adr, wb_dat_o_rx);
wb_en_rx <= 0;
@(posedge clk);
$display("Done reading out RX RAM\n");
end
endtask // FillRAM
task ResetBuffer;
input [3:0] buffer_num;
begin
buf_num <= buffer_num;
clear <= 1; read <= 0; write <= 0;
go <= 1;
@(posedge clk);
go <= 0;
@(posedge clk);
$display("Buffer Reset");
end
endtask // ClearBuffer
task SetBufferWrite;
input [3:0] buffer_num;
input [8:0] start;
input [8:0] stop;
begin
buf_num <= buffer_num;
clear <= 0; read <= 0; write <= 1;
firstline <= start;
lastline <= stop;
go <= 1;
@(posedge clk);
go <= 0;
@(posedge clk);
$display("Buffer Set for Write");
end
endtask // SetBufferWrite
task SetBufferRead;
input [3:0] buffer_num;
input [8:0] start;
input [8:0] stop;
begin
buf_num <= buffer_num;
clear <= 0; read <= 1; write <= 0;
firstline <= start;
lastline <= stop;
go <= 1;
@(posedge clk);
go <= 0;
@(posedge clk);
$display("Buffer Set for Read");
end
endtask // SetBufferRead
task WaitForTX;
begin
while (!(fdone_tx | ferror_tx))
@(posedge clk);
end
endtask // WaitForTX
task WaitForRX;
begin
while (!(fdone_rx | ferror_rx))
@(posedge clk);
end
endtask // WaitForRX
task SendSERDES;
input [8:0] start;
input [8:0] stop;
begin
if(~first_tx)
WaitForTX;
else
first_tx <= 0;
ResetBuffer(1);
SetBufferRead(1,start,stop);
$display("Here");
end
endtask // SendSERDES
task ReceiveSERDES;
input [8:0] start;
input [8:0] stop;
begin
if(~first_rx)
WaitForRX;
else
first_rx <= 0;
ResetBuffer(0);
SetBufferWrite(0,start,stop);
$display("Here2");
end
endtask // ReceiveSERDES
endmodule // serdes_tb
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_ifu_sscan.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sparc_ifu_sscan( ctu_sscan_snap, ctu_sscan_se, ctu_tck, lsu_sscan_test_data,
tlu_sscan_test_data, swl_sscan_thrstate, ifq_sscan_test_data, sparc_sscan_so, rclk, si, so, se);
input ctu_sscan_snap;
input ctu_sscan_se;
input ctu_tck;
input si;
input se;
input [10:0] swl_sscan_thrstate;
input [3:0] ifq_sscan_test_data;
input [15:0] lsu_sscan_test_data;
input [62:0] tlu_sscan_test_data;
input rclk;
output sparc_sscan_so;
output so;
//////////////////////////////////////////////////////////////////
wire snap_f;
wire [93:0] snap_data, snap_data_f, snap_data_ff;
`ifdef CONNECT_SHADOW_SCAN
wire [92:0] sscan_shift_data;
`endif
////////
dff_s #(1) snap_inst0(.q(snap_f), .din(ctu_sscan_snap), .clk(rclk), .se(se), .si(), .so());
assign snap_data = {ifq_sscan_test_data, tlu_sscan_test_data, lsu_sscan_test_data, swl_sscan_thrstate};
dffe_s #(94) snap_inst1(.q(snap_data_f), .din(snap_data), .clk(rclk), .en(snap_f), .se(se), .si(), .so());
`ifdef CONNECT_SHADOW_SCAN
dff_sscan #(94) snap_inst2(.q(snap_data_ff), .din(snap_data_f), .clk(ctu_tck), .se(ctu_sscan_se),
.si({sscan_shift_data, 1'b0}),
.so({sparc_sscan_so, sscan_shift_data}));
`else
dff_s #(94) snap_inst2(.q(snap_data_ff), .din(snap_data_f), .clk(ctu_tck), .se(ctu_sscan_se),
.si(), .so());
assign sparc_sscan_so = 1'b0;
`endif
sink #(94) s0(.in (snap_data_ff));
endmodule
|
/*
* Titor - Barrel Processor - A convenience module for referencing fields of the instruction
* Copyright (C) 2012 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_Splitter
`else
`define INC_Splitter
`timescale 1 ns / 100 ps
// Combinational module
// splits the instruction into constituent pieces
module Splitter (
instruction,
fld_opcode,
fld_affect,
fld_field0,
fld_field1,
fld_field2,
fld_shift_type,
fld_shift_IR,
fld_shamt_S,
fld_shamt_I,
fld_shamt_R,
fld_immediate
);
`include "definition/Definition.v"
input [WORD-1 :0] instruction;
output reg [WIDTH_OPCODE-1 :0] fld_opcode;
output reg [WIDTH_AFFECT-1 :0] fld_affect;
output reg [WIDTH_FIELD0-1 :0] fld_field0;
output reg [WIDTH_FIELD1-1 :0] fld_field1;
output reg [WIDTH_FIELD2-1 :0] fld_field2;
output reg [WIDTH_SHIFT_TYPE-1 :0] fld_shift_type;
output reg [WIDTH_SHIFT_IR-1 :0] fld_shift_IR;
output reg [WIDTH_SHAMT_S-1 :0] fld_shamt_S;
output reg [WIDTH_SHAMT_I-1 :0] fld_shamt_I;
output reg [WIDTH_SHAMT_R-1 :0] fld_shamt_R;
output reg [WIDTH_IMMEDIATE-1 :0] fld_immediate;
always @(*) begin
fld_opcode <= instruction[VECT_OPCODE_H :VECT_OPCODE_L];
fld_affect <= instruction[VECT_AFFECT_H :VECT_AFFECT_L];
fld_field0 <= instruction[VECT_FIELD0_H :VECT_FIELD0_L];
fld_field1 <= instruction[VECT_FIELD1_H :VECT_FIELD1_L];
fld_field2 <= instruction[VECT_FIELD2_H :VECT_FIELD2_L];
fld_shift_type <= instruction[VECT_SHIFT_TYPE_H :VECT_SHIFT_TYPE_L];
fld_shift_IR <= instruction[VECT_SHIFT_IR_H :VECT_SHIFT_IR_L];
fld_shamt_S <= instruction[VECT_SHAMT_S_H :VECT_SHAMT_S_L];
fld_shamt_I <= instruction[VECT_SHAMT_I_H :VECT_SHAMT_I_L];
fld_shamt_R <= instruction[VECT_SHAMT_R_H :VECT_SHAMT_R_L];
fld_immediate <= instruction[VECT_IMMEDIATE_H :VECT_IMMEDIATE_L];
end
endmodule
`endif
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:54:40 2016
/////////////////////////////////////////////////////////////
module GeAr_N8_R1_P4 ( in1, in2, res );
input [7:0] in1;
input [7:0] in2;
output [8:0] res;
wire intadd_27_CI, intadd_27_n3, intadd_27_n2, intadd_27_n1, n2, n3, n4,
n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18;
CMPR32X2TS intadd_27_U4 ( .A(in2[1]), .B(in1[1]), .C(intadd_27_CI), .CO(
intadd_27_n3), .S(res[1]) );
CMPR32X2TS intadd_27_U3 ( .A(in2[2]), .B(in1[2]), .C(intadd_27_n3), .CO(
intadd_27_n2), .S(res[2]) );
CMPR32X2TS intadd_27_U2 ( .A(in2[3]), .B(in1[3]), .C(intadd_27_n2), .CO(
intadd_27_n1), .S(res[3]) );
AO21XLTS U2 ( .A0(n8), .A1(n3), .B0(n9), .Y(n4) );
CLKAND2X2TS U3 ( .A(in2[0]), .B(in1[0]), .Y(intadd_27_CI) );
AOI2BB2XLTS U4 ( .B0(in2[5]), .B1(n5), .A0N(n5), .A1N(in2[5]), .Y(n6) );
OAI2BB2XLTS U5 ( .B0(n17), .B1(n16), .A0N(in1[6]), .A1N(in2[6]), .Y(n18) );
OAI32X2TS U6 ( .A0(n14), .A1(n9), .A2(n8), .B0(n13), .B1(n14), .Y(n10) );
AOI22X2TS U7 ( .A0(in2[4]), .A1(in1[4]), .B0(in2[3]), .B1(in1[3]), .Y(n13)
);
OAI211XLTS U8 ( .A0(in1[2]), .A1(in2[2]), .B0(in2[1]), .C0(in1[1]), .Y(n3)
);
AOI2BB1XLTS U9 ( .A0N(in2[0]), .A1N(in1[0]), .B0(intadd_27_CI), .Y(res[0])
);
NOR2X2TS U10 ( .A(in2[4]), .B(in1[4]), .Y(n14) );
AOI21X1TS U11 ( .A0(in1[4]), .A1(in2[4]), .B0(n14), .Y(n2) );
XOR2XLTS U12 ( .A(n2), .B(intadd_27_n1), .Y(res[4]) );
NAND2X1TS U13 ( .A(in1[2]), .B(in2[2]), .Y(n8) );
NOR2X1TS U14 ( .A(in2[3]), .B(in1[3]), .Y(n9) );
AOI21X1TS U15 ( .A0(n4), .A1(n13), .B0(n14), .Y(n7) );
INVX2TS U16 ( .A(in1[5]), .Y(n5) );
XNOR2X1TS U17 ( .A(n7), .B(n6), .Y(res[5]) );
NOR2X1TS U18 ( .A(in1[6]), .B(in2[6]), .Y(n17) );
AOI21X1TS U19 ( .A0(in1[6]), .A1(in2[6]), .B0(n17), .Y(n12) );
AOI222X1TS U20 ( .A0(in2[5]), .A1(in1[5]), .B0(in2[5]), .B1(n10), .C0(in1[5]), .C1(n10), .Y(n11) );
XNOR2X1TS U21 ( .A(n12), .B(n11), .Y(res[6]) );
NOR2X1TS U22 ( .A(n14), .B(n13), .Y(n15) );
AOI222X1TS U23 ( .A0(in1[5]), .A1(n15), .B0(in1[5]), .B1(in2[5]), .C0(n15),
.C1(in2[5]), .Y(n16) );
CMPR32X2TS U24 ( .A(in2[7]), .B(in1[7]), .C(n18), .CO(res[8]), .S(res[7]) );
initial $sdf_annotate("GeAr_N8_R1_P4_syn.sdf");
endmodule
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dpram_32_128x16.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.1 Build 201 11/27/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module dpram_32_128x16 (
byteena_a,
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [3:0] byteena_a;
input [31:0] data;
input [1:0] rdaddress;
input rdclock;
input [3:0] wraddress;
input wrclock;
input wren;
output [127:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "128"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "128"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "2"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "128"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: USED_PORT: byteena_a 0 0 4 0 INPUT VCC byteena_a[3..0]
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0]
// Retrieval info: USED_PORT: rdaddress 0 0 2 0 INPUT NODEFVAL rdaddress[1..0]
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL wraddress[3..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 128 0 @q_b 0 0 128 0
// Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0
// Retrieval info: CONNECT: @address_b 0 0 2 0 rdaddress 0 0 2 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
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`timescale 1ns / 1ps
//-----------------------------------------------
// Company: agh
// Engineer: komorkiewicz
// Create Date: 04/18/2012
// Description: divider core using successive approximation method
//-----------------------------------------------
module divider_28_20 #
(
parameter LATENCY=8,
parameter DIVIDEND_W=28,
parameter DIVISOR_W=20,
parameter QUOTIENT_W=28
)
(
input clk,
input start,
input [DIVIDEND_W-1:0]dividend,
input [DIVISOR_W-1:0]divisor,
output [QUOTIENT_W-1:0]quotient,
output qv
);
//-----------------------------------------------
reg [DIVIDEND_W-1:0] dividend_reg = 0;
reg [DIVISOR_W-1:0] divisor_reg = 0;
reg [QUOTIENT_W-1:0]sar=0;
wire [DIVISOR_W+QUOTIENT_W-1:0]mul_res;
reg [7:0]i;
reg [7:0]lat_cnt;
reg rv_reg=1'b0;
reg [QUOTIENT_W-1:0]result_reg;
//-----------------------------------------------
mult_28_20_lm instance_name
(
.clk(clk),
.a(sar),
.b(divisor_reg),
.p(mul_res)
);
//-----------------------------------------------
parameter IDLE=2'b00;
parameter DIV=2'b01;
parameter NOP=2'b10;
parameter END=2'b11;
reg [1:0]state=IDLE;
//-----------------------------------------------
always @(posedge clk)
begin
rv_reg<=1'b0;
case(state)
IDLE:
begin
i<=QUOTIENT_W-1;
sar<=0;
if(start)
begin
state<=DIV;
dividend_reg <= dividend;
divisor_reg <= divisor;
end
end
DIV:
begin
sar[i]<=1;
lat_cnt<=LATENCY;
state<=NOP;
end
NOP:
begin
lat_cnt<=lat_cnt-1;
if(lat_cnt==0)
begin
if(mul_res>dividend_reg) sar[i]<=0;
i<=i-1;
if(i==0) state<=END;
else state<=DIV;
end
end
END:
begin
rv_reg<=1'b1;
result_reg<=sar;
state<=IDLE;
end
endcase
end
//-----------------------------------------------
assign quotient=result_reg;
assign qv=rv_reg;
//-----------------------------------------------
endmodule
//-----------------------------------------------
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