text
stringlengths
992
1.04M
//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : mig_7series_v4_0_tempmon.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Jul 25 2012 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Monitors chip temperature via the XADC and adjusts the // stage 2 tap values as appropriate. //Reference : //Revision History : //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v4_0_tempmon # ( parameter TCQ = 100, // Register delay (sim only) parameter TEMP_MON_CONTROL = "INTERNAL", // XADC or user temperature source parameter XADC_CLK_PERIOD = 5000, // pS (default to 200 MHz refclk) parameter tTEMPSAMPLE = 10000000 // ps (10 us) ) ( input clk, // Fabric clock input xadc_clk, input rst, // System reset input [11:0] device_temp_i, // User device temperature output [11:0] device_temp // Sampled temperature ); //*************************************************************************** // Function cdiv // Description: // This function performs ceiling division (divide and round-up) // Inputs: // num: integer to be divided // div: divisor // Outputs: // cdiv: result of ceiling division (num/div, rounded up) //*************************************************************************** function integer cdiv (input integer num, input integer div); begin // perform division, then add 1 if and only if remainder is non-zero cdiv = (num/div) + (((num%div)>0) ? 1 : 0); end endfunction // cdiv //*************************************************************************** // Function clogb2 // Description: // This function performs binary logarithm and rounds up // Inputs: // size: integer to perform binary log upon // Outputs: // clogb2: result of binary logarithm, rounded up //*************************************************************************** function integer clogb2 (input integer size); begin size = size - 1; // increment clogb2 from 1 for each bit in size for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1) size = size >> 1; end endfunction // clogb2 // Synchronization registers (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r1; (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r2; (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r3 /* synthesis syn_srlstyle="registers" */; (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r4; (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r5; // Output register (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_r; wire [11:0] device_temp_lcl; reg [3:0] sync_cntr = 4'b0000; reg device_temp_sync_r4_neq_r3; // (* ASYNC_REG = "TRUE" *) reg rst_r1; // (* ASYNC_REG = "TRUE" *) reg rst_r2; // // Synchronization rst to XADC clock domain // always @(posedge xadc_clk) begin // rst_r1 <= rst; // rst_r2 <= rst_r1; // end // Synchronization counter always @(posedge clk) begin device_temp_sync_r1 <= #TCQ device_temp_lcl; device_temp_sync_r2 <= #TCQ device_temp_sync_r1; device_temp_sync_r3 <= #TCQ device_temp_sync_r2; device_temp_sync_r4 <= #TCQ device_temp_sync_r3; device_temp_sync_r5 <= #TCQ device_temp_sync_r4; device_temp_sync_r4_neq_r3 <= #TCQ (device_temp_sync_r4 != device_temp_sync_r3) ? 1'b1 : 1'b0; end always @(posedge clk) if(rst || (device_temp_sync_r4_neq_r3)) sync_cntr <= #TCQ 4'b0000; else if(~&sync_cntr) sync_cntr <= #TCQ sync_cntr + 4'b0001; always @(posedge clk) if(&sync_cntr) device_temp_r <= #TCQ device_temp_sync_r5; assign device_temp = device_temp_r; generate if(TEMP_MON_CONTROL == "EXTERNAL") begin : user_supplied_temperature assign device_temp_lcl = device_temp_i; end else begin : xadc_supplied_temperature // calculate polling timer width and limit localparam nTEMPSAMP = cdiv(tTEMPSAMPLE, XADC_CLK_PERIOD); localparam nTEMPSAMP_CLKS = nTEMPSAMP; localparam nTEMPSAMP_CLKS_M6 = nTEMPSAMP - 6; localparam nTEMPSAMP_CNTR_WIDTH = clogb2(nTEMPSAMP_CLKS); // Temperature sampler FSM encoding localparam INIT_IDLE = 2'b00; localparam REQUEST_READ_TEMP = 2'b01; localparam WAIT_FOR_READ = 2'b10; localparam READ = 2'b11; // polling timer and tick reg [nTEMPSAMP_CNTR_WIDTH-1:0] sample_timer = {nTEMPSAMP_CNTR_WIDTH{1'b0}}; reg sample_timer_en = 1'b0; reg sample_timer_clr = 1'b0; reg sample_en = 1'b0; // Temperature sampler state reg [2:0] tempmon_state = INIT_IDLE; reg [2:0] tempmon_next_state = INIT_IDLE; // XADC interfacing reg xadc_den = 1'b0; wire xadc_drdy; wire [15:0] xadc_do; reg xadc_drdy_r = 1'b0; reg [15:0] xadc_do_r = 1'b0; // Temperature storage reg [11:0] temperature = 12'b0; // Reset sync (* ASYNC_REG = "TRUE" *) reg rst_r1; (* ASYNC_REG = "TRUE" *) reg rst_r2; // Synchronization rst to XADC clock domain always @(posedge xadc_clk) begin rst_r1 <= rst; rst_r2 <= rst_r1; end // XADC polling interval timer always @ (posedge xadc_clk) if(rst_r2 || sample_timer_clr) sample_timer <= #TCQ {nTEMPSAMP_CNTR_WIDTH{1'b0}}; else if(sample_timer_en) sample_timer <= #TCQ sample_timer + 1'b1; // XADC sampler state transition always @(posedge xadc_clk) if(rst_r2) tempmon_state <= #TCQ INIT_IDLE; else tempmon_state <= #TCQ tempmon_next_state; // Sample enable always @(posedge xadc_clk) sample_en <= #TCQ (sample_timer == nTEMPSAMP_CLKS_M6) ? 1'b1 : 1'b0; // XADC sampler next state transition always @(tempmon_state or sample_en or xadc_drdy_r) begin tempmon_next_state = tempmon_state; case(tempmon_state) INIT_IDLE: if(sample_en) tempmon_next_state = REQUEST_READ_TEMP; REQUEST_READ_TEMP: tempmon_next_state = WAIT_FOR_READ; WAIT_FOR_READ: if(xadc_drdy_r) tempmon_next_state = READ; READ: tempmon_next_state = INIT_IDLE; default: tempmon_next_state = INIT_IDLE; endcase end // Sample timer clear always @(posedge xadc_clk) if(rst_r2 || (tempmon_state == WAIT_FOR_READ)) sample_timer_clr <= #TCQ 1'b0; else if(tempmon_state == REQUEST_READ_TEMP) sample_timer_clr <= #TCQ 1'b1; // Sample timer enable always @(posedge xadc_clk) if(rst_r2 || (tempmon_state == REQUEST_READ_TEMP)) sample_timer_en <= #TCQ 1'b0; else if((tempmon_state == INIT_IDLE) || (tempmon_state == READ)) sample_timer_en <= #TCQ 1'b1; // XADC enable always @(posedge xadc_clk) if(rst_r2 || (tempmon_state == WAIT_FOR_READ)) xadc_den <= #TCQ 1'b0; else if(tempmon_state == REQUEST_READ_TEMP) xadc_den <= #TCQ 1'b1; // Register XADC outputs always @(posedge xadc_clk) if(rst_r2) begin xadc_drdy_r <= #TCQ 1'b0; xadc_do_r <= #TCQ 16'b0; end else begin xadc_drdy_r <= #TCQ xadc_drdy; xadc_do_r <= #TCQ xadc_do; end // Store current read value always @(posedge xadc_clk) if(rst_r2) temperature <= #TCQ 12'b0; else if(tempmon_state == READ) temperature <= #TCQ xadc_do_r[15:4]; assign device_temp_lcl = temperature; // XADC: Dual 12-Bit 1MSPS Analog-to-Digital Converter // 7 Series // Xilinx HDL Libraries Guide, version 14.1 XADC #( // INIT_40 - INIT_42: XADC configuration registers .INIT_40(16'h1000), // config reg 0 .INIT_41(16'h2fff), // config reg 1 .INIT_42(16'h0800), // config reg 2 // INIT_48 - INIT_4F: Sequence Registers .INIT_48(16'h0101), // Sequencer channel selection .INIT_49(16'h0000), // Sequencer channel selection .INIT_4A(16'h0100), // Sequencer Average selection .INIT_4B(16'h0000), // Sequencer Average selection .INIT_4C(16'h0000), // Sequencer Bipolar selection .INIT_4D(16'h0000), // Sequencer Bipolar selection .INIT_4E(16'h0000), // Sequencer Acq time selection .INIT_4F(16'h0000), // Sequencer Acq time selection // INIT_50 - INIT_58, INIT5C: Alarm Limit Registers .INIT_50(16'hb5ed), // Temp alarm trigger .INIT_51(16'h57e4), // Vccint upper alarm limit .INIT_52(16'ha147), // Vccaux upper alarm limit .INIT_53(16'hca33), // Temp alarm OT upper .INIT_54(16'ha93a), // Temp alarm reset .INIT_55(16'h52c6), // Vccint lower alarm limit .INIT_56(16'h9555), // Vccaux lower alarm limit .INIT_57(16'hae4e), // Temp alarm OT reset .INIT_58(16'h5999), // VBRAM upper alarm limit .INIT_5C(16'h5111), // VBRAM lower alarm limit // Simulation attributes: Set for proepr simulation behavior .SIM_DEVICE("7SERIES") // Select target device (values) ) XADC_inst ( // ALARMS: 8-bit (each) output: ALM, OT .ALM(), // 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram .OT(), // 1-bit output: Over-Temperature alarm // Dynamic Reconfiguration Port (DRP): 16-bit (each) output: Dynamic Reconfiguration Ports .DO(xadc_do), // 16-bit output: DRP output data bus .DRDY(xadc_drdy), // 1-bit output: DRP data ready // STATUS: 1-bit (each) output: XADC status ports .BUSY(), // 1-bit output: ADC busy output .CHANNEL(), // 5-bit output: Channel selection outputs .EOC(), // 1-bit output: End of Conversion .EOS(), // 1-bit output: End of Sequence .JTAGBUSY(), // 1-bit output: JTAG DRP transaction in progress output .JTAGLOCKED(), // 1-bit output: JTAG requested DRP port lock .JTAGMODIFIED(), // 1-bit output: JTAG Write to the DRP has occurred .MUXADDR(), // 5-bit output: External MUX channel decode // Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0] .VAUXN(16'b0), // 16-bit input: N-side auxiliary analog input .VAUXP(16'b0), // 16-bit input: P-side auxiliary analog input // CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs .CONVST(1'b0), // 1-bit input: Convert start input .CONVSTCLK(1'b0), // 1-bit input: Convert start input .RESET(1'b0), // 1-bit input: Active-high reset // Dedicated Analog Input Pair: 1-bit (each) input: VP/VN .VN(1'b0), // 1-bit input: N-side analog input .VP(1'b0), // 1-bit input: P-side analog input // Dynamic Reconfiguration Port (DRP): 7-bit (each) input: Dynamic Reconfiguration Ports .DADDR(7'b0), // 7-bit input: DRP address bus .DCLK(xadc_clk), // 1-bit input: DRP clock .DEN(xadc_den), // 1-bit input: DRP enable signal .DI(16'b0), // 16-bit input: DRP input data bus .DWE(1'b0) // 1-bit input: DRP write enable ); // End of XADC_inst instantiation end endgenerate endmodule
`include "e200_defines.v" module tb_top(); reg clk; reg lfextclk; reg rst_n; wire hfclk = clk; `define CPU_TOP u_e200_soc_top.u_e200_subsys_top.u_e200_subsys_main.u_e200_cpu_top `define EXU `CPU_TOP.u_e200_cpu.u_e200_core.u_e200_exu `define ITCM `CPU_TOP.u_e200_srams.u_e200_itcm_ram.u_e200_itcm_gnrl_ram.u_sirv_sim_ram `define PC_WRITE_TOHOST `E200_PC_SIZE'h80000086 `define PC_EXT_IRQ_BEFOR_MRET `E200_PC_SIZE'h800000a6 `define PC_SFT_IRQ_BEFOR_MRET `E200_PC_SIZE'h800000be `define PC_TMR_IRQ_BEFOR_MRET `E200_PC_SIZE'h800000d6 `define PC_AFTER_SETMTVEC `E200_PC_SIZE'h8000015C wire [`E200_XLEN-1:0] x3 = `EXU.u_e200_exu_regfile.rf_r[3]; wire [`E200_PC_SIZE-1:0] pc = `EXU.u_e200_exu_commit.alu_cmt_i_pc; wire [`E200_PC_SIZE-1:0] pc_vld = `EXU.u_e200_exu_commit.alu_cmt_i_valid; reg [31:0] pc_write_to_host_cnt; reg [31:0] pc_write_to_host_cycle; reg [31:0] valid_ir_cycle; reg [31:0] cycle_count; reg pc_write_to_host_flag; always @(posedge hfclk or negedge rst_n) begin if(rst_n == 1'b0) begin pc_write_to_host_cnt <= 32'b0; pc_write_to_host_flag <= 1'b0; pc_write_to_host_cycle <= 32'b0; end else if (pc_vld & (pc == `PC_WRITE_TOHOST)) begin pc_write_to_host_cnt <= pc_write_to_host_cnt + 1'b1; pc_write_to_host_flag <= 1'b1; if (pc_write_to_host_flag == 1'b0) begin pc_write_to_host_cycle <= cycle_count; end end end always @(posedge hfclk or negedge rst_n) begin if(rst_n == 1'b0) begin cycle_count <= 32'b0; end else begin cycle_count <= cycle_count + 1'b1; end end wire i_valid = `EXU.i_valid; wire i_ready = `EXU.i_ready; always @(posedge hfclk or negedge rst_n) begin if(rst_n == 1'b0) begin valid_ir_cycle <= 32'b0; end else if(i_valid & i_ready & (pc_write_to_host_flag == 1'b0)) begin valid_ir_cycle <= valid_ir_cycle + 1'b1; end end // Randomly force the external interrupt `define EXT_IRQ u_e200_soc_top.u_e200_subsys_top.u_e200_subsys_main.plic_ext_irq `define SFT_IRQ u_e200_soc_top.u_e200_subsys_top.u_e200_subsys_main.clint_sft_irq `define TMR_IRQ u_e200_soc_top.u_e200_subsys_top.u_e200_subsys_main.clint_tmr_irq `define U_CPU u_e200_soc_top.u_e200_subsys_top.u_e200_subsys_main.u_e200_cpu_top.u_e200_cpu `define ITCM_BUS_ERR `U_CPU.u_e200_itcm_ctrl.sram_icb_rsp_err `define ITCM_BUS_READ `U_CPU.u_e200_itcm_ctrl.sram_icb_rsp_read `define STATUS_MIE `U_CPU.u_e200_core.u_e200_exu.u_e200_exu_commit.u_e200_exu_excp.status_mie_r wire stop_assert_irq = (pc_write_to_host_cnt > 32); reg tb_itcm_bus_err; reg tb_ext_irq; reg tb_tmr_irq; reg tb_sft_irq; initial begin tb_ext_irq = 1'b0; tb_tmr_irq = 1'b0; tb_sft_irq = 1'b0; end `ifdef ENABLE_TB_FORCE initial begin tb_itcm_bus_err = 1'b0; #100 @(pc == `PC_AFTER_SETMTVEC ) // Wait the program goes out the reset_vector program forever begin repeat ($urandom_range(1, 20)) @(posedge clk) tb_itcm_bus_err = 1'b0; // Wait random times repeat ($urandom_range(1, 200)) @(posedge clk) tb_itcm_bus_err = 1'b1; // Wait random times if(stop_assert_irq) begin break; end end end initial begin force `EXT_IRQ = tb_ext_irq; force `SFT_IRQ = tb_sft_irq; force `TMR_IRQ = tb_tmr_irq; // We force the bus-error only when: // It is in common code, not in exception code, by checking MIE bit // It is in read operation, not write, otherwise the test cannot recover force `ITCM_BUS_ERR = tb_itcm_bus_err & `STATUS_MIE & `ITCM_BUS_READ ; end initial begin #100 @(pc == `PC_AFTER_SETMTVEC ) // Wait the program goes out the reset_vector program forever begin repeat ($urandom_range(1, 1000)) @(posedge clk) tb_ext_irq = 1'b0; // Wait random times tb_ext_irq = 1'b1; // assert the irq @((pc == `PC_EXT_IRQ_BEFOR_MRET)) // Wait the program run into the IRQ handler by check PC values tb_ext_irq = 1'b0; if(stop_assert_irq) begin break; end end end initial begin #100 @(pc == `PC_AFTER_SETMTVEC ) // Wait the program goes out the reset_vector program forever begin repeat ($urandom_range(1, 1000)) @(posedge clk) tb_sft_irq = 1'b0; // Wait random times tb_sft_irq = 1'b1; // assert the irq @((pc == `PC_SFT_IRQ_BEFOR_MRET)) // Wait the program run into the IRQ handler by check PC values tb_sft_irq = 1'b0; if(stop_assert_irq) begin break; end end end initial begin #100 @(pc == `PC_AFTER_SETMTVEC ) // Wait the program goes out the reset_vector program forever begin repeat ($urandom_range(1, 1000)) @(posedge clk) tb_tmr_irq = 1'b0; // Wait random times tb_tmr_irq = 1'b1; // assert the irq @((pc == `PC_TMR_IRQ_BEFOR_MRET)) // Wait the program run into the IRQ handler by check PC values tb_tmr_irq = 1'b0; if(stop_assert_irq) begin break; end end end `endif reg[8*300:1] testcase; integer dumpwave; initial begin $display("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"); if($value$plusargs("TESTCASE=%s",testcase))begin $display("TESTCASE=%s",testcase); end pc_write_to_host_flag <=0; clk <=0; lfextclk <=0; rst_n <=0; #120 rst_n <=1; @(pc_write_to_host_cnt == 32'd8) #10 rst_n <=1; `ifdef ENABLE_TB_FORCE @((~tb_tmr_irq) & (~tb_sft_irq) & (~tb_ext_irq)) #10 rst_n <=1;// Wait the interrupt to complete `endif $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~~~~ Test Result Summary ~~~~~~~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); $display("~TESTCASE: %s ~~~~~~~~~~~~~", testcase); $display("~~~~~~~~~~~~~~Total cycle_count value: %d ~~~~~~~~~~~~~", cycle_count); $display("~~~~~~~~~~The valid Instruction Count: %d ~~~~~~~~~~~~~", valid_ir_cycle); $display("~~~~~The test ending reached at cycle: %d ~~~~~~~~~~~~~", pc_write_to_host_cycle); $display("~~~~~~~~~~~~~~~The final x3 Reg value: %d ~~~~~~~~~~~~~", x3); $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); if (x3 == 1) begin $display("~~~~~~~~~~~~~~~~ TEST_PASS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~ ##### ## #### #### ~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~ # # # # # # ~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~ # # # # #### #### ~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~ ##### ###### # #~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~ # # # # # # #~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~ # # # #### #### ~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); end else begin $display("~~~~~~~~~~~~~~~~ TEST_FAIL ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~###### ## # # ~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~# # # # # ~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~##### # # # # ~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~# ###### # # ~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~# # # # # ~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~# # # # ######~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); end #10 $finish; end initial begin #40000000 $display("Time Out !!!"); $finish; end always begin #2 clk <= ~clk; end always begin #33 lfextclk <= ~lfextclk; end initial begin $value$plusargs("DUMPWAVE=%d",dumpwave); if(dumpwave != 0)begin // To add your waveform generation function end end integer i; reg [7:0] itcm_mem [0:(`E200_ITCM_RAM_DP*8)-1]; initial begin $readmemh({testcase, ".verilog"}, itcm_mem); for (i=0;i<(`E200_ITCM_RAM_DP);i=i+1) begin `ITCM.mem_r[i][00+7:00] = itcm_mem[i*8+0]; `ITCM.mem_r[i][08+7:08] = itcm_mem[i*8+1]; `ITCM.mem_r[i][16+7:16] = itcm_mem[i*8+2]; `ITCM.mem_r[i][24+7:24] = itcm_mem[i*8+3]; `ITCM.mem_r[i][32+7:32] = itcm_mem[i*8+4]; `ITCM.mem_r[i][40+7:40] = itcm_mem[i*8+5]; `ITCM.mem_r[i][48+7:48] = itcm_mem[i*8+6]; `ITCM.mem_r[i][56+7:56] = itcm_mem[i*8+7]; end $display("ITCM 0x00: %h", `ITCM.mem_r[8'h00]); $display("ITCM 0x01: %h", `ITCM.mem_r[8'h01]); $display("ITCM 0x02: %h", `ITCM.mem_r[8'h02]); $display("ITCM 0x03: %h", `ITCM.mem_r[8'h03]); $display("ITCM 0x04: %h", `ITCM.mem_r[8'h04]); $display("ITCM 0x05: %h", `ITCM.mem_r[8'h05]); $display("ITCM 0x06: %h", `ITCM.mem_r[8'h06]); $display("ITCM 0x07: %h", `ITCM.mem_r[8'h07]); $display("ITCM 0x16: %h", `ITCM.mem_r[8'h16]); $display("ITCM 0x20: %h", `ITCM.mem_r[8'h20]); end wire jtag_TDI = 1'b0; wire jtag_TDO; wire jtag_TCK = 1'b0; wire jtag_TMS = 1'b0; wire jtag_TRST = 1'b0; wire jtag_DRV_TDO = 1'b0; e200_soc_top u_e200_soc_top( .hfextclk(hfclk), .hfxoscen(), .lfextclk(lfextclk), .lfxoscen(), .io_pads_jtag_TCK_i_ival (jtag_TCK), .io_pads_jtag_TMS_i_ival (jtag_TMS), .io_pads_jtag_TDI_i_ival (jtag_TDI), .io_pads_jtag_TDO_o_oval (jtag_TDO), .io_pads_jtag_TDO_o_oe (), .io_pads_gpio_0_i_ival (1'b1), .io_pads_gpio_0_o_oval (), .io_pads_gpio_0_o_oe (), .io_pads_gpio_0_o_ie (), .io_pads_gpio_0_o_pue (), .io_pads_gpio_0_o_ds (), .io_pads_gpio_1_i_ival (1'b1), .io_pads_gpio_1_o_oval (), .io_pads_gpio_1_o_oe (), .io_pads_gpio_1_o_ie (), .io_pads_gpio_1_o_pue (), .io_pads_gpio_1_o_ds (), .io_pads_gpio_2_i_ival (1'b1), .io_pads_gpio_2_o_oval (), .io_pads_gpio_2_o_oe (), .io_pads_gpio_2_o_ie (), .io_pads_gpio_2_o_pue (), .io_pads_gpio_2_o_ds (), .io_pads_gpio_3_i_ival (1'b1), .io_pads_gpio_3_o_oval (), .io_pads_gpio_3_o_oe (), .io_pads_gpio_3_o_ie (), .io_pads_gpio_3_o_pue (), .io_pads_gpio_3_o_ds (), .io_pads_gpio_4_i_ival (1'b1), .io_pads_gpio_4_o_oval (), .io_pads_gpio_4_o_oe (), .io_pads_gpio_4_o_ie (), .io_pads_gpio_4_o_pue (), .io_pads_gpio_4_o_ds (), .io_pads_gpio_5_i_ival (1'b1), .io_pads_gpio_5_o_oval (), .io_pads_gpio_5_o_oe (), .io_pads_gpio_5_o_ie (), .io_pads_gpio_5_o_pue (), .io_pads_gpio_5_o_ds (), .io_pads_gpio_6_i_ival (1'b1), .io_pads_gpio_6_o_oval (), .io_pads_gpio_6_o_oe (), .io_pads_gpio_6_o_ie (), .io_pads_gpio_6_o_pue (), .io_pads_gpio_6_o_ds (), .io_pads_gpio_7_i_ival (1'b1), .io_pads_gpio_7_o_oval (), .io_pads_gpio_7_o_oe (), .io_pads_gpio_7_o_ie (), .io_pads_gpio_7_o_pue (), .io_pads_gpio_7_o_ds (), .io_pads_gpio_8_i_ival (1'b1), .io_pads_gpio_8_o_oval (), .io_pads_gpio_8_o_oe (), .io_pads_gpio_8_o_ie (), .io_pads_gpio_8_o_pue (), .io_pads_gpio_8_o_ds (), .io_pads_gpio_9_i_ival (1'b1), .io_pads_gpio_9_o_oval (), .io_pads_gpio_9_o_oe (), .io_pads_gpio_9_o_ie (), .io_pads_gpio_9_o_pue (), .io_pads_gpio_9_o_ds (), .io_pads_gpio_10_i_ival (1'b1), .io_pads_gpio_10_o_oval (), .io_pads_gpio_10_o_oe (), .io_pads_gpio_10_o_ie (), .io_pads_gpio_10_o_pue (), .io_pads_gpio_10_o_ds (), .io_pads_gpio_11_i_ival (1'b1), .io_pads_gpio_11_o_oval (), .io_pads_gpio_11_o_oe (), .io_pads_gpio_11_o_ie (), .io_pads_gpio_11_o_pue (), .io_pads_gpio_11_o_ds (), .io_pads_gpio_12_i_ival (1'b1), .io_pads_gpio_12_o_oval (), .io_pads_gpio_12_o_oe (), .io_pads_gpio_12_o_ie (), .io_pads_gpio_12_o_pue (), .io_pads_gpio_12_o_ds (), .io_pads_gpio_13_i_ival (1'b1), .io_pads_gpio_13_o_oval (), .io_pads_gpio_13_o_oe (), .io_pads_gpio_13_o_ie (), .io_pads_gpio_13_o_pue (), .io_pads_gpio_13_o_ds (), .io_pads_gpio_14_i_ival (1'b1), .io_pads_gpio_14_o_oval (), .io_pads_gpio_14_o_oe (), .io_pads_gpio_14_o_ie (), .io_pads_gpio_14_o_pue (), .io_pads_gpio_14_o_ds (), .io_pads_gpio_15_i_ival (1'b1), .io_pads_gpio_15_o_oval (), .io_pads_gpio_15_o_oe (), .io_pads_gpio_15_o_ie (), .io_pads_gpio_15_o_pue (), .io_pads_gpio_15_o_ds (), .io_pads_gpio_16_i_ival (1'b1), .io_pads_gpio_16_o_oval (), .io_pads_gpio_16_o_oe (), .io_pads_gpio_16_o_ie (), .io_pads_gpio_16_o_pue (), .io_pads_gpio_16_o_ds (), .io_pads_gpio_17_i_ival (1'b1), .io_pads_gpio_17_o_oval (), .io_pads_gpio_17_o_oe (), .io_pads_gpio_17_o_ie (), .io_pads_gpio_17_o_pue (), .io_pads_gpio_17_o_ds (), .io_pads_gpio_18_i_ival (1'b1), .io_pads_gpio_18_o_oval (), .io_pads_gpio_18_o_oe (), .io_pads_gpio_18_o_ie (), .io_pads_gpio_18_o_pue (), .io_pads_gpio_18_o_ds (), .io_pads_gpio_19_i_ival (1'b1), .io_pads_gpio_19_o_oval (), .io_pads_gpio_19_o_oe (), .io_pads_gpio_19_o_ie (), .io_pads_gpio_19_o_pue (), .io_pads_gpio_19_o_ds (), .io_pads_gpio_20_i_ival (1'b1), .io_pads_gpio_20_o_oval (), .io_pads_gpio_20_o_oe (), .io_pads_gpio_20_o_ie (), .io_pads_gpio_20_o_pue (), .io_pads_gpio_20_o_ds (), .io_pads_gpio_21_i_ival (1'b1), .io_pads_gpio_21_o_oval (), .io_pads_gpio_21_o_oe (), .io_pads_gpio_21_o_ie (), .io_pads_gpio_21_o_pue (), .io_pads_gpio_21_o_ds (), .io_pads_gpio_22_i_ival (1'b1), .io_pads_gpio_22_o_oval (), .io_pads_gpio_22_o_oe (), .io_pads_gpio_22_o_ie (), .io_pads_gpio_22_o_pue (), .io_pads_gpio_22_o_ds (), .io_pads_gpio_23_i_ival (1'b1), .io_pads_gpio_23_o_oval (), .io_pads_gpio_23_o_oe (), .io_pads_gpio_23_o_ie (), .io_pads_gpio_23_o_pue (), .io_pads_gpio_23_o_ds (), .io_pads_gpio_24_i_ival (1'b1), .io_pads_gpio_24_o_oval (), .io_pads_gpio_24_o_oe (), .io_pads_gpio_24_o_ie (), .io_pads_gpio_24_o_pue (), .io_pads_gpio_24_o_ds (), .io_pads_gpio_25_i_ival (1'b1), .io_pads_gpio_25_o_oval (), .io_pads_gpio_25_o_oe (), .io_pads_gpio_25_o_ie (), .io_pads_gpio_25_o_pue (), .io_pads_gpio_25_o_ds (), .io_pads_gpio_26_i_ival (1'b1), .io_pads_gpio_26_o_oval (), .io_pads_gpio_26_o_oe (), .io_pads_gpio_26_o_ie (), .io_pads_gpio_26_o_pue (), .io_pads_gpio_26_o_ds (), .io_pads_gpio_27_i_ival (1'b1), .io_pads_gpio_27_o_oval (), .io_pads_gpio_27_o_oe (), .io_pads_gpio_27_o_ie (), .io_pads_gpio_27_o_pue (), .io_pads_gpio_27_o_ds (), .io_pads_gpio_28_i_ival (1'b1), .io_pads_gpio_28_o_oval (), .io_pads_gpio_28_o_oe (), .io_pads_gpio_28_o_ie (), .io_pads_gpio_28_o_pue (), .io_pads_gpio_28_o_ds (), .io_pads_gpio_29_i_ival (1'b1), .io_pads_gpio_29_o_oval (), .io_pads_gpio_29_o_oe (), .io_pads_gpio_29_o_ie (), .io_pads_gpio_29_o_pue (), .io_pads_gpio_29_o_ds (), .io_pads_gpio_30_i_ival (1'b1), .io_pads_gpio_30_o_oval (), .io_pads_gpio_30_o_oe (), .io_pads_gpio_30_o_ie (), .io_pads_gpio_30_o_pue (), .io_pads_gpio_30_o_ds (), .io_pads_gpio_31_i_ival (1'b1), .io_pads_gpio_31_o_oval (), .io_pads_gpio_31_o_oe (), .io_pads_gpio_31_o_ie (), .io_pads_gpio_31_o_pue (), .io_pads_gpio_31_o_ds (), .io_pads_qspi_sck_o_oval (), .io_pads_qspi_dq_0_i_ival (1'b1), .io_pads_qspi_dq_0_o_oval (), .io_pads_qspi_dq_0_o_oe (), .io_pads_qspi_dq_0_o_ie (), .io_pads_qspi_dq_0_o_pue (), .io_pads_qspi_dq_0_o_ds (), .io_pads_qspi_dq_1_i_ival (1'b1), .io_pads_qspi_dq_1_o_oval (), .io_pads_qspi_dq_1_o_oe (), .io_pads_qspi_dq_1_o_ie (), .io_pads_qspi_dq_1_o_pue (), .io_pads_qspi_dq_1_o_ds (), .io_pads_qspi_dq_2_i_ival (1'b1), .io_pads_qspi_dq_2_o_oval (), .io_pads_qspi_dq_2_o_oe (), .io_pads_qspi_dq_2_o_ie (), .io_pads_qspi_dq_2_o_pue (), .io_pads_qspi_dq_2_o_ds (), .io_pads_qspi_dq_3_i_ival (1'b1), .io_pads_qspi_dq_3_o_oval (), .io_pads_qspi_dq_3_o_oe (), .io_pads_qspi_dq_3_o_ie (), .io_pads_qspi_dq_3_o_pue (), .io_pads_qspi_dq_3_o_ds (), .io_pads_qspi_cs_0_o_oval (), .io_pads_aon_erst_n_i_ival (rst_n),//This is the real reset, active low .io_pads_aon_pmu_dwakeup_n_i_ival (1'b1), .io_pads_aon_pmu_vddpaden_o_oval (), .io_pads_aon_pmu_padrst_o_oval (), .io_pads_bootrom_n_i_ival (1'b0),// In Simulation we boot from ROM .io_pads_dbgmode0_n_i_ival (1'b1), .io_pads_dbgmode1_n_i_ival (1'b1), .io_pads_dbgmode2_n_i_ival (1'b1) ); endmodule
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 // Date : Thu Jun 01 02:22:05 2017 // Host : GILAMONSTER running 64-bit major release (build 9200) // Command : write_verilog -force -mode synth_stub // c:/ZyboIP/examples/test_cdma/test_cdma.srcs/sources_1/bd/system/ip/system_xlconstant_0_0/system_xlconstant_0_0_stub.v // Design : system_xlconstant_0_0 // Purpose : Stub declaration of top-level module interface // Device : xc7z020clg484-1 // -------------------------------------------------------------------------------- // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. module system_xlconstant_0_0(dout) /* synthesis syn_black_box black_box_pad_pin="dout[0:0]" */; output [0:0]dout; endmodule
// (C) 2001-2015 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // -------------------------------------------------------------------------------- //| Avalon ST Idle Inserter // -------------------------------------------------------------------------------- `timescale 1ns / 100ps module altera_avalon_st_idle_inserter ( // Interface: clk input clk, input reset_n, // Interface: ST in output reg in_ready, input in_valid, input [7: 0] in_data, // Interface: ST out input out_ready, output reg out_valid, output reg [7: 0] out_data ); // --------------------------------------------------------------------- //| Signal Declarations // --------------------------------------------------------------------- reg received_esc; wire escape_char, idle_char; // --------------------------------------------------------------------- //| Thingofamagick // --------------------------------------------------------------------- assign idle_char = (in_data == 8'h4a); assign escape_char = (in_data == 8'h4d); always @(posedge clk or negedge reset_n) begin if (!reset_n) begin received_esc <= 0; end else begin if (in_valid & out_ready) begin if ((idle_char | escape_char) & ~received_esc & out_ready) begin received_esc <= 1; end else begin received_esc <= 0; end end end end always @* begin //we are always valid out_valid = 1'b1; in_ready = out_ready & (~in_valid | ((~idle_char & ~escape_char) | received_esc)); out_data = (~in_valid) ? 8'h4a : //if input is not valid, insert idle (received_esc) ? in_data ^ 8'h20 : //escaped once, send data XOR'd (idle_char | escape_char) ? 8'h4d : //input needs escaping, send escape_char in_data; //send data end endmodule
// *************************************************************************** // *************************************************************************** // Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are // developed independently, and may be accompanied by separate and unique license // terms. // // The user should read each of these license terms, and understand the // freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR // A PARTICULAR PURPOSE. // // Redistribution and use of source or resulting binaries, with or without modification // of this file, are permitted under one of the following two license terms: // // 1. The GNU General Public License version 2 as published by the // Free Software Foundation, which can be found in the top level directory // of this repository (LICENSE_GPL2), and also online at: // <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html> // // OR // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: // https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** // Color Space Conversion, adder. This is a simple adder, but had to be // pipe-lined for faster clock rates. The delay input is delay-matched to // the sum pipe-line stages `timescale 1ps/1ps module ad_csc_1_add #( parameter DELAY_DATA_WIDTH = 16) ( // all signed input clk, input [24:0] data_1, input [24:0] data_2, input [24:0] data_3, input [24:0] data_4, output reg [ 7:0] data_p, // delay match input [DW:0] ddata_in, output reg [DW:0] ddata_out); localparam DW = DELAY_DATA_WIDTH - 1; // internal registers reg [DW:0] p1_ddata = 'd0; reg [24:0] p1_data_1 = 'd0; reg [24:0] p1_data_2 = 'd0; reg [24:0] p1_data_3 = 'd0; reg [24:0] p1_data_4 = 'd0; reg [DW:0] p2_ddata = 'd0; reg [24:0] p2_data_0 = 'd0; reg [24:0] p2_data_1 = 'd0; reg [DW:0] p3_ddata = 'd0; reg [24:0] p3_data = 'd0; // internal signals wire [24:0] p1_data_1_p_s; wire [24:0] p1_data_1_n_s; wire [24:0] p1_data_1_s; wire [24:0] p1_data_2_p_s; wire [24:0] p1_data_2_n_s; wire [24:0] p1_data_2_s; wire [24:0] p1_data_3_p_s; wire [24:0] p1_data_3_n_s; wire [24:0] p1_data_3_s; wire [24:0] p1_data_4_p_s; wire [24:0] p1_data_4_n_s; wire [24:0] p1_data_4_s; // pipe line stage 1, get the two's complement versions assign p1_data_1_p_s = {1'b0, data_1[23:0]}; assign p1_data_1_n_s = ~p1_data_1_p_s + 1'b1; assign p1_data_1_s = (data_1[24] == 1'b1) ? p1_data_1_n_s : p1_data_1_p_s; assign p1_data_2_p_s = {1'b0, data_2[23:0]}; assign p1_data_2_n_s = ~p1_data_2_p_s + 1'b1; assign p1_data_2_s = (data_2[24] == 1'b1) ? p1_data_2_n_s : p1_data_2_p_s; assign p1_data_3_p_s = {1'b0, data_3[23:0]}; assign p1_data_3_n_s = ~p1_data_3_p_s + 1'b1; assign p1_data_3_s = (data_3[24] == 1'b1) ? p1_data_3_n_s : p1_data_3_p_s; assign p1_data_4_p_s = {1'b0, data_4[23:0]}; assign p1_data_4_n_s = ~p1_data_4_p_s + 1'b1; assign p1_data_4_s = (data_4[24] == 1'b1) ? p1_data_4_n_s : p1_data_4_p_s; always @(posedge clk) begin p1_ddata <= ddata_in; p1_data_1 <= p1_data_1_s; p1_data_2 <= p1_data_2_s; p1_data_3 <= p1_data_3_s; p1_data_4 <= p1_data_4_s; end // pipe line stage 2, get the sum (intermediate, 4->2) always @(posedge clk) begin p2_ddata <= p1_ddata; p2_data_0 <= p1_data_1 + p1_data_2; p2_data_1 <= p1_data_3 + p1_data_4; end // pipe line stage 3, get the sum (final, 2->1) always @(posedge clk) begin p3_ddata <= p2_ddata; p3_data <= p2_data_0 + p2_data_1; end // output registers, output is unsigned (0 if sum is < 0) and saturated. // the inputs are expected to be 1.4.20 format (output is 8bits). always @(posedge clk) begin ddata_out <= p3_ddata; if (p3_data[24] == 1'b1) begin data_p <= 8'h00; end else if (p3_data[23:20] == 'd0) begin data_p <= p3_data[19:12]; end else begin data_p <= 8'hff; end end endmodule // *************************************************************************** // ***************************************************************************
module stage_ex( input reset , input [31:0] instruction_i , output [31:0] instruction_o , input [ 7:0] operator_i , output [ 7:0] operator_o , input [ 2:0] category , input [31:0] operand_a_i , output [31:0] operand_a_o , input [31:0] operand_b_i , output [31:0] operand_b_o , input register_write_enable_i , output reg register_write_enable_o , input [ 4:0] register_write_address_i , output reg [ 4:0] register_write_address_o , input [31:0] register_write_data_i , output reg [31:0] register_write_data_o , output reg register_hi_write_enable , output reg [31:0] register_hi_write_data , output reg register_lo_write_enable , output reg [31:0] register_lo_write_data , input mem_register_hi_write_enable, input [31:0] mem_register_hi_write_data , input mem_register_lo_write_enable, input [31:0] mem_register_lo_write_data , input [31:0] wb_register_hi_read_data , input wb_register_hi_write_enable , input [31:0] wb_register_hi_write_data , input [31:0] wb_register_lo_read_data , input wb_register_lo_write_enable , input [31:0] wb_register_lo_write_data , output reg stall_request ); wire [31:0] operand_a_complement = ~operand_a_i + 1; wire [31:0] operand_b_complement = ~operand_b_i + 1; wire [31:0] operand_sum = operand_a_i + (operator_i == `OPERATOR_SLT || operator_i == `OPERATOR_SUB || operator_i == `OPERATOR_SUBU ? operand_b_complement : operand_b_i ); assign instruction_o = instruction_i; assign operator_o = operator_i ; assign operand_a_o = operand_a_i ; assign operand_b_o = operand_b_i ; reg [31:0] register_hi; always @ (*) begin if (reset == `RESET_ENABLE) begin register_hi <= 32'b0; end else if (mem_register_hi_write_enable == `WRITE_ENABLE) begin register_hi <= mem_register_hi_write_data; end else if (wb_register_hi_write_enable == `WRITE_ENABLE) begin register_hi <= wb_register_hi_write_data; end else begin register_hi <= wb_register_hi_read_data; end end reg [31:0] register_lo; always @ (*) begin if (reset == `RESET_ENABLE) begin register_lo <= 32'b0; end else if (mem_register_lo_write_enable == `WRITE_ENABLE) begin register_lo <= mem_register_lo_write_data; end else if (wb_register_lo_write_enable == `WRITE_ENABLE) begin register_lo <= wb_register_lo_write_data; end else begin register_lo <= wb_register_lo_read_data; end end reg [31:0] result_logic; always @ (*) begin if (reset == `RESET_ENABLE) begin result_logic <= 32'b0; end else begin case (operator_i) `OPERATOR_AND : begin result_logic <= operand_a_i & operand_b_i; end `OPERATOR_OR : begin result_logic <= operand_a_i | operand_b_i; end `OPERATOR_XOR : begin result_logic <= operand_a_i ^ operand_b_i; end `OPERATOR_NOR : begin result_logic <= ~(operand_a_i | operand_b_i); end default : begin result_logic <= 32'b0; end endcase end end reg [31:0] result_shift; always @ (*) begin if (reset == `RESET_ENABLE) begin result_shift <= 32'b0; end else begin case (operator_i) `OPERATOR_SLL : begin result_shift <= operand_b_i << operand_a_i[4:0]; end `OPERATOR_SRL : begin result_shift <= operand_b_i >> operand_a_i[4:0]; end `OPERATOR_SRA : begin result_shift <= ({32 {operand_b_i[31]}} << (6'd32 - {1'b0, operand_a_i[4:0]})) | operand_b_i >> operand_a_i[4:0]; end default : begin result_shift <= 32'b0; end endcase end end reg [31:0] result_move; always @ (*) begin if (reset == `RESET_ENABLE) begin result_move <= 32'b0; end else begin case (operator_i) `OPERATOR_MFHI : begin result_move <= register_hi; end `OPERATOR_MFLO : begin result_move <= register_lo; end `OPERATOR_MOVN : begin result_move <= operand_a_i; end `OPERATOR_MOVZ : begin result_move <= operand_a_i; end default : begin result_move <= 32'b0; end endcase end end reg [63:0] result_arithmetic; always @ (*) begin if (reset == `RESET_ENABLE) begin result_arithmetic <= 32'b0; end else begin case (operator_i) `OPERATOR_SLT : begin result_arithmetic <= (operand_a_i[31] == 1'b1 && operand_b_i[31] == 1'b0) || (operand_a_i[31] == 1'b0 && operand_b_i[31] == 1'b0 && operand_sum[31] == 1'b1) || (operand_a_i[31] == 1'b1 && operand_b_i[31] == 1'b1 && operand_sum[31] == 1'b1); end `OPERATOR_SLTU : begin result_arithmetic <= operand_a_i < operand_b_i; end `OPERATOR_ADD, `OPERATOR_ADDU, `OPERATOR_SUB, `OPERATOR_SUBU : begin result_arithmetic <= operand_sum; end `OPERATOR_CLZ : begin result_arithmetic <= operand_a_i[31] == 1'b1 ? 32'd0 : operand_a_i[30] == 1'b1 ? 32'd1 : operand_a_i[29] == 1'b1 ? 32'd2 : operand_a_i[28] == 1'b1 ? 32'd3 : operand_a_i[27] == 1'b1 ? 32'd4 : operand_a_i[26] == 1'b1 ? 32'd5 : operand_a_i[25] == 1'b1 ? 32'd6 : operand_a_i[24] == 1'b1 ? 32'd7 : operand_a_i[23] == 1'b1 ? 32'd8 : operand_a_i[22] == 1'b1 ? 32'd9 : operand_a_i[21] == 1'b1 ? 32'd10 : operand_a_i[20] == 1'b1 ? 32'd11 : operand_a_i[19] == 1'b1 ? 32'd12 : operand_a_i[18] == 1'b1 ? 32'd13 : operand_a_i[17] == 1'b1 ? 32'd14 : operand_a_i[16] == 1'b1 ? 32'd15 : operand_a_i[15] == 1'b1 ? 32'd16 : operand_a_i[14] == 1'b1 ? 32'd17 : operand_a_i[13] == 1'b1 ? 32'd18 : operand_a_i[12] == 1'b1 ? 32'd19 : operand_a_i[11] == 1'b1 ? 32'd20 : operand_a_i[10] == 1'b1 ? 32'd21 : operand_a_i[9] == 1'b1 ? 32'd22 : operand_a_i[8] == 1'b1 ? 32'd23 : operand_a_i[7] == 1'b1 ? 32'd24 : operand_a_i[6] == 1'b1 ? 32'd25 : operand_a_i[5] == 1'b1 ? 32'd26 : operand_a_i[4] == 1'b1 ? 32'd27 : operand_a_i[3] == 1'b1 ? 32'd28 : operand_a_i[2] == 1'b1 ? 32'd29 : operand_a_i[1] == 1'b1 ? 32'd30 : operand_a_i[0] == 1'b1 ? 32'd31 : 32'd32 ; end `OPERATOR_CLO : begin result_arithmetic <= operand_a_i[31] == 1'b0 ? 32'd0 : operand_a_i[30] == 1'b0 ? 32'd1 : operand_a_i[29] == 1'b0 ? 32'd2 : operand_a_i[28] == 1'b0 ? 32'd3 : operand_a_i[27] == 1'b0 ? 32'd4 : operand_a_i[26] == 1'b0 ? 32'd5 : operand_a_i[25] == 1'b0 ? 32'd6 : operand_a_i[24] == 1'b0 ? 32'd7 : operand_a_i[23] == 1'b0 ? 32'd8 : operand_a_i[22] == 1'b0 ? 32'd9 : operand_a_i[21] == 1'b0 ? 32'd10 : operand_a_i[20] == 1'b0 ? 32'd11 : operand_a_i[19] == 1'b0 ? 32'd12 : operand_a_i[18] == 1'b0 ? 32'd13 : operand_a_i[17] == 1'b0 ? 32'd14 : operand_a_i[16] == 1'b0 ? 32'd15 : operand_a_i[15] == 1'b0 ? 32'd16 : operand_a_i[14] == 1'b0 ? 32'd17 : operand_a_i[13] == 1'b0 ? 32'd18 : operand_a_i[12] == 1'b0 ? 32'd19 : operand_a_i[11] == 1'b0 ? 32'd20 : operand_a_i[10] == 1'b0 ? 32'd21 : operand_a_i[9] == 1'b0 ? 32'd22 : operand_a_i[8] == 1'b0 ? 32'd23 : operand_a_i[7] == 1'b0 ? 32'd24 : operand_a_i[6] == 1'b0 ? 32'd25 : operand_a_i[5] == 1'b0 ? 32'd26 : operand_a_i[4] == 1'b0 ? 32'd27 : operand_a_i[3] == 1'b0 ? 32'd28 : operand_a_i[2] == 1'b0 ? 32'd29 : operand_a_i[1] == 1'b0 ? 32'd30 : operand_a_i[0] == 1'b0 ? 32'd31 : 32'd32 ; end `OPERATOR_MULT, `OPERATOR_MUL : begin if (operand_a_i[31] == 1'b0 && operand_b_i[31] == 1'b0) begin result_arithmetic <= operand_a_i * operand_b_i; end else if (operand_a_i[31] == 1'b0 && operand_b_i[31] == 1'b1) begin result_arithmetic <= ~(operand_a_i * operand_b_complement) + 1; end else if (operand_a_i[31] == 1'b1 && operand_b_i[31] == 1'b0) begin result_arithmetic <= ~(operand_a_complement * operand_b_i) + 1; end else if (operand_a_i[31] == 1'b1 && operand_b_i[31] == 1'b1) begin result_arithmetic <= operand_a_complement * operand_b_complement; end end `OPERATOR_MULTU : begin result_arithmetic <= operand_a_i * operand_b_i; end default : begin result_arithmetic <= 32'b0; end endcase end end reg [31:0] result_jump; always @ (*) begin if (reset == `RESET_ENABLE) begin result_jump <= 32'b0; end else begin result_jump <= register_write_data_i; end end always @ (*) begin case (operator_i) `OPERATOR_ADD : begin if ((operand_a_i[31] == 1'b0 && operand_b_i[31] == 1'b0 && operand_sum[31] == 1'b1) || (operand_a_i[31] == 1'b1 && operand_b_i[31] == 1'b1 && operand_sum[31] == 1'b0) ) begin register_write_enable_o <= `WRITE_DISABLE; end else begin register_write_enable_o <= register_write_enable_i; end end `OPERATOR_SUB : begin if ((operand_a_i[31] == 1'b0 && operand_b_complement[31] == 1'b0 && operand_sum[31] == 1'b1) || (operand_a_i[31] == 1'b1 && operand_b_complement[31] == 1'b1 && operand_sum[31] == 1'b0) ) begin register_write_enable_o <= `WRITE_DISABLE; end else begin register_write_enable_o <= register_write_enable_i; end end default : begin register_write_enable_o <= register_write_enable_i; end endcase register_write_address_o <= register_write_address_i; case (category) `CATEGORY_LOGIC : begin register_write_data_o <= result_logic; end `CATEGORY_SHIFT : begin register_write_data_o <= result_shift; end `CATEGORY_MOVE : begin register_write_data_o <= result_move; end `CATEGORY_ARITHMETIC : begin register_write_data_o <= result_arithmetic[31:0]; end `CATEGORY_JUMP : begin register_write_data_o <= result_jump; end default : begin register_write_data_o <= 32'b0; end endcase end always @ (*) begin if (reset == `RESET_ENABLE) begin register_hi_write_enable <= `WRITE_DISABLE; register_hi_write_data <= 32'b0 ; register_lo_write_enable <= `WRITE_DISABLE; register_lo_write_data <= 32'b0 ; end else begin case (operator_i) `OPERATOR_MTHI : begin register_hi_write_enable <= `WRITE_ENABLE ; register_hi_write_data <= operand_a_i ; register_lo_write_enable <= `WRITE_DISABLE; register_lo_write_data <= 32'b0 ; end `OPERATOR_MTLO : begin register_hi_write_enable <= `WRITE_DISABLE; register_hi_write_data <= 32'b0 ; register_lo_write_enable <= `WRITE_ENABLE ; register_lo_write_data <= operand_a_i ; end `OPERATOR_MULT, `OPERATOR_MULTU : begin register_hi_write_enable <= `WRITE_ENABLE ; register_hi_write_data <= result_arithmetic[63:32]; register_lo_write_enable <= `WRITE_ENABLE ; register_lo_write_data <= result_arithmetic[31:0] ; end default : begin register_hi_write_enable <= `WRITE_DISABLE; register_hi_write_data <= 32'b0 ; register_lo_write_enable <= `WRITE_DISABLE; register_lo_write_data <= 32'b0 ; end endcase end end endmodule
/* Copyright 2018 Nuclei System Technology, Inc. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. */ module sirv_flash_qspi( input clock, input reset, output io_port_sck, input io_port_dq_0_i, output io_port_dq_0_o, output io_port_dq_0_oe, input io_port_dq_1_i, output io_port_dq_1_o, output io_port_dq_1_oe, input io_port_dq_2_i, output io_port_dq_2_o, output io_port_dq_2_oe, input io_port_dq_3_i, output io_port_dq_3_o, output io_port_dq_3_oe, output io_port_cs_0, output io_tl_i_0_0, output io_tl_r_0_a_ready, input io_tl_r_0_a_valid, input [2:0] io_tl_r_0_a_bits_opcode, input [2:0] io_tl_r_0_a_bits_param, input [2:0] io_tl_r_0_a_bits_size, input [4:0] io_tl_r_0_a_bits_source, input [28:0] io_tl_r_0_a_bits_address, input [3:0] io_tl_r_0_a_bits_mask, input [31:0] io_tl_r_0_a_bits_data, input io_tl_r_0_b_ready, output io_tl_r_0_b_valid, output [2:0] io_tl_r_0_b_bits_opcode, output [1:0] io_tl_r_0_b_bits_param, output [2:0] io_tl_r_0_b_bits_size, output [4:0] io_tl_r_0_b_bits_source, output [28:0] io_tl_r_0_b_bits_address, output [3:0] io_tl_r_0_b_bits_mask, output [31:0] io_tl_r_0_b_bits_data, output io_tl_r_0_c_ready, input io_tl_r_0_c_valid, input [2:0] io_tl_r_0_c_bits_opcode, input [2:0] io_tl_r_0_c_bits_param, input [2:0] io_tl_r_0_c_bits_size, input [4:0] io_tl_r_0_c_bits_source, input [28:0] io_tl_r_0_c_bits_address, input [31:0] io_tl_r_0_c_bits_data, input io_tl_r_0_c_bits_error, input io_tl_r_0_d_ready, output io_tl_r_0_d_valid, output [2:0] io_tl_r_0_d_bits_opcode, output [1:0] io_tl_r_0_d_bits_param, output [2:0] io_tl_r_0_d_bits_size, output [4:0] io_tl_r_0_d_bits_source, output io_tl_r_0_d_bits_sink, output [1:0] io_tl_r_0_d_bits_addr_lo, output [31:0] io_tl_r_0_d_bits_data, output io_tl_r_0_d_bits_error, output io_tl_r_0_e_ready, input io_tl_r_0_e_valid, input io_tl_r_0_e_bits_sink, output io_tl_f_0_a_ready, input io_tl_f_0_a_valid, input [2:0] io_tl_f_0_a_bits_opcode, input [2:0] io_tl_f_0_a_bits_param, input [2:0] io_tl_f_0_a_bits_size, input [6:0] io_tl_f_0_a_bits_source, input [29:0] io_tl_f_0_a_bits_address, input io_tl_f_0_a_bits_mask, input [7:0] io_tl_f_0_a_bits_data, input io_tl_f_0_b_ready, output io_tl_f_0_b_valid, output [2:0] io_tl_f_0_b_bits_opcode, output [1:0] io_tl_f_0_b_bits_param, output [2:0] io_tl_f_0_b_bits_size, output [6:0] io_tl_f_0_b_bits_source, output [29:0] io_tl_f_0_b_bits_address, output io_tl_f_0_b_bits_mask, output [7:0] io_tl_f_0_b_bits_data, output io_tl_f_0_c_ready, input io_tl_f_0_c_valid, input [2:0] io_tl_f_0_c_bits_opcode, input [2:0] io_tl_f_0_c_bits_param, input [2:0] io_tl_f_0_c_bits_size, input [6:0] io_tl_f_0_c_bits_source, input [29:0] io_tl_f_0_c_bits_address, input [7:0] io_tl_f_0_c_bits_data, input io_tl_f_0_c_bits_error, input io_tl_f_0_d_ready, output io_tl_f_0_d_valid, output [2:0] io_tl_f_0_d_bits_opcode, output [1:0] io_tl_f_0_d_bits_param, output [2:0] io_tl_f_0_d_bits_size, output [6:0] io_tl_f_0_d_bits_source, output io_tl_f_0_d_bits_sink, output io_tl_f_0_d_bits_addr_lo, output [7:0] io_tl_f_0_d_bits_data, output io_tl_f_0_d_bits_error, output io_tl_f_0_e_ready, input io_tl_f_0_e_valid, input io_tl_f_0_e_bits_sink ); wire [1:0] T_1840_fmt_proto; wire T_1840_fmt_endian; wire T_1840_fmt_iodir; wire [3:0] T_1840_fmt_len; wire [11:0] T_1840_sck_div; wire T_1840_sck_pol; wire T_1840_sck_pha; wire T_1840_cs_id; wire T_1840_cs_dflt_0; wire [1:0] T_1840_cs_mode; wire [7:0] T_1840_dla_cssck; wire [7:0] T_1840_dla_sckcs; wire [7:0] T_1840_dla_intercs; wire [7:0] T_1840_dla_interxfr; wire [3:0] T_1840_wm_tx; wire [3:0] T_1840_wm_rx; reg [1:0] ctrl_fmt_proto; reg [31:0] GEN_273; reg ctrl_fmt_endian; reg [31:0] GEN_274; reg ctrl_fmt_iodir; reg [31:0] GEN_275; reg [3:0] ctrl_fmt_len; reg [31:0] GEN_276; reg [11:0] ctrl_sck_div; reg [31:0] GEN_277; reg ctrl_sck_pol; reg [31:0] GEN_278; reg ctrl_sck_pha; reg [31:0] GEN_279; reg ctrl_cs_id; reg [31:0] GEN_280; reg ctrl_cs_dflt_0; reg [31:0] GEN_281; reg [1:0] ctrl_cs_mode; reg [31:0] GEN_282; reg [7:0] ctrl_dla_cssck; reg [31:0] GEN_283; reg [7:0] ctrl_dla_sckcs; reg [31:0] GEN_284; reg [7:0] ctrl_dla_intercs; reg [31:0] GEN_285; reg [7:0] ctrl_dla_interxfr; reg [31:0] GEN_286; reg [3:0] ctrl_wm_tx; reg [31:0] GEN_287; reg [3:0] ctrl_wm_rx; reg [31:0] GEN_288; wire fifo_clock; wire fifo_reset; wire [1:0] fifo_io_ctrl_fmt_proto; wire fifo_io_ctrl_fmt_endian; wire fifo_io_ctrl_fmt_iodir; wire [3:0] fifo_io_ctrl_fmt_len; wire [1:0] fifo_io_ctrl_cs_mode; wire [3:0] fifo_io_ctrl_wm_tx; wire [3:0] fifo_io_ctrl_wm_rx; wire fifo_io_link_tx_ready; wire fifo_io_link_tx_valid; wire [7:0] fifo_io_link_tx_bits; wire fifo_io_link_rx_valid; wire [7:0] fifo_io_link_rx_bits; wire [7:0] fifo_io_link_cnt; wire [1:0] fifo_io_link_fmt_proto; wire fifo_io_link_fmt_endian; wire fifo_io_link_fmt_iodir; wire fifo_io_link_cs_set; wire fifo_io_link_cs_clear; wire fifo_io_link_cs_hold; wire fifo_io_link_active; wire fifo_io_link_lock; wire fifo_io_tx_ready; wire fifo_io_tx_valid; wire [7:0] fifo_io_tx_bits; wire fifo_io_rx_ready; wire fifo_io_rx_valid; wire [7:0] fifo_io_rx_bits; wire fifo_io_ip_txwm; wire fifo_io_ip_rxwm; wire mac_clock; wire mac_reset; wire mac_io_port_sck; wire mac_io_port_dq_0_i; wire mac_io_port_dq_0_o; wire mac_io_port_dq_0_oe; wire mac_io_port_dq_1_i; wire mac_io_port_dq_1_o; wire mac_io_port_dq_1_oe; wire mac_io_port_dq_2_i; wire mac_io_port_dq_2_o; wire mac_io_port_dq_2_oe; wire mac_io_port_dq_3_i; wire mac_io_port_dq_3_o; wire mac_io_port_dq_3_oe; wire mac_io_port_cs_0; wire [11:0] mac_io_ctrl_sck_div; wire mac_io_ctrl_sck_pol; wire mac_io_ctrl_sck_pha; wire [7:0] mac_io_ctrl_dla_cssck; wire [7:0] mac_io_ctrl_dla_sckcs; wire [7:0] mac_io_ctrl_dla_intercs; wire [7:0] mac_io_ctrl_dla_interxfr; wire mac_io_ctrl_cs_id; wire mac_io_ctrl_cs_dflt_0; wire mac_io_link_tx_ready; wire mac_io_link_tx_valid; wire [7:0] mac_io_link_tx_bits; wire mac_io_link_rx_valid; wire [7:0] mac_io_link_rx_bits; wire [7:0] mac_io_link_cnt; wire [1:0] mac_io_link_fmt_proto; wire mac_io_link_fmt_endian; wire mac_io_link_fmt_iodir; wire mac_io_link_cs_set; wire mac_io_link_cs_clear; wire mac_io_link_cs_hold; wire mac_io_link_active; wire T_1906_txwm; wire T_1906_rxwm; wire [1:0] T_1910; wire T_1911; wire T_1912; reg ie_txwm; reg [31:0] GEN_289; reg ie_rxwm; reg [31:0] GEN_290; wire T_1915; wire T_1916; wire T_1917; wire T_1921; wire T_1924; wire flash_clock; wire flash_reset; wire flash_io_en; wire [1:0] flash_io_ctrl_insn_cmd_proto; wire [7:0] flash_io_ctrl_insn_cmd_code; wire flash_io_ctrl_insn_cmd_en; wire [1:0] flash_io_ctrl_insn_addr_proto; wire [2:0] flash_io_ctrl_insn_addr_len; wire [7:0] flash_io_ctrl_insn_pad_code; wire [3:0] flash_io_ctrl_insn_pad_cnt; wire [1:0] flash_io_ctrl_insn_data_proto; wire flash_io_ctrl_fmt_endian; wire flash_io_addr_ready; wire flash_io_addr_valid; wire [31:0] flash_io_addr_bits_next; wire [31:0] flash_io_addr_bits_hold; wire flash_io_data_ready; wire flash_io_data_valid; wire [7:0] flash_io_data_bits; wire flash_io_link_tx_ready; wire flash_io_link_tx_valid; wire [7:0] flash_io_link_tx_bits; wire flash_io_link_rx_valid; wire [7:0] flash_io_link_rx_bits; wire [7:0] flash_io_link_cnt; wire [1:0] flash_io_link_fmt_proto; wire flash_io_link_fmt_endian; wire flash_io_link_fmt_iodir; wire flash_io_link_cs_set; wire flash_io_link_cs_clear; wire flash_io_link_cs_hold; wire flash_io_link_active; wire flash_io_link_lock; wire arb_clock; wire arb_reset; wire arb_io_inner_0_tx_ready; wire arb_io_inner_0_tx_valid; wire [7:0] arb_io_inner_0_tx_bits; wire arb_io_inner_0_rx_valid; wire [7:0] arb_io_inner_0_rx_bits; wire [7:0] arb_io_inner_0_cnt; wire [1:0] arb_io_inner_0_fmt_proto; wire arb_io_inner_0_fmt_endian; wire arb_io_inner_0_fmt_iodir; wire arb_io_inner_0_cs_set; wire arb_io_inner_0_cs_clear; wire arb_io_inner_0_cs_hold; wire arb_io_inner_0_active; wire arb_io_inner_0_lock; wire arb_io_inner_1_tx_ready; wire arb_io_inner_1_tx_valid; wire [7:0] arb_io_inner_1_tx_bits; wire arb_io_inner_1_rx_valid; wire [7:0] arb_io_inner_1_rx_bits; wire [7:0] arb_io_inner_1_cnt; wire [1:0] arb_io_inner_1_fmt_proto; wire arb_io_inner_1_fmt_endian; wire arb_io_inner_1_fmt_iodir; wire arb_io_inner_1_cs_set; wire arb_io_inner_1_cs_clear; wire arb_io_inner_1_cs_hold; wire arb_io_inner_1_active; wire arb_io_inner_1_lock; wire arb_io_outer_tx_ready; wire arb_io_outer_tx_valid; wire [7:0] arb_io_outer_tx_bits; wire arb_io_outer_rx_valid; wire [7:0] arb_io_outer_rx_bits; wire [7:0] arb_io_outer_cnt; wire [1:0] arb_io_outer_fmt_proto; wire arb_io_outer_fmt_endian; wire arb_io_outer_fmt_iodir; wire arb_io_outer_cs_set; wire arb_io_outer_cs_clear; wire arb_io_outer_cs_hold; wire arb_io_outer_active; wire arb_io_sel; reg [2:0] a_opcode; reg [31:0] GEN_291; reg [2:0] a_param; reg [31:0] GEN_292; reg [2:0] a_size; reg [31:0] GEN_293; reg [6:0] a_source; reg [31:0] GEN_294; reg [29:0] a_address; reg [31:0] GEN_295; reg a_mask; reg [31:0] GEN_296; reg [7:0] a_data; reg [31:0] GEN_297; wire T_1935; wire [2:0] GEN_6; wire [2:0] GEN_7; wire [2:0] GEN_8; wire [6:0] GEN_9; wire [29:0] GEN_10; wire GEN_11; wire [7:0] GEN_12; wire [28:0] T_1936; wire [28:0] T_1937; wire [2:0] T_1949_opcode; wire [1:0] T_1949_param; wire [2:0] T_1949_size; wire [6:0] T_1949_source; wire T_1949_sink; wire T_1949_addr_lo; wire [7:0] T_1949_data; wire T_1949_error; wire [1:0] T_1973_cmd_proto; wire [7:0] T_1973_cmd_code; wire T_1973_cmd_en; wire [1:0] T_1973_addr_proto; wire [2:0] T_1973_addr_len; wire [7:0] T_1973_pad_code; wire [3:0] T_1973_pad_cnt; wire [1:0] T_1973_data_proto; reg [1:0] insn_cmd_proto; reg [31:0] GEN_298; reg [7:0] insn_cmd_code; reg [31:0] GEN_299; reg insn_cmd_en; reg [31:0] GEN_300; reg [1:0] insn_addr_proto; reg [31:0] GEN_301; reg [2:0] insn_addr_len; reg [31:0] GEN_302; reg [7:0] insn_pad_code; reg [31:0] GEN_303; reg [3:0] insn_pad_cnt; reg [31:0] GEN_304; reg [1:0] insn_data_proto; reg [31:0] GEN_305; reg flash_en; reg [31:0] GEN_306; wire T_2005; wire T_2029_ready; wire T_2029_valid; wire T_2029_bits_read; wire [9:0] T_2029_bits_index; wire [31:0] T_2029_bits_data; wire [3:0] T_2029_bits_mask; wire [9:0] T_2029_bits_extra; wire T_2046; wire [26:0] T_2047; wire [1:0] T_2048; wire [6:0] T_2049; wire [9:0] T_2050; wire T_2068_ready; wire T_2068_valid; wire T_2068_bits_read; wire [31:0] T_2068_bits_data; wire [9:0] T_2068_bits_extra; wire T_2104_ready; wire T_2104_valid; wire T_2104_bits_read; wire [9:0] T_2104_bits_index; wire [31:0] T_2104_bits_data; wire [3:0] T_2104_bits_mask; wire [9:0] T_2104_bits_extra; wire [9:0] T_2189; wire T_2191; wire [9:0] T_2197; wire [9:0] T_2198; wire T_2200; wire [9:0] T_2206; wire [9:0] T_2207; wire T_2209; wire [9:0] T_2215; wire [9:0] T_2216; wire T_2218; wire [9:0] T_2224; wire [9:0] T_2225; wire T_2227; wire [9:0] T_2233; wire [9:0] T_2234; wire T_2236; wire [9:0] T_2242; wire [9:0] T_2243; wire T_2245; wire [9:0] T_2251; wire [9:0] T_2252; wire T_2254; wire [9:0] T_2260; wire [9:0] T_2261; wire T_2263; wire [9:0] T_2269; wire [9:0] T_2270; wire T_2272; wire [9:0] T_2278; wire [9:0] T_2279; wire T_2281; wire [9:0] T_2287; wire [9:0] T_2288; wire T_2290; wire [9:0] T_2296; wire [9:0] T_2297; wire T_2299; wire [9:0] T_2305; wire [9:0] T_2306; wire T_2308; wire [9:0] T_2314; wire [9:0] T_2315; wire T_2317; wire [9:0] T_2323; wire [9:0] T_2324; wire T_2326; wire T_2334_0; wire T_2334_1; wire T_2334_2; wire T_2334_3; wire T_2334_4; wire T_2334_5; wire T_2334_6; wire T_2334_7; wire T_2334_8; wire T_2334_9; wire T_2334_10; wire T_2334_11; wire T_2334_12; wire T_2334_13; wire T_2334_14; wire T_2334_15; wire T_2334_16; wire T_2334_17; wire T_2334_18; wire T_2334_19; wire T_2334_20; wire T_2334_21; wire T_2334_22; wire T_2334_23; wire T_2334_24; wire T_2334_25; wire T_2334_26; wire T_2334_27; wire T_2334_28; wire T_2334_29; wire T_2334_30; wire T_2334_31; wire T_2334_32; wire T_2334_33; wire T_2334_34; wire T_2339_0; wire T_2339_1; wire T_2339_2; wire T_2339_3; wire T_2339_4; wire T_2339_5; wire T_2339_6; wire T_2339_7; wire T_2339_8; wire T_2339_9; wire T_2339_10; wire T_2339_11; wire T_2339_12; wire T_2339_13; wire T_2339_14; wire T_2339_15; wire T_2339_16; wire T_2339_17; wire T_2339_18; wire T_2339_19; wire T_2339_20; wire T_2339_21; wire T_2339_22; wire T_2339_23; wire T_2339_24; wire T_2339_25; wire T_2339_26; wire T_2339_27; wire T_2339_28; wire T_2339_29; wire T_2339_30; wire T_2339_31; wire T_2339_32; wire T_2339_33; wire T_2339_34; wire T_2344_0; wire T_2344_1; wire T_2344_2; wire T_2344_3; wire T_2344_4; wire T_2344_5; wire T_2344_6; wire T_2344_7; wire T_2344_8; wire T_2344_9; wire T_2344_10; wire T_2344_11; wire T_2344_12; wire T_2344_13; wire T_2344_14; wire T_2344_15; wire T_2344_16; wire T_2344_17; wire T_2344_18; wire T_2344_19; wire T_2344_20; wire T_2344_21; wire T_2344_22; wire T_2344_23; wire T_2344_24; wire T_2344_25; wire T_2344_26; wire T_2344_27; wire T_2344_28; wire T_2344_29; wire T_2344_30; wire T_2344_31; wire T_2344_32; wire T_2344_33; wire T_2344_34; wire T_2349_0; wire T_2349_1; wire T_2349_2; wire T_2349_3; wire T_2349_4; wire T_2349_5; wire T_2349_6; wire T_2349_7; wire T_2349_8; wire T_2349_9; wire T_2349_10; wire T_2349_11; wire T_2349_12; wire T_2349_13; wire T_2349_14; wire T_2349_15; wire T_2349_16; wire T_2349_17; wire T_2349_18; wire T_2349_19; wire T_2349_20; wire T_2349_21; wire T_2349_22; wire T_2349_23; wire T_2349_24; wire T_2349_25; wire T_2349_26; wire T_2349_27; wire T_2349_28; wire T_2349_29; wire T_2349_30; wire T_2349_31; wire T_2349_32; wire T_2349_33; wire T_2349_34; wire T_2354_0; wire T_2354_1; wire T_2354_2; wire T_2354_3; wire T_2354_4; wire T_2354_5; wire T_2354_6; wire T_2354_7; wire T_2354_8; wire T_2354_9; wire T_2354_10; wire T_2354_11; wire T_2354_12; wire T_2354_13; wire T_2354_14; wire T_2354_15; wire T_2354_16; wire T_2354_17; wire T_2354_18; wire T_2354_19; wire T_2354_20; wire T_2354_21; wire T_2354_22; wire T_2354_23; wire T_2354_24; wire T_2354_25; wire T_2354_26; wire T_2354_27; wire T_2354_28; wire T_2354_29; wire T_2354_30; wire T_2354_31; wire T_2354_32; wire T_2354_33; wire T_2354_34; wire T_2359_0; wire T_2359_1; wire T_2359_2; wire T_2359_3; wire T_2359_4; wire T_2359_5; wire T_2359_6; wire T_2359_7; wire T_2359_8; wire T_2359_9; wire T_2359_10; wire T_2359_11; wire T_2359_12; wire T_2359_13; wire T_2359_14; wire T_2359_15; wire T_2359_16; wire T_2359_17; wire T_2359_18; wire T_2359_19; wire T_2359_20; wire T_2359_21; wire T_2359_22; wire T_2359_23; wire T_2359_24; wire T_2359_25; wire T_2359_26; wire T_2359_27; wire T_2359_28; wire T_2359_29; wire T_2359_30; wire T_2359_31; wire T_2359_32; wire T_2359_33; wire T_2359_34; wire T_2364_0; wire T_2364_1; wire T_2364_2; wire T_2364_3; wire T_2364_4; wire T_2364_5; wire T_2364_6; wire T_2364_7; wire T_2364_8; wire T_2364_9; wire T_2364_10; wire T_2364_11; wire T_2364_12; wire T_2364_13; wire T_2364_14; wire T_2364_15; wire T_2364_16; wire T_2364_17; wire T_2364_18; wire T_2364_19; wire T_2364_20; wire T_2364_21; wire T_2364_22; wire T_2364_23; wire T_2364_24; wire T_2364_25; wire T_2364_26; wire T_2364_27; wire T_2364_28; wire T_2364_29; wire T_2364_30; wire T_2364_31; wire T_2364_32; wire T_2364_33; wire T_2364_34; wire T_2369_0; wire T_2369_1; wire T_2369_2; wire T_2369_3; wire T_2369_4; wire T_2369_5; wire T_2369_6; wire T_2369_7; wire T_2369_8; wire T_2369_9; wire T_2369_10; wire T_2369_11; wire T_2369_12; wire T_2369_13; wire T_2369_14; wire T_2369_15; wire T_2369_16; wire T_2369_17; wire T_2369_18; wire T_2369_19; wire T_2369_20; wire T_2369_21; wire T_2369_22; wire T_2369_23; wire T_2369_24; wire T_2369_25; wire T_2369_26; wire T_2369_27; wire T_2369_28; wire T_2369_29; wire T_2369_30; wire T_2369_31; wire T_2369_32; wire T_2369_33; wire T_2369_34; wire T_2531; wire T_2532; wire T_2533; wire T_2534; wire [7:0] T_2538; wire [7:0] T_2542; wire [7:0] T_2546; wire [7:0] T_2550; wire [15:0] T_2551; wire [15:0] T_2552; wire [31:0] T_2553; wire [11:0] T_2577; wire [11:0] T_2581; wire T_2583; wire T_2596; wire [11:0] T_2597; wire [11:0] GEN_13; wire T_2617; wire T_2621; wire T_2623; wire T_2636; wire T_2637; wire GEN_14; wire [7:0] T_2657; wire T_2659; wire [7:0] T_2661; wire T_2663; wire T_2676; wire [7:0] T_2677; wire [7:0] GEN_15; wire [7:0] T_2697; wire [7:0] T_2701; wire T_2703; wire T_2716; wire [7:0] T_2717; wire [7:0] GEN_16; wire [23:0] GEN_226; wire [23:0] T_2732; wire [23:0] GEN_227; wire [23:0] T_2736; wire T_2756; wire GEN_17; wire T_2796; wire GEN_18; wire [2:0] T_2817; wire [2:0] T_2821; wire T_2823; wire T_2836; wire [2:0] T_2837; wire [2:0] GEN_19; wire [3:0] GEN_228; wire [3:0] T_2852; wire [3:0] GEN_229; wire [3:0] T_2856; wire [3:0] T_2857; wire [3:0] T_2861; wire T_2863; wire T_2876; wire [3:0] T_2877; wire [3:0] GEN_20; wire [7:0] GEN_230; wire [7:0] T_2892; wire [7:0] GEN_231; wire [7:0] T_2896; wire [1:0] T_2897; wire [1:0] T_2901; wire T_2903; wire T_2916; wire [1:0] T_2917; wire [1:0] GEN_21; wire [9:0] GEN_232; wire [9:0] T_2932; wire [9:0] GEN_233; wire [9:0] T_2936; wire [1:0] T_2937; wire [1:0] T_2941; wire T_2943; wire T_2956; wire [1:0] T_2957; wire [1:0] GEN_22; wire [11:0] GEN_234; wire [11:0] T_2972; wire [11:0] GEN_235; wire [11:0] T_2976; wire [1:0] T_2977; wire [1:0] T_2981; wire T_2983; wire T_2996; wire [1:0] T_2997; wire [1:0] GEN_23; wire [13:0] GEN_236; wire [13:0] T_3012; wire [13:0] GEN_237; wire [13:0] T_3016; wire T_3036; wire [7:0] GEN_24; wire [23:0] GEN_238; wire [23:0] T_3052; wire [23:0] GEN_239; wire [23:0] T_3056; wire [7:0] T_3057; wire [7:0] T_3061; wire T_3063; wire T_3076; wire [7:0] T_3077; wire [7:0] GEN_25; wire [31:0] GEN_240; wire [31:0] T_3092; wire [31:0] GEN_241; wire [31:0] T_3096; wire [3:0] T_3097; wire [3:0] T_3101; wire T_3103; wire T_3116; wire [3:0] T_3117; wire [3:0] GEN_26; wire T_3172; wire T_3177; wire T_3181; wire T_3183; wire T_3197; wire [1:0] GEN_242; wire [1:0] T_3212; wire [1:0] GEN_243; wire [1:0] T_3216; wire T_3236; wire GEN_27; wire T_3276; wire GEN_28; wire [1:0] GEN_244; wire [1:0] T_3292; wire [1:0] GEN_245; wire [1:0] T_3296; wire [1:0] T_3297; wire [1:0] T_3301; wire T_3303; wire T_3316; wire [1:0] T_3317; wire [1:0] GEN_29; wire T_3356; wire GEN_30; wire T_3396; wire GEN_31; wire [1:0] GEN_246; wire [1:0] T_3412; wire [1:0] GEN_247; wire [1:0] T_3416; wire T_3436; wire [3:0] GEN_32; wire T_3476; wire [31:0] GEN_248; wire [31:0] T_3572; wire T_3596; wire [1:0] GEN_33; wire T_3617; wire T_3621; wire T_3623; wire T_3636; wire T_3637; wire GEN_34; wire [2:0] GEN_249; wire [2:0] T_3652; wire [2:0] GEN_250; wire [2:0] T_3656; wire T_3657; wire T_3661; wire T_3663; wire T_3676; wire T_3677; wire GEN_35; wire [3:0] GEN_251; wire [3:0] T_3692; wire [3:0] GEN_252; wire [3:0] T_3696; wire [3:0] T_3697; wire [3:0] T_3701; wire T_3703; wire T_3716; wire [3:0] T_3717; wire [3:0] GEN_36; wire [19:0] GEN_253; wire [19:0] T_3732; wire [19:0] GEN_254; wire [19:0] T_3736; wire T_3756; wire [7:0] GEN_37; wire T_3796; wire [7:0] GEN_38; wire [23:0] GEN_255; wire [23:0] T_3812; wire [23:0] GEN_256; wire [23:0] T_3816; wire T_3832; wire [7:0] T_3852; wire [30:0] T_3896; wire [31:0] GEN_257; wire [31:0] T_3932; wire [31:0] GEN_258; wire [31:0] T_3936; wire T_3956; wire GEN_39; wire T_3978; wire T_3980; wire T_3982; wire T_3983; wire T_3985; wire T_3993; wire T_3995; wire T_3997; wire T_3999; wire T_4001; wire T_4003; wire T_4014; wire T_4015; wire T_4017; wire T_4019; wire T_4020; wire T_4022; wire T_4036; wire T_4037; wire T_4038; wire T_4039; wire T_4041; wire T_4046; wire T_4047; wire T_4048; wire T_4050; wire T_4052; wire T_4053; wire T_4054; wire T_4056; wire T_4058; wire T_4060; wire T_4062; wire T_4064; wire T_4072; wire T_4074; wire T_4076; wire T_4077; wire T_4078; wire T_4079; wire T_4080; wire T_4081; wire T_4082; wire T_4083; wire T_4085; wire T_4093; wire T_4094; wire T_4096; wire T_4098; wire T_4099; wire T_4101; wire T_4143_0; wire T_4143_1; wire T_4143_2; wire T_4143_3; wire T_4143_4; wire T_4143_5; wire T_4143_6; wire T_4143_7; wire T_4143_8; wire T_4143_9; wire T_4143_10; wire T_4143_11; wire T_4143_12; wire T_4143_13; wire T_4143_14; wire T_4143_15; wire T_4143_16; wire T_4143_17; wire T_4143_18; wire T_4143_19; wire T_4143_20; wire T_4143_21; wire T_4143_22; wire T_4143_23; wire T_4143_24; wire T_4143_25; wire T_4143_26; wire T_4143_27; wire T_4143_28; wire T_4143_29; wire T_4143_30; wire T_4143_31; wire T_4181; wire T_4184; wire T_4186; wire T_4196; wire T_4200; wire T_4204; wire T_4216; wire T_4218; wire T_4221; wire T_4223; wire T_4238; wire T_4239; wire T_4240; wire T_4242; wire T_4248; wire T_4249; wire T_4251; wire T_4254; wire T_4255; wire T_4257; wire T_4261; wire T_4265; wire T_4275; wire T_4278; wire T_4279; wire T_4280; wire T_4281; wire T_4282; wire T_4283; wire T_4284; wire T_4286; wire T_4295; wire T_4297; wire T_4300; wire T_4302; wire T_4344_0; wire T_4344_1; wire T_4344_2; wire T_4344_3; wire T_4344_4; wire T_4344_5; wire T_4344_6; wire T_4344_7; wire T_4344_8; wire T_4344_9; wire T_4344_10; wire T_4344_11; wire T_4344_12; wire T_4344_13; wire T_4344_14; wire T_4344_15; wire T_4344_16; wire T_4344_17; wire T_4344_18; wire T_4344_19; wire T_4344_20; wire T_4344_21; wire T_4344_22; wire T_4344_23; wire T_4344_24; wire T_4344_25; wire T_4344_26; wire T_4344_27; wire T_4344_28; wire T_4344_29; wire T_4344_30; wire T_4344_31; wire T_4382; wire T_4385; wire T_4387; wire T_4397; wire T_4401; wire T_4405; wire T_4417; wire T_4419; wire T_4422; wire T_4424; wire T_4439; wire T_4440; wire T_4441; wire T_4443; wire T_4449; wire T_4450; wire T_4452; wire T_4455; wire T_4456; wire T_4458; wire T_4462; wire T_4466; wire T_4476; wire T_4479; wire T_4480; wire T_4481; wire T_4482; wire T_4483; wire T_4484; wire T_4485; wire T_4487; wire T_4496; wire T_4498; wire T_4501; wire T_4503; wire T_4545_0; wire T_4545_1; wire T_4545_2; wire T_4545_3; wire T_4545_4; wire T_4545_5; wire T_4545_6; wire T_4545_7; wire T_4545_8; wire T_4545_9; wire T_4545_10; wire T_4545_11; wire T_4545_12; wire T_4545_13; wire T_4545_14; wire T_4545_15; wire T_4545_16; wire T_4545_17; wire T_4545_18; wire T_4545_19; wire T_4545_20; wire T_4545_21; wire T_4545_22; wire T_4545_23; wire T_4545_24; wire T_4545_25; wire T_4545_26; wire T_4545_27; wire T_4545_28; wire T_4545_29; wire T_4545_30; wire T_4545_31; wire T_4583; wire T_4586; wire T_4588; wire T_4598; wire T_4602; wire T_4606; wire T_4618; wire T_4620; wire T_4623; wire T_4625; wire T_4640; wire T_4641; wire T_4642; wire T_4644; wire T_4650; wire T_4651; wire T_4653; wire T_4656; wire T_4657; wire T_4659; wire T_4663; wire T_4667; wire T_4677; wire T_4680; wire T_4681; wire T_4682; wire T_4683; wire T_4684; wire T_4685; wire T_4686; wire T_4688; wire T_4697; wire T_4699; wire T_4702; wire T_4704; wire T_4746_0; wire T_4746_1; wire T_4746_2; wire T_4746_3; wire T_4746_4; wire T_4746_5; wire T_4746_6; wire T_4746_7; wire T_4746_8; wire T_4746_9; wire T_4746_10; wire T_4746_11; wire T_4746_12; wire T_4746_13; wire T_4746_14; wire T_4746_15; wire T_4746_16; wire T_4746_17; wire T_4746_18; wire T_4746_19; wire T_4746_20; wire T_4746_21; wire T_4746_22; wire T_4746_23; wire T_4746_24; wire T_4746_25; wire T_4746_26; wire T_4746_27; wire T_4746_28; wire T_4746_29; wire T_4746_30; wire T_4746_31; wire T_4781; wire T_4782; wire T_4783; wire T_4784; wire T_4785; wire [1:0] T_4791; wire [1:0] T_4792; wire [2:0] T_4793; wire [4:0] T_4794; wire GEN_0; wire GEN_40; wire GEN_41; wire GEN_42; wire GEN_43; wire GEN_44; wire GEN_45; wire GEN_46; wire GEN_47; wire GEN_48; wire GEN_49; wire GEN_50; wire GEN_51; wire GEN_52; wire GEN_53; wire GEN_54; wire GEN_55; wire GEN_56; wire GEN_57; wire GEN_58; wire GEN_59; wire GEN_60; wire GEN_61; wire GEN_62; wire GEN_63; wire GEN_64; wire GEN_65; wire GEN_66; wire GEN_67; wire GEN_68; wire GEN_69; wire GEN_70; wire GEN_1; wire GEN_71; wire GEN_72; wire GEN_73; wire GEN_74; wire GEN_75; wire GEN_76; wire GEN_77; wire GEN_78; wire GEN_79; wire GEN_80; wire GEN_81; wire GEN_82; wire GEN_83; wire GEN_84; wire GEN_85; wire GEN_86; wire GEN_87; wire GEN_88; wire GEN_89; wire GEN_90; wire GEN_91; wire GEN_92; wire GEN_93; wire GEN_94; wire GEN_95; wire GEN_96; wire GEN_97; wire GEN_98; wire GEN_99; wire GEN_100; wire GEN_101; wire T_4811; wire GEN_2; wire GEN_102; wire GEN_103; wire GEN_104; wire GEN_105; wire GEN_106; wire GEN_107; wire GEN_108; wire GEN_109; wire GEN_110; wire GEN_111; wire GEN_112; wire GEN_113; wire GEN_114; wire GEN_115; wire GEN_116; wire GEN_117; wire GEN_118; wire GEN_119; wire GEN_120; wire GEN_121; wire GEN_122; wire GEN_123; wire GEN_124; wire GEN_125; wire GEN_126; wire GEN_127; wire GEN_128; wire GEN_129; wire GEN_130; wire GEN_131; wire GEN_132; wire GEN_3; wire GEN_133; wire GEN_134; wire GEN_135; wire GEN_136; wire GEN_137; wire GEN_138; wire GEN_139; wire GEN_140; wire GEN_141; wire GEN_142; wire GEN_143; wire GEN_144; wire GEN_145; wire GEN_146; wire GEN_147; wire GEN_148; wire GEN_149; wire GEN_150; wire GEN_151; wire GEN_152; wire GEN_153; wire GEN_154; wire GEN_155; wire GEN_156; wire GEN_157; wire GEN_158; wire GEN_159; wire GEN_160; wire GEN_161; wire GEN_162; wire GEN_163; wire T_4814; wire T_4815; wire T_4816; wire T_4817; wire T_4818; wire [31:0] T_4820; wire [1:0] T_4821; wire [3:0] T_4823; wire [1:0] T_4824; wire [1:0] T_4825; wire [3:0] T_4826; wire [7:0] T_4827; wire [1:0] T_4829; wire [3:0] T_4830; wire [7:0] T_4834; wire [15:0] T_4835; wire [1:0] T_4836; wire [1:0] T_4837; wire [3:0] T_4838; wire [1:0] T_4839; wire [3:0] T_4841; wire [7:0] T_4842; wire [1:0] T_4843; wire [3:0] T_4845; wire [1:0] T_4846; wire [3:0] T_4848; wire [7:0] T_4849; wire [15:0] T_4850; wire [31:0] T_4851; wire [31:0] T_4852; wire T_4887; wire T_4888; wire T_4889; wire T_4890; wire T_4893; wire T_4894; wire T_4896; wire T_4897; wire T_4898; wire T_4900; wire T_4904; wire T_4906; wire T_4909; wire T_4910; wire T_4916; wire T_4920; wire T_4926; wire T_4969; wire T_4970; wire T_4976; wire T_4980; wire T_4986; wire T_4989; wire T_4990; wire T_4996; wire T_5000; wire T_5006; wire T_5009; wire T_5010; wire T_5016; wire T_5020; wire T_5026; wire T_5089; wire T_5090; wire T_5096; wire T_5100; wire T_5106; wire T_5109; wire T_5110; wire T_5116; wire T_5120; wire T_5126; wire T_5209; wire T_5210; wire T_5216; wire T_5220; wire T_5226; wire T_5249; wire T_5250; wire T_5256; wire T_5260; wire T_5266; wire T_5269; wire T_5270; wire T_5276; wire T_5280; wire T_5286; wire T_5289; wire T_5290; wire T_5296; wire T_5300; wire T_5306; wire T_5309; wire T_5310; wire T_5316; wire T_5320; wire T_5326; wire T_5369; wire T_5370; wire T_5376; wire T_5380; wire T_5386; wire T_5389; wire T_5390; wire T_5396; wire T_5400; wire T_5406; wire T_5449; wire T_5450; wire T_5456; wire T_5460; wire T_5466; wire T_5469; wire T_5470; wire T_5476; wire T_5480; wire T_5486; wire T_5535; wire T_5537; wire T_5539; wire T_5541; wire T_5543; wire T_5545; wire T_5547; wire T_5549; wire T_5555; wire T_5556; wire T_5557; wire T_5558; wire T_5559; wire T_5560; wire T_5561; wire T_5563; wire T_5564; wire T_5565; wire T_5566; wire T_5567; wire T_5568; wire T_5569; wire T_5571; wire T_5572; wire T_5573; wire T_5574; wire T_5575; wire T_5576; wire T_5577; wire T_5579; wire T_5580; wire T_5581; wire T_5582; wire T_5583; wire T_5584; wire T_5585; wire T_5593; wire T_5601; wire T_5609; wire T_5617; wire T_5624; wire T_5625; wire T_5632; wire T_5633; wire T_5640; wire T_5641; wire T_5648; wire T_5649; wire T_5655; wire T_5656; wire T_5657; wire T_5663; wire T_5664; wire T_5665; wire T_5671; wire T_5672; wire T_5673; wire T_5679; wire T_5680; wire T_5681; wire T_5686; wire T_5687; wire T_5688; wire T_5689; wire T_5694; wire T_5695; wire T_5696; wire T_5697; wire T_5702; wire T_5703; wire T_5704; wire T_5705; wire T_5710; wire T_5711; wire T_5712; wire T_5713; wire T_5717; wire T_5718; wire T_5719; wire T_5720; wire T_5721; wire T_5725; wire T_5726; wire T_5727; wire T_5728; wire T_5729; wire T_5733; wire T_5734; wire T_5735; wire T_5736; wire T_5737; wire T_5741; wire T_5742; wire T_5743; wire T_5744; wire T_5745; wire T_5748; wire T_5749; wire T_5750; wire T_5751; wire T_5752; wire T_5753; wire T_5756; wire T_5757; wire T_5758; wire T_5759; wire T_5760; wire T_5761; wire T_5764; wire T_5765; wire T_5766; wire T_5767; wire T_5768; wire T_5769; wire T_5772; wire T_5773; wire T_5774; wire T_5775; wire T_5776; wire T_5777; wire T_5779; wire T_5780; wire T_5781; wire T_5782; wire T_5783; wire T_5784; wire T_5785; wire T_5787; wire T_5788; wire T_5789; wire T_5790; wire T_5791; wire T_5792; wire T_5793; wire T_5795; wire T_5796; wire T_5797; wire T_5798; wire T_5799; wire T_5800; wire T_5801; wire T_5803; wire T_5804; wire T_5805; wire T_5806; wire T_5807; wire T_5808; wire T_5809; wire T_5815; wire T_5817; wire T_5819; wire T_5821; wire T_5823; wire T_5825; wire T_5827; wire T_5829; wire T_5831; wire T_5833; wire T_5835; wire T_5837; wire T_5839; wire T_5841; wire T_5843; wire T_5845; wire T_5851; wire T_5853; wire T_5855; wire T_5857; wire T_5859; wire T_5861; wire T_5863; wire T_5865; wire T_5871; wire T_5872; wire T_5874; wire T_5875; wire T_5877; wire T_5878; wire T_5880; wire T_5881; wire T_5884; wire T_5887; wire T_5890; wire T_5893; wire T_5895; wire T_5896; wire T_5898; wire T_5899; wire T_5901; wire T_5902; wire T_5904; wire T_5905; wire T_5907; wire T_5908; wire T_5909; wire T_5911; wire T_5912; wire T_5913; wire T_5915; wire T_5916; wire T_5917; wire T_5919; wire T_5920; wire T_5921; wire T_5925; wire T_5929; wire T_5933; wire T_5937; wire T_5940; wire T_5941; wire T_5944; wire T_5945; wire T_5948; wire T_5949; wire T_5952; wire T_5953; wire T_5955; wire T_5956; wire T_5957; wire T_5959; wire T_5960; wire T_5961; wire T_5963; wire T_5964; wire T_5965; wire T_5967; wire T_5968; wire T_5969; wire T_5971; wire T_5973; wire T_5975; wire T_5977; wire T_5979; wire T_5981; wire T_5983; wire T_5985; wire T_5987; wire T_5988; wire T_5990; wire T_5991; wire T_5993; wire T_5994; wire T_5996; wire T_5997; wire T_6000; wire T_6003; wire T_6006; wire T_6009; wire T_6011; wire T_6012; wire T_6014; wire T_6015; wire T_6017; wire T_6018; wire T_6020; wire T_6021; wire T_6062_0; wire T_6062_1; wire T_6062_2; wire T_6062_3; wire T_6062_4; wire T_6062_5; wire T_6062_6; wire T_6062_7; wire T_6062_8; wire T_6062_9; wire T_6062_10; wire T_6062_11; wire T_6062_12; wire T_6062_13; wire T_6062_14; wire T_6062_15; wire T_6062_16; wire T_6062_17; wire T_6062_18; wire T_6062_19; wire T_6062_20; wire T_6062_21; wire T_6062_22; wire T_6062_23; wire T_6062_24; wire T_6062_25; wire T_6062_26; wire T_6062_27; wire T_6062_28; wire T_6062_29; wire T_6062_30; wire T_6062_31; wire [31:0] T_6133_0; wire [31:0] T_6133_1; wire [31:0] T_6133_2; wire [31:0] T_6133_3; wire [31:0] T_6133_4; wire [31:0] T_6133_5; wire [31:0] T_6133_6; wire [31:0] T_6133_7; wire [31:0] T_6133_8; wire [31:0] T_6133_9; wire [31:0] T_6133_10; wire [31:0] T_6133_11; wire [31:0] T_6133_12; wire [31:0] T_6133_13; wire [31:0] T_6133_14; wire [31:0] T_6133_15; wire [31:0] T_6133_16; wire [31:0] T_6133_17; wire [31:0] T_6133_18; wire [31:0] T_6133_19; wire [31:0] T_6133_20; wire [31:0] T_6133_21; wire [31:0] T_6133_22; wire [31:0] T_6133_23; wire [31:0] T_6133_24; wire [31:0] T_6133_25; wire [31:0] T_6133_26; wire [31:0] T_6133_27; wire [31:0] T_6133_28; wire [31:0] T_6133_29; wire [31:0] T_6133_30; wire [31:0] T_6133_31; wire GEN_4; wire GEN_164; wire GEN_165; wire GEN_166; wire GEN_167; wire GEN_168; wire GEN_169; wire GEN_170; wire GEN_171; wire GEN_172; wire GEN_173; wire GEN_174; wire GEN_175; wire GEN_176; wire GEN_177; wire GEN_178; wire GEN_179; wire GEN_180; wire GEN_181; wire GEN_182; wire GEN_183; wire GEN_184; wire GEN_185; wire GEN_186; wire GEN_187; wire GEN_188; wire GEN_189; wire GEN_190; wire GEN_191; wire GEN_192; wire GEN_193; wire GEN_194; wire [31:0] GEN_5; wire [31:0] GEN_195; wire [31:0] GEN_196; wire [31:0] GEN_197; wire [31:0] GEN_198; wire [31:0] GEN_199; wire [31:0] GEN_200; wire [31:0] GEN_201; wire [31:0] GEN_202; wire [31:0] GEN_203; wire [31:0] GEN_204; wire [31:0] GEN_205; wire [31:0] GEN_206; wire [31:0] GEN_207; wire [31:0] GEN_208; wire [31:0] GEN_209; wire [31:0] GEN_210; wire [31:0] GEN_211; wire [31:0] GEN_212; wire [31:0] GEN_213; wire [31:0] GEN_214; wire [31:0] GEN_215; wire [31:0] GEN_216; wire [31:0] GEN_217; wire [31:0] GEN_218; wire [31:0] GEN_219; wire [31:0] GEN_220; wire [31:0] GEN_221; wire [31:0] GEN_222; wire [31:0] GEN_223; wire [31:0] GEN_224; wire [31:0] GEN_225; wire [31:0] T_6170; wire [1:0] T_6171; wire [4:0] T_6173; wire [2:0] T_6174; wire [2:0] T_6185_opcode; wire [1:0] T_6185_param; wire [2:0] T_6185_size; wire [4:0] T_6185_source; wire T_6185_sink; wire [1:0] T_6185_addr_lo; wire [31:0] T_6185_data; wire T_6185_error; wire [2:0] GEN_259 = 3'b0; reg [31:0] GEN_307; wire [1:0] GEN_260 = 2'b0; reg [31:0] GEN_308; wire [2:0] GEN_261 = 3'b0; reg [31:0] GEN_309; wire [4:0] GEN_262 = 5'b0; reg [31:0] GEN_310; wire [28:0] GEN_263 = 29'b0; reg [31:0] GEN_311; wire [3:0] GEN_264 = 4'b0; reg [31:0] GEN_312; wire [31:0] GEN_265 = 32'b0; reg [31:0] GEN_313; wire [2:0] GEN_266 = 3'b0; reg [31:0] GEN_314; wire [1:0] GEN_267 = 2'b0; reg [31:0] GEN_315; wire [2:0] GEN_268 = 3'b0; reg [31:0] GEN_316; wire [6:0] GEN_269 = 7'b0; reg [31:0] GEN_317; wire [29:0] GEN_270 = 30'b0; reg [31:0] GEN_318; wire GEN_271 = 1'b0; reg [31:0] GEN_319; wire [7:0] GEN_272 = 8'b0; reg [31:0] GEN_320; sirv_qspi_fifo fifo ( .clock(fifo_clock), .reset(fifo_reset), .io_ctrl_fmt_proto(fifo_io_ctrl_fmt_proto), .io_ctrl_fmt_endian(fifo_io_ctrl_fmt_endian), .io_ctrl_fmt_iodir(fifo_io_ctrl_fmt_iodir), .io_ctrl_fmt_len(fifo_io_ctrl_fmt_len), .io_ctrl_cs_mode(fifo_io_ctrl_cs_mode), .io_ctrl_wm_tx(fifo_io_ctrl_wm_tx), .io_ctrl_wm_rx(fifo_io_ctrl_wm_rx), .io_link_tx_ready(fifo_io_link_tx_ready), .io_link_tx_valid(fifo_io_link_tx_valid), .io_link_tx_bits(fifo_io_link_tx_bits), .io_link_rx_valid(fifo_io_link_rx_valid), .io_link_rx_bits(fifo_io_link_rx_bits), .io_link_cnt(fifo_io_link_cnt), .io_link_fmt_proto(fifo_io_link_fmt_proto), .io_link_fmt_endian(fifo_io_link_fmt_endian), .io_link_fmt_iodir(fifo_io_link_fmt_iodir), .io_link_cs_set(fifo_io_link_cs_set), .io_link_cs_clear(fifo_io_link_cs_clear), .io_link_cs_hold(fifo_io_link_cs_hold), .io_link_active(fifo_io_link_active), .io_link_lock(fifo_io_link_lock), .io_tx_ready(fifo_io_tx_ready), .io_tx_valid(fifo_io_tx_valid), .io_tx_bits(fifo_io_tx_bits), .io_rx_ready(fifo_io_rx_ready), .io_rx_valid(fifo_io_rx_valid), .io_rx_bits(fifo_io_rx_bits), .io_ip_txwm(fifo_io_ip_txwm), .io_ip_rxwm(fifo_io_ip_rxwm) ); sirv_qspi_media mac ( .clock(mac_clock), .reset(mac_reset), .io_port_sck(mac_io_port_sck), .io_port_dq_0_i(mac_io_port_dq_0_i), .io_port_dq_0_o(mac_io_port_dq_0_o), .io_port_dq_0_oe(mac_io_port_dq_0_oe), .io_port_dq_1_i(mac_io_port_dq_1_i), .io_port_dq_1_o(mac_io_port_dq_1_o), .io_port_dq_1_oe(mac_io_port_dq_1_oe), .io_port_dq_2_i(mac_io_port_dq_2_i), .io_port_dq_2_o(mac_io_port_dq_2_o), .io_port_dq_2_oe(mac_io_port_dq_2_oe), .io_port_dq_3_i(mac_io_port_dq_3_i), .io_port_dq_3_o(mac_io_port_dq_3_o), .io_port_dq_3_oe(mac_io_port_dq_3_oe), .io_port_cs_0(mac_io_port_cs_0), .io_ctrl_sck_div(mac_io_ctrl_sck_div), .io_ctrl_sck_pol(mac_io_ctrl_sck_pol), .io_ctrl_sck_pha(mac_io_ctrl_sck_pha), .io_ctrl_dla_cssck(mac_io_ctrl_dla_cssck), .io_ctrl_dla_sckcs(mac_io_ctrl_dla_sckcs), .io_ctrl_dla_intercs(mac_io_ctrl_dla_intercs), .io_ctrl_dla_interxfr(mac_io_ctrl_dla_interxfr), .io_ctrl_cs_id(mac_io_ctrl_cs_id), .io_ctrl_cs_dflt_0(mac_io_ctrl_cs_dflt_0), .io_link_tx_ready(mac_io_link_tx_ready), .io_link_tx_valid(mac_io_link_tx_valid), .io_link_tx_bits(mac_io_link_tx_bits), .io_link_rx_valid(mac_io_link_rx_valid), .io_link_rx_bits(mac_io_link_rx_bits), .io_link_cnt(mac_io_link_cnt), .io_link_fmt_proto(mac_io_link_fmt_proto), .io_link_fmt_endian(mac_io_link_fmt_endian), .io_link_fmt_iodir(mac_io_link_fmt_iodir), .io_link_cs_set(mac_io_link_cs_set), .io_link_cs_clear(mac_io_link_cs_clear), .io_link_cs_hold(mac_io_link_cs_hold), .io_link_active(mac_io_link_active) ); sirv_qspi_flashmap flash ( .clock(flash_clock), .reset(flash_reset), .io_en(flash_io_en), .io_ctrl_insn_cmd_proto(flash_io_ctrl_insn_cmd_proto), .io_ctrl_insn_cmd_code(flash_io_ctrl_insn_cmd_code), .io_ctrl_insn_cmd_en(flash_io_ctrl_insn_cmd_en), .io_ctrl_insn_addr_proto(flash_io_ctrl_insn_addr_proto), .io_ctrl_insn_addr_len(flash_io_ctrl_insn_addr_len), .io_ctrl_insn_pad_code(flash_io_ctrl_insn_pad_code), .io_ctrl_insn_pad_cnt(flash_io_ctrl_insn_pad_cnt), .io_ctrl_insn_data_proto(flash_io_ctrl_insn_data_proto), .io_ctrl_fmt_endian(flash_io_ctrl_fmt_endian), .io_addr_ready(flash_io_addr_ready), .io_addr_valid(flash_io_addr_valid), .io_addr_bits_next(flash_io_addr_bits_next), .io_addr_bits_hold(flash_io_addr_bits_hold), .io_data_ready(flash_io_data_ready), .io_data_valid(flash_io_data_valid), .io_data_bits(flash_io_data_bits), .io_link_tx_ready(flash_io_link_tx_ready), .io_link_tx_valid(flash_io_link_tx_valid), .io_link_tx_bits(flash_io_link_tx_bits), .io_link_rx_valid(flash_io_link_rx_valid), .io_link_rx_bits(flash_io_link_rx_bits), .io_link_cnt(flash_io_link_cnt), .io_link_fmt_proto(flash_io_link_fmt_proto), .io_link_fmt_endian(flash_io_link_fmt_endian), .io_link_fmt_iodir(flash_io_link_fmt_iodir), .io_link_cs_set(flash_io_link_cs_set), .io_link_cs_clear(flash_io_link_cs_clear), .io_link_cs_hold(flash_io_link_cs_hold), .io_link_active(flash_io_link_active), .io_link_lock(flash_io_link_lock) ); sirv_qspi_arbiter arb ( .clock(arb_clock), .reset(arb_reset), .io_inner_0_tx_ready(arb_io_inner_0_tx_ready), .io_inner_0_tx_valid(arb_io_inner_0_tx_valid), .io_inner_0_tx_bits(arb_io_inner_0_tx_bits), .io_inner_0_rx_valid(arb_io_inner_0_rx_valid), .io_inner_0_rx_bits(arb_io_inner_0_rx_bits), .io_inner_0_cnt(arb_io_inner_0_cnt), .io_inner_0_fmt_proto(arb_io_inner_0_fmt_proto), .io_inner_0_fmt_endian(arb_io_inner_0_fmt_endian), .io_inner_0_fmt_iodir(arb_io_inner_0_fmt_iodir), .io_inner_0_cs_set(arb_io_inner_0_cs_set), .io_inner_0_cs_clear(arb_io_inner_0_cs_clear), .io_inner_0_cs_hold(arb_io_inner_0_cs_hold), .io_inner_0_active(arb_io_inner_0_active), .io_inner_0_lock(arb_io_inner_0_lock), .io_inner_1_tx_ready(arb_io_inner_1_tx_ready), .io_inner_1_tx_valid(arb_io_inner_1_tx_valid), .io_inner_1_tx_bits(arb_io_inner_1_tx_bits), .io_inner_1_rx_valid(arb_io_inner_1_rx_valid), .io_inner_1_rx_bits(arb_io_inner_1_rx_bits), .io_inner_1_cnt(arb_io_inner_1_cnt), .io_inner_1_fmt_proto(arb_io_inner_1_fmt_proto), .io_inner_1_fmt_endian(arb_io_inner_1_fmt_endian), .io_inner_1_fmt_iodir(arb_io_inner_1_fmt_iodir), .io_inner_1_cs_set(arb_io_inner_1_cs_set), .io_inner_1_cs_clear(arb_io_inner_1_cs_clear), .io_inner_1_cs_hold(arb_io_inner_1_cs_hold), .io_inner_1_active(arb_io_inner_1_active), .io_inner_1_lock(arb_io_inner_1_lock), .io_outer_tx_ready(arb_io_outer_tx_ready), .io_outer_tx_valid(arb_io_outer_tx_valid), .io_outer_tx_bits(arb_io_outer_tx_bits), .io_outer_rx_valid(arb_io_outer_rx_valid), .io_outer_rx_bits(arb_io_outer_rx_bits), .io_outer_cnt(arb_io_outer_cnt), .io_outer_fmt_proto(arb_io_outer_fmt_proto), .io_outer_fmt_endian(arb_io_outer_fmt_endian), .io_outer_fmt_iodir(arb_io_outer_fmt_iodir), .io_outer_cs_set(arb_io_outer_cs_set), .io_outer_cs_clear(arb_io_outer_cs_clear), .io_outer_cs_hold(arb_io_outer_cs_hold), .io_outer_active(arb_io_outer_active), .io_sel(arb_io_sel) ); assign io_port_sck = mac_io_port_sck; assign io_port_dq_0_o = mac_io_port_dq_0_o; assign io_port_dq_0_oe = mac_io_port_dq_0_oe; assign io_port_dq_1_o = mac_io_port_dq_1_o; assign io_port_dq_1_oe = mac_io_port_dq_1_oe; assign io_port_dq_2_o = mac_io_port_dq_2_o; assign io_port_dq_2_oe = mac_io_port_dq_2_oe; assign io_port_dq_3_o = mac_io_port_dq_3_o; assign io_port_dq_3_oe = mac_io_port_dq_3_oe; assign io_port_cs_0 = mac_io_port_cs_0; assign io_tl_i_0_0 = T_1917; assign io_tl_r_0_a_ready = T_2029_ready; assign io_tl_r_0_b_valid = 1'h0; assign io_tl_r_0_b_bits_opcode = GEN_259; assign io_tl_r_0_b_bits_param = GEN_260; assign io_tl_r_0_b_bits_size = GEN_261; assign io_tl_r_0_b_bits_source = GEN_262; assign io_tl_r_0_b_bits_address = GEN_263; assign io_tl_r_0_b_bits_mask = GEN_264; assign io_tl_r_0_b_bits_data = GEN_265; assign io_tl_r_0_c_ready = 1'h1; assign io_tl_r_0_d_valid = T_2068_valid; assign io_tl_r_0_d_bits_opcode = {{2'd0}, T_2068_bits_read}; assign io_tl_r_0_d_bits_param = T_6185_param; assign io_tl_r_0_d_bits_size = T_6185_size; assign io_tl_r_0_d_bits_source = T_6185_source; assign io_tl_r_0_d_bits_sink = T_6185_sink; assign io_tl_r_0_d_bits_addr_lo = T_6185_addr_lo; assign io_tl_r_0_d_bits_data = T_2068_bits_data; assign io_tl_r_0_d_bits_error = T_6185_error; assign io_tl_r_0_e_ready = 1'h1; assign io_tl_f_0_a_ready = flash_io_addr_ready; assign io_tl_f_0_b_valid = 1'h0; assign io_tl_f_0_b_bits_opcode = GEN_266; assign io_tl_f_0_b_bits_param = GEN_267; assign io_tl_f_0_b_bits_size = GEN_268; assign io_tl_f_0_b_bits_source = GEN_269; assign io_tl_f_0_b_bits_address = GEN_270; assign io_tl_f_0_b_bits_mask = GEN_271; assign io_tl_f_0_b_bits_data = GEN_272; assign io_tl_f_0_c_ready = 1'h1; assign io_tl_f_0_d_valid = flash_io_data_valid; assign io_tl_f_0_d_bits_opcode = T_1949_opcode; assign io_tl_f_0_d_bits_param = T_1949_param; assign io_tl_f_0_d_bits_size = T_1949_size; assign io_tl_f_0_d_bits_source = T_1949_source; assign io_tl_f_0_d_bits_sink = T_1949_sink; assign io_tl_f_0_d_bits_addr_lo = T_1949_addr_lo; assign io_tl_f_0_d_bits_data = T_1949_data; assign io_tl_f_0_d_bits_error = T_1949_error; assign io_tl_f_0_e_ready = 1'h1; assign T_1840_fmt_proto = 2'h0; assign T_1840_fmt_endian = 1'h0; assign T_1840_fmt_iodir = 1'h0; assign T_1840_fmt_len = 4'h8; assign T_1840_sck_div = 12'h3; assign T_1840_sck_pol = 1'h0; assign T_1840_sck_pha = 1'h0; assign T_1840_cs_id = 1'h0; assign T_1840_cs_dflt_0 = 1'h1; assign T_1840_cs_mode = 2'h0; assign T_1840_dla_cssck = 8'h1; assign T_1840_dla_sckcs = 8'h1; assign T_1840_dla_intercs = 8'h1; assign T_1840_dla_interxfr = 8'h0; assign T_1840_wm_tx = 4'h0; assign T_1840_wm_rx = 4'h0; assign fifo_clock = clock; assign fifo_reset = reset; assign fifo_io_ctrl_fmt_proto = ctrl_fmt_proto; assign fifo_io_ctrl_fmt_endian = ctrl_fmt_endian; assign fifo_io_ctrl_fmt_iodir = ctrl_fmt_iodir; assign fifo_io_ctrl_fmt_len = ctrl_fmt_len; assign fifo_io_ctrl_cs_mode = ctrl_cs_mode; assign fifo_io_ctrl_wm_tx = ctrl_wm_tx; assign fifo_io_ctrl_wm_rx = ctrl_wm_rx; assign fifo_io_link_tx_ready = arb_io_inner_1_tx_ready; assign fifo_io_link_rx_valid = arb_io_inner_1_rx_valid; assign fifo_io_link_rx_bits = arb_io_inner_1_rx_bits; assign fifo_io_link_active = arb_io_inner_1_active; assign fifo_io_tx_valid = T_3476; assign fifo_io_tx_bits = T_2677; assign fifo_io_rx_ready = T_3832; assign mac_clock = clock; assign mac_reset = reset; assign mac_io_port_dq_0_i = io_port_dq_0_i; assign mac_io_port_dq_1_i = io_port_dq_1_i; assign mac_io_port_dq_2_i = io_port_dq_2_i; assign mac_io_port_dq_3_i = io_port_dq_3_i; assign mac_io_ctrl_sck_div = ctrl_sck_div; assign mac_io_ctrl_sck_pol = ctrl_sck_pol; assign mac_io_ctrl_sck_pha = ctrl_sck_pha; assign mac_io_ctrl_dla_cssck = ctrl_dla_cssck; assign mac_io_ctrl_dla_sckcs = ctrl_dla_sckcs; assign mac_io_ctrl_dla_intercs = ctrl_dla_intercs; assign mac_io_ctrl_dla_interxfr = ctrl_dla_interxfr; assign mac_io_ctrl_cs_id = ctrl_cs_id; assign mac_io_ctrl_cs_dflt_0 = ctrl_cs_dflt_0; assign mac_io_link_tx_valid = arb_io_outer_tx_valid; assign mac_io_link_tx_bits = arb_io_outer_tx_bits; assign mac_io_link_cnt = arb_io_outer_cnt; assign mac_io_link_fmt_proto = arb_io_outer_fmt_proto; assign mac_io_link_fmt_endian = arb_io_outer_fmt_endian; assign mac_io_link_fmt_iodir = arb_io_outer_fmt_iodir; assign mac_io_link_cs_set = arb_io_outer_cs_set; assign mac_io_link_cs_clear = arb_io_outer_cs_clear; assign mac_io_link_cs_hold = arb_io_outer_cs_hold; assign T_1906_txwm = T_1912; assign T_1906_rxwm = T_1911; assign T_1910 = 2'h0; assign T_1911 = T_1910[0]; assign T_1912 = T_1910[1]; assign T_1915 = fifo_io_ip_txwm & ie_txwm; assign T_1916 = fifo_io_ip_rxwm & ie_rxwm; assign T_1917 = T_1915 | T_1916; assign T_1921 = fifo_io_tx_ready == 1'h0; assign T_1924 = fifo_io_rx_valid == 1'h0; assign flash_clock = clock; assign flash_reset = reset; assign flash_io_en = flash_en; assign flash_io_ctrl_insn_cmd_proto = insn_cmd_proto; assign flash_io_ctrl_insn_cmd_code = insn_cmd_code; assign flash_io_ctrl_insn_cmd_en = insn_cmd_en; assign flash_io_ctrl_insn_addr_proto = insn_addr_proto; assign flash_io_ctrl_insn_addr_len = insn_addr_len; assign flash_io_ctrl_insn_pad_code = insn_pad_code; assign flash_io_ctrl_insn_pad_cnt = insn_pad_cnt; assign flash_io_ctrl_insn_data_proto = insn_data_proto; assign flash_io_ctrl_fmt_endian = ctrl_fmt_endian; assign flash_io_addr_valid = io_tl_f_0_a_valid; assign flash_io_addr_bits_next = {{3'd0}, T_1936}; assign flash_io_addr_bits_hold = {{3'd0}, T_1937}; assign flash_io_data_ready = io_tl_f_0_d_ready; assign flash_io_link_tx_ready = arb_io_inner_0_tx_ready; assign flash_io_link_rx_valid = arb_io_inner_0_rx_valid; assign flash_io_link_rx_bits = arb_io_inner_0_rx_bits; assign flash_io_link_active = arb_io_inner_0_active; assign arb_clock = clock; assign arb_reset = reset; assign arb_io_inner_0_tx_valid = flash_io_link_tx_valid; assign arb_io_inner_0_tx_bits = flash_io_link_tx_bits; assign arb_io_inner_0_cnt = flash_io_link_cnt; assign arb_io_inner_0_fmt_proto = flash_io_link_fmt_proto; assign arb_io_inner_0_fmt_endian = flash_io_link_fmt_endian; assign arb_io_inner_0_fmt_iodir = flash_io_link_fmt_iodir; assign arb_io_inner_0_cs_set = flash_io_link_cs_set; assign arb_io_inner_0_cs_clear = flash_io_link_cs_clear; assign arb_io_inner_0_cs_hold = flash_io_link_cs_hold; assign arb_io_inner_0_lock = flash_io_link_lock; assign arb_io_inner_1_tx_valid = fifo_io_link_tx_valid; assign arb_io_inner_1_tx_bits = fifo_io_link_tx_bits; assign arb_io_inner_1_cnt = fifo_io_link_cnt; assign arb_io_inner_1_fmt_proto = fifo_io_link_fmt_proto; assign arb_io_inner_1_fmt_endian = fifo_io_link_fmt_endian; assign arb_io_inner_1_fmt_iodir = fifo_io_link_fmt_iodir; assign arb_io_inner_1_cs_set = fifo_io_link_cs_set; assign arb_io_inner_1_cs_clear = fifo_io_link_cs_clear; assign arb_io_inner_1_cs_hold = fifo_io_link_cs_hold; assign arb_io_inner_1_lock = fifo_io_link_lock; assign arb_io_outer_tx_ready = mac_io_link_tx_ready; assign arb_io_outer_rx_valid = mac_io_link_rx_valid; assign arb_io_outer_rx_bits = mac_io_link_rx_bits; assign arb_io_outer_active = mac_io_link_active; assign arb_io_sel = T_2005; assign T_1935 = io_tl_f_0_a_ready & io_tl_f_0_a_valid; assign GEN_6 = T_1935 ? io_tl_f_0_a_bits_opcode : a_opcode; assign GEN_7 = T_1935 ? io_tl_f_0_a_bits_param : a_param; assign GEN_8 = T_1935 ? io_tl_f_0_a_bits_size : a_size; assign GEN_9 = T_1935 ? io_tl_f_0_a_bits_source : a_source; assign GEN_10 = T_1935 ? io_tl_f_0_a_bits_address : a_address; assign GEN_11 = T_1935 ? io_tl_f_0_a_bits_mask : a_mask; assign GEN_12 = T_1935 ? io_tl_f_0_a_bits_data : a_data; assign T_1936 = io_tl_f_0_a_bits_address[28:0]; assign T_1937 = a_address[28:0]; assign T_1949_opcode = 3'h1; assign T_1949_param = 2'h0; assign T_1949_size = a_size; assign T_1949_source = a_source; assign T_1949_sink = 1'h0; assign T_1949_addr_lo = 1'h0; assign T_1949_data = flash_io_data_bits; assign T_1949_error = 1'h0; assign T_1973_cmd_proto = 2'h0; assign T_1973_cmd_code = 8'h3; assign T_1973_cmd_en = 1'h1; assign T_1973_addr_proto = 2'h0; assign T_1973_addr_len = 3'h3; assign T_1973_pad_code = 8'h0; assign T_1973_pad_cnt = 4'h0; assign T_1973_data_proto = 2'h0; assign T_2005 = flash_en == 1'h0; assign T_2029_ready = T_4815; assign T_2029_valid = io_tl_r_0_a_valid; assign T_2029_bits_read = T_2046; assign T_2029_bits_index = T_2047[9:0]; assign T_2029_bits_data = io_tl_r_0_a_bits_data; assign T_2029_bits_mask = io_tl_r_0_a_bits_mask; assign T_2029_bits_extra = T_2050; assign T_2046 = io_tl_r_0_a_bits_opcode == 3'h4; assign T_2047 = io_tl_r_0_a_bits_address[28:2]; assign T_2048 = io_tl_r_0_a_bits_address[1:0]; assign T_2049 = {T_2048,io_tl_r_0_a_bits_source}; assign T_2050 = {T_2049,io_tl_r_0_a_bits_size}; assign T_2068_ready = io_tl_r_0_d_ready; assign T_2068_valid = T_4818; assign T_2068_bits_read = T_2104_bits_read; assign T_2068_bits_data = T_6170; assign T_2068_bits_extra = T_2104_bits_extra; assign T_2104_ready = T_4817; assign T_2104_valid = T_4816; assign T_2104_bits_read = T_2029_bits_read; assign T_2104_bits_index = T_2029_bits_index; assign T_2104_bits_data = T_2029_bits_data; assign T_2104_bits_mask = T_2029_bits_mask; assign T_2104_bits_extra = T_2029_bits_extra; assign T_2189 = T_2104_bits_index & 10'h3e0; assign T_2191 = T_2189 == 10'h0; assign T_2197 = T_2104_bits_index ^ 10'h5; assign T_2198 = T_2197 & 10'h3e0; assign T_2200 = T_2198 == 10'h0; assign T_2206 = T_2104_bits_index ^ 10'ha; assign T_2207 = T_2206 & 10'h3e0; assign T_2209 = T_2207 == 10'h0; assign T_2215 = T_2104_bits_index ^ 10'h18; assign T_2216 = T_2215 & 10'h3e0; assign T_2218 = T_2216 == 10'h0; assign T_2224 = T_2104_bits_index ^ 10'h19; assign T_2225 = T_2224 & 10'h3e0; assign T_2227 = T_2225 == 10'h0; assign T_2233 = T_2104_bits_index ^ 10'h14; assign T_2234 = T_2233 & 10'h3e0; assign T_2236 = T_2234 == 10'h0; assign T_2242 = T_2104_bits_index ^ 10'h1d; assign T_2243 = T_2242 & 10'h3e0; assign T_2245 = T_2243 == 10'h0; assign T_2251 = T_2104_bits_index ^ 10'h1; assign T_2252 = T_2251 & 10'h3e0; assign T_2254 = T_2252 == 10'h0; assign T_2260 = T_2104_bits_index ^ 10'h6; assign T_2261 = T_2260 & 10'h3e0; assign T_2263 = T_2261 == 10'h0; assign T_2269 = T_2104_bits_index ^ 10'h1c; assign T_2270 = T_2269 & 10'h3e0; assign T_2272 = T_2270 == 10'h0; assign T_2278 = T_2104_bits_index ^ 10'h15; assign T_2279 = T_2278 & 10'h3e0; assign T_2281 = T_2279 == 10'h0; assign T_2287 = T_2104_bits_index ^ 10'h12; assign T_2288 = T_2287 & 10'h3e0; assign T_2290 = T_2288 == 10'h0; assign T_2296 = T_2104_bits_index ^ 10'h10; assign T_2297 = T_2296 & 10'h3e0; assign T_2299 = T_2297 == 10'h0; assign T_2305 = T_2104_bits_index ^ 10'hb; assign T_2306 = T_2305 & 10'h3e0; assign T_2308 = T_2306 == 10'h0; assign T_2314 = T_2104_bits_index ^ 10'h13; assign T_2315 = T_2314 & 10'h3e0; assign T_2317 = T_2315 == 10'h0; assign T_2323 = T_2104_bits_index ^ 10'h4; assign T_2324 = T_2323 & 10'h3e0; assign T_2326 = T_2324 == 10'h0; assign T_2334_0 = T_4890; assign T_2334_1 = T_4990; assign T_2334_2 = T_5535; assign T_2334_3 = T_5543; assign T_2334_4 = T_5370; assign T_2334_5 = T_5561; assign T_2334_6 = T_5593; assign T_2334_7 = T_5625; assign T_2334_8 = T_5657; assign T_2334_9 = T_5689; assign T_2334_10 = T_5721; assign T_2334_11 = T_5753; assign T_2334_12 = T_5785; assign T_2334_13 = T_5290; assign T_2334_14 = T_5815; assign T_2334_15 = T_5823; assign T_2334_16 = T_5831; assign T_2334_17 = T_5839; assign T_2334_18 = T_5010; assign T_2334_19 = T_5851; assign T_2334_20 = T_5859; assign T_2334_21 = T_5310; assign T_2334_22 = T_5872; assign T_2334_23 = T_5884; assign T_2334_24 = T_5896; assign T_2334_25 = T_5909; assign T_2334_26 = T_5925; assign T_2334_27 = T_5941; assign T_2334_28 = T_5957; assign T_2334_29 = T_5971; assign T_2334_30 = T_5979; assign T_2334_31 = T_5988; assign T_2334_32 = T_6000; assign T_2334_33 = T_6012; assign T_2334_34 = T_4970; assign T_2339_0 = T_4896; assign T_2339_1 = T_4996; assign T_2339_2 = T_5537; assign T_2339_3 = T_5545; assign T_2339_4 = T_5376; assign T_2339_5 = T_5569; assign T_2339_6 = T_5601; assign T_2339_7 = T_5633; assign T_2339_8 = T_5665; assign T_2339_9 = T_5697; assign T_2339_10 = T_5729; assign T_2339_11 = T_5761; assign T_2339_12 = T_5793; assign T_2339_13 = T_5296; assign T_2339_14 = T_5817; assign T_2339_15 = T_5825; assign T_2339_16 = T_5833; assign T_2339_17 = T_5841; assign T_2339_18 = T_5016; assign T_2339_19 = T_5853; assign T_2339_20 = T_5861; assign T_2339_21 = T_5316; assign T_2339_22 = T_5875; assign T_2339_23 = T_5887; assign T_2339_24 = T_5899; assign T_2339_25 = T_5913; assign T_2339_26 = T_5929; assign T_2339_27 = T_5945; assign T_2339_28 = T_5961; assign T_2339_29 = T_5973; assign T_2339_30 = T_5981; assign T_2339_31 = T_5991; assign T_2339_32 = T_6003; assign T_2339_33 = T_6015; assign T_2339_34 = T_4976; assign T_2344_0 = 1'h1; assign T_2344_1 = 1'h1; assign T_2344_2 = 1'h1; assign T_2344_3 = 1'h1; assign T_2344_4 = 1'h1; assign T_2344_5 = 1'h1; assign T_2344_6 = 1'h1; assign T_2344_7 = 1'h1; assign T_2344_8 = 1'h1; assign T_2344_9 = 1'h1; assign T_2344_10 = 1'h1; assign T_2344_11 = 1'h1; assign T_2344_12 = 1'h1; assign T_2344_13 = 1'h1; assign T_2344_14 = 1'h1; assign T_2344_15 = 1'h1; assign T_2344_16 = 1'h1; assign T_2344_17 = 1'h1; assign T_2344_18 = 1'h1; assign T_2344_19 = 1'h1; assign T_2344_20 = 1'h1; assign T_2344_21 = 1'h1; assign T_2344_22 = 1'h1; assign T_2344_23 = 1'h1; assign T_2344_24 = 1'h1; assign T_2344_25 = 1'h1; assign T_2344_26 = 1'h1; assign T_2344_27 = 1'h1; assign T_2344_28 = 1'h1; assign T_2344_29 = 1'h1; assign T_2344_30 = 1'h1; assign T_2344_31 = 1'h1; assign T_2344_32 = 1'h1; assign T_2344_33 = 1'h1; assign T_2344_34 = 1'h1; assign T_2349_0 = 1'h1; assign T_2349_1 = 1'h1; assign T_2349_2 = 1'h1; assign T_2349_3 = 1'h1; assign T_2349_4 = 1'h1; assign T_2349_5 = 1'h1; assign T_2349_6 = 1'h1; assign T_2349_7 = 1'h1; assign T_2349_8 = 1'h1; assign T_2349_9 = 1'h1; assign T_2349_10 = 1'h1; assign T_2349_11 = 1'h1; assign T_2349_12 = 1'h1; assign T_2349_13 = 1'h1; assign T_2349_14 = 1'h1; assign T_2349_15 = 1'h1; assign T_2349_16 = 1'h1; assign T_2349_17 = 1'h1; assign T_2349_18 = 1'h1; assign T_2349_19 = 1'h1; assign T_2349_20 = 1'h1; assign T_2349_21 = 1'h1; assign T_2349_22 = 1'h1; assign T_2349_23 = 1'h1; assign T_2349_24 = 1'h1; assign T_2349_25 = 1'h1; assign T_2349_26 = 1'h1; assign T_2349_27 = 1'h1; assign T_2349_28 = 1'h1; assign T_2349_29 = 1'h1; assign T_2349_30 = 1'h1; assign T_2349_31 = 1'h1; assign T_2349_32 = 1'h1; assign T_2349_33 = 1'h1; assign T_2349_34 = 1'h1; assign T_2354_0 = 1'h1; assign T_2354_1 = 1'h1; assign T_2354_2 = 1'h1; assign T_2354_3 = 1'h1; assign T_2354_4 = 1'h1; assign T_2354_5 = 1'h1; assign T_2354_6 = 1'h1; assign T_2354_7 = 1'h1; assign T_2354_8 = 1'h1; assign T_2354_9 = 1'h1; assign T_2354_10 = 1'h1; assign T_2354_11 = 1'h1; assign T_2354_12 = 1'h1; assign T_2354_13 = 1'h1; assign T_2354_14 = 1'h1; assign T_2354_15 = 1'h1; assign T_2354_16 = 1'h1; assign T_2354_17 = 1'h1; assign T_2354_18 = 1'h1; assign T_2354_19 = 1'h1; assign T_2354_20 = 1'h1; assign T_2354_21 = 1'h1; assign T_2354_22 = 1'h1; assign T_2354_23 = 1'h1; assign T_2354_24 = 1'h1; assign T_2354_25 = 1'h1; assign T_2354_26 = 1'h1; assign T_2354_27 = 1'h1; assign T_2354_28 = 1'h1; assign T_2354_29 = 1'h1; assign T_2354_30 = 1'h1; assign T_2354_31 = 1'h1; assign T_2354_32 = 1'h1; assign T_2354_33 = 1'h1; assign T_2354_34 = 1'h1; assign T_2359_0 = 1'h1; assign T_2359_1 = 1'h1; assign T_2359_2 = 1'h1; assign T_2359_3 = 1'h1; assign T_2359_4 = 1'h1; assign T_2359_5 = 1'h1; assign T_2359_6 = 1'h1; assign T_2359_7 = 1'h1; assign T_2359_8 = 1'h1; assign T_2359_9 = 1'h1; assign T_2359_10 = 1'h1; assign T_2359_11 = 1'h1; assign T_2359_12 = 1'h1; assign T_2359_13 = 1'h1; assign T_2359_14 = 1'h1; assign T_2359_15 = 1'h1; assign T_2359_16 = 1'h1; assign T_2359_17 = 1'h1; assign T_2359_18 = 1'h1; assign T_2359_19 = 1'h1; assign T_2359_20 = 1'h1; assign T_2359_21 = 1'h1; assign T_2359_22 = 1'h1; assign T_2359_23 = 1'h1; assign T_2359_24 = 1'h1; assign T_2359_25 = 1'h1; assign T_2359_26 = 1'h1; assign T_2359_27 = 1'h1; assign T_2359_28 = 1'h1; assign T_2359_29 = 1'h1; assign T_2359_30 = 1'h1; assign T_2359_31 = 1'h1; assign T_2359_32 = 1'h1; assign T_2359_33 = 1'h1; assign T_2359_34 = 1'h1; assign T_2364_0 = T_4900; assign T_2364_1 = T_5000; assign T_2364_2 = T_5539; assign T_2364_3 = T_5547; assign T_2364_4 = T_5380; assign T_2364_5 = T_5577; assign T_2364_6 = T_5609; assign T_2364_7 = T_5641; assign T_2364_8 = T_5673; assign T_2364_9 = T_5705; assign T_2364_10 = T_5737; assign T_2364_11 = T_5769; assign T_2364_12 = T_5801; assign T_2364_13 = T_5300; assign T_2364_14 = T_5819; assign T_2364_15 = T_5827; assign T_2364_16 = T_5835; assign T_2364_17 = T_5843; assign T_2364_18 = T_5020; assign T_2364_19 = T_5855; assign T_2364_20 = T_5863; assign T_2364_21 = T_5320; assign T_2364_22 = T_5878; assign T_2364_23 = T_5890; assign T_2364_24 = T_5902; assign T_2364_25 = T_5917; assign T_2364_26 = T_5933; assign T_2364_27 = T_5949; assign T_2364_28 = T_5965; assign T_2364_29 = T_5975; assign T_2364_30 = T_5983; assign T_2364_31 = T_5994; assign T_2364_32 = T_6006; assign T_2364_33 = T_6018; assign T_2364_34 = T_4980; assign T_2369_0 = T_4906; assign T_2369_1 = T_5006; assign T_2369_2 = T_5541; assign T_2369_3 = T_5549; assign T_2369_4 = T_5386; assign T_2369_5 = T_5585; assign T_2369_6 = T_5617; assign T_2369_7 = T_5649; assign T_2369_8 = T_5681; assign T_2369_9 = T_5713; assign T_2369_10 = T_5745; assign T_2369_11 = T_5777; assign T_2369_12 = T_5809; assign T_2369_13 = T_5306; assign T_2369_14 = T_5821; assign T_2369_15 = T_5829; assign T_2369_16 = T_5837; assign T_2369_17 = T_5845; assign T_2369_18 = T_5026; assign T_2369_19 = T_5857; assign T_2369_20 = T_5865; assign T_2369_21 = T_5326; assign T_2369_22 = T_5881; assign T_2369_23 = T_5893; assign T_2369_24 = T_5905; assign T_2369_25 = T_5921; assign T_2369_26 = T_5937; assign T_2369_27 = T_5953; assign T_2369_28 = T_5969; assign T_2369_29 = T_5977; assign T_2369_30 = T_5985; assign T_2369_31 = T_5997; assign T_2369_32 = T_6009; assign T_2369_33 = T_6021; assign T_2369_34 = T_4986; assign T_2531 = T_2104_bits_mask[0]; assign T_2532 = T_2104_bits_mask[1]; assign T_2533 = T_2104_bits_mask[2]; assign T_2534 = T_2104_bits_mask[3]; assign T_2538 = T_2531 ? 8'hff : 8'h0; assign T_2542 = T_2532 ? 8'hff : 8'h0; assign T_2546 = T_2533 ? 8'hff : 8'h0; assign T_2550 = T_2534 ? 8'hff : 8'h0; assign T_2551 = {T_2542,T_2538}; assign T_2552 = {T_2550,T_2546}; assign T_2553 = {T_2552,T_2551}; assign T_2577 = T_2553[11:0]; assign T_2581 = ~ T_2577; assign T_2583 = T_2581 == 12'h0; assign T_2596 = T_2369_0 & T_2583; assign T_2597 = T_2104_bits_data[11:0]; assign GEN_13 = T_2596 ? T_2597 : ctrl_sck_div; assign T_2617 = T_2553[0]; assign T_2621 = ~ T_2617; assign T_2623 = T_2621 == 1'h0; assign T_2636 = T_2369_1 & T_2623; assign T_2637 = T_2104_bits_data[0]; assign GEN_14 = T_2636 ? T_2637 : ctrl_cs_dflt_0; assign T_2657 = T_2553[7:0]; assign T_2659 = T_2657 != 8'h0; assign T_2661 = ~ T_2657; assign T_2663 = T_2661 == 8'h0; assign T_2676 = T_2369_2 & T_2663; assign T_2677 = T_2104_bits_data[7:0]; assign GEN_15 = T_2676 ? T_2677 : ctrl_dla_cssck; assign T_2697 = T_2553[23:16]; assign T_2701 = ~ T_2697; assign T_2703 = T_2701 == 8'h0; assign T_2716 = T_2369_3 & T_2703; assign T_2717 = T_2104_bits_data[23:16]; assign GEN_16 = T_2716 ? T_2717 : ctrl_dla_sckcs; assign GEN_226 = {{16'd0}, ctrl_dla_sckcs}; assign T_2732 = GEN_226 << 16; assign GEN_227 = {{16'd0}, ctrl_dla_cssck}; assign T_2736 = GEN_227 | T_2732; assign T_2756 = T_2369_4 & T_2623; assign GEN_17 = T_2756 ? T_2637 : flash_en; assign T_2796 = T_2369_5 & T_2623; assign GEN_18 = T_2796 ? T_2637 : insn_cmd_en; assign T_2817 = T_2553[3:1]; assign T_2821 = ~ T_2817; assign T_2823 = T_2821 == 3'h0; assign T_2836 = T_2369_6 & T_2823; assign T_2837 = T_2104_bits_data[3:1]; assign GEN_19 = T_2836 ? T_2837 : insn_addr_len; assign GEN_228 = {{1'd0}, insn_addr_len}; assign T_2852 = GEN_228 << 1; assign GEN_229 = {{3'd0}, insn_cmd_en}; assign T_2856 = GEN_229 | T_2852; assign T_2857 = T_2553[7:4]; assign T_2861 = ~ T_2857; assign T_2863 = T_2861 == 4'h0; assign T_2876 = T_2369_7 & T_2863; assign T_2877 = T_2104_bits_data[7:4]; assign GEN_20 = T_2876 ? T_2877 : insn_pad_cnt; assign GEN_230 = {{4'd0}, insn_pad_cnt}; assign T_2892 = GEN_230 << 4; assign GEN_231 = {{4'd0}, T_2856}; assign T_2896 = GEN_231 | T_2892; assign T_2897 = T_2553[9:8]; assign T_2901 = ~ T_2897; assign T_2903 = T_2901 == 2'h0; assign T_2916 = T_2369_8 & T_2903; assign T_2917 = T_2104_bits_data[9:8]; assign GEN_21 = T_2916 ? T_2917 : insn_cmd_proto; assign GEN_232 = {{8'd0}, insn_cmd_proto}; assign T_2932 = GEN_232 << 8; assign GEN_233 = {{2'd0}, T_2896}; assign T_2936 = GEN_233 | T_2932; assign T_2937 = T_2553[11:10]; assign T_2941 = ~ T_2937; assign T_2943 = T_2941 == 2'h0; assign T_2956 = T_2369_9 & T_2943; assign T_2957 = T_2104_bits_data[11:10]; assign GEN_22 = T_2956 ? T_2957 : insn_addr_proto; assign GEN_234 = {{10'd0}, insn_addr_proto}; assign T_2972 = GEN_234 << 10; assign GEN_235 = {{2'd0}, T_2936}; assign T_2976 = GEN_235 | T_2972; assign T_2977 = T_2553[13:12]; assign T_2981 = ~ T_2977; assign T_2983 = T_2981 == 2'h0; assign T_2996 = T_2369_10 & T_2983; assign T_2997 = T_2104_bits_data[13:12]; assign GEN_23 = T_2996 ? T_2997 : insn_data_proto; assign GEN_236 = {{12'd0}, insn_data_proto}; assign T_3012 = GEN_236 << 12; assign GEN_237 = {{2'd0}, T_2976}; assign T_3016 = GEN_237 | T_3012; assign T_3036 = T_2369_11 & T_2703; assign GEN_24 = T_3036 ? T_2717 : insn_cmd_code; assign GEN_238 = {{16'd0}, insn_cmd_code}; assign T_3052 = GEN_238 << 16; assign GEN_239 = {{10'd0}, T_3016}; assign T_3056 = GEN_239 | T_3052; assign T_3057 = T_2553[31:24]; assign T_3061 = ~ T_3057; assign T_3063 = T_3061 == 8'h0; assign T_3076 = T_2369_12 & T_3063; assign T_3077 = T_2104_bits_data[31:24]; assign GEN_25 = T_3076 ? T_3077 : insn_pad_code; assign GEN_240 = {{24'd0}, insn_pad_code}; assign T_3092 = GEN_240 << 24; assign GEN_241 = {{8'd0}, T_3056}; assign T_3096 = GEN_241 | T_3092; assign T_3097 = T_2553[3:0]; assign T_3101 = ~ T_3097; assign T_3103 = T_3101 == 4'h0; assign T_3116 = T_2369_13 & T_3103; assign T_3117 = T_2104_bits_data[3:0]; assign GEN_26 = T_3116 ? T_3117 : ctrl_wm_tx; assign T_3172 = fifo_io_ip_txwm; assign T_3177 = T_2553[1]; assign T_3181 = ~ T_3177; assign T_3183 = T_3181 == 1'h0; assign T_3197 = T_2104_bits_data[1]; assign GEN_242 = {{1'd0}, fifo_io_ip_rxwm}; assign T_3212 = GEN_242 << 1; assign GEN_243 = {{1'd0}, T_3172}; assign T_3216 = GEN_243 | T_3212; assign T_3236 = T_2369_16 & T_2623; assign GEN_27 = T_3236 ? T_2637 : ctrl_sck_pha; assign T_3276 = T_2369_17 & T_3183; assign GEN_28 = T_3276 ? T_3197 : ctrl_sck_pol; assign GEN_244 = {{1'd0}, ctrl_sck_pol}; assign T_3292 = GEN_244 << 1; assign GEN_245 = {{1'd0}, ctrl_sck_pha}; assign T_3296 = GEN_245 | T_3292; assign T_3297 = T_2553[1:0]; assign T_3301 = ~ T_3297; assign T_3303 = T_3301 == 2'h0; assign T_3316 = T_2369_18 & T_3303; assign T_3317 = T_2104_bits_data[1:0]; assign GEN_29 = T_3316 ? T_3317 : ctrl_cs_mode; assign T_3356 = T_2369_19 & T_2623; assign GEN_30 = T_3356 ? T_2637 : ie_txwm; assign T_3396 = T_2369_20 & T_3183; assign GEN_31 = T_3396 ? T_3197 : ie_rxwm; assign GEN_246 = {{1'd0}, ie_rxwm}; assign T_3412 = GEN_246 << 1; assign GEN_247 = {{1'd0}, ie_txwm}; assign T_3416 = GEN_247 | T_3412; assign T_3436 = T_2369_21 & T_3103; assign GEN_32 = T_3436 ? T_3117 : ctrl_wm_rx; assign T_3476 = T_2369_22 & T_2663; assign GEN_248 = {{31'd0}, T_1921}; assign T_3572 = GEN_248 << 31; assign T_3596 = T_2369_25 & T_3303; assign GEN_33 = T_3596 ? T_3317 : ctrl_fmt_proto; assign T_3617 = T_2553[2]; assign T_3621 = ~ T_3617; assign T_3623 = T_3621 == 1'h0; assign T_3636 = T_2369_26 & T_3623; assign T_3637 = T_2104_bits_data[2]; assign GEN_34 = T_3636 ? T_3637 : ctrl_fmt_endian; assign GEN_249 = {{2'd0}, ctrl_fmt_endian}; assign T_3652 = GEN_249 << 2; assign GEN_250 = {{1'd0}, ctrl_fmt_proto}; assign T_3656 = GEN_250 | T_3652; assign T_3657 = T_2553[3]; assign T_3661 = ~ T_3657; assign T_3663 = T_3661 == 1'h0; assign T_3676 = T_2369_27 & T_3663; assign T_3677 = T_2104_bits_data[3]; assign GEN_35 = T_3676 ? T_3677 : ctrl_fmt_iodir; assign GEN_251 = {{3'd0}, ctrl_fmt_iodir}; assign T_3692 = GEN_251 << 3; assign GEN_252 = {{1'd0}, T_3656}; assign T_3696 = GEN_252 | T_3692; assign T_3697 = T_2553[19:16]; assign T_3701 = ~ T_3697; assign T_3703 = T_3701 == 4'h0; assign T_3716 = T_2369_28 & T_3703; assign T_3717 = T_2104_bits_data[19:16]; assign GEN_36 = T_3716 ? T_3717 : ctrl_fmt_len; assign GEN_253 = {{16'd0}, ctrl_fmt_len}; assign T_3732 = GEN_253 << 16; assign GEN_254 = {{16'd0}, T_3696}; assign T_3736 = GEN_254 | T_3732; assign T_3756 = T_2369_29 & T_2663; assign GEN_37 = T_3756 ? T_2677 : ctrl_dla_intercs; assign T_3796 = T_2369_30 & T_2703; assign GEN_38 = T_3796 ? T_2717 : ctrl_dla_interxfr; assign GEN_255 = {{16'd0}, ctrl_dla_interxfr}; assign T_3812 = GEN_255 << 16; assign GEN_256 = {{16'd0}, ctrl_dla_intercs}; assign T_3816 = GEN_256 | T_3812; assign T_3832 = T_2364_31 & T_2659; assign T_3852 = fifo_io_rx_bits; assign T_3896 = {{23'd0}, T_3852}; assign GEN_257 = {{31'd0}, T_1924}; assign T_3932 = GEN_257 << 31; assign GEN_258 = {{1'd0}, T_3896}; assign T_3936 = GEN_258 | T_3932; assign T_3956 = T_2369_34 & T_2623; assign GEN_39 = T_3956 ? T_2637 : ctrl_cs_id; assign T_3978 = T_2191 == 1'h0; assign T_3980 = T_3978 | T_2344_0; assign T_3982 = T_2254 == 1'h0; assign T_3983 = T_2344_17 & T_2344_16; assign T_3985 = T_3982 | T_3983; assign T_3993 = T_2326 == 1'h0; assign T_3995 = T_3993 | T_2344_34; assign T_3997 = T_2200 == 1'h0; assign T_3999 = T_3997 | T_2344_1; assign T_4001 = T_2263 == 1'h0; assign T_4003 = T_4001 | T_2344_18; assign T_4014 = T_2209 == 1'h0; assign T_4015 = T_2344_3 & T_2344_2; assign T_4017 = T_4014 | T_4015; assign T_4019 = T_2308 == 1'h0; assign T_4020 = T_2344_30 & T_2344_29; assign T_4022 = T_4019 | T_4020; assign T_4036 = T_2299 == 1'h0; assign T_4037 = T_2344_28 & T_2344_27; assign T_4038 = T_4037 & T_2344_26; assign T_4039 = T_4038 & T_2344_25; assign T_4041 = T_4036 | T_4039; assign T_4046 = T_2290 == 1'h0; assign T_4047 = T_2344_24 & T_2344_23; assign T_4048 = T_4047 & T_2344_22; assign T_4050 = T_4046 | T_4048; assign T_4052 = T_2317 == 1'h0; assign T_4053 = T_2344_33 & T_2344_32; assign T_4054 = T_4053 & T_2344_31; assign T_4056 = T_4052 | T_4054; assign T_4058 = T_2236 == 1'h0; assign T_4060 = T_4058 | T_2344_13; assign T_4062 = T_2281 == 1'h0; assign T_4064 = T_4062 | T_2344_21; assign T_4072 = T_2218 == 1'h0; assign T_4074 = T_4072 | T_2344_4; assign T_4076 = T_2227 == 1'h0; assign T_4077 = T_2344_12 & T_2344_11; assign T_4078 = T_4077 & T_2344_10; assign T_4079 = T_4078 & T_2344_9; assign T_4080 = T_4079 & T_2344_8; assign T_4081 = T_4080 & T_2344_7; assign T_4082 = T_4081 & T_2344_6; assign T_4083 = T_4082 & T_2344_5; assign T_4085 = T_4076 | T_4083; assign T_4093 = T_2272 == 1'h0; assign T_4094 = T_2344_20 & T_2344_19; assign T_4096 = T_4093 | T_4094; assign T_4098 = T_2245 == 1'h0; assign T_4099 = T_2344_15 & T_2344_14; assign T_4101 = T_4098 | T_4099; assign T_4143_0 = T_3980; assign T_4143_1 = T_3985; assign T_4143_2 = 1'h1; assign T_4143_3 = 1'h1; assign T_4143_4 = T_3995; assign T_4143_5 = T_3999; assign T_4143_6 = T_4003; assign T_4143_7 = 1'h1; assign T_4143_8 = 1'h1; assign T_4143_9 = 1'h1; assign T_4143_10 = T_4017; assign T_4143_11 = T_4022; assign T_4143_12 = 1'h1; assign T_4143_13 = 1'h1; assign T_4143_14 = 1'h1; assign T_4143_15 = 1'h1; assign T_4143_16 = T_4041; assign T_4143_17 = 1'h1; assign T_4143_18 = T_4050; assign T_4143_19 = T_4056; assign T_4143_20 = T_4060; assign T_4143_21 = T_4064; assign T_4143_22 = 1'h1; assign T_4143_23 = 1'h1; assign T_4143_24 = T_4074; assign T_4143_25 = T_4085; assign T_4143_26 = 1'h1; assign T_4143_27 = 1'h1; assign T_4143_28 = T_4096; assign T_4143_29 = T_4101; assign T_4143_30 = 1'h1; assign T_4143_31 = 1'h1; assign T_4181 = T_3978 | T_2349_0; assign T_4184 = T_2349_17 & T_2349_16; assign T_4186 = T_3982 | T_4184; assign T_4196 = T_3993 | T_2349_34; assign T_4200 = T_3997 | T_2349_1; assign T_4204 = T_4001 | T_2349_18; assign T_4216 = T_2349_3 & T_2349_2; assign T_4218 = T_4014 | T_4216; assign T_4221 = T_2349_30 & T_2349_29; assign T_4223 = T_4019 | T_4221; assign T_4238 = T_2349_28 & T_2349_27; assign T_4239 = T_4238 & T_2349_26; assign T_4240 = T_4239 & T_2349_25; assign T_4242 = T_4036 | T_4240; assign T_4248 = T_2349_24 & T_2349_23; assign T_4249 = T_4248 & T_2349_22; assign T_4251 = T_4046 | T_4249; assign T_4254 = T_2349_33 & T_2349_32; assign T_4255 = T_4254 & T_2349_31; assign T_4257 = T_4052 | T_4255; assign T_4261 = T_4058 | T_2349_13; assign T_4265 = T_4062 | T_2349_21; assign T_4275 = T_4072 | T_2349_4; assign T_4278 = T_2349_12 & T_2349_11; assign T_4279 = T_4278 & T_2349_10; assign T_4280 = T_4279 & T_2349_9; assign T_4281 = T_4280 & T_2349_8; assign T_4282 = T_4281 & T_2349_7; assign T_4283 = T_4282 & T_2349_6; assign T_4284 = T_4283 & T_2349_5; assign T_4286 = T_4076 | T_4284; assign T_4295 = T_2349_20 & T_2349_19; assign T_4297 = T_4093 | T_4295; assign T_4300 = T_2349_15 & T_2349_14; assign T_4302 = T_4098 | T_4300; assign T_4344_0 = T_4181; assign T_4344_1 = T_4186; assign T_4344_2 = 1'h1; assign T_4344_3 = 1'h1; assign T_4344_4 = T_4196; assign T_4344_5 = T_4200; assign T_4344_6 = T_4204; assign T_4344_7 = 1'h1; assign T_4344_8 = 1'h1; assign T_4344_9 = 1'h1; assign T_4344_10 = T_4218; assign T_4344_11 = T_4223; assign T_4344_12 = 1'h1; assign T_4344_13 = 1'h1; assign T_4344_14 = 1'h1; assign T_4344_15 = 1'h1; assign T_4344_16 = T_4242; assign T_4344_17 = 1'h1; assign T_4344_18 = T_4251; assign T_4344_19 = T_4257; assign T_4344_20 = T_4261; assign T_4344_21 = T_4265; assign T_4344_22 = 1'h1; assign T_4344_23 = 1'h1; assign T_4344_24 = T_4275; assign T_4344_25 = T_4286; assign T_4344_26 = 1'h1; assign T_4344_27 = 1'h1; assign T_4344_28 = T_4297; assign T_4344_29 = T_4302; assign T_4344_30 = 1'h1; assign T_4344_31 = 1'h1; assign T_4382 = T_3978 | T_2354_0; assign T_4385 = T_2354_17 & T_2354_16; assign T_4387 = T_3982 | T_4385; assign T_4397 = T_3993 | T_2354_34; assign T_4401 = T_3997 | T_2354_1; assign T_4405 = T_4001 | T_2354_18; assign T_4417 = T_2354_3 & T_2354_2; assign T_4419 = T_4014 | T_4417; assign T_4422 = T_2354_30 & T_2354_29; assign T_4424 = T_4019 | T_4422; assign T_4439 = T_2354_28 & T_2354_27; assign T_4440 = T_4439 & T_2354_26; assign T_4441 = T_4440 & T_2354_25; assign T_4443 = T_4036 | T_4441; assign T_4449 = T_2354_24 & T_2354_23; assign T_4450 = T_4449 & T_2354_22; assign T_4452 = T_4046 | T_4450; assign T_4455 = T_2354_33 & T_2354_32; assign T_4456 = T_4455 & T_2354_31; assign T_4458 = T_4052 | T_4456; assign T_4462 = T_4058 | T_2354_13; assign T_4466 = T_4062 | T_2354_21; assign T_4476 = T_4072 | T_2354_4; assign T_4479 = T_2354_12 & T_2354_11; assign T_4480 = T_4479 & T_2354_10; assign T_4481 = T_4480 & T_2354_9; assign T_4482 = T_4481 & T_2354_8; assign T_4483 = T_4482 & T_2354_7; assign T_4484 = T_4483 & T_2354_6; assign T_4485 = T_4484 & T_2354_5; assign T_4487 = T_4076 | T_4485; assign T_4496 = T_2354_20 & T_2354_19; assign T_4498 = T_4093 | T_4496; assign T_4501 = T_2354_15 & T_2354_14; assign T_4503 = T_4098 | T_4501; assign T_4545_0 = T_4382; assign T_4545_1 = T_4387; assign T_4545_2 = 1'h1; assign T_4545_3 = 1'h1; assign T_4545_4 = T_4397; assign T_4545_5 = T_4401; assign T_4545_6 = T_4405; assign T_4545_7 = 1'h1; assign T_4545_8 = 1'h1; assign T_4545_9 = 1'h1; assign T_4545_10 = T_4419; assign T_4545_11 = T_4424; assign T_4545_12 = 1'h1; assign T_4545_13 = 1'h1; assign T_4545_14 = 1'h1; assign T_4545_15 = 1'h1; assign T_4545_16 = T_4443; assign T_4545_17 = 1'h1; assign T_4545_18 = T_4452; assign T_4545_19 = T_4458; assign T_4545_20 = T_4462; assign T_4545_21 = T_4466; assign T_4545_22 = 1'h1; assign T_4545_23 = 1'h1; assign T_4545_24 = T_4476; assign T_4545_25 = T_4487; assign T_4545_26 = 1'h1; assign T_4545_27 = 1'h1; assign T_4545_28 = T_4498; assign T_4545_29 = T_4503; assign T_4545_30 = 1'h1; assign T_4545_31 = 1'h1; assign T_4583 = T_3978 | T_2359_0; assign T_4586 = T_2359_17 & T_2359_16; assign T_4588 = T_3982 | T_4586; assign T_4598 = T_3993 | T_2359_34; assign T_4602 = T_3997 | T_2359_1; assign T_4606 = T_4001 | T_2359_18; assign T_4618 = T_2359_3 & T_2359_2; assign T_4620 = T_4014 | T_4618; assign T_4623 = T_2359_30 & T_2359_29; assign T_4625 = T_4019 | T_4623; assign T_4640 = T_2359_28 & T_2359_27; assign T_4641 = T_4640 & T_2359_26; assign T_4642 = T_4641 & T_2359_25; assign T_4644 = T_4036 | T_4642; assign T_4650 = T_2359_24 & T_2359_23; assign T_4651 = T_4650 & T_2359_22; assign T_4653 = T_4046 | T_4651; assign T_4656 = T_2359_33 & T_2359_32; assign T_4657 = T_4656 & T_2359_31; assign T_4659 = T_4052 | T_4657; assign T_4663 = T_4058 | T_2359_13; assign T_4667 = T_4062 | T_2359_21; assign T_4677 = T_4072 | T_2359_4; assign T_4680 = T_2359_12 & T_2359_11; assign T_4681 = T_4680 & T_2359_10; assign T_4682 = T_4681 & T_2359_9; assign T_4683 = T_4682 & T_2359_8; assign T_4684 = T_4683 & T_2359_7; assign T_4685 = T_4684 & T_2359_6; assign T_4686 = T_4685 & T_2359_5; assign T_4688 = T_4076 | T_4686; assign T_4697 = T_2359_20 & T_2359_19; assign T_4699 = T_4093 | T_4697; assign T_4702 = T_2359_15 & T_2359_14; assign T_4704 = T_4098 | T_4702; assign T_4746_0 = T_4583; assign T_4746_1 = T_4588; assign T_4746_2 = 1'h1; assign T_4746_3 = 1'h1; assign T_4746_4 = T_4598; assign T_4746_5 = T_4602; assign T_4746_6 = T_4606; assign T_4746_7 = 1'h1; assign T_4746_8 = 1'h1; assign T_4746_9 = 1'h1; assign T_4746_10 = T_4620; assign T_4746_11 = T_4625; assign T_4746_12 = 1'h1; assign T_4746_13 = 1'h1; assign T_4746_14 = 1'h1; assign T_4746_15 = 1'h1; assign T_4746_16 = T_4644; assign T_4746_17 = 1'h1; assign T_4746_18 = T_4653; assign T_4746_19 = T_4659; assign T_4746_20 = T_4663; assign T_4746_21 = T_4667; assign T_4746_22 = 1'h1; assign T_4746_23 = 1'h1; assign T_4746_24 = T_4677; assign T_4746_25 = T_4688; assign T_4746_26 = 1'h1; assign T_4746_27 = 1'h1; assign T_4746_28 = T_4699; assign T_4746_29 = T_4704; assign T_4746_30 = 1'h1; assign T_4746_31 = 1'h1; assign T_4781 = T_2104_bits_index[0]; assign T_4782 = T_2104_bits_index[1]; assign T_4783 = T_2104_bits_index[2]; assign T_4784 = T_2104_bits_index[3]; assign T_4785 = T_2104_bits_index[4]; assign T_4791 = {T_4782,T_4781}; assign T_4792 = {T_4785,T_4784}; assign T_4793 = {T_4792,T_4783}; assign T_4794 = {T_4793,T_4791}; assign GEN_0 = GEN_70; assign GEN_40 = 5'h1 == T_4794 ? T_4143_1 : T_4143_0; assign GEN_41 = 5'h2 == T_4794 ? T_4143_2 : GEN_40; assign GEN_42 = 5'h3 == T_4794 ? T_4143_3 : GEN_41; assign GEN_43 = 5'h4 == T_4794 ? T_4143_4 : GEN_42; assign GEN_44 = 5'h5 == T_4794 ? T_4143_5 : GEN_43; assign GEN_45 = 5'h6 == T_4794 ? T_4143_6 : GEN_44; assign GEN_46 = 5'h7 == T_4794 ? T_4143_7 : GEN_45; assign GEN_47 = 5'h8 == T_4794 ? T_4143_8 : GEN_46; assign GEN_48 = 5'h9 == T_4794 ? T_4143_9 : GEN_47; assign GEN_49 = 5'ha == T_4794 ? T_4143_10 : GEN_48; assign GEN_50 = 5'hb == T_4794 ? T_4143_11 : GEN_49; assign GEN_51 = 5'hc == T_4794 ? T_4143_12 : GEN_50; assign GEN_52 = 5'hd == T_4794 ? T_4143_13 : GEN_51; assign GEN_53 = 5'he == T_4794 ? T_4143_14 : GEN_52; assign GEN_54 = 5'hf == T_4794 ? T_4143_15 : GEN_53; assign GEN_55 = 5'h10 == T_4794 ? T_4143_16 : GEN_54; assign GEN_56 = 5'h11 == T_4794 ? T_4143_17 : GEN_55; assign GEN_57 = 5'h12 == T_4794 ? T_4143_18 : GEN_56; assign GEN_58 = 5'h13 == T_4794 ? T_4143_19 : GEN_57; assign GEN_59 = 5'h14 == T_4794 ? T_4143_20 : GEN_58; assign GEN_60 = 5'h15 == T_4794 ? T_4143_21 : GEN_59; assign GEN_61 = 5'h16 == T_4794 ? T_4143_22 : GEN_60; assign GEN_62 = 5'h17 == T_4794 ? T_4143_23 : GEN_61; assign GEN_63 = 5'h18 == T_4794 ? T_4143_24 : GEN_62; assign GEN_64 = 5'h19 == T_4794 ? T_4143_25 : GEN_63; assign GEN_65 = 5'h1a == T_4794 ? T_4143_26 : GEN_64; assign GEN_66 = 5'h1b == T_4794 ? T_4143_27 : GEN_65; assign GEN_67 = 5'h1c == T_4794 ? T_4143_28 : GEN_66; assign GEN_68 = 5'h1d == T_4794 ? T_4143_29 : GEN_67; assign GEN_69 = 5'h1e == T_4794 ? T_4143_30 : GEN_68; assign GEN_70 = 5'h1f == T_4794 ? T_4143_31 : GEN_69; assign GEN_1 = GEN_101; assign GEN_71 = 5'h1 == T_4794 ? T_4344_1 : T_4344_0; assign GEN_72 = 5'h2 == T_4794 ? T_4344_2 : GEN_71; assign GEN_73 = 5'h3 == T_4794 ? T_4344_3 : GEN_72; assign GEN_74 = 5'h4 == T_4794 ? T_4344_4 : GEN_73; assign GEN_75 = 5'h5 == T_4794 ? T_4344_5 : GEN_74; assign GEN_76 = 5'h6 == T_4794 ? T_4344_6 : GEN_75; assign GEN_77 = 5'h7 == T_4794 ? T_4344_7 : GEN_76; assign GEN_78 = 5'h8 == T_4794 ? T_4344_8 : GEN_77; assign GEN_79 = 5'h9 == T_4794 ? T_4344_9 : GEN_78; assign GEN_80 = 5'ha == T_4794 ? T_4344_10 : GEN_79; assign GEN_81 = 5'hb == T_4794 ? T_4344_11 : GEN_80; assign GEN_82 = 5'hc == T_4794 ? T_4344_12 : GEN_81; assign GEN_83 = 5'hd == T_4794 ? T_4344_13 : GEN_82; assign GEN_84 = 5'he == T_4794 ? T_4344_14 : GEN_83; assign GEN_85 = 5'hf == T_4794 ? T_4344_15 : GEN_84; assign GEN_86 = 5'h10 == T_4794 ? T_4344_16 : GEN_85; assign GEN_87 = 5'h11 == T_4794 ? T_4344_17 : GEN_86; assign GEN_88 = 5'h12 == T_4794 ? T_4344_18 : GEN_87; assign GEN_89 = 5'h13 == T_4794 ? T_4344_19 : GEN_88; assign GEN_90 = 5'h14 == T_4794 ? T_4344_20 : GEN_89; assign GEN_91 = 5'h15 == T_4794 ? T_4344_21 : GEN_90; assign GEN_92 = 5'h16 == T_4794 ? T_4344_22 : GEN_91; assign GEN_93 = 5'h17 == T_4794 ? T_4344_23 : GEN_92; assign GEN_94 = 5'h18 == T_4794 ? T_4344_24 : GEN_93; assign GEN_95 = 5'h19 == T_4794 ? T_4344_25 : GEN_94; assign GEN_96 = 5'h1a == T_4794 ? T_4344_26 : GEN_95; assign GEN_97 = 5'h1b == T_4794 ? T_4344_27 : GEN_96; assign GEN_98 = 5'h1c == T_4794 ? T_4344_28 : GEN_97; assign GEN_99 = 5'h1d == T_4794 ? T_4344_29 : GEN_98; assign GEN_100 = 5'h1e == T_4794 ? T_4344_30 : GEN_99; assign GEN_101 = 5'h1f == T_4794 ? T_4344_31 : GEN_100; assign T_4811 = T_2104_bits_read ? GEN_0 : GEN_1; assign GEN_2 = GEN_132; assign GEN_102 = 5'h1 == T_4794 ? T_4545_1 : T_4545_0; assign GEN_103 = 5'h2 == T_4794 ? T_4545_2 : GEN_102; assign GEN_104 = 5'h3 == T_4794 ? T_4545_3 : GEN_103; assign GEN_105 = 5'h4 == T_4794 ? T_4545_4 : GEN_104; assign GEN_106 = 5'h5 == T_4794 ? T_4545_5 : GEN_105; assign GEN_107 = 5'h6 == T_4794 ? T_4545_6 : GEN_106; assign GEN_108 = 5'h7 == T_4794 ? T_4545_7 : GEN_107; assign GEN_109 = 5'h8 == T_4794 ? T_4545_8 : GEN_108; assign GEN_110 = 5'h9 == T_4794 ? T_4545_9 : GEN_109; assign GEN_111 = 5'ha == T_4794 ? T_4545_10 : GEN_110; assign GEN_112 = 5'hb == T_4794 ? T_4545_11 : GEN_111; assign GEN_113 = 5'hc == T_4794 ? T_4545_12 : GEN_112; assign GEN_114 = 5'hd == T_4794 ? T_4545_13 : GEN_113; assign GEN_115 = 5'he == T_4794 ? T_4545_14 : GEN_114; assign GEN_116 = 5'hf == T_4794 ? T_4545_15 : GEN_115; assign GEN_117 = 5'h10 == T_4794 ? T_4545_16 : GEN_116; assign GEN_118 = 5'h11 == T_4794 ? T_4545_17 : GEN_117; assign GEN_119 = 5'h12 == T_4794 ? T_4545_18 : GEN_118; assign GEN_120 = 5'h13 == T_4794 ? T_4545_19 : GEN_119; assign GEN_121 = 5'h14 == T_4794 ? T_4545_20 : GEN_120; assign GEN_122 = 5'h15 == T_4794 ? T_4545_21 : GEN_121; assign GEN_123 = 5'h16 == T_4794 ? T_4545_22 : GEN_122; assign GEN_124 = 5'h17 == T_4794 ? T_4545_23 : GEN_123; assign GEN_125 = 5'h18 == T_4794 ? T_4545_24 : GEN_124; assign GEN_126 = 5'h19 == T_4794 ? T_4545_25 : GEN_125; assign GEN_127 = 5'h1a == T_4794 ? T_4545_26 : GEN_126; assign GEN_128 = 5'h1b == T_4794 ? T_4545_27 : GEN_127; assign GEN_129 = 5'h1c == T_4794 ? T_4545_28 : GEN_128; assign GEN_130 = 5'h1d == T_4794 ? T_4545_29 : GEN_129; assign GEN_131 = 5'h1e == T_4794 ? T_4545_30 : GEN_130; assign GEN_132 = 5'h1f == T_4794 ? T_4545_31 : GEN_131; assign GEN_3 = GEN_163; assign GEN_133 = 5'h1 == T_4794 ? T_4746_1 : T_4746_0; assign GEN_134 = 5'h2 == T_4794 ? T_4746_2 : GEN_133; assign GEN_135 = 5'h3 == T_4794 ? T_4746_3 : GEN_134; assign GEN_136 = 5'h4 == T_4794 ? T_4746_4 : GEN_135; assign GEN_137 = 5'h5 == T_4794 ? T_4746_5 : GEN_136; assign GEN_138 = 5'h6 == T_4794 ? T_4746_6 : GEN_137; assign GEN_139 = 5'h7 == T_4794 ? T_4746_7 : GEN_138; assign GEN_140 = 5'h8 == T_4794 ? T_4746_8 : GEN_139; assign GEN_141 = 5'h9 == T_4794 ? T_4746_9 : GEN_140; assign GEN_142 = 5'ha == T_4794 ? T_4746_10 : GEN_141; assign GEN_143 = 5'hb == T_4794 ? T_4746_11 : GEN_142; assign GEN_144 = 5'hc == T_4794 ? T_4746_12 : GEN_143; assign GEN_145 = 5'hd == T_4794 ? T_4746_13 : GEN_144; assign GEN_146 = 5'he == T_4794 ? T_4746_14 : GEN_145; assign GEN_147 = 5'hf == T_4794 ? T_4746_15 : GEN_146; assign GEN_148 = 5'h10 == T_4794 ? T_4746_16 : GEN_147; assign GEN_149 = 5'h11 == T_4794 ? T_4746_17 : GEN_148; assign GEN_150 = 5'h12 == T_4794 ? T_4746_18 : GEN_149; assign GEN_151 = 5'h13 == T_4794 ? T_4746_19 : GEN_150; assign GEN_152 = 5'h14 == T_4794 ? T_4746_20 : GEN_151; assign GEN_153 = 5'h15 == T_4794 ? T_4746_21 : GEN_152; assign GEN_154 = 5'h16 == T_4794 ? T_4746_22 : GEN_153; assign GEN_155 = 5'h17 == T_4794 ? T_4746_23 : GEN_154; assign GEN_156 = 5'h18 == T_4794 ? T_4746_24 : GEN_155; assign GEN_157 = 5'h19 == T_4794 ? T_4746_25 : GEN_156; assign GEN_158 = 5'h1a == T_4794 ? T_4746_26 : GEN_157; assign GEN_159 = 5'h1b == T_4794 ? T_4746_27 : GEN_158; assign GEN_160 = 5'h1c == T_4794 ? T_4746_28 : GEN_159; assign GEN_161 = 5'h1d == T_4794 ? T_4746_29 : GEN_160; assign GEN_162 = 5'h1e == T_4794 ? T_4746_30 : GEN_161; assign GEN_163 = 5'h1f == T_4794 ? T_4746_31 : GEN_162; assign T_4814 = T_2104_bits_read ? GEN_2 : GEN_3; assign T_4815 = T_2104_ready & T_4811; assign T_4816 = T_2029_valid & T_4811; assign T_4817 = T_2068_ready & T_4814; assign T_4818 = T_2104_valid & T_4814; assign T_4820 = 32'h1 << T_4794; assign T_4821 = {T_2254,T_2191}; assign T_4823 = {2'h3,T_4821}; assign T_4824 = {T_2200,T_2326}; assign T_4825 = {1'h1,T_2263}; assign T_4826 = {T_4825,T_4824}; assign T_4827 = {T_4826,T_4823}; assign T_4829 = {T_2308,T_2209}; assign T_4830 = {T_4829,2'h3}; assign T_4834 = {4'hf,T_4830}; assign T_4835 = {T_4834,T_4827}; assign T_4836 = {1'h1,T_2299}; assign T_4837 = {T_2317,T_2290}; assign T_4838 = {T_4837,T_4836}; assign T_4839 = {T_2281,T_2236}; assign T_4841 = {2'h3,T_4839}; assign T_4842 = {T_4841,T_4838}; assign T_4843 = {T_2227,T_2218}; assign T_4845 = {2'h3,T_4843}; assign T_4846 = {T_2245,T_2272}; assign T_4848 = {2'h3,T_4846}; assign T_4849 = {T_4848,T_4845}; assign T_4850 = {T_4849,T_4842}; assign T_4851 = {T_4850,T_4835}; assign T_4852 = T_4820 & T_4851; assign T_4887 = T_2029_valid & T_2104_ready; assign T_4888 = T_4887 & T_2104_bits_read; assign T_4889 = T_4852[0]; assign T_4890 = T_4888 & T_4889; assign T_4893 = T_2104_bits_read == 1'h0; assign T_4894 = T_4887 & T_4893; assign T_4896 = T_4894 & T_4889; assign T_4897 = T_2104_valid & T_2068_ready; assign T_4898 = T_4897 & T_2104_bits_read; assign T_4900 = T_4898 & T_4889; assign T_4904 = T_4897 & T_4893; assign T_4906 = T_4904 & T_4889; assign T_4909 = T_4852[1]; assign T_4910 = T_4888 & T_4909; assign T_4916 = T_4894 & T_4909; assign T_4920 = T_4898 & T_4909; assign T_4926 = T_4904 & T_4909; assign T_4969 = T_4852[4]; assign T_4970 = T_4888 & T_4969; assign T_4976 = T_4894 & T_4969; assign T_4980 = T_4898 & T_4969; assign T_4986 = T_4904 & T_4969; assign T_4989 = T_4852[5]; assign T_4990 = T_4888 & T_4989; assign T_4996 = T_4894 & T_4989; assign T_5000 = T_4898 & T_4989; assign T_5006 = T_4904 & T_4989; assign T_5009 = T_4852[6]; assign T_5010 = T_4888 & T_5009; assign T_5016 = T_4894 & T_5009; assign T_5020 = T_4898 & T_5009; assign T_5026 = T_4904 & T_5009; assign T_5089 = T_4852[10]; assign T_5090 = T_4888 & T_5089; assign T_5096 = T_4894 & T_5089; assign T_5100 = T_4898 & T_5089; assign T_5106 = T_4904 & T_5089; assign T_5109 = T_4852[11]; assign T_5110 = T_4888 & T_5109; assign T_5116 = T_4894 & T_5109; assign T_5120 = T_4898 & T_5109; assign T_5126 = T_4904 & T_5109; assign T_5209 = T_4852[16]; assign T_5210 = T_4888 & T_5209; assign T_5216 = T_4894 & T_5209; assign T_5220 = T_4898 & T_5209; assign T_5226 = T_4904 & T_5209; assign T_5249 = T_4852[18]; assign T_5250 = T_4888 & T_5249; assign T_5256 = T_4894 & T_5249; assign T_5260 = T_4898 & T_5249; assign T_5266 = T_4904 & T_5249; assign T_5269 = T_4852[19]; assign T_5270 = T_4888 & T_5269; assign T_5276 = T_4894 & T_5269; assign T_5280 = T_4898 & T_5269; assign T_5286 = T_4904 & T_5269; assign T_5289 = T_4852[20]; assign T_5290 = T_4888 & T_5289; assign T_5296 = T_4894 & T_5289; assign T_5300 = T_4898 & T_5289; assign T_5306 = T_4904 & T_5289; assign T_5309 = T_4852[21]; assign T_5310 = T_4888 & T_5309; assign T_5316 = T_4894 & T_5309; assign T_5320 = T_4898 & T_5309; assign T_5326 = T_4904 & T_5309; assign T_5369 = T_4852[24]; assign T_5370 = T_4888 & T_5369; assign T_5376 = T_4894 & T_5369; assign T_5380 = T_4898 & T_5369; assign T_5386 = T_4904 & T_5369; assign T_5389 = T_4852[25]; assign T_5390 = T_4888 & T_5389; assign T_5396 = T_4894 & T_5389; assign T_5400 = T_4898 & T_5389; assign T_5406 = T_4904 & T_5389; assign T_5449 = T_4852[28]; assign T_5450 = T_4888 & T_5449; assign T_5456 = T_4894 & T_5449; assign T_5460 = T_4898 & T_5449; assign T_5466 = T_4904 & T_5449; assign T_5469 = T_4852[29]; assign T_5470 = T_4888 & T_5469; assign T_5476 = T_4894 & T_5469; assign T_5480 = T_4898 & T_5469; assign T_5486 = T_4904 & T_5469; assign T_5535 = T_5090 & T_2344_3; assign T_5537 = T_5096 & T_2349_3; assign T_5539 = T_5100 & T_2354_3; assign T_5541 = T_5106 & T_2359_3; assign T_5543 = T_5090 & T_2344_2; assign T_5545 = T_5096 & T_2349_2; assign T_5547 = T_5100 & T_2354_2; assign T_5549 = T_5106 & T_2359_2; assign T_5555 = T_5390 & T_2344_12; assign T_5556 = T_5555 & T_2344_11; assign T_5557 = T_5556 & T_2344_10; assign T_5558 = T_5557 & T_2344_9; assign T_5559 = T_5558 & T_2344_8; assign T_5560 = T_5559 & T_2344_7; assign T_5561 = T_5560 & T_2344_6; assign T_5563 = T_5396 & T_2349_12; assign T_5564 = T_5563 & T_2349_11; assign T_5565 = T_5564 & T_2349_10; assign T_5566 = T_5565 & T_2349_9; assign T_5567 = T_5566 & T_2349_8; assign T_5568 = T_5567 & T_2349_7; assign T_5569 = T_5568 & T_2349_6; assign T_5571 = T_5400 & T_2354_12; assign T_5572 = T_5571 & T_2354_11; assign T_5573 = T_5572 & T_2354_10; assign T_5574 = T_5573 & T_2354_9; assign T_5575 = T_5574 & T_2354_8; assign T_5576 = T_5575 & T_2354_7; assign T_5577 = T_5576 & T_2354_6; assign T_5579 = T_5406 & T_2359_12; assign T_5580 = T_5579 & T_2359_11; assign T_5581 = T_5580 & T_2359_10; assign T_5582 = T_5581 & T_2359_9; assign T_5583 = T_5582 & T_2359_8; assign T_5584 = T_5583 & T_2359_7; assign T_5585 = T_5584 & T_2359_6; assign T_5593 = T_5560 & T_2344_5; assign T_5601 = T_5568 & T_2349_5; assign T_5609 = T_5576 & T_2354_5; assign T_5617 = T_5584 & T_2359_5; assign T_5624 = T_5559 & T_2344_6; assign T_5625 = T_5624 & T_2344_5; assign T_5632 = T_5567 & T_2349_6; assign T_5633 = T_5632 & T_2349_5; assign T_5640 = T_5575 & T_2354_6; assign T_5641 = T_5640 & T_2354_5; assign T_5648 = T_5583 & T_2359_6; assign T_5649 = T_5648 & T_2359_5; assign T_5655 = T_5558 & T_2344_7; assign T_5656 = T_5655 & T_2344_6; assign T_5657 = T_5656 & T_2344_5; assign T_5663 = T_5566 & T_2349_7; assign T_5664 = T_5663 & T_2349_6; assign T_5665 = T_5664 & T_2349_5; assign T_5671 = T_5574 & T_2354_7; assign T_5672 = T_5671 & T_2354_6; assign T_5673 = T_5672 & T_2354_5; assign T_5679 = T_5582 & T_2359_7; assign T_5680 = T_5679 & T_2359_6; assign T_5681 = T_5680 & T_2359_5; assign T_5686 = T_5557 & T_2344_8; assign T_5687 = T_5686 & T_2344_7; assign T_5688 = T_5687 & T_2344_6; assign T_5689 = T_5688 & T_2344_5; assign T_5694 = T_5565 & T_2349_8; assign T_5695 = T_5694 & T_2349_7; assign T_5696 = T_5695 & T_2349_6; assign T_5697 = T_5696 & T_2349_5; assign T_5702 = T_5573 & T_2354_8; assign T_5703 = T_5702 & T_2354_7; assign T_5704 = T_5703 & T_2354_6; assign T_5705 = T_5704 & T_2354_5; assign T_5710 = T_5581 & T_2359_8; assign T_5711 = T_5710 & T_2359_7; assign T_5712 = T_5711 & T_2359_6; assign T_5713 = T_5712 & T_2359_5; assign T_5717 = T_5556 & T_2344_9; assign T_5718 = T_5717 & T_2344_8; assign T_5719 = T_5718 & T_2344_7; assign T_5720 = T_5719 & T_2344_6; assign T_5721 = T_5720 & T_2344_5; assign T_5725 = T_5564 & T_2349_9; assign T_5726 = T_5725 & T_2349_8; assign T_5727 = T_5726 & T_2349_7; assign T_5728 = T_5727 & T_2349_6; assign T_5729 = T_5728 & T_2349_5; assign T_5733 = T_5572 & T_2354_9; assign T_5734 = T_5733 & T_2354_8; assign T_5735 = T_5734 & T_2354_7; assign T_5736 = T_5735 & T_2354_6; assign T_5737 = T_5736 & T_2354_5; assign T_5741 = T_5580 & T_2359_9; assign T_5742 = T_5741 & T_2359_8; assign T_5743 = T_5742 & T_2359_7; assign T_5744 = T_5743 & T_2359_6; assign T_5745 = T_5744 & T_2359_5; assign T_5748 = T_5555 & T_2344_10; assign T_5749 = T_5748 & T_2344_9; assign T_5750 = T_5749 & T_2344_8; assign T_5751 = T_5750 & T_2344_7; assign T_5752 = T_5751 & T_2344_6; assign T_5753 = T_5752 & T_2344_5; assign T_5756 = T_5563 & T_2349_10; assign T_5757 = T_5756 & T_2349_9; assign T_5758 = T_5757 & T_2349_8; assign T_5759 = T_5758 & T_2349_7; assign T_5760 = T_5759 & T_2349_6; assign T_5761 = T_5760 & T_2349_5; assign T_5764 = T_5571 & T_2354_10; assign T_5765 = T_5764 & T_2354_9; assign T_5766 = T_5765 & T_2354_8; assign T_5767 = T_5766 & T_2354_7; assign T_5768 = T_5767 & T_2354_6; assign T_5769 = T_5768 & T_2354_5; assign T_5772 = T_5579 & T_2359_10; assign T_5773 = T_5772 & T_2359_9; assign T_5774 = T_5773 & T_2359_8; assign T_5775 = T_5774 & T_2359_7; assign T_5776 = T_5775 & T_2359_6; assign T_5777 = T_5776 & T_2359_5; assign T_5779 = T_5390 & T_2344_11; assign T_5780 = T_5779 & T_2344_10; assign T_5781 = T_5780 & T_2344_9; assign T_5782 = T_5781 & T_2344_8; assign T_5783 = T_5782 & T_2344_7; assign T_5784 = T_5783 & T_2344_6; assign T_5785 = T_5784 & T_2344_5; assign T_5787 = T_5396 & T_2349_11; assign T_5788 = T_5787 & T_2349_10; assign T_5789 = T_5788 & T_2349_9; assign T_5790 = T_5789 & T_2349_8; assign T_5791 = T_5790 & T_2349_7; assign T_5792 = T_5791 & T_2349_6; assign T_5793 = T_5792 & T_2349_5; assign T_5795 = T_5400 & T_2354_11; assign T_5796 = T_5795 & T_2354_10; assign T_5797 = T_5796 & T_2354_9; assign T_5798 = T_5797 & T_2354_8; assign T_5799 = T_5798 & T_2354_7; assign T_5800 = T_5799 & T_2354_6; assign T_5801 = T_5800 & T_2354_5; assign T_5803 = T_5406 & T_2359_11; assign T_5804 = T_5803 & T_2359_10; assign T_5805 = T_5804 & T_2359_9; assign T_5806 = T_5805 & T_2359_8; assign T_5807 = T_5806 & T_2359_7; assign T_5808 = T_5807 & T_2359_6; assign T_5809 = T_5808 & T_2359_5; assign T_5815 = T_5470 & T_2344_15; assign T_5817 = T_5476 & T_2349_15; assign T_5819 = T_5480 & T_2354_15; assign T_5821 = T_5486 & T_2359_15; assign T_5823 = T_5470 & T_2344_14; assign T_5825 = T_5476 & T_2349_14; assign T_5827 = T_5480 & T_2354_14; assign T_5829 = T_5486 & T_2359_14; assign T_5831 = T_4910 & T_2344_17; assign T_5833 = T_4916 & T_2349_17; assign T_5835 = T_4920 & T_2354_17; assign T_5837 = T_4926 & T_2359_17; assign T_5839 = T_4910 & T_2344_16; assign T_5841 = T_4916 & T_2349_16; assign T_5843 = T_4920 & T_2354_16; assign T_5845 = T_4926 & T_2359_16; assign T_5851 = T_5450 & T_2344_20; assign T_5853 = T_5456 & T_2349_20; assign T_5855 = T_5460 & T_2354_20; assign T_5857 = T_5466 & T_2359_20; assign T_5859 = T_5450 & T_2344_19; assign T_5861 = T_5456 & T_2349_19; assign T_5863 = T_5460 & T_2354_19; assign T_5865 = T_5466 & T_2359_19; assign T_5871 = T_5250 & T_2344_24; assign T_5872 = T_5871 & T_2344_23; assign T_5874 = T_5256 & T_2349_24; assign T_5875 = T_5874 & T_2349_23; assign T_5877 = T_5260 & T_2354_24; assign T_5878 = T_5877 & T_2354_23; assign T_5880 = T_5266 & T_2359_24; assign T_5881 = T_5880 & T_2359_23; assign T_5884 = T_5871 & T_2344_22; assign T_5887 = T_5874 & T_2349_22; assign T_5890 = T_5877 & T_2354_22; assign T_5893 = T_5880 & T_2359_22; assign T_5895 = T_5250 & T_2344_23; assign T_5896 = T_5895 & T_2344_22; assign T_5898 = T_5256 & T_2349_23; assign T_5899 = T_5898 & T_2349_22; assign T_5901 = T_5260 & T_2354_23; assign T_5902 = T_5901 & T_2354_22; assign T_5904 = T_5266 & T_2359_23; assign T_5905 = T_5904 & T_2359_22; assign T_5907 = T_5210 & T_2344_28; assign T_5908 = T_5907 & T_2344_27; assign T_5909 = T_5908 & T_2344_26; assign T_5911 = T_5216 & T_2349_28; assign T_5912 = T_5911 & T_2349_27; assign T_5913 = T_5912 & T_2349_26; assign T_5915 = T_5220 & T_2354_28; assign T_5916 = T_5915 & T_2354_27; assign T_5917 = T_5916 & T_2354_26; assign T_5919 = T_5226 & T_2359_28; assign T_5920 = T_5919 & T_2359_27; assign T_5921 = T_5920 & T_2359_26; assign T_5925 = T_5908 & T_2344_25; assign T_5929 = T_5912 & T_2349_25; assign T_5933 = T_5916 & T_2354_25; assign T_5937 = T_5920 & T_2359_25; assign T_5940 = T_5907 & T_2344_26; assign T_5941 = T_5940 & T_2344_25; assign T_5944 = T_5911 & T_2349_26; assign T_5945 = T_5944 & T_2349_25; assign T_5948 = T_5915 & T_2354_26; assign T_5949 = T_5948 & T_2354_25; assign T_5952 = T_5919 & T_2359_26; assign T_5953 = T_5952 & T_2359_25; assign T_5955 = T_5210 & T_2344_27; assign T_5956 = T_5955 & T_2344_26; assign T_5957 = T_5956 & T_2344_25; assign T_5959 = T_5216 & T_2349_27; assign T_5960 = T_5959 & T_2349_26; assign T_5961 = T_5960 & T_2349_25; assign T_5963 = T_5220 & T_2354_27; assign T_5964 = T_5963 & T_2354_26; assign T_5965 = T_5964 & T_2354_25; assign T_5967 = T_5226 & T_2359_27; assign T_5968 = T_5967 & T_2359_26; assign T_5969 = T_5968 & T_2359_25; assign T_5971 = T_5110 & T_2344_30; assign T_5973 = T_5116 & T_2349_30; assign T_5975 = T_5120 & T_2354_30; assign T_5977 = T_5126 & T_2359_30; assign T_5979 = T_5110 & T_2344_29; assign T_5981 = T_5116 & T_2349_29; assign T_5983 = T_5120 & T_2354_29; assign T_5985 = T_5126 & T_2359_29; assign T_5987 = T_5270 & T_2344_33; assign T_5988 = T_5987 & T_2344_32; assign T_5990 = T_5276 & T_2349_33; assign T_5991 = T_5990 & T_2349_32; assign T_5993 = T_5280 & T_2354_33; assign T_5994 = T_5993 & T_2354_32; assign T_5996 = T_5286 & T_2359_33; assign T_5997 = T_5996 & T_2359_32; assign T_6000 = T_5987 & T_2344_31; assign T_6003 = T_5990 & T_2349_31; assign T_6006 = T_5993 & T_2354_31; assign T_6009 = T_5996 & T_2359_31; assign T_6011 = T_5270 & T_2344_32; assign T_6012 = T_6011 & T_2344_31; assign T_6014 = T_5276 & T_2349_32; assign T_6015 = T_6014 & T_2349_31; assign T_6017 = T_5280 & T_2354_32; assign T_6018 = T_6017 & T_2354_31; assign T_6020 = T_5286 & T_2359_32; assign T_6021 = T_6020 & T_2359_31; assign T_6062_0 = T_2191; assign T_6062_1 = T_2254; assign T_6062_2 = 1'h1; assign T_6062_3 = 1'h1; assign T_6062_4 = T_2326; assign T_6062_5 = T_2200; assign T_6062_6 = T_2263; assign T_6062_7 = 1'h1; assign T_6062_8 = 1'h1; assign T_6062_9 = 1'h1; assign T_6062_10 = T_2209; assign T_6062_11 = T_2308; assign T_6062_12 = 1'h1; assign T_6062_13 = 1'h1; assign T_6062_14 = 1'h1; assign T_6062_15 = 1'h1; assign T_6062_16 = T_2299; assign T_6062_17 = 1'h1; assign T_6062_18 = T_2290; assign T_6062_19 = T_2317; assign T_6062_20 = T_2236; assign T_6062_21 = T_2281; assign T_6062_22 = 1'h1; assign T_6062_23 = 1'h1; assign T_6062_24 = T_2218; assign T_6062_25 = T_2227; assign T_6062_26 = 1'h1; assign T_6062_27 = 1'h1; assign T_6062_28 = T_2272; assign T_6062_29 = T_2245; assign T_6062_30 = 1'h1; assign T_6062_31 = 1'h1; assign T_6133_0 = {{20'd0}, ctrl_sck_div}; assign T_6133_1 = {{30'd0}, T_3296}; assign T_6133_2 = 32'h0; assign T_6133_3 = 32'h0; assign T_6133_4 = {{31'd0}, ctrl_cs_id}; assign T_6133_5 = {{31'd0}, ctrl_cs_dflt_0}; assign T_6133_6 = {{30'd0}, ctrl_cs_mode}; assign T_6133_7 = 32'h0; assign T_6133_8 = 32'h0; assign T_6133_9 = 32'h0; assign T_6133_10 = {{8'd0}, T_2736}; assign T_6133_11 = {{8'd0}, T_3816}; assign T_6133_12 = 32'h0; assign T_6133_13 = 32'h0; assign T_6133_14 = 32'h0; assign T_6133_15 = 32'h0; assign T_6133_16 = {{12'd0}, T_3736}; assign T_6133_17 = 32'h0; assign T_6133_18 = T_3572; assign T_6133_19 = T_3936; assign T_6133_20 = {{28'd0}, ctrl_wm_tx}; assign T_6133_21 = {{28'd0}, ctrl_wm_rx}; assign T_6133_22 = 32'h0; assign T_6133_23 = 32'h0; assign T_6133_24 = {{31'd0}, flash_en}; assign T_6133_25 = T_3096; assign T_6133_26 = 32'h0; assign T_6133_27 = 32'h0; assign T_6133_28 = {{30'd0}, T_3416}; assign T_6133_29 = {{30'd0}, T_3216}; assign T_6133_30 = 32'h0; assign T_6133_31 = 32'h0; assign GEN_4 = GEN_194; assign GEN_164 = 5'h1 == T_4794 ? T_6062_1 : T_6062_0; assign GEN_165 = 5'h2 == T_4794 ? T_6062_2 : GEN_164; assign GEN_166 = 5'h3 == T_4794 ? T_6062_3 : GEN_165; assign GEN_167 = 5'h4 == T_4794 ? T_6062_4 : GEN_166; assign GEN_168 = 5'h5 == T_4794 ? T_6062_5 : GEN_167; assign GEN_169 = 5'h6 == T_4794 ? T_6062_6 : GEN_168; assign GEN_170 = 5'h7 == T_4794 ? T_6062_7 : GEN_169; assign GEN_171 = 5'h8 == T_4794 ? T_6062_8 : GEN_170; assign GEN_172 = 5'h9 == T_4794 ? T_6062_9 : GEN_171; assign GEN_173 = 5'ha == T_4794 ? T_6062_10 : GEN_172; assign GEN_174 = 5'hb == T_4794 ? T_6062_11 : GEN_173; assign GEN_175 = 5'hc == T_4794 ? T_6062_12 : GEN_174; assign GEN_176 = 5'hd == T_4794 ? T_6062_13 : GEN_175; assign GEN_177 = 5'he == T_4794 ? T_6062_14 : GEN_176; assign GEN_178 = 5'hf == T_4794 ? T_6062_15 : GEN_177; assign GEN_179 = 5'h10 == T_4794 ? T_6062_16 : GEN_178; assign GEN_180 = 5'h11 == T_4794 ? T_6062_17 : GEN_179; assign GEN_181 = 5'h12 == T_4794 ? T_6062_18 : GEN_180; assign GEN_182 = 5'h13 == T_4794 ? T_6062_19 : GEN_181; assign GEN_183 = 5'h14 == T_4794 ? T_6062_20 : GEN_182; assign GEN_184 = 5'h15 == T_4794 ? T_6062_21 : GEN_183; assign GEN_185 = 5'h16 == T_4794 ? T_6062_22 : GEN_184; assign GEN_186 = 5'h17 == T_4794 ? T_6062_23 : GEN_185; assign GEN_187 = 5'h18 == T_4794 ? T_6062_24 : GEN_186; assign GEN_188 = 5'h19 == T_4794 ? T_6062_25 : GEN_187; assign GEN_189 = 5'h1a == T_4794 ? T_6062_26 : GEN_188; assign GEN_190 = 5'h1b == T_4794 ? T_6062_27 : GEN_189; assign GEN_191 = 5'h1c == T_4794 ? T_6062_28 : GEN_190; assign GEN_192 = 5'h1d == T_4794 ? T_6062_29 : GEN_191; assign GEN_193 = 5'h1e == T_4794 ? T_6062_30 : GEN_192; assign GEN_194 = 5'h1f == T_4794 ? T_6062_31 : GEN_193; assign GEN_5 = GEN_225; assign GEN_195 = 5'h1 == T_4794 ? T_6133_1 : T_6133_0; assign GEN_196 = 5'h2 == T_4794 ? T_6133_2 : GEN_195; assign GEN_197 = 5'h3 == T_4794 ? T_6133_3 : GEN_196; assign GEN_198 = 5'h4 == T_4794 ? T_6133_4 : GEN_197; assign GEN_199 = 5'h5 == T_4794 ? T_6133_5 : GEN_198; assign GEN_200 = 5'h6 == T_4794 ? T_6133_6 : GEN_199; assign GEN_201 = 5'h7 == T_4794 ? T_6133_7 : GEN_200; assign GEN_202 = 5'h8 == T_4794 ? T_6133_8 : GEN_201; assign GEN_203 = 5'h9 == T_4794 ? T_6133_9 : GEN_202; assign GEN_204 = 5'ha == T_4794 ? T_6133_10 : GEN_203; assign GEN_205 = 5'hb == T_4794 ? T_6133_11 : GEN_204; assign GEN_206 = 5'hc == T_4794 ? T_6133_12 : GEN_205; assign GEN_207 = 5'hd == T_4794 ? T_6133_13 : GEN_206; assign GEN_208 = 5'he == T_4794 ? T_6133_14 : GEN_207; assign GEN_209 = 5'hf == T_4794 ? T_6133_15 : GEN_208; assign GEN_210 = 5'h10 == T_4794 ? T_6133_16 : GEN_209; assign GEN_211 = 5'h11 == T_4794 ? T_6133_17 : GEN_210; assign GEN_212 = 5'h12 == T_4794 ? T_6133_18 : GEN_211; assign GEN_213 = 5'h13 == T_4794 ? T_6133_19 : GEN_212; assign GEN_214 = 5'h14 == T_4794 ? T_6133_20 : GEN_213; assign GEN_215 = 5'h15 == T_4794 ? T_6133_21 : GEN_214; assign GEN_216 = 5'h16 == T_4794 ? T_6133_22 : GEN_215; assign GEN_217 = 5'h17 == T_4794 ? T_6133_23 : GEN_216; assign GEN_218 = 5'h18 == T_4794 ? T_6133_24 : GEN_217; assign GEN_219 = 5'h19 == T_4794 ? T_6133_25 : GEN_218; assign GEN_220 = 5'h1a == T_4794 ? T_6133_26 : GEN_219; assign GEN_221 = 5'h1b == T_4794 ? T_6133_27 : GEN_220; assign GEN_222 = 5'h1c == T_4794 ? T_6133_28 : GEN_221; assign GEN_223 = 5'h1d == T_4794 ? T_6133_29 : GEN_222; assign GEN_224 = 5'h1e == T_4794 ? T_6133_30 : GEN_223; assign GEN_225 = 5'h1f == T_4794 ? T_6133_31 : GEN_224; assign T_6170 = GEN_4 ? GEN_5 : 32'h0; assign T_6171 = T_2068_bits_extra[9:8]; assign T_6173 = T_2068_bits_extra[7:3]; assign T_6174 = T_2068_bits_extra[2:0]; assign T_6185_opcode = 3'h0; assign T_6185_param = 2'h0; assign T_6185_size = T_6174; assign T_6185_source = T_6173; assign T_6185_sink = 1'h0; assign T_6185_addr_lo = T_6171; assign T_6185_data = 32'h0; assign T_6185_error = 1'h0; always @(posedge clock or posedge reset) if (reset) begin ctrl_fmt_proto <= T_1840_fmt_proto; end else begin if (T_3596) begin ctrl_fmt_proto <= T_3317; end end always @(posedge clock or posedge reset) if (reset) begin ctrl_fmt_endian <= T_1840_fmt_endian; end else begin if (T_3636) begin ctrl_fmt_endian <= T_3637; end end always @(posedge clock or posedge reset) if (reset) begin ctrl_fmt_iodir <= T_1840_fmt_iodir; end else begin if (T_3676) begin ctrl_fmt_iodir <= T_3677; end end always @(posedge clock or posedge reset) if (reset) begin ctrl_fmt_len <= T_1840_fmt_len; end else begin if (T_3716) begin ctrl_fmt_len <= T_3717; end end always @(posedge clock or posedge reset) if (reset) begin ctrl_sck_div <= T_1840_sck_div; end else begin if (T_2596) begin ctrl_sck_div <= T_2597; end end always @(posedge clock or posedge reset) if (reset) begin ctrl_sck_pol <= T_1840_sck_pol; end else begin if (T_3276) begin ctrl_sck_pol <= T_3197; end end always @(posedge clock or posedge reset) if (reset) begin ctrl_sck_pha <= T_1840_sck_pha; end else begin if (T_3236) begin ctrl_sck_pha <= T_2637; end end always @(posedge clock or posedge reset) if (reset) begin ctrl_cs_id <= T_1840_cs_id; end else begin if (T_3956) begin ctrl_cs_id <= T_2637; end end always @(posedge clock or posedge reset) if (reset) begin ctrl_cs_dflt_0 <= T_1840_cs_dflt_0; end else begin if (T_2636) begin ctrl_cs_dflt_0 <= T_2637; end end always @(posedge clock or posedge reset) if (reset) begin ctrl_cs_mode <= T_1840_cs_mode; end else begin if (T_3316) begin ctrl_cs_mode <= T_3317; end end always @(posedge clock or posedge reset) if (reset) begin ctrl_dla_cssck <= T_1840_dla_cssck; end else begin if (T_2676) begin ctrl_dla_cssck <= T_2677; end end always @(posedge clock or posedge reset) if (reset) begin ctrl_dla_sckcs <= T_1840_dla_sckcs; end else begin if (T_2716) begin ctrl_dla_sckcs <= T_2717; end end always @(posedge clock or posedge reset) if (reset) begin ctrl_dla_intercs <= T_1840_dla_intercs; end else begin if (T_3756) begin ctrl_dla_intercs <= T_2677; end end always @(posedge clock or posedge reset) if (reset) begin ctrl_dla_interxfr <= T_1840_dla_interxfr; end else begin if (T_3796) begin ctrl_dla_interxfr <= T_2717; end end always @(posedge clock or posedge reset) if (reset) begin ctrl_wm_tx <= T_1840_wm_tx; end else begin if (T_3116) begin ctrl_wm_tx <= T_3117; end end always @(posedge clock or posedge reset) if (reset) begin ctrl_wm_rx <= T_1840_wm_rx; end else begin if (T_3436) begin ctrl_wm_rx <= T_3117; end end always @(posedge clock or posedge reset) if (reset) begin ie_txwm <= T_1906_txwm; end else begin if (T_3356) begin ie_txwm <= T_2637; end end always @(posedge clock or posedge reset) if (reset) begin ie_rxwm <= T_1906_rxwm; end else begin if (T_3396) begin ie_rxwm <= T_3197; end end always @(posedge clock or posedge reset) if (reset) begin insn_cmd_proto <= T_1973_cmd_proto; end else begin if (T_2916) begin insn_cmd_proto <= T_2917; end end always @(posedge clock or posedge reset) if (reset) begin insn_cmd_code <= T_1973_cmd_code; end else begin if (T_3036) begin insn_cmd_code <= T_2717; end end always @(posedge clock or posedge reset) if (reset) begin insn_cmd_en <= T_1973_cmd_en; end else begin if (T_2796) begin insn_cmd_en <= T_2637; end end always @(posedge clock or posedge reset) if (reset) begin insn_addr_proto <= T_1973_addr_proto; end else begin if (T_2956) begin insn_addr_proto <= T_2957; end end always @(posedge clock or posedge reset) if (reset) begin insn_addr_len <= T_1973_addr_len; end else begin if (T_2836) begin insn_addr_len <= T_2837; end end always @(posedge clock or posedge reset) if (reset) begin insn_pad_code <= T_1973_pad_code; end else begin if (T_3076) begin insn_pad_code <= T_3077; end end always @(posedge clock or posedge reset) if (reset) begin insn_pad_cnt <= T_1973_pad_cnt; end else begin if (T_2876) begin insn_pad_cnt <= T_2877; end end always @(posedge clock or posedge reset) if (reset) begin insn_data_proto <= T_1973_data_proto; end else begin if (T_2996) begin insn_data_proto <= T_2997; end end always @(posedge clock or posedge reset) if (reset) begin flash_en <= 1'h1; end else begin if (T_2756) begin flash_en <= T_2637; end end always @(posedge clock or posedge reset) begin if(reset) begin a_opcode <= 3'b0; a_param <= 3'b0; a_size <= 3'b0; a_source <= 7'b0; a_address <= 30'b0; a_mask <= 1'b0; a_data <= 8'b0; end else begin if (T_1935) begin a_opcode <= io_tl_f_0_a_bits_opcode; end if (T_1935) begin a_param <= io_tl_f_0_a_bits_param; end if (T_1935) begin a_size <= io_tl_f_0_a_bits_size; end if (T_1935) begin a_source <= io_tl_f_0_a_bits_source; end if (T_1935) begin a_address <= io_tl_f_0_a_bits_address; end if (T_1935) begin a_mask <= io_tl_f_0_a_bits_mask; end if (T_1935) begin a_data <= io_tl_f_0_a_bits_data; end end end endmodule
//////////////////////////////////////////////////////////////////////////////////// // Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. // // // // Redistribution and use in source and binary forms, with or without // // modification, are permitted provided that the following conditions are met: // // * Redistributions of source code must retain the above copyright // // notice, this list of conditions and the following disclaimer. // // * Redistributions in binary form must reproduce the above copyright // // notice, this list of conditions and the following disclaimer in the // // documentation and/or other materials provided with the distribution. // // * Neither the name of the University of British Columbia (UBC) nor the names // // of its contributors may be used to endorse or promote products // // derived from this software without specific prior written permission. // // // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE // // DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE // // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL // // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR // // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER // // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, // // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // //////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////// // lvt_reg.v: Register-based binary-coded LVT (Live-Value-Table) // // // // Author: Ameer M.S. Abdelhadi ([email protected], [email protected]) // // Switched SRAM-based Multi-ported RAM; University of British Columbia, 2014 // //////////////////////////////////////////////////////////////////////////////////// `include "utils.vh" module lvt_reg #( parameter MEMD = 16, // memory depth parameter nRP = 2 , // number of reading ports parameter nWP = 2 , // number of writing ports parameter RDWB = 0 , // new data for Read-During-Write parameter ZERO = 0 , // binary / Initial RAM with zeros (has priority over FILE) parameter FILE = "" // initialization file, optional )( input clk , // clock input [ nWP-1:0] WEnb , // write enable for each writing port input [`log2(MEMD)*nWP-1:0] WAddr, // write addresses - packed from nWP write ports input [`log2(MEMD)*nRP-1:0] RAddr, // read addresses - packed from nRP read ports output [`log2(nWP )*nRP-1:0] RBank); // read bank selector - packed from nRP read ports localparam ADRW = `log2(MEMD); // address width localparam LVTW = `log2(nWP ); // required memory width // Generate Bank ID's to write into LVT reg [LVTW*nWP-1:0] WData1D ; wire [LVTW -1:0] WData2D [nWP-1:0]; genvar gi; generate for (gi=0;gi<nWP;gi=gi+1) begin: GenerateID assign WData2D[gi]=gi; end endgenerate // packing/unpacking arrays into 1D/2D/3D structures; see utils.vh for definitions // pack ID's into 1D array `ARRINIT; always @* `ARR2D1D(nWP,LVTW,WData2D,WData1D); mpram_reg #( .MEMD (MEMD ), // memory depth .DATW (LVTW ), // data width .nRP (nRP ), // number of reading ports .nWP (nWP ), // number of writing ports .RDWB (RDWB ), // provide new data when Read-During-Write? .ZERO (ZERO ), // binary / Initial RAM with zeros (has priority over FILE) .FILE (FILE )) // initialization file, optional mpram_reg_ins ( .clk (clk ), // clock - in .WEnb (WEnb ), // write enable for each writing port - in : [ nWP-1:0] .WAddr (WAddr ), // write addresses - packed from nWP write ports - in : [ADRW*nWP-1:0] .WData (WData1D), // write data - packed from nRP read ports - in : [LVTW*nWP-1:0] .RAddr (RAddr ), // read addresses - packed from nRP read ports - in : [ADRW*nRP-1:0] .RData (RBank )); // read data - packed from nRP read ports - out: [LVTW*nRP-1:0] endmodule
class foo(); int my_field; endclass // foo class temp; extern function test(); extern function test2(); function foo(); foo = 1; endfunction // foo extern function test3(); reg [31:0] b; endclass // temp class short extends temp; logic a; endclass `define vmm_channel(A) A+A module foo; reg a; reg [1:0] b; initial begin b = `vmm_channel(a); end // initial begin endmodule // foo class A; extern function int e1(); extern function int e2(int src,int dst); extern static function int f1(); extern static function int f2(int src,int dst); extern static function int f3(int src,int dst); extern static function chandle f10(int src); extern static function automatic int f11(int mcid); extern function automatic int f13(int mcid); static function int s1(); int i = 0; endfunction static function int s2(); int i = 0; endfunction function int f1(); int i = 0; endfunction function int f2(); int i = 0; endfunction endclass
/****************************************************************************** * License Agreement * * * * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. * * All rights reserved. * * * * Any megafunction design, and related net list (encrypted or decrypted), * * support information, device programming or simulation file, and any other * * associated documentation or information provided by Altera or a partner * * under Altera's Megafunction Partnership Program may be used only to * * program PLD devices (but not masked PLD devices) from Altera. Any other * * use of such megafunction design, net list, support information, device * * programming or simulation file, or any other related documentation or * * information is prohibited for any other purpose, including, but not * * limited to modification, reverse engineering, de-compiling, or use with * * any other silicon devices, unless such use is explicitly licensed under * * a separate agreement with Altera or a megafunction partner. Title to * * the intellectual property, including patents, copyrights, trademarks, * * trade secrets, or maskworks, embodied in any such megafunction design, * * net list, support information, device programming or simulation file, or * * any other related documentation or information provided by Altera or a * * megafunction partner, remains with Altera, the megafunction partner, or * * their respective licensors. No other licenses, including any licenses * * needed under any third party's intellectual property, are provided herein.* * Copying or modifying any file, or portion thereof, to which this notice * * is attached violates this copyright. * * * * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS * * IN THIS FILE. * * * * This agreement shall be governed in all respects by the laws of the State * * of California and by the laws of the United States of America. * * * ******************************************************************************/ /****************************************************************************** * * * This module controls 16x2 character LCD on the Altera DE2 Board. * * * ******************************************************************************/ module niosII_system_character_lcd_0 ( // Inputs clk, reset, address, chipselect, read, write, writedata, // Bidirectionals LCD_DATA, // Outputs LCD_ON, LCD_BLON, LCD_EN, LCD_RS, LCD_RW, readdata, waitrequest ); /***************************************************************************** * Parameter Declarations * *****************************************************************************/ parameter CURSOR_ON = 1'b1; parameter BLINKING_ON = 1'b0; /***************************************************************************** * Port Declarations * *****************************************************************************/ // Inputs input clk; input reset; input address; input chipselect; input read; input write; input [ 7: 0] writedata; // Bidirectionals inout [ 7: 0] LCD_DATA; // LCD Data bus 8 bits // Outputs output LCD_ON; // LCD Power ON/OFF output LCD_BLON; // LCD Back Light ON/OFF output LCD_EN; // LCD Enable output LCD_RS; // LCD 0-Command/1-Data Select output LCD_RW; // LCD 1-Read/0-Write Select output [ 7: 0] readdata; output waitrequest; /***************************************************************************** * Constant Declarations * *****************************************************************************/ // states localparam LCD_STATE_0_IDLE = 3'h0, LCD_STATE_1_INITIALIZE = 3'h1, LCD_STATE_2_START_CHECK_BUSY = 3'h2, LCD_STATE_3_CHECK_BUSY = 3'h3, LCD_STATE_4_BEGIN_TRANSFER = 3'h4, LCD_STATE_5_TRANSFER = 3'h5, LCD_STATE_6_COMPLETE = 3'h6; /***************************************************************************** * Internal Wires and Registers Declarations * *****************************************************************************/ // Internal Wires wire transfer_complete; wire done_initialization; wire init_send_command; wire [ 8: 0] init_command; wire send_data; wire [ 7: 0] data_received; // Internal Registers reg initialize_lcd_display; reg [ 7: 0] data_to_send; reg rs; reg rw; // State Machine Registers reg [ 2: 0] ns_lcd_controller; reg [ 2: 0] s_lcd_controller; /***************************************************************************** * Finite State Machine(s) * *****************************************************************************/ always @(posedge clk) begin if (reset) s_lcd_controller <= LCD_STATE_0_IDLE; else s_lcd_controller <= ns_lcd_controller; end always @(*) begin // Defaults ns_lcd_controller = LCD_STATE_0_IDLE; case (s_lcd_controller) LCD_STATE_0_IDLE: begin if (initialize_lcd_display) ns_lcd_controller = LCD_STATE_1_INITIALIZE; else if (chipselect) ns_lcd_controller = LCD_STATE_2_START_CHECK_BUSY; else ns_lcd_controller = LCD_STATE_0_IDLE; end LCD_STATE_1_INITIALIZE: begin if (done_initialization) ns_lcd_controller = LCD_STATE_6_COMPLETE; else ns_lcd_controller = LCD_STATE_1_INITIALIZE; end LCD_STATE_2_START_CHECK_BUSY: begin if (transfer_complete == 1'b0) ns_lcd_controller = LCD_STATE_3_CHECK_BUSY; else ns_lcd_controller = LCD_STATE_2_START_CHECK_BUSY; end LCD_STATE_3_CHECK_BUSY: begin if ((transfer_complete) && (data_received[7])) ns_lcd_controller = LCD_STATE_2_START_CHECK_BUSY; else if ((transfer_complete) && (data_received[7] == 1'b0)) ns_lcd_controller = LCD_STATE_4_BEGIN_TRANSFER; else ns_lcd_controller = LCD_STATE_3_CHECK_BUSY; end LCD_STATE_4_BEGIN_TRANSFER: begin if (transfer_complete == 1'b0) ns_lcd_controller = LCD_STATE_5_TRANSFER; else ns_lcd_controller = LCD_STATE_4_BEGIN_TRANSFER; end LCD_STATE_5_TRANSFER: begin if (transfer_complete) ns_lcd_controller = LCD_STATE_6_COMPLETE; else ns_lcd_controller = LCD_STATE_5_TRANSFER; end LCD_STATE_6_COMPLETE: begin ns_lcd_controller = LCD_STATE_0_IDLE; end default: begin ns_lcd_controller = LCD_STATE_0_IDLE; end endcase end /***************************************************************************** * Sequential Logic * *****************************************************************************/ always @(posedge clk) begin if (reset) initialize_lcd_display <= 1'b1; else if (done_initialization) initialize_lcd_display <= 1'b0; end always @(posedge clk) begin if (reset) data_to_send <= 8'h00; else if (s_lcd_controller == LCD_STATE_1_INITIALIZE) data_to_send <= init_command[7:0]; else if (s_lcd_controller == LCD_STATE_4_BEGIN_TRANSFER) data_to_send <= writedata[7:0]; end always @(posedge clk) begin if (reset) rs <= 1'b0; else if (s_lcd_controller == LCD_STATE_1_INITIALIZE) rs <= init_command[8]; else if (s_lcd_controller == LCD_STATE_2_START_CHECK_BUSY) rs <= 1'b0; else if (s_lcd_controller == LCD_STATE_4_BEGIN_TRANSFER) rs <= address; end always @(posedge clk) begin if (reset) rw <= 1'b0; else if (s_lcd_controller == LCD_STATE_1_INITIALIZE) rw <= 1'b0; else if (s_lcd_controller == LCD_STATE_2_START_CHECK_BUSY) rw <= 1'b1; else if (s_lcd_controller == LCD_STATE_4_BEGIN_TRANSFER) rw <= ~write; end /***************************************************************************** * Combinational Logic * *****************************************************************************/ // Output Assignments assign readdata = data_received; assign waitrequest = chipselect & (s_lcd_controller != LCD_STATE_6_COMPLETE); // Internal Assignments assign send_data = (s_lcd_controller == LCD_STATE_1_INITIALIZE) ? init_send_command : (s_lcd_controller == LCD_STATE_3_CHECK_BUSY) ? 1'b1 : (s_lcd_controller == LCD_STATE_5_TRANSFER) ? 1'b1 : 1'b0; /***************************************************************************** * Internal Modules * *****************************************************************************/ altera_up_character_lcd_communication Char_LCD_Comm ( // Inputs .clk (clk), .reset (reset), .data_in (data_to_send), .enable (send_data), .rs (rs), .rw (rw), .display_on (1'b1), .back_light_on (1'b1), // Bidirectionals .LCD_DATA (LCD_DATA), // Outputs .LCD_ON (LCD_ON), .LCD_BLON (LCD_BLON), .LCD_EN (LCD_EN), .LCD_RS (LCD_RS), .LCD_RW (LCD_RW), .data_out (data_received), .transfer_complete (transfer_complete) ); altera_up_character_lcd_initialization Char_LCD_Init ( // Inputs .clk (clk), .reset (reset), .initialize_LCD_display (initialize_lcd_display), .command_was_sent (transfer_complete), // Bidirectionals // Outputs .done_initialization (done_initialization), .send_command (init_send_command), .the_command (init_command) ); defparam Char_LCD_Init.CURSOR_ON = CURSOR_ON, Char_LCD_Init.BLINKING_ON = BLINKING_ON; endmodule
/******************************************************************************* * This file is owned and controlled by Xilinx and must be used solely * * for design, simulation, implementation and creation of design files * * limited to Xilinx devices or technologies. Use with non-Xilinx * * devices or technologies is expressly prohibited and immediately * * terminates your license. * * * * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * * FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * * PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * * IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * * MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * * CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * * RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * * DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * * PARTICULAR PURPOSE. * * * * Xilinx products are not intended for use in life support appliances, * * devices, or systems. Use in such applications are expressly * * prohibited. * * * * (c) Copyright 1995-2020 Xilinx, Inc. * * All rights reserved. * *******************************************************************************/ // You must compile the wrapper file msu_databuf.v when simulating // the core, msu_databuf. When compiling the wrapper file, be sure to // reference the XilinxCoreLib Verilog simulation library. For detailed // instructions, please refer to the "CORE Generator Help". // The synthesis directives "translate_off/translate_on" specified below are // supported by Xilinx, Mentor Graphics and Synplicity synthesis // tools. Ensure they are correct for your synthesis tool(s). `timescale 1ns/1ps module msu_databuf( clka, wea, addra, dina, clkb, addrb, doutb ); input clka; input [0 : 0] wea; input [13 : 0] addra; input [7 : 0] dina; input clkb; input [13 : 0] addrb; output [7 : 0] doutb; // synthesis translate_off BLK_MEM_GEN_V7_3 #( .C_ADDRA_WIDTH(14), .C_ADDRB_WIDTH(14), .C_ALGORITHM(1), .C_AXI_ID_WIDTH(4), .C_AXI_SLAVE_TYPE(0), .C_AXI_TYPE(1), .C_BYTE_SIZE(9), .C_COMMON_CLK(1), .C_DEFAULT_DATA("0"), .C_DISABLE_WARN_BHV_COLL(0), .C_DISABLE_WARN_BHV_RANGE(0), .C_ENABLE_32BIT_ADDRESS(0), .C_FAMILY("spartan3"), .C_HAS_AXI_ID(0), .C_HAS_ENA(0), .C_HAS_ENB(0), .C_HAS_INJECTERR(0), .C_HAS_MEM_OUTPUT_REGS_A(0), .C_HAS_MEM_OUTPUT_REGS_B(0), .C_HAS_MUX_OUTPUT_REGS_A(0), .C_HAS_MUX_OUTPUT_REGS_B(0), .C_HAS_REGCEA(0), .C_HAS_REGCEB(0), .C_HAS_RSTA(0), .C_HAS_RSTB(0), .C_HAS_SOFTECC_INPUT_REGS_A(0), .C_HAS_SOFTECC_OUTPUT_REGS_B(0), .C_INIT_FILE("BlankString"), .C_INIT_FILE_NAME("no_coe_file_loaded"), .C_INITA_VAL("0"), .C_INITB_VAL("0"), .C_INTERFACE_TYPE(0), .C_LOAD_INIT_FILE(0), .C_MEM_TYPE(1), .C_MUX_PIPELINE_STAGES(0), .C_PRIM_TYPE(1), .C_READ_DEPTH_A(16384), .C_READ_DEPTH_B(16384), .C_READ_WIDTH_A(8), .C_READ_WIDTH_B(8), .C_RST_PRIORITY_A("CE"), .C_RST_PRIORITY_B("CE"), .C_RST_TYPE("SYNC"), .C_RSTRAM_A(0), .C_RSTRAM_B(0), .C_SIM_COLLISION_CHECK("ALL"), .C_USE_BRAM_BLOCK(0), .C_USE_BYTE_WEA(0), .C_USE_BYTE_WEB(0), .C_USE_DEFAULT_DATA(0), .C_USE_ECC(0), .C_USE_SOFTECC(0), .C_WEA_WIDTH(1), .C_WEB_WIDTH(1), .C_WRITE_DEPTH_A(16384), .C_WRITE_DEPTH_B(16384), .C_WRITE_MODE_A("WRITE_FIRST"), .C_WRITE_MODE_B("WRITE_FIRST"), .C_WRITE_WIDTH_A(8), .C_WRITE_WIDTH_B(8), .C_XDEVICEFAMILY("spartan3") ) inst ( .CLKA(clka), .WEA(wea), .ADDRA(addra), .DINA(dina), .CLKB(clkb), .ADDRB(addrb), .DOUTB(doutb), .RSTA(), .ENA(), .REGCEA(), .DOUTA(), .RSTB(), .ENB(), .REGCEB(), .WEB(), .DINB(), .INJECTSBITERR(), .INJECTDBITERR(), .SBITERR(), .DBITERR(), .RDADDRECC(), .S_ACLK(), .S_ARESETN(), .S_AXI_AWID(), .S_AXI_AWADDR(), .S_AXI_AWLEN(), .S_AXI_AWSIZE(), .S_AXI_AWBURST(), .S_AXI_AWVALID(), .S_AXI_AWREADY(), .S_AXI_WDATA(), .S_AXI_WSTRB(), .S_AXI_WLAST(), .S_AXI_WVALID(), .S_AXI_WREADY(), .S_AXI_BID(), .S_AXI_BRESP(), .S_AXI_BVALID(), .S_AXI_BREADY(), .S_AXI_ARID(), .S_AXI_ARADDR(), .S_AXI_ARLEN(), .S_AXI_ARSIZE(), .S_AXI_ARBURST(), .S_AXI_ARVALID(), .S_AXI_ARREADY(), .S_AXI_RID(), .S_AXI_RDATA(), .S_AXI_RRESP(), .S_AXI_RLAST(), .S_AXI_RVALID(), .S_AXI_RREADY(), .S_AXI_INJECTSBITERR(), .S_AXI_INJECTDBITERR(), .S_AXI_SBITERR(), .S_AXI_DBITERR(), .S_AXI_RDADDRECC() ); // synthesis translate_on endmodule
/* ---------------------------------------------------------------------------------- Copyright (c) 2013-2014 Embedded and Network Computing Lab. Open SSD Project Hanyang University All rights reserved. ---------------------------------------------------------------------------------- Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. All advertising materials mentioning features or use of this source code must display the following acknowledgement: This product includes source code developed by the Embedded and Network Computing Lab. and the Open SSD Project. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------------- http://enclab.hanyang.ac.kr/ http://www.openssd-project.org/ http://www.hanyang.ac.kr/ ---------------------------------------------------------------------------------- */ `timescale 1ns / 1ps module pcie_tx_dma # ( parameter C_PCIE_DATA_WIDTH = 128, parameter C_PCIE_ADDR_WIDTH = 36, parameter C_M_AXI_DATA_WIDTH = 64 ) ( input pcie_user_clk, input pcie_user_rst_n, input [2:0] pcie_max_payload_size, input pcie_tx_cmd_wr_en, input [33:0] pcie_tx_cmd_wr_data, output pcie_tx_cmd_full_n, output tx_dma_mwr_req, output [7:0] tx_dma_mwr_tag, output [11:2] tx_dma_mwr_len, output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mwr_addr, input tx_dma_mwr_req_ack, input tx_dma_mwr_data_last, input pcie_tx_dma_fifo_rd_en, output [C_PCIE_DATA_WIDTH-1:0] pcie_tx_dma_fifo_rd_data, output dma_tx_done_wr_en, output [20:0] dma_tx_done_wr_data, input dma_tx_done_wr_rdy_n, input dma_bus_clk, input dma_bus_rst_n, input pcie_tx_fifo_alloc_en, input [9:4] pcie_tx_fifo_alloc_len, input pcie_tx_fifo_wr_en, input [C_M_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data, output pcie_tx_fifo_full_n ); wire w_pcie_tx_cmd_rd_en; wire [33:0] w_pcie_tx_cmd_rd_data; wire w_pcie_tx_cmd_empty_n; wire w_pcie_tx_fifo_free_en; wire [9:4] w_pcie_tx_fifo_free_len; wire w_pcie_tx_fifo_empty_n; pcie_tx_cmd_fifo pcie_tx_cmd_fifo_inst0 ( .clk (pcie_user_clk), .rst_n (pcie_user_rst_n), .wr_en (pcie_tx_cmd_wr_en), .wr_data (pcie_tx_cmd_wr_data), .full_n (pcie_tx_cmd_full_n), .rd_en (w_pcie_tx_cmd_rd_en), .rd_data (w_pcie_tx_cmd_rd_data), .empty_n (w_pcie_tx_cmd_empty_n) ); pcie_tx_fifo pcie_tx_fifo_inst0 ( .wr_clk (dma_bus_clk), .wr_rst_n (pcie_user_rst_n), .alloc_en (pcie_tx_fifo_alloc_en), .alloc_len (pcie_tx_fifo_alloc_len), .wr_en (pcie_tx_fifo_wr_en), .wr_data (pcie_tx_fifo_wr_data), .full_n (pcie_tx_fifo_full_n), .rd_clk (pcie_user_clk), .rd_rst_n (pcie_user_rst_n), .rd_en (pcie_tx_dma_fifo_rd_en), .rd_data (pcie_tx_dma_fifo_rd_data), .free_en (w_pcie_tx_fifo_free_en), .free_len (w_pcie_tx_fifo_free_len), .empty_n (w_pcie_tx_fifo_empty_n) ); pcie_tx_req # ( .C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH), .C_PCIE_ADDR_WIDTH (C_PCIE_ADDR_WIDTH) ) pcie_tx_req_inst0( .pcie_user_clk (pcie_user_clk), .pcie_user_rst_n (pcie_user_rst_n), .pcie_max_payload_size (pcie_max_payload_size), .pcie_tx_cmd_rd_en (w_pcie_tx_cmd_rd_en), .pcie_tx_cmd_rd_data (w_pcie_tx_cmd_rd_data), .pcie_tx_cmd_empty_n (w_pcie_tx_cmd_empty_n), .pcie_tx_fifo_free_en (w_pcie_tx_fifo_free_en), .pcie_tx_fifo_free_len (w_pcie_tx_fifo_free_len), .pcie_tx_fifo_empty_n (w_pcie_tx_fifo_empty_n), .tx_dma_mwr_req (tx_dma_mwr_req), .tx_dma_mwr_tag (tx_dma_mwr_tag), .tx_dma_mwr_len (tx_dma_mwr_len), .tx_dma_mwr_addr (tx_dma_mwr_addr), .tx_dma_mwr_req_ack (tx_dma_mwr_req_ack), .tx_dma_mwr_data_last (tx_dma_mwr_data_last), .dma_tx_done_wr_en (dma_tx_done_wr_en), .dma_tx_done_wr_data (dma_tx_done_wr_data), .dma_tx_done_wr_rdy_n (dma_tx_done_wr_rdy_n) ); endmodule
///////////////////////////////////////////////////////////////////////// // Copyright (c) 2008 Xilinx, Inc. All rights reserved. // // XILINX CONFIDENTIAL PROPERTY // This document contains proprietary information which is // protected by copyright. All rights are reserved. This notice // refers to original work by Xilinx, Inc. which may be derivitive // of other work distributed under license of the authors. In the // case of derivitive work, nothing in this notice overrides the // original author's license agreeement. Where applicable, the // original license agreement is included in it's original // unmodified form immediately below this header. // // Xilinx, Inc. // XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A // COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS // ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR // STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION // IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE // FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. // XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO // THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO // ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE // FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY // AND FITNESS FOR A PARTICULAR PURPOSE. // ///////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////// //// //// //// OR1200's register file read operands mux //// //// //// //// This file is part of the OpenRISC 1200 project //// //// http://www.opencores.org/cores/or1k/ //// //// //// //// Description //// //// Mux for two register file read operands. //// //// //// //// To Do: //// //// - make it smaller and faster //// //// //// //// Author(s): //// //// - Damjan Lampret, [email protected] //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: or1200_operandmuxes.v,v $ // Revision 1.1 2008/05/07 22:43:22 daughtry // Initial Demo RTL check-in // // Revision 1.2 2002/03/29 15:16:56 lampret // Some of the warnings fixed. // // Revision 1.1 2002/01/03 08:16:15 lampret // New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. // // Revision 1.9 2001/11/12 01:45:40 lampret // Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. // // Revision 1.8 2001/10/21 17:57:16 lampret // Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. // // Revision 1.7 2001/10/14 13:12:09 lampret // MP3 version. // // Revision 1.1.1.1 2001/10/06 10:18:36 igorm // no message // // Revision 1.2 2001/08/09 13:39:33 lampret // Major clean-up. // // Revision 1.1 2001/07/20 00:46:05 lampret // Development version of RTL. Libraries are missing. // // // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "or1200_defines.v" module or1200_operandmuxes( // Clock and reset clk, rst, // Internal i/f id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw, simm, sel_a, sel_b, operand_a, operand_b, muxed_b ); parameter width = `OR1200_OPERAND_WIDTH; // // I/O // input clk; input rst; input id_freeze; input ex_freeze; input [width-1:0] rf_dataa; input [width-1:0] rf_datab; input [width-1:0] ex_forw; input [width-1:0] wb_forw; input [width-1:0] simm; input [`OR1200_SEL_WIDTH-1:0] sel_a; input [`OR1200_SEL_WIDTH-1:0] sel_b; output [width-1:0] operand_a; output [width-1:0] operand_b; output [width-1:0] muxed_b; // // Internal wires and regs // reg [width-1:0] operand_a; reg [width-1:0] operand_b; reg [width-1:0] muxed_a; reg [width-1:0] muxed_b; reg saved_a; reg saved_b; // // Operand A register // always @(posedge clk or posedge rst) begin if (rst) begin operand_a <= #1 32'd0; saved_a <= #1 1'b0; end else if (!ex_freeze && id_freeze && !saved_a) begin operand_a <= #1 muxed_a; saved_a <= #1 1'b1; end else if (!ex_freeze && !saved_a) begin operand_a <= #1 muxed_a; end else if (!ex_freeze && !id_freeze) saved_a <= #1 1'b0; end // // Operand B register // always @(posedge clk or posedge rst) begin if (rst) begin operand_b <= #1 32'd0; saved_b <= #1 1'b0; end else if (!ex_freeze && id_freeze && !saved_b) begin operand_b <= #1 muxed_b; saved_b <= #1 1'b1; end else if (!ex_freeze && !saved_b) begin operand_b <= #1 muxed_b; end else if (!ex_freeze && !id_freeze) saved_b <= #1 1'b0; end // // Forwarding logic for operand A register // always @(ex_forw or wb_forw or rf_dataa or sel_a) begin `ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES casex (sel_a) // synopsys parallel_case infer_mux `else casex (sel_a) // synopsys parallel_case `endif `OR1200_SEL_EX_FORW: muxed_a = ex_forw; `OR1200_SEL_WB_FORW: muxed_a = wb_forw; default: muxed_a = rf_dataa; endcase end // // Forwarding logic for operand B register // always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin `ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES casex (sel_b) // synopsys parallel_case infer_mux `else casex (sel_b) // synopsys parallel_case `endif `OR1200_SEL_IMM: muxed_b = simm; `OR1200_SEL_EX_FORW: muxed_b = ex_forw; `OR1200_SEL_WB_FORW: muxed_b = wb_forw; default: muxed_b = rf_datab; endcase end endmodule
// megafunction wizard: %FIFO% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: dcfifo // ============================================================ // File Name: adc_data_fifo.v // Megafunction Name(s): // dcfifo // // Simulation Library Files(s): // altera_mf // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 13.0.1 Build 232 06/12/2013 SP 1.dp1 SJ Full Version // ************************************************************ //Copyright (C) 1991-2013 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module adc_data_fifo ( aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, wrfull); input aclr; input [11:0] data; input rdclk; input rdreq; input wrclk; input wrreq; output [11:0] q; output rdempty; output wrfull; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri0 aclr; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif wire sub_wire0; wire [11:0] sub_wire1; wire sub_wire2; wire wrfull = sub_wire0; wire [11:0] q = sub_wire1[11:0]; wire rdempty = sub_wire2; dcfifo dcfifo_component ( .rdclk (rdclk), .wrclk (wrclk), .wrreq (wrreq), .aclr (aclr), .data (data), .rdreq (rdreq), .wrfull (sub_wire0), .q (sub_wire1), .rdempty (sub_wire2), .rdfull (), .rdusedw (), .wrempty (), .wrusedw ()); defparam dcfifo_component.intended_device_family = "Cyclone V", dcfifo_component.lpm_numwords = 2048, dcfifo_component.lpm_showahead = "ON", dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = 12, dcfifo_component.lpm_widthu = 11, dcfifo_component.overflow_checking = "ON", dcfifo_component.rdsync_delaypipe = 4, dcfifo_component.read_aclr_synch = "OFF", dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON", dcfifo_component.write_aclr_synch = "OFF", dcfifo_component.wrsync_delaypipe = 4; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" // Retrieval info: PRIVATE: AlmostFull NUMERIC "0" // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" // Retrieval info: PRIVATE: Clock NUMERIC "4" // Retrieval info: PRIVATE: Depth NUMERIC "2048" // Retrieval info: PRIVATE: Empty NUMERIC "1" // Retrieval info: PRIVATE: Full NUMERIC "1" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" // Retrieval info: PRIVATE: Optimize NUMERIC "0" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" // Retrieval info: PRIVATE: UsedW NUMERIC "1" // Retrieval info: PRIVATE: Width NUMERIC "12" // Retrieval info: PRIVATE: dc_aclr NUMERIC "1" // Retrieval info: PRIVATE: diff_widths NUMERIC "0" // Retrieval info: PRIVATE: msb_usedw NUMERIC "0" // Retrieval info: PRIVATE: output_width NUMERIC "12" // Retrieval info: PRIVATE: rsEmpty NUMERIC "1" // Retrieval info: PRIVATE: rsFull NUMERIC "0" // Retrieval info: PRIVATE: rsUsedW NUMERIC "0" // Retrieval info: PRIVATE: sc_aclr NUMERIC "0" // Retrieval info: PRIVATE: sc_sclr NUMERIC "0" // Retrieval info: PRIVATE: wsEmpty NUMERIC "0" // Retrieval info: PRIVATE: wsFull NUMERIC "1" // Retrieval info: PRIVATE: wsUsedW NUMERIC "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048" // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12" // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11" // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" // Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" // Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF" // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" // Retrieval info: CONSTANT: USE_EAB STRING "ON" // Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" // Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr" // Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL "data[11..0]" // Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]" // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" // Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty" // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" // Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull" // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 // Retrieval info: CONNECT: @data 0 0 12 0 data 0 0 12 0 // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 // Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0 // Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 // Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 // Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo_bb.v TRUE // Retrieval info: LIB_FILE: altera_mf
// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2003 by Wilson Snyder. module t (/*AUTOARG*/ // Inputs fastclk ); input fastclk; t_netlist tnetlist (.also_fastclk (fastclk), /*AUTOINST*/ // Inputs .fastclk (fastclk)); endmodule module t_netlist (/*AUTOARG*/ // Inputs fastclk, also_fastclk ); // surefire lint_off ASWEMB input fastclk; input also_fastclk; integer _mode; initial _mode = 0; // This entire module should optimize to nearly nothing... // verilator lint_off UNOPTFLAT reg [4:0] a,a2,b,c,d,e; // verilator lint_on UNOPTFLAT initial a=5'd1; always @ (posedge fastclk) begin b <= a+5'd1; c <= b+5'd1; // Better for ordering if this moves before previous statement end // verilator lint_off UNOPT always @ (d or /*AS*/a or c) begin e = d+5'd1; a2 = a+5'd1; // This can be pulled out of the middle of the always d = c+5'd1; // Better for ordering if this moves before previous statement end // verilator lint_on UNOPT always @ (posedge also_fastclk) begin if (_mode==5) begin if (a2 != 5'd2) $stop; if (e != 5'd5) $stop; $write("*-* All Finished *-*\n"); $finish; end _mode <= _mode + 1; end endmodule
//***************************************************************************** // (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 2.0 // \ \ Application : MIG // / / Filename : wiredly.v // /___/ /\ Date Last Modified : $Date: 2011/06/23 08:25:20 $ // \ \ / \ Date Created : Fri Oct 14 2011 // \___\/\___\ // // Device : 7Series // Design Name : DDR2 SDRAM // Purpose : // This module provide the definition of a zero ohm component (A, B). // // The applications of this component include: // . Normal operation of a jumper wire (data flowing in both directions) // This can corrupt data from DRAM to FPGA useful for verifying ECC function. // // The component consists of 2 ports: // . Port A: One side of the pass-through switch // . Port B: The other side of the pass-through switch // The model is sensitive to transactions on all ports. Once a transaction // is detected, all other transactions are ignored for that simulation time // (i.e. further transactions in that delta time are ignored). // Model Limitations and Restrictions: // Signals asserted on the ports of the error injector should not have // transactions occuring in multiple delta times because the model // is sensitive to transactions on port A, B ONLY ONCE during // a simulation time. Thus, once fired, a process will // not refire if there are multiple transactions occuring in delta times. // This condition may occur in gate level simulations with // ZERO delays because transactions may occur in multiple delta times. // // Reference : // Revision History : //***************************************************************************** `timescale 1ns / 1ps module WireDelay # ( parameter Delay_g = 0, parameter Delay_rd = 0, parameter ERR_INSERT = "OFF" ) ( inout A, inout B, input reset, input phy_init_done ); reg A_r; reg B_r; reg B_inv ; reg line_en; reg B_nonX; assign A = A_r; assign B = B_r; always @ (*) begin if (B === 1'bx) B_nonX <= $random; else B_nonX <= B; end always@(*) begin if((B_nonX == 'b1) || (B_nonX == 'b0)) B_inv <= #0 ~B_nonX ; else B_inv <= #0 'bz ; end always @(*) begin if (!reset) begin A_r <= 1'bz; B_r <= 1'bz; line_en <= 1'b0; end else begin if (line_en) begin B_r <= 1'bz; if ((ERR_INSERT == "ON") & (phy_init_done)) A_r <= #Delay_rd B_inv; else A_r <= #Delay_rd B_nonX; end else begin B_r <= #Delay_g A; A_r <= 1'bz; end end end always @(A or B) begin if (!reset) begin line_en <= 1'b0; end else if (A !== A_r) begin line_en <= 1'b0; end else if (B_r !== B) begin line_en <= 1'b1; end else begin line_en <= line_en; end end endmodule
/* * Milkymist SoC * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 3 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ module pfpu_f2i( input sys_clk, input alu_rst, input [31:0] a, input valid_i, output reg [31:0] r, output reg valid_o ); wire a_sign = a[31]; wire [7:0] a_expn = a[30:23]; wire [23:0] a_mant = {1'b1, a[22:0]}; reg [30:0] shifted; always @(*) begin if(a_expn >= 8'd150) shifted = a_mant << (a_expn - 8'd150); else shifted = a_mant >> (8'd150 - a_expn); end always @(posedge sys_clk) begin if(alu_rst) valid_o <= 1'b0; else valid_o <= valid_i; if(a_sign) r <= 32'd0 - {1'b0, shifted}; else r <= {1'b0, shifted}; end endmodule
// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Wilson Snyder. module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; wire [4:0] in = crc[4:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out), // Inputs .clk (clk), .in (in[4:0])); // Aggregate outputs into a single result vector wire [63:0] result = {63'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h7a7bd4ee927e7cc3 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); //bug718 input clk; input logic [4:0] in; output logic out; always @(posedge clk) begin out <= in inside {5'b1_1?1?}; end endmodule // t
/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BEHAVIORAL_V `define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BEHAVIORAL_V /** * lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail. * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none `celldefine module sky130_fd_sc_hd__lpflow_clkbufkapwr ( X, A ); // Module ports output X; input A; // Module supplies supply1 KAPWR; supply1 VPWR ; supply0 VGND ; supply1 VPB ; supply0 VNB ; // Local signals wire buf0_out_X; // Name Output Other arguments buf buf0 (buf0_out_X, A ); buf buf1 (X , buf0_out_X ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BEHAVIORAL_V
module test; reg [0:0] io_in_valid; reg [31:0] io_in_bits; reg [0:0] io_out_ready; reg [0:0] io_pcIn_valid; reg [0:0] io_pcIn_bits_request; reg [15:0] io_pcIn_bits_moduleId; reg [7:0] io_pcIn_bits_portId; reg [15:0] io_pcIn_bits_pcValue; reg [3:0] io_pcIn_bits_pcType; wire [0:0] io_in_ready; wire [0:0] io_out_valid; wire [31:0] io_out_bits; wire [0:0] io_pcOut_valid; wire [0:0] io_pcOut_bits_request; wire [15:0] io_pcOut_bits_moduleId; wire [7:0] io_pcOut_bits_portId; wire [15:0] io_pcOut_bits_pcValue; wire [3:0] io_pcOut_bits_pcType; reg clk = 0; reg reset = 1; initial begin reset = 1; #250 reset = 0; end always #100 clk = ~clk; Offloaded Offloaded( .clk(clk), .reset(reset), .io_in_valid(io_in_valid), .io_in_bits(io_in_bits), .io_out_ready(io_out_ready), .io_pcIn_valid(io_pcIn_valid), .io_pcIn_bits_request(io_pcIn_bits_request), .io_pcIn_bits_moduleId(io_pcIn_bits_moduleId), .io_pcIn_bits_portId(io_pcIn_bits_portId), .io_pcIn_bits_pcValue(io_pcIn_bits_pcValue), .io_pcIn_bits_pcType(io_pcIn_bits_pcType), .io_in_ready(io_in_ready), .io_out_valid(io_out_valid), .io_out_bits(io_out_bits), .io_pcOut_valid(io_pcOut_valid), .io_pcOut_bits_request(io_pcOut_bits_request), .io_pcOut_bits_moduleId(io_pcOut_bits_moduleId), .io_pcOut_bits_portId(io_pcOut_bits_portId), .io_pcOut_bits_pcValue(io_pcOut_bits_pcValue), .io_pcOut_bits_pcType(io_pcOut_bits_pcType) ); integer count; always @(negedge clk) begin; #50; if (!reset) count = $fscanf('h80000000, "%x %x %x %x %x %x %x %x %x", io_in_valid, io_in_bits, io_out_ready, io_pcIn_valid, io_pcIn_bits_request, io_pcIn_bits_moduleId, io_pcIn_bits_portId, io_pcIn_bits_pcValue, io_pcIn_bits_pcType); if (count == -1) $finish(1); end always @(posedge clk) begin if (!reset) $display("0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x", io_in_ready, io_out_valid, io_out_bits, io_pcOut_valid, io_pcOut_bits_request, io_pcOut_bits_moduleId, io_pcOut_bits_portId, io_pcOut_bits_pcValue, io_pcOut_bits_pcType); end endmodule
// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Wilson Snyder. module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[31:0]), // Inputs .clk (clk), .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h458c2de282e30f8b if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); input clk; input [31:0] in; output wire [31:0] out; reg [31:0] stage [3:0]; genvar g; generate for (g=0; g<4; g++) begin always_comb begin if (g==0) stage[g] = in; else stage[g] = {stage[g-1][30:0],1'b1}; end end endgenerate assign out = stage[3]; endmodule
// ------------------------------------------------------------- // // File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Control_Current.v // Created: 2014-08-25 21:11:09 // // Generated by MATLAB 8.2 and HDL Coder 3.3 // // ------------------------------------------------------------- // ------------------------------------------------------------- // // Module: velocityControlHdl_Control_Current // Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current // Hierarchy Level: 5 // // ------------------------------------------------------------- `timescale 1 ns / 1 ns module velocityControlHdl_Control_Current ( CLK_IN, reset, enb_1_2000_0, Reest, Err, param_current_p_gain, param_current_i_gain, Out ); input CLK_IN; input reset; input enb_1_2000_0; input Reest; input signed [17:0] Err; // sfix18_En14 input signed [17:0] param_current_p_gain; // sfix18_En10 input signed [17:0] param_current_i_gain; // sfix18_En2 output signed [17:0] Out; // sfix18_En12 wire signed [35:0] Product2_out1; // sfix36_En24 wire signed [35:0] Convert_Data_Type1_out1; // sfix36_En23 wire signed [17:0] Constant2_out1; // sfix18_En31 wire signed [35:0] Product_out1; // sfix36_En33 wire signed [17:0] pre_integrator; // sfix18_En15 wire signed [35:0] pre_integrator_1; // sfix36_En29 wire signed [35:0] Constant_out1; // sfix36_En29 wire signed [35:0] u; // sfix36_En23 wire PI_Sat_out2; wire Clamp_out1; wire switch_compare_1; wire signed [35:0] Switch_out1; // sfix36_En29 wire signed [31:0] I_term; // sfix32_En26 wire signed [36:0] Add_add_cast; // sfix37_En29 wire signed [36:0] Add_add_cast_1; // sfix37_En29 wire signed [36:0] Add_add_temp; // sfix37_En29 wire signed [31:0] Add_out1; // sfix32_En26 wire signed [39:0] Sum1_add_cast; // sfix40_En26 wire signed [39:0] Sum1_add_cast_1; // sfix40_En26 wire signed [39:0] Sum1_add_temp; // sfix40_En26 wire signed [35:0] u_sat; // sfix36_En23 wire signed [17:0] D_Data_Type_out1; // sfix18_En12 // Control Current // <S7>/Product2 assign Product2_out1 = param_current_p_gain * Err; // <S7>/Convert_Data_Type1 velocityControlHdl_Convert_Data_Type1 u_Convert_Data_Type1 (.In1(Product2_out1), // sfix36_En24 .Out1(Convert_Data_Type1_out1) // sfix36_En23 ); // <S7>/Constant2 assign Constant2_out1 = 18'sb010100111110001011; // <S7>/Product assign Product_out1 = param_current_i_gain * Constant2_out1; // <S7>/Maintain_Range velocityControlHdl_Maintain_Range u_Maintain_Range (.In1(Product_out1), // sfix36_En33 .Out1(pre_integrator) // sfix18_En15 ); // <S7>/Product1 assign pre_integrator_1 = Err * pre_integrator; // <S7>/Constant assign Constant_out1 = 36'sh000000000; // <S7>/Clamp velocityControlHdl_Clamp u_Clamp (.preIntegrator(pre_integrator_1), // sfix36_En29 .preSat(u), // sfix36_En23 .saturated(PI_Sat_out2), .Clamp(Clamp_out1) ); assign switch_compare_1 = (Clamp_out1 > 1'b0 ? 1'b1 : 1'b0); // <S7>/Switch assign Switch_out1 = (switch_compare_1 == 1'b0 ? pre_integrator_1 : Constant_out1); // <S7>/Add assign Add_add_cast = Switch_out1; assign Add_add_cast_1 = {{2{I_term[31]}}, {I_term, 3'b000}}; assign Add_add_temp = Add_add_cast + Add_add_cast_1; assign Add_out1 = ((Add_add_temp[36] == 1'b0) && (Add_add_temp[35:34] != 2'b00) ? 32'sb01111111111111111111111111111111 : ((Add_add_temp[36] == 1'b1) && (Add_add_temp[35:34] != 2'b11) ? 32'sb10000000000000000000000000000000 : $signed(Add_add_temp[34:3]))); // <S7>/Reset_Delay velocityControlHdl_Reset_Delay u_Reset_Delay (.CLK_IN(CLK_IN), .reset(reset), .enb_1_2000_0(enb_1_2000_0), .Reset_1(Reest), .In(Add_out1), // sfix32_En26 .Out(I_term) // sfix32_En26 ); // <S7>/Sum1 assign Sum1_add_cast = {Convert_Data_Type1_out1[35], {Convert_Data_Type1_out1, 3'b000}}; assign Sum1_add_cast_1 = I_term; assign Sum1_add_temp = Sum1_add_cast + Sum1_add_cast_1; assign u = Sum1_add_temp[38:3]; // <S7>/PI_Sat velocityControlHdl_PI_Sat u_PI_Sat (.In1(u), // sfix36_En23 .Out1(u_sat), // sfix36_En23 .saturated(PI_Sat_out2) ); // <S7>/D_Data_Type assign D_Data_Type_out1 = u_sat[28:11]; assign Out = D_Data_Type_out1; endmodule // velocityControlHdl_Control_Current
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HD__A21O_BLACKBOX_V `define SKY130_FD_SC_HD__A21O_BLACKBOX_V /** * a21o: 2-input AND into first input of 2-input OR. * * X = ((A1 & A2) | B1) * * Verilog stub definition (black box without power pins). * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_hd__a21o ( X , A1, A2, B1 ); output X ; input A1; input A2; input B1; // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; endmodule `default_nettype wire `endif // SKY130_FD_SC_HD__A21O_BLACKBOX_V
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HD__O22AI_1_V `define SKY130_FD_SC_HD__O22AI_1_V /** * o22ai: 2-input OR into both inputs of 2-input NAND. * * Y = !((A1 | A2) & (B1 | B2)) * * Verilog wrapper for o22ai with size of 1 units. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none `include "sky130_fd_sc_hd__o22ai.v" `ifdef USE_POWER_PINS /*********************************************************/ `celldefine module sky130_fd_sc_hd__o22ai_1 ( Y , A1 , A2 , B1 , B2 , VPWR, VGND, VPB , VNB ); output Y ; input A1 ; input A2 ; input B1 ; input B2 ; input VPWR; input VGND; input VPB ; input VNB ; sky130_fd_sc_hd__o22ai base ( .Y(Y), .A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB) ); endmodule `endcelldefine /*********************************************************/ `else // If not USE_POWER_PINS /*********************************************************/ `celldefine module sky130_fd_sc_hd__o22ai_1 ( Y , A1, A2, B1, B2 ); output Y ; input A1; input A2; input B1; input B2; // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; sky130_fd_sc_hd__o22ai base ( .Y(Y), .A1(A1), .A2(A2), .B1(B1), .B2(B2) ); endmodule `endcelldefine /*********************************************************/ `endif // USE_POWER_PINS `default_nettype wire `endif // SKY130_FD_SC_HD__O22AI_1_V
/* * Copyright (c) 2000 Stephen Williams ([email protected]) * * This source code is free software; you can redistribute it * and/or modify it in source code form under the terms of the GNU * General Public License as published by the Free Software * Foundation; either version 2 of the License, or (at your option) * any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ /* * This test checks that times within modules are scaled up to the * precision of the simulation. */ `timescale 100us / 1us module slow (out); output out; reg out; initial begin #0 out = 0; #1 out = 1; end endmodule // slow `timescale 10us / 1us module fast (out); output out; reg out; initial begin #0 out = 0; #1 out = 1; end endmodule // fast `timescale 1us / 1us module main; wire slow, fast; slow m1 (slow); fast m2 (fast); initial begin #5 if (slow !== 1'b0) begin $display("FAILED"); $finish; end if (fast !== 1'b0) begin $display("FAILED"); $finish; end #10 if (slow !== 1'b0) begin $display("FAILED"); $finish; end if (fast !== 1'b1) begin $display("FAILED"); $finish; end #80 if (slow !== 1'b0) begin $display("FAILED"); $finish; end if (fast !== 1'b1) begin $display("FAILED"); $finish; end #10 if (slow !== 1'b1) begin $display("FAILED"); $finish; end if (fast !== 1'b1) begin $display("FAILED"); $finish; end $display("PASSED"); end // initial begin endmodule // main
(************************************************************************) (* * The Coq Proof Assistant / The Coq Development Team *) (* v * Copyright INRIA, CNRS and contributors *) (* <O___,, * (see version control and CREDITS file for authors & dates) *) (* \VV/ **************************************************************) (* // * This file is distributed under the terms of the *) (* * GNU Lesser General Public License Version 2.1 *) (* * (see LICENSE file for the text of the license) *) (************************************************************************) Require Export NumPrelude NZAxioms. Require Import NZBase NZOrder NZAddOrder Plus Minus. (** In this file, we investigate the shape of domains satisfying the [NZDomainSig] interface. In particular, we define a translation from Peano numbers [nat] into NZ. *) Local Notation "f ^ n" := (fun x => nat_rect _ x (fun _ => f) n). #[global] Instance nat_rect_wd n {A} (R:relation A) : Proper (R==>(R==>R)==>R) (fun x f => nat_rect (fun _ => _) x (fun _ => f) n). Proof. intros x y eq_xy f g eq_fg; induction n; [assumption | now apply eq_fg]. Qed. Module NZDomainProp (Import NZ:NZDomainSig'). Include NZBaseProp NZ. (** * Relationship between points thanks to [succ] and [pred]. *) (** For any two points, one is an iterated successor of the other. *) Lemma itersucc_or_itersucc n m : exists k, n == (S^k) m \/ m == (S^k) n. Proof. revert n. apply central_induction with (z:=m). { intros x y eq_xy; apply ex_iff_morphism. intros n; apply or_iff_morphism. + split; intros; etransitivity; try eassumption; now symmetry. + split; intros; (etransitivity; [eassumption|]); [|symmetry]; (eapply nat_rect_wd; [eassumption|apply succ_wd]). } exists 0%nat. now left. intros n. split; intros [k [L|R]]. exists (Datatypes.S k). left. now apply succ_wd. destruct k as [|k]. simpl in R. exists 1%nat. left. now apply succ_wd. rewrite nat_rect_succ_r in R. exists k. now right. destruct k as [|k]; simpl in L. exists 1%nat. now right. apply succ_inj in L. exists k. now left. exists (Datatypes.S k). right. now rewrite nat_rect_succ_r. Qed. (** Generalized version of [pred_succ] when iterating *) Lemma succ_swap_pred : forall k n m, n == (S^k) m -> m == (P^k) n. Proof. induction k. simpl; auto with *. simpl; intros. apply pred_wd in H. rewrite pred_succ in H. apply IHk in H; auto. rewrite <- nat_rect_succ_r in H; auto. Qed. (** From a given point, all others are iterated successors or iterated predecessors. *) Lemma itersucc_or_iterpred : forall n m, exists k, n == (S^k) m \/ n == (P^k) m. Proof. intros n m. destruct (itersucc_or_itersucc n m) as (k,[H|H]). exists k; left; auto. exists k; right. apply succ_swap_pred; auto. Qed. (** In particular, all points are either iterated successors of [0] or iterated predecessors of [0] (or both). *) Lemma itersucc0_or_iterpred0 : forall n, exists p:nat, n == (S^p) 0 \/ n == (P^p) 0. Proof. intros n. exact (itersucc_or_iterpred n 0). Qed. (** * Study of initial point w.r.t. [succ] (if any). *) Definition initial n := forall m, n ~= S m. Lemma initial_alt : forall n, initial n <-> S (P n) ~= n. Proof. split. intros Bn EQ. symmetry in EQ. destruct (Bn _ EQ). intros NEQ m EQ. apply NEQ. rewrite EQ, pred_succ; auto with *. Qed. Lemma initial_alt2 : forall n, initial n <-> ~exists m, n == S m. Proof. firstorder. Qed. (** First case: let's assume such an initial point exists (i.e. [S] isn't surjective)... *) Section InitialExists. Hypothesis init : t. Hypothesis Initial : initial init. (** ... then we have unicity of this initial point. *) Lemma initial_unique : forall m, initial m -> m == init. Proof. intros m Im. destruct (itersucc_or_itersucc init m) as (p,[H|H]). destruct p. now simpl in *. destruct (Initial _ H). destruct p. now simpl in *. destruct (Im _ H). Qed. (** ... then all other points are descendant of it. *) Lemma initial_ancestor : forall m, exists p, m == (S^p) init. Proof. intros m. destruct (itersucc_or_itersucc init m) as (p,[H|H]). destruct p; simpl in *; auto. exists O; auto with *. destruct (Initial _ H). exists p; auto. Qed. (** NB : We would like to have [pred n == n] for the initial element, but nothing forces that. For instance we can have -3 as initial point, and P(-3) = 2. A bit odd indeed, but legal according to [NZDomainSig]. We can hence have [n == (P^k) m] without [exists k', m == (S^k') n]. *) (** We need decidability of [eq] (or classical reasoning) for this: *) Section SuccPred. Hypothesis eq_decidable : forall n m, n==m \/ n~=m. Lemma succ_pred_approx : forall n, ~initial n -> S (P n) == n. Proof. intros n NB. rewrite initial_alt in NB. destruct (eq_decidable (S (P n)) n); auto. elim NB; auto. Qed. End SuccPred. End InitialExists. (** Second case : let's suppose now [S] surjective, i.e. no initial point. *) Section InitialDontExists. Hypothesis succ_onto : forall n, exists m, n == S m. Lemma succ_onto_gives_succ_pred : forall n, S (P n) == n. Proof. intros n. destruct (succ_onto n) as (m,H). rewrite H, pred_succ; auto with *. Qed. Lemma succ_onto_pred_injective : forall n m, P n == P m -> n == m. Proof. intros n m. intros H; apply succ_wd in H. rewrite !succ_onto_gives_succ_pred in H; auto. Qed. End InitialDontExists. (** To summarize: S is always injective, P is always surjective (thanks to [pred_succ]). I) If S is not surjective, we have an initial point, which is unique. This bottom is below zero: we have N shifted (or not) to the left. P cannot be injective: P init = P (S (P init)). (P init) can be arbitrary. II) If S is surjective, we have [forall n, S (P n) = n], S and P are bijective and reciprocal. IIa) if [exists k<>O, 0 == S^k 0], then we have a cyclic structure Z/nZ IIb) otherwise, we have Z *) (** * An alternative induction principle using [S] and [P]. *) (** It is weaker than [bi_induction]. For instance it cannot prove that we can go from one point by many [S] _or_ many [P], but only by many [S] mixed with many [P]. Think of a model with two copies of N: 0, 1=S 0, 2=S 1, ... 0', 1'=S 0', 2'=S 1', ... and P 0 = 0' and P 0' = 0. *) Lemma bi_induction_pred : forall A : t -> Prop, Proper (eq==>iff) A -> A 0 -> (forall n, A n -> A (S n)) -> (forall n, A n -> A (P n)) -> forall n, A n. Proof. intros. apply bi_induction; auto. clear n. intros n; split; auto. intros G; apply H2 in G. rewrite pred_succ in G; auto. Qed. Lemma central_induction_pred : forall A : t -> Prop, Proper (eq==>iff) A -> forall n0, A n0 -> (forall n, A n -> A (S n)) -> (forall n, A n -> A (P n)) -> forall n, A n. Proof. intros. assert (A 0). destruct (itersucc_or_iterpred 0 n0) as (k,[Hk|Hk]); rewrite Hk; clear Hk. clear H2. induction k; simpl in *; auto. clear H1. induction k; simpl in *; auto. apply bi_induction_pred; auto. Qed. End NZDomainProp. (** We now focus on the translation from [nat] into [NZ]. First, relationship with [0], [succ], [pred]. *) Module NZOfNat (Import NZ:NZDomainSig'). Definition ofnat (n : nat) : t := (S^n) 0. Declare Scope ofnat. Local Open Scope ofnat. Notation "[ n ]" := (ofnat n) (at level 7) : ofnat. Lemma ofnat_zero : [O] == 0. Proof. reflexivity. Qed. Lemma ofnat_succ : forall n, [Datatypes.S n] == succ [n]. Proof. now unfold ofnat. Qed. Lemma ofnat_pred : forall n, n<>O -> [Peano.pred n] == P [n]. Proof. unfold ofnat. destruct n. destruct 1; auto. intros _. simpl. symmetry. apply pred_succ. Qed. (** Since [P 0] can be anything in NZ (either [-1], [0], or even other numbers, we cannot state previous lemma for [n=O]. *) End NZOfNat. (** If we require in addition a strict order on NZ, we can prove that [ofnat] is injective, and hence that NZ is infinite (i.e. we ban Z/nZ models) *) Module NZOfNatOrd (Import NZ:NZOrdSig'). Include NZOfNat NZ. Include NZBaseProp NZ <+ NZOrderProp NZ. Local Open Scope ofnat. Theorem ofnat_S_gt_0 : forall n : nat, 0 < [Datatypes.S n]. Proof. unfold ofnat. intros n; induction n as [| n IH]; simpl in *. apply lt_succ_diag_r. apply lt_trans with (S 0). apply lt_succ_diag_r. now rewrite <- succ_lt_mono. Qed. Theorem ofnat_S_neq_0 : forall n : nat, 0 ~= [Datatypes.S n]. Proof. intros. apply lt_neq, ofnat_S_gt_0. Qed. Lemma ofnat_injective : forall n m, [n]==[m] -> n = m. Proof. induction n as [|n IH]; destruct m; auto. intros H; elim (ofnat_S_neq_0 _ H). intros H; symmetry in H; elim (ofnat_S_neq_0 _ H). intros. f_equal. apply IH. now rewrite <- succ_inj_wd. Qed. Lemma ofnat_eq : forall n m, [n]==[m] <-> n = m. Proof. split. apply ofnat_injective. intros; now subst. Qed. (* In addition, we can prove that [ofnat] preserves order. *) Lemma ofnat_lt : forall n m : nat, [n]<[m] <-> (n<m)%nat. Proof. induction n as [|n IH]; destruct m; repeat rewrite ofnat_zero; split. intro H; elim (lt_irrefl _ H). inversion 1. auto with arith. intros; apply ofnat_S_gt_0. intro H; elim (lt_asymm _ _ H); apply ofnat_S_gt_0. inversion 1. rewrite !ofnat_succ, <- succ_lt_mono, IH; auto with arith. rewrite !ofnat_succ, <- succ_lt_mono, IH; auto with arith. Qed. Lemma ofnat_le : forall n m : nat, [n]<=[m] <-> (n<=m)%nat. Proof. intros. rewrite lt_eq_cases, ofnat_lt, ofnat_eq. split. destruct 1; subst; auto with arith. apply Lt.le_lt_or_eq. Qed. End NZOfNatOrd. (** For basic operations, we can prove correspondence with their counterpart in [nat]. *) Module NZOfNatOps (Import NZ:NZAxiomsSig'). Include NZOfNat NZ. Local Open Scope ofnat. Lemma ofnat_add_l : forall n m, [n]+m == (S^n) m. Proof. induction n; intros. apply add_0_l. rewrite ofnat_succ, add_succ_l. simpl. now f_equiv. Qed. Lemma ofnat_add : forall n m, [n+m] == [n]+[m]. Proof. intros. rewrite ofnat_add_l. induction n; simpl. reflexivity. now f_equiv. Qed. Lemma ofnat_mul : forall n m, [n*m] == [n]*[m]. Proof. induction n; simpl; intros. symmetry. apply mul_0_l. rewrite plus_comm. rewrite ofnat_add, mul_succ_l. now f_equiv. Qed. Lemma ofnat_sub_r : forall n m, n-[m] == (P^m) n. Proof. induction m; simpl; intros. apply sub_0_r. rewrite sub_succ_r. now f_equiv. Qed. Lemma ofnat_sub : forall n m, m<=n -> [n-m] == [n]-[m]. Proof. intros n m H. rewrite ofnat_sub_r. revert n H. induction m. intros. rewrite <- minus_n_O. now simpl. intros. destruct n. inversion H. rewrite nat_rect_succ_r. simpl. etransitivity. apply IHm. auto with arith. eapply nat_rect_wd; [symmetry;apply pred_succ|apply pred_wd]. Qed. End NZOfNatOps.
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // File name: decerr_slave.v // // Description: // Phantom slave interface used to complete W, R and B channel transfers when an // erroneous transaction is trapped in the crossbar. //-------------------------------------------------------------------------- // // Structure: // decerr_slave // //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_9_decerr_slave # ( parameter integer C_AXI_ID_WIDTH = 1, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_BUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AXI_PROTOCOL = 0, parameter integer C_RESP = 2'b11, parameter integer C_IGNORE_ID = 0 ) ( input wire ACLK, input wire ARESETN, input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID, input wire S_AXI_AWVALID, output wire S_AXI_AWREADY, input wire S_AXI_WLAST, input wire S_AXI_WVALID, output wire S_AXI_WREADY, output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID, output wire [1:0] S_AXI_BRESP, output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire S_AXI_BVALID, input wire S_AXI_BREADY, input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID, input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] S_AXI_ARLEN, input wire S_AXI_ARVALID, output wire S_AXI_ARREADY, output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID, output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA, output wire [1:0] S_AXI_RRESP, output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, output wire S_AXI_RLAST, output wire S_AXI_RVALID, input wire S_AXI_RREADY ); reg s_axi_awready_i; reg s_axi_wready_i; reg s_axi_bvalid_i; reg s_axi_arready_i; reg s_axi_rvalid_i; localparam P_WRITE_IDLE = 2'b00; localparam P_WRITE_DATA = 2'b01; localparam P_WRITE_RESP = 2'b10; localparam P_READ_IDLE = 2'b00; localparam P_READ_START = 2'b01; localparam P_READ_DATA = 2'b10; localparam integer P_AXI4 = 0; localparam integer P_AXI3 = 1; localparam integer P_AXILITE = 2; assign S_AXI_BRESP = C_RESP; assign S_AXI_RRESP = C_RESP; assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}}; assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}}; assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}}; assign S_AXI_AWREADY = s_axi_awready_i; assign S_AXI_WREADY = s_axi_wready_i; assign S_AXI_BVALID = s_axi_bvalid_i; assign S_AXI_ARREADY = s_axi_arready_i; assign S_AXI_RVALID = s_axi_rvalid_i; generate if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite reg s_axi_rvalid_en; assign S_AXI_RLAST = 1'b1; assign S_AXI_BID = 0; assign S_AXI_RID = 0; always @(posedge ACLK) begin if (~ARESETN) begin s_axi_awready_i <= 1'b0; s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b0; end else begin if (s_axi_bvalid_i) begin if (S_AXI_BREADY) begin s_axi_bvalid_i <= 1'b0; s_axi_awready_i <= 1'b1; end end else if (S_AXI_WVALID & s_axi_wready_i) begin s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b1; end else if (S_AXI_AWVALID & s_axi_awready_i) begin s_axi_awready_i <= 1'b0; s_axi_wready_i <= 1'b1; end else begin s_axi_awready_i <= 1'b1; end end end always @(posedge ACLK) begin if (~ARESETN) begin s_axi_arready_i <= 1'b0; s_axi_rvalid_i <= 1'b0; s_axi_rvalid_en <= 1'b0; end else begin if (s_axi_rvalid_i) begin if (S_AXI_RREADY) begin s_axi_rvalid_i <= 1'b0; s_axi_arready_i <= 1'b1; end end else if (s_axi_rvalid_en) begin s_axi_rvalid_en <= 1'b0; s_axi_rvalid_i <= 1'b1; end else if (S_AXI_ARVALID & s_axi_arready_i) begin s_axi_arready_i <= 1'b0; s_axi_rvalid_en <= 1'b1; end else begin s_axi_arready_i <= 1'b1; end end end end else begin : gen_axi reg s_axi_rlast_i; reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i; reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i; reg [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] read_cnt; reg [1:0] write_cs; reg [1:0] read_cs; assign S_AXI_RLAST = s_axi_rlast_i; assign S_AXI_BID = C_IGNORE_ID ? 0 : s_axi_bid_i; assign S_AXI_RID = C_IGNORE_ID ? 0 : s_axi_rid_i; always @(posedge ACLK) begin if (~ARESETN) begin write_cs <= P_WRITE_IDLE; s_axi_awready_i <= 1'b0; s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b0; s_axi_bid_i <= 0; end else begin case (write_cs) P_WRITE_IDLE: begin if (S_AXI_AWVALID & s_axi_awready_i) begin s_axi_awready_i <= 1'b0; if (C_IGNORE_ID == 0) s_axi_bid_i <= S_AXI_AWID; s_axi_wready_i <= 1'b1; write_cs <= P_WRITE_DATA; end else begin s_axi_awready_i <= 1'b1; end end P_WRITE_DATA: begin if (S_AXI_WVALID & S_AXI_WLAST) begin s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b1; write_cs <= P_WRITE_RESP; end end P_WRITE_RESP: begin if (S_AXI_BREADY) begin s_axi_bvalid_i <= 1'b0; s_axi_awready_i <= 1'b1; write_cs <= P_WRITE_IDLE; end end endcase end end always @(posedge ACLK) begin if (~ARESETN) begin read_cs <= P_READ_IDLE; s_axi_arready_i <= 1'b0; s_axi_rvalid_i <= 1'b0; s_axi_rlast_i <= 1'b0; s_axi_rid_i <= 0; read_cnt <= 0; end else begin case (read_cs) P_READ_IDLE: begin if (S_AXI_ARVALID & s_axi_arready_i) begin s_axi_arready_i <= 1'b0; if (C_IGNORE_ID == 0) s_axi_rid_i <= S_AXI_ARID; read_cnt <= S_AXI_ARLEN; s_axi_rlast_i <= (S_AXI_ARLEN == 0); read_cs <= P_READ_START; end else begin s_axi_arready_i <= 1'b1; end end P_READ_START: begin s_axi_rvalid_i <= 1'b1; read_cs <= P_READ_DATA; end P_READ_DATA: begin if (S_AXI_RREADY) begin if (read_cnt == 0) begin s_axi_rvalid_i <= 1'b0; s_axi_rlast_i <= 1'b0; s_axi_arready_i <= 1'b1; read_cs <= P_READ_IDLE; end else begin if (read_cnt == 1) begin s_axi_rlast_i <= 1'b1; end read_cnt <= read_cnt - 1; end end end endcase end end end endgenerate endmodule `default_nettype wire
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // BCHDecoderControl for Cosmos OpenSSD // Copyright (c) 2015 Hanyang University ENC Lab. // Contributed by Jinwoo Jeong <[email protected]> // Kibin Park <[email protected]> // Yong Ho Song <[email protected]> // // This file is part of Cosmos OpenSSD. // // Cosmos OpenSSD is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 3, or (at your option) // any later version. // // Cosmos OpenSSD is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. // See the GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with Cosmos OpenSSD; see the file COPYING. // If not, see <http://www.gnu.org/licenses/>. ////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////// // Company: ENC Lab. <http://enc.hanyang.ac.kr> // Engineer: Jinwoo Jeong <[email protected]> // Kibin Park <[email protected]> // // Project Name: Cosmos OpenSSD // Design Name: BCH decoder controller // Module Name: BCHDecoderControl // File Name: BCHDecoderControl.v // // Version: v1.0.0 // // Description: BCH decoder controller // ////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////// // Revision History: // // * v1.0.0 // - first draft ////////////////////////////////////////////////////////////////////////////////// module BCHDecoderControl # ( parameter AddressWidth = 32 , parameter DataWidth = 32 , parameter InnerIFLengthWidth = 16 , parameter ThisID = 2 , parameter Multi = 2 , parameter GaloisFieldDegree = 12 , parameter MaxErrorCountBits = 9 , parameter Syndromes = 27 , parameter ELPCoefficients = 15 ) ( iClock , iReset , iSrcOpcode , iSrcTargetID , iSrcSourceID , iSrcAddress , iSrcLength , iSrcCmdValid , oSrcCmdReady , iSrcWriteData , iSrcWriteValid , iSrcWriteLast , oSrcWriteReady , oDstOpcode , oDstTargetID , oDstSourceID , oDstAddress , oDstLength , oDstCmdValid , iDstCmdReady , oDstWriteData , oDstWriteValid , oDstWriteLast , iDstWriteReady , iSharedKESReady , oErrorDetectionEnd , oDecodeNeeded , oSyndromes , iIntraSharedKESEnd , iErroredChunk , iCorrectionFail , iErrorCount , iELPCoefficients , oCSAvailable ); input iClock ; input iReset ; input [5:0] iSrcOpcode ; input [4:0] iSrcTargetID ; input [4:0] iSrcSourceID ; input [AddressWidth - 1:0] iSrcAddress ; input [InnerIFLengthWidth - 1:0] iSrcLength ; input iSrcCmdValid ; output oSrcCmdReady ; output [5:0] oDstOpcode ; output [4:0] oDstTargetID ; output [4:0] oDstSourceID ; output [AddressWidth - 1:0] oDstAddress ; output [InnerIFLengthWidth - 1:0] oDstLength ; output oDstCmdValid ; input iDstCmdReady ; input [DataWidth - 1:0] iSrcWriteData ; input iSrcWriteValid ; input iSrcWriteLast ; output oSrcWriteReady ; output [DataWidth - 1:0] oDstWriteData ; output oDstWriteValid ; output oDstWriteLast ; input iDstWriteReady ; input iSharedKESReady ; output [Multi - 1:0] oErrorDetectionEnd ; output [Multi - 1:0] oDecodeNeeded ; output [Multi*GaloisFieldDegree*Syndromes - 1:0] oSyndromes ; input iIntraSharedKESEnd ; input [Multi - 1:0] iErroredChunk ; input [Multi - 1:0] iCorrectionFail ; input [Multi*MaxErrorCountBits - 1:0] iErrorCount ; input [Multi*GaloisFieldDegree*ELPCoefficients - 1:0] iELPCoefficients ; output oCSAvailable ; wire [4:0] wQueuedCmdSourceID ; wire [4:0] wQueuedCmdTargetID ; wire [5:0] wQueuedCmdOpcode ; wire [1:0] wQueuedCmdType ; wire [AddressWidth - 1:0] wQueuedCmdAddress ; wire [InnerIFLengthWidth - 1:0] wQueuedCmdLength ; wire wQueuedCmdValid ; wire wQueuedCmdReady ; wire [4:0] wCmdSourceID ; wire [4:0] wCmdTargetID ; wire [5:0] wCmdOpcode ; wire [1:0] wCmdType ; wire [AddressWidth - 1:0] wCmdAddress ; wire [InnerIFLengthWidth - 1:0] wCmdLength ; wire wCmdValid ; wire wCmdReady ; wire [DataWidth - 1:0] wBufferedWriteData ; wire wBufferedWriteValid ; wire wBufferedWriteLast ; wire wBufferedWriteReady ; wire wDataQueuePushSignal; wire wDataQueuePopSignal ; wire wDataQueueFull ; wire wDataQueueEmpty ; wire [DataWidth - 1:0] wBypassWriteData ; wire wBypassWriteLast ; wire wBypassWriteValid ; wire wBypassWriteReady ; wire [DataWidth - 1:0] wDecWriteData ; wire wDecWriteValid ; wire wDecWriteReady ; wire wDecInDataLast ; wire wDecAvailable ; wire wDecodeFinished ; wire wDecodeSuccess ; wire [MaxErrorCountBits - 1:0] wErrorSum ; wire [4*Multi - 1:0] wErrorCountOut ; wire [DataWidth - 1:0] wCorrectedData ; wire wCorrectedDataLast ; wire wCorrectedDataValid ; wire wCorrectedDataReady ; wire wCSReset ; wire wCSAvailable ; wire wDecStandby ; assign oCSAvailable = wCSAvailable && wDecStandby; BCHDecoderCommandReception # ( .AddressWidth (AddressWidth ), .DataWidth (DataWidth ), .InnerIFLengthWidth (InnerIFLengthWidth ), .ThisID (ThisID ) ) Inst_BCHDecoderCommandReception ( .iClock (iClock ), .iReset (iReset ), .iSrcOpcode (iSrcOpcode ), .iSrcTargetID (iSrcTargetID ), .iSrcSourceID (iSrcSourceID ), .iSrcAddress (iSrcAddress ), .iSrcLength (iSrcLength ), .iSrcCmdValid (iSrcCmdValid ), .oSrcCmdReady (oSrcCmdReady ), .oQueuedCmdType (wQueuedCmdType ), .oQueuedCmdSourceID (wQueuedCmdSourceID ), .oQueuedCmdTargetID (wQueuedCmdTargetID ), .oQueuedCmdOpcode (wQueuedCmdOpcode ), .oQueuedCmdAddress (wQueuedCmdAddress ), .oQueuedCmdLength (wQueuedCmdLength ), .oQueuedCmdValid (wQueuedCmdValid ), .iQueuedCmdReady (wQueuedCmdReady ) ); BCHDecoderInputControl # ( .AddressWidth (AddressWidth ), .DataWidth (DataWidth ), .InnerIFLengthWidth (InnerIFLengthWidth ), .ThisID (ThisID ) ) Inst_BCHDecoderInControlCore ( .iClock (iClock ), .iReset (iReset ), .oDstOpcode (wCmdOpcode ), .oDstTargetID (wCmdTargetID ), .oDstSourceID (wCmdSourceID ), .oDstCmdType (wCmdType ), .oDstAddress (wCmdAddress ), .oDstLength (wCmdLength ), .oDstCmdValid (wCmdValid ), .iDstCmdReady (wCmdReady ), .iCmdSourceID (wQueuedCmdSourceID ), .iCmdTargetID (wQueuedCmdTargetID ), .iCmdOpcode (wQueuedCmdOpcode ), .iCmdType (wQueuedCmdType ), .iCmdAddress (wQueuedCmdAddress ), .iCmdLength (wQueuedCmdLength ), .iCmdValid (wQueuedCmdValid ), .oCmdReady (wQueuedCmdReady ), .iSrcWriteData (iSrcWriteData ), .iSrcWriteValid (iSrcWriteValid ), .iSrcWriteLast (iSrcWriteLast ), .oSrcWriteReady (oSrcWriteReady ), .oBypassWriteData (wBypassWriteData ), .oBypassWriteLast (wBypassWriteLast ), .oBypassWriteValid (wBypassWriteValid ), .iBypassWriteReady (wBypassWriteReady ), .oDecWriteData (wDecWriteData ), .oDecWriteValid (wDecWriteValid ), .iDecWriteReady (wDecWriteReady ), .iDecInDataLast (wDecInDataLast ), .iDecAvailable (wDecAvailable ) ); BCHDecoderX # ( .DataWidth (DataWidth ), .Multi (Multi ), .MaxErrorCountBits (MaxErrorCountBits ), .GaloisFieldDegree (GaloisFieldDegree ), .Syndromes (Syndromes ), .ELPCoefficients (ELPCoefficients ) ) Inst_BCHDecoderIO ( .iClock (iClock ), .iReset (iReset ), .iData (wDecWriteData ), .iDataValid (wDecWriteValid ), .oDataReady (wDecWriteReady ), .oDataLast (wDecInDataLast ), .oDecoderReady (wDecAvailable ), .oDecodeFinished (wDecodeFinished ), .oDecodeSuccess (wDecodeSuccess ), .oErrorSum (wErrorSum ), .oErrorCountOut (wErrorCountOut ), .oCorrectedData (wCorrectedData ), .oCorrectedDataValid (wCorrectedDataValid ), .oCorrectedDataLast (wCorrectedDataLast ), .iCorrectedDataReady (wCorrectedDataReady ), .iSharedKESReady (iSharedKESReady ), .oErrorDetectionEnd (oErrorDetectionEnd ), .oDecodeNeeded (oDecodeNeeded ), .oSyndromes (oSyndromes ), .iIntraSharedKESEnd (iIntraSharedKESEnd ), .iErroredChunk (iErroredChunk ), .iCorrectionFail (iCorrectionFail ), .iErrorCount (iErrorCount ), .iELPCoefficients (iELPCoefficients ), .oCSAvailable (wCSAvailable ), .iCSReset (wCSReset ) ); BCHDecoderOutputControl # ( .AddressWidth (AddressWidth ), .DataWidth (DataWidth ), .InnerIFLengthWidth (InnerIFLengthWidth ), .ThisID (ThisID ), .Multi (Multi ), .MaxErrorCountBits (MaxErrorCountBits ) ) Inst_BCHDecoderOutControlCore ( .iClock (iClock ), .iReset (iReset ), .oDstOpcode (oDstOpcode ), .oDstTargetID (oDstTargetID ), .oDstSourceID (oDstSourceID ), .oDstAddress (oDstAddress ), .oDstLength (oDstLength ), .oDstCmdValid (oDstCmdValid ), .iDstCmdReady (iDstCmdReady ), .iCmdSourceID (wCmdSourceID ), .iCmdTargetID (wCmdTargetID ), .iCmdOpcode (wCmdOpcode ), .iCmdType (wCmdType ), .iCmdAddress (wCmdAddress ), .iCmdLength (wCmdLength ), .iCmdValid (wCmdValid ), .oCmdReady (wCmdReady ), .iBypassWriteData (wBypassWriteData ), .iBypassWriteLast (wBypassWriteLast ), .iBypassWriteValid (wBypassWriteValid ), .oBypassWriteReady (wBypassWriteReady ), .iDecWriteData (wCorrectedData ), .iDecWriteValid (wCorrectedDataValid ), .iDecWriteLast (wCorrectedDataLast ), .oDecWriteReady (wCorrectedDataReady ), .oDstWriteData (wBufferedWriteData ), .oDstWriteValid (wBufferedWriteValid ), .oDstWriteLast (wBufferedWriteLast ), .iDstWriteReady (wBufferedWriteReady ), .iDecodeFinished (wDecodeFinished ), .iDecodeSuccess (wDecodeSuccess ), .iErrorSum (wErrorSum ), .iErrorCountOut (wErrorCountOut ), .oCSReset (wCSReset ), .oDecStandby (wDecStandby ) ); assign wDataQueuePushSignal = wBufferedWriteValid && !wDataQueueFull; assign wBufferedWriteReady = !wDataQueueFull; AutoFIFOPopControl Inst_DataQueueAutoPopControl ( .iClock (iClock ), .iReset (iReset ), .oPopSignal (wDataQueuePopSignal), .iEmpty (wDataQueueEmpty ), .oValid (oDstWriteValid ), .iReady (iDstWriteReady ) ); SCFIFO_64x64_withCount Inst_DataQueue ( .iClock (iClock ), .iReset (iReset ), .iPushData ({wBufferedWriteData, wBufferedWriteLast} ), .iPushEnable (wDataQueuePushSignal ), .oIsFull (wDataQueueFull ), .oPopData ({oDstWriteData, oDstWriteLast} ), .iPopEnable (wDataQueuePopSignal ), .oIsEmpty (wDataQueueEmpty ), .oDataCount ( ) ); endmodule
//----------------------------------------------------------------------------- // // (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //----------------------------------------------------------------------------- // Project : V5-Block Plus for PCI Express // File : cmm_errman_nfl.v //-------------------------------------------------------------------------------- //-------------------------------------------------------------------------------- /*********************************************************************** Description: This module figures out what to do for non-fatal errors: 1) count up or count down, 2) how much to add or to subtract. It returns the number and a add/subtract_b signals to the error tracking counter. The outputs are based on how many errors are asserted by the error reporting modules. ***********************************************************************/ module cmm_errman_nfl ( nfl_num, // Output inc_dec_b, cfg_err_cpl_timeout_n, decr_nfl, rst, clk ); output nfl_num; output inc_dec_b; // 1 = increment, 0 = decrement input cfg_err_cpl_timeout_n; input decr_nfl; input rst; input clk; //******************************************************************// // Reality check. // //******************************************************************// parameter FFD = 1; // clock to out delay model //******************************************************************// // Figure out how many errors to increment. // //******************************************************************// reg to_incr; reg add_sub_b; always @(cfg_err_cpl_timeout_n or decr_nfl) begin case ({cfg_err_cpl_timeout_n, decr_nfl}) // synthesis full_case parallel_case 2'b10: begin to_incr = 1'b0; add_sub_b = 1'b1; end 2'b11: begin to_incr = 1'b1; add_sub_b = 1'b0; end 2'b00: begin to_incr = 1'b1; add_sub_b = 1'b1; end 2'b01: begin to_incr = 1'b0; add_sub_b = 1'b1; end default: begin to_incr = 1'b0; add_sub_b = 1'b1; end endcase end //******************************************************************// // Register the outputs. // //******************************************************************// reg reg_nfl_num; reg reg_inc_dec_b; always @(posedge clk or posedge rst) begin if (rst) begin reg_nfl_num <= #FFD 1'b0; reg_inc_dec_b <= #FFD 1'b0; end else begin reg_nfl_num <= #FFD to_incr; reg_inc_dec_b <= #FFD add_sub_b; end end assign nfl_num = reg_nfl_num; assign inc_dec_b = reg_inc_dec_b; //******************************************************************// // // //******************************************************************// endmodule
////////////////////////////////////////////////////////////////////// //// //// //// fpu_addsub //// //// //// //// This file is part of the OpenRISC 1200 project //// //// http://opencores.org/project,or1k //// //// //// //// Description //// //// addition/subtraction entity for the addition/subtraction //// //// unit //// //// //// //// To Do: //// //// //// //// //// //// Author(s): //// //// - Original design (FPU100) - //// //// Jidan Al-eryani, [email protected] //// //// - Conv. to Verilog and inclusion in OR1200 - //// //// Julius Baxter, [email protected] //// //// //// ////////////////////////////////////////////////////////////////////// // // Copyright (C) 2006, 2010 // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED // TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS // FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR // OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE // GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT // OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // module fpu_addsub( clk, rst, fpu_op_i, fracta_i, fractb_i, signa_i, signb_i, fract_o, sign_o); parameter FP_WIDTH = 32; parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial parameter FRAC_WIDTH = 23; parameter EXP_WIDTH = 8; parameter ZERO_VECTOR = 31'd0; parameter INF = 31'b1111111100000000000000000000000; parameter QNAN = 31'b1111111110000000000000000000000; parameter SNAN = 31'b1111111100000000000000000000001; input clk; input rst; input fpu_op_i; input [FRAC_WIDTH+4:0] fracta_i; input [FRAC_WIDTH+4:0] fractb_i; input signa_i; input signb_i; output reg [FRAC_WIDTH+4:0] fract_o; output reg sign_o; wire [FRAC_WIDTH+4:0] s_fracta_i; wire [FRAC_WIDTH+4:0] s_fractb_i; wire [FRAC_WIDTH+4:0] s_fract_o; wire s_signa_i, s_signb_i, s_sign_o; wire s_fpu_op_i; wire fracta_gt_fractb; wire s_addop; assign s_fracta_i = fracta_i; assign s_fractb_i = fractb_i; assign s_signa_i = signa_i; assign s_signb_i = signb_i; assign s_fpu_op_i = fpu_op_i; always @(posedge clk or posedge rst) if (rst) begin fract_o <= 'd0; sign_o <= 1'b0; end else begin fract_o <= s_fract_o; sign_o <= s_sign_o; end assign fracta_gt_fractb = s_fracta_i > s_fractb_i; // check if its a subtraction or an addition operation assign s_addop = ((s_signa_i ^ s_signb_i) & !s_fpu_op_i) | ((s_signa_i ^~ s_signb_i) & s_fpu_op_i); // sign of result assign s_sign_o = ((s_fract_o == 28'd0) & !(s_signa_i & s_signb_i)) ? 1'b0 : (!s_signa_i & (!fracta_gt_fractb & (fpu_op_i^s_signb_i)))| (s_signa_i & (fracta_gt_fractb | (fpu_op_i^s_signb_i))); // add/substract assign s_fract_o = s_addop ? (fracta_gt_fractb ? s_fracta_i - s_fractb_i : s_fractb_i - s_fracta_i) : s_fracta_i + s_fractb_i; endmodule // fpu_addsub
// test_simulation_mod_1_xx.v module f1_test(in1, in2, out); input in1; input in2; output out; wire synth_net_0; wire synth_net_1; BUF synth_BUF_0(.in(synth_net_1), .out(out )); DIV1 synth_DIV(.in1(in1), .in2(in2), .rem(synth_net_0), .out(synth_net_1 )); endmodule // test_simulation_always_31_tt.v module f2_test(clk, cond, data); input cond; input clk; output data; wire synth_net; wire synth_net_0; wire synth_net_1; wire synth_net_2; wire synth_net_3; wire synth_net_4; wire synth_net_5; wire synth_net_6; wire synth_net_7; wire synth_net_8; wire synth_net_9; wire synth_net_10; wire synth_net_11; wire tmp; AND2 synth_AND(.in({synth_net_0, synth_net_1}), . out(synth_net_2)); AND2 synth_AND_0(.in({synth_net_3, synth_net_4}), .out( synth_net_5)); AND2 synth_AND_1(.in({synth_net_6, synth_net_7}), .out( synth_net_8)); AND2 synth_AND_2(.in({synth_net_9, synth_net_10}), .out( synth_net_11)); BUF synth_BUF(.in(synth_net), .out(synth_net_0)); BUF synth_BUF_0(.in(data), .out(synth_net_3)); BUF synth_BUF_1(.in(synth_net_8) , .out(tmp)); BUF synth_BUF_2(.in(tmp), .out(synth_net_9)); MUX2 synth_MUX(. in({synth_net_2, synth_net_5}), .select(cond), .out(synth_net_6)); MUX2 synth_MUX_0(.in({synth_net_1, synth_net_4}), .select(cond), .out(synth_net_7 )); FF synth_FF(.d(synth_net_11), .clk(clk), .q(data)); VCC synth_VCC(.out( synth_net)); VCC synth_VCC_0(.out(synth_net_1)); VCC synth_VCC_1(.out( synth_net_4)); VCC synth_VCC_2(.out(synth_net_10)); endmodule
// ---------------------------------------------------------------------- // Copyright (c) 2016, The Regents of the University of California All // rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following // disclaimer in the documentation and/or other materials provided // with the distribution. // // * Neither the name of The Regents of the University of California // nor the names of its contributors may be used to endorse or // promote products derived from this software without specific // prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE // UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, // BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS // OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND // ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR // TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE // USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH // DAMAGE. // ---------------------------------------------------------------------- //---------------------------------------------------------------------------- // Filename: counter.v // Version: 1.00.a // Verilog Standard: Verilog-2001 // Description: A simple up-counter. The maximum value is the largest expected // value. The counter will not pass the SAT_VALUE. If the SAT_VALUE > MAX_VALUE, // the counter will roll over and never stop. On RST_IN, the counter // synchronously resets to the RST_VALUE // Author: Dustin Richmond (@darichmond) //----------------------------------------------------------------------------- `timescale 1ns/1ns `include "functions.vh" module counter #(parameter C_MAX_VALUE = 10, parameter C_SAT_VALUE = 10, parameter C_RST_VALUE = 0) ( input CLK, input RST_IN, input ENABLE, output [clog2s(C_MAX_VALUE+1)-1:0] VALUE ); wire wEnable; reg [clog2s(C_MAX_VALUE+1)-1:0] wCtrValue; reg [clog2s(C_MAX_VALUE+1)-1:0] rCtrValue; /* verilator lint_off WIDTH */ assign wEnable = ENABLE & (C_SAT_VALUE > rCtrValue); /* verilator lint_on WIDTH */ assign VALUE = rCtrValue; always @(posedge CLK) begin if(RST_IN) begin rCtrValue <= C_RST_VALUE[clog2s(C_MAX_VALUE+1)-1:0]; end else if(wEnable) begin rCtrValue <= rCtrValue + 1; end end endmodule
// Copyright (c) 2013, Simon Que // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // // Redistributions of source code must retain the above copyright notice, this // list of conditions and the following disclaimer. // Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution. // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // A dual-port multiplexed SPI bus interface. module SPIBus( // Primary SPI bus. input main_nss, input main_sck, input main_mosi, output main_miso, // Secondary SPI bus. input alt_nss, input alt_sck, input alt_mosi, output alt_miso, // Output SPI bus. output reg nss, output reg sck, output reg mosi, input miso ); // Each bus is granted access when its select is asserted and the other bus' // select is not asserted. wire alt_bus_enabled = (alt_nss == 'b0) & (main_nss == 'b1); wire main_bus_enabled = (alt_nss == 'b1) & (main_nss == 'b0); // Multiplex the two SPI buses. // nSS should be allowed to assert only if only one bus is asserting it. // This avoids undefined behavior when the main bus interrupts the secondary // bus. always @ (*) begin if (alt_bus_enabled) begin nss <= 'b0; sck <= alt_sck; mosi <= alt_mosi; end else if (main_bus_enabled) begin nss <= 'b0; sck <= main_sck; mosi <= main_mosi; end else begin nss <= 'b1; sck <= 0; mosi <= 0; end end assign main_miso = (main_nss == 'b0) ? miso : 'bz; assign alt_miso = (alt_nss == 'b0) ? miso : 'bz; endmodule
// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Wilson Snyder. module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [15:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[15:0]), // Inputs .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {48'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h4afe43fb79d7b71e if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module callee (input [7:0] port [7:0], output [7:0] o); assign o = ^{port[0], port[1], port[2], port[3], port[4], port[5], port[6], port[7]}; endmodule // callee module Test (/*AUTOARG*/ // Outputs out, // Inputs in ); input [31:0] in; output reg [15:0] out; wire [7:0] port [15:0]; wire [7:0] goodport [7:0]; always_comb begin port[0][7:0] = in[7:0]; port[1][7:0] = in[16:8]; port[2] = '0; port[3] = '0; port[4] = '0; port[5] = '0; port[6] = '0; port[7] = '0; end always_comb begin goodport[0][7:0] = in[7:0]; goodport[1][7:0] = in[16:8]; goodport[2] = '0; goodport[3] = '0; goodport[4] = '0; goodport[5] = '0; goodport[6] = '0; goodport[7] = '0; end callee good (.port(goodport), .o(out[7:0])); // This is a slice, unsupported by other tools, bug711 callee bad (.port(port[7:0]), .o(out[15:8])); endmodule
/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_LP__DFRBP_FUNCTIONAL_V `define SKY130_FD_SC_LP__DFRBP_FUNCTIONAL_V /** * dfrbp: Delay flop, inverted reset, complementary outputs. * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none // Import user defined primitives. `include "../../models/udp_dff_pr/sky130_fd_sc_lp__udp_dff_pr.v" `celldefine module sky130_fd_sc_lp__dfrbp ( Q , Q_N , CLK , D , RESET_B ); // Module ports output Q ; output Q_N ; input CLK ; input D ; input RESET_B; // Local signals wire buf_Q; wire RESET; // Delay Name Output Other arguments not not0 (RESET , RESET_B ); sky130_fd_sc_lp__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET ); buf buf0 (Q , buf_Q ); not not1 (Q_N , buf_Q ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_LP__DFRBP_FUNCTIONAL_V
/* * This demonstrates a basic dynamic array */ module main; int foo[]; int idx; initial begin if (foo.size() != 0) begin $display("FAILED -- foo.size()=%0d, s.b. 0", foo.size()); $finish; end foo = new[10]; if (foo.size() != 10) begin $display("FAILED -- foo.size()=%0d, s.b. 10", foo.size()); $finish; end for (idx = 0 ; idx < foo.size() ; idx += 1) begin foo[idx] = idx; end $display("foo[7] = %d", foo[7]); if (foo[7] != 7) begin $display("FAILED -- foo[7] = %0d (s.b. 7)", foo[7]); $finish; end $display("foo[9] = %d", foo[9]); if (foo[9] != 9) begin $display("FAILED -- foo[9] = %0d (s.b. 9)", foo[9]); $finish; end for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin if (foo[idx%10] != (idx%10)) begin $display("FAILED -- foo[%0d%%10] = %0d", foo[idx%10]); $finish; end end foo.delete(); if (foo.size() != 0) begin $display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size()); $finish; end $display("PASSED"); end endmodule // main
/******************************************************************************* * (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. * * * * This file contains confidential and proprietary information * * of Xilinx, Inc. and is protected under U.S. and * * international copyright and other intellectual property * * laws. * * * * DISCLAIMER * * This disclaimer is not a license and does not grant any * * rights to the materials distributed herewith. Except as * * otherwise provided in a valid license issued to you by * * Xilinx, and to the maximum extent permitted by applicable * * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND * * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES * * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING * * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- * * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and * * (2) Xilinx shall not be liable (whether in contract or tort, * * including negligence, or under any other theory of * * liability) for any loss or damage of any kind or nature * * related to, arising under or in connection with these * * materials, including for any direct, or any indirect, * * special, incidental, or consequential loss or damage * * (including loss of data, profits, goodwill, or any type of * * loss or damage suffered as a result of any action brought * * by a third party) even if such damage or loss was * * reasonably foreseeable or Xilinx had been advised of the * * possibility of the same. * * * * CRITICAL APPLICATIONS * * Xilinx products are not designed or intended to be fail- * * safe, or for use in any application requiring fail-safe * * performance, such as life-support or safety devices or * * systems, Class III medical devices, nuclear facilities, * * applications related to the deployment of airbags, or any * * other applications that could lead to death, personal * * injury, or severe property or environmental damage * * (individually and collectively, "Critical * * Applications"). Customer assumes the sole risk and * * liability of any use of Xilinx products in Critical * * Applications, subject only to applicable laws and * * regulations governing limitations on product liability. * * * * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS * * PART OF THIS FILE AT ALL TIMES. * *******************************************************************************/ // The synthesis directives "translate_off/translate_on" specified below are // supported by Xilinx, Mentor Graphics and Synplicity synthesis // tools. Ensure they are correct for your synthesis tool(s). // You must compile the wrapper file lut_xilinx.v when simulating // the core, lut_xilinx. When compiling the wrapper file, be sure to // reference the XilinxCoreLib Verilog simulation library. For detailed // instructions, please refer to the "CORE Generator Help". ZUMA_LUT_SIZE `timescale 1ns/1ps module lut_xilinx( a, d, dpra, clk, we, dpo); input [ZUMA_LUT_SIZE-1 : 0] a; input [0 : 0] d; input [ZUMA_LUT_SIZE-1 : 0] dpra; input clk; input we; output [0 : 0] dpo; // synthesis translate_off DIST_MEM_GEN_V6_1 #( .C_ADDR_WIDTH(6), .C_DEFAULT_DATA("0"), .C_DEPTH(64), .C_FAMILY("virtex5"), .C_HAS_CLK(1), .C_HAS_D(1), .C_HAS_DPO(1), .C_HAS_DPRA(1), .C_HAS_I_CE(0), .C_HAS_QDPO(0), .C_HAS_QDPO_CE(0), .C_HAS_QDPO_CLK(0), .C_HAS_QDPO_RST(0), .C_HAS_QDPO_SRST(0), .C_HAS_QSPO(0), .C_HAS_QSPO_CE(0), .C_HAS_QSPO_RST(0), .C_HAS_QSPO_SRST(0), .C_HAS_SPO(0), .C_HAS_SPRA(0), .C_HAS_WE(1), .C_MEM_INIT_FILE("no_coe_file_loaded"), .C_MEM_TYPE(4), .C_PARSER_TYPE(1), .C_PIPELINE_STAGES(0), .C_QCE_JOINED(0), .C_QUALIFY_WE(0), .C_READ_MIF(0), .C_REG_A_D_INPUTS(0), .C_REG_DPRA_INPUT(0), .C_SYNC_ENABLE(1), .C_WIDTH(1)) inst ( .A(a), .D(d), .DPRA(dpra), .CLK(clk), .WE(we), .DPO(dpo), .SPRA(), .I_CE(), .QSPO_CE(), .QDPO_CE(), .QDPO_CLK(), .QSPO_RST(), .QDPO_RST(), .QSPO_SRST(), .QDPO_SRST(), .SPO(), .QSPO(), .QDPO()); // synthesis translate_on endmodule
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: SILAB , Physics Institute of Bonn University // Engineer: Viacheslav Filimonov // // Create Date: 10:40:28 12/16/2013 // Design Name: // Module Name: KX7_IF_Test_Top // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module mmc3_top( // FX 3 interface input wire fx3_pclk_100MHz, (* IOB = "FORCE" *) input wire fx3_wr, // force IOB register (* IOB = "FORCE" *) input wire fx3_cs, // async. signal (* IOB = "FORCE" *) input wire fx3_oe, // async. signal input wire fx3_rst, // async. signal from FX3, active high (* IOB = "FORCE" *) output wire fx3_ack, // force IOB register (* IOB = "FORCE" *) output wire fx3_rdy, // force IOB register // output wire reset_fx3, inout wire [31:0] fx3_bus, // 32 bit databus // 200 MHz oscillator input wire sys_clk_p, input wire sys_clk_n, // 100 Mhz oscillator input wire Clk100, // GPIO output wire [8:1] led, output wire [3:0] PWR_EN, (* IOB = "FORCE" *) output wire fx3_rd_finish, input wire Reset_button,// async. signal input wire FLAG1, // was DMA Flag; currently connected to TEST signal from FX3 (* IOB = "FORCE" *) input wire FLAG2, // DMA watermark flag for thread 2 of FX3 // Power supply regulators EN signals output wire EN_VD1, output wire EN_VD2, output wire EN_VA1, output wire EN_VA2, // Command sequencer signals output wire CMD_CLK_OUT, (* IOB = "FORCE" *) output wire CMD_DATA, // FE-I4_rx signals (* IOB = "FORCE" *) input wire DOBOUT ); //assign reset_fx3 = 1; // not to reset fx3 while loading fpga assign EN_VD1 = 1; assign EN_VD2 = 1; assign EN_VA1 = 1; assign EN_VA2 = 1; wire [31:0] BUS_ADD; wire [31:0] BUS_DATA; wire BUS_RD, BUS_WR, BUS_RST, BUS_CLK; //assign BUS_RST = (BUS_RST | (!LOCKED)); wire BUS_BYTE_ACCESS; assign BUS_BYTE_ACCESS = (BUS_ADD < 32'h8000_0000) ? 1'b1 : 1'b0; wire RST; assign RST = ((fx3_rst)|(!LOCKED)|(!Reset_button)); // Button is acticve low FX3_IF FX3_IF_inst ( .fx3_bus(fx3_bus), .fx3_wr(fx3_wr), .fx3_oe(fx3_oe), .fx3_cs(fx3_cs), .fx3_clk(fx3_pclk_100MHz), .fx3_rdy(fx3_rdy), .fx3_ack(fx3_ack), .fx3_rd_finish(fx3_rd_finish), .fx3_rst(RST), // PLL is reset first .BUS_CLK(BUS_CLK), .BUS_RST(BUS_RST), .BUS_ADD(BUS_ADD), .BUS_DATA(BUS_DATA), .BUS_RD(BUS_RD), .BUS_WR(BUS_WR), .BUS_BYTE_ACCESS(BUS_BYTE_ACCESS), .FLAG1(FLAG1), .FLAG2(FLAG2) ); wire clk40mhz_pll, clk320mhz_pll, clk160mhz_pll, clk16mhz_pll; wire pll_feedback, LOCKED; PLLE2_BASE #( .BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW .CLKFBOUT_MULT(64), // Multiply value for all CLKOUT, (2-64) .CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000). .CLKIN1_PERIOD(10.000), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). .CLKOUT0_DIVIDE(32), // Divide amount for CLKOUT0 (1-128) .CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999). .CLKOUT0_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000). .CLKOUT1_DIVIDE(4), // Divide amount for CLKOUT0 (1-128) .CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999). .CLKOUT1_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000). .CLKOUT2_DIVIDE(8), // Divide amount for CLKOUT0 (1-128) .CLKOUT2_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999). .CLKOUT2_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000). .CLKOUT3_DIVIDE(80), // Divide amount for CLKOUT0 (1-128) .CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999). .CLKOUT3_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000). .DIVCLK_DIVIDE(5), // Master division value, (1-56) .REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999). .STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE") ) PLLE2_BASE_inst ( // Generated 40 MHz clock .CLKOUT0(clk40mhz_pll), .CLKOUT1(clk320mhz_pll), .CLKOUT2(clk160mhz_pll), .CLKOUT3(clk16mhz_pll), .CLKOUT4(), .CLKOUT5(), .CLKFBOUT(pll_feedback), .LOCKED(LOCKED), // 1-bit output: LOCK // Input 100 MHz clock .CLKIN1(BUS_CLK), // Control Ports .PWRDWN(0), .RST(fx3_rst), // Reset from FX3 // Feedback .CLKFBIN(pll_feedback) ); wire clk40mhz, clk320mhz, clk160mhz, clk16mhz; BUFG BUFG_inst_40 ( .O(clk40mhz), // Clock buffer output .I(clk40mhz_pll) // Clock buffer input ); BUFG BUFG_inst_320 ( .O(clk320mhz), // Clock buffer output .I(clk320mhz_pll) // Clock buffer input ); BUFG BUFG_inst_160 ( .O(clk160mhz), // Clock buffer output .I(clk160mhz_pll) // Clock buffer input ); BUFG BUFG_inst_16 ( .O(clk16mhz), // Clock buffer output .I(clk16mhz_pll) // Clock buffer input ); // ------- MODULE ADDRESSES ------- // localparam CMD_BASEADDR = 32'h0000; localparam CMD_HIGHADDR = 32'h1000-1; localparam GPIO1_BASEADDR = 32'h1000; localparam GPIO1_HIGHADDR = 32'h1003; localparam GPIO2_BASEADDR = 32'h1004; localparam GPIO2_HIGHADDR = 32'h1007; localparam FIFO_BASEADDR = 32'h8100; localparam FIFO_HIGHADDR = 32'h8200-1; localparam RX4_BASEADDR = 32'h8300; localparam RX4_HIGHADDR = 32'h8400-1; localparam RX3_BASEADDR = 32'h8400; localparam RX3_HIGHADDR = 32'h8500-1; localparam RX2_BASEADDR = 32'h8500; localparam RX2_HIGHADDR = 32'h8600-1; localparam RX1_BASEADDR = 32'h8600; localparam RX1_HIGHADDR = 32'h8700-1; localparam FIFO_BASEADDR_DATA = 32'h8000_0000; localparam FIFO_HIGHADDR_DATA = 32'h9000_0000; localparam ABUSWIDTH = 32; wire CMD_EXT_START_FLAG; assign CMD_EXT_START_FLAG = 0; gpio #( .BASEADDR(GPIO1_BASEADDR), .HIGHADDR(GPIO1_HIGHADDR), .ABUSWIDTH(ABUSWIDTH), .IO_WIDTH(8), .IO_DIRECTION(8'hff), .IO_TRI(0) )gpio1( .BUS_CLK(BUS_CLK), .BUS_RST(BUS_RST), .BUS_ADD(BUS_ADD), .BUS_DATA(BUS_DATA[7:0]), .BUS_RD(BUS_RD), .BUS_WR(BUS_WR), .IO(led) ); gpio #( .BASEADDR(GPIO2_BASEADDR), .HIGHADDR(GPIO2_HIGHADDR), .ABUSWIDTH(ABUSWIDTH), .IO_WIDTH(8), .IO_DIRECTION(8'hff), .IO_TRI(0) )gpio2( .BUS_CLK(BUS_CLK), .BUS_RST(BUS_RST), .BUS_ADD(BUS_ADD), .BUS_DATA(BUS_DATA[7:0]), .BUS_RD(BUS_RD), .BUS_WR(BUS_WR), .IO(PWR_EN[3:0]) ); cmd_seq #( .BASEADDR(CMD_BASEADDR), .HIGHADDR(CMD_HIGHADDR), .ABUSWIDTH(ABUSWIDTH) ) icmd ( .BUS_CLK(BUS_CLK), .BUS_RST(BUS_RST), .BUS_ADD(BUS_ADD), .BUS_DATA(BUS_DATA[7:0]), .BUS_RD(BUS_RD), .BUS_WR(BUS_WR), .CMD_CLK_OUT(CMD_CLK_OUT), .CMD_CLK_IN(clk40mhz), .CMD_EXT_START_FLAG(CMD_EXT_START_FLAG), .CMD_EXT_START_ENABLE(), .CMD_DATA(CMD_DATA), .CMD_READY(), .CMD_START_FLAG() ); parameter DSIZE = 10; wire FIFO_READ, FIFO_EMPTY; wire [31:0] FIFO_DATA; //assign FIFO_READ = 0; genvar i; generate for (i = 3; i < 4; i = i + 1) begin: rx_gen fei4_rx #( .BASEADDR(RX1_BASEADDR-32'h0100*i), .HIGHADDR(RX1_HIGHADDR-32'h0100*i), .DSIZE(DSIZE), .DATA_IDENTIFIER(i+1), .ABUSWIDTH(ABUSWIDTH) ) i_fei4_rx ( .RX_CLK(clk160mhz), .RX_CLK2X(clk320mhz), .DATA_CLK(clk16mhz), .RX_DATA(DOBOUT), .RX_READY(), .RX_8B10B_DECODER_ERR(), .RX_FIFO_OVERFLOW_ERR(), .FIFO_CLK(1'b0), .FIFO_READ(FIFO_READ), .FIFO_EMPTY(FIFO_EMPTY), .FIFO_DATA(FIFO_DATA), .RX_FIFO_FULL(), .BUS_CLK(BUS_CLK), .BUS_RST(BUS_RST), .BUS_ADD(BUS_ADD), .BUS_DATA(BUS_DATA[7:0]), .BUS_RD(BUS_RD), .BUS_WR(BUS_WR) ); end endgenerate wire FIFO_NOT_EMPTY, FIFO_FULL, FIFO_NEAR_FULL, FIFO_READ_ERROR; bram_fifo #( .BASEADDR(FIFO_BASEADDR), .HIGHADDR(FIFO_HIGHADDR), .BASEADDR_DATA(FIFO_BASEADDR_DATA), .HIGHADDR_DATA(FIFO_HIGHADDR_DATA), .ABUSWIDTH(ABUSWIDTH) ) i_out_fifo ( .BUS_CLK(BUS_CLK), .BUS_RST(BUS_RST), .BUS_ADD(BUS_ADD), .BUS_DATA(BUS_DATA), .BUS_RD(BUS_RD), .BUS_WR(BUS_WR), .FIFO_READ_NEXT_OUT(FIFO_READ), .FIFO_EMPTY_IN(FIFO_EMPTY), .FIFO_DATA(FIFO_DATA), .FIFO_NOT_EMPTY(FIFO_NOT_EMPTY), .FIFO_FULL(FIFO_FULL), .FIFO_NEAR_FULL(FIFO_NEAR_FULL), .FIFO_READ_ERROR(FIFO_READ_ERROR) ); //assign led[5] = FIFO_NOT_EMPTY; //assign led[6] = FIFO_FULL; //assign led[7] = FIFO_NEAR_FULL; //assign led[8] = FIFO_READ_ERROR; /* always @ (posedge BUS_CLK) begin if (BUS_RST) begin led[5] <= 0; led[6] <= 0; led[7] <= 0; led[8] <= 0; end else begin if (FIFO_NOT_EMPTY) led[5] <= 1; else if (FIFO_FULL) led[6] <= 1; else if (FIFO_NEAR_FULL) led[7] <= 1; else if (FIFO_READ_ERROR) led[8] <= 1; end end */ /* gpio #( .BASEADDR(GPIO_BASEADDR), .HIGHADDR(GPIO_HIGHADDR), .ABUSWIDTH(32), .IO_WIDTH(8), .IO_DIRECTION(8'hff) ) i_gpio ( .BUS_CLK(BUS_CLK), .BUS_RST(BUS_RST), .BUS_ADD(BUS_ADD), .BUS_DATA(BUS_DATA), .BUS_RD(BUS_RD), .BUS_WR(BUS_WR), .IO(led[8:1]) ); */ /* Register #( .REG_SIZE(32), .ADDRESS(1)) Reg1_inst ( .D(DataIn), .WR(WR), .RD(RD), .Addr(Addr), .CLK(CLK_100MHz), .Q(Reg1), .RB(DataOut), .RDYB(RDYB), .RD_VALID_N(ACKB), .RST(RST) ); Register #( .REG_SIZE(32), .ADDRESS(2)) Reg2_inst ( .D(DataIn), .WR(WR), .RD(RD), .Addr(Addr), .CLK(CLK_100MHz), .Q(Reg2), .RB(DataOut), .RDYB(RDYB), .RD_VALID_N(ACKB), .RST(RST) ); BRAM_Test #( .ADDRESS( 32'h10_00_00_00), .MEM_SIZE(32'h00_00_40_00)) BRAM_Test_inst ( .DataIn(DataIn), .WR(WR), .RD(RD), .CLK(CLK_100MHz), .DataOut(DataOut), .Addr(Addr[31:0]), .RDYB(RDYB), .RD_VALID_N(ACKB), // .DMA_RDY(DMA_RDY), .RST(RST) ); DDR3_256_8 #( .ADDRESS( 32'h20_00_00_00), .MEM_SIZE(32'h10_00_00_00)) DDR3_256_8_inst ( .DataIn(DataIn[31:0]), .WR(WR), .RD(RD), .Addr(Addr[31:0]), .DataOut(DataOut[31:0]), .RDY_N(RDYB), .RD_VALID_N(ACKB), .CLK_OUT(CLK_100MHz), .RST(RST), .Reset_button2(Reset_button2), .INIT_COMPLETE(INIT_COMPLETE), .ddr3_dq(ddr3_dq), .ddr3_addr(ddr3_addr), // .ddr3_dm(ddr3_dm), .ddr3_dqs_p(ddr3_dqs_p), .ddr3_dqs_n(ddr3_dqs_n), .ddr3_ba(ddr3_ba), .ddr3_ck_p(ddr3_ck_p), .ddr3_ck_n(ddr3_ck_n), .ddr3_ras_n(ddr3_ras_n), .ddr3_cas_n(ddr3_cas_n), .ddr3_we_n(ddr3_we_n), .ddr3_reset_n(ddr3_reset_n), .ddr3_cke(ddr3_cke), .ddr3_odt(ddr3_odt), // .ddr3_cs_n(ddr3_cs_n), .sys_clk_p(sys_clk_p), .sys_clk_n(sys_clk_n), .Clk100(Clk100), .full_fifo(full_fifo), // .DMA_RDY(DMA_RDY), .CS_FX3(CS_FX3), .FLAG2_reg(FLAG2_reg) ); */ endmodule
// (C) 1992-2014 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // // Top level module for pipelined memory access. // // Properties - Coalesced: No, Ordered: N/A, Hazard-Safe: Yes, Pipelined: Yes // (see lsu_top.v for details) // // Description: Requests are submitted as soon as they are received. // Pipelined access to memory so multiple requests can be // in flight at a time. // Pipelined atomic unit: // Accept read requests on the upstream interface. When a request is // received, store the requested byte address in the request fifo and // pass the request through to the avalon interface. Response data // is buffered in the response fifo and the appropriate word is muxed // out of the response fifo based on the address in the request fifo. // The response fifo has limited capacity, so a counter is used to track // the number of pending responses to generate an upstream stall if // we run out of room. module lsu_atomic_pipelined ( clk, reset, o_stall, i_valid, i_address, i_burstcount, i_stall, o_valid, o_readdata, o_active, //Debugging signal avm_address, avm_read, avm_readdata, avm_waitrequest, avm_byteenable, avm_readdatavalid, o_input_fifo_depth, avm_burstcount, // specific for write data path i_atomic_op, i_writedata, i_cmpdata, avm_writeack, avm_writedata ); /************* * Parameters * *************/ parameter AWIDTH=32; // Address width (32-bits for Avalon) parameter WIDTH_BYTES=4; // Width of the memory access (bytes) parameter MWIDTH_BYTES=32; // Width of the global memory bus (bytes) parameter WRITEDATAWIDTH_BYTES=32; // Width of the readdata/writedata signals, // may be larger than MWIDTH_BYTES parameter ALIGNMENT_ABITS=2; // Request address alignment (address bits) parameter KERNEL_SIDE_MEM_LATENCY=32; // The max number of live threads parameter USEBURST=0; parameter BURSTCOUNT_WIDTH=6; // Size of Avalon burst count port parameter USEINPUTFIFO=1; parameter USEOUTPUTFIFO=1; parameter INPUTFIFOSIZE=32; parameter PIPELINE_INPUT=0; parameter SUPERPIPELINE=0; // Enable extremely aggressive pipelining of the LSU parameter ATOMIC_WIDTH=6; // atomic operation range localparam INPUTFIFO_USEDW_MAXBITS=$clog2(INPUTFIFOSIZE); // Derived parameters localparam MAX_BURST=2**(BURSTCOUNT_WIDTH-1); localparam WIDTH=8*WIDTH_BYTES; localparam MWIDTH=8*MWIDTH_BYTES; localparam WRITEDATAWIDTH=8*WRITEDATAWIDTH_BYTES; localparam BYTE_SELECT_BITS=$clog2(MWIDTH_BYTES); localparam SEGMENT_SELECT_BITS=BYTE_SELECT_BITS-ALIGNMENT_ABITS; localparam SEGMENT_WIDTH_BYTES=(2**ALIGNMENT_ABITS); localparam UNUSED_WRITEDATA_WIDTH = WRITEDATAWIDTH - (2 * WIDTH + ATOMIC_WIDTH + BYTE_SELECT_BITS + 1); // // We only o_stall if we have more than KERNEL_SIDE_MEM_LATENCY inflight requests // localparam RETURN_FIFO_SIZE=KERNEL_SIDE_MEM_LATENCY+(USEBURST ? 0 : 1); localparam COUNTER_WIDTH=USEBURST ? $clog2(RETURN_FIFO_SIZE+1+MAX_BURST) : $clog2(RETURN_FIFO_SIZE+1); /******** * Ports * ********/ // Standard global signals input clk; input reset; // Upstream interface output o_stall; input i_valid; input [AWIDTH-1:0] i_address; input [BURSTCOUNT_WIDTH-1:0] i_burstcount; // Downstream interface input i_stall; output o_valid; output [WIDTH-1:0] o_readdata; output reg o_active; // Atomic signals input [ATOMIC_WIDTH-1:0] i_atomic_op; // Avalon read interface output [AWIDTH-1:0] avm_address; output avm_read; input [WRITEDATAWIDTH-1:0] avm_readdata; input avm_waitrequest; output logic [WRITEDATAWIDTH_BYTES-1:0] avm_byteenable; input avm_readdatavalid; // Avalon write interface input [WIDTH-1:0] i_writedata; input [WIDTH-1:0] i_cmpdata; input avm_writeack; output [WRITEDATAWIDTH-1:0] avm_writedata; output [BURSTCOUNT_WIDTH-1:0] avm_burstcount; // For profiler/performance monitor output [INPUTFIFO_USEDW_MAXBITS-1:0] o_input_fifo_depth; /*************** * Architecture * ***************/ wire i_valid_from_fifo; wire [AWIDTH-1:0] i_address_from_fifo; wire o_stall_to_fifo; wire [BURSTCOUNT_WIDTH-1:0] i_burstcount_from_fifo; wire [WIDTH-1:0] i_writedata_from_fifo; wire [WIDTH-1:0] i_cmpdata_from_fifo; wire [ATOMIC_WIDTH-1:0] i_atomic_op_from_fifo; wire [BYTE_SELECT_BITS-1:0] segment_address; wire read_accepted; wire read_used; wire [BYTE_SELECT_BITS-1:0] byte_select; wire ready; wire out_fifo_wait; localparam FIFO_DEPTH_BITS=USEINPUTFIFO ? $clog2(INPUTFIFOSIZE) : 0; wire [FIFO_DEPTH_BITS-1:0] usedw_true_width; generate if (USEINPUTFIFO) assign o_input_fifo_depth[FIFO_DEPTH_BITS-1:0] = usedw_true_width; // Set unused bits to 0 genvar bit_index; for(bit_index = FIFO_DEPTH_BITS; bit_index < INPUTFIFO_USEDW_MAXBITS; bit_index = bit_index + 1) begin: read_fifo_depth_zero_assign assign o_input_fifo_depth[bit_index] = 1'b0; end endgenerate generate if(USEINPUTFIFO && SUPERPIPELINE) begin wire int_stall; wire int_valid; wire [WIDTH+AWIDTH+BURSTCOUNT_WIDTH-1:0] int_data; acl_fifo #( .DATA_WIDTH(ATOMIC_WIDTH+2*WIDTH+AWIDTH+BURSTCOUNT_WIDTH), .DEPTH(INPUTFIFOSIZE) ) input_fifo ( .clock(clk), .resetn(!reset), .data_in( {i_atomic_op,i_cmpdata,i_writedata,i_address,i_burstcount} ), .data_out( int_data ), .valid_in( i_valid ), .valid_out( int_valid ), .stall_in( int_stall ), .stall_out( o_stall ), .usedw( usedw_true_width ) ); // Add a pipeline and stall-breaking FIFO // TODO: Consider making this parameterizeable acl_data_fifo #( .DATA_WIDTH(ATOMIC_WIDTH+2*WIDTH+AWIDTH+BURSTCOUNT_WIDTH), .DEPTH(2), .IMPL("ll_reg") ) input_fifo_buffer ( .clock(clk), .resetn(!reset), .data_in( int_data ), .valid_in( int_valid ), .data_out( {i_atomic_op_from_fifo,i_cmpdata_from_fifo,i_writedata_from_fifo,i_address_from_fifo,i_burstcount_from_fifo} ), .valid_out( i_valid_from_fifo ), .stall_in( o_stall_to_fifo ), .stall_out( int_stall ) ); end else if(USEINPUTFIFO && !SUPERPIPELINE) begin acl_fifo #( .DATA_WIDTH(ATOMIC_WIDTH+2*AWIDTH+BURSTCOUNT_WIDTH), .DEPTH(INPUTFIFOSIZE) ) input_fifo ( .clock(clk), .resetn(!reset), .data_in( {i_atomic_op,i_cmpdata,i_writedata,i_address,i_burstcount} ), .data_out( {i_atomic_op_from_fifo,i_cmpdata_from_fifo,i_writedata_from_fifo,i_address_from_fifo,i_burstcount_from_fifo} ), .valid_in( i_valid ), .valid_out( i_valid_from_fifo ), .stall_in( o_stall_to_fifo ), .stall_out( o_stall ), .usedw( usedw_true_width ) ); end else if(PIPELINE_INPUT) begin reg r_valid; reg [AWIDTH-1:0] r_address; reg [WIDTH-1:0] r_writedata; reg [WIDTH-1:0] r_cmpdata; reg [ATOMIC_WIDTH-1:0] r_atomic_op; reg [BURSTCOUNT_WIDTH-1:0] r_burstcount; assign o_stall = r_valid && o_stall_to_fifo; always@(posedge clk or posedge reset) begin if(reset == 1'b1) r_valid <= 1'b0; else begin if (!o_stall) begin r_valid <= i_valid; r_address <= i_address; r_atomic_op <= i_atomic_op; r_writedata <= i_writedata; r_cmpdata <= i_cmpdata; r_burstcount <= i_burstcount; end end end assign i_valid_from_fifo = r_valid; assign i_address_from_fifo = r_address; assign i_atomic_op_from_fifo = r_atomic_op; assign i_writedata_from_fifo = r_writedata; assign i_cmpdata_from_fifo = r_cmpdata; assign i_burstcount_from_fifo = r_burstcount; end else begin assign i_valid_from_fifo = i_valid; assign i_address_from_fifo = i_address; assign i_atomic_op_from_fifo = i_atomic_op; assign i_writedata_from_fifo = i_writedata; assign i_cmpdata_from_fifo = i_cmpdata; assign o_stall = o_stall_to_fifo; assign i_burstcount_from_fifo = i_burstcount; end endgenerate // Track the number of transactions waiting in the pipeline here reg [COUNTER_WIDTH-1:0] counter; wire incr, decr; assign incr = read_accepted; assign decr = read_used; always@(posedge clk or posedge reset) begin if(reset == 1'b1) begin counter <= {COUNTER_WIDTH{1'b0}}; o_active <= 1'b0; end else begin o_active <= (counter != {COUNTER_WIDTH{1'b0}}); // incr - add one or i_burstcount_from_fifo; decr - subtr one; if (USEBURST==1) counter <= counter + (incr ? i_burstcount_from_fifo : 0) - decr; else counter <= counter + incr - decr; end end generate if(USEBURST) // Use the burstcount to figure out if there is enough space assign ready = ((counter+i_burstcount_from_fifo) <= RETURN_FIFO_SIZE); // // Can also use decr in this calaculation to make ready respond faster // but this seems to hurt Fmax ( ie. not worth it ) //assign ready = ((counter+i_burstcount_from_fifo-decr) <= RETURN_FIFO_SIZE); else // Can we hold one more item assign ready = (counter <= (RETURN_FIFO_SIZE-1)); //utku: what if we dont use return fifo? endgenerate assign o_stall_to_fifo = !ready || out_fifo_wait; // Optional Pipeline register before return // reg r_avm_readdatavalid; reg [WRITEDATAWIDTH-1:0] r_avm_readdata; generate if(SUPERPIPELINE) begin always@(posedge clk or posedge reset) begin if(reset == 1'b1) begin r_avm_readdata <= 'x; r_avm_readdatavalid <= 1'b0; end else begin r_avm_readdata <= avm_readdata; r_avm_readdatavalid <= avm_readdatavalid; end end end else begin // Don't register the return always@(*) begin r_avm_readdata = avm_readdata; r_avm_readdatavalid = avm_readdatavalid; end end endgenerate wire [WIDTH-1:0] rdata; // Byte-addresses enter a FIFO so we can demux the appropriate data back out. generate if(SEGMENT_SELECT_BITS > 0) begin wire [SEGMENT_SELECT_BITS-1:0] segment_address_out; wire [SEGMENT_SELECT_BITS-1:0] segment_address_in; assign segment_address_in = i_address_from_fifo[ALIGNMENT_ABITS +: BYTE_SELECT_BITS-ALIGNMENT_ABITS]; acl_ll_fifo #( .WIDTH(SEGMENT_SELECT_BITS), .DEPTH(KERNEL_SIDE_MEM_LATENCY+1) ) req_fifo ( .clk(clk), .reset(reset), .data_in( segment_address_in ), .data_out( segment_address_out ), .write( read_accepted ), .read( r_avm_readdatavalid ), .empty(), .full() ); assign byte_select = (segment_address_out << ALIGNMENT_ABITS); assign rdata = r_avm_readdata[8*byte_select +: WIDTH]; end else begin assign byte_select = {BYTE_SELECT_BITS{1'b0}}; assign rdata = r_avm_readdata; end endgenerate // set byteenable properly for read path generate if(SEGMENT_SELECT_BITS > 0) begin wire [SEGMENT_SELECT_BITS-1:0] segment_select; assign segment_select = i_address_from_fifo[ALIGNMENT_ABITS +: BYTE_SELECT_BITS-ALIGNMENT_ABITS]; assign segment_address = segment_select*SEGMENT_WIDTH_BYTES; //always@(*) //begin // avm_byteenable = {WRITEDATAWIDTH_BYTES{1'b0}}; // avm_byteenable[segment_select*SEGMENT_WIDTH_BYTES +: WIDTH_BYTES] = {WIDTH_BYTES{1'b1}}; //end end else begin assign segment_address = {BYTE_SELECT_BITS{1'b0}}; //always@(*) //begin //avm_byteenable = {WRITEDATAWIDTH_BYTES{1'b1}}; //end end endgenerate always@(*) begin avm_byteenable = {WRITEDATAWIDTH_BYTES{1'b0}}; avm_byteenable[segment_address +: WIDTH_BYTES] = {WIDTH_BYTES{1'b1}}; end // Status bits assign read_accepted = i_valid_from_fifo && ready && !out_fifo_wait; assign read_used = o_valid && !i_stall; // Optional: Pipelining FIFO on the AVM interface // generate if(SUPERPIPELINE) begin acl_data_fifo #( .DATA_WIDTH(WRITEDATAWIDTH+AWIDTH+BURSTCOUNT_WIDTH), .DEPTH(2), .IMPL("ll_reg") ) avm_buffer ( .clock(clk), .resetn(!reset), .data_in({ {UNUSED_WRITEDATA_WIDTH{1'b0}},segment_address,i_atomic_op_from_fifo,i_cmpdata_from_fifo,i_writedata_from_fifo,1'b1,((i_address_from_fifo >> BYTE_SELECT_BITS) << BYTE_SELECT_BITS),i_burstcount_from_fifo}), .valid_in( i_valid_from_fifo && ready ), .data_out( {avm_writedata,avm_address,avm_burstcount} ), .valid_out( avm_read ), .stall_in( avm_waitrequest ), .stall_out( out_fifo_wait ) ); end else begin // No interface pipelining assign out_fifo_wait = avm_waitrequest; assign avm_address = ((i_address_from_fifo >> BYTE_SELECT_BITS) << BYTE_SELECT_BITS); assign avm_read = i_valid_from_fifo && ready; assign avm_burstcount = i_burstcount_from_fifo; // avm_writedata contains {valid atomic bit, writedata, cmpdata, atomic_op} assign avm_writedata[0:0] = 1'b1; assign avm_writedata[WIDTH:1] = i_writedata_from_fifo; assign avm_writedata[2*WIDTH:WIDTH+1] = i_cmpdata_from_fifo; assign avm_writedata[2*WIDTH+ATOMIC_WIDTH:2*WIDTH+1] = i_atomic_op_from_fifo; assign avm_writedata[2*WIDTH+ATOMIC_WIDTH+BYTE_SELECT_BITS:2*WIDTH+ATOMIC_WIDTH+1] = segment_address; assign avm_writedata[WRITEDATAWIDTH-1:2*WIDTH+ATOMIC_WIDTH+BYTE_SELECT_BITS+1] = { UNUSED_WRITEDATA_WIDTH{1'b0} }; end endgenerate // --------------------------------------------------------------------------------- // Output fifo - must be at least as deep as the maximum number of pending requests // so that we can guarantee a place for the response data if the downstream blocks // are stalling. // generate if(USEOUTPUTFIFO) begin acl_fifo #( .DATA_WIDTH(WIDTH), .DEPTH(RETURN_FIFO_SIZE) ) data_fifo ( .clock(clk), .resetn(!reset), .data_in( rdata ), .data_out( o_readdata ), .valid_in( r_avm_readdatavalid ), .valid_out( o_valid ), .stall_in( i_stall ), .stall_out() ); end else begin assign o_valid = r_avm_readdatavalid; assign o_readdata = rdata; end endgenerate endmodule
`timescale 1ns/10ps module spw_babasu_pll_0( // interface 'refclk' input wire refclk, // interface 'reset' input wire rst, // interface 'outclk0' output wire outclk_0, // interface 'locked' output wire locked ); altera_pll #( .fractional_vco_multiplier("false"), .reference_clock_frequency("50.0 MHz"), .operation_mode("direct"), .number_of_clocks(1), .output_clock_frequency0("200.000000 MHz"), .phase_shift0("0 ps"), .duty_cycle0(50), .output_clock_frequency1("0 MHz"), .phase_shift1("0 ps"), .duty_cycle1(50), .output_clock_frequency2("0 MHz"), .phase_shift2("0 ps"), .duty_cycle2(50), .output_clock_frequency3("0 MHz"), .phase_shift3("0 ps"), .duty_cycle3(50), .output_clock_frequency4("0 MHz"), .phase_shift4("0 ps"), .duty_cycle4(50), .output_clock_frequency5("0 MHz"), .phase_shift5("0 ps"), .duty_cycle5(50), .output_clock_frequency6("0 MHz"), .phase_shift6("0 ps"), .duty_cycle6(50), .output_clock_frequency7("0 MHz"), .phase_shift7("0 ps"), .duty_cycle7(50), .output_clock_frequency8("0 MHz"), .phase_shift8("0 ps"), .duty_cycle8(50), .output_clock_frequency9("0 MHz"), .phase_shift9("0 ps"), .duty_cycle9(50), .output_clock_frequency10("0 MHz"), .phase_shift10("0 ps"), .duty_cycle10(50), .output_clock_frequency11("0 MHz"), .phase_shift11("0 ps"), .duty_cycle11(50), .output_clock_frequency12("0 MHz"), .phase_shift12("0 ps"), .duty_cycle12(50), .output_clock_frequency13("0 MHz"), .phase_shift13("0 ps"), .duty_cycle13(50), .output_clock_frequency14("0 MHz"), .phase_shift14("0 ps"), .duty_cycle14(50), .output_clock_frequency15("0 MHz"), .phase_shift15("0 ps"), .duty_cycle15(50), .output_clock_frequency16("0 MHz"), .phase_shift16("0 ps"), .duty_cycle16(50), .output_clock_frequency17("0 MHz"), .phase_shift17("0 ps"), .duty_cycle17(50), .pll_type("General"), .pll_subtype("General") ) altera_pll_i ( .rst (rst), .outclk ({outclk_0}), .locked (locked), .fboutclk ( ), .fbclk (1'b0), .refclk (refclk) ); endmodule
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 03/12/2016 06:18:20 PM // Design Name: // Module Name: Mux_Array // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// // synopsys dc_script_begin // // synopsys dc_script_end module Mux_Array #(parameter SWR=26, parameter EWR=5) ( input wire clk, input wire rst, input wire load_i, input wire [SWR-1:0] Data_i, input wire FSM_left_right_i, input wire [EWR-1:0] Shift_Value_i, input wire bit_shift_i, output wire [SWR-1:0] Data_o ); ////ge wire [SWR-1:0] Data_array[EWR+1:0]; //////////////////7 genvar k;//Level ///////////////////77777 Rotate_Mux_Array #(.SWR(SWR)) first_rotate( .Data_i(Data_i), .select_i(FSM_left_right_i), .Data_o(Data_array [0][SWR-1:0]) ); generate for (k=0; k < 3; k=k+1) begin : SHIFT_1LVLS shift_mux_array #(.SWR(SWR), .LEVEL(k)) shift_mux_array( .Data_i(Data_array[k]), .select_i(Shift_Value_i[k]), .bit_shift_i(bit_shift_i), .Data_o(Data_array[k+1]) ); end endgenerate RegisterAdd #(.W(SWR)) Mid_Reg( .clk(clk), .rst(rst), .load(1'b1), .D(Data_array[3]), .Q(Data_array[4]) ); generate for (k=3; k < EWR; k=k+1) begin : SHIFT_2LVLS shift_mux_array #(.SWR(SWR), .LEVEL(k)) shift_mux_array( .Data_i(Data_array[k+1]), .select_i(Shift_Value_i[k]), .bit_shift_i(bit_shift_i), .Data_o(Data_array[k+2]) ); end endgenerate Rotate_Mux_Array #(.SWR(SWR)) last_rotate( .Data_i(Data_array[EWR+1]), .select_i(FSM_left_right_i), .Data_o(Data_o) ); endmodule
/***************************************************************************** * File : processing_system7_bfm_v2_0_afi_slave.v * * Date : 2012-11 * * Description : Model that acts as AFI port interface. It uses AXI3 Slave BFM * from Cadence. *****************************************************************************/ module processing_system7_bfm_v2_0_afi_slave ( S_RESETN, S_ARREADY, S_AWREADY, S_BVALID, S_RLAST, S_RVALID, S_WREADY, S_BRESP, S_RRESP, S_RDATA, S_BID, S_RID, S_ACLK, S_ARVALID, S_AWVALID, S_BREADY, S_RREADY, S_WLAST, S_WVALID, S_ARBURST, S_ARLOCK, S_ARSIZE, S_AWBURST, S_AWLOCK, S_AWSIZE, S_ARPROT, S_AWPROT, S_ARADDR, S_AWADDR, S_WDATA, S_ARCACHE, S_ARLEN, S_AWCACHE, S_AWLEN, S_WSTRB, S_ARID, S_AWID, S_WID, S_AWQOS, S_ARQOS, SW_CLK, WR_DATA_ACK_OCM, WR_DATA_ACK_DDR, WR_ADDR, WR_DATA, WR_BYTES, WR_DATA_VALID_OCM, WR_DATA_VALID_DDR, WR_QOS, RD_REQ_DDR, RD_REQ_OCM, RD_ADDR, RD_DATA_OCM, RD_DATA_DDR, RD_BYTES, RD_QOS, RD_DATA_VALID_OCM, RD_DATA_VALID_DDR, S_RDISSUECAP1_EN, S_WRISSUECAP1_EN, S_RCOUNT, S_WCOUNT, S_RACOUNT, S_WACOUNT ); parameter enable_this_port = 0; parameter slave_name = "Slave"; parameter data_bus_width = 32; parameter address_bus_width = 32; parameter id_bus_width = 6; parameter slave_base_address = 0; parameter slave_high_address = 4; parameter max_outstanding_transactions = 8; parameter exclusive_access_supported = 0; `include "processing_system7_bfm_v2_0_local_params.v" /* Local parameters only for this module */ /* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles. This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported. 1-bit extra width than the no.of.bits needed to represent the outstanding transactions Extra bit helps in generating the empty and full flags */ parameter int_cntr_width = clogb2(max_outstanding_transactions)+1; /* RESP data */ parameter rsp_fifo_bits = axi_rsp_width+id_bus_width; parameter rsp_lsb = 0; parameter rsp_msb = axi_rsp_width-1; parameter rsp_id_lsb = rsp_msb + 1; parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1; input S_RESETN; output S_ARREADY; output S_AWREADY; output S_BVALID; output S_RLAST; output S_RVALID; output S_WREADY; output [axi_rsp_width-1:0] S_BRESP; output [axi_rsp_width-1:0] S_RRESP; output [data_bus_width-1:0] S_RDATA; output [id_bus_width-1:0] S_BID; output [id_bus_width-1:0] S_RID; input S_ACLK; input S_ARVALID; input S_AWVALID; input S_BREADY; input S_RREADY; input S_WLAST; input S_WVALID; input [axi_brst_type_width-1:0] S_ARBURST; input [axi_lock_width-1:0] S_ARLOCK; input [axi_size_width-1:0] S_ARSIZE; input [axi_brst_type_width-1:0] S_AWBURST; input [axi_lock_width-1:0] S_AWLOCK; input [axi_size_width-1:0] S_AWSIZE; input [axi_prot_width-1:0] S_ARPROT; input [axi_prot_width-1:0] S_AWPROT; input [address_bus_width-1:0] S_ARADDR; input [address_bus_width-1:0] S_AWADDR; input [data_bus_width-1:0] S_WDATA; input [axi_cache_width-1:0] S_ARCACHE; input [axi_cache_width-1:0] S_ARLEN; input [axi_qos_width-1:0] S_ARQOS; input [axi_cache_width-1:0] S_AWCACHE; input [axi_len_width-1:0] S_AWLEN; input [axi_qos_width-1:0] S_AWQOS; input [(data_bus_width/8)-1:0] S_WSTRB; input [id_bus_width-1:0] S_ARID; input [id_bus_width-1:0] S_AWID; input [id_bus_width-1:0] S_WID; input SW_CLK; input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM; output WR_DATA_VALID_DDR, WR_DATA_VALID_OCM; output [max_burst_bits-1:0] WR_DATA; output [addr_width-1:0] WR_ADDR; output [max_transfer_bytes_width:0] WR_BYTES; output reg RD_REQ_OCM, RD_REQ_DDR; output reg [addr_width-1:0] RD_ADDR; input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM; output reg[max_transfer_bytes_width:0] RD_BYTES; input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR; output [axi_qos_width-1:0] WR_QOS; output reg [axi_qos_width-1:0] RD_QOS; input S_RDISSUECAP1_EN; input S_WRISSUECAP1_EN; output [7:0] S_RCOUNT; output [7:0] S_WCOUNT; output [2:0] S_RACOUNT; output [5:0] S_WACOUNT; wire net_ARVALID; wire net_AWVALID; wire net_WVALID; real s_aclk_period; cdn_axi3_slave_bfm #(slave_name, data_bus_width, address_bus_width, id_bus_width, slave_base_address, (slave_high_address- slave_base_address), max_outstanding_transactions, 0, ///MEMORY_MODEL_MODE, exclusive_access_supported) slave (.ACLK (S_ACLK), .ARESETn (S_RESETN), /// confirm this // Write Address Channel .AWID (S_AWID), .AWADDR (S_AWADDR), .AWLEN (S_AWLEN), .AWSIZE (S_AWSIZE), .AWBURST (S_AWBURST), .AWLOCK (S_AWLOCK), .AWCACHE (S_AWCACHE), .AWPROT (S_AWPROT), .AWVALID (net_AWVALID), .AWREADY (S_AWREADY), // Write Data Channel Signals. .WID (S_WID), .WDATA (S_WDATA), .WSTRB (S_WSTRB), .WLAST (S_WLAST), .WVALID (net_WVALID), .WREADY (S_WREADY), // Write Response Channel Signals. .BID (S_BID), .BRESP (S_BRESP), .BVALID (S_BVALID), .BREADY (S_BREADY), // Read Address Channel Signals. .ARID (S_ARID), .ARADDR (S_ARADDR), .ARLEN (S_ARLEN), .ARSIZE (S_ARSIZE), .ARBURST (S_ARBURST), .ARLOCK (S_ARLOCK), .ARCACHE (S_ARCACHE), .ARPROT (S_ARPROT), .ARVALID (net_ARVALID), .ARREADY (S_ARREADY), // Read Data Channel Signals. .RID (S_RID), .RDATA (S_RDATA), .RRESP (S_RRESP), .RLAST (S_RLAST), .RVALID (S_RVALID), .RREADY (S_RREADY)); wire wr_intr_fifo_full; reg temp_wr_intr_fifo_full; /* Interconnect WR_FIFO model instance */ processing_system7_bfm_v2_0_intr_wr_mem wr_intr_fifo(SW_CLK, S_RESETN, wr_intr_fifo_full, WR_DATA_ACK_OCM, WR_DATA_ACK_DDR, WR_ADDR, WR_DATA, WR_BYTES, WR_QOS, WR_DATA_VALID_OCM, WR_DATA_VALID_DDR); /* Register the async 'full' signal to S_ACLK clock */ always@(posedge S_ACLK) temp_wr_intr_fifo_full = wr_intr_fifo_full; /* Latency type and Debug/Error Control */ reg[1:0] latency_type = RANDOM_CASE; reg DEBUG_INFO = 1; reg STOP_ON_ERROR = 1'b1; /* Internal nets/regs for calling slave BFM API's*/ reg [wr_afi_fifo_data_bits-1:0] wr_fifo [0:max_outstanding_transactions-1]; reg [int_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0; wire wr_fifo_empty; /* Store the awvalid receive time --- necessary for calculating the bresp latency */ reg [7:0] aw_time_cnt = 0,bresp_time_cnt = 0; real awvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new awvalid is received reg awvalid_flag[0:max_outstanding_transactions]; // store the time when a new awvalid is received /* Address Write Channel handshake*/ reg[int_cntr_width-1:0] aw_cnt = 0;// /* various FIFOs for storing the ADDR channel info */ reg [axi_size_width-1:0] awsize [0:max_outstanding_transactions-1]; reg [axi_prot_width-1:0] awprot [0:max_outstanding_transactions-1]; reg [axi_lock_width-1:0] awlock [0:max_outstanding_transactions-1]; reg [axi_cache_width-1:0] awcache [0:max_outstanding_transactions-1]; reg [axi_brst_type_width-1:0] awbrst [0:max_outstanding_transactions-1]; reg [axi_len_width-1:0] awlen [0:max_outstanding_transactions-1]; reg aw_flag [0:max_outstanding_transactions-1]; reg [addr_width-1:0] awaddr [0:max_outstanding_transactions-1]; reg [id_bus_width-1:0] awid [0:max_outstanding_transactions-1]; reg [axi_qos_width-1:0] awqos [0:max_outstanding_transactions-1]; wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached) /* internal fifos to store burst write data, ID & strobes*/ reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_outstanding_transactions-1]; reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer reg wlast_flag [0:max_outstanding_transactions-1]; // flag to indicate WLAST received wire wd_fifo_full; /* Write Data Channel and Write Response handshake signals*/ reg [int_cntr_width-1:0] wd_cnt = 0; reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data; reg [addr_width-1:0] aligned_wr_addr; reg [max_burst_bytes_width:0] valid_data_bytes; reg [int_cntr_width-1:0] wr_bresp_cnt = 0; reg [axi_rsp_width-1:0] bresp; reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response reg enable_write_bresp; reg [int_cntr_width-1:0] rd_bresp_cnt = 0; integer wr_latency_count; reg wr_delayed; wire bresp_fifo_empty; /* keep track of count values */ reg[7:0] wcount; reg[5:0] wacount; /* Qos*/ reg [axi_qos_width-1:0] ar_qos, aw_qos; initial begin if(DEBUG_INFO) begin if(enable_this_port) $display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name); else $display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name); end end /*--------------------------------------------------------------------------------*/ /* Store the Clock cycle time period */ always@(S_RESETN) begin if(S_RESETN) begin @(posedge S_ACLK); s_aclk_period = $time; @(posedge S_ACLK); s_aclk_period = $time - s_aclk_period; end end /*--------------------------------------------------------------------------------*/ initial slave.set_disable_reset_value_checks(1); initial begin repeat(2) @(posedge S_ACLK); if(!enable_this_port) begin slave.set_channel_level_info(0); slave.set_function_level_info(0); end slave.RESPONSE_TIMEOUT = 0; end /*--------------------------------------------------------------------------------*/ /* Set Latency type to be used */ task set_latency_type; input[1:0] lat; begin if(enable_this_port) latency_type = lat; else begin //if(DEBUG_INFO) $display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name); end end endtask /*--------------------------------------------------------------------------------*/ /* Set ARQoS to be used */ task set_arqos; input[axi_qos_width-1:0] qos; begin if(enable_this_port) ar_qos = qos; else begin if(DEBUG_INFO) $display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name); end end endtask /*--------------------------------------------------------------------------------*/ /* Set AWQoS to be used */ task set_awqos; input[axi_qos_width-1:0] qos; begin if(enable_this_port) aw_qos = qos; else begin if(DEBUG_INFO) $display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name); end end endtask /*--------------------------------------------------------------------------------*/ /* get the wr latency number */ function [31:0] get_wr_lat_number; input dummy; reg[1:0] temp; begin case(latency_type) BEST_CASE : get_wr_lat_number = afi_wr_min; AVG_CASE : get_wr_lat_number = afi_wr_avg; WORST_CASE : get_wr_lat_number = afi_wr_max; default : begin // RANDOM_CASE temp = $random; case(temp) 2'b00 : get_wr_lat_number = ($random()%10+ afi_wr_min); 2'b01 : get_wr_lat_number = ($random()%40+ afi_wr_avg); default : get_wr_lat_number = ($random()%60+ afi_wr_max); endcase end endcase end endfunction /*--------------------------------------------------------------------------------*/ /* get the rd latency number */ function [31:0] get_rd_lat_number; input dummy; reg[1:0] temp; begin case(latency_type) BEST_CASE : get_rd_lat_number = afi_rd_min; AVG_CASE : get_rd_lat_number = afi_rd_avg; WORST_CASE : get_rd_lat_number = afi_rd_max; default : begin // RANDOM_CASE temp = $random; case(temp) 2'b00 : get_rd_lat_number = ($random()%10+ afi_rd_min); 2'b01 : get_rd_lat_number = ($random()%40+ afi_rd_avg); default : get_rd_lat_number = ($random()%60+ afi_rd_max); endcase end endcase end endfunction /*--------------------------------------------------------------------------------*/ /* Check for any WRITE/READs when this port is disabled */ always@(S_AWVALID or S_WVALID or S_ARVALID) begin if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin $display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name); $stop; end end /*--------------------------------------------------------------------------------*/ assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0; assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0; assign net_WVALID = enable_this_port ? S_WVALID : 1'b0; assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0; assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0; assign bresp_fifo_full = ((wr_bresp_cnt[int_cntr_width-1] !== rd_bresp_cnt[int_cntr_width-1]) && (wr_bresp_cnt[int_cntr_width-2:0] === rd_bresp_cnt[int_cntr_width-2:0]))?1'b1:1'b0; assign S_WCOUNT = wcount; assign S_WACOUNT = wacount; // FIFO_STATUS (only if AFI port) 1- full function automatic wrfifo_full ; input [axi_len_width-1:0] fifo_space_exp; integer fifo_space_left; begin fifo_space_left = afi_fifo_locations - wcount; if(fifo_space_left < fifo_space_exp) wrfifo_full = 1; else wrfifo_full = 0; end endfunction /*--------------------------------------------------------------------------------*/ /* Store the awvalid receive time --- necessary for calculating the bresp latency */ always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID ) begin if(!S_RESETN) aw_time_cnt <= 0; else begin if(S_AWVALID) begin awvalid_receive_time[aw_time_cnt] <= $time; awvalid_flag[aw_time_cnt] <= 1'b1; aw_time_cnt <= aw_time_cnt + 1; end end // else end /// always /*--------------------------------------------------------------------------------*/ always@(posedge S_ACLK) begin if(net_AWVALID && S_AWREADY) begin if(S_AWQOS === 0) awqos[aw_cnt[int_cntr_width-2:0]] = aw_qos; else awqos[aw_cnt[int_cntr_width-2:0]] = S_AWQOS; end end /* Address Write Channel handshake*/ always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN) begin aw_cnt <= 0; wacount <= 0; end else begin if(S_AWVALID && !wrfifo_full(S_AWLEN+1)) begin slave.RECEIVE_WRITE_ADDRESS(0, id_invalid, awaddr[aw_cnt[int_cntr_width-2:0]], awlen[aw_cnt[int_cntr_width-2:0]], awsize[aw_cnt[int_cntr_width-2:0]], awbrst[aw_cnt[int_cntr_width-2:0]], awlock[aw_cnt[int_cntr_width-2:0]], awcache[aw_cnt[int_cntr_width-2:0]], awprot[aw_cnt[int_cntr_width-2:0]], awid[aw_cnt[int_cntr_width-2:0]]); /// sampled valid ID. aw_flag[aw_cnt[int_cntr_width-2:0]] <= 1'b1; aw_cnt <= aw_cnt + 1; wacount <= wacount + 1; end // if (!aw_fifo_full) end /// if else end /// always /*--------------------------------------------------------------------------------*/ /* Write Data Channel Handshake */ always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN) begin wd_cnt <= 0; end else begin if(aw_flag[wd_cnt[int_cntr_width-2:0]]) begin if(S_WVALID && !wrfifo_full(awlen[wd_cnt[int_cntr_width-2:0]] + 1)) begin slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]); wlast_flag[wd_cnt[int_cntr_width-2:0]] <= 1'b1; wd_cnt <= wd_cnt + 1; end end else begin if(!wrfifo_full(axi_burst_len) && S_WVALID) begin slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]); wlast_flag[wd_cnt[int_cntr_width-2:0]] <= 1'b1; wd_cnt <= wd_cnt + 1; end end /// if end /// else end /// always /*--------------------------------------------------------------------------------*/ /* Align the wrap data for write transaction */ task automatic get_wrap_aligned_wr_data; output [(data_bus_width*axi_burst_len)-1:0] aligned_data; output [addr_width-1:0] start_addr; /// aligned start address input [addr_width-1:0] addr; input [(data_bus_width*axi_burst_len)-1:0] b_data; input [max_burst_bytes_width:0] v_bytes; reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data; integer wrp_bytes; integer i; begin start_addr = (addr/v_bytes) * v_bytes; wrp_bytes = addr - start_addr; wrp_data = b_data; temp_data = 0; wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8)); while(wrp_bytes > 0) begin /// get the data that is wrapped temp_data = temp_data << 8; temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8]; wrp_data = wrp_data << 8; wrp_bytes = wrp_bytes - 1; end wrp_bytes = addr - start_addr; wrp_data = b_data << (wrp_bytes*8); aligned_data = (temp_data | wrp_data); end endtask /*--------------------------------------------------------------------------------*/ /* Calculate the Response for each read/write transaction */ function [axi_rsp_width-1:0] calculate_resp; input [addr_width-1:0] awaddr; input [axi_prot_width-1:0] awprot; reg [axi_rsp_width-1:0] rsp; begin rsp = AXI_OK; /* Address Decode */ if(decode_address(awaddr) === INVALID_MEM_TYPE) begin rsp = AXI_SLV_ERR; //slave error $display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr); end else if(decode_address(awaddr) === REG_MEM) begin rsp = AXI_SLV_ERR; //slave error $display("[%0d] : %0s : %0s : AXI Access to Register Map(0x%0h) is not allowed through this port.",$time, DISP_ERR, slave_name, awaddr); end if(secure_access_enabled && awprot[1]) rsp = AXI_DEC_ERR; // decode error calculate_resp = rsp; end endfunction /*--------------------------------------------------------------------------------*/ reg[max_burst_bits-1:0] temp_wr_data; /* Store the Write response for each write transaction */ always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN) begin wr_fifo_wr_ptr <= 0; wcount <= 0; end else begin enable_write_bresp = aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] && wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]]; /* calculate bresp only when AWVALID && WLAST is received */ if(enable_write_bresp) begin aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] <= 0; wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] <= 0; bresp = calculate_resp(awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], awprot[wr_fifo_wr_ptr[int_cntr_width-2:0]]); /* Fill AFI_WR_data FIFO */ if(bresp === AXI_OK ) begin if(awbrst[wr_fifo_wr_ptr[int_cntr_width-2:0]]=== AXI_WRAP) begin /// wrap type? then align the data get_wrap_aligned_wr_data(aligned_wr_data, aligned_wr_addr, awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]],burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]); /// gives wrapped start address end else begin aligned_wr_data = burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]]; aligned_wr_addr = awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]] ; end valid_data_bytes = burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]; end else valid_data_bytes = 0; temp_wr_data = aligned_wr_data; wr_fifo[wr_fifo_wr_ptr[int_cntr_width-2:0]] = {awqos[wr_fifo_wr_ptr[int_cntr_width-2:0]], awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]], awid[wr_fifo_wr_ptr[int_cntr_width-2:0]], bresp, temp_wr_data, aligned_wr_addr, valid_data_bytes}; wcount <= wcount + awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]]+1; wr_fifo_wr_ptr <= wr_fifo_wr_ptr + 1; end end // else end // always /*--------------------------------------------------------------------------------*/ /* Send Write Response Channel handshake */ always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN) begin rd_bresp_cnt <= 0; wr_latency_count = get_wr_lat_number(1); wr_delayed = 0; bresp_time_cnt <= 0; end else begin wr_delayed = 1'b0; if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count)) wr_delayed = 1; if(!bresp_fifo_empty && wr_delayed) begin slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb], // ID fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_msb : rsp_lsb] // Response ); wr_delayed = 0; awvalid_flag[bresp_time_cnt] = 1'b0; bresp_time_cnt <= bresp_time_cnt+1; rd_bresp_cnt <= rd_bresp_cnt + 1; wr_latency_count = get_wr_lat_number(1); end end // else end//always /*--------------------------------------------------------------------------------*/ /* Write Response Channel handshake */ reg wr_int_state; /* Reading from the wr_fifo and sending to Interconnect fifo*/ always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN) begin wr_int_state <= 1'b0; wr_bresp_cnt <= 0; wr_fifo_rd_ptr <= 0; end else begin case(wr_int_state) 1'b0 : begin wr_int_state <= 1'b0; if(!temp_wr_intr_fifo_full && !bresp_fifo_full && !wr_fifo_empty) begin wr_intr_fifo.write_mem({wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_qos_msb:wr_afi_qos_lsb], wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_data_msb:wr_afi_bytes_lsb]}); /// qos, data, address and valid_bytes wr_int_state <= 1'b1; /* start filling the write response fifo at the same time */ fifo_bresp[wr_bresp_cnt[int_cntr_width-2:0]] <= wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_id_msb:wr_afi_rsp_lsb]; // ID and Resp wcount <= wcount - (wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_ln_msb:wr_afi_ln_lsb] + 1); /// burst length wacount <= wacount - 1; wr_fifo_rd_ptr <= wr_fifo_rd_ptr + 1; wr_bresp_cnt <= wr_bresp_cnt+1; end end 1'b1 : begin wr_int_state <= 0; end endcase end end /*--------------------------------------------------------------------------------*/ /*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/ /*-------------------------------- READ HANDSHAKE ---------------------------------------------*/ /* READ CHANNELS */ /* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */ reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0; real arvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new arvalid is received reg arvalid_flag[0:max_outstanding_transactions]; // store the time when a new arvalid is received reg [int_cntr_width-1:0] ar_cnt = 0;// counter for arvalid info /* various FIFOs for storing the ADDR channel info */ reg [axi_size_width-1:0] arsize [0:max_outstanding_transactions-1]; reg [axi_prot_width-1:0] arprot [0:max_outstanding_transactions-1]; reg [axi_brst_type_width-1:0] arbrst [0:max_outstanding_transactions-1]; reg [axi_len_width-1:0] arlen [0:max_outstanding_transactions-1]; reg [axi_cache_width-1:0] arcache [0:max_outstanding_transactions-1]; reg [axi_lock_width-1:0] arlock [0:max_outstanding_transactions-1]; reg ar_flag [0:max_outstanding_transactions-1]; reg [addr_width-1:0] araddr [0:max_outstanding_transactions-1]; reg [id_bus_width-1:0] arid [0:max_outstanding_transactions-1]; reg [axi_qos_width-1:0] arqos [0:max_outstanding_transactions-1]; wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached) reg [int_cntr_width-1:0] wr_rresp_cnt = 0; reg [axi_rsp_width-1:0] rresp; reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response reg enable_write_rresp; /* Send Read Response & Data Channel handshake */ integer rd_latency_count; reg rd_delayed; reg [rd_afi_fifo_bits-1:0] read_fifo[0:max_outstanding_transactions-1]; /// Read Burst Data, addr, size, burst, len, RID, RRESP, valid_bytes reg [int_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0; wire read_fifo_full; reg [7:0] rcount; reg [2:0] racount; wire rd_intr_fifo_full, rd_intr_fifo_empty; wire read_fifo_empty; /* signals to communicate with interconnect RD_FIFO model */ reg rd_req, invalid_rd_req; /* REad control Info 56:25 : Address (32) 24:22 : Size (3) 21:20 : BRST (2) 19:16 : LEN (4) 15:10 : RID (6) 9:8 : RRSP (2) 7:0 : byte cnt (8) */ reg [rd_info_bits-1:0] read_control_info; reg [(data_bus_width*axi_burst_len)-1:0] aligned_rd_data; reg temp_rd_intr_fifo_empty; processing_system7_bfm_v2_0_intr_rd_mem rd_intr_fifo(SW_CLK, S_RESETN, rd_intr_fifo_full, rd_intr_fifo_empty, rd_req, invalid_rd_req, read_control_info , RD_DATA_OCM, RD_DATA_DDR, RD_DATA_VALID_OCM, RD_DATA_VALID_DDR); assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0; assign S_RCOUNT = rcount; assign S_RACOUNT = racount; /* Register the asynch signal empty coming from Interconnect READ FIFO */ always@(posedge S_ACLK) temp_rd_intr_fifo_empty = rd_intr_fifo_empty; // FIFO_STATUS (only if AFI port) 1- full function automatic rdfifo_full ; input [axi_len_width-1:0] fifo_space_exp; integer fifo_space_left; begin fifo_space_left = afi_fifo_locations - rcount; if(fifo_space_left < fifo_space_exp) rdfifo_full = 1; else rdfifo_full = 0; end endfunction /* Store the arvalid receive time --- necessary for calculating the bresp latency */ always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID ) begin if(!S_RESETN) ar_time_cnt <= 0; else begin if(S_ARVALID) begin arvalid_receive_time[ar_time_cnt] <= $time; arvalid_flag[ar_time_cnt] <= 1'b1; ar_time_cnt <= ar_time_cnt + 1; end end // else end /// always /*--------------------------------------------------------------------------------*/ always@(posedge S_ACLK) begin if(net_ARVALID && S_ARREADY) begin if(S_ARQOS === 0) arqos[aw_cnt[int_cntr_width-2:0]] = ar_qos; else arqos[aw_cnt[int_cntr_width-2:0]] = S_ARQOS; end end /* Address Read Channel handshake*/ always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN) begin ar_cnt <= 0; racount <= 0; end else begin if(S_ARVALID && !rdfifo_full(S_ARLEN+1)) begin /// if AFI read fifo is not full slave.RECEIVE_READ_ADDRESS(0, id_invalid, araddr[ar_cnt[int_cntr_width-2:0]], arlen[ar_cnt[int_cntr_width-2:0]], arsize[ar_cnt[int_cntr_width-2:0]], arbrst[ar_cnt[int_cntr_width-2:0]], arlock[ar_cnt[int_cntr_width-2:0]], arcache[ar_cnt[int_cntr_width-2:0]], arprot[ar_cnt[int_cntr_width-2:0]], arid[ar_cnt[int_cntr_width-2:0]]); /// sampled valid ID. ar_flag[ar_cnt[int_cntr_width-2:0]] <= 1'b1; ar_cnt <= ar_cnt+1; racount <= racount + 1; end /// if(!ar_fifo_full) end /// if else end /// always*/ /*--------------------------------------------------------------------------------*/ /* Align Wrap data for read transaction*/ task automatic get_wrap_aligned_rd_data; output [(data_bus_width*axi_burst_len)-1:0] aligned_data; input [addr_width-1:0] addr; input [(data_bus_width*axi_burst_len)-1:0] b_data; input [max_burst_bytes_width:0] v_bytes; reg [addr_width-1:0] start_addr; reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data; integer wrp_bytes; integer i; begin start_addr = (addr/v_bytes) * v_bytes; wrp_bytes = addr - start_addr; wrp_data = b_data; temp_data = 0; while(wrp_bytes > 0) begin /// get the data that is wrapped temp_data = temp_data >> 8; temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0]; wrp_data = wrp_data >> 8; wrp_bytes = wrp_bytes - 1; end temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8)); wrp_bytes = addr - start_addr; wrp_data = b_data >> (wrp_bytes*8); aligned_data = (temp_data | wrp_data); end endtask /*--------------------------------------------------------------------------------*/ parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1; reg rd_fifo_state; reg [addr_width-1:0] temp_read_address; reg [max_burst_bytes_width:0] temp_rd_valid_bytes; /* get the data from memory && also calculate the rresp*/ always@(negedge S_RESETN or posedge SW_CLK) begin if(!S_RESETN)begin wr_rresp_cnt <=0; rd_fifo_state <= RD_DATA_REQ; temp_rd_valid_bytes = 0; temp_read_address <= 0; RD_REQ_DDR <= 1'b0; RD_REQ_OCM <= 1'b0; rd_req <= 0; invalid_rd_req<= 0; RD_QOS <= 0; end else begin case(rd_fifo_state) RD_DATA_REQ : begin rd_fifo_state <= RD_DATA_REQ; RD_REQ_DDR <= 1'b0; RD_REQ_OCM <= 1'b0; invalid_rd_req <= 0; if(ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] && !rd_intr_fifo_full) begin /// check the rd_fifo_bytes, interconnect fifo full condition ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] <= 0; rresp = calculate_resp(araddr[wr_rresp_cnt[int_cntr_width-2:0]],arprot[wr_rresp_cnt[int_cntr_width-2:0]]); temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_cntr_width-2:0]]);//data_bus_width/8; if(arbrst[wr_rresp_cnt[int_cntr_width-2:0]] === AXI_WRAP) /// wrap begin temp_read_address = (araddr[wr_rresp_cnt[int_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes; else temp_read_address = araddr[wr_rresp_cnt[int_cntr_width-2:0]]; if(rresp === AXI_OK) begin case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_cntr_width-2:0]]); OCM_MEM : RD_REQ_OCM <= 1; DDR_MEM : RD_REQ_DDR <= 1; default : invalid_rd_req <= 1; endcase end else invalid_rd_req <= 1; RD_ADDR <= temp_read_address; ///araddr[wr_rresp_cnt[int_cntr_width-2:0]]; RD_BYTES <= temp_rd_valid_bytes; RD_QOS <= arqos[wr_rresp_cnt[int_cntr_width-2:0]]; rd_fifo_state <= WAIT_RD_VALID; rd_req <= 1; racount <= racount - 1; read_control_info <= {araddr[wr_rresp_cnt[int_cntr_width-2:0]], arsize[wr_rresp_cnt[int_cntr_width-2:0]], arbrst[wr_rresp_cnt[int_cntr_width-2:0]], arlen[wr_rresp_cnt[int_cntr_width-2:0]], arid[wr_rresp_cnt[int_cntr_width-2:0]], rresp, temp_rd_valid_bytes }; wr_rresp_cnt <= wr_rresp_cnt + 1; end end WAIT_RD_VALID : begin rd_fifo_state <= WAIT_RD_VALID; rd_req <= 0; if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd_req) begin ///temp_dec == 2'b11) begin RD_REQ_DDR <= 1'b0; RD_REQ_OCM <= 1'b0; invalid_rd_req <= 0; rd_fifo_state <= RD_DATA_REQ; end end endcase end /// else end /// always /*--------------------------------------------------------------------------------*/ /* thread to fill in the AFI RD_FIFO */ reg[rd_afi_fifo_bits-1:0] temp_rd_data;//Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes reg tmp_state; always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN)begin rd_fifo_wr_ptr <= 0; rcount <= 0; tmp_state <= 0; end else begin case(tmp_state) 0 : begin tmp_state <= 0; if(!temp_rd_intr_fifo_empty) begin rd_intr_fifo.read_mem(temp_rd_data); tmp_state <= 1; end end 1 : begin tmp_state <= 1; if(!rdfifo_full(temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1)) begin read_fifo[rd_fifo_wr_ptr[int_cntr_width-2:0]] = temp_rd_data; rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1; rcount <= rcount + temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1; /// Burst length tmp_state <= 0; end end endcase end end /*--------------------------------------------------------------------------------*/ reg[max_burst_bytes_width:0] rd_v_b; reg[rd_afi_fifo_bits-1:0] tmp_fifo_rd; /// Data, addr, size, burst, len, RID, RRESP,valid_bytes reg[(data_bus_width*axi_burst_len)-1:0] temp_read_data; reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp; /* Read Data Channel handshake */ always@(negedge S_RESETN or posedge S_ACLK) begin if(!S_RESETN)begin rd_fifo_rd_ptr <= 0; rd_latency_count <= get_rd_lat_number(1); rd_delayed = 0; rresp_time_cnt <= 0; rd_v_b = 0; end else begin if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count)) begin rd_delayed = 1; end if(!read_fifo_empty && rd_delayed)begin rd_delayed = 0; arvalid_flag[rresp_time_cnt] = 1'b0; tmp_fifo_rd = read_fifo[rd_fifo_rd_ptr[int_cntr_width-2:0]]; rd_v_b = (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1)*(2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb]); temp_read_data = tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb]; if(tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb] === AXI_WRAP) begin get_wrap_aligned_rd_data(aligned_rd_data, tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb], rd_v_b); temp_read_data = aligned_rd_data; end temp_read_rsp = 0; repeat(axi_burst_len) begin temp_read_rsp = temp_read_rsp >> axi_rsp_width; temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = tmp_fifo_rd[rd_afi_rsp_msb : rd_afi_rsp_lsb]; end slave.SEND_READ_BURST_RESP_CTRL(tmp_fifo_rd[rd_afi_id_msb : rd_afi_id_lsb], tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb], tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb], tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb], temp_read_data, temp_read_rsp); rcount <= rcount - (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+ 1) ; rresp_time_cnt <= rresp_time_cnt+1; rd_latency_count <= get_rd_lat_number(1); rd_fifo_rd_ptr <= rd_fifo_rd_ptr+1; end end /// else end /// always endmodule
/////////////////////////////////////////////////////////////////////////////// // // Copyright (C) 2014 Francis Bruno, All Rights Reserved // // This program is free software; you can redistribute it and/or modify it // under the terms of the GNU General Public License as published by the Free // Software Foundation; either version 3 of the License, or (at your option) // any later version. // // This program is distributed in the hope that it will be useful, but // WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY // or FITNESS FOR A PARTICULAR PURPOSE. // See the GNU General Public License for more details. // // You should have received a copy of the GNU General Public License along with // this program; if not, see <http://www.gnu.org/licenses>. // // This code is available under licenses for commercial use. Please contact // Francis Bruno for more information. // // http://www.gplgpu.com // http://www.asicsolutions.com // // Title : Final Cursor // File : final_cursor.v // Author : Frank Bruno // Created : 29-Dec-2005 // RCS File : $Source:$ // Status : $Id:$ // /////////////////////////////////////////////////////////////////////////////// // // Description : // // This module generates the final cursor by using the // cursor-y and cursor-x position. The cursor blinking // is achieved by counting 32 Vsync's. // ////////////////////////////////////////////////////////////////////////////// // // Modules Instantiated: // /////////////////////////////////////////////////////////////////////////////// // // Modification History: // // $Log:$ // /////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// `timescale 1 ns / 10 ps module final_cursor ( input h_reset_n, input t_crt_clk, input c_shift_ld, // Load signal to Attribute serializer input m_att_data_b32, // cursor text attribute input c_cr0b_b6, // Text cursor skew control 1 input c_cr0b_b5, // Text cursor skew control 0 input c_cr0a_b5, // Disable Text cursor input c_t_vsync, // Vertical sync. input ar12_b4, // cursor blink disable (Vid status mux [0]) output cursor_blink_rate, output finalcursor, output char_blink_rate ); reg mux_op; reg [2:0] shifted_data; reg ctvsync_hold; reg [4:0] blink_rate; wire [2:0] m_att_data_b32_d; // delayed m_att_data_b32 wire int_final_cursor; always @(posedge t_crt_clk or negedge h_reset_n) if (!h_reset_n) shifted_data <= 3'b0; else if (c_shift_ld) shifted_data <= {shifted_data[1:0], m_att_data_b32}; assign m_att_data_b32_d = shifted_data; // CR06[6:5] defines the skew applied to the cursor for proper alignment always @* case({c_cr0b_b6, c_cr0b_b5}) 2'b00: mux_op = m_att_data_b32; 2'b01: mux_op = m_att_data_b32_d[0]; 2'b10: mux_op = m_att_data_b32_d[1]; 2'b11: mux_op = m_att_data_b32_d[2]; endcase always @(posedge t_crt_clk or negedge h_reset_n) if (!h_reset_n) begin ctvsync_hold <= 1'b0; blink_rate <= 5'b0; end else begin ctvsync_hold <= c_t_vsync; // Disable blinking if this bit is set. if (ar12_b4) blink_rate <= 5'b0; // Otherwise increment the blinker on every edge of vertical sync. // The actual edge should not matter. else if (c_t_vsync && ~ctvsync_hold) blink_rate <= blink_rate + 1'b1; end // Cursor blinks faster than characters assign cursor_blink_rate = ~blink_rate[3]; assign char_blink_rate = blink_rate[4]; assign int_final_cursor = ~( ~cursor_blink_rate | (~mux_op) ); assign finalcursor = (int_final_cursor & (~c_cr0a_b5)); endmodule
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your //use of Altera Corporation's design tools, logic functions and other //software and tools, and its AMPP partner logic functions, and any //output files any of the foregoing (including device programming or //simulation files), and any associated documentation or information are //expressly subject to the terms and conditions of the Altera Program //License Subscription Agreement or other applicable license agreement, //including, without limitation, that your use is for the sole purpose //of programming logic devices manufactured by Altera and sold by Altera //or its authorized distributors. Please refer to the applicable //agreement for further details. // synthesis translate_off `timescale 1ns / 1ps // synthesis translate_on // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module nios_system_jtag_uart_log_module ( // inputs: clk, data, strobe, valid ) ; input clk; input [ 7: 0] data; input strobe; input valid; //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS reg [31:0] text_handle; // for $fopen initial text_handle = $fopen ("nios_system_jtag_uart_output_stream.dat"); always @(posedge clk) begin if (valid && strobe) begin $fwrite (text_handle, "%b\n", data); // echo raw binary strings to file as ascii to screen $write("%s", ((data == 8'hd) ? 8'ha : data)); // non-standard; poorly documented; required to get real data stream. $fflush (text_handle); end end // clk //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on endmodule // synthesis translate_off `timescale 1ns / 1ps // synthesis translate_on // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module nios_system_jtag_uart_sim_scfifo_w ( // inputs: clk, fifo_wdata, fifo_wr, // outputs: fifo_FF, r_dat, wfifo_empty, wfifo_used ) ; output fifo_FF; output [ 7: 0] r_dat; output wfifo_empty; output [ 5: 0] wfifo_used; input clk; input [ 7: 0] fifo_wdata; input fifo_wr; wire fifo_FF; wire [ 7: 0] r_dat; wire wfifo_empty; wire [ 5: 0] wfifo_used; //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS //nios_system_jtag_uart_log, which is an e_log nios_system_jtag_uart_log_module nios_system_jtag_uart_log ( .clk (clk), .data (fifo_wdata), .strobe (fifo_wr), .valid (fifo_wr) ); assign wfifo_used = {6{1'b0}}; assign r_dat = {8{1'b0}}; assign fifo_FF = 1'b0; assign wfifo_empty = 1'b1; //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on endmodule // synthesis translate_off `timescale 1ns / 1ps // synthesis translate_on // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module nios_system_jtag_uart_scfifo_w ( // inputs: clk, fifo_clear, fifo_wdata, fifo_wr, rd_wfifo, // outputs: fifo_FF, r_dat, wfifo_empty, wfifo_used ) ; output fifo_FF; output [ 7: 0] r_dat; output wfifo_empty; output [ 5: 0] wfifo_used; input clk; input fifo_clear; input [ 7: 0] fifo_wdata; input fifo_wr; input rd_wfifo; wire fifo_FF; wire [ 7: 0] r_dat; wire wfifo_empty; wire [ 5: 0] wfifo_used; //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS nios_system_jtag_uart_sim_scfifo_w the_nios_system_jtag_uart_sim_scfifo_w ( .clk (clk), .fifo_FF (fifo_FF), .fifo_wdata (fifo_wdata), .fifo_wr (fifo_wr), .r_dat (r_dat), .wfifo_empty (wfifo_empty), .wfifo_used (wfifo_used) ); //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on //synthesis read_comments_as_HDL on // scfifo wfifo // ( // .aclr (fifo_clear), // .clock (clk), // .data (fifo_wdata), // .empty (wfifo_empty), // .full (fifo_FF), // .q (r_dat), // .rdreq (rd_wfifo), // .usedw (wfifo_used), // .wrreq (fifo_wr) // ); // // defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", // wfifo.lpm_numwords = 64, // wfifo.lpm_showahead = "OFF", // wfifo.lpm_type = "scfifo", // wfifo.lpm_width = 8, // wfifo.lpm_widthu = 6, // wfifo.overflow_checking = "OFF", // wfifo.underflow_checking = "OFF", // wfifo.use_eab = "ON"; // //synthesis read_comments_as_HDL off endmodule // synthesis translate_off `timescale 1ns / 1ps // synthesis translate_on // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module nios_system_jtag_uart_drom_module ( // inputs: clk, incr_addr, reset_n, // outputs: new_rom, num_bytes, q, safe ) ; parameter POLL_RATE = 100; output new_rom; output [ 31: 0] num_bytes; output [ 7: 0] q; output safe; input clk; input incr_addr; input reset_n; reg [ 11: 0] address; reg d1_pre; reg d2_pre; reg d3_pre; reg d4_pre; reg d5_pre; reg d6_pre; reg d7_pre; reg d8_pre; reg d9_pre; reg [ 7: 0] mem_array [2047: 0]; reg [ 31: 0] mutex [ 1: 0]; reg new_rom; wire [ 31: 0] num_bytes; reg pre; wire [ 7: 0] q; wire safe; //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS assign q = mem_array[address]; always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin d1_pre <= 0; d2_pre <= 0; d3_pre <= 0; d4_pre <= 0; d5_pre <= 0; d6_pre <= 0; d7_pre <= 0; d8_pre <= 0; d9_pre <= 0; new_rom <= 0; end else begin d1_pre <= pre; d2_pre <= d1_pre; d3_pre <= d2_pre; d4_pre <= d3_pre; d5_pre <= d4_pre; d6_pre <= d5_pre; d7_pre <= d6_pre; d8_pre <= d7_pre; d9_pre <= d8_pre; new_rom <= d9_pre; end end assign num_bytes = mutex[1]; reg safe_delay; reg [31:0] poll_count; reg [31:0] mutex_handle; wire interactive = 1'b0 ; // ' assign safe = (address < mutex[1]); initial poll_count = POLL_RATE; always @(posedge clk or negedge reset_n) begin if (reset_n !== 1) begin safe_delay <= 0; end else begin safe_delay <= safe; end end // safe_delay always @(posedge clk or negedge reset_n) begin if (reset_n !== 1) begin // dont worry about null _stream.dat file address <= 0; mem_array[0] <= 0; mutex[0] <= 0; mutex[1] <= 0; pre <= 0; end else begin // deal with the non-reset case pre <= 0; if (incr_addr && safe) address <= address + 1; if (mutex[0] && !safe && safe_delay) begin // and blast the mutex after falling edge of safe if interactive if (interactive) begin mutex_handle = $fopen ("nios_system_jtag_uart_input_mutex.dat"); $fdisplay (mutex_handle, "0"); $fclose (mutex_handle); // $display ($stime, "\t%m:\n\t\tMutex cleared!"); end else begin // sleep until next reset, do not bash mutex. wait (!reset_n); end end // OK to bash mutex. if (poll_count < POLL_RATE) begin // wait poll_count = poll_count + 1; end else begin // do the interesting stuff. poll_count = 0; if (mutex_handle) begin $readmemh ("nios_system_jtag_uart_input_mutex.dat", mutex); end if (mutex[0] && !safe) begin // read stream into mem_array after current characters are gone! // save mutex[0] value to compare to address (generates 'safe') mutex[1] <= mutex[0]; // $display ($stime, "\t%m:\n\t\tMutex hit: Trying to read %d bytes...", mutex[0]); $readmemb("nios_system_jtag_uart_input_stream.dat", mem_array); // bash address and send pulse outside to send the char: address <= 0; pre <= -1; end // else mutex miss... end // poll_count end // reset end // posedge clk //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on endmodule // synthesis translate_off `timescale 1ns / 1ps // synthesis translate_on // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module nios_system_jtag_uart_sim_scfifo_r ( // inputs: clk, fifo_rd, rst_n, // outputs: fifo_EF, fifo_rdata, rfifo_full, rfifo_used ) ; output fifo_EF; output [ 7: 0] fifo_rdata; output rfifo_full; output [ 5: 0] rfifo_used; input clk; input fifo_rd; input rst_n; reg [ 31: 0] bytes_left; wire fifo_EF; reg fifo_rd_d; wire [ 7: 0] fifo_rdata; wire new_rom; wire [ 31: 0] num_bytes; wire [ 6: 0] rfifo_entries; wire rfifo_full; wire [ 5: 0] rfifo_used; wire safe; //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS //nios_system_jtag_uart_drom, which is an e_drom nios_system_jtag_uart_drom_module nios_system_jtag_uart_drom ( .clk (clk), .incr_addr (fifo_rd_d), .new_rom (new_rom), .num_bytes (num_bytes), .q (fifo_rdata), .reset_n (rst_n), .safe (safe) ); // Generate rfifo_entries for simulation always @(posedge clk or negedge rst_n) begin if (rst_n == 0) begin bytes_left <= 32'h0; fifo_rd_d <= 1'b0; end else begin fifo_rd_d <= fifo_rd; // decrement on read if (fifo_rd_d) bytes_left <= bytes_left - 1'b1; // catch new contents if (new_rom) bytes_left <= num_bytes; end end assign fifo_EF = bytes_left == 32'b0; assign rfifo_full = bytes_left > 7'h40; assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left; assign rfifo_used = rfifo_entries[5 : 0]; //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on endmodule // synthesis translate_off `timescale 1ns / 1ps // synthesis translate_on // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module nios_system_jtag_uart_scfifo_r ( // inputs: clk, fifo_clear, fifo_rd, rst_n, t_dat, wr_rfifo, // outputs: fifo_EF, fifo_rdata, rfifo_full, rfifo_used ) ; output fifo_EF; output [ 7: 0] fifo_rdata; output rfifo_full; output [ 5: 0] rfifo_used; input clk; input fifo_clear; input fifo_rd; input rst_n; input [ 7: 0] t_dat; input wr_rfifo; wire fifo_EF; wire [ 7: 0] fifo_rdata; wire rfifo_full; wire [ 5: 0] rfifo_used; //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS nios_system_jtag_uart_sim_scfifo_r the_nios_system_jtag_uart_sim_scfifo_r ( .clk (clk), .fifo_EF (fifo_EF), .fifo_rd (fifo_rd), .fifo_rdata (fifo_rdata), .rfifo_full (rfifo_full), .rfifo_used (rfifo_used), .rst_n (rst_n) ); //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on //synthesis read_comments_as_HDL on // scfifo rfifo // ( // .aclr (fifo_clear), // .clock (clk), // .data (t_dat), // .empty (fifo_EF), // .full (rfifo_full), // .q (fifo_rdata), // .rdreq (fifo_rd), // .usedw (rfifo_used), // .wrreq (wr_rfifo) // ); // // defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", // rfifo.lpm_numwords = 64, // rfifo.lpm_showahead = "OFF", // rfifo.lpm_type = "scfifo", // rfifo.lpm_width = 8, // rfifo.lpm_widthu = 6, // rfifo.overflow_checking = "OFF", // rfifo.underflow_checking = "OFF", // rfifo.use_eab = "ON"; // //synthesis read_comments_as_HDL off endmodule // synthesis translate_off `timescale 1ns / 1ps // synthesis translate_on // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module nios_system_jtag_uart ( // inputs: av_address, av_chipselect, av_read_n, av_write_n, av_writedata, clk, rst_n, // outputs: av_irq, av_readdata, av_waitrequest, dataavailable, readyfordata ) /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ; output av_irq; output [ 31: 0] av_readdata; output av_waitrequest; output dataavailable; output readyfordata; input av_address; input av_chipselect; input av_read_n; input av_write_n; input [ 31: 0] av_writedata; input clk; input rst_n; reg ac; wire activity; wire av_irq; wire [ 31: 0] av_readdata; reg av_waitrequest; reg dataavailable; reg fifo_AE; reg fifo_AF; wire fifo_EF; wire fifo_FF; wire fifo_clear; wire fifo_rd; wire [ 7: 0] fifo_rdata; wire [ 7: 0] fifo_wdata; reg fifo_wr; reg ien_AE; reg ien_AF; wire ipen_AE; wire ipen_AF; reg pause_irq; wire [ 7: 0] r_dat; wire r_ena; reg r_val; wire rd_wfifo; reg read_0; reg readyfordata; wire rfifo_full; wire [ 5: 0] rfifo_used; reg rvalid; reg sim_r_ena; reg sim_t_dat; reg sim_t_ena; reg sim_t_pause; wire [ 7: 0] t_dat; reg t_dav; wire t_ena; wire t_pause; wire wfifo_empty; wire [ 5: 0] wfifo_used; reg woverflow; wire wr_rfifo; //avalon_jtag_slave, which is an e_avalon_slave assign rd_wfifo = r_ena & ~wfifo_empty; assign wr_rfifo = t_ena & ~rfifo_full; assign fifo_clear = ~rst_n; nios_system_jtag_uart_scfifo_w the_nios_system_jtag_uart_scfifo_w ( .clk (clk), .fifo_FF (fifo_FF), .fifo_clear (fifo_clear), .fifo_wdata (fifo_wdata), .fifo_wr (fifo_wr), .r_dat (r_dat), .rd_wfifo (rd_wfifo), .wfifo_empty (wfifo_empty), .wfifo_used (wfifo_used) ); nios_system_jtag_uart_scfifo_r the_nios_system_jtag_uart_scfifo_r ( .clk (clk), .fifo_EF (fifo_EF), .fifo_clear (fifo_clear), .fifo_rd (fifo_rd), .fifo_rdata (fifo_rdata), .rfifo_full (rfifo_full), .rfifo_used (rfifo_used), .rst_n (rst_n), .t_dat (t_dat), .wr_rfifo (wr_rfifo) ); assign ipen_AE = ien_AE & fifo_AE; assign ipen_AF = ien_AF & (pause_irq | fifo_AF); assign av_irq = ipen_AE | ipen_AF; assign activity = t_pause | t_ena; always @(posedge clk or negedge rst_n) begin if (rst_n == 0) pause_irq <= 1'b0; else // only if fifo is not empty... if (t_pause & ~fifo_EF) pause_irq <= 1'b1; else if (read_0) pause_irq <= 1'b0; end always @(posedge clk or negedge rst_n) begin if (rst_n == 0) begin r_val <= 1'b0; t_dav <= 1'b1; end else begin r_val <= r_ena & ~wfifo_empty; t_dav <= ~rfifo_full; end end always @(posedge clk or negedge rst_n) begin if (rst_n == 0) begin fifo_AE <= 1'b0; fifo_AF <= 1'b0; fifo_wr <= 1'b0; rvalid <= 1'b0; read_0 <= 1'b0; ien_AE <= 1'b0; ien_AF <= 1'b0; ac <= 1'b0; woverflow <= 1'b0; av_waitrequest <= 1'b1; end else begin fifo_AE <= {fifo_FF,wfifo_used} <= 8; fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8; fifo_wr <= 1'b0; read_0 <= 1'b0; av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest); if (activity) ac <= 1'b1; // write if (av_chipselect & ~av_write_n & av_waitrequest) // addr 1 is control; addr 0 is data if (av_address) begin ien_AF <= av_writedata[0]; ien_AE <= av_writedata[1]; if (av_writedata[10] & ~activity) ac <= 1'b0; end else begin fifo_wr <= ~fifo_FF; woverflow <= fifo_FF; end // read if (av_chipselect & ~av_read_n & av_waitrequest) begin // addr 1 is interrupt; addr 0 is data if (~av_address) rvalid <= ~fifo_EF; read_0 <= ~av_address; end end end assign fifo_wdata = av_writedata[7 : 0]; assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0; assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF }; always @(posedge clk or negedge rst_n) begin if (rst_n == 0) readyfordata <= 0; else readyfordata <= ~fifo_FF; end //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS // Tie off Atlantic Interface signals not used for simulation always @(posedge clk) begin sim_t_pause <= 1'b0; sim_t_ena <= 1'b0; sim_t_dat <= t_dav ? r_dat : {8{r_val}}; sim_r_ena <= 1'b0; end assign r_ena = sim_r_ena; assign t_ena = sim_t_ena; assign t_dat = sim_t_dat; assign t_pause = sim_t_pause; always @(fifo_EF) begin dataavailable = ~fifo_EF; end //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on //synthesis read_comments_as_HDL on // alt_jtag_atlantic nios_system_jtag_uart_alt_jtag_atlantic // ( // .clk (clk), // .r_dat (r_dat), // .r_ena (r_ena), // .r_val (r_val), // .rst_n (rst_n), // .t_dat (t_dat), // .t_dav (t_dav), // .t_ena (t_ena), // .t_pause (t_pause) // ); // // defparam nios_system_jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0, // nios_system_jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6, // nios_system_jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6, // nios_system_jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES"; // // always @(posedge clk or negedge rst_n) // begin // if (rst_n == 0) // dataavailable <= 0; // else // dataavailable <= ~fifo_EF; // end // // //synthesis read_comments_as_HDL off endmodule
module main; reg a, b, c; reg clk, rst, rnd; (* ivl_sinthesis_on *) always @(posedge clk or posedge rst) if (rst) begin a <= 0; b <= 0; c <= 0; end else if (rnd) begin a <= 0; b <= 0; end else begin {c, b, a} <= {c, b, a} + 3'b001; end (* ivl_synthesis_off *) initial begin clk = 0; rst = 0; rnd = 0; #1 rst = 1; #1 rst = 0; if ({c,b,a} !== 3'b000) begin $display("FAILED - no async reset"); $finish; end #1 clk = 1; #1 clk = 0; if ({c,b,a} !== 3'b001) begin $display("FAILED - First clock failed. {%b,%b,%b}", c, b, a); $finish; end #1 clk = 1; #1 clk = 0; #1 clk = 1; #1 clk = 0; #1 clk = 1; #1 clk = 0; #1 clk = 1; #1 clk = 0; if ({c,b,a} !== 3'b101) begin $display("FAILED - Fifth clock failed. {%b,%b,%b}", c, b, a); $finish; end rnd = 1; #1 clk = 1; #1 clk = 0; if ({c,b,a} !== 3'b100) begin $display("FAILED - rnd failed. {%b,%b,%b}", c, b, a); $finish; end $display("PASSED"); end endmodule // main
/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HD__CONB_FUNCTIONAL_PP_V `define SKY130_FD_SC_HD__CONB_FUNCTIONAL_PP_V /** * conb: Constant value, low, high outputs. * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none // Import user defined primitives. `include "../../models/udp_pwrgood_pp_g/sky130_fd_sc_hd__udp_pwrgood_pp_g.v" `include "../../models/udp_pwrgood_pp_p/sky130_fd_sc_hd__udp_pwrgood_pp_p.v" `celldefine module sky130_fd_sc_hd__conb ( HI , LO , VPWR, VGND, VPB , VNB ); // Module ports output HI ; output LO ; input VPWR; input VGND; input VPB ; input VNB ; // Local signals wire pullup0_out_HI ; wire pulldown0_out_LO; // Name Output Other arguments pullup pullup0 (pullup0_out_HI ); sky130_fd_sc_hd__udp_pwrgood_pp$P pwrgood_pp0 (HI , pullup0_out_HI, VPWR ); pulldown pulldown0 (pulldown0_out_LO); sky130_fd_sc_hd__udp_pwrgood_pp$G pwrgood_pp1 (LO , pulldown0_out_LO, VGND); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_HD__CONB_FUNCTIONAL_PP_V
(************************************************************************) (* * The Coq Proof Assistant / The Coq Development Team *) (* v * INRIA, CNRS and contributors - Copyright 1999-2019 *) (* <O___,, * (see CREDITS file for the list of authors) *) (* \VV/ **************************************************************) (* // * This file is distributed under the terms of the *) (* * GNU Lesser General Public License Version 2.1 *) (* * (see LICENSE file for the text of the license) *) (************************************************************************) Require Import ZAxioms ZMulOrder ZSgnAbs NZDiv. (** * Euclidean Division for integers, Euclid convention We use here the "usual" formulation of the Euclid Theorem [forall a b, b<>0 -> exists r q, a = b*q+r /\ 0 <= r < |b| ] The outcome of the modulo function is hence always positive. This corresponds to convention "E" in the following paper: R. Boute, "The Euclidean definition of the functions div and mod", ACM Transactions on Programming Languages and Systems, Vol. 14, No.2, pp. 127-144, April 1992. See files [ZDivTrunc] and [ZDivFloor] for others conventions. We simply extend NZDiv with a bound for modulo that holds regardless of the sign of a and b. This new specification subsume mod_bound_pos, which nonetheless stays there for subtyping. Note also that ZAxiomSig now already contain a div and a modulo (that follow the Floor convention). We just ignore them here. *) Module Type EuclidSpec (Import A : ZAxiomsSig')(Import B : DivMod A). Axiom mod_always_pos : forall a b, b ~= 0 -> 0 <= B.modulo a b < abs b. End EuclidSpec. Module Type ZEuclid (Z:ZAxiomsSig) := NZDiv.NZDiv Z <+ EuclidSpec Z. Module ZEuclidProp (Import A : ZAxiomsSig') (Import B : ZMulOrderProp A) (Import C : ZSgnAbsProp A B) (Import D : ZEuclid A). (** We put notations in a scope, to avoid warnings about redefinitions of notations *) Declare Scope euclid. Infix "/" := D.div : euclid. Infix "mod" := D.modulo : euclid. Local Open Scope euclid. Module Import Private_NZDiv := Nop <+ NZDivProp A D B. (** Another formulation of the main equation *) Lemma mod_eq : forall a b, b~=0 -> a mod b == a - b*(a/b). Proof. intros. rewrite <- add_move_l. symmetry. now apply div_mod. Qed. Ltac pos_or_neg a := let LT := fresh "LT" in let LE := fresh "LE" in destruct (le_gt_cases 0 a) as [LE|LT]; [|rewrite <- opp_pos_neg in LT]. (** Uniqueness theorems *) Theorem div_mod_unique : forall b q1 q2 r1 r2 : t, 0<=r1<abs b -> 0<=r2<abs b -> b*q1+r1 == b*q2+r2 -> q1 == q2 /\ r1 == r2. Proof. intros b q1 q2 r1 r2 Hr1 Hr2 EQ. pos_or_neg b. rewrite abs_eq in * by trivial. apply div_mod_unique with b; trivial. rewrite abs_neq' in * by auto using lt_le_incl. rewrite eq_sym_iff. apply div_mod_unique with (-b); trivial. rewrite 2 mul_opp_l. rewrite add_move_l, sub_opp_r. rewrite <-add_assoc. symmetry. rewrite add_move_l, sub_opp_r. now rewrite (add_comm r2), (add_comm r1). Qed. Theorem div_unique: forall a b q r, 0<=r<abs b -> a == b*q + r -> q == a/b. Proof. intros a b q r Hr EQ. assert (Hb : b~=0). pos_or_neg b. rewrite abs_eq in Hr; intuition; order. rewrite <- opp_0, eq_opp_r. rewrite abs_neq' in Hr; intuition; order. destruct (div_mod_unique b q (a/b) r (a mod b)); trivial. now apply mod_always_pos. now rewrite <- div_mod. Qed. Theorem mod_unique: forall a b q r, 0<=r<abs b -> a == b*q + r -> r == a mod b. Proof. intros a b q r Hr EQ. assert (Hb : b~=0). pos_or_neg b. rewrite abs_eq in Hr; intuition; order. rewrite <- opp_0, eq_opp_r. rewrite abs_neq' in Hr; intuition; order. destruct (div_mod_unique b q (a/b) r (a mod b)); trivial. now apply mod_always_pos. now rewrite <- div_mod. Qed. (** Sign rules *) Lemma div_opp_r : forall a b, b~=0 -> a/(-b) == -(a/b). Proof. intros. symmetry. apply div_unique with (a mod b). rewrite abs_opp; now apply mod_always_pos. rewrite mul_opp_opp; now apply div_mod. Qed. Lemma mod_opp_r : forall a b, b~=0 -> a mod (-b) == a mod b. Proof. intros. symmetry. apply mod_unique with (-(a/b)). rewrite abs_opp; now apply mod_always_pos. rewrite mul_opp_opp; now apply div_mod. Qed. Lemma div_opp_l_z : forall a b, b~=0 -> a mod b == 0 -> (-a)/b == -(a/b). Proof. intros a b Hb Hab. symmetry. apply div_unique with (-(a mod b)). rewrite Hab, opp_0. split; [order|]. pos_or_neg b; [rewrite abs_eq | rewrite abs_neq']; order. now rewrite mul_opp_r, <-opp_add_distr, <-div_mod. Qed. Lemma div_opp_l_nz : forall a b, b~=0 -> a mod b ~= 0 -> (-a)/b == -(a/b)-sgn b. Proof. intros a b Hb Hab. symmetry. apply div_unique with (abs b -(a mod b)). rewrite lt_sub_lt_add_l. rewrite <- le_add_le_sub_l. nzsimpl. rewrite <- (add_0_l (abs b)) at 2. rewrite <- add_lt_mono_r. destruct (mod_always_pos a b); intuition order. rewrite <- 2 add_opp_r, mul_add_distr_l, 2 mul_opp_r. rewrite sgn_abs. rewrite add_shuffle2, add_opp_diag_l; nzsimpl. rewrite <-opp_add_distr, <-div_mod; order. Qed. Lemma mod_opp_l_z : forall a b, b~=0 -> a mod b == 0 -> (-a) mod b == 0. Proof. intros a b Hb Hab. symmetry. apply mod_unique with (-(a/b)). split; [order|now rewrite abs_pos]. now rewrite <-opp_0, <-Hab, mul_opp_r, <-opp_add_distr, <-div_mod. Qed. Lemma mod_opp_l_nz : forall a b, b~=0 -> a mod b ~= 0 -> (-a) mod b == abs b - (a mod b). Proof. intros a b Hb Hab. symmetry. apply mod_unique with (-(a/b)-sgn b). rewrite lt_sub_lt_add_l. rewrite <- le_add_le_sub_l. nzsimpl. rewrite <- (add_0_l (abs b)) at 2. rewrite <- add_lt_mono_r. destruct (mod_always_pos a b); intuition order. rewrite <- 2 add_opp_r, mul_add_distr_l, 2 mul_opp_r. rewrite sgn_abs. rewrite add_shuffle2, add_opp_diag_l; nzsimpl. rewrite <-opp_add_distr, <-div_mod; order. Qed. Lemma div_opp_opp_z : forall a b, b~=0 -> a mod b == 0 -> (-a)/(-b) == a/b. Proof. intros. now rewrite div_opp_r, div_opp_l_z, opp_involutive. Qed. Lemma div_opp_opp_nz : forall a b, b~=0 -> a mod b ~= 0 -> (-a)/(-b) == a/b + sgn(b). Proof. intros. rewrite div_opp_r, div_opp_l_nz by trivial. now rewrite opp_sub_distr, opp_involutive. Qed. Lemma mod_opp_opp_z : forall a b, b~=0 -> a mod b == 0 -> (-a) mod (-b) == 0. Proof. intros. now rewrite mod_opp_r, mod_opp_l_z. Qed. Lemma mod_opp_opp_nz : forall a b, b~=0 -> a mod b ~= 0 -> (-a) mod (-b) == abs b - a mod b. Proof. intros. now rewrite mod_opp_r, mod_opp_l_nz. Qed. (** A division by itself returns 1 *) Lemma div_same : forall a, a~=0 -> a/a == 1. Proof. intros. symmetry. apply div_unique with 0. split; [order|now rewrite abs_pos]. now nzsimpl. Qed. Lemma mod_same : forall a, a~=0 -> a mod a == 0. Proof. intros. rewrite mod_eq, div_same by trivial. nzsimpl. apply sub_diag. Qed. (** A division of a small number by a bigger one yields zero. *) Theorem div_small: forall a b, 0<=a<b -> a/b == 0. Proof. exact div_small. Qed. (** Same situation, in term of modulo: *) Theorem mod_small: forall a b, 0<=a<b -> a mod b == a. Proof. exact mod_small. Qed. (** * Basic values of divisions and modulo. *) Lemma div_0_l: forall a, a~=0 -> 0/a == 0. Proof. intros. pos_or_neg a. apply div_0_l; order. apply opp_inj. rewrite <- div_opp_r, opp_0 by trivial. now apply div_0_l. Qed. Lemma mod_0_l: forall a, a~=0 -> 0 mod a == 0. Proof. intros; rewrite mod_eq, div_0_l; now nzsimpl. Qed. Lemma div_1_r: forall a, a/1 == a. Proof. intros. symmetry. apply div_unique with 0. assert (H:=lt_0_1); rewrite abs_pos; intuition; order. now nzsimpl. Qed. Lemma mod_1_r: forall a, a mod 1 == 0. Proof. intros. rewrite mod_eq, div_1_r; nzsimpl; auto using sub_diag. apply neq_sym, lt_neq; apply lt_0_1. Qed. Lemma div_1_l: forall a, 1<a -> 1/a == 0. Proof. exact div_1_l. Qed. Lemma mod_1_l: forall a, 1<a -> 1 mod a == 1. Proof. exact mod_1_l. Qed. Lemma div_mul : forall a b, b~=0 -> (a*b)/b == a. Proof. intros. symmetry. apply div_unique with 0. split; [order|now rewrite abs_pos]. nzsimpl; apply mul_comm. Qed. Lemma mod_mul : forall a b, b~=0 -> (a*b) mod b == 0. Proof. intros. rewrite mod_eq, div_mul by trivial. rewrite mul_comm; apply sub_diag. Qed. Theorem div_unique_exact a b q: b~=0 -> a == b*q -> q == a/b. Proof. intros Hb H. rewrite H, mul_comm. symmetry. now apply div_mul. Qed. (** * Order results about mod and div *) (** A modulo cannot grow beyond its starting point. *) Theorem mod_le: forall a b, 0<=a -> b~=0 -> a mod b <= a. Proof. intros. pos_or_neg b. apply mod_le; order. rewrite <- mod_opp_r by trivial. apply mod_le; order. Qed. Theorem div_pos : forall a b, 0<=a -> 0<b -> 0<= a/b. Proof. exact div_pos. Qed. Lemma div_str_pos : forall a b, 0<b<=a -> 0 < a/b. Proof. exact div_str_pos. Qed. Lemma div_small_iff : forall a b, b~=0 -> (a/b==0 <-> 0<=a<abs b). Proof. intros a b Hb. split. intros EQ. rewrite (div_mod a b Hb), EQ; nzsimpl. now apply mod_always_pos. intros. pos_or_neg b. apply div_small. now rewrite <- (abs_eq b). apply opp_inj; rewrite opp_0, <- div_opp_r by trivial. apply div_small. rewrite <- (abs_neq' b) by order. trivial. Qed. Lemma mod_small_iff : forall a b, b~=0 -> (a mod b == a <-> 0<=a<abs b). Proof. intros. rewrite <- div_small_iff, mod_eq by trivial. rewrite sub_move_r, <- (add_0_r a) at 1. rewrite add_cancel_l. rewrite eq_sym_iff, eq_mul_0. tauto. Qed. (** As soon as the divisor is strictly greater than 1, the division is strictly decreasing. *) Lemma div_lt : forall a b, 0<a -> 1<b -> a/b < a. Proof. exact div_lt. Qed. (** [le] is compatible with a positive division. *) Lemma div_le_mono : forall a b c, 0<c -> a<=b -> a/c <= b/c. Proof. intros a b c Hc Hab. rewrite lt_eq_cases in Hab. destruct Hab as [LT|EQ]; [|rewrite EQ; order]. rewrite <- lt_succ_r. rewrite (mul_lt_mono_pos_l c) by order. nzsimpl. rewrite (add_lt_mono_r _ _ (a mod c)). rewrite <- div_mod by order. apply lt_le_trans with b; trivial. rewrite (div_mod b c) at 1 by order. rewrite <- add_assoc, <- add_le_mono_l. apply le_trans with (c+0). nzsimpl; destruct (mod_always_pos b c); try order. rewrite abs_eq in *; order. rewrite <- add_le_mono_l. destruct (mod_always_pos a c); order. Qed. (** In this convention, [div] performs Rounding-Toward-Bottom when divisor is positive, and Rounding-Toward-Top otherwise. Since we cannot speak of rational values here, we express this fact by multiplying back by [b], and this leads to a nice unique statement. *) Lemma mul_div_le : forall a b, b~=0 -> b*(a/b) <= a. Proof. intros. rewrite (div_mod a b) at 2; trivial. rewrite <- (add_0_r (b*(a/b))) at 1. rewrite <- add_le_mono_l. now destruct (mod_always_pos a b). Qed. (** Giving a reversed bound is slightly more complex *) Lemma mul_succ_div_gt: forall a b, 0<b -> a < b*(S (a/b)). Proof. intros. nzsimpl. rewrite (div_mod a b) at 1; try order. rewrite <- add_lt_mono_l. destruct (mod_always_pos a b). order. rewrite abs_eq in *; order. Qed. Lemma mul_pred_div_gt: forall a b, b<0 -> a < b*(P (a/b)). Proof. intros a b Hb. rewrite mul_pred_r, <- add_opp_r. rewrite (div_mod a b) at 1; try order. rewrite <- add_lt_mono_l. destruct (mod_always_pos a b). order. rewrite <- opp_pos_neg in Hb. rewrite abs_neq' in *; order. Qed. (** NB: The three previous properties could be used as specifications for [div]. *) (** Inequality [mul_div_le] is exact iff the modulo is zero. *) Lemma div_exact : forall a b, b~=0 -> (a == b*(a/b) <-> a mod b == 0). Proof. intros. rewrite (div_mod a b) at 1; try order. rewrite <- (add_0_r (b*(a/b))) at 2. apply add_cancel_l. Qed. (** Some additional inequalities about div. *) Theorem div_lt_upper_bound: forall a b q, 0<b -> a < b*q -> a/b < q. Proof. intros. rewrite (mul_lt_mono_pos_l b) by trivial. apply le_lt_trans with a; trivial. apply mul_div_le; order. Qed. Theorem div_le_upper_bound: forall a b q, 0<b -> a <= b*q -> a/b <= q. Proof. intros. rewrite <- (div_mul q b) by order. apply div_le_mono; trivial. now rewrite mul_comm. Qed. Theorem div_le_lower_bound: forall a b q, 0<b -> b*q <= a -> q <= a/b. Proof. intros. rewrite <- (div_mul q b) by order. apply div_le_mono; trivial. now rewrite mul_comm. Qed. (** A division respects opposite monotonicity for the divisor *) Lemma div_le_compat_l: forall p q r, 0<=p -> 0<q<=r -> p/r <= p/q. Proof. exact div_le_compat_l. Qed. (** * Relations between usual operations and mod and div *) Lemma mod_add : forall a b c, c~=0 -> (a + b * c) mod c == a mod c. Proof. intros. symmetry. apply mod_unique with (a/c+b); trivial. now apply mod_always_pos. rewrite mul_add_distr_l, add_shuffle0, <- div_mod by order. now rewrite mul_comm. Qed. Lemma div_add : forall a b c, c~=0 -> (a + b * c) / c == a / c + b. Proof. intros. apply (mul_cancel_l _ _ c); try order. apply (add_cancel_r _ _ ((a+b*c) mod c)). rewrite <- div_mod, mod_add by order. rewrite mul_add_distr_l, add_shuffle0, <- div_mod by order. now rewrite mul_comm. Qed. Lemma div_add_l: forall a b c, b~=0 -> (a * b + c) / b == a + c / b. Proof. intros a b c. rewrite (add_comm _ c), (add_comm a). now apply div_add. Qed. (** Cancellations. *) (** With the current convention, the following isn't always true when [c<0]: [-3*-1 / -2*-1 = 3/2 = 1] while [-3/-2 = 2] *) Lemma div_mul_cancel_r : forall a b c, b~=0 -> 0<c -> (a*c)/(b*c) == a/b. Proof. intros. symmetry. apply div_unique with ((a mod b)*c). (* ineqs *) rewrite abs_mul, (abs_eq c) by order. rewrite <-(mul_0_l c), <-mul_lt_mono_pos_r, <-mul_le_mono_pos_r by trivial. now apply mod_always_pos. (* equation *) rewrite (div_mod a b) at 1 by order. rewrite mul_add_distr_r. rewrite add_cancel_r. rewrite <- 2 mul_assoc. now rewrite (mul_comm c). Qed. Lemma div_mul_cancel_l : forall a b c, b~=0 -> 0<c -> (c*a)/(c*b) == a/b. Proof. intros. rewrite !(mul_comm c); now apply div_mul_cancel_r. Qed. Lemma mul_mod_distr_l: forall a b c, b~=0 -> 0<c -> (c*a) mod (c*b) == c * (a mod b). Proof. intros. rewrite <- (add_cancel_l _ _ ((c*b)* ((c*a)/(c*b)))). rewrite <- div_mod. rewrite div_mul_cancel_l by trivial. rewrite <- mul_assoc, <- mul_add_distr_l, mul_cancel_l by order. apply div_mod; order. rewrite <- neq_mul_0; intuition; order. Qed. Lemma mul_mod_distr_r: forall a b c, b~=0 -> 0<c -> (a*c) mod (b*c) == (a mod b) * c. Proof. intros. rewrite !(mul_comm _ c); now rewrite mul_mod_distr_l. Qed. (** Operations modulo. *) Theorem mod_mod: forall a n, n~=0 -> (a mod n) mod n == a mod n. Proof. intros. rewrite mod_small_iff by trivial. now apply mod_always_pos. Qed. Lemma mul_mod_idemp_l : forall a b n, n~=0 -> ((a mod n)*b) mod n == (a*b) mod n. Proof. intros a b n Hn. symmetry. rewrite (div_mod a n) at 1 by order. rewrite add_comm, (mul_comm n), (mul_comm _ b). rewrite mul_add_distr_l, mul_assoc. rewrite mod_add by trivial. now rewrite mul_comm. Qed. Lemma mul_mod_idemp_r : forall a b n, n~=0 -> (a*(b mod n)) mod n == (a*b) mod n. Proof. intros. rewrite !(mul_comm a). now apply mul_mod_idemp_l. Qed. Theorem mul_mod: forall a b n, n~=0 -> (a * b) mod n == ((a mod n) * (b mod n)) mod n. Proof. intros. now rewrite mul_mod_idemp_l, mul_mod_idemp_r. Qed. Lemma add_mod_idemp_l : forall a b n, n~=0 -> ((a mod n)+b) mod n == (a+b) mod n. Proof. intros a b n Hn. symmetry. rewrite (div_mod a n) at 1 by order. rewrite <- add_assoc, add_comm, mul_comm. now rewrite mod_add. Qed. Lemma add_mod_idemp_r : forall a b n, n~=0 -> (a+(b mod n)) mod n == (a+b) mod n. Proof. intros. rewrite !(add_comm a). now apply add_mod_idemp_l. Qed. Theorem add_mod: forall a b n, n~=0 -> (a+b) mod n == (a mod n + b mod n) mod n. Proof. intros. now rewrite add_mod_idemp_l, add_mod_idemp_r. Qed. (** With the current convention, the following result isn't always true with a negative intermediate divisor. For instance [ 3/(-2)/(-2) = 1 <> 0 = 3 / (-2*-2) ] and [ 3/(-2)/2 = -1 <> 0 = 3 / (-2*2) ]. *) Lemma div_div : forall a b c, 0<b -> c~=0 -> (a/b)/c == a/(b*c). Proof. intros a b c Hb Hc. apply div_unique with (b*((a/b) mod c) + a mod b). (* begin 0<= ... <abs(b*c) *) rewrite abs_mul. destruct (mod_always_pos (a/b) c), (mod_always_pos a b); try order. split. apply add_nonneg_nonneg; trivial. apply mul_nonneg_nonneg; order. apply lt_le_trans with (b*((a/b) mod c) + abs b). now rewrite <- add_lt_mono_l. rewrite (abs_eq b) by order. now rewrite <- mul_succ_r, <- mul_le_mono_pos_l, le_succ_l. (* end 0<= ... < abs(b*c) *) rewrite (div_mod a b) at 1 by order. rewrite add_assoc, add_cancel_r. rewrite <- mul_assoc, <- mul_add_distr_l, mul_cancel_l by order. apply div_mod; order. Qed. (** Similarly, the following result doesn't always hold when [b<0]. For instance [3 mod (-2*-2)) = 3] while [3 mod (-2) + (-2)*((3/-2) mod -2) = -1]. *) Lemma mod_mul_r : forall a b c, 0<b -> c~=0 -> a mod (b*c) == a mod b + b*((a/b) mod c). Proof. intros a b c Hb Hc. apply add_cancel_l with (b*c*(a/(b*c))). rewrite <- div_mod by (apply neq_mul_0; split; order). rewrite <- div_div by trivial. rewrite add_assoc, add_shuffle0, <- mul_assoc, <- mul_add_distr_l. rewrite <- div_mod by order. apply div_mod; order. Qed. Lemma mod_div: forall a b, b~=0 -> a mod b / b == 0. Proof. intros a b Hb. rewrite div_small_iff by assumption. auto using mod_always_pos. Qed. (** A last inequality: *) Theorem div_mul_le: forall a b c, 0<=a -> 0<b -> 0<=c -> c*(a/b) <= (c*a)/b. Proof. exact div_mul_le. Qed. (** mod is related to divisibility *) Lemma mod_divides : forall a b, b~=0 -> (a mod b == 0 <-> (b|a)). Proof. intros a b Hb. split. intros Hab. exists (a/b). rewrite mul_comm. rewrite (div_mod a b Hb) at 1. rewrite Hab; now nzsimpl. intros (c,Hc). rewrite Hc. now apply mod_mul. Qed. End ZEuclidProp.
/* Copyright (c) 2014-2018 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ // Language: Verilog 2001 `resetall `timescale 1ns / 1ps `default_nettype none /* * IP ethernet frame transmitter (IP frame in, Ethernet frame out) */ module ip_eth_tx ( input wire clk, input wire rst, /* * IP frame input */ input wire s_ip_hdr_valid, output wire s_ip_hdr_ready, input wire [47:0] s_eth_dest_mac, input wire [47:0] s_eth_src_mac, input wire [15:0] s_eth_type, input wire [5:0] s_ip_dscp, input wire [1:0] s_ip_ecn, input wire [15:0] s_ip_length, input wire [15:0] s_ip_identification, input wire [2:0] s_ip_flags, input wire [12:0] s_ip_fragment_offset, input wire [7:0] s_ip_ttl, input wire [7:0] s_ip_protocol, input wire [31:0] s_ip_source_ip, input wire [31:0] s_ip_dest_ip, input wire [7:0] s_ip_payload_axis_tdata, input wire s_ip_payload_axis_tvalid, output wire s_ip_payload_axis_tready, input wire s_ip_payload_axis_tlast, input wire s_ip_payload_axis_tuser, /* * Ethernet frame output */ output wire m_eth_hdr_valid, input wire m_eth_hdr_ready, output wire [47:0] m_eth_dest_mac, output wire [47:0] m_eth_src_mac, output wire [15:0] m_eth_type, output wire [7:0] m_eth_payload_axis_tdata, output wire m_eth_payload_axis_tvalid, input wire m_eth_payload_axis_tready, output wire m_eth_payload_axis_tlast, output wire m_eth_payload_axis_tuser, /* * Status signals */ output wire busy, output wire error_payload_early_termination ); /* IP Frame Field Length Destination MAC address 6 octets Source MAC address 6 octets Ethertype (0x0800) 2 octets Version (4) 4 bits IHL (5-15) 4 bits DSCP (0) 6 bits ECN (0) 2 bits length 2 octets identification (0?) 2 octets flags (010) 3 bits fragment offset (0) 13 bits time to live (64?) 1 octet protocol 1 octet header checksum 2 octets source IP 4 octets destination IP 4 octets options (IHL-5)*4 octets payload length octets This module receives an IP frame with header fields in parallel along with the payload in an AXI stream, combines the header with the payload, passes through the Ethernet headers, and transmits the complete Ethernet payload on an AXI interface. */ localparam [2:0] STATE_IDLE = 3'd0, STATE_WRITE_HEADER = 3'd1, STATE_WRITE_PAYLOAD = 3'd2, STATE_WRITE_PAYLOAD_LAST = 3'd3, STATE_WAIT_LAST = 3'd4; reg [2:0] state_reg = STATE_IDLE, state_next; // datapath control signals reg store_ip_hdr; reg store_last_word; reg [5:0] hdr_ptr_reg = 6'd0, hdr_ptr_next; reg [15:0] word_count_reg = 16'd0, word_count_next; reg [15:0] hdr_sum_reg = 16'd0, hdr_sum_next; reg [7:0] last_word_data_reg = 8'd0; reg [5:0] ip_dscp_reg = 6'd0; reg [1:0] ip_ecn_reg = 2'd0; reg [15:0] ip_length_reg = 16'd0; reg [15:0] ip_identification_reg = 16'd0; reg [2:0] ip_flags_reg = 3'd0; reg [12:0] ip_fragment_offset_reg = 13'd0; reg [7:0] ip_ttl_reg = 8'd0; reg [7:0] ip_protocol_reg = 8'd0; reg [31:0] ip_source_ip_reg = 32'd0; reg [31:0] ip_dest_ip_reg = 32'd0; reg s_ip_hdr_ready_reg = 1'b0, s_ip_hdr_ready_next; reg s_ip_payload_axis_tready_reg = 1'b0, s_ip_payload_axis_tready_next; reg m_eth_hdr_valid_reg = 1'b0, m_eth_hdr_valid_next; reg [47:0] m_eth_dest_mac_reg = 48'd0; reg [47:0] m_eth_src_mac_reg = 48'd0; reg [15:0] m_eth_type_reg = 16'd0; reg busy_reg = 1'b0; reg error_payload_early_termination_reg = 1'b0, error_payload_early_termination_next; // internal datapath reg [7:0] m_eth_payload_axis_tdata_int; reg m_eth_payload_axis_tvalid_int; reg m_eth_payload_axis_tready_int_reg = 1'b0; reg m_eth_payload_axis_tlast_int; reg m_eth_payload_axis_tuser_int; wire m_eth_payload_axis_tready_int_early; assign s_ip_hdr_ready = s_ip_hdr_ready_reg; assign s_ip_payload_axis_tready = s_ip_payload_axis_tready_reg; assign m_eth_hdr_valid = m_eth_hdr_valid_reg; assign m_eth_dest_mac = m_eth_dest_mac_reg; assign m_eth_src_mac = m_eth_src_mac_reg; assign m_eth_type = m_eth_type_reg; assign busy = busy_reg; assign error_payload_early_termination = error_payload_early_termination_reg; function [15:0] add1c16b; input [15:0] a, b; reg [16:0] t; begin t = a+b; add1c16b = t[15:0] + t[16]; end endfunction always @* begin state_next = STATE_IDLE; s_ip_hdr_ready_next = 1'b0; s_ip_payload_axis_tready_next = 1'b0; store_ip_hdr = 1'b0; store_last_word = 1'b0; hdr_ptr_next = hdr_ptr_reg; word_count_next = word_count_reg; hdr_sum_next = hdr_sum_reg; m_eth_hdr_valid_next = m_eth_hdr_valid_reg && !m_eth_hdr_ready; error_payload_early_termination_next = 1'b0; m_eth_payload_axis_tdata_int = 8'd0; m_eth_payload_axis_tvalid_int = 1'b0; m_eth_payload_axis_tlast_int = 1'b0; m_eth_payload_axis_tuser_int = 1'b0; case (state_reg) STATE_IDLE: begin // idle state - wait for data hdr_ptr_next = 6'd0; s_ip_hdr_ready_next = !m_eth_hdr_valid_next; if (s_ip_hdr_ready && s_ip_hdr_valid) begin store_ip_hdr = 1'b1; s_ip_hdr_ready_next = 1'b0; m_eth_hdr_valid_next = 1'b1; if (m_eth_payload_axis_tready_int_reg) begin m_eth_payload_axis_tvalid_int = 1'b1; m_eth_payload_axis_tdata_int = {4'd4, 4'd5}; // ip_version, ip_ihl hdr_ptr_next = 6'd1; end state_next = STATE_WRITE_HEADER; end else begin state_next = STATE_IDLE; end end STATE_WRITE_HEADER: begin // write header word_count_next = ip_length_reg - 5*4; if (m_eth_payload_axis_tready_int_reg) begin hdr_ptr_next = hdr_ptr_reg + 6'd1; m_eth_payload_axis_tvalid_int = 1; state_next = STATE_WRITE_HEADER; case (hdr_ptr_reg) 6'h00: begin m_eth_payload_axis_tdata_int = {4'd4, 4'd5}; // ip_version, ip_ihl end 6'h01: begin m_eth_payload_axis_tdata_int = {ip_dscp_reg, ip_ecn_reg}; hdr_sum_next = {4'd4, 4'd5, ip_dscp_reg, ip_ecn_reg}; end 6'h02: begin m_eth_payload_axis_tdata_int = ip_length_reg[15: 8]; hdr_sum_next = add1c16b(hdr_sum_reg, ip_length_reg); end 6'h03: begin m_eth_payload_axis_tdata_int = ip_length_reg[ 7: 0]; hdr_sum_next = add1c16b(hdr_sum_reg, ip_identification_reg); end 6'h04: begin m_eth_payload_axis_tdata_int = ip_identification_reg[15: 8]; hdr_sum_next = add1c16b(hdr_sum_reg, {ip_flags_reg, ip_fragment_offset_reg}); end 6'h05: begin m_eth_payload_axis_tdata_int = ip_identification_reg[ 7: 0]; hdr_sum_next = add1c16b(hdr_sum_reg, {ip_ttl_reg, ip_protocol_reg}); end 6'h06: begin m_eth_payload_axis_tdata_int = {ip_flags_reg, ip_fragment_offset_reg[12:8]}; hdr_sum_next = add1c16b(hdr_sum_reg, ip_source_ip_reg[31:16]); end 6'h07: begin m_eth_payload_axis_tdata_int = ip_fragment_offset_reg[ 7: 0]; hdr_sum_next = add1c16b(hdr_sum_reg, ip_source_ip_reg[15:0]); end 6'h08: begin m_eth_payload_axis_tdata_int = ip_ttl_reg; hdr_sum_next = add1c16b(hdr_sum_reg, ip_dest_ip_reg[31:16]); end 6'h09: begin m_eth_payload_axis_tdata_int = ip_protocol_reg; hdr_sum_next = add1c16b(hdr_sum_reg, ip_dest_ip_reg[15:0]); end 6'h0A: m_eth_payload_axis_tdata_int = ~hdr_sum_reg[15: 8]; 6'h0B: m_eth_payload_axis_tdata_int = ~hdr_sum_reg[ 7: 0]; 6'h0C: m_eth_payload_axis_tdata_int = ip_source_ip_reg[31:24]; 6'h0D: m_eth_payload_axis_tdata_int = ip_source_ip_reg[23:16]; 6'h0E: m_eth_payload_axis_tdata_int = ip_source_ip_reg[15: 8]; 6'h0F: m_eth_payload_axis_tdata_int = ip_source_ip_reg[ 7: 0]; 6'h10: m_eth_payload_axis_tdata_int = ip_dest_ip_reg[31:24]; 6'h11: m_eth_payload_axis_tdata_int = ip_dest_ip_reg[23:16]; 6'h12: m_eth_payload_axis_tdata_int = ip_dest_ip_reg[15: 8]; 6'h13: begin m_eth_payload_axis_tdata_int = ip_dest_ip_reg[ 7: 0]; s_ip_payload_axis_tready_next = m_eth_payload_axis_tready_int_early; state_next = STATE_WRITE_PAYLOAD; end endcase end else begin state_next = STATE_WRITE_HEADER; end end STATE_WRITE_PAYLOAD: begin // write payload s_ip_payload_axis_tready_next = m_eth_payload_axis_tready_int_early; m_eth_payload_axis_tdata_int = s_ip_payload_axis_tdata; m_eth_payload_axis_tlast_int = s_ip_payload_axis_tlast; m_eth_payload_axis_tuser_int = s_ip_payload_axis_tuser; if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin // word transfer through word_count_next = word_count_reg - 6'd1; m_eth_payload_axis_tvalid_int = 1'b1; if (s_ip_payload_axis_tlast) begin if (word_count_reg != 16'd1) begin // end of frame, but length does not match m_eth_payload_axis_tuser_int = 1'b1; error_payload_early_termination_next = 1'b1; end s_ip_hdr_ready_next = !m_eth_hdr_valid_next; s_ip_payload_axis_tready_next = 1'b0; state_next = STATE_IDLE; end else begin if (word_count_reg == 16'd1) begin store_last_word = 1'b1; m_eth_payload_axis_tvalid_int = 1'b0; state_next = STATE_WRITE_PAYLOAD_LAST; end else begin state_next = STATE_WRITE_PAYLOAD; end end end else begin state_next = STATE_WRITE_PAYLOAD; end end STATE_WRITE_PAYLOAD_LAST: begin // read and discard until end of frame s_ip_payload_axis_tready_next = m_eth_payload_axis_tready_int_early; m_eth_payload_axis_tdata_int = last_word_data_reg; m_eth_payload_axis_tlast_int = s_ip_payload_axis_tlast; m_eth_payload_axis_tuser_int = s_ip_payload_axis_tuser; if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin if (s_ip_payload_axis_tlast) begin s_ip_hdr_ready_next = !m_eth_hdr_valid_next; s_ip_payload_axis_tready_next = 1'b0; m_eth_payload_axis_tvalid_int = 1'b1; state_next = STATE_IDLE; end else begin state_next = STATE_WRITE_PAYLOAD_LAST; end end else begin state_next = STATE_WRITE_PAYLOAD_LAST; end end STATE_WAIT_LAST: begin // read and discard until end of frame s_ip_payload_axis_tready_next = 1'b1; if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin if (s_ip_payload_axis_tlast) begin s_ip_hdr_ready_next = !m_eth_hdr_valid_next; s_ip_payload_axis_tready_next = 1'b0; state_next = STATE_IDLE; end else begin state_next = STATE_WAIT_LAST; end end else begin state_next = STATE_WAIT_LAST; end end endcase end always @(posedge clk) begin if (rst) begin state_reg <= STATE_IDLE; s_ip_hdr_ready_reg <= 1'b0; s_ip_payload_axis_tready_reg <= 1'b0; m_eth_hdr_valid_reg <= 1'b0; busy_reg <= 1'b0; error_payload_early_termination_reg <= 1'b0; end else begin state_reg <= state_next; s_ip_hdr_ready_reg <= s_ip_hdr_ready_next; s_ip_payload_axis_tready_reg <= s_ip_payload_axis_tready_next; m_eth_hdr_valid_reg <= m_eth_hdr_valid_next; busy_reg <= state_next != STATE_IDLE; error_payload_early_termination_reg <= error_payload_early_termination_next; end hdr_ptr_reg <= hdr_ptr_next; word_count_reg <= word_count_next; hdr_sum_reg <= hdr_sum_next; // datapath if (store_ip_hdr) begin m_eth_dest_mac_reg <= s_eth_dest_mac; m_eth_src_mac_reg <= s_eth_src_mac; m_eth_type_reg <= s_eth_type; ip_dscp_reg <= s_ip_dscp; ip_ecn_reg <= s_ip_ecn; ip_length_reg <= s_ip_length; ip_identification_reg <= s_ip_identification; ip_flags_reg <= s_ip_flags; ip_fragment_offset_reg <= s_ip_fragment_offset; ip_ttl_reg <= s_ip_ttl; ip_protocol_reg <= s_ip_protocol; ip_source_ip_reg <= s_ip_source_ip; ip_dest_ip_reg <= s_ip_dest_ip; end if (store_last_word) begin last_word_data_reg <= m_eth_payload_axis_tdata_int; end end // output datapath logic reg [7:0] m_eth_payload_axis_tdata_reg = 8'd0; reg m_eth_payload_axis_tvalid_reg = 1'b0, m_eth_payload_axis_tvalid_next; reg m_eth_payload_axis_tlast_reg = 1'b0; reg m_eth_payload_axis_tuser_reg = 1'b0; reg [7:0] temp_m_eth_payload_axis_tdata_reg = 8'd0; reg temp_m_eth_payload_axis_tvalid_reg = 1'b0, temp_m_eth_payload_axis_tvalid_next; reg temp_m_eth_payload_axis_tlast_reg = 1'b0; reg temp_m_eth_payload_axis_tuser_reg = 1'b0; // datapath control reg store_eth_payload_int_to_output; reg store_eth_payload_int_to_temp; reg store_eth_payload_axis_temp_to_output; assign m_eth_payload_axis_tdata = m_eth_payload_axis_tdata_reg; assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg; assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg; assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg; // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int)); always @* begin // transfer sink ready state to source m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_reg; temp_m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg; store_eth_payload_int_to_output = 1'b0; store_eth_payload_int_to_temp = 1'b0; store_eth_payload_axis_temp_to_output = 1'b0; if (m_eth_payload_axis_tready_int_reg) begin // input is ready if (m_eth_payload_axis_tready || !m_eth_payload_axis_tvalid_reg) begin // output is ready or currently not valid, transfer data to output m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int; store_eth_payload_int_to_output = 1'b1; end else begin // output is not ready, store input in temp temp_m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int; store_eth_payload_int_to_temp = 1'b1; end end else if (m_eth_payload_axis_tready) begin // input is not ready, but output is ready m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg; temp_m_eth_payload_axis_tvalid_next = 1'b0; store_eth_payload_axis_temp_to_output = 1'b1; end end always @(posedge clk) begin if (rst) begin m_eth_payload_axis_tvalid_reg <= 1'b0; m_eth_payload_axis_tready_int_reg <= 1'b0; temp_m_eth_payload_axis_tvalid_reg <= 1'b0; end else begin m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next; m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early; temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next; end // datapath if (store_eth_payload_int_to_output) begin m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int; m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int; m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int; end else if (store_eth_payload_axis_temp_to_output) begin m_eth_payload_axis_tdata_reg <= temp_m_eth_payload_axis_tdata_reg; m_eth_payload_axis_tlast_reg <= temp_m_eth_payload_axis_tlast_reg; m_eth_payload_axis_tuser_reg <= temp_m_eth_payload_axis_tuser_reg; end if (store_eth_payload_int_to_temp) begin temp_m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int; temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int; temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int; end end endmodule `resetall
///////////////////////////////////////////////////////////// // Created by: Synopsys DC Ultra(TM) in wire load mode // Version : L-2016.03-SP3 // Date : Sat Nov 19 20:29:56 2016 ///////////////////////////////////////////////////////////// module FPU_PIPELINED_FPADDSUB_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_OP, Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag, zero_flag, ready, final_result_ieee ); input [63:0] Data_X; input [63:0] Data_Y; output [63:0] final_result_ieee; input clk, rst, beg_OP, add_subt; output busy, overflow_flag, underflow_flag, zero_flag, ready; wire Shift_reg_FLAGS_7_6, Shift_reg_FLAGS_7_5, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, Data_array_SWR_3__53_, left_right_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG, ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1065, n1066, n1067, n1068, n1075, n1076, n1077, n1078, n1079, n1080, n1082, n1083, n1085, n1086, n1089, n1090, n1091, n1094, n1095, n1096, n1097, n1098, n1099, n1102, n1103, n1104, n1105, n1107, n1108, n1110, n1111, n1112, n1113, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1607, n1608, n1609, n1626, n1627, n1628, n1635, n1644, n1645, n1663, n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1856, n1857, n1859, n1860, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2944, n2945, n2946, n2947, n2949, n2950, n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244, n3245, n3246, n3248, n3249, n3250, n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3991, n3992, n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100, n4101, n4102, n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114, n4115, n4116, n4117, n4119, n4120, n4121, n4122, n4123, n4124, n4125, n4126, n4127, n4128, n4129, n4130, n4131, n4132, n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153, n4154, n4155, n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163, n4164, n4165, n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173, n4174, n4175, n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183, n4184, n4185, n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193, n4194, n4195, n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203, n4204, n4205, n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213, n4214, n4215, n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223, n4224, n4225, n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233, n4234, n4235, n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243, n4244, n4245, n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253, n4254, n4255, n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264, n4265, n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274, n4275, n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284, n4285, n4286, n4288, n4289, n4290, n4291, n4292, n4293, n4294, n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304, n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314, n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324, n4325, n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334, n4335, n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344, n4345, n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354, n4355, n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364, n4365, n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374, n4375, n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384, n4385, n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393, n4394, n4395, n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404, n4405, n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414, n4415, n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424, n4425, n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434, n4435, n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444, n4445, n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454, n4455, n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464, n4465, n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473, n4474, n4475, n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484, n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504, n4505, n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533, n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554, n4555, n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574, n4575, n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584, n4585, n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594, n4595, n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604, n4605, n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614, n4615, n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624, n4625, n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634, n4635, n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644, n4645, n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654, n4655, n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664, n4665, n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674, n4675, n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684, n4685, n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694, n4695, n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704, n4705, n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714, n4715, n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724, n4725, n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734, n4735, n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744, n4745, n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754, n4755, n4756, n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764, n4765, n4766, n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774, n4775, n4776, n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784, n4785, n4786, n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794, n4795, n4796, n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804, n4805, n4806, n4807, n4808, n4809, n4810, n4811, n4812, n4813, n4814, n4815, n4816, n4817, n4818, n4819, n4820, n4821, n4822, n4823, n4824, n4825, n4826, n4827, n4828, n4829, n4830, n4831, n4832, n4833, n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841, n4842, n4843, n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851, n4852, n4853, n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861, n4862, n4863, n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881, n4882, n4883, n4884, n4885, n4886, n4887, n4888, n4889, n4890, n4891, n4892, n4893, n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901, n4902, n4903, n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913, n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4921, n4922, n4923, n4924, n4925, n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933, n4934, n4935, n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943, n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953, n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963, n4964, n4965, n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973, n4974, n4975, n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983, n4984, n4985, n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993, n4994, n4995, n4996, n4997, n4998, n4999, n5000, n5001, n5002, n5003, n5004, n5005, n5006, n5007, n5008, n5009, n5010, n5011, n5012, n5013, n5014, n5015, n5016, n5017, n5018, n5019, n5020, n5021, n5022, n5023, n5024, n5025, n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033, n5034, n5035, n5036, n5037, n5038, n5039, n5040, n5041, n5042, n5043, n5044, n5045, n5046, n5047, n5048, n5049, n5050, n5051, n5052, n5053, n5054, n5055, n5056, n5057, n5058, n5059, n5060, n5061, n5062, n5063, n5064, n5065, n5066, n5067, n5068, n5069, n5070, n5071, n5072, n5073, n5074, n5075, n5076, n5077, n5078, n5079, n5080, n5081, n5082, n5083, n5084, n5085, n5086, n5087, n5088, n5089, n5090, n5091, n5092, n5093, n5094, n5095, n5096, n5097, n5098, n5099, n5100, n5101, n5102, n5103, n5104, n5105, n5106, n5107, n5108, n5109, n5110, n5111, n5112, n5113, n5114, n5115, n5116, n5117, n5118, n5119, n5120, n5121, n5122, n5123, n5124, n5125, n5126, n5127, n5128, n5129, n5130, n5131, n5132, n5133, n5134, n5135, n5136, n5137, n5138, n5139, n5140, n5141, n5142, n5143, n5144, n5145, n5146, n5147, n5148, n5149, n5150, n5151, n5152, n5153, n5154, n5155, n5156, n5157, n5158, n5159, n5160, n5161, n5162, n5163, n5164, n5165, n5166, n5167, n5168, n5169, n5170, n5171, n5172, n5173, n5174, n5175, n5176, n5177, n5178, n5179, n5180, n5181, n5182, n5183, n5184, n5185, n5186, n5187, n5188, n5189, n5190, n5191, n5192, n5193, n5194, n5195, n5196, n5197, n5198, n5199, n5200, n5201, n5202, n5203, n5204, n5205, n5206, n5207, n5208, n5209, n5210, n5211, n5212, n5213, n5214, n5215, n5216, n5217, n5218, n5219, n5220, n5221, n5222, n5223, n5224, n5225, n5226, n5227, n5228, n5229, n5230, n5231, n5232, n5233, n5234, n5235, n5236, n5237, n5238, n5239, n5240, n5241, n5242, n5243, n5244, n5245, n5246, n5247, n5248, n5249, n5250, n5251, n5252, n5253, n5254, n5255, n5256, n5257, n5258, n5259, n5260, n5261, n5262, n5263, n5264, n5265, n5266, n5267, n5268, n5269, n5270, n5271, n5272, n5273, n5274, n5275, n5276, n5277, n5278, n5279, n5280, n5281, n5282, n5283, n5284, n5285, n5286, n5287, n5288, n5289, n5290, n5291, n5292, n5293, n5294, n5295, n5296, n5297, n5298, n5299, n5300, n5301, n5302, n5303, n5304, n5305, n5306, n5307, n5308, n5309, n5310, n5311, n5312, n5313, n5314, n5315, n5316, n5317, n5318, n5319, n5320, n5321, n5322, n5323, n5324, n5325, n5326, n5327, n5328, n5329, n5330, n5332, n5335, n5337, n5338, n5339, n5340, n5341, n5342, n5343, n5344, n5345, n5346, n5347, n5348, n5349, n5350, n5351, n5352, n5353, n5354, n5355, n5356, n5357, n5358, n5359, n5360, n5361, n5362, n5363, n5364, n5365, n5366, n5367, n5368, n5369, n5370, n5371, n5372, n5373, n5374, n5375, n5376, n5377, n5378, n5379, n5380, n5381, n5382, n5383, n5384, n5385, n5386, n5387, n5388, n5389, n5390, n5391, n5392, n5393, n5394, n5395, n5396, n5397, n5398, n5399, n5400, n5401, n5402, n5403, n5404, n5405, n5406, n5407, n5408, n5409, n5410, n5411, n5412, n5413, n5414, n5415, n5416, n5417, n5418, n5419, n5420, n5421, n5422, n5423, n5424, n5425, n5426, n5427, n5428, n5429, n5430, n5431, n5432, n5433, n5434, n5435, n5436, n5437, n5438, n5439, n5440, n5441, n5442, n5443, n5444, n5445, n5446, n5447, n5448, n5449, n5450, n5451, n5452, n5453, n5454, n5455, n5456, n5457, n5458, n5459, n5460, n5461, n5462, n5463, n5464, n5465, n5466, n5467, n5468, n5469, n5470, n5471, n5472, n5473, n5474, n5475, n5476, n5477, n5478, n5479, n5480, n5481, n5482, n5483, n5484, n5485, n5486, n5487, n5488, n5489, n5490, n5491, n5492, n5493, n5494, n5495, n5496, n5497, n5498, n5499, n5500, n5501, n5502, n5503, n5504, n5505, n5506, n5507, n5508, n5509, n5510, n5511, n5512, n5513, n5514, n5515, n5516, n5517, n5518, n5519, n5520, n5521, n5522, n5523, n5524, n5525, n5526, n5527, n5528, n5529, n5530, n5531, n5532, n5533, n5534, n5535, n5536, n5537, n5538, n5539, n5540, n5541, n5542, n5543, n5544, n5545, n5546, n5547, n5548, n5549, n5550, n5551, n5552, n5553, n5554, n5555, n5556, n5557, n5558, n5559, n5560, n5561, n5562, n5563, n5564, n5565, n5566, n5567, n5568, n5569, n5570, n5571, n5572, n5573, n5574, n5575, n5576, n5577, n5578, n5579, n5580, n5581, n5582, n5583, n5584, n5585, n5586, n5587, n5588, n5589, n5590, n5591, n5592, n5593, n5594, n5595, n5596, n5597, n5598, n5599, n5600, n5601, n5602, n5603, n5604, n5605, n5606, n5607, n5608, n5609, n5610, n5611, n5612, n5613, n5614, n5615, n5616, n5617, n5618, n5619, n5620, n5621, n5622, n5623, n5624, n5625, n5626, n5627, n5628, n5629, n5630, n5631, n5632, n5633, n5634, n5635, n5636, n5637, n5638, n5639, n5640, n5641, n5642, n5643, n5644, n5645, n5646, n5647, n5648, n5649, n5650, n5651, n5652, n5653, n5654, n5655, n5656, n5657, n5658, n5659, n5660, n5661, n5662, n5663, n5664, n5665, n5666, n5667, n5668, n5669, n5670, n5671, n5672, n5673, n5674, n5675, n5676, n5677, n5678, n5679, n5680, n5681, n5682, n5683, n5684, n5685, n5686, n5687, n5688, n5689, n5690, n5691, n5692, n5693, n5694, n5695, n5696, n5697, n5698, n5699, n5700, n5701, n5702, n5703, n5704, n5705, n5706, n5707, n5708, n5709, n5710, n5711, n5712, n5713, n5714, n5715, n5716, n5717, n5718, n5719, n5720, n5721, n5722, n5723, n5724, n5725, n5726, n5727, n5728, n5729, n5730, n5731, n5732, n5733, n5734, n5735, n5736, n5737, n5738, n5739, n5740, n5741, n5742, n5743, n5747, n5748, n5749, n5750, n5751, n5752, n5753, n5754, n5755, n5756, n5757, n5758, n5759, n5760, n5761, n5762, n5763, n5764, n5765, n5766, n5767, n5768, n5769, n5770, n5771, n5772, n5773, n5774, n5775, n5776, n5777, n5778, n5779, n5780, n5781, n5782, n5783, n5784, n5785, n5786, n5787, n5788, n5789, n5790, n5791, n5792, n5793, n5794, n5795, n5796, n5797, n5798, n5799, n5800, n5801, n5802, n5803, n5804, n5805, n5806, n5807, n5808, n5809, n5810, n5811, n5812, n5813, n5814, n5815, n5816, n5817, n5818, n5819, n5820, n5821, n5822, n5823, n5824, n5825, n5826, n5827, n5828, n5829, n5830, n5831, n5832, n5833, n5834, n5835, n5836, n5837, n5838, n5839, n5840, n5841, n5842, n5843, n5844, n5845, n5846, n5847, n5848, n5849, n5850, n5851, n5852, n5853, n5854, n5855, n5856, n5857, n5858, n5859, n5860, n5861, n5862, n5863, n5864, n5865, n5866, n5867, n5868, n5869, n5870, n5871, n5872, n5873, n5874, n5875, n5876, n5877, n5878, n5879, n5880, n5881, n5882, n5883, n5884, n5885, n5886, n5887, n5888, n5889, n5890, n5891, n5892, n5893, n5894, n5895, n5896, n5897, n5898, n5899, n5900, n5901, n5902, n5903, n5904, n5905, n5906, n5907, n5908, n5909, n5910, n5911, n5912, n5913, n5914, n5915, n5916, n5917, n5918, n5919, n5920, n5921, n5922, n5923, n5924, n5925, n5926, n5927, n5928, n5929, n5930, n5931, n5932, n5933, n5934, n5935, n5936, n5937, n5938, n5939, n5940, n5941, n5942, n5943, n5944, n5945, n5946, n5947, n5948, n5949, n5950, n5951, n5952, n5953, n5954, n5955, n5956, n5957, n5958, n5959, n5960, n5961, n5962, n5963, n5964, n5965, n5966, n5967, n5968, n5969, n5970, n5971, n5972, n5973, n5974, n5975, n5976, n5977, n5978, n5979, n5980, n5981, n5982, n5983, n5984, n5985, n5986, n5987, n5988, n5989, n5990, n5991, n5992, n5993, n5994, n5995, n5996, n5997, n5998, n5999, n6000, n6001, n6002, n6003, n6004, n6005, n6006, n6007, n6008, n6009, n6010, n6011, n6013, n6014, n6015, n6016, n6017, n6018, n6019, n6020, n6021, n6022, n6023, n6024, n6025, n6026, n6027, n6028, n6029, n6030, n6031, n6032, n6033, n6034, n6035, n6036, n6037, n6038, n6039, n6040, n6041, n6042, n6043, n6044, n6045, n6046, n6047, n6048, n6049, n6050, n6051, n6052, n6053, n6054, n6055, n6056, n6057, n6058, n6059, n6060, n6061, n6062, n6063, n6064, n6065, n6066, n6067, n6068, n6069, n6070, n6071, n6072, n6073, n6074, n6075, n6076, n6077, n6078, n6079, n6080, n6081, n6082, n6083, n6084, n6085, n6086, n6087, n6088, n6089, n6090, n6091, n6092, n6093, n6094, n6095, n6096, n6097, n6098, n6099, n6100, n6101, n6102, n6103, n6104, n6105, n6106, n6107, n6108, n6109, n6110, n6111, n6112, n6113, n6114, n6115, n6116, n6117, n6118, n6119, n6120, n6121, n6122, n6123, n6124, n6125, n6126, n6127, n6128, n6129, n6130, n6131, n6132, n6133, n6134, n6135, n6136, n6137, n6138, n6139, n6140, n6141, n6142, n6143, n6144, n6145, n6146, n6147, n6148, n6149, n6150, n6151, n6152, n6153, n6154, n6155, n6156, n6157, n6158, n6159, n6160, n6161, n6162, n6163, n6164, n6165, n6166, n6167, n6168, n6169, n6170, n6171, n6172, n6173, n6174, n6175, n6176, n6177, n6178, n6179, n6180, n6181, n6182, n6183, n6184, n6185, n6186, n6187, n6188, n6189, n6190, n6191, n6192, n6193, n6194, n6195, n6196, n6197, n6198, n6199, n6200, n6201, n6202, n6203, n6204, n6205, n6206, n6207, n6208, n6209, n6210, n6211, n6212, n6213, n6214, n6215, n6216, n6217, n6218, n6219, n6220, n6221, n6222, n6223, n6224, n6225, n6226, n6227, n6228, n6229, n6230, n6231, n6232, n6233, n6234, n6235, n6236, n6237, n6238, n6239, n6240, n6241, n6242, n6243, n6244, n6245, n6246, n6247, n6248, n6249, n6250, n6251, n6252, n6253, n6254, n6255, n6256, n6257, n6258, n6259, n6260, n6261, n6262, n6263, n6264, n6265, n6266, n6267, n6268, n6269, n6270, n6271, n6272, n6273, n6274, n6275, n6276, n6277, n6278, n6279, n6280, n6281, n6282, n6283, n6284, n6285, n6286, n6287, n6288, n6289, n6290, n6291, n6292, n6293, n6295, n6296, n6297, n6298, n6299, n6300, n6301, n6302, n6303, n6304, n6305, n6306, n6307, n6308, n6309, n6310, n6311, n6312, n6313, n6314, n6315, n6316, n6317, n6318, n6319, n6320, n6321, n6322, n6323, n6324, n6325, n6326, n6327, n6328, n6329, n6330, n6331, n6332, n6333, n6334, n6335, n6336, n6337, n6338, n6339, n6340, n6341, n6342, n6343, n6344, n6345, n6346, n6347, n6348, n6349, n6350, n6351, n6352, n6353, n6354, n6355, n6356, n6357, n6358, n6359, n6360, n6361, n6362, n6363, n6364, n6365, n6366, n6367, n6368, n6369, n6370, n6371, n6372, n6373, n6374, n6375, n6376, n6377, n6378, n6379, n6380, n6381, n6382, n6383, n6384, n6385, n6386, n6387, n6388, n6389, n6390, n6391, n6392, n6393, n6394, n6395, n6396, n6397, n6398, n6399, n6400, n6401, n6402, n6403, n6404, n6405, n6406, n6407, n6408, n6409, n6410, n6411, n6412, n6413, n6414, n6415, n6416, n6417, n6418, n6419, n6420, n6421, n6422, n6423, n6424, n6425, n6426, n6427, n6428, n6429, n6430, n6431, n6432, n6433, n6434, n6435, n6436, n6437, n6438, n6439, n6440, n6441, n6442, n6443, n6444, n6445, n6446, n6447, n6448, n6449, n6450, n6451, n6452, n6453, n6454, n6455, n6456, n6457, n6458, n6459, n6460, n6461, n6462, n6463, n6464, n6465; wire [3:0] Shift_reg_FLAGS_7; wire [63:0] intDX_EWSW; wire [63:0] intDY_EWSW; wire [62:0] DMP_EXP_EWSW; wire [57:0] DmP_EXP_EWSW; wire [62:0] DMP_SHT1_EWSW; wire [51:0] DmP_mant_SHT1_SW; wire [5:0] Shift_amount_SHT1_EWR; wire [53:0] Raw_mant_NRM_SWR; wire [62:0] DMP_SHT2_EWSW; wire [4:2] shift_value_SHT2_EWR; wire [10:0] DMP_exp_NRM2_EW; wire [10:0] DMP_exp_NRM_EW; wire [5:0] LZD_output_NRM2_EW; wire [62:0] DMP_SFG; wire [54:0] DmP_mant_SFG_SWR; wire [2:0] inst_FSM_INPUT_ENABLE_state_reg; DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D( inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n6254), .Q( inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n5489) ); DFFRX2TS inst_ShiftRegister_Q_reg_3_ ( .D(n1798), .CK(clk), .RN(n6254), .Q( Shift_reg_FLAGS_7[3]), .QN(n5447) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1782), .CK(clk), .RN(n6281), .Q(intDX_EWSW[12]), .QN(n3289) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1781), .CK(clk), .RN(n6281), .Q(intDX_EWSW[13]), .QN(n3340) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1779), .CK(clk), .RN(n6274), .Q(intDX_EWSW[15]), .QN(n3290) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1778), .CK(clk), .RN(n6288), .Q(intDX_EWSW[16]), .QN(n3310) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1777), .CK(clk), .RN(n4462), .Q(intDX_EWSW[17]), .QN(n3341) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1776), .CK(clk), .RN(n5651), .Q(intDX_EWSW[18]), .QN(n3356) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1775), .CK(clk), .RN(n6244), .Q(intDX_EWSW[19]), .QN(n3291) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1774), .CK(clk), .RN(n5648), .Q(intDX_EWSW[20]), .QN(n3303) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1773), .CK(clk), .RN(n4461), .Q(intDX_EWSW[21]), .QN(n3311) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1772), .CK(clk), .RN(n4461), .Q(intDX_EWSW[22]), .QN(n3333) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1771), .CK(clk), .RN(n6267), .Q(intDX_EWSW[23]), .QN(n3342) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1770), .CK(clk), .RN(n5670), .Q(intDX_EWSW[24]), .QN(n3348) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1769), .CK(clk), .RN(n6282), .Q(intDX_EWSW[25]), .QN(n3357) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1768), .CK(clk), .RN(n6282), .Q(intDX_EWSW[26]), .QN(n3361) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1767), .CK(clk), .RN(n6282), .Q(intDX_EWSW[27]), .QN(n3292) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1766), .CK(clk), .RN(n6282), .Q(intDX_EWSW[28]), .QN(n3300) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1765), .CK(clk), .RN(n6282), .Q(intDX_EWSW[29]), .QN(n3304) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1764), .CK(clk), .RN(n6282), .Q(intDX_EWSW[30]), .QN(n3307) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1763), .CK(clk), .RN(n6282), .Q(intDX_EWSW[31]), .QN(n3312) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_32_ ( .D(n1762), .CK(clk), .RN(n6282), .Q(intDX_EWSW[32]), .QN(n3316) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_33_ ( .D(n1761), .CK(clk), .RN(n6282), .Q(intDX_EWSW[33]), .QN(n3334) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_34_ ( .D(n1760), .CK(clk), .RN(n6282), .Q(intDX_EWSW[34]), .QN(n3337) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_35_ ( .D(n1759), .CK(clk), .RN(n6283), .Q(intDX_EWSW[35]), .QN(n3343) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_36_ ( .D(n1758), .CK(clk), .RN(n6283), .Q(intDX_EWSW[36]), .QN(n3346) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_37_ ( .D(n1757), .CK(clk), .RN(n6283), .Q(intDX_EWSW[37]), .QN(n3349) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_38_ ( .D(n1756), .CK(clk), .RN(n6283), .Q(intDX_EWSW[38]), .QN(n3351) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_39_ ( .D(n1755), .CK(clk), .RN(n6283), .Q(intDX_EWSW[39]), .QN(n3358) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_40_ ( .D(n1754), .CK(clk), .RN(n6283), .Q(intDX_EWSW[40]), .QN(n3360) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_41_ ( .D(n1753), .CK(clk), .RN(n6283), .Q(intDX_EWSW[41]), .QN(n3362) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_42_ ( .D(n1752), .CK(clk), .RN(n6283), .Q(intDX_EWSW[42]), .QN(n3363) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_43_ ( .D(n1751), .CK(clk), .RN(n6283), .Q(intDX_EWSW[43]), .QN(n3293) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_44_ ( .D(n1750), .CK(clk), .RN(n6283), .Q(intDX_EWSW[44]), .QN(n3294) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_45_ ( .D(n1749), .CK(clk), .RN(n6284), .Q(intDX_EWSW[45]), .QN(n3301) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_46_ ( .D(n1748), .CK(clk), .RN(n6284), .Q(intDX_EWSW[46]), .QN(n3302) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_47_ ( .D(n1747), .CK(clk), .RN(n6284), .Q(intDX_EWSW[47]), .QN(n3305) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_48_ ( .D(n1746), .CK(clk), .RN(n6284), .Q(intDX_EWSW[48]), .QN(n3306) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_49_ ( .D(n1745), .CK(clk), .RN(n6284), .Q(intDX_EWSW[49]), .QN(n3308) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_50_ ( .D(n1744), .CK(clk), .RN(n6284), .Q(intDX_EWSW[50]), .QN(n3309) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_51_ ( .D(n1743), .CK(clk), .RN(n6284), .Q(intDX_EWSW[51]), .QN(n3313) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_52_ ( .D(n1742), .CK(clk), .RN(n6284), .Q(intDX_EWSW[52]), .QN(n3314) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_53_ ( .D(n1741), .CK(clk), .RN(n6284), .Q(intDX_EWSW[53]), .QN(n3318) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_54_ ( .D(n1740), .CK(clk), .RN(n6284), .Q(intDX_EWSW[54]), .QN(n3332) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_55_ ( .D(n1739), .CK(clk), .RN(n6285), .Q(intDX_EWSW[55]), .QN(n3335) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_56_ ( .D(n1738), .CK(clk), .RN(n6285), .Q(intDX_EWSW[56]), .QN(n3336) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_57_ ( .D(n1737), .CK(clk), .RN(n6285), .Q(intDX_EWSW[57]), .QN(n3338) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_58_ ( .D(n1736), .CK(clk), .RN(n6285), .Q(intDX_EWSW[58]), .QN(n3339) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_59_ ( .D(n1735), .CK(clk), .RN(n6285), .Q(intDX_EWSW[59]), .QN(n3344) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_60_ ( .D(n1734), .CK(clk), .RN(n6285), .Q(intDX_EWSW[60]), .QN(n3345) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_61_ ( .D(n1733), .CK(clk), .RN(n6285), .Q(intDX_EWSW[61]), .QN(n3347) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_62_ ( .D(n1732), .CK(clk), .RN(n6285), .Q(intDX_EWSW[62]), .QN(n3377) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1701), .CK(clk), .RN(n6277), .Q(intDY_EWSW[27]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1700), .CK(clk), .RN(n6277), .Q(intDY_EWSW[28]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1699), .CK(clk), .RN(n6277), .Q(intDY_EWSW[29]), .QN(n2254) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1698), .CK(clk), .RN(n6277), .Q(intDY_EWSW[30]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1697), .CK(clk), .RN(n6277), .Q(intDY_EWSW[31]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_32_ ( .D(n1696), .CK(clk), .RN(n6277), .Q(intDY_EWSW[32]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_33_ ( .D(n1695), .CK(clk), .RN(n6277), .Q(intDY_EWSW[33]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_34_ ( .D(n1694), .CK(clk), .RN(n6277), .Q(intDY_EWSW[34]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_35_ ( .D(n1693), .CK(clk), .RN(n6277), .Q(intDY_EWSW[35]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_36_ ( .D(n1692), .CK(clk), .RN(n6277), .Q(intDY_EWSW[36]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_37_ ( .D(n1691), .CK(clk), .RN(n6278), .Q(intDY_EWSW[37]), .QN(n2320) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_38_ ( .D(n1690), .CK(clk), .RN(n6278), .Q(intDY_EWSW[38]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_39_ ( .D(n1689), .CK(clk), .RN(n6278), .Q(intDY_EWSW[39]), .QN(n2302) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_40_ ( .D(n1688), .CK(clk), .RN(n6278), .Q(intDY_EWSW[40]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_41_ ( .D(n1687), .CK(clk), .RN(n6278), .Q(intDY_EWSW[41]), .QN(n2485) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_42_ ( .D(n1686), .CK(clk), .RN(n6278), .Q(intDY_EWSW[42]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_43_ ( .D(n1685), .CK(clk), .RN(n6278), .Q(intDY_EWSW[43]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_44_ ( .D(n1684), .CK(clk), .RN(n6278), .Q(intDY_EWSW[44]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_46_ ( .D(n1682), .CK(clk), .RN(n6278), .Q(intDY_EWSW[46]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_62_ ( .D(n1666), .CK(clk), .RN(n6285), .Q(intDY_EWSW[62]) ); DFFRX2TS SHT2_SHIFT_DATA_Q_reg_53_ ( .D(n1663), .CK(clk), .RN(n6260), .Q( Data_array_SWR_3__53_) ); DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1603), .CK(clk), .RN(n6270), .Q(Shift_amount_SHT1_EWR[1]), .QN(n3366) ); DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1601), .CK(clk), .RN(n6263), .Q(Shift_amount_SHT1_EWR[3]) ); DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1600), .CK(clk), .RN(n6269), .Q(Shift_amount_SHT1_EWR[4]) ); DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_5_ ( .D(n1599), .CK(clk), .RN(n6269), .Q(Shift_amount_SHT1_EWR[5]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_0_ ( .D(n1587), .CK(clk), .RN(n6260), .Q( DMP_EXP_EWSW[0]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_3_ ( .D(n1584), .CK(clk), .RN(n5659), .Q( DMP_EXP_EWSW[3]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_8_ ( .D(n1579), .CK(clk), .RN(n6266), .Q( DMP_EXP_EWSW[8]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_9_ ( .D(n1578), .CK(clk), .RN(n5675), .Q( DMP_EXP_EWSW[9]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_15_ ( .D(n1572), .CK(clk), .RN(n6241), .Q( DMP_EXP_EWSW[15]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_18_ ( .D(n1569), .CK(clk), .RN(n6242), .Q( DMP_EXP_EWSW[18]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_20_ ( .D(n1567), .CK(clk), .RN(n6243), .Q( DMP_EXP_EWSW[20]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n1564), .CK(clk), .RN(n6244), .Q( DMP_EXP_EWSW[23]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n1563), .CK(clk), .RN(n6245), .Q( DMP_EXP_EWSW[24]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n1562), .CK(clk), .RN(n6245), .Q( DMP_EXP_EWSW[25]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_27_ ( .D(n1560), .CK(clk), .RN(n6246), .Q( DMP_EXP_EWSW[27]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_28_ ( .D(n1559), .CK(clk), .RN(n6246), .Q( DMP_EXP_EWSW[28]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_29_ ( .D(n1558), .CK(clk), .RN(n6247), .Q( DMP_EXP_EWSW[29]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_31_ ( .D(n1556), .CK(clk), .RN(n6248), .Q( DMP_EXP_EWSW[31]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_33_ ( .D(n1554), .CK(clk), .RN(n6248), .Q( DMP_EXP_EWSW[33]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_39_ ( .D(n1548), .CK(clk), .RN(n6291), .Q( DMP_EXP_EWSW[39]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_42_ ( .D(n1545), .CK(clk), .RN(n6250), .Q( DMP_EXP_EWSW[42]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_45_ ( .D(n1542), .CK(clk), .RN(n6251), .Q( DMP_EXP_EWSW[45]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_46_ ( .D(n1541), .CK(clk), .RN(n6252), .Q( DMP_EXP_EWSW[46]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_47_ ( .D(n1540), .CK(clk), .RN(n6252), .Q( DMP_EXP_EWSW[47]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_48_ ( .D(n1539), .CK(clk), .RN(n6252), .Q( DMP_EXP_EWSW[48]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_49_ ( .D(n1538), .CK(clk), .RN(n2544), .Q( DMP_EXP_EWSW[49]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_51_ ( .D(n1536), .CK(clk), .RN(n5623), .Q( DMP_EXP_EWSW[51]) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_55_ ( .D(n1532), .CK(clk), .RN(n6273), .Q( DMP_EXP_EWSW[55]), .QN(n5555) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_56_ ( .D(n1531), .CK(clk), .RN(n6273), .Q( DMP_EXP_EWSW[56]), .QN(n5554) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_58_ ( .D(n1529), .CK(clk), .RN(n6274), .Q( DMP_EXP_EWSW[58]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_59_ ( .D(n1528), .CK(clk), .RN(n6275), .Q( DMP_EXP_EWSW[59]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_61_ ( .D(n1526), .CK(clk), .RN(n6240), .Q( DMP_EXP_EWSW[61]) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_62_ ( .D(n1525), .CK(clk), .RN(n6240), .Q( DMP_EXP_EWSW[62]) ); DFFRX1TS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1524), .CK(clk), .RN(n2515), .Q( OP_FLAG_EXP) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1521), .CK(clk), .RN(n6260), .Q( DMP_SHT1_EWSW[0]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1520), .CK(clk), .RN(n6260), .Q( DMP_SHT2_EWSW[0]), .QN(n5361) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1518), .CK(clk), .RN(n5658), .Q( DMP_SHT1_EWSW[1]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1517), .CK(clk), .RN(n5670), .Q( DMP_SHT2_EWSW[1]), .QN(n5452) ); DFFRXLTS SGF_STAGE_DMP_Q_reg_1_ ( .D(n1516), .CK(clk), .RN(n4462), .Q( DMP_SFG[1]), .QN(n5350) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1515), .CK(clk), .RN(n2542), .Q( DMP_SHT1_EWSW[2]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1514), .CK(clk), .RN(n2541), .Q( DMP_SHT2_EWSW[2]), .QN(n5453) ); DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n1513), .CK(clk), .RN(n6264), .Q( DMP_SFG[2]), .QN(n5351) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1512), .CK(clk), .RN(n5659), .Q( DMP_SHT1_EWSW[3]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1511), .CK(clk), .RN(n5652), .Q( DMP_SHT2_EWSW[3]), .QN(n5362) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1509), .CK(clk), .RN(n6266), .Q( DMP_SHT1_EWSW[4]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1508), .CK(clk), .RN(n6266), .Q( DMP_SHT2_EWSW[4]), .QN(n5449) ); DFFRXLTS SGF_STAGE_DMP_Q_reg_4_ ( .D(n1507), .CK(clk), .RN(n6265), .Q( DMP_SFG[4]), .QN(n5347) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1506), .CK(clk), .RN(n6253), .Q( DMP_SHT1_EWSW[5]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1505), .CK(clk), .RN(n5675), .Q( DMP_SHT2_EWSW[5]), .QN(n5456) ); DFFRXLTS SGF_STAGE_DMP_Q_reg_5_ ( .D(n1504), .CK(clk), .RN(n5675), .Q( DMP_SFG[5]), .QN(n5353) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1503), .CK(clk), .RN(n6263), .Q( DMP_SHT1_EWSW[6]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1502), .CK(clk), .RN(n6263), .Q( DMP_SHT2_EWSW[6]), .QN(n5455) ); DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n1501), .CK(clk), .RN(n6263), .Q( DMP_SFG[6]), .QN(n5352) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1500), .CK(clk), .RN(n6265), .Q( DMP_SHT1_EWSW[7]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1499), .CK(clk), .RN(n6265), .Q( DMP_SHT2_EWSW[7]), .QN(n5450) ); DFFRXLTS SGF_STAGE_DMP_Q_reg_7_ ( .D(n1498), .CK(clk), .RN(n6265), .Q( DMP_SFG[7]), .QN(n5348) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1497), .CK(clk), .RN(n6266), .Q( DMP_SHT1_EWSW[8]) ); DFFRXLTS SGF_STAGE_DMP_Q_reg_8_ ( .D(n1495), .CK(clk), .RN(n6266), .Q( DMP_SFG[8]), .QN(n5346) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1494), .CK(clk), .RN(n5675), .Q( DMP_SHT1_EWSW[9]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1493), .CK(clk), .RN(n6261), .Q( DMP_SHT2_EWSW[9]), .QN(n5457) ); DFFRXLTS SGF_STAGE_DMP_Q_reg_9_ ( .D(n1492), .CK(clk), .RN(n6261), .Q( DMP_SFG[9]), .QN(n5354) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1490), .CK(clk), .RN(n6261), .Q( DMP_SHT2_EWSW[10]), .QN(n5458) ); DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n1489), .CK(clk), .RN(n6261), .Q( DMP_SFG[10]), .QN(n5355) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1488), .CK(clk), .RN(n6265), .Q( DMP_SHT1_EWSW[11]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1487), .CK(clk), .RN(n6265), .Q( DMP_SHT2_EWSW[11]), .QN(n5451) ); DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n1486), .CK(clk), .RN(n6265), .Q( DMP_SFG[11]), .QN(n5349) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1485), .CK(clk), .RN(n6264), .Q( DMP_SHT1_EWSW[12]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1484), .CK(clk), .RN(n6264), .Q( DMP_SHT2_EWSW[12]), .QN(n5454) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1482), .CK(clk), .RN(n6270), .Q( DMP_SHT1_EWSW[13]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1481), .CK(clk), .RN(n6269), .Q( DMP_SHT2_EWSW[13]), .QN(n5360) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n1480), .CK(clk), .RN(n6269), .Q( DMP_SFG[13]), .QN(n5467) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1479), .CK(clk), .RN(n6241), .Q( DMP_SHT1_EWSW[14]) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n1477), .CK(clk), .RN(n6241), .Q( DMP_SFG[14]), .QN(n5473) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1476), .CK(clk), .RN(n6241), .Q( DMP_SHT1_EWSW[15]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1475), .CK(clk), .RN(n6241), .Q( DMP_SHT2_EWSW[15]), .QN(n5395) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n1474), .CK(clk), .RN(n6241), .Q( DMP_SFG[15]), .QN(n5486) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1473), .CK(clk), .RN(n6242), .Q( DMP_SHT1_EWSW[16]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1472), .CK(clk), .RN(n6241), .Q( DMP_SHT2_EWSW[16]), .QN(n5394) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1470), .CK(clk), .RN(n6242), .Q( DMP_SHT1_EWSW[17]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1469), .CK(clk), .RN(n6242), .Q( DMP_SHT2_EWSW[17]), .QN(n5393) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n1468), .CK(clk), .RN(n6242), .Q( DMP_SFG[17]), .QN(n5466) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1467), .CK(clk), .RN(n6242), .Q( DMP_SHT1_EWSW[18]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1466), .CK(clk), .RN(n6242), .Q( DMP_SHT2_EWSW[18]), .QN(n5392) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n1465), .CK(clk), .RN(n6242), .Q( DMP_SFG[18]), .QN(n5477) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1464), .CK(clk), .RN(n6243), .Q( DMP_SHT1_EWSW[19]) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n1462), .CK(clk), .RN(n6243), .Q( DMP_SFG[19]), .QN(n5517) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1461), .CK(clk), .RN(n6243), .Q( DMP_SHT1_EWSW[20]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1460), .CK(clk), .RN(n6243), .Q( DMP_SHT2_EWSW[20]), .QN(n5390) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n1459), .CK(clk), .RN(n6243), .Q( DMP_SFG[20]), .QN(n5461) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1458), .CK(clk), .RN(n6244), .Q( DMP_SHT1_EWSW[21]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1457), .CK(clk), .RN(n6243), .Q( DMP_SHT2_EWSW[21]), .QN(n5389) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n1456), .CK(clk), .RN(n6243), .Q( DMP_SFG[21]), .QN(n5485) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1455), .CK(clk), .RN(n6244), .Q( DMP_SHT1_EWSW[22]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1454), .CK(clk), .RN(n6244), .Q( DMP_SHT2_EWSW[22]), .QN(n5388) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1452), .CK(clk), .RN(n6244), .Q( DMP_SHT1_EWSW[23]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1451), .CK(clk), .RN(n6244), .Q( DMP_SHT2_EWSW[23]), .QN(n5387) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_23_ ( .D(n1450), .CK(clk), .RN(n6244), .Q( DMP_SFG[23]), .QN(n5465) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1449), .CK(clk), .RN(n6245), .Q( DMP_SHT1_EWSW[24]) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_24_ ( .D(n1447), .CK(clk), .RN(n6245), .Q( DMP_SFG[24]), .QN(n5476) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1446), .CK(clk), .RN(n6245), .Q( DMP_SHT1_EWSW[25]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1445), .CK(clk), .RN(n6245), .Q( DMP_SHT2_EWSW[25]), .QN(n5385) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_25_ ( .D(n1444), .CK(clk), .RN(n6245), .Q( DMP_SFG[25]), .QN(n5464) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1443), .CK(clk), .RN(n6246), .Q( DMP_SHT1_EWSW[26]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1442), .CK(clk), .RN(n6245), .Q( DMP_SHT2_EWSW[26]), .QN(n5384) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1440), .CK(clk), .RN(n6246), .Q( DMP_SHT1_EWSW[27]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1439), .CK(clk), .RN(n6246), .Q( DMP_SHT2_EWSW[27]), .QN(n5383) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1437), .CK(clk), .RN(n6246), .Q( DMP_SHT1_EWSW[28]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1436), .CK(clk), .RN(n6246), .Q( DMP_SHT2_EWSW[28]), .QN(n5382) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_28_ ( .D(n1435), .CK(clk), .RN(n6246), .Q( DMP_SFG[28]), .QN(n5475) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1434), .CK(clk), .RN(n6247), .Q( DMP_SHT1_EWSW[29]) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_29_ ( .D(n1432), .CK(clk), .RN(n6247), .Q( DMP_SFG[29]), .QN(n5484) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1431), .CK(clk), .RN(n6247), .Q( DMP_SHT1_EWSW[30]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1430), .CK(clk), .RN(n6247), .Q( DMP_SHT2_EWSW[30]), .QN(n5380) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_30_ ( .D(n1429), .CK(clk), .RN(n6247), .Q( DMP_SFG[30]), .QN(n5471) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_31_ ( .D(n1428), .CK(clk), .RN(n6248), .Q( DMP_SHT1_EWSW[31]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_31_ ( .D(n1427), .CK(clk), .RN(n6247), .Q( DMP_SHT2_EWSW[31]), .QN(n5379) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_31_ ( .D(n1426), .CK(clk), .RN(n6247), .Q( DMP_SFG[31]), .QN(n5483) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_32_ ( .D(n1425), .CK(clk), .RN(n6248), .Q( DMP_SHT1_EWSW[32]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_32_ ( .D(n1424), .CK(clk), .RN(n6248), .Q( DMP_SHT2_EWSW[32]), .QN(n5378) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_32_ ( .D(n1423), .CK(clk), .RN(n6248), .Q( DMP_SFG[32]), .QN(n5482) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_33_ ( .D(n1422), .CK(clk), .RN(n6248), .Q( DMP_SHT1_EWSW[33]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_33_ ( .D(n1421), .CK(clk), .RN(n6248), .Q( DMP_SHT2_EWSW[33]), .QN(n5377) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_33_ ( .D(n1420), .CK(clk), .RN(n6248), .Q( DMP_SFG[33]), .QN(n5481) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_34_ ( .D(n1419), .CK(clk), .RN(n1881), .Q( DMP_SHT1_EWSW[34]) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_34_ ( .D(n1417), .CK(clk), .RN(n1880), .Q( DMP_SFG[34]), .QN(n5470) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_35_ ( .D(n1416), .CK(clk), .RN(n1882), .Q( DMP_SHT1_EWSW[35]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_35_ ( .D(n1415), .CK(clk), .RN(n1882), .Q( DMP_SHT2_EWSW[35]), .QN(n5375) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_35_ ( .D(n1414), .CK(clk), .RN(n1880), .Q( DMP_SFG[35]), .QN(n5515) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_36_ ( .D(n1413), .CK(clk), .RN(n2515), .Q( DMP_SHT1_EWSW[36]) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_36_ ( .D(n1411), .CK(clk), .RN(n1880), .Q( DMP_SFG[36]), .QN(n5463) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_37_ ( .D(n1410), .CK(clk), .RN(n5681), .Q( DMP_SHT1_EWSW[37]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_37_ ( .D(n1409), .CK(clk), .RN(n6233), .Q( DMP_SHT2_EWSW[37]), .QN(n5373) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_37_ ( .D(n1408), .CK(clk), .RN(n5681), .Q( DMP_SFG[37]), .QN(n5514) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_38_ ( .D(n1407), .CK(clk), .RN(n5685), .Q( DMP_SHT1_EWSW[38]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_38_ ( .D(n1406), .CK(clk), .RN(n5683), .Q( DMP_SHT2_EWSW[38]), .QN(n5372) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_38_ ( .D(n1405), .CK(clk), .RN(n2566), .Q( DMP_SFG[38]), .QN(n5469) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_39_ ( .D(n1404), .CK(clk), .RN(n2542), .Q( DMP_SHT1_EWSW[39]) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_40_ ( .D(n1401), .CK(clk), .RN(n5647), .Q( DMP_SHT1_EWSW[40]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_40_ ( .D(n1400), .CK(clk), .RN(n2541), .Q( DMP_SHT2_EWSW[40]), .QN(n6406) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_41_ ( .D(n1398), .CK(clk), .RN(n6250), .Q( DMP_SHT1_EWSW[41]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_41_ ( .D(n1397), .CK(clk), .RN(n2542), .Q( DMP_SHT2_EWSW[41]), .QN(n5337) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_41_ ( .D(n1396), .CK(clk), .RN(n6255), .Q( DMP_SFG[41]), .QN(n5398) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_42_ ( .D(n1395), .CK(clk), .RN(n6250), .Q( DMP_SHT1_EWSW[42]) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_42_ ( .D(n1393), .CK(clk), .RN(n6250), .Q( DMP_SFG[42]), .QN(n5462) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_43_ ( .D(n1392), .CK(clk), .RN(n6250), .Q( DMP_SHT1_EWSW[43]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_43_ ( .D(n1391), .CK(clk), .RN(n6250), .Q( DMP_SHT2_EWSW[43]), .QN(n5370) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_43_ ( .D(n1390), .CK(clk), .RN(n6250), .Q( DMP_SFG[43]), .QN(n5480) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_44_ ( .D(n1389), .CK(clk), .RN(n6251), .Q( DMP_SHT1_EWSW[44]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_44_ ( .D(n1388), .CK(clk), .RN(n6251), .Q( DMP_SHT2_EWSW[44]), .QN(n5369) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_44_ ( .D(n1387), .CK(clk), .RN(n6251), .Q( DMP_SFG[44]), .QN(n5474) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_45_ ( .D(n1386), .CK(clk), .RN(n6251), .Q( DMP_SHT1_EWSW[45]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_45_ ( .D(n1385), .CK(clk), .RN(n6251), .Q( DMP_SHT2_EWSW[45]), .QN(n5368) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_45_ ( .D(n1384), .CK(clk), .RN(n6251), .Q( DMP_SFG[45]), .QN(n5479) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_46_ ( .D(n1383), .CK(clk), .RN(n6252), .Q( DMP_SHT1_EWSW[46]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_46_ ( .D(n1382), .CK(clk), .RN(n6251), .Q( DMP_SHT2_EWSW[46]), .QN(n5367) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_46_ ( .D(n1381), .CK(clk), .RN(n6251), .Q( DMP_SFG[46]), .QN(n5468) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_47_ ( .D(n1380), .CK(clk), .RN(n6252), .Q( DMP_SHT1_EWSW[47]) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_47_ ( .D(n1378), .CK(clk), .RN(n6252), .Q( DMP_SFG[47]), .QN(n5513) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_48_ ( .D(n1377), .CK(clk), .RN(n6252), .Q( DMP_SHT1_EWSW[48]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_48_ ( .D(n1376), .CK(clk), .RN(n6252), .Q( DMP_SHT2_EWSW[48]), .QN(n5365) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_48_ ( .D(n1375), .CK(clk), .RN(n6252), .Q( DMP_SFG[48]), .QN(n5460) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_49_ ( .D(n1374), .CK(clk), .RN(n6287), .Q( DMP_SHT1_EWSW[49]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_49_ ( .D(n1373), .CK(clk), .RN(n6258), .Q( DMP_SHT2_EWSW[49]), .QN(n5459) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_50_ ( .D(n1371), .CK(clk), .RN(n2545), .Q( DMP_SHT1_EWSW[50]) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_51_ ( .D(n1368), .CK(clk), .RN(n5623), .Q( DMP_SHT1_EWSW[51]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_51_ ( .D(n1367), .CK(clk), .RN(n2512), .Q( DMP_SHT2_EWSW[51]), .QN(n5363) ); DFFRX2TS SHT2_STAGE_DMP_Q_reg_52_ ( .D(n1364), .CK(clk), .RN(n6271), .QN( n5501) ); DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1362), .CK(clk), .RN(n2515), .Q( DMP_exp_NRM_EW[0]) ); DFFRX2TS SHT2_STAGE_DMP_Q_reg_53_ ( .D(n1359), .CK(clk), .RN(n6271), .QN( n5500) ); DFFRX1TS SGF_STAGE_DMP_Q_reg_53_ ( .D(n1358), .CK(clk), .RN(n6271), .Q( DMP_SFG[53]), .QN(n5409) ); DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1357), .CK(clk), .RN(n6271), .Q( DMP_exp_NRM_EW[1]) ); DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1352), .CK(clk), .RN(n6272), .Q( DMP_exp_NRM_EW[2]) ); DFFRX2TS SHT2_STAGE_DMP_Q_reg_55_ ( .D(n1349), .CK(clk), .RN(n6272), .QN( n5498) ); DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1347), .CK(clk), .RN(n6272), .Q( DMP_exp_NRM_EW[3]) ); DFFRX2TS SHT2_STAGE_DMP_Q_reg_56_ ( .D(n1344), .CK(clk), .RN(n6273), .QN( n5497) ); DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1342), .CK(clk), .RN(n6273), .Q( DMP_exp_NRM_EW[4]) ); DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1341), .CK(clk), .RN(n6273), .Q( DMP_exp_NRM2_EW[4]) ); DFFRX2TS SHT1_STAGE_DMP_Q_reg_57_ ( .D(n1340), .CK(clk), .RN(n6274), .QN( n5402) ); DFFRX1TS SGF_STAGE_DMP_Q_reg_57_ ( .D(n1338), .CK(clk), .RN(n6273), .Q( DMP_SFG[57]), .QN(n5408) ); DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1337), .CK(clk), .RN(n6273), .Q( DMP_exp_NRM_EW[5]) ); DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1336), .CK(clk), .RN(n6273), .Q( DMP_exp_NRM2_EW[5]) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_58_ ( .D(n1335), .CK(clk), .RN(n6274), .Q( DMP_SHT1_EWSW[58]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_58_ ( .D(n1334), .CK(clk), .RN(n6274), .Q( DMP_SHT2_EWSW[58]), .QN(n5359) ); DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1332), .CK(clk), .RN(n6274), .Q( DMP_exp_NRM_EW[6]) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_59_ ( .D(n1330), .CK(clk), .RN(n6275), .Q( DMP_SHT1_EWSW[59]) ); DFFRX1TS SGF_STAGE_DMP_Q_reg_59_ ( .D(n1328), .CK(clk), .RN(n6275), .Q( DMP_SFG[59]), .QN(n5510) ); DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1327), .CK(clk), .RN(n6275), .Q( DMP_exp_NRM_EW[7]) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_60_ ( .D(n1325), .CK(clk), .RN(n6275), .Q( DMP_SHT1_EWSW[60]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_60_ ( .D(n1324), .CK(clk), .RN(n6275), .Q( DMP_SHT2_EWSW[60]), .QN(n5357) ); DFFRX1TS SGF_STAGE_DMP_Q_reg_60_ ( .D(n1323), .CK(clk), .RN(n6275), .Q( DMP_SFG[60]), .QN(n5509) ); DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_8_ ( .D(n1322), .CK(clk), .RN(n6275), .Q( DMP_exp_NRM_EW[8]) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_61_ ( .D(n1320), .CK(clk), .RN(n2566), .Q( DMP_SHT1_EWSW[61]) ); DFFRX1TS SHT2_STAGE_DMP_Q_reg_61_ ( .D(n1319), .CK(clk), .RN(n6256), .Q( DMP_SHT2_EWSW[61]), .QN(n5356) ); DFFRX1TS SGF_STAGE_DMP_Q_reg_61_ ( .D(n1318), .CK(clk), .RN(n2543), .Q( DMP_SFG[61]), .QN(n5508) ); DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_9_ ( .D(n1317), .CK(clk), .RN(n2538), .Q( DMP_exp_NRM_EW[9]) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_62_ ( .D(n1315), .CK(clk), .RN(n2511), .Q( DMP_SHT1_EWSW[62]) ); DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_10_ ( .D(n1312), .CK(clk), .RN(n2512), .Q( DMP_exp_NRM_EW[10]) ); DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1309), .CK(clk), .RN(n2545), .Q( DmP_mant_SHT1_SW[0]) ); DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1307), .CK(clk), .RN(n2544), .Q( DmP_mant_SHT1_SW[1]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_2_ ( .D(n1306), .CK(clk), .RN(n2543), .Q( DmP_EXP_EWSW[2]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_4_ ( .D(n1302), .CK(clk), .RN(n2532), .Q( DmP_EXP_EWSW[4]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_6_ ( .D(n1298), .CK(clk), .RN(n5668), .Q( DmP_EXP_EWSW[6]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_7_ ( .D(n1296), .CK(clk), .RN(n2532), .Q( DmP_EXP_EWSW[7]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_10_ ( .D(n1290), .CK(clk), .RN(n2532), .Q( DmP_EXP_EWSW[10]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_15_ ( .D(n1280), .CK(clk), .RN(n6260), .Q( DmP_EXP_EWSW[15]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_16_ ( .D(n1278), .CK(clk), .RN(n5671), .Q( DmP_EXP_EWSW[16]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_17_ ( .D(n1276), .CK(clk), .RN(n2540), .Q( DmP_EXP_EWSW[17]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_21_ ( .D(n1268), .CK(clk), .RN(n6264), .Q( DmP_EXP_EWSW[21]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_22_ ( .D(n1266), .CK(clk), .RN(n2566), .Q( DmP_EXP_EWSW[22]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n1262), .CK(clk), .RN(n6263), .Q( DmP_EXP_EWSW[24]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_28_ ( .D(n1254), .CK(clk), .RN(n6232), .Q( DmP_EXP_EWSW[28]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_30_ ( .D(n1250), .CK(clk), .RN(n2566), .Q( DmP_EXP_EWSW[30]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_31_ ( .D(n1248), .CK(clk), .RN(n5683), .Q( DmP_EXP_EWSW[31]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_32_ ( .D(n1246), .CK(clk), .RN(n2566), .Q( DmP_EXP_EWSW[32]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_33_ ( .D(n1244), .CK(clk), .RN(n2567), .Q( DmP_EXP_EWSW[33]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_35_ ( .D(n1240), .CK(clk), .RN(n5629), .Q( DmP_EXP_EWSW[35]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_36_ ( .D(n1238), .CK(clk), .RN(n5683), .Q( DmP_EXP_EWSW[36]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_37_ ( .D(n1236), .CK(clk), .RN(n5683), .Q( DmP_EXP_EWSW[37]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_39_ ( .D(n1232), .CK(clk), .RN(n6261), .Q( DmP_EXP_EWSW[39]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_41_ ( .D(n1228), .CK(clk), .RN(n5675), .Q( DmP_EXP_EWSW[41]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_42_ ( .D(n1226), .CK(clk), .RN(n5658), .Q( DmP_EXP_EWSW[42]) ); DFFRX1TS EXP_STAGE_DmP_Q_reg_46_ ( .D(n1218), .CK(clk), .RN(n5668), .Q( DmP_EXP_EWSW[46]) ); DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n1198), .CK(clk), .RN(n5644), .Q( ZERO_FLAG_SHT1) ); DFFRX1TS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n1197), .CK(clk), .RN(n5670), .Q( ZERO_FLAG_SHT2), .QN(n6464) ); DFFRX1TS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1194), .CK(clk), .RN(n6262), .Q(ZERO_FLAG_SHT1SHT2) ); DFFRX1TS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1191), .CK(clk), .RN(n2515), .Q( OP_FLAG_SHT2) ); DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1189), .CK(clk), .RN(n6253), .Q( SIGN_FLAG_SHT1) ); DFFRX1TS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1186), .CK(clk), .RN(n6253), .Q( SIGN_FLAG_NRM) ); DFFRX1TS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1185), .CK(clk), .RN(n5633), .Q(SIGN_FLAG_SHT1SHT2) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1142), .CK(clk), .RN(n5633), .Q( Raw_mant_NRM_SWR[14]), .QN(n5570) ); DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1140), .CK(clk), .RN(n6256), .Q( DmP_mant_SFG_SWR[1]) ); DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1137), .CK(clk), .RN(n6258), .Q( DmP_mant_SFG_SWR[0]) ); DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_46_ ( .D(n1024), .CK(clk), .RN(n2511), .Q( DmP_mant_SFG_SWR[46]), .QN(n5559) ); DFFSX1TS R_15 ( .D(n6363), .CK(clk), .SN(n5645), .Q(n6195) ); DFFSX1TS R_35 ( .D(n6325), .CK(clk), .SN(n2533), .Q(n6194) ); DFFSX1TS R_47 ( .D(n6388), .CK(clk), .SN(n5638), .Q(n6193) ); DFFSX1TS R_75 ( .D(n6336), .CK(clk), .SN(n5661), .Q(n6190) ); DFFSX1TS R_88 ( .D(n6402), .CK(clk), .SN(n5624), .Q(n6189) ); DFFSX1TS R_91 ( .D(n6375), .CK(clk), .SN(n5638), .Q(n6188) ); DFFSX1TS R_110 ( .D(n6296), .CK(clk), .SN(n2541), .Q(n6183) ); DFFSX1TS R_134 ( .D(n6359), .CK(clk), .SN(n5646), .Q(n6172) ); DFFSX1TS R_138 ( .D(n6300), .CK(clk), .SN(n2567), .Q(n6171) ); DFFSX1TS R_162 ( .D(n6398), .CK(clk), .SN(n5630), .Q(n6164) ); DFFSX1TS R_164 ( .D(n6397), .CK(clk), .SN(n5630), .Q(n6163) ); DFFSX1TS R_172 ( .D(n6365), .CK(clk), .SN(n5645), .Q(n6162) ); DFFSX1TS R_189 ( .D(n6380), .CK(clk), .SN(n5638), .Q(n6159) ); DFFSX1TS R_203 ( .D(n6367), .CK(clk), .SN(n5646), .Q(n6157) ); DFFSX1TS R_211 ( .D(n6306), .CK(clk), .SN(n5681), .Q(n6156) ); DFFSX1TS R_234 ( .D(n6395), .CK(clk), .SN(n5634), .Q(n6150) ); DFFSX1TS R_235 ( .D(n6394), .CK(clk), .SN(n5634), .Q(n6149) ); DFFSX1TS R_236 ( .D(n6393), .CK(clk), .SN(n5634), .Q(n6148) ); DFFSX1TS R_247 ( .D(n6384), .CK(clk), .SN(n5638), .Q(n6143) ); DFFSX2TS R_249 ( .D(n6382), .CK(clk), .SN(n5639), .Q(n6141) ); DFFSX1TS R_254 ( .D(n6349), .CK(clk), .SN(n5654), .Q(n6138) ); DFFSX2TS R_281 ( .D(n2506), .CK(clk), .SN(n6254), .Q(n6124) ); DFFSX2TS R_289 ( .D(n1906), .CK(clk), .SN(n5646), .Q(n6120) ); DFFSX1TS R_307 ( .D(n6329), .CK(clk), .SN(n2545), .Q(n6108) ); DFFSX1TS R_308 ( .D(n6328), .CK(clk), .SN(n2544), .Q(n6107) ); DFFSX1TS R_309 ( .D(n6327), .CK(clk), .SN(n2545), .Q(n6106) ); DFFRX2TS R_319 ( .D(n6392), .CK(clk), .RN(n5653), .Q(n6101) ); DFFRX1TS R_508 ( .D(n6339), .CK(clk), .RN(n5661), .Q(n5965) ); DFFSX2TS R_517 ( .D(n2497), .CK(clk), .SN(n5679), .Q(n5958) ); DFFSX2TS R_525 ( .D(n6203), .CK(clk), .SN(n5649), .QN(n2225) ); DFFSX2TS R_537 ( .D(n6204), .CK(clk), .SN(n5665), .Q(n5951) ); DFFRX2TS R_550 ( .D(DmP_mant_SHT1_SW[20]), .CK(clk), .RN(n5634), .Q(n5945) ); DFFSX2TS R_555 ( .D(n6200), .CK(clk), .SN(n5656), .QN(n2231) ); DFFSX2TS R_597 ( .D(n6223), .CK(clk), .SN(n5626), .Q(n5914) ); DFFSX2TS R_584 ( .D(DmP_mant_SHT1_SW[28]), .CK(clk), .SN(n5627), .Q(n5927) ); DFFRX1TS R_585 ( .D(n6305), .CK(clk), .RN(n5624), .Q(n5926) ); DFFSX2TS R_586 ( .D(DmP_mant_SHT1_SW[39]), .CK(clk), .SN(n5627), .Q(n5925) ); DFFSX2TS R_588 ( .D(DmP_mant_SHT1_SW[47]), .CK(clk), .SN(n5627), .Q(n5923) ); DFFSX2TS R_590 ( .D(DmP_mant_SHT1_SW[45]), .CK(clk), .SN(n5627), .Q(n5921) ); DFFRX1TS R_591 ( .D(n6324), .CK(clk), .RN(n5624), .Q(n5920) ); DFFRX1TS R_593 ( .D(n6319), .CK(clk), .RN(n5624), .Q(n5918) ); DFFSX2TS R_594 ( .D(DmP_mant_SHT1_SW[41]), .CK(clk), .SN(n5627), .Q(n5917) ); DFFSX2TS R_596 ( .D(DmP_mant_SHT1_SW[35]), .CK(clk), .SN(n5626), .Q(n5915) ); DFFSX2TS R_599 ( .D(DmP_mant_SHT1_SW[24]), .CK(clk), .SN(n5626), .Q(n5912) ); DFFSX2TS R_522_RW_0 ( .D(DmP_mant_SHT1_SW[22]), .CK(clk), .SN(n5626), .Q( n5957) ); DFFRX2TS R_631 ( .D(n6211), .CK(clk), .RN(n5660), .Q(n5892) ); DFFSX2TS R_645 ( .D(n6200), .CK(clk), .SN(n5657), .Q(n5882) ); DFFSX2TS R_659 ( .D(n6223), .CK(clk), .SN(n5627), .Q(n5873) ); DFFSX2TS R_657 ( .D(n2501), .CK(clk), .SN(n5626), .Q(n5874) ); DFFRX2TS R_662 ( .D(n6413), .CK(clk), .RN(n6236), .Q(n5870) ); DFFSX2TS R_692 ( .D(n2500), .CK(clk), .SN(n5651), .Q(n5853) ); DFFRX2TS R_701 ( .D(Raw_mant_NRM_SWR[28]), .CK(clk), .RN(n5676), .Q(n5848) ); DFFRX1TS R_708 ( .D(n2441), .CK(clk), .RN(n2532), .Q(n5843) ); DFFSX2TS R_794 ( .D(n6201), .CK(clk), .SN(n5643), .Q(n5795) ); DFFSX2TS R_835 ( .D(n2497), .CK(clk), .SN(n5681), .Q(n5771) ); DFFSX2TS R_837 ( .D(n2506), .CK(clk), .SN(n5643), .Q(n5770) ); DFFRX2TS R_842 ( .D(n6455), .CK(clk), .RN(n2540), .Q(n5768) ); DFFRX2TS R_846 ( .D(n6457), .CK(clk), .RN(n5650), .Q(n5766) ); DFFSX2TS R_858 ( .D(n2556), .CK(clk), .SN(n5680), .Q(n5757) ); DFFSX2TS R_864 ( .D(n6203), .CK(clk), .SN(n2541), .Q(n5754) ); DFFSX2TS R_883 ( .D(n2506), .CK(clk), .SN(n5651), .Q(n5743) ); DFFRX2TS R_906 ( .D(n6439), .CK(clk), .RN(n2544), .Q(n5731) ); DFFSX2TS R_931 ( .D(n2506), .CK(clk), .SN(n6288), .Q(n5712) ); DFFRX2TS R_936 ( .D(n6441), .CK(clk), .RN(n2545), .Q(n5710) ); DFFSX2TS R_939 ( .D(n2496), .CK(clk), .SN(n5635), .Q(n5709) ); DFFSX2TS R_947 ( .D(n6204), .CK(clk), .SN(n5667), .Q(n5705) ); DFFRXLTS SGF_STAGE_DMP_Q_reg_3_ ( .D(n1510), .CK(clk), .RN(n5652), .Q( DMP_SFG[3]), .QN(n5512) ); DFFRXLTS SGF_STAGE_DMP_Q_reg_0_ ( .D(n1519), .CK(clk), .RN(n6260), .Q( DMP_SFG[0]), .QN(n5511) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_48_ ( .D(n1067), .CK(clk), .RN(n2520), .Q( final_result_ieee[48]), .QN(n5506) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1107), .CK(clk), .RN(n6234), .Q( final_result_ieee[27]), .QN(n5537) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1103), .CK(clk), .RN(n6286), .Q( final_result_ieee[22]), .QN(n5532) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1102), .CK(clk), .RN(n6234), .Q( final_result_ieee[28]), .QN(n5538) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1098), .CK(clk), .RN(n6255), .Q( final_result_ieee[26]), .QN(n5536) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1095), .CK(clk), .RN(n6235), .Q( final_result_ieee[8]), .QN(n5529) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_42_ ( .D(n1094), .CK(clk), .RN(n2521), .Q( final_result_ieee[42]), .QN(n5541) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_43_ ( .D(n1090), .CK(clk), .RN(n2520), .Q( final_result_ieee[43]), .QN(n5542) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1086), .CK(clk), .RN(n6235), .Q( final_result_ieee[9]), .QN(n5530) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_41_ ( .D(n1085), .CK(clk), .RN(n2521), .Q( final_result_ieee[41]), .QN(n5540) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1080), .CK(clk), .RN(n6235), .Q( final_result_ieee[6]), .QN(n5527) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_44_ ( .D(n1079), .CK(clk), .RN(n2520), .Q( final_result_ieee[44]), .QN(n5543) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1078), .CK(clk), .RN(n6235), .Q( final_result_ieee[5]), .QN(n5526) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1076), .CK(clk), .RN(n6235), .Q( final_result_ieee[4]), .QN(n5525) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_46_ ( .D(n1075), .CK(clk), .RN(n2520), .Q( final_result_ieee[46]), .QN(n5544) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1066), .CK(clk), .RN(n6235), .Q( final_result_ieee[1]), .QN(n5522) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1065), .CK(clk), .RN(n6235), .Q( final_result_ieee[3]), .QN(n5524) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_47_ ( .D(n1060), .CK(clk), .RN(n2521), .Q( final_result_ieee[47]), .QN(n5545) ); DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n1523), .CK(clk), .RN(n5636), .Q( ZERO_FLAG_EXP), .QN(n5401) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_62_ ( .D(n1588), .CK(clk), .RN(n6256), .Q( final_result_ieee[62]), .QN(n5503) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1059), .CK(clk), .RN(n6235), .Q( final_result_ieee[0]), .QN(n5504) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_50_ ( .D(n1057), .CK(clk), .RN(n6289), .Q( final_result_ieee[50]), .QN(n5505) ); DFFSX2TS R_741 ( .D(n6433), .CK(clk), .SN(n6288), .Q(n5822) ); DFFSX2TS R_745 ( .D(n6431), .CK(clk), .SN(n5622), .Q(n5820) ); DFFSX2TS R_751 ( .D(n6438), .CK(clk), .SN(n5618), .Q(n5816) ); DFFSX2TS R_755 ( .D(n6442), .CK(clk), .SN(n5618), .Q(n5814) ); DFFSX2TS R_759 ( .D(n6460), .CK(clk), .SN(n5620), .Q(n5812) ); DFFSX2TS R_769 ( .D(n6416), .CK(clk), .SN(n5622), .Q(n5807) ); DFFSX2TS R_775 ( .D(n6420), .CK(clk), .SN(n6288), .Q(n5804) ); DFFSX2TS R_789 ( .D(n6435), .CK(clk), .SN(n6232), .Q(n5798) ); DFFSX2TS R_793 ( .D(n6458), .CK(clk), .SN(n5620), .Q(n5796) ); DFFSX2TS R_803 ( .D(n6463), .CK(clk), .SN(n2521), .Q(n5791) ); DFFSX2TS R_807 ( .D(n6456), .CK(clk), .SN(n5621), .Q(n5789) ); DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1200), .CK(clk), .RN(n2544), .Q( underflow_flag) ); DFFRXLTS R_729 ( .D(n6449), .CK(clk), .RN(n5660), .Q(n5830) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_52_ ( .D(n1598), .CK(clk), .RN(n6289), .Q( final_result_ieee[52]) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_54_ ( .D(n1596), .CK(clk), .RN(n4465), .Q( final_result_ieee[54]) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_56_ ( .D(n1594), .CK(clk), .RN(n5628), .Q( final_result_ieee[56]) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_58_ ( .D(n1592), .CK(clk), .RN(n5632), .Q( final_result_ieee[58]) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_60_ ( .D(n1590), .CK(clk), .RN(n5632), .Q( final_result_ieee[60]) ); DFFSX1TS R_150 ( .D(n6425), .CK(clk), .SN(n5649), .Q(n6168) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_63_ ( .D(n1184), .CK(clk), .RN(n5628), .Q( final_result_ieee[63]) ); DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1193), .CK(clk), .RN(n6292), .Q( zero_flag) ); DFFSX1TS R_115 ( .D(n6428), .CK(clk), .SN(n6290), .Q(n6181) ); DFFSX1TS R_118 ( .D(n6423), .CK(clk), .SN(n4463), .Q(n6179) ); DFFRXLTS EXP_STAGE_DmP_Q_reg_57_ ( .D(n1201), .CK(clk), .RN(n6270), .Q( DmP_EXP_EWSW[57]), .QN(n5496) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_53_ ( .D(n1597), .CK(clk), .RN(n6273), .Q( final_result_ieee[53]) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_55_ ( .D(n1595), .CK(clk), .RN(n4465), .Q( final_result_ieee[55]) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_57_ ( .D(n1593), .CK(clk), .RN(n5628), .Q( final_result_ieee[57]) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_59_ ( .D(n1591), .CK(clk), .RN(n2515), .Q( final_result_ieee[59]) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_61_ ( .D(n1589), .CK(clk), .RN(n6236), .Q( final_result_ieee[61]) ); DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1301), .CK(clk), .RN(n2532), .Q( DmP_mant_SHT1_SW[4]), .QN(n5595) ); DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1299), .CK(clk), .RN(n5668), .Q( DmP_mant_SHT1_SW[5]) ); DFFSX2TS R_351 ( .D(n6225), .CK(clk), .SN(n5655), .Q(n6075) ); DFFSX2TS R_382 ( .D(n2556), .CK(clk), .SN(n5654), .Q(n6053) ); DFFSX1TS R_326 ( .D(n6302), .CK(clk), .SN(n5681), .Q(n6094) ); DFFSX1TS R_665 ( .D(n6389), .CK(clk), .SN(n5636), .Q(n5867) ); DFFSX1TS R_325 ( .D(n6303), .CK(clk), .SN(n5681), .Q(n6095) ); DFFSX1TS R_664 ( .D(n6390), .CK(clk), .SN(n5636), .Q(n5868) ); DFFSX1TS R_324 ( .D(n6304), .CK(clk), .SN(n5681), .Q(n6096) ); DFFSX1TS R_663 ( .D(n6391), .CK(clk), .SN(n5635), .Q(n5869) ); DFFSX2TS R_477 ( .D(n2564), .CK(clk), .SN(n2533), .Q(n5985) ); DFFSX2TS R_426 ( .D(n5600), .CK(clk), .SN(n5640), .Q(n6022) ); DFFSX2TS R_438 ( .D(n5587), .CK(clk), .SN(n5641), .Q(n6011) ); DFFSX2TS R_450 ( .D(n5586), .CK(clk), .SN(n6257), .Q(n6005) ); DFFSX2TS R_478 ( .D(n5597), .CK(clk), .SN(n2533), .Q(n5984) ); DFFSX2TS R_544 ( .D(n1915), .CK(clk), .SN(n5649), .Q(n5949) ); DFFSX2TS R_436 ( .D(n5422), .CK(clk), .SN(n5641), .Q(n6013) ); DFFRXLTS R_316 ( .D(n6409), .CK(clk), .RN(n5653), .Q(n6103) ); DFFSX1TS R_577 ( .D(n6226), .CK(clk), .SN(n5632), .Q(n5932) ); DFFSX2TS R_466 ( .D(n5575), .CK(clk), .SN(n5656), .QN(n2222) ); DFFSX2TS R_447 ( .D(n2346), .CK(clk), .SN(n6257), .QN(n2220) ); DFFSX2TS R_421 ( .D(n2564), .CK(clk), .SN(n5663), .Q(n6026) ); DFFSX2TS R_441 ( .D(n6223), .CK(clk), .SN(n5672), .QN(n2226) ); DFFSX2TS R_445 ( .D(n2499), .CK(clk), .SN(n5635), .Q(n6008) ); DFFSX2TS R_457 ( .D(n6224), .CK(clk), .SN(n5673), .Q(n5999) ); DFFSX2TS R_469 ( .D(n2564), .CK(clk), .SN(n5635), .Q(n5992) ); DFFSX2TS R_473 ( .D(n2498), .CK(clk), .SN(n5682), .Q(n5988) ); DFFSX2TS R_481 ( .D(n6223), .CK(clk), .SN(n5677), .Q(n5982) ); DFFSX2TS R_485 ( .D(n6223), .CK(clk), .SN(n5641), .Q(n5978) ); DFFSX2TS R_489 ( .D(n2564), .CK(clk), .SN(n5664), .Q(n5975) ); DFFSX2TS R_369 ( .D(n6225), .CK(clk), .SN(n2545), .Q(n6063) ); DFFSX2TS R_760 ( .D(n2287), .CK(clk), .SN(n2533), .Q(n5811) ); DFFSX2TS R_422 ( .D(n5617), .CK(clk), .SN(n5663), .Q(n6025) ); DFFSX2TS R_446 ( .D(n5611), .CK(clk), .SN(n5635), .Q(n6007) ); DFFSX2TS R_454 ( .D(n5582), .CK(clk), .SN(n5648), .Q(n6002) ); DFFSX2TS R_458 ( .D(n5601), .CK(clk), .SN(n5673), .Q(n5998) ); DFFSX2TS R_462 ( .D(n5578), .CK(clk), .SN(n5649), .Q(n5994) ); DFFSX2TS R_470 ( .D(n5594), .CK(clk), .SN(n5635), .Q(n5991) ); DFFSX2TS R_482 ( .D(n5576), .CK(clk), .SN(n5677), .Q(n5981) ); DFFSX2TS R_486 ( .D(n5414), .CK(clk), .SN(n5641), .Q(n5977) ); DFFSX2TS R_490 ( .D(n5413), .CK(clk), .SN(n5664), .Q(n5974) ); DFFSX2TS R_499 ( .D(n5584), .CK(clk), .SN(n5678), .Q(n5969) ); DFFSX2TS R_562 ( .D(n2523), .CK(clk), .SN(n5632), .Q(n5942) ); DFFSX2TS R_412 ( .D(n5570), .CK(clk), .SN(n5663), .Q(n6032) ); DFFSX2TS R_444 ( .D(n5573), .CK(clk), .SN(n5635), .Q(n6009) ); DFFSX2TS R_460 ( .D(n1857), .CK(clk), .SN(n5649), .Q(n5996) ); DFFSX2TS R_480 ( .D(n3298), .CK(clk), .SN(n5677), .QN(n2408) ); DFFSX2TS R_484 ( .D(n5491), .CK(clk), .SN(n5641), .Q(n5979) ); DFFSX2TS R_488 ( .D(n5439), .CK(clk), .SN(n5664), .QN(n2415) ); DFFSX2TS R_497 ( .D(n5427), .CK(clk), .SN(n5678), .QN(n2219) ); DFFSX2TS R_511 ( .D(n1635), .CK(clk), .SN(n5629), .Q(n5962) ); DFFSX2TS R_515 ( .D(n1626), .CK(clk), .SN(n5649), .Q(n5959) ); DFFSX2TS R_713 ( .D(n1627), .CK(clk), .SN(n5674), .Q(n5839) ); DFFSX2TS R_455 ( .D(n5342), .CK(clk), .SN(n5672), .Q(n6001) ); DFFSX2TS R_671 ( .D(n2306), .CK(clk), .SN(n5680), .Q(n5863) ); DFFSX2TS R_711 ( .D(n2306), .CK(clk), .SN(n5674), .Q(n5841) ); DFFSX2TS R_619 ( .D(n6226), .CK(clk), .SN(n5674), .Q(n5898) ); DFFSX2TS R_668 ( .D(n6225), .CK(clk), .SN(n5657), .Q(n5865) ); DFFSX2TS R_553 ( .D(n2528), .CK(clk), .SN(n5625), .Q(n5943) ); DFFSX2TS R_628 ( .D(n2498), .CK(clk), .SN(n5650), .Q(n5894) ); DFFSX2TS R_635 ( .D(n2499), .CK(clk), .SN(n5656), .Q(n5890) ); DFFSX2TS R_639 ( .D(n2498), .CK(clk), .SN(n5627), .Q(n5887) ); DFFSX2TS R_655 ( .D(n6224), .CK(clk), .SN(n5665), .Q(n5876) ); DFFSX2TS R_839 ( .D(n2523), .CK(clk), .SN(n5643), .Q(n5769) ); DFFSX2TS R_849 ( .D(n2523), .CK(clk), .SN(n5680), .Q(n5763) ); DFFSX2TS R_866 ( .D(n2523), .CK(clk), .SN(n2542), .Q(n5753) ); DFFSX2TS R_881 ( .D(n1915), .CK(clk), .SN(n5675), .QN(n1842) ); DFFSX2TS R_901 ( .D(n2523), .CK(clk), .SN(n5685), .Q(n5733) ); DFFSX2TS R_941 ( .D(n6212), .CK(clk), .SN(n6286), .Q(n5708) ); DFFSX2TS R_623 ( .D(n6200), .CK(clk), .SN(n5650), .Q(n5896) ); DFFSX2TS R_889 ( .D(n6200), .CK(clk), .SN(n4463), .Q(n5739) ); DFFSX2TS R_897 ( .D(n2496), .CK(clk), .SN(n5639), .Q(n5735) ); DFFSX2TS R_921 ( .D(n6201), .CK(clk), .SN(n5636), .Q(n5719) ); DFFSX2TS R_945 ( .D(n6201), .CK(clk), .SN(n5677), .Q(n5706) ); DFFSX2TS R_359 ( .D(n6224), .CK(clk), .SN(n5630), .Q(n6069) ); DFFSX2TS R_363 ( .D(n6223), .CK(clk), .SN(n5647), .QN(n2229) ); DFFSX2TS R_524 ( .D(n5445), .CK(clk), .SN(n5625), .QN(n2413) ); DFFSX2TS R_536 ( .D(n5440), .CK(clk), .SN(n5664), .QN(n2411) ); DFFSX2TS R_598 ( .D(n5608), .CK(clk), .SN(n5626), .Q(n5913) ); DFFSX2TS R_601 ( .D(n5590), .CK(clk), .SN(n5626), .Q(n5910) ); DFFSX2TS R_629 ( .D(n2974), .CK(clk), .SN(n5650), .Q(n5893) ); DFFSX2TS R_636 ( .D(n2971), .CK(clk), .SN(n5657), .Q(n5889) ); DFFSX2TS R_640 ( .D(n2976), .CK(clk), .SN(n5627), .Q(n5886) ); DFFSX2TS R_644 ( .D(n5598), .CK(clk), .SN(n5665), .Q(n5883) ); DFFSX2TS R_648 ( .D(n5607), .CK(clk), .SN(n5657), .Q(n5880) ); DFFSX2TS R_656 ( .D(n5603), .CK(clk), .SN(n5665), .Q(n5875) ); DFFSX2TS R_660 ( .D(n5606), .CK(clk), .SN(n5624), .Q(n5872) ); DFFSX2TS R_894 ( .D(n2301), .CK(clk), .SN(n5666), .QN(n2409) ); DFFSX2TS R_500 ( .D(n6226), .CK(clk), .SN(n5631), .Q(n5968) ); DFFSX2TS R_895 ( .D(n6204), .CK(clk), .SN(n5640), .Q(n5736) ); DFFSX2TS R_919 ( .D(n2500), .CK(clk), .SN(n6233), .Q(n5721) ); DFFSX2TS R_958 ( .D(n2506), .CK(clk), .SN(n5678), .Q(n5698) ); DFFSX2TS R_346 ( .D(n5615), .CK(clk), .SN(n5678), .Q(n6078) ); DFFSX2TS R_350 ( .D(n2969), .CK(clk), .SN(n2542), .Q(n6076) ); DFFSX2TS R_360 ( .D(n5595), .CK(clk), .SN(n5630), .Q(n6068) ); DFFSX2TS R_364 ( .D(n5593), .CK(clk), .SN(n5648), .QN(n2230) ); DFFSX2TS R_381 ( .D(n5605), .CK(clk), .SN(n5669), .Q(n6054) ); DFFSX2TS R_387 ( .D(n5589), .CK(clk), .SN(n5648), .Q(n6050) ); DFFSX2TS R_391 ( .D(n5609), .CK(clk), .SN(n5664), .QN(n2414) ); DFFSX2TS R_402 ( .D(n5613), .CK(clk), .SN(n5648), .Q(n6040) ); DFFSX2TS R_406 ( .D(n5416), .CK(clk), .SN(n5640), .Q(n6036) ); DFFSX2TS R_410 ( .D(n5592), .CK(clk), .SN(n5672), .Q(n6034) ); DFFSX2TS R_430 ( .D(n5616), .CK(clk), .SN(n5655), .Q(n6019) ); DFFSX2TS R_434 ( .D(n5591), .CK(clk), .SN(n5631), .Q(n6015) ); DFFSX2TS R_357 ( .D(n3367), .CK(clk), .SN(n5631), .Q(n6071) ); DFFSX2TS R_431 ( .D(n5432), .CK(clk), .SN(n5631), .Q(n6018) ); DFFSX2TS R_826 ( .D(n6227), .CK(clk), .SN(n5643), .Q(n5777) ); DFFSX2TS R_851 ( .D(n2556), .CK(clk), .SN(n2541), .Q(n5762) ); DFFSX2TS R_955 ( .D(n2501), .CK(clk), .SN(n5658), .Q(n5700) ); DFFRXLTS R_725 ( .D(n6399), .CK(clk), .RN(n5628), .Q(n5831) ); DFFSX1TS R_493 ( .D(n6297), .CK(clk), .SN(n2568), .Q(n5971) ); DFFSX2TS R_404 ( .D(n2015), .CK(clk), .SN(n5640), .Q(n6038) ); DFFRXLTS R_920 ( .D(DmP_mant_SHT1_SW[7]), .CK(clk), .RN(n5633), .Q(n5720) ); DFFSX2TS R_746 ( .D(n2553), .CK(clk), .SN(n5636), .Q(n5819) ); DFFSX2TS R_736 ( .D(n6412), .CK(clk), .SN(n5651), .Q(n5825) ); DFFSX2TS R_870 ( .D(n6212), .CK(clk), .SN(n5636), .Q(n5751) ); DFFSX2TS R_368 ( .D(n5585), .CK(clk), .SN(n2545), .Q(n6064) ); DFFSX2TS R_418 ( .D(n6224), .CK(clk), .SN(n5655), .Q(n6027) ); DFFSX2TS R_190 ( .D(n6212), .CK(clk), .SN(n5662), .Q(n6158) ); DFFSX2TS R_278 ( .D(n6213), .CK(clk), .SN(n5625), .Q(n6126) ); DFFSX2TS R_735 ( .D(n6353), .CK(clk), .SN(n5651), .Q(n5826) ); DFFSX2TS R_565 ( .D(n2497), .CK(clk), .SN(n5673), .Q(n5940) ); DFFSX2TS R_970 ( .D(n1628), .CK(clk), .SN(n5667), .Q(n5691) ); DFFSX2TS R_974 ( .D(n6200), .CK(clk), .SN(n5658), .Q(n5688) ); DFFSX2TS R_416 ( .D(n5423), .CK(clk), .SN(n5655), .QN(n2412) ); DFFSX2TS R_568 ( .D(n5604), .CK(clk), .SN(n5679), .Q(n5938) ); DFFSX2TS R_572 ( .D(n5577), .CK(clk), .SN(n5673), .Q(n5935) ); DFFSX2TS R_911 ( .D(n6203), .CK(clk), .SN(n6290), .Q(n5727) ); DFFSX2TS R_332 ( .D(n5599), .CK(clk), .SN(n5630), .QN(n2407) ); DFFSX2TS R_355 ( .D(n2498), .CK(clk), .SN(n5684), .Q(n6073) ); DFFSX2TS R_417 ( .D(n5602), .CK(clk), .SN(n5655), .Q(n6028) ); DFFSX2TS R_569 ( .D(n6410), .CK(clk), .SN(n5679), .Q(n5937) ); DFFSX2TS R_573 ( .D(n6411), .CK(clk), .SN(n5673), .Q(n5934) ); DFFSX2TS R_365 ( .D(n5433), .CK(clk), .SN(n2544), .Q(n6067) ); DFFSX2TS R_567 ( .D(n2499), .CK(clk), .SN(n5679), .Q(n5939) ); DFFSX2TS R_808 ( .D(Raw_mant_NRM_SWR[19]), .CK(clk), .SN(n5685), .Q(n5788) ); DFFSX2TS R_968 ( .D(n2553), .CK(clk), .SN(n5661), .Q(n5693) ); DFFSX1TS R_492 ( .D(n6298), .CK(clk), .SN(n2568), .Q(n5972) ); DFFSX1TS R_732 ( .D(n6225), .CK(clk), .SN(n5685), .Q(n5828) ); DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1128), .CK(clk), .RN(n5628), .Q( Raw_mant_NRM_SWR[3]), .QN(n5339) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_40_ ( .D(n1158), .CK(clk), .RN(n6269), .Q( Raw_mant_NRM_SWR[40]), .QN(n6207) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_45_ ( .D(n1153), .CK(clk), .RN(n6268), .Q( Raw_mant_NRM_SWR[45]), .QN(n5487) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1793), .CK(clk), .RN(n6280), .Q(intDX_EWSW[1]), .QN(n3328) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1792), .CK(clk), .RN(n6280), .Q(intDX_EWSW[2]), .QN(n3327) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1721), .CK(clk), .RN(n6276), .Q(intDY_EWSW[7]), .QN(n2478) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1717), .CK(clk), .RN(n6276), .Q(intDY_EWSW[11]), .QN(n2477) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1791), .CK(clk), .RN(n6280), .Q(intDX_EWSW[3]), .QN(n3326) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1722), .CK(clk), .RN(n6234), .Q(intDY_EWSW[6]), .QN(n2481) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1794), .CK(clk), .RN(n6280), .Q(intDX_EWSW[0]), .QN(n3325) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1709), .CK(clk), .RN(n5634), .Q(intDY_EWSW[19]), .QN(n2372) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1790), .CK(clk), .RN(n6280), .Q(intDX_EWSW[4]), .QN(n3324) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1711), .CK(clk), .RN(n5632), .Q(intDY_EWSW[17]), .QN(n2442) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1715), .CK(clk), .RN(n6276), .Q(intDY_EWSW[13]), .QN(n2486) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1713), .CK(clk), .RN(n6276), .Q(intDY_EWSW[15]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_48_ ( .D(n1680), .CK(clk), .RN(n6279), .Q(intDY_EWSW[48]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_49_ ( .D(n1679), .CK(clk), .RN(n6279), .Q(intDY_EWSW[49]), .QN(n2376) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_55_ ( .D(n1673), .CK(clk), .RN(n6279), .Q(intDY_EWSW[55]), .QN(n2475) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_51_ ( .D(n1677), .CK(clk), .RN(n6279), .Q(intDY_EWSW[51]) ); DFFRX4TS R_785 ( .D(n6147), .CK(clk), .RN(n2514), .Q(n6161), .QN(n2294) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_50_ ( .D(n1678), .CK(clk), .RN(n6279), .Q(intDY_EWSW[50]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_56_ ( .D(n1672), .CK(clk), .RN(n6279), .Q(intDY_EWSW[56]) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1182), .CK(clk), .RN(n6264), .Q( Raw_mant_NRM_SWR[16]), .QN(n5581) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_52_ ( .D(n1676), .CK(clk), .RN(n6279), .Q(intDY_EWSW[52]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_57_ ( .D(n1671), .CK(clk), .RN(n6280), .Q(intDY_EWSW[57]), .QN(n2371) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_47_ ( .D(n1681), .CK(clk), .RN(n6279), .Q(intDY_EWSW[47]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1716), .CK(clk), .RN(n6276), .Q(intDY_EWSW[12]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1705), .CK(clk), .RN(n5633), .Q(intDY_EWSW[23]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_54_ ( .D(n1674), .CK(clk), .RN(n6279), .Q(intDY_EWSW[54]), .QN(n2332) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1702), .CK(clk), .RN(n5636), .Q(intDY_EWSW[26]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1726), .CK(clk), .RN(n2543), .Q(intDY_EWSW[2]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1704), .CK(clk), .RN(n5618), .Q(intDY_EWSW[24]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1725), .CK(clk), .RN(n6240), .Q(intDY_EWSW[3]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1712), .CK(clk), .RN(n6276), .Q(intDY_EWSW[16]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1710), .CK(clk), .RN(n5619), .Q(intDY_EWSW[18]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1706), .CK(clk), .RN(n5634), .Q(intDY_EWSW[22]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1708), .CK(clk), .RN(n5632), .Q(intDY_EWSW[20]) ); DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_14_ ( .D(n1125), .CK(clk), .RN(n6258), .Q(LZD_output_NRM2_EW[3]), .QN(n3376) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1724), .CK(clk), .RN(n6240), .Q(intDY_EWSW[4]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_58_ ( .D(n1670), .CK(clk), .RN(n6280), .Q(intDY_EWSW[58]) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1139), .CK(clk), .RN(n6256), .Q( Raw_mant_NRM_SWR[1]), .QN(n5419) ); DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1331), .CK(clk), .RN(n6274), .Q( DMP_exp_NRM2_EW[6]), .QN(n5435) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1131), .CK(clk), .RN(n5652), .Q( Raw_mant_NRM_SWR[5]), .QN(n5429) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1179), .CK(clk), .RN(n6266), .Q( Raw_mant_NRM_SWR[19]), .QN(n5341) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_59_ ( .D(n1669), .CK(clk), .RN(n6280), .Q(intDY_EWSW[59]), .QN(n2374) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1116), .CK(clk), .RN(n5637), .Q( Raw_mant_NRM_SWR[11]), .QN(n5490) ); DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1346), .CK(clk), .RN(n6272), .Q( DMP_exp_NRM2_EW[3]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_60_ ( .D(n1668), .CK(clk), .RN(n6280), .Q(intDY_EWSW[60]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1728), .CK(clk), .RN(n6256), .Q(intDY_EWSW[0]) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_61_ ( .D(n1667), .CK(clk), .RN(n6280), .Q(intDY_EWSW[61]) ); DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1321), .CK(clk), .RN(n6275), .Q( DMP_exp_NRM2_EW[8]) ); DFFRX4TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n1483), .CK(clk), .RN(n6263), .Q( DMP_SFG[12]), .QN(n3350) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1783), .CK(clk), .RN(n6281), .Q(intDX_EWSW[11]), .QN(n3323) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1096), .CK(clk), .RN(n5623), .Q( Raw_mant_NRM_SWR[10]), .QN(n5439) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1120), .CK(clk), .RN(n5637), .Q( Raw_mant_NRM_SWR[7]), .QN(n5424) ); DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1356), .CK(clk), .RN(n6271), .Q( DMP_exp_NRM2_EW[1]) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1787), .CK(clk), .RN(n6281), .Q(intDX_EWSW[7]), .QN(n3352) ); DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1138), .CK(clk), .RN(n6236), .Q(LZD_output_NRM2_EW[0]), .QN(n3321) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1180), .CK(clk), .RN(n6264), .Q( Raw_mant_NRM_SWR[18]), .QN(n5440) ); DFFRX2TS R_322 ( .D(n6369), .CK(clk), .RN(n5638), .Q(n6098) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1110), .CK(clk), .RN(n5628), .Q( Raw_mant_NRM_SWR[13]), .QN(n5443) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1789), .CK(clk), .RN(n6281), .Q(intDX_EWSW[5]), .QN(n3359) ); DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_16_ ( .D(n1141), .CK(clk), .RN(n6257), .Q(LZD_output_NRM2_EW[5]), .QN(n3369) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1785), .CK(clk), .RN(n6281), .Q(intDX_EWSW[9]), .QN(n3319) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1176), .CK(clk), .RN(n5670), .Q( Raw_mant_NRM_SWR[22]), .QN(n5441) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1780), .CK(clk), .RN(n6281), .Q(intDX_EWSW[14]), .QN(n3355) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1788), .CK(clk), .RN(n6281), .Q(intDX_EWSW[6]), .QN(n3317) ); DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_15_ ( .D(n1135), .CK(clk), .RN(n6259), .Q(LZD_output_NRM2_EW[4]), .QN(n3373) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_29_ ( .D(n1169), .CK(clk), .RN(n6291), .Q( Raw_mant_NRM_SWR[29]), .QN(n5343) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1136), .CK(clk), .RN(n6259), .Q( Raw_mant_NRM_SWR[0]), .QN(n5546) ); DFFRX2TS R_672 ( .D(Raw_mant_NRM_SWR[18]), .CK(clk), .RN(n5676), .Q(n5862) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1173), .CK(clk), .RN(n4466), .Q( Raw_mant_NRM_SWR[25]), .QN(n3298) ); DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1326), .CK(clk), .RN(n6274), .Q( DMP_exp_NRM2_EW[7]) ); DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_13_ ( .D(n1122), .CK(clk), .RN(n6258), .Q(LZD_output_NRM2_EW[2]), .QN(n3375) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_38_ ( .D(n1160), .CK(clk), .RN(n6269), .Q( Raw_mant_NRM_SWR[38]), .QN(n3371) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_55_ ( .D(n1203), .CK(clk), .RN(n6270), .Q( DmP_EXP_EWSW[55]), .QN(n3354) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1784), .CK(clk), .RN(n6281), .Q(intDX_EWSW[10]), .QN(n3353) ); DFFRX2TS R_948 ( .D(DmP_mant_SHT1_SW[41]), .CK(clk), .RN(n5659), .Q(n5704) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1123), .CK(clk), .RN(n5623), .Q( Raw_mant_NRM_SWR[6]), .QN(n5423) ); DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1786), .CK(clk), .RN(n6281), .Q(intDX_EWSW[8]), .QN(n3315) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_36_ ( .D(n1162), .CK(clk), .RN(n6268), .Q( Raw_mant_NRM_SWR[36]), .QN(n6209) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_35_ ( .D(n1163), .CK(clk), .RN(n6268), .Q( Raw_mant_NRM_SWR[35]), .QN(n3364) ); DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n1800), .CK(clk), .RN(n6257), .Q( Shift_reg_FLAGS_7_5), .QN(n5596) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1112), .CK(clk), .RN(n5644), .Q( Raw_mant_NRM_SWR[12]), .QN(n5438) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1118), .CK(clk), .RN(n5633), .Q( Raw_mant_NRM_SWR[8]), .QN(n5491) ); DFFRX4TS R_878 ( .D(n5747), .CK(clk), .RN(n2514), .Q(n6405), .QN(n5421) ); DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1054), .CK(clk), .RN(n6237), .Q( DmP_mant_SFG_SWR[16]) ); DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_35_ ( .D(n1035), .CK(clk), .RN(n6238), .Q( DmP_mant_SFG_SWR[35]) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1177), .CK(clk), .RN(n6291), .Q( Raw_mant_NRM_SWR[21]), .QN(n5427) ); DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n1609), .CK(clk), .RN(n5628), .Q(shift_value_SHT2_EWR[2]), .QN(n5436) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1183), .CK(clk), .RN(n6264), .Q( Raw_mant_NRM_SWR[15]), .QN(n5426) ); DFFRX2TS R_714 ( .D(n5041), .CK(clk), .RN(n4463), .Q(n5838) ); DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n1607), .CK(clk), .RN(n5623), .Q(shift_value_SHT2_EWR[4]), .QN(n3372) ); DFFSX1TS R_816 ( .D(final_result_ieee[31]), .CK(clk), .SN(n5621), .Q(n5783) ); DFFSX1TS R_804 ( .D(final_result_ieee[37]), .CK(clk), .SN(n5621), .Q(n5790) ); DFFSX1TS R_800 ( .D(final_result_ieee[40]), .CK(clk), .SN(n2521), .Q(n5792) ); DFFSX1TS R_790 ( .D(final_result_ieee[38]), .CK(clk), .SN(n5621), .Q(n5797) ); DFFSX1TS R_786 ( .D(final_result_ieee[20]), .CK(clk), .SN(n6255), .Q(n5799) ); DFFSX1TS R_780 ( .D(final_result_ieee[10]), .CK(clk), .SN(n5622), .Q(n5801) ); DFFSX1TS R_776 ( .D(final_result_ieee[12]), .CK(clk), .SN(n5685), .Q(n5803) ); DFFSX1TS R_772 ( .D(final_result_ieee[13]), .CK(clk), .SN(n6255), .Q(n5805) ); DFFSX1TS R_766 ( .D(final_result_ieee[11]), .CK(clk), .SN(n5685), .Q(n5808) ); DFFSX1TS R_756 ( .D(final_result_ieee[39]), .CK(clk), .SN(n5620), .Q(n5813) ); DFFSX1TS R_752 ( .D(final_result_ieee[32]), .CK(clk), .SN(n5619), .Q(n5815) ); DFFSX1TS R_748 ( .D(final_result_ieee[30]), .CK(clk), .SN(n5618), .Q(n5817) ); DFFSX1TS R_742 ( .D(final_result_ieee[18]), .CK(clk), .SN(n5622), .Q(n5821) ); DFFSX1TS R_738 ( .D(final_result_ieee[19]), .CK(clk), .SN(n5643), .Q(n5823) ); DFFSX1TS R_154 ( .D(n6429), .CK(clk), .SN(n4464), .Q(n6165) ); DFFSX1TS R_102 ( .D(n6453), .CK(clk), .SN(n5619), .Q(n6184) ); DFFSX1TS R_99 ( .D(n6447), .CK(clk), .SN(n5620), .Q(n6186) ); DFFSX1TS R_12 ( .D(n6444), .CK(clk), .SN(n5619), .Q(n6196) ); DFFSX1TS R_9 ( .D(n6450), .CK(clk), .SN(n5620), .Q(n6197) ); DFFSX1TS R_151 ( .D(n6424), .CK(clk), .SN(n6290), .Q(n6167) ); DFFSX1TS R_117 ( .D(n6427), .CK(clk), .SN(n6288), .Q(n6180) ); DFFSX1TS R_120 ( .D(n6422), .CK(clk), .SN(n6290), .Q(n6178) ); DFFSRHQX4TS SHT2_STAGE_DMP_Q_reg_62_ ( .D(n1314), .CK(clk), .SN(1'b1), .RN( n6233), .Q(DMP_SHT2_EWSW[62]) ); DFFRHQX2TS SHT2_STAGE_DMP_Q_reg_57_ ( .D(n1339), .CK(clk), .RN(n6254), .Q( n5335) ); DFFRHQX4TS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1192), .CK(clk), .RN(n6232), .Q( OP_FLAG_SHT1) ); DFFRHQX4TS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1491), .CK(clk), .RN(n2521), .Q( DMP_SHT1_EWSW[10]) ); DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_45_ ( .D(n1219), .CK(clk), .RN(n2539), .Q(DmP_mant_SHT1_SW[45]) ); DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1277), .CK(clk), .RN(n5671), .Q(DmP_mant_SHT1_SW[16]) ); DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1289), .CK(clk), .RN(n2533), .Q(DmP_mant_SHT1_SW[10]) ); DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1265), .CK(clk), .RN(n2567), .Q(DmP_mant_SHT1_SW[22]) ); DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_50_ ( .D(n1209), .CK(clk), .RN(n6287), .Q(DmP_mant_SHT1_SW[50]) ); DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1271), .CK(clk), .RN(n6287), .Q(DmP_mant_SHT1_SW[19]) ); DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_38_ ( .D(n1233), .CK(clk), .RN(n5671), .Q(DmP_mant_SHT1_SW[38]) ); DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_25_ ( .D(n1259), .CK(clk), .RN(n6263), .Q(DmP_mant_SHT1_SW[25]) ); DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_41_ ( .D(n1227), .CK(clk), .RN(n5675), .Q(DmP_mant_SHT1_SW[41]) ); DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1281), .CK(clk), .RN(n6236), .Q(DmP_mant_SHT1_SW[14]) ); DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_39_ ( .D(n1231), .CK(clk), .RN(n6261), .Q(DmP_mant_SHT1_SW[39]) ); DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1291), .CK(clk), .RN(n2533), .Q(DmP_mant_SHT1_SW[9]) ); DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_48_ ( .D(n1213), .CK(clk), .RN(n6260), .Q(DmP_mant_SHT1_SW[48]) ); DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_32_ ( .D(n1245), .CK(clk), .RN(n2568), .Q(DmP_mant_SHT1_SW[32]) ); DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1303), .CK(clk), .RN(n5668), .Q(DmP_mant_SHT1_SW[3]) ); DFFRHQX1TS Ready_reg_Q_reg_0_ ( .D(n6293), .CK(clk), .RN(n2539), .Q(ready) ); DFFSX4TS R_916 ( .D(n5574), .CK(clk), .SN(n2545), .Q(n5723) ); DFFSRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_63_ ( .D(n1731), .CK(clk), .SN(1'b1), .RN(n6232), .Q(intDX_EWSW[63]) ); DFFSX1TS R_643 ( .D(n2564), .CK(clk), .SN(n5665), .Q(n5884) ); DFFSX1TS R_600 ( .D(n2564), .CK(clk), .SN(n5626), .Q(n5911) ); DFFSX1TS R_401 ( .D(n6224), .CK(clk), .SN(n5648), .Q(n6041) ); DFFSX1TS R_390 ( .D(n2564), .CK(clk), .SN(n5663), .Q(n6048) ); DFFSX1TS R_386 ( .D(n2564), .CK(clk), .SN(n5647), .Q(n6051) ); DFFSX1TS R_367 ( .D(n2499), .CK(clk), .SN(n2544), .Q(n6065) ); DFFSX1TS R_925 ( .D(n6212), .CK(clk), .SN(n5678), .Q(n5717) ); DFFSX1TS R_917 ( .D(n6212), .CK(clk), .SN(n5666), .Q(n5722) ); DFFSX1TS R_913 ( .D(n6212), .CK(clk), .SN(n5651), .Q(n5725) ); DFFSX1TS R_862 ( .D(n6212), .CK(clk), .SN(n5632), .Q(n5755) ); DFFSX1TS R_843 ( .D(n6212), .CK(clk), .SN(n5666), .Q(n5767) ); DFFSX1TS R_814 ( .D(n2557), .CK(clk), .SN(n5636), .Q(n5784) ); DFFSX1TS R_615 ( .D(n6220), .CK(clk), .SN(n5674), .Q(n5900) ); DFFSX1TS R_523 ( .D(n2528), .CK(clk), .SN(n5625), .Q(n5956) ); DFFSX1TS R_487 ( .D(n3046), .CK(clk), .SN(n5664), .Q(n5976) ); DFFSX1TS R_435 ( .D(n3046), .CK(clk), .SN(n5641), .Q(n6014) ); DFFSX1TS R_415 ( .D(n6222), .CK(clk), .SN(n5654), .Q(n6029) ); DFFSX1TS R_389 ( .D(n2528), .CK(clk), .SN(n5662), .Q(n6049) ); DFFSX1TS R_371 ( .D(n2528), .CK(clk), .SN(n5681), .Q(n6062) ); DFFSX1TS R_366 ( .D(n6220), .CK(clk), .SN(n2545), .Q(n6066) ); DFFSX1TS R_331 ( .D(n2528), .CK(clk), .SN(n5630), .Q(n6090) ); DFFSX1TS R_874 ( .D(n2496), .CK(clk), .SN(n5670), .Q(n5748) ); DFFSX1TS R_284 ( .D(n6409), .CK(clk), .SN(n2512), .Q(n6123) ); DFFSX1TS R_269 ( .D(n6374), .CK(clk), .SN(n5639), .Q(n6132) ); DFFSX1TS R_100 ( .D(n6454), .CK(clk), .SN(n5619), .Q(n6185) ); DFFSX1TS R_606 ( .D(n6316), .CK(clk), .SN(n5674), .Q(n5906) ); DFFSX1TS R_303 ( .D(n6313), .CK(clk), .SN(n5678), .Q(n6111) ); DFFSX1TS R_276 ( .D(n6434), .CK(clk), .SN(n5667), .Q(n6127) ); DFFSX1TS R_264 ( .D(n6432), .CK(clk), .SN(n5668), .Q(n6134) ); DFFSX1TS R_260 ( .D(n6415), .CK(clk), .SN(n5667), .Q(n6136) ); DFFSX1TS R_274 ( .D(n6417), .CK(clk), .SN(n5667), .Q(n6128) ); DFFSX1TS R_272 ( .D(n6421), .CK(clk), .SN(n6238), .Q(n6129) ); DFFSX1TS R_258 ( .D(n6436), .CK(clk), .SN(n6254), .Q(n6137) ); DFFSX1TS R_262 ( .D(n6419), .CK(clk), .SN(n6261), .Q(n6135) ); DFFSX1TS R_126 ( .D(n6337), .CK(clk), .SN(n5661), .Q(n6173) ); DFFSX1TS R_301 ( .D(n6356), .CK(clk), .SN(n5647), .Q(n6113) ); DFFSX1TS R_122 ( .D(n6346), .CK(clk), .SN(n5655), .Q(n6176) ); DFFSX1TS R_97 ( .D(n6448), .CK(clk), .SN(n5619), .Q(n6187) ); DFFSX1TS R_335 ( .D(n6377), .CK(clk), .SN(n5639), .Q(n6087) ); DFFSX1TS R_737 ( .D(n6352), .CK(clk), .SN(n5651), .Q(n5824) ); DFFSX1TS R_245 ( .D(n6400), .CK(clk), .SN(n5625), .Q(n6144) ); DFFSX1TS R_270 ( .D(n6373), .CK(clk), .SN(n5639), .Q(n6131) ); DFFSX1TS R_227 ( .D(n6331), .CK(clk), .SN(n6257), .Q(n6153) ); DFFSX1TS R_340 ( .D(n6322), .CK(clk), .SN(n5672), .Q(n6082) ); DFFSX1TS R_334 ( .D(n6378), .CK(clk), .SN(n5640), .Q(n6088) ); DFFSX1TS R_604 ( .D(n6386), .CK(clk), .SN(n5641), .Q(n5908) ); DFFSX1TS R_607 ( .D(n6315), .CK(clk), .SN(n5674), .Q(n5905) ); DFFSX1TS R_152 ( .D(n6430), .CK(clk), .SN(n5663), .Q(n6166) ); DFFSX1TS R_338 ( .D(n6334), .CK(clk), .SN(n5662), .Q(n6084) ); DFFSX1TS R_393 ( .D(n6309), .CK(clk), .SN(n5678), .Q(n6046) ); DFFSX1TS R_149 ( .D(n6426), .CK(clk), .SN(n5661), .Q(n6169) ); DFFSX1TS R_341 ( .D(n6321), .CK(clk), .SN(n5667), .Q(n6081) ); DFFSX1TS R_55 ( .D(n6317), .CK(clk), .SN(n4463), .Q(n6192) ); DFFSX1TS R_375 ( .D(n6343), .CK(clk), .SN(n5662), .Q(n6059) ); DFFSX1TS R_226 ( .D(n5430), .CK(clk), .SN(n6258), .Q(n6154) ); DFFSX1TS R_300 ( .D(n6357), .CK(clk), .SN(n5646), .Q(n6114) ); DFFSX1TS R_337 ( .D(n6335), .CK(clk), .SN(n5662), .Q(n6085) ); DFFSX1TS R_603 ( .D(n6387), .CK(clk), .SN(n5642), .Q(n5909) ); DFFSX1TS R_125 ( .D(n6338), .CK(clk), .SN(n5661), .Q(n6174) ); DFFSX1TS R_248 ( .D(n6383), .CK(clk), .SN(n5638), .Q(n6142) ); DFFSX1TS R_7 ( .D(n6451), .CK(clk), .SN(n5620), .Q(n6198) ); DFFSX1TS R_868 ( .D(n6226), .CK(clk), .SN(n2533), .Q(n5752) ); DFFSX1TS R_820 ( .D(n6225), .CK(clk), .SN(n5636), .Q(n5781) ); DFFSX1TS R_677 ( .D(n6227), .CK(clk), .SN(n5642), .Q(n5859) ); DFFSX1TS R_653 ( .D(n6226), .CK(clk), .SN(n5666), .Q(n5877) ); DFFSX1TS R_649 ( .D(n6226), .CK(clk), .SN(n5679), .Q(n5879) ); DFFSX1TS R_621 ( .D(n2556), .CK(clk), .SN(n5650), .Q(n5897) ); DFFSX1TS R_549 ( .D(n6225), .CK(clk), .SN(n5635), .Q(n5946) ); DFFSX1TS R_244 ( .D(n2375), .CK(clk), .SN(n5624), .Q(n6145) ); DFFSX1TS R_608 ( .D(n6314), .CK(clk), .SN(n5674), .Q(n5904) ); DFFSX1TS R_394 ( .D(n6308), .CK(clk), .SN(n5678), .Q(n6045) ); DFFSX1TS R_339 ( .D(n6333), .CK(clk), .SN(n5662), .Q(n6083) ); DFFSX1TS R_228 ( .D(n6330), .CK(clk), .SN(n6257), .Q(n6152) ); DFFSX1TS R_305 ( .D(n6311), .CK(clk), .SN(n5677), .Q(n6109) ); DFFSX1TS R_392 ( .D(n6310), .CK(clk), .SN(n5677), .Q(n6047) ); DFFSX1TS R_314 ( .D(n6326), .CK(clk), .SN(n2544), .Q(n6104) ); DFFSX1TS R_323 ( .D(n6368), .CK(clk), .SN(n5639), .Q(n6097) ); DFFSX1TS R_317 ( .D(n6350), .CK(clk), .SN(n5654), .Q(n6102) ); DFFSX1TS R_491 ( .D(n6299), .CK(clk), .SN(n2567), .Q(n5973) ); DFFSX1TS R_231 ( .D(n6318), .CK(clk), .SN(n5638), .Q(n6151) ); DFFSX1TS R_224 ( .D(n6307), .CK(clk), .SN(n5677), .Q(n6155) ); DFFSX1TS R_243 ( .D(n6401), .CK(clk), .SN(n5625), .Q(n6146) ); DFFSX1TS R_605 ( .D(n6385), .CK(clk), .SN(n5642), .Q(n5907) ); DFFSX1TS R_336 ( .D(n6376), .CK(clk), .SN(n5640), .Q(n6086) ); DFFSX1TS R_302 ( .D(n6355), .CK(clk), .SN(n5646), .Q(n6112) ); DFFSX1TS R_271 ( .D(n6372), .CK(clk), .SN(n5639), .Q(n6130) ); DFFSX1TS R_123 ( .D(n6345), .CK(clk), .SN(n5654), .Q(n6175) ); DFFSX1TS R_320 ( .D(n6348), .CK(clk), .SN(n5654), .Q(n6100) ); DFFSX1TS R_290 ( .D(n6354), .CK(clk), .SN(n5646), .Q(n6119) ); DFFRHQX2TS SGF_STAGE_DMP_Q_reg_50_ ( .D(n1369), .CK(clk), .RN(n2539), .Q( DMP_SFG[50]) ); DFFRHQX2TS SGF_STAGE_DMP_Q_reg_49_ ( .D(n1372), .CK(clk), .RN(n2538), .Q( DMP_SFG[49]) ); DFFRHQX2TS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1187), .CK(clk), .RN(n4465), .Q( SIGN_FLAG_SFG) ); DFFRHQX2TS SGF_STAGE_DMP_Q_reg_62_ ( .D(n1313), .CK(clk), .RN(n2511), .Q( DMP_SFG[62]) ); DFFRHQX2TS SGF_STAGE_DMP_Q_reg_51_ ( .D(n1366), .CK(clk), .RN(n2539), .Q( DMP_SFG[51]) ); DFFRHQX2TS SGF_STAGE_DMP_Q_reg_58_ ( .D(n1333), .CK(clk), .RN(n6274), .Q( DMP_SFG[58]) ); DFFRHQX2TS SGF_STAGE_DMP_Q_reg_56_ ( .D(n1343), .CK(clk), .RN(n2538), .Q( DMP_SFG[56]) ); DFFRHQX2TS SGF_STAGE_DMP_Q_reg_54_ ( .D(n1353), .CK(clk), .RN(n6272), .Q( DMP_SFG[54]) ); DFFRHQX2TS SGF_STAGE_DMP_Q_reg_52_ ( .D(n1363), .CK(clk), .RN(n2515), .Q( DMP_SFG[52]) ); DFFRHQX2TS SGF_STAGE_DMP_Q_reg_55_ ( .D(n1348), .CK(clk), .RN(n6272), .Q( DMP_SFG[55]) ); DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1111), .CK(clk), .RN(n2539), .Q(DmP_mant_SFG_SWR[13]) ); DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1113), .CK(clk), .RN(n5644), .Q(DmP_mant_SFG_SWR[12]) ); DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1119), .CK(clk), .RN(n2539), .Q(DmP_mant_SFG_SWR[8]) ); DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1134), .CK(clk), .RN(n5652), .Q(DmP_mant_SFG_SWR[2]) ); DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1129), .CK(clk), .RN(n2538), .Q(DmP_mant_SFG_SWR[3]) ); DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1105), .CK(clk), .RN(n2539), .Q(DmP_mant_SFG_SWR[9]) ); DFFRHQX2TS EXP_STAGE_DMP_Q_reg_53_ ( .D(n1534), .CK(clk), .RN(n6271), .Q( DMP_EXP_EWSW[53]) ); DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1097), .CK(clk), .RN(n5623), .Q(DmP_mant_SFG_SWR[10]) ); DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1124), .CK(clk), .RN(n5623), .Q(DmP_mant_SFG_SWR[6]) ); DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1132), .CK(clk), .RN(n5652), .Q(DmP_mant_SFG_SWR[5]) ); DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1117), .CK(clk), .RN(n5637), .Q(DmP_mant_SFG_SWR[11]) ); DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1127), .CK(clk), .RN(n2538), .Q(DmP_mant_SFG_SWR[4]) ); DFFRHQX2TS NRM_STAGE_Raw_mant_Q_reg_51_ ( .D(n1147), .CK(clk), .RN(n6267), .Q(Raw_mant_NRM_SWR[51]) ); DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1121), .CK(clk), .RN(n5637), .Q(DmP_mant_SFG_SWR[7]) ); DFFRXLTS R_765 ( .D(n6459), .CK(clk), .RN(n5618), .Q(n5809) ); DFFRHQX2TS EXP_STAGE_DmP_Q_reg_43_ ( .D(n1224), .CK(clk), .RN(n2538), .Q( DmP_EXP_EWSW[43]) ); DFFRHQX1TS R_877 ( .D(n1143), .CK(clk), .RN(n2538), .Q(n5332) ); DFFSRHQX4TS INPUT_STAGE_OPERANDY_Q_reg_63_ ( .D(n1665), .CK(clk), .SN(1'b1), .RN(n6286), .Q(intDY_EWSW[63]) ); DFFSHQX8TS NRM_STAGE_Raw_mant_Q_reg_44_ ( .D(n5330), .CK(clk), .SN(n6465), .Q(n5428) ); DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1604), .CK(clk), .RN(n6270), .Q(Shift_amount_SHT1_EWR[0]), .QN(n5434) ); DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1496), .CK(clk), .RN(n6266), .Q( DMP_SHT2_EWSW[8]), .QN(n5448) ); DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1448), .CK(clk), .RN(n6245), .Q( DMP_SHT2_EWSW[24]), .QN(n5386) ); DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1433), .CK(clk), .RN(n6247), .Q( DMP_SHT2_EWSW[29]), .QN(n5381) ); DFFRXLTS SHT2_STAGE_DMP_Q_reg_34_ ( .D(n1418), .CK(clk), .RN(n1882), .Q( DMP_SHT2_EWSW[34]), .QN(n5376) ); DFFRXLTS SHT2_STAGE_DMP_Q_reg_39_ ( .D(n1403), .CK(clk), .RN(n6258), .Q( DMP_SHT2_EWSW[39]), .QN(n5338) ); DFFRXLTS SHT2_STAGE_DMP_Q_reg_50_ ( .D(n1370), .CK(clk), .RN(n6233), .Q( DMP_SHT2_EWSW[50]), .QN(n5364) ); DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_50_ ( .D(n1020), .CK(clk), .RN(n2512), .Q( DmP_mant_SFG_SWR[50]), .QN(n5558) ); DFFRXLTS R_709 ( .D(n6208), .CK(clk), .RN(n2532), .Q(n5842) ); DFFRXLTS R_957 ( .D(n6351), .CK(clk), .RN(n5652), .Q(n5699) ); DFFSX1TS R_783 ( .D(n6414), .CK(clk), .SN(n5622), .Q(n5800) ); DFFSX1TS R_819 ( .D(n6440), .CK(clk), .SN(n5621), .Q(n5782) ); DFFRX1TS EXP_STAGE_DMP_Q_reg_52_ ( .D(n1535), .CK(clk), .RN(n6271), .Q( DMP_EXP_EWSW[52]), .QN(n5557) ); DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1279), .CK(clk), .RN(n5671), .Q(DmP_mant_SHT1_SW[15]) ); DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1287), .CK(clk), .RN(n6258), .Q(DmP_mant_SHT1_SW[11]) ); DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_29_ ( .D(n1041), .CK(clk), .RN(n6238), .Q( n2293), .QN(n5518) ); DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_31_ ( .D(n1039), .CK(clk), .RN(n6238), .Q( DmP_mant_SFG_SWR[31]) ); DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_30_ ( .D(n1040), .CK(clk), .RN(n6238), .Q( DmP_mant_SFG_SWR[30]) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_33_ ( .D(n1165), .CK(clk), .RN(n6268), .Q( Raw_mant_NRM_SWR[33]), .QN(n5569) ); DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_33_ ( .D(n1037), .CK(clk), .RN(n6238), .Q( DmP_mant_SFG_SWR[33]) ); DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_37_ ( .D(n1033), .CK(clk), .RN(n6239), .Q( DmP_mant_SFG_SWR[37]) ); DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_44_ ( .D(n1221), .CK(clk), .RN(n6465), .Q(DmP_mant_SHT1_SW[44]), .QN(n5416) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_26_ ( .D(n1172), .CK(clk), .RN(n5625), .Q( Raw_mant_NRM_SWR[26]), .QN(n5431) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_48_ ( .D(n1150), .CK(clk), .RN(n6267), .Q( Raw_mant_NRM_SWR[48]), .QN(n5420) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_37_ ( .D(n1161), .CK(clk), .RN(n6269), .Q( Raw_mant_NRM_SWR[37]), .QN(n5345) ); DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1052), .CK(clk), .RN(n6237), .Q( DmP_mant_SFG_SWR[18]) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_43_ ( .D(n1155), .CK(clk), .RN(n6268), .Q( Raw_mant_NRM_SWR[43]), .QN(n5433) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1718), .CK(clk), .RN(n6276), .Q(intDY_EWSW[10]) ); DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_36_ ( .D(n1034), .CK(clk), .RN(n6239), .Q( DmP_mant_SFG_SWR[36]) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_42_ ( .D(n1156), .CK(clk), .RN(n6268), .Q( Raw_mant_NRM_SWR[42]), .QN(n2416) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_50_ ( .D(n1148), .CK(clk), .RN(n6267), .Q( Raw_mant_NRM_SWR[50]), .QN(n5580) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_32_ ( .D(n1166), .CK(clk), .RN(n4466), .Q( Raw_mant_NRM_SWR[32]), .QN(n5573) ); DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n1801), .CK(clk), .RN(n6291), .Q( Shift_reg_FLAGS_7_6), .QN(n5495) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_47_ ( .D(n1151), .CK(clk), .RN(n6267), .Q( Raw_mant_NRM_SWR[47]), .QN(n5579) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1714), .CK(clk), .RN(n6276), .Q(intDY_EWSW[14]) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_46_ ( .D(n1152), .CK(clk), .RN(n6268), .Q( Raw_mant_NRM_SWR[46]), .QN(n5425) ); DFFRX4TS R_965 ( .D(Raw_mant_NRM_SWR[17]), .CK(clk), .RN(n5659), .Q(n5695) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1181), .CK(clk), .RN(n6264), .Q( Raw_mant_NRM_SWR[17]), .QN(n5572) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_52_ ( .D(n1206), .CK(clk), .RN(n6270), .Q( DmP_EXP_EWSW[52]), .QN(n3329) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_53_ ( .D(n1205), .CK(clk), .RN(n6270), .Q( DmP_EXP_EWSW[53]), .QN(n3331) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1720), .CK(clk), .RN(n6276), .Q(intDY_EWSW[8]), .QN(n2288) ); DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n1608), .CK(clk), .RN(n5633), .Q(shift_value_SHT2_EWR[3]), .QN(n5344) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_54_ ( .D(n1533), .CK(clk), .RN(n6272), .Q( DMP_EXP_EWSW[54]), .QN(n5556) ); DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1351), .CK(clk), .RN(n6271), .Q( DMP_exp_NRM2_EW[2]), .QN(n1867) ); DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1719), .CK(clk), .RN(n6276), .Q(intDY_EWSW[9]) ); DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_38_ ( .D(n1032), .CK(clk), .RN(n6239), .Q( DmP_mant_SFG_SWR[38]) ); DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n1795), .CK(clk), .RN(n6285), .Q( Shift_reg_FLAGS_7[0]), .QN(n5571) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_28_ ( .D(n1170), .CK(clk), .RN(n5625), .Q( Raw_mant_NRM_SWR[28]), .QN(n5492) ); DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1361), .CK(clk), .RN(n2514), .Q( DMP_exp_NRM2_EW[0]) ); DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n1797), .CK(clk), .RN(n5658), .Q( Shift_reg_FLAGS_7[2]), .QN(n5446) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_40_ ( .D(n1399), .CK(clk), .RN(n5670), .Q( DMP_SFG[40]), .QN(n5399) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1175), .CK(clk), .RN(n4466), .Q( Raw_mant_NRM_SWR[23]), .QN(n5342) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_53_ ( .D(n1145), .CK(clk), .RN(n6267), .Q( Raw_mant_NRM_SWR[53]), .QN(n5574) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_41_ ( .D(n1157), .CK(clk), .RN(n6268), .Q( Raw_mant_NRM_SWR[41]), .QN(n5422) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_27_ ( .D(n1171), .CK(clk), .RN(n6240), .Q( Raw_mant_NRM_SWR[27]), .QN(n5432) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1104), .CK(clk), .RN(n5628), .Q( Raw_mant_NRM_SWR[9]), .QN(n5340) ); DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n1729), .CK(clk), .RN(n6269), .Q(left_right_SHT2), .QN(n2449) ); DFFRX2TS R_510 ( .D(Raw_mant_NRM_SWR[26]), .CK(clk), .RN(n5628), .Q(n5963) ); DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_44_ ( .D(n1026), .CK(clk), .RN(n6239), .Q( DmP_mant_SFG_SWR[44]), .QN(n5552) ); DFFSX2TS R_429 ( .D(n6224), .CK(clk), .SN(n5655), .Q(n6020) ); DFFRX2TS SGF_STAGE_DMP_Q_reg_39_ ( .D(n1402), .CK(clk), .RN(n6289), .Q( DMP_SFG[39]), .QN(n5400) ); DFFSX2TS R_380 ( .D(n2499), .CK(clk), .SN(n5669), .Q(n6055) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_30_ ( .D(n1168), .CK(clk), .RN(n6269), .Q( Raw_mant_NRM_SWR[30]), .QN(n5445) ); DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1049), .CK(clk), .RN(n6237), .Q( DmP_mant_SFG_SWR[21]), .QN(n5564) ); DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n1803), .CK(clk), .RN( n6253), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]), .QN(n5494) ); DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1045), .CK(clk), .RN(n6237), .Q( DmP_mant_SFG_SWR[25]) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_31_ ( .D(n1167), .CK(clk), .RN(n6267), .Q( Raw_mant_NRM_SWR[31]), .QN(n5442) ); DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_52_ ( .D(n1018), .CK(clk), .RN(n2512), .QN(n5548) ); DFFRX2TS R_311 ( .D(n6147), .CK(clk), .RN(n2515), .Q(n6160) ); DFFSX2TS R_633 ( .D(n2556), .CK(clk), .SN(n5657), .Q(n5891) ); DFFSX4TS R_506 ( .D(DmP_mant_SHT1_SW[30]), .CK(clk), .SN(n5664), .Q(n5966) ); DFFSX2TS R_409 ( .D(n5032), .CK(clk), .SN(n5673), .Q(n6035) ); DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1046), .CK(clk), .RN(n6237), .Q( DmP_mant_SFG_SWR[24]), .QN(n5521) ); DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1048), .CK(clk), .RN(n6237), .Q( DmP_mant_SFG_SWR[22]), .QN(n5563) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_34_ ( .D(n1164), .CK(clk), .RN(n6268), .Q( Raw_mant_NRM_SWR[34]), .QN(n5437) ); DFFSX2TS R_453 ( .D(n6223), .CK(clk), .SN(n5648), .Q(n6003) ); DFFSX2TS R_449 ( .D(n2564), .CK(clk), .SN(n6257), .Q(n6006) ); DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n1802), .CK(clk), .RN( n5643), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n5444) ); DFFSX2TS R_641 ( .D(n6226), .CK(clk), .SN(n5665), .Q(n5885) ); DFFRX2TS R_313 ( .D(n6381), .CK(clk), .RN(n2543), .Q(n6105) ); DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_39_ ( .D(n1031), .CK(clk), .RN(n6239), .Q( DmP_mant_SFG_SWR[39]) ); DFFSX4TS R_978 ( .D(n2287), .CK(clk), .SN(n5631), .QN(n2436) ); DFFRX4TS R_979 ( .D(Raw_mant_NRM_SWR[2]), .CK(clk), .RN(n5629), .QN(n2379) ); DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_41_ ( .D(n1029), .CK(clk), .RN(n6239), .Q( DmP_mant_SFG_SWR[41]), .QN(n5561) ); DFFSX4TS R_980 ( .D(n6201), .CK(clk), .SN(n5630), .Q(n5687) ); DFFSX4TS R_321 ( .D(n6408), .CK(clk), .SN(n5639), .Q(n6099) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1133), .CK(clk), .RN(n5644), .Q( Raw_mant_NRM_SWR[2]), .QN(n5412) ); DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1055), .CK(clk), .RN(n5623), .Q( DmP_mant_SFG_SWR[15]), .QN(n5566) ); DFFSX2TS R_483 ( .D(n3046), .CK(clk), .SN(n5641), .Q(n5980) ); DFFSX4TS R_964 ( .D(n2553), .CK(clk), .SN(n5661), .Q(n5696) ); DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_26_ ( .D(n1044), .CK(clk), .RN(n6238), .Q( DmP_mant_SFG_SWR[26]), .QN(n5520) ); DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n1796), .CK(clk), .RN(n6289), .Q( Shift_reg_FLAGS_7[1]), .QN(n2384) ); DFFSX2TS R_951 ( .D(n6204), .CK(clk), .SN(n5645), .Q(n5702) ); DFFRX1TS FRMT_STAGE_DATAOUT_Q_reg_49_ ( .D(n1058), .CK(clk), .RN(n2520), .Q( final_result_ieee[49]), .QN(n5502) ); DFFRX1TS FRMT_STAGE_DATAOUT_Q_reg_51_ ( .D(n1056), .CK(clk), .RN(n6289), .Q( final_result_ieee[51]), .QN(n5507) ); DFFRX1TS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1068), .CK(clk), .RN(n6235), .Q( final_result_ieee[2]), .QN(n5523) ); DFFSX4TS R_673 ( .D(n1645), .CK(clk), .SN(n5679), .Q(n5861) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_52_ ( .D(n1146), .CK(clk), .RN(n6267), .Q( Raw_mant_NRM_SWR[52]), .QN(n5417) ); DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_40_ ( .D(n1030), .CK(clk), .RN(n6239), .Q( DmP_mant_SFG_SWR[40]), .QN(n5562) ); DFFSX2TS R_479 ( .D(n3046), .CK(clk), .SN(n5677), .Q(n5983) ); DFFSX2TS R_342 ( .D(n6320), .CK(clk), .SN(n4463), .Q(n6080) ); DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_48_ ( .D(n1022), .CK(clk), .RN(n2511), .Q( DmP_mant_SFG_SWR[48]), .QN(n5550) ); DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_32_ ( .D(n1038), .CK(clk), .RN(n6238), .Q( DmP_mant_SFG_SWR[32]), .QN(n5568) ); DFFSX4TS R_611 ( .D(n6227), .CK(clk), .SN(n5665), .Q(n5902) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1089), .CK(clk), .RN(n6234), .Q( final_result_ieee[25]), .QN(n5535) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1099), .CK(clk), .RN(n6234), .Q( final_result_ieee[24]), .QN(n5534) ); DFFSX2TS R_907 ( .D(n2553), .CK(clk), .SN(n5658), .Q(n5730) ); DFFSX2TS R_329 ( .D(n6360), .CK(clk), .SN(n5647), .Q(n6091) ); DFFRX1TS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1083), .CK(clk), .RN(n6234), .Q( final_result_ieee[21]), .QN(n5531) ); DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1293), .CK(clk), .RN(n2543), .Q( DmP_mant_SHT1_SW[8]) ); DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1305), .CK(clk), .RN(n2543), .Q( DmP_mant_SHT1_SW[2]) ); DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_51_ ( .D(n1207), .CK(clk), .RN(n6260), .Q(DmP_mant_SHT1_SW[51]), .QN(n5617) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_57_ ( .D(n1530), .CK(clk), .RN(n6274), .Q( DMP_EXP_EWSW[57]), .QN(n5553) ); DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_28_ ( .D(n1253), .CK(clk), .RN(n2569), .Q(DmP_mant_SHT1_SW[28]), .QN(n5576) ); DFFRX4TS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1602), .CK(clk), .RN(n2540), .Q(Shift_amount_SHT1_EWR[2]) ); DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_37_ ( .D(n1235), .CK(clk), .RN(n5683), .Q(DmP_mant_SHT1_SW[37]), .QN(n5588) ); DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_26_ ( .D(n1257), .CK(clk), .RN(n5685), .Q(DmP_mant_SHT1_SW[26]), .QN(n5591) ); DFFRX4TS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1730), .CK(clk), .RN(n2514), .Q( intAS) ); DFFSX2TS R_333 ( .D(n2564), .CK(clk), .SN(n5630), .Q(n6089) ); DFFSX2TS R_345 ( .D(n6223), .CK(clk), .SN(n5676), .Q(n6079) ); DFFSX2TS R_349 ( .D(n2499), .CK(clk), .SN(n2541), .Q(n6077) ); DFFSX2TS R_413 ( .D(n2499), .CK(clk), .SN(n5663), .Q(n6031) ); DFFSX2TS R_425 ( .D(n2499), .CK(clk), .SN(n5640), .Q(n6023) ); DFFSX2TS R_437 ( .D(n2498), .CK(clk), .SN(n5641), .QN(n1898) ); DFFSX2TS R_461 ( .D(n2498), .CK(clk), .SN(n5649), .Q(n5995) ); DFFSX2TS R_498 ( .D(n2498), .CK(clk), .SN(n5678), .Q(n5970) ); DFFSX2TS R_571 ( .D(n6224), .CK(clk), .SN(n5673), .Q(n5936) ); DFFSX2TS R_647 ( .D(n6224), .CK(clk), .SN(n5657), .Q(n5881) ); DFFSX2TS R_702 ( .D(n2523), .CK(clk), .SN(n5680), .Q(n5847) ); DFFSX2TS R_698 ( .D(n2557), .CK(clk), .SN(n5642), .Q(n5850) ); DFFSX2TS R_694 ( .D(n2557), .CK(clk), .SN(n5650), .Q(n5852) ); DFFSX2TS R_685 ( .D(n2557), .CK(clk), .SN(n2520), .Q(n5855) ); DFFSX2TS R_915 ( .D(n2557), .CK(clk), .SN(n2544), .Q(n5724) ); DFFSX2TS R_909 ( .D(n2557), .CK(clk), .SN(n5657), .Q(n5728) ); DFFSX2TS R_893 ( .D(n2557), .CK(clk), .SN(n5666), .Q(n5737) ); DFFSX2TS R_885 ( .D(n2557), .CK(clk), .SN(n5651), .Q(n5742) ); DFFSX2TS R_831 ( .D(n2557), .CK(clk), .SN(n6258), .Q(n5773) ); DFFSX2TS R_297 ( .D(n2557), .CK(clk), .SN(n5646), .Q(n6116) ); DFFSX4TS R_717 ( .D(n6201), .CK(clk), .SN(n5680), .Q(n5836) ); DFFSX4TS R_723 ( .D(n6227), .CK(clk), .SN(n5632), .Q(n5833) ); DFFSX2TS R_927 ( .D(n2553), .CK(clk), .SN(n5669), .Q(n5716) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_54_ ( .D(n1204), .CK(clk), .RN(n6270), .Q( DmP_EXP_EWSW[54]), .QN(n3330) ); DFFSX2TS R_266 ( .D(n6204), .CK(clk), .SN(n5677), .Q(n6133) ); DFFSX2TS R_822 ( .D(n6203), .CK(clk), .SN(n5666), .Q(n5780) ); DFFSX2TS R_294 ( .D(n2500), .CK(clk), .SN(n5630), .Q(n6117) ); DFFSX2TS R_535 ( .D(n6220), .CK(clk), .SN(n5664), .Q(n5952) ); DFFSX2TS R_531 ( .D(n6222), .CK(clk), .SN(n5656), .Q(n5954) ); DFFSX2TS R_403 ( .D(n2528), .CK(clk), .SN(n5640), .Q(n6039) ); DFFSX2TS R_395 ( .D(n6222), .CK(clk), .SN(n2514), .Q(n6044) ); DFFSX2TS R_424 ( .D(n6222), .CK(clk), .SN(n5640), .Q(n6024) ); DFFSX2TS R_456 ( .D(n2528), .CK(clk), .SN(n5672), .Q(n6000) ); DFFSX2TS R_468 ( .D(n6220), .CK(clk), .SN(n5635), .Q(n5993) ); DFFSX2TS R_476 ( .D(n6222), .CK(clk), .SN(n2533), .Q(n5986) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_5_ ( .D(n1582), .CK(clk), .RN(n6465), .Q( DMP_EXP_EWSW[5]) ); DFFRX4TS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n1195), .CK(clk), .RN(n6465), .Q( ZERO_FLAG_NRM) ); DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_29_ ( .D(n1251), .CK(clk), .RN(n6465), .Q(DmP_mant_SHT1_SW[29]), .QN(n5610) ); DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_35_ ( .D(n1239), .CK(clk), .RN(n6465), .Q(DmP_mant_SHT1_SW[35]), .QN(n5603) ); DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_43_ ( .D(n1223), .CK(clk), .RN(n6465), .Q(DmP_mant_SHT1_SW[43]), .QN(n5413) ); DFFSX2TS R_972 ( .D(n2500), .CK(clk), .SN(n5654), .Q(n5690) ); DFFSX2TS R_291 ( .D(n2501), .CK(clk), .SN(n5646), .Q(n6118) ); DFFSX4TS R_923 ( .D(n2508), .CK(clk), .SN(n6262), .Q(n5718) ); DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_49_ ( .D(n1149), .CK(clk), .RN(n6267), .Q( Raw_mant_NRM_SWR[49]), .QN(n3367) ); DFFSX2TS R_67 ( .D(n6332), .CK(clk), .SN(n6258), .Q(n6191) ); DFFRHQX2TS SHT1_STAGE_DmP_mant_Q_reg_47_ ( .D(n1215), .CK(clk), .RN(n5659), .Q(DmP_mant_SHT1_SW[47]) ); DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_34_ ( .D(n1036), .CK(clk), .RN(n6238), .Q( DmP_mant_SFG_SWR[34]), .QN(n5567) ); DFFRHQX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1707), .CK(clk), .RN(n5631), .Q(n2479) ); DFFRX4TS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1199), .CK(clk), .RN(n5670), .Q( overflow_flag), .QN(n5411) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_17_ ( .D(n1570), .CK(clk), .RN(n6242), .Q( DMP_EXP_EWSW[17]) ); DFFSX4TS R_779 ( .D(n6418), .CK(clk), .SN(n6286), .Q(n5802) ); DFFRX4TS R_724 ( .D(DmP_mant_SHT1_SW[49]), .CK(clk), .RN(n5629), .Q(n5832) ); DFFRHQX2TS SHT1_STAGE_DmP_mant_Q_reg_49_ ( .D(n1211), .CK(clk), .RN(n6287), .Q(DmP_mant_SHT1_SW[49]) ); DFFRHQX2TS SHT1_STAGE_DmP_mant_Q_reg_27_ ( .D(n1255), .CK(clk), .RN(n6266), .Q(DmP_mant_SHT1_SW[27]) ); DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1269), .CK(clk), .RN(n2542), .Q(DmP_mant_SHT1_SW[20]) ); DFFRHQX2TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1283), .CK(clk), .RN(n6236), .Q(DmP_mant_SHT1_SW[13]) ); DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_51_ ( .D(n1019), .CK(clk), .RN(n2511), .Q( n2451), .QN(n5418) ); DFFSRHQX4TS SGF_STAGE_DmP_mant_Q_reg_28_ ( .D(n1042), .CK(clk), .SN(1'b1), .RN(n2539), .Q(DmP_mant_SFG_SWR[28]) ); DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_53_ ( .D(n1017), .CK(clk), .RN(n2511), .Q( n2450), .QN(n5547) ); DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1295), .CK(clk), .RN(n2533), .Q( DmP_mant_SHT1_SW[7]), .QN(n5616) ); DFFSX2TS R_176 ( .D(n6340), .CK(clk), .SN(n5662), .QN(n2390) ); DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n1799), .CK(clk), .RN(n5667), .Q( n2383), .QN(n5493) ); DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_43_ ( .D(n1027), .CK(clk), .RN(n6239), .Q( DmP_mant_SFG_SWR[43]) ); DFFRHQX8TS R_876 ( .D(n6147), .CK(clk), .RN(n2514), .Q(n2487) ); DFFRHQX2TS NRM_STAGE_Raw_mant_Q_reg_39_ ( .D(n1159), .CK(clk), .RN(n6268), .Q(n2345) ); DFFRX2TS R_761 ( .D(Raw_mant_NRM_SWR[46]), .CK(clk), .RN(n2532), .Q(n5810) ); DFFSX4TS R_872 ( .D(n1823), .CK(clk), .SN(n5670), .Q(n5750) ); DFFSX4TS R_730 ( .D(n1823), .CK(clk), .SN(n5666), .Q(n5829) ); DFFSX2TS R_114 ( .D(n6344), .CK(clk), .SN(n5661), .Q(n6182) ); DFFRHQX2TS NRM_STAGE_Raw_mant_Q_reg_54_ ( .D(n1144), .CK(clk), .RN(n6267), .Q(n2323) ); DFFSX2TS R_253 ( .D(n6370), .CK(clk), .SN(n5639), .Q(n6139) ); DFFRX4TS R_587 ( .D(n6364), .CK(clk), .RN(n5624), .Q(n5924) ); DFFRX4TS R_734 ( .D(n6301), .CK(clk), .RN(n5684), .Q(n5827) ); DFFRX4TS R_853 ( .D(n6295), .CK(clk), .RN(n2540), .Q(n5761) ); DFFRX4TS R_828 ( .D(n6379), .CK(clk), .RN(n5637), .Q(n5776) ); DFFRX4TS R_589 ( .D(n6366), .CK(clk), .RN(n5624), .Q(n5922) ); DFFSX2TS R_513 ( .D(n2287), .CK(clk), .SN(n5649), .Q(n5961) ); DFFSX2TS R_704 ( .D(n2553), .CK(clk), .SN(n5657), .Q(n5846) ); DFFRHQX4TS EXP_STAGE_DmP_Q_reg_8_ ( .D(n1294), .CK(clk), .RN(n2532), .Q( n2312) ); DFFSX2TS R_304 ( .D(n6312), .CK(clk), .SN(n5677), .Q(n6110) ); DFFRHQX2TS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1130), .CK(clk), .RN(n6257), .Q(n2307) ); DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_49_ ( .D(n1021), .CK(clk), .RN(n2512), .Q( DmP_mant_SFG_SWR[49]), .QN(n5549) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_45_ ( .D(n1220), .CK(clk), .RN(n6233), .Q( DmP_EXP_EWSW[45]) ); DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1174), .CK(clk), .RN(n6291), .Q(n2300) ); DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_45_ ( .D(n1025), .CK(clk), .RN(n6239), .Q(n2298) ); DFFSX2TS R_252 ( .D(n6371), .CK(clk), .SN(n5639), .Q(n6140) ); DFFRHQX8TS R_238 ( .D(n6147), .CK(clk), .RN(n2514), .Q(n2492) ); DFFSX2TS R_376 ( .D(n6342), .CK(clk), .SN(n5662), .Q(n6058) ); DFFRHQX2TS INPUT_STAGE_OPERANDY_Q_reg_53_ ( .D(n1675), .CK(clk), .RN(n6279), .Q(n2292) ); DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1047), .CK(clk), .RN(n6237), .Q( DmP_mant_SFG_SWR[23]) ); DFFSX4TS R_983 ( .D(n5686), .CK(clk), .SN(n2515), .Q(n2488), .QN(n5864) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_52_ ( .D(n1365), .CK(clk), .RN(n6271), .QN( n5407) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_53_ ( .D(n1360), .CK(clk), .RN(n6271), .QN( n5406) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_54_ ( .D(n1355), .CK(clk), .RN(n6272), .QN( n5405) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_55_ ( .D(n1350), .CK(clk), .RN(n6272), .QN( n5404) ); DFFRX1TS SHT1_STAGE_DMP_Q_reg_56_ ( .D(n1345), .CK(clk), .RN(n6273), .QN( n5403) ); DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_46_ ( .D(n1217), .CK(clk), .RN(n6262), .Q(DmP_mant_SHT1_SW[46]) ); DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_40_ ( .D(n1229), .CK(clk), .RN(n6261), .Q(DmP_mant_SHT1_SW[40]) ); DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_36_ ( .D(n1237), .CK(clk), .RN(n5683), .Q(DmP_mant_SHT1_SW[36]) ); DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_34_ ( .D(n1241), .CK(clk), .RN(n5683), .Q(DmP_mant_SHT1_SW[34]) ); DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_33_ ( .D(n1243), .CK(clk), .RN(n2567), .Q(DmP_mant_SHT1_SW[33]) ); DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_31_ ( .D(n1247), .CK(clk), .RN(n5683), .Q(DmP_mant_SHT1_SW[31]) ); DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_23_ ( .D(n1263), .CK(clk), .RN(n2568), .Q(DmP_mant_SHT1_SW[23]) ); DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1273), .CK(clk), .RN(n2542), .Q(DmP_mant_SHT1_SW[18]) ); DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1267), .CK(clk), .RN(n6264), .Q(DmP_mant_SHT1_SW[21]) ); DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_30_ ( .D(n1249), .CK(clk), .RN(n5683), .Q(DmP_mant_SHT1_SW[30]) ); DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_24_ ( .D(n1261), .CK(clk), .RN(n6263), .Q(DmP_mant_SHT1_SW[24]) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1082), .CK(clk), .RN(n6234), .Q( final_result_ieee[29]), .QN(n5539) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1091), .CK(clk), .RN(n6235), .Q( final_result_ieee[7]), .QN(n5528) ); DFFRXLTS R_688 ( .D(n6210), .CK(clk), .RN(n5634), .Q(n5854) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_32_ ( .D(n1555), .CK(clk), .RN(n6248), .Q( DMP_EXP_EWSW[32]) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_30_ ( .D(n1557), .CK(clk), .RN(n6247), .Q( DMP_EXP_EWSW[30]) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_0_ ( .D(n1310), .CK(clk), .RN(n2543), .Q( DmP_EXP_EWSW[0]) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_37_ ( .D(n1550), .CK(clk), .RN(n6286), .Q( DMP_EXP_EWSW[37]) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n1561), .CK(clk), .RN(n6246), .Q( DMP_EXP_EWSW[26]) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_50_ ( .D(n1210), .CK(clk), .RN(n6265), .Q( DmP_EXP_EWSW[50]) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_38_ ( .D(n1234), .CK(clk), .RN(n5671), .Q( DmP_EXP_EWSW[38]) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n1260), .CK(clk), .RN(n6263), .Q( DmP_EXP_EWSW[25]) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_13_ ( .D(n1574), .CK(clk), .RN(n6270), .Q( DMP_EXP_EWSW[13]) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_40_ ( .D(n1230), .CK(clk), .RN(n6261), .Q( DmP_EXP_EWSW[40]) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_49_ ( .D(n1212), .CK(clk), .RN(n6257), .Q( DmP_EXP_EWSW[49]) ); DFFRXLTS EXP_STAGE_DmP_Q_reg_34_ ( .D(n1242), .CK(clk), .RN(n5683), .Q( DmP_EXP_EWSW[34]) ); DFFRXLTS EXP_STAGE_DmP_Q_reg_29_ ( .D(n1252), .CK(clk), .RN(n6262), .Q( DmP_EXP_EWSW[29]) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_6_ ( .D(n1581), .CK(clk), .RN(n6263), .Q( DMP_EXP_EWSW[6]) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_1_ ( .D(n1586), .CK(clk), .RN(n6236), .Q( DMP_EXP_EWSW[1]) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_12_ ( .D(n1575), .CK(clk), .RN(n6264), .Q( DMP_EXP_EWSW[12]) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n1258), .CK(clk), .RN(n6286), .Q( DmP_EXP_EWSW[26]) ); DFFRX4TS R_809 ( .D(n6219), .CK(clk), .RN(n5684), .Q(n5787) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n1264), .CK(clk), .RN(n2566), .Q( DmP_EXP_EWSW[23]) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_41_ ( .D(n1546), .CK(clk), .RN(n6250), .Q( DMP_EXP_EWSW[41]) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_12_ ( .D(n1286), .CK(clk), .RN(n6256), .Q( DmP_EXP_EWSW[12]) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_35_ ( .D(n1552), .CK(clk), .RN(n1880), .Q( DMP_EXP_EWSW[35]) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_11_ ( .D(n1576), .CK(clk), .RN(n6265), .Q( DMP_EXP_EWSW[11]) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_7_ ( .D(n1580), .CK(clk), .RN(n6265), .Q( DMP_EXP_EWSW[7]) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_56_ ( .D(n1202), .CK(clk), .RN(n6270), .Q( DmP_EXP_EWSW[56]), .QN(n5488) ); DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1522), .CK(clk), .RN(n5633), .Q( SIGN_FLAG_EXP) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_19_ ( .D(n1272), .CK(clk), .RN(n5670), .Q( DmP_EXP_EWSW[19]) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_13_ ( .D(n1284), .CK(clk), .RN(n6256), .Q( DmP_EXP_EWSW[13]) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_1_ ( .D(n1308), .CK(clk), .RN(n2543), .Q( DmP_EXP_EWSW[1]) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_36_ ( .D(n1551), .CK(clk), .RN(n6233), .Q( DMP_EXP_EWSW[36]) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_9_ ( .D(n1292), .CK(clk), .RN(n2532), .Q( DmP_EXP_EWSW[9]) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n1256), .CK(clk), .RN(n6266), .Q( DmP_EXP_EWSW[27]) ); DFFSX2TS R_443 ( .D(n3046), .CK(clk), .SN(n5634), .Q(n6010) ); DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1108), .CK(clk), .RN(n6234), .Q( final_result_ieee[23]), .QN(n5533) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_44_ ( .D(n1543), .CK(clk), .RN(n6251), .Q( DMP_EXP_EWSW[44]) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_51_ ( .D(n1208), .CK(clk), .RN(n6260), .Q( DmP_EXP_EWSW[51]) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_10_ ( .D(n1577), .CK(clk), .RN(n6261), .Q( DMP_EXP_EWSW[10]) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_5_ ( .D(n1300), .CK(clk), .RN(n5668), .Q( DmP_EXP_EWSW[5]) ); DFFRHQX2TS EXP_STAGE_DMP_Q_reg_19_ ( .D(n1568), .CK(clk), .RN(n6243), .Q( n2259) ); DFFRHQX8TS R_625 ( .D(n6147), .CK(clk), .RN(n2514), .Q(n2257) ); DFFRHQX2TS EXP_STAGE_DmP_Q_reg_18_ ( .D(n1274), .CK(clk), .RN(n2540), .Q( n2256) ); DFFRHQX2TS EXP_STAGE_DMP_Q_reg_21_ ( .D(n1566), .CK(clk), .RN(n6244), .Q( n2255) ); DFFSX2TS R_411 ( .D(n6220), .CK(clk), .SN(n5663), .Q(n6033) ); DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1178), .CK(clk), .RN(n6236), .Q(n2252) ); DFFRHQX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1703), .CK(clk), .RN(n5635), .Q(n2250) ); DFFSX2TS R_991 ( .D(n3582), .CK(clk), .SN(n5659), .Q(n2249) ); DFFSX2TS R_992 ( .D(n3583), .CK(clk), .SN(n5659), .Q(n2248) ); DFFSX2TS R_993 ( .D(n3581), .CK(clk), .SN(n5659), .Q(n2247) ); DFFSX2TS R_994 ( .D(n2690), .CK(clk), .SN(n5619), .Q(n2246) ); DFFRX2TS R_995 ( .D(n5183), .CK(clk), .RN(n5619), .Q(n2245) ); DFFSX2TS R_996 ( .D(n6215), .CK(clk), .SN(n4463), .Q(n2244) ); DFFSX2TS R_997 ( .D(n3616), .CK(clk), .SN(n5618), .Q(n2243) ); DFFSX2TS R_998 ( .D(n3617), .CK(clk), .SN(n5621), .Q(n2242) ); DFFSX2TS R_999 ( .D(n3615), .CK(clk), .SN(n6232), .Q(n2241) ); DFFSX2TS R_1000 ( .D(n3598), .CK(clk), .SN(n1881), .Q(n2240) ); DFFSX2TS R_1001 ( .D(n3599), .CK(clk), .SN(n1882), .Q(n2239) ); DFFSX2TS R_1002 ( .D(n3597), .CK(clk), .SN(n1881), .Q(n2238) ); DFFSX2TS R_1003 ( .D(n4387), .CK(clk), .SN(n6259), .Q(n2237) ); DFFSX2TS R_1004 ( .D(n4388), .CK(clk), .SN(n6259), .Q(n2236) ); DFFSX2TS R_1005 ( .D(n4386), .CK(clk), .SN(n6259), .Q(n2235) ); DFFSX1TS R_299 ( .D(n6358), .CK(clk), .SN(n5646), .Q(n6115) ); DFFSX2TS R_575 ( .D(n6226), .CK(clk), .SN(n5665), .Q(n5933) ); DFFSX4TS R_502 ( .D(n6200), .CK(clk), .SN(n5631), .Q(n5967) ); DFFSX2TS R_719 ( .D(n6227), .CK(clk), .SN(n5651), .Q(n5835) ); DFFSX4TS R_583 ( .D(n1906), .CK(clk), .SN(n5626), .Q(n5928) ); DFFSX1TS R_121 ( .D(n6347), .CK(clk), .SN(n5654), .Q(n6177) ); DFFSX2TS R_442 ( .D(n5612), .CK(clk), .SN(n5672), .QN(n2227) ); DFFSX2TS R_465 ( .D(n2498), .CK(clk), .SN(n5656), .QN(n2221) ); DFFSX1TS R_405 ( .D(n6224), .CK(clk), .SN(n5640), .Q(n6037) ); DFFSX4TS R_372 ( .D(n2301), .CK(clk), .SN(n5681), .QN(n2438) ); DFFSX1TS R_280 ( .D(n6403), .CK(clk), .SN(n5625), .Q(n6125) ); DFFSX1TS R_427 ( .D(n2528), .CK(clk), .SN(n5655), .Q(n6021) ); DFFSX1TS R_397 ( .D(n2498), .CK(clk), .SN(n2521), .Q(n6043) ); DFFSX2TS R_398 ( .D(n5415), .CK(clk), .SN(n2514), .Q(n6042) ); DFFSX1TS R_715 ( .D(n2556), .CK(clk), .SN(n5680), .Q(n5837) ); DFFSX1TS R_358 ( .D(n6222), .CK(clk), .SN(n5631), .Q(n6070) ); DFFSX1TS R_384 ( .D(n6222), .CK(clk), .SN(n5647), .Q(n6052) ); DFFRX2TS R_1017 ( .D(n5571), .CK(clk), .RN(n5643), .Q(n2218) ); DFFSX1TS R_353 ( .D(n2528), .CK(clk), .SN(n5684), .Q(n6074) ); DFFSX1TS R_637 ( .D(n6225), .CK(clk), .SN(n5627), .Q(n5888) ); DFFSX1TS R_626 ( .D(n6225), .CK(clk), .SN(n5650), .Q(n5895) ); DFFSX1TS R_471 ( .D(n3046), .CK(clk), .SN(n5682), .Q(n5990) ); DFFSX1TS R_451 ( .D(n3046), .CK(clk), .SN(n5648), .Q(n6004) ); DFFSX1TS R_796 ( .D(n6212), .CK(clk), .SN(n5642), .Q(n5794) ); DFFSX4TS R_847 ( .D(n2553), .CK(clk), .SN(n5680), .Q(n5765) ); DFFSX1TS R_373 ( .D(n2499), .CK(clk), .SN(n5682), .Q(n6061) ); DFFSX1TS R_613 ( .D(n6222), .CK(clk), .SN(n5679), .Q(n5901) ); DFFSX2TS R_533 ( .D(n2506), .CK(clk), .SN(n5664), .Q(n5953) ); DFFRX2TS R_888 ( .D(Raw_mant_NRM_SWR[14]), .CK(clk), .RN(n5671), .Q(n5740) ); DFFSX2TS R_1027 ( .D(n6462), .CK(clk), .SN(n6292), .Q(n2214) ); DFFSX1TS R_539 ( .D(n6222), .CK(clk), .SN(n5664), .Q(n5950) ); DFFSX1TS R_433 ( .D(n6224), .CK(clk), .SN(n5631), .Q(n6016) ); DFFSX1TS R_432 ( .D(n6220), .CK(clk), .SN(n5631), .Q(n6017) ); DFFRX2TS R_928 ( .D(Raw_mant_NRM_SWR[10]), .CK(clk), .RN(n5668), .Q(n5715) ); DFFSX1TS R_706 ( .D(n6212), .CK(clk), .SN(n5657), .Q(n5844) ); DFFRX2TS R_705 ( .D(Raw_mant_NRM_SWR[41]), .CK(clk), .RN(n5653), .Q(n5845) ); DFFRX2TS R_969 ( .D(Raw_mant_NRM_SWR[33]), .CK(clk), .RN(n5659), .Q(n5692) ); DFFSX4TS R_966 ( .D(n1644), .CK(clk), .SN(n5661), .Q(n5694) ); DFFRX2TS R_1031 ( .D(n5571), .CK(clk), .RN(n6256), .Q(n2213) ); DFFSX2TS R_1032 ( .D(n2088), .CK(clk), .SN(n5619), .Q(n2212) ); DFFSX2TS R_1034 ( .D(n2509), .CK(clk), .SN(n5619), .Q(n2211) ); DFFSX2TS R_949 ( .D(n2497), .CK(clk), .SN(n5667), .Q(n5703) ); DFFSX1TS R_563 ( .D(n6225), .CK(clk), .SN(n5673), .Q(n5941) ); DFFSX2TS R_679 ( .D(n2500), .CK(clk), .SN(n5682), .Q(n5858) ); DFFRX2TS R_973 ( .D(DmP_mant_SHT1_SW[45]), .CK(clk), .RN(n5652), .Q(n5689) ); DFFSX2TS R_1038 ( .D(n2453), .CK(clk), .SN(n5622), .Q(n2209) ); DFFSX1TS R_547 ( .D(n2528), .CK(clk), .SN(n2568), .Q(n5947) ); DFFSX4TS R_824 ( .D(n6200), .CK(clk), .SN(n5666), .Q(n5778) ); DFFSX2TS R_891 ( .D(n2501), .CK(clk), .SN(n5666), .Q(n5738) ); DFFSX2TS R_1041 ( .D(n2088), .CK(clk), .SN(n5618), .Q(n2208) ); DFFSX1TS R_529 ( .D(n6225), .CK(clk), .SN(n5656), .Q(n5955) ); DFFRXLTS R_873 ( .D(Raw_mant_NRM_SWR[6]), .CK(clk), .RN(n5668), .Q(n5749) ); DFFSX4TS R_829 ( .D(n1823), .CK(clk), .SN(n5676), .Q(n5775) ); DFFRX4TS R_1044 ( .D(DmP_mant_SHT1_SW[44]), .CK(clk), .RN(n5652), .Q(n2206) ); DFFSX2TS R_1045 ( .D(n5345), .CK(clk), .SN(n5650), .Q(n2205) ); DFFSX2TS R_1046 ( .D(n5492), .CK(clk), .SN(n2567), .Q(n2204) ); DFFSX2TS R_1047 ( .D(n6396), .CK(clk), .SN(n5654), .Q(n2203) ); DFFRX4TS R_1048 ( .D(n2873), .CK(clk), .RN(n5628), .Q(n2202) ); DFFRX4TS R_1049 ( .D(DmP_mant_SHT1_SW[29]), .CK(clk), .RN(n5675), .Q(n2201) ); DFFRX4TS R_1050 ( .D(DmP_mant_SHT1_SW[46]), .CK(clk), .RN(n5644), .Q(n2200) ); DFFRX4TS R_1051 ( .D(DmP_mant_SHT1_SW[40]), .CK(clk), .RN(n5659), .Q(n2199) ); DFFRX4TS R_1052 ( .D(DmP_mant_SHT1_SW[36]), .CK(clk), .RN(n5660), .Q(n2198) ); DFFRX4TS R_1053 ( .D(DmP_mant_SHT1_SW[34]), .CK(clk), .RN(n5643), .Q(n2197) ); DFFRX4TS R_1054 ( .D(DmP_mant_SHT1_SW[33]), .CK(clk), .RN(n5676), .Q(n2196) ); DFFRX4TS R_1055 ( .D(DmP_mant_SHT1_SW[31]), .CK(clk), .RN(n5671), .Q(n2195) ); DFFRX4TS R_1056 ( .D(DmP_mant_SHT1_SW[23]), .CK(clk), .RN(n5629), .Q(n2194) ); DFFRX4TS R_1057 ( .D(DmP_mant_SHT1_SW[18]), .CK(clk), .RN(n5633), .Q(n2193) ); DFFRX4TS R_1058 ( .D(DmP_mant_SHT1_SW[21]), .CK(clk), .RN(n5623), .Q(n2192) ); DFFSX2TS R_1060 ( .D(n5339), .CK(clk), .SN(n5630), .Q(n2190) ); DFFSX2TS R_1061 ( .D(n6207), .CK(clk), .SN(n5658), .Q(n2189), .QN(n2188) ); DFFSX2TS R_1062 ( .D(n5429), .CK(clk), .SN(n5647), .Q(n2187), .QN(n2186) ); DFFSX2TS R_1063 ( .D(n5341), .CK(clk), .SN(n5680), .Q(n2185) ); DFFSX4TS R_1064 ( .D(n5490), .CK(clk), .SN(n2520), .Q(n2184) ); DFFSX4TS R_1065 ( .D(n5424), .CK(clk), .SN(n5669), .Q(n2183), .QN(n1907) ); DFFSX2TS R_1066 ( .D(n5443), .CK(clk), .SN(n5648), .Q(n2182) ); DFFSX2TS R_1067 ( .D(n5441), .CK(clk), .SN(n5662), .Q(n2181), .QN(n2180) ); DFFSX2TS R_1068 ( .D(n5343), .CK(clk), .SN(n5679), .Q(n2179) ); DFFSX2TS R_1069 ( .D(n3371), .CK(clk), .SN(n5656), .Q(n2178), .QN(n2177) ); DFFSX2TS R_1070 ( .D(n6209), .CK(clk), .SN(n5647), .Q(n2176) ); DFFSX2TS R_1071 ( .D(n3364), .CK(clk), .SN(n5672), .Q(n2175) ); DFFSX2TS R_1073 ( .D(n5426), .CK(clk), .SN(n5673), .Q(n2173) ); DFFRX2TS R_1074 ( .D(DmP_mant_SHT1_SW[16]), .CK(clk), .RN(n5671), .Q(n2172) ); DFFRX2TS R_1075 ( .D(DmP_mant_SHT1_SW[10]), .CK(clk), .RN(n5637), .Q(n2171) ); DFFRX4TS R_1076 ( .D(DmP_mant_SHT1_SW[50]), .CK(clk), .RN(n5637), .Q(n2170) ); DFFRX4TS R_1078 ( .D(DmP_mant_SHT1_SW[38]), .CK(clk), .RN(n5644), .Q(n2168) ); DFFRX4TS R_1079 ( .D(DmP_mant_SHT1_SW[25]), .CK(clk), .RN(n5675), .Q(n2167) ); DFFRX2TS R_1080 ( .D(DmP_mant_SHT1_SW[14]), .CK(clk), .RN(n5645), .Q(n2166) ); DFFRX2TS R_1081 ( .D(DmP_mant_SHT1_SW[12]), .CK(clk), .RN(n5653), .Q(n2165) ); DFFRX2TS R_1082 ( .D(DmP_mant_SHT1_SW[9]), .CK(clk), .RN(n5637), .Q(n2164) ); DFFRX4TS R_1083 ( .D(DmP_mant_SHT1_SW[17]), .CK(clk), .RN(n5648), .Q(n2163) ); DFFRX2TS R_1084 ( .D(DmP_mant_SHT1_SW[48]), .CK(clk), .RN(n5629), .Q(n2162) ); DFFRX2TS R_1085 ( .D(DmP_mant_SHT1_SW[32]), .CK(clk), .RN(n5671), .Q(n2161) ); DFFRX2TS R_1086 ( .D(DmP_mant_SHT1_SW[6]), .CK(clk), .RN(n5633), .Q(n2160) ); DFFSX2TS R_1087 ( .D(n5428), .CK(clk), .SN(n5657), .Q(n2159) ); DFFSX2TS R_1088 ( .D(n6231), .CK(clk), .SN(n5673), .Q(n2158) ); DFFSX2TS R_1089 ( .D(n6216), .CK(clk), .SN(n5646), .Q(n2157) ); DFFRX2TS R_1090 ( .D(DmP_mant_SHT1_SW[11]), .CK(clk), .RN(n5645), .Q(n2156), .QN(n2155) ); DFFRX4TS R_1092 ( .D(n6228), .CK(clk), .RN(n5676), .Q(n2153) ); DFFSX2TS R_1093 ( .D(n5431), .CK(clk), .SN(n5682), .Q(n2152) ); DFFSX2TS R_1094 ( .D(n5580), .CK(clk), .SN(n5656), .Q(n2151) ); DFFSX2TS R_1095 ( .D(n5579), .CK(clk), .SN(n5642), .Q(n2150) ); DFFRX2TS R_1096 ( .D(n6446), .CK(clk), .RN(n5618), .Q(n2149) ); DFFSX2TS R_1097 ( .D(n5425), .CK(clk), .SN(n5655), .Q(n2148) ); DFFSX2TS R_1098 ( .D(n5572), .CK(clk), .SN(n5676), .Q(n2147), .QN(n2146) ); DFFRX2TS R_1099 ( .D(n6452), .CK(clk), .RN(n5618), .Q(n2145) ); DFFRX2TS R_1100 ( .D(n6443), .CK(clk), .RN(n2512), .Q(n2144) ); DFFSX2TS R_1102 ( .D(n5442), .CK(clk), .SN(n5674), .Q(n2143), .QN(n2142) ); DFFSX2TS R_1103 ( .D(n5437), .CK(clk), .SN(n5665), .Q(n2141) ); DFFRX2TS R_1105 ( .D(n2572), .CK(clk), .RN(n5638), .Q(n2138) ); DFFRX2TS R_1106 ( .D(DmP_mant_SHT1_SW[8]), .CK(clk), .RN(n5653), .Q(n2137), .QN(n2136) ); DFFRX4TS R_1107 ( .D(DmP_mant_SHT1_SW[2]), .CK(clk), .RN(n5653), .Q(n2135) ); DFFRX2TS R_1108 ( .D(DmP_mant_SHT1_SW[26]), .CK(clk), .RN(n5623), .Q(n2134) ); DFFRX4TS R_1110 ( .D(DmP_mant_SHT1_SW[42]), .CK(clk), .RN(n5638), .Q(n2132) ); DFFRX4TS R_1111 ( .D(DmP_mant_SHT1_SW[43]), .CK(clk), .RN(n5637), .Q(n2131) ); DFFRX4TS R_1112 ( .D(DmP_mant_SHT1_SW[47]), .CK(clk), .RN(n5629), .Q(n2130) ); DFFSX2TS R_1113 ( .D(n2527), .CK(clk), .SN(n5650), .Q(n2129) ); DFFRX2TS R_1114 ( .D(DmP_mant_SHT1_SW[27]), .CK(clk), .RN(n5676), .Q(n2128), .QN(n1903) ); DFFRX2TS R_1115 ( .D(DmP_mant_SHT1_SW[13]), .CK(clk), .RN(n6256), .Q(n2127) ); DFFRX4TS R_1116 ( .D(DmP_mant_SHT1_SW[30]), .CK(clk), .RN(n5675), .Q(n2126) ); DFFRX2TS R_1117 ( .D(DmP_mant_SHT1_SW[24]), .CK(clk), .RN(n5624), .Q(n2125) ); DFFSX2TS R_1120 ( .D(n2253), .CK(clk), .SN(n5663), .Q(n2124) ); DFFRHQX2TS EXP_STAGE_DMP_Q_reg_40_ ( .D(n1547), .CK(clk), .RN(n2540), .Q( n2123) ); DFFRHQX2TS EXP_STAGE_DMP_Q_reg_43_ ( .D(n1544), .CK(clk), .RN(n6250), .Q( n2122) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_3_ ( .D(n1304), .CK(clk), .RN(n5668), .Q( DmP_EXP_EWSW[3]) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_44_ ( .D(n1222), .CK(clk), .RN(n6287), .Q( DmP_EXP_EWSW[44]) ); DFFRHQX2TS FRMT_STAGE_DATAOUT_Q_reg_45_ ( .D(n1077), .CK(clk), .RN(n2520), .Q(final_result_ieee[45]) ); DFFSX2TS R_960 ( .D(n6200), .CK(clk), .SN(n5649), .Q(n5697) ); DFFRX4TS SGF_STAGE_DMP_Q_reg_26_ ( .D(n1441), .CK(clk), .RN(n6245), .Q( DMP_SFG[26]), .QN(n5472) ); DFFSX4TS R_414 ( .D(n5583), .CK(clk), .SN(n5663), .Q(n6030) ); DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_47_ ( .D(n1023), .CK(clk), .RN(n2512), .Q( DmP_mant_SFG_SWR[47]), .QN(n5551) ); DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1050), .CK(clk), .RN(n6237), .Q( DmP_mant_SFG_SWR[20]), .QN(n5565) ); DFFRX4TS SGF_STAGE_DMP_Q_reg_27_ ( .D(n1438), .CK(clk), .RN(n6246), .Q( DMP_SFG[27]), .QN(n5516) ); DFFSX4TS R_810 ( .D(n2496), .CK(clk), .SN(n5685), .Q(n5786) ); DFFSX4TS R_1059 ( .D(n6221), .CK(clk), .SN(n6291), .Q(n2191) ); DFFSX2TS R_579 ( .D(n6226), .CK(clk), .SN(n5674), .Q(n5930) ); DFFSX4TS R_1104 ( .D(n5412), .CK(clk), .SN(n6290), .Q(n2140), .QN(n2139) ); DFFRX4TS R_1077 ( .D(DmP_mant_SHT1_SW[19]), .CK(clk), .RN(n2540), .Q(n2169) ); DFFRX4TS R_731 ( .D(Raw_mant_NRM_SWR[9]), .CK(clk), .RN(n5660), .QN(n2410) ); DFFSX4TS R_651 ( .D(n6226), .CK(clk), .SN(n5665), .Q(n5878) ); DFFRX4TS R_1109 ( .D(DmP_mant_SHT1_SW[35]), .CK(clk), .RN(n5661), .Q(n2133) ); DFFSX2TS R_377 ( .D(n6341), .CK(clk), .SN(n5662), .Q(n6057) ); DFFSX4TS R_953 ( .D(n6200), .CK(clk), .SN(n6290), .Q(n5701) ); DFFSX4TS R_1014 ( .D(n6221), .CK(clk), .SN(n5656), .Q(n2233), .QN(n1902) ); DFFRHQX4TS INPUT_STAGE_OPERANDY_Q_reg_45_ ( .D(n1683), .CK(clk), .RN(n6278), .Q(n2299) ); DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1053), .CK(clk), .RN(n6237), .Q( DmP_mant_SFG_SWR[17]) ); DFFSX2TS R_459 ( .D(n3046), .CK(clk), .SN(n5649), .Q(n5997) ); DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1478), .CK(clk), .RN(n6241), .Q( DMP_SHT2_EWSW[14]), .QN(n5396) ); DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1463), .CK(clk), .RN(n6243), .Q( DMP_SHT2_EWSW[19]), .QN(n5391) ); DFFRXLTS SHT2_STAGE_DMP_Q_reg_36_ ( .D(n1412), .CK(clk), .RN(n1881), .Q( DMP_SHT2_EWSW[36]), .QN(n5374) ); DFFRXLTS SHT2_STAGE_DMP_Q_reg_42_ ( .D(n1394), .CK(clk), .RN(n6250), .Q( DMP_SHT2_EWSW[42]), .QN(n5371) ); DFFRXLTS SHT2_STAGE_DMP_Q_reg_47_ ( .D(n1379), .CK(clk), .RN(n6252), .Q( DMP_SHT2_EWSW[47]), .QN(n5366) ); DFFRXLTS SHT2_STAGE_DMP_Q_reg_54_ ( .D(n1354), .CK(clk), .RN(n6272), .QN( n5499) ); DFFRXLTS SHT2_STAGE_DMP_Q_reg_59_ ( .D(n1329), .CK(clk), .RN(n6275), .Q( DMP_SHT2_EWSW[59]), .QN(n5358) ); DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1188), .CK(clk), .RN(n6253), .Q( SIGN_FLAG_SHT2), .QN(n5397) ); DFFRXLTS R_285 ( .D(n6408), .CK(clk), .RN(n2511), .Q(n6122) ); DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n1196), .CK(clk), .RN(n2541), .Q( ZERO_FLAG_SFG), .QN(n5410) ); DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1297), .CK(clk), .RN(n5668), .Q(DmP_mant_SHT1_SW[6]) ); DFFRHQX2TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n1453), .CK(clk), .RN(n6292), .Q( DMP_SFG[22]) ); DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_27_ ( .D(n1043), .CK(clk), .RN(n6238), .Q( DmP_mant_SFG_SWR[27]), .QN(n5519) ); DFFSX2TS R_592 ( .D(DmP_mant_SHT1_SW[37]), .CK(clk), .SN(n5627), .Q(n5919) ); DFFRXLTS R_799 ( .D(n6461), .CK(clk), .RN(n2520), .Q(n5793) ); DFFSX1TS R_700 ( .D(n2287), .CK(clk), .SN(n5680), .Q(n5849) ); DFFRXLTS R_578 ( .D(DmP_mant_SHT1_SW[3]), .CK(clk), .RN(n5629), .Q(n5931) ); DFFSX1TS R_374 ( .D(n5610), .CK(clk), .SN(n5682), .Q(n6060) ); DFFRX1TS R_908 ( .D(Raw_mant_NRM_SWR[37]), .CK(clk), .RN(n5652), .Q(n5729) ); DFFRHQX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1285), .CK(clk), .RN(n6259), .Q(DmP_mant_SHT1_SW[12]) ); DFFRX4TS EXP_STAGE_DmP_Q_reg_20_ ( .D(n1270), .CK(clk), .RN(n6259), .Q( DmP_EXP_EWSW[20]) ); DFFRXLTS R_661 ( .D(n6201), .CK(clk), .RN(n6259), .Q(n5871) ); DFFRXLTS R_904 ( .D(n6437), .CK(clk), .RN(n6259), .Q(n5732) ); DFFRHQX2TS EXP_STAGE_DmP_Q_reg_11_ ( .D(n1288), .CK(clk), .RN(n6256), .Q( n1864) ); DFFSX2TS R_142 ( .D(n6404), .CK(clk), .SN(n5625), .Q(n6170) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_16_ ( .D(n1571), .CK(clk), .RN(n6242), .Q( DMP_EXP_EWSW[16]) ); DFFRHQX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1126), .CK(clk), .RN(n5633), .Q(n1856) ); DFFRXLTS EXP_STAGE_DmP_Q_reg_48_ ( .D(n1214), .CK(clk), .RN(n6260), .Q( DmP_EXP_EWSW[48]) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_4_ ( .D(n1583), .CK(clk), .RN(n6266), .Q( DMP_EXP_EWSW[4]) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_22_ ( .D(n1565), .CK(clk), .RN(n6244), .Q( DMP_EXP_EWSW[22]) ); DFFSX2TS R_879 ( .D(n2287), .CK(clk), .SN(n5671), .QN(n1844) ); DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1051), .CK(clk), .RN(n6237), .Q(n1840) ); DFFRX4TS EXP_STAGE_DMP_Q_reg_14_ ( .D(n1573), .CK(clk), .RN(n6241), .Q( DMP_EXP_EWSW[14]) ); DFFSX4TS R_696 ( .D(n2501), .CK(clk), .SN(n5642), .Q(n5851) ); DFFRX4TS R_595 ( .D(n6323), .CK(clk), .RN(n5624), .Q(n5916) ); DFFSX4TS R_857 ( .D(n2015), .CK(clk), .SN(n6240), .Q(n5758) ); DFFSX4TS R_929 ( .D(n6200), .CK(clk), .SN(n5669), .Q(n5714) ); DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1275), .CK(clk), .RN(n2541), .Q(DmP_mant_SHT1_SW[17]) ); DFFRHQX2TS EXP_STAGE_DmP_Q_reg_14_ ( .D(n1282), .CK(clk), .RN(n2545), .Q( n2313) ); DFFRHQX2TS EXP_STAGE_DMP_Q_reg_2_ ( .D(n1585), .CK(clk), .RN(n2540), .Q( n2276) ); DFFRX4TS R_930 ( .D(DmP_mant_SHT1_SW[39]), .CK(clk), .RN(n5669), .Q(n5713) ); DFFRX4TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n1471), .CK(clk), .RN(n6241), .QN( n5478) ); DFFRHQX8TS SHT2_STAGE_SHFTVARS1_Q_reg_5_ ( .D(n1605), .CK(clk), .RN(n6269), .Q(n2330) ); DFFSX4TS R_1072 ( .D(n5438), .CK(clk), .SN(n5666), .Q(n2174) ); DFFSX2TS R_328 ( .D(n6361), .CK(clk), .SN(n5647), .Q(n6092) ); DFFSX4TS R_509 ( .D(n2287), .CK(clk), .SN(n5629), .Q(n5964) ); DFFSX2TS R_327 ( .D(n6362), .CK(clk), .SN(n5647), .Q(n6093) ); DFFSX4TS R_887 ( .D(n2287), .CK(clk), .SN(n5679), .Q(n5741) ); DFFSX4TS R_856 ( .D(n6213), .CK(clk), .SN(n2514), .Q(n5759) ); DFFRHQX4TS R_984 ( .D(n6147), .CK(clk), .RN(n2515), .Q(n1839) ); DFFRHQX4TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1723), .CK(clk), .RN(n2539), .Q(n2295) ); DFFRHQX4TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1727), .CK(clk), .RN(n6262), .Q(n2310) ); DFFSX2TS R_860 ( .D(n6204), .CK(clk), .SN(n5632), .Q(n5756) ); DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_42_ ( .D(n1028), .CK(clk), .RN(n6239), .Q( DmP_mant_SFG_SWR[42]), .QN(n5560) ); DFFRX2TS R_848 ( .D(Raw_mant_NRM_SWR[16]), .CK(clk), .RN(n5676), .Q(n5764) ); DFFRX2TS R_823 ( .D(DmP_mant_SHT1_SW[37]), .CK(clk), .RN(n5660), .Q(n5779) ); DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1316), .CK(clk), .RN(n2569), .Q( DMP_exp_NRM2_EW[9]) ); DFFSX2TS R_933 ( .D(n6200), .CK(clk), .SN(n5680), .Q(n5711) ); DFFSX2TS R_683 ( .D(n2508), .CK(clk), .SN(n6234), .Q(n5856) ); DFFSX2TS R_379 ( .D(n6222), .CK(clk), .SN(n5669), .Q(n6056) ); DFFSX2TS R_472 ( .D(n5581), .CK(clk), .SN(n5682), .Q(n5989) ); DFFSX2TS R_474 ( .D(n5588), .CK(clk), .SN(n5682), .Q(n5987) ); DFFSX1TS R_617 ( .D(n6227), .CK(clk), .SN(n5682), .Q(n5899) ); DFFSX1TS R_854 ( .D(n2508), .CK(clk), .SN(n2521), .Q(n5760) ); DFFSX1TS R_833 ( .D(n2508), .CK(clk), .SN(n5681), .Q(n5772) ); DFFSX2TS R_899 ( .D(n2506), .CK(clk), .SN(n5684), .Q(n5734) ); DFFSX1TS R_770 ( .D(n6227), .CK(clk), .SN(n6236), .Q(n5806) ); DFFRX2TS R_912 ( .D(DmP_mant_SHT1_SW[51]), .CK(clk), .RN(n5644), .Q(n5726) ); DFFRX2TS R_712 ( .D(Raw_mant_NRM_SWR[36]), .CK(clk), .RN(n5651), .Q(n5840) ); DFFSX1TS R_666 ( .D(n2556), .CK(clk), .SN(n5642), .Q(n5866) ); DFFSX2TS R_609 ( .D(n6227), .CK(clk), .SN(n5679), .Q(n5903) ); DFFSX1TS R_943 ( .D(n2508), .CK(clk), .SN(n5678), .Q(n5707) ); DFFSX2TS R_551 ( .D(n6201), .CK(clk), .SN(n5626), .Q(n5944) ); DFFSX2TS R_1091 ( .D(n5569), .CK(clk), .SN(n2542), .Q(n2154), .QN(n1843) ); DFFRX2TS R_880 ( .D(Raw_mant_NRM_SWR[30]), .CK(clk), .RN(n5644), .QN(n1845) ); DFFRX2TS R_514 ( .D(n2037), .CK(clk), .RN(n5645), .Q(n5960) ); DFFRX2TS R_830 ( .D(n1825), .CK(clk), .RN(n5663), .Q(n5774) ); DFFRX2TS R_747 ( .D(n1986), .CK(clk), .RN(n5634), .Q(n5818) ); DFFSX2TS R_356 ( .D(n5614), .CK(clk), .SN(n5684), .Q(n6072) ); DFFSX2TS R_721 ( .D(n6227), .CK(clk), .SN(n5642), .Q(n5834) ); DFFSX2TS R_675 ( .D(n6227), .CK(clk), .SN(n5650), .Q(n5860) ); DFFSX1TS R_681 ( .D(n2523), .CK(clk), .SN(n5682), .Q(n5857) ); DFFSX1TS R_545 ( .D(n2508), .CK(clk), .SN(n2568), .Q(n5948) ); DFFSX1TS R_581 ( .D(n6201), .CK(clk), .SN(n5674), .Q(n5929) ); DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1311), .CK(clk), .RN(n6255), .Q(DMP_exp_NRM2_EW[10]) ); DFFRX2TS R_1043 ( .D(DmP_mant_SHT1_SW[15]), .CK(clk), .RN(n5637), .Q(n2207) ); DFFSX1TS R_286 ( .D(n6407), .CK(clk), .SN(n2512), .Q(n6121) ); DFFSX1TS R_812 ( .D(n2497), .CK(clk), .SN(n5636), .Q(n5785) ); DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_54_ ( .D(n1016), .CK(clk), .RN(n2511), .Q( DmP_mant_SFG_SWR[54]) ); DFFRHQX2TS EXP_STAGE_DMP_Q_reg_60_ ( .D(n1527), .CK(clk), .RN(n6465), .Q( n2303) ); DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_42_ ( .D(n1225), .CK(clk), .RN(n6465), .Q(DmP_mant_SHT1_SW[42]), .QN(n5415) ); NOR2BX1TS U1842 ( .AN(n2018), .B(n2990), .Y(n2509) ); INVX2TS U1843 ( .A(n3261), .Y(n1915) ); OAI2BB1X1TS U1844 ( .A0N(n5149), .A1N(n6441), .B0(n5148), .Y(n1036) ); NAND2X6TS U1845 ( .A(n2925), .B(Raw_mant_NRM_SWR[18]), .Y(n6320) ); NAND2X1TS U1846 ( .A(n6204), .B(DmP_mant_SHT1_SW[3]), .Y(n6394) ); BUFX8TS U1847 ( .A(n5032), .Y(n6223) ); NAND2X1TS U1848 ( .A(n3124), .B(intDY_EWSW[38]), .Y(n3617) ); INVX8TS U1849 ( .A(n1906), .Y(n2556) ); CLKINVX2TS U1850 ( .A(n1879), .Y(n1882) ); CLKINVX2TS U1851 ( .A(n1879), .Y(n1881) ); OAI21X2TS U1852 ( .A0(n4617), .A1(n5216), .B0(n1826), .Y(n1021) ); NAND2X6TS U1853 ( .A(n2495), .B(Raw_mant_NRM_SWR[1]), .Y(n6333) ); NAND2X2TS U1854 ( .A(n4863), .B(intDX_EWSW[34]), .Y(n3598) ); MXI2X2TS U1855 ( .A(n5290), .B(n5558), .S0(n1868), .Y(n1020) ); CLKMX2X3TS U1856 ( .A(Data_Y[38]), .B(intDY_EWSW[38]), .S0(n5235), .Y(n1690) ); BUFX12TS U1857 ( .A(n2925), .Y(n1823) ); AND2X2TS U1858 ( .A(n3261), .B(n2012), .Y(n2441) ); NAND2X4TS U1859 ( .A(n2984), .B(n5127), .Y(n1016) ); CLKINVX2TS U1860 ( .A(n1879), .Y(n1880) ); MXI2X1TS U1861 ( .A(n5251), .B(n5250), .S0(n2554), .Y(n1105) ); NAND3X2TS U1862 ( .A(n3660), .B(n3661), .C(n3659), .Y(n1525) ); NAND2X2TS U1863 ( .A(n4545), .B(n4544), .Y(n1052) ); NAND3X4TS U1864 ( .A(n4441), .B(n4442), .C(n4440), .Y(n1575) ); NAND3X4TS U1865 ( .A(n4399), .B(n4398), .C(n4397), .Y(n1536) ); MXI2X1TS U1866 ( .A(n2989), .B(n4303), .S0(n2505), .Y(n1134) ); NAND3X2TS U1867 ( .A(n4402), .B(n4401), .C(n4400), .Y(n1582) ); NAND3X2TS U1868 ( .A(n3817), .B(n3818), .C(n3816), .Y(n1288) ); INVX12TS U1869 ( .A(n3261), .Y(n6213) ); NAND2X2TS U1870 ( .A(n2531), .B(n2295), .Y(n4402) ); NAND2X2TS U1871 ( .A(n4807), .B(n2026), .Y(n3690) ); NAND2X2TS U1872 ( .A(n2049), .B(intDX_EWSW[53]), .Y(n4367) ); NAND2X2TS U1873 ( .A(n6449), .B(n5123), .Y(n4508) ); NAND2X2TS U1874 ( .A(n4863), .B(intDX_EWSW[12]), .Y(n4441) ); NAND2X1TS U1875 ( .A(n1836), .B(intDX_EWSW[11]), .Y(n3818) ); CLKINVX2TS U1876 ( .A(n2527), .Y(n1873) ); OR2X6TS U1877 ( .A(n3266), .B(n2439), .Y(n3285) ); NAND2X1TS U1878 ( .A(n6443), .B(n4543), .Y(n4481) ); INVX4TS U1879 ( .A(n4332), .Y(n5041) ); AND2X6TS U1880 ( .A(n2500), .B(DmP_mant_SHT1_SW[28]), .Y(n2428) ); NAND2X1TS U1881 ( .A(n1838), .B(intDY_EWSW[19]), .Y(n3682) ); BUFX4TS U1882 ( .A(Shift_reg_FLAGS_7[0]), .Y(n5292) ); NAND2X4TS U1883 ( .A(n2648), .B(n2986), .Y(n6412) ); NAND3X1TS U1884 ( .A(n2240), .B(n2239), .C(n2238), .Y(n1553) ); NAND3X1TS U1885 ( .A(n2243), .B(n2242), .C(n2241), .Y(n1549) ); NAND3X1TS U1886 ( .A(n2237), .B(n2236), .C(n2235), .Y(n1537) ); NAND3X1TS U1887 ( .A(n2249), .B(n2248), .C(n2247), .Y(n1216) ); NAND2X2TS U1888 ( .A(n2053), .B(intDY_EWSW[11]), .Y(n3817) ); NAND2X2TS U1889 ( .A(n4424), .B(n2046), .Y(n4423) ); NAND2X2TS U1890 ( .A(n2530), .B(n1923), .Y(n4442) ); NAND2X2TS U1891 ( .A(n4425), .B(intDX_EWSW[62]), .Y(n3660) ); BUFX3TS U1892 ( .A(Shift_reg_FLAGS_7[0]), .Y(n5287) ); NAND2X6TS U1893 ( .A(n2452), .B(intDX_EWSW[17]), .Y(n3669) ); NAND2X1TS U1894 ( .A(n5264), .B(DmP_mant_SFG_SWR[23]), .Y(n3063) ); NAND2XLTS U1895 ( .A(n5319), .B(n1913), .Y(n3186) ); NAND2XLTS U1896 ( .A(n5205), .B(n5428), .Y(n2907) ); NAND2XLTS U1897 ( .A(n5319), .B(Raw_mant_NRM_SWR[36]), .Y(n2903) ); NAND2X1TS U1898 ( .A(n4396), .B(DMP_EXP_EWSW[48]), .Y(n4389) ); NAND2X6TS U1899 ( .A(n2964), .B(n2049), .Y(n4809) ); INVX6TS U1900 ( .A(n1817), .Y(n1816) ); NAND2XLTS U1901 ( .A(n4853), .B(DmP_EXP_EWSW[23]), .Y(n4828) ); NAND2XLTS U1902 ( .A(n5216), .B(n3136), .Y(n3135) ); NAND2XLTS U1903 ( .A(n5245), .B(DmP_mant_SFG_SWR[8]), .Y(n3109) ); NAND2XLTS U1904 ( .A(n2554), .B(n2450), .Y(n2953) ); NAND2X1TS U1905 ( .A(n5005), .B(Raw_mant_NRM_SWR[51]), .Y(n2718) ); NOR2X6TS U1906 ( .A(n1937), .B(n1935), .Y(n3320) ); NAND2XLTS U1907 ( .A(n4864), .B(DmP_EXP_EWSW[6]), .Y(n4111) ); NAND2XLTS U1908 ( .A(n4396), .B(DMP_EXP_EWSW[41]), .Y(n3600) ); NAND2XLTS U1909 ( .A(n4396), .B(DMP_EXP_EWSW[44]), .Y(n3609) ); NAND2XLTS U1910 ( .A(n4864), .B(DmP_EXP_EWSW[5]), .Y(n4865) ); NAND2XLTS U1911 ( .A(n4864), .B(DmP_EXP_EWSW[3]), .Y(n4403) ); MX2X2TS U1912 ( .A(n6460), .B(n5561), .S0(n5224), .Y(n5142) ); NAND2X2TS U1913 ( .A(n2116), .B(n2745), .Y(n4824) ); NAND2X4TS U1914 ( .A(n2649), .B(n2669), .Y(n2668) ); BUFX3TS U1915 ( .A(n6289), .Y(n6259) ); NAND2XLTS U1916 ( .A(n2534), .B(n2313), .Y(n4307) ); AND2X4TS U1917 ( .A(n4416), .B(n2045), .Y(n2265) ); NAND2X2TS U1918 ( .A(n4430), .B(intDY_EWSW[7]), .Y(n4076) ); NAND2X4TS U1919 ( .A(n2951), .B(intDY_EWSW[48]), .Y(n4104) ); NAND2XLTS U1920 ( .A(n5005), .B(n5029), .Y(n3277) ); NAND2XLTS U1921 ( .A(n5005), .B(n2037), .Y(n3203) ); NAND2XLTS U1922 ( .A(n2012), .B(n2551), .Y(n3279) ); NAND2X2TS U1923 ( .A(n4369), .B(intDX_EWSW[40]), .Y(n3592) ); NAND2XLTS U1924 ( .A(n2535), .B(n2276), .Y(n4878) ); INVX1TS U1925 ( .A(Raw_mant_NRM_SWR[41]), .Y(n2327) ); NAND2X2TS U1926 ( .A(n2731), .B(n2730), .Y(n2729) ); MX2X4TS U1927 ( .A(n6416), .B(n5131), .S0(n2505), .Y(n5132) ); NAND2X4TS U1928 ( .A(n5124), .B(n5123), .Y(n2984) ); OR2X2TS U1929 ( .A(n3231), .B(n3877), .Y(n3228) ); NAND2X2TS U1930 ( .A(n3587), .B(intDX_EWSW[20]), .Y(n4848) ); NAND2X2TS U1931 ( .A(n4807), .B(intDX_EWSW[61]), .Y(n3678) ); MX2X4TS U1932 ( .A(n6435), .B(n5563), .S0(n5159), .Y(n5152) ); NAND3X4TS U1933 ( .A(n2677), .B(n2402), .C(n3178), .Y(n3176) ); NAND2X2TS U1934 ( .A(n2725), .B(n2735), .Y(n2724) ); NAND2BXLTS U1935 ( .AN(n2546), .B(n2571), .Y(n2776) ); OR2X2TS U1936 ( .A(n2835), .B(n2444), .Y(n2369) ); OA21X1TS U1937 ( .A0(n2382), .A1(n2373), .B0(n3208), .Y(n2671) ); NAND2X2TS U1938 ( .A(n5163), .B(n3119), .Y(n4587) ); NAND2X1TS U1939 ( .A(n5227), .B(n2021), .Y(n2020) ); NAND2X2TS U1940 ( .A(n3181), .B(n3178), .Y(n3177) ); NAND2XLTS U1941 ( .A(n5227), .B(n2451), .Y(n2841) ); NAND2X2TS U1942 ( .A(n6455), .B(n5149), .Y(n2828) ); INVX2TS U1943 ( .A(n6249), .Y(n1879) ); NAND3X2TS U1944 ( .A(n2835), .B(n2836), .C(n2834), .Y(n2830) ); NAND2X2TS U1945 ( .A(n2876), .B(n2875), .Y(n2874) ); NAND2XLTS U1946 ( .A(n5216), .B(n1827), .Y(n1826) ); BUFX6TS U1947 ( .A(n4791), .Y(n4853) ); BUFX6TS U1948 ( .A(n4791), .Y(n4426) ); OR2X6TS U1949 ( .A(n2502), .B(n2560), .Y(n2710) ); INVX2TS U1950 ( .A(n1875), .Y(n1878) ); BUFX16TS U1951 ( .A(n3125), .Y(n2526) ); INVX2TS U1952 ( .A(n2733), .Y(n2725) ); NAND2X1TS U1953 ( .A(n3921), .B(n3232), .Y(n2382) ); CLKBUFX2TS U1954 ( .A(Raw_mant_NRM_SWR[49]), .Y(n2012) ); INVX2TS U1955 ( .A(n6465), .Y(n2537) ); CLKBUFX2TS U1956 ( .A(Shift_amount_SHT1_EWR[4]), .Y(n2571) ); NAND2X4TS U1957 ( .A(n1963), .B(n1959), .Y(n6449) ); BUFX4TS U1958 ( .A(n5123), .Y(n5149) ); NAND2XLTS U1959 ( .A(n4737), .B(n4746), .Y(n4738) ); INVX4TS U1960 ( .A(n6293), .Y(n5277) ); NAND2X1TS U1961 ( .A(n5030), .B(n4722), .Y(n4725) ); NAND2X1TS U1962 ( .A(n4712), .B(n4711), .Y(n4713) ); NAND2X1TS U1963 ( .A(n2757), .B(n2738), .Y(n5098) ); NAND2X1TS U1964 ( .A(n4723), .B(n1635), .Y(n4687) ); NAND2XLTS U1965 ( .A(n5328), .B(n2673), .Y(n5329) ); INVX4TS U1966 ( .A(n5315), .Y(n2525) ); OAI2BB1X2TS U1967 ( .A0N(n5141), .A1N(n3062), .B0(n4605), .Y(n1831) ); NAND2X1TS U1968 ( .A(n5150), .B(n4685), .Y(n4501) ); CLKBUFX2TS U1969 ( .A(intDY_EWSW[18]), .Y(n2025) ); CLKBUFX2TS U1970 ( .A(intDY_EWSW[3]), .Y(n2737) ); NAND2XLTS U1971 ( .A(n4995), .B(n4994), .Y(n2359) ); INVX4TS U1972 ( .A(n2342), .Y(n2284) ); CLKAND2X2TS U1973 ( .A(n3275), .B(n4779), .Y(n2360) ); NAND2XLTS U1974 ( .A(n4928), .B(n4927), .Y(n2358) ); AND2X2TS U1975 ( .A(n3407), .B(n3406), .Y(n1841) ); NAND2X4TS U1976 ( .A(n4614), .B(n4613), .Y(n4615) ); NAND2X2TS U1977 ( .A(n3892), .B(n2735), .Y(n2728) ); CLKBUFX2TS U1978 ( .A(n5685), .Y(n6249) ); NAND2XLTS U1979 ( .A(n3016), .B(n4949), .Y(n4950) ); NAND2XLTS U1980 ( .A(n5086), .B(n5085), .Y(n5087) ); INVX2TS U1981 ( .A(n5294), .Y(n5299) ); NOR2X1TS U1982 ( .A(n3918), .B(n2550), .Y(n3173) ); CLKAND2X2TS U1983 ( .A(n3918), .B(n3179), .Y(n3178) ); NOR2X4TS U1984 ( .A(n2836), .B(n2444), .Y(n2833) ); INVX2TS U1985 ( .A(n4332), .Y(n6230) ); CLKAND2X2TS U1986 ( .A(n5324), .B(n5323), .Y(n2355) ); NOR2X6TS U1987 ( .A(n3085), .B(n1828), .Y(n2591) ); INVX6TS U1988 ( .A(n2883), .Y(n2876) ); CLKAND2X2TS U1989 ( .A(n4909), .B(n2373), .Y(n2352) ); NAND2XLTS U1990 ( .A(n3374), .B(n4241), .Y(n2434) ); NAND2X2TS U1991 ( .A(n4243), .B(n3374), .Y(n2835) ); CLKBUFX2TS U1992 ( .A(intDY_EWSW[42]), .Y(n1815) ); CLKAND2X2TS U1993 ( .A(n4974), .B(n4975), .Y(n2361) ); NAND2X4TS U1994 ( .A(n2988), .B(n3784), .Y(n2968) ); CLKBUFX2TS U1995 ( .A(intDY_EWSW[41]), .Y(n2026) ); NOR2X1TS U1996 ( .A(n3921), .B(n2670), .Y(n2669) ); NOR2X2TS U1997 ( .A(n4498), .B(n4497), .Y(n4504) ); NOR3X1TS U1998 ( .A(n4242), .B(n4244), .C(n5205), .Y(n2834) ); NOR2X1TS U1999 ( .A(n4689), .B(n4678), .Y(n4680) ); CLKAND2X2TS U2000 ( .A(n4771), .B(n4767), .Y(n2365) ); NAND2X2TS U2001 ( .A(n2880), .B(n2881), .Y(n2381) ); CLKINVX1TS U2002 ( .A(intDY_EWSW[40]), .Y(n1818) ); NAND2X2TS U2003 ( .A(n2400), .B(n3043), .Y(n3042) ); BUFX3TS U2004 ( .A(n4917), .Y(n5005) ); BUFX3TS U2005 ( .A(n5259), .Y(n5218) ); NAND2X6TS U2006 ( .A(n4079), .B(n4077), .Y(n1817) ); OAI22X2TS U2007 ( .A0(n4718), .A1(n4643), .B0(n4716), .B1(n4642), .Y(n4648) ); NAND2X2TS U2008 ( .A(n3031), .B(n5297), .Y(n3030) ); INVX2TS U2009 ( .A(n5549), .Y(n1827) ); CLKINVX1TS U2010 ( .A(n5006), .Y(n4070) ); NAND2X1TS U2011 ( .A(n5075), .B(n5073), .Y(n4735) ); NOR2X2TS U2012 ( .A(n4677), .B(n4679), .Y(n2590) ); CLKAND2X2TS U2013 ( .A(n1914), .B(n4749), .Y(n2366) ); OAI21X1TS U2014 ( .A0(n2444), .A1(n4241), .B0(n3278), .Y(n2832) ); BUFX3TS U2015 ( .A(n2317), .Y(n2325) ); INVX2TS U2016 ( .A(n5327), .Y(n5328) ); BUFX6TS U2017 ( .A(n2764), .Y(n5125) ); NAND2X1TS U2018 ( .A(n2389), .B(n3920), .Y(n3921) ); NAND2XLTS U2019 ( .A(n2373), .B(n3179), .Y(n2670) ); NAND2X2TS U2020 ( .A(n5154), .B(n4711), .Y(n4541) ); NAND2X1TS U2021 ( .A(n4722), .B(n5036), .Y(n2816) ); BUFX16TS U2022 ( .A(n2334), .Y(n2362) ); AND2X2TS U2023 ( .A(n3910), .B(n3912), .Y(n2402) ); NAND2X1TS U2024 ( .A(n5488), .B(DMP_EXP_EWSW[56]), .Y(n5306) ); NAND2X1TS U2025 ( .A(n4618), .B(n2516), .Y(n4609) ); NAND2X4TS U2026 ( .A(n3246), .B(n2677), .Y(n2836) ); INVX2TS U2027 ( .A(n4952), .Y(n4954) ); NAND2X1TS U2028 ( .A(n5143), .B(n2518), .Y(n4607) ); OAI22X1TS U2029 ( .A0(n6411), .A1(n4709), .B0(n4718), .B1(n4684), .Y(n2639) ); NAND2X2TS U2030 ( .A(n5138), .B(n2519), .Y(n3067) ); AND4X4TS U2031 ( .A(n2894), .B(n4344), .C(n2753), .D(n2893), .Y(n2377) ); NOR2X1TS U2032 ( .A(n2611), .B(n4674), .Y(n4677) ); NAND2X2TS U2033 ( .A(n4686), .B(n2517), .Y(n3104) ); CLKINVX1TS U2034 ( .A(n5073), .Y(n5074) ); NAND2X6TS U2035 ( .A(n3242), .B(n3237), .Y(n3239) ); BUFX3TS U2036 ( .A(n4917), .Y(n5205) ); INVX2TS U2037 ( .A(n4977), .Y(n4964) ); INVX2TS U2038 ( .A(n4980), .Y(n4963) ); NAND2XLTS U2039 ( .A(n5232), .B(DmP_mant_SFG_SWR[10]), .Y(n2886) ); CLKINVX6TS U2040 ( .A(n3091), .Y(n2765) ); NAND2X4TS U2041 ( .A(n3172), .B(n4135), .Y(n3171) ); INVX2TS U2042 ( .A(n3913), .Y(n3268) ); CLKINVX3TS U2043 ( .A(n4243), .Y(n3211) ); NOR2X1TS U2044 ( .A(n4021), .B(n2663), .Y(n2662) ); NOR2X6TS U2045 ( .A(n3081), .B(n2778), .Y(n5309) ); INVX1TS U2046 ( .A(n4240), .Y(n3908) ); NAND2X2TS U2047 ( .A(n3232), .B(n4244), .Y(n2444) ); INVX2TS U2048 ( .A(n4943), .Y(n2120) ); NAND2X1TS U2049 ( .A(n5294), .B(n3032), .Y(n3031) ); OR2X2TS U2050 ( .A(n4493), .B(n4492), .Y(n2503) ); NOR2X2TS U2051 ( .A(n2552), .B(n6411), .Y(n4679) ); INVX4TS U2052 ( .A(n2549), .Y(n2550) ); CLKAND2X4TS U2053 ( .A(n4890), .B(n2429), .Y(n2272) ); NAND2X2TS U2054 ( .A(n2419), .B(n2522), .Y(n2880) ); NAND2X2TS U2055 ( .A(n5139), .B(n5147), .Y(n3161) ); OR2X4TS U2056 ( .A(n2330), .B(n2560), .Y(n4477) ); CLKINVX3TS U2057 ( .A(n3281), .Y(n2755) ); NAND2X2TS U2058 ( .A(n1872), .B(n4089), .Y(n2960) ); INVX2TS U2059 ( .A(n4734), .Y(n5075) ); BUFX6TS U2060 ( .A(n4543), .Y(n5161) ); NAND2BX2TS U2061 ( .AN(n4673), .B(n3086), .Y(n3085) ); AOI21X1TS U2062 ( .A0(DmP_mant_SHT1_SW[51]), .A1(n2384), .B0(n5019), .Y( n4435) ); NAND2X2TS U2063 ( .A(n4649), .B(n5145), .Y(n4650) ); INVX4TS U2064 ( .A(n4683), .Y(n1828) ); NAND2BX2TS U2065 ( .AN(n3160), .B(n4692), .Y(n3159) ); NAND2X1TS U2066 ( .A(n4708), .B(n4656), .Y(n2089) ); CLKAND2X2TS U2067 ( .A(n4909), .B(n2389), .Y(n2339) ); NAND2X2TS U2068 ( .A(n5140), .B(n2519), .Y(n3105) ); NAND2X2TS U2069 ( .A(n2022), .B(n2519), .Y(n4625) ); NAND2X2TS U2070 ( .A(n4645), .B(n4685), .Y(n2100) ); NAND2X2TS U2071 ( .A(n4721), .B(n5145), .Y(n1939) ); NAND2X2TS U2072 ( .A(n4977), .B(n1921), .Y(n4982) ); AND2X4TS U2073 ( .A(n3896), .B(n3232), .Y(n2735) ); NAND3BX2TS U2074 ( .AN(n4894), .B(n4887), .C(n4902), .Y(n2075) ); NAND2BX2TS U2075 ( .AN(n2393), .B(n4692), .Y(n3066) ); NAND2X2TS U2076 ( .A(n4987), .B(n4923), .Y(n4925) ); NOR2X2TS U2077 ( .A(n4669), .B(n2560), .Y(n5274) ); AOI21X2TS U2078 ( .A0(n3281), .A1(n5000), .B0(n4999), .Y(n5001) ); NOR2X2TS U2079 ( .A(n3887), .B(n2665), .Y(n2664) ); OAI21X1TS U2080 ( .A0(n4756), .A1(n4755), .B0(n4754), .Y(n4757) ); NAND2X4TS U2081 ( .A(n4971), .B(n4987), .Y(n4973) ); NOR2X4TS U2082 ( .A(n4537), .B(n4536), .Y(n4539) ); CLKINVX2TS U2083 ( .A(n4769), .Y(n4765) ); NOR2X1TS U2084 ( .A(n4702), .B(n5058), .Y(n3802) ); CLKBUFX2TS U2085 ( .A(n2405), .Y(n2757) ); CLKBUFX2TS U2086 ( .A(n4338), .Y(n2753) ); NAND2X1TS U2087 ( .A(n4722), .B(n5017), .Y(n4695) ); INVX2TS U2088 ( .A(n3919), .Y(n4909) ); CLKBUFX2TS U2089 ( .A(DmP_mant_SHT1_SW[4]), .Y(n2548) ); NOR2X4TS U2090 ( .A(n4958), .B(n4914), .Y(n4943) ); NAND2X1TS U2091 ( .A(n4722), .B(n4331), .Y(n4127) ); BUFX6TS U2092 ( .A(n3365), .Y(n5147) ); NAND2X2TS U2093 ( .A(n5139), .B(n2517), .Y(n3146) ); INVX2TS U2094 ( .A(n4918), .Y(n4923) ); NAND2X2TS U2095 ( .A(n4682), .B(n4681), .Y(n4683) ); CLKXOR2X2TS U2096 ( .A(n2257), .B(DmP_mant_SFG_SWR[54]), .Y(n4244) ); NOR2X6TS U2097 ( .A(n4958), .B(n4961), .Y(n4977) ); NAND2X2TS U2098 ( .A(n3913), .B(n3912), .Y(n2785) ); INVX2TS U2099 ( .A(n1875), .Y(n1877) ); AOI2BB2X1TS U2100 ( .B0(Raw_mant_NRM_SWR[32]), .B1(n4343), .A0N(n3248), .A1N(n5492), .Y(n4344) ); INVX8TS U2101 ( .A(n2393), .Y(n2516) ); NOR2BX2TS U2102 ( .AN(n1856), .B(n2474), .Y(n3199) ); NAND2X1TS U2103 ( .A(n3880), .B(n3232), .Y(n3231) ); NOR2X1TS U2104 ( .A(n4706), .B(n4668), .Y(n3799) ); CLKAND2X2TS U2105 ( .A(n4240), .B(n3374), .Y(n3246) ); OAI22X2TS U2106 ( .A0(n6411), .A1(n1874), .B0(n4702), .B1(n4684), .Y(n1960) ); INVX4TS U2107 ( .A(n4286), .Y(n1832) ); NOR2X2TS U2108 ( .A(n4709), .B(n4710), .Y(n4532) ); BUFX3TS U2109 ( .A(n4917), .Y(n5089) ); NAND2X2TS U2110 ( .A(n3909), .B(DMP_SFG[51]), .Y(n4241) ); NOR2X1TS U2111 ( .A(n4689), .B(n4653), .Y(n4596) ); NOR2X4TS U2112 ( .A(n4968), .B(n4993), .Y(n4971) ); NAND2X2TS U2113 ( .A(n5086), .B(n3295), .Y(n4755) ); OAI22X2TS U2114 ( .A0(n2611), .A1(n4490), .B0(n4716), .B1(n4489), .Y(n4493) ); NOR2X2TS U2115 ( .A(n4669), .B(n4325), .Y(n4326) ); CLKAND2X2TS U2116 ( .A(n5061), .B(n5019), .Y(n2427) ); OAI22X2TS U2117 ( .A0(n4665), .A1(n4702), .B0(n4666), .B1(n4718), .Y(n3115) ); NAND2X2TS U2118 ( .A(n4135), .B(n3283), .Y(n2473) ); NAND2X2TS U2119 ( .A(n3240), .B(n4350), .Y(n2893) ); NAND2X1TS U2120 ( .A(n3019), .B(n3018), .Y(n2900) ); OAI21X1TS U2121 ( .A0(n5297), .A1(n5300), .B0(n5301), .Y(n3081) ); INVX2TS U2122 ( .A(n1875), .Y(n1876) ); AOI21X1TS U2123 ( .A0(n1920), .A1(n3295), .B0(n4753), .Y(n4754) ); INVX4TS U2124 ( .A(n4620), .Y(n5050) ); NAND2X1TS U2125 ( .A(n3262), .B(n2751), .Y(n4898) ); CLKINVX6TS U2126 ( .A(n4657), .Y(n5058) ); NAND2X1TS U2127 ( .A(n2723), .B(DMP_SFG[26]), .Y(n4767) ); AND2X6TS U2128 ( .A(n2560), .B(n1951), .Y(n3062) ); INVX2TS U2129 ( .A(n4751), .Y(n5086) ); NAND2X1TS U2130 ( .A(n3354), .B(DMP_EXP_EWSW[55]), .Y(n5301) ); INVX2TS U2131 ( .A(n4989), .Y(n4968) ); BUFX4TS U2132 ( .A(n4920), .Y(n2930) ); INVX2TS U2133 ( .A(n3898), .Y(n3912) ); INVX4TS U2134 ( .A(n5022), .Y(n4710) ); INVX6TS U2135 ( .A(n2080), .Y(n5138) ); CLKINVX6TS U2136 ( .A(n5013), .Y(n4653) ); INVX3TS U2137 ( .A(n5028), .Y(n4325) ); INVX4TS U2138 ( .A(n4523), .Y(n5049) ); NAND2X1TS U2139 ( .A(n4708), .B(n5038), .Y(n2630) ); INVX2TS U2140 ( .A(n4342), .Y(n3019) ); INVX2TS U2141 ( .A(n3897), .Y(n4136) ); INVX4TS U2142 ( .A(n1626), .Y(n4717) ); NAND2X4TS U2143 ( .A(n3275), .B(n4959), .Y(n4961) ); NAND2X6TS U2144 ( .A(n3147), .B(n4641), .Y(n5139) ); CLKINVX1TS U2145 ( .A(n4254), .Y(n4255) ); INVX3TS U2146 ( .A(n4333), .Y(n4489) ); NAND2X2TS U2147 ( .A(n3269), .B(n4020), .Y(n4021) ); NOR2X4TS U2148 ( .A(n4958), .B(n4783), .Y(n5322) ); NAND2X6TS U2149 ( .A(n4336), .B(n4252), .Y(n4266) ); NOR2X6TS U2150 ( .A(n2663), .B(n4019), .Y(n3910) ); OR2X2TS U2151 ( .A(n3909), .B(DMP_SFG[51]), .Y(n3374) ); NOR2BX1TS U2152 ( .AN(n2252), .B(n4341), .Y(n3018) ); AOI22X2TS U2153 ( .A0(n4659), .A1(n5037), .B0(n2780), .B1(n4322), .Y(n3857) ); NAND2X2TS U2154 ( .A(n2529), .B(n5025), .Y(n4059) ); NAND2X2TS U2155 ( .A(n4658), .B(n4620), .Y(n4621) ); NAND2X4TS U2156 ( .A(n2780), .B(n5051), .Y(n4329) ); OR2X4TS U2157 ( .A(n4654), .B(n3858), .Y(n2103) ); NAND2X2TS U2158 ( .A(n2555), .B(n5033), .Y(n4624) ); OAI21X2TS U2159 ( .A0(n4351), .A1(n2037), .B0(n2897), .Y(n2896) ); INVX4TS U2160 ( .A(n4672), .Y(n5057) ); NAND2X6TS U2161 ( .A(n5140), .B(n4691), .Y(n2601) ); XNOR2X1TS U2162 ( .A(intDX_EWSW[1]), .B(n2310), .Y(n4152) ); NOR2BX2TS U2163 ( .AN(n2392), .B(n4893), .Y(n2899) ); NAND2X1TS U2164 ( .A(n4722), .B(n5020), .Y(n2703) ); XNOR2X1TS U2165 ( .A(intDX_EWSW[37]), .B(intDY_EWSW[37]), .Y(n4157) ); NAND2X2TS U2166 ( .A(n2262), .B(n5033), .Y(n4485) ); NOR2X6TS U2167 ( .A(n4702), .B(n4715), .Y(n2071) ); INVX2TS U2168 ( .A(n4785), .Y(n5324) ); NAND2X2TS U2169 ( .A(n4722), .B(n5013), .Y(n2104) ); INVX3TS U2170 ( .A(n3900), .Y(n4998) ); NOR2X2TS U2171 ( .A(n4517), .B(n4516), .Y(n4528) ); AND2X4TS U2172 ( .A(n4063), .B(n4066), .Y(n2941) ); XNOR2X2TS U2173 ( .A(n2028), .B(intDY_EWSW[39]), .Y(n4155) ); OR2X2TS U2174 ( .A(n4701), .B(n4662), .Y(n3060) ); XOR2X1TS U2175 ( .A(intDX_EWSW[55]), .B(n2475), .Y(n4211) ); CLKINVX1TS U2176 ( .A(n4685), .Y(n2079) ); XNOR2X1TS U2177 ( .A(intDX_EWSW[57]), .B(intDY_EWSW[57]), .Y(n4210) ); AND2X4TS U2178 ( .A(n4120), .B(n4122), .Y(n2578) ); NAND2X2TS U2179 ( .A(n3237), .B(n5006), .Y(n2854) ); NAND4X2TS U2180 ( .A(n4087), .B(n6150), .C(n6149), .D(n6148), .Y(n5015) ); NAND2X1TS U2181 ( .A(n4473), .B(n5014), .Y(n4084) ); INVX1TS U2182 ( .A(n4716), .Y(n2632) ); CLKINVX3TS U2183 ( .A(n5038), .Y(n4701) ); INVX6TS U2184 ( .A(n5035), .Y(n4715) ); NAND2X4TS U2185 ( .A(n2054), .B(n4247), .Y(n4891) ); NAND2X2TS U2186 ( .A(n5024), .B(n4658), .Y(n3972) ); CLKINVX6TS U2187 ( .A(n5021), .Y(n4643) ); BUFX4TS U2188 ( .A(n4910), .Y(n4911) ); NAND2X4TS U2189 ( .A(n4691), .B(n2529), .Y(n4706) ); NAND2X4TS U2190 ( .A(n4711), .B(n2560), .Y(n2393) ); NAND2X6TS U2191 ( .A(n4935), .B(n3275), .Y(n4936) ); NAND2X2TS U2192 ( .A(n1644), .B(n1919), .Y(n4064) ); BUFX16TS U2193 ( .A(n4669), .Y(n4702) ); INVX6TS U2194 ( .A(n4763), .Y(n4958) ); INVX6TS U2195 ( .A(n2952), .Y(n4962) ); INVX2TS U2196 ( .A(n4698), .Y(n2106) ); NOR2X6TS U2197 ( .A(n2077), .B(n5439), .Y(n4885) ); NOR2X4TS U2198 ( .A(Shift_amount_SHT1_EWR[0]), .B(n2562), .Y(n5006) ); OR2X2TS U2199 ( .A(n2646), .B(n2464), .Y(n4259) ); INVX6TS U2200 ( .A(n5262), .Y(n4696) ); NAND2X2TS U2201 ( .A(n1919), .B(n5037), .Y(n3093) ); INVX2TS U2202 ( .A(n4332), .Y(n6229) ); INVX2TS U2203 ( .A(n2855), .Y(n3237) ); CLKAND2X2TS U2204 ( .A(n5054), .B(n2262), .Y(n2398) ); INVX8TS U2205 ( .A(n1627), .Y(n4684) ); NAND2X2TS U2206 ( .A(n2555), .B(n1917), .Y(n4066) ); INVX2TS U2207 ( .A(n4019), .Y(n3269) ); INVX6TS U2208 ( .A(n5036), .Y(n4534) ); AND2X6TS U2209 ( .A(n3255), .B(n3254), .Y(n3222) ); AND2X6TS U2210 ( .A(n3024), .B(n3023), .Y(n4339) ); NAND2X4TS U2211 ( .A(n3888), .B(DMP_SFG[47]), .Y(n4135) ); OA22X2TS U2212 ( .A0(n2225), .A1(n2155), .B0(n2232), .B1(n2189), .Y(n3946) ); NAND2X4TS U2213 ( .A(n4658), .B(n5033), .Y(n4080) ); INVX3TS U2214 ( .A(n4049), .Y(n4521) ); NOR2X4TS U2215 ( .A(n2902), .B(n3068), .Y(n4912) ); CLKINVX3TS U2216 ( .A(n5045), .Y(n1918) ); NAND2X2TS U2217 ( .A(n2529), .B(n1859), .Y(n4524) ); INVX8TS U2218 ( .A(n2076), .Y(n2077) ); BUFX16TS U2219 ( .A(n3833), .Y(n4716) ); NOR2BX2TS U2220 ( .AN(n4257), .B(n3745), .Y(n2646) ); OAI2BB2X2TS U2221 ( .B0(n2154), .B1(n2232), .A0N(n2223), .A1N(n2224), .Y( n3703) ); NOR2X6TS U2222 ( .A(n3919), .B(n3873), .Y(n4018) ); NAND2X2TS U2223 ( .A(n3894), .B(DMP_SFG[50]), .Y(n3901) ); NAND2X2TS U2224 ( .A(n3890), .B(DMP_SFG[49]), .Y(n5003) ); NAND3X4TS U2225 ( .A(n2563), .B(n3023), .C(n3024), .Y(n3026) ); BUFX4TS U2226 ( .A(left_right_SHT2), .Y(n2560) ); BUFX3TS U2227 ( .A(n4781), .Y(n2759) ); CLKINVX6TS U2228 ( .A(n4689), .Y(n4488) ); AND2X4TS U2229 ( .A(n4593), .B(n4592), .Y(n2081) ); NAND2X2TS U2230 ( .A(n3241), .B(n5061), .Y(n2855) ); INVX4TS U2231 ( .A(n2551), .Y(n3287) ); INVX12TS U2232 ( .A(n4644), .Y(n1870) ); INVX6TS U2233 ( .A(n3781), .Y(n3188) ); BUFX6TS U2234 ( .A(n3804), .Y(n4659) ); AND2X6TS U2235 ( .A(n3401), .B(n4989), .Y(n2397) ); CLKAND2X2TS U2236 ( .A(n5819), .B(n5818), .Y(n3948) ); AND2X2TS U2237 ( .A(n5824), .B(n6119), .Y(n2459) ); INVX4TS U2238 ( .A(n5174), .Y(n3130) ); NAND2X4TS U2239 ( .A(n3027), .B(n4257), .Y(n3023) ); INVX12TS U2240 ( .A(n4669), .Y(n4722) ); NAND2X6TS U2241 ( .A(n2644), .B(n2640), .Y(n1644) ); NAND2X4TS U2242 ( .A(n2821), .B(n2087), .Y(n5023) ); NAND4BX2TS U2243 ( .AN(n4036), .B(n4035), .C(n4034), .D(n6170), .Y(n1860) ); NAND2X2TS U2244 ( .A(n5834), .B(n2207), .Y(n3707) ); OAI22X2TS U2245 ( .A0(n6074), .A1(n2124), .B0(n6073), .B1(n6072), .Y(n3959) ); NOR2X4TS U2246 ( .A(n2979), .B(n3201), .Y(n2978) ); NOR2X6TS U2247 ( .A(n4138), .B(n3897), .Y(n5000) ); NAND2X4TS U2248 ( .A(n1971), .B(n1972), .Y(n3887) ); INVX4TS U2249 ( .A(n2742), .Y(n2076) ); OR3X2TS U2250 ( .A(n4300), .B(n4299), .C(n4298), .Y(n5031) ); BUFX12TS U2251 ( .A(n4600), .Y(n2780) ); NOR2X2TS U2252 ( .A(n2607), .B(n2606), .Y(n2610) ); AOI21X2TS U2253 ( .A0(n4974), .A1(n3134), .B0(n3133), .Y(n3254) ); AOI21X2TS U2254 ( .A0(n3885), .A1(n3368), .B0(n3884), .Y(n1965) ); BUFX6TS U2255 ( .A(n4600), .Y(n1869) ); XNOR2X2TS U2256 ( .A(n2285), .B(n4013), .Y(n1848) ); BUFX3TS U2257 ( .A(n3185), .Y(n4974) ); CLKINVX6TS U2258 ( .A(n4681), .Y(n4062) ); AND3X2TS U2259 ( .A(n6114), .B(n6113), .C(n6112), .Y(n3934) ); NAND3X1TS U2260 ( .A(n6154), .B(n6153), .C(n6152), .Y(n3836) ); OR2X6TS U2261 ( .A(n3233), .B(n3753), .Y(n1894) ); AND2X2TS U2262 ( .A(n6144), .B(n6145), .Y(n2809) ); CLKAND2X2TS U2263 ( .A(n6146), .B(n6189), .Y(n2810) ); NOR2BX2TS U2264 ( .AN(n2438), .B(n6062), .Y(n2796) ); NOR2X1TS U2265 ( .A(n5442), .B(Raw_mant_NRM_SWR[32]), .Y(n3755) ); INVX4TS U2266 ( .A(n5054), .Y(n2607) ); NAND2X6TS U2267 ( .A(n4959), .B(n1896), .Y(n3215) ); AOI22X2TS U2268 ( .A0(n5690), .A1(n5689), .B0(n5688), .B1(n2206), .Y(n3971) ); NAND2BX2TS U2269 ( .AN(n5737), .B(n2409), .Y(n3048) ); NOR2X2TS U2270 ( .A(n5826), .B(n5825), .Y(n2462) ); NOR2X6TS U2271 ( .A(n4267), .B(n3028), .Y(n3027) ); NAND2X4TS U2272 ( .A(n1849), .B(n2911), .Y(n2910) ); NOR2X6TS U2273 ( .A(n3154), .B(n3152), .Y(n3151) ); AOI2BB2X2TS U2274 ( .B0(n5891), .B1(n2171), .A0N(n5890), .A1N(n5889), .Y( n4023) ); NAND2X2TS U2275 ( .A(n5903), .B(n2195), .Y(n3697) ); AOI21X2TS U2276 ( .A0(n5877), .A1(n2197), .B0(n2645), .Y(n2644) ); NOR2X6TS U2277 ( .A(n2464), .B(n2000), .Y(n1999) ); AOI2BB2X2TS U2278 ( .B0(n2220), .B1(n1902), .A0N(n6006), .A1N(n6005), .Y( n3835) ); AOI2BB2X2TS U2279 ( .B0(n1902), .B1(n2219), .A0N(n5970), .A1N(n5969), .Y( n3699) ); CLKAND2X2TS U2280 ( .A(n4009), .B(n4008), .Y(n2311) ); NAND2BX1TS U2281 ( .AN(n1903), .B(n5879), .Y(n2087) ); NOR2X6TS U2282 ( .A(n1973), .B(n1969), .Y(n1967) ); INVX4TS U2283 ( .A(n2561), .Y(n2513) ); NOR2X4TS U2284 ( .A(n3890), .B(DMP_SFG[49]), .Y(n5002) ); AND2X4TS U2285 ( .A(n3185), .B(n4995), .Y(n3401) ); NAND2X2TS U2286 ( .A(n3757), .B(n2032), .Y(n3761) ); OR2X6TS U2287 ( .A(n4926), .B(n4921), .Y(n2949) ); NAND2X1TS U2288 ( .A(n6063), .B(n2164), .Y(n3859) ); AND2X6TS U2289 ( .A(n2406), .B(n5083), .Y(n2921) ); BUFX4TS U2290 ( .A(n4983), .Y(n2760) ); NAND2X2TS U2291 ( .A(n3400), .B(DMP_SFG[39]), .Y(n4975) ); AND2X6TS U2292 ( .A(n4347), .B(n5438), .Y(n2078) ); INVX2TS U2293 ( .A(n1933), .Y(n1926) ); NAND2X2TS U2294 ( .A(n3394), .B(DMP_SFG[34]), .Y(n4944) ); AND2X4TS U2295 ( .A(n4019), .B(n4020), .Y(n1969) ); CLKINVX3TS U2296 ( .A(n2490), .Y(n3753) ); CLKINVX6TS U2297 ( .A(n1997), .Y(n1996) ); NAND2X6TS U2298 ( .A(n2699), .B(n2694), .Y(n5047) ); AOI21X2TS U2299 ( .A0(n5921), .A1(n4047), .B0(n5920), .Y(n3838) ); NAND2X2TS U2300 ( .A(n6175), .B(n6176), .Y(n2784) ); NOR2X2TS U2301 ( .A(n3397), .B(DMP_SFG[36]), .Y(n4918) ); BUFX16TS U2302 ( .A(n4600), .Y(n4658) ); NAND2X2TS U2303 ( .A(n3876), .B(DMP_SFG[45]), .Y(n3916) ); INVX2TS U2304 ( .A(n2837), .Y(n2822) ); NAND2X6TS U2305 ( .A(n4749), .B(n2651), .Y(n2952) ); BUFX16TS U2306 ( .A(n4600), .Y(n2529) ); NAND2X2TS U2307 ( .A(n3879), .B(DMP_SFG[46]), .Y(n3883) ); NAND2X2TS U2308 ( .A(n3395), .B(DMP_SFG[35]), .Y(n4949) ); NAND2X2TS U2309 ( .A(n3398), .B(DMP_SFG[37]), .Y(n4927) ); BUFX3TS U2310 ( .A(n3111), .Y(n1951) ); AOI21X2TS U2311 ( .A0(n2131), .A1(n5748), .B0(n2774), .Y(n2773) ); NAND2X4TS U2312 ( .A(n4271), .B(n3769), .Y(n4280) ); NOR2X2TS U2313 ( .A(n1929), .B(n1928), .Y(n1927) ); NOR2X6TS U2314 ( .A(n3113), .B(n3207), .Y(n3112) ); CLKBUFX2TS U2315 ( .A(Raw_mant_NRM_SWR[47]), .Y(n2032) ); OR2X4TS U2316 ( .A(n4886), .B(Raw_mant_NRM_SWR[2]), .Y(n2403) ); NAND2X2TS U2317 ( .A(n3998), .B(n3997), .Y(n3999) ); NOR2X6TS U2318 ( .A(n2319), .B(n5443), .Y(n3756) ); INVX2TS U2319 ( .A(n4267), .Y(n3249) ); INVX6TS U2320 ( .A(n4004), .Y(n2843) ); CLKAND2X2TS U2321 ( .A(n6109), .B(n6110), .Y(n2839) ); NAND2X4TS U2322 ( .A(n4600), .B(n1925), .Y(n1957) ); INVX2TS U2323 ( .A(n4251), .Y(n3770) ); NOR2X6TS U2324 ( .A(n3874), .B(DMP_SFG[43]), .Y(n4019) ); AOI21X2TS U2325 ( .A0(n5848), .A1(n5849), .B0(n3138), .Y(n3137) ); INVX12TS U2326 ( .A(n4779), .Y(n3272) ); BUFX3TS U2327 ( .A(n4012), .Y(n2962) ); INVX2TS U2328 ( .A(n3870), .Y(n3871) ); NAND2X2TS U2329 ( .A(n2652), .B(DMP_SFG[24]), .Y(n4749) ); NAND2BX2TS U2330 ( .AN(n5983), .B(n2408), .Y(n2824) ); OR2X4TS U2331 ( .A(n3879), .B(DMP_SFG[46]), .Y(n3368) ); NAND2X4TS U2332 ( .A(n4257), .B(n2037), .Y(n1997) ); AND2X4TS U2333 ( .A(n3693), .B(n3694), .Y(n1901) ); NOR2X6TS U2334 ( .A(n3221), .B(n2752), .Y(n3220) ); NAND2X6TS U2335 ( .A(n4892), .B(n3744), .Y(n4886) ); NAND2X6TS U2336 ( .A(n3461), .B(n3478), .Y(n3481) ); AOI2BB2X2TS U2337 ( .B0(n5958), .B1(n2196), .A0N(n2232), .A1N(n2147), .Y( n3695) ); NAND2X2TS U2338 ( .A(n3397), .B(DMP_SFG[36]), .Y(n4921) ); BUFX2TS U2339 ( .A(n2465), .Y(n1824) ); AND2X4TS U2340 ( .A(n4347), .B(n3783), .Y(n3035) ); NAND2X2TS U2341 ( .A(n3508), .B(n3523), .Y(n3509) ); NOR2X2TS U2342 ( .A(DMP_exp_NRM2_EW[9]), .B(DMP_exp_NRM2_EW[8]), .Y(n4002) ); INVX2TS U2343 ( .A(n2947), .Y(n3978) ); NOR2X4TS U2344 ( .A(n4258), .B(n1986), .Y(n3735) ); NOR2X4TS U2345 ( .A(n3513), .B(n3559), .Y(n3518) ); INVX6TS U2346 ( .A(n3094), .Y(n1850) ); NAND2X1TS U2347 ( .A(n3785), .B(n3784), .Y(n3788) ); BUFX3TS U2348 ( .A(Raw_mant_NRM_SWR[53]), .Y(n2019) ); NAND2X2TS U2349 ( .A(n3405), .B(DMP_SFG[42]), .Y(n3870) ); BUFX3TS U2350 ( .A(n3984), .Y(n2947) ); NAND3X4TS U2351 ( .A(n2616), .B(n3779), .C(n2615), .Y(n4246) ); BUFX4TS U2352 ( .A(n3750), .Y(n3219) ); OR2X4TS U2353 ( .A(n4005), .B(n4007), .Y(n4004) ); INVX2TS U2354 ( .A(n4759), .Y(n3387) ); NOR2X6TS U2355 ( .A(n3876), .B(DMP_SFG[45]), .Y(n3915) ); NAND2X4TS U2356 ( .A(n3515), .B(n3560), .Y(n3517) ); OR2X4TS U2357 ( .A(n3403), .B(DMP_SFG[41]), .Y(n2389) ); BUFX3TS U2358 ( .A(Raw_mant_NRM_SWR[43]), .Y(n1986) ); NAND2X2TS U2359 ( .A(n3774), .B(n2766), .Y(n4260) ); NOR2X6TS U2360 ( .A(n3380), .B(n5095), .Y(n3381) ); NOR2X1TS U2361 ( .A(n6001), .B(n6000), .Y(n2592) ); NAND2BX2TS U2362 ( .AN(Raw_mant_NRM_SWR[6]), .B(n4248), .Y(n3731) ); INVX4TS U2363 ( .A(n4742), .Y(n4753) ); OR2X4TS U2364 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM2_EW[6]), .Y(n2387) ); INVX6TS U2365 ( .A(n1925), .Y(n1953) ); NOR2X2TS U2366 ( .A(n2173), .B(n2232), .Y(n2582) ); NAND2BX2TS U2367 ( .AN(n3041), .B(n5445), .Y(n3040) ); INVX2TS U2368 ( .A(n3920), .Y(n3872) ); INVX6TS U2369 ( .A(n4748), .Y(n1914) ); NOR2X4TS U2370 ( .A(n3460), .B(n3473), .Y(n3461) ); NOR2X4TS U2371 ( .A(n3485), .B(n2768), .Y(n3467) ); BUFX4TS U2372 ( .A(Raw_mant_NRM_SWR[35]), .Y(n2037) ); AND2X6TS U2373 ( .A(intDX_EWSW[6]), .B(n2481), .Y(n3420) ); BUFX8TS U2374 ( .A(n4939), .Y(n2744) ); BUFX4TS U2375 ( .A(n2467), .Y(n2052) ); NAND2X4TS U2376 ( .A(n5420), .B(n2889), .Y(n4349) ); BUFX4TS U2377 ( .A(n3980), .Y(n2011) ); NAND2X2TS U2378 ( .A(n2844), .B(DMP_SFG[32]), .Y(n4955) ); NOR2X6TS U2379 ( .A(n3561), .B(n2708), .Y(n3516) ); NAND2X4TS U2380 ( .A(n3392), .B(DMP_SFG[30]), .Y(n4978) ); NOR2X6TS U2381 ( .A(n3342), .B(intDY_EWSW[23]), .Y(n3476) ); NOR2X6TS U2382 ( .A(n2652), .B(DMP_SFG[24]), .Y(n4748) ); NAND2X2TS U2383 ( .A(n3356), .B(intDY_EWSW[18]), .Y(n2455) ); NAND2X2TS U2384 ( .A(n3289), .B(intDY_EWSW[12]), .Y(n3446) ); NOR2X2TS U2385 ( .A(n3315), .B(intDY_EWSW[8]), .Y(n3434) ); NAND2X4TS U2386 ( .A(n3310), .B(intDY_EWSW[16]), .Y(n2458) ); NOR2X2TS U2387 ( .A(n3289), .B(intDY_EWSW[12]), .Y(n3431) ); NAND2X6TS U2388 ( .A(n2862), .B(n3545), .Y(n3548) ); NOR2X6TS U2389 ( .A(n2687), .B(n2705), .Y(n3553) ); NAND2X2TS U2390 ( .A(n3762), .B(n3763), .Y(n2626) ); NOR2X4TS U2391 ( .A(n3333), .B(intDY_EWSW[22]), .Y(n3118) ); NAND2X2TS U2392 ( .A(n3340), .B(intDY_EWSW[13]), .Y(n3445) ); NAND2X2TS U2393 ( .A(n3323), .B(intDY_EWSW[11]), .Y(n3439) ); NAND2X2TS U2394 ( .A(n3317), .B(intDY_EWSW[6]), .Y(n3426) ); NAND2X2TS U2395 ( .A(n3332), .B(intDY_EWSW[54]), .Y(n3558) ); NAND2X6TS U2396 ( .A(n2031), .B(intDY_EWSW[58]), .Y(n2804) ); NAND2X2TS U2397 ( .A(n3369), .B(DMP_exp_NRM2_EW[5]), .Y(n4008) ); NAND2X6TS U2398 ( .A(n4780), .B(n2667), .Y(n2674) ); NOR2X4TS U2399 ( .A(n3356), .B(intDY_EWSW[18]), .Y(n2456) ); NAND2X6TS U2400 ( .A(n3306), .B(intDY_EWSW[48]), .Y(n2689) ); NAND2X2TS U2401 ( .A(n3359), .B(n2295), .Y(n3422) ); NAND2X2TS U2402 ( .A(n3328), .B(n2310), .Y(n3410) ); NOR2X4TS U2403 ( .A(n3183), .B(DMP_SFG[15]), .Y(n5095) ); NAND2X2TS U2404 ( .A(n3319), .B(intDY_EWSW[9]), .Y(n2741) ); NOR2X6TS U2405 ( .A(n3357), .B(n2250), .Y(n3485) ); NAND3X4TS U2406 ( .A(n2015), .B(n3782), .C(n3743), .Y(n4245) ); NAND2X4TS U2407 ( .A(n1987), .B(intDY_EWSW[56]), .Y(n2808) ); INVX12TS U2408 ( .A(n1866), .Y(n3986) ); NAND2X2TS U2409 ( .A(n2301), .B(n3772), .Y(n2625) ); BUFX6TS U2410 ( .A(n4270), .Y(n2038) ); INVX3TS U2411 ( .A(n3765), .Y(n2869) ); OR2X6TS U2412 ( .A(n3379), .B(DMP_SFG[17]), .Y(n3370) ); AND2X6TS U2413 ( .A(intDX_EWSW[54]), .B(n2332), .Y(n3512) ); INVX4TS U2414 ( .A(n2650), .Y(n3389) ); NAND2X4TS U2415 ( .A(n3373), .B(DMP_exp_NRM2_EW[4]), .Y(n4012) ); NOR2X4TS U2416 ( .A(n3336), .B(intDY_EWSW[56]), .Y(n3514) ); NAND2X4TS U2417 ( .A(n3360), .B(intDY_EWSW[40]), .Y(n3531) ); INVX2TS U2418 ( .A(n2004), .Y(n3748) ); NOR2X2TS U2419 ( .A(n5999), .B(n5998), .Y(n2595) ); NOR2X6TS U2420 ( .A(n2007), .B(n2006), .Y(n3523) ); NAND2X2TS U2421 ( .A(n3302), .B(intDY_EWSW[46]), .Y(n3542) ); OR2X4TS U2422 ( .A(n3346), .B(intDY_EWSW[36]), .Y(n1900) ); INVX4TS U2423 ( .A(n6216), .Y(n5029) ); NOR2X4TS U2424 ( .A(n3306), .B(intDY_EWSW[48]), .Y(n2117) ); AND2X6TS U2425 ( .A(n5279), .B(n5473), .Y(n2343) ); NOR2X6TS U2426 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[7]), .Y(n4248) ); NOR2X6TS U2427 ( .A(DMP_SFG[31]), .B(n2628), .Y(n4983) ); INVX8TS U2428 ( .A(n4348), .Y(n2851) ); NAND2X2TS U2429 ( .A(n3349), .B(intDY_EWSW[37]), .Y(n3524) ); INVX4TS U2430 ( .A(n2307), .Y(n2308) ); NOR2X4TS U2431 ( .A(n3360), .B(intDY_EWSW[40]), .Y(n2860) ); NOR2X2TS U2432 ( .A(Raw_mant_NRM_SWR[5]), .B(Raw_mant_NRM_SWR[9]), .Y(n3742) ); NOR2X2TS U2433 ( .A(Raw_mant_NRM_SWR[35]), .B(Raw_mant_NRM_SWR[34]), .Y( n2868) ); NOR2X6TS U2434 ( .A(n3301), .B(n2299), .Y(n3540) ); NOR2X6TS U2435 ( .A(n3363), .B(intDY_EWSW[42]), .Y(n2861) ); NAND2X6TS U2436 ( .A(n3762), .B(n2005), .Y(n2004) ); NOR2X2TS U2437 ( .A(n2300), .B(n2252), .Y(n2005) ); NAND2X6TS U2438 ( .A(n3789), .B(n3790), .Y(n4348) ); NAND2X4TS U2439 ( .A(n2062), .B(n2061), .Y(n2063) ); NOR2X4TS U2440 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[22]), .Y( n1991) ); NAND2X6TS U2441 ( .A(n2057), .B(n2056), .Y(n2060) ); NOR2X6TS U2442 ( .A(Raw_mant_NRM_SWR[28]), .B(Raw_mant_NRM_SWR[34]), .Y( n2065) ); INVX4TS U2443 ( .A(n1851), .Y(n1852) ); INVX6TS U2444 ( .A(n1851), .Y(n1853) ); INVX3TS U2445 ( .A(Raw_mant_NRM_SWR[49]), .Y(n3726) ); INVX2TS U2446 ( .A(n1854), .Y(n2493) ); INVX8TS U2447 ( .A(n1851), .Y(n1854) ); INVX16TS U2448 ( .A(n2934), .Y(n2495) ); OAI22X4TS U2449 ( .A0(n5248), .A1(n1916), .B0(n5287), .B1(n5526), .Y(n1078) ); NAND2X4TS U2450 ( .A(n5138), .B(n5145), .Y(n3148) ); BUFX20TS U2451 ( .A(n6221), .Y(n6222) ); NOR2X6TS U2452 ( .A(n6456), .B(n5245), .Y(n3145) ); OR3X6TS U2453 ( .A(n3058), .B(n2503), .C(n2504), .Y(n5124) ); INVX12TS U2454 ( .A(n1906), .Y(n6227) ); CLKINVX6TS U2455 ( .A(n1958), .Y(n4474) ); NAND2X2TS U2456 ( .A(n4905), .B(n4904), .Y(n1605) ); NAND2X2TS U2457 ( .A(n4548), .B(n4547), .Y(n1034) ); NAND2X4TS U2458 ( .A(n4512), .B(n5161), .Y(n4515) ); NAND3X8TS U2459 ( .A(n2573), .B(n2579), .C(n2424), .Y(n4512) ); OAI2BB1X4TS U2460 ( .A0N(n5161), .A1N(n6459), .B0(n5132), .Y(n1111) ); NAND3X4TS U2461 ( .A(n3586), .B(n3585), .C(n3584), .Y(n1224) ); OAI21X4TS U2462 ( .A0(n4606), .A1(n5264), .B0(n3079), .Y(n1040) ); AND2X8TS U2463 ( .A(n3080), .B(n2775), .Y(n4606) ); NAND3X4TS U2464 ( .A(n4312), .B(n4311), .C(n4310), .Y(n1294) ); NAND3X8TS U2465 ( .A(n3974), .B(n3973), .C(n3972), .Y(n4618) ); NAND2X8TS U2466 ( .A(n3839), .B(n2704), .Y(n4682) ); NAND2X4TS U2467 ( .A(n5051), .B(n2555), .Y(n3839) ); NAND2X4TS U2468 ( .A(n5263), .B(n2449), .Y(n2852) ); NOR2X6TS U2469 ( .A(n4630), .B(n4629), .Y(n5254) ); NAND2X4TS U2470 ( .A(n3156), .B(n3155), .Y(n1039) ); AOI22X2TS U2471 ( .A0(n4637), .A1(n4672), .B0(n5054), .B1(n3846), .Y(n3096) ); INVX16TS U2472 ( .A(n3045), .Y(n3046) ); INVX8TS U2473 ( .A(n1635), .Y(n4678) ); NOR2X4TS U2474 ( .A(n2611), .B(n5049), .Y(n4533) ); INVX6TS U2475 ( .A(n2767), .Y(n5096) ); NAND2X4TS U2476 ( .A(n4672), .B(n2529), .Y(n3099) ); OAI21X2TS U2477 ( .A0(n5249), .A1(n2554), .B0(n3109), .Y(n1119) ); NAND4X4TS U2478 ( .A(n4623), .B(n4621), .C(n4622), .D(n4624), .Y(n5136) ); NAND3X6TS U2479 ( .A(n4082), .B(n4081), .C(n4080), .Y(n4704) ); NAND3BX2TS U2480 ( .AN(n2928), .B(n4030), .C(n4031), .Y(n2927) ); NAND2X2TS U2481 ( .A(n6174), .B(n6173), .Y(n2928) ); OA22X4TS U2482 ( .A0(n5980), .A1(n5979), .B0(n5978), .B1(n5977), .Y(n3936) ); NAND2X8TS U2483 ( .A(n3044), .B(n2941), .Y(n2637) ); NAND2X4TS U2484 ( .A(n5124), .B(n5161), .Y(n4495) ); AOI22X2TS U2485 ( .A0(n4633), .A1(n3062), .B0(n2518), .B1(n4721), .Y(n2472) ); NAND2X2TS U2486 ( .A(n4633), .B(n5147), .Y(n4628) ); OAI21X2TS U2487 ( .A0(n4662), .A1(n4675), .B0(n3857), .Y(n3867) ); INVX16TS U2488 ( .A(n4662), .Y(n2555) ); NOR3X8TS U2489 ( .A(n2390), .B(n5965), .C(n3053), .Y(n3052) ); NAND3X6TS U2490 ( .A(n4041), .B(n4040), .C(n4039), .Y(n4712) ); CLKINVX12TS U2491 ( .A(n6221), .Y(n3045) ); BUFX8TS U2492 ( .A(n6221), .Y(n6220) ); NAND2X4TS U2493 ( .A(n5143), .B(n4685), .Y(n2798) ); AOI22X2TS U2494 ( .A0(n4637), .A1(n4699), .B0(n2780), .B1(n5035), .Y(n4086) ); NAND2X2TS U2495 ( .A(n4658), .B(n4699), .Y(n4484) ); NAND2X2TS U2496 ( .A(n2261), .B(n4699), .Y(n4622) ); NOR2X8TS U2497 ( .A(n3145), .B(n2385), .Y(n3144) ); NAND2X4TS U2498 ( .A(n2041), .B(intDX_EWSW[43]), .Y(n3586) ); OAI2BB1X2TS U2499 ( .A0N(n4543), .A1N(n6452), .B0(n4507), .Y(n1054) ); NAND2X4TS U2500 ( .A(n2027), .B(intDX_EWSW[8]), .Y(n4312) ); NAND3X4TS U2501 ( .A(n4422), .B(n4423), .C(n4421), .Y(n1561) ); NOR2X2TS U2502 ( .A(n3853), .B(n3852), .Y(n3856) ); AOI22X2TS U2503 ( .A0(n5941), .A1(n2192), .B0(n5940), .B1(n2169), .Y(n3855) ); NAND3X8TS U2504 ( .A(n3933), .B(n3934), .C(n3151), .Y(n5025) ); OR2X4TS U2505 ( .A(n5722), .B(n2176), .Y(n4031) ); NAND2X4TS U2506 ( .A(n1944), .B(n5028), .Y(n1942) ); AOI21X4TS U2507 ( .A0(n3245), .A1(n5075), .B0(n5074), .Y(n5080) ); OAI2BB1X4TS U2508 ( .A0N(n5016), .A1N(n2558), .B0(n4486), .Y(n3061) ); INVX6TS U2509 ( .A(n5030), .Y(n4490) ); NAND2X4TS U2510 ( .A(n5344), .B(n5436), .Y(n2769) ); NOR2X6TS U2511 ( .A(n5436), .B(n5344), .Y(n3804) ); OAI21X2TS U2512 ( .A0(n4756), .A1(n4751), .B0(n5085), .Y(n4740) ); NAND4X2TS U2513 ( .A(n4173), .B(n4172), .C(n4171), .D(n4170), .Y(n4184) ); INVX16TS U2514 ( .A(n3234), .Y(n2557) ); NAND3X4TS U2515 ( .A(n3592), .B(n3593), .C(n3591), .Y(n1547) ); NAND2X4TS U2516 ( .A(intDX_EWSW[59]), .B(n4873), .Y(n3589) ); NAND3X8TS U2517 ( .A(n2105), .B(n2104), .C(n2103), .Y(n2102) ); NAND2X4TS U2518 ( .A(n4671), .B(n2330), .Y(n3072) ); NAND4BX4TS U2519 ( .AN(n3715), .B(n3714), .C(n6140), .D(n6139), .Y(n5275) ); AOI2BB2X4TS U2520 ( .B0(n5948), .B1(n2194), .A0N(n5947), .A1N(n2204), .Y( n3960) ); NAND3X4TS U2521 ( .A(n2998), .B(n2997), .C(n2996), .Y(n2995) ); OAI21X2TS U2522 ( .A0(n2904), .A1(n5005), .B0(n2903), .Y(n1162) ); NAND2X8TS U2523 ( .A(n2968), .B(n4320), .Y(n6381) ); OAI22X4TS U2524 ( .A0(n6037), .A1(n6036), .B0(n6039), .B1(n6038), .Y(n3721) ); AOI21X4TS U2525 ( .A0(n5777), .A1(n2131), .B0(n5776), .Y(n3720) ); NAND3X2TS U2526 ( .A(n3690), .B(n3691), .C(n3689), .Y(n1228) ); CLKINVX12TS U2527 ( .A(n4656), .Y(n6410) ); NAND2X8TS U2528 ( .A(n3139), .B(n3137), .Y(n4656) ); NAND2X4TS U2529 ( .A(n5153), .B(n4487), .Y(n2998) ); NAND2X8TS U2530 ( .A(n4091), .B(n4090), .Y(n5153) ); OAI22X2TS U2531 ( .A0(n1916), .A1(n5249), .B0(n5287), .B1(n5527), .Y(n1080) ); MX2X4TS U2532 ( .A(n5090), .B(Raw_mant_NRM_SWR[22]), .S0(n5205), .Y(n1176) ); AOI2BB1X4TS U2533 ( .A0N(n6440), .A1N(n5159), .B0(n2380), .Y(n2588) ); NOR2X8TS U2534 ( .A(n4616), .B(n4615), .Y(n5266) ); AOI22X2TS U2535 ( .A0(n2982), .A1(Raw_mant_NRM_SWR[13]), .B0(n5014), .B1( n6230), .Y(n6361) ); NOR2X6TS U2536 ( .A(n3384), .B(DMP_SFG[20]), .Y(n4751) ); NAND2X4TS U2537 ( .A(DMP_SFG[20]), .B(n3384), .Y(n5085) ); NOR2X6TS U2538 ( .A(n3005), .B(n3000), .Y(n2999) ); NAND4BX4TS U2539 ( .AN(n4664), .B(n6164), .C(n4663), .D(n6163), .Y(n5043) ); OAI22X2TS U2540 ( .A0(n6071), .A1(n6070), .B0(n6069), .B1(n6068), .Y(n4664) ); NAND2X2TS U2541 ( .A(n5932), .B(n5931), .Y(n4663) ); OAI22X4TS U2542 ( .A0(n6052), .A1(n2187), .B0(n6051), .B1(n6050), .Y(n3718) ); AOI21X4TS U2543 ( .A0(n4047), .A1(n5923), .B0(n5922), .Y(n3717) ); NOR4X2TS U2544 ( .A(n4224), .B(n4223), .C(n4222), .D(n4221), .Y(n4225) ); NAND4X2TS U2545 ( .A(n4209), .B(n4208), .C(n4207), .D(n4206), .Y(n4224) ); NAND2X8TS U2546 ( .A(n4131), .B(n2939), .Y(n1143) ); NAND2X4TS U2547 ( .A(n4412), .B(intDX_EWSW[26]), .Y(n4422) ); AOI22X4TS U2548 ( .A0(n5930), .A1(n2163), .B0(n5929), .B1(n2207), .Y(n3829) ); NOR2X8TS U2549 ( .A(n6353), .B(n3022), .Y(n3047) ); INVX6TS U2550 ( .A(n2653), .Y(n2906) ); AOI22X2TS U2551 ( .A0(n4659), .A1(n1644), .B0(n2780), .B1(n5036), .Y(n4048) ); NAND4BX2TS U2552 ( .AN(n3715), .B(n3714), .C(n6140), .D(n6139), .Y(n2297) ); NAND2X4TS U2553 ( .A(n6206), .B(n1986), .Y(n2016) ); BUFX20TS U2554 ( .A(n4430), .Y(n2041) ); NAND3X6TS U2555 ( .A(n4420), .B(n4419), .C(n4418), .Y(n1577) ); NAND2X4TS U2556 ( .A(n4863), .B(intDX_EWSW[10]), .Y(n4419) ); NAND2X4TS U2557 ( .A(n4877), .B(intDX_EWSW[5]), .Y(n4401) ); NAND3X4TS U2558 ( .A(n4450), .B(n4451), .C(n4449), .Y(n1202) ); BUFX20TS U2559 ( .A(n3261), .Y(n3234) ); NAND3X4TS U2560 ( .A(n4829), .B(n4830), .C(n4828), .Y(n1264) ); NAND3X4TS U2561 ( .A(n4841), .B(n4842), .C(n4840), .Y(n1258) ); NAND2X2TS U2562 ( .A(n2529), .B(n1628), .Y(n4294) ); NAND2X2TS U2563 ( .A(n6461), .B(n6215), .Y(n6415) ); NAND2X2TS U2564 ( .A(n6439), .B(n6215), .Y(n6434) ); AND2X6TS U2565 ( .A(n4424), .B(intDX_EWSW[22]), .Y(n2281) ); NAND2X4TS U2566 ( .A(n2115), .B(intDY_EWSW[56]), .Y(n4450) ); NAND2X4TS U2567 ( .A(n5157), .B(n4691), .Y(n2579) ); OAI21X2TS U2568 ( .A0(n3209), .A1(n2550), .B0(n3267), .Y(n1145) ); NAND3X4TS U2569 ( .A(n3579), .B(n3580), .C(n3578), .Y(n1222) ); NOR2X4TS U2570 ( .A(n3398), .B(DMP_SFG[37]), .Y(n4926) ); NAND2X4TS U2571 ( .A(n3846), .B(n5262), .Y(n4530) ); NAND2X4TS U2572 ( .A(n2261), .B(n5262), .Y(n4060) ); NAND2X4TS U2573 ( .A(n4416), .B(intDX_EWSW[51]), .Y(n4110) ); OAI22X2TS U2574 ( .A0(n1916), .A1(n4092), .B0(n5289), .B1(n5544), .Y(n1075) ); NAND3X6TS U2575 ( .A(n3672), .B(n3673), .C(n3671), .Y(n1569) ); NAND2X4TS U2576 ( .A(n4863), .B(intDX_EWSW[18]), .Y(n3672) ); NAND2X2TS U2577 ( .A(n3630), .B(intDX_EWSW[24]), .Y(n4833) ); NAND2BX2TS U2578 ( .AN(n2965), .B(n4102), .Y(n1278) ); NAND3X4TS U2579 ( .A(n4872), .B(n4871), .C(n4870), .Y(n1573) ); NAND2X4TS U2580 ( .A(n4379), .B(intDX_EWSW[14]), .Y(n4871) ); OAI22X2TS U2581 ( .A0(n3022), .A1(n2324), .B0(n4332), .B1(n5010), .Y(n5011) ); BUFX20TS U2582 ( .A(n5040), .Y(n3022) ); NAND2X4TS U2583 ( .A(n2988), .B(Raw_mant_NRM_SWR[50]), .Y(n4306) ); CLKINVX12TS U2584 ( .A(n2648), .Y(n2988) ); AOI22X2TS U2585 ( .A0(n4657), .A1(n1869), .B0(n5021), .B1(n4659), .Y(n4660) ); OAI21X4TS U2586 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n5424), .B0(n5340), .Y(n4253) ); NAND2X4TS U2587 ( .A(n4078), .B(n1816), .Y(n1574) ); NAND3X6TS U2588 ( .A(n3670), .B(n3669), .C(n3668), .Y(n1570) ); INVX16TS U2589 ( .A(n2934), .Y(n2287) ); NAND3X6TS U2590 ( .A(n4075), .B(n4076), .C(n4074), .Y(n1580) ); INVX16TS U2591 ( .A(n6202), .Y(n2496) ); NAND2X2TS U2592 ( .A(n6381), .B(n6408), .Y(n6382) ); NAND2X2TS U2593 ( .A(n6408), .B(n4321), .Y(n6327) ); NAND2X2TS U2594 ( .A(n4412), .B(intDY_EWSW[49]), .Y(n4850) ); NAND2X6TS U2595 ( .A(n2951), .B(n1815), .Y(n3576) ); AOI22X2TS U2596 ( .A0(n2982), .A1(Raw_mant_NRM_SWR[7]), .B0(n5024), .B1( n5041), .Y(n6346) ); NOR2X8TS U2597 ( .A(n4939), .B(n4983), .Y(n3070) ); INVX12TS U2598 ( .A(n4965), .Y(n1921) ); NOR2X8TS U2599 ( .A(n2972), .B(n1899), .Y(n6388) ); AND2X6TS U2600 ( .A(n6203), .B(DmP_mant_SHT1_SW[43]), .Y(n1899) ); NAND3X6TS U2601 ( .A(n4411), .B(n4410), .C(n4409), .Y(n1578) ); NAND2X4TS U2602 ( .A(n4877), .B(intDX_EWSW[9]), .Y(n4410) ); BUFX20TS U2603 ( .A(n3087), .Y(n2531) ); NAND2X4TS U2604 ( .A(n2494), .B(n5175), .Y(n1595) ); NAND2X4TS U2605 ( .A(n2494), .B(n5177), .Y(n1597) ); NAND2X4TS U2606 ( .A(n2494), .B(n5179), .Y(n1593) ); NAND2X4TS U2607 ( .A(n2494), .B(n5181), .Y(n1589) ); NAND2X4TS U2608 ( .A(n2494), .B(n5165), .Y(n1596) ); NAND2X4TS U2609 ( .A(n2494), .B(n5173), .Y(n1591) ); NAND2X4TS U2610 ( .A(n2494), .B(n5171), .Y(n1594) ); NAND2X4TS U2611 ( .A(n2494), .B(n5167), .Y(n1590) ); NAND2X4TS U2612 ( .A(n2494), .B(n5168), .Y(n1592) ); NAND2X4TS U2613 ( .A(n2494), .B(n5170), .Y(n1598) ); AOI22X2TS U2614 ( .A0(n6218), .A1(Raw_mant_NRM_SWR[21]), .B0(n6199), .B1( DmP_mant_SHT1_SW[28]), .Y(n6340) ); AOI22X2TS U2615 ( .A0(n6218), .A1(n1856), .B0(n6199), .B1( DmP_mant_SHT1_SW[45]), .Y(n6367) ); NAND2X4TS U2616 ( .A(n6199), .B(DmP_mant_SHT1_SW[22]), .Y(n6298) ); NAND2X4TS U2617 ( .A(n6199), .B(DmP_mant_SHT1_SW[16]), .Y(n6338) ); AOI22X2TS U2618 ( .A0(n6206), .A1(Raw_mant_NRM_SWR[17]), .B0(n5033), .B1( n6230), .Y(n6303) ); NAND4X6TS U2619 ( .A(n3038), .B(n4279), .C(n2647), .D(n3037), .Y(n3201) ); NAND3X4TS U2620 ( .A(n4281), .B(n4279), .C(n4280), .Y(n4282) ); NAND3X6TS U2621 ( .A(n4362), .B(n4361), .C(n4360), .Y(n1535) ); NAND2X4TS U2622 ( .A(n2116), .B(intDX_EWSW[52]), .Y(n4361) ); NAND2X2TS U2623 ( .A(n5157), .B(n1872), .Y(n1963) ); NAND2XLTS U2624 ( .A(n5264), .B(DmP_mant_SFG_SWR[30]), .Y(n3079) ); NAND2X2TS U2625 ( .A(n4379), .B(intDY_EWSW[8]), .Y(n4311) ); AOI22X4TS U2626 ( .A0(n5882), .A1(n2165), .B0(n2127), .B1(n5700), .Y(n2234) ); NAND2X2TS U2627 ( .A(n1837), .B(intDY_EWSW[50]), .Y(n4836) ); MXI2X2TS U2628 ( .A(n5394), .B(n5478), .S0(n5224), .Y(n1471) ); NAND2X4TS U2629 ( .A(n4412), .B(intDX_EWSW[51]), .Y(n4398) ); OAI22X2TS U2630 ( .A0(n5268), .A1(n2453), .B0(n5287), .B1(n5523), .Y(n1068) ); OAI22X2TS U2631 ( .A0(n2597), .A1(n2453), .B0(n5292), .B1(n5542), .Y(n1090) ); NAND2X2TS U2632 ( .A(n2535), .B(DmP_EXP_EWSW[2]), .Y(n4373) ); NAND2X4TS U2633 ( .A(n4417), .B(DmP_EXP_EWSW[40]), .Y(n3683) ); NAND2X4TS U2634 ( .A(n2536), .B(DMP_EXP_EWSW[6]), .Y(n4443) ); AND2X4TS U2635 ( .A(n5176), .B(n5169), .Y(n4017) ); INVX6TS U2636 ( .A(n2011), .Y(n3982) ); NAND2X6TS U2637 ( .A(DMP_exp_NRM2_EW[1]), .B(n2308), .Y(n3981) ); OR3X8TS U2638 ( .A(n2281), .B(n2280), .C(n2282), .Y(n1266) ); NOR2X8TS U2639 ( .A(n3327), .B(intDY_EWSW[2]), .Y(n3413) ); NAND2X6TS U2640 ( .A(n2951), .B(intDX_EWSW[48]), .Y(n4390) ); INVX6TS U2641 ( .A(n6214), .Y(n2306) ); NAND2X6TS U2642 ( .A(n3249), .B(n1996), .Y(n1995) ); NAND2BX4TS U2643 ( .AN(n1818), .B(n2951), .Y(n3684) ); BUFX16TS U2644 ( .A(n5027), .Y(n6219) ); NOR2X8TS U2645 ( .A(n3083), .B(n2398), .Y(n3082) ); INVX6TS U2646 ( .A(n4026), .Y(n6200) ); NAND2X4TS U2647 ( .A(n5047), .B(n2780), .Y(n3868) ); NAND3X6TS U2648 ( .A(n3647), .B(n3648), .C(n3646), .Y(n1555) ); NOR3X8TS U2649 ( .A(n4268), .B(Raw_mant_NRM_SWR[30]), .C(n3770), .Y(n2983) ); NAND2X8TS U2650 ( .A(n1820), .B(n1819), .Y(n2693) ); AND2X8TS U2651 ( .A(n2697), .B(n2698), .Y(n1819) ); OR2X8TS U2652 ( .A(n2436), .B(n2379), .Y(n1820) ); MX2X6TS U2653 ( .A(n6433), .B(n5564), .S0(n5245), .Y(n5160) ); OAI21X4TS U2654 ( .A0(n3751), .A1(Raw_mant_NRM_SWR[17]), .B0(n5440), .Y( n3754) ); NAND2X2TS U2655 ( .A(n2691), .B(n4487), .Y(n3090) ); AOI22X4TS U2656 ( .A0(n5957), .A1(n4047), .B0(n5874), .B1(n2192), .Y(n2813) ); INVX12TS U2657 ( .A(n5928), .Y(n4047) ); NOR2X8TS U2658 ( .A(n2812), .B(n2814), .Y(n2811) ); AOI22X4TS U2659 ( .A0(n4061), .A1(n1876), .B0(n5150), .B1(n5145), .Y(n4092) ); NAND3X8TS U2660 ( .A(n4057), .B(n4056), .C(n4058), .Y(n4061) ); NOR2X6TS U2661 ( .A(n2937), .B(n1911), .Y(n2033) ); AND2X8TS U2662 ( .A(n3989), .B(n1821), .Y(n2936) ); NOR2X4TS U2663 ( .A(n3987), .B(n3984), .Y(n1821) ); INVX4TS U2664 ( .A(n2966), .Y(n1822) ); NAND2X4TS U2665 ( .A(n1822), .B(n4104), .Y(n1214) ); AOI22X2TS U2666 ( .A0(n6219), .A1(n2012), .B0(n5031), .B1(n6228), .Y(n6350) ); BUFX6TS U2667 ( .A(Raw_mant_NRM_SWR[34]), .Y(n1825) ); NAND3X6TS U2668 ( .A(n2001), .B(n1999), .C(n1894), .Y(n1998) ); NAND2X8TS U2669 ( .A(n2285), .B(n2843), .Y(n2750) ); BUFX16TS U2670 ( .A(n5027), .Y(n6218) ); BUFX20TS U2671 ( .A(n2470), .Y(n2088) ); BUFX20TS U2672 ( .A(n3087), .Y(n4424) ); NAND3X8TS U2673 ( .A(n3244), .B(n4249), .C(n3243), .Y(n2034) ); NAND3X8TS U2674 ( .A(n3073), .B(n3072), .C(n3071), .Y(n4604) ); NAND2X2TS U2675 ( .A(n4473), .B(n4672), .Y(n3844) ); NAND2X8TS U2676 ( .A(n1990), .B(n1991), .Y(n1992) ); NOR2X8TS U2677 ( .A(n4246), .B(n3731), .Y(n2942) ); BUFX20TS U2678 ( .A(n3087), .Y(n2530) ); NAND2X4TS U2679 ( .A(n4369), .B(n2945), .Y(n4802) ); NAND3X6TS U2680 ( .A(n3590), .B(n3589), .C(n3588), .Y(n1528) ); OAI2BB1X4TS U2681 ( .A0N(n5149), .A1N(n6439), .B0(n2588), .Y(n1037) ); OAI21X4TS U2682 ( .A0(n2685), .A1(n3559), .B0(n1829), .Y(n3570) ); AOI21X4TS U2683 ( .A0(n2682), .A1(n2684), .B0(n2681), .Y(n1829) ); NAND2X8TS U2684 ( .A(n5580), .B(n3726), .Y(n2890) ); NAND2X8TS U2685 ( .A(n2921), .B(n5084), .Y(n2915) ); NOR2X8TS U2686 ( .A(n1830), .B(n2603), .Y(n3108) ); NAND2X8TS U2687 ( .A(n2601), .B(n2602), .Y(n1830) ); NAND2X8TS U2688 ( .A(n3240), .B(Raw_mant_NRM_SWR[25]), .Y(n4281) ); BUFX20TS U2689 ( .A(n3123), .Y(n3125) ); OAI2BB1X4TS U2690 ( .A0N(n5051), .A1N(n4659), .B0(n4117), .Y(n3083) ); MXI2X4TS U2691 ( .A(n2349), .B(n5445), .S0(n4997), .Y(n1168) ); BUFX20TS U2692 ( .A(n2114), .Y(n4863) ); NAND2BX4TS U2693 ( .AN(n2445), .B(n4110), .Y(n2956) ); NOR2X6TS U2694 ( .A(n3318), .B(n2292), .Y(n3556) ); NAND2X6TS U2695 ( .A(n3100), .B(n3099), .Y(n3098) ); NOR2X8TS U2696 ( .A(n3103), .B(n1831), .Y(n5255) ); AND4X8TS U2697 ( .A(n1832), .B(n4902), .C(n4285), .D(n4284), .Y(n2483) ); OR3X6TS U2698 ( .A(n2277), .B(n2265), .C(n4392), .Y(n1540) ); NOR2X8TS U2699 ( .A(n1833), .B(n3065), .Y(n5257) ); OAI2BB1X4TS U2700 ( .A0N(n5139), .A1N(n5158), .B0(n4650), .Y(n1833) ); NOR2X4TS U2701 ( .A(n3329), .B(DMP_EXP_EWSW[52]), .Y(n5311) ); XNOR2X4TS U2702 ( .A(n2488), .B(DmP_mant_SFG_SWR[23]), .Y(n3385) ); INVX12TS U2703 ( .A(n3128), .Y(n2636) ); BUFX6TS U2704 ( .A(n2937), .Y(n2916) ); INVX2TS U2705 ( .A(n5283), .Y(n1835) ); BUFX20TS U2706 ( .A(n2334), .Y(n2653) ); BUFX20TS U2707 ( .A(n3125), .Y(n1836) ); BUFX20TS U2708 ( .A(n4790), .Y(n1837) ); BUFX20TS U2709 ( .A(n3087), .Y(n1838) ); NAND2X2TS U2710 ( .A(n2963), .B(intDY_EWSW[52]), .Y(n4362) ); NAND2X2TS U2711 ( .A(n4430), .B(intDY_EWSW[58]), .Y(n4359) ); NAND2X2TS U2712 ( .A(n3587), .B(n2024), .Y(n4872) ); NAND2X2TS U2713 ( .A(n1836), .B(n2050), .Y(n4411) ); NAND2X4TS U2714 ( .A(n2963), .B(intDY_EWSW[13]), .Y(n4079) ); BUFX20TS U2715 ( .A(n4431), .Y(n2049) ); BUFX20TS U2716 ( .A(n2114), .Y(n4877) ); OR2X6TS U2717 ( .A(n2936), .B(n3988), .Y(n2285) ); OR2X6TS U2718 ( .A(n2936), .B(n3988), .Y(n2286) ); AND2X4TS U2719 ( .A(n3748), .B(n3264), .Y(n3263) ); INVX12TS U2720 ( .A(n3264), .Y(n4268) ); NAND2X4TS U2721 ( .A(n3122), .B(n4586), .Y(n3121) ); NAND2X2TS U2722 ( .A(n4807), .B(intDX_EWSW[24]), .Y(n4414) ); NAND2X8TS U2723 ( .A(n2344), .B(DMP_SFG[14]), .Y(n5316) ); NAND2X6TS U2724 ( .A(n3270), .B(n5279), .Y(n2344) ); NAND2X2TS U2725 ( .A(n4425), .B(intDX_EWSW[37]), .Y(n3632) ); NAND2X4TS U2726 ( .A(n2336), .B(n4998), .Y(n2756) ); XOR2X4TS U2727 ( .A(n3408), .B(n1841), .Y(n3409) ); AOI2BB2X4TS U2728 ( .B0(n1842), .B1(n1843), .A0N(n1844), .A1N(n1845), .Y( n3854) ); NOR2X8TS U2729 ( .A(n3193), .B(n3192), .Y(n2870) ); NAND4X6TS U2730 ( .A(n3188), .B(n2476), .C(n3187), .D(n3194), .Y(n3193) ); CLKINVX6TS U2731 ( .A(n2866), .Y(n2865) ); NAND2X6TS U2732 ( .A(n2977), .B(n3797), .Y(n2853) ); OAI22X2TS U2733 ( .A0(n1916), .A1(n5288), .B0(n5287), .B1(n5507), .Y(n1056) ); OAI21X2TS U2734 ( .A0(n5288), .A1(n5218), .B0(n2953), .Y(n1017) ); OAI2BB2X2TS U2735 ( .B0(n2232), .B1(n2151), .A0N(n2221), .A1N(n2222), .Y( n4299) ); AND2X8TS U2736 ( .A(n3793), .B(n3735), .Y(n1849) ); NAND3X6TS U2737 ( .A(n3684), .B(n3685), .C(n3683), .Y(n1230) ); NAND2X8TS U2738 ( .A(n1850), .B(n3850), .Y(n5037) ); INVX16TS U2739 ( .A(n2492), .Y(n1851) ); INVX4TS U2740 ( .A(n1856), .Y(n1857) ); NAND2X8TS U2741 ( .A(n2983), .B(n3771), .Y(n3248) ); NAND2X4TS U2742 ( .A(n3846), .B(n5047), .Y(n3100) ); NAND3X4TS U2743 ( .A(n1910), .B(n5164), .C(n4017), .Y(n3129) ); NOR3X8TS U2744 ( .A(n2620), .B(n2618), .C(n3781), .Y(n2967) ); NAND4BX4TS U2745 ( .AN(n4036), .B(n4035), .C(n4034), .D(n6170), .Y(n1859) ); NAND4BX2TS U2746 ( .AN(n4036), .B(n4035), .C(n4034), .D(n6170), .Y(n5022) ); NAND4X8TS U2747 ( .A(n3216), .B(n3212), .C(n3215), .D(n2386), .Y(n2466) ); MX2X4TS U2748 ( .A(n4745), .B(Raw_mant_NRM_SWR[23]), .S0(n5089), .Y(n1175) ); AND2X8TS U2749 ( .A(n4249), .B(n2935), .Y(n3034) ); NOR3X4TS U2750 ( .A(n3747), .B(Raw_mant_NRM_SWR[23]), .C( Raw_mant_NRM_SWR[19]), .Y(n3749) ); NAND2X8TS U2751 ( .A(n2915), .B(n2279), .Y(n3182) ); NAND2X6TS U2752 ( .A(n2636), .B(n2635), .Y(n2470) ); CLKINVX12TS U2753 ( .A(Raw_mant_NRM_SWR[50]), .Y(n2056) ); BUFX12TS U2754 ( .A(n4790), .Y(n4379) ); AOI21X2TS U2755 ( .A0(n2019), .A1(n6205), .B0(n5011), .Y(n6407) ); OAI21X4TS U2756 ( .A0(n5073), .A1(n5076), .B0(n5077), .Y(n2289) ); OAI21X2TS U2757 ( .A0(n5073), .A1(n5076), .B0(n5077), .Y(n5082) ); NAND2X8TS U2758 ( .A(n3381), .B(n5064), .Y(n2634) ); BUFX20TS U2759 ( .A(n3123), .Y(n3087) ); OR2X8TS U2760 ( .A(n2936), .B(n3988), .Y(n1865) ); AOI22X1TS U2761 ( .A0(n2982), .A1(Raw_mant_NRM_SWR[22]), .B0(n2873), .B1( n5021), .Y(n6309) ); NAND2X2TS U2762 ( .A(n4412), .B(n2310), .Y(n4377) ); NAND2X2TS U2763 ( .A(n4425), .B(intDX_EWSW[36]), .Y(n3622) ); NAND2X2TS U2764 ( .A(n4379), .B(n2737), .Y(n4404) ); AND2X8TS U2765 ( .A(n4838), .B(n2017), .Y(n2023) ); NAND3X6TS U2766 ( .A(n4029), .B(n4028), .C(n3025), .Y(n5040) ); NOR2X8TS U2767 ( .A(LZD_output_NRM2_EW[2]), .B(n1867), .Y(n1866) ); INVX16TS U2768 ( .A(n5283), .Y(n2494) ); INVX8TS U2769 ( .A(n2657), .Y(n2676) ); INVX16TS U2770 ( .A(n2002), .Y(n3262) ); NAND2X6TS U2771 ( .A(n3262), .B(n2621), .Y(n3195) ); NAND3X4TS U2772 ( .A(n4296), .B(n4295), .C(n4294), .Y(n4297) ); AOI22X4TS U2773 ( .A0(n5693), .A1(n5692), .B0(n5691), .B1(n2153), .Y(n4030) ); BUFX12TS U2774 ( .A(n2114), .Y(n4873) ); BUFX20TS U2775 ( .A(n5227), .Y(n1868) ); MXI2X4TS U2776 ( .A(n5380), .B(n5471), .S0(n5227), .Y(n1429) ); MXI2X4TS U2777 ( .A(n5379), .B(n5483), .S0(n5227), .Y(n1426) ); MXI2X4TS U2778 ( .A(n5382), .B(n5475), .S0(n5227), .Y(n1435) ); MXI2X4TS U2779 ( .A(n5384), .B(n5472), .S0(n5227), .Y(n1441) ); BUFX20TS U2780 ( .A(n2764), .Y(n5227) ); NAND2X2TS U2781 ( .A(n4425), .B(intDX_EWSW[25]), .Y(n4428) ); NAND2X2TS U2782 ( .A(n4412), .B(intDY_EWSW[4]), .Y(n4115) ); NAND2X2TS U2783 ( .A(n1837), .B(intDY_EWSW[0]), .Y(n4381) ); NAND2X2TS U2784 ( .A(n1837), .B(n2295), .Y(n4866) ); NAND2X2TS U2785 ( .A(n2116), .B(intDY_EWSW[57]), .Y(n4788) ); NAND2X2TS U2786 ( .A(n4600), .B(shift_value_SHT2_EWR[4]), .Y(n1958) ); NAND2X6TS U2787 ( .A(n1917), .B(n1869), .Y(n4039) ); INVX16TS U2788 ( .A(n1870), .Y(n1871) ); INVX4TS U2789 ( .A(n1870), .Y(n1872) ); NAND2X2TS U2790 ( .A(n1837), .B(intDX_EWSW[23]), .Y(n4407) ); CLKINVX12TS U2791 ( .A(n4488), .Y(n1874) ); INVX16TS U2792 ( .A(n2559), .Y(n1875) ); NOR2X4TS U2793 ( .A(n3540), .B(n2863), .Y(n2862) ); INVX2TS U2794 ( .A(n2751), .Y(n3777) ); NOR2X6TS U2795 ( .A(Raw_mant_NRM_SWR[48]), .B(Raw_mant_NRM_SWR[47]), .Y( n3787) ); NAND2BX2TS U2796 ( .AN(n6089), .B(n2407), .Y(n2695) ); XNOR2X2TS U2797 ( .A(intDX_EWSW[28]), .B(n2745), .Y(n4191) ); NAND2X2TS U2798 ( .A(n5023), .B(n2780), .Y(n2108) ); NAND2X2TS U2799 ( .A(n2261), .B(n4620), .Y(n3965) ); XNOR2X1TS U2800 ( .A(intDX_EWSW[11]), .B(intDY_EWSW[11]), .Y(n4219) ); NOR2BX2TS U2801 ( .AN(shift_value_SHT2_EWR[4]), .B(n2331), .Y(n4487) ); NOR2X1TS U2802 ( .A(n4752), .B(n4755), .Y(n4758) ); NOR2X4TS U2803 ( .A(n2111), .B(n4266), .Y(n2110) ); OA22X2TS U2804 ( .A0(n6010), .A1(n6009), .B0(n6008), .B1(n6007), .Y(n3930) ); INVX2TS U2805 ( .A(n4585), .Y(n2030) ); NAND2X2TS U2806 ( .A(n2262), .B(n5018), .Y(n3974) ); NAND2X1TS U2807 ( .A(n4141), .B(n3287), .Y(n3286) ); NAND2X1TS U2808 ( .A(n3296), .B(n3870), .Y(n2363) ); NAND2X2TS U2809 ( .A(n5835), .B(n2162), .Y(n3933) ); AND2X2TS U2810 ( .A(n4923), .B(n4921), .Y(n2364) ); OAI21X2TS U2811 ( .A0(n5096), .A1(n5095), .B0(n5094), .Y(n5099) ); AOI22X2TS U2812 ( .A0(n4618), .A1(n2519), .B0(n5143), .B1(n2517), .Y(n2775) ); NAND2X1TS U2813 ( .A(n3087), .B(intDX_EWSW[19]), .Y(n4859) ); INVX4TS U2814 ( .A(DmP_mant_SFG_SWR[28]), .Y(n2758) ); NAND2X1TS U2815 ( .A(n5271), .B(DmP_mant_SFG_SWR[25]), .Y(n3101) ); CLKBUFX2TS U2816 ( .A(intDY_EWSW[15]), .Y(n2035) ); NAND2X2TS U2817 ( .A(n2530), .B(intDY_EWSW[48]), .Y(n4391) ); CLKBUFX2TS U2818 ( .A(intDY_EWSW[43]), .Y(n2051) ); NOR2X1TS U2819 ( .A(n2449), .B(n1916), .Y(n6462) ); AND2X8TS U2820 ( .A(n3296), .B(n3872), .Y(n1895) ); AND3X6TS U2821 ( .A(n3218), .B(n3272), .C(n3396), .Y(n1896) ); AND2X4TS U2822 ( .A(n2262), .B(n5047), .Y(n1897) ); NOR2X6TS U2823 ( .A(n2885), .B(n2884), .Y(n2883) ); OR4X2TS U2824 ( .A(Raw_mant_NRM_SWR[38]), .B(Raw_mant_NRM_SWR[40]), .C(n5345), .D(n5029), .Y(n1904) ); AND2X8TS U2825 ( .A(n3738), .B(n4270), .Y(n1905) ); OR2X8TS U2826 ( .A(n6353), .B(n4070), .Y(n1906) ); NOR2X4TS U2827 ( .A(n3394), .B(DMP_SFG[34]), .Y(n4915) ); OA21X4TS U2828 ( .A0(n4891), .A1(n5424), .B0(n4890), .Y(n1908) ); OR2X8TS U2829 ( .A(n2034), .B(n2403), .Y(n1909) ); XNOR2X4TS U2830 ( .A(n2285), .B(n4013), .Y(n1910) ); OR2X6TS U2831 ( .A(n3992), .B(n5166), .Y(n1911) ); NAND2X6TS U2832 ( .A(n3378), .B(DMP_SFG[13]), .Y(n5279) ); CLKINVX12TS U2833 ( .A(Raw_mant_NRM_SWR[45]), .Y(n1912) ); INVX16TS U2834 ( .A(n1912), .Y(n1913) ); NAND2X2TS U2835 ( .A(n4877), .B(n2051), .Y(n3585) ); NAND2X2TS U2836 ( .A(n4369), .B(intDY_EWSW[13]), .Y(n3814) ); NAND2X2TS U2837 ( .A(n4877), .B(intDX_EWSW[1]), .Y(n4875) ); NAND2X2TS U2838 ( .A(n4369), .B(intDX_EWSW[44]), .Y(n3610) ); NAND2X2TS U2839 ( .A(n4877), .B(intDX_EWSW[41]), .Y(n3601) ); INVX4TS U2840 ( .A(n4263), .Y(n2113) ); INVX4TS U2841 ( .A(n2023), .Y(n4109) ); INVX3TS U2842 ( .A(n4946), .Y(n2121) ); INVX3TS U2843 ( .A(n3171), .Y(n3170) ); OAI21X2TS U2844 ( .A0(n2432), .A1(n3887), .B0(n2659), .Y(n2658) ); AND2X6TS U2845 ( .A(n3090), .B(n3089), .Y(n2424) ); INVX2TS U2846 ( .A(n4137), .Y(n3169) ); NAND2X2TS U2847 ( .A(n3887), .B(n4021), .Y(n2659) ); NAND2X4TS U2848 ( .A(n1967), .B(n1968), .Y(n1966) ); INVX6TS U2849 ( .A(n5023), .Y(n4661) ); INVX2TS U2850 ( .A(n4645), .Y(n2283) ); NOR2X4TS U2851 ( .A(n4958), .B(n3207), .Y(n4769) ); INVX8TS U2852 ( .A(n5191), .Y(n3157) ); NAND2X2TS U2853 ( .A(n4473), .B(n4707), .Y(n4045) ); INVX4TS U2854 ( .A(n3906), .Y(n1964) ); BUFX12TS U2855 ( .A(n5233), .Y(n5235) ); BUFX8TS U2856 ( .A(n5034), .Y(n1917) ); BUFX12TS U2857 ( .A(n5233), .Y(n5253) ); BUFX12TS U2858 ( .A(n5233), .Y(n5236) ); AND2X2TS U2859 ( .A(n4985), .B(n4984), .Y(n2356) ); BUFX12TS U2860 ( .A(n5233), .Y(n5258) ); BUFX8TS U2861 ( .A(n2764), .Y(n5216) ); BUFX20TS U2862 ( .A(n5259), .Y(n2764) ); BUFX8TS U2863 ( .A(n5259), .Y(n5159) ); NAND2X2TS U2864 ( .A(n2261), .B(Data_array_SWR_3__53_), .Y(n3869) ); BUFX8TS U2865 ( .A(n5259), .Y(n5271) ); BUFX8TS U2866 ( .A(n5259), .Y(n5224) ); OR2X4TS U2867 ( .A(n3706), .B(n2096), .Y(n5013) ); NAND2X2TS U2868 ( .A(n1919), .B(n4518), .Y(n4091) ); BUFX8TS U2869 ( .A(n5259), .Y(n5245) ); AND2X2TS U2870 ( .A(n3912), .B(n3911), .Y(n2367) ); NAND2X1TS U2871 ( .A(n2513), .B(LZD_output_NRM2_EW[3]), .Y(n3196) ); INVX2TS U2872 ( .A(n4747), .Y(n4737) ); BUFX6TS U2873 ( .A(n5234), .Y(n5233) ); NAND2X1TS U2874 ( .A(n4396), .B(DMP_EXP_EWSW[42]), .Y(n3612) ); NAND2X1TS U2875 ( .A(n4864), .B(DmP_EXP_EWSW[7]), .Y(n3819) ); NAND2X1TS U2876 ( .A(n4426), .B(DMP_EXP_EWSW[24]), .Y(n4413) ); NAND2X1TS U2877 ( .A(n4864), .B(DmP_EXP_EWSW[46]), .Y(n4096) ); NAND2X1TS U2878 ( .A(n4426), .B(DMP_EXP_EWSW[23]), .Y(n4406) ); NAND2X1TS U2879 ( .A(n4864), .B(DmP_EXP_EWSW[10]), .Y(n4313) ); NAND2X1TS U2880 ( .A(n4426), .B(DMP_EXP_EWSW[29]), .Y(n3649) ); INVX2TS U2881 ( .A(n4994), .Y(n3134) ); NAND2X1TS U2882 ( .A(n4997), .B(Raw_mant_NRM_SWR[37]), .Y(n2931) ); INVX2TS U2883 ( .A(n5095), .Y(n5091) ); NAND2X1TS U2884 ( .A(n5089), .B(Raw_mant_NRM_SWR[46]), .Y(n2954) ); INVX2TS U2885 ( .A(n2228), .Y(n3927) ); NAND2X1TS U2886 ( .A(n4396), .B(DMP_EXP_EWSW[49]), .Y(n4393) ); NAND2X1TS U2887 ( .A(n4853), .B(DmP_EXP_EWSW[31]), .Y(n4817) ); NAND2X1TS U2888 ( .A(n4396), .B(DMP_EXP_EWSW[51]), .Y(n4397) ); NAND2X1TS U2889 ( .A(n4853), .B(DmP_EXP_EWSW[30]), .Y(n4792) ); NAND2X1TS U2890 ( .A(n4417), .B(DMP_EXP_EWSW[0]), .Y(n4383) ); NAND2X1TS U2891 ( .A(n4853), .B(DmP_EXP_EWSW[24]), .Y(n4831) ); NAND2X1TS U2892 ( .A(n4853), .B(DmP_EXP_EWSW[37]), .Y(n4820) ); INVX2TS U2893 ( .A(n4138), .Y(n4140) ); NAND2X1TS U2894 ( .A(n4853), .B(DmP_EXP_EWSW[32]), .Y(n4804) ); NAND2X6TS U2895 ( .A(n3516), .B(n3563), .Y(n3566) ); NAND2X1TS U2896 ( .A(n4396), .B(DMP_EXP_EWSW[45]), .Y(n3603) ); NAND2X1TS U2897 ( .A(n4396), .B(DMP_EXP_EWSW[46]), .Y(n3594) ); NAND4BBX2TS U2898 ( .AN(n2796), .BN(n5926), .C(n6156), .D(n2067), .Y(n2066) ); NAND2X1TS U2899 ( .A(n4853), .B(DmP_EXP_EWSW[33]), .Y(n4801) ); NAND2X1TS U2900 ( .A(n4853), .B(DmP_EXP_EWSW[36]), .Y(n4814) ); NAND2X4TS U2901 ( .A(n3385), .B(DMP_SFG[21]), .Y(n4742) ); INVX8TS U2902 ( .A(n5200), .Y(n5202) ); INVX8TS U2903 ( .A(n5200), .Y(n5203) ); NAND2X1TS U2904 ( .A(n2535), .B(DMP_EXP_EWSW[1]), .Y(n4874) ); INVX8TS U2905 ( .A(n5200), .Y(n5194) ); NAND2X1TS U2906 ( .A(n2535), .B(DMP_EXP_EWSW[12]), .Y(n4440) ); NAND2BX2TS U2907 ( .AN(n3860), .B(n3859), .Y(n1943) ); INVX16TS U2908 ( .A(n5101), .Y(n2562) ); INVX4TS U2909 ( .A(n4248), .Y(n3191) ); NAND2X2TS U2910 ( .A(n2095), .B(n1898), .Y(n2090) ); MXI2X2TS U2911 ( .A(n5494), .B(inst_FSM_INPUT_ENABLE_state_reg[1]), .S0( inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n4579) ); NAND2X1TS U2912 ( .A(n2214), .B(n2144), .Y(n5189) ); NAND2X1TS U2913 ( .A(n2214), .B(n2145), .Y(n5186) ); CLKBUFX2TS U2914 ( .A(Shift_amount_SHT1_EWR[5]), .Y(n2570) ); INVX2TS U2915 ( .A(n6182), .Y(n1988) ); INVX4TS U2916 ( .A(n2257), .Y(n2258) ); INVX8TS U2917 ( .A(Raw_mant_NRM_SWR[33]), .Y(n2062) ); BUFX8TS U2918 ( .A(left_right_SHT2), .Y(n2559) ); INVX2TS U2919 ( .A(n2156), .Y(n2094) ); INVX2TS U2920 ( .A(n6011), .Y(n2095) ); INVX2TS U2921 ( .A(n5552), .Y(n2021) ); INVX12TS U2922 ( .A(n3261), .Y(n2523) ); NAND2X4TS U2923 ( .A(n3197), .B(n3196), .Y(n1125) ); NAND2X4TS U2924 ( .A(n4881), .B(n2561), .Y(n3197) ); NAND4X6TS U2925 ( .A(n2272), .B(n2113), .C(n4352), .D(n2110), .Y(n4881) ); NAND3X2TS U2926 ( .A(n4428), .B(n4429), .C(n4427), .Y(n1562) ); NAND3X2TS U2927 ( .A(n4867), .B(n4866), .C(n4865), .Y(n1300) ); NAND3X2TS U2928 ( .A(n4859), .B(n4858), .C(n4857), .Y(n1272) ); NAND2X4TS U2929 ( .A(n2112), .B(n4262), .Y(n2111) ); NOR2X4TS U2930 ( .A(n2732), .B(n3892), .Y(n2731) ); NAND2X2TS U2931 ( .A(n2877), .B(n2874), .Y(n1097) ); INVX3TS U2932 ( .A(n3181), .Y(n3914) ); NAND2X4TS U2933 ( .A(n4885), .B(n5490), .Y(n2112) ); NAND2X4TS U2934 ( .A(n3144), .B(n2828), .Y(n1031) ); NOR2X4TS U2935 ( .A(n3171), .B(n3169), .Y(n3168) ); MX2X2TS U2936 ( .A(n4739), .B(Raw_mant_NRM_SWR[25]), .S0(n5089), .Y(n1173) ); NAND2X4TS U2937 ( .A(n2733), .B(n2734), .Y(n2732) ); NAND2BX2TS U2938 ( .AN(n5490), .B(n4337), .Y(n2894) ); NAND2X4TS U2939 ( .A(n3105), .B(n3104), .Y(n3103) ); NAND2X4TS U2940 ( .A(n2785), .B(n3911), .Y(n3181) ); NOR2X4TS U2941 ( .A(n1961), .B(n1960), .Y(n1959) ); AND2X4TS U2942 ( .A(n4943), .B(n3017), .Y(n2321) ); NOR2X4TS U2943 ( .A(n2882), .B(n1936), .Y(n1935) ); NAND2X4TS U2944 ( .A(n1970), .B(n1964), .Y(n3273) ); NAND2X4TS U2945 ( .A(n6457), .B(n5161), .Y(n2939) ); NOR2X4TS U2946 ( .A(n2069), .B(n4703), .Y(n2068) ); OR2X4TS U2947 ( .A(n4137), .B(n3286), .Y(n2439) ); NAND2X4TS U2948 ( .A(n3067), .B(n3066), .Y(n3065) ); NAND2X6TS U2949 ( .A(n1966), .B(n1965), .Y(n1970) ); NAND3X4TS U2950 ( .A(n2820), .B(n2817), .C(n2816), .Y(n2815) ); NAND2X4TS U2951 ( .A(n2631), .B(n2630), .Y(n2629) ); NAND2X4TS U2952 ( .A(n4608), .B(n1872), .Y(n2801) ); NAND2X4TS U2953 ( .A(n2578), .B(n4121), .Y(n2577) ); INVX2TS U2954 ( .A(n4772), .Y(n4764) ); NOR2X4TS U2955 ( .A(n2072), .B(n2071), .Y(n2070) ); NOR2X4TS U2956 ( .A(n2819), .B(n2818), .Y(n2817) ); AND2X4TS U2957 ( .A(n3217), .B(n2728), .Y(n2727) ); NOR2X6TS U2958 ( .A(n3906), .B(n3900), .Y(n4240) ); INVX2TS U2959 ( .A(n5274), .Y(n2264) ); AOI21X2TS U2960 ( .A0(n3272), .A1(n2759), .B0(n2959), .Y(n4782) ); NAND2X4TS U2961 ( .A(n2086), .B(n2085), .Y(n2084) ); CLKMX2X2TS U2962 ( .A(Data_Y[48]), .B(intDY_EWSW[48]), .S0(n5253), .Y(n1680) ); INVX4TS U2963 ( .A(n3284), .Y(n3283) ); AND2X4TS U2964 ( .A(n3964), .B(n3966), .Y(n2802) ); INVX2TS U2965 ( .A(n2519), .Y(n3160) ); NAND2X2TS U2966 ( .A(n5216), .B(n2923), .Y(n2922) ); AND2X4TS U2967 ( .A(n4064), .B(n4065), .Y(n3044) ); NAND2X4TS U2968 ( .A(n1645), .B(n4637), .Y(n2085) ); NAND2X4TS U2969 ( .A(n3886), .B(n4018), .Y(n3900) ); CLKMX2X2TS U2970 ( .A(Data_X[46]), .B(intDX_EWSW[46]), .S0(n5238), .Y(n1748) ); CLKMX2X2TS U2971 ( .A(Data_X[39]), .B(n2028), .S0(n5239), .Y(n1755) ); NAND3X6TS U2972 ( .A(n3723), .B(n3724), .C(n3722), .Y(n4645) ); BUFX12TS U2973 ( .A(n5217), .Y(n5240) ); BUFX12TS U2974 ( .A(n5242), .Y(n5237) ); BUFX12TS U2975 ( .A(n5217), .Y(n5238) ); NOR2X4TS U2976 ( .A(n3881), .B(n5002), .Y(n3893) ); INVX2TS U2977 ( .A(n3227), .Y(n3226) ); CLKMX2X2TS U2978 ( .A(Data_Y[10]), .B(n2048), .S0(n4531), .Y(n1718) ); CLKMX2X2TS U2979 ( .A(Data_Y[14]), .B(n2024), .S0(n4531), .Y(n1714) ); CLKMX2X2TS U2980 ( .A(Data_Y[8]), .B(intDY_EWSW[8]), .S0(n4531), .Y(n1720) ); CLKMX2X2TS U2981 ( .A(Data_Y[9]), .B(n2050), .S0(n4531), .Y(n1719) ); INVX2TS U2982 ( .A(n4349), .Y(n2898) ); BUFX16TS U2983 ( .A(n4332), .Y(n5061) ); INVX6TS U2984 ( .A(n4332), .Y(n2873) ); CLKMX2X3TS U2985 ( .A(add_subt), .B(intAS), .S0(n5242), .Y(n1730) ); INVX6TS U2986 ( .A(n4332), .Y(n6228) ); NOR2X4TS U2987 ( .A(n1973), .B(n4019), .Y(n3886) ); NAND2X4TS U2988 ( .A(n3401), .B(n4988), .Y(n3255) ); BUFX8TS U2989 ( .A(n4332), .Y(n6231) ); AND2X2TS U2990 ( .A(n4334), .B(Raw_mant_NRM_SWR[0]), .Y(n2986) ); INVX6TS U2991 ( .A(n4018), .Y(n2663) ); BUFX8TS U2992 ( .A(n5234), .Y(n5252) ); NOR2X4TS U2993 ( .A(n2593), .B(n2592), .Y(n2596) ); CLKMX2X2TS U2994 ( .A(DmP_mant_SHT1_SW[8]), .B(n2312), .S0(n5207), .Y(n1293) ); CLKMX2X2TS U2995 ( .A(DmP_mant_SHT1_SW[2]), .B(DmP_EXP_EWSW[2]), .S0(n5207), .Y(n1305) ); CLKMX2X2TS U2996 ( .A(DmP_mant_SHT1_SW[51]), .B(DmP_EXP_EWSW[51]), .S0(n5213), .Y(n1207) ); CLKMX2X2TS U2997 ( .A(DmP_mant_SHT1_SW[37]), .B(DmP_EXP_EWSW[37]), .S0(n5204), .Y(n1235) ); CLKMX2X2TS U2998 ( .A(DmP_mant_SHT1_SW[26]), .B(DmP_EXP_EWSW[26]), .S0(n5204), .Y(n1257) ); INVX2TS U2999 ( .A(n4932), .Y(n4933) ); AND2X2TS U3000 ( .A(n3017), .B(n4944), .Y(n4916) ); BUFX8TS U3001 ( .A(n3365), .Y(n5145) ); BUFX4TS U3002 ( .A(n2289), .Y(n2924) ); BUFX8TS U3003 ( .A(n5259), .Y(n5265) ); BUFX12TS U3004 ( .A(n5259), .Y(n5191) ); INVX2TS U3005 ( .A(n4999), .Y(n3891) ); AND2X2TS U3006 ( .A(n1921), .B(n4978), .Y(n4966) ); AND2X2TS U3007 ( .A(n5004), .B(n5003), .Y(n2338) ); AND2X2TS U3008 ( .A(n3069), .B(n4955), .Y(n2337) ); MX2X1TS U3009 ( .A(Data_X[62]), .B(intDX_EWSW[62]), .S0(n5234), .Y(n1732) ); BUFX12TS U3010 ( .A(n3062), .Y(n5155) ); MX2X1TS U3011 ( .A(Data_Y[62]), .B(intDY_EWSW[62]), .S0(n5234), .Y(n1666) ); BUFX8TS U3012 ( .A(n5234), .Y(n5239) ); BUFX12TS U3013 ( .A(n5234), .Y(n5242) ); BUFX8TS U3014 ( .A(n3062), .Y(n5158) ); BUFX8TS U3015 ( .A(n5234), .Y(n4531) ); NOR2X4TS U3016 ( .A(n3143), .B(n3140), .Y(n3139) ); NOR2X4TS U3017 ( .A(n2823), .B(n2822), .Y(n2821) ); BUFX8TS U3018 ( .A(n5234), .Y(n5241) ); NAND4X6TS U3019 ( .A(n1926), .B(n6059), .C(n1930), .D(n1927), .Y(n5034) ); NAND2X1TS U3020 ( .A(n3652), .B(n2123), .Y(n3591) ); NAND2X1TS U3021 ( .A(n4417), .B(n2122), .Y(n3606) ); INVX2TS U3022 ( .A(n2558), .Y(n2606) ); INVX2TS U3023 ( .A(n5094), .Y(n5066) ); INVX6TS U3024 ( .A(n4915), .Y(n3017) ); AND2X2TS U3025 ( .A(n4417), .B(DmP_EXP_EWSW[51]), .Y(n2445) ); NAND2X1TS U3026 ( .A(n5089), .B(n1986), .Y(n3208) ); INVX8TS U3027 ( .A(n5200), .Y(n5204) ); INVX2TS U3028 ( .A(n3883), .Y(n3884) ); INVX8TS U3029 ( .A(n4997), .Y(n5208) ); NAND2BX1TS U3030 ( .AN(n5504), .B(n5571), .Y(n2991) ); AND2X2TS U3031 ( .A(n4864), .B(DmP_EXP_EWSW[16]), .Y(n2446) ); INVX8TS U3032 ( .A(n5200), .Y(n5211) ); AND2X2TS U3033 ( .A(n4417), .B(DmP_EXP_EWSW[48]), .Y(n2447) ); INVX8TS U3034 ( .A(n5200), .Y(n5213) ); INVX8TS U3035 ( .A(n5200), .Y(n5206) ); INVX8TS U3036 ( .A(n5200), .Y(n5207) ); NAND2X1TS U3037 ( .A(n2244), .B(n2145), .Y(n4467) ); NAND2X1TS U3038 ( .A(n2244), .B(n2149), .Y(n5190) ); NAND2X1TS U3039 ( .A(n2244), .B(n2144), .Y(n5185) ); INVX8TS U3040 ( .A(n5284), .Y(n5198) ); INVX8TS U3041 ( .A(n5284), .Y(n5199) ); NAND2X1TS U3042 ( .A(n6293), .B(SIGN_FLAG_SHT1SHT2), .Y(n3119) ); NAND2X4TS U3043 ( .A(n2599), .B(n2598), .Y(n3822) ); INVX2TS U3044 ( .A(n1876), .Y(n1936) ); AND4X6TS U3045 ( .A(n3957), .B(n3956), .C(n3955), .D(n3954), .Y(n2266) ); NAND2BX2TS U3046 ( .AN(n6014), .B(n2092), .Y(n2091) ); NOR2X4TS U3047 ( .A(n4042), .B(n3076), .Y(n2920) ); BUFX8TS U3048 ( .A(n2993), .Y(n2522) ); INVX16TS U3049 ( .A(n5101), .Y(n2561) ); INVX8TS U3050 ( .A(n5244), .Y(n5196) ); INVX8TS U3051 ( .A(n5244), .Y(n5195) ); NAND2X4TS U3052 ( .A(n3386), .B(DMP_SFG[22]), .Y(n4759) ); INVX3TS U3053 ( .A(n3762), .Y(n3773) ); NAND2X4TS U3054 ( .A(n3875), .B(DMP_SFG[44]), .Y(n3911) ); INVX8TS U3055 ( .A(n5244), .Y(busy) ); INVX8TS U3056 ( .A(n5200), .Y(n5201) ); INVX8TS U3057 ( .A(n2546), .Y(n2547) ); NAND2X4TS U3058 ( .A(n3399), .B(DMP_SFG[38]), .Y(n4994) ); INVX8TS U3059 ( .A(n5284), .Y(n5197) ); NAND2X4TS U3060 ( .A(n5833), .B(n5832), .Y(n2698) ); NAND2X4TS U3061 ( .A(n2130), .B(n5687), .Y(n2697) ); INVX2TS U3062 ( .A(n6013), .Y(n2092) ); NOR2X4TS U3063 ( .A(n6033), .B(n6032), .Y(n1928) ); NAND2X4TS U3064 ( .A(n6057), .B(n6058), .Y(n1929) ); AND2X4TS U3065 ( .A(n5780), .B(n5779), .Y(n1931) ); NAND3X1TS U3066 ( .A(n6169), .B(n6168), .C(n6167), .Y(final_result_ieee[15]) ); NAND2X1TS U3067 ( .A(n2211), .B(n5830), .Y(n5187) ); NAND2X8TS U3068 ( .A(n2384), .B(n3366), .Y(n3797) ); NAND2X1TS U3069 ( .A(n2211), .B(n2149), .Y(n5188) ); INVX8TS U3070 ( .A(Shift_reg_FLAGS_7_6), .Y(n4791) ); CLKAND2X2TS U3071 ( .A(n6053), .B(n2135), .Y(n4298) ); OR2X2TS U3072 ( .A(n5496), .B(DMP_EXP_EWSW[57]), .Y(n3407) ); INVX8TS U3073 ( .A(n5596), .Y(n2546) ); NAND2X4TS U3074 ( .A(n5964), .B(n5963), .Y(n2598) ); INVX2TS U3075 ( .A(n6077), .Y(n2223) ); INVX2TS U3076 ( .A(n6076), .Y(n2224) ); INVX2TS U3077 ( .A(intDX_EWSW[63]), .Y(n4229) ); INVX12TS U3078 ( .A(Shift_reg_FLAGS_7_5), .Y(n5200) ); INVX6TS U3079 ( .A(n5596), .Y(n5209) ); BUFX20TS U3080 ( .A(Shift_reg_FLAGS_7[0]), .Y(n6293) ); NOR2X4TS U3081 ( .A(Raw_mant_NRM_SWR[26]), .B(Raw_mant_NRM_SWR[6]), .Y(n2919) ); INVX6TS U3082 ( .A(n5596), .Y(n5210) ); BUFX8TS U3083 ( .A(n3336), .Y(n1987) ); INVX4TS U3084 ( .A(n2300), .Y(n2301) ); INVX2TS U3085 ( .A(n2252), .Y(n2253) ); NAND2X4TS U3086 ( .A(n3348), .B(intDY_EWSW[24]), .Y(n3484) ); INVX3TS U3087 ( .A(DmP_mant_SFG_SWR[15]), .Y(n2333) ); INVX8TS U3088 ( .A(Raw_mant_NRM_SWR[42]), .Y(n6216) ); BUFX8TS U3089 ( .A(n5493), .Y(n5244) ); NAND2X6TS U3090 ( .A(n2016), .B(n2946), .Y(n4025) ); NAND2X6TS U3091 ( .A(n4306), .B(n4305), .Y(n4321) ); NOR2X4TS U3092 ( .A(n2421), .B(n2970), .Y(n6332) ); INVX8TS U3093 ( .A(n3239), .Y(n6396) ); NAND2X4TS U3094 ( .A(n4881), .B(n2562), .Y(n4883) ); NAND2X4TS U3095 ( .A(n2713), .B(n3268), .Y(n3899) ); NAND2X4TS U3096 ( .A(n2756), .B(n2755), .Y(n2754) ); MX2X2TS U3097 ( .A(n5321), .B(n2307), .S0(n2513), .Y(n1130) ); NAND2X4TS U3098 ( .A(n3283), .B(n3168), .Y(n3167) ); NAND2X4TS U3099 ( .A(n2336), .B(n3910), .Y(n2713) ); NAND2X4TS U3100 ( .A(n4888), .B(n4903), .Y(n2073) ); BUFX20TS U3101 ( .A(n2470), .Y(n1916) ); MX2X2TS U3102 ( .A(n4762), .B(n2300), .S0(n5005), .Y(n1174) ); MX2X2TS U3103 ( .A(n5081), .B(Raw_mant_NRM_SWR[21]), .S0(n4997), .Y(n1177) ); NAND2X4TS U3104 ( .A(n3158), .B(n3157), .Y(n3156) ); NAND2X6TS U3105 ( .A(n3281), .B(n3893), .Y(n2733) ); NAND2X4TS U3106 ( .A(n4495), .B(n4494), .Y(n1137) ); NAND3X6TS U3107 ( .A(n1940), .B(n1939), .C(n1938), .Y(n1937) ); MX2X2TS U3108 ( .A(n4736), .B(n2252), .S0(n2550), .Y(n1178) ); NOR2X6TS U3109 ( .A(n3042), .B(n2047), .Y(n5261) ); NAND2X4TS U3110 ( .A(n2703), .B(n2575), .Y(n2574) ); NAND2X6TS U3111 ( .A(n3273), .B(n3905), .Y(n4243) ); NAND3X6TS U3112 ( .A(n4688), .B(n4687), .C(n2638), .Y(n6459) ); OAI2BB1X2TS U3113 ( .A0N(n5161), .A1N(n6461), .B0(n5134), .Y(n1113) ); NAND4X4TS U3114 ( .A(n3163), .B(n3162), .C(n3161), .D(n3159), .Y(n3158) ); NOR2X4TS U3115 ( .A(n2879), .B(n2878), .Y(n2877) ); AND2X4TS U3116 ( .A(n4634), .B(n2472), .Y(n2471) ); MX2X4TS U3117 ( .A(n6463), .B(n5560), .S0(n5159), .Y(n5137) ); MX2X4TS U3118 ( .A(n6418), .B(n4130), .S0(n5264), .Y(n4131) ); MX2X2TS U3119 ( .A(n5093), .B(Raw_mant_NRM_SWR[17]), .S0(n5005), .Y(n1181) ); MX2X2TS U3120 ( .A(n6458), .B(n5562), .S0(n5265), .Y(n5144) ); NAND2X4TS U3121 ( .A(n2884), .B(n1877), .Y(n1938) ); NAND2X6TS U3122 ( .A(n2786), .B(n4020), .Y(n3913) ); INVX8TS U3123 ( .A(n1970), .Y(n3907) ); NAND4X4TS U3124 ( .A(n4727), .B(n4726), .C(n4725), .D(n4724), .Y(n6461) ); INVX8TS U3125 ( .A(n2647), .Y(n2464) ); NAND2X6TS U3126 ( .A(n3887), .B(n3269), .Y(n2786) ); NAND2X6TS U3127 ( .A(n4597), .B(n2083), .Y(n4649) ); INVX3TS U3128 ( .A(n2419), .Y(n2882) ); CLKMX2X2TS U3129 ( .A(n6431), .B(n5565), .S0(n5232), .Y(n5156) ); XOR2X2TS U3130 ( .A(n5096), .B(n5092), .Y(n5093) ); CLKBUFX3TS U3131 ( .A(n4461), .Y(n5643) ); MX2X4TS U3132 ( .A(n6438), .B(n5568), .S0(n5159), .Y(n5146) ); NAND2X4TS U3133 ( .A(n2632), .B(n5030), .Y(n2631) ); NAND2X2TS U3134 ( .A(n4628), .B(n4627), .Y(n4629) ); AND2X4TS U3135 ( .A(n3893), .B(n4998), .Y(n2401) ); NAND2X4TS U3136 ( .A(n4607), .B(n4609), .Y(n2047) ); BUFX12TS U3137 ( .A(n5135), .Y(n2022) ); AND3X6TS U3138 ( .A(n4693), .B(n4695), .C(n2437), .Y(n2829) ); XNOR2X1TS U3139 ( .A(n5318), .B(n5317), .Y(n5320) ); NAND2X4TS U3140 ( .A(n4998), .B(n4136), .Y(n4137) ); OA21X4TS U3141 ( .A0(n4962), .A1(n4783), .B0(n4782), .Y(n5325) ); NAND2X4TS U3142 ( .A(n4472), .B(n3372), .Y(n4476) ); MXI2X2TS U3143 ( .A(n5455), .B(n5352), .S0(n2505), .Y(n1501) ); MXI2X2TS U3144 ( .A(n5457), .B(n5354), .S0(n2505), .Y(n1492) ); MXI2X2TS U3145 ( .A(n5458), .B(n5355), .S0(n2505), .Y(n1489) ); MXI2X2TS U3146 ( .A(n5453), .B(n5351), .S0(n2505), .Y(n1513) ); MXI2X2TS U3147 ( .A(n5451), .B(n5349), .S0(n2505), .Y(n1486) ); INVX4TS U3148 ( .A(n3194), .Y(n2979) ); NAND3X6TS U3149 ( .A(n1971), .B(n1972), .C(n4020), .Y(n1968) ); INVX8TS U3150 ( .A(n4709), .Y(n1944) ); OA22X2TS U3151 ( .A0(n3832), .A1(n4654), .B0(n4716), .B1(n4653), .Y(n4655) ); NAND2X6TS U3152 ( .A(n2425), .B(n4519), .Y(n5135) ); INVX6TS U3153 ( .A(n4722), .Y(n2552) ); NAND2X1TS U3154 ( .A(n2341), .B(n5316), .Y(n5318) ); MXI2X2TS U3155 ( .A(n5362), .B(n5512), .S0(n2505), .Y(n1510) ); MXI2X2TS U3156 ( .A(n5361), .B(n5511), .S0(n2505), .Y(n1519) ); CLKMX2X2TS U3157 ( .A(Data_Y[30]), .B(intDY_EWSW[30]), .S0(n5236), .Y(n1698) ); CLKMX2X2TS U3158 ( .A(Data_Y[23]), .B(n1984), .S0(n5258), .Y(n1705) ); CLKMX2X2TS U3159 ( .A(Data_Y[58]), .B(intDY_EWSW[58]), .S0(n5252), .Y(n1670) ); CLKMX2X2TS U3160 ( .A(Data_Y[54]), .B(intDY_EWSW[54]), .S0(n5253), .Y(n1674) ); CLKMX2X2TS U3161 ( .A(Data_Y[40]), .B(intDY_EWSW[40]), .S0(n5235), .Y(n1688) ); INVX12TS U3162 ( .A(n3157), .Y(n2505) ); CLKMX2X2TS U3163 ( .A(Data_Y[39]), .B(intDY_EWSW[39]), .S0(n5235), .Y(n1689) ); CLKMX2X2TS U3164 ( .A(Data_X[27]), .B(intDX_EWSW[27]), .S0(n5237), .Y(n1767) ); CLKMX2X2TS U3165 ( .A(Data_X[26]), .B(intDX_EWSW[26]), .S0(n5237), .Y(n1768) ); CLKMX2X2TS U3166 ( .A(Data_X[5]), .B(intDX_EWSW[5]), .S0(n5241), .Y(n1789) ); CLKMX2X2TS U3167 ( .A(Data_Y[47]), .B(n2045), .S0(n5253), .Y(n1681) ); MX2X2TS U3168 ( .A(Data_X[32]), .B(intDX_EWSW[32]), .S0(n5237), .Y(n1762) ); CLKMX2X2TS U3169 ( .A(Data_Y[27]), .B(n2964), .S0(n5236), .Y(n1701) ); CLKMX2X2TS U3170 ( .A(Data_X[31]), .B(intDX_EWSW[31]), .S0(n5237), .Y(n1763) ); CLKMX2X2TS U3171 ( .A(Data_X[30]), .B(intDX_EWSW[30]), .S0(n5237), .Y(n1764) ); CLKMX2X2TS U3172 ( .A(Data_X[28]), .B(intDX_EWSW[28]), .S0(n5237), .Y(n1766) ); CLKMX2X2TS U3173 ( .A(Data_X[29]), .B(intDX_EWSW[29]), .S0(n5237), .Y(n1765) ); CLKMX2X2TS U3174 ( .A(Data_Y[52]), .B(intDY_EWSW[52]), .S0(n5253), .Y(n1676) ); CLKMX2X2TS U3175 ( .A(Data_Y[59]), .B(intDY_EWSW[59]), .S0(n5252), .Y(n1669) ); CLKMX2X2TS U3176 ( .A(Data_X[50]), .B(intDX_EWSW[50]), .S0(n5238), .Y(n1744) ); CLKMX2X2TS U3177 ( .A(Data_X[49]), .B(intDX_EWSW[49]), .S0(n5238), .Y(n1745) ); CLKMX2X2TS U3178 ( .A(Data_X[48]), .B(intDX_EWSW[48]), .S0(n5238), .Y(n1746) ); CLKMX2X2TS U3179 ( .A(Data_Y[20]), .B(intDY_EWSW[20]), .S0(n5258), .Y(n1708) ); CLKMX2X2TS U3180 ( .A(Data_X[51]), .B(intDX_EWSW[51]), .S0(n5238), .Y(n1743) ); CLKMX2X2TS U3181 ( .A(Data_X[47]), .B(intDX_EWSW[47]), .S0(n5238), .Y(n1747) ); AND2X4TS U3182 ( .A(n4084), .B(n4083), .Y(n1946) ); CLKMX2X2TS U3183 ( .A(Data_Y[22]), .B(n2036), .S0(n5258), .Y(n1706) ); CLKMX2X2TS U3184 ( .A(Data_Y[60]), .B(intDY_EWSW[60]), .S0(n5252), .Y(n1668) ); CLKMX2X2TS U3185 ( .A(Data_X[52]), .B(intDX_EWSW[52]), .S0(n5238), .Y(n1742) ); CLKMX2X2TS U3186 ( .A(Data_X[45]), .B(intDX_EWSW[45]), .S0(n5238), .Y(n1749) ); CLKMX2X2TS U3187 ( .A(Data_X[44]), .B(intDX_EWSW[44]), .S0(n5238), .Y(n1750) ); CLKMX2X2TS U3188 ( .A(Data_Y[18]), .B(n2025), .S0(n5258), .Y(n1710) ); CLKMX2X2TS U3189 ( .A(Data_X[53]), .B(intDX_EWSW[53]), .S0(n5238), .Y(n1741) ); CLKMX2X2TS U3190 ( .A(Data_Y[43]), .B(n2051), .S0(n5235), .Y(n1685) ); CLKMX2X2TS U3191 ( .A(Data_Y[28]), .B(n2745), .S0(n5236), .Y(n1700) ); CLKMX2X2TS U3192 ( .A(Data_Y[44]), .B(intDY_EWSW[44]), .S0(n5235), .Y(n1684) ); MXI2X2TS U3193 ( .A(n5456), .B(n5353), .S0(n5227), .Y(n1504) ); CLKMX2X2TS U3194 ( .A(Data_Y[24]), .B(intDY_EWSW[24]), .S0(n5258), .Y(n1704) ); CLKMX2X2TS U3195 ( .A(Data_Y[41]), .B(n2026), .S0(n5235), .Y(n1687) ); CLKMX2X2TS U3196 ( .A(Data_X[7]), .B(intDX_EWSW[7]), .S0(n5241), .Y(n1787) ); CLKMX2X2TS U3197 ( .A(Data_Y[26]), .B(n2046), .S0(n5236), .Y(n1702) ); NAND2X4TS U3198 ( .A(n3469), .B(n3504), .Y(n3014) ); CLKMX2X2TS U3199 ( .A(Data_Y[29]), .B(intDY_EWSW[29]), .S0(n5236), .Y(n1699) ); NAND2X4TS U3200 ( .A(n4656), .B(n4658), .Y(n2086) ); CLKMX2X2TS U3201 ( .A(Data_Y[46]), .B(n1922), .S0(n5253), .Y(n1682) ); CLKMX2X2TS U3202 ( .A(Data_X[12]), .B(intDX_EWSW[12]), .S0(n5241), .Y(n1782) ); CLKMX2X2TS U3203 ( .A(Data_Y[33]), .B(n2945), .S0(n5236), .Y(n1695) ); CLKMX2X2TS U3204 ( .A(Data_Y[35]), .B(n2940), .S0(n5236), .Y(n1693) ); CLKMX2X2TS U3205 ( .A(Data_X[4]), .B(intDX_EWSW[4]), .S0(n5241), .Y(n1790) ); NAND2BX2TS U3206 ( .AN(n2898), .B(n2851), .Y(n2897) ); CLKMX2X2TS U3207 ( .A(Data_Y[34]), .B(n2740), .S0(n5236), .Y(n1694) ); CLKMX2X2TS U3208 ( .A(Data_X[0]), .B(intDX_EWSW[0]), .S0(n5252), .Y(n1794) ); CLKMX2X2TS U3209 ( .A(Data_X[10]), .B(intDX_EWSW[10]), .S0(n5241), .Y(n1784) ); CLKMX2X2TS U3210 ( .A(Data_X[3]), .B(intDX_EWSW[3]), .S0(n5252), .Y(n1791) ); CLKMX2X2TS U3211 ( .A(Data_X[8]), .B(intDX_EWSW[8]), .S0(n5241), .Y(n1786) ); CLKMX2X2TS U3212 ( .A(Data_X[1]), .B(intDX_EWSW[1]), .S0(n5252), .Y(n1793) ); NAND2X6TS U3213 ( .A(n4060), .B(n4059), .Y(n5150) ); CLKMX2X2TS U3214 ( .A(Data_X[2]), .B(intDX_EWSW[2]), .S0(n5252), .Y(n1792) ); CLKMX2X2TS U3215 ( .A(Data_X[20]), .B(intDX_EWSW[20]), .S0(n5240), .Y(n1774) ); CLKMX2X2TS U3216 ( .A(Data_Y[36]), .B(intDY_EWSW[36]), .S0(n5235), .Y(n1692) ); CLKMX2X2TS U3217 ( .A(Data_X[19]), .B(intDX_EWSW[19]), .S0(n5240), .Y(n1775) ); CLKMX2X2TS U3218 ( .A(Data_Y[56]), .B(intDY_EWSW[56]), .S0(n5252), .Y(n1672) ); CLKMX2X2TS U3219 ( .A(Data_X[6]), .B(intDX_EWSW[6]), .S0(n5241), .Y(n1788) ); CLKMX2X2TS U3220 ( .A(Data_X[21]), .B(intDX_EWSW[21]), .S0(n5240), .Y(n1773) ); CLKMX2X2TS U3221 ( .A(Data_Y[50]), .B(intDY_EWSW[50]), .S0(n5253), .Y(n1678) ); CLKMX2X2TS U3222 ( .A(Data_X[22]), .B(intDX_EWSW[22]), .S0(n5240), .Y(n1772) ); CLKMX2X2TS U3223 ( .A(Data_X[18]), .B(intDX_EWSW[18]), .S0(n5240), .Y(n1776) ); CLKMX2X2TS U3224 ( .A(Data_X[17]), .B(intDX_EWSW[17]), .S0(n5240), .Y(n1777) ); CLKMX2X2TS U3225 ( .A(Data_Y[31]), .B(n2961), .S0(n5236), .Y(n1697) ); CLKMX2X2TS U3226 ( .A(Data_Y[37]), .B(intDY_EWSW[37]), .S0(n5235), .Y(n1691) ); CLKMX2X2TS U3227 ( .A(Data_X[23]), .B(intDX_EWSW[23]), .S0(n5240), .Y(n1771) ); CLKMX2X2TS U3228 ( .A(Data_X[16]), .B(intDX_EWSW[16]), .S0(n5240), .Y(n1778) ); CLKMX2X2TS U3229 ( .A(Data_Y[51]), .B(n2017), .S0(n5253), .Y(n1677) ); CLKMX2X2TS U3230 ( .A(Data_X[25]), .B(intDX_EWSW[25]), .S0(n5237), .Y(n1769) ); OAI2BB1X1TS U3231 ( .A0N(OP_FLAG_EXP), .A1N(n2535), .B0(n5162), .Y(n1524) ); CLKMX2X2TS U3232 ( .A(Data_X[9]), .B(intDX_EWSW[9]), .S0(n5241), .Y(n1785) ); CLKMX2X2TS U3233 ( .A(Data_Y[55]), .B(intDY_EWSW[55]), .S0(n5253), .Y(n1673) ); CLKMX2X2TS U3234 ( .A(Data_X[24]), .B(intDX_EWSW[24]), .S0(n5237), .Y(n1770) ); CLKMX2X2TS U3235 ( .A(Data_X[15]), .B(intDX_EWSW[15]), .S0(n5240), .Y(n1779) ); CLKMX2X2TS U3236 ( .A(Data_X[13]), .B(intDX_EWSW[13]), .S0(n5241), .Y(n1781) ); AND2X2TS U3237 ( .A(n5224), .B(DmP_mant_SFG_SWR[33]), .Y(n2380) ); CLKMX2X2TS U3238 ( .A(Data_X[40]), .B(intDX_EWSW[40]), .S0(n5239), .Y(n1754) ); CLKMX2X2TS U3239 ( .A(Data_X[38]), .B(intDX_EWSW[38]), .S0(n5239), .Y(n1756) ); CLKMX2X2TS U3240 ( .A(Data_X[37]), .B(intDX_EWSW[37]), .S0(n5239), .Y(n1757) ); CLKMX2X2TS U3241 ( .A(Data_X[41]), .B(intDX_EWSW[41]), .S0(n5239), .Y(n1753) ); CLKMX2X2TS U3242 ( .A(Data_X[36]), .B(intDX_EWSW[36]), .S0(n5239), .Y(n1758) ); CLKMX2X2TS U3243 ( .A(Data_X[42]), .B(intDX_EWSW[42]), .S0(n5239), .Y(n1752) ); CLKMX2X3TS U3244 ( .A(Data_Y[0]), .B(intDY_EWSW[0]), .S0(n5242), .Y(n1728) ); CLKMX2X3TS U3245 ( .A(Data_Y[63]), .B(intDY_EWSW[63]), .S0(n5242), .Y(n1665) ); INVX2TS U3246 ( .A(n4767), .Y(n4770) ); INVX8TS U3247 ( .A(n2924), .Y(n4756) ); NAND2X2TS U3248 ( .A(n4226), .B(n4227), .Y(n1924) ); NAND2X6TS U3249 ( .A(n2596), .B(n3847), .Y(n5026) ); INVX2TS U3250 ( .A(n4988), .Y(n4969) ); CLKMX2X2TS U3251 ( .A(Data_X[34]), .B(intDX_EWSW[34]), .S0(n5239), .Y(n1760) ); CLKMX2X2TS U3252 ( .A(Data_X[35]), .B(intDX_EWSW[35]), .S0(n5239), .Y(n1759) ); NAND2X2TS U3253 ( .A(DmP_mant_SFG_SWR[43]), .B(n5191), .Y(n2827) ); CLKMX2X3TS U3254 ( .A(Data_Y[4]), .B(intDY_EWSW[4]), .S0(n5242), .Y(n1724) ); CLKMX2X2TS U3255 ( .A(Data_X[57]), .B(intDX_EWSW[57]), .S0(n5217), .Y(n1737) ); CLKMX2X2TS U3256 ( .A(Data_X[58]), .B(intDX_EWSW[58]), .S0(n5217), .Y(n1736) ); CLKMX2X2TS U3257 ( .A(Data_X[59]), .B(intDX_EWSW[59]), .S0(n5217), .Y(n1735) ); INVX12TS U3258 ( .A(n2393), .Y(n2517) ); INVX12TS U3259 ( .A(n2395), .Y(n2519) ); INVX1TS U3260 ( .A(n4260), .Y(n4261) ); CLKMX2X2TS U3261 ( .A(Data_X[60]), .B(intDX_EWSW[60]), .S0(n5217), .Y(n1734) ); CLKMX2X2TS U3262 ( .A(Data_Y[12]), .B(n1923), .S0(n4531), .Y(n1716) ); CLKMX2X3TS U3263 ( .A(Data_Y[3]), .B(n2737), .S0(n5242), .Y(n1725) ); INVX2TS U3264 ( .A(n5324), .Y(n2290) ); CLKMX2X2TS U3265 ( .A(Data_X[61]), .B(intDX_EWSW[61]), .S0(n5217), .Y(n1733) ); CLKMX2X2TS U3266 ( .A(Data_Y[7]), .B(intDY_EWSW[7]), .S0(n4531), .Y(n1721) ); CLKMX2X2TS U3267 ( .A(Data_X[56]), .B(intDX_EWSW[56]), .S0(n5217), .Y(n1738) ); CLKMX2X2TS U3268 ( .A(Data_X[54]), .B(intDX_EWSW[54]), .S0(n5217), .Y(n1740) ); CLKMX2X2TS U3269 ( .A(Data_Y[15]), .B(n2035), .S0(n4531), .Y(n1713) ); CLKMX2X2TS U3270 ( .A(Data_Y[6]), .B(intDY_EWSW[6]), .S0(n4531), .Y(n1722) ); NAND2X2TS U3271 ( .A(n5091), .B(n2757), .Y(n5068) ); CLKMX2X2TS U3272 ( .A(Data_Y[13]), .B(intDY_EWSW[13]), .S0(n4531), .Y(n1715) ); CLKMX2X2TS U3273 ( .A(Data_X[55]), .B(intDX_EWSW[55]), .S0(n5217), .Y(n1739) ); CLKMX2X2TS U3274 ( .A(Data_Y[11]), .B(intDY_EWSW[11]), .S0(n4531), .Y(n1717) ); NOR2X4TS U3275 ( .A(n2551), .B(n3880), .Y(n3227) ); CLKMX2X2TS U3276 ( .A(DmP_mant_SHT1_SW[47]), .B(n1216), .S0(n5206), .Y(n1215) ); NAND2X2TS U3277 ( .A(n4742), .B(n3295), .Y(n4743) ); NAND2X2TS U3278 ( .A(n3917), .B(n3916), .Y(n3918) ); XNOR2X1TS U3279 ( .A(n5281), .B(n5280), .Y(n5282) ); OR2X6TS U3280 ( .A(n3861), .B(n1943), .Y(n5028) ); CLKMX2X2TS U3281 ( .A(ZERO_FLAG_NRM), .B(ZERO_FLAG_SFG), .S0(n5208), .Y( n1195) ); BUFX8TS U3282 ( .A(n5259), .Y(n5232) ); BUFX12TS U3283 ( .A(n5234), .Y(n5217) ); NAND2X6TS U3284 ( .A(n2722), .B(DMP_SFG[27]), .Y(n4775) ); CLKMX2X2TS U3285 ( .A(DmP_mant_SHT1_SW[36]), .B(DmP_EXP_EWSW[36]), .S0(n5204), .Y(n1237) ); CLKMX2X2TS U3286 ( .A(DmP_mant_SHT1_SW[46]), .B(DmP_EXP_EWSW[46]), .S0(n5213), .Y(n1217) ); INVX2TS U3287 ( .A(n2760), .Y(n4985) ); MXI2X1TS U3288 ( .A(n2513), .B(n5243), .S0(n5314), .Y(n1795) ); NAND2X6TS U3289 ( .A(n3904), .B(n5000), .Y(n3906) ); CLKINVX2TS U3290 ( .A(n5019), .Y(n4334) ); NAND2X6TS U3291 ( .A(n4711), .B(n2449), .Y(n2395) ); CLKMX2X2TS U3292 ( .A(DmP_mant_SHT1_SW[31]), .B(DmP_EXP_EWSW[31]), .S0(n5204), .Y(n1247) ); NAND2X6TS U3293 ( .A(n3882), .B(n3368), .Y(n1973) ); MXI2X1TS U3294 ( .A(n4580), .B(n2525), .S0(n5314), .Y(n1801) ); MX2X1TS U3295 ( .A(n2040), .B(DMP_exp_NRM_EW[0]), .S0(n2561), .Y(n1361) ); INVX12TS U3296 ( .A(n2266), .Y(n5033) ); INVX12TS U3297 ( .A(n2551), .Y(n3179) ); NAND4BX2TS U3298 ( .AN(n2093), .B(n2097), .C(n2091), .D(n2090), .Y(n2096) ); INVX12TS U3299 ( .A(n2551), .Y(n3232) ); INVX2TS U3300 ( .A(n4978), .Y(n4979) ); NAND2X2TS U3301 ( .A(n2550), .B(n2019), .Y(n3267) ); INVX2TS U3302 ( .A(n4926), .Y(n4928) ); INVX2TS U3303 ( .A(n4921), .Y(n4922) ); INVX6TS U3304 ( .A(n4993), .Y(n4995) ); INVX2TS U3305 ( .A(n5002), .Y(n5004) ); INVX2TS U3306 ( .A(n4955), .Y(n4937) ); AND2X2TS U3307 ( .A(n4853), .B(DmP_EXP_EWSW[22]), .Y(n2282) ); NAND2X1TS U3308 ( .A(n2525), .B(DMP_EXP_EWSW[20]), .Y(n3674) ); NAND2X1TS U3309 ( .A(n4396), .B(n1537), .Y(n4386) ); NOR3X6TS U3310 ( .A(n3251), .B(n3253), .C(n2747), .Y(n3250) ); INVX2TS U3311 ( .A(n3915), .Y(n3917) ); BUFX4TS U3312 ( .A(n5128), .Y(n4555) ); INVX6TS U3313 ( .A(n4948), .Y(n3016) ); BUFX4TS U3314 ( .A(n4551), .Y(n4554) ); INVX2TS U3315 ( .A(n4975), .Y(n3133) ); NAND2X4TS U3316 ( .A(n2594), .B(n6192), .Y(n2593) ); NAND2X1TS U3317 ( .A(n5212), .B(n4470), .Y(n1803) ); INVX2TS U3318 ( .A(n2297), .Y(n2263) ); NOR2X6TS U3319 ( .A(n3969), .B(n2795), .Y(n2794) ); NAND2X6TS U3320 ( .A(n3296), .B(n2389), .Y(n3873) ); AND2X2TS U3321 ( .A(n4396), .B(DMP_EXP_EWSW[47]), .Y(n4392) ); NOR2X4TS U3322 ( .A(n4579), .B(n4578), .Y(n5314) ); INVX16TS U3323 ( .A(n2260), .Y(n1919) ); CLKAND2X2TS U3324 ( .A(n4346), .B(Raw_mant_NRM_SWR[14]), .Y(n2392) ); INVX4TS U3325 ( .A(n3805), .Y(n1950) ); NOR3X6TS U3326 ( .A(n2463), .B(n2462), .C(n2461), .Y(n2460) ); NAND3X4TS U3327 ( .A(n3713), .B(n2824), .C(n2839), .Y(n2823) ); INVX12TS U3328 ( .A(n2549), .Y(n2551) ); AND2X2TS U3329 ( .A(n2534), .B(DmP_EXP_EWSW[17]), .Y(n4852) ); CLKMX2X2TS U3330 ( .A(DmP_mant_SHT1_SW[24]), .B(DmP_EXP_EWSW[24]), .S0(n5210), .Y(n1261) ); NOR3X6TS U3331 ( .A(n2784), .B(n2783), .C(n2782), .Y(n2781) ); CLKMX2X2TS U3332 ( .A(DmP_mant_SHT1_SW[21]), .B(DmP_EXP_EWSW[21]), .S0(n5210), .Y(n1267) ); CLKMX2X2TS U3333 ( .A(DmP_mant_SHT1_SW[18]), .B(n2256), .S0(n5209), .Y(n1273) ); CLKMX2X2TS U3334 ( .A(DmP_mant_SHT1_SW[27]), .B(DmP_EXP_EWSW[27]), .S0(n2546), .Y(n1255) ); BUFX12TS U3335 ( .A(n4917), .Y(n5319) ); BUFX8TS U3336 ( .A(n4791), .Y(n4864) ); BUFX8TS U3337 ( .A(n4791), .Y(n4417) ); INVX6TS U3338 ( .A(n5085), .Y(n1920) ); INVX2TS U3339 ( .A(n3789), .Y(n3791) ); NAND2X6TS U3340 ( .A(n3183), .B(DMP_SFG[15]), .Y(n5094) ); NAND2X6TS U3341 ( .A(n3874), .B(DMP_SFG[43]), .Y(n4020) ); NAND2X6TS U3342 ( .A(n3402), .B(DMP_SFG[40]), .Y(n2373) ); NOR2X2TS U3343 ( .A(n3739), .B(Raw_mant_NRM_SWR[29]), .Y(n2491) ); INVX12TS U3344 ( .A(n5315), .Y(n2524) ); NAND2X1TS U3345 ( .A(n2534), .B(DmP_EXP_EWSW[13]), .Y(n3813) ); BUFX8TS U3346 ( .A(n4791), .Y(n4396) ); INVX12TS U3347 ( .A(n5101), .Y(n2563) ); BUFX8TS U3348 ( .A(n4791), .Y(n3652) ); INVX3TS U3349 ( .A(n3400), .Y(n3184) ); BUFX12TS U3350 ( .A(n4917), .Y(n4997) ); NOR3X6TS U3351 ( .A(Raw_mant_NRM_SWR[14]), .B(Raw_mant_NRM_SWR[13]), .C( Raw_mant_NRM_SWR[15]), .Y(n2623) ); INVX2TS U3352 ( .A(n2323), .Y(n2324) ); BUFX3TS U3353 ( .A(Shift_amount_SHT1_EWR[3]), .Y(n2565) ); INVX8TS U3354 ( .A(n5446), .Y(n2549) ); INVX2TS U3355 ( .A(n5335), .Y(n5214) ); INVX6TS U3356 ( .A(Shift_reg_FLAGS_7_6), .Y(n2534) ); NOR2X6TS U3357 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n5444), .Y(n4471) ); MX2X1TS U3358 ( .A(DMP_SHT2_EWSW[14]), .B(DMP_SHT1_EWSW[14]), .S0(n2383), .Y(n1478) ); INVX6TS U3359 ( .A(Raw_mant_NRM_SWR[35]), .Y(n2061) ); NAND2X2TS U3360 ( .A(n5839), .B(n5838), .Y(n3075) ); INVX12TS U3361 ( .A(Shift_reg_FLAGS_7[1]), .Y(n5101) ); NAND2X1TS U3362 ( .A(n2246), .B(n2245), .Y(n6445) ); BUFX4TS U3363 ( .A(intDX_EWSW[39]), .Y(n2028) ); CLKINVX6TS U3364 ( .A(Raw_mant_NRM_SWR[47]), .Y(n2059) ); INVX4TS U3365 ( .A(left_right_SHT2), .Y(n2993) ); NOR2X4TS U3366 ( .A(n5975), .B(n5974), .Y(n2210) ); INVX2TS U3367 ( .A(n5559), .Y(n2923) ); INVX2TS U3368 ( .A(n2449), .Y(n2018) ); XNOR2X2TS U3369 ( .A(n2257), .B(n5547), .Y(n3909) ); MX2X1TS U3370 ( .A(DMP_SHT2_EWSW[62]), .B(DMP_SHT1_EWSW[62]), .S0(n2383), .Y(n1314) ); INVX2TS U3371 ( .A(DmP_mant_SHT1_SW[34]), .Y(n5612) ); OAI22X2TS U3372 ( .A0(n2182), .A1(n2191), .B0(n6041), .B1(n6040), .Y(n3712) ); XOR2X2TS U3373 ( .A(n6160), .B(DmP_mant_SFG_SWR[39]), .Y(n3398) ); CLKINVX6TS U3374 ( .A(n2488), .Y(n2489) ); BUFX3TS U3375 ( .A(DmP_mant_SHT1_SW[5]), .Y(n2572) ); INVX2TS U3376 ( .A(DMP_SHT2_EWSW[62]), .Y(n5226) ); INVX2TS U3377 ( .A(DmP_mant_SHT1_SW[15]), .Y(n5607) ); NOR2X4TS U3378 ( .A(n5939), .B(n5938), .Y(n2215) ); BUFX6TS U3379 ( .A(intDY_EWSW[46]), .Y(n1922) ); NAND2X8TS U3380 ( .A(n3220), .B(n2634), .Y(n5084) ); NAND4X2TS U3381 ( .A(n4217), .B(n4216), .C(n4215), .D(n4214), .Y(n4222) ); BUFX6TS U3382 ( .A(intDY_EWSW[12]), .Y(n1923) ); NAND3X4TS U3383 ( .A(n4733), .B(n3124), .C(n4729), .Y(n4233) ); NAND3BX4TS U3384 ( .AN(n1924), .B(n4225), .C(n4228), .Y(n4733) ); MXI2X4TS U3385 ( .A(n5256), .B(n2758), .S0(n5265), .Y(n1042) ); BUFX16TS U3386 ( .A(n3111), .Y(n1925) ); NOR2X8TS U3387 ( .A(shift_value_SHT2_EWR[4]), .B(n2330), .Y(n3111) ); NOR2X8TS U3388 ( .A(n1932), .B(n1931), .Y(n1930) ); OAI2BB1X4TS U3389 ( .A0N(n2198), .A1N(n5778), .B0(n4038), .Y(n1932) ); NOR2BX4TS U3390 ( .AN(n1934), .B(n6031), .Y(n1933) ); INVX2TS U3391 ( .A(n6030), .Y(n1934) ); NAND2X4TS U3392 ( .A(n2885), .B(n1877), .Y(n1940) ); OAI21X4TS U3393 ( .A0(n3320), .A1(n1868), .B0(n2020), .Y(n1026) ); NOR2X8TS U3394 ( .A(n2576), .B(n1941), .Y(n2575) ); OAI21X4TS U3395 ( .A0(n4689), .A1(n1918), .B0(n1942), .Y(n1941) ); AOI22X4TS U3396 ( .A0(n4603), .A1(n1878), .B0(n5145), .B1(n5153), .Y(n5290) ); NAND4X8TS U3397 ( .A(n1948), .B(n1947), .C(n2960), .D(n1945), .Y(n4603) ); NAND2X8TS U3398 ( .A(n5182), .B(n2330), .Y(n1945) ); NAND2X8TS U3399 ( .A(n4085), .B(n1946), .Y(n5182) ); AOI2BB1X4TS U3400 ( .A0N(n4489), .A1N(n1874), .B0(n2633), .Y(n1947) ); AOI2BB1X4TS U3401 ( .A0N(n4088), .A1N(n4702), .B0(n2629), .Y(n1948) ); BUFX6TS U3402 ( .A(n3111), .Y(n1949) ); INVX16TS U3403 ( .A(n1952), .Y(n3833) ); OR2X8TS U3404 ( .A(n5344), .B(shift_value_SHT2_EWR[2]), .Y(n3805) ); NOR2X8TS U3405 ( .A(n3805), .B(n1953), .Y(n1952) ); NOR2X4TS U3406 ( .A(n3514), .B(n1954), .Y(n3515) ); OAI22X4TS U3407 ( .A0(n2808), .A1(n1954), .B0(intDX_EWSW[57]), .B1(n2371), .Y(n2807) ); NOR2X8TS U3408 ( .A(n3338), .B(intDY_EWSW[57]), .Y(n1954) ); NOR2X6TS U3409 ( .A(n2860), .B(n1955), .Y(n2859) ); OAI21X4TS U3410 ( .A0(n1955), .A1(n3531), .B0(n3530), .Y(n3537) ); NOR2X8TS U3411 ( .A(n3362), .B(intDY_EWSW[41]), .Y(n1955) ); NOR2X8TS U3412 ( .A(n3512), .B(n1956), .Y(n2684) ); OAI21X4TS U3413 ( .A0(n1956), .A1(n3558), .B0(n3557), .Y(n2681) ); NOR2X8TS U3414 ( .A(n3335), .B(intDY_EWSW[55]), .Y(n1956) ); XOR2X4TS U3415 ( .A(DmP_mant_SFG_SWR[31]), .B(n1854), .Y(n3391) ); INVX12TS U3416 ( .A(n1957), .Y(n3110) ); AOI22X4TS U3417 ( .A0(n5047), .A1(n2558), .B0(n1869), .B1(n5054), .Y(n2704) ); OAI21X4TS U3418 ( .A0(n3833), .A1(n4678), .B0(n1962), .Y(n1961) ); AOI2BB2X4TS U3419 ( .B0(n2691), .B1(n4691), .A0N(n3832), .A1N(n4675), .Y( n1962) ); NAND2X8TS U3420 ( .A(n3868), .B(n3869), .Y(n2691) ); NAND2X8TS U3421 ( .A(n3082), .B(n4119), .Y(n5157) ); NOR2X8TS U3422 ( .A(n3902), .B(n5002), .Y(n3904) ); NOR2X6TS U3423 ( .A(n3894), .B(DMP_SFG[50]), .Y(n3902) ); OR2X8TS U3424 ( .A(n3873), .B(n2373), .Y(n1971) ); NOR2X8TS U3425 ( .A(n3871), .B(n1895), .Y(n1972) ); XOR2X4TS U3426 ( .A(DmP_mant_SFG_SWR[46]), .B(n2487), .Y(n3875) ); NAND2X6TS U3427 ( .A(n1975), .B(n1974), .Y(n2913) ); NOR2X4TS U3428 ( .A(n2858), .B(n3548), .Y(n1974) ); NAND2X8TS U3429 ( .A(n2859), .B(n3536), .Y(n2858) ); OAI21X4TS U3430 ( .A0(n1981), .A1(n3529), .B0(n1976), .Y(n1975) ); AOI21X4TS U3431 ( .A0(n1978), .A1(n1980), .B0(n1977), .Y(n1976) ); OAI21X4TS U3432 ( .A0(n3528), .A1(n3527), .B0(n3526), .Y(n1977) ); OAI21X4TS U3433 ( .A0(n2679), .A1(n3525), .B0(n3524), .Y(n1978) ); NAND3X8TS U3434 ( .A(n1900), .B(n1980), .C(n1979), .Y(n3529) ); INVX3TS U3435 ( .A(n2679), .Y(n1979) ); NOR2X8TS U3436 ( .A(n3506), .B(n3528), .Y(n1980) ); AOI21X4TS U3437 ( .A0(n3523), .A1(n1983), .B0(n1982), .Y(n1981) ); OAI21X4TS U3438 ( .A0(n2007), .A1(n3522), .B0(n3521), .Y(n1982) ); OAI21X4TS U3439 ( .A0(n3520), .A1(n2008), .B0(n3519), .Y(n1983) ); BUFX6TS U3440 ( .A(intDY_EWSW[23]), .Y(n1984) ); OR2X8TS U3441 ( .A(n3233), .B(n3189), .Y(n2423) ); AOI22X4TS U3442 ( .A0(n2637), .A1(n2518), .B0(n5143), .B1(n5155), .Y(n6418) ); NOR3X4TS U3443 ( .A(n1988), .B(n2642), .C(n2641), .Y(n2640) ); OR2X8TS U3444 ( .A(n3405), .B(DMP_SFG[42]), .Y(n3296) ); BUFX16TS U3445 ( .A(n3779), .Y(n1989) ); NOR2X8TS U3446 ( .A(Raw_mant_NRM_SWR[15]), .B(Raw_mant_NRM_SWR[25]), .Y( n1990) ); INVX16TS U3447 ( .A(n1992), .Y(n3779) ); NOR2X8TS U3448 ( .A(n1998), .B(n1993), .Y(n4029) ); NAND3X6TS U3449 ( .A(n1909), .B(n1995), .C(n1994), .Y(n1993) ); OR2X8TS U3450 ( .A(n1904), .B(n2748), .Y(n1994) ); OAI2BB1X4TS U3451 ( .A0N(n2251), .A1N(n2324), .B0(n3741), .Y(n2000) ); NAND2X6TS U3452 ( .A(n3262), .B(n2749), .Y(n2001) ); NAND3X8TS U3453 ( .A(n3263), .B(n3299), .C(n3749), .Y(n2002) ); NAND2X8TS U3454 ( .A(n1905), .B(n2003), .Y(n2850) ); NAND4X8TS U3455 ( .A(n1905), .B(n2849), .C(n2003), .D(n2851), .Y(n2848) ); AND2X8TS U3456 ( .A(n3727), .B(n3728), .Y(n2003) ); NOR2X8TS U3457 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[22]), .Y( n3762) ); NOR2X4TS U3458 ( .A(n3337), .B(intDY_EWSW[34]), .Y(n2006) ); NOR2X8TS U3459 ( .A(n3343), .B(intDY_EWSW[35]), .Y(n2007) ); NAND2X4TS U3460 ( .A(n3316), .B(intDY_EWSW[32]), .Y(n2008) ); NOR2X8TS U3461 ( .A(n3334), .B(intDY_EWSW[33]), .Y(n3520) ); NOR2X6TS U3462 ( .A(n2456), .B(n2009), .Y(n3470) ); OAI22X4TS U3463 ( .A0(n2009), .A1(n2455), .B0(intDX_EWSW[19]), .B1(n2372), .Y(n2454) ); NOR2X8TS U3464 ( .A(n3291), .B(intDY_EWSW[19]), .Y(n2009) ); NAND2X2TS U3465 ( .A(n2526), .B(n2017), .Y(n4399) ); NAND2X2TS U3466 ( .A(n1836), .B(intDY_EWSW[59]), .Y(n3590) ); OAI21X4TS U3467 ( .A0(n2627), .A1(n3426), .B0(n3425), .Y(n3427) ); AND2X8TS U3468 ( .A(n2478), .B(intDX_EWSW[7]), .Y(n2627) ); NAND3X6TS U3469 ( .A(n4444), .B(n4445), .C(n4443), .Y(n1581) ); NAND2X8TS U3470 ( .A(n3202), .B(n2563), .Y(n2985) ); CLKINVX12TS U3471 ( .A(n2013), .Y(n2616) ); AND2X8TS U3472 ( .A(n4425), .B(n2036), .Y(n2280) ); BUFX16TS U3473 ( .A(n2902), .Y(n2846) ); NAND3X8TS U3474 ( .A(n4335), .B(n3772), .C(n5431), .Y(n2013) ); NAND3X6TS U3475 ( .A(n2787), .B(n2788), .C(n3222), .Y(n2336) ); NOR2X8TS U3476 ( .A(n3392), .B(DMP_SFG[30]), .Y(n4965) ); XOR2X4TS U3477 ( .A(DmP_mant_SFG_SWR[32]), .B(n1854), .Y(n3392) ); XOR2X4TS U3478 ( .A(DmP_mant_SFG_SWR[33]), .B(n1852), .Y(n2628) ); AOI22X2TS U3479 ( .A0(n6219), .A1(Raw_mant_NRM_SWR[23]), .B0(n6199), .B1( DmP_mant_SHT1_SW[26]), .Y(n6306) ); AOI22X2TS U3480 ( .A0(n6219), .A1(Raw_mant_NRM_SWR[12]), .B0(n6199), .B1( DmP_mant_SHT1_SW[37]), .Y(n6365) ); AOI22X2TS U3481 ( .A0(n6199), .A1(DmP_mant_SHT1_SW[3]), .B0(n2548), .B1( n2500), .Y(n6325) ); NOR2X8TS U3482 ( .A(n2014), .B(n2063), .Y(n2394) ); NAND3X8TS U3483 ( .A(n2064), .B(n2065), .C(n5442), .Y(n2014) ); NAND2X4TS U3484 ( .A(n3337), .B(intDY_EWSW[34]), .Y(n3522) ); BUFX6TS U3485 ( .A(n5340), .Y(n2015) ); AOI2BB1X4TS U3486 ( .A0N(n3752), .A1N(Raw_mant_NRM_SWR[25]), .B0( Raw_mant_NRM_SWR[26]), .Y(n2490) ); AOI2BB2X2TS U3487 ( .B0(n5709), .B1(n2193), .A0N(n5708), .A1N(n2141), .Y( n3929) ); BUFX6TS U3488 ( .A(intDY_EWSW[51]), .Y(n2017) ); NOR2X8TS U3489 ( .A(n3420), .B(n2627), .Y(n3428) ); NAND2X2TS U3490 ( .A(n3587), .B(intDY_EWSW[62]), .Y(n3661) ); CLKINVX12TS U3491 ( .A(Raw_mant_NRM_SWR[48]), .Y(n2057) ); BUFX20TS U3492 ( .A(n4790), .Y(n4425) ); AOI22X1TS U3493 ( .A0(n6206), .A1(n2252), .B0(n5037), .B1(n2873), .Y(n6321) ); NOR2X8TS U3494 ( .A(n2848), .B(n3750), .Y(n2847) ); NAND2X8TS U3495 ( .A(n2394), .B(n2892), .Y(n3750) ); NAND2X8TS U3496 ( .A(n2033), .B(n3127), .Y(n2635) ); OR2X8TS U3497 ( .A(n3233), .B(n3759), .Y(n3760) ); AND3X6TS U3498 ( .A(n5178), .B(n5172), .C(n4016), .Y(n2944) ); NOR4X2TS U3499 ( .A(n4185), .B(n4184), .C(n4183), .D(n4182), .Y(n4227) ); NAND2X4TS U3500 ( .A(n3362), .B(intDY_EWSW[41]), .Y(n3530) ); NOR2X4TS U3501 ( .A(Raw_mant_NRM_SWR[36]), .B(Raw_mant_NRM_SWR[30]), .Y( n3729) ); OAI2BB1X4TS U3502 ( .A0N(n5161), .A1N(n6455), .B0(n5130), .Y(n1055) ); OAI22X2TS U3503 ( .A0(n2990), .A1(n5063), .B0(n5287), .B1(n2119), .Y(n1077) ); AOI22X2TS U3504 ( .A0(n6218), .A1(Raw_mant_NRM_SWR[48]), .B0(n5043), .B1( n6230), .Y(n6398) ); AOI22X4TS U3505 ( .A0(n5139), .A1(n2519), .B0(n5155), .B1(n5138), .Y(n6420) ); AOI22X2TS U3506 ( .A0(n6205), .A1(n2012), .B0(n5015), .B1(n5041), .Y(n6395) ); NAND2X2TS U3507 ( .A(n2529), .B(n5021), .Y(n4638) ); NAND2X2TS U3508 ( .A(n3846), .B(n5025), .Y(n3944) ); AND2X8TS U3509 ( .A(n2320), .B(intDX_EWSW[37]), .Y(n2679) ); OAI22X4TS U3510 ( .A0(n4684), .A1(n2611), .B0(n4709), .B1(n4324), .Y(n3837) ); NAND2X2TS U3511 ( .A(n3587), .B(n2036), .Y(n3639) ); INVX12TS U3512 ( .A(n3805), .Y(n3846) ); NAND2X4TS U3513 ( .A(n2555), .B(n1644), .Y(n4525) ); NAND4X6TS U3514 ( .A(n4527), .B(n4526), .C(n4525), .D(n4524), .Y(n4633) ); OAI22X4TS U3515 ( .A0(n4617), .A1(n2990), .B0(n5292), .B1(n5545), .Y(n1060) ); AND2X8TS U3516 ( .A(n4873), .B(intDY_EWSW[17]), .Y(n2271) ); NAND2X4TS U3517 ( .A(n5141), .B(n5147), .Y(n4614) ); NAND2BX4TS U3518 ( .AN(n4266), .B(n4265), .Y(n4288) ); NAND2X4TS U3519 ( .A(n3678), .B(n2305), .Y(n1526) ); NAND2X4TS U3520 ( .A(n1919), .B(n1917), .Y(n4290) ); BUFX6TS U3521 ( .A(intDY_EWSW[14]), .Y(n2024) ); BUFX6TS U3522 ( .A(n3587), .Y(n2027) ); AOI22X1TS U3523 ( .A0(n2982), .A1(Raw_mant_NRM_SWR[52]), .B0(n5020), .B1( n2873), .Y(n6329) ); NOR2X8TS U3524 ( .A(n2029), .B(n2060), .Y(n2891) ); NAND2X8TS U3525 ( .A(n2058), .B(n2059), .Y(n2029) ); NOR2X8TS U3526 ( .A(Raw_mant_NRM_SWR[53]), .B(n2323), .Y(n3790) ); AND2X8TS U3527 ( .A(n3120), .B(n2030), .Y(n5283) ); BUFX6TS U3528 ( .A(n3339), .Y(n2031) ); NAND3X6TS U3529 ( .A(n4352), .B(n2417), .C(n2377), .Y(n4353) ); NAND2X8TS U3530 ( .A(n4353), .B(n2562), .Y(n4908) ); NAND2X8TS U3531 ( .A(n3132), .B(n5286), .Y(n2937) ); BUFX20TS U3532 ( .A(n4790), .Y(n4412) ); NAND2X1TS U3533 ( .A(n3087), .B(intDX_EWSW[57]), .Y(n4789) ); NOR2X6TS U3534 ( .A(n3118), .B(n3476), .Y(n3478) ); INVX16TS U3535 ( .A(n6217), .Y(n2934) ); NOR2X8TS U3536 ( .A(Raw_mant_NRM_SWR[23]), .B(n2300), .Y(n4335) ); NAND2X8TS U3537 ( .A(n6205), .B(n1913), .Y(n3260) ); NAND3X2TS U3538 ( .A(n4112), .B(n4113), .C(n4111), .Y(n1298) ); MXI2X4TS U3539 ( .A(n2763), .B(n5411), .S0(n5277), .Y(n1199) ); BUFX20TS U3540 ( .A(n3087), .Y(n3630) ); INVX12TS U3541 ( .A(n3175), .Y(n2342) ); AOI22X4TS U3542 ( .A0(n4604), .A1(n2560), .B0(n2691), .B1(n3365), .Y(n4617) ); NAND2X2TS U3543 ( .A(n4474), .B(n5262), .Y(n4083) ); BUFX6TS U3544 ( .A(intDY_EWSW[22]), .Y(n2036) ); NAND2X8TS U3545 ( .A(n2452), .B(intDX_EWSW[3]), .Y(n4433) ); NAND2X4TS U3546 ( .A(n2049), .B(n2050), .Y(n4317) ); NAND3X4TS U3547 ( .A(n4317), .B(n4318), .C(n4316), .Y(n1292) ); NOR2X6TS U3548 ( .A(n5421), .B(n3350), .Y(n3378) ); NAND2X8TS U3549 ( .A(n5316), .B(n2039), .Y(n5064) ); NAND2X8TS U3550 ( .A(n2341), .B(n5317), .Y(n2039) ); NAND2X8TS U3551 ( .A(n2343), .B(n3270), .Y(n2341) ); NOR4X2TS U3552 ( .A(n4205), .B(n4204), .C(n4203), .D(n4202), .Y(n4226) ); BUFX6TS U3553 ( .A(DMP_exp_NRM2_EW[0]), .Y(n2040) ); NAND2X4TS U3554 ( .A(n4116), .B(n4114), .Y(n2958) ); NAND2X2TS U3555 ( .A(n2963), .B(intDY_EWSW[49]), .Y(n4395) ); BUFX6TS U3556 ( .A(n3550), .Y(n2042) ); CLKINVX6TS U3557 ( .A(n3907), .Y(n3281) ); OR2X8TS U3558 ( .A(n3907), .B(n3897), .Y(n3172) ); NOR2X6TS U3559 ( .A(n3307), .B(intDY_EWSW[30]), .Y(n3464) ); INVX4TS U3560 ( .A(n2440), .Y(n2314) ); NAND3X6TS U3561 ( .A(n2723), .B(n2789), .C(DMP_SFG[26]), .Y(n2675) ); NOR2X6TS U3562 ( .A(n3302), .B(intDY_EWSW[46]), .Y(n2864) ); NAND2X8TS U3563 ( .A(n2802), .B(n2043), .Y(n4608) ); AND2X8TS U3564 ( .A(n3963), .B(n3965), .Y(n2043) ); NAND4BX4TS U3565 ( .AN(n3932), .B(n2799), .C(n2801), .D(n2798), .Y(n4619) ); NAND2X2TS U3566 ( .A(n4699), .B(n3846), .Y(n3964) ); INVX8TS U3567 ( .A(n4920), .Y(n3256) ); AOI21X4TS U3568 ( .A0(n3490), .A1(n3489), .B0(n2044), .Y(n3502) ); OAI21X4TS U3569 ( .A0(n3487), .A1(n3488), .B0(n3486), .Y(n2044) ); AND2X8TS U3570 ( .A(n2302), .B(intDX_EWSW[39]), .Y(n3528) ); NOR2X8TS U3571 ( .A(DMP_exp_NRM2_EW[1]), .B(n2308), .Y(n3980) ); AND2X8TS U3572 ( .A(n4771), .B(n2789), .Y(n4781) ); BUFX6TS U3573 ( .A(intDY_EWSW[47]), .Y(n2045) ); OAI22X2TS U3574 ( .A0(n2453), .A1(n5256), .B0(n5289), .B1(n5536), .Y(n1098) ); OAI22X2TS U3575 ( .A0(n2453), .A1(n5255), .B0(n5292), .B1(n5533), .Y(n1108) ); NOR2X8TS U3576 ( .A(n2610), .B(n2609), .Y(n2608) ); BUFX6TS U3577 ( .A(intDY_EWSW[26]), .Y(n2046) ); NAND2X4TS U3578 ( .A(n3303), .B(intDY_EWSW[20]), .Y(n3472) ); OAI22X4TS U3579 ( .A0(n3322), .A1(n1916), .B0(n5292), .B1(n5529), .Y(n1095) ); XOR2X4TS U3580 ( .A(DmP_mant_SFG_SWR[35]), .B(n1852), .Y(n2842) ); BUFX6TS U3581 ( .A(intDY_EWSW[10]), .Y(n2048) ); BUFX6TS U3582 ( .A(intDY_EWSW[9]), .Y(n2050) ); NOR2X8TS U3583 ( .A(n2274), .B(n3010), .Y(n2273) ); NAND4X8TS U3584 ( .A(n4029), .B(n4028), .C(n4338), .D(n4339), .Y(n3202) ); NOR2X8TS U3585 ( .A(n4340), .B(n2888), .Y(n4028) ); NOR2X8TS U3586 ( .A(n3432), .B(n3450), .Y(n3452) ); OAI21X4TS U3587 ( .A0(n3495), .A1(n3496), .B0(n3494), .Y(n3497) ); AND2X8TS U3588 ( .A(n4838), .B(n2299), .Y(n2275) ); NAND2X2TS U3589 ( .A(n4430), .B(intDY_EWSW[8]), .Y(n4134) ); NAND3X6TS U3590 ( .A(n4133), .B(n4134), .C(n4132), .Y(n1579) ); NAND2X2TS U3591 ( .A(n4430), .B(intDY_EWSW[0]), .Y(n4385) ); NAND2X2TS U3592 ( .A(n1838), .B(n2250), .Y(n4429) ); NAND2X2TS U3593 ( .A(n3587), .B(intDY_EWSW[20]), .Y(n3676) ); NAND3BX4TS U3594 ( .AN(n2275), .B(n4826), .C(n4827), .Y(n1220) ); BUFX20TS U3595 ( .A(n4838), .Y(n2053) ); NAND2X8TS U3596 ( .A(n2053), .B(intDX_EWSW[30]), .Y(n3644) ); NAND2X8TS U3597 ( .A(n2053), .B(intDX_EWSW[32]), .Y(n3647) ); NAND2X8TS U3598 ( .A(n2495), .B(n2300), .Y(n6311) ); NAND2X6TS U3599 ( .A(n2925), .B(Raw_mant_NRM_SWR[11]), .Y(n6360) ); BUFX12TS U3600 ( .A(n2980), .Y(n2054) ); NAND2X6TS U3601 ( .A(n2055), .B(n2980), .Y(n3187) ); NAND2X4TS U3602 ( .A(n3780), .B(n4260), .Y(n2055) ); NAND2X8TS U3603 ( .A(n3734), .B(n2480), .Y(n3265) ); NAND2X8TS U3604 ( .A(n3035), .B(n2980), .Y(n4897) ); INVX16TS U3605 ( .A(n3233), .Y(n2980) ); CLKINVX12TS U3606 ( .A(Raw_mant_NRM_SWR[27]), .Y(n2058) ); NOR2X8TS U3607 ( .A(Raw_mant_NRM_SWR[29]), .B(Raw_mant_NRM_SWR[32]), .Y( n2064) ); OR2X8TS U3608 ( .A(n2066), .B(n2797), .Y(n4620) ); AOI22X4TS U3609 ( .A0(n4047), .A1(n5927), .B0(n5858), .B1(n2128), .Y(n2067) ); OAI2BB1X4TS U3610 ( .A0N(n5161), .A1N(n6441), .B0(n5156), .Y(n1050) ); NAND3BX4TS U3611 ( .AN(n4700), .B(n2068), .C(n4705), .Y(n6441) ); OAI21X4TS U3612 ( .A0(n3833), .A1(n5050), .B0(n2070), .Y(n2069) ); OAI22X4TS U3613 ( .A0(n4697), .A1(n4698), .B0(n4706), .B1(n4696), .Y(n2072) ); OAI2BB1X4TS U3614 ( .A0N(LZD_output_NRM2_EW[5]), .A1N(n2513), .B0(n4905), .Y(n1141) ); OAI21X4TS U3615 ( .A0(n2074), .A1(n2073), .B0(n2563), .Y(n4905) ); NAND3BX4TS U3616 ( .AN(n2075), .B(n1908), .C(n4889), .Y(n2074) ); INVX16TS U3617 ( .A(n3233), .Y(n2480) ); NAND2X8TS U3618 ( .A(n2480), .B(n2078), .Y(n2742) ); OAI21X4TS U3619 ( .A0(n2079), .A1(n2080), .B0(n2082), .Y(n3091) ); AND3X8TS U3620 ( .A(n2081), .B(n4591), .C(n4590), .Y(n2080) ); NAND2X8TS U3621 ( .A(n4649), .B(n1872), .Y(n2082) ); AOI21X4TS U3622 ( .A0(n5023), .A1(n2261), .B0(n2084), .Y(n2083) ); NAND3X8TS U3623 ( .A(n3695), .B(n3696), .C(n1901), .Y(n1645) ); OAI22X4TS U3624 ( .A0(n5291), .A1(n2088), .B0(n6293), .B1(n5502), .Y(n1058) ); AOI2BB2X4TS U3625 ( .B0(n5276), .B1(n1877), .A0N(n2263), .A1N(n2264), .Y( n5291) ); NAND4X8TS U3626 ( .A(n3114), .B(n4655), .C(n3116), .D(n2089), .Y(n5276) ); NOR2BX4TS U3627 ( .AN(n5859), .B(n2094), .Y(n2093) ); AOI22X4TS U3628 ( .A0(n2164), .A1(n5735), .B0(n5736), .B1(n2171), .Y(n2097) ); NOR2X8TS U3629 ( .A(Raw_mant_NRM_SWR[40]), .B(n2345), .Y(n4270) ); OAI21X4TS U3630 ( .A0(n2099), .A1(n4997), .B0(n2098), .Y(n1159) ); NAND2X1TS U3631 ( .A(n4997), .B(n2345), .Y(n2098) ); XOR2X4TS U3632 ( .A(n4929), .B(n2358), .Y(n2099) ); NAND4BBX4TS U3633 ( .AN(n3704), .BN(n3705), .C(n2101), .D(n2100), .Y(n4496) ); NOR2X8TS U3634 ( .A(n2107), .B(n2102), .Y(n2101) ); NAND2BX4TS U3635 ( .AN(n4643), .B(n2106), .Y(n2105) ); AOI21X4TS U3636 ( .A0(n2109), .A1(n2108), .B0(n2826), .Y(n2107) ); AOI22X2TS U3637 ( .A0(n1645), .A1(n1950), .B0(n4636), .B1(n4659), .Y(n2109) ); BUFX20TS U3638 ( .A(n2510), .Y(n2114) ); BUFX20TS U3639 ( .A(n4431), .Y(n2115) ); BUFX20TS U3640 ( .A(n2114), .Y(n2116) ); AND2X8TS U3641 ( .A(n3571), .B(Shift_reg_FLAGS_7_6), .Y(n2510) ); NOR2X8TS U3642 ( .A(n2117), .B(n2042), .Y(n3510) ); NOR2X8TS U3643 ( .A(n3308), .B(intDY_EWSW[49]), .Y(n3550) ); INVX2TS U3644 ( .A(final_result_ieee[45]), .Y(n2119) ); OA21X4TS U3645 ( .A0(n2120), .A1(n2653), .B0(n2121), .Y(n2905) ); AOI22X4TS U3646 ( .A0(n5155), .A1(n5154), .B0(n2517), .B1(n5153), .Y(n6431) ); NAND4X8TS U3647 ( .A(n4292), .B(n4289), .C(n4290), .D(n4291), .Y(n5154) ); NAND3X8TS U3648 ( .A(n3944), .B(n3942), .C(n2418), .Y(n5143) ); AOI22X2TS U3649 ( .A0(n2637), .A1(n2516), .B0(n5145), .B1(n5143), .Y(n6458) ); NAND2X2TS U3650 ( .A(n1919), .B(n5016), .Y(n3942) ); NAND2X2TS U3651 ( .A(n4807), .B(intDX_EWSW[20]), .Y(n3675) ); OAI22X2TS U3652 ( .A0(n5876), .A1(n5875), .B0(n2124), .B1(n6158), .Y(n2641) ); OAI2BB1X4TS U3653 ( .A0N(n5726), .A1N(n5727), .B0(n6120), .Y(n2461) ); NAND2BX4TS U3654 ( .AN(n5928), .B(n5966), .Y(n3054) ); OA22X2TS U3655 ( .A0(n2205), .A1(n2129), .B0(n2178), .B1(n5949), .Y(n3925) ); NAND2X1TS U3656 ( .A(n5878), .B(n2132), .Y(n4043) ); AOI2BB2X2TS U3657 ( .B0(n5851), .B1(n2132), .A0N(n5850), .A1N(n2184), .Y( n3719) ); NAND2X1TS U3658 ( .A(n5781), .B(n2137), .Y(n3950) ); NAND2X1TS U3659 ( .A(n5752), .B(n2138), .Y(n3863) ); AOI2BB2X1TS U3660 ( .B0(n5795), .B1(n2138), .A0N(n5794), .A1N(n2150), .Y( n4594) ); AOI2BB2X1TS U3661 ( .B0(n5951), .B1(n2163), .A0N(n5950), .A1N(n2141), .Y( n4033) ); NOR2X1TS U3662 ( .A(n5751), .B(n2148), .Y(n3949) ); OAI22X1TS U3663 ( .A0(n6021), .A1(n2148), .B0(n6020), .B1(n6019), .Y(n4051) ); OAI22X2TS U3664 ( .A0(n6061), .A1(n6060), .B0(n5857), .B1(n2152), .Y(n2797) ); OA22X4TS U3665 ( .A0(n2231), .A1(n2136), .B0(n2232), .B1(n2157), .Y(n4024) ); OAI21X1TS U3666 ( .A0(n6116), .A1(n2157), .B0(n6115), .Y(n3947) ); OAI22X2TS U3667 ( .A0(n5936), .A1(n5935), .B0(n5934), .B1(n2158), .Y(n3852) ); OA22X1TS U3668 ( .A0(n2159), .A1(n5993), .B0(n5992), .B1(n5991), .Y(n3952) ); AOI2BB2X2TS U3669 ( .B0(n5846), .B1(n5845), .A0N(n5844), .A1N(n2159), .Y( n4022) ); AND2X2TS U3670 ( .A(n6075), .B(n2160), .Y(n4050) ); AOI22X2TS U3671 ( .A0(n5721), .A1(n5720), .B0(n5719), .B1(n2160), .Y(n3951) ); AOI22X2TS U3672 ( .A0(n5698), .A1(n2161), .B0(n5697), .B1(n2195), .Y(n3849) ); OAI2BB2X2TS U3673 ( .B0(n2190), .B1(n6090), .A0N(n2162), .A1N(n5756), .Y( n2700) ); AOI2BB2X2TS U3674 ( .B0(n5895), .B1(n2165), .A0N(n5894), .A1N(n5893), .Y( n3945) ); AOI22X2TS U3675 ( .A0(n5897), .A1(n2172), .B0(n5896), .B1(n2166), .Y(n3924) ); AOI22X2TS U3676 ( .A0(n5968), .A1(n2167), .B0(n5967), .B1(n2194), .Y(n3823) ); NAND2X4TS U3677 ( .A(n5902), .B(n2168), .Y(n4038) ); AOI21X2TS U3678 ( .A0(n5762), .A1(n2169), .B0(n5761), .Y(n3702) ); NAND2X2TS U3679 ( .A(n5933), .B(n2170), .Y(n3967) ); AOI2BB2X2TS U3680 ( .B0(n5754), .B1(n2193), .A0N(n5753), .A1N(n2175), .Y( n3701) ); AOI2BB2X4TS U3681 ( .B0(n5853), .B1(n2200), .A0N(n5852), .A1N(n2183), .Y( n3716) ); OAI22X2TS U3682 ( .A0(n6044), .A1(n2184), .B0(n6043), .B1(n6042), .Y(n3842) ); AOI2BB2X2TS U3683 ( .B0(n2226), .B1(n2227), .A0N(n2185), .A1N(n2232), .Y( n3850) ); AOI2BB2X1TS U3684 ( .B0(n5885), .B1(n2193), .A0N(n5884), .A1N(n5883), .Y( n4032) ); NAND2X2TS U3685 ( .A(n5757), .B(n2196), .Y(n3848) ); AOI22X2TS U3686 ( .A0(n5772), .A1(n2133), .B0(n5771), .B1(n2197), .Y(n3955) ); NAND2X1TS U3687 ( .A(n5899), .B(n2198), .Y(n3954) ); NAND2X2TS U3688 ( .A(n5865), .B(n2200), .Y(n3970) ); NAND2X4TS U3689 ( .A(n5962), .B(n2202), .Y(n2599) ); OAI2BB1X1TS U3690 ( .A0N(n2203), .A1N(n6101), .B0(n6100), .Y(n4052) ); OAI2BB1X1TS U3691 ( .A0N(n2203), .A1N(n6105), .B0(n6104), .Y(n3861) ); OAI21X4TS U3692 ( .A0(n6126), .A1(n2204), .B0(n6125), .Y(n4036) ); AOI2BB2X2TS U3693 ( .B0(n5775), .B1(n5774), .A0N(n5773), .A1N(n2205), .Y( n3828) ); OA22X4TS U3694 ( .A0(n2205), .A1(n6024), .B0(n6023), .B1(n6022), .Y(n3708) ); NAND2X2TS U3695 ( .A(n5866), .B(n2206), .Y(n3935) ); NOR2BX2TS U3696 ( .AN(n5829), .B(n2410), .Y(n3076) ); AOI22X4TS U3697 ( .A0(n2166), .A1(n5955), .B0(n5729), .B1(n5730), .Y(n3001) ); AOI2BB2X1TS U3698 ( .B0(n5803), .B1(n2213), .A0N(n2208), .A1N(n5802), .Y( n5107) ); AOI2BB2X1TS U3699 ( .B0(n5817), .B1(n2213), .A0N(n2208), .A1N(n5816), .Y( n5110) ); AOI21X4TS U3700 ( .A0(n6118), .A1(n2207), .B0(n3923), .Y(n3926) ); OAI2BB1X4TS U3701 ( .A0N(n2201), .A1N(n5738), .B0(n3054), .Y(n3053) ); INVX8TS U3702 ( .A(n3922), .Y(n6203) ); AOI2BB2X1TS U3703 ( .B0(n5801), .B1(n2213), .A0N(n2209), .A1N(n5800), .Y( n5116) ); AOI21X4TS U3704 ( .A0(n6117), .A1(n2125), .B0(n3822), .Y(n3825) ); AOI22X4TS U3705 ( .A0(n5788), .A1(n5787), .B0(n5786), .B1(n2126), .Y(n3958) ); AOI22X4TS U3706 ( .A0(n5716), .A1(n5715), .B0(n5714), .B1(n5713), .Y(n3840) ); AOI21X4TS U3707 ( .A0(n5703), .A1(n2199), .B0(n2210), .Y(n3078) ); AOI2BB2X4TS U3708 ( .B0(n5856), .B1(n2199), .A0N(n5855), .A1N(n2182), .Y( n3841) ); AOI22X4TS U3709 ( .A0(n5707), .A1(n2126), .B0(n5706), .B1(n2201), .Y(n3698) ); AOI22X4TS U3710 ( .A0(n5739), .A1(n2133), .B0(n5718), .B1(n2198), .Y(n2585) ); AOI21X2TS U3711 ( .A0(n5760), .A1(n2206), .B0(n2772), .Y(n2771) ); AOI2BB2X1TS U3712 ( .B0(n5808), .B1(n2213), .A0N(n2212), .A1N(n5807), .Y( n5109) ); AOI2BB2X1TS U3713 ( .B0(n5805), .B1(n2213), .A0N(n2212), .A1N(n5804), .Y( n5114) ); AOI2BB2X4TS U3714 ( .B0(n5765), .B1(n5764), .A0N(n5763), .A1N(n2185), .Y( n3693) ); AOI22X4TS U3715 ( .A0(n2202), .A1(n5694), .B0(n5696), .B1(n5695), .Y(n2643) ); OAI22X1TS U3716 ( .A0(n6067), .A1(n6066), .B0(n6065), .B1(n6064), .Y(n3860) ); OAI22X1TS U3717 ( .A0(n6018), .A1(n6017), .B0(n6016), .B1(n6015), .Y(n3826) ); NOR2BX4TS U3718 ( .AN(n2411), .B(n5952), .Y(n2645) ); OAI2BB1X4TS U3719 ( .A0N(n2130), .A1N(n5702), .B0(n3153), .Y(n3152) ); AOI21X4TS U3720 ( .A0(n5705), .A1(n5704), .B0(n5892), .Y(n3077) ); AOI21X4TS U3721 ( .A0(n6133), .A1(n2197), .B0(n3692), .Y(n3696) ); AO22X4TS U3722 ( .A0(n5961), .A1(n5960), .B0(n5959), .B1(n2202), .Y(n3923) ); AOI22X4TS U3723 ( .A0(n4047), .A1(n5919), .B0(n5741), .B1(n5740), .Y(n2587) ); AOI21X4TS U3724 ( .A0(n6124), .A1(n2172), .B0(n3827), .Y(n3830) ); OAI2BB1X4TS U3725 ( .A0N(n2196), .A1N(n5953), .B0(n2643), .Y(n2642) ); AOI21X4TS U3726 ( .A0(n5734), .A1(n2195), .B0(n5827), .Y(n3057) ); AOI22X4TS U3727 ( .A0(n5712), .A1(n2134), .B0(n5711), .B1(n2167), .Y(n3713) ); AOI2BB2X4TS U3728 ( .B0(n5743), .B1(n2168), .A0N(n5742), .A1N(n2173), .Y( n3710) ); AOI2BB2X4TS U3729 ( .B0(n5770), .B1(n2170), .A0N(n5769), .A1N(n2190), .Y( n3714) ); OAI2BB2X4TS U3730 ( .B0(n5901), .B1(n2179), .A0N(n2194), .A1N(n5837), .Y( n3143) ); OAI21X4TS U3731 ( .A0(n5733), .A1(n2181), .B0(n3057), .Y(n3056) ); NOR2BX4TS U3732 ( .AN(n2142), .B(n5847), .Y(n3138) ); OA22X2TS U3733 ( .A0(n2204), .A1(n2129), .B0(n2179), .B1(n5942), .Y(n3824) ); NOR2X8TS U3734 ( .A(n2950), .B(n3056), .Y(n3055) ); AOI2BB2X4TS U3735 ( .B0(n5944), .B1(n2125), .A0N(n5943), .A1N(n2152), .Y( n4034) ); AOI21X4TS U3736 ( .A0(n5836), .A1(n2192), .B0(n2215), .Y(n3141) ); NOR2BX4TS U3737 ( .AN(n2415), .B(n5976), .Y(n2217) ); OAI22X4TS U3738 ( .A0(n5995), .A1(n5994), .B0(n5997), .B1(n5996), .Y(n3154) ); OA22X4TS U3739 ( .A0(n6004), .A1(n2174), .B0(n6003), .B1(n6002), .Y(n3939) ); OA22X2TS U3740 ( .A0(n5990), .A1(n5989), .B0(n5988), .B1(n5987), .Y(n3956) ); INVX4TS U3741 ( .A(n2217), .Y(n2216) ); OAI21X4TS U3742 ( .A0(n5873), .A1(n5872), .B0(n2813), .Y(n2812) ); AOI2BB2X4TS U3743 ( .B0(n4047), .B1(n5915), .A0N(n5914), .A1N(n5913), .Y( n3694) ); OAI22X1TS U3744 ( .A0(n2175), .A1(n2191), .B0(n6079), .B1(n6078), .Y(n3831) ); BUFX12TS U3745 ( .A(n5032), .Y(n2498) ); OAI22X4TS U3746 ( .A0(n6055), .A1(n6054), .B0(n5759), .B1(n5758), .Y(n2772) ); AOI2BB2X1TS U3747 ( .B0(n5783), .B1(n2218), .A0N(n2212), .A1N(n5782), .Y( n5102) ); AOI2BB2X1TS U3748 ( .B0(n5790), .B1(n2218), .A0N(n2208), .A1N(n5789), .Y( n5117) ); AOI2BB2X1TS U3749 ( .B0(n5792), .B1(n2218), .A0N(n2209), .A1N(n5791), .Y( n5121) ); AOI2BB2X1TS U3750 ( .B0(n5797), .B1(n2218), .A0N(n2212), .A1N(n5796), .Y( n5105) ); AOI2BB2X1TS U3751 ( .B0(n5799), .B1(n2218), .A0N(n2208), .A1N(n5798), .Y( n5115) ); AOI2BB2X1TS U3752 ( .B0(n5813), .B1(n2218), .A0N(n2209), .A1N(n5812), .Y( n5112) ); AOI2BB2X1TS U3753 ( .B0(n5815), .B1(n2218), .A0N(n2212), .A1N(n5814), .Y( n5119) ); AOI2BB2X1TS U3754 ( .B0(n5821), .B1(n2218), .A0N(n2209), .A1N(n5820), .Y( n5104) ); AOI2BB2X1TS U3755 ( .B0(n5823), .B1(n2218), .A0N(n2209), .A1N(n5822), .Y( n5108) ); OA22X2TS U3756 ( .A0(n2150), .A1(n5986), .B0(n5985), .B1(n5984), .Y(n3864) ); NOR2BX4TS U3757 ( .AN(n2177), .B(n5954), .Y(n3004) ); NOR2BX4TS U3758 ( .AN(n2412), .B(n6029), .Y(n2783) ); NOR2BX4TS U3759 ( .AN(n1907), .B(n6056), .Y(n2774) ); NOR2BX4TS U3760 ( .AN(n2180), .B(n6049), .Y(n3050) ); NOR2BX4TS U3761 ( .AN(n2413), .B(n5956), .Y(n2814) ); NAND2X2TS U3762 ( .A(n2555), .B(n1860), .Y(n4295) ); AOI21X4TS U3763 ( .A0(n1860), .A1(n4708), .B0(n4037), .Y(n4058) ); NAND2X2TS U3764 ( .A(n4723), .B(n1859), .Y(n4126) ); NAND2X2TS U3765 ( .A(n2529), .B(n1645), .Y(n3806) ); AND3X4TS U3766 ( .A(n4638), .B(n4640), .C(n4639), .Y(n3147) ); AOI2BB2X4TS U3767 ( .B0(n2229), .B1(n2230), .A0N(n2232), .A1N(n2176), .Y( n2228) ); BUFX16TS U3768 ( .A(n2233), .Y(n2232) ); OAI21X4TS U3769 ( .A0(n5881), .A1(n5880), .B0(n2234), .Y(n3005) ); OAI21X4TS U3770 ( .A0(n6028), .A1(n6027), .B0(n6177), .Y(n2782) ); NOR2BX4TS U3771 ( .AN(n2414), .B(n6048), .Y(n3051) ); AOI2BB2X2TS U3772 ( .B0(n4047), .B1(n5912), .A0N(n5911), .A1N(n5910), .Y( n3961) ); OA22X2TS U3773 ( .A0(n2191), .A1(n2140), .B0(n6026), .B1(n6025), .Y(n3968) ); NOR2BX4TS U3774 ( .AN(n2146), .B(n5717), .Y(n2581) ); NOR2BX4TS U3775 ( .AN(n2139), .B(n5725), .Y(n2463) ); NAND2BX4TS U3776 ( .AN(n5755), .B(n2186), .Y(n2702) ); NOR2X4TS U3777 ( .A(n5767), .B(n2174), .Y(n4042) ); NAND2X1TS U3778 ( .A(n5946), .B(n5945), .Y(n3928) ); NOR2X4TS U3779 ( .A(n4718), .B(n4710), .Y(n2819) ); NAND4X6TS U3780 ( .A(n4129), .B(n4128), .C(n4127), .D(n4126), .Y(n6457) ); OAI2BB1X4TS U3781 ( .A0N(n5828), .A1N(n2161), .B0(n3958), .Y(n2950) ); NAND4X4TS U3782 ( .A(n3929), .B(n3930), .C(n3931), .D(n3928), .Y(n5035) ); NAND2X1TS U3783 ( .A(n5806), .B(n2127), .Y(n3834) ); NAND2X4TS U3784 ( .A(n5860), .B(n2199), .Y(n3938) ); AOI21X4TS U3785 ( .A0(n5898), .A1(n2201), .B0(n2595), .Y(n2594) ); NOR2BX4TS U3786 ( .AN(n2188), .B(n5728), .Y(n3003) ); AOI2BB2X4TS U3787 ( .B0(n5785), .B1(n2135), .A0N(n5784), .A1N(n2151), .Y( n4087) ); NAND4X1TS U3788 ( .A(n4123), .B(n6108), .C(n6107), .D(n6106), .Y(n5020) ); NAND2X4TS U3789 ( .A(n5701), .B(n2200), .Y(n3153) ); NAND2X1TS U3790 ( .A(n3652), .B(n1553), .Y(n3597) ); NAND2X1TS U3791 ( .A(n3652), .B(n1549), .Y(n3615) ); NAND3X2TS U3792 ( .A(n6445), .B(n5189), .C(n6196), .Y(final_result_ieee[33]) ); NAND2X1TS U3793 ( .A(n2535), .B(n1216), .Y(n3581) ); NAND3X6TS U3794 ( .A(n4433), .B(n4434), .C(n4432), .Y(n1584) ); NAND2X2TS U3795 ( .A(n4369), .B(n2250), .Y(n4855) ); AO21X4TS U3796 ( .A0(n3740), .A1(n5417), .B0(n2019), .Y(n2251) ); NOR2X4TS U3797 ( .A(n3481), .B(n3462), .Y(n3469) ); NOR2X8TS U3798 ( .A(n3501), .B(n3468), .Y(n3504) ); AOI22X2TS U3799 ( .A0(n6205), .A1(Raw_mant_NRM_SWR[38]), .B0(n5041), .B1( n5017), .Y(n6373) ); AOI22X2TS U3800 ( .A0(n6205), .A1(Raw_mant_NRM_SWR[9]), .B0(n2873), .B1( n5016), .Y(n6386) ); AOI22X2TS U3801 ( .A0(n6205), .A1(Raw_mant_NRM_SWR[1]), .B0(n5262), .B1( n5041), .Y(n6352) ); AOI22X2TS U3802 ( .A0(n6205), .A1(n2300), .B0(n6230), .B1(n5026), .Y(n6315) ); AOI22X2TS U3803 ( .A0(n6205), .A1(Raw_mant_NRM_SWR[3]), .B0(n5018), .B1( n2873), .Y(n6334) ); AND2X8TS U3804 ( .A(intDX_EWSW[29]), .B(n2254), .Y(n3493) ); NOR2X2TS U3805 ( .A(n4245), .B(n2319), .Y(n4247) ); NAND2X8TS U3806 ( .A(n2750), .B(n4003), .Y(n4015) ); NOR2X4TS U3807 ( .A(n4015), .B(DMP_exp_NRM2_EW[10]), .Y(n4016) ); BUFX20TS U3808 ( .A(n4026), .Y(n6202) ); BUFX20TS U3809 ( .A(n2114), .Y(n4431) ); BUFX16TS U3810 ( .A(n2114), .Y(n4369) ); NAND2X4TS U3811 ( .A(n3376), .B(DMP_exp_NRM2_EW[3]), .Y(n3985) ); NAND2X2TS U3812 ( .A(n4873), .B(n1923), .Y(n3573) ); NAND2X2TS U3813 ( .A(n2116), .B(intDX_EWSW[35]), .Y(n3625) ); AND2X8TS U3814 ( .A(n4838), .B(intDX_EWSW[47]), .Y(n2277) ); NAND2X2TS U3815 ( .A(n4877), .B(intDY_EWSW[38]), .Y(n4100) ); NAND2X2TS U3816 ( .A(n4863), .B(n1984), .Y(n4829) ); NAND2X4TS U3817 ( .A(n2049), .B(intDX_EWSW[13]), .Y(n4078) ); NAND2X8TS U3818 ( .A(n2889), .B(n3787), .Y(n3258) ); AOI21X4TS U3819 ( .A0(n3240), .A1(Raw_mant_NRM_SWR[26]), .B0(n4259), .Y( n4262) ); BUFX20TS U3820 ( .A(n2054), .Y(n3240) ); NAND3X2TS U3821 ( .A(n3682), .B(n3681), .C(n3680), .Y(n1568) ); BUFX20TS U3822 ( .A(n2502), .Y(n2453) ); INVX16TS U3823 ( .A(n2399), .Y(n2260) ); INVX12TS U3824 ( .A(n2260), .Y(n2261) ); INVX12TS U3825 ( .A(n2260), .Y(n2262) ); NOR2X4TS U3826 ( .A(n5436), .B(shift_value_SHT2_EWR[3]), .Y(n2399) ); NAND2X2TS U3827 ( .A(n2116), .B(intDX_EWSW[11]), .Y(n4143) ); NAND2X4TS U3828 ( .A(n2115), .B(intDX_EWSW[7]), .Y(n4075) ); NAND2X4TS U3829 ( .A(n2115), .B(intDX_EWSW[8]), .Y(n4133) ); INVX12TS U3830 ( .A(n2870), .Y(n2872) ); NAND2X4TS U3831 ( .A(n2115), .B(n2046), .Y(n4841) ); NAND2X4TS U3832 ( .A(n2049), .B(intDX_EWSW[6]), .Y(n4444) ); NAND2BX4TS U3833 ( .AN(n2956), .B(n4109), .Y(n1208) ); NAND2X4TS U3834 ( .A(n5138), .B(n2517), .Y(n3162) ); INVX8TS U3835 ( .A(n6203), .Y(n2507) ); OAI21X2TS U3836 ( .A0(n4631), .A1(n5191), .B0(n2827), .Y(n1027) ); OAI22X2TS U3837 ( .A0(n2990), .A1(n4631), .B0(n5292), .B1(n5540), .Y(n1085) ); NOR2X6TS U3838 ( .A(n5180), .B(n5172), .Y(n3132) ); NOR2X6TS U3839 ( .A(n3375), .B(DMP_exp_NRM2_EW[2]), .Y(n3984) ); AND2X8TS U3840 ( .A(n4901), .B(Raw_mant_NRM_SWR[6]), .Y(n3200) ); NOR2X6TS U3841 ( .A(n4891), .B(n3191), .Y(n4901) ); NAND2X4TS U3842 ( .A(n4908), .B(n4907), .Y(n1609) ); OR2X8TS U3843 ( .A(intDX_EWSW[8]), .B(n2288), .Y(n2267) ); NAND3X8TS U3844 ( .A(n2616), .B(n3779), .C(n2615), .Y(n2268) ); NAND3X6TS U3845 ( .A(n4390), .B(n4391), .C(n4389), .Y(n1539) ); AOI2BB1X4TS U3846 ( .A0N(n2290), .A1N(n5325), .B0(n2269), .Y(n2656) ); OAI21X2TS U3847 ( .A0(n2334), .A1(n5326), .B0(n5323), .Y(n2269) ); NOR3X2TS U3848 ( .A(n2899), .B(n4340), .C(n2896), .Y(n2895) ); NAND2X4TS U3849 ( .A(n3262), .B(n4345), .Y(n4893) ); NAND3X6TS U3850 ( .A(n4810), .B(n4809), .C(n4808), .Y(n1256) ); NAND3X4TS U3851 ( .A(n4233), .B(n4232), .C(n4231), .Y(n1522) ); NAND2X4TS U3852 ( .A(n4425), .B(intDX_EWSW[63]), .Y(n4232) ); AOI2BB2X4TS U3853 ( .B0(n4488), .B1(n5044), .A0N(n4709), .A1N(n4521), .Y( n4301) ); OR3X8TS U3854 ( .A(n2270), .B(n2271), .C(n4852), .Y(n1276) ); AND2X4TS U3855 ( .A(n1836), .B(intDX_EWSW[17]), .Y(n2270) ); NAND2X4TS U3856 ( .A(n3428), .B(n3421), .Y(n3430) ); OR2X4TS U3857 ( .A(n3509), .B(n3529), .Y(n2274) ); NAND2X2TS U3858 ( .A(n4369), .B(intDX_EWSW[4]), .Y(n4072) ); NAND2X2TS U3859 ( .A(n4877), .B(intDY_EWSW[24]), .Y(n4832) ); NAND2X4TS U3860 ( .A(n2531), .B(n2025), .Y(n3673) ); BUFX20TS U3861 ( .A(n3087), .Y(n4439) ); NOR2X8TS U3862 ( .A(n3784), .B(n1913), .Y(n3738) ); NAND2X8TS U3863 ( .A(n3737), .B(n3738), .Y(n3765) ); NOR3X4TS U3864 ( .A(n3765), .B(Raw_mant_NRM_SWR[41]), .C(n5029), .Y(n3766) ); AND3X4TS U3865 ( .A(n3779), .B(n2616), .C(n2615), .Y(n2278) ); BUFX20TS U3866 ( .A(n5046), .Y(n6206) ); NAND2X2TS U3867 ( .A(n4863), .B(intDX_EWSW[27]), .Y(n3657) ); NAND2X2TS U3868 ( .A(n1836), .B(intDY_EWSW[56]), .Y(n4236) ); NAND2X2TS U3869 ( .A(n4430), .B(intDY_EWSW[55]), .Y(n4239) ); NAND2X4TS U3870 ( .A(n2526), .B(n2048), .Y(n4420) ); NAND2X4TS U3871 ( .A(n4416), .B(intDX_EWSW[4]), .Y(n4116) ); OR2X4TS U3872 ( .A(n4342), .B(n5427), .Y(n4284) ); NAND4X6TS U3873 ( .A(n3937), .B(n3936), .C(n6193), .D(n3935), .Y(n5016) ); NAND2X2TS U3874 ( .A(n4877), .B(n2740), .Y(n4796) ); NAND2X2TS U3875 ( .A(n4877), .B(intDY_EWSW[29]), .Y(n4799) ); AOI21X4TS U3876 ( .A0(n2289), .A1(n2406), .B0(n3388), .Y(n2279) ); NAND2X2TS U3877 ( .A(n2116), .B(n2961), .Y(n4818) ); NAND3X2TS U3878 ( .A(n2677), .B(n2401), .C(n2735), .Y(n2726) ); NAND2X2TS U3879 ( .A(n4807), .B(intDX_EWSW[58]), .Y(n4358) ); INVX8TS U3880 ( .A(n2934), .Y(n2553) ); BUFX20TS U3881 ( .A(n4431), .Y(n2951) ); NAND3X4TS U3882 ( .A(n3644), .B(n3645), .C(n3643), .Y(n1557) ); OAI21X4TS U3883 ( .A0(n3280), .A1(n2550), .B0(n3279), .Y(n1149) ); NAND2X4TS U3884 ( .A(n3334), .B(intDY_EWSW[33]), .Y(n3519) ); INVX8TS U3885 ( .A(n2507), .Y(n2506) ); NAND2X2TS U3886 ( .A(n4807), .B(intDY_EWSW[37]), .Y(n4821) ); INVX12TS U3887 ( .A(n3219), .Y(n3244) ); NAND2X2TS U3888 ( .A(n4807), .B(intDY_EWSW[20]), .Y(n4847) ); NAND2X2TS U3889 ( .A(n4379), .B(n2940), .Y(n4812) ); NAND2X2TS U3890 ( .A(n4425), .B(intDY_EWSW[30]), .Y(n4793) ); MXI2X2TS U3891 ( .A(n5454), .B(n3350), .S0(n5265), .Y(n1483) ); NOR2X6TS U3892 ( .A(n1848), .B(n5178), .Y(n4586) ); NAND3X6TS U3893 ( .A(n4897), .B(n2423), .C(n2619), .Y(n2620) ); NAND2X8TS U3894 ( .A(n3034), .B(n2980), .Y(n2619) ); INVX8TS U3895 ( .A(n3922), .Y(n2501) ); NAND4X4TS U3896 ( .A(n2416), .B(n2867), .C(n2868), .D(n3767), .Y(n2866) ); NOR3X6TS U3897 ( .A(Raw_mant_NRM_SWR[33]), .B(Raw_mant_NRM_SWR[41]), .C( Raw_mant_NRM_SWR[36]), .Y(n2867) ); NAND2BX4TS U3898 ( .AN(n2447), .B(n4105), .Y(n2966) ); NAND2X4TS U3899 ( .A(n3587), .B(intDX_EWSW[48]), .Y(n4105) ); XOR2X4TS U3900 ( .A(n2905), .B(n4916), .Y(n2904) ); NAND2X4TS U3901 ( .A(n3465), .B(n3498), .Y(n3501) ); AO22X4TS U3902 ( .A0(n4587), .A1(n2763), .B0(final_result_ieee[63]), .B1( n5571), .Y(n1184) ); INVX16TS U3903 ( .A(n2769), .Y(n4600) ); BUFX16TS U3904 ( .A(n6221), .Y(n2528) ); INVX12TS U3905 ( .A(n3047), .Y(n6221) ); OAI21X4TS U3906 ( .A0(n3493), .A1(n3492), .B0(n3491), .Y(n3499) ); NAND2X8TS U3907 ( .A(n2635), .B(n2636), .Y(n2502) ); OAI22X2TS U3908 ( .A0(n5251), .A1(n2453), .B0(n5292), .B1(n5528), .Y(n1091) ); CLKBUFX2TS U3909 ( .A(n5278), .Y(n2763) ); NOR2X4TS U3910 ( .A(n2611), .B(n4324), .Y(n2576) ); BUFX20TS U3911 ( .A(n3832), .Y(n2611) ); NAND4BX4TS U3912 ( .AN(n3836), .B(n3835), .C(n6191), .D(n3834), .Y(n5042) ); NOR2X8TS U3913 ( .A(n3121), .B(n2916), .Y(n3120) ); OAI22X2TS U3914 ( .A0(n1916), .A1(n5260), .B0(n5287), .B1(n5539), .Y(n1082) ); NAND2X4TS U3915 ( .A(n4712), .B(n3372), .Y(n4046) ); NAND2X2TS U3916 ( .A(n5024), .B(n2261), .Y(n2792) ); AND2X4TS U3917 ( .A(n3844), .B(n3843), .Y(n2926) ); NOR2X4TS U3918 ( .A(n3355), .B(intDY_EWSW[14]), .Y(n3432) ); INVX4TS U3919 ( .A(n4331), .Y(n4520) ); NAND2X4TS U3920 ( .A(n3039), .B(n4257), .Y(n3038) ); OR2X4TS U3921 ( .A(n3796), .B(n2038), .Y(n3037) ); NOR2X4TS U3922 ( .A(n3373), .B(DMP_exp_NRM2_EW[4]), .Y(n4005) ); AOI22X2TS U3923 ( .A0(n4722), .A1(n5031), .B0(n4708), .B1(n5036), .Y(n2997) ); OR2X4TS U3924 ( .A(n4520), .B(n3832), .Y(n2996) ); INVX4TS U3925 ( .A(n2330), .Y(n2331) ); NOR2X4TS U3926 ( .A(n3888), .B(DMP_SFG[47]), .Y(n3897) ); NOR2X4TS U3927 ( .A(n3875), .B(DMP_SFG[44]), .Y(n3898) ); NAND2X4TS U3928 ( .A(n3967), .B(n6190), .Y(n2795) ); AND2X4TS U3929 ( .A(n3736), .B(n6216), .Y(n2911) ); NAND2X6TS U3930 ( .A(n4343), .B(n3755), .Y(n3024) ); NAND2X1TS U3931 ( .A(n3364), .B(Raw_mant_NRM_SWR[33]), .Y(n3029) ); INVX4TS U3932 ( .A(n5164), .Y(n4583) ); NAND2X4TS U3933 ( .A(n4707), .B(n4658), .Y(n2791) ); NAND2BX2TS U3934 ( .AN(n4706), .B(Data_array_SWR_3__53_), .Y(n3086) ); NOR2X4TS U3935 ( .A(n3372), .B(n2330), .Y(n4681) ); NOR2X4TS U3936 ( .A(n2582), .B(n2581), .Y(n2580) ); NOR2X4TS U3937 ( .A(n3051), .B(n3050), .Y(n3049) ); NAND2X1TS U3938 ( .A(n4708), .B(n4322), .Y(n3089) ); INVX2TS U3939 ( .A(n5831), .Y(n2694) ); NOR2X4TS U3940 ( .A(n3328), .B(n2310), .Y(n3411) ); NOR2X4TS U3941 ( .A(n3359), .B(n2295), .Y(n3424) ); NAND2X4TS U3942 ( .A(n3324), .B(intDY_EWSW[4]), .Y(n3423) ); NAND2X2TS U3943 ( .A(n3335), .B(intDY_EWSW[55]), .Y(n3557) ); NAND2X2TS U3944 ( .A(n3345), .B(intDY_EWSW[60]), .Y(n3021) ); NOR2X2TS U3945 ( .A(n3310), .B(intDY_EWSW[16]), .Y(n2707) ); NOR2X4TS U3946 ( .A(n3348), .B(intDY_EWSW[24]), .Y(n2768) ); NOR2X4TS U3947 ( .A(n3431), .B(n3447), .Y(n3433) ); INVX4TS U3948 ( .A(n4751), .Y(n2857) ); NAND2X4TS U3949 ( .A(n3403), .B(DMP_SFG[41]), .Y(n3920) ); NAND2X4TS U3950 ( .A(n3889), .B(DMP_SFG[48]), .Y(n4139) ); INVX12TS U3951 ( .A(n3068), .Y(n3218) ); NOR2X4TS U3952 ( .A(Raw_mant_NRM_SWR[32]), .B(Raw_mant_NRM_SWR[31]), .Y( n4251) ); NAND4X4TS U3953 ( .A(n3782), .B(n3742), .C(n4248), .D(n3743), .Y(n2617) ); NAND2X2TS U3954 ( .A(n2605), .B(n4723), .Y(n2604) ); NAND2X2TS U3955 ( .A(n1950), .B(n5021), .Y(n4597) ); NOR2X2TS U3956 ( .A(n3896), .B(n2551), .Y(n2734) ); NAND2X2TS U3957 ( .A(n1635), .B(n1869), .Y(n2614) ); INVX2TS U3958 ( .A(n5083), .Y(n4752) ); INVX6TS U3959 ( .A(n3994), .Y(n3998) ); NOR2X6TS U3960 ( .A(n3130), .B(n3129), .Y(n3131) ); NAND2X6TS U3961 ( .A(n2994), .B(n2929), .Y(n5263) ); NAND2X4TS U3962 ( .A(n2388), .B(n4528), .Y(n2884) ); NOR2X1TS U3963 ( .A(n4752), .B(n4751), .Y(n4741) ); NOR2X1TS U3964 ( .A(n3271), .B(n3226), .Y(n3225) ); NAND2X4TS U3965 ( .A(n3383), .B(DMP_SFG[19]), .Y(n5077) ); INVX2TS U3966 ( .A(n5076), .Y(n5078) ); NAND2X2TS U3967 ( .A(n4952), .B(n3069), .Y(n4938) ); INVX4TS U3968 ( .A(n4288), .Y(n2482) ); NOR2X6TS U3969 ( .A(n4734), .B(n5076), .Y(n5083) ); AND2X4TS U3970 ( .A(n4021), .B(n2663), .Y(n2432) ); INVX2TS U3971 ( .A(n4021), .Y(n2665) ); NAND2X4TS U3972 ( .A(n4987), .B(n4989), .Y(n4992) ); NAND3X2TS U3973 ( .A(n4582), .B(n6293), .C(n4581), .Y(n4584) ); AND3X6TS U3974 ( .A(n2793), .B(n2792), .C(n2791), .Y(n2425) ); NAND2X2TS U3975 ( .A(n5018), .B(n1950), .Y(n2793) ); NAND2X2TS U3976 ( .A(n1950), .B(n5055), .Y(n4593) ); NOR2X6TS U3977 ( .A(n2779), .B(n5298), .Y(n2778) ); MX2X1TS U3978 ( .A(Data_Y[16]), .B(intDY_EWSW[16]), .S0(n5258), .Y(n1712) ); MX2X2TS U3979 ( .A(Data_Y[2]), .B(intDY_EWSW[2]), .S0(n5242), .Y(n1726) ); MX2X1TS U3980 ( .A(Data_Y[25]), .B(n2250), .S0(n5258), .Y(n1703) ); MX2X1TS U3981 ( .A(Data_Y[19]), .B(intDY_EWSW[19]), .S0(n5258), .Y(n1709) ); NOR2X6TS U3982 ( .A(n3312), .B(intDY_EWSW[31]), .Y(n3496) ); NAND2X2TS U3983 ( .A(n3307), .B(intDY_EWSW[30]), .Y(n3495) ); NAND2X4TS U3984 ( .A(n3309), .B(intDY_EWSW[50]), .Y(n3552) ); NAND2X2TS U3985 ( .A(n3333), .B(intDY_EWSW[22]), .Y(n3475) ); NOR2X4TS U3986 ( .A(n3294), .B(intDY_EWSW[44]), .Y(n2863) ); NAND2X2TS U3987 ( .A(n3318), .B(n2292), .Y(n3554) ); NAND2X2TS U3988 ( .A(n3347), .B(intDY_EWSW[61]), .Y(n3020) ); NOR2X4TS U3989 ( .A(n3345), .B(intDY_EWSW[60]), .Y(n2708) ); NOR2X6TS U3990 ( .A(n4931), .B(n2744), .Y(n3393) ); NAND2X1TS U3991 ( .A(n5343), .B(Raw_mant_NRM_SWR[28]), .Y(n3041) ); INVX6TS U3992 ( .A(n4586), .Y(n3126) ); NAND2X4TS U3993 ( .A(n3470), .B(n2706), .Y(n3462) ); NOR2X4TS U3994 ( .A(n3455), .B(n3437), .Y(n3458) ); NAND2X6TS U3995 ( .A(n2613), .B(n2612), .Y(n2609) ); NAND2X2TS U3996 ( .A(n5026), .B(n1919), .Y(n2612) ); INVX6TS U3997 ( .A(n4763), .Y(n3113) ); NOR3X1TS U3998 ( .A(Raw_mant_NRM_SWR[29]), .B(Raw_mant_NRM_SWR[28]), .C( Raw_mant_NRM_SWR[26]), .Y(n4278) ); NOR2X4TS U3999 ( .A(n4892), .B(Raw_mant_NRM_SWR[6]), .Y(n2935) ); INVX2TS U4000 ( .A(n4346), .Y(n2622) ); NOR2X2TS U4001 ( .A(n2611), .B(n4717), .Y(n2633) ); CLKINVX6TS U4002 ( .A(n5042), .Y(n4324) ); XNOR2X1TS U4003 ( .A(intDX_EWSW[53]), .B(n2292), .Y(n4213) ); NOR2X4TS U4004 ( .A(n5982), .B(n5981), .Y(n2838) ); NOR2X4TS U4005 ( .A(n5937), .B(n2158), .Y(n3142) ); INVX4TS U4006 ( .A(n2617), .Y(n3778) ); NOR2X2TS U4007 ( .A(n5166), .B(n3992), .Y(n3122) ); NAND2X2TS U4008 ( .A(n1950), .B(n5014), .Y(n4486) ); NAND2X2TS U4009 ( .A(n2637), .B(n3062), .Y(n3043) ); NOR2X4TS U4010 ( .A(n4698), .B(n5057), .Y(n4673) ); OAI22X2TS U4011 ( .A0(n2611), .A1(n5053), .B0(n2552), .B1(n4661), .Y(n4646) ); NAND2X4TS U4012 ( .A(n5322), .B(n5324), .Y(n5326) ); INVX2TS U4013 ( .A(n5322), .Y(n4784) ); NAND2X6TS U4014 ( .A(n3390), .B(DMP_SFG[25]), .Y(n4779) ); INVX2TS U4015 ( .A(n4944), .Y(n4945) ); INVX2TS U4016 ( .A(n2373), .Y(n3404) ); NAND2X4TS U4017 ( .A(n5001), .B(n2721), .Y(n2720) ); INVX2TS U4018 ( .A(n4686), .Y(n3107) ); INVX2TS U4019 ( .A(n5155), .Y(n3106) ); NAND2X2TS U4020 ( .A(n4769), .B(n4771), .Y(n4774) ); NAND2X6TS U4021 ( .A(n2909), .B(n5516), .Y(n2789) ); NOR2X2TS U4022 ( .A(n2387), .B(DMP_exp_NRM2_EW[8]), .Y(n3997) ); NOR2X2TS U4023 ( .A(n4718), .B(n4534), .Y(n4537) ); INVX2TS U4024 ( .A(n3365), .Y(n2825) ); NAND2X2TS U4025 ( .A(n4721), .B(n5155), .Y(n2881) ); NAND2X2TS U4026 ( .A(n5136), .B(n5147), .Y(n4632) ); NAND2X2TS U4027 ( .A(n4723), .B(n1644), .Y(n2820) ); NOR2X4TS U4028 ( .A(n5049), .B(n4709), .Y(n2818) ); NAND2X2TS U4029 ( .A(n4637), .B(n5018), .Y(n4041) ); MX2X2TS U4030 ( .A(Data_Y[53]), .B(n2292), .S0(n5253), .Y(n1675) ); NAND2X2TS U4031 ( .A(n6201), .B(DmP_mant_SHT1_SW[49]), .Y(n6371) ); NAND2X2TS U4032 ( .A(n5216), .B(n2298), .Y(n2761) ); NAND2X2TS U4033 ( .A(n1873), .B(Raw_mant_NRM_SWR[2]), .Y(n6370) ); NAND3X4TS U4034 ( .A(n2831), .B(n2830), .C(n2369), .Y(n1144) ); OAI21X2TS U4035 ( .A0(n2362), .A1(n4925), .B0(n4924), .Y(n4929) ); MX2X1TS U4036 ( .A(DmP_mant_SHT1_SW[29]), .B(DmP_EXP_EWSW[29]), .S0(n5204), .Y(n1251) ); INVX2TS U4037 ( .A(n3158), .Y(n5260) ); OAI21X2TS U4038 ( .A0(n5063), .A1(n5216), .B0(n3135), .Y(n1023) ); INVX2TS U4039 ( .A(n5551), .Y(n3136) ); NAND2X2TS U4040 ( .A(n1838), .B(intDX_EWSW[52]), .Y(n4454) ); NAND2X1TS U4041 ( .A(n2550), .B(n2032), .Y(n3274) ); NAND2X1TS U4042 ( .A(n5191), .B(DmP_mant_SFG_SWR[31]), .Y(n3155) ); OAI2BB2X2TS U4043 ( .B0(n2527), .B1(n5420), .A0N(n5045), .A1N(n6230), .Y( n6208) ); INVX3TS U4044 ( .A(rst), .Y(n6465) ); NAND2X2TS U4045 ( .A(n2690), .B(n4671), .Y(n6451) ); NAND2X2TS U4046 ( .A(n3234), .B(Raw_mant_NRM_SWR[10]), .Y(n6387) ); AOI2BB2X2TS U4047 ( .B0(n2306), .B1(n5029), .A0N(n4653), .A1N(n6231), .Y( n6377) ); NAND2X2TS U4048 ( .A(n3234), .B(Raw_mant_NRM_SWR[27]), .Y(n6313) ); NAND2X2TS U4049 ( .A(n3234), .B(Raw_mant_NRM_SWR[25]), .Y(n6316) ); NAND2X2TS U4050 ( .A(n2690), .B(n4506), .Y(n6454) ); MX2X1TS U4051 ( .A(DmP_mant_SHT1_SW[34]), .B(DmP_EXP_EWSW[34]), .S0(n5204), .Y(n1241) ); AOI22X1TS U4052 ( .A0(n4506), .A1(n4542), .B0(DmP_mant_SFG_SWR[16]), .B1( n5218), .Y(n4507) ); OAI21X2TS U4053 ( .A0(n3204), .A1(n5005), .B0(n3203), .Y(n1163) ); NAND2X1TS U4054 ( .A(n2384), .B(LZD_output_NRM2_EW[0]), .Y(n2987) ); MX2X1TS U4055 ( .A(Data_X[11]), .B(intDX_EWSW[11]), .S0(n5241), .Y(n1783) ); MX2X1TS U4056 ( .A(Data_Y[61]), .B(intDY_EWSW[61]), .S0(n5252), .Y(n1667) ); MX2X1TS U4057 ( .A(Data_Y[57]), .B(intDY_EWSW[57]), .S0(n5252), .Y(n1671) ); MX2X1TS U4058 ( .A(Data_Y[49]), .B(intDY_EWSW[49]), .S0(n5253), .Y(n1679) ); MX2X1TS U4059 ( .A(Data_Y[17]), .B(intDY_EWSW[17]), .S0(n5258), .Y(n1711) ); NAND3X6TS U4060 ( .A(n2661), .B(n2660), .C(n2658), .Y(n2666) ); INVX2TS U4061 ( .A(n5319), .Y(n2318) ); INVX2TS U4062 ( .A(DmP_mant_SHT1_SW[47]), .Y(n5602) ); INVX2TS U4063 ( .A(DmP_mant_SHT1_SW[50]), .Y(n5599) ); INVX2TS U4064 ( .A(DmP_mant_SHT1_SW[22]), .Y(n5577) ); INVX2TS U4065 ( .A(DmP_mant_SHT1_SW[24]), .Y(n5604) ); INVX2TS U4066 ( .A(DmP_mant_SHT1_SW[10]), .Y(n5585) ); INVX2TS U4067 ( .A(DmP_mant_SHT1_SW[38]), .Y(n5592) ); INVX2TS U4068 ( .A(DmP_mant_SHT1_SW[40]), .Y(n5613) ); INVX2TS U4069 ( .A(DmP_mant_SHT1_SW[31]), .Y(n5609) ); INVX2TS U4070 ( .A(DmP_mant_SHT1_SW[48]), .Y(n5589) ); INVX2TS U4071 ( .A(DmP_mant_SHT1_SW[46]), .Y(n5605) ); INVX2TS U4072 ( .A(DmP_mant_SHT1_SW[17]), .Y(n5593) ); INVX2TS U4073 ( .A(DmP_mant_SHT1_SW[18]), .Y(n5615) ); INVX2TS U4074 ( .A(DmP_mant_SHT1_SW[23]), .Y(n5606) ); INVX2TS U4075 ( .A(DmP_mant_SHT1_SW[19]), .Y(n5598) ); INVX2TS U4076 ( .A(DmP_mant_SHT1_SW[25]), .Y(n5590) ); INVX2TS U4077 ( .A(DmP_mant_SHT1_SW[36]), .Y(n5608) ); INVX2TS U4078 ( .A(DmP_mant_SHT1_SW[32]), .Y(n5584) ); INVX2TS U4079 ( .A(DmP_mant_SHT1_SW[45]), .Y(n5414) ); INVX2TS U4080 ( .A(DmP_mant_SHT1_SW[9]), .Y(n5594) ); INVX2TS U4081 ( .A(DmP_mant_SHT1_SW[49]), .Y(n5578) ); INVX2TS U4082 ( .A(DmP_mant_SHT1_SW[41]), .Y(n5582) ); INVX2TS U4083 ( .A(DmP_mant_SHT1_SW[21]), .Y(n5611) ); INVX2TS U4084 ( .A(DmP_mant_SHT1_SW[39]), .Y(n5583) ); INVX2TS U4085 ( .A(DmP_mant_SHT1_SW[3]), .Y(n5575) ); INVX2TS U4086 ( .A(DmP_mant_SHT1_SW[6]), .Y(n5597) ); INVX2TS U4087 ( .A(DmP_mant_SHT1_SW[14]), .Y(n5586) ); INVX2TS U4088 ( .A(DmP_mant_SHT1_SW[12]), .Y(n5587) ); INVX2TS U4089 ( .A(DmP_mant_SHT1_SW[16]), .Y(n5600) ); AOI2BB2X2TS U4090 ( .B0(n6205), .B1(Raw_mant_NRM_SWR[33]), .A0N(n4715), .A1N(n4332), .Y(n6391) ); NAND2X2TS U4091 ( .A(n3234), .B(Raw_mant_NRM_SWR[18]), .Y(n6304) ); NAND2X2TS U4092 ( .A(n5184), .B(n4506), .Y(n6423) ); OAI22X2TS U4093 ( .A0(n1916), .A1(n4145), .B0(n5289), .B1(n5543), .Y(n1079) ); INVX2TS U4094 ( .A(n2537), .Y(n2521) ); BUFX3TS U4095 ( .A(n6292), .Y(n6234) ); CLKINVX3TS U4096 ( .A(rst), .Y(n2520) ); NAND2X4TS U4097 ( .A(n3260), .B(n3259), .Y(n6210) ); NAND2X1TS U4098 ( .A(n2873), .B(n4333), .Y(n3259) ); INVX2TS U4099 ( .A(DmP_mant_SHT1_SW[33]), .Y(n5614) ); NAND2X2TS U4100 ( .A(n6228), .B(n4049), .Y(n2946) ); NAND2X2TS U4101 ( .A(n3234), .B(Raw_mant_NRM_SWR[30]), .Y(n6300) ); NOR2X2TS U4102 ( .A(n4026), .B(n2974), .Y(n2973) ); CLKINVX3TS U4103 ( .A(rst), .Y(n2533) ); BUFX3TS U4104 ( .A(n6289), .Y(n6257) ); NAND2X1TS U4105 ( .A(n4417), .B(DmP_EXP_EWSW[41]), .Y(n3689) ); NAND2X1TS U4106 ( .A(n4417), .B(DmP_EXP_EWSW[39]), .Y(n3686) ); NAND2X2TS U4107 ( .A(n2116), .B(intDY_EWSW[39]), .Y(n3687) ); NAND2X1TS U4108 ( .A(n4864), .B(DmP_EXP_EWSW[38]), .Y(n4099) ); NAND2X2TS U4109 ( .A(n3630), .B(intDX_EWSW[33]), .Y(n4803) ); NAND2X2TS U4110 ( .A(n2531), .B(intDX_EWSW[32]), .Y(n4806) ); NAND2X2TS U4111 ( .A(n1838), .B(intDX_EWSW[30]), .Y(n4794) ); CLKBUFX3TS U4112 ( .A(n6292), .Y(n6232) ); NAND2X1TS U4113 ( .A(n4853), .B(DmP_EXP_EWSW[25]), .Y(n4854) ); NAND2X2TS U4114 ( .A(n4424), .B(intDX_EWSW[25]), .Y(n4856) ); NAND2X2TS U4115 ( .A(n3630), .B(intDX_EWSW[23]), .Y(n4830) ); NAND2X1TS U4116 ( .A(n4417), .B(DmP_EXP_EWSW[15]), .Y(n4106) ); NAND2X2TS U4117 ( .A(n4412), .B(n2035), .Y(n4107) ); NAND2X1TS U4118 ( .A(n4864), .B(DmP_EXP_EWSW[4]), .Y(n4114) ); NAND2X2TS U4119 ( .A(n4873), .B(intDY_EWSW[2]), .Y(n4374) ); CLKINVX3TS U4120 ( .A(n2537), .Y(n2545) ); BUFX3TS U4121 ( .A(n6233), .Y(n6253) ); MXI2X1TS U4122 ( .A(n4728), .B(SIGN_FLAG_EXP), .S0(n2524), .Y(n4231) ); NAND2X1TS U4123 ( .A(n2525), .B(DMP_EXP_EWSW[62]), .Y(n3659) ); INVX2TS U4124 ( .A(rst), .Y(n2544) ); NAND2X1TS U4125 ( .A(n3652), .B(DMP_EXP_EWSW[39]), .Y(n3618) ); NAND2X1TS U4126 ( .A(n3652), .B(DMP_EXP_EWSW[37]), .Y(n3631) ); NAND2X1TS U4127 ( .A(n3652), .B(DMP_EXP_EWSW[36]), .Y(n3621) ); NAND2X1TS U4128 ( .A(n3652), .B(DMP_EXP_EWSW[35]), .Y(n3624) ); NAND2X1TS U4129 ( .A(n3652), .B(DMP_EXP_EWSW[33]), .Y(n3627) ); NAND2X1TS U4130 ( .A(n3652), .B(DMP_EXP_EWSW[32]), .Y(n3646) ); NAND2X1TS U4131 ( .A(n3652), .B(DMP_EXP_EWSW[31]), .Y(n3653) ); NAND2X1TS U4132 ( .A(n4426), .B(DMP_EXP_EWSW[28]), .Y(n3640) ); NAND2X1TS U4133 ( .A(n4426), .B(DMP_EXP_EWSW[27]), .Y(n3656) ); NAND2X1TS U4134 ( .A(n4426), .B(DMP_EXP_EWSW[26]), .Y(n4421) ); NAND2X1TS U4135 ( .A(n4426), .B(DMP_EXP_EWSW[25]), .Y(n4427) ); NAND2X1TS U4136 ( .A(n4426), .B(DMP_EXP_EWSW[22]), .Y(n3637) ); NAND2X1TS U4137 ( .A(n4426), .B(n2255), .Y(n3634) ); NAND2X1TS U4138 ( .A(n2525), .B(n2259), .Y(n3680) ); NAND2X2TS U4139 ( .A(n2049), .B(intDX_EWSW[19]), .Y(n3681) ); NAND2X1TS U4140 ( .A(n4417), .B(DMP_EXP_EWSW[10]), .Y(n4418) ); NAND2X1TS U4141 ( .A(n4417), .B(DMP_EXP_EWSW[9]), .Y(n4409) ); NAND2X1TS U4142 ( .A(n4834), .B(DMP_EXP_EWSW[7]), .Y(n4074) ); NAND2X2TS U4143 ( .A(n3124), .B(intDY_EWSW[6]), .Y(n4445) ); NAND2X2TS U4144 ( .A(n2526), .B(n2737), .Y(n4434) ); BUFX3TS U4145 ( .A(n6289), .Y(n6236) ); MX2X4TS U4146 ( .A(n3409), .B(n2570), .S0(n2547), .Y(n1599) ); NAND2X1TS U4147 ( .A(n6230), .B(Data_array_SWR_3__53_), .Y(n4436) ); MX2X1TS U4148 ( .A(Data_Y[42]), .B(n1815), .S0(n5235), .Y(n1686) ); MX2X1TS U4149 ( .A(Data_Y[32]), .B(n2957), .S0(n5236), .Y(n1696) ); NAND2X8TS U4150 ( .A(n2736), .B(n3007), .Y(n3006) ); XOR2X4TS U4151 ( .A(n2493), .B(n2293), .Y(n2909) ); XNOR2X4TS U4152 ( .A(n2294), .B(DmP_mant_SFG_SWR[22]), .Y(n3384) ); NOR2X6TS U4153 ( .A(n5040), .B(n2855), .Y(n3236) ); AOI22X2TS U4154 ( .A0(n6206), .A1(Raw_mant_NRM_SWR[15]), .B0(n1917), .B1( n6228), .Y(n6342) ); NAND4BX4TS U4155 ( .AN(n3715), .B(n3714), .C(n6140), .D(n6139), .Y(n2296) ); CLKMX2X3TS U4156 ( .A(Data_Y[5]), .B(n2295), .S0(n5242), .Y(n1723) ); NAND2X2TS U4157 ( .A(n1837), .B(intDX_EWSW[15]), .Y(n3666) ); NAND2X2TS U4158 ( .A(n4807), .B(n2048), .Y(n4314) ); NAND2X4TS U4159 ( .A(n3677), .B(n3679), .Y(n2304) ); INVX4TS U4160 ( .A(n2304), .Y(n2305) ); NAND2X4TS U4161 ( .A(n4416), .B(intDY_EWSW[61]), .Y(n3679) ); NAND2X2TS U4162 ( .A(n4863), .B(intDX_EWSW[16]), .Y(n3663) ); NAND2X2TS U4163 ( .A(n4369), .B(intDX_EWSW[22]), .Y(n3638) ); INVX12TS U4164 ( .A(n2853), .Y(n3235) ); NAND2X4TS U4165 ( .A(n4610), .B(n4611), .Y(n4616) ); NAND2X2TS U4166 ( .A(n5140), .B(n2516), .Y(n4611) ); INVX12TS U4167 ( .A(n5046), .Y(n6214) ); OA21X4TS U4168 ( .A0(n2011), .A1(n2465), .B0(n3981), .Y(n2309) ); AOI22X2TS U4169 ( .A0(n6205), .A1(Raw_mant_NRM_SWR[26]), .B0(n5023), .B1( n5041), .Y(n6312) ); XNOR2X4TS U4170 ( .A(n4010), .B(n2311), .Y(n5178) ); AND2X4TS U4171 ( .A(n2262), .B(n5025), .Y(n3150) ); OAI21X2TS U4172 ( .A0(n5291), .A1(n5216), .B0(n2841), .Y(n1019) ); AOI22X2TS U4173 ( .A0(n6219), .A1(Raw_mant_NRM_SWR[0]), .B0(n2296), .B1( n6228), .Y(n6368) ); AND2X4TS U4174 ( .A(n4474), .B(n2296), .Y(n2430) ); NAND2X2TS U4175 ( .A(n4838), .B(intDY_EWSW[54]), .Y(n4447) ); NAND3X2TS U4176 ( .A(n4825), .B(n4824), .C(n4823), .Y(n1254) ); BUFX12TS U4177 ( .A(n2985), .Y(n2648) ); NAND2X2TS U4178 ( .A(n6219), .B(Raw_mant_NRM_SWR[5]), .Y(n6345) ); MXI2X2TS U4179 ( .A(n5266), .B(n5518), .S0(n2554), .Y(n1041) ); BUFX20TS U4180 ( .A(n2502), .Y(n2990) ); NAND2X4TS U4181 ( .A(n3294), .B(intDY_EWSW[44]), .Y(n3539) ); NAND4X4TS U4182 ( .A(n2314), .B(n2315), .C(n3167), .D(n3285), .Y(n1148) ); OA21X4TS U4183 ( .A0(n3170), .A1(n3286), .B0(n3288), .Y(n2315) ); NAND2X2TS U4184 ( .A(n6218), .B(Raw_mant_NRM_SWR[40]), .Y(n6376) ); INVX6TS U4185 ( .A(n4766), .Y(n4771) ); NAND3X6TS U4186 ( .A(n4257), .B(n3299), .C(Raw_mant_NRM_SWR[27]), .Y(n4279) ); AND2X4TS U4187 ( .A(n3272), .B(n4912), .Y(n2316) ); NOR2X8TS U4188 ( .A(n2316), .B(n4911), .Y(n4913) ); OAI22X2TS U4189 ( .A0(n2453), .A1(n4652), .B0(n5292), .B1(n5530), .Y(n1086) ); BUFX20TS U4190 ( .A(n5046), .Y(n2982) ); AOI22X4TS U4191 ( .A0(n2516), .A1(n5136), .B0(n2022), .B1(n5145), .Y(n6463) ); AND4X8TS U4192 ( .A(n3216), .B(n3212), .C(n3215), .D(n2386), .Y(n2317) ); MXI2X4TS U4193 ( .A(n6207), .B(n2347), .S0(n2318), .Y(n1158) ); NAND3X4TS U4194 ( .A(n2615), .B(n1989), .C(n2616), .Y(n2319) ); BUFX12TS U4195 ( .A(n3804), .Y(n4637) ); INVX1TS U4196 ( .A(n3149), .Y(n5321) ); AOI21X2TS U4197 ( .A0(n4901), .A1(n4900), .B0(n4899), .Y(n4903) ); NOR2X4TS U4198 ( .A(n4026), .B(n5415), .Y(n2972) ); INVX16TS U4199 ( .A(n4026), .Y(n6199) ); NOR3X6TS U4200 ( .A(n4027), .B(n4254), .C(n3026), .Y(n3025) ); INVX12TS U4201 ( .A(n2317), .Y(n4990) ); BUFX12TS U4202 ( .A(n5032), .Y(n6224) ); BUFX12TS U4203 ( .A(n5032), .Y(n2564) ); BUFX12TS U4204 ( .A(n5032), .Y(n2499) ); NOR2X4TS U4205 ( .A(Raw_mant_NRM_SWR[36]), .B(Raw_mant_NRM_SWR[43]), .Y( n3252) ); NOR2X4TS U4206 ( .A(Raw_mant_NRM_SWR[43]), .B(Raw_mant_NRM_SWR[42]), .Y( n3727) ); NOR2X4TS U4207 ( .A(Raw_mant_NRM_SWR[43]), .B(Raw_mant_NRM_SWR[46]), .Y( n3737) ); OAI2BB1X4TS U4208 ( .A0N(n2906), .A1N(n2321), .B0(n4947), .Y(n4951) ); XOR2X4TS U4209 ( .A(n2322), .B(n2363), .Y(n2908) ); AOI21X4TS U4210 ( .A0(n2677), .A1(n2339), .B0(n2340), .Y(n2322) ); AOI21X2TS U4211 ( .A0(n4990), .A1(n4923), .B0(n4922), .Y(n4924) ); NAND2X4TS U4212 ( .A(n2278), .B(n3190), .Y(n3189) ); AND3X6TS U4213 ( .A(n2942), .B(n3732), .C(n3733), .Y(n3734) ); AOI2BB2X4TS U4214 ( .B0(n2497), .B1(DmP_mant_SHT1_SW[32]), .A0N(n5341), .A1N(n2527), .Y(n6344) ); NAND2X4TS U4215 ( .A(n2648), .B(n2987), .Y(n1138) ); NAND4X6TS U4216 ( .A(n3213), .B(n2952), .C(n3275), .D(n3218), .Y(n3212) ); BUFX16TS U4217 ( .A(n3833), .Y(n4709) ); MXI2X4TS U4218 ( .A(n2328), .B(n2327), .S0(n5319), .Y(n1157) ); XOR2X4TS U4219 ( .A(n4996), .B(n2359), .Y(n2347) ); OAI2BB1X4TS U4220 ( .A0N(n3272), .A1N(n4935), .B0(n2326), .Y(n2368) ); AND2X8TS U4221 ( .A(n4933), .B(n2717), .Y(n2326) ); NAND2X4TS U4222 ( .A(n5037), .B(n2555), .Y(n2613) ); NOR2X4TS U4223 ( .A(n3402), .B(DMP_SFG[40]), .Y(n3919) ); XNOR2X4TS U4224 ( .A(n4976), .B(n2361), .Y(n2328) ); AND3X8TS U4225 ( .A(n2423), .B(n4897), .C(n2619), .Y(n2329) ); NOR2X6TS U4226 ( .A(n3511), .B(n3556), .Y(n2683) ); NAND2X6TS U4227 ( .A(n3266), .B(n2664), .Y(n2661) ); INVX16TS U4228 ( .A(n2342), .Y(n3266) ); INVX16TS U4229 ( .A(n3261), .Y(n6212) ); XOR2X4TS U4230 ( .A(n2333), .B(n2258), .Y(n5281) ); INVX16TS U4231 ( .A(n2712), .Y(n3175) ); NAND3X8TS U4232 ( .A(n2787), .B(n2788), .C(n3222), .Y(n2712) ); NAND2X4TS U4233 ( .A(n3767), .B(n5422), .Y(n2747) ); NOR2X4TS U4234 ( .A(n2368), .B(n2715), .Y(n4953) ); NAND2X4TS U4235 ( .A(n2711), .B(n4930), .Y(n2717) ); NAND2XLTS U4236 ( .A(n5089), .B(n2323), .Y(n3278) ); CLKBUFX2TS U4237 ( .A(n4780), .Y(n2959) ); NAND2X4TS U4238 ( .A(n2426), .B(n2677), .Y(n2721) ); AND2X8TS U4239 ( .A(n2915), .B(n3257), .Y(n2334) ); MXI2X2TS U4240 ( .A(n2335), .B(n5573), .S0(n5319), .Y(n1166) ); XNOR2X4TS U4241 ( .A(n4967), .B(n4966), .Y(n2335) ); XOR2X4TS U4242 ( .A(n4956), .B(n2337), .Y(n4957) ); NOR2X4TS U4243 ( .A(Raw_mant_NRM_SWR[46]), .B(Raw_mant_NRM_SWR[41]), .Y( n3728) ); NOR2X6TS U4244 ( .A(n1913), .B(Raw_mant_NRM_SWR[46]), .Y(n3785) ); NAND3X2TS U4245 ( .A(n3757), .B(n1913), .C(n5425), .Y(n3741) ); XNOR2X4TS U4246 ( .A(n2720), .B(n2338), .Y(n2719) ); AO21X1TS U4247 ( .A0(n3404), .A1(n2389), .B0(n3872), .Y(n2340) ); CLKBUFX2TS U4248 ( .A(n5064), .Y(n2767) ); NAND2X8TS U4249 ( .A(n2404), .B(n5281), .Y(n3270) ); INVX6TS U4250 ( .A(n2345), .Y(n2346) ); NAND2X4TS U4251 ( .A(n2346), .B(n3252), .Y(n3251) ); MXI2X2TS U4252 ( .A(n2348), .B(n3371), .S0(n5205), .Y(n1160) ); XNOR2X4TS U4253 ( .A(n4919), .B(n2364), .Y(n2348) ); XNOR2X4TS U4254 ( .A(n4786), .B(n2355), .Y(n2349) ); MXI2X4TS U4255 ( .A(n5432), .B(n2350), .S0(n3232), .Y(n1171) ); XNOR2X4TS U4256 ( .A(n4778), .B(n2360), .Y(n2350) ); NAND2X4TS U4257 ( .A(n4250), .B(n5432), .Y(n3747) ); AOI2BB2X2TS U4258 ( .B0(n6203), .B1(DmP_mant_SHT1_SW[22]), .A0N(n5445), .A1N(n2527), .Y(n6307) ); MXI2X4TS U4259 ( .A(n5569), .B(n2351), .S0(n3232), .Y(n1165) ); XNOR2X4TS U4260 ( .A(n4986), .B(n2356), .Y(n2351) ); XNOR2X4TS U4261 ( .A(n2677), .B(n2352), .Y(n3276) ); MXI2X2TS U4262 ( .A(n5492), .B(n2353), .S0(n3232), .Y(n1170) ); XNOR2X4TS U4263 ( .A(n4768), .B(n2365), .Y(n2353) ); MXI2X4TS U4264 ( .A(n5431), .B(n2354), .S0(n3287), .Y(n1172) ); XNOR2X4TS U4265 ( .A(n4750), .B(n2366), .Y(n2354) ); MXI2X4TS U4266 ( .A(n5343), .B(n2357), .S0(n3287), .Y(n1169) ); XOR2X4TS U4267 ( .A(n4777), .B(n4776), .Y(n2357) ); XNOR2X4TS U4268 ( .A(n3899), .B(n2367), .Y(n2955) ); INVX16TS U4269 ( .A(n3175), .Y(n2677) ); AOI21X2TS U4270 ( .A0(n3245), .A1(n4741), .B0(n4740), .Y(n4744) ); AOI21X2TS U4271 ( .A0(n3245), .A1(n4758), .B0(n4757), .Y(n4761) ); MX2X6TS U4272 ( .A(OP_FLAG_SHT2), .B(n2489), .S0(n2764), .Y(n6147) ); NAND2X4TS U4273 ( .A(n2401), .B(n2342), .Y(n2730) ); OR2X2TS U4274 ( .A(n3878), .B(n3231), .Y(n2370) ); INVX2TS U4275 ( .A(n4241), .Y(n4242) ); INVX12TS U4276 ( .A(n4062), .Y(n4711) ); INVX2TS U4277 ( .A(n2917), .Y(n2723) ); OR2X2TS U4278 ( .A(n4026), .B(n2969), .Y(n2375) ); INVX6TS U4279 ( .A(n2992), .Y(n2989) ); AND2X8TS U4280 ( .A(n3298), .B(n5440), .Y(n2378) ); NAND2X1TS U4281 ( .A(n2551), .B(Raw_mant_NRM_SWR[50]), .Y(n3288) ); AND2X2TS U4282 ( .A(n5271), .B(DmP_mant_SFG_SWR[39]), .Y(n2385) ); OA21X2TS U4283 ( .A0(n4948), .A1(n4944), .B0(n4949), .Y(n2386) ); OR2X2TS U4284 ( .A(n4718), .B(n4520), .Y(n2388) ); AND2X2TS U4285 ( .A(n4637), .B(Data_array_SWR_3__53_), .Y(n2391) ); AND2X2TS U4286 ( .A(n2780), .B(n5026), .Y(n2396) ); INVX8TS U4287 ( .A(n3207), .Y(n3275) ); INVX12TS U4288 ( .A(n1906), .Y(n6225) ); INVX12TS U4289 ( .A(n1906), .Y(n6226) ); NAND2X2TS U4290 ( .A(n4608), .B(n5147), .Y(n2400) ); OR2X8TS U4291 ( .A(n3378), .B(DMP_SFG[13]), .Y(n2404) ); INVX8TS U4292 ( .A(n5097), .Y(n5065) ); NAND2X4TS U4293 ( .A(n2840), .B(n5478), .Y(n2405) ); AND3X8TS U4294 ( .A(n2857), .B(n3297), .C(n3295), .Y(n2406) ); AND4X4TS U4295 ( .A(n2901), .B(n2900), .C(n2895), .D(n4339), .Y(n2417) ); AND2X8TS U4296 ( .A(n3941), .B(n3943), .Y(n2418) ); INVX8TS U4297 ( .A(n2611), .Y(n4723) ); AND2X4TS U4298 ( .A(n5135), .B(n4685), .Y(n2419) ); AND2X8TS U4299 ( .A(n3078), .B(n3077), .Y(n2420) ); AND2X8TS U4300 ( .A(n2501), .B(DmP_mant_SHT1_SW[12]), .Y(n2421) ); AND2X4TS U4301 ( .A(n3218), .B(n3396), .Y(n2422) ); INVX2TS U4302 ( .A(n3878), .Y(n3271) ); NAND2X4TS U4303 ( .A(n3910), .B(n3882), .Y(n3878) ); AND2X2TS U4304 ( .A(n4998), .B(n5000), .Y(n2426) ); AND2X4TS U4305 ( .A(n4281), .B(n4274), .Y(n2429) ); INVX2TS U4306 ( .A(n4930), .Y(n4934) ); NOR2X4TS U4307 ( .A(n2760), .B(n4965), .Y(n4930) ); AND2X2TS U4308 ( .A(n4136), .B(n4135), .Y(n2431) ); NAND2X2TS U4309 ( .A(n2261), .B(n5051), .Y(n2433) ); OR2X8TS U4310 ( .A(n2649), .B(n2382), .Y(n2435) ); OR2X2TS U4311 ( .A(n3833), .B(n6410), .Y(n2437) ); INVX2TS U4312 ( .A(n1871), .Y(n2826) ); AND2X4TS U4313 ( .A(n3175), .B(n2678), .Y(n2440) ); NAND2X4TS U4314 ( .A(n6216), .B(n6207), .Y(n3253) ); INVX2TS U4315 ( .A(n3032), .Y(n5298) ); OR2X2TS U4316 ( .A(n3331), .B(DMP_EXP_EWSW[53]), .Y(n2443) ); AND2X2TS U4317 ( .A(n2550), .B(Raw_mant_NRM_SWR[48]), .Y(n2448) ); INVX2TS U4318 ( .A(n2673), .Y(n3166) ); INVX2TS U4319 ( .A(DmP_mant_SHT1_SW[11]), .Y(n2971) ); INVX6TS U4320 ( .A(n5428), .Y(n3784) ); INVX2TS U4321 ( .A(DmP_mant_SHT1_SW[13]), .Y(n2974) ); INVX2TS U4322 ( .A(DmP_mant_SHT1_SW[20]), .Y(n2969) ); INVX2TS U4323 ( .A(DmP_mant_SHT1_SW[27]), .Y(n2976) ); INVX2TS U4324 ( .A(n2537), .Y(n2540) ); CLKINVX3TS U4325 ( .A(rst), .Y(n2512) ); CLKBUFX3TS U4326 ( .A(n6289), .Y(n6258) ); INVX3TS U4327 ( .A(rst), .Y(n2514) ); CLKBUFX2TS U4328 ( .A(n4465), .Y(n6240) ); INVX2TS U4329 ( .A(rst), .Y(n2542) ); INVX2TS U4330 ( .A(rst), .Y(n2541) ); BUFX3TS U4331 ( .A(n6289), .Y(n6256) ); INVX2TS U4332 ( .A(rst), .Y(n2543) ); INVX2TS U4333 ( .A(n2537), .Y(n2511) ); BUFX20TS U4334 ( .A(n4838), .Y(n2452) ); OAI21X4TS U4335 ( .A0(n2989), .A1(n2088), .B0(n2991), .Y(n1059) ); AOI21X4TS U4336 ( .A0(n2457), .A1(n3470), .B0(n2454), .Y(n3482) ); OAI22X4TS U4337 ( .A0(n2467), .A1(n2458), .B0(intDX_EWSW[17]), .B1(n2442), .Y(n2457) ); NOR2X8TS U4338 ( .A(n3341), .B(intDY_EWSW[17]), .Y(n2467) ); NOR2X8TS U4339 ( .A(n3248), .B(n2491), .Y(n4027) ); NAND2X8TS U4340 ( .A(n2460), .B(n2459), .Y(n5262) ); OAI21X4TS U4341 ( .A0(n2465), .A1(n3980), .B0(n3981), .Y(n3989) ); XOR2X4TS U4342 ( .A(n3983), .B(n1824), .Y(n5176) ); NOR2X8TS U4343 ( .A(n3321), .B(DMP_exp_NRM2_EW[0]), .Y(n2465) ); NAND2X8TS U4344 ( .A(n2466), .B(n2397), .Y(n2787) ); NOR2X8TS U4345 ( .A(n2707), .B(n2052), .Y(n2706) ); AND2X8TS U4346 ( .A(n2486), .B(intDX_EWSW[13]), .Y(n3447) ); XOR2X4TS U4347 ( .A(DmP_mant_SFG_SWR[26]), .B(n1839), .Y(n2652) ); NAND2X8TS U4348 ( .A(n2468), .B(n1914), .Y(n2651) ); INVX8TS U4349 ( .A(n4746), .Y(n2468) ); OR2X8TS U4350 ( .A(n2650), .B(n5465), .Y(n4746) ); NOR2X8TS U4351 ( .A(n2469), .B(n2850), .Y(n3243) ); NAND2X4TS U4352 ( .A(n2851), .B(n2849), .Y(n2469) ); AND2X8TS U4353 ( .A(n2891), .B(n3367), .Y(n2849) ); AND2X8TS U4354 ( .A(n2471), .B(n4632), .Y(n5256) ); NAND2X4TS U4355 ( .A(n3314), .B(intDY_EWSW[52]), .Y(n3555) ); NOR2X6TS U4356 ( .A(n3311), .B(n2479), .Y(n3473) ); NAND2XLTS U4357 ( .A(n3370), .B(n5069), .Y(n5070) ); XNOR2X2TS U4358 ( .A(n3245), .B(n4735), .Y(n4736) ); NAND2X2TS U4359 ( .A(n6215), .B(n6455), .Y(n6421) ); NAND2X2TS U4360 ( .A(n6215), .B(n6437), .Y(n6436) ); NAND2X2TS U4361 ( .A(n6215), .B(n6441), .Y(n6432) ); NAND2X2TS U4362 ( .A(n6215), .B(n6459), .Y(n6417) ); NAND2X2TS U4363 ( .A(n6215), .B(n6449), .Y(n6425) ); NAND2X2TS U4364 ( .A(n6215), .B(n6457), .Y(n6419) ); NAND2X2TS U4365 ( .A(n2116), .B(n2479), .Y(n4861) ); NOR2BX4TS U4366 ( .AN(n3172), .B(n2473), .Y(n2678) ); XOR2X4TS U4367 ( .A(n3210), .B(n2434), .Y(n3209) ); NAND3X4TS U4368 ( .A(n3244), .B(n3243), .C(n4249), .Y(n2474) ); NAND2X2TS U4369 ( .A(n2690), .B(n5182), .Y(n6448) ); NAND2X4TS U4370 ( .A(n2558), .B(n5262), .Y(n3943) ); BUFX20TS U4371 ( .A(n3125), .Y(n3587) ); NAND2X4TS U4372 ( .A(n3262), .B(n2621), .Y(n2476) ); AND2X8TS U4373 ( .A(intDX_EWSW[11]), .B(n2477), .Y(n3441) ); OAI22X2TS U4374 ( .A0(n2990), .A1(n5246), .B0(n5289), .B1(n5535), .Y(n1089) ); OAI21X1TS U4375 ( .A0(n3248), .A1(n4278), .B0(n4351), .Y(n4283) ); INVX12TS U4376 ( .A(n5046), .Y(n2527) ); NAND2X4TS U4377 ( .A(n3351), .B(intDY_EWSW[38]), .Y(n3527) ); NOR2X8TS U4378 ( .A(n3351), .B(intDY_EWSW[38]), .Y(n3506) ); BUFX20TS U4379 ( .A(n3125), .Y(n4430) ); NAND3X4TS U4380 ( .A(n4284), .B(n4255), .C(n4256), .Y(n4263) ); NAND2X2TS U4381 ( .A(n4884), .B(n4253), .Y(n4256) ); INVX16TS U4382 ( .A(n2847), .Y(n3233) ); NOR2X4TS U4383 ( .A(n4349), .B(n4348), .Y(n3757) ); NAND2X8TS U4384 ( .A(n2482), .B(n2483), .Y(n2484) ); NAND2X8TS U4385 ( .A(n2484), .B(n2563), .Y(n4869) ); OAI22X2TS U4386 ( .A0(n2990), .A1(n5254), .B0(n5289), .B1(n5534), .Y(n1099) ); NAND2X2TS U4387 ( .A(n2262), .B(n5055), .Y(n3723) ); NOR2X4TS U4388 ( .A(n3507), .B(n3520), .Y(n3508) ); XNOR2X1TS U4389 ( .A(n3362), .B(n2485), .Y(n4217) ); AOI21X4TS U4390 ( .A0(n4055), .A1(n1871), .B0(n4054), .Y(n4056) ); AOI21X2TS U4391 ( .A0(n3245), .A1(n5083), .B0(n2924), .Y(n5088) ); XNOR2X4TS U4392 ( .A(n2754), .B(n2431), .Y(n3280) ); OAI2BB1X2TS U4393 ( .A0N(n5123), .A1N(n6452), .B0(n4505), .Y(n1032) ); NAND3X2TS U4394 ( .A(n4896), .B(n4897), .C(n4898), .Y(n4899) ); NAND2X8TS U4395 ( .A(n3036), .B(n2329), .Y(n3192) ); NOR2X8TS U4396 ( .A(n3201), .B(n2513), .Y(n3036) ); OAI21X2TS U4397 ( .A0(n3773), .A1(n3772), .B0(n4335), .Y(n3774) ); NOR2X8TS U4398 ( .A(n3464), .B(n3496), .Y(n3498) ); INVX12TS U4399 ( .A(n6353), .Y(n6408) ); BUFX4TS U4400 ( .A(n5084), .Y(n3245) ); AOI2BB2X4TS U4401 ( .B0(n2496), .B1(DmP_mant_SHT1_SW[10]), .A0N(n5422), .A1N(n2527), .Y(n6359) ); NAND2X8TS U4402 ( .A(n3756), .B(n2480), .Y(n4896) ); NAND2X1TS U4403 ( .A(n2789), .B(n4775), .Y(n4776) ); AOI21X2TS U4404 ( .A0(DmP_mant_SHT1_SW[14]), .A1(n6204), .B0(n2973), .Y( n6375) ); AOI22X4TS U4405 ( .A0(n2496), .A1(DmP_mant_SHT1_SW[38]), .B0( DmP_mant_SHT1_SW[39]), .B1(n6204), .Y(n6363) ); INVX8TS U4406 ( .A(n3922), .Y(n2500) ); INVX8TS U4407 ( .A(n3922), .Y(n6204) ); INVX16TS U4408 ( .A(n6202), .Y(n2497) ); BUFX20TS U4409 ( .A(n3125), .Y(n4416) ); BUFX4TS U4410 ( .A(n2716), .Y(n2711) ); AO22X2TS U4411 ( .A0(n4488), .A1(n5015), .B0(n5150), .B1(n4487), .Y(n2504) ); OAI22X2TS U4412 ( .A0(n2088), .A1(n5266), .B0(n5289), .B1(n5537), .Y(n1107) ); OAI22X2TS U4413 ( .A0(n2088), .A1(n4606), .B0(n5289), .B1(n5538), .Y(n1102) ); OAI22X2TS U4414 ( .A0(n2088), .A1(n5270), .B0(n5287), .B1(n5524), .Y(n1065) ); OAI22X2TS U4415 ( .A0(n2088), .A1(n5293), .B0(n5292), .B1(n5505), .Y(n1057) ); AOI21X4TS U4416 ( .A0(n4047), .A1(n5925), .B0(n5924), .Y(n3711) ); MXI2X2TS U4417 ( .A(n5248), .B(n5247), .S0(n2554), .Y(n1121) ); NAND2X6TS U4418 ( .A(n3433), .B(n3452), .Y(n3455) ); AOI21X4TS U4419 ( .A0(n2501), .A1(DmP_mant_SHT1_SW[9]), .B0(n4025), .Y(n6349) ); NOR2X2TS U4420 ( .A(n5342), .B(n2300), .Y(n3752) ); NAND2X4TS U4421 ( .A(n4416), .B(intDX_EWSW[16]), .Y(n4103) ); MXI2X2TS U4422 ( .A(n5273), .B(n5272), .S0(n5265), .Y(n1129) ); INVX8TS U4423 ( .A(n2507), .Y(n2508) ); NAND2X2TS U4424 ( .A(n4412), .B(n1922), .Y(n4097) ); NAND2X2TS U4425 ( .A(n1837), .B(n2957), .Y(n4805) ); NAND2X2TS U4426 ( .A(n4412), .B(intDX_EWSW[45]), .Y(n3604) ); NAND2X2TS U4427 ( .A(n4379), .B(n2028), .Y(n3619) ); NAND2X2TS U4428 ( .A(n4412), .B(intDX_EWSW[42]), .Y(n3613) ); INVX2TS U4429 ( .A(n2537), .Y(n2538) ); INVX8TS U4430 ( .A(n4026), .Y(n6201) ); NOR2X2TS U4431 ( .A(n3858), .B(n4701), .Y(n4703) ); NOR2X2TS U4432 ( .A(n4718), .B(n4717), .Y(n4719) ); OAI22X2TS U4433 ( .A0(n4717), .A1(n4716), .B0(n4718), .B1(n4490), .Y(n2800) ); BUFX12TS U4434 ( .A(n3858), .Y(n4718) ); BUFX20TS U4435 ( .A(n2510), .Y(n4790) ); AOI22X1TS U4436 ( .A0(n6217), .A1(Raw_mant_NRM_SWR[27]), .B0(n5038), .B1( n6228), .Y(n6299) ); AOI22X2TS U4437 ( .A0(n6218), .A1(n1913), .B0(n6228), .B1(n5044), .Y(n6348) ); AOI22X2TS U4438 ( .A0(n6218), .A1(n5029), .B0(n2845), .B1(n5028), .Y(n6326) ); NAND2X2TS U4439 ( .A(n6219), .B(Raw_mant_NRM_SWR[13]), .Y(n6341) ); NAND2X2TS U4440 ( .A(n6218), .B(Raw_mant_NRM_SWR[7]), .Y(n6385) ); NOR2X2TS U4441 ( .A(n4689), .B(n6410), .Y(n3803) ); NOR2X2TS U4442 ( .A(n4689), .B(n4535), .Y(n4124) ); NAND2X2TS U4443 ( .A(n4425), .B(intDY_EWSW[36]), .Y(n4815) ); NAND2X2TS U4444 ( .A(n4807), .B(intDX_EWSW[31]), .Y(n3654) ); NAND2X2TS U4445 ( .A(n4379), .B(intDX_EWSW[0]), .Y(n4384) ); NAND2X2TS U4446 ( .A(n1837), .B(intDX_EWSW[28]), .Y(n3641) ); NAND2X2TS U4447 ( .A(n4425), .B(intDY_EWSW[16]), .Y(n4102) ); NAND2X2TS U4448 ( .A(n1837), .B(intDX_EWSW[46]), .Y(n3595) ); NAND2X2TS U4449 ( .A(n2116), .B(intDX_EWSW[29]), .Y(n3650) ); NAND2X2TS U4450 ( .A(n4863), .B(intDX_EWSW[49]), .Y(n4394) ); BUFX20TS U4451 ( .A(n6217), .Y(n2925) ); NAND2X2TS U4452 ( .A(n4807), .B(intDX_EWSW[57]), .Y(n4371) ); NAND2X2TS U4453 ( .A(n4425), .B(intDY_EWSW[7]), .Y(n3820) ); NAND2X2TS U4454 ( .A(n1837), .B(intDX_EWSW[55]), .Y(n4238) ); NAND2X2TS U4455 ( .A(n4863), .B(intDY_EWSW[44]), .Y(n3579) ); NAND2X2TS U4456 ( .A(n4412), .B(intDX_EWSW[56]), .Y(n4235) ); NAND2X2TS U4457 ( .A(n2049), .B(intDX_EWSW[21]), .Y(n3635) ); NAND2X2TS U4458 ( .A(n4873), .B(intDY_EWSW[6]), .Y(n4112) ); NAND2X2TS U4459 ( .A(n1837), .B(intDX_EWSW[33]), .Y(n3628) ); NAND2X4TS U4460 ( .A(n3797), .B(n2384), .Y(n3241) ); CLKINVX3TS U4461 ( .A(n2537), .Y(n2515) ); INVX6TS U4462 ( .A(n2395), .Y(n2518) ); INVX16TS U4463 ( .A(n3238), .Y(n3261) ); INVX8TS U4464 ( .A(n5495), .Y(n5315) ); NOR2X2TS U4465 ( .A(n4730), .B(n2524), .Y(n4731) ); OAI22X2TS U4466 ( .A0(n6214), .A1(n1857), .B0(n5061), .B1(n5048), .Y(n6399) ); OAI22X2TS U4467 ( .A0(n6214), .A1(n3298), .B0(n6231), .B1(n5050), .Y(n6305) ); OAI22X2TS U4468 ( .A0(n6214), .A1(n5581), .B0(n6231), .B1(n2607), .Y(n6319) ); OAI22X2TS U4469 ( .A0(n6214), .A1(n5491), .B0(n6231), .B1(n5052), .Y(n6324) ); OAI22X2TS U4470 ( .A0(n6214), .A1(n5342), .B0(n6231), .B1(n5049), .Y(n6339) ); OAI22X2TS U4471 ( .A0(n6214), .A1(n5438), .B0(n6231), .B1(n5057), .Y(n6323) ); AOI2BB2X2TS U4472 ( .B0(n2501), .B1(DmP_mant_SHT1_SW[20]), .A0N(n5573), .A1N(n6214), .Y(n6318) ); OAI22X2TS U4473 ( .A0(n2527), .A1(n5427), .B0(n6231), .B1(n5059), .Y(n6301) ); OAI22X2TS U4474 ( .A0(n6214), .A1(n5423), .B0(n5061), .B1(n5056), .Y(n6366) ); OAI22X2TS U4475 ( .A0(n2527), .A1(n5439), .B0(n5061), .B1(n5062), .Y(n6379) ); OAI22X2TS U4476 ( .A0(n2527), .A1(n5437), .B0(n5061), .B1(n5058), .Y(n6295) ); OAI22X2TS U4477 ( .A0(n2527), .A1(n5570), .B0(n5061), .B1(n5053), .Y(n6364) ); NAND2X2TS U4478 ( .A(n2963), .B(intDY_EWSW[4]), .Y(n4073) ); NAND2X2TS U4479 ( .A(n4424), .B(intDY_EWSW[16]), .Y(n3664) ); NAND2X2TS U4480 ( .A(n3124), .B(n2035), .Y(n3667) ); NAND2X2TS U4481 ( .A(n2530), .B(intDY_EWSW[17]), .Y(n3670) ); CLKINVX3TS U4482 ( .A(n2537), .Y(n2532) ); CLKINVX6TS U4483 ( .A(Shift_reg_FLAGS_7_6), .Y(n2535) ); CLKINVX6TS U4484 ( .A(Shift_reg_FLAGS_7_6), .Y(n2536) ); CLKINVX3TS U4485 ( .A(n2537), .Y(n2539) ); NAND2X1TS U4486 ( .A(n2500), .B(DmP_mant_SHT1_SW[6]), .Y(n6383) ); NAND2X1TS U4487 ( .A(n6203), .B(DmP_mant_SHT1_SW[0]), .Y(n6328) ); CLKBUFX3TS U4488 ( .A(n6292), .Y(n6286) ); INVX12TS U4489 ( .A(Shift_reg_FLAGS_7[2]), .Y(n4917) ); NOR2X2TS U4490 ( .A(n4702), .B(n4535), .Y(n4536) ); OAI22X2TS U4491 ( .A0(n4689), .A1(n4521), .B0(n4702), .B1(n4053), .Y(n4054) ); NAND2X2TS U4492 ( .A(n1919), .B(n4523), .Y(n4526) ); NAND2X2TS U4493 ( .A(n1919), .B(n1645), .Y(n4639) ); BUFX8TS U4494 ( .A(n2764), .Y(n2554) ); NOR2X1TS U4495 ( .A(n2554), .B(n1876), .Y(n2875) ); NOR2X2TS U4496 ( .A(n2880), .B(n2554), .Y(n2879) ); OAI21X2TS U4497 ( .A0(n2881), .A1(n5265), .B0(n2886), .Y(n2878) ); MXI2X2TS U4498 ( .A(n5270), .B(n5269), .S0(n5264), .Y(n1132) ); NAND2X4TS U4499 ( .A(n3846), .B(n5024), .Y(n4040) ); INVX16TS U4500 ( .A(n3846), .Y(n4662) ); BUFX16TS U4501 ( .A(n3804), .Y(n2558) ); NAND2X2TS U4502 ( .A(n2558), .B(n5024), .Y(n4291) ); NAND2X2TS U4503 ( .A(n4659), .B(n5033), .Y(n3966) ); NAND2X8TS U4504 ( .A(n1949), .B(n2558), .Y(n3832) ); NAND2X2TS U4505 ( .A(n2041), .B(intDY_EWSW[2]), .Y(n4880) ); NAND2X2TS U4506 ( .A(n1836), .B(intDX_EWSW[21]), .Y(n4862) ); NAND2X2TS U4507 ( .A(n1836), .B(intDY_EWSW[11]), .Y(n4144) ); NAND2X2TS U4508 ( .A(n1836), .B(intDX_EWSW[2]), .Y(n4375) ); NAND2X2TS U4509 ( .A(n2531), .B(intDX_EWSW[1]), .Y(n4378) ); NAND2X2TS U4510 ( .A(n2526), .B(intDX_EWSW[0]), .Y(n4382) ); NOR2X8TS U4511 ( .A(n2764), .B(n2560), .Y(n4543) ); CLKBUFX2TS U4512 ( .A(n6262), .Y(n2566) ); CLKBUFX2TS U4513 ( .A(n2569), .Y(n2567) ); CLKBUFX2TS U4514 ( .A(n2569), .Y(n2568) ); CLKBUFX2TS U4515 ( .A(n2541), .Y(n2569) ); XOR2X4TS U4516 ( .A(intDY_EWSW[63]), .B(intAS), .Y(n4729) ); CLKMX2X2TS U4517 ( .A(n5296), .B(Shift_amount_SHT1_EWR[2]), .S0(n2547), .Y( n1602) ); AOI22X2TS U4518 ( .A0(n4906), .A1(Shift_amount_SHT1_EWR[2]), .B0( shift_value_SHT2_EWR[2]), .B1(n6230), .Y(n4907) ); AOI22X1TS U4519 ( .A0(n2982), .A1(Raw_mant_NRM_SWR[46]), .B0(n2873), .B1( n5039), .Y(n6384) ); AOI22X1TS U4520 ( .A0(n6217), .A1(n2345), .B0(n5041), .B1(n5030), .Y(n6358) ); AOI21X4TS U4521 ( .A0(n2577), .A1(n4711), .B0(n2574), .Y(n2573) ); NAND2X8TS U4522 ( .A(n2583), .B(n2580), .Y(n5054) ); NOR2X8TS U4523 ( .A(n2586), .B(n2584), .Y(n2583) ); OAI21X4TS U4524 ( .A0(n6035), .A1(n6034), .B0(n2585), .Y(n2584) ); NAND2BX4TS U4525 ( .AN(n5918), .B(n2587), .Y(n2586) ); AOI22X4TS U4526 ( .A0(n5157), .A1(n5145), .B0(n2691), .B1(n2518), .Y(n6440) ); NAND4BBX4TS U4527 ( .AN(n4676), .BN(n4680), .C(n2591), .D(n2590), .Y(n6439) ); OAI21X2TS U4528 ( .A0(n2597), .A1(n1868), .B0(n2761), .Y(n1025) ); AOI22X4TS U4529 ( .A0(n4651), .A1(n1878), .B0(n3365), .B1(n4686), .Y(n2597) ); NAND2X8TS U4530 ( .A(n4612), .B(n1872), .Y(n2602) ); NAND2BX4TS U4531 ( .AN(n4323), .B(n2604), .Y(n2603) ); INVX2TS U4532 ( .A(n6411), .Y(n2605) ); INVX12TS U4533 ( .A(n4322), .Y(n6411) ); NAND2X8TS U4534 ( .A(n2608), .B(n2614), .Y(n4612) ); OAI22X4TS U4535 ( .A0(n5273), .A1(n2088), .B0(n5287), .B1(n5522), .Y(n1066) ); CLKINVX12TS U4536 ( .A(n4895), .Y(n2615) ); NAND2X8TS U4537 ( .A(n3763), .B(n3730), .Y(n4895) ); NOR2X8TS U4538 ( .A(n2268), .B(n2617), .Y(n4249) ); NAND2X8TS U4539 ( .A(n3187), .B(n3195), .Y(n2618) ); NOR2BX4TS U4540 ( .AN(n2622), .B(n3794), .Y(n2621) ); NAND2X8TS U4541 ( .A(n4280), .B(n4273), .Y(n3781) ); NAND4X8TS U4542 ( .A(n2623), .B(n5342), .C(n5431), .D(n2378), .Y(n2624) ); NOR2X8TS U4543 ( .A(Raw_mant_NRM_SWR[26]), .B(Raw_mant_NRM_SWR[25]), .Y( n4250) ); NOR3X8TS U4544 ( .A(n2626), .B(n2625), .C(n2624), .Y(n4347) ); NAND3X8TS U4545 ( .A(n3070), .B(n3069), .C(n1921), .Y(n3068) ); NAND2X2TS U4546 ( .A(n2628), .B(DMP_SFG[31]), .Y(n4984) ); INVX12TS U4547 ( .A(n4708), .Y(n4698) ); AND2X8TS U4548 ( .A(n1919), .B(n4681), .Y(n4708) ); NAND4BX4TS U4549 ( .AN(n3947), .B(n3946), .C(n6172), .D(n3945), .Y(n5030) ); NAND4BX4TS U4550 ( .AN(n3927), .B(n3926), .C(n3924), .D(n3925), .Y(n1626) ); OAI21X4TS U4551 ( .A0(n3472), .A1(n3473), .B0(n3471), .Y(n3479) ); NAND2X4TS U4552 ( .A(n3327), .B(intDY_EWSW[2]), .Y(n3415) ); NAND4X4TS U4553 ( .A(n2729), .B(n2727), .C(n2726), .D(n2724), .Y(n1146) ); NAND2X4TS U4554 ( .A(n3002), .B(n3001), .Y(n3000) ); NOR2X8TS U4555 ( .A(n2676), .B(DMP_SFG[28]), .Y(n4785) ); XOR2X4TS U4556 ( .A(n5088), .B(n5087), .Y(n5090) ); OAI22X4TS U4557 ( .A0(n5257), .A1(n2990), .B0(n5292), .B1(n5531), .Y(n1083) ); AOI22X2TS U4558 ( .A0(n2637), .A1(n5147), .B0(n4608), .B1(n5158), .Y(n3080) ); OAI2BB1X4TS U4559 ( .A0N(n5149), .A1N(n6459), .B0(n5142), .Y(n1029) ); AOI21X4TS U4560 ( .A0(n4685), .A1(n4686), .B0(n2639), .Y(n2638) ); NAND3BX4TS U4561 ( .AN(n1897), .B(n4329), .C(n4330), .Y(n4686) ); NAND2X8TS U4562 ( .A(n4257), .B(n3746), .Y(n2647) ); NOR2X8TS U4563 ( .A(n2985), .B(n3149), .Y(n5027) ); NAND2X8TS U4564 ( .A(n2677), .B(n4909), .Y(n2649) ); XNOR2X4TS U4565 ( .A(DmP_mant_SFG_SWR[25]), .B(n1839), .Y(n2650) ); OAI21X4TS U4566 ( .A0(n2655), .A1(n2550), .B0(n2654), .Y(n1167) ); NAND2X1TS U4567 ( .A(n2551), .B(Raw_mant_NRM_SWR[31]), .Y(n2654) ); XNOR2X4TS U4568 ( .A(n2656), .B(n5329), .Y(n2655) ); AND2X8TS U4569 ( .A(n5472), .B(n2917), .Y(n4766) ); NAND2X8TS U4570 ( .A(n4781), .B(n2667), .Y(n2902) ); NOR2X8TS U4571 ( .A(n4785), .B(n5327), .Y(n2667) ); NOR2X8TS U4572 ( .A(n3391), .B(DMP_SFG[29]), .Y(n5327) ); XNOR2X4TS U4573 ( .A(n1853), .B(DmP_mant_SFG_SWR[30]), .Y(n2657) ); NAND2BX4TS U4574 ( .AN(n3175), .B(n2402), .Y(n3174) ); NAND2X4TS U4575 ( .A(n2677), .B(n2662), .Y(n2660) ); OAI21X4TS U4576 ( .A0(n2666), .A1(n5005), .B0(n3186), .Y(n1153) ); NAND3X8TS U4577 ( .A(n2435), .B(n2671), .C(n2668), .Y(n1155) ); NAND2X8TS U4578 ( .A(n2674), .B(n2672), .Y(n2716) ); AOI2BB1X4TS U4579 ( .A0N(n5323), .A1N(n5327), .B0(n3166), .Y(n2672) ); NAND2X4TS U4580 ( .A(DMP_SFG[29]), .B(n3391), .Y(n2673) ); NAND2X8TS U4581 ( .A(n2676), .B(DMP_SFG[28]), .Y(n5323) ); NAND2X8TS U4582 ( .A(n2675), .B(n4775), .Y(n4780) ); OAI21X4TS U4583 ( .A0(n3556), .A1(n3555), .B0(n3554), .Y(n2682) ); NAND2X6TS U4584 ( .A(n2684), .B(n2683), .Y(n3559) ); AOI21X4TS U4585 ( .A0(n2688), .A1(n3553), .B0(n2686), .Y(n2685) ); OAI21X4TS U4586 ( .A0(n2705), .A1(n3552), .B0(n3551), .Y(n2686) ); NOR2X8TS U4587 ( .A(n3309), .B(intDY_EWSW[50]), .Y(n2687) ); OAI22X4TS U4588 ( .A0(n3550), .A1(n2689), .B0(intDX_EWSW[49]), .B1(n2376), .Y(n2688) ); NOR2X8TS U4589 ( .A(n2990), .B(n4477), .Y(n2690) ); AOI22X2TS U4590 ( .A0(n5157), .A1(n5158), .B0(n2516), .B1(n2691), .Y(n6433) ); AOI22X4TS U4591 ( .A0(n4604), .A1(n2522), .B0(n5158), .B1(n2691), .Y(n5270) ); NAND3X8TS U4592 ( .A(n2695), .B(n2702), .C(n2692), .Y(n2701) ); CLKINVX12TS U4593 ( .A(n2693), .Y(n2692) ); NOR2X8TS U4594 ( .A(n2701), .B(n2700), .Y(n2699) ); NOR2X8TS U4595 ( .A(n3313), .B(intDY_EWSW[51]), .Y(n2705) ); NOR2X8TS U4596 ( .A(n3347), .B(intDY_EWSW[61]), .Y(n3561) ); INVX16TS U4597 ( .A(n2710), .Y(n6215) ); XOR2X4TS U4598 ( .A(n1853), .B(n2758), .Y(n2917) ); NAND2X8TS U4599 ( .A(n2716), .B(n3218), .Y(n3165) ); OAI22X4TS U4600 ( .A0(n2714), .A1(n2368), .B0(n4937), .B1(n3069), .Y(n3206) ); OR2X8TS U4601 ( .A(n2715), .B(n4937), .Y(n2714) ); NOR2X8TS U4602 ( .A(n4936), .B(n4962), .Y(n2715) ); OAI21X4TS U4603 ( .A0(n2719), .A1(n5005), .B0(n2718), .Y(n1147) ); INVX3TS U4604 ( .A(n2909), .Y(n2722) ); NAND2X8TS U4605 ( .A(n3008), .B(n3011), .Y(n2736) ); NAND3X8TS U4606 ( .A(n3182), .B(n3256), .C(n2397), .Y(n2788) ); CLKBUFX2TS U4607 ( .A(n5097), .Y(n2738) ); NAND2X6TS U4608 ( .A(n2739), .B(n5069), .Y(n3221) ); NAND2X4TS U4609 ( .A(n5065), .B(n3370), .Y(n2739) ); BUFX6TS U4610 ( .A(intDY_EWSW[34]), .Y(n2740) ); OAI21X4TS U4611 ( .A0(n3438), .A1(n2267), .B0(n2741), .Y(n3444) ); NOR2X8TS U4612 ( .A(n3319), .B(intDY_EWSW[9]), .Y(n3438) ); NOR2X6TS U4613 ( .A(n3488), .B(n3466), .Y(n3489) ); INVX8TS U4614 ( .A(n4062), .Y(n4644) ); NAND2BX4TS U4615 ( .AN(n3851), .B(n3848), .Y(n3095) ); NOR2X8TS U4616 ( .A(n3290), .B(intDY_EWSW[15]), .Y(n3450) ); NAND2X2TS U4617 ( .A(n4721), .B(n2516), .Y(n4627) ); OR2X8TS U4618 ( .A(n3092), .B(n2396), .Y(n5141) ); OAI21X4TS U4619 ( .A0(n2743), .A1(n3430), .B0(n2912), .Y(n3459) ); AOI21X4TS U4620 ( .A0(n3417), .A1(n3418), .B0(n2746), .Y(n2743) ); NAND2X8TS U4621 ( .A(n2967), .B(n2978), .Y(n2977) ); NOR2X6TS U4622 ( .A(n3292), .B(intDY_EWSW[27]), .Y(n3488) ); NAND2X2TS U4623 ( .A(n3312), .B(intDY_EWSW[31]), .Y(n3494) ); BUFX6TS U4624 ( .A(intDY_EWSW[28]), .Y(n2745) ); OAI21X4TS U4625 ( .A0(n3415), .A1(n3416), .B0(n3414), .Y(n2746) ); NAND2X2TS U4626 ( .A(n3355), .B(intDY_EWSW[14]), .Y(n3449) ); NAND2X2TS U4627 ( .A(n4658), .B(n5037), .Y(n4119) ); NAND2X2TS U4628 ( .A(n2529), .B(n5038), .Y(n3963) ); NAND2X2TS U4629 ( .A(n1627), .B(n2780), .Y(n4120) ); NOR2X6TS U4630 ( .A(n3435), .B(n3441), .Y(n3443) ); NAND2X8TS U4631 ( .A(n5183), .B(n2330), .Y(n3116) ); NAND2X8TS U4632 ( .A(n4476), .B(n3117), .Y(n5183) ); NAND2X4TS U4633 ( .A(n3467), .B(n3489), .Y(n3468) ); NAND2X4TS U4634 ( .A(n3346), .B(intDY_EWSW[36]), .Y(n3525) ); NOR2X8TS U4635 ( .A(n4254), .B(n4027), .Y(n4338) ); NOR2X4TS U4636 ( .A(n3314), .B(intDY_EWSW[52]), .Y(n3511) ); NOR2X4TS U4637 ( .A(n3361), .B(intDY_EWSW[26]), .Y(n3466) ); OAI21X2TS U4638 ( .A0(n4662), .A1(n4661), .B0(n4660), .Y(n4667) ); NOR2X2TS U4639 ( .A(n5900), .B(n2143), .Y(n3853) ); NAND2X2TS U4640 ( .A(n4659), .B(n5055), .Y(n3808) ); INVX8TS U4641 ( .A(n2846), .Y(n2914) ); INVX6TS U4642 ( .A(n2902), .Y(n4959) ); AOI2BB1X4TS U4643 ( .A0N(n4678), .A1N(n4698), .B0(n3837), .Y(n3074) ); NAND3X8TS U4644 ( .A(n3149), .B(n3202), .C(n2562), .Y(n2981) ); NOR2X4TS U4645 ( .A(n3434), .B(n3438), .Y(n3436) ); NAND2X8TS U4646 ( .A(n3793), .B(n3735), .Y(n2748) ); NOR2X8TS U4647 ( .A(n4934), .B(n2846), .Y(n4935) ); NOR2X4TS U4648 ( .A(n3324), .B(intDY_EWSW[4]), .Y(n3419) ); OAI22X2TS U4649 ( .A0(n2453), .A1(n5286), .B0(n5287), .B1(n5503), .Y(n1588) ); NAND2X4TS U4650 ( .A(n6449), .B(n4543), .Y(n4510) ); AOI22X2TS U4651 ( .A0(n6218), .A1(Raw_mant_NRM_SWR[29]), .B0(n5036), .B1( n2845), .Y(n6401) ); NOR2X4TS U4652 ( .A(n3413), .B(n3416), .Y(n3417) ); CLKINVX12TS U4653 ( .A(n4268), .Y(n3793) ); BUFX20TS U4654 ( .A(n4250), .Y(n2766) ); OAI21X4TS U4655 ( .A0(n3441), .A1(n3440), .B0(n3439), .Y(n3442) ); NAND2X4TS U4656 ( .A(n3363), .B(intDY_EWSW[42]), .Y(n3533) ); NAND2X2TS U4657 ( .A(n4479), .B(n4478), .Y(n1035) ); INVX2TS U4658 ( .A(n3754), .Y(n2749) ); XOR2X4TS U4659 ( .A(n4015), .B(DMP_exp_NRM2_EW[10]), .Y(n5286) ); XOR2X4TS U4660 ( .A(n2309), .B(n3979), .Y(n5164) ); AOI21X4TS U4661 ( .A0(n3545), .A1(n3546), .B0(n3544), .Y(n3547) ); OAI21X4TS U4662 ( .A0(n3476), .A1(n3475), .B0(n3474), .Y(n3477) ); BUFX6TS U4663 ( .A(n4895), .Y(n2751) ); OAI21X4TS U4664 ( .A0(n3485), .A1(n3484), .B0(n3483), .Y(n3490) ); NAND2X2TS U4665 ( .A(n4637), .B(n5025), .Y(n4082) ); NOR2X8TS U4666 ( .A(n5094), .B(n3380), .Y(n2752) ); MX2X4TS U4667 ( .A(n6420), .B(n5566), .S0(n5224), .Y(n5130) ); INVX16TS U4668 ( .A(n4095), .Y(n4026) ); NAND3X6TS U4669 ( .A(n3174), .B(n3914), .C(n3173), .Y(n3180) ); NAND2X8TS U4670 ( .A(n5278), .B(n6293), .Y(n3128) ); NAND2X8TS U4671 ( .A(n2944), .B(n3131), .Y(n5278) ); NAND2X4TS U4672 ( .A(n2762), .B(n2856), .Y(n3388) ); AOI21X4TS U4673 ( .A0(n4753), .A1(n3297), .B0(n3387), .Y(n2762) ); OR2X8TS U4674 ( .A(n2840), .B(n5478), .Y(n5097) ); XNOR2X4TS U4675 ( .A(n2489), .B(DmP_mant_SFG_SWR[18]), .Y(n2840) ); NAND3X8TS U4676 ( .A(n2422), .B(n3112), .C(n2914), .Y(n4920) ); NAND4X4TS U4677 ( .A(n3229), .B(n3223), .C(n3224), .D(n3228), .Y(n1150) ); XOR2X4TS U4678 ( .A(n2487), .B(DmP_mant_SFG_SWR[44]), .Y(n3405) ); NAND2X4TS U4679 ( .A(n3436), .B(n3443), .Y(n3437) ); OAI21X4TS U4680 ( .A0(n3175), .A1(n3908), .B0(n3211), .Y(n3210) ); OAI21X4TS U4681 ( .A0(n3412), .A1(n3411), .B0(n3410), .Y(n3418) ); OAI21X4TS U4682 ( .A0(n3534), .A1(n3533), .B0(n3532), .Y(n3535) ); NAND2X4TS U4683 ( .A(n6396), .B(n6369), .Y(n4438) ); NOR2X4TS U4684 ( .A(n3004), .B(n3003), .Y(n3002) ); NAND2X4TS U4685 ( .A(n4633), .B(n4711), .Y(n2887) ); OAI21X4TS U4686 ( .A0(n3450), .A1(n3449), .B0(n3448), .Y(n3451) ); NAND2X2TS U4687 ( .A(n4482), .B(n4481), .Y(n1051) ); AOI22X4TS U4688 ( .A0(n4496), .A1(n2449), .B0(n5155), .B1(n4645), .Y(n4652) ); NOR2X4TS U4689 ( .A(n4480), .B(n5125), .Y(n4542) ); NAND3X8TS U4690 ( .A(n2765), .B(n4599), .C(n4598), .Y(n4635) ); NAND2X2TS U4691 ( .A(n4658), .B(n5016), .Y(n4529) ); NAND2X8TS U4692 ( .A(n2872), .B(n3797), .Y(n4069) ); OA21X4TS U4693 ( .A0(n3549), .A1(n3548), .B0(n3547), .Y(n2933) ); NOR2X4TS U4694 ( .A(n3463), .B(n3493), .Y(n3465) ); NAND4X4TS U4695 ( .A(n3776), .B(n3778), .C(n3777), .D(n1989), .Y(n3780) ); NOR2X4TS U4696 ( .A(n2428), .B(n2975), .Y(n6317) ); NOR2X2TS U4697 ( .A(n4720), .B(n4719), .Y(n4727) ); NOR2X4TS U4698 ( .A(n3353), .B(intDY_EWSW[10]), .Y(n3435) ); AOI21X4TS U4699 ( .A0(n3444), .A1(n3443), .B0(n3442), .Y(n3456) ); OAI2BB1X4TS U4700 ( .A0N(n5749), .A1N(n5750), .B0(n2770), .Y(n5051) ); AND3X8TS U4701 ( .A(n2773), .B(n2771), .C(n3838), .Y(n2770) ); OAI21X4TS U4702 ( .A0(n2777), .A1(n2547), .B0(n2776), .Y(n1600) ); XNOR2X4TS U4703 ( .A(n5308), .B(n5309), .Y(n2777) ); NAND2X8TS U4704 ( .A(n5294), .B(n5302), .Y(n2779) ); NAND2X8TS U4705 ( .A(n3033), .B(n5310), .Y(n5294) ); NAND3X8TS U4706 ( .A(n2781), .B(n3971), .C(n3970), .Y(n5024) ); XOR2X4TS U4707 ( .A(DmP_mant_SFG_SWR[42]), .B(n6161), .Y(n3402) ); NOR2X8TS U4708 ( .A(n3325), .B(intDY_EWSW[0]), .Y(n3412) ); NAND2X8TS U4709 ( .A(n2790), .B(n4008), .Y(n3994) ); OR2X8TS U4710 ( .A(n4007), .B(n4012), .Y(n2790) ); NOR2X8TS U4711 ( .A(n3369), .B(DMP_exp_NRM2_EW[5]), .Y(n4007) ); NAND4X8TS U4712 ( .A(n2216), .B(n2920), .C(n4043), .D(n2420), .Y(n4707) ); NAND2X8TS U4713 ( .A(n3968), .B(n2794), .Y(n5018) ); AOI22X4TS U4714 ( .A0(n4619), .A1(n2560), .B0(n4618), .B1(n5145), .Y(n4145) ); AOI2BB1X4TS U4715 ( .A0N(n4669), .A1N(n4489), .B0(n2800), .Y(n2799) ); AOI21X4TS U4716 ( .A0(n2807), .A1(n3560), .B0(n2803), .Y(n3567) ); OAI22X4TS U4717 ( .A0(n2806), .A1(n2804), .B0(intDX_EWSW[59]), .B1(n2374), .Y(n2803) ); NOR2X8TS U4718 ( .A(n2806), .B(n2805), .Y(n3560) ); NOR2X8TS U4719 ( .A(n3339), .B(intDY_EWSW[58]), .Y(n2805) ); NOR2X8TS U4720 ( .A(n3344), .B(intDY_EWSW[59]), .Y(n2806) ); NAND3X8TS U4721 ( .A(n2811), .B(n2810), .C(n2809), .Y(n5036) ); OAI2BB1X4TS U4722 ( .A0N(n5161), .A1N(n6437), .B0(n5152), .Y(n1048) ); NAND3BX4TS U4723 ( .AN(n2815), .B(n4714), .C(n4713), .Y(n6437) ); NOR2X8TS U4724 ( .A(n3326), .B(intDY_EWSW[3]), .Y(n3416) ); AOI2BB2X4TS U4725 ( .B0(n4496), .B1(n2560), .A0N(n2283), .A1N(n2825), .Y( n4631) ); NAND3BX4TS U4726 ( .AN(n4690), .B(n4694), .C(n2829), .Y(n6455) ); XNOR2X4TS U4727 ( .A(n5418), .B(n2257), .Y(n3890) ); NOR2X8TS U4728 ( .A(n2833), .B(n2832), .Y(n2831) ); NOR2BX4TS U4729 ( .AN(n6111), .B(n2838), .Y(n2837) ); NOR2X8TS U4730 ( .A(DMP_SFG[33]), .B(n2842), .Y(n4939) ); NAND2X4TS U4731 ( .A(DMP_SFG[33]), .B(n2842), .Y(n4940) ); NOR2X8TS U4732 ( .A(n2844), .B(DMP_SFG[32]), .Y(n4931) ); XOR2X4TS U4733 ( .A(DmP_mant_SFG_SWR[34]), .B(n1853), .Y(n2844) ); INVX16TS U4734 ( .A(n2845), .Y(n4332) ); NOR2X8TS U4735 ( .A(n2383), .B(n2561), .Y(n2845) ); AOI22X1TS U4736 ( .A0(n4906), .A1(n2570), .B0(n6229), .B1(n2330), .Y(n4904) ); NOR2X8TS U4737 ( .A(n2902), .B(n3214), .Y(n3213) ); NOR2X8TS U4738 ( .A(Raw_mant_NRM_SWR[38]), .B(Raw_mant_NRM_SWR[37]), .Y( n3767) ); NOR2X8TS U4739 ( .A(n1856), .B(Raw_mant_NRM_SWR[3]), .Y(n4892) ); OAI2BB1X4TS U4740 ( .A0N(n2203), .A1N(n6103), .B0(n6102), .Y(n4300) ); OAI2BB1X4TS U4741 ( .A0N(n2560), .A1N(n4302), .B0(n2852), .Y(n2992) ); NOR2X8TS U4742 ( .A(n3235), .B(n2854), .Y(n4095) ); NAND3X4TS U4743 ( .A(n3295), .B(n3297), .C(n1920), .Y(n2856) ); OR2X8TS U4744 ( .A(n3548), .B(n2858), .Y(n3010) ); NOR2X8TS U4745 ( .A(n3534), .B(n2861), .Y(n3536) ); NOR2X8TS U4746 ( .A(n3293), .B(intDY_EWSW[43]), .Y(n3534) ); NOR2X8TS U4747 ( .A(n3543), .B(n2864), .Y(n3545) ); NOR2X8TS U4748 ( .A(n3305), .B(intDY_EWSW[47]), .Y(n3543) ); NAND3X8TS U4749 ( .A(n2869), .B(n2865), .C(n2038), .Y(n3795) ); NAND2X8TS U4750 ( .A(n2872), .B(n2871), .Y(n6353) ); NOR2BX4TS U4751 ( .AN(n3797), .B(n6229), .Y(n2871) ); AOI21X4TS U4752 ( .A0(n2876), .A1(n2449), .B0(n2381), .Y(n3322) ); NAND2BX4TS U4753 ( .AN(n4522), .B(n2887), .Y(n2885) ); NAND3X8TS U4754 ( .A(n3760), .B(n4896), .C(n3761), .Y(n4340) ); NAND2X8TS U4755 ( .A(n3265), .B(n2910), .Y(n4254) ); NOR2X8TS U4756 ( .A(n2742), .B(n3764), .Y(n2888) ); CLKINVX12TS U4757 ( .A(n2890), .Y(n2889) ); NOR2X8TS U4758 ( .A(Raw_mant_NRM_SWR[51]), .B(Raw_mant_NRM_SWR[52]), .Y( n3789) ); AND2X8TS U4759 ( .A(n3729), .B(n3767), .Y(n2892) ); OR2X8TS U4760 ( .A(n4336), .B(n4341), .Y(n2901) ); OR2X8TS U4761 ( .A(n4342), .B(n5441), .Y(n4336) ); NAND2X8TS U4762 ( .A(n2766), .B(n2054), .Y(n4342) ); OAI21X4TS U4763 ( .A0(n2908), .A1(n5005), .B0(n2907), .Y(n5330) ); NOR2X8TS U4764 ( .A(Raw_mant_NRM_SWR[14]), .B(Raw_mant_NRM_SWR[18]), .Y( n3730) ); NAND2X2TS U4765 ( .A(n3313), .B(intDY_EWSW[51]), .Y(n3551) ); NAND2X2TS U4766 ( .A(n3352), .B(intDY_EWSW[7]), .Y(n3425) ); AOI21X4TS U4767 ( .A0(n3429), .A1(n3428), .B0(n3427), .Y(n2912) ); NAND2X8TS U4768 ( .A(n2913), .B(n2933), .Y(n3008) ); NAND2X2TS U4769 ( .A(n3357), .B(n2250), .Y(n3483) ); NAND2X2TS U4770 ( .A(n3361), .B(intDY_EWSW[26]), .Y(n3487) ); NAND2X2TS U4771 ( .A(n1950), .B(n5275), .Y(n3724) ); AOI22X4TS U4772 ( .A0(n5263), .A1(n1877), .B0(n5262), .B1(n5274), .Y(n5293) ); OAI21X4TS U4773 ( .A0(n3482), .A1(n3481), .B0(n3480), .Y(n3505) ); NOR2X4TS U4774 ( .A(n3303), .B(intDY_EWSW[20]), .Y(n3460) ); NAND2X2TS U4775 ( .A(n4721), .B(n4685), .Y(n4726) ); OAI2BB1X4TS U4776 ( .A0N(n5149), .A1N(n6461), .B0(n5137), .Y(n1028) ); NAND2X2TS U4777 ( .A(n3326), .B(intDY_EWSW[3]), .Y(n3414) ); NAND2X2TS U4778 ( .A(n4637), .B(n5275), .Y(n4592) ); NAND2X2TS U4779 ( .A(n3587), .B(intDX_EWSW[3]), .Y(n4405) ); AOI21X4TS U4780 ( .A0(n3453), .A1(n3452), .B0(n3451), .Y(n3454) ); INVX16TS U4781 ( .A(n4268), .Y(n4257) ); NOR2X2TS U4782 ( .A(n4596), .B(n4595), .Y(n4598) ); NOR2BX4TS U4783 ( .AN(n2918), .B(n3775), .Y(n3776) ); NOR2BX4TS U4784 ( .AN(n2919), .B(Raw_mant_NRM_SWR[2]), .Y(n2918) ); NAND4X2TS U4785 ( .A(n4594), .B(n6143), .C(n6142), .D(n6141), .Y(n5039) ); NAND3X2TS U4786 ( .A(n6085), .B(n6084), .C(n6083), .Y(n3969) ); NAND2X2TS U4787 ( .A(n2022), .B(n2517), .Y(n4634) ); NOR2X6TS U4788 ( .A(n3517), .B(n3566), .Y(n3569) ); NAND2X2TS U4789 ( .A(n4511), .B(n4510), .Y(n1053) ); OAI21X4TS U4790 ( .A0(n4145), .A1(n1868), .B0(n2922), .Y(n1024) ); AOI21X4TS U4791 ( .A0(n3537), .A1(n3536), .B0(n3535), .Y(n3549) ); NOR2X2TS U4792 ( .A(n4258), .B(n5433), .Y(n3746) ); OAI22X4TS U4793 ( .A0(n5261), .A1(n2990), .B0(n5292), .B1(n5532), .Y(n1103) ); NAND2X8TS U4794 ( .A(n3845), .B(n2926), .Y(n4671) ); NAND2X2TS U4795 ( .A(n3301), .B(n2299), .Y(n3538) ); OAI21X4TS U4796 ( .A0(n3540), .A1(n3539), .B0(n3538), .Y(n3546) ); OAI21X2TS U4797 ( .A0(n4969), .A1(n4993), .B0(n4994), .Y(n4970) ); NAND2X2TS U4798 ( .A(n6219), .B(Raw_mant_NRM_SWR[3]), .Y(n6355) ); NAND2X2TS U4799 ( .A(n3342), .B(intDY_EWSW[23]), .Y(n3474) ); OAI2BB1X4TS U4800 ( .A0N(n5149), .A1N(n6437), .B0(n5146), .Y(n1038) ); AOI22X4TS U4801 ( .A0(n3365), .A1(n5151), .B0(n2518), .B1(n5150), .Y(n6438) ); NAND2X2TS U4802 ( .A(n2780), .B(n5014), .Y(n3941) ); NOR2X2TS U4803 ( .A(n3832), .B(n4534), .Y(n4517) ); NOR2X6TS U4804 ( .A(n3266), .B(n2370), .Y(n3230) ); AOI21X4TS U4805 ( .A0(n3564), .A1(n3563), .B0(n3562), .Y(n3565) ); OAI21X4TS U4806 ( .A0(n3567), .A1(n3566), .B0(n3565), .Y(n3568) ); NAND3BX4TS U4807 ( .AN(n2927), .B(n4033), .C(n4032), .Y(n1628) ); AOI22X4TS U4808 ( .A0(n4297), .A1(n1871), .B0(n4685), .B1(n5154), .Y(n2929) ); XNOR2X2TS U4809 ( .A(intDX_EWSW[14]), .B(n2024), .Y(n4180) ); NAND2X2TS U4810 ( .A(n3311), .B(n2479), .Y(n3471) ); NOR2X8TS U4811 ( .A(n3390), .B(DMP_SFG[25]), .Y(n3207) ); BUFX20TS U4812 ( .A(n4790), .Y(n4807) ); NAND2X2TS U4813 ( .A(n5136), .B(n3062), .Y(n4626) ); NAND2X2TS U4814 ( .A(n4686), .B(n2518), .Y(n4610) ); NAND2X2TS U4815 ( .A(n4612), .B(n5147), .Y(n4605) ); MXI2X4TS U4816 ( .A(n5254), .B(n5520), .S0(n2554), .Y(n1044) ); INVX8TS U4817 ( .A(n1628), .Y(n4535) ); OAI22X2TS U4818 ( .A0(n3832), .A1(n4535), .B0(n4716), .B1(n4520), .Y(n4037) ); NAND2X8TS U4819 ( .A(n2405), .B(n3370), .Y(n3380) ); NAND2X4TS U4820 ( .A(n4883), .B(n4882), .Y(n1608) ); NAND4BX4TS U4821 ( .AN(n3709), .B(n3708), .C(n6188), .D(n3707), .Y(n5017) ); OAI2BB1X4TS U4822 ( .A0N(underflow_flag), .A1N(n5571), .B0(n1835), .Y(n1200) ); NAND2X2TS U4823 ( .A(n3290), .B(intDY_EWSW[15]), .Y(n3448) ); NAND2X4TS U4824 ( .A(n3510), .B(n3553), .Y(n3513) ); OAI21X4TS U4825 ( .A0(n2932), .A1(n5205), .B0(n2931), .Y(n1161) ); XOR2X4TS U4826 ( .A(n4951), .B(n4950), .Y(n2932) ); NAND2X2TS U4827 ( .A(n6218), .B(Raw_mant_NRM_SWR[36]), .Y(n6372) ); NAND2X2TS U4828 ( .A(n4838), .B(intDY_EWSW[55]), .Y(n4459) ); NAND2X4TS U4829 ( .A(n3096), .B(n3093), .Y(n3092) ); NOR2X2TS U4830 ( .A(n4327), .B(n4326), .Y(n4328) ); OR2X8TS U4831 ( .A(n3386), .B(DMP_SFG[22]), .Y(n3297) ); NOR2X2TS U4832 ( .A(n4533), .B(n4532), .Y(n4540) ); NAND2X4TS U4833 ( .A(n4869), .B(n4868), .Y(n1607) ); BUFX6TS U4834 ( .A(n5140), .Y(n2938) ); NAND4X2TS U4835 ( .A(n4273), .B(n4274), .C(n4275), .D(n4272), .Y(n4286) ); NOR2X2TS U4836 ( .A(n4589), .B(n4588), .Y(n4599) ); XOR2X4TS U4837 ( .A(n1143), .B(n6147), .Y(n5747) ); NAND2X2TS U4838 ( .A(n4637), .B(n4707), .Y(n4065) ); BUFX6TS U4839 ( .A(intDY_EWSW[35]), .Y(n2940) ); NOR4X2TS U4840 ( .A(n4165), .B(n4164), .C(n4163), .D(n4162), .Y(n4228) ); OAI22X2TS U4841 ( .A0(n4733), .A1(n5162), .B0(Shift_reg_FLAGS_7_6), .B1( n5401), .Y(n1523) ); NAND2X4TS U4842 ( .A(n3766), .B(n3264), .Y(n3796) ); NAND2X2TS U4843 ( .A(n2555), .B(n4672), .Y(n4117) ); INVX16TS U4844 ( .A(n2981), .Y(n5046) ); BUFX6TS U4845 ( .A(intDY_EWSW[33]), .Y(n2945) ); OAI21X4TS U4846 ( .A0(n3502), .A1(n3501), .B0(n3500), .Y(n3503) ); OAI22X2TS U4847 ( .A0(n4718), .A1(n4325), .B0(n4702), .B1(n1918), .Y(n3866) ); NAND2X8TS U4848 ( .A(n2949), .B(n4927), .Y(n4988) ); BUFX20TS U4849 ( .A(n5046), .Y(n6205) ); AOI22X4TS U4850 ( .A0(n2519), .A1(n5141), .B0(n2938), .B1(n5158), .Y(n6416) ); NOR2X2TS U4851 ( .A(n3801), .B(n3800), .Y(n3811) ); XOR2X4TS U4852 ( .A(DmP_mant_SFG_SWR[47]), .B(n2487), .Y(n3876) ); AOI22X4TS U4853 ( .A0(n2519), .A1(n5136), .B0(n2022), .B1(n5158), .Y(n6414) ); NAND2X6TS U4854 ( .A(n4602), .B(n4601), .Y(n4692) ); AOI22X2TS U4855 ( .A0(n6219), .A1(Raw_mant_NRM_SWR[32]), .B0(n6199), .B1( DmP_mant_SHT1_SW[17]), .Y(n6296) ); AOI22X2TS U4856 ( .A0(n6218), .A1(Raw_mant_NRM_SWR[8]), .B0(n6199), .B1( DmP_mant_SHT1_SW[41]), .Y(n6380) ); AOI21X4TS U4857 ( .A0(n2286), .A1(n2843), .B0(n3994), .Y(n3991) ); NAND2X2TS U4858 ( .A(n3358), .B(intDY_EWSW[39]), .Y(n3526) ); NOR2X4TS U4859 ( .A(n3316), .B(n2957), .Y(n3507) ); NAND2X2TS U4860 ( .A(n2529), .B(n5060), .Y(n3722) ); NAND2X2TS U4861 ( .A(n3304), .B(intDY_EWSW[29]), .Y(n3491) ); NAND3X2TS U4862 ( .A(n6082), .B(n6081), .C(n6080), .Y(n3851) ); NAND2X2TS U4863 ( .A(n3846), .B(n5016), .Y(n4081) ); NAND3X2TS U4864 ( .A(n6093), .B(n6092), .C(n6091), .Y(n3940) ); AOI22X4TS U4865 ( .A0(n4603), .A1(n2522), .B0(n5158), .B1(n5153), .Y(n5268) ); AOI22X4TS U4866 ( .A0(n5155), .A1(n5151), .B0(n2516), .B1(n5150), .Y(n6435) ); NAND2X2TS U4867 ( .A(n3305), .B(intDY_EWSW[47]), .Y(n3541) ); NAND2X2TS U4868 ( .A(n4612), .B(n5155), .Y(n4613) ); AND3X2TS U4869 ( .A(n5909), .B(n5908), .C(n5907), .Y(n3937) ); AND2X8TS U4870 ( .A(n3011), .B(n2273), .Y(n3009) ); OA21X4TS U4871 ( .A0(n3022), .A1(n5487), .B0(n4319), .Y(n4320) ); NAND4X4TS U4872 ( .A(n4583), .B(n3130), .C(n4582), .D(n4581), .Y(n4014) ); OAI21X4TS U4873 ( .A0(n2947), .A1(n2309), .B0(n3986), .Y(n3977) ); NAND2X4TS U4874 ( .A(n3998), .B(n5435), .Y(n3995) ); NAND2X2TS U4875 ( .A(n3292), .B(intDY_EWSW[27]), .Y(n3486) ); CLKINVX6TS U4876 ( .A(n5017), .Y(n4654) ); MXI2X2TS U4877 ( .A(n5293), .B(n5548), .S0(n5265), .Y(n1018) ); NAND2X2TS U4878 ( .A(n5060), .B(n3846), .Y(n3807) ); MXI2X2TS U4879 ( .A(n5268), .B(n5267), .S0(n5264), .Y(n1127) ); NAND2X2TS U4880 ( .A(n5046), .B(Raw_mant_NRM_SWR[0]), .Y(n4437) ); XNOR2X4TS U4881 ( .A(n5548), .B(n2257), .Y(n3894) ); AOI22X4TS U4882 ( .A0(n4512), .A1(n1878), .B0(Data_array_SWR_3__53_), .B1( n5274), .Y(n5288) ); CLKINVX12TS U4883 ( .A(n3795), .Y(n3771) ); NAND2X2TS U4884 ( .A(n3343), .B(intDY_EWSW[35]), .Y(n3521) ); AOI22X4TS U4885 ( .A0(n4061), .A1(n2522), .B0(n5158), .B1(n5150), .Y(n4094) ); OAI21X2TS U4886 ( .A0(n4662), .A1(n5050), .B0(n4086), .Y(n4089) ); OAI21X4TS U4887 ( .A0(n2955), .A1(n5089), .B0(n2954), .Y(n1152) ); NOR2X6TS U4888 ( .A(n3395), .B(DMP_SFG[35]), .Y(n4948) ); NAND2X2TS U4889 ( .A(n3300), .B(intDY_EWSW[28]), .Y(n3492) ); BUFX6TS U4890 ( .A(intDY_EWSW[32]), .Y(n2957) ); NOR2X6TS U4891 ( .A(n3383), .B(DMP_SFG[19]), .Y(n5076) ); NAND2BX2TS U4892 ( .AN(n2958), .B(n4115), .Y(n1302) ); AOI21X4TS U4893 ( .A0(n3499), .A1(n3498), .B0(n3497), .Y(n3500) ); NOR2X2TS U4894 ( .A(n3300), .B(intDY_EWSW[28]), .Y(n3463) ); NAND3X2TS U4895 ( .A(n4515), .B(n4514), .C(n4513), .Y(n1140) ); BUFX20TS U4896 ( .A(n3125), .Y(n2963) ); OAI21X4TS U4897 ( .A0(n3456), .A1(n3455), .B0(n3454), .Y(n3457) ); NAND2X2TS U4898 ( .A(n3353), .B(intDY_EWSW[10]), .Y(n3440) ); NOR2X2TS U4899 ( .A(n3768), .B(n4269), .Y(n3769) ); NAND2X2TS U4900 ( .A(n3293), .B(intDY_EWSW[43]), .Y(n3532) ); XOR2X4TS U4901 ( .A(DmP_mant_SFG_SWR[43]), .B(n2487), .Y(n3403) ); CLKXOR2X4TS U4902 ( .A(n1839), .B(DmP_mant_SFG_SWR[20]), .Y(n3382) ); XOR2X4TS U4903 ( .A(DmP_mant_SFG_SWR[24]), .B(n2487), .Y(n3386) ); OR3X4TS U4904 ( .A(n4052), .B(n4051), .C(n4050), .Y(n5044) ); NAND4X4TS U4905 ( .A(n3856), .B(n3855), .C(n6151), .D(n3854), .Y(n4322) ); NAND3X2TS U4906 ( .A(n4788), .B(n4789), .C(n4787), .Y(n1201) ); NOR2X8TS U4907 ( .A(n2391), .B(n3098), .Y(n3097) ); MXI2X4TS U4908 ( .A(n5261), .B(n5521), .S0(n2554), .Y(n1046) ); BUFX3TS U4909 ( .A(intDY_EWSW[31]), .Y(n2961) ); BUFX20TS U4910 ( .A(n4790), .Y(n4838) ); AOI21X2TS U4911 ( .A0(n4253), .A1(n5439), .B0(Raw_mant_NRM_SWR[11]), .Y( n3764) ); OAI22X2TS U4912 ( .A0(n1916), .A1(n3320), .B0(n5289), .B1(n5541), .Y(n1094) ); NOR2X1TS U4913 ( .A(n4669), .B(n4521), .Y(n4522) ); OAI22X2TS U4914 ( .A0(n2990), .A1(n5290), .B0(n5289), .B1(n5506), .Y(n1067) ); NAND3X2TS U4915 ( .A(n4875), .B(n4876), .C(n4874), .Y(n1586) ); NAND3X2TS U4916 ( .A(n4847), .B(n4848), .C(n4846), .Y(n1270) ); NAND3X2TS U4917 ( .A(n4844), .B(n4845), .C(n4843), .Y(n1274) ); NAND3X2TS U4918 ( .A(n4850), .B(n4851), .C(n4849), .Y(n1212) ); NAND3X2TS U4919 ( .A(n4836), .B(n4837), .C(n4835), .Y(n1210) ); AOI22X4TS U4920 ( .A0(n5147), .A1(n5154), .B0(n2518), .B1(n5153), .Y(n6442) ); BUFX6TS U4921 ( .A(intDY_EWSW[27]), .Y(n2964) ); NAND3X6TS U4922 ( .A(n3577), .B(n3576), .C(n3575), .Y(n1226) ); XOR2X4TS U4923 ( .A(n4744), .B(n4743), .Y(n4745) ); XOR2X4TS U4924 ( .A(n4761), .B(n4760), .Y(n4762) ); XOR2X4TS U4925 ( .A(n5080), .B(n5079), .Y(n5081) ); NAND2BX4TS U4926 ( .AN(n2446), .B(n4103), .Y(n2965) ); OAI2BB1X4TS U4927 ( .A0N(n5161), .A1N(n6439), .B0(n5160), .Y(n1049) ); INVX12TS U4928 ( .A(n2977), .Y(n3149) ); AOI21X2TS U4929 ( .A0(n3788), .A1(n3787), .B0(n3786), .Y(n3792) ); OAI21X4TS U4930 ( .A0(n3792), .A1(n3791), .B0(n3790), .Y(n3194) ); NOR2X2TS U4931 ( .A(n4026), .B(n2971), .Y(n2970) ); NOR2X2TS U4932 ( .A(n4026), .B(n2976), .Y(n2975) ); XOR2X4TS U4933 ( .A(DmP_mant_SFG_SWR[48]), .B(n2257), .Y(n3879) ); OAI21X4TS U4934 ( .A0(n2648), .A1(n5579), .B0(n4068), .Y(n6392) ); OAI21X4TS U4935 ( .A0(n2648), .A1(n5009), .B0(n5008), .Y(n6409) ); NOR2BX4TS U4936 ( .AN(n4301), .B(n2995), .Y(n2994) ); NAND2BX4TS U4937 ( .AN(n5699), .B(n2999), .Y(n4331) ); AOI21X4TS U4938 ( .A0(n3012), .A1(n3009), .B0(n3006), .Y(n3571) ); AOI21X4TS U4939 ( .A0(n3570), .A1(n3569), .B0(n3568), .Y(n3007) ); AND2X8TS U4940 ( .A(n3569), .B(n3518), .Y(n3011) ); OAI21X4TS U4941 ( .A0(n3015), .A1(n3014), .B0(n3013), .Y(n3012) ); AOI21X4TS U4942 ( .A0(n3505), .A1(n3504), .B0(n3503), .Y(n3013) ); AOI21X4TS U4943 ( .A0(n3459), .A1(n3458), .B0(n3457), .Y(n3015) ); INVX12TS U4944 ( .A(n3214), .Y(n3396) ); NAND2X8TS U4945 ( .A(n3017), .B(n3016), .Y(n3214) ); XOR2X4TS U4946 ( .A(n1853), .B(DmP_mant_SFG_SWR[37]), .Y(n3395) ); XOR2X4TS U4947 ( .A(n1854), .B(DmP_mant_SFG_SWR[36]), .Y(n3394) ); OAI21X4TS U4948 ( .A0(n3561), .A1(n3021), .B0(n3020), .Y(n3564) ); NAND2BX4TS U4949 ( .AN(n3029), .B(n5437), .Y(n3028) ); XNOR2X4TS U4950 ( .A(n3030), .B(n5303), .Y(n5304) ); NAND2BX4TS U4951 ( .AN(n3330), .B(n5556), .Y(n3032) ); NAND2BX4TS U4952 ( .AN(n5311), .B(n2443), .Y(n3033) ); NOR2X8TS U4953 ( .A(n3040), .B(n3795), .Y(n3039) ); NAND3X8TS U4954 ( .A(n3052), .B(n3049), .C(n3048), .Y(n4523) ); NAND2BX4TS U4955 ( .AN(n3959), .B(n3055), .Y(n4699) ); OAI2BB1X4TS U4956 ( .A0N(n4691), .A1N(n5151), .B0(n3059), .Y(n3058) ); OAI2BB1X4TS U4957 ( .A0N(n3060), .A1N(n4483), .B0(n4711), .Y(n3059) ); NAND3BX4TS U4958 ( .AN(n3061), .B(n4485), .C(n4484), .Y(n5151) ); OAI21X4TS U4959 ( .A0(n5257), .A1(n5218), .B0(n3063), .Y(n1047) ); INVX12TS U4960 ( .A(n4931), .Y(n3069) ); NAND2BX4TS U4961 ( .AN(n2826), .B(n3867), .Y(n3071) ); NOR2BX4TS U4962 ( .AN(n3074), .B(n3866), .Y(n3073) ); OAI2BB1X4TS U4963 ( .A0N(n5841), .A1N(n5840), .B0(n3075), .Y(n3827) ); OAI21X4TS U4964 ( .A0(n5309), .A1(n5305), .B0(n5306), .Y(n3408) ); NAND2BX4TS U4965 ( .AN(n5556), .B(n3330), .Y(n5297) ); OR2X8TS U4966 ( .A(n2331), .B(shift_value_SHT2_EWR[4]), .Y(n4293) ); NOR2X8TS U4967 ( .A(n2524), .B(n3571), .Y(n3123) ); NAND4BX4TS U4968 ( .AN(n3842), .B(n3840), .C(n3841), .D(n3088), .Y(n4672) ); AOI21X4TS U4969 ( .A0(n5917), .A1(n4047), .B0(n5916), .Y(n3088) ); AOI22X4TS U4970 ( .A0(n4635), .A1(n2449), .B0(n4692), .B1(n5158), .Y(n5248) ); AOI22X4TS U4971 ( .A0(n5145), .A1(n2938), .B0(n2517), .B1(n5141), .Y(n6460) ); NAND2BX4TS U4972 ( .AN(n3095), .B(n3849), .Y(n3094) ); NAND2X8TS U4973 ( .A(n3097), .B(n2433), .Y(n5140) ); OAI21X4TS U4974 ( .A0(n5255), .A1(n5218), .B0(n3101), .Y(n1045) ); AOI2BB2X4TS U4975 ( .B0(n4651), .B1(n2522), .A0N(n3107), .A1N(n3106), .Y( n5251) ); NAND2X8TS U4976 ( .A(n3108), .B(n4328), .Y(n4651) ); AOI22X4TS U4977 ( .A0(n4619), .A1(n2522), .B0(n4618), .B1(n5155), .Y(n5249) ); NAND2X8TS U4978 ( .A(n2261), .B(n1951), .Y(n3858) ); INVX16TS U4979 ( .A(n3110), .Y(n4669) ); AND2X8TS U4980 ( .A(n2993), .B(n1951), .Y(n3365) ); AOI21X4TS U4981 ( .A0(n4667), .A1(n4711), .B0(n3115), .Y(n3114) ); NOR2BX4TS U4982 ( .AN(n4475), .B(n2430), .Y(n3117) ); NOR2X8TS U4983 ( .A(n3376), .B(DMP_exp_NRM2_EW[3]), .Y(n3987) ); NAND2BX4TS U4984 ( .AN(n4585), .B(n3120), .Y(n5163) ); XOR2X4TS U4985 ( .A(n3993), .B(DMP_exp_NRM2_EW[8]), .Y(n5166) ); BUFX20TS U4986 ( .A(n3087), .Y(n3124) ); NOR2X8TS U4987 ( .A(n3126), .B(n4014), .Y(n3127) ); AOI22X4TS U4988 ( .A0(n4635), .A1(n1878), .B0(n4692), .B1(n3365), .Y(n5063) ); NAND3BX4TS U4989 ( .AN(n3142), .B(n6155), .C(n3141), .Y(n3140) ); OAI2BB1X4TS U4990 ( .A0N(n6098), .A1N(n6099), .B0(n6097), .Y(n3715) ); AND2X8TS U4991 ( .A(n3148), .B(n3146), .Y(n6456) ); INVX12TS U4992 ( .A(n3235), .Y(n3242) ); NAND3BX4TS U4993 ( .AN(n3150), .B(n4530), .C(n4529), .Y(n4721) ); NAND2X2TS U4994 ( .A(n4649), .B(n5158), .Y(n3163) ); OAI21X4TS U4995 ( .A0(n4983), .A1(n4978), .B0(n4984), .Y(n4932) ); NAND2X8TS U4996 ( .A(n3165), .B(n3164), .Y(n4910) ); AOI21X4TS U4997 ( .A0(n4932), .A1(n3393), .B0(n3282), .Y(n3164) ); NAND3X2TS U4998 ( .A(n4879), .B(n4880), .C(n4878), .Y(n1585) ); NAND3X2TS U4999 ( .A(n4861), .B(n4862), .C(n4860), .Y(n1268) ); NAND3X2TS U5000 ( .A(n4799), .B(n4800), .C(n4798), .Y(n1252) ); NAND3X2TS U5001 ( .A(n4796), .B(n4797), .C(n4795), .Y(n1242) ); NAND3X2TS U5002 ( .A(n4812), .B(n4813), .C(n4811), .Y(n1240) ); NAND3X2TS U5003 ( .A(n4832), .B(n4833), .C(n4831), .Y(n1262) ); NAND3X2TS U5004 ( .A(n4793), .B(n4794), .C(n4792), .Y(n1250) ); NAND3X2TS U5005 ( .A(n4805), .B(n4806), .C(n4804), .Y(n1246) ); NAND3X2TS U5006 ( .A(n4815), .B(n4816), .C(n4814), .Y(n1238) ); NAND3X2TS U5007 ( .A(n4802), .B(n4803), .C(n4801), .Y(n1244) ); NAND3X2TS U5008 ( .A(n4818), .B(n4819), .C(n4817), .Y(n1248) ); NAND3X2TS U5009 ( .A(n4855), .B(n4856), .C(n4854), .Y(n1260) ); NAND3X2TS U5010 ( .A(n4821), .B(n4822), .C(n4820), .Y(n1236) ); CLKINVX6TS U5011 ( .A(n3796), .Y(n4271) ); XOR2X4TS U5012 ( .A(n1839), .B(DmP_mant_SFG_SWR[16]), .Y(n5317) ); NAND2X4TS U5013 ( .A(n6443), .B(n5149), .Y(n4478) ); NAND4BX4TS U5014 ( .AN(n3703), .B(n3702), .C(n3701), .D(n6183), .Y(n4657) ); NOR2X2TS U5015 ( .A(Raw_mant_NRM_SWR[6]), .B(n5419), .Y(n3744) ); NAND4X4TS U5016 ( .A(n3180), .B(n3274), .C(n3177), .D(n3176), .Y(n1151) ); XOR2X4TS U5017 ( .A(DmP_mant_SFG_SWR[17]), .B(n1839), .Y(n3183) ); NAND2BX4TS U5018 ( .AN(DMP_SFG[39]), .B(n3184), .Y(n3185) ); NOR2BX4TS U5019 ( .AN(n3191), .B(n4245), .Y(n3190) ); NAND2X8TS U5020 ( .A(n2427), .B(n4069), .Y(n3922) ); NOR3X8TS U5021 ( .A(n3200), .B(n3199), .C(n3198), .Y(n4352) ); NOR2BX4TS U5022 ( .AN(n3253), .B(n2748), .Y(n3198) ); NOR2X8TS U5023 ( .A(n2850), .B(n3750), .Y(n3299) ); XOR2X4TS U5024 ( .A(n3205), .B(n4942), .Y(n3204) ); OAI21X4TS U5025 ( .A0(n2362), .A1(n4938), .B0(n3206), .Y(n3205) ); NAND2X8TS U5026 ( .A(n4910), .B(n3396), .Y(n3216) ); NAND2XLTS U5027 ( .A(n2551), .B(Raw_mant_NRM_SWR[52]), .Y(n3217) ); XOR2X4TS U5028 ( .A(DmP_mant_SFG_SWR[21]), .B(n6161), .Y(n3383) ); NAND3X2TS U5029 ( .A(n2284), .B(n3877), .C(n3227), .Y(n3223) ); NAND2X2TS U5030 ( .A(n3877), .B(n3225), .Y(n3224) ); NOR2X8TS U5031 ( .A(n3230), .B(n2448), .Y(n3229) ); NAND2X8TS U5032 ( .A(n3242), .B(n3236), .Y(n3238) ); OAI22X4TS U5033 ( .A0(n6412), .A1(n3239), .B0(n5012), .B1(n6231), .Y(n6413) ); NAND2X8TS U5034 ( .A(n3240), .B(n4261), .Y(n4274) ); OR2X8TS U5035 ( .A(n4891), .B(n5491), .Y(n4890) ); XOR2X4TS U5036 ( .A(n2298), .B(n6161), .Y(n3874) ); NAND2X8TS U5037 ( .A(n3745), .B(n3250), .Y(n4267) ); AOI21X4TS U5038 ( .A0(n5082), .A1(n2406), .B0(n3388), .Y(n3257) ); NOR2X8TS U5039 ( .A(n3258), .B(n4348), .Y(n3264) ); XOR2X4TS U5040 ( .A(DmP_mant_SFG_SWR[41]), .B(n2487), .Y(n3400) ); XOR2X4TS U5041 ( .A(DmP_mant_SFG_SWR[40]), .B(n6161), .Y(n3399) ); XOR2X4TS U5042 ( .A(DmP_mant_SFG_SWR[27]), .B(n1839), .Y(n3390) ); OAI21X4TS U5043 ( .A0(n3276), .A1(n5319), .B0(n3277), .Y(n1156) ); OAI21X4TS U5044 ( .A0(n4955), .A1(n4939), .B0(n4940), .Y(n3282) ); NAND2BX4TS U5045 ( .AN(n4141), .B(n3287), .Y(n3284) ); AND2X8TS U5046 ( .A(n2262), .B(n3372), .Y(n4473) ); OAI21X4TS U5047 ( .A0(n3543), .A1(n3542), .B0(n3541), .Y(n3544) ); OAI21X4TS U5048 ( .A0(n3447), .A1(n3446), .B0(n3445), .Y(n3453) ); OAI21X2TS U5049 ( .A0(n4662), .A1(n5049), .B0(n4048), .Y(n4055) ); NOR2X2TS U5050 ( .A(n4669), .B(n4666), .Y(n4595) ); CLKINVX3TS U5051 ( .A(n5039), .Y(n4666) ); NAND2X4TS U5052 ( .A(n3982), .B(n3981), .Y(n3983) ); NOR2X2TS U5053 ( .A(n3833), .B(n4684), .Y(n4323) ); NAND2X8TS U5054 ( .A(n6408), .B(n5019), .Y(n5032) ); OAI21X4TS U5055 ( .A0(n3987), .A1(n3986), .B0(n3985), .Y(n3988) ); NOR2X4TS U5056 ( .A(n4283), .B(n4282), .Y(n4285) ); NAND2X4TS U5057 ( .A(n4277), .B(n1825), .Y(n4351) ); AOI21X4TS U5058 ( .A0(n3478), .A1(n3479), .B0(n3477), .Y(n3480) ); NOR3X4TS U5059 ( .A(n4648), .B(n4647), .C(n4646), .Y(n5246) ); AND2X4TS U5060 ( .A(n4645), .B(n1872), .Y(n4647) ); OR2X4TS U5061 ( .A(n2523), .B(n2346), .Y(n6374) ); OR2X4TS U5062 ( .A(n2523), .B(n5570), .Y(n6362) ); OR2X4TS U5063 ( .A(n6213), .B(n5573), .Y(n6402) ); OR2X4TS U5064 ( .A(n6213), .B(n5581), .Y(n6343) ); MX2X4TS U5065 ( .A(n4957), .B(n1825), .S0(n5205), .Y(n1164) ); AOI22X2TS U5066 ( .A0(n6204), .A1(DmP_mant_SHT1_SW[49]), .B0(n6199), .B1( DmP_mant_SHT1_SW[48]), .Y(n6336) ); NAND4BX4TS U5067 ( .AN(n3712), .B(n3711), .C(n3710), .D(n6162), .Y(n4636) ); NAND4X4TS U5068 ( .A(n3953), .B(n3952), .C(n3951), .D(n3950), .Y(n4333) ); XOR2X4TS U5069 ( .A(n2362), .B(n4738), .Y(n4739) ); NAND4X4TS U5070 ( .A(n6138), .B(n4024), .C(n4023), .D(n4022), .Y(n4049) ); NAND2X2TS U5071 ( .A(n6219), .B(Raw_mant_NRM_SWR[38]), .Y(n6330) ); NAND2X2TS U5072 ( .A(n6218), .B(n2252), .Y(n6308) ); NAND2X1TS U5073 ( .A(n5091), .B(n5094), .Y(n5092) ); NAND4X4TS U5074 ( .A(n3812), .B(n3811), .C(n3810), .D(n3809), .Y(n6443) ); NOR2X2TS U5075 ( .A(n3799), .B(n3798), .Y(n3812) ); NAND4BX4TS U5076 ( .AN(n3721), .B(n3720), .C(n3719), .D(n6159), .Y(n5060) ); NAND4BX4TS U5077 ( .AN(n3718), .B(n3717), .C(n3716), .D(n6157), .Y(n5055) ); XOR2X4TS U5078 ( .A(n5864), .B(n1840), .Y(n3379) ); NAND4BX4TS U5079 ( .AN(n3962), .B(n3961), .C(n3960), .D(n6171), .Y(n5038) ); OR2X4TS U5080 ( .A(n6213), .B(n5342), .Y(n6310) ); OAI22X2TS U5081 ( .A0(n4893), .A1(n5426), .B0(n4892), .B1(n2474), .Y(n4894) ); OR2X4TS U5082 ( .A(n2523), .B(n5422), .Y(n5430) ); MX2X4TS U5083 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n2563), .Y(n1351) ); BUFX20TS U5084 ( .A(n5027), .Y(n6217) ); NAND2X4TS U5085 ( .A(n4658), .B(n1644), .Y(n4289) ); NOR2X2TS U5086 ( .A(n3833), .B(n4535), .Y(n4516) ); AOI2BB2X4TS U5087 ( .B0(n5888), .B1(n2134), .A0N(n5887), .A1N(n5886), .Y( n4035) ); NAND2X2TS U5088 ( .A(n3978), .B(n3986), .Y(n3979) ); NAND4X4TS U5089 ( .A(n4504), .B(n4503), .C(n4502), .D(n4501), .Y(n6452) ); NOR2X2TS U5090 ( .A(n4500), .B(n4499), .Y(n4502) ); OAI21X2TS U5091 ( .A0(n2252), .A1(n5341), .B0(n5427), .Y(n3758) ); NOR2X8TS U5092 ( .A(Raw_mant_NRM_SWR[19]), .B(n2252), .Y(n3772) ); BUFX20TS U5093 ( .A(n3858), .Y(n4689) ); NOR2X2TS U5094 ( .A(n4125), .B(n4124), .Y(n4129) ); NAND4X4TS U5095 ( .A(n4541), .B(n4540), .C(n4539), .D(n4538), .Y(n6446) ); NAND3X6TS U5096 ( .A(n3771), .B(n3793), .C(n3770), .Y(n4273) ); MXI2X4TS U5097 ( .A(n5276), .B(n4670), .S0(n1876), .Y(n5273) ); NAND4BX4TS U5098 ( .AN(n3700), .B(n3699), .C(n3698), .D(n3697), .Y(n5021) ); INVX4TS U5099 ( .A(n4258), .Y(n3745) ); NOR2X8TS U5100 ( .A(Raw_mant_NRM_SWR[12]), .B(Raw_mant_NRM_SWR[11]), .Y( n3782) ); NOR2X8TS U5101 ( .A(n3795), .B(n4268), .Y(n4343) ); NAND2X4TS U5102 ( .A(n4626), .B(n4625), .Y(n4630) ); NAND4X4TS U5103 ( .A(n3865), .B(n3864), .C(n6194), .D(n3863), .Y(n5045) ); NOR3X4TS U5104 ( .A(n5843), .B(n5842), .C(n3862), .Y(n3865) ); XOR2X4TS U5105 ( .A(n3991), .B(DMP_exp_NRM2_EW[6]), .Y(n3992) ); OR2X4TS U5106 ( .A(n6213), .B(n5427), .Y(n6322) ); OR2X4TS U5107 ( .A(n6213), .B(n5423), .Y(n6357) ); OR2X4TS U5108 ( .A(n6213), .B(n5491), .Y(n6347) ); OR2X4TS U5109 ( .A(n6213), .B(n1857), .Y(n6335) ); OR2X4TS U5110 ( .A(n6213), .B(n5433), .Y(n6378) ); NAND2X2TS U5111 ( .A(n4508), .B(n4509), .Y(n1033) ); NAND4BX4TS U5112 ( .AN(n3826), .B(n3825), .C(n3824), .D(n3823), .Y(n1635) ); NOR2X8TS U5113 ( .A(Raw_mant_NRM_SWR[13]), .B(Raw_mant_NRM_SWR[10]), .Y( n3743) ); XNOR2X4TS U5114 ( .A(n3977), .B(n3976), .Y(n5174) ); NAND2X2TS U5115 ( .A(n3975), .B(n3985), .Y(n3976) ); XOR2X4TS U5116 ( .A(n3996), .B(DMP_exp_NRM2_EW[7]), .Y(n5172) ); OR2X8TS U5117 ( .A(n3385), .B(DMP_SFG[21]), .Y(n3295) ); CLKBUFX3TS U5118 ( .A(n6290), .Y(n4462) ); CLKBUFX3TS U5119 ( .A(n6254), .Y(n6288) ); CLKBUFX3TS U5120 ( .A(n6288), .Y(n6290) ); INVX2TS U5121 ( .A(n5000), .Y(n3881) ); NAND2X4TS U5122 ( .A(n3275), .B(n4912), .Y(n4914) ); NAND2X4TS U5123 ( .A(n3275), .B(n2759), .Y(n4783) ); NAND2X2TS U5124 ( .A(n3379), .B(DMP_SFG[17]), .Y(n5069) ); NAND2X2TS U5125 ( .A(n3368), .B(n3883), .Y(n3880) ); NOR2XLTS U5126 ( .A(n4669), .B(n4696), .Y(n4302) ); NAND2X1TS U5127 ( .A(n4439), .B(n2745), .Y(n3642) ); CLKBUFX3TS U5128 ( .A(n6233), .Y(n4465) ); BUFX3TS U5129 ( .A(n4465), .Y(n6238) ); INVX2TS U5130 ( .A(DmP_mant_SHT1_SW[30]), .Y(n5601) ); CLKBUFX3TS U5131 ( .A(n4466), .Y(n5655) ); CLKBUFX2TS U5132 ( .A(n6286), .Y(n5620) ); CLKBUFX3TS U5133 ( .A(n2521), .Y(n5680) ); CLKBUFX3TS U5134 ( .A(n4462), .Y(n5649) ); CLKBUFX3TS U5135 ( .A(n6286), .Y(n5629) ); CLKBUFX3TS U5136 ( .A(n4462), .Y(n5646) ); BUFX3TS U5137 ( .A(n5655), .Y(n6275) ); BUFX3TS U5138 ( .A(n4465), .Y(n6241) ); XOR2X4TS U5139 ( .A(n6161), .B(DmP_mant_SFG_SWR[38]), .Y(n3397) ); NOR2X8TS U5140 ( .A(n4918), .B(n4926), .Y(n4989) ); NOR2X8TS U5141 ( .A(n3399), .B(DMP_SFG[38]), .Y(n4993) ); NOR2X8TS U5142 ( .A(n3389), .B(DMP_SFG[23]), .Y(n4747) ); NOR2X8TS U5143 ( .A(n4747), .B(n4748), .Y(n4763) ); NOR2X8TS U5144 ( .A(n3382), .B(DMP_SFG[18]), .Y(n4734) ); NAND2X8TS U5145 ( .A(n3382), .B(DMP_SFG[18]), .Y(n5073) ); NAND2X1TS U5150 ( .A(n3331), .B(DMP_EXP_EWSW[53]), .Y(n5310) ); NOR2X2TS U5151 ( .A(n3354), .B(DMP_EXP_EWSW[55]), .Y(n5300) ); NOR2X1TS U5152 ( .A(n5488), .B(DMP_EXP_EWSW[56]), .Y(n5305) ); NAND2X1TS U5153 ( .A(n5496), .B(DMP_EXP_EWSW[57]), .Y(n3406) ); NOR2X4TS U5154 ( .A(n3424), .B(n3419), .Y(n3421) ); OAI21X4TS U5155 ( .A0(n3424), .A1(n3423), .B0(n3422), .Y(n3429) ); OR2X4TS U5156 ( .A(n3377), .B(intDY_EWSW[62]), .Y(n3563) ); AND2X2TS U5157 ( .A(n3377), .B(intDY_EWSW[62]), .Y(n3562) ); NAND2X2TS U5158 ( .A(n2963), .B(intDX_EWSW[12]), .Y(n3574) ); NAND2X1TS U5159 ( .A(n2534), .B(DmP_EXP_EWSW[12]), .Y(n3572) ); NAND3X2TS U5160 ( .A(n3573), .B(n3574), .C(n3572), .Y(n1286) ); NAND2X2TS U5161 ( .A(n1838), .B(intDX_EWSW[42]), .Y(n3577) ); BUFX4TS U5162 ( .A(n5495), .Y(n4839) ); NAND2X1TS U5163 ( .A(n4839), .B(DmP_EXP_EWSW[42]), .Y(n3575) ); NAND2X2TS U5164 ( .A(n2530), .B(intDX_EWSW[44]), .Y(n3580) ); NAND2X1TS U5165 ( .A(n4839), .B(DmP_EXP_EWSW[44]), .Y(n3578) ); NAND2X2TS U5166 ( .A(n2041), .B(intDX_EWSW[47]), .Y(n3583) ); NAND2X1TS U5167 ( .A(n4369), .B(n2045), .Y(n3582) ); NAND2X1TS U5168 ( .A(n4839), .B(DmP_EXP_EWSW[43]), .Y(n3584) ); NAND2X1TS U5169 ( .A(n2535), .B(DMP_EXP_EWSW[59]), .Y(n3588) ); NAND2X2TS U5170 ( .A(n2530), .B(intDY_EWSW[40]), .Y(n3593) ); NAND2X2TS U5171 ( .A(n2526), .B(n1922), .Y(n3596) ); NAND3X2TS U5172 ( .A(n3595), .B(n3596), .C(n3594), .Y(n1541) ); NAND2X2TS U5173 ( .A(n3630), .B(n2740), .Y(n3599) ); NAND2X2TS U5174 ( .A(n2531), .B(n2026), .Y(n3602) ); NAND3X2TS U5175 ( .A(n3601), .B(n3602), .C(n3600), .Y(n1546) ); NAND2X2TS U5176 ( .A(n1836), .B(n2299), .Y(n3605) ); NAND3X2TS U5177 ( .A(n3604), .B(n3605), .C(n3603), .Y(n1542) ); NAND2X2TS U5178 ( .A(n2041), .B(n2051), .Y(n3608) ); NAND2X1TS U5179 ( .A(n4873), .B(intDX_EWSW[43]), .Y(n3607) ); NAND3X2TS U5180 ( .A(n3608), .B(n3607), .C(n3606), .Y(n1544) ); NAND2X2TS U5181 ( .A(n2526), .B(intDY_EWSW[44]), .Y(n3611) ); NAND3X2TS U5182 ( .A(n3610), .B(n3611), .C(n3609), .Y(n1543) ); NAND2X2TS U5183 ( .A(n2530), .B(n1815), .Y(n3614) ); NAND3X2TS U5184 ( .A(n3613), .B(n3614), .C(n3612), .Y(n1545) ); NAND2X1TS U5185 ( .A(n2053), .B(intDX_EWSW[38]), .Y(n3616) ); NAND2X2TS U5186 ( .A(n2531), .B(intDY_EWSW[39]), .Y(n3620) ); NAND3X2TS U5187 ( .A(n3619), .B(n3620), .C(n3618), .Y(n1548) ); NAND2X2TS U5188 ( .A(n2531), .B(intDY_EWSW[36]), .Y(n3623) ); NAND3X2TS U5189 ( .A(n3622), .B(n3623), .C(n3621), .Y(n1551) ); NAND2X2TS U5190 ( .A(n4424), .B(n2940), .Y(n3626) ); NAND3X2TS U5191 ( .A(n3625), .B(n3626), .C(n3624), .Y(n1552) ); NAND2X2TS U5192 ( .A(n1838), .B(n2945), .Y(n3629) ); NAND3X2TS U5193 ( .A(n3628), .B(n3629), .C(n3627), .Y(n1554) ); NAND2X2TS U5194 ( .A(n2530), .B(intDY_EWSW[37]), .Y(n3633) ); NAND3X2TS U5195 ( .A(n3632), .B(n3633), .C(n3631), .Y(n1550) ); NAND2X1TS U5196 ( .A(n2526), .B(n2479), .Y(n3636) ); NAND3X2TS U5197 ( .A(n3636), .B(n3635), .C(n3634), .Y(n1566) ); NAND3X2TS U5198 ( .A(n3639), .B(n3638), .C(n3637), .Y(n1565) ); NAND3X2TS U5199 ( .A(n3642), .B(n3641), .C(n3640), .Y(n1559) ); NAND2X2TS U5200 ( .A(n3124), .B(intDY_EWSW[30]), .Y(n3645) ); NAND2X2TS U5201 ( .A(n4426), .B(DMP_EXP_EWSW[30]), .Y(n3643) ); NAND2X2TS U5202 ( .A(n1838), .B(n2957), .Y(n3648) ); NAND2X2TS U5203 ( .A(n4424), .B(intDY_EWSW[29]), .Y(n3651) ); NAND3X2TS U5204 ( .A(n3650), .B(n3651), .C(n3649), .Y(n1558) ); NAND2X2TS U5205 ( .A(n1838), .B(n2961), .Y(n3655) ); NAND3X2TS U5206 ( .A(n3654), .B(n3655), .C(n3653), .Y(n1556) ); NAND2X2TS U5207 ( .A(n3124), .B(n2964), .Y(n3658) ); NAND3X2TS U5208 ( .A(n3657), .B(n3658), .C(n3656), .Y(n1560) ); NAND2X1TS U5209 ( .A(n2525), .B(DMP_EXP_EWSW[16]), .Y(n3662) ); NAND3X2TS U5210 ( .A(n3664), .B(n3663), .C(n3662), .Y(n1571) ); NAND2X1TS U5211 ( .A(n2525), .B(DMP_EXP_EWSW[15]), .Y(n3665) ); NAND3X2TS U5212 ( .A(n3666), .B(n3667), .C(n3665), .Y(n1572) ); NAND2X1TS U5213 ( .A(n2525), .B(DMP_EXP_EWSW[17]), .Y(n3668) ); NAND2X1TS U5214 ( .A(n2525), .B(DMP_EXP_EWSW[18]), .Y(n3671) ); NAND3X2TS U5215 ( .A(n3675), .B(n3676), .C(n3674), .Y(n1567) ); NAND2X1TS U5216 ( .A(n2524), .B(DMP_EXP_EWSW[61]), .Y(n3677) ); NAND2X2TS U5217 ( .A(n4430), .B(intDX_EWSW[40]), .Y(n3685) ); NAND2X2TS U5218 ( .A(n2963), .B(n2028), .Y(n3688) ); NAND3X2TS U5219 ( .A(n3687), .B(n3688), .C(n3686), .Y(n1232) ); NAND2X2TS U5220 ( .A(n4430), .B(intDX_EWSW[41]), .Y(n3691) ); AO22X4TS U5221 ( .A0(n5863), .A1(n5862), .B0(n5861), .B1(n2153), .Y(n3692) ); NAND3X1TS U5222 ( .A(n6047), .B(n6046), .C(n6045), .Y(n3700) ); NOR2X1TS U5223 ( .A(n3832), .B(n6410), .Y(n3705) ); NOR2X1TS U5224 ( .A(n4716), .B(n5058), .Y(n3704) ); NAND3X1TS U5225 ( .A(n6088), .B(n6087), .C(n6086), .Y(n3706) ); NAND3X1TS U5226 ( .A(n6132), .B(n6131), .C(n6130), .Y(n3709) ); INVX2TS U5227 ( .A(DmP_mant_SFG_SWR[11]), .Y(n3725) ); INVX16TS U5228 ( .A(n6293), .Y(n5243) ); NAND2X8TS U5229 ( .A(n5243), .B(Shift_reg_FLAGS_7[3]), .Y(n5259) ); MXI2X2TS U5230 ( .A(n4652), .B(n3725), .S0(n5218), .Y(n1117) ); INVX2TS U5231 ( .A(n4245), .Y(n3733) ); OAI21X1TS U5232 ( .A0(n1856), .A1(n5339), .B0(n5429), .Y(n3732) ); NOR2X8TS U5233 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y( n3763) ); NAND2X6TS U5234 ( .A(n5428), .B(n3785), .Y(n4258) ); OAI21X1TS U5235 ( .A0(Raw_mant_NRM_SWR[40]), .A1(n2346), .B0(n5422), .Y( n3736) ); NOR2X1TS U5236 ( .A(n5432), .B(Raw_mant_NRM_SWR[28]), .Y(n3739) ); INVX2TS U5237 ( .A(Raw_mant_NRM_SWR[51]), .Y(n5009) ); OAI21X2TS U5238 ( .A0(Raw_mant_NRM_SWR[50]), .A1(n3367), .B0(n5009), .Y( n3740) ); NOR2X1TS U5239 ( .A(n5426), .B(Raw_mant_NRM_SWR[16]), .Y(n3751) ); NAND4X1TS U5240 ( .A(n3758), .B(n4335), .C(n2766), .D(n5441), .Y(n3759) ); OAI2BB1X1TS U5241 ( .A0N(n6209), .A1N(n3364), .B0(n4270), .Y(n3768) ); INVX2TS U5242 ( .A(n3767), .Y(n4269) ); NAND2X1TS U5243 ( .A(n5419), .B(Raw_mant_NRM_SWR[0]), .Y(n3775) ); INVX2TS U5244 ( .A(n3782), .Y(n3783) ); CLKINVX1TS U5245 ( .A(n2889), .Y(n3786) ); NOR2X2TS U5246 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[18]), .Y( n4345) ); INVX2TS U5247 ( .A(n4345), .Y(n3794) ); NOR2X2TS U5248 ( .A(Raw_mant_NRM_SWR[16]), .B(Raw_mant_NRM_SWR[15]), .Y( n4346) ); CLKINVX6TS U5249 ( .A(n4293), .Y(n4691) ); INVX2TS U5250 ( .A(n2296), .Y(n4668) ); INVX2TS U5251 ( .A(n4636), .Y(n5053) ); NOR2X1TS U5252 ( .A(n4698), .B(n5053), .Y(n3798) ); NOR2X1TS U5253 ( .A(n3832), .B(n4643), .Y(n3801) ); NOR2X1TS U5254 ( .A(n3833), .B(n4661), .Y(n3800) ); NOR2X1TS U5255 ( .A(n3803), .B(n3802), .Y(n3810) ); NAND3X4TS U5256 ( .A(n3808), .B(n3807), .C(n3806), .Y(n4472) ); NAND2X1TS U5257 ( .A(n4472), .B(n1871), .Y(n3809) ); NAND2X2TS U5258 ( .A(n2526), .B(intDX_EWSW[13]), .Y(n3815) ); NAND3X2TS U5259 ( .A(n3814), .B(n3815), .C(n3813), .Y(n1284) ); NAND2X1TS U5260 ( .A(n2536), .B(n1864), .Y(n3816) ); NAND2X2TS U5261 ( .A(n3630), .B(intDX_EWSW[7]), .Y(n3821) ); NAND3X2TS U5262 ( .A(n3820), .B(n3821), .C(n3819), .Y(n1296) ); NAND4BX4TS U5263 ( .AN(n3831), .B(n3830), .C(n3829), .D(n3828), .Y(n1627) ); NAND2X4TS U5264 ( .A(n4682), .B(n3372), .Y(n3845) ); NAND2X1TS U5265 ( .A(n4474), .B(Data_array_SWR_3__53_), .Y(n3843) ); AND3X2TS U5266 ( .A(n5906), .B(n5905), .C(n5904), .Y(n3847) ); INVX2TS U5267 ( .A(n5026), .Y(n4675) ); AND2X2TS U5268 ( .A(n5811), .B(n5810), .Y(n3862) ); NOR2X8TS U5269 ( .A(n3898), .B(n3915), .Y(n3882) ); OAI21X4TS U5270 ( .A0(n3915), .A1(n3911), .B0(n3916), .Y(n3885) ); AOI21X4TS U5271 ( .A0(n3913), .A1(n3882), .B0(n3885), .Y(n3877) ); XOR2X4TS U5272 ( .A(n2257), .B(DmP_mant_SFG_SWR[50]), .Y(n3889) ); NOR2X8TS U5273 ( .A(n3889), .B(DMP_SFG[48]), .Y(n4138) ); XOR2X4TS U5274 ( .A(n2257), .B(DmP_mant_SFG_SWR[49]), .Y(n3888) ); OAI21X4TS U5275 ( .A0(n4138), .A1(n4135), .B0(n4139), .Y(n4999) ); OAI21X4TS U5276 ( .A0(n3891), .A1(n5002), .B0(n5003), .Y(n3892) ); INVX2TS U5277 ( .A(n3902), .Y(n3895) ); NAND2X2TS U5278 ( .A(n3895), .B(n3901), .Y(n3896) ); NOR2X8TS U5279 ( .A(n5434), .B(n2561), .Y(n5019) ); AOI22X2TS U5280 ( .A0(n6219), .A1(Raw_mant_NRM_SWR[25]), .B0(n2501), .B1( DmP_mant_SHT1_SW[25]), .Y(n6404) ); OAI21X4TS U5281 ( .A0(n3902), .A1(n5003), .B0(n3901), .Y(n3903) ); AOI21X4TS U5282 ( .A0(n4999), .A1(n3904), .B0(n3903), .Y(n3905) ); NAND2X2TS U5283 ( .A(n2500), .B(DmP_mant_SHT1_SW[19]), .Y(n6390) ); AND3X2TS U5284 ( .A(n5869), .B(n5868), .C(n5867), .Y(n3931) ); NOR2X1TS U5285 ( .A(n2611), .B(n4715), .Y(n3932) ); NAND4BX4TS U5286 ( .AN(n3940), .B(n3939), .C(n6195), .D(n3938), .Y(n5014) ); NOR3X4TS U5287 ( .A(n3949), .B(n5854), .C(n3948), .Y(n3953) ); AND3X2TS U5288 ( .A(n6096), .B(n6095), .C(n6094), .Y(n3957) ); NAND3X1TS U5289 ( .A(n5973), .B(n5972), .C(n5971), .Y(n3962) ); OR2X4TS U5290 ( .A(n5871), .B(n5870), .Y(n4518) ); NAND2X2TS U5291 ( .A(n1950), .B(n4518), .Y(n3973) ); CLKINVX1TS U5292 ( .A(n3987), .Y(n3975) ); INVX2TS U5293 ( .A(n5176), .Y(n4582) ); XNOR2X2TS U5294 ( .A(n3321), .B(n2040), .Y(n5169) ); INVX2TS U5295 ( .A(n5169), .Y(n4581) ); OR2X8TS U5296 ( .A(n3994), .B(n2387), .Y(n4001) ); AOI21X4TS U5297 ( .A0(n2286), .A1(n2843), .B0(n4001), .Y(n3993) ); AOI21X4TS U5298 ( .A0(n1865), .A1(n2843), .B0(n3995), .Y(n3996) ); AOI21X4TS U5299 ( .A0(n2286), .A1(n2843), .B0(n3999), .Y(n4000) ); XOR2X4TS U5300 ( .A(n4000), .B(DMP_exp_NRM2_EW[9]), .Y(n5180) ); NOR2BX4TS U5301 ( .AN(n4002), .B(n4001), .Y(n4003) ); INVX2TS U5302 ( .A(n4005), .Y(n4011) ); INVX2TS U5303 ( .A(n2962), .Y(n4006) ); AOI21X4TS U5304 ( .A0(n1865), .A1(n4011), .B0(n4006), .Y(n4010) ); INVX2TS U5305 ( .A(n4007), .Y(n4009) ); NAND2X2TS U5306 ( .A(n2962), .B(n4011), .Y(n4013) ); BUFX4TS U5307 ( .A(Shift_reg_FLAGS_7[0]), .Y(n5289) ); NAND2X1TS U5308 ( .A(n4474), .B(n4518), .Y(n4044) ); NAND3X6TS U5309 ( .A(n4046), .B(n4045), .C(n4044), .Y(n4506) ); NAND2X4TS U5310 ( .A(n4506), .B(n2330), .Y(n4057) ); INVX2TS U5311 ( .A(n5044), .Y(n4053) ); OAI22X2TS U5312 ( .A0(n2088), .A1(n4094), .B0(n5287), .B1(n5525), .Y(n1076) ); NAND2X1TS U5313 ( .A(n4658), .B(n4523), .Y(n4063) ); AOI22X1TS U5314 ( .A0(n5019), .A1(n2572), .B0(n5006), .B1(n2548), .Y(n4067) ); OA21X4TS U5315 ( .A0(n3022), .A1(n5420), .B0(n4067), .Y(n4068) ); BUFX4TS U5316 ( .A(n5495), .Y(n4834) ); NAND2X1TS U5317 ( .A(n4834), .B(DMP_EXP_EWSW[4]), .Y(n4071) ); NAND3X2TS U5318 ( .A(n4073), .B(n4072), .C(n4071), .Y(n1583) ); NAND2X1TS U5319 ( .A(n4834), .B(DMP_EXP_EWSW[13]), .Y(n4077) ); NAND2X4TS U5320 ( .A(n4704), .B(n3372), .Y(n4085) ); INVX2TS U5321 ( .A(n5015), .Y(n4088) ); NAND2X2TS U5322 ( .A(n2529), .B(n5018), .Y(n4090) ); MXI2X2TS U5323 ( .A(n4092), .B(n5550), .S0(n5216), .Y(n1022) ); INVX2TS U5324 ( .A(DmP_mant_SFG_SWR[6]), .Y(n4093) ); MXI2X2TS U5325 ( .A(n4094), .B(n4093), .S0(n5218), .Y(n1124) ); NAND2X2TS U5326 ( .A(n3124), .B(intDX_EWSW[46]), .Y(n4098) ); NAND3X2TS U5327 ( .A(n4097), .B(n4098), .C(n4096), .Y(n1218) ); NAND2X2TS U5328 ( .A(n3630), .B(intDX_EWSW[38]), .Y(n4101) ); NAND3X2TS U5329 ( .A(n4100), .B(n4101), .C(n4099), .Y(n1234) ); NAND2X2TS U5330 ( .A(n4424), .B(intDX_EWSW[15]), .Y(n4108) ); NAND3X2TS U5331 ( .A(n4107), .B(n4108), .C(n4106), .Y(n1280) ); NAND2X2TS U5332 ( .A(n2531), .B(intDX_EWSW[6]), .Y(n4113) ); NAND2X1TS U5333 ( .A(n2558), .B(n5026), .Y(n4122) ); NAND2X2TS U5334 ( .A(n2555), .B(n1635), .Y(n4121) ); OR2X2TS U5335 ( .A(n5724), .B(n5723), .Y(n4123) ); BUFX12TS U5336 ( .A(n2764), .Y(n5264) ); NOR2X1TS U5337 ( .A(n4716), .B(n4534), .Y(n4125) ); NAND2X2TS U5338 ( .A(n4618), .B(n4691), .Y(n4128) ); INVX2TS U5339 ( .A(n5332), .Y(n4130) ); NAND2X1TS U5340 ( .A(n4834), .B(DMP_EXP_EWSW[8]), .Y(n4132) ); NAND2X2TS U5341 ( .A(n4140), .B(n4139), .Y(n4141) ); NAND2X1TS U5342 ( .A(n4834), .B(DMP_EXP_EWSW[11]), .Y(n4142) ); NAND3X2TS U5343 ( .A(n4144), .B(n4143), .C(n4142), .Y(n1576) ); OR2X2TS U5344 ( .A(n2522), .B(n2330), .Y(n4480) ); NOR2X8TS U5345 ( .A(n2453), .B(n4480), .Y(n5184) ); XNOR2X1TS U5346 ( .A(intDX_EWSW[45]), .B(n2299), .Y(n4149) ); XNOR2X1TS U5347 ( .A(intDX_EWSW[44]), .B(intDY_EWSW[44]), .Y(n4148) ); XNOR2X1TS U5348 ( .A(intDX_EWSW[47]), .B(n2045), .Y(n4147) ); XNOR2X1TS U5349 ( .A(intDX_EWSW[46]), .B(n1922), .Y(n4146) ); NAND4X1TS U5350 ( .A(n4149), .B(n4148), .C(n4147), .D(n4146), .Y(n4165) ); XNOR2X1TS U5351 ( .A(intDX_EWSW[33]), .B(n2945), .Y(n4153) ); XNOR2X1TS U5352 ( .A(intDX_EWSW[35]), .B(n2940), .Y(n4151) ); XNOR2X1TS U5353 ( .A(intDX_EWSW[34]), .B(n2740), .Y(n4150) ); NAND4X1TS U5354 ( .A(n4153), .B(n4152), .C(n4151), .D(n4150), .Y(n4164) ); XNOR2X1TS U5355 ( .A(intDX_EWSW[36]), .B(intDY_EWSW[36]), .Y(n4156) ); XNOR2X1TS U5356 ( .A(intDX_EWSW[38]), .B(intDY_EWSW[38]), .Y(n4154) ); NAND4X1TS U5357 ( .A(n4157), .B(n4156), .C(n4155), .D(n4154), .Y(n4163) ); XNOR2X1TS U5358 ( .A(intDX_EWSW[31]), .B(n2961), .Y(n4161) ); XNOR2X1TS U5359 ( .A(intDX_EWSW[30]), .B(intDY_EWSW[30]), .Y(n4160) ); XNOR2X1TS U5360 ( .A(intDX_EWSW[29]), .B(intDY_EWSW[29]), .Y(n4159) ); XNOR2X1TS U5361 ( .A(intDX_EWSW[20]), .B(intDY_EWSW[20]), .Y(n4158) ); NAND4X1TS U5362 ( .A(n4161), .B(n4160), .C(n4159), .D(n4158), .Y(n4162) ); XNOR2X1TS U5363 ( .A(intDX_EWSW[27]), .B(n2964), .Y(n4169) ); XNOR2X1TS U5364 ( .A(intDX_EWSW[26]), .B(n2046), .Y(n4168) ); XNOR2X1TS U5365 ( .A(intDX_EWSW[32]), .B(n2957), .Y(n4167) ); XNOR2X1TS U5366 ( .A(intDX_EWSW[25]), .B(n2250), .Y(n4166) ); NAND4X1TS U5367 ( .A(n4169), .B(n4168), .C(n4167), .D(n4166), .Y(n4185) ); XNOR2X1TS U5368 ( .A(intDX_EWSW[23]), .B(n1984), .Y(n4173) ); XNOR2X1TS U5369 ( .A(intDX_EWSW[22]), .B(n2036), .Y(n4172) ); XNOR2X1TS U5370 ( .A(intDX_EWSW[48]), .B(intDY_EWSW[48]), .Y(n4171) ); XNOR2X1TS U5371 ( .A(intDX_EWSW[21]), .B(n2479), .Y(n4170) ); XNOR2X1TS U5372 ( .A(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n4177) ); XNOR2X1TS U5373 ( .A(intDX_EWSW[18]), .B(intDY_EWSW[18]), .Y(n4176) ); XNOR2X1TS U5374 ( .A(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n4175) ); XNOR2X1TS U5375 ( .A(intDX_EWSW[17]), .B(intDY_EWSW[17]), .Y(n4174) ); NAND4X1TS U5376 ( .A(n4177), .B(n4176), .C(n4175), .D(n4174), .Y(n4183) ); XNOR2X1TS U5377 ( .A(intDX_EWSW[15]), .B(intDY_EWSW[15]), .Y(n4181) ); XNOR2X1TS U5378 ( .A(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n4179) ); XNOR2X1TS U5379 ( .A(intDX_EWSW[4]), .B(intDY_EWSW[4]), .Y(n4178) ); NAND4X1TS U5380 ( .A(n4181), .B(n4180), .C(n4179), .D(n4178), .Y(n4182) ); XNOR2X1TS U5381 ( .A(intDX_EWSW[12]), .B(n1923), .Y(n4189) ); XNOR2X1TS U5382 ( .A(intDX_EWSW[10]), .B(n2048), .Y(n4188) ); XNOR2X1TS U5383 ( .A(intDX_EWSW[16]), .B(intDY_EWSW[16]), .Y(n4187) ); XNOR2X1TS U5384 ( .A(intDX_EWSW[9]), .B(n2050), .Y(n4186) ); NAND4X1TS U5385 ( .A(n4189), .B(n4188), .C(n4187), .D(n4186), .Y(n4205) ); XNOR2X1TS U5386 ( .A(intDX_EWSW[7]), .B(intDY_EWSW[7]), .Y(n4193) ); XNOR2X1TS U5387 ( .A(intDX_EWSW[6]), .B(intDY_EWSW[6]), .Y(n4192) ); XNOR2X1TS U5388 ( .A(intDX_EWSW[5]), .B(n2295), .Y(n4190) ); NAND4X1TS U5389 ( .A(n4193), .B(n4192), .C(n4191), .D(n4190), .Y(n4204) ); XNOR2X1TS U5390 ( .A(intDX_EWSW[58]), .B(intDY_EWSW[58]), .Y(n4197) ); XNOR2X1TS U5391 ( .A(intDX_EWSW[60]), .B(intDY_EWSW[60]), .Y(n4196) ); XNOR2X1TS U5392 ( .A(intDX_EWSW[59]), .B(intDY_EWSW[59]), .Y(n4195) ); XNOR2X1TS U5393 ( .A(intDX_EWSW[62]), .B(intDY_EWSW[62]), .Y(n4194) ); NAND4X1TS U5394 ( .A(n4197), .B(n4196), .C(n4195), .D(n4194), .Y(n4203) ); XNOR2X1TS U5395 ( .A(intDX_EWSW[3]), .B(intDY_EWSW[3]), .Y(n4201) ); XNOR2X1TS U5396 ( .A(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n4200) ); XNOR2X1TS U5397 ( .A(intDX_EWSW[8]), .B(intDY_EWSW[8]), .Y(n4199) ); XNOR2X1TS U5398 ( .A(intDX_EWSW[0]), .B(intDY_EWSW[0]), .Y(n4198) ); NAND4X1TS U5399 ( .A(n4201), .B(n4200), .C(n4199), .D(n4198), .Y(n4202) ); XNOR2X1TS U5400 ( .A(intDX_EWSW[49]), .B(intDY_EWSW[49]), .Y(n4209) ); XNOR2X1TS U5401 ( .A(intDX_EWSW[52]), .B(intDY_EWSW[52]), .Y(n4208) ); XNOR2X1TS U5402 ( .A(intDX_EWSW[51]), .B(n2017), .Y(n4207) ); XNOR2X1TS U5403 ( .A(intDX_EWSW[54]), .B(intDY_EWSW[54]), .Y(n4206) ); XNOR2X1TS U5404 ( .A(intDX_EWSW[56]), .B(intDY_EWSW[56]), .Y(n4212) ); NAND4X1TS U5405 ( .A(n4213), .B(n4212), .C(n4211), .D(n4210), .Y(n4223) ); XNOR2X1TS U5406 ( .A(intDX_EWSW[40]), .B(intDY_EWSW[40]), .Y(n4216) ); XNOR2X1TS U5407 ( .A(intDX_EWSW[43]), .B(intDY_EWSW[43]), .Y(n4215) ); XNOR2X1TS U5408 ( .A(intDX_EWSW[42]), .B(intDY_EWSW[42]), .Y(n4214) ); XNOR2X1TS U5409 ( .A(intDX_EWSW[61]), .B(intDY_EWSW[61]), .Y(n4220) ); XNOR2X1TS U5410 ( .A(intDX_EWSW[50]), .B(intDY_EWSW[50]), .Y(n4218) ); NAND3X1TS U5411 ( .A(n4220), .B(n4219), .C(n4218), .Y(n4221) ); INVX2TS U5412 ( .A(n4729), .Y(n4230) ); NOR2X2TS U5413 ( .A(n4230), .B(n4229), .Y(n4728) ); NAND2X1TS U5414 ( .A(n2534), .B(DMP_EXP_EWSW[56]), .Y(n4234) ); NAND3X2TS U5415 ( .A(n4235), .B(n4236), .C(n4234), .Y(n1531) ); NAND2X1TS U5416 ( .A(n2534), .B(DMP_EXP_EWSW[55]), .Y(n4237) ); NAND3X2TS U5417 ( .A(n4238), .B(n4239), .C(n4237), .Y(n1532) ); NAND3X1TS U5418 ( .A(n4343), .B(n4251), .C(Raw_mant_NRM_SWR[30]), .Y(n4252) ); NOR2X8TS U5419 ( .A(n2077), .B(Raw_mant_NRM_SWR[11]), .Y(n4884) ); NAND2X1TS U5420 ( .A(n4892), .B(n5423), .Y(n4264) ); NOR2X8TS U5421 ( .A(n2474), .B(n4264), .Y(n4276) ); OAI21X1TS U5422 ( .A0(Raw_mant_NRM_SWR[2]), .A1(Raw_mant_NRM_SWR[1]), .B0( n4276), .Y(n4265) ); NOR2X4TS U5423 ( .A(n4267), .B(n4268), .Y(n4277) ); NAND2X1TS U5424 ( .A(n4277), .B(Raw_mant_NRM_SWR[33]), .Y(n4275) ); NAND3X1TS U5425 ( .A(n4271), .B(n2038), .C(n4269), .Y(n4272) ); NAND2X4TS U5426 ( .A(n4276), .B(Raw_mant_NRM_SWR[0]), .Y(n4902) ); OAI2BB1X4TS U5427 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n2384), .B0(n4869), .Y(n1135) ); NAND2X4TS U5428 ( .A(n2555), .B(n4707), .Y(n4292) ); INVX4TS U5429 ( .A(n4293), .Y(n4685) ); NAND2X1TS U5430 ( .A(n4659), .B(n4523), .Y(n4296) ); INVX2TS U5431 ( .A(DmP_mant_SFG_SWR[2]), .Y(n4303) ); AOI22X1TS U5432 ( .A0(n5019), .A1(DmP_mant_SHT1_SW[2]), .B0(n5006), .B1( DmP_mant_SHT1_SW[1]), .Y(n4304) ); OA21X4TS U5433 ( .A0(n3022), .A1(n5009), .B0(n4304), .Y(n4305) ); NAND2X4TS U5434 ( .A(n4321), .B(n6396), .Y(n6397) ); NAND2X2TS U5435 ( .A(n2041), .B(intDX_EWSW[14]), .Y(n4309) ); NAND2X1TS U5436 ( .A(n2951), .B(n2024), .Y(n4308) ); NAND3X2TS U5437 ( .A(n4308), .B(n4309), .C(n4307), .Y(n1282) ); NAND2X1TS U5438 ( .A(n2536), .B(n2312), .Y(n4310) ); NAND2X2TS U5439 ( .A(n3630), .B(intDX_EWSW[10]), .Y(n4315) ); NAND3X2TS U5440 ( .A(n4314), .B(n4315), .C(n4313), .Y(n1290) ); NAND2X2TS U5441 ( .A(n1838), .B(intDX_EWSW[9]), .Y(n4318) ); NAND2X2TS U5442 ( .A(n4864), .B(DmP_EXP_EWSW[9]), .Y(n4316) ); AOI22X1TS U5443 ( .A0(n5019), .A1(DmP_mant_SHT1_SW[8]), .B0(n5006), .B1( DmP_mant_SHT1_SW[7]), .Y(n4319) ); NOR2X1TS U5444 ( .A(n4689), .B(n4324), .Y(n4327) ); NAND2X1TS U5445 ( .A(n3846), .B(Data_array_SWR_3__53_), .Y(n4330) ); AO22X4TS U5446 ( .A0(n6206), .A1(n2345), .B0(n4331), .B1(n6228), .Y(n6351) ); AO22X4TS U5447 ( .A0(n2982), .A1(Raw_mant_NRM_SWR[11]), .B0(n4707), .B1( n5041), .Y(n6211) ); NAND2X2TS U5448 ( .A(n6201), .B(DmP_mant_SHT1_SW[50]), .Y(n6354) ); INVX2TS U5449 ( .A(n4335), .Y(n4341) ); INVX2TS U5450 ( .A(n2077), .Y(n4337) ); AND2X2TS U5451 ( .A(n4347), .B(Raw_mant_NRM_SWR[12]), .Y(n4350) ); OAI2BB1X4TS U5452 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n2384), .B0(n4908), .Y(n1122) ); NAND2X1TS U5453 ( .A(n3587), .B(intDY_EWSW[60]), .Y(n4356) ); NAND2X1TS U5454 ( .A(n4863), .B(intDX_EWSW[60]), .Y(n4355) ); NAND2X1TS U5455 ( .A(n2524), .B(n2303), .Y(n4354) ); NAND3X2TS U5456 ( .A(n4356), .B(n4355), .C(n4354), .Y(n1527) ); NAND2X1TS U5457 ( .A(n2524), .B(DMP_EXP_EWSW[58]), .Y(n4357) ); NAND3X2TS U5458 ( .A(n4359), .B(n4358), .C(n4357), .Y(n1529) ); NAND2X1TS U5459 ( .A(n2536), .B(DMP_EXP_EWSW[52]), .Y(n4360) ); NAND2X2TS U5460 ( .A(n2526), .B(intDY_EWSW[54]), .Y(n4365) ); NAND2X2TS U5461 ( .A(n4369), .B(intDX_EWSW[54]), .Y(n4364) ); NAND2X1TS U5462 ( .A(n2534), .B(DMP_EXP_EWSW[54]), .Y(n4363) ); NAND3X2TS U5463 ( .A(n4365), .B(n4364), .C(n4363), .Y(n1533) ); NAND2X1TS U5464 ( .A(n2963), .B(n2292), .Y(n4368) ); NAND2X1TS U5465 ( .A(n2536), .B(DMP_EXP_EWSW[53]), .Y(n4366) ); NAND3X2TS U5466 ( .A(n4368), .B(n4367), .C(n4366), .Y(n1534) ); NAND2X1TS U5467 ( .A(n3087), .B(intDY_EWSW[57]), .Y(n4372) ); NAND2X1TS U5468 ( .A(n2534), .B(DMP_EXP_EWSW[57]), .Y(n4370) ); NAND3X2TS U5469 ( .A(n4372), .B(n4371), .C(n4370), .Y(n1530) ); NAND3X2TS U5470 ( .A(n4374), .B(n4375), .C(n4373), .Y(n1306) ); NAND2X1TS U5471 ( .A(n2535), .B(DmP_EXP_EWSW[1]), .Y(n4376) ); NAND3X2TS U5472 ( .A(n4377), .B(n4378), .C(n4376), .Y(n1308) ); NAND2X1TS U5473 ( .A(n2536), .B(DmP_EXP_EWSW[0]), .Y(n4380) ); NAND3X2TS U5474 ( .A(n4381), .B(n4382), .C(n4380), .Y(n1310) ); NAND3X2TS U5475 ( .A(n4384), .B(n4385), .C(n4383), .Y(n1587) ); NAND2X2TS U5476 ( .A(n5184), .B(n4671), .Y(n6426) ); NAND2X1TS U5477 ( .A(n4430), .B(intDY_EWSW[50]), .Y(n4388) ); NAND2X1TS U5478 ( .A(n2053), .B(intDX_EWSW[50]), .Y(n4387) ); NAND3X2TS U5479 ( .A(n4394), .B(n4395), .C(n4393), .Y(n1538) ); NAND2X1TS U5480 ( .A(n4839), .B(DMP_EXP_EWSW[5]), .Y(n4400) ); NAND3X2TS U5481 ( .A(n4404), .B(n4405), .C(n4403), .Y(n1304) ); NAND2X1TS U5482 ( .A(n4439), .B(n1984), .Y(n4408) ); NAND3X2TS U5483 ( .A(n4408), .B(n4407), .C(n4406), .Y(n1564) ); NAND2X1TS U5484 ( .A(n4439), .B(intDY_EWSW[24]), .Y(n4415) ); NAND3X2TS U5485 ( .A(n4415), .B(n4414), .C(n4413), .Y(n1563) ); NAND2X1TS U5486 ( .A(n2525), .B(DMP_EXP_EWSW[3]), .Y(n4432) ); OAI21X4TS U5487 ( .A0(n3022), .A1(n5419), .B0(n4435), .Y(n6369) ); NAND3X2TS U5488 ( .A(n4438), .B(n4437), .C(n4436), .Y(n1663) ); NAND2X2TS U5489 ( .A(n3630), .B(intDX_EWSW[54]), .Y(n4448) ); NAND2X1TS U5490 ( .A(n4834), .B(DmP_EXP_EWSW[54]), .Y(n4446) ); NAND3X2TS U5491 ( .A(n4448), .B(n4447), .C(n4446), .Y(n1204) ); NAND2X2TS U5492 ( .A(n4424), .B(intDX_EWSW[56]), .Y(n4451) ); NAND2X1TS U5493 ( .A(n2536), .B(DmP_EXP_EWSW[56]), .Y(n4449) ); NAND2X2TS U5494 ( .A(n4877), .B(intDY_EWSW[52]), .Y(n4453) ); NAND2X1TS U5495 ( .A(n4834), .B(DmP_EXP_EWSW[52]), .Y(n4452) ); NAND3X2TS U5496 ( .A(n4454), .B(n4453), .C(n4452), .Y(n1206) ); NAND2X2TS U5497 ( .A(n3124), .B(intDX_EWSW[53]), .Y(n4457) ); NAND2X2TS U5498 ( .A(n4838), .B(n2292), .Y(n4456) ); NAND2X1TS U5499 ( .A(n4834), .B(DmP_EXP_EWSW[53]), .Y(n4455) ); NAND3X2TS U5500 ( .A(n4457), .B(n4456), .C(n4455), .Y(n1205) ); NAND2X2TS U5501 ( .A(n2530), .B(intDX_EWSW[55]), .Y(n4460) ); NAND2X1TS U5502 ( .A(n2534), .B(DmP_EXP_EWSW[55]), .Y(n4458) ); NAND3X2TS U5503 ( .A(n4460), .B(n4459), .C(n4458), .Y(n1203) ); NAND2X2TS U5504 ( .A(n6392), .B(n6408), .Y(n6393) ); CLKBUFX3TS U5505 ( .A(n2533), .Y(n6262) ); CLKBUFX3TS U5506 ( .A(n6262), .Y(n6292) ); CLKBUFX3TS U5507 ( .A(n6292), .Y(n6254) ); CLKBUFX3TS U5508 ( .A(n6288), .Y(n4463) ); CLKBUFX2TS U5509 ( .A(n4463), .Y(n5672) ); CLKBUFX3TS U5510 ( .A(n4463), .Y(n5674) ); CLKBUFX3TS U5511 ( .A(n6290), .Y(n4464) ); CLKBUFX3TS U5512 ( .A(n4464), .Y(n5662) ); CLKBUFX3TS U5513 ( .A(n4462), .Y(n5647) ); CLKBUFX3TS U5514 ( .A(n4462), .Y(n5648) ); CLKBUFX3TS U5515 ( .A(n4463), .Y(n5673) ); CLKBUFX3TS U5516 ( .A(n6290), .Y(n4466) ); CLKBUFX3TS U5517 ( .A(n6290), .Y(n4461) ); CLKBUFX3TS U5518 ( .A(n4461), .Y(n5641) ); CLKBUFX3TS U5519 ( .A(n4461), .Y(n5640) ); CLKBUFX3TS U5520 ( .A(n4464), .Y(n5663) ); CLKBUFX3TS U5521 ( .A(n5621), .Y(n5678) ); CLKBUFX3TS U5522 ( .A(n4464), .Y(n5664) ); CLKBUFX3TS U5523 ( .A(n4466), .Y(n5656) ); CLKBUFX3TS U5524 ( .A(n6232), .Y(n5632) ); CLKBUFX3TS U5525 ( .A(n5620), .Y(n5679) ); CLKBUFX3TS U5526 ( .A(n4461), .Y(n5642) ); CLKBUFX3TS U5527 ( .A(n4462), .Y(n5650) ); CLKBUFX3TS U5528 ( .A(n4464), .Y(n5665) ); CLKBUFX3TS U5529 ( .A(n6292), .Y(n6233) ); CLKBUFX3TS U5530 ( .A(n4466), .Y(n5657) ); CLKBUFX3TS U5531 ( .A(n6254), .Y(n5619) ); CLKBUFX2TS U5532 ( .A(n5658), .Y(n5622) ); CLKBUFX2TS U5533 ( .A(n6232), .Y(n5621) ); CLKBUFX3TS U5534 ( .A(n6233), .Y(n5630) ); CLKBUFX3TS U5535 ( .A(n6255), .Y(n5631) ); CLKBUFX3TS U5536 ( .A(n6292), .Y(n6255) ); CLKBUFX3TS U5537 ( .A(n6255), .Y(n5635) ); BUFX3TS U5538 ( .A(n4465), .Y(n6289) ); CLKBUFX3TS U5539 ( .A(n4462), .Y(n5651) ); CLKBUFX3TS U5540 ( .A(n5618), .Y(n5677) ); CLKBUFX3TS U5541 ( .A(n6286), .Y(n5636) ); CLKBUFX3TS U5542 ( .A(n4464), .Y(n5666) ); CLKBUFX3TS U5543 ( .A(n4461), .Y(n5639) ); CLKBUFX3TS U5544 ( .A(n4466), .Y(n5654) ); BUFX3TS U5545 ( .A(n5643), .Y(n6287) ); BUFX3TS U5546 ( .A(n6287), .Y(n6235) ); BUFX3TS U5547 ( .A(n2569), .Y(n5683) ); CLKBUFX3TS U5548 ( .A(n4464), .Y(n5661) ); CLKBUFX3TS U5549 ( .A(n6255), .Y(n5618) ); BUFX3TS U5550 ( .A(n4465), .Y(n6239) ); BUFX3TS U5551 ( .A(n6286), .Y(n6281) ); BUFX3TS U5552 ( .A(n4461), .Y(n6267) ); BUFX3TS U5553 ( .A(n6232), .Y(n6282) ); BUFX3TS U5554 ( .A(n6254), .Y(n6283) ); BUFX3TS U5555 ( .A(n6255), .Y(n6284) ); BUFX3TS U5556 ( .A(n6236), .Y(n5670) ); BUFX3TS U5557 ( .A(n5641), .Y(n6280) ); BUFX3TS U5558 ( .A(n6234), .Y(n6285) ); BUFX3TS U5559 ( .A(n6287), .Y(n6268) ); BUFX3TS U5560 ( .A(n5656), .Y(n6279) ); BUFX3TS U5561 ( .A(n6254), .Y(n6278) ); BUFX3TS U5562 ( .A(n5654), .Y(n6276) ); CLKBUFX2TS U5563 ( .A(n4466), .Y(n5653) ); CLKBUFX3TS U5564 ( .A(n4464), .Y(n5667) ); BUFX3TS U5565 ( .A(n5667), .Y(n6247) ); CLKBUFX3TS U5566 ( .A(n4466), .Y(n5658) ); BUFX3TS U5567 ( .A(n5658), .Y(n6248) ); BUFX3TS U5568 ( .A(n6292), .Y(n6291) ); BUFX3TS U5569 ( .A(n2538), .Y(n6250) ); BUFX3TS U5570 ( .A(n2515), .Y(n6251) ); BUFX3TS U5571 ( .A(n2520), .Y(n6252) ); BUFX3TS U5572 ( .A(n5667), .Y(n6271) ); BUFX3TS U5573 ( .A(n5658), .Y(n6272) ); CLKBUFX3TS U5574 ( .A(n2532), .Y(n5676) ); BUFX3TS U5575 ( .A(n6232), .Y(n5628) ); CLKBUFX3TS U5576 ( .A(n6262), .Y(n5685) ); BUFX3TS U5577 ( .A(n6287), .Y(n6274) ); CLKBUFX3TS U5578 ( .A(n4461), .Y(n5638) ); BUFX3TS U5579 ( .A(n6288), .Y(n6260) ); BUFX3TS U5580 ( .A(n6259), .Y(n6237) ); BUFX3TS U5581 ( .A(n5643), .Y(n6263) ); BUFX3TS U5582 ( .A(n6232), .Y(n6266) ); BUFX3TS U5583 ( .A(n6288), .Y(n6261) ); BUFX3TS U5584 ( .A(n4465), .Y(n6265) ); BUFX3TS U5585 ( .A(n2512), .Y(n6264) ); BUFX3TS U5586 ( .A(n6287), .Y(n6270) ); BUFX3TS U5587 ( .A(n6287), .Y(n6269) ); BUFX3TS U5588 ( .A(n6291), .Y(n6246) ); CLKBUFX2TS U5589 ( .A(n4462), .Y(n5645) ); BUFX3TS U5590 ( .A(n4461), .Y(n5637) ); CLKBUFX3TS U5591 ( .A(n6236), .Y(n5669) ); CLKBUFX2TS U5592 ( .A(n4464), .Y(n5660) ); BUFX3TS U5593 ( .A(n6254), .Y(n5633) ); BUFX3TS U5594 ( .A(n6257), .Y(n5668) ); BUFX3TS U5595 ( .A(n5660), .Y(n5675) ); CLKBUFX3TS U5596 ( .A(n4462), .Y(n5644) ); BUFX3TS U5597 ( .A(n4463), .Y(n5671) ); CLKBUFX3TS U5598 ( .A(n6255), .Y(n5634) ); BUFX3TS U5599 ( .A(n6291), .Y(n6245) ); BUFX3TS U5600 ( .A(n4464), .Y(n5659) ); BUFX3TS U5601 ( .A(n4465), .Y(n6242) ); CLKBUFX3TS U5602 ( .A(n4466), .Y(n5652) ); BUFX3TS U5603 ( .A(n6291), .Y(n6243) ); BUFX3TS U5604 ( .A(n6291), .Y(n6244) ); OAI21X1TS U5605 ( .A0(n2383), .A1(n2522), .B0(n2384), .Y(n1729) ); CLKMX2X2TS U5606 ( .A(DMP_exp_NRM2_EW[9]), .B(DMP_exp_NRM_EW[9]), .S0(n2563), .Y(n1316) ); CLKMX2X2TS U5607 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n2562), .Y(n1331) ); NAND3X2TS U5608 ( .A(n6179), .B(n4467), .C(n6178), .Y(final_result_ieee[14]) ); NAND2X1TS U5609 ( .A(n5571), .B(final_result_ieee[14]), .Y(n6422) ); CLKMX2X2TS U5610 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n2563), .Y(n1346) ); CLKMX2X2TS U5611 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n2562), .Y(n1326) ); CLKMX2X2TS U5612 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n2563), .Y(n1356) ); CLKMX2X2TS U5613 ( .A(DMP_exp_NRM2_EW[8]), .B(DMP_exp_NRM_EW[8]), .S0(n2562), .Y(n1321) ); MXI2X1TS U5614 ( .A(beg_OP), .B(n5494), .S0( inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n4469) ); NOR2X1TS U5615 ( .A(inst_FSM_INPUT_ENABLE_state_reg[1]), .B( inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n4468) ); NAND2X1TS U5616 ( .A(n4468), .B(inst_FSM_INPUT_ENABLE_state_reg[2]), .Y( n4470) ); OAI21X1TS U5617 ( .A0(n4469), .A1(n4471), .B0(n4470), .Y(n1802) ); INVX2TS U5618 ( .A(n4471), .Y(n5212) ); MXI2X4TS U5619 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n4471), .S0( inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n4577) ); NAND2X8TS U5620 ( .A(n4577), .B(beg_OP), .Y(n5234) ); NAND2X1TS U5621 ( .A(n4473), .B(n4636), .Y(n4475) ); NOR2X2TS U5622 ( .A(n2764), .B(n4477), .Y(n4546) ); AOI22X1TS U5623 ( .A0(n5183), .A1(n4546), .B0(DmP_mant_SFG_SWR[35]), .B1( n5125), .Y(n4479) ); NOR2X8TS U5624 ( .A(n2764), .B(n2449), .Y(n5123) ); AOI22X1TS U5625 ( .A0(n5183), .A1(n4542), .B0(n1840), .B1(n5125), .Y(n4482) ); AOI22X1TS U5626 ( .A0(n4637), .A1(n4620), .B0(n2780), .B1(n1626), .Y(n4483) ); OAI2BB1X1TS U5627 ( .A0N(n6123), .A1N(n6122), .B0(n6121), .Y(n4491) ); INVX2TS U5628 ( .A(n4491), .Y(n5010) ); OAI22X1TS U5629 ( .A0(n4698), .A1(n4715), .B0(n4702), .B1(n5010), .Y(n4492) ); INVX2TS U5630 ( .A(n4518), .Y(n5012) ); NOR2X1TS U5631 ( .A(n4669), .B(n5012), .Y(n5126) ); AOI22X1TS U5632 ( .A0(n5126), .A1(n5149), .B0(DmP_mant_SFG_SWR[0]), .B1( n5125), .Y(n4494) ); CLKMX2X3TS U5633 ( .A(Data_Y[1]), .B(n2310), .S0(n5242), .Y(n1727) ); NOR2X1TS U5634 ( .A(n2611), .B(n5050), .Y(n4498) ); NOR2X1TS U5635 ( .A(n4702), .B(n4717), .Y(n4497) ); NAND2X2TS U5636 ( .A(n5151), .B(n1871), .Y(n4503) ); NOR2X1TS U5637 ( .A(n4718), .B(n4715), .Y(n4500) ); NOR2X1TS U5638 ( .A(n3833), .B(n4701), .Y(n4499) ); AOI22X1TS U5639 ( .A0(n4506), .A1(n4546), .B0(DmP_mant_SFG_SWR[38]), .B1( n5125), .Y(n4505) ); AOI22X1TS U5640 ( .A0(n4671), .A1(n4546), .B0(DmP_mant_SFG_SWR[37]), .B1( n5125), .Y(n4509) ); AOI22X1TS U5641 ( .A0(n4671), .A1(n4542), .B0(DmP_mant_SFG_SWR[17]), .B1( n5125), .Y(n4511) ); NAND2X1TS U5642 ( .A(n2764), .B(DmP_mant_SFG_SWR[1]), .Y(n4514) ); NAND3X1TS U5643 ( .A(n4722), .B(n5123), .C(Data_array_SWR_3__53_), .Y(n4513) ); NAND2X1TS U5644 ( .A(n4659), .B(n4518), .Y(n4519) ); NAND2X1TS U5645 ( .A(n4659), .B(n5034), .Y(n4527) ); NAND2X2TS U5646 ( .A(n5153), .B(n4685), .Y(n4538) ); AOI22X1TS U5647 ( .A0(n5182), .A1(n4542), .B0(DmP_mant_SFG_SWR[18]), .B1( n5125), .Y(n4545) ); NAND2X2TS U5648 ( .A(n6446), .B(n4543), .Y(n4544) ); AOI22X1TS U5649 ( .A0(n5182), .A1(n4546), .B0(DmP_mant_SFG_SWR[36]), .B1( n5125), .Y(n4548) ); NAND2X2TS U5650 ( .A(n6446), .B(n5149), .Y(n4547) ); MXI2X1TS U5651 ( .A(Raw_mant_NRM_SWR[10]), .B(DMP_SFG[8]), .S0(n3287), .Y( n4550) ); NOR2BX4TS U5652 ( .AN(n2487), .B(n4917), .Y(n4551) ); NOR2BX4TS U5653 ( .AN(n2549), .B(n2257), .Y(n5128) ); MXI2X1TS U5654 ( .A(n4554), .B(n4555), .S0(DmP_mant_SFG_SWR[10]), .Y(n4549) ); NAND2X1TS U5655 ( .A(n4550), .B(n4549), .Y(n1096) ); MXI2X1TS U5656 ( .A(Raw_mant_NRM_SWR[12]), .B(DMP_SFG[10]), .S0(n3232), .Y( n4553) ); MXI2X1TS U5657 ( .A(n4551), .B(n4555), .S0(DmP_mant_SFG_SWR[12]), .Y(n4552) ); NAND2X1TS U5658 ( .A(n4553), .B(n4552), .Y(n1112) ); MXI2X1TS U5659 ( .A(Raw_mant_NRM_SWR[6]), .B(DMP_SFG[4]), .S0(n3179), .Y( n4557) ); MXI2X1TS U5660 ( .A(n4551), .B(n5128), .S0(DmP_mant_SFG_SWR[6]), .Y(n4556) ); NAND2X1TS U5661 ( .A(n4557), .B(n4556), .Y(n1123) ); MXI2X1TS U5662 ( .A(Raw_mant_NRM_SWR[11]), .B(DMP_SFG[9]), .S0(n3287), .Y( n4559) ); MXI2X1TS U5663 ( .A(n4554), .B(n5128), .S0(DmP_mant_SFG_SWR[11]), .Y(n4558) ); NAND2X1TS U5664 ( .A(n4559), .B(n4558), .Y(n1116) ); MXI2X1TS U5665 ( .A(Raw_mant_NRM_SWR[7]), .B(DMP_SFG[5]), .S0(n3232), .Y( n4561) ); MXI2X1TS U5666 ( .A(n4551), .B(n5128), .S0(DmP_mant_SFG_SWR[7]), .Y(n4560) ); NAND2X1TS U5667 ( .A(n4561), .B(n4560), .Y(n1120) ); MXI2X1TS U5668 ( .A(Raw_mant_NRM_SWR[8]), .B(DMP_SFG[6]), .S0(n3287), .Y( n4563) ); MXI2X1TS U5669 ( .A(n4554), .B(n4555), .S0(DmP_mant_SFG_SWR[8]), .Y(n4562) ); NAND2X1TS U5670 ( .A(n4563), .B(n4562), .Y(n1118) ); MXI2X1TS U5671 ( .A(n1856), .B(DMP_SFG[2]), .S0(n3287), .Y(n4565) ); MXI2X1TS U5672 ( .A(n4554), .B(n4555), .S0(DmP_mant_SFG_SWR[4]), .Y(n4564) ); NAND2X1TS U5673 ( .A(n4565), .B(n4564), .Y(n1126) ); MXI2X1TS U5674 ( .A(Raw_mant_NRM_SWR[13]), .B(DMP_SFG[11]), .S0(n3232), .Y( n4567) ); MXI2X1TS U5675 ( .A(n4554), .B(n4555), .S0(DmP_mant_SFG_SWR[13]), .Y(n4566) ); NAND2X1TS U5676 ( .A(n4567), .B(n4566), .Y(n1110) ); MXI2X1TS U5677 ( .A(Raw_mant_NRM_SWR[5]), .B(DMP_SFG[3]), .S0(n5208), .Y( n4569) ); MXI2X1TS U5678 ( .A(n4554), .B(n5128), .S0(DmP_mant_SFG_SWR[5]), .Y(n4568) ); NAND2X1TS U5679 ( .A(n4569), .B(n4568), .Y(n1131) ); MXI2X1TS U5680 ( .A(Raw_mant_NRM_SWR[2]), .B(DMP_SFG[0]), .S0(n5208), .Y( n4571) ); MXI2X1TS U5681 ( .A(n4551), .B(n5128), .S0(DmP_mant_SFG_SWR[2]), .Y(n4570) ); NAND2X1TS U5682 ( .A(n4571), .B(n4570), .Y(n1133) ); MXI2X1TS U5683 ( .A(Raw_mant_NRM_SWR[3]), .B(DMP_SFG[1]), .S0(n3287), .Y( n4573) ); MXI2X1TS U5684 ( .A(n4551), .B(n5128), .S0(DmP_mant_SFG_SWR[3]), .Y(n4572) ); NAND2X1TS U5685 ( .A(n4573), .B(n4572), .Y(n1128) ); MXI2X1TS U5686 ( .A(Raw_mant_NRM_SWR[9]), .B(DMP_SFG[7]), .S0(n3287), .Y( n4575) ); MXI2X1TS U5687 ( .A(n4554), .B(n5128), .S0(DmP_mant_SFG_SWR[9]), .Y(n4574) ); NAND2X1TS U5688 ( .A(n4575), .B(n4574), .Y(n1104) ); MXI2X1TS U5689 ( .A(n4551), .B(n4555), .S0(DmP_mant_SFG_SWR[1]), .Y(n4576) ); OAI21X1TS U5690 ( .A0(n5208), .A1(n5419), .B0(n4576), .Y(n1139) ); CLKINVX1TS U5691 ( .A(n4577), .Y(n4580) ); NOR2X1TS U5692 ( .A(n5489), .B(inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n4578) ); NAND3BX2TS U5693 ( .AN(n4584), .B(n4583), .C(n3130), .Y(n4585) ); NOR2X1TS U5694 ( .A(n3832), .B(n5058), .Y(n4589) ); NOR2X1TS U5695 ( .A(n4716), .B(n4654), .Y(n4588) ); NAND2X1TS U5696 ( .A(n1919), .B(n5060), .Y(n4591) ); NAND2X1TS U5697 ( .A(n1869), .B(n4636), .Y(n4590) ); NAND2X2TS U5698 ( .A(n2261), .B(n2297), .Y(n4602) ); NAND2X2TS U5699 ( .A(n1869), .B(n5055), .Y(n4601) ); NAND2X1TS U5700 ( .A(n2558), .B(n5014), .Y(n4623) ); NAND2X1TS U5701 ( .A(n2555), .B(n4636), .Y(n4641) ); NAND2X1TS U5702 ( .A(n4637), .B(n5060), .Y(n4640) ); INVX2TS U5703 ( .A(n1645), .Y(n4642) ); INVX2TS U5704 ( .A(n5043), .Y(n4665) ); NOR2X1TS U5705 ( .A(n4669), .B(n4668), .Y(n4670) ); INVX2TS U5706 ( .A(n5037), .Y(n4674) ); NOR2X1TS U5707 ( .A(n3833), .B(n4675), .Y(n4676) ); NAND2X2TS U5708 ( .A(n4722), .B(n5042), .Y(n4688) ); NOR2X1TS U5709 ( .A(n4689), .B(n5058), .Y(n4690) ); NAND2X2TS U5710 ( .A(n4692), .B(n4691), .Y(n4694) ); NAND2X2TS U5711 ( .A(n4723), .B(n5023), .Y(n4693) ); INVX2TS U5712 ( .A(n5014), .Y(n4697) ); INVX2TS U5713 ( .A(n4699), .Y(n5059) ); NOR2X1TS U5714 ( .A(n3832), .B(n5059), .Y(n4700) ); NAND2X1TS U5715 ( .A(n4704), .B(n4711), .Y(n4705) ); AOI2BB2X1TS U5716 ( .B0(n4708), .B1(n4707), .A0N(n4706), .A1N(n5012), .Y( n4714) ); NOR2X1TS U5717 ( .A(n4716), .B(n4715), .Y(n4720) ); NAND2X2TS U5718 ( .A(n4723), .B(n5038), .Y(n4724) ); INVX2TS U5719 ( .A(n4728), .Y(n4732) ); NOR2X1TS U5720 ( .A(n4729), .B(intDX_EWSW[63]), .Y(n4730) ); NAND2X2TS U5721 ( .A(n4732), .B(n4731), .Y(n5162) ); OAI21X4TS U5722 ( .A0(n2362), .A1(n4747), .B0(n4746), .Y(n4750) ); NAND2X2TS U5723 ( .A(n3297), .B(n4759), .Y(n4760) ); OAI21X4TS U5724 ( .A0(n4962), .A1(n3207), .B0(n4779), .Y(n4772) ); OAI21X4TS U5725 ( .A0(n2653), .A1(n4765), .B0(n4764), .Y(n4768) ); AOI21X4TS U5726 ( .A0(n4772), .A1(n4771), .B0(n4770), .Y(n4773) ); OAI21X4TS U5727 ( .A0(n2362), .A1(n4774), .B0(n4773), .Y(n4777) ); OAI21X4TS U5728 ( .A0(n2362), .A1(n4958), .B0(n4962), .Y(n4778) ); OAI21X4TS U5729 ( .A0(n2362), .A1(n4784), .B0(n5325), .Y(n4786) ); NAND2X1TS U5730 ( .A(n2535), .B(DmP_EXP_EWSW[57]), .Y(n4787) ); NAND2X2TS U5731 ( .A(n3630), .B(intDX_EWSW[34]), .Y(n4797) ); NAND2X1TS U5732 ( .A(n4839), .B(DmP_EXP_EWSW[34]), .Y(n4795) ); NAND2X2TS U5733 ( .A(n1838), .B(intDX_EWSW[29]), .Y(n4800) ); NAND2X1TS U5734 ( .A(n4839), .B(DmP_EXP_EWSW[29]), .Y(n4798) ); NAND2X2TS U5735 ( .A(n2531), .B(intDX_EWSW[27]), .Y(n4810) ); NAND2X1TS U5736 ( .A(n4834), .B(DmP_EXP_EWSW[27]), .Y(n4808) ); NAND2X2TS U5737 ( .A(n3630), .B(intDX_EWSW[35]), .Y(n4813) ); NAND2X1TS U5738 ( .A(n4839), .B(DmP_EXP_EWSW[35]), .Y(n4811) ); NAND2X2TS U5739 ( .A(n3124), .B(intDX_EWSW[36]), .Y(n4816) ); NAND2X2TS U5740 ( .A(n3124), .B(intDX_EWSW[31]), .Y(n4819) ); NAND2X2TS U5741 ( .A(n4424), .B(intDX_EWSW[37]), .Y(n4822) ); NAND2X2TS U5742 ( .A(n4424), .B(intDX_EWSW[28]), .Y(n4825) ); NAND2X1TS U5743 ( .A(n4839), .B(DmP_EXP_EWSW[28]), .Y(n4823) ); NAND2X2TS U5744 ( .A(n2530), .B(intDX_EWSW[45]), .Y(n4827) ); NAND2X1TS U5745 ( .A(n4839), .B(DmP_EXP_EWSW[45]), .Y(n4826) ); NAND2X2TS U5746 ( .A(n4430), .B(intDX_EWSW[50]), .Y(n4837) ); NAND2X1TS U5747 ( .A(n4834), .B(DmP_EXP_EWSW[50]), .Y(n4835) ); NAND2X2TS U5748 ( .A(n2530), .B(intDX_EWSW[26]), .Y(n4842) ); NAND2X1TS U5749 ( .A(n4839), .B(DmP_EXP_EWSW[26]), .Y(n4840) ); NAND2X2TS U5750 ( .A(n2027), .B(intDX_EWSW[18]), .Y(n4845) ); NAND2X1TS U5751 ( .A(n4369), .B(n2025), .Y(n4844) ); NAND2X1TS U5752 ( .A(n2536), .B(n2256), .Y(n4843) ); NAND2X1TS U5753 ( .A(n2536), .B(DmP_EXP_EWSW[20]), .Y(n4846) ); NAND2X2TS U5754 ( .A(n2963), .B(intDX_EWSW[49]), .Y(n4851) ); NAND2X1TS U5755 ( .A(n2535), .B(DmP_EXP_EWSW[49]), .Y(n4849) ); NAND2X2TS U5756 ( .A(n2116), .B(intDY_EWSW[19]), .Y(n4858) ); NAND2X1TS U5757 ( .A(n2534), .B(DmP_EXP_EWSW[19]), .Y(n4857) ); NAND2X1TS U5758 ( .A(n2536), .B(DmP_EXP_EWSW[21]), .Y(n4860) ); NAND2X2TS U5759 ( .A(n2963), .B(intDX_EWSW[5]), .Y(n4867) ); NOR2X2TS U5760 ( .A(n5493), .B(n2561), .Y(n4906) ); AOI22X1TS U5761 ( .A0(n4906), .A1(n2571), .B0(shift_value_SHT2_EWR[4]), .B1( n6229), .Y(n4868) ); NAND2X1TS U5762 ( .A(n2524), .B(DMP_EXP_EWSW[14]), .Y(n4870) ); NAND2X2TS U5763 ( .A(n1836), .B(n2310), .Y(n4876) ); NAND2X1TS U5764 ( .A(n2951), .B(intDX_EWSW[2]), .Y(n4879) ); AOI22X1TS U5765 ( .A0(n4906), .A1(n2565), .B0(shift_value_SHT2_EWR[3]), .B1( n6229), .Y(n4882) ); NAND2X1TS U5766 ( .A(n4884), .B(Raw_mant_NRM_SWR[9]), .Y(n4889) ); INVX2TS U5767 ( .A(n4885), .Y(n4888) ); OR2X2TS U5768 ( .A(n2474), .B(n4886), .Y(n4887) ); OR3X1TS U5769 ( .A(Raw_mant_NRM_SWR[5]), .B(Raw_mant_NRM_SWR[2]), .C( Raw_mant_NRM_SWR[6]), .Y(n4900) ); OAI21X4TS U5770 ( .A0(n4962), .A1(n4914), .B0(n4913), .Y(n4946) ); OAI21X4TS U5771 ( .A0(n2653), .A1(n2930), .B0(n2325), .Y(n4919) ); INVX12TS U5772 ( .A(n2930), .Y(n4987) ); NOR2X8TS U5773 ( .A(n4958), .B(n4936), .Y(n4952) ); INVX2TS U5774 ( .A(n2744), .Y(n4941) ); NAND2X2TS U5775 ( .A(n4941), .B(n4940), .Y(n4942) ); AOI21X4TS U5776 ( .A0(n4946), .A1(n3017), .B0(n4945), .Y(n4947) ); OAI21X4TS U5777 ( .A0(n2653), .A1(n4954), .B0(n4953), .Y(n4956) ); AOI21X4TS U5778 ( .A0(n3272), .A1(n4959), .B0(n2711), .Y(n4960) ); OAI21X4TS U5779 ( .A0(n4962), .A1(n4961), .B0(n4960), .Y(n4980) ); OAI21X4TS U5780 ( .A0(n2653), .A1(n4964), .B0(n4963), .Y(n4967) ); AOI21X4TS U5781 ( .A0(n4990), .A1(n4971), .B0(n4970), .Y(n4972) ); OAI21X4TS U5782 ( .A0(n2362), .A1(n4973), .B0(n4972), .Y(n4976) ); AOI21X4TS U5783 ( .A0(n4980), .A1(n1921), .B0(n4979), .Y(n4981) ); OAI21X4TS U5784 ( .A0(n2362), .A1(n4982), .B0(n4981), .Y(n4986) ); AOI21X4TS U5785 ( .A0(n4990), .A1(n4989), .B0(n4988), .Y(n4991) ); OAI21X4TS U5786 ( .A0(n2362), .A1(n4992), .B0(n4991), .Y(n4996) ); AOI22X1TS U5787 ( .A0(n5019), .A1(DmP_mant_SHT1_SW[1]), .B0(n5006), .B1( DmP_mant_SHT1_SW[0]), .Y(n5007) ); OA21X4TS U5788 ( .A0(n3022), .A1(n5417), .B0(n5007), .Y(n5008) ); NAND2X1TS U5789 ( .A(n6205), .B(n2037), .Y(n6337) ); NAND2X1TS U5790 ( .A(n6206), .B(Raw_mant_NRM_SWR[29]), .Y(n6297) ); NAND2X1TS U5791 ( .A(n6217), .B(Raw_mant_NRM_SWR[22]), .Y(n6314) ); NAND2X1TS U5792 ( .A(n2982), .B(Raw_mant_NRM_SWR[31]), .Y(n6400) ); NAND2X1TS U5793 ( .A(n6217), .B(Raw_mant_NRM_SWR[31]), .Y(n6389) ); NAND2X1TS U5794 ( .A(n6217), .B(Raw_mant_NRM_SWR[15]), .Y(n6302) ); AOI22X1TS U5795 ( .A0(n6206), .A1(Raw_mant_NRM_SWR[27]), .B0(n1859), .B1( n5041), .Y(n6403) ); AOI22X1TS U5796 ( .A0(n6206), .A1(Raw_mant_NRM_SWR[5]), .B0(n5025), .B1( n6230), .Y(n6356) ); AOI22X1TS U5797 ( .A0(n2982), .A1(Raw_mant_NRM_SWR[40]), .B0(n5042), .B1( n6228), .Y(n6331) ); INVX2TS U5798 ( .A(n5047), .Y(n5048) ); INVX2TS U5799 ( .A(n5051), .Y(n5052) ); INVX2TS U5800 ( .A(n5055), .Y(n5056) ); INVX2TS U5801 ( .A(n5060), .Y(n5062) ); AOI21X4TS U5802 ( .A0(n5066), .A1(n2757), .B0(n5065), .Y(n5067) ); OAI21X4TS U5803 ( .A0(n5068), .A1(n5096), .B0(n5067), .Y(n5071) ); XNOR2X4TS U5804 ( .A(n5071), .B(n5070), .Y(n5072) ); CLKMX2X2TS U5805 ( .A(n5072), .B(Raw_mant_NRM_SWR[19]), .S0(n5089), .Y(n1179) ); NAND2X2TS U5806 ( .A(n5078), .B(n5077), .Y(n5079) ); XNOR2X4TS U5807 ( .A(n5099), .B(n5098), .Y(n5100) ); CLKMX2X2TS U5808 ( .A(n5100), .B(Raw_mant_NRM_SWR[18]), .S0(n5319), .Y(n1180) ); CLKMX2X2TS U5809 ( .A(ZERO_FLAG_SHT1SHT2), .B(ZERO_FLAG_NRM), .S0(n2563), .Y(n1194) ); CLKMX2X2TS U5810 ( .A(SIGN_FLAG_SHT1SHT2), .B(SIGN_FLAG_NRM), .S0(n2562), .Y(n1185) ); CLKMX2X2TS U5811 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n2562), .Y(n1341) ); CLKMX2X2TS U5812 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n2563), .Y(n1336) ); CLKMX2X2TS U5813 ( .A(DMP_exp_NRM2_EW[10]), .B(DMP_exp_NRM_EW[10]), .S0( n2562), .Y(n1311) ); CLKBUFX3TS U5814 ( .A(n6253), .Y(n5627) ); CLKBUFX3TS U5815 ( .A(n2569), .Y(n5682) ); CLKBUFX3TS U5816 ( .A(n6253), .Y(n5625) ); CLKBUFX3TS U5817 ( .A(n6253), .Y(n5626) ); CLKBUFX3TS U5818 ( .A(n6262), .Y(n5681) ); CLKBUFX2TS U5819 ( .A(n6262), .Y(n5684) ); BUFX3TS U5820 ( .A(n2539), .Y(n6277) ); BUFX3TS U5821 ( .A(n5685), .Y(n6273) ); BUFX3TS U5822 ( .A(n6253), .Y(n5623) ); BUFX3TS U5823 ( .A(n6253), .Y(n5624) ); NAND2X1TS U5824 ( .A(n2214), .B(n5731), .Y(n5103) ); NAND2X2TS U5825 ( .A(n5103), .B(n5102), .Y(final_result_ieee[31]) ); NAND2X2TS U5826 ( .A(n6134), .B(n5104), .Y(final_result_ieee[18]) ); NAND2X1TS U5827 ( .A(n2214), .B(n5766), .Y(n5106) ); NAND2X2TS U5828 ( .A(n5106), .B(n5105), .Y(final_result_ieee[38]) ); NAND2X2TS U5829 ( .A(n6135), .B(n5107), .Y(final_result_ieee[12]) ); NAND2X2TS U5830 ( .A(n6127), .B(n5108), .Y(final_result_ieee[19]) ); NAND2X2TS U5831 ( .A(n6128), .B(n5109), .Y(final_result_ieee[11]) ); NAND2X1TS U5832 ( .A(n2211), .B(n5732), .Y(n5111) ); NAND2X2TS U5833 ( .A(n5111), .B(n5110), .Y(final_result_ieee[30]) ); NAND2X1TS U5834 ( .A(n2214), .B(n5809), .Y(n5113) ); NAND2X2TS U5835 ( .A(n5113), .B(n5112), .Y(final_result_ieee[39]) ); NAND2X2TS U5836 ( .A(n6129), .B(n5114), .Y(final_result_ieee[13]) ); NAND2X2TS U5837 ( .A(n6137), .B(n5115), .Y(final_result_ieee[20]) ); NAND2X2TS U5838 ( .A(n6136), .B(n5116), .Y(final_result_ieee[10]) ); NAND2X1TS U5839 ( .A(n2211), .B(n5768), .Y(n5118) ); NAND2X2TS U5840 ( .A(n5118), .B(n5117), .Y(final_result_ieee[37]) ); NAND2X1TS U5841 ( .A(n2211), .B(n5710), .Y(n5120) ); NAND2X2TS U5842 ( .A(n5120), .B(n5119), .Y(final_result_ieee[32]) ); NAND2X1TS U5843 ( .A(n2214), .B(n5793), .Y(n5122) ); NAND2X2TS U5844 ( .A(n5122), .B(n5121), .Y(final_result_ieee[40]) ); INVX2TS U5845 ( .A(n6147), .Y(n5686) ); AOI22X1TS U5846 ( .A0(n5126), .A1(n5161), .B0(DmP_mant_SFG_SWR[54]), .B1( n5125), .Y(n5127) ); MXI2X1TS U5847 ( .A(n4554), .B(n5128), .S0(DmP_mant_SFG_SWR[0]), .Y(n5129) ); OAI21X1TS U5848 ( .A0(n5208), .A1(n5546), .B0(n5129), .Y(n1136) ); INVX2TS U5849 ( .A(DmP_mant_SFG_SWR[13]), .Y(n5131) ); INVX2TS U5850 ( .A(DmP_mant_SFG_SWR[12]), .Y(n5133) ); CLKMX2X2TS U5851 ( .A(n6414), .B(n5133), .S0(n5232), .Y(n5134) ); OAI2BB1X2TS U5852 ( .A0N(n5149), .A1N(n6457), .B0(n5144), .Y(n1030) ); CLKMX2X2TS U5853 ( .A(n6442), .B(n5567), .S0(n5271), .Y(n5148) ); MXI2X1TS U5854 ( .A(n5164), .B(final_result_ieee[54]), .S0(n5277), .Y(n5165) ); MXI2X1TS U5855 ( .A(n5166), .B(final_result_ieee[60]), .S0(n5277), .Y(n5167) ); MXI2X1TS U5856 ( .A(n3992), .B(final_result_ieee[58]), .S0(n5277), .Y(n5168) ); MXI2X1TS U5857 ( .A(n5169), .B(final_result_ieee[52]), .S0(n5243), .Y(n5170) ); MXI2X1TS U5858 ( .A(n1910), .B(final_result_ieee[56]), .S0(n5277), .Y(n5171) ); MXI2X1TS U5859 ( .A(n5172), .B(final_result_ieee[59]), .S0(n5277), .Y(n5173) ); MXI2X1TS U5860 ( .A(n5174), .B(final_result_ieee[55]), .S0(n5277), .Y(n5175) ); MXI2X1TS U5861 ( .A(n5176), .B(final_result_ieee[53]), .S0(n5277), .Y(n5177) ); MXI2X1TS U5862 ( .A(n5178), .B(final_result_ieee[57]), .S0(n5277), .Y(n5179) ); MXI2X1TS U5863 ( .A(n5180), .B(final_result_ieee[61]), .S0(n5277), .Y(n5181) ); NAND2X2TS U5864 ( .A(n5184), .B(n5182), .Y(n6428) ); NAND2X2TS U5865 ( .A(n5184), .B(n5183), .Y(n6430) ); NAND3X2TS U5866 ( .A(n6166), .B(n5185), .C(n6165), .Y(final_result_ieee[17]) ); NAND3X2TS U5867 ( .A(n6185), .B(n5186), .C(n6184), .Y(final_result_ieee[36]) ); NAND3X2TS U5868 ( .A(n6198), .B(n5187), .C(n6197), .Y(final_result_ieee[35]) ); NAND3X2TS U5869 ( .A(n6187), .B(n5188), .C(n6186), .Y(final_result_ieee[34]) ); NAND3X2TS U5870 ( .A(n6181), .B(n5190), .C(n6180), .Y(final_result_ieee[16]) ); MXI2X1TS U5871 ( .A(n5358), .B(n5510), .S0(n5191), .Y(n1328) ); MXI2X1TS U5872 ( .A(n5357), .B(n5509), .S0(n5191), .Y(n1323) ); MXI2X1TS U5873 ( .A(n5356), .B(n5508), .S0(n5191), .Y(n1318) ); MXI2X1TS U5874 ( .A(n5500), .B(n5409), .S0(n5191), .Y(n1358) ); MXI2X1TS U5875 ( .A(n6406), .B(n5399), .S0(n5271), .Y(n1399) ); MXI2X1TS U5876 ( .A(n5499), .B(n5405), .S0(busy), .Y(n1354) ); MXI2X1TS U5877 ( .A(n5497), .B(n5403), .S0(busy), .Y(n1344) ); MXI2X1TS U5878 ( .A(n5214), .B(n5402), .S0(n2383), .Y(n1339) ); MXI2X1TS U5879 ( .A(n5501), .B(n5407), .S0(n2383), .Y(n1364) ); MXI2X1TS U5880 ( .A(n5500), .B(n5406), .S0(n2383), .Y(n1359) ); MXI2X1TS U5881 ( .A(n5498), .B(n5404), .S0(n2383), .Y(n1349) ); NAND2X1TS U5882 ( .A(n5243), .B(final_result_ieee[17]), .Y(n6429) ); NAND2X1TS U5883 ( .A(n5243), .B(final_result_ieee[36]), .Y(n6453) ); NAND2X1TS U5884 ( .A(n5243), .B(final_result_ieee[35]), .Y(n6450) ); NAND2X1TS U5885 ( .A(n5243), .B(final_result_ieee[34]), .Y(n6447) ); NAND2X1TS U5886 ( .A(n5243), .B(final_result_ieee[33]), .Y(n6444) ); NAND2X1TS U5887 ( .A(n5243), .B(final_result_ieee[15]), .Y(n6424) ); NAND2X1TS U5888 ( .A(n5243), .B(final_result_ieee[16]), .Y(n6427) ); NOR2X1TS U5889 ( .A(n6405), .B(DMP_SFG[12]), .Y(n5192) ); MXI2X1TS U5890 ( .A(n5192), .B(n5570), .S0(n5319), .Y(n1142) ); MXI2X1TS U5891 ( .A(n5404), .B(n5555), .S0(n5194), .Y(n1350) ); MXI2X1TS U5892 ( .A(n5403), .B(n5554), .S0(n5194), .Y(n1345) ); INVX2TS U5893 ( .A(DMP_EXP_EWSW[53]), .Y(n5193) ); MXI2X1TS U5894 ( .A(n5406), .B(n5193), .S0(n5194), .Y(n1360) ); MXI2X1TS U5895 ( .A(n5407), .B(n5557), .S0(n5194), .Y(n1365) ); MXI2X1TS U5896 ( .A(n5405), .B(n5556), .S0(n5194), .Y(n1355) ); MXI2X1TS U5897 ( .A(n5402), .B(n5553), .S0(n5194), .Y(n1340) ); CLKMX2X2TS U5898 ( .A(DMP_SHT2_EWSW[4]), .B(DMP_SHT1_EWSW[4]), .S0(busy), .Y(n1508) ); CLKMX2X2TS U5899 ( .A(OP_FLAG_SHT2), .B(OP_FLAG_SHT1), .S0(busy), .Y(n1191) ); CLKMX2X2TS U5900 ( .A(DMP_SHT2_EWSW[13]), .B(DMP_SHT1_EWSW[13]), .S0(busy), .Y(n1481) ); CLKMX2X2TS U5901 ( .A(DMP_SHT2_EWSW[61]), .B(DMP_SHT1_EWSW[61]), .S0(busy), .Y(n1319) ); CLKMX2X2TS U5902 ( .A(DMP_SHT2_EWSW[8]), .B(DMP_SHT1_EWSW[8]), .S0(busy), .Y(n1496) ); CLKMX2X2TS U5903 ( .A(DMP_SHT2_EWSW[58]), .B(DMP_SHT1_EWSW[58]), .S0(busy), .Y(n1334) ); CLKMX2X2TS U5904 ( .A(DMP_SHT2_EWSW[60]), .B(DMP_SHT1_EWSW[60]), .S0(busy), .Y(n1324) ); CLKMX2X2TS U5905 ( .A(DMP_SHT2_EWSW[59]), .B(DMP_SHT1_EWSW[59]), .S0(busy), .Y(n1329) ); CLKMX2X2TS U5906 ( .A(DMP_SHT1_EWSW[7]), .B(DMP_EXP_EWSW[7]), .S0(n5209), .Y(n1500) ); CLKMX2X2TS U5907 ( .A(DMP_SHT1_EWSW[12]), .B(DMP_EXP_EWSW[12]), .S0(n5210), .Y(n1485) ); CLKMX2X2TS U5908 ( .A(DMP_SHT1_EWSW[4]), .B(DMP_EXP_EWSW[4]), .S0(n5209), .Y(n1509) ); CLKMX2X2TS U5909 ( .A(DMP_SHT1_EWSW[1]), .B(DMP_EXP_EWSW[1]), .S0(n5209), .Y(n1518) ); CLKMX2X2TS U5910 ( .A(DMP_SHT1_EWSW[6]), .B(DMP_EXP_EWSW[6]), .S0(n5210), .Y(n1503) ); CLKMX2X2TS U5911 ( .A(DMP_SHT1_EWSW[11]), .B(DMP_EXP_EWSW[11]), .S0(n5209), .Y(n1488) ); CLKMX2X2TS U5912 ( .A(DMP_SHT1_EWSW[2]), .B(n2276), .S0(n5210), .Y(n1515) ); CLKMX2X2TS U5913 ( .A(DMP_SHT1_EWSW[62]), .B(DMP_EXP_EWSW[62]), .S0(n5194), .Y(n1315) ); CLKMX2X2TS U5914 ( .A(DMP_SHT1_EWSW[14]), .B(DMP_EXP_EWSW[14]), .S0(n5194), .Y(n1479) ); CLKMX2X2TS U5915 ( .A(SIGN_FLAG_SHT1), .B(SIGN_FLAG_EXP), .S0(n5194), .Y( n1189) ); CLKMX2X2TS U5916 ( .A(DMP_SHT1_EWSW[16]), .B(DMP_EXP_EWSW[16]), .S0(n5194), .Y(n1473) ); CLKMX2X2TS U5917 ( .A(DMP_SHT1_EWSW[61]), .B(DMP_EXP_EWSW[61]), .S0(n2546), .Y(n1320) ); CLKMX2X2TS U5918 ( .A(OP_FLAG_SHT1), .B(OP_FLAG_EXP), .S0(n2546), .Y(n1192) ); CLKMX2X2TS U5919 ( .A(DMP_SHT1_EWSW[59]), .B(DMP_EXP_EWSW[59]), .S0(n2546), .Y(n1330) ); CLKMX2X2TS U5920 ( .A(DMP_SHT1_EWSW[13]), .B(DMP_EXP_EWSW[13]), .S0(n2546), .Y(n1482) ); CLKMX2X2TS U5921 ( .A(DMP_SHT1_EWSW[8]), .B(DMP_EXP_EWSW[8]), .S0(n2546), .Y(n1497) ); CLKMX2X2TS U5922 ( .A(DMP_SHT1_EWSW[60]), .B(n2303), .S0(n2546), .Y(n1325) ); CLKMX2X2TS U5923 ( .A(DMP_SHT1_EWSW[58]), .B(DMP_EXP_EWSW[58]), .S0(n2546), .Y(n1335) ); CLKMX2X2TS U5924 ( .A(DMP_SHT2_EWSW[43]), .B(DMP_SHT1_EWSW[43]), .S0(n5195), .Y(n1391) ); CLKMX2X2TS U5925 ( .A(DMP_SHT2_EWSW[1]), .B(DMP_SHT1_EWSW[1]), .S0(n5196), .Y(n1517) ); CLKMX2X2TS U5926 ( .A(DMP_SHT2_EWSW[11]), .B(DMP_SHT1_EWSW[11]), .S0(n5196), .Y(n1487) ); CLKMX2X2TS U5927 ( .A(DMP_SHT2_EWSW[46]), .B(DMP_SHT1_EWSW[46]), .S0(n5195), .Y(n1382) ); CLKMX2X2TS U5928 ( .A(DMP_SHT2_EWSW[51]), .B(DMP_SHT1_EWSW[51]), .S0(n5195), .Y(n1367) ); CLKMX2X2TS U5929 ( .A(DMP_SHT2_EWSW[45]), .B(DMP_SHT1_EWSW[45]), .S0(n5195), .Y(n1385) ); CLKMX2X2TS U5930 ( .A(DMP_SHT2_EWSW[5]), .B(DMP_SHT1_EWSW[5]), .S0(n5196), .Y(n1505) ); CLKMX2X2TS U5931 ( .A(DMP_SHT2_EWSW[48]), .B(DMP_SHT1_EWSW[48]), .S0(n5195), .Y(n1376) ); CLKMX2X2TS U5932 ( .A(DMP_SHT2_EWSW[12]), .B(DMP_SHT1_EWSW[12]), .S0(n5196), .Y(n1484) ); CLKMX2X2TS U5933 ( .A(DMP_SHT2_EWSW[3]), .B(DMP_SHT1_EWSW[3]), .S0(n5195), .Y(n1511) ); CLKMX2X2TS U5934 ( .A(DMP_SHT2_EWSW[0]), .B(DMP_SHT1_EWSW[0]), .S0(n5196), .Y(n1520) ); CLKMX2X2TS U5935 ( .A(DMP_SHT2_EWSW[44]), .B(DMP_SHT1_EWSW[44]), .S0(n5195), .Y(n1388) ); CLKMX2X2TS U5936 ( .A(DMP_SHT2_EWSW[49]), .B(DMP_SHT1_EWSW[49]), .S0(n5195), .Y(n1373) ); CLKMX2X2TS U5937 ( .A(DMP_SHT2_EWSW[50]), .B(DMP_SHT1_EWSW[50]), .S0(n5195), .Y(n1370) ); CLKMX2X2TS U5938 ( .A(DMP_SHT2_EWSW[2]), .B(DMP_SHT1_EWSW[2]), .S0(n5196), .Y(n1514) ); CLKMX2X2TS U5939 ( .A(DMP_SHT2_EWSW[6]), .B(DMP_SHT1_EWSW[6]), .S0(n5196), .Y(n1502) ); CLKMX2X2TS U5940 ( .A(DMP_SHT2_EWSW[47]), .B(DMP_SHT1_EWSW[47]), .S0(n5195), .Y(n1379) ); CLKMX2X2TS U5941 ( .A(DMP_SHT2_EWSW[9]), .B(DMP_SHT1_EWSW[9]), .S0(n5196), .Y(n1493) ); CLKMX2X2TS U5942 ( .A(DMP_SHT2_EWSW[10]), .B(DMP_SHT1_EWSW[10]), .S0(n5196), .Y(n1490) ); CLKMX2X2TS U5943 ( .A(DMP_SHT2_EWSW[7]), .B(DMP_SHT1_EWSW[7]), .S0(n5196), .Y(n1499) ); BUFX8TS U5944 ( .A(n5493), .Y(n5284) ); CLKMX2X2TS U5945 ( .A(DMP_SHT2_EWSW[37]), .B(DMP_SHT1_EWSW[37]), .S0(n5197), .Y(n1409) ); CLKMX2X2TS U5946 ( .A(SIGN_FLAG_SHT2), .B(SIGN_FLAG_SHT1), .S0(n5199), .Y( n1188) ); CLKMX2X2TS U5947 ( .A(DMP_SHT2_EWSW[36]), .B(DMP_SHT1_EWSW[36]), .S0(n5197), .Y(n1412) ); CLKMX2X2TS U5948 ( .A(DMP_SHT2_EWSW[30]), .B(DMP_SHT1_EWSW[30]), .S0(n5198), .Y(n1430) ); CLKMX2X2TS U5949 ( .A(DMP_SHT2_EWSW[31]), .B(DMP_SHT1_EWSW[31]), .S0(n5198), .Y(n1427) ); CLKMX2X2TS U5950 ( .A(DMP_SHT2_EWSW[25]), .B(DMP_SHT1_EWSW[25]), .S0(n5198), .Y(n1445) ); CLKMX2X2TS U5951 ( .A(DMP_SHT2_EWSW[34]), .B(DMP_SHT1_EWSW[34]), .S0(n5197), .Y(n1418) ); CLKMX2X2TS U5952 ( .A(DMP_SHT2_EWSW[41]), .B(DMP_SHT1_EWSW[41]), .S0(n5197), .Y(n1397) ); CLKMX2X2TS U5953 ( .A(DMP_SHT2_EWSW[26]), .B(DMP_SHT1_EWSW[26]), .S0(n5198), .Y(n1442) ); CLKMX2X2TS U5954 ( .A(DMP_SHT2_EWSW[33]), .B(DMP_SHT1_EWSW[33]), .S0(n5198), .Y(n1421) ); CLKMX2X2TS U5955 ( .A(DMP_SHT2_EWSW[42]), .B(DMP_SHT1_EWSW[42]), .S0(n5197), .Y(n1394) ); CLKMX2X2TS U5956 ( .A(DMP_SHT2_EWSW[32]), .B(DMP_SHT1_EWSW[32]), .S0(n5198), .Y(n1424) ); CLKMX2X2TS U5957 ( .A(DMP_SHT2_EWSW[40]), .B(DMP_SHT1_EWSW[40]), .S0(n5197), .Y(n1400) ); CLKMX2X2TS U5958 ( .A(DMP_SHT2_EWSW[39]), .B(DMP_SHT1_EWSW[39]), .S0(n5197), .Y(n1403) ); CLKMX2X2TS U5959 ( .A(DMP_SHT2_EWSW[35]), .B(DMP_SHT1_EWSW[35]), .S0(n5197), .Y(n1415) ); CLKMX2X2TS U5960 ( .A(DMP_SHT2_EWSW[24]), .B(DMP_SHT1_EWSW[24]), .S0(n5198), .Y(n1448) ); CLKMX2X2TS U5961 ( .A(DMP_SHT2_EWSW[28]), .B(DMP_SHT1_EWSW[28]), .S0(n5198), .Y(n1436) ); CLKMX2X2TS U5962 ( .A(DMP_SHT2_EWSW[27]), .B(DMP_SHT1_EWSW[27]), .S0(n5197), .Y(n1439) ); CLKMX2X2TS U5963 ( .A(DMP_SHT2_EWSW[38]), .B(DMP_SHT1_EWSW[38]), .S0(n5197), .Y(n1406) ); CLKMX2X2TS U5964 ( .A(ZERO_FLAG_SHT2), .B(ZERO_FLAG_SHT1), .S0(n5199), .Y( n1197) ); CLKMX2X2TS U5965 ( .A(DMP_SHT2_EWSW[29]), .B(DMP_SHT1_EWSW[29]), .S0(n5198), .Y(n1433) ); CLKMX2X2TS U5966 ( .A(DMP_SHT2_EWSW[20]), .B(DMP_SHT1_EWSW[20]), .S0(n5199), .Y(n1460) ); CLKMX2X2TS U5967 ( .A(DMP_SHT2_EWSW[19]), .B(DMP_SHT1_EWSW[19]), .S0(n5199), .Y(n1463) ); CLKMX2X2TS U5968 ( .A(DMP_SHT2_EWSW[16]), .B(DMP_SHT1_EWSW[16]), .S0(n5199), .Y(n1472) ); CLKMX2X2TS U5969 ( .A(DMP_SHT2_EWSW[15]), .B(DMP_SHT1_EWSW[15]), .S0(n5199), .Y(n1475) ); CLKMX2X2TS U5970 ( .A(DMP_SHT2_EWSW[23]), .B(DMP_SHT1_EWSW[23]), .S0(n5198), .Y(n1451) ); CLKMX2X2TS U5971 ( .A(DMP_SHT2_EWSW[22]), .B(DMP_SHT1_EWSW[22]), .S0(n5199), .Y(n1454) ); CLKMX2X2TS U5972 ( .A(DMP_SHT2_EWSW[18]), .B(DMP_SHT1_EWSW[18]), .S0(n5199), .Y(n1466) ); CLKMX2X2TS U5973 ( .A(DMP_SHT2_EWSW[21]), .B(DMP_SHT1_EWSW[21]), .S0(n5199), .Y(n1457) ); CLKMX2X2TS U5974 ( .A(DMP_SHT2_EWSW[17]), .B(DMP_SHT1_EWSW[17]), .S0(n5199), .Y(n1469) ); CLKMX2X2TS U5975 ( .A(DmP_mant_SHT1_SW[7]), .B(DmP_EXP_EWSW[7]), .S0(n5207), .Y(n1295) ); CLKMX2X2TS U5976 ( .A(n2548), .B(DmP_EXP_EWSW[4]), .S0(n5207), .Y(n1301) ); CLKMX2X2TS U5977 ( .A(DMP_SHT1_EWSW[40]), .B(n2123), .S0(n5201), .Y(n1401) ); CLKMX2X2TS U5978 ( .A(DMP_SHT1_EWSW[5]), .B(DMP_EXP_EWSW[5]), .S0(n5211), .Y(n1506) ); CLKMX2X2TS U5979 ( .A(DMP_SHT1_EWSW[39]), .B(DMP_EXP_EWSW[39]), .S0(n5201), .Y(n1404) ); CLKMX2X2TS U5980 ( .A(DMP_SHT1_EWSW[51]), .B(DMP_EXP_EWSW[51]), .S0(n5206), .Y(n1368) ); CLKMX2X2TS U5981 ( .A(DMP_SHT1_EWSW[48]), .B(DMP_EXP_EWSW[48]), .S0(n5206), .Y(n1377) ); CLKMX2X2TS U5982 ( .A(DMP_SHT1_EWSW[37]), .B(DMP_EXP_EWSW[37]), .S0(n5201), .Y(n1410) ); CLKMX2X2TS U5983 ( .A(DMP_SHT1_EWSW[9]), .B(DMP_EXP_EWSW[9]), .S0(n5211), .Y(n1494) ); CLKMX2X2TS U5984 ( .A(DmP_mant_SHT1_SW[1]), .B(DmP_EXP_EWSW[1]), .S0(n5207), .Y(n1307) ); CLKMX2X2TS U5985 ( .A(DMP_SHT1_EWSW[0]), .B(DMP_EXP_EWSW[0]), .S0(n5211), .Y(n1521) ); CLKMX2X2TS U5986 ( .A(DMP_SHT1_EWSW[42]), .B(DMP_EXP_EWSW[42]), .S0(n5201), .Y(n1395) ); CLKMX2X2TS U5987 ( .A(DmP_mant_SHT1_SW[0]), .B(DmP_EXP_EWSW[0]), .S0(n5207), .Y(n1309) ); CLKMX2X2TS U5988 ( .A(DMP_SHT1_EWSW[3]), .B(DMP_EXP_EWSW[3]), .S0(n5206), .Y(n1512) ); CLKMX2X2TS U5989 ( .A(DmP_mant_SHT1_SW[28]), .B(DmP_EXP_EWSW[28]), .S0(n5204), .Y(n1253) ); CLKMX2X2TS U5990 ( .A(DMP_SHT1_EWSW[36]), .B(DMP_EXP_EWSW[36]), .S0(n5201), .Y(n1413) ); CLKMX2X2TS U5991 ( .A(DMP_SHT1_EWSW[47]), .B(DMP_EXP_EWSW[47]), .S0(n5206), .Y(n1380) ); CLKMX2X2TS U5992 ( .A(DMP_SHT1_EWSW[50]), .B(n1537), .S0(n5206), .Y(n1371) ); CLKMX2X2TS U5993 ( .A(DMP_SHT1_EWSW[43]), .B(n2122), .S0(n5201), .Y(n1392) ); CLKMX2X2TS U5994 ( .A(DMP_SHT1_EWSW[49]), .B(DMP_EXP_EWSW[49]), .S0(n5206), .Y(n1374) ); CLKMX2X2TS U5995 ( .A(DMP_SHT1_EWSW[44]), .B(DMP_EXP_EWSW[44]), .S0(n5201), .Y(n1389) ); CLKMX2X2TS U5996 ( .A(DMP_SHT1_EWSW[38]), .B(n1549), .S0(n5201), .Y(n1407) ); CLKMX2X2TS U5997 ( .A(DMP_SHT1_EWSW[41]), .B(DMP_EXP_EWSW[41]), .S0(n5201), .Y(n1398) ); CLKMX2X2TS U5998 ( .A(DMP_SHT1_EWSW[10]), .B(DMP_EXP_EWSW[10]), .S0(n5211), .Y(n1491) ); CLKMX2X2TS U5999 ( .A(DMP_SHT1_EWSW[45]), .B(DMP_EXP_EWSW[45]), .S0(n5201), .Y(n1386) ); CLKMX2X2TS U6000 ( .A(DMP_SHT1_EWSW[46]), .B(DMP_EXP_EWSW[46]), .S0(n5206), .Y(n1383) ); CLKMX2X2TS U6001 ( .A(ZERO_FLAG_SHT1), .B(ZERO_FLAG_EXP), .S0(n5213), .Y( n1198) ); CLKMX2X2TS U6002 ( .A(DMP_SHT1_EWSW[18]), .B(DMP_EXP_EWSW[18]), .S0(n5202), .Y(n1467) ); CLKMX2X2TS U6003 ( .A(DMP_SHT1_EWSW[23]), .B(DMP_EXP_EWSW[23]), .S0(n5202), .Y(n1452) ); CLKMX2X2TS U6004 ( .A(DMP_SHT1_EWSW[33]), .B(DMP_EXP_EWSW[33]), .S0(n5203), .Y(n1422) ); CLKMX2X2TS U6005 ( .A(DMP_SHT1_EWSW[26]), .B(DMP_EXP_EWSW[26]), .S0(n5203), .Y(n1443) ); CLKMX2X2TS U6006 ( .A(DMP_SHT1_EWSW[28]), .B(DMP_EXP_EWSW[28]), .S0(n5203), .Y(n1437) ); CLKMX2X2TS U6007 ( .A(DMP_SHT1_EWSW[22]), .B(DMP_EXP_EWSW[22]), .S0(n5202), .Y(n1455) ); CLKMX2X2TS U6008 ( .A(DMP_SHT1_EWSW[19]), .B(n2259), .S0(n5202), .Y(n1464) ); CLKMX2X2TS U6009 ( .A(DMP_SHT1_EWSW[24]), .B(DMP_EXP_EWSW[24]), .S0(n5202), .Y(n1449) ); CLKMX2X2TS U6010 ( .A(DMP_SHT1_EWSW[17]), .B(DMP_EXP_EWSW[17]), .S0(n5202), .Y(n1470) ); CLKMX2X2TS U6011 ( .A(DMP_SHT1_EWSW[15]), .B(DMP_EXP_EWSW[15]), .S0(n5202), .Y(n1476) ); CLKMX2X2TS U6012 ( .A(DMP_SHT1_EWSW[21]), .B(n2255), .S0(n5202), .Y(n1458) ); CLKMX2X2TS U6013 ( .A(DMP_SHT1_EWSW[20]), .B(DMP_EXP_EWSW[20]), .S0(n5202), .Y(n1461) ); CLKMX2X2TS U6014 ( .A(DMP_SHT1_EWSW[35]), .B(DMP_EXP_EWSW[35]), .S0(n5203), .Y(n1416) ); CLKMX2X2TS U6015 ( .A(DMP_SHT1_EWSW[25]), .B(DMP_EXP_EWSW[25]), .S0(n5202), .Y(n1446) ); CLKMX2X2TS U6016 ( .A(DMP_SHT1_EWSW[32]), .B(DMP_EXP_EWSW[32]), .S0(n5203), .Y(n1425) ); CLKMX2X2TS U6017 ( .A(DMP_SHT1_EWSW[27]), .B(DMP_EXP_EWSW[27]), .S0(n5203), .Y(n1440) ); CLKMX2X2TS U6018 ( .A(DMP_SHT1_EWSW[29]), .B(DMP_EXP_EWSW[29]), .S0(n5203), .Y(n1434) ); CLKMX2X2TS U6019 ( .A(DMP_SHT1_EWSW[31]), .B(DMP_EXP_EWSW[31]), .S0(n5203), .Y(n1428) ); CLKMX2X2TS U6020 ( .A(DMP_SHT1_EWSW[30]), .B(DMP_EXP_EWSW[30]), .S0(n5203), .Y(n1431) ); CLKMX2X2TS U6021 ( .A(DMP_SHT1_EWSW[34]), .B(n1553), .S0(n5203), .Y(n1419) ); CLKMX2X2TS U6022 ( .A(DmP_mant_SHT1_SW[35]), .B(DmP_EXP_EWSW[35]), .S0(n5204), .Y(n1239) ); CLKMX2X2TS U6023 ( .A(DmP_mant_SHT1_SW[43]), .B(DmP_EXP_EWSW[43]), .S0(n5211), .Y(n1223) ); CLKMX2X2TS U6024 ( .A(DmP_mant_SHT1_SW[44]), .B(DmP_EXP_EWSW[44]), .S0(n5211), .Y(n1221) ); CLKMX2X2TS U6025 ( .A(DmP_mant_SHT1_SW[45]), .B(DmP_EXP_EWSW[45]), .S0(n5204), .Y(n1219) ); CLKMX2X2TS U6026 ( .A(DmP_mant_SHT1_SW[42]), .B(DmP_EXP_EWSW[42]), .S0(n5211), .Y(n1225) ); CLKMX2X2TS U6027 ( .A(DmP_mant_SHT1_SW[33]), .B(DmP_EXP_EWSW[33]), .S0(n5210), .Y(n1243) ); CLKMX2X2TS U6028 ( .A(DmP_mant_SHT1_SW[40]), .B(DmP_EXP_EWSW[40]), .S0(n5211), .Y(n1229) ); CLKMX2X2TS U6029 ( .A(DmP_mant_SHT1_SW[15]), .B(DmP_EXP_EWSW[15]), .S0(n5213), .Y(n1279) ); CLKMX2X2TS U6030 ( .A(DmP_mant_SHT1_SW[23]), .B(DmP_EXP_EWSW[23]), .S0(n5210), .Y(n1263) ); CLKMX2X2TS U6031 ( .A(DmP_mant_SHT1_SW[30]), .B(DmP_EXP_EWSW[30]), .S0(n5204), .Y(n1249) ); CLKMX2X2TS U6032 ( .A(n2572), .B(DmP_EXP_EWSW[5]), .S0(n5213), .Y(n1299) ); CLKMX2X2TS U6033 ( .A(zero_flag), .B(ZERO_FLAG_SHT1SHT2), .S0(n5289), .Y( n1193) ); CLKMX2X2TS U6034 ( .A(DmP_mant_SHT1_SW[16]), .B(DmP_EXP_EWSW[16]), .S0(n5213), .Y(n1277) ); CLKMX2X2TS U6035 ( .A(DmP_mant_SHT1_SW[9]), .B(DmP_EXP_EWSW[9]), .S0(n5207), .Y(n1291) ); CLKMX2X2TS U6036 ( .A(DmP_mant_SHT1_SW[25]), .B(DmP_EXP_EWSW[25]), .S0(n5210), .Y(n1259) ); CLKMX2X2TS U6037 ( .A(DmP_mant_SHT1_SW[38]), .B(DmP_EXP_EWSW[38]), .S0(n5213), .Y(n1233) ); CLKMX2X2TS U6038 ( .A(DmP_mant_SHT1_SW[17]), .B(DmP_EXP_EWSW[17]), .S0(n5209), .Y(n1275) ); CLKMX2X2TS U6039 ( .A(DmP_mant_SHT1_SW[13]), .B(DmP_EXP_EWSW[13]), .S0(n5207), .Y(n1283) ); CLKMX2X2TS U6040 ( .A(DmP_mant_SHT1_SW[48]), .B(DmP_EXP_EWSW[48]), .S0(n5213), .Y(n1213) ); CLKMX2X2TS U6041 ( .A(DmP_mant_SHT1_SW[11]), .B(n1864), .S0(n5206), .Y(n1287) ); CLKMX2X2TS U6042 ( .A(DMP_exp_NRM_EW[4]), .B(DMP_SFG[56]), .S0(n3179), .Y( n1342) ); CLKMX2X2TS U6043 ( .A(SIGN_FLAG_NRM), .B(SIGN_FLAG_SFG), .S0(n3179), .Y( n1186) ); CLKMX2X2TS U6044 ( .A(DMP_exp_NRM_EW[6]), .B(DMP_SFG[58]), .S0(n3179), .Y( n1332) ); CLKMX2X2TS U6045 ( .A(DMP_exp_NRM_EW[7]), .B(DMP_SFG[59]), .S0(n3179), .Y( n1327) ); CLKMX2X2TS U6046 ( .A(DMP_exp_NRM_EW[8]), .B(DMP_SFG[60]), .S0(n3179), .Y( n1322) ); CLKMX2X2TS U6047 ( .A(DMP_exp_NRM_EW[10]), .B(DMP_SFG[62]), .S0(n3179), .Y( n1312) ); CLKMX2X2TS U6048 ( .A(DMP_exp_NRM_EW[9]), .B(DMP_SFG[61]), .S0(n3179), .Y( n1317) ); CLKMX2X2TS U6049 ( .A(DmP_mant_SHT1_SW[14]), .B(n2313), .S0(n5207), .Y(n1281) ); CLKMX2X2TS U6050 ( .A(DmP_mant_SHT1_SW[12]), .B(DmP_EXP_EWSW[12]), .S0(n5206), .Y(n1285) ); CLKMX2X2TS U6051 ( .A(DmP_mant_SHT1_SW[10]), .B(DmP_EXP_EWSW[10]), .S0(n5207), .Y(n1289) ); CLKMX2X2TS U6052 ( .A(DmP_mant_SHT1_SW[32]), .B(DmP_EXP_EWSW[32]), .S0(n5210), .Y(n1245) ); CLKMX2X2TS U6053 ( .A(DmP_mant_SHT1_SW[39]), .B(DmP_EXP_EWSW[39]), .S0(n5211), .Y(n1231) ); CLKMX2X2TS U6054 ( .A(DMP_exp_NRM_EW[5]), .B(DMP_SFG[57]), .S0(n5208), .Y( n1337) ); CLKMX2X2TS U6055 ( .A(DMP_exp_NRM_EW[2]), .B(DMP_SFG[54]), .S0(n5208), .Y( n1352) ); CLKMX2X2TS U6056 ( .A(DMP_exp_NRM_EW[3]), .B(DMP_SFG[55]), .S0(n5208), .Y( n1347) ); CLKMX2X2TS U6057 ( .A(DMP_exp_NRM_EW[0]), .B(DMP_SFG[52]), .S0(n5208), .Y( n1362) ); CLKMX2X2TS U6058 ( .A(DMP_exp_NRM_EW[1]), .B(DMP_SFG[53]), .S0(n5208), .Y( n1357) ); CLKMX2X2TS U6059 ( .A(DmP_mant_SHT1_SW[50]), .B(DmP_EXP_EWSW[50]), .S0(n5209), .Y(n1209) ); CLKMX2X2TS U6060 ( .A(DmP_mant_SHT1_SW[6]), .B(DmP_EXP_EWSW[6]), .S0(n5213), .Y(n1297) ); CLKMX2X2TS U6061 ( .A(DmP_mant_SHT1_SW[19]), .B(DmP_EXP_EWSW[19]), .S0(n5209), .Y(n1271) ); CLKMX2X2TS U6062 ( .A(DmP_mant_SHT1_SW[49]), .B(DmP_EXP_EWSW[49]), .S0(n5209), .Y(n1211) ); CLKMX2X2TS U6063 ( .A(DmP_mant_SHT1_SW[20]), .B(DmP_EXP_EWSW[20]), .S0(n5209), .Y(n1269) ); CLKMX2X2TS U6064 ( .A(DmP_mant_SHT1_SW[22]), .B(DmP_EXP_EWSW[22]), .S0(n5210), .Y(n1265) ); CLKMX2X2TS U6065 ( .A(DmP_mant_SHT1_SW[41]), .B(DmP_EXP_EWSW[41]), .S0(n5211), .Y(n1227) ); MXI2X1TS U6066 ( .A(n5212), .B(inst_FSM_INPUT_ENABLE_state_reg[0]), .S0( inst_FSM_INPUT_ENABLE_state_reg[1]), .Y( inst_FSM_INPUT_ENABLE_state_next_1_) ); CLKMX2X2TS U6067 ( .A(DmP_mant_SHT1_SW[3]), .B(DmP_EXP_EWSW[3]), .S0(n5213), .Y(n1303) ); MXI2X1TS U6068 ( .A(n5214), .B(n5408), .S0(n5191), .Y(n1338) ); INVX2TS U6069 ( .A(DMP_SFG[22]), .Y(n5215) ); MXI2X1TS U6070 ( .A(n5388), .B(n5215), .S0(n5191), .Y(n1453) ); CLKMX2X3TS U6071 ( .A(Data_X[63]), .B(intDX_EWSW[63]), .S0(n5242), .Y(n1731) ); MXI2X1TS U6072 ( .A(n5383), .B(n5516), .S0(n5216), .Y(n1438) ); MXI2X1TS U6073 ( .A(n5385), .B(n5464), .S0(n5216), .Y(n1444) ); MXI2X1TS U6074 ( .A(n5381), .B(n5484), .S0(n5216), .Y(n1432) ); MXI2X1TS U6075 ( .A(n5387), .B(n5465), .S0(n5224), .Y(n1450) ); MXI2X1TS U6076 ( .A(n5386), .B(n5476), .S0(n5232), .Y(n1447) ); MXI2X1TS U6077 ( .A(n5390), .B(n5461), .S0(n5265), .Y(n1459) ); MXI2X1TS U6078 ( .A(n5395), .B(n5486), .S0(n5265), .Y(n1474) ); MXI2X1TS U6079 ( .A(n5396), .B(n5473), .S0(n5245), .Y(n1477) ); MXI2X1TS U6080 ( .A(n5392), .B(n5477), .S0(n5232), .Y(n1465) ); MXI2X1TS U6081 ( .A(n5389), .B(n5485), .S0(n5271), .Y(n1456) ); MXI2X1TS U6082 ( .A(n5393), .B(n5466), .S0(n5224), .Y(n1468) ); MXI2X1TS U6083 ( .A(n5391), .B(n5517), .S0(n5245), .Y(n1462) ); INVX2TS U6084 ( .A(DMP_SFG[55]), .Y(n5219) ); MXI2X1TS U6085 ( .A(n5498), .B(n5219), .S0(n2505), .Y(n1348) ); MXI2X1TS U6086 ( .A(n5449), .B(n5347), .S0(n5224), .Y(n1507) ); MXI2X1TS U6087 ( .A(n5448), .B(n5346), .S0(n5265), .Y(n1495) ); MXI2X1TS U6088 ( .A(n5452), .B(n5350), .S0(n5232), .Y(n1516) ); MXI2X1TS U6089 ( .A(n5450), .B(n5348), .S0(n5245), .Y(n1498) ); INVX2TS U6090 ( .A(DMP_SFG[58]), .Y(n5220) ); MXI2X1TS U6091 ( .A(n5359), .B(n5220), .S0(n5264), .Y(n1333) ); INVX2TS U6092 ( .A(DMP_SFG[56]), .Y(n5221) ); MXI2X1TS U6093 ( .A(n5497), .B(n5221), .S0(n5264), .Y(n1343) ); INVX2TS U6094 ( .A(DMP_SFG[54]), .Y(n5222) ); MXI2X1TS U6095 ( .A(n5499), .B(n5222), .S0(n2554), .Y(n1353) ); INVX2TS U6096 ( .A(DMP_SFG[52]), .Y(n5223) ); MXI2X1TS U6097 ( .A(n5501), .B(n5223), .S0(n5264), .Y(n1363) ); MXI2X1TS U6098 ( .A(n5360), .B(n5467), .S0(n5271), .Y(n1480) ); MXI2X1TS U6099 ( .A(n5338), .B(n5400), .S0(n5271), .Y(n1402) ); INVX2TS U6100 ( .A(DMP_SFG[62]), .Y(n5225) ); MXI2X1TS U6101 ( .A(n5226), .B(n5225), .S0(n5245), .Y(n1313) ); INVX2TS U6102 ( .A(DMP_SFG[49]), .Y(n5228) ); MXI2X1TS U6103 ( .A(n5459), .B(n5228), .S0(n5265), .Y(n1372) ); INVX2TS U6104 ( .A(DMP_SFG[50]), .Y(n5229) ); MXI2X1TS U6105 ( .A(n5364), .B(n5229), .S0(n5264), .Y(n1369) ); INVX2TS U6106 ( .A(SIGN_FLAG_SFG), .Y(n5230) ); MXI2X1TS U6107 ( .A(n5397), .B(n5230), .S0(n5245), .Y(n1187) ); INVX2TS U6108 ( .A(DMP_SFG[51]), .Y(n5231) ); MXI2X1TS U6109 ( .A(n5363), .B(n5231), .S0(n5245), .Y(n1366) ); MXI2X1TS U6110 ( .A(n6464), .B(n5410), .S0(n5224), .Y(n1196) ); MXI2X1TS U6111 ( .A(n5373), .B(n5514), .S0(n5271), .Y(n1408) ); MXI2X1TS U6112 ( .A(n5372), .B(n5469), .S0(n5232), .Y(n1405) ); MXI2X1TS U6113 ( .A(n5370), .B(n5480), .S0(n5159), .Y(n1390) ); MXI2X1TS U6114 ( .A(n5368), .B(n5479), .S0(n5271), .Y(n1384) ); MXI2X1TS U6115 ( .A(n5366), .B(n5513), .S0(n5159), .Y(n1378) ); MXI2X1TS U6116 ( .A(n5337), .B(n5398), .S0(n5271), .Y(n1396) ); MXI2X1TS U6117 ( .A(n5377), .B(n5481), .S0(n5232), .Y(n1420) ); MXI2X1TS U6118 ( .A(n5365), .B(n5460), .S0(n5159), .Y(n1375) ); MXI2X1TS U6119 ( .A(n5371), .B(n5462), .S0(n5245), .Y(n1393) ); MXI2X1TS U6120 ( .A(n5374), .B(n5463), .S0(n5232), .Y(n1411) ); MXI2X1TS U6121 ( .A(n5375), .B(n5515), .S0(n5232), .Y(n1414) ); MXI2X1TS U6122 ( .A(n5376), .B(n5470), .S0(n5224), .Y(n1417) ); MXI2X1TS U6123 ( .A(n5367), .B(n5468), .S0(n5224), .Y(n1381) ); MXI2X1TS U6124 ( .A(n5378), .B(n5482), .S0(n5159), .Y(n1423) ); MXI2X1TS U6125 ( .A(n5369), .B(n5474), .S0(n5159), .Y(n1387) ); CLKMX2X3TS U6126 ( .A(Data_Y[45]), .B(n2299), .S0(n5235), .Y(n1683) ); CLKMX2X2TS U6127 ( .A(Data_X[43]), .B(intDX_EWSW[43]), .S0(n5239), .Y(n1751) ); CLKMX2X2TS U6128 ( .A(Data_X[33]), .B(intDX_EWSW[33]), .S0(n5237), .Y(n1761) ); CLKMX2X2TS U6129 ( .A(Data_X[14]), .B(intDX_EWSW[14]), .S0(n5240), .Y(n1780) ); MXI2X1TS U6130 ( .A(n5447), .B(n5205), .S0(n5314), .Y(n1797) ); MXI2X1TS U6131 ( .A(n5089), .B(n2384), .S0(n5314), .Y(n1796) ); MXI2X1TS U6132 ( .A(n5244), .B(n5447), .S0(n5314), .Y(n1798) ); MXI2X1TS U6133 ( .A(n5246), .B(n5519), .S0(n5159), .Y(n1043) ); INVX2TS U6134 ( .A(DmP_mant_SFG_SWR[7]), .Y(n5247) ); INVX2TS U6135 ( .A(DmP_mant_SFG_SWR[9]), .Y(n5250) ); CLKMX2X3TS U6136 ( .A(Data_Y[21]), .B(n2479), .S0(n5258), .Y(n1707) ); INVX2TS U6137 ( .A(DmP_mant_SFG_SWR[4]), .Y(n5267) ); INVX2TS U6138 ( .A(DmP_mant_SFG_SWR[5]), .Y(n5269) ); INVX2TS U6139 ( .A(DmP_mant_SFG_SWR[3]), .Y(n5272) ); NAND2X4TS U6140 ( .A(n2404), .B(n5279), .Y(n5280) ); CLKMX2X2TS U6141 ( .A(n5282), .B(Raw_mant_NRM_SWR[15]), .S0(n5319), .Y(n1183) ); MXI2X1TS U6142 ( .A(n2547), .B(n5284), .S0(n5314), .Y(n1799) ); XNOR2X1TS U6143 ( .A(n3329), .B(DMP_EXP_EWSW[52]), .Y(n5285) ); CLKMX2X2TS U6144 ( .A(n5285), .B(Shift_amount_SHT1_EWR[0]), .S0(n2547), .Y( n1604) ); NAND2X1TS U6145 ( .A(n3032), .B(n5297), .Y(n5295) ); XOR2X1TS U6146 ( .A(n5299), .B(n5295), .Y(n5296) ); INVX2TS U6147 ( .A(n5300), .Y(n5302) ); NAND2X1TS U6148 ( .A(n5302), .B(n5301), .Y(n5303) ); CLKMX2X2TS U6149 ( .A(n5304), .B(n2565), .S0(n2547), .Y(n1601) ); INVX2TS U6150 ( .A(n5305), .Y(n5307) ); NAND2X1TS U6151 ( .A(n5307), .B(n5306), .Y(n5308) ); NAND2X1TS U6152 ( .A(n2443), .B(n5310), .Y(n5312) ); XOR2X1TS U6153 ( .A(n5312), .B(n5311), .Y(n5313) ); CLKMX2X2TS U6154 ( .A(n5313), .B(Shift_amount_SHT1_EWR[1]), .S0(n2547), .Y( n1603) ); MXI2X1TS U6155 ( .A(n2525), .B(n2547), .S0(n5314), .Y(n1800) ); CLKMX2X2TS U6156 ( .A(n5320), .B(Raw_mant_NRM_SWR[16]), .S0(n5205), .Y(n1182) ); initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk1.tcl_LOA_syn.sdf"); endmodule
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HD__O32AI_TB_V `define SKY130_FD_SC_HD__O32AI_TB_V /** * o32ai: 3-input OR and 2-input OR into 2-input NAND. * * Y = !((A1 | A2 | A3) & (B1 | B2)) * * Autogenerated test bench. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none `include "sky130_fd_sc_hd__o32ai.v" module top(); // Inputs are registered reg A1; reg A2; reg A3; reg B1; reg B2; reg VPWR; reg VGND; reg VPB; reg VNB; // Outputs are wires wire Y; initial begin // Initial state is x for all inputs. A1 = 1'bX; A2 = 1'bX; A3 = 1'bX; B1 = 1'bX; B2 = 1'bX; VGND = 1'bX; VNB = 1'bX; VPB = 1'bX; VPWR = 1'bX; #20 A1 = 1'b0; #40 A2 = 1'b0; #60 A3 = 1'b0; #80 B1 = 1'b0; #100 B2 = 1'b0; #120 VGND = 1'b0; #140 VNB = 1'b0; #160 VPB = 1'b0; #180 VPWR = 1'b0; #200 A1 = 1'b1; #220 A2 = 1'b1; #240 A3 = 1'b1; #260 B1 = 1'b1; #280 B2 = 1'b1; #300 VGND = 1'b1; #320 VNB = 1'b1; #340 VPB = 1'b1; #360 VPWR = 1'b1; #380 A1 = 1'b0; #400 A2 = 1'b0; #420 A3 = 1'b0; #440 B1 = 1'b0; #460 B2 = 1'b0; #480 VGND = 1'b0; #500 VNB = 1'b0; #520 VPB = 1'b0; #540 VPWR = 1'b0; #560 VPWR = 1'b1; #580 VPB = 1'b1; #600 VNB = 1'b1; #620 VGND = 1'b1; #640 B2 = 1'b1; #660 B1 = 1'b1; #680 A3 = 1'b1; #700 A2 = 1'b1; #720 A1 = 1'b1; #740 VPWR = 1'bx; #760 VPB = 1'bx; #780 VNB = 1'bx; #800 VGND = 1'bx; #820 B2 = 1'bx; #840 B1 = 1'bx; #860 A3 = 1'bx; #880 A2 = 1'bx; #900 A1 = 1'bx; end sky130_fd_sc_hd__o32ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y)); endmodule `default_nettype wire `endif // SKY130_FD_SC_HD__O32AI_TB_V
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HDLL__AND4BB_PP_SYMBOL_V `define SKY130_FD_SC_HDLL__AND4BB_PP_SYMBOL_V /** * and4bb: 4-input AND, first two inputs inverted. * * Verilog stub (with power pins) for graphical symbol definition * generation. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_hdll__and4bb ( //# {{data|Data Signals}} input A_N , input B_N , input C , input D , output X , //# {{power|Power}} input VPB , input VPWR, input VGND, input VNB ); endmodule `default_nettype wire `endif // SKY130_FD_SC_HDLL__AND4BB_PP_SYMBOL_V
/* * Zet processor core * Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]> * * This file is part of the Zet processor. This processor is free * hardware; you can redistribute it and/or modify it under the terms of * the GNU General Public License as published by the Free Software * Foundation; either version 3, or (at your option) any later version. * * Zet is distrubuted in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public * License for more details. * * You should have received a copy of the GNU General Public License * along with Zet; see the file COPYING. If not, see * <http://www.gnu.org/licenses/>. */ `include "defines.v" module zet_core ( input clk, input rst, // interrupts input intr, output inta, input nmi, output nmia, // interface to wishbone output [19:0] cpu_adr_o, input [15:0] iid_dat_i, input [15:0] cpu_dat_i, output [15:0] cpu_dat_o, output cpu_byte_o, input cpu_block, output cpu_mem_op, output cpu_m_io, output cpu_we_o, output [19:0] pc // for debugging purposes ); // Net declarations wire [`IR_SIZE-1:0] ir; wire [15:0] off; wire [15:0] imm; wire wr_ip0; wire [15:0] cs; wire [15:0] ip; wire of; wire zf; wire ifl; wire iflm; wire tfl; wire tflm; wire iflss; wire wr_ss; wire cx_zero; wire div_exc; wire [19:0] addr_exec; wire byte_fetch; wire byte_exec; // wire decode - microcode wire [`MICRO_ADDR_WIDTH-1:0] seq_addr; wire [3:0] src; wire [3:0] dst; wire [3:0] base; wire [3:0] index; wire [1:0] seg; wire end_seq; wire [2:0] fdec; wire div; // wires fetch - decode wire [7:0] opcode; wire [7:0] modrm; wire rep; wire exec_st; wire ld_base; wire [2:0] sop_l; wire need_modrm; wire need_off; wire need_imm; wire off_size; wire imm_size; wire ext_int; // wires fetch - microcode wire [15:0] off_l; wire [15:0] imm_l; wire [15:0] imm_d; wire [`IR_SIZE-1:0] rom_ir; wire [5:0] ftype; // wires fetch - exec wire [15:0] imm_f; // wires and regs for hlt wire block_or_hlt; wire hlt_op; wire hlt_in; wire hlt_out; reg hlt_op_old; reg hlt; // regs for nmi reg nmir; reg nmi_old; reg nmia_old; // Module instantiations zet_fetch fetch ( .clk (clk), .rst (rst), // to decode .opcode (opcode), .modrm (modrm), .rep (rep), .exec_st (exec_st), .ld_base (ld_base), .sop_l (sop_l), // from decode .need_modrm (need_modrm), .need_off (need_off), .need_imm (need_imm), .off_size (off_size), .imm_size (imm_size), .ext_int (ext_int), .end_seq (end_seq), // to microcode .off_l (off_l), .imm_l (imm_l), // from microcode .ftype (ftype), // to exec .imm_f (imm_f), .wr_ip0 (wr_ip0), // from exec .cs (cs), .ip (ip), .of (of), .zf (zf), .iflm (iflm), .tflm (tflm), .iflss (iflss), .cx_zero (cx_zero), .div_exc (div_exc), // to wb .data (cpu_dat_i), .pc (pc), .bytefetch (byte_fetch), .block (block_or_hlt), .intr (intr), .nmir (nmir) ); zet_decode decode ( .clk (clk), .rst (rst), .opcode (opcode), .modrm (modrm), .rep (rep), .block (block_or_hlt), .exec_st (exec_st), .div_exc (div_exc), .ld_base (ld_base), .div (div), .tfl (tfl), .tflm (tflm), .need_modrm (need_modrm), .need_off (need_off), .need_imm (need_imm), .off_size (off_size), .imm_size (imm_size), .sop_l (sop_l), .intr (intr), .ifl (ifl), .iflm (iflm), .inta (inta), .ext_int (ext_int), .nmir (nmir), .nmia (nmia), .wr_ss (wr_ss), .iflss (iflss), .seq_addr (seq_addr), .src (src), .dst (dst), .base (base), .index (index), .seg (seg), .f (fdec), .end_seq (end_seq) ); zet_micro_data micro_data ( // from decode .n_micro (seq_addr), .off_i (off_l), .imm_i (imm_l), .src (src), .dst (dst), .base (base), .index (index), .seg (seg), .fdec (fdec), .div (div), .end_seq (end_seq), // to exec .ir (rom_ir), .off_o (off), .imm_o (imm_d) ); zet_exec exec ( .clk (clk), .rst (rst), // from fetch .ir (ir), .off (off), .imm (imm), .wrip0 (wr_ip0), // to fetch .cs (cs), .ip (ip), .of (of), .zf (zf), .ifl (ifl), .tfl (tfl), .cx_zero (cx_zero), .div_exc (div_exc), .wr_ss (wr_ss), // from wb .memout (iid_dat_i), .wr_data (cpu_dat_o), .addr (addr_exec), .we (cpu_we_o), .m_io (cpu_m_io), .byteop (byte_exec), .block (block_or_hlt) ); // Assignments assign cpu_adr_o = exec_st ? addr_exec : pc; assign cpu_byte_o = exec_st ? byte_exec : byte_fetch; assign cpu_mem_op = ir[`MEM_OP]; assign ir = exec_st ? rom_ir : `ADD_IP; assign imm = exec_st ? imm_d : imm_f; assign ftype = rom_ir[28:23]; assign hlt_op = ((opcode == `OP_HLT) && exec_st); assign hlt_in = (hlt_op && !hlt_op_old && !hlt_out); assign hlt_out = (intr & ifl) | nmir; assign block_or_hlt = cpu_block | hlt | hlt_in; // Behaviour always @(posedge clk) if (rst) hlt_op_old <= 1'b0; else if (hlt_op) hlt_op_old <= 1'b1; else hlt_op_old <= 1'b0; always @(posedge clk) if (rst) hlt <= 1'b0; else if (hlt_in) hlt <= 1'b1; else if (hlt_out) hlt <= 1'b0; always @(posedge clk) if (rst) begin nmir <= 1'b0; nmi_old <= 1'b0; nmia_old <= 1'b0; end else begin nmi_old <= nmi; nmia_old <= nmia; if (nmi & ~nmi_old) nmir <= 1'b1; else if (nmia_old) nmir <= 1'b0; end endmodule
// USED ONLY TO SELECT PL BLOCKED STATUS // OPTIMISE FOR XY ROUTING /* autovdoc@ * * component@ unary_select_pair * what@ A sort of mux! * authors@ Robert Mullins * date@ 5.3.04 * revised@ 5.3.04 * description@ * * Takes two unary (one-hot) encoded select signals and selects one bit of the input. * * Implements the following: * * {\tt selectedbit=datain[binary(sela)*WB+binary(selb)]} * * pin@ sel_a, WA, in, select signal A (unary encoded) * pin@ sel_b, WB, in, select signal B (unary encoded) * pin@ data_in, WA*WB, in, input data * pin@ selected_bit, 1, out, selected data bit (see above) * * param@ WA, >1, width of select signal A * param@ WB, >1, width of select signal B * * autovdoc@ */ module unary_select_pair (sel_a, sel_b, data_in, selected_bit); parameter input_port = 0; // from 'input_port' to 'sel_a' output port parameter WA = 4; parameter WB = 4; input [WA-1:0] sel_a; input [WB-1:0] sel_b; input [WA*WB-1:0] data_in; output selected_bit; genvar i,j; wire [WA*WB-1:0] selected; generate for (i=0; i<WA; i=i+1) begin:ol for (j=0; j<WB; j=j+1) begin:il assign selected[i*WB+j] = (LAG_route_valid_turn(input_port, i)) ? data_in[i*WB+j] & sel_a[i] & sel_b[j] : 1'b0; /* // i = output_port // assume XY routing and that data never leaves on port it entered if ((input_port==i) || (((input_port==`NORTH)||(input_port==`SOUTH)) && ((i==`EAST)||(i==`WEST)))) begin assign selected[i*WB+j]=1'b0; end else begin assign selected[i*WB+j]=data_in[i*WB+j] & sel_a[i] & sel_b[j]; end */ end end endgenerate assign selected_bit=|selected; endmodule // unary_select_pair
/* Copyright 2015, Google Inc. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. */ module sd_link ( input wire clk_50, input wire reset_n, output wire [3:0] link_card_state, input wire [47:0] phy_cmd_in, input wire phy_cmd_in_crc_good, input wire phy_cmd_in_act, output reg phy_data_in_act, input wire phy_data_in_busy, output reg phy_data_in_stop, output reg phy_data_in_another, input wire phy_data_in_done, input wire phy_data_in_crc_good, output reg [135:0] phy_resp_out, output reg [3:0] phy_resp_type, output reg phy_resp_busy, output reg phy_resp_act, input wire phy_resp_done, output reg phy_mode_4bit, output reg [511:0] phy_data_out_reg, output reg phy_data_out_src, output reg [9:0] phy_data_out_len, input wire phy_data_out_busy, output reg phy_data_out_act, output reg phy_data_out_stop, input wire phy_data_out_done, output reg block_read_act, input wire block_read_go, output reg [31:0] block_read_addr, output reg [31:0] block_read_num, output reg block_read_stop, output reg block_write_act, input wire block_write_done, output reg [31:0] block_write_addr, output reg [31:0] block_write_num, output reg [22:0] block_preerase_num, output reg [31:0] block_erase_start, output reg [31:0] block_erase_end, input wire opt_enable_hs, output reg [5:0] cmd_in_last, output reg info_card_desel, output reg err_host_is_spi, output reg err_op_out_range, output reg err_unhandled_cmd, output reg err_cmd_crc , output wire [5:0] cmd_in_cmd ); `include "sd_params.vh" `include "sd_const.vh" reg [47:0] cmd_in_latch; // wire [5:0] cmd_in_cmd = cmd_in_latch[45:40] /* synthesis noprune */; assign cmd_in_cmd = cmd_in_latch[45:40]; wire [31:0] cmd_in_arg = cmd_in_latch[39:8] /* synthesis noprune */; wire [6:0] cmd_in_crc = cmd_in_latch[7:1]; reg [3:0] card_state; assign link_card_state = card_state; reg [3:0] card_state_next; reg [3:0] card_acmd41_count; reg [2:0] card_erase_state; reg card_appcmd; reg [31:0] card_status; reg [127:0] card_sd_status; reg [127:0] card_csd; reg [127:0] card_cid; reg [31:0] card_ocr; reg [15:0] card_rca; reg [63:0] card_scr; reg [111:0] card_function_caps; reg [23:0] card_function; reg [23:0] card_function_check; reg [31:0] card_blocks_written; reg [127:0] resp_arg; // for 32 or 128bit reg [3:0] resp_type; reg [15:0] dc; reg [15:0] ddc; reg [6:0] state; parameter [6:0] ST_RESET = 'd0, ST_IDLE = 'd4, ST_CMD_ACT = 'd8, ST_CMD_RESP_0 = 'd9, ST_CMD_RESP_1 = 'd10, ST_CMD_RESP_2 = 'd11, ST_LAST = 'd127; reg [6:0] data_state; parameter [6:0] DST_RESET = 'd0, DST_IDLE = 'd1, DST_IDLE_1 = 'd2, DST_DATA_OUT_0 = 'd10, DST_DATA_OUT_1 = 'd11, DST_DATA_OUT_2 = 'd12, DST_DATA_OUT_3 = 'd13, DST_DATA_OUT_4 = 'd14, DST_DATA_OUT_5 = 'd15, DST_DATA_IN_0 = 'd20, DST_DATA_IN_1 = 'd21, DST_DATA_IN_2 = 'd22, DST_DATA_IN_3 = 'd23, DST_DATA_IN_4 = 'd24, DST_DATA_IN_5 = 'd25, DST_LAST = 'd127; reg data_op_send_scr; reg data_op_send_sdstatus; reg data_op_send_function; reg data_op_send_written; reg data_op_send_block; reg data_op_send_block_queue; reg data_op_recv_block; // synchronizers wire reset_s; wire [47:0] cmd_in_s; wire cmd_in_crc_good_s; wire cmd_in_act_s, cmd_in_act_r; wire data_in_busy_s; wire data_in_done_s, data_in_done_r; wire data_in_crc_good_s; wire resp_done_s, resp_done_r; wire data_out_busy_s; wire data_out_done_s, data_out_done_r; synch_3 a(reset_n, reset_s, clk_50); synch_3 #(48) b(phy_cmd_in, cmd_in_s, clk_50); synch_3 c(phy_cmd_in_crc_good, cmd_in_crc_good_s, clk_50); synch_3 d(phy_cmd_in_act, cmd_in_act_s, clk_50, cmd_in_act_r); synch_3 e(phy_data_in_busy, data_in_busy_s, clk_50); synch_3 f(phy_data_in_done, data_in_done_s, clk_50, data_in_done_r); synch_3 g(phy_data_in_crc_good, data_in_crc_good_s, clk_50); synch_3 h(phy_resp_done, resp_done_s, clk_50, resp_done_r); synch_3 i(phy_data_out_busy, data_out_busy_s, clk_50); synch_3 j(phy_data_out_done, data_out_done_s, clk_50, data_out_done_r); always @(posedge clk_50) begin // free running counter dc <= dc + 1'b1; case(state) ST_RESET: begin dc <= 0; info_card_desel <= 0; err_host_is_spi <= 0; err_op_out_range <= 0; err_unhandled_cmd <= 0; err_cmd_crc <= 0; card_erase_state <= 0; card_acmd41_count <= 0; card_blocks_written <= 0; card_appcmd <= 0; card_rca <= 16'h0; card_status <= 0; card_status[STAT_READY_FOR_DATA] <= 1'b1; card_state <= CARD_IDLE; card_ocr <= {8'b01000000, OCR_VOLTAGE_WINDOW}; // high capacity, not powered up card_cid <= {CID_FIELD_MID, CID_FIELD_OID, CID_FIELD_PNM, CID_FIELD_PRV, CID_FIELD_PSN, 4'b0, CID_FIELD_MDT, 8'hFF}; card_csd <= {CSD_CSD_STRUCTURE, 6'h0, CSD_TAAC, CSD_NSAC, CSD_TRAN_SPEED_25, CSD_CCC, CSD_READ_BL_LEN, CSD_READ_BL_PARTIAL, CSD_WRITE_BLK_MISALIGN, CSD_READ_BLK_MISALIGN, CSD_DSR_IMPL, 6'h0, CSD_C_SIZE, 1'b0, CSD_ERASE_BLK_EN, CSD_SECTOR_SIZE, CSD_WP_GRP_SIZE, CSD_WP_GRP_ENABLE, 2'b00, CSD_R2W_FACTOR, CSD_WRITE_BL_LEN, CSD_WRITE_BL_PARTIAL, 5'h0, CSD_FILE_FORMAT_GRP, CSD_COPY, CSD_PERM_WRITE_PROTECT, CSD_TMP_WRITE_PROTECT, CSD_FILE_FORMAT, 2'h0, 8'hFF}; card_scr <= {SCR_SCR_STRUCTURE, SCR_SD_SPEC, SCR_DATA_STATE_ERASE, SCR_SD_SECURITY, SCR_SD_BUS_WIDTHS, SCR_SD_SPEC3, 13'h0, 2'h0, 32'h0}; card_sd_status <= { STAT_DAT_BUS_WIDTH_1, STAT_SECURED_MODE, 7'h0, 6'h0, STAT_SD_CARD_TYPE, STAT_SIZE_OF_PROT_AREA, STAT_SPEED_CLASS, STAT_PERFORMANCE_MOVE, STAT_AU_SIZE, 4'h0, STAT_ERASE_SIZE, STAT_ERASE_TIMEOUT, STAT_ERASE_OFFSET, 15'h0}; // set high speed capability bit card_function_caps <= 112'h0032800180018001800180018001 | opt_enable_hs ? 2'b10 : 2'b00; card_function <= 24'h0; card_function_check <= 24'h0; data_op_send_scr <= 0; data_op_send_sdstatus <= 0; data_op_send_function <= 0; data_op_send_written <= 0; data_op_send_block <= 0; data_op_send_block_queue <= 0; data_op_recv_block <= 0; phy_data_in_act <= 0; phy_data_in_stop <= 0; phy_resp_act <= 0; phy_data_out_act <= 0; phy_data_out_stop <= 0; phy_mode_4bit <= 0; block_read_act <= 0; block_read_num <= 0; block_read_stop <= 0; block_write_act <= 0; block_write_num <= 0; block_preerase_num <= 0; state <= ST_IDLE; end ST_IDLE: begin // rising edge + crc is good if(cmd_in_act_r) begin phy_resp_act <= 0; if(cmd_in_crc_good_s) begin // new command cmd_in_latch <= phy_cmd_in; //cmd_in_s; card_status[STAT_COM_CRC_ERROR] <= 0; card_status[STAT_ILLEGAL_COMMAND] <= 0; state <= ST_CMD_ACT; cmd_in_last <= cmd_in_cmd; end else begin // bad crc err_cmd_crc <= 1; card_status[STAT_COM_CRC_ERROR] <= 1; end end end ST_CMD_ACT: begin // parse the command state <= ST_CMD_RESP_0; // unless otherwise, stay in the same SD state card_state_next <= card_state; // unless set below, assume it's illegal resp_type <= RESP_BAD; if(~card_appcmd) begin // CMD case(cmd_in_cmd) CMD0_GO_IDLE: begin if(card_state != CARD_INA) begin // reset everything to default resp_type <= RESP_NONE; state <= ST_RESET; data_state <= DST_RESET; end end CMD2_ALL_SEND_CID: case(card_state) CARD_READY: begin resp_type <= RESP_R2; card_state_next <= CARD_IDENT; end endcase CMD3_SEND_REL_ADDR : case(card_state) CARD_IDENT, CARD_STBY: begin card_rca <= card_rca + 16'h1337; resp_type <= RESP_R6; card_state_next <= CARD_STBY; end endcase //CMD4_SET_DSR: begin //end CMD6_SWITCH_FUNC: begin case(card_state) CARD_TRAN: begin case(cmd_in_arg[23:20]) 4'h0, 4'hF: card_function_check[23:20] <= 4'h0; // valid default: card_function_check[23:20] <= 4'hF; // invalid endcase case(cmd_in_arg[19:16]) 4'h0, 4'hF: card_function_check[19:16] <= 4'h0; // valid default: card_function_check[19:16] <= 4'hF; // invalid endcase case(cmd_in_arg[15:12]) 4'h0, 4'hF: card_function_check[15:12] <= 4'h0; // valid default: card_function_check[15:12] <= 4'hF; // invalid endcase case(cmd_in_arg[11:8]) 4'h0, 4'hF: card_function_check[11:8] <= 4'h0; // valid default: card_function_check[11:8] <= 4'hF; // invalid endcase case(cmd_in_arg[7:4]) 4'h0, 4'hF: card_function_check[7:4] <= 4'h0; // valid default: card_function_check[7:4] <= 4'hF; // invalid endcase case(cmd_in_arg[3:0]) 4'h0: card_function_check[3:0] <= 4'h0; 4'hF: card_function_check[3:0] <= card_function[3:0]; 4'h1: begin card_function_check[3:0] <= 4'h1; // high speed enable if(cmd_in_arg[31]) card_function[3:0] <= 4'h1; end default: card_function_check[3:0] <= 4'hF; // invalid endcase resp_type <= RESP_R1; card_state_next <= CARD_DATA; data_op_send_function <= 1; end endcase end CMD7_SEL_CARD: begin if(cmd_in_arg[31:16] == card_rca) begin // select resp_type <= RESP_R1B; case(card_state) CARD_STBY: card_state_next <= CARD_TRAN; //CARD_DIS: card_state_next <= CARD_PRG; CARD_DIS: card_state_next <= CARD_TRAN; default: resp_type <= RESP_BAD; endcase end else begin // deselected case(card_state) CARD_STBY: card_state_next <= CARD_STBY; CARD_TRAN: card_state_next <= CARD_STBY; CARD_DATA: card_state_next <= CARD_STBY; CARD_PRG: card_state_next <= CARD_DIS; //default: resp_type <= RESP_BAD; endcase info_card_desel <= 1; resp_type <= RESP_NONE; end end CMD8_SEND_IF_COND: case(card_state) CARD_IDLE: begin if(cmd_in_arg[11:8] == 4'b0001) begin resp_type <= RESP_R7; resp_arg <= {20'h0, 4'b0001, cmd_in_arg[7:0]}; end else resp_type <= RESP_NONE; end endcase CMD9_SEND_CSD: begin if(cmd_in_arg[31:16] == card_rca) begin case(card_state) CARD_STBY: begin resp_type <= RESP_R2; end endcase end else resp_type <= RESP_NONE; end CMD10_SEND_CID: begin if(cmd_in_arg[31:16] == card_rca) begin case(card_state) CARD_STBY: begin resp_type <= RESP_R2; end endcase end else resp_type <= RESP_NONE; end CMD12_STOP: case(card_state) // N.B. should not be allowed in PRG state, but readers do anyway CARD_DATA, CARD_RCV, CARD_PRG: begin resp_type <= RESP_R1B; if(card_state == CARD_DATA) card_state_next <= CARD_TRAN; // PRG > TRAN transition is handled by the data states below if(card_state == CARD_RCV) card_state_next <= CARD_TRAN; if(card_state == CARD_PRG) card_state_next <= CARD_TRAN; phy_data_in_stop <= 1; phy_data_out_stop <= 1; end endcase CMD13_SEND_STATUS: begin if(cmd_in_arg[31:16] == card_rca) begin case(card_state) CARD_STBY, CARD_TRAN, CARD_DATA, CARD_RCV, CARD_PRG, CARD_DIS: begin resp_type <= RESP_R1; end endcase end else resp_type <= RESP_NONE; end CMD15_GO_INACTIVE: begin if(cmd_in_arg[31:16] == card_rca) begin case(card_state) CARD_STBY, CARD_TRAN, CARD_DATA, CARD_RCV, CARD_PRG, CARD_DIS: begin card_state_next <= CARD_INA; resp_type <= RESP_NONE; end endcase end else resp_type <= RESP_NONE; end CMD16_SET_BLOCKLEN: case(card_state) CARD_TRAN: begin resp_type <= RESP_R1; if(cmd_in_arg > 512) card_status[STAT_BLOCK_LEN_ERROR] <= 1; end endcase CMD17_READ_SINGLE: case(card_state) CARD_TRAN: begin if(cmd_in_arg >= SD_TOTAL_BLOCKS) begin card_status[STAT_OUT_OF_RANGE] <= 1'b1; err_op_out_range <= 1; end else begin resp_type <= RESP_R1; block_read_addr <= cmd_in_arg; block_read_num <= 1; data_op_send_block_queue <= 1; card_state_next <= CARD_DATA; end end endcase CMD18_READ_MULTIPLE: case(card_state) CARD_TRAN: begin if(cmd_in_arg >= SD_TOTAL_BLOCKS) begin card_status[STAT_OUT_OF_RANGE] <= 1'b1; err_op_out_range <= 1; end else begin resp_type <= RESP_R1; block_read_addr <= cmd_in_arg; block_read_num <= 32'hFFFFFFFF; data_op_send_block_queue <= 1; card_state_next <= CARD_DATA; end end endcase CMD24_WRITE_SINGLE: case(card_state) CARD_TRAN: begin if(cmd_in_arg >= SD_TOTAL_BLOCKS) begin card_status[STAT_OUT_OF_RANGE] <= 1'b1; err_op_out_range <= 1; end else begin resp_type <= RESP_R1; block_write_addr <= cmd_in_arg; block_write_num <= 1; card_blocks_written <= 0; data_op_recv_block <= 1; card_state_next <= CARD_RCV; end end endcase CMD25_WRITE_MULTIPLE: case(card_state) CARD_TRAN: begin if(cmd_in_arg >= SD_TOTAL_BLOCKS) begin card_status[STAT_OUT_OF_RANGE] <= 1'b1; err_op_out_range <= 1; end else begin resp_type <= RESP_R1; block_write_addr <= cmd_in_arg; block_write_num <= 32'hFFFFFFFF; card_blocks_written <= 0; data_op_recv_block <= 1; card_state_next <= CARD_RCV; end end endcase //CMD27_PROGRAM_CSD: begin //end CMD32_ERASE_START: case(card_state) CARD_TRAN: begin resp_type <= RESP_R1; card_erase_state <= 0; if(card_erase_state == 0) begin block_erase_start <= cmd_in_arg; card_erase_state <= 1; end else card_status[STAT_ERASE_SEQ_ERROR] <= 1'b1; end endcase CMD33_ERASE_END: case(card_state) CARD_TRAN: begin resp_type <= RESP_R1; card_erase_state <= 0; if(card_erase_state == 1) begin block_erase_end <= cmd_in_arg; card_erase_state <= 2; end else card_status[STAT_ERASE_SEQ_ERROR] <= 1'b1; end endcase CMD38_ERASE: case(card_state) CARD_TRAN: begin resp_type <= RESP_R1B; card_erase_state <= 0; if(card_erase_state == 2) begin // process erase end else card_status[STAT_ERASE_SEQ_ERROR] <= 1'b1; // since erase are unimpl they happen immediately //card_state_next <= CARD_PRG; end endcase //CMD42_LOCK_UNLOCK: begin //end CMD55_APP_CMD: begin if(cmd_in_arg[31:16] == card_rca) begin case(card_state) CARD_IDLE, CARD_STBY, CARD_TRAN, CARD_DATA, CARD_RCV, CARD_PRG, CARD_DIS: begin resp_type <= RESP_R1; card_appcmd <= 1; card_status[STAT_APP_CMD] <= 1; end endcase end else resp_type <= RESP_NONE; end //CMD56_GEN_CMD: begin //end default: begin err_unhandled_cmd <= 1; if(cmd_in_cmd == 6'd1) err_unhandled_cmd <= 0; // CMD1 for SPI cards if(cmd_in_cmd == 6'd5) err_unhandled_cmd <= 0; // CMD5 for SDIO combo cards end endcase // CMD1 is only used in SPI mode, which is not supported if(cmd_in_cmd == 6'h1) err_host_is_spi <= 1; // check for illegal commands during an expected erase sequence if(card_erase_state > 0) begin if( cmd_in_cmd != CMD13_SEND_STATUS && cmd_in_cmd != CMD33_ERASE_END && cmd_in_cmd != CMD38_ERASE) begin card_erase_state <= 0; card_status[STAT_ERASE_RESET] <= 1; end end end else begin // ACMD case(cmd_in_cmd) ACMD6_SET_BUS_WIDTH: case(card_state) CARD_TRAN: begin resp_type <= RESP_R1; phy_mode_4bit <= cmd_in_arg[1]; end endcase ACMD13_SD_STATUS: case(card_state) CARD_TRAN: begin resp_type <= RESP_R1; // send SD status data_op_send_sdstatus <= 1; card_state_next <= CARD_DATA; end endcase ACMD22_NUM_WR_BLK: case(card_state) CARD_TRAN: begin resp_type <= RESP_R1; // send number blocks written data_op_send_written <= 1; card_state_next <= CARD_DATA; end endcase ACMD23_SET_WR_BLK: case(card_state) CARD_TRAN: begin resp_type <= RESP_R1; block_preerase_num[22:0] <= cmd_in_arg[22:0]; end endcase ACMD41_SEND_OP_COND: case(card_state) CARD_IDLE: begin resp_type <= RESP_R3; card_acmd41_count <= card_acmd41_count + 1'b1; if(cmd_in_arg[23:0] == 24'h0) begin // ocr is zero, this is a query. end else if(cmd_in_arg[30]) begin // is host SDHC compatible? otherwise we'll never be ready if(card_acmd41_count > 2) begin card_ocr[OCR_POWERED_UP] <= 1; card_state_next <= CARD_READY; end end end endcase ACMD42_SET_CARD_DET: case(card_state) // card detect pullup is unsupported CARD_TRAN: resp_type <= RESP_R1; endcase ACMD51_SEND_SCR: case(card_state) CARD_TRAN: begin resp_type <= RESP_R1; // send SCR data_op_send_scr <= 1; card_state_next <= CARD_DATA; end endcase default: begin // retry this as a regular CMD (retry this state with APPCMD=0) state <= ST_CMD_ACT; card_appcmd <= 0; //err_unhandled_cmd <= 1; end endcase end end ST_CMD_RESP_0: begin // update status register and such card_status[12:9] <= card_state; state <= ST_CMD_RESP_1; end ST_CMD_RESP_1: begin // send response state <= ST_CMD_RESP_2; phy_resp_type <= resp_type; phy_resp_busy <= 0; case(resp_type) RESP_NONE: begin // don't send a response card_state <= card_state_next; state <= ST_IDLE; end RESP_BAD: begin // illegal card_status[STAT_ILLEGAL_COMMAND] <= 1; state <= ST_IDLE; end RESP_R1, RESP_R1B: begin phy_resp_out <= {2'b00, cmd_in_cmd, card_status, 8'h1, 88'h0}; end RESP_R2: begin phy_resp_out <= {2'b00, 6'b111111, cmd_in_cmd == CMD9_SEND_CSD ? card_csd[127:1] : card_cid[127:1], 1'b1}; end RESP_R3: begin phy_resp_out <= {2'b00, 6'b111111, card_ocr, 8'hFF, 88'h0}; end RESP_R6: begin phy_resp_out <= {2'b00, 6'b000011, card_rca, {card_status[23:22], card_status[19], card_status[12:0]}, 8'h1, 88'h0}; end RESP_R7: begin phy_resp_out <= {2'b00, 6'b001000, resp_arg[31:0], 8'h1, 88'h0}; end endcase end ST_CMD_RESP_2: begin phy_resp_act <= 1; if(resp_done_r) begin // rising edge, phy is done sending response phy_resp_act <= 0; // clear APP_CMD after ACMD response sent if(card_appcmd && (cmd_in_cmd != CMD55_APP_CMD)) begin card_appcmd <= 0; card_status[STAT_APP_CMD] <= 0; // not spec? but cards do it end case(cmd_in_cmd) CMD13_SEND_STATUS: begin // clear all bits that are Clear-On-Read card_status[STAT_OUT_OF_RANGE] <= 0; card_status[STAT_ADDRESS_ERROR] <= 0; card_status[STAT_BLOCK_LEN_ERROR] <= 0; card_status[STAT_ERASE_SEQ_ERROR] <= 0; card_status[STAT_ERASE_PARAM] <= 0; card_status[STAT_WP_VIOLATION] <= 0; card_status[STAT_LOCK_UNLOCK_FAILED] <= 0; card_status[STAT_CARD_ECC_FAILED] <= 0; card_status[STAT_CC_ERROR] <= 0; card_status[STAT_CSD_OVERWRITE] <= 0; card_status[STAT_WP_ERASE_SKIP] <= 0; card_status[STAT_ERASE_RESET] <= 0; card_status[STAT_APP_CMD] <= 0; card_status[STAT_AKE_SEQ_ERROR] <= 0; end endcase card_state <= card_state_next; state <= ST_IDLE; end end endcase // data FSM // must be separate so that data packets can be transferred // and commands still sent/responsed // // free running counter ddc <= ddc + 1'b1; case(data_state) DST_RESET: begin phy_data_out_act <= 0; data_state <= DST_IDLE; end DST_IDLE: begin card_status[STAT_READY_FOR_DATA] <= 1'b1; if(data_op_recv_block) begin // for data receive ops data_state <= DST_DATA_IN_0; end else if( data_op_send_scr | data_op_send_sdstatus | data_op_send_function | data_op_send_written | data_op_send_block_queue ) begin // move to next state once response is processing // to prevent false starts if(~resp_done_s) begin data_state <= DST_IDLE_1; // queue block read, so that it can be accepted after a much-delayed read cycle if(data_op_send_block_queue) begin //card_state <= CARD_DATA; data_op_send_block_queue <= 0; data_op_send_block <= 1; end end end end DST_IDLE_1: begin ddc <= 0; // process these data ops while response starts to send if( data_op_send_scr | data_op_send_sdstatus | data_op_send_function | data_op_send_written | data_op_send_block ) begin phy_data_out_src <= 1; // default: send from register data_state <= DST_DATA_OUT_0; if(data_op_send_scr) begin data_op_send_scr <= 0; phy_data_out_len <= 8; phy_data_out_reg <= {card_scr, 448'h0}; end else if(data_op_send_sdstatus) begin data_op_send_sdstatus <= 0; phy_data_out_len <= 64; phy_data_out_reg <= {card_sd_status, 384'h0}; end else if(data_op_send_function) begin data_op_send_function <= 0; phy_data_out_len <= 64; phy_data_out_reg <= {card_function_caps, card_function_check, 376'h0}; end else if(data_op_send_written) begin data_op_send_written <= 0; phy_data_out_len <= 4; phy_data_out_reg <= {card_blocks_written, 480'h0}; end else if(data_op_send_block) begin phy_data_out_src <= 0; // send data from bram phy_data_out_len <= 512; data_state <= DST_DATA_OUT_5; end end end DST_DATA_OUT_5: begin // make sure MGR cleared from any previous ops if(~block_read_go) begin block_read_stop <= 0; data_state <= DST_DATA_OUT_3; end end DST_DATA_OUT_3: begin // external bram op: // wait for bram contents to be valid block_read_act <= 1; if(block_read_go) begin // ready block_read_act <= 0; data_state <= DST_DATA_OUT_0; end end DST_DATA_OUT_0: begin // wait to send data until response was sent if(resp_done_s) begin phy_data_out_act <= 1; data_state <= DST_DATA_OUT_1; end end DST_DATA_OUT_1: begin if(data_out_done_r) begin // rising edge, phy is done sending data phy_data_out_act <= 0; // did link detect a stop command? if(phy_data_out_stop) begin phy_data_in_stop <= 0; phy_data_out_stop <= 0; data_op_send_block <= 0; end // tell upper level we're done block_read_stop <= 1; data_state <= DST_DATA_OUT_4; end end DST_DATA_OUT_4: begin // wait for SD_MGR to finish if(~block_read_go) data_state <= DST_DATA_OUT_2; // link detected stop while we're waiting if(phy_data_out_stop) begin phy_data_in_stop <= 0; phy_data_out_stop <= 0; data_op_send_block <= 0; block_read_stop <= 1; data_state <= DST_DATA_OUT_2; end end DST_DATA_OUT_2: begin // wait until phy de-asserts busy so that it can detect another rising edge // due to clocking differences if(~data_out_busy_s) begin //block_read_stop <= 0; // fall back to TRAN state card_state <= CARD_TRAN; data_state <= DST_IDLE; // don't wait around for a response to be sent if more blocks are to be done if(data_op_send_block) begin if(block_read_num == 1) begin data_op_send_block <= 0; end else begin // stay in current state // advance block count card_state <= card_state; block_read_addr <= block_read_addr + 1'b1; block_read_num <= block_read_num - 1'b1; if(block_read_addr >= SD_TOTAL_BLOCKS) begin card_status[STAT_OUT_OF_RANGE] <= 1'b1; err_op_out_range <= 1; end data_state <= DST_IDLE_1; end end end end DST_DATA_IN_0: begin // signal to PHY that we are expecting a data packet phy_data_in_act <= 1; if(data_in_done_r) begin card_status[STAT_READY_FOR_DATA] <= 1'b0; data_state <= DST_DATA_IN_1; end if(phy_data_in_stop) begin phy_data_in_act <= 0; card_state <= CARD_TRAN; data_state <= DST_DATA_IN_2; end end DST_DATA_IN_1: begin if(~data_in_crc_good_s) begin // bad CRC, don't commit // expect host to re-send entire CMD24/25 sequence phy_data_in_act <= 0; data_op_recv_block <= 0; card_state <= CARD_TRAN; data_state <= DST_IDLE; end else begin // tell mgr/ext there is data to be written block_write_act <= 1; card_state <= CARD_PRG; // mgr/ext has finished if(block_write_done) begin // tell PHY to let go of the busy signal on DAT0 card_state <= CARD_RCV; phy_data_in_act <= 0; block_write_act <= 0; data_state <= DST_DATA_IN_2; end end end DST_DATA_IN_2: begin // wait until PHY is able to detect new ACT // or if it's a burst write, just go ahead anyway if(~data_in_busy_s | (phy_data_in_another & ~phy_data_in_stop)) begin data_state <= DST_DATA_IN_3; end phy_data_in_another <= block_write_num > 1; //phy_data_in_stop <= 1; end DST_DATA_IN_3: begin card_blocks_written <= card_blocks_written + 1'b1; if(block_write_num == 1 || phy_data_in_stop) begin // last block, or it was CMD12'd card_state <= CARD_TRAN; phy_data_in_stop <= 0; phy_data_out_stop <= 0; phy_data_in_another <= 0; data_op_recv_block <= 0; data_state <= DST_IDLE; end else begin // more blocks to go card_state <= CARD_RCV; card_status[STAT_READY_FOR_DATA] <= 1'b1; block_write_addr <= block_write_addr + 1'b1; block_write_num <= block_write_num - 1'b1; if(block_write_addr >= SD_TOTAL_BLOCKS) begin card_status[STAT_OUT_OF_RANGE] <= 1'b1; err_op_out_range <= 1; end data_state <= DST_DATA_IN_0; end end endcase if(~reset_s) begin state <= ST_RESET; data_state <= DST_RESET; end end endmodule
//----------------------------------------------------------------------------- // // (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //----------------------------------------------------------------------------- // Project : Series-7 Integrated Block for PCI Express // File : pcie_7x_0_core_top_gtp_cpllpd_ovrd.v // Version : 3.0 `timescale 1ns / 1ps module pcie_7x_0_core_top_gtp_cpllpd_ovrd ( input i_ibufds_gte2, output o_cpllpd_ovrd, output o_cpllreset_ovrd ); (* equivalent_register_removal="no" *) reg [95:0] cpllpd_wait = 96'hFFFFFFFFFFFFFFFFFFFFFFFF; (* equivalent_register_removal="no" *) reg [127:0] cpllreset_wait = 128'h000000000000000000000000000000FF; always @(posedge i_ibufds_gte2) begin cpllpd_wait <= {cpllpd_wait[94:0], 1'b0}; cpllreset_wait <= {cpllreset_wait[126:0], 1'b0}; end assign o_cpllpd_ovrd = cpllpd_wait[95]; assign o_cpllreset_ovrd = cpllreset_wait[127]; endmodule
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HD__DLRBP_TB_V `define SKY130_FD_SC_HD__DLRBP_TB_V /** * dlrbp: Delay latch, inverted reset, non-inverted enable, * complementary outputs. * * Autogenerated test bench. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none `include "sky130_fd_sc_hd__dlrbp.v" module top(); // Inputs are registered reg RESET_B; reg D; reg VPWR; reg VGND; reg VPB; reg VNB; // Outputs are wires wire Q; wire Q_N; initial begin // Initial state is x for all inputs. D = 1'bX; RESET_B = 1'bX; VGND = 1'bX; VNB = 1'bX; VPB = 1'bX; VPWR = 1'bX; #20 D = 1'b0; #40 RESET_B = 1'b0; #60 VGND = 1'b0; #80 VNB = 1'b0; #100 VPB = 1'b0; #120 VPWR = 1'b0; #140 D = 1'b1; #160 RESET_B = 1'b1; #180 VGND = 1'b1; #200 VNB = 1'b1; #220 VPB = 1'b1; #240 VPWR = 1'b1; #260 D = 1'b0; #280 RESET_B = 1'b0; #300 VGND = 1'b0; #320 VNB = 1'b0; #340 VPB = 1'b0; #360 VPWR = 1'b0; #380 VPWR = 1'b1; #400 VPB = 1'b1; #420 VNB = 1'b1; #440 VGND = 1'b1; #460 RESET_B = 1'b1; #480 D = 1'b1; #500 VPWR = 1'bx; #520 VPB = 1'bx; #540 VNB = 1'bx; #560 VGND = 1'bx; #580 RESET_B = 1'bx; #600 D = 1'bx; end // Create a clock reg GATE; initial begin GATE = 1'b0; end always begin #5 GATE = ~GATE; end sky130_fd_sc_hd__dlrbp dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE(GATE)); endmodule `default_nettype wire `endif // SKY130_FD_SC_HD__DLRBP_TB_V
/* Copyright (c) 2014-2018 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ // Language: Verilog 2001 `timescale 1ns / 1ps /* * FPGA top-level module */ module fpga ( /* * Clock: 125MHz LVDS * Reset: Push button, active low */ input wire clk_125mhz_p, input wire clk_125mhz_n, input wire reset, /* * GPIO */ input wire btnu, input wire btnl, input wire btnd, input wire btnr, input wire btnc, input wire [3:0] sw, output wire [7:0] led, /* * I2C for board management */ inout wire i2c_scl, inout wire i2c_sda, /* * Ethernet: QSFP28 */ input wire qsfp_rx1_p, input wire qsfp_rx1_n, input wire qsfp_rx2_p, input wire qsfp_rx2_n, input wire qsfp_rx3_p, input wire qsfp_rx3_n, input wire qsfp_rx4_p, input wire qsfp_rx4_n, output wire qsfp_tx1_p, output wire qsfp_tx1_n, output wire qsfp_tx2_p, output wire qsfp_tx2_n, output wire qsfp_tx3_p, output wire qsfp_tx3_n, output wire qsfp_tx4_p, output wire qsfp_tx4_n, input wire qsfp_mgt_refclk_0_p, input wire qsfp_mgt_refclk_0_n, // input wire qsfp_mgt_refclk_1_p, // input wire qsfp_mgt_refclk_1_n, // output wire qsfp_recclk_p, // output wire qsfp_recclk_n, output wire qsfp_modsell, output wire qsfp_resetl, input wire qsfp_modprsl, input wire qsfp_intl, output wire qsfp_lpmode, /* * Ethernet: 1000BASE-T SGMII */ input wire phy_sgmii_rx_p, input wire phy_sgmii_rx_n, output wire phy_sgmii_tx_p, output wire phy_sgmii_tx_n, input wire phy_sgmii_clk_p, input wire phy_sgmii_clk_n, output wire phy_reset_n, input wire phy_int_n, /* * UART: 500000 bps, 8N1 */ input wire uart_rxd, output wire uart_txd, output wire uart_rts, input wire uart_cts ); // Clock and reset wire clk_125mhz_ibufg; // Internal 125 MHz clock wire clk_125mhz_mmcm_out; wire clk_125mhz_int; wire rst_125mhz_int; // Internal 156.25 MHz clock wire clk_156mhz_int; wire rst_156mhz_int; wire mmcm_rst = reset; wire mmcm_locked; wire mmcm_clkfb; IBUFGDS #( .DIFF_TERM("FALSE"), .IBUF_LOW_PWR("FALSE") ) clk_125mhz_ibufg_inst ( .O (clk_125mhz_ibufg), .I (clk_125mhz_p), .IB (clk_125mhz_n) ); // MMCM instance // 125 MHz in, 125 MHz out // PFD range: 10 MHz to 500 MHz // VCO range: 600 MHz to 1440 MHz // M = 5, D = 1 sets Fvco = 625 MHz (in range) // Divide by 5 to get output frequency of 125 MHz MMCME3_BASE #( .BANDWIDTH("OPTIMIZED"), .CLKOUT0_DIVIDE_F(5), .CLKOUT0_DUTY_CYCLE(0.5), .CLKOUT0_PHASE(0), .CLKOUT1_DIVIDE(1), .CLKOUT1_DUTY_CYCLE(0.5), .CLKOUT1_PHASE(0), .CLKOUT2_DIVIDE(1), .CLKOUT2_DUTY_CYCLE(0.5), .CLKOUT2_PHASE(0), .CLKOUT3_DIVIDE(1), .CLKOUT3_DUTY_CYCLE(0.5), .CLKOUT3_PHASE(0), .CLKOUT4_DIVIDE(1), .CLKOUT4_DUTY_CYCLE(0.5), .CLKOUT4_PHASE(0), .CLKOUT5_DIVIDE(1), .CLKOUT5_DUTY_CYCLE(0.5), .CLKOUT5_PHASE(0), .CLKOUT6_DIVIDE(1), .CLKOUT6_DUTY_CYCLE(0.5), .CLKOUT6_PHASE(0), .CLKFBOUT_MULT_F(5), .CLKFBOUT_PHASE(0), .DIVCLK_DIVIDE(1), .REF_JITTER1(0.010), .CLKIN1_PERIOD(8.0), .STARTUP_WAIT("FALSE"), .CLKOUT4_CASCADE("FALSE") ) clk_mmcm_inst ( .CLKIN1(clk_125mhz_ibufg), .CLKFBIN(mmcm_clkfb), .RST(mmcm_rst), .PWRDWN(1'b0), .CLKOUT0(clk_125mhz_mmcm_out), .CLKOUT0B(), .CLKOUT1(), .CLKOUT1B(), .CLKOUT2(), .CLKOUT2B(), .CLKOUT3(), .CLKOUT3B(), .CLKOUT4(), .CLKOUT5(), .CLKOUT6(), .CLKFBOUT(mmcm_clkfb), .CLKFBOUTB(), .LOCKED(mmcm_locked) ); BUFG clk_125mhz_bufg_inst ( .I(clk_125mhz_mmcm_out), .O(clk_125mhz_int) ); sync_reset #( .N(4) ) sync_reset_125mhz_inst ( .clk(clk_125mhz_int), .rst(~mmcm_locked), .out(rst_125mhz_int) ); // GPIO wire btnu_int; wire btnl_int; wire btnd_int; wire btnr_int; wire btnc_int; wire [3:0] sw_int; debounce_switch #( .WIDTH(9), .N(4), .RATE(156000) ) debounce_switch_inst ( .clk(clk_156mhz_int), .rst(rst_156mhz_int), .in({btnu, btnl, btnd, btnr, btnc, sw}), .out({btnu_int, btnl_int, btnd_int, btnr_int, btnc_int, sw_int}) ); wire uart_rxd_int; wire uart_cts_int; sync_signal #( .WIDTH(2), .N(2) ) sync_signal_inst ( .clk(clk_156mhz_int), .in({uart_rxd, uart_cts}), .out({uart_rxd_int, uart_cts_int}) ); // SI570 I2C wire i2c_scl_i; wire i2c_scl_o = 1'b1; wire i2c_scl_t = 1'b1; wire i2c_sda_i; wire i2c_sda_o = 1'b1; wire i2c_sda_t = 1'b1; assign i2c_scl_i = i2c_scl; assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o; assign i2c_sda_i = i2c_sda; assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o; // XGMII 10G PHY assign qsfp_modsell = 1'b0; assign qsfp_resetl = 1'b1; assign qsfp_lpmode = 1'b0; wire qsfp_tx_clk_1_int; wire qsfp_tx_rst_1_int; wire [63:0] qsfp_txd_1_int; wire [7:0] qsfp_txc_1_int; wire qsfp_rx_clk_1_int; wire qsfp_rx_rst_1_int; wire [63:0] qsfp_rxd_1_int; wire [7:0] qsfp_rxc_1_int; wire qsfp_tx_clk_2_int; wire qsfp_tx_rst_2_int; wire [63:0] qsfp_txd_2_int; wire [7:0] qsfp_txc_2_int; wire qsfp_rx_clk_2_int; wire qsfp_rx_rst_2_int; wire [63:0] qsfp_rxd_2_int; wire [7:0] qsfp_rxc_2_int; wire qsfp_tx_clk_3_int; wire qsfp_tx_rst_3_int; wire [63:0] qsfp_txd_3_int; wire [7:0] qsfp_txc_3_int; wire qsfp_rx_clk_3_int; wire qsfp_rx_rst_3_int; wire [63:0] qsfp_rxd_3_int; wire [7:0] qsfp_rxc_3_int; wire qsfp_tx_clk_4_int; wire qsfp_tx_rst_4_int; wire [63:0] qsfp_txd_4_int; wire [7:0] qsfp_txc_4_int; wire qsfp_rx_clk_4_int; wire qsfp_rx_rst_4_int; wire [63:0] qsfp_rxd_4_int; wire [7:0] qsfp_rxc_4_int; wire qsfp_rx_block_lock_1; wire qsfp_rx_block_lock_2; wire qsfp_rx_block_lock_3; wire qsfp_rx_block_lock_4; wire qsfp_mgt_refclk_0; wire [3:0] gt_txclkout; wire gt_txusrclk; wire [3:0] gt_rxclkout; wire [3:0] gt_rxusrclk; wire gt_reset_tx_done; wire gt_reset_rx_done; wire [3:0] gt_txprgdivresetdone; wire [3:0] gt_txpmaresetdone; wire [3:0] gt_rxprgdivresetdone; wire [3:0] gt_rxpmaresetdone; wire gt_tx_reset = ~((&gt_txprgdivresetdone) & (&gt_txpmaresetdone)); wire gt_rx_reset = ~&gt_rxpmaresetdone; reg gt_userclk_tx_active = 1'b0; reg [3:0] gt_userclk_rx_active = 1'b0; IBUFDS_GTE3 ibufds_gte3_qsfp_mgt_refclk_0_inst ( .I (qsfp_mgt_refclk_0_p), .IB (qsfp_mgt_refclk_0_n), .CEB (1'b0), .O (qsfp_mgt_refclk_0), .ODIV2 () ); BUFG_GT bufg_gt_tx_usrclk_inst ( .CE (1'b1), .CEMASK (1'b0), .CLR (gt_tx_reset), .CLRMASK (1'b0), .DIV (3'd0), .I (gt_txclkout[0]), .O (gt_txusrclk) ); assign clk_156mhz_int = gt_txusrclk; always @(posedge gt_txusrclk, posedge gt_tx_reset) begin if (gt_tx_reset) begin gt_userclk_tx_active <= 1'b0; end else begin gt_userclk_tx_active <= 1'b1; end end genvar n; generate for (n = 0; n < 4; n = n + 1) begin BUFG_GT bufg_gt_rx_usrclk_inst ( .CE (1'b1), .CEMASK (1'b0), .CLR (gt_rx_reset), .CLRMASK (1'b0), .DIV (3'd0), .I (gt_rxclkout[n]), .O (gt_rxusrclk[n]) ); always @(posedge gt_rxusrclk[n], posedge gt_rx_reset) begin if (gt_rx_reset) begin gt_userclk_rx_active[n] <= 1'b0; end else begin gt_userclk_rx_active[n] <= 1'b1; end end end endgenerate sync_reset #( .N(4) ) sync_reset_156mhz_inst ( .clk(clk_156mhz_int), .rst(~gt_reset_tx_done), .out(rst_156mhz_int) ); wire [5:0] qsfp_gt_txheader_1; wire [63:0] qsfp_gt_txdata_1; wire qsfp_gt_rxgearboxslip_1; wire [5:0] qsfp_gt_rxheader_1; wire [1:0] qsfp_gt_rxheadervalid_1; wire [63:0] qsfp_gt_rxdata_1; wire [1:0] qsfp_gt_rxdatavalid_1; wire [5:0] qsfp_gt_txheader_2; wire [63:0] qsfp_gt_txdata_2; wire qsfp_gt_rxgearboxslip_2; wire [5:0] qsfp_gt_rxheader_2; wire [1:0] qsfp_gt_rxheadervalid_2; wire [63:0] qsfp_gt_rxdata_2; wire [1:0] qsfp_gt_rxdatavalid_2; wire [5:0] qsfp_gt_txheader_3; wire [63:0] qsfp_gt_txdata_3; wire qsfp_gt_rxgearboxslip_3; wire [5:0] qsfp_gt_rxheader_3; wire [1:0] qsfp_gt_rxheadervalid_3; wire [63:0] qsfp_gt_rxdata_3; wire [1:0] qsfp_gt_rxdatavalid_3; wire [5:0] qsfp_gt_txheader_4; wire [63:0] qsfp_gt_txdata_4; wire qsfp_gt_rxgearboxslip_4; wire [5:0] qsfp_gt_rxheader_4; wire [1:0] qsfp_gt_rxheadervalid_4; wire [63:0] qsfp_gt_rxdata_4; wire [1:0] qsfp_gt_rxdatavalid_4; gtwizard_ultrascale_0 qsfp_gty_inst ( .gtwiz_userclk_tx_active_in(&gt_userclk_tx_active), .gtwiz_userclk_rx_active_in(&gt_userclk_rx_active), .gtwiz_reset_clk_freerun_in(clk_125mhz_int), .gtwiz_reset_all_in(rst_125mhz_int), .gtwiz_reset_tx_pll_and_datapath_in(1'b0), .gtwiz_reset_tx_datapath_in(1'b0), .gtwiz_reset_rx_pll_and_datapath_in(1'b0), .gtwiz_reset_rx_datapath_in(1'b0), .gtwiz_reset_rx_cdr_stable_out(), .gtwiz_reset_tx_done_out(gt_reset_tx_done), .gtwiz_reset_rx_done_out(gt_reset_rx_done), .gtrefclk00_in({1{qsfp_mgt_refclk_0}}), .qpll0outclk_out(), .qpll0outrefclk_out(), .gtyrxn_in({qsfp_rx4_n, qsfp_rx3_n, qsfp_rx2_n, qsfp_rx1_n}), .gtyrxp_in({qsfp_rx4_p, qsfp_rx3_p, qsfp_rx2_p, qsfp_rx1_p}), .rxusrclk_in(gt_rxusrclk), .rxusrclk2_in(gt_rxusrclk), .gtwiz_userdata_tx_in({qsfp_gt_txdata_4, qsfp_gt_txdata_3, qsfp_gt_txdata_2, qsfp_gt_txdata_1}), .txheader_in({qsfp_gt_txheader_4, qsfp_gt_txheader_3, qsfp_gt_txheader_2, qsfp_gt_txheader_1}), .txsequence_in({4{1'b0}}), .txusrclk_in({4{gt_txusrclk}}), .txusrclk2_in({4{gt_txusrclk}}), .gtpowergood_out(), .gtytxn_out({qsfp_tx4_n, qsfp_tx3_n, qsfp_tx2_n, qsfp_tx1_n}), .gtytxp_out({qsfp_tx4_p, qsfp_tx3_p, qsfp_tx2_p, qsfp_tx1_p}), .rxgearboxslip_in({qsfp_gt_rxgearboxslip_4, qsfp_gt_rxgearboxslip_3, qsfp_gt_rxgearboxslip_2, qsfp_gt_rxgearboxslip_1}), .gtwiz_userdata_rx_out({qsfp_gt_rxdata_4, qsfp_gt_rxdata_3, qsfp_gt_rxdata_2, qsfp_gt_rxdata_1}), .rxdatavalid_out({qsfp_gt_rxdatavalid_4, qsfp_gt_rxdatavalid_3, qsfp_gt_rxdatavalid_2, qsfp_gt_rxdatavalid_1}), .rxheader_out({qsfp_gt_rxheader_4, qsfp_gt_rxheader_3, qsfp_gt_rxheader_2, qsfp_gt_rxheader_1}), .rxheadervalid_out({qsfp_gt_rxheadervalid_4, qsfp_gt_rxheadervalid_3, qsfp_gt_rxheadervalid_2, qsfp_gt_rxheadervalid_1}), .rxoutclk_out(gt_rxclkout), .rxpmaresetdone_out(gt_rxpmaresetdone), .rxprgdivresetdone_out(gt_rxprgdivresetdone), .rxstartofseq_out(), .txoutclk_out(gt_txclkout), .txpmaresetdone_out(gt_txpmaresetdone), .txprgdivresetdone_out(gt_txprgdivresetdone) ); assign qsfp_tx_clk_1_int = clk_156mhz_int; assign qsfp_tx_rst_1_int = rst_156mhz_int; assign qsfp_rx_clk_1_int = gt_rxusrclk[0]; sync_reset #( .N(4) ) qsfp_rx_rst_1_reset_sync_inst ( .clk(qsfp_rx_clk_1_int), .rst(~gt_reset_rx_done), .out(qsfp_rx_rst_1_int) ); eth_phy_10g #( .BIT_REVERSE(1) ) qsfp_phy_1_inst ( .tx_clk(qsfp_tx_clk_1_int), .tx_rst(qsfp_tx_rst_1_int), .rx_clk(qsfp_rx_clk_1_int), .rx_rst(qsfp_rx_rst_1_int), .xgmii_txd(qsfp_txd_1_int), .xgmii_txc(qsfp_txc_1_int), .xgmii_rxd(qsfp_rxd_1_int), .xgmii_rxc(qsfp_rxc_1_int), .serdes_tx_data(qsfp_gt_txdata_1), .serdes_tx_hdr(qsfp_gt_txheader_1), .serdes_rx_data(qsfp_gt_rxdata_1), .serdes_rx_hdr(qsfp_gt_rxheader_1), .serdes_rx_bitslip(qsfp_gt_rxgearboxslip_1), .rx_block_lock(qsfp_rx_block_lock_1), .rx_high_ber() ); assign qsfp_tx_clk_2_int = clk_156mhz_int; assign qsfp_tx_rst_2_int = rst_156mhz_int; assign qsfp_rx_clk_2_int = gt_rxusrclk[1]; sync_reset #( .N(4) ) qsfp_rx_rst_2_reset_sync_inst ( .clk(qsfp_rx_clk_2_int), .rst(~gt_reset_rx_done), .out(qsfp_rx_rst_2_int) ); eth_phy_10g #( .BIT_REVERSE(1) ) qsfp_phy_2_inst ( .tx_clk(qsfp_tx_clk_2_int), .tx_rst(qsfp_tx_rst_2_int), .rx_clk(qsfp_rx_clk_2_int), .rx_rst(qsfp_rx_rst_2_int), .xgmii_txd(qsfp_txd_2_int), .xgmii_txc(qsfp_txc_2_int), .xgmii_rxd(qsfp_rxd_2_int), .xgmii_rxc(qsfp_rxc_2_int), .serdes_tx_data(qsfp_gt_txdata_2), .serdes_tx_hdr(qsfp_gt_txheader_2), .serdes_rx_data(qsfp_gt_rxdata_2), .serdes_rx_hdr(qsfp_gt_rxheader_2), .serdes_rx_bitslip(qsfp_gt_rxgearboxslip_2), .rx_block_lock(qsfp_rx_block_lock_2), .rx_high_ber() ); assign qsfp_tx_clk_3_int = clk_156mhz_int; assign qsfp_tx_rst_3_int = rst_156mhz_int; assign qsfp_rx_clk_3_int = gt_rxusrclk[2]; sync_reset #( .N(4) ) qsfp_rx_rst_3_reset_sync_inst ( .clk(qsfp_rx_clk_3_int), .rst(~gt_reset_rx_done), .out(qsfp_rx_rst_3_int) ); eth_phy_10g #( .BIT_REVERSE(1) ) qsfp_phy_3_inst ( .tx_clk(qsfp_tx_clk_3_int), .tx_rst(qsfp_tx_rst_3_int), .rx_clk(qsfp_rx_clk_3_int), .rx_rst(qsfp_rx_rst_3_int), .xgmii_txd(qsfp_txd_3_int), .xgmii_txc(qsfp_txc_3_int), .xgmii_rxd(qsfp_rxd_3_int), .xgmii_rxc(qsfp_rxc_3_int), .serdes_tx_data(qsfp_gt_txdata_3), .serdes_tx_hdr(qsfp_gt_txheader_3), .serdes_rx_data(qsfp_gt_rxdata_3), .serdes_rx_hdr(qsfp_gt_rxheader_3), .serdes_rx_bitslip(qsfp_gt_rxgearboxslip_3), .rx_block_lock(qsfp_rx_block_lock_3), .rx_high_ber() ); assign qsfp_tx_clk_4_int = clk_156mhz_int; assign qsfp_tx_rst_4_int = rst_156mhz_int; assign qsfp_rx_clk_4_int = gt_rxusrclk[3]; sync_reset #( .N(4) ) qsfp_rx_rst_4_reset_sync_inst ( .clk(qsfp_rx_clk_4_int), .rst(~gt_reset_rx_done), .out(qsfp_rx_rst_4_int) ); eth_phy_10g #( .BIT_REVERSE(1) ) qsfp_phy_4_inst ( .tx_clk(qsfp_tx_clk_4_int), .tx_rst(qsfp_tx_rst_4_int), .rx_clk(qsfp_rx_clk_4_int), .rx_rst(qsfp_rx_rst_4_int), .xgmii_txd(qsfp_txd_4_int), .xgmii_txc(qsfp_txc_4_int), .xgmii_rxd(qsfp_rxd_4_int), .xgmii_rxc(qsfp_rxc_4_int), .serdes_tx_data(qsfp_gt_txdata_4), .serdes_tx_hdr(qsfp_gt_txheader_4), .serdes_rx_data(qsfp_gt_rxdata_4), .serdes_rx_hdr(qsfp_gt_rxheader_4), .serdes_rx_bitslip(qsfp_gt_rxgearboxslip_4), .rx_block_lock(qsfp_rx_block_lock_4), .rx_high_ber() ); // SGMII interface to PHY wire phy_gmii_clk_int; wire phy_gmii_rst_int; wire phy_gmii_clk_en_int; wire [7:0] phy_gmii_txd_int; wire phy_gmii_tx_en_int; wire phy_gmii_tx_er_int; wire [7:0] phy_gmii_rxd_int; wire phy_gmii_rx_dv_int; wire phy_gmii_rx_er_int; wire [15:0] gig_eth_pcspma_status_vector; wire gig_eth_pcspma_status_link_status = gig_eth_pcspma_status_vector[0]; wire gig_eth_pcspma_status_link_synchronization = gig_eth_pcspma_status_vector[1]; wire gig_eth_pcspma_status_rudi_c = gig_eth_pcspma_status_vector[2]; wire gig_eth_pcspma_status_rudi_i = gig_eth_pcspma_status_vector[3]; wire gig_eth_pcspma_status_rudi_invalid = gig_eth_pcspma_status_vector[4]; wire gig_eth_pcspma_status_rxdisperr = gig_eth_pcspma_status_vector[5]; wire gig_eth_pcspma_status_rxnotintable = gig_eth_pcspma_status_vector[6]; wire gig_eth_pcspma_status_phy_link_status = gig_eth_pcspma_status_vector[7]; wire [1:0] gig_eth_pcspma_status_remote_fault_encdg = gig_eth_pcspma_status_vector[9:8]; wire [1:0] gig_eth_pcspma_status_speed = gig_eth_pcspma_status_vector[11:10]; wire gig_eth_pcspma_status_duplex = gig_eth_pcspma_status_vector[12]; wire gig_eth_pcspma_status_remote_fault = gig_eth_pcspma_status_vector[13]; wire [1:0] gig_eth_pcspma_status_pause = gig_eth_pcspma_status_vector[15:14]; wire [4:0] gig_eth_pcspma_config_vector; assign gig_eth_pcspma_config_vector[4] = 1'b1; // autonegotiation enable assign gig_eth_pcspma_config_vector[3] = 1'b0; // isolate assign gig_eth_pcspma_config_vector[2] = 1'b0; // power down assign gig_eth_pcspma_config_vector[1] = 1'b0; // loopback enable assign gig_eth_pcspma_config_vector[0] = 1'b0; // unidirectional enable wire [15:0] gig_eth_pcspma_an_config_vector; assign gig_eth_pcspma_an_config_vector[15] = 1'b1; // SGMII link status assign gig_eth_pcspma_an_config_vector[14] = 1'b1; // SGMII Acknowledge assign gig_eth_pcspma_an_config_vector[13:12] = 2'b01; // full duplex assign gig_eth_pcspma_an_config_vector[11:10] = 2'b10; // SGMII speed assign gig_eth_pcspma_an_config_vector[9] = 1'b0; // reserved assign gig_eth_pcspma_an_config_vector[8:7] = 2'b00; // pause frames - SGMII reserved assign gig_eth_pcspma_an_config_vector[6] = 1'b0; // reserved assign gig_eth_pcspma_an_config_vector[5] = 1'b0; // full duplex - SGMII reserved assign gig_eth_pcspma_an_config_vector[4:1] = 4'b0000; // reserved assign gig_eth_pcspma_an_config_vector[0] = 1'b1; // SGMII gig_ethernet_pcs_pma_0 gig_eth_pcspma ( // SGMII .txp (phy_sgmii_tx_p), .txn (phy_sgmii_tx_n), .rxp (phy_sgmii_rx_p), .rxn (phy_sgmii_rx_n), // Ref clock from PHY .refclk625_p (phy_sgmii_clk_p), .refclk625_n (phy_sgmii_clk_n), // async reset .reset (rst_125mhz_int), // clock and reset outputs .clk125_out (phy_gmii_clk_int), .clk625_out (), .clk312_out (), .rst_125_out (phy_gmii_rst_int), .idelay_rdy_out (), .mmcm_locked_out (), // MAC clocking .sgmii_clk_r (), .sgmii_clk_f (), .sgmii_clk_en (phy_gmii_clk_en_int), // Speed control .speed_is_10_100 (gig_eth_pcspma_status_speed != 2'b10), .speed_is_100 (gig_eth_pcspma_status_speed == 2'b01), // Internal GMII .gmii_txd (phy_gmii_txd_int), .gmii_tx_en (phy_gmii_tx_en_int), .gmii_tx_er (phy_gmii_tx_er_int), .gmii_rxd (phy_gmii_rxd_int), .gmii_rx_dv (phy_gmii_rx_dv_int), .gmii_rx_er (phy_gmii_rx_er_int), .gmii_isolate (), // Configuration .configuration_vector (gig_eth_pcspma_config_vector), .an_interrupt (), .an_adv_config_vector (gig_eth_pcspma_an_config_vector), .an_restart_config (1'b0), // Status .status_vector (gig_eth_pcspma_status_vector), .signal_detect (1'b1) ); wire [7:0] led_int; assign led = sw[0] ? {4'd0, qsfp_rx_block_lock_4, qsfp_rx_block_lock_3, qsfp_rx_block_lock_2, qsfp_rx_block_lock_1} : led_int; fpga_core core_inst ( /* * Clock: 156.25 MHz * Synchronous reset */ .clk(clk_156mhz_int), .rst(rst_156mhz_int), /* * GPIO */ .btnu(btnu_int), .btnl(btnl_int), .btnd(btnd_int), .btnr(btnr_int), .btnc(btnc_int), .sw(sw_int), .led(led_int), /* * Ethernet: QSFP28 */ .qsfp_tx_clk_1(qsfp_tx_clk_1_int), .qsfp_tx_rst_1(qsfp_tx_rst_1_int), .qsfp_txd_1(qsfp_txd_1_int), .qsfp_txc_1(qsfp_txc_1_int), .qsfp_rx_clk_1(qsfp_rx_clk_1_int), .qsfp_rx_rst_1(qsfp_rx_rst_1_int), .qsfp_rxd_1(qsfp_rxd_1_int), .qsfp_rxc_1(qsfp_rxc_1_int), .qsfp_tx_clk_2(qsfp_tx_clk_2_int), .qsfp_tx_rst_2(qsfp_tx_rst_2_int), .qsfp_txd_2(qsfp_txd_2_int), .qsfp_txc_2(qsfp_txc_2_int), .qsfp_rx_clk_2(qsfp_rx_clk_2_int), .qsfp_rx_rst_2(qsfp_rx_rst_2_int), .qsfp_rxd_2(qsfp_rxd_2_int), .qsfp_rxc_2(qsfp_rxc_2_int), .qsfp_tx_clk_3(qsfp_tx_clk_3_int), .qsfp_tx_rst_3(qsfp_tx_rst_3_int), .qsfp_txd_3(qsfp_txd_3_int), .qsfp_txc_3(qsfp_txc_3_int), .qsfp_rx_clk_3(qsfp_rx_clk_3_int), .qsfp_rx_rst_3(qsfp_rx_rst_3_int), .qsfp_rxd_3(qsfp_rxd_3_int), .qsfp_rxc_3(qsfp_rxc_3_int), .qsfp_tx_clk_4(qsfp_tx_clk_4_int), .qsfp_tx_rst_4(qsfp_tx_rst_4_int), .qsfp_txd_4(qsfp_txd_4_int), .qsfp_txc_4(qsfp_txc_4_int), .qsfp_rx_clk_4(qsfp_rx_clk_4_int), .qsfp_rx_rst_4(qsfp_rx_rst_4_int), .qsfp_rxd_4(qsfp_rxd_4_int), .qsfp_rxc_4(qsfp_rxc_4_int), /* * Ethernet: 1000BASE-T SGMII */ .phy_gmii_clk(phy_gmii_clk_int), .phy_gmii_rst(phy_gmii_rst_int), .phy_gmii_clk_en(phy_gmii_clk_en_int), .phy_gmii_rxd(phy_gmii_rxd_int), .phy_gmii_rx_dv(phy_gmii_rx_dv_int), .phy_gmii_rx_er(phy_gmii_rx_er_int), .phy_gmii_txd(phy_gmii_txd_int), .phy_gmii_tx_en(phy_gmii_tx_en_int), .phy_gmii_tx_er(phy_gmii_tx_er_int), .phy_reset_n(phy_reset_n), .phy_int_n(phy_int_n), /* * UART: 115200 bps, 8N1 */ .uart_rxd(uart_rxd_int), .uart_txd(uart_txd), .uart_rts(uart_rts), .uart_cts(uart_cts_int) ); endmodule
/* This file is part of JT12. JT12 program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. JT12 program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with JT12. If not, see <http://www.gnu.org/licenses/>. Author: Jose Tejada Gomez. Twitter: @topapate Version: 1.0 Date: 21-03-2019 */ // calculates d=a/b // a = b*d + r module jt10_adpcm_div #(parameter dw=16)( input rst_n, input clk, // CPU clock input cen, input start, // strobe input [dw-1:0] a, input [dw-1:0] b, output reg [dw-1:0] d, output reg [dw-1:0] r, output working ); reg [dw-1:0] cycle; assign working = cycle[0]; wire [dw:0] sub = { r[dw-2:0], d[dw-1] } - b; always @(posedge clk or negedge rst_n) if( !rst_n ) begin cycle <= 'd0; end else if(cen) begin if( start ) begin cycle <= ~16'd0; r <= 16'd0; d <= a; end else if(cycle[0]) begin cycle <= { 1'b0, cycle[dw-1:1] }; if( sub[dw] == 0 ) begin r <= sub[dw-1:0]; d <= { d[dw-2:0], 1'b1}; end else begin r <= { r[dw-2:0], d[dw-1] }; d <= { d[dw-2:0], 1'b0 }; end end end endmodule // jt10_adpcm_div
module axis_control_if #( parameter C_s_axis_TDATA_WIDTH = 32, parameter C_m_axis_TDATA_WIDTH = 32, parameter C_m_axis_START_COUNT = 32, parameter C_S_AXIS_RXS_TDATA_WIDTH = 32, parameter C_M_AXIS_TXC_TDATA_WIDTH = 32, parameter C_m_axis_txc_START_COUNT = 32, parameter ENABLE_LEN = 1 ) ( // Ports of Axi Master Bus Interface m_axis input m_axis_txd_tvalid, input m_axis_txd_tlast, input m_axis_txd_tready, input [11:0] tx_pkt_byte_cnt, input tx_pkt_byte_cnt_vld, input s_axis_rxs_aclk, input s_axis_rxs_aresetn, output s_axis_rxs_tready, input [C_S_AXIS_RXS_TDATA_WIDTH-1 : 0] s_axis_rxs_tdata, input [(C_S_AXIS_RXS_TDATA_WIDTH/8)-1 : 0] s_axis_rxs_tkeep, input s_axis_rxs_tlast, input s_axis_rxs_tvalid, input m_axis_txc_aclk, input m_axis_txc_aresetn, output reg m_axis_txc_tvalid, output reg [C_M_AXIS_TXC_TDATA_WIDTH-1 : 0] m_axis_txc_tdata, output reg [(C_M_AXIS_TXC_TDATA_WIDTH/8)-1 : 0] m_axis_txc_tkeep, output reg m_axis_txc_tlast, input m_axis_txc_tready ); reg [2:0] tx_ctrl_state; localparam WAIT_FOR_REQ = 1, SEND_CTRL_PKTS = 2, WAIT_FOR_NXT = 4; reg [7:0] send_ctrl_words; localparam WORD0 = 1, WORD1 = 2, WORD2 = 4, WORD3 = 8, WORD4 = 16, WORD5 = 32; assign s_axis_rxs_tready = 1'b1; reg len_fifo_rd_en; wire [11:0] len_fifo_dout; generate if(ENABLE_LEN)begin small_fifo #( .WIDTH(12), .MAX_DEPTH_BITS(5)) pkt_len_fifo ( .clk(m_axis_txc_aclk), .reset(!m_axis_txc_aresetn), .din(tx_pkt_byte_cnt), .wr_en(tx_pkt_byte_cnt_vld), .rd_en(len_fifo_rd_en), .dout(len_fifo_dout), .full( ), .prog_full(), .nearly_full(), .empty( ) ); end else begin assign len_fifo_dout = 12'hFFF; end endgenerate always@(posedge m_axis_txc_aclk) if(!m_axis_txc_aresetn) len_fifo_rd_en <= 1'b0; else if(tx_pkt_byte_cnt_vld) len_fifo_rd_en <= 1'b1; else len_fifo_rd_en<=0; always @(posedge m_axis_txc_aclk) if(!m_axis_txc_aresetn)begin tx_ctrl_state <= WAIT_FOR_REQ; send_ctrl_words <= WORD0; m_axis_txc_tvalid <= 1'b0; m_axis_txc_tdata <= 32'hFF_FF_FF_FF; m_axis_txc_tkeep <= 4'hF; m_axis_txc_tlast <= 1'b0; end else begin m_axis_txc_tvalid <= 1'b0; m_axis_txc_tdata <= {24'h50000,len_fifo_dout}; m_axis_txc_tkeep <= 4'hF; m_axis_txc_tlast <= 1'b0; case (tx_ctrl_state) WAIT_FOR_REQ: begin if(m_axis_txd_tvalid) begin m_axis_txc_tvalid <= 1'b1; tx_ctrl_state <= SEND_CTRL_PKTS; end end SEND_CTRL_PKTS: begin m_axis_txc_tvalid <= 1'b1; if(m_axis_txc_tready) begin case (send_ctrl_words) WORD0: send_ctrl_words <= WORD1; WORD1: send_ctrl_words <= WORD2; WORD2: send_ctrl_words <= WORD3; WORD3: send_ctrl_words <= WORD4; WORD4: begin send_ctrl_words <= WORD0; m_axis_txc_tlast <= 1'b1; tx_ctrl_state <= WAIT_FOR_NXT; end endcase end end WAIT_FOR_NXT: begin if(m_axis_txd_tready && m_axis_txd_tlast)tx_ctrl_state <= WAIT_FOR_REQ; end default: tx_ctrl_state<=WAIT_FOR_REQ; endcase end endmodule
/* * Copyright (c) 2009 Zeus Gomez Marmolejo <[email protected]> * * This file is part of the Zet processor. This processor is free * hardware; you can redistribute it and/or modify it under the terms of * the GNU General Public License as published by the Free Software * Foundation; either version 3, or (at your option) any later version. * * Zet is distrubuted in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public * License for more details. * * You should have received a copy of the GNU General Public License * along with Zet; see the file COPYING. If not, see * <http://www.gnu.org/licenses/>. */ module hex_display ( input [15:0] num, input en, output [6:0] hex0, output [6:0] hex1, output [6:0] hex2, output [6:0] hex3 ); // Module instantiations seg_7 hex_group0 ( .num (num[3:0]), .en (en), .seg (hex0) ); seg_7 hex_group1 ( .num (num[7:4]), .en (en), .seg (hex1) ); seg_7 hex_group2 ( .num (num[11:8]), .en (en), .seg (hex2) ); seg_7 hex_group3 ( .num (num[15:12]), .en (en), .seg (hex3) ); endmodule
// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2006 by Wilson Snyder. module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=0; reg [63:0] crc; reg [63:0] sum; reg out1; sub sub (.in(crc[23:0]), .out1(out1)); always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x sum=%x out=%x\n",$time, cyc, crc, sum, out1); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {63'h0,out1}; if (cyc==1) begin // Setup crc <= 64'h00000000_00000097; sum <= 64'h0; end else if (cyc==90) begin if (sum !== 64'h2e5cb972eb02b8a0) $stop; end else if (cyc==91) begin end else if (cyc==92) begin end else if (cyc==93) begin end else if (cyc==94) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub (/*AUTOARG*/ // Outputs out1, // Inputs in ); input [23:0] in; output reg [0:0] out1; // Note this tests a vector of 1 bit, which is different from a non-arrayed signal parameter [1023:0] RANDOM = 1024'b101011010100011011100111101001000000101000001111111111100110000110011011010110011101000100110000110101111101000111100100010111001001110001010101000111000100010000010011100001100011110110110000101100011111000110111110010110011000011111111010101110001101010010001111110111100000110111101100110101110001110110000010000110101110111001111001100001101110001011100111001001110101001010000110101010100101111000010000010110100101110100110000110110101000100011101111100011000110011001100010010011001101100100101110010100110101001110011111110010000111001111000010001101100101101110111110001000010110010011100101001011111110011010110111110000110010011110001110110011010011010110011011111001110100010110100011100001011000101111000010011111010111001110110011101110101011111001100011000101000001000100111110010100111011101010101011001101000100000101111110010011010011010001111010001110000110010100011110110011001010000011001010010110111101010010011111111010001000101100010100100010011001100110000111111000001000000001001111101110000100101; always @* begin casez (in[17:16]) 2'b00: casez (in[2:0]) 3'h0: out1[0] = in[0]^RANDOM[0]; 3'h1: out1[0] = in[0]^RANDOM[1]; 3'h2: out1[0] = in[0]^RANDOM[2]; 3'h3: out1[0] = in[0]^RANDOM[3]; 3'h4: out1[0] = in[0]^RANDOM[4]; 3'h5: out1[0] = in[0]^RANDOM[5]; 3'h6: out1[0] = in[0]^RANDOM[6]; 3'h7: out1[0] = in[0]^RANDOM[7]; endcase 2'b01: casez (in[2:0]) 3'h0: out1[0] = RANDOM[10]; 3'h1: out1[0] = RANDOM[11]; 3'h2: out1[0] = RANDOM[12]; 3'h3: out1[0] = RANDOM[13]; 3'h4: out1[0] = RANDOM[14]; 3'h5: out1[0] = RANDOM[15]; 3'h6: out1[0] = RANDOM[16]; 3'h7: out1[0] = RANDOM[17]; endcase 2'b1?: casez (in[4]) 1'b1: casez (in[2:0]) 3'h0: out1[0] = RANDOM[20]; 3'h1: out1[0] = RANDOM[21]; 3'h2: out1[0] = RANDOM[22]; 3'h3: out1[0] = RANDOM[23]; 3'h4: out1[0] = RANDOM[24]; 3'h5: out1[0] = RANDOM[25]; 3'h6: out1[0] = RANDOM[26]; 3'h7: out1[0] = RANDOM[27]; endcase 1'b0: casez (in[2:0]) 3'h0: out1[0] = RANDOM[30]; 3'h1: out1[0] = RANDOM[31]; 3'h2: out1[0] = RANDOM[32]; 3'h3: out1[0] = RANDOM[33]; 3'h4: out1[0] = RANDOM[34]; 3'h5: out1[0] = RANDOM[35]; 3'h6: out1[0] = RANDOM[36]; 3'h7: out1[0] = RANDOM[37]; endcase endcase endcase end endmodule
// ------------------------------------------------------------- // // Generated Architecture Declaration for rtl of inst_edb_e // // Generated // by: wig // on: Mon Mar 22 13:27:29 2004 // cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls // // !!! Do not edit this file! Autogenerated by MIX !!! // $Author: wig $ // $Id: inst_edb_e.v,v 1.1 2004/04/06 10:50:30 wig Exp $ // $Date: 2004/04/06 10:50:30 $ // $Log: inst_edb_e.v,v $ // Revision 1.1 2004/04/06 10:50:30 wig // Adding result/mde_tests // // // Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v // Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp // // Generator: mix_0.pl Revision: 1.26 , [email protected] // (C) 2003 Micronas GmbH // // -------------------------------------------------------------- `timescale 1ns / 1ps // // // Start of Generated Module rtl of inst_edb_e // // No `defines in this module module inst_edb_e // // Generated module inst_edb // ( acg_systime_init, cgu_scani, cgu_scano, ifu_gpio0_wkup, ifu_gpio1_wkup, ifu_gpio2_wkup, nreset, nreset_s, vclkl27 ); // Generated Module Inputs: input [30:0] acg_systime_init; input cgu_scani; input ifu_gpio0_wkup; input ifu_gpio1_wkup; input ifu_gpio2_wkup; input nreset; input nreset_s; input vclkl27; // Generated Module Outputs: output cgu_scano; // Generated Wires: wire [30:0] acg_systime_init; wire cgu_scani; wire cgu_scano; wire ifu_gpio0_wkup; wire ifu_gpio1_wkup; wire ifu_gpio2_wkup; wire nreset; wire nreset_s; wire vclkl27; // End of generated module header // Internal signals // // Generated Signal List // // // End of Generated Signal List // // %COMPILER_OPTS% // Generated Signal Assignments // // Generated Instances // wiring ... // Generated Instances and Port Mappings endmodule // // End of Generated Module rtl of inst_edb_e // // //!End of Module/s // --------------------------------------------------------------
(* Copyright © 1998-2006 * Henk Barendregt * Luís Cruz-Filipe * Herman Geuvers * Mariusz Giero * Rik van Ginneken * Dimitri Hendriks * Sébastien Hinderer * Bart Kirkels * Pierre Letouzey * Iris Loeb * Lionel Mamane * Milad Niqui * Russell O’Connor * Randy Pollack * Nickolay V. Shmyrev * Bas Spitters * Dan Synek * Freek Wiedijk * Jan Zwanenburg * * This work is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This work is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License along * with this work; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *) Require Export Intervals. (** * Metric Spaces (traditional) *) Section Relations. (** ** Relations necessary for Pseudo Metric Spaces and Metric Spaces %\begin{convention}% Let [A : CSetoid], [d : (CSetoid_bin_fun A A IR)]. %\end{convention}% *) Variable A : CSetoid. Variable d : CSetoid_bin_fun A A IR. Set Implicit Arguments. Unset Strict Implicit. Definition com : Prop := forall x y : A, d x y[=]d y x. Definition nneg : Prop := forall x y : A, [0][<=]d x y. Definition pos_imp_ap : CProp := forall x y : A, [0][<]d x y -> x[#]y. Definition tri_ineq : Prop := forall x y z : A, d x z[<=]d x y[+]d y z. Set Strict Implicit. Unset Implicit Arguments. Definition diag_zero (X : CSetoid) (d : CSetoid_bin_fun X X IR) : Prop := forall x : X, d x x[=][0]. Definition apdiag_imp_grzero (X : CSetoid) (d : CSetoid_bin_fun X X IR) : CProp := forall x y : X, x[#]y -> [0][<]d x y. End Relations. Section Definition_PsMS0. (** ** Definition of Pseudo Metric Space *) (** A pseudo metric space consists of a setoid and a %''pseudo metric''% #"pseudo metric"#, also called %''distance''% #"distance"#, a binairy function that fulfils certain properties. *) Record is_CPsMetricSpace (A : CSetoid) (d : CSetoid_bin_fun A A IR) : Type := {ax_d_com : com d; ax_d_nneg : nneg d; ax_d_pos_imp_ap : pos_imp_ap d; ax_d_tri_ineq : tri_ineq d}. Record CPsMetricSpace : Type := {cms_crr :> CSetoid; cms_d : CSetoid_bin_fun cms_crr cms_crr IR; cms_proof : is_CPsMetricSpace cms_crr cms_d}. End Definition_PsMS0. Implicit Arguments cms_d [c]. Infix "[-d]" := cms_d (at level 68, left associativity). Section PsMS_axioms. (** ** Pseudo Metric Space axioms %\begin{convention}% Let [A] be a pseudo metric space. %\end{convention}% *) Variable A : CPsMetricSpace. Lemma CPsMetricSpace_is_CPsMetricSpace : is_CPsMetricSpace A cms_d. Proof cms_proof A. Lemma d_com : com (cms_d (c:=A)). Proof. elim CPsMetricSpace_is_CPsMetricSpace. auto. Qed. Lemma d_nneg : nneg (cms_d (c:=A)). Proof. elim CPsMetricSpace_is_CPsMetricSpace. auto. Qed. Lemma d_pos_imp_ap : pos_imp_ap (cms_d (c:=A)). Proof. elim CPsMetricSpace_is_CPsMetricSpace. auto. Qed. Lemma d_tri_ineq : tri_ineq (cms_d (c:=A)). Proof. elim CPsMetricSpace_is_CPsMetricSpace. auto. Qed. End PsMS_axioms. Section PsMS_basics. (** ** Pseudo Metric Space basics %\begin{convention}% Let [Y] be a pseudo metric space. %\end{convention}% *) Variable Y : CPsMetricSpace. Lemma rev_tri_ineq : forall a b c : cms_crr Y, AbsSmall (b[-d]c) ((a[-d]b)[-](a[-d]c)). Proof. intros. unfold AbsSmall in |- *. split. apply shift_leEq_minus. apply shift_plus_leEq'. unfold cg_minus in |- *. cut ([--][--](b[-d]c)[=]b[-d]c). intros. apply leEq_wdr with ((a[-d]b)[+](b[-d]c)). apply ax_d_tri_ineq. apply CPsMetricSpace_is_CPsMetricSpace. apply eq_symmetric_unfolded. apply bin_op_wd_unfolded. apply eq_reflexive_unfolded. exact H. apply cg_inv_inv. astepr (c[-d]b). apply shift_minus_leEq. apply shift_leEq_plus'. apply shift_minus_leEq. apply ax_d_tri_ineq. apply CPsMetricSpace_is_CPsMetricSpace. apply ax_d_com. apply CPsMetricSpace_is_CPsMetricSpace. Qed. (** Instead of taking [pos_imp_ap] as axiom, we could as well have taken [diag_zero]. *) Lemma diag_zero_imp_pos_imp_ap : forall (X : CSetoid) (d : CSetoid_bin_fun X X IR), diag_zero X d -> pos_imp_ap d. Proof. intros X d. unfold diag_zero in |- *. unfold pos_imp_ap in |- *. intros H. intros x y H0. cut (x[#]x or x[#]y). intro H1. elim H1. cut (Not (x[#]x)). intros H3 H4. set (H5 := H3 H4) in *. intuition. apply ap_irreflexive_unfolded. intro H2. exact H2. apply (csbf_strext X X IR d). astepl ZeroR. apply less_imp_ap. exact H0. Qed. Lemma pos_imp_ap_imp_diag_zero : forall (X : CSetoid) (d : CSetoid_bin_fun X X IR), pos_imp_ap d -> nneg d -> diag_zero X d. Proof. intros X d. unfold pos_imp_ap in |- *. unfold nneg in |- *. intros H H6. unfold diag_zero in |- *. intro x. apply not_ap_imp_eq. red in |- *. intro H0. set (H1 := less_conf_ap IR (d x x) [0]) in *. generalize H1. unfold Iff in |- *. intro H2. elim H2. intros H3 H4. set (H5 := H3 H0) in *. elim H5. generalize H6. intros H7 H8. set (H9 := H7 x x) in *. rewrite -> leEq_def in H9. set (H10 := H9 H8) in *. exact H10. intro H7. set (H8 := H x x) in *. set (H9 := H8 H7) in *. set (H10 := ap_irreflexive_unfolded X x H9) in *. exact H10. Qed. Lemma is_CPsMetricSpace_diag_zero : forall (X : CSetoid) (d : CSetoid_bin_fun X X IR), com d /\ tri_ineq d /\ nneg d /\ diag_zero X d -> is_CPsMetricSpace X d. Proof. intros X d H. elim H. intros H1 H2. elim H2. intros H3 H4. elim H4. intros H5 H6. apply (Build_is_CPsMetricSpace X d H1 H5 (diag_zero_imp_pos_imp_ap X d H6) H3). Qed. End PsMS_basics. Section Zerof. (** ** Zero function *) (** Every setoid forms with the binary function that always returns zero, a pseudo metric space. *) Definition zero_fun (X : CSetoid) (x y : X) : IR := ZeroR. Lemma zero_fun_strext : forall X : CSetoid, bin_fun_strext X X IR (zero_fun X). Proof. intro X. unfold bin_fun_strext in |- *. unfold zero_fun in |- *. intros x1 x2 y1 y2 Z. set (H := ap_irreflexive_unfolded IR [0] Z) in *. intuition. Qed. Definition Zero_fun (X : CSetoid) := Build_CSetoid_bin_fun X X IR (zero_fun X) (zero_fun_strext X). Lemma zero_fun_com : forall X : CSetoid, com (Zero_fun X). Proof. intro X. unfold com in |- *. intros x y. unfold Zero_fun in |- *. simpl in |- *. unfold zero_fun in |- *. intuition. Qed. Lemma zero_fun_nneg : forall X : CSetoid, nneg (Zero_fun X). Proof. intro X. unfold nneg in |- *. intros x y. unfold Zero_fun in |- *. simpl in |- *. unfold zero_fun in |- *. apply eq_imp_leEq. intuition. Qed. Lemma zero_fun_pos_imp_ap : forall X : CSetoid, pos_imp_ap (Zero_fun X). Proof. intro X. unfold pos_imp_ap in |- *. intros x y. unfold Zero_fun in |- *. simpl in |- *. unfold zero_fun in |- *. intro Z. set (H := less_irreflexive IR [0] Z) in *. intuition. Qed. Lemma zero_fun_tri_ineq : forall X : CSetoid, tri_ineq (Zero_fun X). Proof. intro X. unfold tri_ineq in |- *. intros x y z. unfold Zero_fun in |- *. simpl in |- *. unfold zero_fun in |- *. apply eq_imp_leEq. rational. Qed. Definition zf_is_CPsMetricSpace (X : CSetoid) := Build_is_CPsMetricSpace X (Zero_fun X) (zero_fun_com X) ( zero_fun_nneg X) (zero_fun_pos_imp_ap X) (zero_fun_tri_ineq X). Definition zf_as_CPsMetricSpace (X : CSetoid) := Build_CPsMetricSpace X (Zero_fun X) (zf_is_CPsMetricSpace X). End Zerof.
//================================================================================================== // Filename : musb_idex_register.v // Created On : 2014-09-27 20:34:32 // Last Modified : 2015-05-31 13:04:35 // Revision : 1.0 // Author : Angel Terrones // Company : Universidad Simón Bolívar // Email : [email protected] // // Description : Pipeline register: ID -> EX //================================================================================================== module musb_idex_register( input clk, // Main clock input rst, // Main reset input [4:0] id_alu_operation, // ALU operation from ID stage input [31:0] id_data_rs, // Data Rs (forwarded) input [31:0] id_data_rt, // Data Rt (forwarded) input id_gpr_we, // GPR write enable input id_mem_to_gpr_select, // Select MEM/ALU to GPR input id_mem_write, // write to memory input [1:0] id_alu_port_a_select, // Select: GPR, shamt, 0x00000004 input [1:0] id_alu_port_b_select, // Select: GPR, Imm16, PCAdd4 input [1:0] id_gpr_wa_select, // Select: direccion: Rt, Rd, $31 input id_mem_byte, // byte access input id_mem_halfword, // halfword access input id_mem_data_sign_ext, // Zero/Sign extend input [4:0] id_rs, // Rs input [4:0] id_rt, // Rt input id_imm_sign_ext, // extend the imm16 input [15:0] id_sign_imm16, // sign_ext(imm16) input [31:0] id_cp0_data, // input [31:0] id_exception_pc, // Current PC input id_movn, input id_movz, input id_llsc, input id_kernel_mode, input id_is_bds, input id_trap, input id_trap_condition, input id_ex_exception_source, input id_mem_exception_source, input id_flush, // clean input id_stall, // Stall ID stage input ex_stall, // Stall EX stage output reg [4:0] ex_alu_operation, // Same signals, but on EX stage output reg [31:0] ex_data_rs, // output reg [31:0] ex_data_rt, // output reg ex_gpr_we, // output reg ex_mem_to_gpr_select, // output reg ex_mem_write, // output reg [1:0] ex_alu_port_a_select, // output reg [1:0] ex_alu_port_b_select, // output reg [1:0] ex_gpr_wa_select, // output reg ex_mem_byte, // output reg ex_mem_halfword, // output reg ex_mem_data_sign_ext, // output reg [4:0] ex_rs, // output reg [4:0] ex_rt, // output reg [16:0] ex_sign_imm16, // output reg [31:0] ex_cp0_data, output reg [31:0] ex_exception_pc, output reg ex_movn, output reg ex_movz, output reg ex_llsc, output reg ex_kernel_mode, output reg ex_is_bds, output reg ex_trap, output reg ex_trap_condition, output reg ex_ex_exception_source, output reg ex_mem_exception_source ); // sign extend the imm16 wire [16:0] id_imm_extended = (id_imm_sign_ext) ? {id_sign_imm16[15], id_sign_imm16[15:0]} : {1'b0, id_sign_imm16}; //-------------------------------------------------------------------------- // Propagate signals // Clear only critical signals: op, WE, MEM write and Next PC //-------------------------------------------------------------------------- always @(posedge clk) begin ex_alu_operation <= (rst) ? 5'b0 : ((ex_stall) ? ex_alu_operation : ((id_stall | id_flush) ? 5'b0 : id_alu_operation)); ex_data_rs <= (rst) ? 32'b0 : ((ex_stall) ? ex_data_rs : id_data_rs); ex_data_rt <= (rst) ? 32'b0 : ((ex_stall) ? ex_data_rt : id_data_rt); ex_gpr_we <= (rst) ? 1'b0 : ((ex_stall) ? ex_gpr_we : ((id_stall | id_flush) ? 1'b0 : id_gpr_we)); ex_mem_to_gpr_select <= (rst) ? 1'b0 : ((ex_stall) ? ex_mem_to_gpr_select : ((id_stall | id_flush) ? 1'b0 : id_mem_to_gpr_select)); ex_mem_write <= (rst) ? 1'b0 : ((ex_stall) ? ex_mem_write : ((id_stall | id_flush) ? 1'b0 : id_mem_write)); ex_alu_port_a_select <= (rst) ? 2'b0 : ((ex_stall) ? ex_alu_port_a_select : id_alu_port_a_select); ex_alu_port_b_select <= (rst) ? 2'b0 : ((ex_stall) ? ex_alu_port_b_select : id_alu_port_b_select); ex_gpr_wa_select <= (rst) ? 2'b0 : ((ex_stall) ? ex_gpr_wa_select : id_gpr_wa_select); ex_mem_byte <= (rst) ? 1'b0 : ((ex_stall) ? ex_mem_byte : id_mem_byte); ex_mem_halfword <= (rst) ? 1'b0 : ((ex_stall) ? ex_mem_halfword : id_mem_halfword); ex_mem_data_sign_ext <= (rst) ? 1'b0 : ((ex_stall) ? ex_mem_data_sign_ext : id_mem_data_sign_ext); ex_rs <= (rst) ? 5'b0 : ((ex_stall) ? ex_rs : id_rs); ex_rt <= (rst) ? 5'b0 : ((ex_stall) ? ex_rt : id_rt); ex_sign_imm16 <= (rst) ? 17'b0 : ((ex_stall) ? ex_sign_imm16 : id_imm_extended); ex_cp0_data <= (rst) ? 32'b0 : ((ex_stall) ? ex_cp0_data : id_cp0_data); ex_exception_pc <= (rst) ? 32'b0 : ((ex_stall) ? ex_exception_pc : id_exception_pc); ex_movn <= (rst) ? 1'b0 : ((ex_stall) ? ex_movn : ((id_stall | id_flush) ? 1'b0 : id_movn)); ex_movz <= (rst) ? 1'b0 : ((ex_stall) ? ex_movz : ((id_stall | id_flush) ? 1'b0 : id_movz)); ex_llsc <= (rst) ? 1'b0 : ((ex_stall) ? ex_llsc : ((id_stall | id_flush) ? 1'b0 : id_llsc)); ex_kernel_mode <= (rst) ? 1'b0 : ((ex_stall) ? ex_kernel_mode : id_kernel_mode); ex_is_bds <= (rst) ? 1'b0 : ((ex_stall) ? ex_is_bds : id_is_bds); ex_trap <= (rst) ? 1'b0 : ((ex_stall) ? ex_trap : ((id_stall | id_flush) ? 1'b0 : id_trap)); ex_trap_condition <= (rst) ? 1'b0 : ((ex_stall) ? ex_trap_condition : id_trap_condition); ex_ex_exception_source <= (rst) ? 1'b0 : ((ex_stall) ? ex_ex_exception_source : ((id_stall | id_flush) ? 1'b0 : id_ex_exception_source)); ex_mem_exception_source <= (rst) ? 1'b0 : ((ex_stall) ? ex_mem_exception_source : ((id_stall | id_flush) ? 1'b0 : id_mem_exception_source)); end endmodule
// (C) 2001-2016 Intel Corporation. All rights reserved. // Your use of Intel Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Intel Program License Subscription // Agreement, Intel MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Intel and sold by // Intel or its authorized distributors. Please refer to the applicable // agreement for further details. // $Id: //acds/rel/16.1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ // $Revision: #1 $ // $Date: 2016/08/07 $ // $Author: swbranch $ // ----------------------------------------------- // Reset Synchronizer // ----------------------------------------------- `timescale 1 ns / 1 ns module altera_reset_synchronizer #( parameter ASYNC_RESET = 1, parameter DEPTH = 2 ) ( input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, input clk, output reset_out ); // ----------------------------------------------- // Synchronizer register chain. We cannot reuse the // standard synchronizer in this implementation // because our timing constraints are different. // // Instead of cutting the timing path to the d-input // on the first flop we need to cut the aclr input. // // We omit the "preserve" attribute on the final // output register, so that the synthesis tool can // duplicate it where needed. // ----------------------------------------------- (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; reg altera_reset_synchronizer_int_chain_out; generate if (ASYNC_RESET) begin // ----------------------------------------------- // Assert asynchronously, deassert synchronously. // ----------------------------------------------- always @(posedge clk or posedge reset_in) begin if (reset_in) begin altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; altera_reset_synchronizer_int_chain_out <= 1'b1; end else begin altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; end end assign reset_out = altera_reset_synchronizer_int_chain_out; end else begin // ----------------------------------------------- // Assert synchronously, deassert synchronously. // ----------------------------------------------- always @(posedge clk) begin altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; end assign reset_out = altera_reset_synchronizer_int_chain_out; end endgenerate endmodule
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014 // // most of pentevo ports are here /* This file is part of ZX-Evo Base Configuration firmware. ZX-Evo Base Configuration firmware is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. ZX-Evo Base Configuration firmware is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with ZX-Evo Base Configuration firmware. If not, see <http://www.gnu.org/licenses/>. */ `include "../include/tune.v" module zports( input wire zclk, // z80 clock input wire fclk, // global FPGA clock input wire rst_n, // system reset input wire zpos, input wire zneg, input wire [ 7:0] din, output reg [ 7:0] dout, output wire dataout, input wire [15:0] a, input wire iorq_n, input wire mreq_n, input wire m1_n, input wire rd_n, input wire wr_n, output reg porthit, // when internal port hit occurs, this is 1, else 0; used for iorq1_n iorq2_n on zxbus output reg external_port, // asserts for AY and VG93 accesses output wire [15:0] ideout, input wire [15:0] idein, output wire idedataout, // IDE must IN data from IDE device when idedataout=0, else it OUTs output wire [ 2:0] ide_a, output wire ide_cs0_n, output wire ide_cs1_n, output wire ide_rd_n, output wire ide_wr_n, input wire [ 4:0] keys_in, // keys (port FE) input wire [ 7:0] mus_in, // mouse (xxDF) input wire [ 4:0] kj_in, output reg [ 3:0] border, input wire dos, output wire ay_bdir, output wire ay_bc1, output wire [ 7:0] p7ffd, output wire [ 7:0] peff7, input wire tape_read, output wire vg_cs_n, input wire vg_intrq, input wire vg_drq, // from vg93 module - drq + irq read output wire vg_wrFF, // write strobe of #FF port output wire sd_cs_n_val, output wire sd_cs_n_stb, output wire sd_start, output wire [ 7:0] sd_datain, input wire [ 7:0] sd_dataout, // WAIT-ports related // output reg [ 7:0] gluclock_addr, // output reg [ 2:0] comport_addr, // output wire wait_start_gluclock, // begin wait from some ports output wire wait_start_comport, // // output reg wait_rnw, // whether it was read(=1) or write(=0) output reg [ 7:0] wait_write, input wire [ 7:0] wait_read, output wire atmF7_wr_fclk, // used in atm_pager.v output reg [ 2:0] atm_scr_mode, // RG0..RG2 in docs output reg atm_turbo, // turbo mode ON output reg atm_pen, // pager_off in atm_pager.v, NOT inverted!!! output reg atm_cpm_n, // permanent dos on output reg atm_pen2, // PEN2 - fucking palette mode, NOT inverted!!! output wire romrw_en, // from port BF output wire pent1m_ram0_0, // d3.eff7 output wire pent1m_1m_on, // d2.eff7 output wire [ 5:0] pent1m_page, // full 1 meg page number output wire pent1m_ROM, // d4.7ffd output wire atm_palwr, // palette write strobe output wire [ 5:0] atm_paldata, // palette write data output wire covox_wr, output wire beeper_wr, output wire clr_nmi, output wire fnt_wr, // write to font_ram enabled // inputs from atm_pagers, to read back its config input wire [63:0] pages, input wire [ 7:0] ramnroms, input wire [ 7:0] dos7ffds, input wire [ 7:0] wrdisables, input wire [ 5:0] palcolor, input wire [ 7:0] fontrom_readback, // ulaplus output reg up_ena, output reg [ 5:0] up_paladdr, output wire [ 7:0] up_paldata, output wire up_palwr, // NMI generation output reg set_nmi, // break enable & address output reg brk_ena, output reg [15:0] brk_addr ); `define IS_NIDE_REGS(x) ( (x[2:0]==3'b000) && (x[3]!=x[4]) ) `define IS_NIDE_HIGH(x) ( x[7:0]==8'h11 ) `define IS_PORT_NIDE(x) ( `IS_NIDE_REGS(x) || `IS_NIDE_HIGH(x) ) `define NIDE_REGS 8'h10,8'h30,8'h50,8'h70,8'h90,8'hB0,8'hD0,8'hF0, \ 8'h08,8'h28,8'h48,8'h68,8'h88,8'hA8,8'hC8,8'hE8 localparam PORTFE = 8'hFE; localparam PORTF6 = 8'hF6; localparam PORTF7 = 8'hF7; localparam NIDE10 = 8'h10; localparam NIDE11 = 8'h11; localparam NIDE30 = 8'h30; localparam NIDE50 = 8'h50; localparam NIDE70 = 8'h70; localparam NIDE90 = 8'h90; localparam NIDEB0 = 8'hB0; localparam NIDED0 = 8'hD0; localparam NIDEF0 = 8'hF0; localparam NIDEC8 = 8'hC8; localparam PORTFD = 8'hFD; localparam VGCOM = 8'h1F; localparam VGTRK = 8'h3F; localparam VGSEC = 8'h5F; localparam VGDAT = 8'h7F; localparam VGSYS = 8'hFF; localparam SAVPORT1 = 8'h2F; localparam SAVPORT2 = 8'h4F; localparam SAVPORT3 = 8'h6F; localparam SAVPORT4 = 8'h8F; localparam KJOY = 8'h1F; localparam KMOUSE = 8'hDF; localparam SDCFG = 8'h77; localparam SDDAT = 8'h57; localparam ATMF7 = 8'hF7; localparam ATM77 = 8'h77; localparam ZXEVBE = 8'hBE; // xxBE config-read and nmi-end port localparam ZXEVBF = 8'hBF; // xxBF config port localparam ZXEVBRK = 8'hBD; // xxBD breakpoint address port localparam COMPORT = 8'hEF; // F8EF..FFEF - rs232 ports localparam COVOX = 8'hFB; localparam ULAPLUS = 8'h3B; reg port_wr; reg port_rd; reg iowr_reg; reg iord_reg; reg port_wr_fclk, port_rd_fclk, mem_wr_fclk; reg [1:0] iowr_reg_fclk, iord_reg_fclk; reg [1:0] memwr_reg_fclk; wire [7:0] loa; wire ideout_hi_wr; wire idein_lo_rd; reg [7:0] idehiin; // IDE high part read register: low part is read directly to Z80 bus, // while high part is remembered here reg ide_ports; // ide ports selected reg ide_rd_trig; // nemo-divide read trigger reg ide_rd_latch; // to save state of trigger during read cycle reg ide_wrlo_trig, ide_wrhi_trig; // nemo-divide write triggers reg ide_wrlo_latch, ide_wrhi_latch; // save state during write cycles reg [15:0] idewrreg; // write register, either low or high part is pre-written here, // while other part is out directly from Z80 bus wire [ 7:0] iderdeven; // to control read data from "even" ide ports (all except #11) wire [ 7:0] iderdodd; // read data from "odd" port (#11) reg pre_bc1,pre_bdir; wire gluclock_on; reg shadow_en_reg; //bit0.xxBF reg romrw_en_reg; //bit1.xxBF reg fntw_en_reg; //bit2.xxBF wire shadow; reg [7:0] portbemux; reg [7:0] savport [3:0]; reg [5:0] vgFF; reg [7:0] up_lastwritten; assign shadow = dos || shadow_en_reg; assign loa=a[7:0]; always @* begin if( (loa==PORTFE) || (loa==PORTF6) || (loa==PORTFD) || (loa==8'hFC) || `IS_PORT_NIDE(loa) || // (loa==NIDE10) || (loa==NIDE11) || (loa==NIDE30) || (loa==NIDE50) || (loa==NIDE70) || // (loa==NIDE90) || (loa==NIDEB0) || (loa==NIDED0) || (loa==NIDEF0) || (loa==NIDEC8) || (loa==KMOUSE) || ( (loa==VGCOM)&&shadow ) || ( (loa==VGTRK)&&shadow ) || ( (loa==VGSEC)&&shadow ) || ( (loa==VGDAT)&&shadow ) || ( (loa==VGSYS)&&shadow ) || ( (loa==KJOY)&&(!shadow) ) || ( (loa==SAVPORT1)&&shadow ) || ( (loa==SAVPORT2)&&shadow ) || ( (loa==SAVPORT3)&&shadow ) || ( (loa==SAVPORT4)&&shadow ) || ( (loa==PORTF7)&&(!shadow) ) || ( (loa==SDCFG)&&(!shadow) ) || ( (loa==SDDAT) ) || ( (loa==ATMF7)&&shadow ) || ( (loa==ATM77)&&shadow ) || ( loa==ZXEVBF ) || ( loa==ZXEVBE) || ( loa==ZXEVBRK) || ( loa==COMPORT ) || ( loa==ULAPLUS) ) porthit = 1'b1; else porthit = 1'b0; end always @* begin if( ((loa==PORTFD) && a[15]) || // 0xBFFD/0xFFFD ports (( (loa==VGCOM)&&shadow ) || ( (loa==VGTRK)&&shadow ) || ( (loa==VGSEC)&&shadow ) || ( (loa==VGDAT)&&shadow )) ) // vg93 ports external_port = 1'b1; else external_port = 1'b0; end assign dataout = porthit & (~iorq_n) & (~rd_n) & (~external_port); // this is zclk-synchronous strobes always @(posedge zclk) begin iowr_reg <= ~(iorq_n | wr_n); iord_reg <= ~(iorq_n | rd_n); if( (!iowr_reg) && (!iorq_n) && (!wr_n) ) port_wr <= 1'b1; else port_wr <= 1'b0; if( (!iord_reg) && (!iorq_n) && (!rd_n) ) port_rd <= 1'b1; else port_rd <= 1'b0; end // fclk-synchronous stobes // always @(posedge fclk) if( zpos ) begin iowr_reg_fclk[0] <= ~(iorq_n | wr_n); iord_reg_fclk[0] <= ~(iorq_n | rd_n); end always @(posedge fclk) begin iowr_reg_fclk[1] <= iowr_reg_fclk[0]; iord_reg_fclk[1] <= iord_reg_fclk[0]; end always @(posedge fclk) begin port_wr_fclk <= iowr_reg_fclk[0] && (!iowr_reg_fclk[1]); port_rd_fclk <= iord_reg_fclk[0] && (!iord_reg_fclk[1]); end always @(posedge fclk) memwr_reg_fclk[1:0] <= { memwr_reg_fclk[0], ~(mreq_n | wr_n) }; always @(posedge fclk) mem_wr_fclk <= memwr_reg_fclk[0] && (!memwr_reg_fclk[1]); // dout data always @* begin case( loa ) PORTFE: dout = { 1'b1, tape_read, 1'b0, keys_in }; PORTF6: dout = { 1'b1, tape_read, 1'b0, keys_in }; `NIDE_REGS: dout = iderdeven; NIDE11: dout = iderdodd; //PORTFD: VGSYS: dout = { vg_intrq, vg_drq, vgFF }; // 6'b111111 }; SAVPORT1, SAVPORT2, SAVPORT3, SAVPORT4: dout = savport[ loa[6:5] ]; KJOY: dout = {3'b000, kj_in}; KMOUSE: dout = mus_in; SDCFG: dout = 8'h00; // always SD inserted, SD is in R/W mode SDDAT: dout = sd_dataout; PORTF7: begin if( !a[14] && (a[8]^shadow) && gluclock_on ) // $BFF7 - data i/o dout = wait_read; else // any other $xxF7 port dout = 8'hFF; end COMPORT: begin dout = wait_read; // $F8EF..$FFEF end ZXEVBF: begin dout = { 3'b000, brk_ena, set_nmi, fntw_en_reg, romrw_en_reg, shadow_en_reg }; end ZXEVBE: begin dout = portbemux; end ULAPLUS: begin dout = up_lastwritten; end default: dout = 8'hFF; endcase end assign portfd_wr = ( (loa==PORTFD || loa==8'hFC) && port_wr); // F7 ports (like EFF7) are accessible in shadow mode but at addresses like EEF7, DEF7, BEF7 so that // there are no conflicts in shadow mode with ATM xFF7 and x7F7 ports assign portf7_wr = ( (loa==PORTF7) && (a[8]==1'b1) && port_wr && (!shadow) ) || ( (loa==PORTF7) && (a[8]==1'b0) && port_wr && shadow ) ; assign portf7_rd = ( (loa==PORTF7) && (a[8]==1'b1) && port_rd && (!shadow) ) || ( (loa==PORTF7) && (a[8]==1'b0) && port_rd && shadow ) ; assign vg_wrFF = ( ( (loa==VGSYS)&&shadow ) && port_wr); always @(posedge zclk) if( vg_wrFF ) vgFF <= din[5:0]; assign comport_wr = ( (loa==COMPORT) && port_wr); assign comport_rd = ( (loa==COMPORT) && port_rd); assign zxevbrk_wr_fclk = ( (loa==ZXEVBRK) && port_wr_fclk); // break address write always @(posedge fclk) if( zxevbrk_wr_fclk) begin if( !a[8] ) brk_addr[ 7:0] <= din; else // a[8]==1 brk_addr[15:8] <= din; end //border port FE wire portwe_wr_fclk; assign portfe_wr_fclk = (((loa==PORTFE) || (loa==PORTF6) || (loa==8'hFC)) && port_wr_fclk); always @(posedge fclk) if( portfe_wr_fclk ) border <= { ~a[3], din[2:0] }; // IDE ports // IDE physical ports (that go to IDE device) always @(loa) if( `IS_NIDE_REGS(loa) ) ide_ports = 1'b1; else ide_ports = 1'b0; assign idein_lo_rd = port_rd && (loa==NIDE10) && (!ide_rd_trig); // control read & write triggers, which allow nemo-divide mod to work. // // read trigger: always @(posedge zclk) begin if( (loa==NIDE10) && port_rd && !ide_rd_trig ) ide_rd_trig <= 1'b1; else if( ( ide_ports || (loa==NIDE11) ) && ( port_rd || port_wr ) ) ide_rd_trig <= 1'b0; end // // two triggers for write sequence... always @(posedge zclk) if( ( ide_ports || (loa==NIDE11) ) && ( port_rd || port_wr ) ) begin if( (loa==NIDE11) && port_wr ) ide_wrhi_trig <= 1'b1; else ide_wrhi_trig <= 1'b0; // if( (loa==NIDE10) && port_wr && !ide_wrhi_trig && !ide_wrlo_trig ) ide_wrlo_trig <= 1'b1; else ide_wrlo_trig <= 1'b0; end // normal read: #10(low), #11(high) // divide read: #10(low), #10(high) // // normal write: #11(high), #10(low) // divide write: #10(low), #10(high) always @(posedge zclk) begin if( port_wr && (loa==NIDE11) ) idewrreg[15:8] <= din; if( port_wr && (loa==NIDE10) && !ide_wrlo_trig ) idewrreg[ 7:0] <= din; end always @(posedge zclk) if( idein_lo_rd ) idehiin <= idein[15:8]; assign ide_a = a[7:5]; // This is unknown shit... Probably need more testing with old WD // drives WITHOUT this commented fix. // // trying to fix old WD drives... //assign ide_cs0_n = iorq_n | (rd_n&wr_n) | (~ide_ports) | (~(loa!=NIDEC8)); //assign ide_cs1_n = iorq_n | (rd_n&wr_n) | (~ide_ports) | (~(loa==NIDEC8)); // fix ends... assign ide_cs0_n = (~ide_ports) | (~(loa!=NIDEC8)); assign ide_cs1_n = (~ide_ports) | (~(loa==NIDEC8)); // generate read cycles for IDE as usual, except for reading #10 // instead of #11 for high byte (nemo-divide). I use additional latch // since 'ide_rd_trig' clears during second Z80 IO read cycle to #10 always @* if( rd_n ) ide_rd_latch <= ide_rd_trig; // assign ide_rd_n = iorq_n | rd_n | (~ide_ports) | (ide_rd_latch && (loa==NIDE10)); always @* if( wr_n ) ide_wrlo_latch <= ide_wrlo_trig; // same for write triggers always @* if( wr_n ) ide_wrhi_latch <= ide_wrhi_trig; // // assign ide_wr_n = iorq_n | wr_n | (~ide_ports) | ( (loa==NIDE10) && !ide_wrlo_latch && !ide_wrhi_latch ); // do NOT generate IDE write, if neither of ide_wrhi|lo latches // set and writing to NIDE10 // assign idedataout = ide_rd_n; assign idedataout = ~ide_wr_n; // shit-fix in try to fix IDE errors // warning: this fix kinda blind-picking, good way is to // have idedataout lead wr or rd strobes. also good point to disable data ringing // on ide data bus while not accessing IDE // data read by Z80 from IDE // assign iderdodd[ 7:0] = idehiin[ 7:0]; // assign iderdeven[ 7:0] = (ide_rd_latch && (loa==NIDE10)) ? idehiin[ 7:0] : idein[ 7:0]; // data written to IDE from Z80 // assign ideout[15:8] = ide_wrhi_latch ? idewrreg[15:8] : din[ 7:0]; assign ideout[ 7:0] = ide_wrlo_latch ? idewrreg[ 7:0] : din[ 7:0]; // AY control always @* begin pre_bc1 = 1'b0; pre_bdir = 1'b0; if( loa==PORTFD ) begin if( a[15:14]==2'b11 ) begin pre_bc1=1'b1; pre_bdir=1'b1; end else if( a[15:14]==2'b10 ) begin pre_bc1=1'b0; pre_bdir=1'b1; end end end assign ay_bc1 = pre_bc1 & (~iorq_n) & ((~rd_n)|(~wr_n)); assign ay_bdir = pre_bdir & (~iorq_n) & (~wr_n); // 7FFD port reg [7:0] p7ffd_int,peff7_int; reg p7ffd_rom_int; wire block7ffd; wire block1m; always @(posedge zclk, negedge rst_n) begin if( !rst_n ) p7ffd_int <= 7'h00; else if( (a[15]==1'b0) && portfd_wr && (!block7ffd) ) p7ffd_int <= din; // 2..0 - page, 3 - screen, 4 - rom, 5 - block48k, 6..7 - end always @(posedge zclk, negedge rst_n) if( !rst_n ) p7ffd_rom_int <= 1'b0; else if( (a[15]==1'b0) && portfd_wr && (!block7ffd) ) p7ffd_rom_int <= din[4]; assign block7ffd=p7ffd_int[5] & block1m; // EFF7 port always @(posedge zclk, negedge rst_n) begin if( !rst_n ) peff7_int <= 8'h00; else if( !a[12] && portf7_wr && (!shadow) ) // EEF7 in shadow mode is abandoned! peff7_int <= din; // 4 - turbooff, 0 - p16c on, 2 - block1meg end assign block1m = peff7_int[2]; assign p7ffd = { (block1m ? 3'b0 : p7ffd_int[7:5]),p7ffd_rom_int,p7ffd_int[3:0]}; assign peff7 = block1m ? { peff7_int[7], 1'b0, peff7_int[5], peff7_int[4], 3'b000, peff7_int[0] } : peff7_int; assign pent1m_ROM = p7ffd_int[4]; assign pent1m_page[5:0] = { p7ffd_int[7:5], p7ffd_int[2:0] }; assign pent1m_1m_on = ~peff7_int[2]; assign pent1m_ram0_0 = peff7_int[3]; // gluclock ports (bit7:eff7 is above) assign gluclock_on = peff7_int[7] || shadow; // in shadow mode EEF7 is abandoned: instead, gluclock access // is ON forever in shadow mode. always @(posedge zclk) begin if( gluclock_on && portf7_wr ) // gluclocks on begin if( !a[13] ) // $DFF7 - addr reg gluclock_addr <= din; // write to waiting register is not here - in separate section managing wait_write end end // comports always @(posedge zclk) begin if( comport_wr || comport_rd ) comport_addr <= a[10:8 ]; end // write to wait registers always @(posedge zclk) begin // gluclocks if( gluclock_on && portf7_wr && !a[14] ) // $BFF7 - data reg wait_write <= din; // com ports else if( comport_wr ) // $F8EF..$FFEF - comports wait_write <= din; end // wait from wait registers // // ACHTUNG!!!! here portxx_wr are ON Z80 CLOCK! logic must change when moving to fclk strobes // assign wait_start_gluclock = ( gluclock_on && !a[14] && (portf7_rd || portf7_wr) ); // $BFF7 - gluclock r/w // assign wait_start_comport = ( comport_rd || comport_wr ); // // always @(posedge zclk) // wait rnw - only meanful during wait begin if( port_wr ) wait_rnw <= 1'b0; if( port_rd ) wait_rnw <= 1'b1; end // VG93 control assign vg_cs_n = (~shadow) | iorq_n | (rd_n & wr_n) | ( ~((loa==VGCOM)|(loa==VGTRK)|(loa==VGSEC)|(loa==VGDAT)) ); // SD card (z-control¸r compatible) wire sdcfg_wr,sddat_wr,sddat_rd; assign sdcfg_wr = ( (loa==SDCFG) && port_wr_fclk && (!shadow) ) || ( (loa==SDDAT) && port_wr_fclk && shadow && (a[15]==1'b1) ) ; assign sddat_wr = ( (loa==SDDAT) && port_wr_fclk && (!shadow) ) || ( (loa==SDDAT) && port_wr_fclk && shadow && (a[15]==1'b0) ) ; assign sddat_rd = ( (loa==SDDAT) && port_rd_fclk ); // SDCFG write - sdcs_n control assign sd_cs_n_stb = sdcfg_wr; assign sd_cs_n_val = din[1]; // start signal for SPI module with resyncing to fclk assign sd_start = sddat_wr || sddat_rd; // data for SPI module assign sd_datain = sddat_rd ? 8'hFF : din; ///////////////////////////////////////////////////////////////////////////////////////////////// /////////////// // ATM ports // /////////////// wire atm77_wr_fclk; wire zxevbf_wr_fclk; assign atmF7_wr_fclk = ( (loa==ATMF7) && (a[8]==1'b1) && shadow && port_wr_fclk ); // xFF7 and x7F7 ports, NOT xEF7! assign atm77_wr_fclk = ( (loa==ATM77) && shadow && port_wr_fclk ); assign zxevbf_wr_fclk = ( (loa==ZXEVBF) && port_wr_fclk ); // port BF write // always @(posedge fclk, negedge rst_n) if( !rst_n ) begin shadow_en_reg <= 1'b0; romrw_en_reg <= 1'b0; fntw_en_reg <= 1'b0; set_nmi <= 1'b0; brk_ena <= 1'b0; end else if( zxevbf_wr_fclk ) begin shadow_en_reg <= din[0]; romrw_en_reg <= din[1]; fntw_en_reg <= din[2]; set_nmi <= din[3]; brk_ena <= din[4]; end assign romrw_en = romrw_en_reg; // port xx77 write always @(posedge fclk, negedge rst_n) if( !rst_n ) begin atm_scr_mode = 3'b011; atm_turbo = 1'b0; atm_pen = 1'b1; // no manager, atm_cpm_n = 1'b0; // permanent dosen (shadow ports on) atm_pen2 = 1'b0; end else if( atm77_wr_fclk ) begin atm_scr_mode <= din[2:0]; atm_turbo <= din[3]; atm_pen <= ~a[8]; atm_cpm_n <= a[9]; atm_pen2 <= ~a[14]; end // atm palette strobe and data wire vg_wrFF_fclk; assign vg_wrFF_fclk = ( ( (loa==VGSYS)&&shadow ) && port_wr_fclk); assign atm_palwr = vg_wrFF_fclk & atm_pen2; assign atm_paldata = { ~din[4], ~din[7], ~din[1], ~din[6], ~din[0], ~din[5] }; // port BE write assign clr_nmi = ( (loa==ZXEVBE) && port_wr_fclk ); // covox/beeper writes assign beeper_wr = (loa==PORTFE) && portfe_wr_fclk; assign covox_wr = (loa==COVOX) && port_wr_fclk; // font write enable assign fnt_wr = fntw_en_reg && mem_wr_fclk; // port BE read always @* case( a[12:8] ) 5'h0: portbemux = pages[ 7:0 ]; 5'h1: portbemux = pages[15:8 ]; 5'h2: portbemux = pages[23:16]; 5'h3: portbemux = pages[31:24]; 5'h4: portbemux = pages[39:32]; 5'h5: portbemux = pages[47:40]; 5'h6: portbemux = pages[55:48]; 5'h7: portbemux = pages[63:56]; 5'h8: portbemux = ramnroms; 5'h9: portbemux = dos7ffds; 5'hA: portbemux = p7ffd_int; 5'hB: portbemux = peff7_int; 5'hC: portbemux = { ~atm_pen2, atm_cpm_n, ~atm_pen, dos, atm_turbo, atm_scr_mode }; 5'hD: portbemux = { ~palcolor[4], ~palcolor[2], ~palcolor[0], ~palcolor[5], 2'b11, ~palcolor[3], ~palcolor[1] }; // assign atm_paldata = { ~din[4], ~din[7], ~din[1], ~din[6], ~din[0], ~din[5] }; // {GgRrBb} -> {grbG11RB} // was: 76543210 -> 471605 // now: 543210 -> 4205xx31 5'hE: portbemux = fontrom_readback; 5'hF: portbemux = { 4'bXXXX, border }; 5'h10: portbemux = brk_addr[7:0]; 5'h11: portbemux = brk_addr[15:8]; 5'h12: portbemux = wrdisables; default: portbemux = 8'bXXXXXXXX; endcase // savelij ports write // always @(posedge fclk) if( port_wr_fclk && shadow ) begin if( (loa==SAVPORT1) || (loa==SAVPORT2) || (loa==SAVPORT3) || (loa==SAVPORT4) ) savport[ loa[6:5] ] <= din; end // ULAPLUS ports reg up_select; // 0 -- ena/dis, 1 -- palette write // wire up_wr = port_wr_fclk && (loa==ULAPLUS); // always @(posedge fclk) if( up_wr && !a[14] ) begin if( !din[7] && din[6] ) begin up_select <= 1'b1; end if( !din[7] && !din[6] ) begin up_select <= 1'b0; up_paladdr[5:0] <= din[5:0]; end end // always @(posedge fclk) if( up_wr && a[14] ) up_lastwritten <= din; // assign up_palwr = up_wr && a[14] && !up_select; // always @(posedge fclk, negedge rst_n) if( !rst_n ) up_ena <= 1'b0; else if( up_wr && a[14] && up_select ) up_ena <= din[0]; // assign up_paldata = {din[4:2],din[7:5],din[1:0]}; // G3R3B2 to R3G3B2 endmodule
module mem_window ( clk, reset, // Memory slave port s1_address, s1_read, s1_readdata, s1_readdatavalid, s1_write, s1_writedata, s1_burstcount, s1_byteenable, s1_waitrequest, // Configuration register slave port cra_write, cra_writedata, cra_byteenable, // Bridged master port to memory m1_address, m1_read, m1_readdata, m1_readdatavalid, m1_write, m1_writedata, m1_burstcount, m1_byteenable, m1_waitrequest ); parameter PAGE_ADDRESS_WIDTH = 20; parameter MEM_ADDRESS_WIDTH = 32; parameter NUM_BYTES = 32; parameter BURSTCOUNT_WIDTH = 1; parameter CRA_BITWIDTH = 32; localparam ADDRESS_SHIFT = $clog2(NUM_BYTES); localparam PAGE_ID_WIDTH = MEM_ADDRESS_WIDTH - PAGE_ADDRESS_WIDTH - ADDRESS_SHIFT; localparam DATA_WIDTH = NUM_BYTES * 8; input clk; input reset; // Memory slave port input [PAGE_ADDRESS_WIDTH-1:0] s1_address; input s1_read; output [DATA_WIDTH-1:0] s1_readdata; output s1_readdatavalid; input s1_write; input [DATA_WIDTH-1:0] s1_writedata; input [BURSTCOUNT_WIDTH-1:0] s1_burstcount; input [NUM_BYTES-1:0] s1_byteenable; output s1_waitrequest; // Bridged master port to memory output [MEM_ADDRESS_WIDTH-1:0] m1_address; output m1_read; input [DATA_WIDTH-1:0] m1_readdata; input m1_readdatavalid; output m1_write; output [DATA_WIDTH-1:0] m1_writedata; output [BURSTCOUNT_WIDTH-1:0] m1_burstcount; output [NUM_BYTES-1:0] m1_byteenable; input m1_waitrequest; // CRA slave input cra_write; input [CRA_BITWIDTH-1:0] cra_writedata; input [CRA_BITWIDTH/8-1:0] cra_byteenable; // Architecture // CRA slave allows the master to change the active page reg [PAGE_ID_WIDTH-1:0] page_id; reg [CRA_BITWIDTH-1:0] cra_writemask; integer i; always@* for (i=0; i<CRA_BITWIDTH; i=i+1) cra_writemask[i] = cra_byteenable[i/8] & cra_write; always@(posedge clk or posedge reset) begin if(reset == 1'b1) page_id <= {PAGE_ID_WIDTH{1'b0}}; else page_id <= (cra_writedata & cra_writemask) | (page_id & ~cra_writemask); end // The s1 port bridges to the m1 port - with the page ID tacked on to the address assign m1_address = {page_id, s1_address, {ADDRESS_SHIFT{1'b0}}}; assign m1_read = s1_read; assign s1_readdata = m1_readdata; assign s1_readdatavalid = m1_readdatavalid; assign m1_write = s1_write; assign m1_writedata = s1_writedata; assign m1_burstcount = s1_burstcount; assign m1_byteenable = s1_byteenable; assign s1_waitrequest = m1_waitrequest; endmodule
(** * Types: Type Systems *) Require Export Smallstep. Hint Constructors multi. (** Our next major topic is _type systems_ -- static program analyses that classify expressions according to the "shapes" of their results. We'll begin with a typed version of a very simple language with just booleans and numbers, to introduce the basic ideas of types, typing rules, and the fundamental theorems about type systems: _type preservation_ and _progress_. Then we'll move on to the _simply typed lambda-calculus_, which lives at the core of every modern functional programming language (including Coq). *) (* ###################################################################### *) (** * Typed Arithmetic Expressions *) (** To motivate the discussion of type systems, let's begin as usual with an extremely simple toy language. We want it to have the potential for programs "going wrong" because of runtime type errors, so we need something a tiny bit more complex than the language of constants and addition that we used in chapter [Smallstep]: a single kind of data (just numbers) is too simple, but just two kinds (numbers and booleans) already gives us enough material to tell an interesting story. The language definition is completely routine. *) (* ###################################################################### *) (** ** Syntax *) (** Informally: t ::= true | false | if t then t else t | 0 | succ t | pred t | iszero t Formally: *) Inductive tm : Type := | ttrue : tm | tfalse : tm | tif : tm -> tm -> tm -> tm | tzero : tm | tsucc : tm -> tm | tpred : tm -> tm | tiszero : tm -> tm. (** _Values_ are [true], [false], and numeric values... *) Inductive bvalue : tm -> Prop := | bv_true : bvalue ttrue | bv_false : bvalue tfalse. Inductive nvalue : tm -> Prop := | nv_zero : nvalue tzero | nv_succ : forall t, nvalue t -> nvalue (tsucc t). Definition value (t:tm) := bvalue t \/ nvalue t. Hint Constructors bvalue nvalue. Hint Unfold value. Hint Unfold extend. (* ###################################################################### *) (** ** Operational Semantics *) (** Informally: *) (** ------------------------------ (ST_IfTrue) if true then t1 else t2 ==> t1 ------------------------------- (ST_IfFalse) if false then t1 else t2 ==> t2 t1 ==> t1' ------------------------- (ST_If) if t1 then t2 else t3 ==> if t1' then t2 else t3 t1 ==> t1' -------------------- (ST_Succ) succ t1 ==> succ t1' ------------ (ST_PredZero) pred 0 ==> 0 numeric value v1 --------------------- (ST_PredSucc) pred (succ v1) ==> v1 t1 ==> t1' -------------------- (ST_Pred) pred t1 ==> pred t1' ----------------- (ST_IszeroZero) iszero 0 ==> true numeric value v1 -------------------------- (ST_IszeroSucc) iszero (succ v1) ==> false t1 ==> t1' ------------------------ (ST_Iszero) iszero t1 ==> iszero t1' *) (** Formally: *) Reserved Notation "t1 '==>' t2" (at level 40). Inductive step : tm -> tm -> Prop := | ST_IfTrue : forall t1 t2, (tif ttrue t1 t2) ==> t1 | ST_IfFalse : forall t1 t2, (tif tfalse t1 t2) ==> t2 | ST_If : forall t1 t1' t2 t3, t1 ==> t1' -> (tif t1 t2 t3) ==> (tif t1' t2 t3) | ST_Succ : forall t1 t1', t1 ==> t1' -> (tsucc t1) ==> (tsucc t1') | ST_PredZero : (tpred tzero) ==> tzero | ST_PredSucc : forall t1, nvalue t1 -> (tpred (tsucc t1)) ==> t1 | ST_Pred : forall t1 t1', t1 ==> t1' -> (tpred t1) ==> (tpred t1') | ST_IszeroZero : (tiszero tzero) ==> ttrue | ST_IszeroSucc : forall t1, nvalue t1 -> (tiszero (tsucc t1)) ==> tfalse | ST_Iszero : forall t1 t1', t1 ==> t1' -> (tiszero t1) ==> (tiszero t1') where "t1 '==>' t2" := (step t1 t2). Tactic Notation "step_cases" tactic(first) ident(c) := first; [ Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If" | Case_aux c "ST_Succ" | Case_aux c "ST_PredZero" | Case_aux c "ST_PredSucc" | Case_aux c "ST_Pred" | Case_aux c "ST_IszeroZero" | Case_aux c "ST_IszeroSucc" | Case_aux c "ST_Iszero" ]. Hint Constructors step. (** Notice that the [step] relation doesn't care about whether expressions make global sense -- it just checks that the operation in the _next_ reduction step is being applied to the right kinds of operands. For example, the term [succ true] (i.e., [tsucc ttrue] in the formal syntax) cannot take a step, but the almost as obviously nonsensical term succ (if true then true else true) can take a step (once, before becoming stuck). *) (* ###################################################################### *) (** ** Normal Forms and Values *) (** The first interesting thing about the [step] relation in this language is that the strong progress theorem from the Smallstep chapter fails! That is, there are terms that are normal forms (they can't take a step) but not values (because we have not included them in our definition of possible "results of evaluation"). Such terms are _stuck_. *) Notation step_normal_form := (normal_form step). Definition stuck (t:tm) : Prop := step_normal_form t /\ ~ value t. Hint Unfold stuck. (** **** Exercise: 2 stars (some_term_is_stuck) *) Example some_term_is_stuck : exists t, stuck t. Proof. (* FILL IN HERE *) Admitted. (** [] *) (** However, although values and normal forms are not the same in this language, the former set is included in the latter. This is important because it shows we did not accidentally define things so that some value could still take a step. *) (** **** Exercise: 3 stars, advanced (value_is_nf) *) (** Hint: You will reach a point in this proof where you need to use an induction to reason about a term that is known to be a numeric value. This induction can be performed either over the term itself or over the evidence that it is a numeric value. The proof goes through in either case, but you will find that one way is quite a bit shorter than the other. For the sake of the exercise, try to complete the proof both ways. *) Lemma value_is_nf : forall t, value t -> step_normal_form t. Proof. (* FILL IN HERE *) Admitted. (** [] *) (** **** Exercise: 3 stars, optional (step_deterministic) *) (** Using [value_is_nf], we can show that the [step] relation is also deterministic... *) Theorem step_deterministic: deterministic step. Proof with eauto. (* FILL IN HERE *) Admitted. (** [] *) (* ###################################################################### *) (** ** Typing *) (** The next critical observation about this language is that, although there are stuck terms, they are all "nonsensical", mixing booleans and numbers in a way that we don't even _want_ to have a meaning. We can easily exclude such ill-typed terms by defining a _typing relation_ that relates terms to the types (either numeric or boolean) of their final results. *) Inductive ty : Type := | TBool : ty | TNat : ty. (** In informal notation, the typing relation is often written [|- t \in T], pronounced "[t] has type [T]." The [|-] symbol is called a "turnstile". (Below, we're going to see richer typing relations where an additional "context" argument is written to the left of the turnstile. Here, the context is always empty.) *) (** ---------------- (T_True) |- true \in Bool ----------------- (T_False) |- false \in Bool |- t1 \in Bool |- t2 \in T |- t3 \in T -------------------------------------------- (T_If) |- if t1 then t2 else t3 \in T ------------ (T_Zero) |- 0 \in Nat |- t1 \in Nat ------------------ (T_Succ) |- succ t1 \in Nat |- t1 \in Nat ------------------ (T_Pred) |- pred t1 \in Nat |- t1 \in Nat --------------------- (T_IsZero) |- iszero t1 \in Bool *) Reserved Notation "'|-' t '\in' T" (at level 40). Inductive has_type : tm -> ty -> Prop := | T_True : |- ttrue \in TBool | T_False : |- tfalse \in TBool | T_If : forall t1 t2 t3 T, |- t1 \in TBool -> |- t2 \in T -> |- t3 \in T -> |- tif t1 t2 t3 \in T | T_Zero : |- tzero \in TNat | T_Succ : forall t1, |- t1 \in TNat -> |- tsucc t1 \in TNat | T_Pred : forall t1, |- t1 \in TNat -> |- tpred t1 \in TNat | T_Iszero : forall t1, |- t1 \in TNat -> |- tiszero t1 \in TBool where "'|-' t '\in' T" := (has_type t T). Tactic Notation "has_type_cases" tactic(first) ident(c) := first; [ Case_aux c "T_True" | Case_aux c "T_False" | Case_aux c "T_If" | Case_aux c "T_Zero" | Case_aux c "T_Succ" | Case_aux c "T_Pred" | Case_aux c "T_Iszero" ]. Hint Constructors has_type. (* ###################################################################### *) (** *** Examples *) (** It's important to realize that the typing relation is a _conservative_ (or _static_) approximation: it does not calculate the type of the normal form of a term. *) Example has_type_1 : |- tif tfalse tzero (tsucc tzero) \in TNat. Proof. apply T_If. apply T_False. apply T_Zero. apply T_Succ. apply T_Zero. Qed. (** (Since we've included all the constructors of the typing relation in the hint database, the [auto] tactic can actually find this proof automatically.) *) Example has_type_not : ~ (|- tif tfalse tzero ttrue \in TBool). Proof. intros Contra. solve by inversion 2. Qed. (** **** Exercise: 1 star, optional (succ_hastype_nat__hastype_nat) *) Example succ_hastype_nat__hastype_nat : forall t, |- tsucc t \in TNat -> |- t \in TNat. Proof. (* FILL IN HERE *) Admitted. (** [] *) (* ###################################################################### *) (** ** Canonical forms *) (** The following two lemmas capture the basic property that defines the shape of well-typed values. They say that the definition of value and the typing relation agree. *) Lemma bool_canonical : forall t, |- t \in TBool -> value t -> bvalue t. Proof. intros t HT HV. inversion HV; auto. induction H; inversion HT; auto. Qed. Lemma nat_canonical : forall t, |- t \in TNat -> value t -> nvalue t. Proof. intros t HT HV. inversion HV. inversion H; subst; inversion HT. auto. Qed. (* ###################################################################### *) (** ** Progress *) (** The typing relation enjoys two critical properties. The first is that well-typed normal forms are values (i.e., not stuck). *) Theorem progress : forall t T, |- t \in T -> value t \/ exists t', t ==> t'. (** **** Exercise: 3 stars (finish_progress) *) (** Complete the formal proof of the [progress] property. (Make sure you understand the informal proof fragment in the following exercise before starting -- this will save you a lot of time.) *) Proof with auto. intros t T HT. has_type_cases (induction HT) Case... (* The cases that were obviously values, like T_True and T_False, were eliminated immediately by auto *) Case "T_If". right. inversion IHHT1; clear IHHT1. SCase "t1 is a value". apply (bool_canonical t1 HT1) in H. inversion H; subst; clear H. exists t2... exists t3... SCase "t1 can take a step". inversion H as [t1' H1]. exists (tif t1' t2 t3)... (* FILL IN HERE *) Admitted. (** [] *) (** **** Exercise: 3 stars, advanced (finish_progress_informal) *) (** Complete the corresponding informal proof: *) (** _Theorem_: If [|- t \in T], then either [t] is a value or else [t ==> t'] for some [t']. *) (** _Proof_: By induction on a derivation of [|- t \in T]. - If the last rule in the derivation is [T_If], then [t = if t1 then t2 else t3], with [|- t1 \in Bool], [|- t2 \in T] and [|- t3 \in T]. By the IH, either [t1] is a value or else [t1] can step to some [t1']. - If [t1] is a value, then by the canonical forms lemmas and the fact that [|- t1 \in Bool] we have that [t1] is a [bvalue] -- i.e., it is either [true] or [false]. If [t1 = true], then [t] steps to [t2] by [ST_IfTrue], while if [t1 = false], then [t] steps to [t3] by [ST_IfFalse]. Either way, [t] can step, which is what we wanted to show. - If [t1] itself can take a step, then, by [ST_If], so can [t]. (* FILL IN HERE *) [] *) (** This is more interesting than the strong progress theorem that we saw in the Smallstep chapter, where _all_ normal forms were values. Here, a term can be stuck, but only if it is ill typed. *) (** **** Exercise: 1 star (step_review) *) (** Quick review. Answer _true_ or _false_. In this language... - Every well-typed normal form is a value. - Every value is a normal form. - The single-step evaluation relation is a partial function (i.e., it is deterministic). - The single-step evaluation relation is a _total_ function. *) (** [] *) (* ###################################################################### *) (** ** Type Preservation *) (** The second critical property of typing is that, when a well-typed term takes a step, the result is also a well-typed term. This theorem is often called the _subject reduction_ property, because it tells us what happens when the "subject" of the typing relation is reduced. This terminology comes from thinking of typing statements as sentences, where the term is the subject and the type is the predicate. *) Theorem preservation : forall t t' T, |- t \in T -> t ==> t' -> |- t' \in T. (** **** Exercise: 2 stars (finish_preservation) *) (** Complete the formal proof of the [preservation] property. (Again, make sure you understand the informal proof fragment in the following exercise first.) *) Proof with auto. intros t t' T HT HE. generalize dependent t'. has_type_cases (induction HT) Case; (* every case needs to introduce a couple of things *) intros t' HE; (* and we can deal with several impossible cases all at once *) try (solve by inversion). Case "T_If". inversion HE; subst; clear HE. SCase "ST_IFTrue". assumption. SCase "ST_IfFalse". assumption. SCase "ST_If". apply T_If; try assumption. apply IHHT1; assumption. (* FILL IN HERE *) Admitted. (** [] *) (** **** Exercise: 3 stars, advanced (finish_preservation_informal) *) (** Complete the following proof: *) (** _Theorem_: If [|- t \in T] and [t ==> t'], then [|- t' \in T]. *) (** _Proof_: By induction on a derivation of [|- t \in T]. - If the last rule in the derivation is [T_If], then [t = if t1 then t2 else t3], with [|- t1 \in Bool], [|- t2 \in T] and [|- t3 \in T]. Inspecting the rules for the small-step reduction relation and remembering that [t] has the form [if ...], we see that the only ones that could have been used to prove [t ==> t'] are [ST_IfTrue], [ST_IfFalse], or [ST_If]. - If the last rule was [ST_IfTrue], then [t' = t2]. But we know that [|- t2 \in T], so we are done. - If the last rule was [ST_IfFalse], then [t' = t3]. But we know that [|- t3 \in T], so we are done. - If the last rule was [ST_If], then [t' = if t1' then t2 else t3], where [t1 ==> t1']. We know [|- t1 \in Bool] so, by the IH, [|- t1' \in Bool]. The [T_If] rule then gives us [|- if t1' then t2 else t3 \in T], as required. (* FILL IN HERE *) [] *) (** **** Exercise: 3 stars (preservation_alternate_proof) *) (** Now prove the same property again by induction on the _evaluation_ derivation instead of on the typing derivation. Begin by carefully reading and thinking about the first few lines of the above proof to make sure you understand what each one is doing. The set-up for this proof is similar, but not exactly the same. *) Theorem preservation' : forall t t' T, |- t \in T -> t ==> t' -> |- t' \in T. Proof with eauto. (* FILL IN HERE *) Admitted. (** [] *) (* ###################################################################### *) (** ** Type Soundness *) (** Putting progress and preservation together, we can see that a well-typed term can _never_ reach a stuck state. *) Definition multistep := (multi step). Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40). Corollary soundness : forall t t' T, |- t \in T -> t ==>* t' -> ~(stuck t'). Proof. intros t t' T HT P. induction P; intros [R S]. destruct (progress x T HT); auto. apply IHP. apply (preservation x y T HT H). unfold stuck. split; auto. Qed. (* ###################################################################### *) (** * Aside: the [normalize] Tactic *) (** When experimenting with definitions of programming languages in Coq, we often want to see what a particular concrete term steps to -- i.e., we want to find proofs for goals of the form [t ==>* t'], where [t] is a completely concrete term and [t'] is unknown. These proofs are simple but repetitive to do by hand. Consider for example reducing an arithmetic expression using the small-step relation [astep]. *) Definition amultistep st := multi (astep st). Notation " t '/' st '==>a*' t' " := (amultistep st t t') (at level 40, st at level 39). Example astep_example1 : (APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state ==>a* (ANum 15). Proof. apply multi_step with (APlus (ANum 3) (ANum 12)). apply AS_Plus2. apply av_num. apply AS_Mult. apply multi_step with (ANum 15). apply AS_Plus. apply multi_refl. Qed. (** We repeatedly apply [multi_step] until we get to a normal form. The proofs that the intermediate steps are possible are simple enough that [auto], with appropriate hints, can solve them. *) Hint Constructors astep aval. Example astep_example1' : (APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state ==>a* (ANum 15). Proof. eapply multi_step. auto. simpl. eapply multi_step. auto. simpl. apply multi_refl. Qed. (** The following custom [Tactic Notation] definition captures this pattern. In addition, before each [multi_step] we print out the current goal, so that the user can follow how the term is being evaluated. *) Tactic Notation "print_goal" := match goal with |- ?x => idtac x end. Tactic Notation "normalize" := repeat (print_goal; eapply multi_step ; [ (eauto 10; fail) | (instantiate; simpl)]); apply multi_refl. Example astep_example1'' : (APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state ==>a* (ANum 15). Proof. normalize. (* At this point in the proof script, the Coq response shows a trace of how the expression evaluated. (APlus (ANum 3) (AMult (ANum 3) (ANum 4)) / empty_state ==>a* ANum 15) (multi (astep empty_state) (APlus (ANum 3) (ANum 12)) (ANum 15)) (multi (astep empty_state) (ANum 15) (ANum 15)) *) Qed. (** The [normalize] tactic also provides a simple way to calculate what the normal form of a term is, by proving a goal with an existential variable in it. *) Example astep_example1''' : exists e', (APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state ==>a* e'. Proof. eapply ex_intro. normalize. (* This time, the trace will be: (APlus (ANum 3) (AMult (ANum 3) (ANum 4)) / empty_state ==>a* ??) (multi (astep empty_state) (APlus (ANum 3) (ANum 12)) ??) (multi (astep empty_state) (ANum 15) ??) where ?? is the variable ``guessed'' by eapply. *) Qed. (** **** Exercise: 1 star (normalize_ex) *) Theorem normalize_ex : exists e', (AMult (ANum 3) (AMult (ANum 2) (ANum 1))) / empty_state ==>a* e'. Proof. (* FILL IN HERE *) Admitted. (** [] *) (** **** Exercise: 1 star, optional (normalize_ex') *) (** For comparison, prove it using [apply] instead of [eapply]. *) Theorem normalize_ex' : exists e', (AMult (ANum 3) (AMult (ANum 2) (ANum 1))) / empty_state ==>a* e'. Proof. (* FILL IN HERE *) Admitted. (** [] *) (* ###################################################################### *) (** ** Additional Exercises *) (** **** Exercise: 2 stars (subject_expansion) *) (** Having seen the subject reduction property, it is reasonable to wonder whether the opposity property -- subject _expansion_ -- also holds. That is, is it always the case that, if [t ==> t'] and [|- t' \in T], then [|- t \in T]? If so, prove it. If not, give a counter-example. (You do not need to prove your counter-example in Coq, but feel free to do so if you like.) (* FILL IN HERE *) [] *) (** **** Exercise: 2 stars (variation1) *) (** Suppose, that we add this new rule to the typing relation: | T_SuccBool : forall t, |- t \in TBool -> |- tsucc t \in TBool Which of the following properties remain true in the presence of this rule? For each one, write either "remains true" or else "becomes false." If a property becomes false, give a counterexample. - Determinism of [step] - Progress - Preservation [] *) (** **** Exercise: 2 stars (variation2) *) (** Suppose, instead, that we add this new rule to the [step] relation: | ST_Funny1 : forall t2 t3, (tif ttrue t2 t3) ==> t3 Which of the above properties become false in the presence of this rule? For each one that does, give a counter-example. [] *) (** **** Exercise: 2 stars, optional (variation3) *) (** Suppose instead that we add this rule: | ST_Funny2 : forall t1 t2 t2' t3, t2 ==> t2' -> (tif t1 t2 t3) ==> (tif t1 t2' t3) Which of the above properties become false in the presence of this rule? For each one that does, give a counter-example. [] *) (** **** Exercise: 2 stars, optional (variation4) *) (** Suppose instead that we add this rule: | ST_Funny3 : (tpred tfalse) ==> (tpred (tpred tfalse)) Which of the above properties become false in the presence of this rule? For each one that does, give a counter-example. [] *) (** **** Exercise: 2 stars, optional (variation5) *) (** Suppose instead that we add this rule: | T_Funny4 : |- tzero \in TBool ]] Which of the above properties become false in the presence of this rule? For each one that does, give a counter-example. [] *) (** **** Exercise: 2 stars, optional (variation6) *) (** Suppose instead that we add this rule: | T_Funny5 : |- tpred tzero \in TBool ]] Which of the above properties become false in the presence of this rule? For each one that does, give a counter-example. [] *) (** **** Exercise: 3 stars, optional (more_variations) *) (** Make up some exercises of your own along the same lines as the ones above. Try to find ways of selectively breaking properties -- i.e., ways of changing the definitions that break just one of the properties and leave the others alone. [] *) (** **** Exercise: 1 star (remove_predzero) *) (** The evaluation rule [E_PredZero] is a bit counter-intuitive: we might feel that it makes more sense for the predecessor of zero to be undefined, rather than being defined to be zero. Can we achieve this simply by removing the rule from the definition of [step]? Would doing so create any problems elsewhere? (* FILL IN HERE *) [] *) (** **** Exercise: 4 stars, advanced (prog_pres_bigstep) *) (** Suppose our evaluation relation is defined in the big-step style. What are the appropriate analogs of the progress and preservation properties? (* FILL IN HERE *) [] *) (** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ecc_dec_fix.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_ecc_dec_fix #( parameter TCQ = 100, parameter PAYLOAD_WIDTH = 64, parameter CODE_WIDTH = 72, parameter DATA_WIDTH = 64, parameter DQ_WIDTH = 72, parameter ECC_WIDTH = 8, parameter nCK_PER_CLK = 4 ) ( /*AUTOARG*/ // Outputs rd_data, ecc_single, ecc_multiple, // Inputs clk, rst, h_rows, phy_rddata, correct_en, ecc_status_valid ); input clk; input rst; // Compute syndromes. input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows; input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata; wire [2*nCK_PER_CLK*ECC_WIDTH-1:0] syndrome_ns; genvar k; genvar m; generate for (k=0; k<2*nCK_PER_CLK; k=k+1) begin : ecc_word for (m=0; m<ECC_WIDTH; m=m+1) begin : ecc_bit assign syndrome_ns[k*ECC_WIDTH+m] = ^(phy_rddata[k*DQ_WIDTH+:CODE_WIDTH] & h_rows[m*CODE_WIDTH+:CODE_WIDTH]); end end endgenerate reg [2*nCK_PER_CLK*ECC_WIDTH-1:0] syndrome_r; always @(posedge clk) syndrome_r <= #TCQ syndrome_ns; // Extract payload bits from raw DRAM bits and register. wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] ecc_rddata_ns; genvar i; generate for (i=0; i<2*nCK_PER_CLK; i=i+1) begin : extract_payload assign ecc_rddata_ns[i*PAYLOAD_WIDTH+:PAYLOAD_WIDTH] = phy_rddata[i*DQ_WIDTH+:PAYLOAD_WIDTH]; end endgenerate reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] ecc_rddata_r; always @(posedge clk) ecc_rddata_r <= #TCQ ecc_rddata_ns; // Regenerate h_matrix from h_rows leaving out the identity part // since we're not going to correct the ECC bits themselves. genvar n; genvar p; wire [ECC_WIDTH-1:0] h_matrix [DATA_WIDTH-1:0]; generate for (n=0; n<DATA_WIDTH; n=n+1) begin : h_col for (p=0; p<ECC_WIDTH; p=p+1) begin : h_bit assign h_matrix [n][p] = h_rows [p*CODE_WIDTH+n]; end end endgenerate // Compute flip bits. wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] flip_bits; genvar q; genvar r; generate for (q=0; q<2*nCK_PER_CLK; q=q+1) begin : flip_word for (r=0; r<DATA_WIDTH; r=r+1) begin : flip_bit assign flip_bits[q*DATA_WIDTH+r] = h_matrix[r] == syndrome_r[q*ECC_WIDTH+:ECC_WIDTH]; end end endgenerate // Correct data. output reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data; input correct_en; integer s; always @(/*AS*/correct_en or ecc_rddata_r or flip_bits) for (s=0; s<2*nCK_PER_CLK; s=s+1) if (correct_en) rd_data[s*PAYLOAD_WIDTH+:DATA_WIDTH] = ecc_rddata_r[s*PAYLOAD_WIDTH+:DATA_WIDTH] ^ flip_bits[s*DATA_WIDTH+:DATA_WIDTH]; else rd_data[s*PAYLOAD_WIDTH+:DATA_WIDTH] = ecc_rddata_r[s*PAYLOAD_WIDTH+:DATA_WIDTH]; // Copy raw payload bits if ECC_TEST is ON. localparam RAW_BIT_WIDTH = PAYLOAD_WIDTH - DATA_WIDTH; genvar t; generate if (RAW_BIT_WIDTH > 0) for (t=0; t<2*nCK_PER_CLK; t=t+1) begin : copy_raw_bits always @(/*AS*/ecc_rddata_r) rd_data[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH] = ecc_rddata_r[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH]; end endgenerate // Generate status information. input ecc_status_valid; output wire [2*nCK_PER_CLK-1:0] ecc_single; output wire [2*nCK_PER_CLK-1:0] ecc_multiple; genvar v; generate for (v=0; v<2*nCK_PER_CLK; v=v+1) begin : compute_status wire zero = ~|syndrome_r[v*ECC_WIDTH+:ECC_WIDTH]; wire odd = ^syndrome_r[v*ECC_WIDTH+:ECC_WIDTH]; assign ecc_single[v] = ecc_status_valid && ~zero && odd; assign ecc_multiple[v] = ecc_status_valid && ~zero && ~odd; end endgenerate endmodule
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HS__DFSBP_PP_BLACKBOX_V `define SKY130_FD_SC_HS__DFSBP_PP_BLACKBOX_V /** * dfsbp: Delay flop, inverted set, complementary outputs. * * Verilog stub definition (black box with power pins). * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_hs__dfsbp ( CLK , D , Q , Q_N , SET_B, VPWR , VGND ); input CLK ; input D ; output Q ; output Q_N ; input SET_B; input VPWR ; input VGND ; endmodule `default_nettype wire `endif // SKY130_FD_SC_HS__DFSBP_PP_BLACKBOX_V
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_LP__DLYBUF4S50KAPWR_PP_SYMBOL_V `define SKY130_FD_SC_LP__DLYBUF4S50KAPWR_PP_SYMBOL_V /** * dlybuf4s50kapwr: Delay Buffer 4-stage 0.50um length inner stage * gates on keep-alive power rail. * * Verilog stub (with power pins) for graphical symbol definition * generation. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_lp__dlybuf4s50kapwr ( //# {{data|Data Signals}} input A , output X , //# {{power|Power}} input KAPWR, input VPB , input VPWR , input VGND , input VNB ); endmodule `default_nettype wire `endif // SKY130_FD_SC_LP__DLYBUF4S50KAPWR_PP_SYMBOL_V
// (C) 2001-2016 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL // THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING // FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS // IN THIS FILE. /****************************************************************************** * * * This module is a FIFO with same clock for both reads and writes. * * * ******************************************************************************/ module altera_up_sync_fifo ( // Inputs clk, reset, write_en, write_data, read_en, // Bidirectionals // Outputs fifo_is_empty, fifo_is_full, words_used, read_data ); /***************************************************************************** * Parameter Declarations * *****************************************************************************/ parameter DW = 31; // Data width parameter DATA_DEPTH = 128; parameter AW = 6; // Address width /***************************************************************************** * Port Declarations * *****************************************************************************/ // Inputs input clk; input reset; input write_en; input [DW: 0] write_data; input read_en; // Bidirectionals // Outputs output fifo_is_empty; output fifo_is_full; output [AW: 0] words_used; output [DW: 0] read_data; /***************************************************************************** * Constant Declarations * *****************************************************************************/ /***************************************************************************** * Internal Wires and Registers Declarations * *****************************************************************************/ // Internal Wires // Internal Registers // State Machine Registers /***************************************************************************** * Finite State Machine(s) * *****************************************************************************/ /***************************************************************************** * Sequential Logic * *****************************************************************************/ /***************************************************************************** * Combinational Logic * *****************************************************************************/ /***************************************************************************** * Internal Modules * *****************************************************************************/ scfifo Sync_FIFO ( // Inputs .clock (clk), .sclr (reset), .data (write_data), .wrreq (write_en), .rdreq (read_en), // Bidirectionals // Outputs .empty (fifo_is_empty), .full (fifo_is_full), .usedw (words_used), .q (read_data), // Unused // synopsys translate_off .aclr (), .almost_empty (), .almost_full () // synopsys translate_on ); defparam Sync_FIFO.add_ram_output_register = "OFF", Sync_FIFO.intended_device_family = "Cyclone II", Sync_FIFO.lpm_numwords = DATA_DEPTH, Sync_FIFO.lpm_showahead = "ON", Sync_FIFO.lpm_type = "scfifo", Sync_FIFO.lpm_width = DW + 1, Sync_FIFO.lpm_widthu = AW + 1, Sync_FIFO.overflow_checking = "OFF", Sync_FIFO.underflow_checking = "OFF", Sync_FIFO.use_eab = "ON"; endmodule
/* * Titor - System - PS/2 controller wrapper * Copyright (C) 2012,2013 Sean Ryan Moore * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ `ifdef INC_PS2_WRAPPER `else `define INC_PS2_WRAPPER `timescale 1 ns / 100 ps module PS2( ps2_clock, ps2_data, rx_data, rx_done, reset, clk ); `include "definition/Definition.v" inout ps2_clock; inout ps2_data; output reg [BYTE-1:0] rx_data; output reg rx_done; input reset; input clk; localparam BITTHROUGH = 10; // the number of bits to accept including Parity and Stop localparam STATE_IDLE = 32'd1, STATE_RX_BIT = 32'd2; wire devclk; wire devclkneg; wire [WORD-1:0] bitcount; wire bitarc; reg [WORD-1:0] state; reg [BITTHROUGH-1:0] shift_in; reg postbitarc; reg [BYTE-1:0] clkbuf; // Clock line conditioning Debounce #(1*MICROS) stable ( .linein(ps2_clock), .lineout(devclk), .reset(reset), .clk(clk) ); Negedge tick ( .linein(devclk), .lineout(devclkneg), .reset(reset), .clk(clk) ); // Bit counting Radix_Counter #(BITTHROUGH) countoff ( .carry_in((state==STATE_RX_BIT) && devclkneg), .carry_out(bitarc), .count(bitcount), .reset(reset), .clk(clk) ); // Finite State Machine always @(posedge clk) begin if(reset) state <= STATE_IDLE; else if((state==STATE_IDLE) && devclkneg) state <= STATE_RX_BIT; else if((state==STATE_RX_BIT) && bitarc) state <= STATE_IDLE; else state <= state; end // Data capture always @(posedge clk) begin if(reset) shift_in <= 0; else if(devclkneg) shift_in <= {ps2_data, shift_in[BITTHROUGH-1:1]}; else shift_in <= shift_in; if(reset) postbitarc <= 0; else postbitarc <= bitarc; if(reset) rx_data <= 0; else if(postbitarc) rx_data <= shift_in; else rx_data <= rx_data; end always @(posedge clk) begin if(reset) rx_done <= 0; else if(postbitarc) rx_done <= 1; else rx_done <= 0; end endmodule `endif
/* * Copyright (c) 2002 Stephen Williams ([email protected]) * * This source code is free software; you can redistribute it * and/or modify it in source code form under the terms of the GNU * General Public License as published by the Free Software * Foundation; either version 2 of the License, or (at your option) * any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ module main; reg a; reg b; wire q = a & b; initial begin a = 1; b = 0; #1; if (q !== 0) begin $display("FAILED -- q did not start out right: %b", q); $finish; end b = 1; if (q !== 0) begin // Since b takes the new value with a blocking assignment, // it is up to the & gate to schedule the q change, and not // actually push the change through. $display("FAILED -- q changed too soon? %b", q); $finish; end if (b !== 1) begin $display("FAILED -- b value did not stick: %b", b); $finish; end // The #0 delay lets the scheduler execute the change to the // q value, so that we can read the correct value out. #0 if (q !== 1) begin $display("FAILED -- q did not change when it should: %b", q); $finish; end $display("PASSED"); end // initial begin endmodule // main
// Icarus 0.7, cvs files from Feb 2, 2003 // -------------------------------------- // // iverilog precision.v // or // iverilog -D DUMP precision.v // vvp a.out // // Use & display of real time periods with `timescale set to 1 ns / 10 ps // // $simtime keeps time in 10ps increments // $simtime cannot be displayed (yet) // $simtime can be used in comparisons -- compared to times in 10 ps units // $time should be $simtime-rounded-to-ns // $time displays according to `timescale and $timeformat // $time can be used in comparisons -- compared to times in 1 ns units // // Assuming that the simulation runs on units of 10ps, a clock which is set to // change value every (15.2 ns)/2 should change every 7.6 ns, i.e. 760*10ps. // // The dumpfile shows a timescale of 10ps; therefore, it should show the clock // changing every 760*10ps. It doesn't. The clock is changing every 700*10ps. // The checks on the clock using $simtime below verify that the dumpfile is // seeing what the simulation is, in fact, doing. // `timescale 1 ns / 10 ps `define PERIODI 15 `define PERIODR 15.2 module top; reg tick,clk, fail; reg [31:0] ii; `ifdef DUMP initial begin $dumpvars; end `endif initial begin $timeformat(-9, 2, "ns", 20); $display("integer & real periods: 'd%0d 'd%0d",`PERIODI,`PERIODR); $display("integer & real periods (15.00, 15.20): 't%0t 't%0t",`PERIODI,`PERIODR); $display("......... %s should be displayed as 15.20 in its timeformat.", ``PERIODR); $display("integer & real periods: 'b%0b 'b%0b",`PERIODI,`PERIODR); $display("integer & real periods: 'h%0h 'h%0h",`PERIODI,`PERIODR); clk = 0; tick = 0; fail = 0; #1; if($time === 1) $display("\t$time is in ns"); if($time === 100) $display("\t$time is in 10 ps"); $display("\ttime (1, 1h): 'd%0d, 't%0t, 'h%0h",$time,$time,$time); if($simtime === 1) $display("\t$simtime is in ns"); if($simtime === 100) $display("\t$simtime is in 10 ps"); $display("\tsimtime (100, 64h): 'd%0d, 't%0t, 'h%0h",$simtime,$simtime,$simtime); #(`PERIODI - 1); tick = 1; if($time !== 15) begin fail = 1;$display("time (15, Fh): 'd%0d, 't%0t, 'h%0h",$time,$time,$time); end if($simtime !== 1500) begin fail=1; $display("simtime not 1500"); end #(`PERIODR); tick = 0; if($time !== 30) begin fail = 1; $display("time (30, 1Eh): 'd%0d, 't%0t, 'h%0h",$time,$time,$time); end if($simtime !== 3020) begin fail=1; $display("simtime not 3020"); end #(`PERIODR); tick = 1; if($time !== 45) begin fail = 1; $display("time (45, 2Dh): 'd%0d, 't%0t, 'h%0h",$time,$time,$time); end if($simtime !== 4540) begin fail=1; $display("simtime not 4540"); end #(`PERIODR); tick = 0; if($time !== 61) begin fail = 1; $display("time (61, 3Dh): 'd%0d, 't%0t, 'h%0h",$time,$time,$time); end if($simtime !== 6060) begin fail=1; $display("simtime not 6060"); end #(`PERIODR); tick = 1; if($time !== 76) begin fail = 1; $display("time (76, 4Ch): 'd%0d, 't%0t, 'h%0h",$time,$time,$time); end if($simtime !== 7580) begin fail=1; $display("simtime not 7580"); end #(`PERIODR); tick = 1; if($time !== 91) begin fail = 1; $display("time (91, 5Bh): 'd%0d, 't%0t, 'h%0h",$time,$time,$time); end if($simtime !== 9100) begin fail=1; $display("simtime not 9100"); end $display("\t\t**********************************************"); if(fail) $display("\t\t****** time precision test FAILED *******"); else $display("\t\t****** time precision test PASSED *******"); $display("\t\t**********************************************\n"); $finish; end initial begin for(ii = 0; ii < 1524; ii = ii + 1) begin #(0.01); if(($simtime == 659) && (clk !== 0)) begin fail=1; $display("time: 659, clk wrong"); end if(($simtime == 701) && (clk !== 0)) begin fail=1; $display("time: 701, clk wrong"); end if(($simtime == 759) && (clk !== 0)) begin fail=1; $display("time: 759, clk wrong"); end if(($simtime == 761) && (clk !== 1)) begin fail=1; $display("time: 761, clk wrong"); end if(($simtime == 1399) && (clk !== 1)) begin fail=1; $display("time: 1399, clk wrong"); end if(($simtime == 1401) && (clk !== 1)) begin fail=1; $display("time: 1401, clk wrong"); end if(($simtime == 1519) && (clk !== 1)) begin fail=1; $display("time: 1519, clk wrong"); end if(($simtime == 1521) && (clk !== 0)) begin fail=1; $display("time: 1521, clk wrong"); end end end always begin #(`PERIODR/2) clk <= ~clk; // clock should change as follows: // T (10ps) : clk // 0 : 0 // 760 : 1 // 1520 : 0 // 2280 : 1 // 3040 : 0 // etc. end endmodule
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your //use of Altera Corporation's design tools, logic functions and other //software and tools, and its AMPP partner logic functions, and any //output files any of the foregoing (including device programming or //simulation files), and any associated documentation or information are //expressly subject to the terms and conditions of the Altera Program //License Subscription Agreement or other applicable license agreement, //including, without limitation, that your use is for the sole purpose //of programming logic devices manufactured by Altera and sold by Altera //or its authorized distributors. Please refer to the applicable //agreement for further details. /////////////////////////////////////////////////////////////////////////////// // Title : DDR controller Avalon Interface // // File : alt_ddrx_avalon_if.v // // Abstract : Avalon interface /////////////////////////////////////////////////////////////////////////////// `timescale 1 ps / 1 ps module alt_ddrx_avalon_if #(parameter INTERNAL_SIZE_WIDTH = 7, LOCAL_SIZE_WIDTH = 6, CTL_HRB_ENABLED = 0, LOCAL_ADDR_WIDTH = 28, INTERNAL_ADDR_WIDTH = 33, DWIDTH_RATIO = 2, LOCAL_DATA_WIDTH = 64, INTERNAL_DATA_WIDTH = 32 ) ( // input ctl_clk, ctl_reset_n, ctl_half_clk , ctl_half_clk_reset_n , local_write_req, local_wdata, local_be, local_addr, internal_ready, local_read_req, local_size, local_burstbegin, ecc_rdata, ecc_rdata_valid, ecc_rdata_error, local_multicast, local_autopch_req, //output avalon_wdata, avalon_be, avalon_addr, avalon_write_req, avalon_read_req, avalon_size, avalon_burstbegin, local_ready, local_rdata, local_rdata_error, local_rdata_valid, avalon_multicast, avalon_autopch_req ); localparam LOCAL_BE_WIDTH = LOCAL_DATA_WIDTH/8; localparam INTERNAL_BE_WIDTH = INTERNAL_DATA_WIDTH/8; localparam AVM_ADDR_WIDTH = LOCAL_ADDR_WIDTH + log2(LOCAL_BE_WIDTH); input ctl_clk; input ctl_reset_n; input ctl_half_clk; input ctl_half_clk_reset_n; input local_write_req; input [LOCAL_DATA_WIDTH -1 : 0] local_wdata; input [LOCAL_BE_WIDTH -1 : 0] local_be; input [LOCAL_ADDR_WIDTH -1 : 0] local_addr; input internal_ready; input local_read_req; input [INTERNAL_DATA_WIDTH -1 : 0] ecc_rdata; input [DWIDTH_RATIO/2-1:0] ecc_rdata_valid; input ecc_rdata_error; input [LOCAL_SIZE_WIDTH-1:0] local_size; input local_burstbegin; input local_multicast; input local_autopch_req; output [INTERNAL_DATA_WIDTH -1 : 0] avalon_wdata; output [INTERNAL_BE_WIDTH -1 : 0] avalon_be; output [INTERNAL_ADDR_WIDTH - 1 : 0]avalon_addr; output avalon_write_req; output avalon_read_req; output [INTERNAL_SIZE_WIDTH-1:0] avalon_size; output avalon_burstbegin; output local_ready; output [LOCAL_DATA_WIDTH -1 : 0] local_rdata; output local_rdata_valid; output local_rdata_error; output avalon_multicast; output avalon_autopch_req; generate if (CTL_HRB_ENABLED == 1) begin wire avs_chipselect; wire [LOCAL_DATA_WIDTH -1 : 0] avs_readdata; wire [LOCAL_DATA_WIDTH -1 : 0] avs_writedata; wire avs_waitrequest; wire avm_write; wire avm_read; wire [AVM_ADDR_WIDTH - 1 : 0] avm_address; reg [LOCAL_ADDR_WIDTH -1 : 0] avs_address; reg [2:0] state; reg [INTERNAL_SIZE_WIDTH-1 : 0] burstcount; reg [INTERNAL_SIZE_WIDTH-1:0] internal_size; reg [INTERNAL_SIZE_WIDTH-1:0] internal_size_r; reg [INTERNAL_SIZE_WIDTH-1:0] avalon_avm_size; wire [2:0] avalon_avm_count; reg [2:0] avalon_avm_count_r; reg avalon_avs_toggle; reg avalon_avm_toggle; reg avalon_avm_toggle_r; wire avalon_avs_clk_ph; reg internal_multicast; reg internal_multicast_r; reg internal_autopch; reg internal_autopch_r; reg avalon_avm_multicast; reg avalon_avm_autopch; assign local_ready = !avs_waitrequest; assign avalon_write_req = avm_write & internal_ready; assign avalon_read_req = avm_read & internal_ready; assign avalon_addr = {avm_address[AVM_ADDR_WIDTH - 1 : log2(LOCAL_BE_WIDTH)],1'b0}; assign avs_chipselect = local_read_req|local_write_req; //burst adaptor logic assign avalon_burstbegin = (burstcount == 0); assign avalon_size = avalon_avm_size; assign avalon_multicast = avalon_avm_multicast; assign avalon_autopch_req = avalon_avm_autopch; assign avalon_avs_clk_ph = avalon_avm_toggle ^ avalon_avm_toggle_r; always @(posedge ctl_half_clk or negedge ctl_reset_n) if (~ctl_reset_n) avalon_avs_toggle <= 1'b0; else avalon_avs_toggle <= ~avalon_avs_toggle; always @(posedge ctl_clk or negedge ctl_reset_n) if (~ctl_reset_n) begin avalon_avm_toggle <= 1'b0; avalon_avm_toggle_r <= 1'b0; end else begin avalon_avm_toggle <= avalon_avs_toggle; avalon_avm_toggle_r <= avalon_avm_toggle; end always @(avalon_avm_count_r,internal_size,internal_multicast,internal_autopch,internal_size_r,internal_multicast_r,internal_autopch_r) begin if(avalon_avm_count_r >=3) begin avalon_avm_size <= internal_size_r; avalon_avm_multicast <= internal_multicast_r; avalon_avm_autopch <= internal_autopch_r; end else begin avalon_avm_size <= internal_size; avalon_avm_multicast <= internal_multicast; avalon_avm_autopch <= internal_autopch; end end assign avalon_avm_count = avalon_avm_count_r + (((local_write_req | local_read_req) & local_ready & avalon_avs_clk_ph) ? 3'd2 : 3'd0) - (avalon_write_req ? 3'd1 : 3'd0) - (avalon_read_req ? 3'd2 : 3'd0); always @(posedge ctl_clk or negedge ctl_reset_n) begin if (!ctl_reset_n) begin avalon_avm_count_r <= 0; end else begin avalon_avm_count_r <= avalon_avm_count; end end always @(posedge ctl_half_clk or negedge ctl_reset_n) begin if (!ctl_reset_n) begin internal_size <= 0; internal_size_r <= 0; internal_multicast <= 0; internal_multicast_r <= 0; internal_autopch <= 0; internal_autopch_r <= 0; end else if((local_write_req | local_read_req) & local_ready) begin internal_size <= {local_size,1'b0}; // multiply local_size by 2 internal_size_r <= internal_size; internal_multicast <= local_multicast; internal_multicast_r <= internal_multicast; internal_autopch <= local_autopch_req; internal_autopch_r <= internal_autopch; end end always @(posedge ctl_clk or negedge ctl_reset_n) begin if (!ctl_reset_n) begin burstcount <= 0; state <= 3'd0; end else begin case (state) 3'd0: begin if(avalon_write_req) begin burstcount <= burstcount + 1; state <= 3'd1; end end 3'd1: begin if(avalon_write_req) begin if(burstcount == avalon_avm_size -1) begin burstcount <= 0; state <= 3'd0; end else begin burstcount <= burstcount + 1; end end end endcase end end altera_avalon_half_rate_bridge #( .AVM_DATA_WIDTH (INTERNAL_DATA_WIDTH), .AVM_ADDR_WIDTH (AVM_ADDR_WIDTH), .AVM_BYTE_WIDTH (INTERNAL_BE_WIDTH), .AVS_DATA_WIDTH (LOCAL_DATA_WIDTH), .AVS_ADDR_WIDTH (LOCAL_ADDR_WIDTH), .AVS_BYTE_WIDTH (LOCAL_BE_WIDTH) ) HRB_inst ( .avs_reset_n (ctl_reset_n), .avm_reset_n (ctl_half_clk_reset_n), // Avalon slave input .avs_clk (ctl_half_clk ), .avs_chipselect (avs_chipselect ), .avs_address (local_addr ), .avs_write (local_write_req ), .avs_read (local_read_req ), .avs_byteenable (local_be ), .avs_writedata (local_wdata ), // Avalon slave output .avs_readdata (local_rdata ), .avs_waitrequest (avs_waitrequest ), .avs_readdatavalid (local_rdata_valid ), // Avalon master input .avm_clk (ctl_clk ), .avm_readdata (ecc_rdata ), .avm_waitrequest (!internal_ready ), .avm_readdatavalid (ecc_rdata_valid[0] ), // Avalon master output .avm_burstcount (), //not going to use it, because burstcount in the HRB is fixed at 2 .avm_address (avm_address ), .avm_write (avm_write ), .avm_read (avm_read ), .avm_byteenable (avalon_be ), .avm_writedata (avalon_wdata ) ); end else begin assign avalon_write_req = local_write_req & internal_ready; assign avalon_wdata = local_wdata; assign avalon_be = local_be; assign avalon_read_req = local_read_req & internal_ready; assign local_rdata = ecc_rdata; assign local_rdata_valid = ecc_rdata_valid[0]; assign local_rdata_error = ecc_rdata_error; assign avalon_addr = local_addr; assign avalon_size = local_size; assign avalon_burstbegin = local_burstbegin; assign local_ready = internal_ready; assign avalon_multicast = local_multicast; assign avalon_autopch_req = local_autopch_req; end endgenerate function integer log2; //constant function input integer value; begin for (log2=0; value>0; log2=log2+1) value = value>>1; log2 = log2 - 1; end endfunction endmodule
// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Wilson Snyder. module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [7:0] sel = crc[7:0]; wire [255+3:0] in = {crc[2:0],crc,crc,crc,crc}; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [3:0] out; // From test of Test.v // End of automatics /* Test AUTO_TEMPLATE ( .i\([0-9]+\) (in[\1 +:4]), ); */ Test test (/*AUTOINST*/ // Outputs .out (out[3:0]), // Inputs .sel (sel[7:0]), .i0 (in[0 +:4]), // Templated .i1 (in[1 +:4]), // Templated .i2 (in[2 +:4]), // Templated .i3 (in[3 +:4]), // Templated .i4 (in[4 +:4]), // Templated .i5 (in[5 +:4]), // Templated .i6 (in[6 +:4]), // Templated .i7 (in[7 +:4]), // Templated .i8 (in[8 +:4]), // Templated .i9 (in[9 +:4]), // Templated .i10 (in[10 +:4]), // Templated .i11 (in[11 +:4]), // Templated .i12 (in[12 +:4]), // Templated .i13 (in[13 +:4]), // Templated .i14 (in[14 +:4]), // Templated .i15 (in[15 +:4]), // Templated .i16 (in[16 +:4]), // Templated .i17 (in[17 +:4]), // Templated .i18 (in[18 +:4]), // Templated .i19 (in[19 +:4]), // Templated .i20 (in[20 +:4]), // Templated .i21 (in[21 +:4]), // Templated .i22 (in[22 +:4]), // Templated .i23 (in[23 +:4]), // Templated .i24 (in[24 +:4]), // Templated .i25 (in[25 +:4]), // Templated .i26 (in[26 +:4]), // Templated .i27 (in[27 +:4]), // Templated .i28 (in[28 +:4]), // Templated .i29 (in[29 +:4]), // Templated .i30 (in[30 +:4]), // Templated .i31 (in[31 +:4]), // Templated .i32 (in[32 +:4]), // Templated .i33 (in[33 +:4]), // Templated .i34 (in[34 +:4]), // Templated .i35 (in[35 +:4]), // Templated .i36 (in[36 +:4]), // Templated .i37 (in[37 +:4]), // Templated .i38 (in[38 +:4]), // Templated .i39 (in[39 +:4]), // Templated .i40 (in[40 +:4]), // Templated .i41 (in[41 +:4]), // Templated .i42 (in[42 +:4]), // Templated .i43 (in[43 +:4]), // Templated .i44 (in[44 +:4]), // Templated .i45 (in[45 +:4]), // Templated .i46 (in[46 +:4]), // Templated .i47 (in[47 +:4]), // Templated .i48 (in[48 +:4]), // Templated .i49 (in[49 +:4]), // Templated .i50 (in[50 +:4]), // Templated .i51 (in[51 +:4]), // Templated .i52 (in[52 +:4]), // Templated .i53 (in[53 +:4]), // Templated .i54 (in[54 +:4]), // Templated .i55 (in[55 +:4]), // Templated .i56 (in[56 +:4]), // Templated .i57 (in[57 +:4]), // Templated .i58 (in[58 +:4]), // Templated .i59 (in[59 +:4]), // Templated .i60 (in[60 +:4]), // Templated .i61 (in[61 +:4]), // Templated .i62 (in[62 +:4]), // Templated .i63 (in[63 +:4]), // Templated .i64 (in[64 +:4]), // Templated .i65 (in[65 +:4]), // Templated .i66 (in[66 +:4]), // Templated .i67 (in[67 +:4]), // Templated .i68 (in[68 +:4]), // Templated .i69 (in[69 +:4]), // Templated .i70 (in[70 +:4]), // Templated .i71 (in[71 +:4]), // Templated .i72 (in[72 +:4]), // Templated .i73 (in[73 +:4]), // Templated .i74 (in[74 +:4]), // Templated .i75 (in[75 +:4]), // Templated .i76 (in[76 +:4]), // Templated .i77 (in[77 +:4]), // Templated .i78 (in[78 +:4]), // Templated .i79 (in[79 +:4]), // Templated .i80 (in[80 +:4]), // Templated .i81 (in[81 +:4]), // Templated .i82 (in[82 +:4]), // Templated .i83 (in[83 +:4]), // Templated .i84 (in[84 +:4]), // Templated .i85 (in[85 +:4]), // Templated .i86 (in[86 +:4]), // Templated .i87 (in[87 +:4]), // Templated .i88 (in[88 +:4]), // Templated .i89 (in[89 +:4]), // Templated .i90 (in[90 +:4]), // Templated .i91 (in[91 +:4]), // Templated .i92 (in[92 +:4]), // Templated .i93 (in[93 +:4]), // Templated .i94 (in[94 +:4]), // Templated .i95 (in[95 +:4]), // Templated .i96 (in[96 +:4]), // Templated .i97 (in[97 +:4]), // Templated .i98 (in[98 +:4]), // Templated .i99 (in[99 +:4]), // Templated .i100 (in[100 +:4]), // Templated .i101 (in[101 +:4]), // Templated .i102 (in[102 +:4]), // Templated .i103 (in[103 +:4]), // Templated .i104 (in[104 +:4]), // Templated .i105 (in[105 +:4]), // Templated .i106 (in[106 +:4]), // Templated .i107 (in[107 +:4]), // Templated .i108 (in[108 +:4]), // Templated .i109 (in[109 +:4]), // Templated .i110 (in[110 +:4]), // Templated .i111 (in[111 +:4]), // Templated .i112 (in[112 +:4]), // Templated .i113 (in[113 +:4]), // Templated .i114 (in[114 +:4]), // Templated .i115 (in[115 +:4]), // Templated .i116 (in[116 +:4]), // Templated .i117 (in[117 +:4]), // Templated .i118 (in[118 +:4]), // Templated .i119 (in[119 +:4]), // Templated .i120 (in[120 +:4]), // Templated .i121 (in[121 +:4]), // Templated .i122 (in[122 +:4]), // Templated .i123 (in[123 +:4]), // Templated .i124 (in[124 +:4]), // Templated .i125 (in[125 +:4]), // Templated .i126 (in[126 +:4]), // Templated .i127 (in[127 +:4]), // Templated .i128 (in[128 +:4]), // Templated .i129 (in[129 +:4]), // Templated .i130 (in[130 +:4]), // Templated .i131 (in[131 +:4]), // Templated .i132 (in[132 +:4]), // Templated .i133 (in[133 +:4]), // Templated .i134 (in[134 +:4]), // Templated .i135 (in[135 +:4]), // Templated .i136 (in[136 +:4]), // Templated .i137 (in[137 +:4]), // Templated .i138 (in[138 +:4]), // Templated .i139 (in[139 +:4]), // Templated .i140 (in[140 +:4]), // Templated .i141 (in[141 +:4]), // Templated .i142 (in[142 +:4]), // Templated .i143 (in[143 +:4]), // Templated .i144 (in[144 +:4]), // Templated .i145 (in[145 +:4]), // Templated .i146 (in[146 +:4]), // Templated .i147 (in[147 +:4]), // Templated .i148 (in[148 +:4]), // Templated .i149 (in[149 +:4]), // Templated .i150 (in[150 +:4]), // Templated .i151 (in[151 +:4]), // Templated .i152 (in[152 +:4]), // Templated .i153 (in[153 +:4]), // Templated .i154 (in[154 +:4]), // Templated .i155 (in[155 +:4]), // Templated .i156 (in[156 +:4]), // Templated .i157 (in[157 +:4]), // Templated .i158 (in[158 +:4]), // Templated .i159 (in[159 +:4]), // Templated .i160 (in[160 +:4]), // Templated .i161 (in[161 +:4]), // Templated .i162 (in[162 +:4]), // Templated .i163 (in[163 +:4]), // Templated .i164 (in[164 +:4]), // Templated .i165 (in[165 +:4]), // Templated .i166 (in[166 +:4]), // Templated .i167 (in[167 +:4]), // Templated .i168 (in[168 +:4]), // Templated .i169 (in[169 +:4]), // Templated .i170 (in[170 +:4]), // Templated .i171 (in[171 +:4]), // Templated .i172 (in[172 +:4]), // Templated .i173 (in[173 +:4]), // Templated .i174 (in[174 +:4]), // Templated .i175 (in[175 +:4]), // Templated .i176 (in[176 +:4]), // Templated .i177 (in[177 +:4]), // Templated .i178 (in[178 +:4]), // Templated .i179 (in[179 +:4]), // Templated .i180 (in[180 +:4]), // Templated .i181 (in[181 +:4]), // Templated .i182 (in[182 +:4]), // Templated .i183 (in[183 +:4]), // Templated .i184 (in[184 +:4]), // Templated .i185 (in[185 +:4]), // Templated .i186 (in[186 +:4]), // Templated .i187 (in[187 +:4]), // Templated .i188 (in[188 +:4]), // Templated .i189 (in[189 +:4]), // Templated .i190 (in[190 +:4]), // Templated .i191 (in[191 +:4]), // Templated .i192 (in[192 +:4]), // Templated .i193 (in[193 +:4]), // Templated .i194 (in[194 +:4]), // Templated .i195 (in[195 +:4]), // Templated .i196 (in[196 +:4]), // Templated .i197 (in[197 +:4]), // Templated .i198 (in[198 +:4]), // Templated .i199 (in[199 +:4]), // Templated .i200 (in[200 +:4]), // Templated .i201 (in[201 +:4]), // Templated .i202 (in[202 +:4]), // Templated .i203 (in[203 +:4]), // Templated .i204 (in[204 +:4]), // Templated .i205 (in[205 +:4]), // Templated .i206 (in[206 +:4]), // Templated .i207 (in[207 +:4]), // Templated .i208 (in[208 +:4]), // Templated .i209 (in[209 +:4]), // Templated .i210 (in[210 +:4]), // Templated .i211 (in[211 +:4]), // Templated .i212 (in[212 +:4]), // Templated .i213 (in[213 +:4]), // Templated .i214 (in[214 +:4]), // Templated .i215 (in[215 +:4]), // Templated .i216 (in[216 +:4]), // Templated .i217 (in[217 +:4]), // Templated .i218 (in[218 +:4]), // Templated .i219 (in[219 +:4]), // Templated .i220 (in[220 +:4]), // Templated .i221 (in[221 +:4]), // Templated .i222 (in[222 +:4]), // Templated .i223 (in[223 +:4]), // Templated .i224 (in[224 +:4]), // Templated .i225 (in[225 +:4]), // Templated .i226 (in[226 +:4]), // Templated .i227 (in[227 +:4]), // Templated .i228 (in[228 +:4]), // Templated .i229 (in[229 +:4]), // Templated .i230 (in[230 +:4]), // Templated .i231 (in[231 +:4]), // Templated .i232 (in[232 +:4]), // Templated .i233 (in[233 +:4]), // Templated .i234 (in[234 +:4]), // Templated .i235 (in[235 +:4]), // Templated .i236 (in[236 +:4]), // Templated .i237 (in[237 +:4]), // Templated .i238 (in[238 +:4]), // Templated .i239 (in[239 +:4]), // Templated .i240 (in[240 +:4]), // Templated .i241 (in[241 +:4]), // Templated .i242 (in[242 +:4]), // Templated .i243 (in[243 +:4]), // Templated .i244 (in[244 +:4]), // Templated .i245 (in[245 +:4]), // Templated .i246 (in[246 +:4]), // Templated .i247 (in[247 +:4]), // Templated .i248 (in[248 +:4]), // Templated .i249 (in[249 +:4]), // Templated .i250 (in[250 +:4]), // Templated .i251 (in[251 +:4]), // Templated .i252 (in[252 +:4]), // Templated .i253 (in[253 +:4]), // Templated .i254 (in[254 +:4]), // Templated .i255 (in[255 +:4])); // Templated // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, out}; // What checksum will we end up with `define EXPECTED_SUM 64'h36f3051d15caf07a // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( output wire [3:0] out, input [7:0] sel, input [3:0] i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, i28, i29, i30, i31, i32, i33, i34, i35, i36, i37, i38, i39, i40, i41, i42, i43, i44, i45, i46, i47, i48, i49, i50, i51, i52, i53, i54, i55, i56, i57, i58, i59, i60, i61, i62, i63, i64, i65, i66, i67, i68, i69, i70, i71, i72, i73, i74, i75, i76, i77, i78, i79, i80, i81, i82, i83, i84, i85, i86, i87, i88, i89, i90, i91, i92, i93, i94, i95, i96, i97, i98, i99, i100, i101, i102, i103, i104, i105, i106, i107, i108, i109, i110, i111, i112, i113, i114, i115, i116, i117, i118, i119, i120, i121, i122, i123, i124, i125, i126, i127, i128, i129, i130, i131, i132, i133, i134, i135, i136, i137, i138, i139, i140, i141, i142, i143, i144, i145, i146, i147, i148, i149, i150, i151, i152, i153, i154, i155, i156, i157, i158, i159, i160, i161, i162, i163, i164, i165, i166, i167, i168, i169, i170, i171, i172, i173, i174, i175, i176, i177, i178, i179, i180, i181, i182, i183, i184, i185, i186, i187, i188, i189, i190, i191, i192, i193, i194, i195, i196, i197, i198, i199, i200, i201, i202, i203, i204, i205, i206, i207, i208, i209, i210, i211, i212, i213, i214, i215, i216, i217, i218, i219, i220, i221, i222, i223, i224, i225, i226, i227, i228, i229, i230, i231, i232, i233, i234, i235, i236, i237, i238, i239, i240, i241, i242, i243, i244, i245, i246, i247, i248, i249, i250, i251, i252, i253, i254, i255 ); assign out = (sel==8'h00) ? i0 : (sel==8'h01) ? i1 : (sel==8'h02) ? i2 : (sel==8'h03) ? i3 : (sel==8'h04) ? i4 : (sel==8'h05) ? i5 : (sel==8'h06) ? i6 : (sel==8'h07) ? i7 : (sel==8'h08) ? i8 : (sel==8'h09) ? i9 : (sel==8'h0a) ? i10 : (sel==8'h0b) ? i11 : (sel==8'h0c) ? i12 : (sel==8'h0d) ? i13 : (sel==8'h0e) ? i14 : (sel==8'h0f) ? i15 : (sel==8'h10) ? i16 : (sel==8'h11) ? i17 : (sel==8'h12) ? i18 : (sel==8'h13) ? i19 : (sel==8'h14) ? i20 : (sel==8'h15) ? i21 : (sel==8'h16) ? i22 : (sel==8'h17) ? i23 : (sel==8'h18) ? i24 : (sel==8'h19) ? i25 : (sel==8'h1a) ? i26 : (sel==8'h1b) ? i27 : (sel==8'h1c) ? i28 : (sel==8'h1d) ? i29 : (sel==8'h1e) ? i30 : (sel==8'h1f) ? i31 : (sel==8'h20) ? i32 : (sel==8'h21) ? i33 : (sel==8'h22) ? i34 : (sel==8'h23) ? i35 : (sel==8'h24) ? i36 : (sel==8'h25) ? i37 : (sel==8'h26) ? i38 : (sel==8'h27) ? i39 : (sel==8'h28) ? i40 : (sel==8'h29) ? i41 : (sel==8'h2a) ? i42 : (sel==8'h2b) ? i43 : (sel==8'h2c) ? i44 : (sel==8'h2d) ? i45 : (sel==8'h2e) ? i46 : (sel==8'h2f) ? i47 : (sel==8'h30) ? i48 : (sel==8'h31) ? i49 : (sel==8'h32) ? i50 : (sel==8'h33) ? i51 : (sel==8'h34) ? i52 : (sel==8'h35) ? i53 : (sel==8'h36) ? i54 : (sel==8'h37) ? i55 : (sel==8'h38) ? i56 : (sel==8'h39) ? i57 : (sel==8'h3a) ? i58 : (sel==8'h3b) ? i59 : (sel==8'h3c) ? i60 : (sel==8'h3d) ? i61 : (sel==8'h3e) ? i62 : (sel==8'h3f) ? i63 : (sel==8'h40) ? i64 : (sel==8'h41) ? i65 : (sel==8'h42) ? i66 : (sel==8'h43) ? i67 : (sel==8'h44) ? i68 : (sel==8'h45) ? i69 : (sel==8'h46) ? i70 : (sel==8'h47) ? i71 : (sel==8'h48) ? i72 : (sel==8'h49) ? i73 : (sel==8'h4a) ? i74 : (sel==8'h4b) ? i75 : (sel==8'h4c) ? i76 : (sel==8'h4d) ? i77 : (sel==8'h4e) ? i78 : (sel==8'h4f) ? i79 : (sel==8'h50) ? i80 : (sel==8'h51) ? i81 : (sel==8'h52) ? i82 : (sel==8'h53) ? i83 : (sel==8'h54) ? i84 : (sel==8'h55) ? i85 : (sel==8'h56) ? i86 : (sel==8'h57) ? i87 : (sel==8'h58) ? i88 : (sel==8'h59) ? i89 : (sel==8'h5a) ? i90 : (sel==8'h5b) ? i91 : (sel==8'h5c) ? i92 : (sel==8'h5d) ? i93 : (sel==8'h5e) ? i94 : (sel==8'h5f) ? i95 : (sel==8'h60) ? i96 : (sel==8'h61) ? i97 : (sel==8'h62) ? i98 : (sel==8'h63) ? i99 : (sel==8'h64) ? i100 : (sel==8'h65) ? i101 : (sel==8'h66) ? i102 : (sel==8'h67) ? i103 : (sel==8'h68) ? i104 : (sel==8'h69) ? i105 : (sel==8'h6a) ? i106 : (sel==8'h6b) ? i107 : (sel==8'h6c) ? i108 : (sel==8'h6d) ? i109 : (sel==8'h6e) ? i110 : (sel==8'h6f) ? i111 : (sel==8'h70) ? i112 : (sel==8'h71) ? i113 : (sel==8'h72) ? i114 : (sel==8'h73) ? i115 : (sel==8'h74) ? i116 : (sel==8'h75) ? i117 : (sel==8'h76) ? i118 : (sel==8'h77) ? i119 : (sel==8'h78) ? i120 : (sel==8'h79) ? i121 : (sel==8'h7a) ? i122 : (sel==8'h7b) ? i123 : (sel==8'h7c) ? i124 : (sel==8'h7d) ? i125 : (sel==8'h7e) ? i126 : (sel==8'h7f) ? i127 : (sel==8'h80) ? i128 : (sel==8'h81) ? i129 : (sel==8'h82) ? i130 : (sel==8'h83) ? i131 : (sel==8'h84) ? i132 : (sel==8'h85) ? i133 : (sel==8'h86) ? i134 : (sel==8'h87) ? i135 : (sel==8'h88) ? i136 : (sel==8'h89) ? i137 : (sel==8'h8a) ? i138 : (sel==8'h8b) ? i139 : (sel==8'h8c) ? i140 : (sel==8'h8d) ? i141 : (sel==8'h8e) ? i142 : (sel==8'h8f) ? i143 : (sel==8'h90) ? i144 : (sel==8'h91) ? i145 : (sel==8'h92) ? i146 : (sel==8'h93) ? i147 : (sel==8'h94) ? i148 : (sel==8'h95) ? i149 : (sel==8'h96) ? i150 : (sel==8'h98) ? i151 : (sel==8'h99) ? i152 : (sel==8'h9a) ? i153 : (sel==8'h9b) ? i154 : (sel==8'h9c) ? i155 : (sel==8'h9d) ? i156 : (sel==8'h9e) ? i157 : (sel==8'h9f) ? i158 : (sel==8'ha0) ? i159 : (sel==8'ha1) ? i160 : (sel==8'ha2) ? i161 : (sel==8'ha3) ? i162 : (sel==8'ha4) ? i163 : (sel==8'ha5) ? i164 : (sel==8'ha6) ? i165 : (sel==8'ha7) ? i166 : (sel==8'ha8) ? i167 : (sel==8'ha9) ? i168 : (sel==8'haa) ? i169 : (sel==8'hab) ? i170 : (sel==8'hac) ? i171 : (sel==8'had) ? i172 : (sel==8'hae) ? i173 : (sel==8'haf) ? i174 : (sel==8'hb0) ? i175 : (sel==8'hb1) ? i176 : (sel==8'hb2) ? i177 : (sel==8'hb3) ? i178 : (sel==8'hb4) ? i179 : (sel==8'hb5) ? i180 : (sel==8'hb6) ? i181 : (sel==8'hb7) ? i182 : (sel==8'hb8) ? i183 : (sel==8'hb9) ? i184 : (sel==8'hba) ? i185 : (sel==8'hbb) ? i186 : (sel==8'hbc) ? i187 : (sel==8'hbd) ? i188 : (sel==8'hbe) ? i189 : (sel==8'hbf) ? i190 : (sel==8'hc0) ? i191 : (sel==8'hc1) ? i192 : (sel==8'hc2) ? i193 : (sel==8'hc3) ? i194 : (sel==8'hc4) ? i195 : (sel==8'hc5) ? i196 : (sel==8'hc6) ? i197 : (sel==8'hc7) ? i198 : (sel==8'hc8) ? i199 : (sel==8'hc9) ? i200 : (sel==8'hca) ? i201 : (sel==8'hcb) ? i202 : (sel==8'hcc) ? i203 : (sel==8'hcd) ? i204 : (sel==8'hce) ? i205 : (sel==8'hcf) ? i206 : (sel==8'hd0) ? i207 : (sel==8'hd1) ? i208 : (sel==8'hd2) ? i209 : (sel==8'hd3) ? i210 : (sel==8'hd4) ? i211 : (sel==8'hd5) ? i212 : (sel==8'hd6) ? i213 : (sel==8'hd7) ? i214 : (sel==8'hd8) ? i215 : (sel==8'hd9) ? i216 : (sel==8'hda) ? i217 : (sel==8'hdb) ? i218 : (sel==8'hdc) ? i219 : (sel==8'hdd) ? i220 : (sel==8'hde) ? i221 : (sel==8'hdf) ? i222 : (sel==8'he0) ? i223 : (sel==8'he1) ? i224 : (sel==8'he2) ? i225 : (sel==8'he3) ? i226 : (sel==8'he4) ? i227 : (sel==8'he5) ? i228 : (sel==8'he6) ? i229 : (sel==8'he7) ? i230 : (sel==8'he8) ? i231 : (sel==8'he9) ? i232 : (sel==8'hea) ? i233 : (sel==8'heb) ? i234 : (sel==8'hec) ? i235 : (sel==8'hed) ? i236 : (sel==8'hee) ? i237 : (sel==8'hef) ? i238 : (sel==8'hf0) ? i239 : (sel==8'hf1) ? i240 : (sel==8'hf2) ? i241 : (sel==8'hf3) ? i242 : (sel==8'hf4) ? i243 : (sel==8'hf5) ? i244 : (sel==8'hf6) ? i245 : (sel==8'hf7) ? i246 : (sel==8'hf8) ? i247 : (sel==8'hf9) ? i248 : (sel==8'hfa) ? i249 : (sel==8'hfb) ? i250 : (sel==8'hfc) ? i251 : (sel==8'hfd) ? i252 : (sel==8'hfe) ? i253 : (sel==8'hff) ? i254 : i255; endmodule
module ahb_dummy ( input wire HCLK, input wire HRESET_N, input wire [`w_HADDR-1:0] HADDR, input wire [`w_HTRANS-1:0] HTRANS, input wire [`w_HBURST-1:0] HBURST, input wire HWRITE, input wire [`w_HSIZE-1:0] HSIZE, input wire HSEL, input wire [`w_HWDATA-1:0] HWDATA, input wire HREADY_I, output reg [`w_HRDATA-1:0] HRDATA, output reg HREADY_O, output wire [1:0] HRESP ); assign HRESP = 2'h0; always @(posedge HCLK) begin if (!HRESET_N) begin HRDATA <= `w_HRDATA'h0; HREADY_O <= 1'b0; end else begin HRDATA <= `w_HRDATA'h5A; HREADY_O <= $urandom(); end end endmodule
module decoder(INST, DR, SA, SB, IMM, MB, FS, MD, LD, MW, BS, OFF, HALT); input [15:0] INST; output [2:0] DR; output [2:0] SA; output [2:0] SB; output [5:0] IMM; output MB; output [2:0] FS; output MD; output LD; output MW; output [2:0] BS; output [5:0] OFF; output HALT; reg [2:0] DR; reg [2:0] SA; reg [2:0] SB; reg MB; reg [2:0] FS; reg MD; reg LD; reg MW; reg [2:0] BS; reg [5:0] OFF; reg HALT; reg [5:0] IMM; wire [3:0] OP; wire [2:0] RS; wire [2:0] RT; wire [2:0] RD; wire [2:0] FUNCT; wire [5:0] IMM_INST; assign OP = INST[15:12]; assign RS = INST[11:9]; assign RT = INST[8:6]; assign RD = INST[5:3]; assign FUNCT = INST[2:0]; assign IMM_INST = INST[5:0]; always @(*) begin case (OP) 4'b0000: begin DR = 3'b0; SA = 3'b0; SB = 3'b0; MB = 1'b0; FS = 3'b0; MD = 1'b0; LD = 1'b0; MW = 1'b0; BS = 3'b100; OFF = 6'b0; HALT = (FUNCT == 3'b001) ? 1'b1 : 1'b0; IMM = IMM_INST; end 4'b0010: begin DR = RT; SA = RS; SB = 3'b0; MB = 1'b1; FS = 3'b000; MD = 1'b1; LD = 1'b1; MW = 1'b0; BS = 3'b100; OFF = 6'b0; HALT = 1'b0; IMM = IMM_INST; end 4'b0100: begin DR = 3'b0; SA = RS; SB = RT; MB = 1'b1; FS = 3'b000; MD = 1'b0; LD = 1'b0; MW = 1'b1; BS = 3'b100; OFF = 6'b0; HALT = 1'b0; IMM = IMM_INST; end 4'b0101: begin DR = RT; SA = RS; SB = 3'b0; MB = 1'b1; FS = 3'b000; MD = 1'b0; LD = 1'b1; MW = 1'b0; BS = 3'b100; OFF = 6'b0; HALT = 1'b0; IMM = IMM_INST; end 4'b0110: begin DR = RT; SA = RS; SB = 3'b0; MB = 1'b1; FS = 3'b101; MD = 1'b0; LD = 1'b1; MW = 1'b0; BS = 3'b100; OFF = 6'b0; HALT = 1'b0; IMM = IMM_INST; end 4'b0111: begin DR = RT; SA = RS; SB = 3'b0; MB = 1'b1; FS = 3'b110; MD = 1'b0; LD = 1'b1; MW = 1'b0; BS = 3'b100; OFF = 6'b0; HALT = 1'b0; IMM = IMM_INST; end 4'b1000: begin DR = 3'b0; SA = RS; SB = RT; MB = 1'b0; FS = 3'b001; MD = 1'b0; LD = 1'b0; MW = 1'b0; BS = 3'b000; OFF = IMM_INST; HALT = 1'b0; IMM = IMM_INST; end 4'b1001: begin DR = 3'b0; SA = RS; SB = RT; MB = 1'b0; FS = 3'b001; MD = 1'b0; LD = 1'b0; MW = 1'b0; BS = 3'b001; OFF = IMM_INST; HALT = 1'b0; IMM = IMM_INST; end 4'b1010: begin DR = 3'b0; SA = RS; SB = 3'b0; MB = 1'b1; FS = 3'b000; MD = 1'b0; LD = 1'b0; MW = 1'b0; BS = 3'b010; OFF = IMM_INST; HALT = 1'b0; IMM = 6'b0; end 4'b1011: begin DR = 3'b0; SA = RS; SB = 3'b0; MB = 1'b1; FS = 3'b000; MD = 1'b0; LD = 1'b0; MW = 1'b0; BS = 3'b011; OFF = IMM_INST; HALT = 1'b0; IMM = 6'b0; end 4'b1111: begin DR = RD; SA = RS; SB = RT; MB = 1'b0; FS = FUNCT; MD = 1'b0; LD = 1'b1; MW = 1'b0; BS = 3'b100; OFF = 6'b0; HALT = 1'b0; IMM = IMM_INST; end default: begin DR = 3'b0; SA = 3'b0; SB = 3'b0; MB = 1'b0; FS = 3'b0; MD = 1'b0; LD = 1'b0; MW = 1'b0; BS = 3'b100; OFF = 6'b0; HALT = 1'b0; IMM = IMM_INST; end endcase end endmodule
// nios_tester_nios2_gen2_0.v // This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes // will probably be lost. // // Generated using ACDS version 18.1 625 `timescale 1 ps / 1 ps module nios_tester_nios2_gen2_0 ( input wire clk, // clk.clk input wire reset_n, // reset.reset_n input wire reset_req, // .reset_req output wire [31:0] d_address, // data_master.address output wire [3:0] d_byteenable, // .byteenable output wire d_read, // .read input wire [31:0] d_readdata, // .readdata input wire d_waitrequest, // .waitrequest output wire d_write, // .write output wire [31:0] d_writedata, // .writedata output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess output wire [29:0] i_address, // instruction_master.address output wire i_read, // .read input wire [31:0] i_readdata, // .readdata input wire i_waitrequest, // .waitrequest input wire [31:0] irq, // irq.irq output wire debug_reset_request, // debug_reset_request.reset input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address input wire [3:0] debug_mem_slave_byteenable, // .byteenable input wire debug_mem_slave_debugaccess, // .debugaccess input wire debug_mem_slave_read, // .read output wire [31:0] debug_mem_slave_readdata, // .readdata output wire debug_mem_slave_waitrequest, // .waitrequest input wire debug_mem_slave_write, // .write input wire [31:0] debug_mem_slave_writedata, // .writedata output wire dummy_ci_port // custom_instruction_master.readra ); nios_tester_nios2_gen2_0_cpu cpu ( .clk (clk), // clk.clk .reset_n (reset_n), // reset.reset_n .reset_req (reset_req), // .reset_req .d_address (d_address), // data_master.address .d_byteenable (d_byteenable), // .byteenable .d_read (d_read), // .read .d_readdata (d_readdata), // .readdata .d_waitrequest (d_waitrequest), // .waitrequest .d_write (d_write), // .write .d_writedata (d_writedata), // .writedata .debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess .i_address (i_address), // instruction_master.address .i_read (i_read), // .read .i_readdata (i_readdata), // .readdata .i_waitrequest (i_waitrequest), // .waitrequest .irq (irq), // irq.irq .debug_reset_request (debug_reset_request), // debug_reset_request.reset .debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address .debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable .debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess .debug_mem_slave_read (debug_mem_slave_read), // .read .debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata .debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest .debug_mem_slave_write (debug_mem_slave_write), // .write .debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata .dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra ); endmodule
// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2003 by Wilson Snyder. module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; // verilator lint_off GENCLK reg printclk; // verilator lint_on GENCLK ps ps (printclk); reg [7:0] a; wire [7:0] z; l1 u (~a,z); always @ (posedge clk) begin printclk <= 0; if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin printclk <= 1'b1; end if (cyc==2) begin a <= 8'b1; end if (cyc==3) begin if (z !== 8'hf8) $stop; //if (u.u1.u1.u1.u0.PARAM !== 1) $stop; //if (u.u1.u1.u1.u1.PARAM !== 2) $stop; //if (u.u0.u0.u0.u0.z !== 8'hfe) $stop; //if (u.u0.u0.u0.u1.z !== 8'hff) $stop; //if (u.u1.u1.u1.u0.z !== 8'h00) $stop; //if (u.u1.u1.u1.u1.z !== 8'h01) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule `ifdef USE_INLINE `define INLINE_MODULE /*verilator inline_module*/ `else `define INLINE_MODULE /*verilator public_module*/ `endif `ifdef USE_PUBLIC `define PUBLIC /*verilator public*/ `else `define PUBLIC `endif module ps (input printclk); `INLINE_MODULE // Check that %m stays correct across inlines always @ (posedge printclk) $write("[%0t] %m: Clocked\n", $time); endmodule module l1 (input [7:0] a, output [7:0] z); `INLINE_MODULE wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC; wire [7:0] z `PUBLIC; assign z = z0+z1; l2 u0 (a, z0); l2 u1 (a, z1); endmodule module l2 (input [7:0] a, output [7:0] z); `INLINE_MODULE wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC; wire [7:0] z `PUBLIC; assign z = z0+z1; wire [7:0] a1 = a+8'd1; l3 u0 (a, z0); l3 u1 (a1, z1); endmodule module l3 (input [7:0] a, output [7:0] z); `INLINE_MODULE wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC; wire [7:0] z `PUBLIC; assign z = z0+z1; wire [7:0] a1 = a+8'd1; l4 u0 (a, z0); l4 u1 (a1, z1); endmodule module l4 (input [7:0] a, output [7:0] z); `INLINE_MODULE wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC; wire [7:0] z `PUBLIC; assign z = z0+z1; wire [7:0] a1 = a+8'd1; l5 #(1) u0 (a, z0); l5 #(2) u1 (a1, z1); endmodule module l5 (input [7:0] a, output [7:0] z); `INLINE_MODULE parameter PARAM = 5; wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC; wire [7:0] z `PUBLIC; assign z = a; endmodule
/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HS__O311A_BEHAVIORAL_V `define SKY130_FD_SC_HS__O311A_BEHAVIORAL_V /** * o311a: 3-input OR into 3-input AND. * * X = ((A1 | A2 | A3) & B1 & C1) * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none // Import sub cells. `include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v" `celldefine module sky130_fd_sc_hs__o311a ( X , A1 , A2 , A3 , B1 , C1 , VPWR, VGND ); // Module ports output X ; input A1 ; input A2 ; input A3 ; input B1 ; input C1 ; input VPWR; input VGND; // Local signals wire B1 or0_out ; wire and0_out_X ; wire u_vpwr_vgnd0_out_X; // Name Output Other arguments or or0 (or0_out , A2, A1, A3 ); and and0 (and0_out_X , or0_out, B1, C1 ); sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND); buf buf0 (X , u_vpwr_vgnd0_out_X ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_HS__O311A_BEHAVIORAL_V
module main; parameter use_wid = 4; reg [use_wid-1:0] d; wire [use_wid-1:0] q; reg clk; defparam dut.wid = use_wid; B dut (.Q(q), .D(d), .C(clk)); initial begin clk = 0; d = 4'b0000; #1 clk = 1; #1 clk = 0; if (q !== 4'b0000) begin $display("FAILED -- d=%b, q=%b", d, q); $finish; end d = 4'b1111; #1 clk = 1; #1 clk = 0; if (q !== 4'b1111) begin $display("FAILED -- d=%b, q=%b", d, q); $finish; end $display("PASSED"); end endmodule // main /* * although the wid paramter is default to 3 in this module, the point * of this test is to have the instantiating module (main) give a * different value and have that value properly handlued in all the * situations of this module. */ module B #(parameter wid = 3) (output [wid-1:0] Q, input [wid-1:0] D, input C); // the override from main will cause this to be a width of 4. prim U [wid-1:0] (Q, D, C); //prim U [wid-1:0] (.Q(Q), .D(D), .C(C)); endmodule // B module prim(output reg Q, input D, C); always @(posedge C) Q <= D; endmodule // prim
/////////////////////////////////////////////////////////////////////////////// // Title : (DDR1/2/3,LPDDR1) address and command decoder // // File : alt_mem_ddrx_addr_cmd.v // // Abstract : Address and command decoder /////////////////////////////////////////////////////////////////////////////// //altera message_off 10036 `include "alt_mem_ddrx_define.iv" `timescale 1 ps / 1 ps module alt_mem_ddrx_addr_cmd # (parameter // Global parameters CFG_PORT_WIDTH_TYPE = 3, CFG_PORT_WIDTH_OUTPUT_REGD = 1, CFG_MEM_IF_CHIP = 1, CFG_MEM_IF_CKE_WIDTH = 1, // same width as CS_WIDTH CFG_MEM_IF_ADDR_WIDTH = 16, // max supported address bits, must be >= row bits (For ddr3 >=13 even if row=12) CFG_MEM_IF_ROW_WIDTH = 16, // max supported row bits CFG_MEM_IF_COL_WIDTH = 12, // max supported column bits CFG_MEM_IF_BA_WIDTH = 3, // max supported bank bits CFG_CTL_RATE = "FULL", CFG_DWIDTH_RATIO = 2 ) ( ctl_clk, ctl_reset_n, ctl_cal_success, //run-time configuration interface cfg_type, cfg_output_regd, cfg_enable_chipsel_for_sideband, // to indicate should we de-assert cs_n for sideband signal (self refresh and deep power down specific) // AFI interface (Signals from Arbiter block) bg_do_write, bg_do_read, bg_do_burst_chop, bg_do_auto_precharge, bg_do_activate, bg_do_precharge, bg_do_precharge_all, bg_do_refresh, bg_do_self_refresh, bg_do_power_down, bg_do_zq_cal, bg_do_lmr, bg_do_burst_terminate, //Currently does not exist in arbiter bg_do_deep_pdown, //Currently does not exist in arbiter // address information bg_to_chip, // active high input (one hot) bg_to_bank, bg_to_row, bg_to_col, bg_to_lmr, //Currently doesn not exist in arbiter lmr_opcode, //output to PHY afi_addr, afi_ba, afi_cke, afi_cs_n, afi_ras_n, afi_cas_n, afi_we_n, afi_rst_n ); //=================================================================================================// // input/output declaration // //=================================================================================================// input ctl_clk; input ctl_reset_n; input ctl_cal_success; //run-time configuration input input [CFG_PORT_WIDTH_TYPE-1:0] cfg_type; input [CFG_PORT_WIDTH_OUTPUT_REGD -1:0] cfg_output_regd; input cfg_enable_chipsel_for_sideband; // Arbiter command inputs input bg_do_write; input bg_do_read; input bg_do_burst_chop; input bg_do_auto_precharge; input bg_do_activate; input bg_do_precharge; input [CFG_MEM_IF_CHIP-1:0] bg_do_precharge_all; input [CFG_MEM_IF_CHIP-1:0] bg_do_refresh; input [CFG_MEM_IF_CHIP-1:0] bg_do_self_refresh; input [CFG_MEM_IF_CHIP-1:0] bg_do_power_down; input [CFG_MEM_IF_CHIP-1:0] bg_do_zq_cal; input bg_do_lmr; input bg_do_burst_terminate; input [CFG_MEM_IF_CHIP-1:0] bg_do_deep_pdown; input [CFG_MEM_IF_CHIP-1:0] bg_to_chip; input [CFG_MEM_IF_BA_WIDTH-1:0] bg_to_bank; input [CFG_MEM_IF_ROW_WIDTH-1:0] bg_to_row; input [CFG_MEM_IF_COL_WIDTH-1:0] bg_to_col; input [CFG_MEM_IF_BA_WIDTH-1:0] bg_to_lmr; input [CFG_MEM_IF_ADDR_WIDTH-1:0] lmr_opcode; //output output [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke; output [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n; output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_ras_n; output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_cas_n; output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_we_n; output [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_ba; output [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr; output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n; //=================================================================================================// // reg/wire declaration // //=================================================================================================// wire bg_do_write; wire bg_do_read; wire bg_do_burst_chop; wire bg_do_auto_precharge; wire bg_do_activate; wire bg_do_precharge; wire [CFG_MEM_IF_CHIP-1:0] bg_do_precharge_all; wire [CFG_MEM_IF_CHIP-1:0] bg_do_refresh; wire [CFG_MEM_IF_CHIP-1:0] bg_do_self_refresh; wire [CFG_MEM_IF_CHIP-1:0] bg_do_power_down; wire [CFG_MEM_IF_CHIP-1:0] bg_do_zq_cal; wire bg_do_lmr; wire [CFG_MEM_IF_CHIP-1:0] bg_do_deep_pdown; wire bg_do_burst_terminate; reg [CFG_MEM_IF_CHIP-1:0] do_self_refresh; reg [CFG_MEM_IF_CHIP-1:0] do_power_down; reg [CFG_MEM_IF_CHIP-1:0] do_deep_pdown; reg [CFG_MEM_IF_CHIP-1:0] do_self_refresh_r; reg [CFG_MEM_IF_CHIP-1:0] do_power_down_r; reg [CFG_MEM_IF_CHIP-1:0] do_deep_pdown_r; wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke; wire [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n; wire [(CFG_DWIDTH_RATIO/2) - 1:0] afi_ras_n; wire [(CFG_DWIDTH_RATIO/2) - 1:0] afi_cas_n; wire [(CFG_DWIDTH_RATIO/2) - 1:0] afi_we_n; wire [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_ba; wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr; wire [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n; reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] int_cke; reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] int_cke_r; reg [(CFG_MEM_IF_CHIP) - 1:0] int_cs_n; reg int_ras_n; reg int_cas_n; reg int_we_n; reg [(CFG_MEM_IF_BA_WIDTH) - 1:0] int_ba; reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_addr; reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] combi_cke ; reg [(CFG_MEM_IF_CHIP) - 1:0] combi_cs_n ; reg combi_ras_n; reg combi_cas_n; reg combi_we_n ; reg [(CFG_MEM_IF_BA_WIDTH) - 1:0] combi_ba ; reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] combi_addr ; reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] combi_cke_r ; reg [(CFG_MEM_IF_CHIP) - 1:0] combi_cs_n_r ; reg combi_ras_n_r; reg combi_cas_n_r; reg combi_we_n_r ; reg [(CFG_MEM_IF_BA_WIDTH) - 1:0] combi_ba_r ; reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] combi_addr_r ; wire [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_row; wire [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] temp_col; wire [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_col; wire col12; wire [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_col_r; reg [CFG_MEM_IF_CHIP-1:0] chip_in_self_refresh; //=================================================================================================// generate if (CFG_MEM_IF_ADDR_WIDTH > CFG_MEM_IF_ROW_WIDTH) begin assign int_row = {{(CFG_MEM_IF_ADDR_WIDTH - CFG_MEM_IF_ROW_WIDTH){1'b0}},bg_to_row}; end else begin assign int_row = bg_to_row; end endgenerate assign temp_col = {{(CFG_MEM_IF_ADDR_WIDTH - CFG_MEM_IF_COL_WIDTH){1'b0}},bg_to_col}; assign afi_rst_n = {(CFG_DWIDTH_RATIO/2){1'b1}}; assign col12 = (cfg_type == `MMR_TYPE_DDR3) ? ~bg_do_burst_chop : temp_col[11]; //DDR3 generate if (CFG_MEM_IF_ADDR_WIDTH < 13) begin assign int_col = {temp_col[CFG_MEM_IF_ADDR_WIDTH-1:10],bg_do_auto_precharge,temp_col[9:0]}; end else if (CFG_MEM_IF_ADDR_WIDTH == 13) begin assign int_col = {col12,temp_col[10],bg_do_auto_precharge,temp_col[9:0]}; end else begin assign int_col = {temp_col[CFG_MEM_IF_ADDR_WIDTH-3:11],col12,temp_col[10],bg_do_auto_precharge,temp_col[9:0]}; end endgenerate generate if (CFG_DWIDTH_RATIO == 2) begin assign afi_cke = int_cke; assign afi_cs_n = int_cs_n; assign afi_ras_n = int_ras_n; assign afi_cas_n = int_cas_n; assign afi_we_n = int_we_n; assign afi_ba = int_ba; assign afi_addr = int_addr; end else begin assign afi_cke = {int_cke,int_cke_r}; assign afi_cs_n = {int_cs_n,{CFG_MEM_IF_CHIP{1'b1}}}; // to provide time for addr bus to settle at high freq, cs sent on 2nd phase assign afi_ras_n = {int_ras_n,int_ras_n}; assign afi_cas_n = {int_cas_n,int_cas_n}; assign afi_we_n = {int_we_n,int_we_n}; assign afi_ba = {int_ba,int_ba}; assign afi_addr = {int_addr,int_addr}; end endgenerate always @(posedge ctl_clk, negedge ctl_reset_n) // aligns cke with cs for slf rfsh & pwrdwn(lpddr1)which is defined only when cs_n goes low begin if (!ctl_reset_n) int_cke_r <= {(CFG_MEM_IF_CKE_WIDTH){1'b0}}; else int_cke_r <= int_cke; end always @(posedge ctl_clk, negedge ctl_reset_n) // toogles cs_n for only one cyle when state machine continues to stay in slf rfsh mode begin if (!ctl_reset_n) chip_in_self_refresh <= {(CFG_MEM_IF_CHIP){1'b0}}; else if ((bg_do_self_refresh) || (bg_do_deep_pdown && cfg_type == `MMR_TYPE_LPDDR1)) //LPDDDR1 chip_in_self_refresh <= bg_to_chip; else chip_in_self_refresh <= {(CFG_MEM_IF_CHIP){1'b0}}; end always @(posedge ctl_clk, negedge ctl_reset_n) begin if (!ctl_reset_n) begin combi_cke_r <= {(CFG_MEM_IF_CKE_WIDTH){1'b1}}; combi_cs_n_r <= {(CFG_MEM_IF_CHIP){1'b1}}; combi_ras_n_r <= 1'b1; combi_cas_n_r <= 1'b1; combi_we_n_r <= 1'b1; combi_ba_r <= {(CFG_MEM_IF_BA_WIDTH){1'b0}}; combi_addr_r <= {(CFG_MEM_IF_ADDR_WIDTH){1'b0}}; end else begin combi_cke_r <= combi_cke; combi_cs_n_r <= combi_cs_n; combi_ras_n_r <= combi_ras_n; combi_cas_n_r <= combi_cas_n; combi_we_n_r <= combi_we_n; combi_ba_r <= combi_ba; combi_addr_r <= combi_addr; end end always @(*) begin if (cfg_output_regd) begin int_cke = combi_cke_r; int_cs_n = combi_cs_n_r; int_ras_n = combi_ras_n_r; int_cas_n = combi_cas_n_r; int_we_n = combi_we_n_r; int_ba = combi_ba_r; int_addr = combi_addr_r; end else begin int_cke = combi_cke; int_cs_n = combi_cs_n; int_ras_n = combi_ras_n; int_cas_n = combi_cas_n; int_we_n = combi_we_n; int_ba = combi_ba; int_addr = combi_addr; end end //CKE generation block always @(*) begin if (ctl_cal_success) begin combi_cke = ~(bg_do_self_refresh | bg_do_power_down | bg_do_deep_pdown); end else begin combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}}; end end //Pulse generator for self refresh, power down and deep power down always @(posedge ctl_clk, negedge ctl_reset_n) begin if (!ctl_reset_n) begin do_self_refresh_r <= {(CFG_MEM_IF_CHIP){1'b0}}; do_power_down_r <= {(CFG_MEM_IF_CHIP){1'b0}}; do_deep_pdown_r <= {(CFG_MEM_IF_CHIP){1'b0}}; end else begin do_self_refresh_r <= ~bg_do_self_refresh; do_power_down_r <= ~bg_do_power_down; do_deep_pdown_r <= ~bg_do_deep_pdown; end end always @(*) begin do_self_refresh = bg_do_self_refresh & do_self_refresh_r; do_power_down = bg_do_power_down & do_power_down_r; do_deep_pdown = bg_do_deep_pdown & do_deep_pdown_r; end always @(*) //All Command inputs are mutually exclusive begin if (ctl_cal_success) begin // combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}}; //Should we put default condition into if(!bg_do_refresh && !bg_do_activate....)?? combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}}; combi_ras_n = 1'b1; combi_cas_n = 1'b1; combi_we_n = 1'b1; combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}}; combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}}; if (|bg_do_refresh) begin // combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}}; combi_cs_n = ~bg_do_refresh; combi_ras_n = 1'b0; combi_cas_n = 1'b0; combi_we_n = 1'b1; combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}}; combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}}; end if (|bg_do_precharge_all) begin // combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}}; combi_cs_n = ~bg_do_precharge_all; combi_ras_n = 1'b0; combi_cas_n = 1'b1; combi_we_n = 1'b0; combi_ba = bg_to_bank; combi_addr[10]= 1'b1; end if (bg_do_activate) begin // combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}}; combi_cs_n = ~bg_to_chip; combi_ras_n = 1'b0; combi_cas_n = 1'b1; combi_we_n = 1'b1; combi_ba = bg_to_bank; combi_addr = int_row; end if (bg_do_precharge) begin // combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}}; combi_cs_n = ~bg_to_chip; combi_ras_n = 1'b0; combi_cas_n = 1'b1; combi_we_n = 1'b0; combi_ba = bg_to_bank; combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}}; end if (bg_do_write) begin // combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}}; combi_cs_n = ~bg_to_chip; combi_ras_n = 1'b1; combi_cas_n = 1'b0; combi_we_n = 1'b0; combi_ba = bg_to_bank; combi_addr = int_col; end if (bg_do_read) begin // combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}}; combi_cs_n = ~bg_to_chip; combi_ras_n = 1'b1; combi_cas_n = 1'b0; combi_we_n = 1'b1; combi_ba = bg_to_bank; combi_addr = int_col; end if (|do_power_down) begin // combi_cke = ~bg_to_chip; combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}}; combi_ras_n = 1'b1; combi_cas_n = 1'b1; combi_we_n = 1'b1; combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}}; combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}}; end if (|do_deep_pdown) //Put assertion for memory type ddr2 and ddr3 as an error begin // combi_cke = ~bg_to_chip; if (cfg_enable_chipsel_for_sideband) begin combi_cs_n = ~do_deep_pdown; // toogles cs_n for only one cyle when state machine continues to stay in slf rfsh mode end else begin combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}}; end combi_ras_n = 1'b1; combi_cas_n = 1'b1; combi_we_n = 1'b0; combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}}; combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}}; end if (|do_self_refresh) begin // combi_cke = ~bg_to_chip; if (cfg_enable_chipsel_for_sideband) begin combi_cs_n = ~do_self_refresh; // toogles cs_n for only one cyle when state machine continues to stay in slf rfsh mode end else begin combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}}; end combi_ras_n = 1'b0; combi_cas_n = 1'b0; combi_we_n = 1'b1; combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}}; combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}}; end if (|bg_do_zq_cal) // Only short zqcal supported begin if (cfg_type == `MMR_TYPE_DDR3) //DDR3 begin // combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}}; combi_cs_n = ~bg_do_zq_cal; combi_ras_n = 1'b1; combi_cas_n = 1'b1; combi_we_n = 1'b0; combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}}; combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}}; end else // Should we flag error or issue as NOP begin // combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}}; combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}}; combi_ras_n = 1'b1; combi_cas_n = 1'b1; combi_we_n = 1'b1; combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}}; combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}}; end end if (bg_do_lmr) begin // combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}}; // to support chng rfsh time based on temp combi_cs_n = ~bg_to_chip; combi_ras_n = 1'b0; combi_cas_n = 1'b0; combi_we_n = 1'b0; combi_ba = bg_to_lmr; combi_addr = lmr_opcode; end if (bg_do_burst_terminate) begin if (cfg_type == `MMR_TYPE_LPDDR1) //lpddr1 begin // combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}}; combi_cs_n = ~bg_to_chip; combi_ras_n = 1'b1; combi_cas_n = 1'b1; combi_we_n = 1'b0; combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}}; combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}}; end else begin // combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}}; combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}}; combi_ras_n = 1'b1; combi_cas_n = 1'b1; combi_we_n = 1'b1; combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}}; combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}}; end end end else begin // combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}}; combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}}; combi_ras_n = 1'b1; combi_cas_n = 1'b1; combi_we_n = 1'b1; combi_ba = {(CFG_MEM_IF_BA_WIDTH){1'b0}}; combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}}; end end endmodule
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // Description: SRL based FIFO for AXIS/AXI Channels. //-------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_infrastructure_v1_1_axic_srl_fifo #( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// parameter C_FAMILY = "virtex7", parameter integer C_PAYLOAD_WIDTH = 1, parameter integer C_FIFO_DEPTH = 16 // Range: 4-16. ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire aclk, // Clock input wire aresetn, // Reset input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data input wire s_valid, // Input data valid output reg s_ready, // Input data ready output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data output reg m_valid, // Output data valid input wire m_ready // Output data ready ); //////////////////////////////////////////////////////////////////////////////// // Functions //////////////////////////////////////////////////////////////////////////////// // ceiling logb2 function integer f_clogb2 (input integer size); integer s; begin s = size; s = s - 1; for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1) s = s >> 1; end endfunction // clogb2 //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH); //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index; wire [4-1:0] fifo_addr; wire push; wire pop ; reg areset_r1; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// always @(posedge aclk) begin areset_r1 <= ~aresetn; end always @(posedge aclk) begin if (~aresetn) begin fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}}; end else begin fifo_index <= push & ~pop ? fifo_index + 1'b1 : ~push & pop ? fifo_index - 1'b1 : fifo_index; end end assign push = s_valid & s_ready; always @(posedge aclk) begin if (~aresetn) begin s_ready <= 1'b0; end else begin s_ready <= areset_r1 ? 1'b1 : push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 : ~push & pop ? 1'b1 : s_ready; end end assign pop = m_valid & m_ready; always @(posedge aclk) begin if (~aresetn) begin m_valid <= 1'b0; end else begin m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 : push & ~pop ? 1'b1 : m_valid; end end generate if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0]; assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}}; end else begin : gen_fifo_addr assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0]; end endgenerate generate genvar i; for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit SRL16E u_srl_fifo( .Q ( m_payload[i] ) , .A0 ( fifo_addr[0] ) , .A1 ( fifo_addr[1] ) , .A2 ( fifo_addr[2] ) , .A3 ( fifo_addr[3] ) , .CE ( push ) , .CLK ( aclk ) , .D ( s_payload[i] ) ); end endgenerate endmodule `default_nettype wire
//----------------------------------------------------------------------------- // processing_system7 // processor sub system wrapper //----------------------------------------------------------------------------- // // ************************************************************************ // ** DISCLAIMER OF LIABILITY ** // ** ** // ** This file contains proprietary and confidential information of ** // ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** // ** from Xilinx, and may be used, copied and/or diSCLosed only ** // ** pursuant to the terms of a valid license agreement with Xilinx. ** // ** ** // ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** // ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** // ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** // ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** // ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** // ** does not warrant that functions included in the Materials will ** // ** meet the requirements of Licensee, or that the operation of the ** // ** Materials will be uninterrupted or error-free, or that defects ** // ** in the Materials will be corrected. Furthermore, Xilinx does ** // ** not warrant or make any representations regarding use, or the ** // ** results of the use, of the Materials in terms of correctness, ** // ** accuracy, reliability or otherwise. ** // ** ** // ** Xilinx products are not designed or intended to be fail-safe, ** // ** or for use in any application requiring fail-safe performance, ** // ** such as life-support or safety devices or systems, Class III ** // ** medical devices, nuclear facilities, applications related to ** // ** the deployment of airbags, or any other applications that could ** // ** lead to death, personal injury or severe property or ** // ** environmental damage (individually and collectively, "critical ** // ** applications"). Customer assumes the sole risk and liability ** // ** of any use of Xilinx products in critical applications, ** // ** subject only to applicable laws and regulations governing ** // ** limitations on product liability. ** // ** ** // ** Copyright 2010 Xilinx, Inc. ** // ** All rights reserved. ** // ** ** // ** This disclaimer and copyright notice must be retained as part ** // ** of this file at all times. ** // ************************************************************************ // //----------------------------------------------------------------------------- // Filename: processing_system7_v5_5_processing_system7.v // Version: v1.00.a // Description: This is the wrapper file for PSS. //----------------------------------------------------------------------------- // Structure: This section shows the hierarchical structure of // pss_wrapper. // // --processing_system7_v5_5_processing_system7.v // --PS7.v - Unisim component //----------------------------------------------------------------------------- // Author: SD // // History: // // SD 09/20/11 -- First version // ~~~~~~ // Created the first version v2.00.a // ^^^^^^ //------------------------------------------------------------------------------ // ^^^^^^ // SR 11/25/11 -- v3.00.a version // ~~~~~~~ // Key changes are // 1. Changed all clock, reset and clktrig ports to be individual // signals instead of vectors. This is required for modeling of tools. // 2. Interrupts are now defined as individual signals as well. // 3. Added Clk buffer logic for FCLK_CLK // 4. Includes the ACP related changes done // // TODO: // 1. C_NUM_F2P_INTR_INPUTS needs to have control on the // number of interrupt ports connected for IRQ_F2P. // //------------------------------------------------------------------------------ // ^^^^^^ // KP 12/07/11 -- v3.00.a version // ~~~~~~~ // Key changes are // C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P //------------------------------------------------------------------------------ // ^^^^^^ // NR 12/09/11 -- v3.00.a version // ~~~~~~~ // Key changes are // C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated // to STRING and fix for CR 640523 //------------------------------------------------------------------------------ // ^^^^^^ // NR 12/13/11 -- v3.00.a version // ~~~~~~~ // Key changes are // Updated IRQ_F2P logic to address CR 641523. //------------------------------------------------------------------------------ // ^^^^^^ // NR 02/01/12 -- v3.01.a version // ~~~~~~~ // Key changes are // Updated SDIO logic to address CR 636210. // | // Added C_PS7_SI_REV parameter to track SI Rev // Removed compress/decompress logic to address CR 642527. //------------------------------------------------------------------------------ // ^^^^^^ // NR 02/27/12 -- v3.01.a version // ~~~~~~~ // Key changes are // TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual // ports as fix for CR 646379 //------------------------------------------------------------------------------ // ^^^^^^ // NR 03/05/12 -- v3.01.a version // ~~~~~~~ // Key changes are // Added/updated compress/decompress logic to address 648393 //------------------------------------------------------------------------------ // ^^^^^^ // NR 03/14/12 -- v4.00.a version // ~~~~~~~ // Unused parameters deleted CR 651120 // Addressed CR 651751 //------------------------------------------------------------------------------ // ^^^^^^ // NR 04/17/12 -- v4.01.a version // ~~~~~~~ // Added FTM trace buffer functionality // Added support for ACP AxUSER ports local update //------------------------------------------------------------------------------ // ^^^^^^ // VR 05/18/12 -- v4.01.a version // ~~~~~~~ // Fixed CR#659157 //------------------------------------------------------------------------------ // ^^^^^^ // VR 07/25/12 -- v4.01.a version // ~~~~~~~ // Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model // Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model //------------------------------------------------------------------------------ // ^^^^^^ // VR 11/06/12 -- v5.00 version // ~~~~~~~ // CR #682573 // Added BIBUF to fixed IO ports and IBUF to fixed input ports //------------------------------------------------------------------------------ (*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *) (* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=533.333313, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=14, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=49.5, PCW_UIPARAM_DDR_T_RAS_MIN=36.0, PCW_UIPARAM_DDR_T_FAW=45.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.025, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.028, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.009, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.061, PCW_UIPARAM_DDR_BOARD_DELAY0=0.41, PCW_UIPARAM_DDR_BOARD_DELAY1=0.411, PCW_UIPARAM_DDR_BOARD_DELAY2=0.341, PCW_UIPARAM_DDR_BOARD_DELAY3=0.358, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=68.4725, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=71.086, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=66.794, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=108.7385, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=64.1705, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=63.686, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=68.46, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=105.4895, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666667, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200.000000, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100.000000, PCW_FPGA1_PERIPHERAL_FREQMHZ=150.000000, PCW_FPGA2_PERIPHERAL_FREQMHZ=50.000000, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=32, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1066.667, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_FTM_CTI_IN0=DISABLED, PCW_FTM_CTI_IN1=DISABLED, PCW_FTM_CTI_IN2=DISABLED, PCW_FTM_CTI_IN3=DISABLED, PCW_FTM_CTI_OUT0=DISABLED, PCW_FTM_CTI_OUT1=DISABLED, PCW_FTM_CTI_OUT2=DISABLED, PCW_FTM_CTI_OUT3=DISABLED, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41J128M16 HA-15E, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=1, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 47, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=MIO 46, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=EMIO, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=0, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=2, PCW_NOR_SRAM_CS0_T_RC=2, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=2, PCW_NOR_SRAM_CS1_T_RC=2, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=2, PCW_NOR_CS0_T_RC=2, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=2, PCW_NOR_CS1_T_RC=2, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=2, PCW_NAND_CYCLES_T_RC=2 }" *) //(* HW_HANDOFF = "design_gpio_led_processing_system7_0_0.hwdef" *) module processing_system7_v5_5_processing_system7 #( parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1, parameter integer C_S_AXI_ACP_ARUSER_VAL = 31, parameter integer C_S_AXI_ACP_AWUSER_VAL = 31, parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12, parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12, parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1, parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1, parameter integer C_M_AXI_GP0_ID_WIDTH = 12, parameter integer C_M_AXI_GP1_ID_WIDTH = 12, parameter integer C_S_AXI_GP0_ID_WIDTH = 6, parameter integer C_S_AXI_GP1_ID_WIDTH = 6, parameter integer C_S_AXI_HP0_ID_WIDTH = 6, parameter integer C_S_AXI_HP1_ID_WIDTH = 6, parameter integer C_S_AXI_HP2_ID_WIDTH = 6, parameter integer C_S_AXI_HP3_ID_WIDTH = 6, parameter integer C_S_AXI_ACP_ID_WIDTH = 3, parameter integer C_S_AXI_HP0_DATA_WIDTH = 64, parameter integer C_S_AXI_HP1_DATA_WIDTH = 64, parameter integer C_S_AXI_HP2_DATA_WIDTH = 64, parameter integer C_S_AXI_HP3_DATA_WIDTH = 64, parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0, parameter integer C_NUM_F2P_INTR_INPUTS = 1, parameter C_FCLK_CLK0_BUF = "TRUE", parameter C_FCLK_CLK1_BUF = "TRUE", parameter C_FCLK_CLK2_BUF = "TRUE", parameter C_FCLK_CLK3_BUF = "TRUE", parameter integer C_EMIO_GPIO_WIDTH = 64, parameter integer C_INCLUDE_TRACE_BUFFER = 0, parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128, parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12, parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0, parameter integer C_TRACE_PIPELINE_WIDTH = 8, parameter C_PS7_SI_REV = "PRODUCTION", parameter integer C_EN_EMIO_ENET0 = 0, parameter integer C_EN_EMIO_ENET1 = 0, parameter integer C_EN_EMIO_TRACE = 0, parameter integer C_DQ_WIDTH = 32, parameter integer C_DQS_WIDTH = 4, parameter integer C_DM_WIDTH = 4, parameter integer C_MIO_PRIMITIVE = 54, parameter C_PACKAGE_NAME = "clg484", parameter C_IRQ_F2P_MODE = "DIRECT", parameter C_TRACE_INTERNAL_WIDTH = 32, parameter integer C_EN_EMIO_PJTAG = 0, // Enable and disable AFI Secure transaction parameter C_USE_AXI_NONSECURE = 0, //parameters for HP enable ports parameter C_USE_S_AXI_HP0 = 0, parameter C_USE_S_AXI_HP1 = 0, parameter C_USE_S_AXI_HP2 = 0, parameter C_USE_S_AXI_HP3 = 0, //parameters for GP and ACP enable ports */ parameter C_USE_M_AXI_GP0 = 0, parameter C_USE_M_AXI_GP1 = 0, parameter C_USE_S_AXI_GP0 = 0, parameter C_USE_S_AXI_GP1 = 0, parameter C_USE_S_AXI_ACP = 0 ) ( //FMIO ========================================= //FMIO CAN0 output CAN0_PHY_TX, input CAN0_PHY_RX, //FMIO CAN1 output CAN1_PHY_TX, input CAN1_PHY_RX, //FMIO ENET0 output reg ENET0_GMII_TX_EN = 'b0, output reg ENET0_GMII_TX_ER = 'b0, output ENET0_MDIO_MDC, output ENET0_MDIO_O, output ENET0_MDIO_T, output ENET0_PTP_DELAY_REQ_RX, output ENET0_PTP_DELAY_REQ_TX, output ENET0_PTP_PDELAY_REQ_RX, output ENET0_PTP_PDELAY_REQ_TX, output ENET0_PTP_PDELAY_RESP_RX, output ENET0_PTP_PDELAY_RESP_TX, output ENET0_PTP_SYNC_FRAME_RX, output ENET0_PTP_SYNC_FRAME_TX, output ENET0_SOF_RX, output ENET0_SOF_TX, output reg [7:0] ENET0_GMII_TXD, input ENET0_GMII_COL, input ENET0_GMII_CRS, input ENET0_GMII_RX_CLK, input ENET0_GMII_RX_DV, input ENET0_GMII_RX_ER, input ENET0_GMII_TX_CLK, input ENET0_MDIO_I, input ENET0_EXT_INTIN, input [7:0] ENET0_GMII_RXD, //FMIO ENET1 output reg ENET1_GMII_TX_EN = 'b0, output reg ENET1_GMII_TX_ER = 'b0, output ENET1_MDIO_MDC, output ENET1_MDIO_O, output ENET1_MDIO_T, output ENET1_PTP_DELAY_REQ_RX, output ENET1_PTP_DELAY_REQ_TX, output ENET1_PTP_PDELAY_REQ_RX, output ENET1_PTP_PDELAY_REQ_TX, output ENET1_PTP_PDELAY_RESP_RX, output ENET1_PTP_PDELAY_RESP_TX, output ENET1_PTP_SYNC_FRAME_RX, output ENET1_PTP_SYNC_FRAME_TX, output ENET1_SOF_RX, output ENET1_SOF_TX, output reg [7:0] ENET1_GMII_TXD, input ENET1_GMII_COL, input ENET1_GMII_CRS, input ENET1_GMII_RX_CLK, input ENET1_GMII_RX_DV, input ENET1_GMII_RX_ER, input ENET1_GMII_TX_CLK, input ENET1_MDIO_I, input ENET1_EXT_INTIN, input [7:0] ENET1_GMII_RXD, //FMIO GPIO input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I, output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O, output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T, //FMIO I2C0 input I2C0_SDA_I, output I2C0_SDA_O, output I2C0_SDA_T, input I2C0_SCL_I, output I2C0_SCL_O, output I2C0_SCL_T, //FMIO I2C1 input I2C1_SDA_I, output I2C1_SDA_O, output I2C1_SDA_T, input I2C1_SCL_I, output I2C1_SCL_O, output I2C1_SCL_T, //FMIO PJTAG input PJTAG_TCK, input PJTAG_TMS, input PJTAG_TDI, output PJTAG_TDO, //FMIO SDIO0 output SDIO0_CLK, input SDIO0_CLK_FB, output SDIO0_CMD_O, input SDIO0_CMD_I, output SDIO0_CMD_T, input [3:0] SDIO0_DATA_I, output [3:0] SDIO0_DATA_O, output [3:0] SDIO0_DATA_T, output SDIO0_LED, input SDIO0_CDN, input SDIO0_WP, output SDIO0_BUSPOW, output [2:0] SDIO0_BUSVOLT, //FMIO SDIO1 output SDIO1_CLK, input SDIO1_CLK_FB, output SDIO1_CMD_O, input SDIO1_CMD_I, output SDIO1_CMD_T, input [3:0] SDIO1_DATA_I, output [3:0] SDIO1_DATA_O, output [3:0] SDIO1_DATA_T, output SDIO1_LED, input SDIO1_CDN, input SDIO1_WP, output SDIO1_BUSPOW, output [2:0] SDIO1_BUSVOLT, //FMIO SPI0 input SPI0_SCLK_I, output SPI0_SCLK_O, output SPI0_SCLK_T, input SPI0_MOSI_I, output SPI0_MOSI_O, output SPI0_MOSI_T, input SPI0_MISO_I, output SPI0_MISO_O, output SPI0_MISO_T, input SPI0_SS_I, output SPI0_SS_O, output SPI0_SS1_O, output SPI0_SS2_O, output SPI0_SS_T, //FMIO SPI1 input SPI1_SCLK_I, output SPI1_SCLK_O, output SPI1_SCLK_T, input SPI1_MOSI_I, output SPI1_MOSI_O, output SPI1_MOSI_T, input SPI1_MISO_I, output SPI1_MISO_O, output SPI1_MISO_T, input SPI1_SS_I, output SPI1_SS_O, output SPI1_SS1_O, output SPI1_SS2_O, output SPI1_SS_T, //FMIO UART0 output UART0_DTRN, output UART0_RTSN, output UART0_TX, input UART0_CTSN, input UART0_DCDN, input UART0_DSRN, input UART0_RIN, input UART0_RX, //FMIO UART1 output UART1_DTRN, output UART1_RTSN, output UART1_TX, input UART1_CTSN, input UART1_DCDN, input UART1_DSRN, input UART1_RIN, input UART1_RX, //FMIO TTC0 output TTC0_WAVE0_OUT, output TTC0_WAVE1_OUT, output TTC0_WAVE2_OUT, input TTC0_CLK0_IN, input TTC0_CLK1_IN, input TTC0_CLK2_IN, //FMIO TTC1 output TTC1_WAVE0_OUT, output TTC1_WAVE1_OUT, output TTC1_WAVE2_OUT, input TTC1_CLK0_IN, input TTC1_CLK1_IN, input TTC1_CLK2_IN, //WDT input WDT_CLK_IN, output WDT_RST_OUT, //FTPORT input TRACE_CLK, output TRACE_CTL, output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA, output reg TRACE_CLK_OUT, // USB output [1:0] USB0_PORT_INDCTL, output USB0_VBUS_PWRSELECT, input USB0_VBUS_PWRFAULT, output [1:0] USB1_PORT_INDCTL, output USB1_VBUS_PWRSELECT, input USB1_VBUS_PWRFAULT, input SRAM_INTIN, //AIO =================================================== //M_AXI_GP0 // -- Output output M_AXI_GP0_ARESETN, output M_AXI_GP0_ARVALID, output M_AXI_GP0_AWVALID, output M_AXI_GP0_BREADY, output M_AXI_GP0_RREADY, output M_AXI_GP0_WLAST, output M_AXI_GP0_WVALID, output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID, output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID, output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID, output [1:0] M_AXI_GP0_ARBURST, output [1:0] M_AXI_GP0_ARLOCK, output [2:0] M_AXI_GP0_ARSIZE, output [1:0] M_AXI_GP0_AWBURST, output [1:0] M_AXI_GP0_AWLOCK, output [2:0] M_AXI_GP0_AWSIZE, output [2:0] M_AXI_GP0_ARPROT, output [2:0] M_AXI_GP0_AWPROT, output [31:0] M_AXI_GP0_ARADDR, output [31:0] M_AXI_GP0_AWADDR, output [31:0] M_AXI_GP0_WDATA, output [3:0] M_AXI_GP0_ARCACHE, output [3:0] M_AXI_GP0_ARLEN, output [3:0] M_AXI_GP0_ARQOS, output [3:0] M_AXI_GP0_AWCACHE, output [3:0] M_AXI_GP0_AWLEN, output [3:0] M_AXI_GP0_AWQOS, output [3:0] M_AXI_GP0_WSTRB, // -- Input input M_AXI_GP0_ACLK, input M_AXI_GP0_ARREADY, input M_AXI_GP0_AWREADY, input M_AXI_GP0_BVALID, input M_AXI_GP0_RLAST, input M_AXI_GP0_RVALID, input M_AXI_GP0_WREADY, input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID, input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID, input [1:0] M_AXI_GP0_BRESP, input [1:0] M_AXI_GP0_RRESP, input [31:0] M_AXI_GP0_RDATA, //M_AXI_GP1 // -- Output output M_AXI_GP1_ARESETN, output M_AXI_GP1_ARVALID, output M_AXI_GP1_AWVALID, output M_AXI_GP1_BREADY, output M_AXI_GP1_RREADY, output M_AXI_GP1_WLAST, output M_AXI_GP1_WVALID, output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID, output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID, output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID, output [1:0] M_AXI_GP1_ARBURST, output [1:0] M_AXI_GP1_ARLOCK, output [2:0] M_AXI_GP1_ARSIZE, output [1:0] M_AXI_GP1_AWBURST, output [1:0] M_AXI_GP1_AWLOCK, output [2:0] M_AXI_GP1_AWSIZE, output [2:0] M_AXI_GP1_ARPROT, output [2:0] M_AXI_GP1_AWPROT, output [31:0] M_AXI_GP1_ARADDR, output [31:0] M_AXI_GP1_AWADDR, output [31:0] M_AXI_GP1_WDATA, output [3:0] M_AXI_GP1_ARCACHE, output [3:0] M_AXI_GP1_ARLEN, output [3:0] M_AXI_GP1_ARQOS, output [3:0] M_AXI_GP1_AWCACHE, output [3:0] M_AXI_GP1_AWLEN, output [3:0] M_AXI_GP1_AWQOS, output [3:0] M_AXI_GP1_WSTRB, // -- Input input M_AXI_GP1_ACLK, input M_AXI_GP1_ARREADY, input M_AXI_GP1_AWREADY, input M_AXI_GP1_BVALID, input M_AXI_GP1_RLAST, input M_AXI_GP1_RVALID, input M_AXI_GP1_WREADY, input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID, input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID, input [1:0] M_AXI_GP1_BRESP, input [1:0] M_AXI_GP1_RRESP, input [31:0] M_AXI_GP1_RDATA, // S_AXI_GP0 // -- Output output S_AXI_GP0_ARESETN, output S_AXI_GP0_ARREADY, output S_AXI_GP0_AWREADY, output S_AXI_GP0_BVALID, output S_AXI_GP0_RLAST, output S_AXI_GP0_RVALID, output S_AXI_GP0_WREADY, output [1:0] S_AXI_GP0_BRESP, output [1:0] S_AXI_GP0_RRESP, output [31:0] S_AXI_GP0_RDATA, output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID, output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID, // -- Input input S_AXI_GP0_ACLK, input S_AXI_GP0_ARVALID, input S_AXI_GP0_AWVALID, input S_AXI_GP0_BREADY, input S_AXI_GP0_RREADY, input S_AXI_GP0_WLAST, input S_AXI_GP0_WVALID, input [1:0] S_AXI_GP0_ARBURST, input [1:0] S_AXI_GP0_ARLOCK, input [2:0] S_AXI_GP0_ARSIZE, input [1:0] S_AXI_GP0_AWBURST, input [1:0] S_AXI_GP0_AWLOCK, input [2:0] S_AXI_GP0_AWSIZE, input [2:0] S_AXI_GP0_ARPROT, input [2:0] S_AXI_GP0_AWPROT, input [31:0] S_AXI_GP0_ARADDR, input [31:0] S_AXI_GP0_AWADDR, input [31:0] S_AXI_GP0_WDATA, input [3:0] S_AXI_GP0_ARCACHE, input [3:0] S_AXI_GP0_ARLEN, input [3:0] S_AXI_GP0_ARQOS, input [3:0] S_AXI_GP0_AWCACHE, input [3:0] S_AXI_GP0_AWLEN, input [3:0] S_AXI_GP0_AWQOS, input [3:0] S_AXI_GP0_WSTRB, input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID, input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID, input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID, // S_AXI_GP1 // -- Output output S_AXI_GP1_ARESETN, output S_AXI_GP1_ARREADY, output S_AXI_GP1_AWREADY, output S_AXI_GP1_BVALID, output S_AXI_GP1_RLAST, output S_AXI_GP1_RVALID, output S_AXI_GP1_WREADY, output [1:0] S_AXI_GP1_BRESP, output [1:0] S_AXI_GP1_RRESP, output [31:0] S_AXI_GP1_RDATA, output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID, output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID, // -- Input input S_AXI_GP1_ACLK, input S_AXI_GP1_ARVALID, input S_AXI_GP1_AWVALID, input S_AXI_GP1_BREADY, input S_AXI_GP1_RREADY, input S_AXI_GP1_WLAST, input S_AXI_GP1_WVALID, input [1:0] S_AXI_GP1_ARBURST, input [1:0] S_AXI_GP1_ARLOCK, input [2:0] S_AXI_GP1_ARSIZE, input [1:0] S_AXI_GP1_AWBURST, input [1:0] S_AXI_GP1_AWLOCK, input [2:0] S_AXI_GP1_AWSIZE, input [2:0] S_AXI_GP1_ARPROT, input [2:0] S_AXI_GP1_AWPROT, input [31:0] S_AXI_GP1_ARADDR, input [31:0] S_AXI_GP1_AWADDR, input [31:0] S_AXI_GP1_WDATA, input [3:0] S_AXI_GP1_ARCACHE, input [3:0] S_AXI_GP1_ARLEN, input [3:0] S_AXI_GP1_ARQOS, input [3:0] S_AXI_GP1_AWCACHE, input [3:0] S_AXI_GP1_AWLEN, input [3:0] S_AXI_GP1_AWQOS, input [3:0] S_AXI_GP1_WSTRB, input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID, input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID, input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID, //S_AXI_ACP // -- Output output S_AXI_ACP_ARESETN, output S_AXI_ACP_ARREADY, output S_AXI_ACP_AWREADY, output S_AXI_ACP_BVALID, output S_AXI_ACP_RLAST, output S_AXI_ACP_RVALID, output S_AXI_ACP_WREADY, output [1:0] S_AXI_ACP_BRESP, output [1:0] S_AXI_ACP_RRESP, output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID, output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID, output [63:0] S_AXI_ACP_RDATA, // -- Input input S_AXI_ACP_ACLK, input S_AXI_ACP_ARVALID, input S_AXI_ACP_AWVALID, input S_AXI_ACP_BREADY, input S_AXI_ACP_RREADY, input S_AXI_ACP_WLAST, input S_AXI_ACP_WVALID, input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID, input [2:0] S_AXI_ACP_ARPROT, input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID, input [2:0] S_AXI_ACP_AWPROT, input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID, input [31:0] S_AXI_ACP_ARADDR, input [31:0] S_AXI_ACP_AWADDR, input [3:0] S_AXI_ACP_ARCACHE, input [3:0] S_AXI_ACP_ARLEN, input [3:0] S_AXI_ACP_ARQOS, input [3:0] S_AXI_ACP_AWCACHE, input [3:0] S_AXI_ACP_AWLEN, input [3:0] S_AXI_ACP_AWQOS, input [1:0] S_AXI_ACP_ARBURST, input [1:0] S_AXI_ACP_ARLOCK, input [2:0] S_AXI_ACP_ARSIZE, input [1:0] S_AXI_ACP_AWBURST, input [1:0] S_AXI_ACP_AWLOCK, input [2:0] S_AXI_ACP_AWSIZE, input [4:0] S_AXI_ACP_ARUSER, input [4:0] S_AXI_ACP_AWUSER, input [63:0] S_AXI_ACP_WDATA, input [7:0] S_AXI_ACP_WSTRB, // S_AXI_HP_0 // -- Output output S_AXI_HP0_ARESETN, output S_AXI_HP0_ARREADY, output S_AXI_HP0_AWREADY, output S_AXI_HP0_BVALID, output S_AXI_HP0_RLAST, output S_AXI_HP0_RVALID, output S_AXI_HP0_WREADY, output [1:0] S_AXI_HP0_BRESP, output [1:0] S_AXI_HP0_RRESP, output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID, output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID, output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA, output [7:0] S_AXI_HP0_RCOUNT, output [7:0] S_AXI_HP0_WCOUNT, output [2:0] S_AXI_HP0_RACOUNT, output [5:0] S_AXI_HP0_WACOUNT, // -- Input input S_AXI_HP0_ACLK, input S_AXI_HP0_ARVALID, input S_AXI_HP0_AWVALID, input S_AXI_HP0_BREADY, input S_AXI_HP0_RDISSUECAP1_EN, input S_AXI_HP0_RREADY, input S_AXI_HP0_WLAST, input S_AXI_HP0_WRISSUECAP1_EN, input S_AXI_HP0_WVALID, input [1:0] S_AXI_HP0_ARBURST, input [1:0] S_AXI_HP0_ARLOCK, input [2:0] S_AXI_HP0_ARSIZE, input [1:0] S_AXI_HP0_AWBURST, input [1:0] S_AXI_HP0_AWLOCK, input [2:0] S_AXI_HP0_AWSIZE, input [2:0] S_AXI_HP0_ARPROT, input [2:0] S_AXI_HP0_AWPROT, input [31:0] S_AXI_HP0_ARADDR, input [31:0] S_AXI_HP0_AWADDR, input [3:0] S_AXI_HP0_ARCACHE, input [3:0] S_AXI_HP0_ARLEN, input [3:0] S_AXI_HP0_ARQOS, input [3:0] S_AXI_HP0_AWCACHE, input [3:0] S_AXI_HP0_AWLEN, input [3:0] S_AXI_HP0_AWQOS, input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID, input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID, input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID, input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA, input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB, // S_AXI_HP1 // -- Output output S_AXI_HP1_ARESETN, output S_AXI_HP1_ARREADY, output S_AXI_HP1_AWREADY, output S_AXI_HP1_BVALID, output S_AXI_HP1_RLAST, output S_AXI_HP1_RVALID, output S_AXI_HP1_WREADY, output [1:0] S_AXI_HP1_BRESP, output [1:0] S_AXI_HP1_RRESP, output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID, output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID, output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA, output [7:0] S_AXI_HP1_RCOUNT, output [7:0] S_AXI_HP1_WCOUNT, output [2:0] S_AXI_HP1_RACOUNT, output [5:0] S_AXI_HP1_WACOUNT, // -- Input input S_AXI_HP1_ACLK, input S_AXI_HP1_ARVALID, input S_AXI_HP1_AWVALID, input S_AXI_HP1_BREADY, input S_AXI_HP1_RDISSUECAP1_EN, input S_AXI_HP1_RREADY, input S_AXI_HP1_WLAST, input S_AXI_HP1_WRISSUECAP1_EN, input S_AXI_HP1_WVALID, input [1:0] S_AXI_HP1_ARBURST, input [1:0] S_AXI_HP1_ARLOCK, input [2:0] S_AXI_HP1_ARSIZE, input [1:0] S_AXI_HP1_AWBURST, input [1:0] S_AXI_HP1_AWLOCK, input [2:0] S_AXI_HP1_AWSIZE, input [2:0] S_AXI_HP1_ARPROT, input [2:0] S_AXI_HP1_AWPROT, input [31:0] S_AXI_HP1_ARADDR, input [31:0] S_AXI_HP1_AWADDR, input [3:0] S_AXI_HP1_ARCACHE, input [3:0] S_AXI_HP1_ARLEN, input [3:0] S_AXI_HP1_ARQOS, input [3:0] S_AXI_HP1_AWCACHE, input [3:0] S_AXI_HP1_AWLEN, input [3:0] S_AXI_HP1_AWQOS, input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID, input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID, input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID, input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA, input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB, // S_AXI_HP2 // -- Output output S_AXI_HP2_ARESETN, output S_AXI_HP2_ARREADY, output S_AXI_HP2_AWREADY, output S_AXI_HP2_BVALID, output S_AXI_HP2_RLAST, output S_AXI_HP2_RVALID, output S_AXI_HP2_WREADY, output [1:0] S_AXI_HP2_BRESP, output [1:0] S_AXI_HP2_RRESP, output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID, output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID, output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA, output [7:0] S_AXI_HP2_RCOUNT, output [7:0] S_AXI_HP2_WCOUNT, output [2:0] S_AXI_HP2_RACOUNT, output [5:0] S_AXI_HP2_WACOUNT, // -- Input input S_AXI_HP2_ACLK, input S_AXI_HP2_ARVALID, input S_AXI_HP2_AWVALID, input S_AXI_HP2_BREADY, input S_AXI_HP2_RDISSUECAP1_EN, input S_AXI_HP2_RREADY, input S_AXI_HP2_WLAST, input S_AXI_HP2_WRISSUECAP1_EN, input S_AXI_HP2_WVALID, input [1:0] S_AXI_HP2_ARBURST, input [1:0] S_AXI_HP2_ARLOCK, input [2:0] S_AXI_HP2_ARSIZE, input [1:0] S_AXI_HP2_AWBURST, input [1:0] S_AXI_HP2_AWLOCK, input [2:0] S_AXI_HP2_AWSIZE, input [2:0] S_AXI_HP2_ARPROT, input [2:0] S_AXI_HP2_AWPROT, input [31:0] S_AXI_HP2_ARADDR, input [31:0] S_AXI_HP2_AWADDR, input [3:0] S_AXI_HP2_ARCACHE, input [3:0] S_AXI_HP2_ARLEN, input [3:0] S_AXI_HP2_ARQOS, input [3:0] S_AXI_HP2_AWCACHE, input [3:0] S_AXI_HP2_AWLEN, input [3:0] S_AXI_HP2_AWQOS, input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID, input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID, input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID, input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA, input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB, // S_AXI_HP_3 // -- Output output S_AXI_HP3_ARESETN, output S_AXI_HP3_ARREADY, output S_AXI_HP3_AWREADY, output S_AXI_HP3_BVALID, output S_AXI_HP3_RLAST, output S_AXI_HP3_RVALID, output S_AXI_HP3_WREADY, output [1:0] S_AXI_HP3_BRESP, output [1:0] S_AXI_HP3_RRESP, output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID, output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID, output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA, output [7:0] S_AXI_HP3_RCOUNT, output [7:0] S_AXI_HP3_WCOUNT, output [2:0] S_AXI_HP3_RACOUNT, output [5:0] S_AXI_HP3_WACOUNT, // -- Input input S_AXI_HP3_ACLK, input S_AXI_HP3_ARVALID, input S_AXI_HP3_AWVALID, input S_AXI_HP3_BREADY, input S_AXI_HP3_RDISSUECAP1_EN, input S_AXI_HP3_RREADY, input S_AXI_HP3_WLAST, input S_AXI_HP3_WRISSUECAP1_EN, input S_AXI_HP3_WVALID, input [1:0] S_AXI_HP3_ARBURST, input [1:0] S_AXI_HP3_ARLOCK, input [2:0] S_AXI_HP3_ARSIZE, input [1:0] S_AXI_HP3_AWBURST, input [1:0] S_AXI_HP3_AWLOCK, input [2:0] S_AXI_HP3_AWSIZE, input [2:0] S_AXI_HP3_ARPROT, input [2:0] S_AXI_HP3_AWPROT, input [31:0] S_AXI_HP3_ARADDR, input [31:0] S_AXI_HP3_AWADDR, input [3:0] S_AXI_HP3_ARCACHE, input [3:0] S_AXI_HP3_ARLEN, input [3:0] S_AXI_HP3_ARQOS, input [3:0] S_AXI_HP3_AWCACHE, input [3:0] S_AXI_HP3_AWLEN, input [3:0] S_AXI_HP3_AWQOS, input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID, input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID, input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID, input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA, input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB, //FIO ======================================== //IRQ //output [28:0] IRQ_P2F, output IRQ_P2F_DMAC_ABORT , output IRQ_P2F_DMAC0, output IRQ_P2F_DMAC1, output IRQ_P2F_DMAC2, output IRQ_P2F_DMAC3, output IRQ_P2F_DMAC4, output IRQ_P2F_DMAC5, output IRQ_P2F_DMAC6, output IRQ_P2F_DMAC7, output IRQ_P2F_SMC, output IRQ_P2F_QSPI, output IRQ_P2F_CTI, output IRQ_P2F_GPIO, output IRQ_P2F_USB0, output IRQ_P2F_ENET0, output IRQ_P2F_ENET_WAKE0, output IRQ_P2F_SDIO0, output IRQ_P2F_I2C0, output IRQ_P2F_SPI0, output IRQ_P2F_UART0, output IRQ_P2F_CAN0, output IRQ_P2F_USB1, output IRQ_P2F_ENET1, output IRQ_P2F_ENET_WAKE1, output IRQ_P2F_SDIO1, output IRQ_P2F_I2C1, output IRQ_P2F_SPI1, output IRQ_P2F_UART1, output IRQ_P2F_CAN1, input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P, input Core0_nFIQ, input Core0_nIRQ, input Core1_nFIQ, input Core1_nIRQ, //DMA output [1:0] DMA0_DATYPE, output DMA0_DAVALID, output DMA0_DRREADY, output DMA0_RSTN, output [1:0] DMA1_DATYPE, output DMA1_DAVALID, output DMA1_DRREADY, output DMA1_RSTN, output [1:0] DMA2_DATYPE, output DMA2_DAVALID, output DMA2_DRREADY, output DMA2_RSTN, output [1:0] DMA3_DATYPE, output DMA3_DAVALID, output DMA3_DRREADY, output DMA3_RSTN, input DMA0_ACLK, input DMA0_DAREADY, input DMA0_DRLAST, input DMA0_DRVALID, input DMA1_ACLK, input DMA1_DAREADY, input DMA1_DRLAST, input DMA1_DRVALID, input DMA2_ACLK, input DMA2_DAREADY, input DMA2_DRLAST, input DMA2_DRVALID, input DMA3_ACLK, input DMA3_DAREADY, input DMA3_DRLAST, input DMA3_DRVALID, input [1:0] DMA0_DRTYPE, input [1:0] DMA1_DRTYPE, input [1:0] DMA2_DRTYPE, input [1:0] DMA3_DRTYPE, //FCLK output FCLK_CLK3, output FCLK_CLK2, output FCLK_CLK1, output FCLK_CLK0, input FCLK_CLKTRIG3_N, input FCLK_CLKTRIG2_N, input FCLK_CLKTRIG1_N, input FCLK_CLKTRIG0_N, output FCLK_RESET3_N, output FCLK_RESET2_N, output FCLK_RESET1_N, output FCLK_RESET0_N, //FTMD input [31:0] FTMD_TRACEIN_DATA, input FTMD_TRACEIN_VALID, input FTMD_TRACEIN_CLK, input [3:0] FTMD_TRACEIN_ATID, //FTMT input FTMT_F2P_TRIG_0, output FTMT_F2P_TRIGACK_0, input FTMT_F2P_TRIG_1, output FTMT_F2P_TRIGACK_1, input FTMT_F2P_TRIG_2, output FTMT_F2P_TRIGACK_2, input FTMT_F2P_TRIG_3, output FTMT_F2P_TRIGACK_3, input [31:0] FTMT_F2P_DEBUG, input FTMT_P2F_TRIGACK_0, output FTMT_P2F_TRIG_0, input FTMT_P2F_TRIGACK_1, output FTMT_P2F_TRIG_1, input FTMT_P2F_TRIGACK_2, output FTMT_P2F_TRIG_2, input FTMT_P2F_TRIGACK_3, output FTMT_P2F_TRIG_3, output [31:0] FTMT_P2F_DEBUG, //FIDLE input FPGA_IDLE_N, //EVENT output EVENT_EVENTO, output [1:0] EVENT_STANDBYWFE, output [1:0] EVENT_STANDBYWFI, input EVENT_EVENTI, //DARB input [3:0] DDR_ARB, inout [C_MIO_PRIMITIVE - 1:0] MIO, //DDR inout DDR_CAS_n, // CASB inout DDR_CKE, // CKE inout DDR_Clk_n, // CKN inout DDR_Clk, // CKP inout DDR_CS_n, // CSB inout DDR_DRSTB, // DDR_DRSTB inout DDR_ODT, // ODT inout DDR_RAS_n, // RASB inout DDR_WEB, inout [2:0] DDR_BankAddr, // BA inout [14:0] DDR_Addr, // A inout DDR_VRN, inout DDR_VRP, inout [C_DM_WIDTH - 1:0] DDR_DM, // DM inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP inout PS_SRSTB, // SRSTB inout PS_CLK, // CLK inout PS_PORB // PORB ); wire [11:0] M_AXI_GP0_AWID_FULL; wire [11:0] M_AXI_GP0_WID_FULL; wire [11:0] M_AXI_GP0_ARID_FULL; wire [11:0] M_AXI_GP0_BID_FULL; wire [11:0] M_AXI_GP0_RID_FULL; wire [11:0] M_AXI_GP1_AWID_FULL; wire [11:0] M_AXI_GP1_WID_FULL; wire [11:0] M_AXI_GP1_ARID_FULL; wire [11:0] M_AXI_GP1_BID_FULL; wire [11:0] M_AXI_GP1_RID_FULL; // ---------------------------------------- // Wires for connecting to the PS7 wire ENET0_GMII_TX_EN_i; wire ENET0_GMII_TX_ER_i; reg ENET0_GMII_COL_i; reg ENET0_GMII_CRS_i; reg ENET0_GMII_RX_DV_i; reg ENET0_GMII_RX_ER_i; reg [7:0] ENET0_GMII_RXD_i; wire [7:0] ENET0_GMII_TXD_i; wire ENET1_GMII_TX_EN_i; wire ENET1_GMII_TX_ER_i; reg ENET1_GMII_COL_i; reg ENET1_GMII_CRS_i; reg ENET1_GMII_RX_DV_i; reg ENET1_GMII_RX_ER_i; reg [7:0] ENET1_GMII_RXD_i; wire [7:0] ENET1_GMII_TXD_i; // Register declarations ////reg ENET0_GMII_TX_EN = 'b0; ////reg ENET0_GMII_TX_ER = 'b0; //reg ENET0_GMII_COL; //reg ENET0_GMII_CRS; //reg ENET0_GMII_RX_DV; //reg ENET0_GMII_RX_ER; //reg [7:0] ENET0_GMII_RXD; ////reg [7:0] ENET0_GMII_TXD; ////reg ENET1_GMII_TX_EN = 'b0; ////reg ENET1_GMII_TX_ER = 'b0; //reg ENET1_GMII_COL; //reg ENET1_GMII_CRS; //reg ENET1_GMII_RX_DV; //reg ENET1_GMII_RX_ER; //reg [7:0] ENET1_GMII_RXD; ////reg [7:0] ENET1_GMII_TXD; // ---------------------------------- reg [31:0] FTMD_TRACEIN_DATA_notracebuf; reg FTMD_TRACEIN_VALID_notracebuf; reg [3:0] FTMD_TRACEIN_ATID_notracebuf; wire [31:0] FTMD_TRACEIN_DATA_i; wire FTMD_TRACEIN_VALID_i; wire [3:0] FTMD_TRACEIN_ATID_i; wire [31:0] FTMD_TRACEIN_DATA_tracebuf; wire FTMD_TRACEIN_VALID_tracebuf; wire [3:0] FTMD_TRACEIN_ATID_tracebuf; wire [5:0] S_AXI_GP0_BID_out; wire [5:0] S_AXI_GP0_RID_out; wire [5:0] S_AXI_GP0_ARID_in; wire [5:0] S_AXI_GP0_AWID_in; wire [5:0] S_AXI_GP0_WID_in; wire [5:0] S_AXI_GP1_BID_out; wire [5:0] S_AXI_GP1_RID_out; wire [5:0] S_AXI_GP1_ARID_in; wire [5:0] S_AXI_GP1_AWID_in; wire [5:0] S_AXI_GP1_WID_in; wire [5:0] S_AXI_HP0_BID_out; wire [5:0] S_AXI_HP0_RID_out; wire [5:0] S_AXI_HP0_ARID_in; wire [5:0] S_AXI_HP0_AWID_in; wire [5:0] S_AXI_HP0_WID_in; wire [5:0] S_AXI_HP1_BID_out; wire [5:0] S_AXI_HP1_RID_out; wire [5:0] S_AXI_HP1_ARID_in; wire [5:0] S_AXI_HP1_AWID_in; wire [5:0] S_AXI_HP1_WID_in; wire [5:0] S_AXI_HP2_BID_out; wire [5:0] S_AXI_HP2_RID_out; wire [5:0] S_AXI_HP2_ARID_in; wire [5:0] S_AXI_HP2_AWID_in; wire [5:0] S_AXI_HP2_WID_in; wire [5:0] S_AXI_HP3_BID_out; wire [5:0] S_AXI_HP3_RID_out; wire [5:0] S_AXI_HP3_ARID_in; wire [5:0] S_AXI_HP3_AWID_in; wire [5:0] S_AXI_HP3_WID_in; wire [2:0] S_AXI_ACP_BID_out; wire [2:0] S_AXI_ACP_RID_out; wire [2:0] S_AXI_ACP_ARID_in; wire [2:0] S_AXI_ACP_AWID_in; wire [2:0] S_AXI_ACP_WID_in; wire [63:0] S_AXI_HP0_WDATA_in; wire [7:0] S_AXI_HP0_WSTRB_in; wire [63:0] S_AXI_HP0_RDATA_out; wire [63:0] S_AXI_HP1_WDATA_in; wire [7:0] S_AXI_HP1_WSTRB_in; wire [63:0] S_AXI_HP1_RDATA_out; wire [63:0] S_AXI_HP2_WDATA_in; wire [7:0] S_AXI_HP2_WSTRB_in; wire [63:0] S_AXI_HP2_RDATA_out; wire [63:0] S_AXI_HP3_WDATA_in; wire [7:0] S_AXI_HP3_WSTRB_in; wire [63:0] S_AXI_HP3_RDATA_out; wire [1:0] M_AXI_GP0_ARSIZE_i; wire [1:0] M_AXI_GP0_AWSIZE_i; wire [1:0] M_AXI_GP1_ARSIZE_i; wire [1:0] M_AXI_GP1_AWSIZE_i; wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W; wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W; wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W; wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W; wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W; wire SAXIACPARREADY_W; wire SAXIACPAWREADY_W; wire SAXIACPBVALID_W; wire SAXIACPRLAST_W; wire SAXIACPRVALID_W; wire SAXIACPWREADY_W; wire [1:0] SAXIACPBRESP_W; wire [1:0] SAXIACPRRESP_W; wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID; wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID; wire [63:0] SAXIACPRDATA_W; wire S_AXI_ATC_ARVALID; wire S_AXI_ATC_AWVALID; wire S_AXI_ATC_BREADY; wire S_AXI_ATC_RREADY; wire S_AXI_ATC_WLAST; wire S_AXI_ATC_WVALID; wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID; wire [2:0] S_AXI_ATC_ARPROT; wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID; wire [2:0] S_AXI_ATC_AWPROT; wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID; wire [31:0] S_AXI_ATC_ARADDR; wire [31:0] S_AXI_ATC_AWADDR; wire [3:0] S_AXI_ATC_ARCACHE; wire [3:0] S_AXI_ATC_ARLEN; wire [3:0] S_AXI_ATC_ARQOS; wire [3:0] S_AXI_ATC_AWCACHE; wire [3:0] S_AXI_ATC_AWLEN; wire [3:0] S_AXI_ATC_AWQOS; wire [1:0] S_AXI_ATC_ARBURST; wire [1:0] S_AXI_ATC_ARLOCK; wire [2:0] S_AXI_ATC_ARSIZE; wire [1:0] S_AXI_ATC_AWBURST; wire [1:0] S_AXI_ATC_AWLOCK; wire [2:0] S_AXI_ATC_AWSIZE; wire [4:0] S_AXI_ATC_ARUSER; wire [4:0] S_AXI_ATC_AWUSER; wire [63:0] S_AXI_ATC_WDATA; wire [7:0] S_AXI_ATC_WSTRB; wire SAXIACPARVALID_W; wire SAXIACPAWVALID_W; wire SAXIACPBREADY_W; wire SAXIACPRREADY_W; wire SAXIACPWLAST_W; wire SAXIACPWVALID_W; wire [2:0] SAXIACPARPROT_W; wire [2:0] SAXIACPAWPROT_W; wire [31:0] SAXIACPARADDR_W; wire [31:0] SAXIACPAWADDR_W; wire [3:0] SAXIACPARCACHE_W; wire [3:0] SAXIACPARLEN_W; wire [3:0] SAXIACPARQOS_W; wire [3:0] SAXIACPAWCACHE_W; wire [3:0] SAXIACPAWLEN_W; wire [3:0] SAXIACPAWQOS_W; wire [1:0] SAXIACPARBURST_W; wire [1:0] SAXIACPARLOCK_W; wire [2:0] SAXIACPARSIZE_W; wire [1:0] SAXIACPAWBURST_W; wire [1:0] SAXIACPAWLOCK_W; wire [2:0] SAXIACPAWSIZE_W; wire [4:0] SAXIACPARUSER_W; wire [4:0] SAXIACPAWUSER_W; wire [63:0] SAXIACPWDATA_W; wire [7:0] SAXIACPWSTRB_W; // AxUSER signal update wire [4:0] param_aruser; wire [4:0] param_awuser; // Added to address CR 651751 wire [3:0] fclk_clktrig_gnd = 4'h0; wire [19:0] irq_f2p_i; wire [15:0] irq_f2p_null = 16'h0000; // EMIO I2C0 wire I2C0_SDA_T_n; wire I2C0_SCL_T_n; // EMIO I2C1 wire I2C1_SDA_T_n; wire I2C1_SCL_T_n; // EMIO SPI0 wire SPI0_SCLK_T_n; wire SPI0_MOSI_T_n; wire SPI0_MISO_T_n; wire SPI0_SS_T_n; // EMIO SPI1 wire SPI1_SCLK_T_n; wire SPI1_MOSI_T_n; wire SPI1_MISO_T_n; wire SPI1_SS_T_n; // EMIO GEM0 wire ENET0_MDIO_T_n; // EMIO GEM1 wire ENET1_MDIO_T_n; // EMIO GPIO wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n; wire [63:0] gpio_out_t_n; wire [63:0] gpio_out; wire [63:0] gpio_in63_0; //For Clock buffering wire [3:0] FCLK_CLK_unbuffered; wire [3:0] FCLK_CLK_buffered; wire FCLK_CLK0_temp; // EMIO PJTAG wire PJTAG_TDO_O; wire PJTAG_TDO_T; wire PJTAG_TDO_T_n; // EMIO SDIO0 wire SDIO0_CMD_T_n; wire [3:0] SDIO0_DATA_T_n; // EMIO SDIO1 wire SDIO1_CMD_T_n; wire [3:0] SDIO1_DATA_T_n; // buffered IO wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO; wire buffered_DDR_WEB; wire buffered_DDR_CAS_n; wire buffered_DDR_CKE; wire buffered_DDR_Clk_n; wire buffered_DDR_Clk; wire buffered_DDR_CS_n; wire buffered_DDR_DRSTB; wire buffered_DDR_ODT; wire buffered_DDR_RAS_n; wire [2:0] buffered_DDR_BankAddr; wire [14:0] buffered_DDR_Addr; wire buffered_DDR_VRN; wire buffered_DDR_VRP; wire [C_DM_WIDTH - 1:0] buffered_DDR_DM; wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ; wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n; wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS; wire buffered_PS_SRSTB; wire buffered_PS_CLK; wire buffered_PS_PORB; wire [31:0] TRACE_DATA_i; wire TRACE_CTL_i; (* keep = "true" *) reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0]; (* keep = "true" *) reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0]; // fixed CR #665394 integer j; generate if (C_EN_EMIO_TRACE == 1) begin always @(posedge TRACE_CLK) begin TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i; TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0]; for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j]; TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j]; end TRACE_CLK_OUT <= ~TRACE_CLK_OUT; end end else begin always @* begin TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0; TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0; for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin TRACE_CTL_PIPE[j-1] <= 1'b0; TRACE_DATA_PIPE[j-1] <= 1'b0; end TRACE_CLK_OUT <= 1'b0; end end endgenerate assign TRACE_CTL = TRACE_CTL_PIPE[0]; assign TRACE_DATA = TRACE_DATA_PIPE[0]; //irq_p2f // Updated IRQ_F2P logic to address CR 641523 generate if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]}; end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]}; end else begin : irq_f2p_select if (C_IRQ_F2P_MODE == "DIRECT") begin assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ, irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0], IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]}; end else begin assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ, IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0], irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]}; end end endgenerate assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]}; assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]}; assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]}; assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]}; // Compress Function // Modified as per CR 631955 //function [11:0] uncompress_id; // input [5:0] id; // begin // case (id[5:0]) // // dmac0 // 6'd1 : uncompress_id = 12'b010000_1000_00 ; // 6'd2 : uncompress_id = 12'b010000_0000_00 ; // 6'd3 : uncompress_id = 12'b010000_0001_00 ; // 6'd4 : uncompress_id = 12'b010000_0010_00 ; // 6'd5 : uncompress_id = 12'b010000_0011_00 ; // 6'd6 : uncompress_id = 12'b010000_0100_00 ; // 6'd7 : uncompress_id = 12'b010000_0101_00 ; // 6'd8 : uncompress_id = 12'b010000_0110_00 ; // 6'd9 : uncompress_id = 12'b010000_0111_00 ; // // ioum // 6'd10 : uncompress_id = 12'b0100000_000_01 ; // 6'd11 : uncompress_id = 12'b0100000_001_01 ; // 6'd12 : uncompress_id = 12'b0100000_010_01 ; // 6'd13 : uncompress_id = 12'b0100000_011_01 ; // 6'd14 : uncompress_id = 12'b0100000_100_01 ; // 6'd15 : uncompress_id = 12'b0100000_101_01 ; // // devci // 6'd16 : uncompress_id = 12'b1000_0000_0000 ; // // dap // 6'd17 : uncompress_id = 12'b1000_0000_0001 ; // // l2m1 (CPU000) // 6'd18 : uncompress_id = 12'b11_000_000_00_00 ; // 6'd19 : uncompress_id = 12'b11_010_000_00_00 ; // 6'd20 : uncompress_id = 12'b11_011_000_00_00 ; // 6'd21 : uncompress_id = 12'b11_100_000_00_00 ; // 6'd22 : uncompress_id = 12'b11_101_000_00_00 ; // 6'd23 : uncompress_id = 12'b11_110_000_00_00 ; // 6'd24 : uncompress_id = 12'b11_111_000_00_00 ; // // l2m1 (CPU001) // 6'd25 : uncompress_id = 12'b11_000_001_00_00 ; // 6'd26 : uncompress_id = 12'b11_010_001_00_00 ; // 6'd27 : uncompress_id = 12'b11_011_001_00_00 ; // 6'd28 : uncompress_id = 12'b11_100_001_00_00 ; // 6'd29 : uncompress_id = 12'b11_101_001_00_00 ; // 6'd30 : uncompress_id = 12'b11_110_001_00_00 ; // 6'd31 : uncompress_id = 12'b11_111_001_00_00 ; // // l2m1 (L2CC) // 6'd32 : uncompress_id = 12'b11_000_00101_00 ; // 6'd33 : uncompress_id = 12'b11_000_01001_00 ; // 6'd34 : uncompress_id = 12'b11_000_01101_00 ; // 6'd35 : uncompress_id = 12'b11_000_10011_00 ; // 6'd36 : uncompress_id = 12'b11_000_10111_00 ; // 6'd37 : uncompress_id = 12'b11_000_11011_00 ; // 6'd38 : uncompress_id = 12'b11_000_11111_00 ; // 6'd39 : uncompress_id = 12'b11_000_00011_00 ; // 6'd40 : uncompress_id = 12'b11_000_00111_00 ; // 6'd41 : uncompress_id = 12'b11_000_01011_00 ; // 6'd42 : uncompress_id = 12'b11_000_01111_00 ; // 6'd43 : uncompress_id = 12'b11_000_00001_00 ; // // l2m1 (ACP) // 6'd44 : uncompress_id = 12'b11_000_10000_00 ; // 6'd45 : uncompress_id = 12'b11_001_10000_00 ; // 6'd46 : uncompress_id = 12'b11_010_10000_00 ; // 6'd47 : uncompress_id = 12'b11_011_10000_00 ; // 6'd48 : uncompress_id = 12'b11_100_10000_00 ; // 6'd49 : uncompress_id = 12'b11_101_10000_00 ; // 6'd50 : uncompress_id = 12'b11_110_10000_00 ; // 6'd51 : uncompress_id = 12'b11_111_10000_00 ; // default : uncompress_id = ~0; // endcase // end //endfunction // //function [5:0] compress_id; // input [11:0] id; // begin // case (id[11:0]) // // dmac0 // 12'b010000_1000_00 : compress_id = 'd1 ; // 12'b010000_0000_00 : compress_id = 'd2 ; // 12'b010000_0001_00 : compress_id = 'd3 ; // 12'b010000_0010_00 : compress_id = 'd4 ; // 12'b010000_0011_00 : compress_id = 'd5 ; // 12'b010000_0100_00 : compress_id = 'd6 ; // 12'b010000_0101_00 : compress_id = 'd7 ; // 12'b010000_0110_00 : compress_id = 'd8 ; // 12'b010000_0111_00 : compress_id = 'd9 ; // // ioum // 12'b0100000_000_01 : compress_id = 'd10 ; // 12'b0100000_001_01 : compress_id = 'd11 ; // 12'b0100000_010_01 : compress_id = 'd12 ; // 12'b0100000_011_01 : compress_id = 'd13 ; // 12'b0100000_100_01 : compress_id = 'd14 ; // 12'b0100000_101_01 : compress_id = 'd15 ; // // devci // 12'b1000_0000_0000 : compress_id = 'd16 ; // // dap // 12'b1000_0000_0001 : compress_id = 'd17 ; // // l2m1 (CPU000) // 12'b11_000_000_00_00 : compress_id = 'd18 ; // 12'b11_010_000_00_00 : compress_id = 'd19 ; // 12'b11_011_000_00_00 : compress_id = 'd20 ; // 12'b11_100_000_00_00 : compress_id = 'd21 ; // 12'b11_101_000_00_00 : compress_id = 'd22 ; // 12'b11_110_000_00_00 : compress_id = 'd23 ; // 12'b11_111_000_00_00 : compress_id = 'd24 ; // // l2m1 (CPU001) // 12'b11_000_001_00_00 : compress_id = 'd25 ; // 12'b11_010_001_00_00 : compress_id = 'd26 ; // 12'b11_011_001_00_00 : compress_id = 'd27 ; // 12'b11_100_001_00_00 : compress_id = 'd28 ; // 12'b11_101_001_00_00 : compress_id = 'd29 ; // 12'b11_110_001_00_00 : compress_id = 'd30 ; // 12'b11_111_001_00_00 : compress_id = 'd31 ; // // l2m1 (L2CC) // 12'b11_000_00101_00 : compress_id = 'd32 ; // 12'b11_000_01001_00 : compress_id = 'd33 ; // 12'b11_000_01101_00 : compress_id = 'd34 ; // 12'b11_000_10011_00 : compress_id = 'd35 ; // 12'b11_000_10111_00 : compress_id = 'd36 ; // 12'b11_000_11011_00 : compress_id = 'd37 ; // 12'b11_000_11111_00 : compress_id = 'd38 ; // 12'b11_000_00011_00 : compress_id = 'd39 ; // 12'b11_000_00111_00 : compress_id = 'd40 ; // 12'b11_000_01011_00 : compress_id = 'd41 ; // 12'b11_000_01111_00 : compress_id = 'd42 ; // 12'b11_000_00001_00 : compress_id = 'd43 ; // // l2m1 (ACP) // 12'b11_000_10000_00 : compress_id = 'd44 ; // 12'b11_001_10000_00 : compress_id = 'd45 ; // 12'b11_010_10000_00 : compress_id = 'd46 ; // 12'b11_011_10000_00 : compress_id = 'd47 ; // 12'b11_100_10000_00 : compress_id = 'd48 ; // 12'b11_101_10000_00 : compress_id = 'd49 ; // 12'b11_110_10000_00 : compress_id = 'd50 ; // 12'b11_111_10000_00 : compress_id = 'd51 ; // default: compress_id = ~0; // endcase // end //endfunction // Modified as per CR 648393 function [5:0] compress_id; input [11:0] id; begin compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]); compress_id[1] = id[8] | id[5] | (~id[11] & id[3]); compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]); compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]); compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]); compress_id[5] = id[11] & id[10] & ~id[3]; end endfunction function [11:0] uncompress_id; input [5:0] id; begin case (id[5:0]) // dmac0 6'b000_010 : uncompress_id = 12'b010000_1000_00 ; 6'b001_000 : uncompress_id = 12'b010000_0000_00 ; 6'b001_001 : uncompress_id = 12'b010000_0001_00 ; 6'b001_010 : uncompress_id = 12'b010000_0010_00 ; 6'b001_011 : uncompress_id = 12'b010000_0011_00 ; 6'b001_100 : uncompress_id = 12'b010000_0100_00 ; 6'b001_101 : uncompress_id = 12'b010000_0101_00 ; 6'b001_110 : uncompress_id = 12'b010000_0110_00 ; 6'b001_111 : uncompress_id = 12'b010000_0111_00 ; // ioum 6'b010_000 : uncompress_id = 12'b0100000_000_01 ; 6'b010_001 : uncompress_id = 12'b0100000_001_01 ; 6'b010_010 : uncompress_id = 12'b0100000_010_01 ; 6'b010_011 : uncompress_id = 12'b0100000_011_01 ; 6'b010_100 : uncompress_id = 12'b0100000_100_01 ; 6'b010_101 : uncompress_id = 12'b0100000_101_01 ; // devci 6'b000_000 : uncompress_id = 12'b1000_0000_0000 ; // dap 6'b000_001 : uncompress_id = 12'b1000_0000_0001 ; // l2m1 (CPU000) 6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ; 6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ; 6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ; 6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ; 6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ; 6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ; 6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ; // l2m1 (CPU001) 6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ; 6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ; 6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ; 6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ; 6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ; 6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ; 6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ; // l2m1 (L2CC) 6'b101_001 : uncompress_id = 12'b11_000_00101_00 ; 6'b101_010 : uncompress_id = 12'b11_000_01001_00 ; 6'b101_011 : uncompress_id = 12'b11_000_01101_00 ; 6'b011_100 : uncompress_id = 12'b11_000_10011_00 ; 6'b011_101 : uncompress_id = 12'b11_000_10111_00 ; 6'b011_110 : uncompress_id = 12'b11_000_11011_00 ; 6'b011_111 : uncompress_id = 12'b11_000_11111_00 ; 6'b011_000 : uncompress_id = 12'b11_000_00011_00 ; 6'b011_001 : uncompress_id = 12'b11_000_00111_00 ; 6'b011_010 : uncompress_id = 12'b11_000_01011_00 ; 6'b011_011 : uncompress_id = 12'b11_000_01111_00 ; 6'b101_000 : uncompress_id = 12'b11_000_00001_00 ; // l2m1 (ACP) 6'b100_000 : uncompress_id = 12'b11_000_10000_00 ; 6'b100_001 : uncompress_id = 12'b11_001_10000_00 ; 6'b100_010 : uncompress_id = 12'b11_010_10000_00 ; 6'b100_011 : uncompress_id = 12'b11_011_10000_00 ; 6'b100_100 : uncompress_id = 12'b11_100_10000_00 ; 6'b100_101 : uncompress_id = 12'b11_101_10000_00 ; 6'b100_110 : uncompress_id = 12'b11_110_10000_00 ; 6'b100_111 : uncompress_id = 12'b11_111_10000_00 ; default : uncompress_id = 12'hx ; endcase end endfunction // Static Remap logic Enablement and Disablement for C_M_AXI0 port assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL; assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL; assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL; assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID; assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID; // Static Remap logic Enablement and Disablement for C_M_AXI1 port assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL; assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL; assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL; assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID; assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID; //// Compress_id and uncompress_id has been removed to address CR 642527 //// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression. // assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL; // assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL; // assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL; // assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID; // assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID; // // assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL; // assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL; // assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL; // assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID; // assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID; // Pipeline Stage for ENET0 generate if (C_EN_EMIO_ENET0 == 1) begin always @(posedge ENET0_GMII_TX_CLK) begin ENET0_GMII_TXD <= ENET0_GMII_TXD_i; ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i; ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i; ENET0_GMII_COL_i <= ENET0_GMII_COL; ENET0_GMII_CRS_i <= ENET0_GMII_CRS; end end else always@* begin ENET0_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i; ENET0_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i; ENET0_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i; ENET0_GMII_COL_i <= 'b0; ENET0_GMII_CRS_i <= 'b0; end endgenerate generate if (C_EN_EMIO_ENET0 == 1) begin always @(posedge ENET0_GMII_RX_CLK) begin ENET0_GMII_RXD_i <= ENET0_GMII_RXD; ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV; ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER; end end else begin always @* begin ENET0_GMII_RXD_i <= 0; ENET0_GMII_RX_DV_i <= 0; ENET0_GMII_RX_ER_i <= 0; end end endgenerate // Pipeline Stage for ENET1 generate if (C_EN_EMIO_ENET1 == 1) begin always @(posedge ENET1_GMII_TX_CLK) begin ENET1_GMII_TXD <= ENET1_GMII_TXD_i; ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i; ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i; ENET1_GMII_COL_i <= ENET1_GMII_COL; ENET1_GMII_CRS_i <= ENET1_GMII_CRS; end end else begin always@* begin ENET1_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i; ENET1_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i; ENET1_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i; ENET1_GMII_COL_i <= 0; ENET1_GMII_CRS_i <= 0; end end endgenerate generate if (C_EN_EMIO_ENET1 == 1) begin always @(posedge ENET1_GMII_RX_CLK) begin ENET1_GMII_RXD_i <= ENET1_GMII_RXD; ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV; ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER; end end else begin always @* begin ENET1_GMII_RXD_i <= 'b0; ENET1_GMII_RX_DV_i <= 'b0; ENET1_GMII_RX_ER_i <= 'b0; end end endgenerate // Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1. generate if (C_EN_EMIO_TRACE == 1) begin if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer // Pipeline Stage for Traceport ATID always @(posedge FTMD_TRACEIN_CLK) begin FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA; FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID; FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID; end assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf; assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf; assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf; end else begin : gen_trace_buffer processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE), .USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR), .C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY) ) trace_buffer_i ( .TRACE_CLK(FTMD_TRACEIN_CLK), .RST(~FCLK_RESET0_N), .TRACE_VALID_IN(FTMD_TRACEIN_VALID), .TRACE_DATA_IN(FTMD_TRACEIN_DATA), .TRACE_ATID_IN(FTMD_TRACEIN_ATID), .TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf), .TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf), .TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf) ); assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf; assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf; assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf; end end else begin assign FTMD_TRACEIN_DATA_i = 1'b0; assign FTMD_TRACEIN_VALID_i = 1'b0; assign FTMD_TRACEIN_ATID_i = 1'b0; end endgenerate // ID Width Control on AXI Slave ports // S_AXI_GP0 function [5:0] id_in_gp0; input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in; begin case (C_S_AXI_GP0_ID_WIDTH) 1: id_in_gp0 = {5'b0, axi_id_gp0_in}; 2: id_in_gp0 = {4'b0, axi_id_gp0_in}; 3: id_in_gp0 = {3'b0, axi_id_gp0_in}; 4: id_in_gp0 = {2'b0, axi_id_gp0_in}; 5: id_in_gp0 = {1'b0, axi_id_gp0_in}; 6: id_in_gp0 = axi_id_gp0_in; default : id_in_gp0 = axi_id_gp0_in; endcase end endfunction assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID); assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID); assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID); function [5:0] id_out_gp0; input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out; begin case (C_S_AXI_GP0_ID_WIDTH) 1: id_out_gp0 = axi_id_gp0_out[0]; 2: id_out_gp0 = axi_id_gp0_out[1:0]; 3: id_out_gp0 = axi_id_gp0_out[2:0]; 4: id_out_gp0 = axi_id_gp0_out[3:0]; 5: id_out_gp0 = axi_id_gp0_out[4:0]; 6: id_out_gp0 = axi_id_gp0_out; default : id_out_gp0 = axi_id_gp0_out; endcase end endfunction assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out); assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out); // S_AXI_GP1 function [5:0] id_in_gp1; input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in; begin case (C_S_AXI_GP1_ID_WIDTH) 1: id_in_gp1 = {5'b0, axi_id_gp1_in}; 2: id_in_gp1 = {4'b0, axi_id_gp1_in}; 3: id_in_gp1 = {3'b0, axi_id_gp1_in}; 4: id_in_gp1 = {2'b0, axi_id_gp1_in}; 5: id_in_gp1 = {1'b0, axi_id_gp1_in}; 6: id_in_gp1 = axi_id_gp1_in; default : id_in_gp1 = axi_id_gp1_in; endcase end endfunction assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID); assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID); assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID); function [5:0] id_out_gp1; input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out; begin case (C_S_AXI_GP1_ID_WIDTH) 1: id_out_gp1 = axi_id_gp1_out[0]; 2: id_out_gp1 = axi_id_gp1_out[1:0]; 3: id_out_gp1 = axi_id_gp1_out[2:0]; 4: id_out_gp1 = axi_id_gp1_out[3:0]; 5: id_out_gp1 = axi_id_gp1_out[4:0]; 6: id_out_gp1 = axi_id_gp1_out; default : id_out_gp1 = axi_id_gp1_out; endcase end endfunction assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out); assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out); // S_AXI_HP0 function [5:0] id_in_hp0; input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in; begin case (C_S_AXI_HP0_ID_WIDTH) 1: id_in_hp0 = {5'b0, axi_id_hp0_in}; 2: id_in_hp0 = {4'b0, axi_id_hp0_in}; 3: id_in_hp0 = {3'b0, axi_id_hp0_in}; 4: id_in_hp0 = {2'b0, axi_id_hp0_in}; 5: id_in_hp0 = {1'b0, axi_id_hp0_in}; 6: id_in_hp0 = axi_id_hp0_in; default : id_in_hp0 = axi_id_hp0_in; endcase end endfunction assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID); assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID); assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID); function [5:0] id_out_hp0; input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out; begin case (C_S_AXI_HP0_ID_WIDTH) 1: id_out_hp0 = axi_id_hp0_out[0]; 2: id_out_hp0 = axi_id_hp0_out[1:0]; 3: id_out_hp0 = axi_id_hp0_out[2:0]; 4: id_out_hp0 = axi_id_hp0_out[3:0]; 5: id_out_hp0 = axi_id_hp0_out[4:0]; 6: id_out_hp0 = axi_id_hp0_out; default : id_out_hp0 = axi_id_hp0_out; endcase end endfunction assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out); assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out); assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA}; assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB}; assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0]; // S_AXI_HP1 function [5:0] id_in_hp1; input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in; begin case (C_S_AXI_HP1_ID_WIDTH) 1: id_in_hp1 = {5'b0, axi_id_hp1_in}; 2: id_in_hp1 = {4'b0, axi_id_hp1_in}; 3: id_in_hp1 = {3'b0, axi_id_hp1_in}; 4: id_in_hp1 = {2'b0, axi_id_hp1_in}; 5: id_in_hp1 = {1'b0, axi_id_hp1_in}; 6: id_in_hp1 = axi_id_hp1_in; default : id_in_hp1 = axi_id_hp1_in; endcase end endfunction assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID); assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID); assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID); function [5:0] id_out_hp1; input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out; begin case (C_S_AXI_HP1_ID_WIDTH) 1: id_out_hp1 = axi_id_hp1_out[0]; 2: id_out_hp1 = axi_id_hp1_out[1:0]; 3: id_out_hp1 = axi_id_hp1_out[2:0]; 4: id_out_hp1 = axi_id_hp1_out[3:0]; 5: id_out_hp1 = axi_id_hp1_out[4:0]; 6: id_out_hp1 = axi_id_hp1_out; default : id_out_hp1 = axi_id_hp1_out; endcase end endfunction assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out); assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out); assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA}; assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB}; assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0]; // S_AXI_HP2 function [5:0] id_in_hp2; input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in; begin case (C_S_AXI_HP2_ID_WIDTH) 1: id_in_hp2 = {5'b0, axi_id_hp2_in}; 2: id_in_hp2 = {4'b0, axi_id_hp2_in}; 3: id_in_hp2 = {3'b0, axi_id_hp2_in}; 4: id_in_hp2 = {2'b0, axi_id_hp2_in}; 5: id_in_hp2 = {1'b0, axi_id_hp2_in}; 6: id_in_hp2 = axi_id_hp2_in; default : id_in_hp2 = axi_id_hp2_in; endcase end endfunction assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID); assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID); assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID); function [5:0] id_out_hp2; input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out; begin case (C_S_AXI_HP2_ID_WIDTH) 1: id_out_hp2 = axi_id_hp2_out[0]; 2: id_out_hp2 = axi_id_hp2_out[1:0]; 3: id_out_hp2 = axi_id_hp2_out[2:0]; 4: id_out_hp2 = axi_id_hp2_out[3:0]; 5: id_out_hp2 = axi_id_hp2_out[4:0]; 6: id_out_hp2 = axi_id_hp2_out; default : id_out_hp2 = axi_id_hp2_out; endcase end endfunction assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out); assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out); assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA}; assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB}; assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0]; // S_AXI_HP3 function [5:0] id_in_hp3; input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in; begin case (C_S_AXI_HP3_ID_WIDTH) 1: id_in_hp3 = {5'b0, axi_id_hp3_in}; 2: id_in_hp3 = {4'b0, axi_id_hp3_in}; 3: id_in_hp3 = {3'b0, axi_id_hp3_in}; 4: id_in_hp3 = {2'b0, axi_id_hp3_in}; 5: id_in_hp3 = {1'b0, axi_id_hp3_in}; 6: id_in_hp3 = axi_id_hp3_in; default : id_in_hp3 = axi_id_hp3_in; endcase end endfunction assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID); assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID); assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID); function [5:0] id_out_hp3; input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out; begin case (C_S_AXI_HP3_ID_WIDTH) 1: id_out_hp3 = axi_id_hp3_out[0]; 2: id_out_hp3 = axi_id_hp3_out[1:0]; 3: id_out_hp3 = axi_id_hp3_out[2:0]; 4: id_out_hp3 = axi_id_hp3_out[3:0]; 5: id_out_hp3 = axi_id_hp3_out[4:0]; 6: id_out_hp3 = axi_id_hp3_out; default : id_out_hp3 = axi_id_hp3_out; endcase end endfunction assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out); assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out); assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA}; assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB}; assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0]; // S_AXI_ACP function [2:0] id_in_acp; input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in; begin case (C_S_AXI_ACP_ID_WIDTH) 1: id_in_acp = {2'b0, axi_id_acp_in}; 2: id_in_acp = {1'b0, axi_id_acp_in}; 3: id_in_acp = axi_id_acp_in; default : id_in_acp = axi_id_acp_in; endcase end endfunction assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W); assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W); assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W); function [2:0] id_out_acp; input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out; begin case (C_S_AXI_ACP_ID_WIDTH) 1: id_out_acp = axi_id_acp_out[0]; 2: id_out_acp = axi_id_acp_out[1:0]; 3: id_out_acp = axi_id_acp_out; default : id_out_acp = axi_id_acp_out; endcase end endfunction assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out); assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out); // FMIO Tristate Inversion logic //FMIO I2C0 assign I2C0_SDA_T = ~ I2C0_SDA_T_n; assign I2C0_SCL_T = ~ I2C0_SCL_T_n; //FMIO I2C1 assign I2C1_SDA_T = ~ I2C1_SDA_T_n; assign I2C1_SCL_T = ~ I2C1_SCL_T_n; //FMIO SPI0 assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n; assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n; assign SPI0_MISO_T = ~ SPI0_MISO_T_n; assign SPI0_SS_T = ~ SPI0_SS_T_n; //FMIO SPI1 assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n; assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n; assign SPI1_MISO_T = ~ SPI1_MISO_T_n; assign SPI1_SS_T = ~ SPI1_SS_T_n; // EMIO GEM0 MDIO assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n; // EMIO GEM1 MDIO assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n; // EMIO GPIO assign GPIO_T = ~ GPIO_T_n; // EMIO GPIO Width Control function [63:0] gpio_width_adjust_in; input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in; begin case (C_EMIO_GPIO_WIDTH) 1: gpio_width_adjust_in = {63'b0, gpio_in}; 2: gpio_width_adjust_in = {62'b0, gpio_in}; 3: gpio_width_adjust_in = {61'b0, gpio_in}; 4: gpio_width_adjust_in = {60'b0, gpio_in}; 5: gpio_width_adjust_in = {59'b0, gpio_in}; 6: gpio_width_adjust_in = {58'b0, gpio_in}; 7: gpio_width_adjust_in = {57'b0, gpio_in}; 8: gpio_width_adjust_in = {56'b0, gpio_in}; 9: gpio_width_adjust_in = {55'b0, gpio_in}; 10: gpio_width_adjust_in = {54'b0, gpio_in}; 11: gpio_width_adjust_in = {53'b0, gpio_in}; 12: gpio_width_adjust_in = {52'b0, gpio_in}; 13: gpio_width_adjust_in = {51'b0, gpio_in}; 14: gpio_width_adjust_in = {50'b0, gpio_in}; 15: gpio_width_adjust_in = {49'b0, gpio_in}; 16: gpio_width_adjust_in = {48'b0, gpio_in}; 17: gpio_width_adjust_in = {47'b0, gpio_in}; 18: gpio_width_adjust_in = {46'b0, gpio_in}; 19: gpio_width_adjust_in = {45'b0, gpio_in}; 20: gpio_width_adjust_in = {44'b0, gpio_in}; 21: gpio_width_adjust_in = {43'b0, gpio_in}; 22: gpio_width_adjust_in = {42'b0, gpio_in}; 23: gpio_width_adjust_in = {41'b0, gpio_in}; 24: gpio_width_adjust_in = {40'b0, gpio_in}; 25: gpio_width_adjust_in = {39'b0, gpio_in}; 26: gpio_width_adjust_in = {38'b0, gpio_in}; 27: gpio_width_adjust_in = {37'b0, gpio_in}; 28: gpio_width_adjust_in = {36'b0, gpio_in}; 29: gpio_width_adjust_in = {35'b0, gpio_in}; 30: gpio_width_adjust_in = {34'b0, gpio_in}; 31: gpio_width_adjust_in = {33'b0, gpio_in}; 32: gpio_width_adjust_in = {32'b0, gpio_in}; 33: gpio_width_adjust_in = {31'b0, gpio_in}; 34: gpio_width_adjust_in = {30'b0, gpio_in}; 35: gpio_width_adjust_in = {29'b0, gpio_in}; 36: gpio_width_adjust_in = {28'b0, gpio_in}; 37: gpio_width_adjust_in = {27'b0, gpio_in}; 38: gpio_width_adjust_in = {26'b0, gpio_in}; 39: gpio_width_adjust_in = {25'b0, gpio_in}; 40: gpio_width_adjust_in = {24'b0, gpio_in}; 41: gpio_width_adjust_in = {23'b0, gpio_in}; 42: gpio_width_adjust_in = {22'b0, gpio_in}; 43: gpio_width_adjust_in = {21'b0, gpio_in}; 44: gpio_width_adjust_in = {20'b0, gpio_in}; 45: gpio_width_adjust_in = {19'b0, gpio_in}; 46: gpio_width_adjust_in = {18'b0, gpio_in}; 47: gpio_width_adjust_in = {17'b0, gpio_in}; 48: gpio_width_adjust_in = {16'b0, gpio_in}; 49: gpio_width_adjust_in = {15'b0, gpio_in}; 50: gpio_width_adjust_in = {14'b0, gpio_in}; 51: gpio_width_adjust_in = {13'b0, gpio_in}; 52: gpio_width_adjust_in = {12'b0, gpio_in}; 53: gpio_width_adjust_in = {11'b0, gpio_in}; 54: gpio_width_adjust_in = {10'b0, gpio_in}; 55: gpio_width_adjust_in = {9'b0, gpio_in}; 56: gpio_width_adjust_in = {8'b0, gpio_in}; 57: gpio_width_adjust_in = {7'b0, gpio_in}; 58: gpio_width_adjust_in = {6'b0, gpio_in}; 59: gpio_width_adjust_in = {5'b0, gpio_in}; 60: gpio_width_adjust_in = {4'b0, gpio_in}; 61: gpio_width_adjust_in = {3'b0, gpio_in}; 62: gpio_width_adjust_in = {2'b0, gpio_in}; 63: gpio_width_adjust_in = {1'b0, gpio_in}; 64: gpio_width_adjust_in = gpio_in; default : gpio_width_adjust_in = gpio_in; endcase end endfunction assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I); function [63:0] gpio_width_adjust_out; input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o; begin case (C_EMIO_GPIO_WIDTH) 1: gpio_width_adjust_out = gpio_o[0]; 2: gpio_width_adjust_out = gpio_o[1:0]; 3: gpio_width_adjust_out = gpio_o[2:0]; 4: gpio_width_adjust_out = gpio_o[3:0]; 5: gpio_width_adjust_out = gpio_o[4:0]; 6: gpio_width_adjust_out = gpio_o[5:0]; 7: gpio_width_adjust_out = gpio_o[6:0]; 8: gpio_width_adjust_out = gpio_o[7:0]; 9: gpio_width_adjust_out = gpio_o[8:0]; 10: gpio_width_adjust_out = gpio_o[9:0]; 11: gpio_width_adjust_out = gpio_o[10:0]; 12: gpio_width_adjust_out = gpio_o[11:0]; 13: gpio_width_adjust_out = gpio_o[12:0]; 14: gpio_width_adjust_out = gpio_o[13:0]; 15: gpio_width_adjust_out = gpio_o[14:0]; 16: gpio_width_adjust_out = gpio_o[15:0]; 17: gpio_width_adjust_out = gpio_o[16:0]; 18: gpio_width_adjust_out = gpio_o[17:0]; 19: gpio_width_adjust_out = gpio_o[18:0]; 20: gpio_width_adjust_out = gpio_o[19:0]; 21: gpio_width_adjust_out = gpio_o[20:0]; 22: gpio_width_adjust_out = gpio_o[21:0]; 23: gpio_width_adjust_out = gpio_o[22:0]; 24: gpio_width_adjust_out = gpio_o[23:0]; 25: gpio_width_adjust_out = gpio_o[24:0]; 26: gpio_width_adjust_out = gpio_o[25:0]; 27: gpio_width_adjust_out = gpio_o[26:0]; 28: gpio_width_adjust_out = gpio_o[27:0]; 29: gpio_width_adjust_out = gpio_o[28:0]; 30: gpio_width_adjust_out = gpio_o[29:0]; 31: gpio_width_adjust_out = gpio_o[30:0]; 32: gpio_width_adjust_out = gpio_o[31:0]; 33: gpio_width_adjust_out = gpio_o[32:0]; 34: gpio_width_adjust_out = gpio_o[33:0]; 35: gpio_width_adjust_out = gpio_o[34:0]; 36: gpio_width_adjust_out = gpio_o[35:0]; 37: gpio_width_adjust_out = gpio_o[36:0]; 38: gpio_width_adjust_out = gpio_o[37:0]; 39: gpio_width_adjust_out = gpio_o[38:0]; 40: gpio_width_adjust_out = gpio_o[39:0]; 41: gpio_width_adjust_out = gpio_o[40:0]; 42: gpio_width_adjust_out = gpio_o[41:0]; 43: gpio_width_adjust_out = gpio_o[42:0]; 44: gpio_width_adjust_out = gpio_o[43:0]; 45: gpio_width_adjust_out = gpio_o[44:0]; 46: gpio_width_adjust_out = gpio_o[45:0]; 47: gpio_width_adjust_out = gpio_o[46:0]; 48: gpio_width_adjust_out = gpio_o[47:0]; 49: gpio_width_adjust_out = gpio_o[48:0]; 50: gpio_width_adjust_out = gpio_o[49:0]; 51: gpio_width_adjust_out = gpio_o[50:0]; 52: gpio_width_adjust_out = gpio_o[51:0]; 53: gpio_width_adjust_out = gpio_o[52:0]; 54: gpio_width_adjust_out = gpio_o[53:0]; 55: gpio_width_adjust_out = gpio_o[54:0]; 56: gpio_width_adjust_out = gpio_o[55:0]; 57: gpio_width_adjust_out = gpio_o[56:0]; 58: gpio_width_adjust_out = gpio_o[57:0]; 59: gpio_width_adjust_out = gpio_o[58:0]; 60: gpio_width_adjust_out = gpio_o[59:0]; 61: gpio_width_adjust_out = gpio_o[60:0]; 62: gpio_width_adjust_out = gpio_o[61:0]; 63: gpio_width_adjust_out = gpio_o[62:0]; 64: gpio_width_adjust_out = gpio_o; default : gpio_width_adjust_out = gpio_o; endcase end endfunction assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out); assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n); // Adding OBUFT to JTAG out port generate if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE OBUFT jtag_obuft_inst ( .O(PJTAG_TDO), .I(PJTAG_TDO_O), .T(PJTAG_TDO_T) ); end else begin assign PJTAG_TDO = 1'b0; end endgenerate // ------- // EMIO PJTAG assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n; // EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon, // FOR Other SI REV, inversion is required assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n); assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]); // EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon, // FOR Other SI REV, inversion is required assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n); assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]); // FCLK_CLK optional clock buffers generate if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0 BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0])); end if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1 BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1])); end if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2 BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2])); end if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3 BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3])); end endgenerate assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0]; assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1]; assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2]; assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3]; assign FCLK_CLK0 = FCLK_CLK0_temp; // Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n)); BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE)); BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n)); BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk)); BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n)); BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB)); BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT)); BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n)); BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB)); BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN)); BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP)); BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB)); BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK)); BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB)); genvar i; generate for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i])); end endgenerate generate for (i=0; i < 3; i=i+1) begin BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i])); end endgenerate generate for (i=0; i < 15; i=i+1) begin BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i])); end endgenerate generate for (i=0; i < C_DM_WIDTH; i=i+1) begin BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i])); end endgenerate generate for (i=0; i < C_DQ_WIDTH; i=i+1) begin BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i])); end endgenerate generate for (i=0; i < C_DQS_WIDTH; i=i+1) begin BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i])); end endgenerate generate for (i=0; i < C_DQS_WIDTH; i=i+1) begin BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i])); end endgenerate // Connect FCLK in case of disable the AXI port for non Secure Transaction //Start wire S_AXI_HP0_ACLK_temp; wire S_AXI_HP1_ACLK_temp; wire S_AXI_HP2_ACLK_temp; wire S_AXI_HP3_ACLK_temp; generate if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp; end else begin assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK; end endgenerate generate if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin assign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp; end else begin assign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK; end endgenerate generate if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin assign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp; end else begin assign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK; end endgenerate generate if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin assign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp; end else begin assign S_AXI_HP3_ACLK_temp = S_AXI_HP2_ACLK; end endgenerate //Start wire M_AXI_GP0_ACLK_temp; wire M_AXI_GP1_ACLK_temp; wire S_AXI_GP0_ACLK_temp; wire S_AXI_GP1_ACLK_temp; wire S_AXI_ACP_ACLK_temp; generate if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin assign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp; end else begin assign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK; end endgenerate generate if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin assign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp; end else begin assign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK; end endgenerate generate if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin assign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp; end else begin assign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK; end endgenerate generate if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin assign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp; end else begin assign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK; end endgenerate generate if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin assign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp; end else begin assign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK; end endgenerate //END //==================== //PSS TOP //==================== generate if (C_PACKAGE_NAME == "clg225" ) begin wire [21:0] dummy; PS7 PS7_i ( .DMA0DATYPE (DMA0_DATYPE ), .DMA0DAVALID (DMA0_DAVALID), .DMA0DRREADY (DMA0_DRREADY), .DMA0RSTN (DMA0_RSTN ), .DMA1DATYPE (DMA1_DATYPE ), .DMA1DAVALID (DMA1_DAVALID), .DMA1DRREADY (DMA1_DRREADY), .DMA1RSTN (DMA1_RSTN ), .DMA2DATYPE (DMA2_DATYPE ), .DMA2DAVALID (DMA2_DAVALID), .DMA2DRREADY (DMA2_DRREADY), .DMA2RSTN (DMA2_RSTN ), .DMA3DATYPE (DMA3_DATYPE ), .DMA3DAVALID (DMA3_DAVALID), .DMA3DRREADY (DMA3_DRREADY), .DMA3RSTN (DMA3_RSTN ), .EMIOCAN0PHYTX (CAN0_PHY_TX ), .EMIOCAN1PHYTX (CAN1_PHY_TX ), .EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ), .EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i), .EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i), .EMIOENET0MDIOMDC (ENET0_MDIO_MDC), .EMIOENET0MDIOO (ENET0_MDIO_O ), .EMIOENET0MDIOTN (ENET0_MDIO_T_n ), .EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX), .EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX), .EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX), .EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX), .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX), .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX), .EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX), .EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX), .EMIOENET0SOFRX (ENET0_SOF_RX), .EMIOENET0SOFTX (ENET0_SOF_TX), .EMIOENET1GMIITXD (ENET1_GMII_TXD_i), //(ENET1_GMII_TXD_i), .EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i), .EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i), .EMIOENET1MDIOMDC (ENET1_MDIO_MDC), .EMIOENET1MDIOO (ENET1_MDIO_O), .EMIOENET1MDIOTN (ENET1_MDIO_T_n), .EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX), .EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX), .EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX), .EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX), .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX), .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX), .EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX), .EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX), .EMIOENET1SOFRX (ENET1_SOF_RX), .EMIOENET1SOFTX (ENET1_SOF_TX), .EMIOGPIOO (gpio_out), .EMIOGPIOTN (gpio_out_t_n), .EMIOI2C0SCLO (I2C0_SCL_O), .EMIOI2C0SCLTN (I2C0_SCL_T_n), .EMIOI2C0SDAO (I2C0_SDA_O), .EMIOI2C0SDATN (I2C0_SDA_T_n), .EMIOI2C1SCLO (I2C1_SCL_O), .EMIOI2C1SCLTN (I2C1_SCL_T_n), .EMIOI2C1SDAO (I2C1_SDA_O), .EMIOI2C1SDATN (I2C1_SDA_T_n), .EMIOPJTAGTDO (PJTAG_TDO_O), .EMIOPJTAGTDTN (PJTAG_TDO_T_n), .EMIOSDIO0BUSPOW (SDIO0_BUSPOW), .EMIOSDIO0CLK (SDIO0_CLK ), .EMIOSDIO0CMDO (SDIO0_CMD_O ), .EMIOSDIO0CMDTN (SDIO0_CMD_T_n ), .EMIOSDIO0DATAO (SDIO0_DATA_O), .EMIOSDIO0DATATN (SDIO0_DATA_T_n), .EMIOSDIO0LED (SDIO0_LED), .EMIOSDIO1BUSPOW (SDIO1_BUSPOW), .EMIOSDIO1CLK (SDIO1_CLK ), .EMIOSDIO1CMDO (SDIO1_CMD_O ), .EMIOSDIO1CMDTN (SDIO1_CMD_T_n ), .EMIOSDIO1DATAO (SDIO1_DATA_O), .EMIOSDIO1DATATN (SDIO1_DATA_T_n), .EMIOSDIO1LED (SDIO1_LED), .EMIOSPI0MO (SPI0_MOSI_O), .EMIOSPI0MOTN (SPI0_MOSI_T_n), .EMIOSPI0SCLKO (SPI0_SCLK_O), .EMIOSPI0SCLKTN (SPI0_SCLK_T_n), .EMIOSPI0SO (SPI0_MISO_O), .EMIOSPI0STN (SPI0_MISO_T_n), .EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}), .EMIOSPI0SSNTN (SPI0_SS_T_n), .EMIOSPI1MO (SPI1_MOSI_O), .EMIOSPI1MOTN (SPI1_MOSI_T_n), .EMIOSPI1SCLKO (SPI1_SCLK_O), .EMIOSPI1SCLKTN (SPI1_SCLK_T_n), .EMIOSPI1SO (SPI1_MISO_O), .EMIOSPI1STN (SPI1_MISO_T_n), .EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}), .EMIOSPI1SSNTN (SPI1_SS_T_n), .EMIOTRACECTL (TRACE_CTL_i), .EMIOTRACEDATA (TRACE_DATA_i), .EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}), .EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}), .EMIOUART0DTRN (UART0_DTRN), .EMIOUART0RTSN (UART0_RTSN), .EMIOUART0TX (UART0_TX ), .EMIOUART1DTRN (UART1_DTRN), .EMIOUART1RTSN (UART1_RTSN), .EMIOUART1TX (UART1_TX ), .EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL), .EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT), .EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL), .EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT), .EMIOWDTRSTO (WDT_RST_OUT), .EVENTEVENTO (EVENT_EVENTO), .EVENTSTANDBYWFE (EVENT_STANDBYWFE), .EVENTSTANDBYWFI (EVENT_STANDBYWFI), .FCLKCLK (FCLK_CLK_unbuffered), .FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}), .EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT), .EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT), .FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}), .FTMTP2FDEBUG (FTMT_P2F_DEBUG ), .FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}), .IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}), .MAXIGP0ARADDR (M_AXI_GP0_ARADDR), .MAXIGP0ARBURST (M_AXI_GP0_ARBURST), .MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE), .MAXIGP0ARESETN (M_AXI_GP0_ARESETN), .MAXIGP0ARID (M_AXI_GP0_ARID_FULL ), .MAXIGP0ARLEN (M_AXI_GP0_ARLEN ), .MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ), .MAXIGP0ARPROT (M_AXI_GP0_ARPROT ), .MAXIGP0ARQOS (M_AXI_GP0_ARQOS ), .MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ), .MAXIGP0ARVALID (M_AXI_GP0_ARVALID), .MAXIGP0AWADDR (M_AXI_GP0_AWADDR ), .MAXIGP0AWBURST (M_AXI_GP0_AWBURST), .MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE), .MAXIGP0AWID (M_AXI_GP0_AWID_FULL ), .MAXIGP0AWLEN (M_AXI_GP0_AWLEN ), .MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ), .MAXIGP0AWPROT (M_AXI_GP0_AWPROT ), .MAXIGP0AWQOS (M_AXI_GP0_AWQOS ), .MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ), .MAXIGP0AWVALID (M_AXI_GP0_AWVALID), .MAXIGP0BREADY (M_AXI_GP0_BREADY ), .MAXIGP0RREADY (M_AXI_GP0_RREADY ), .MAXIGP0WDATA (M_AXI_GP0_WDATA ), .MAXIGP0WID (M_AXI_GP0_WID_FULL ), .MAXIGP0WLAST (M_AXI_GP0_WLAST ), .MAXIGP0WSTRB (M_AXI_GP0_WSTRB ), .MAXIGP0WVALID (M_AXI_GP0_WVALID ), .MAXIGP1ARADDR (M_AXI_GP1_ARADDR ), .MAXIGP1ARBURST (M_AXI_GP1_ARBURST), .MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE), .MAXIGP1ARESETN (M_AXI_GP1_ARESETN), .MAXIGP1ARID (M_AXI_GP1_ARID_FULL ), .MAXIGP1ARLEN (M_AXI_GP1_ARLEN ), .MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ), .MAXIGP1ARPROT (M_AXI_GP1_ARPROT ), .MAXIGP1ARQOS (M_AXI_GP1_ARQOS ), .MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ), .MAXIGP1ARVALID (M_AXI_GP1_ARVALID), .MAXIGP1AWADDR (M_AXI_GP1_AWADDR ), .MAXIGP1AWBURST (M_AXI_GP1_AWBURST), .MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE), .MAXIGP1AWID (M_AXI_GP1_AWID_FULL ), .MAXIGP1AWLEN (M_AXI_GP1_AWLEN ), .MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ), .MAXIGP1AWPROT (M_AXI_GP1_AWPROT ), .MAXIGP1AWQOS (M_AXI_GP1_AWQOS ), .MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ), .MAXIGP1AWVALID (M_AXI_GP1_AWVALID), .MAXIGP1BREADY (M_AXI_GP1_BREADY ), .MAXIGP1RREADY (M_AXI_GP1_RREADY ), .MAXIGP1WDATA (M_AXI_GP1_WDATA ), .MAXIGP1WID (M_AXI_GP1_WID_FULL ), .MAXIGP1WLAST (M_AXI_GP1_WLAST ), .MAXIGP1WSTRB (M_AXI_GP1_WSTRB ), .MAXIGP1WVALID (M_AXI_GP1_WVALID ), .SAXIACPARESETN (S_AXI_ACP_ARESETN), .SAXIACPARREADY (SAXIACPARREADY_W), .SAXIACPAWREADY (SAXIACPAWREADY_W), .SAXIACPBID (S_AXI_ACP_BID_out ), .SAXIACPBRESP (SAXIACPBRESP_W ), .SAXIACPBVALID (SAXIACPBVALID_W ), .SAXIACPRDATA (SAXIACPRDATA_W ), .SAXIACPRID (S_AXI_ACP_RID_out), .SAXIACPRLAST (SAXIACPRLAST_W ), .SAXIACPRRESP (SAXIACPRRESP_W ), .SAXIACPRVALID (SAXIACPRVALID_W ), .SAXIACPWREADY (SAXIACPWREADY_W ), .SAXIGP0ARESETN (S_AXI_GP0_ARESETN), .SAXIGP0ARREADY (S_AXI_GP0_ARREADY), .SAXIGP0AWREADY (S_AXI_GP0_AWREADY), .SAXIGP0BID (S_AXI_GP0_BID_out), .SAXIGP0BRESP (S_AXI_GP0_BRESP ), .SAXIGP0BVALID (S_AXI_GP0_BVALID ), .SAXIGP0RDATA (S_AXI_GP0_RDATA ), .SAXIGP0RID (S_AXI_GP0_RID_out ), .SAXIGP0RLAST (S_AXI_GP0_RLAST ), .SAXIGP0RRESP (S_AXI_GP0_RRESP ), .SAXIGP0RVALID (S_AXI_GP0_RVALID ), .SAXIGP0WREADY (S_AXI_GP0_WREADY ), .SAXIGP1ARESETN (S_AXI_GP1_ARESETN), .SAXIGP1ARREADY (S_AXI_GP1_ARREADY), .SAXIGP1AWREADY (S_AXI_GP1_AWREADY), .SAXIGP1BID (S_AXI_GP1_BID_out ), .SAXIGP1BRESP (S_AXI_GP1_BRESP ), .SAXIGP1BVALID (S_AXI_GP1_BVALID ), .SAXIGP1RDATA (S_AXI_GP1_RDATA ), .SAXIGP1RID (S_AXI_GP1_RID_out ), .SAXIGP1RLAST (S_AXI_GP1_RLAST ), .SAXIGP1RRESP (S_AXI_GP1_RRESP ), .SAXIGP1RVALID (S_AXI_GP1_RVALID ), .SAXIGP1WREADY (S_AXI_GP1_WREADY ), .SAXIHP0ARESETN (S_AXI_HP0_ARESETN), .SAXIHP0ARREADY (S_AXI_HP0_ARREADY), .SAXIHP0AWREADY (S_AXI_HP0_AWREADY), .SAXIHP0BID (S_AXI_HP0_BID_out ), .SAXIHP0BRESP (S_AXI_HP0_BRESP ), .SAXIHP0BVALID (S_AXI_HP0_BVALID ), .SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT), .SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT), .SAXIHP0RDATA (S_AXI_HP0_RDATA_out), .SAXIHP0RID (S_AXI_HP0_RID_out ), .SAXIHP0RLAST (S_AXI_HP0_RLAST), .SAXIHP0RRESP (S_AXI_HP0_RRESP), .SAXIHP0RVALID (S_AXI_HP0_RVALID), .SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT), .SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT), .SAXIHP0WREADY (S_AXI_HP0_WREADY), .SAXIHP1ARESETN (S_AXI_HP1_ARESETN), .SAXIHP1ARREADY (S_AXI_HP1_ARREADY), .SAXIHP1AWREADY (S_AXI_HP1_AWREADY), .SAXIHP1BID (S_AXI_HP1_BID_out ), .SAXIHP1BRESP (S_AXI_HP1_BRESP ), .SAXIHP1BVALID (S_AXI_HP1_BVALID ), .SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ), .SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ), .SAXIHP1RDATA (S_AXI_HP1_RDATA_out), .SAXIHP1RID (S_AXI_HP1_RID_out ), .SAXIHP1RLAST (S_AXI_HP1_RLAST ), .SAXIHP1RRESP (S_AXI_HP1_RRESP ), .SAXIHP1RVALID (S_AXI_HP1_RVALID), .SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT), .SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT), .SAXIHP1WREADY (S_AXI_HP1_WREADY), .SAXIHP2ARESETN (S_AXI_HP2_ARESETN), .SAXIHP2ARREADY (S_AXI_HP2_ARREADY), .SAXIHP2AWREADY (S_AXI_HP2_AWREADY), .SAXIHP2BID (S_AXI_HP2_BID_out ), .SAXIHP2BRESP (S_AXI_HP2_BRESP), .SAXIHP2BVALID (S_AXI_HP2_BVALID), .SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT), .SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT), .SAXIHP2RDATA (S_AXI_HP2_RDATA_out), .SAXIHP2RID (S_AXI_HP2_RID_out ), .SAXIHP2RLAST (S_AXI_HP2_RLAST), .SAXIHP2RRESP (S_AXI_HP2_RRESP), .SAXIHP2RVALID (S_AXI_HP2_RVALID), .SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT), .SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT), .SAXIHP2WREADY (S_AXI_HP2_WREADY), .SAXIHP3ARESETN (S_AXI_HP3_ARESETN), .SAXIHP3ARREADY (S_AXI_HP3_ARREADY), .SAXIHP3AWREADY (S_AXI_HP3_AWREADY), .SAXIHP3BID (S_AXI_HP3_BID_out), .SAXIHP3BRESP (S_AXI_HP3_BRESP), .SAXIHP3BVALID (S_AXI_HP3_BVALID), .SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT), .SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT), .SAXIHP3RDATA (S_AXI_HP3_RDATA_out), .SAXIHP3RID (S_AXI_HP3_RID_out), .SAXIHP3RLAST (S_AXI_HP3_RLAST), .SAXIHP3RRESP (S_AXI_HP3_RRESP), .SAXIHP3RVALID (S_AXI_HP3_RVALID), .SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT), .SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT), .SAXIHP3WREADY (S_AXI_HP3_WREADY), .DDRARB (DDR_ARB), .DMA0ACLK (DMA0_ACLK ), .DMA0DAREADY (DMA0_DAREADY), .DMA0DRLAST (DMA0_DRLAST ), .DMA0DRTYPE (DMA0_DRTYPE), .DMA0DRVALID (DMA0_DRVALID), .DMA1ACLK (DMA1_ACLK ), .DMA1DAREADY (DMA1_DAREADY), .DMA1DRLAST (DMA1_DRLAST ), .DMA1DRTYPE (DMA1_DRTYPE), .DMA1DRVALID (DMA1_DRVALID), .DMA2ACLK (DMA2_ACLK ), .DMA2DAREADY (DMA2_DAREADY), .DMA2DRLAST (DMA2_DRLAST ), .DMA2DRTYPE (DMA2_DRTYPE), .DMA2DRVALID (DMA2_DRVALID), .DMA3ACLK (DMA3_ACLK ), .DMA3DAREADY (DMA3_DAREADY), .DMA3DRLAST (DMA3_DRLAST ), .DMA3DRTYPE (DMA3_DRTYPE), .DMA3DRVALID (DMA3_DRVALID), .EMIOCAN0PHYRX (CAN0_PHY_RX), .EMIOCAN1PHYRX (CAN1_PHY_RX), .EMIOENET0EXTINTIN (ENET0_EXT_INTIN), .EMIOENET0GMIICOL (ENET0_GMII_COL_i), .EMIOENET0GMIICRS (ENET0_GMII_CRS_i), .EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK), .EMIOENET0GMIIRXD (ENET0_GMII_RXD_i), .EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i), .EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i), .EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK), .EMIOENET0MDIOI (ENET0_MDIO_I), .EMIOENET1EXTINTIN (ENET1_EXT_INTIN), .EMIOENET1GMIICOL (ENET1_GMII_COL_i), .EMIOENET1GMIICRS (ENET1_GMII_CRS_i), .EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK), .EMIOENET1GMIIRXD (ENET1_GMII_RXD_i), .EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i), .EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i), .EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK), .EMIOENET1MDIOI (ENET1_MDIO_I), .EMIOGPIOI (gpio_in63_0 ), .EMIOI2C0SCLI (I2C0_SCL_I), .EMIOI2C0SDAI (I2C0_SDA_I), .EMIOI2C1SCLI (I2C1_SCL_I), .EMIOI2C1SDAI (I2C1_SDA_I), .EMIOPJTAGTCK (PJTAG_TCK), .EMIOPJTAGTDI (PJTAG_TDI), .EMIOPJTAGTMS (PJTAG_TMS), .EMIOSDIO0CDN (SDIO0_CDN), .EMIOSDIO0CLKFB (SDIO0_CLK_FB ), .EMIOSDIO0CMDI (SDIO0_CMD_I ), .EMIOSDIO0DATAI (SDIO0_DATA_I ), .EMIOSDIO0WP (SDIO0_WP), .EMIOSDIO1CDN (SDIO1_CDN), .EMIOSDIO1CLKFB (SDIO1_CLK_FB ), .EMIOSDIO1CMDI (SDIO1_CMD_I ), .EMIOSDIO1DATAI (SDIO1_DATA_I ), .EMIOSDIO1WP (SDIO1_WP), .EMIOSPI0MI (SPI0_MISO_I), .EMIOSPI0SCLKI (SPI0_SCLK_I), .EMIOSPI0SI (SPI0_MOSI_I), .EMIOSPI0SSIN (SPI0_SS_I), .EMIOSPI1MI (SPI1_MISO_I), .EMIOSPI1SCLKI (SPI1_SCLK_I), .EMIOSPI1SI (SPI1_MOSI_I), .EMIOSPI1SSIN (SPI1_SS_I), .EMIOSRAMINTIN (SRAM_INTIN), .EMIOTRACECLK (TRACE_CLK), .EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}), .EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}), .EMIOUART0CTSN (UART0_CTSN), .EMIOUART0DCDN (UART0_DCDN), .EMIOUART0DSRN (UART0_DSRN), .EMIOUART0RIN (UART0_RIN ), .EMIOUART0RX (UART0_RX ), .EMIOUART1CTSN (UART1_CTSN), .EMIOUART1DCDN (UART1_DCDN), .EMIOUART1DSRN (UART1_DSRN), .EMIOUART1RIN (UART1_RIN ), .EMIOUART1RX (UART1_RX ), .EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT), .EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT), .EMIOWDTCLKI (WDT_CLK_IN), .EVENTEVENTI (EVENT_EVENTI), .FCLKCLKTRIGN (fclk_clktrig_gnd), .FPGAIDLEN (FPGA_IDLE_N), .FTMDTRACEINATID (FTMD_TRACEIN_ATID_i), .FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK), .FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i), .FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i), .FTMTF2PDEBUG (FTMT_F2P_DEBUG ), .FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}), .FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}), .IRQF2P (irq_f2p_i), .MAXIGP0ACLK (M_AXI_GP0_ACLK_temp), .MAXIGP0ARREADY (M_AXI_GP0_ARREADY), .MAXIGP0AWREADY (M_AXI_GP0_AWREADY), .MAXIGP0BID (M_AXI_GP0_BID_FULL ), .MAXIGP0BRESP (M_AXI_GP0_BRESP ), .MAXIGP0BVALID (M_AXI_GP0_BVALID ), .MAXIGP0RDATA (M_AXI_GP0_RDATA ), .MAXIGP0RID (M_AXI_GP0_RID_FULL ), .MAXIGP0RLAST (M_AXI_GP0_RLAST ), .MAXIGP0RRESP (M_AXI_GP0_RRESP ), .MAXIGP0RVALID (M_AXI_GP0_RVALID ), .MAXIGP0WREADY (M_AXI_GP0_WREADY ), .MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ), .MAXIGP1ARREADY (M_AXI_GP1_ARREADY), .MAXIGP1AWREADY (M_AXI_GP1_AWREADY), .MAXIGP1BID (M_AXI_GP1_BID_FULL ), .MAXIGP1BRESP (M_AXI_GP1_BRESP ), .MAXIGP1BVALID (M_AXI_GP1_BVALID ), .MAXIGP1RDATA (M_AXI_GP1_RDATA ), .MAXIGP1RID (M_AXI_GP1_RID_FULL ), .MAXIGP1RLAST (M_AXI_GP1_RLAST ), .MAXIGP1RRESP (M_AXI_GP1_RRESP ), .MAXIGP1RVALID (M_AXI_GP1_RVALID ), .MAXIGP1WREADY (M_AXI_GP1_WREADY ), .SAXIACPACLK (S_AXI_ACP_ACLK_temp ), .SAXIACPARADDR (SAXIACPARADDR_W ), .SAXIACPARBURST (SAXIACPARBURST_W), .SAXIACPARCACHE (SAXIACPARCACHE_W), .SAXIACPARID (S_AXI_ACP_ARID_in ), .SAXIACPARLEN (SAXIACPARLEN_W ), .SAXIACPARLOCK (SAXIACPARLOCK_W ), .SAXIACPARPROT (SAXIACPARPROT_W ), .SAXIACPARQOS (S_AXI_ACP_ARQOS ), .SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ), .SAXIACPARUSER (SAXIACPARUSER_W ), .SAXIACPARVALID (SAXIACPARVALID_W), .SAXIACPAWADDR (SAXIACPAWADDR_W ), .SAXIACPAWBURST (SAXIACPAWBURST_W), .SAXIACPAWCACHE (SAXIACPAWCACHE_W), .SAXIACPAWID (S_AXI_ACP_AWID_in ), .SAXIACPAWLEN (SAXIACPAWLEN_W ), .SAXIACPAWLOCK (SAXIACPAWLOCK_W ), .SAXIACPAWPROT (SAXIACPAWPROT_W ), .SAXIACPAWQOS (S_AXI_ACP_AWQOS ), .SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ), .SAXIACPAWUSER (SAXIACPAWUSER_W ), .SAXIACPAWVALID (SAXIACPAWVALID_W), .SAXIACPBREADY (SAXIACPBREADY_W ), .SAXIACPRREADY (SAXIACPRREADY_W ), .SAXIACPWDATA (SAXIACPWDATA_W ), .SAXIACPWID (S_AXI_ACP_WID_in ), .SAXIACPWLAST (SAXIACPWLAST_W ), .SAXIACPWSTRB (SAXIACPWSTRB_W ), .SAXIACPWVALID (SAXIACPWVALID_W ), .SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ), .SAXIGP0ARADDR (S_AXI_GP0_ARADDR ), .SAXIGP0ARBURST (S_AXI_GP0_ARBURST), .SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE), .SAXIGP0ARID (S_AXI_GP0_ARID_in ), .SAXIGP0ARLEN (S_AXI_GP0_ARLEN ), .SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ), .SAXIGP0ARPROT (S_AXI_GP0_ARPROT ), .SAXIGP0ARQOS (S_AXI_GP0_ARQOS ), .SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ), .SAXIGP0ARVALID (S_AXI_GP0_ARVALID), .SAXIGP0AWADDR (S_AXI_GP0_AWADDR ), .SAXIGP0AWBURST (S_AXI_GP0_AWBURST), .SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE), .SAXIGP0AWID (S_AXI_GP0_AWID_in ), .SAXIGP0AWLEN (S_AXI_GP0_AWLEN ), .SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ), .SAXIGP0AWPROT (S_AXI_GP0_AWPROT ), .SAXIGP0AWQOS (S_AXI_GP0_AWQOS ), .SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ), .SAXIGP0AWVALID (S_AXI_GP0_AWVALID), .SAXIGP0BREADY (S_AXI_GP0_BREADY ), .SAXIGP0RREADY (S_AXI_GP0_RREADY ), .SAXIGP0WDATA (S_AXI_GP0_WDATA ), .SAXIGP0WID (S_AXI_GP0_WID_in ), .SAXIGP0WLAST (S_AXI_GP0_WLAST ), .SAXIGP0WSTRB (S_AXI_GP0_WSTRB ), .SAXIGP0WVALID (S_AXI_GP0_WVALID ), .SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ), .SAXIGP1ARADDR (S_AXI_GP1_ARADDR ), .SAXIGP1ARBURST (S_AXI_GP1_ARBURST), .SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE), .SAXIGP1ARID (S_AXI_GP1_ARID_in ), .SAXIGP1ARLEN (S_AXI_GP1_ARLEN ), .SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ), .SAXIGP1ARPROT (S_AXI_GP1_ARPROT ), .SAXIGP1ARQOS (S_AXI_GP1_ARQOS ), .SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ), .SAXIGP1ARVALID (S_AXI_GP1_ARVALID), .SAXIGP1AWADDR (S_AXI_GP1_AWADDR ), .SAXIGP1AWBURST (S_AXI_GP1_AWBURST), .SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE), .SAXIGP1AWID (S_AXI_GP1_AWID_in ), .SAXIGP1AWLEN (S_AXI_GP1_AWLEN ), .SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ), .SAXIGP1AWPROT (S_AXI_GP1_AWPROT ), .SAXIGP1AWQOS (S_AXI_GP1_AWQOS ), .SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ), .SAXIGP1AWVALID (S_AXI_GP1_AWVALID), .SAXIGP1BREADY (S_AXI_GP1_BREADY ), .SAXIGP1RREADY (S_AXI_GP1_RREADY ), .SAXIGP1WDATA (S_AXI_GP1_WDATA ), .SAXIGP1WID (S_AXI_GP1_WID_in ), .SAXIGP1WLAST (S_AXI_GP1_WLAST ), .SAXIGP1WSTRB (S_AXI_GP1_WSTRB ), .SAXIGP1WVALID (S_AXI_GP1_WVALID ), .SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ), .SAXIHP0ARADDR (S_AXI_HP0_ARADDR), .SAXIHP0ARBURST (S_AXI_HP0_ARBURST), .SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE), .SAXIHP0ARID (S_AXI_HP0_ARID_in), .SAXIHP0ARLEN (S_AXI_HP0_ARLEN), .SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK), .SAXIHP0ARPROT (S_AXI_HP0_ARPROT), .SAXIHP0ARQOS (S_AXI_HP0_ARQOS), .SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]), .SAXIHP0ARVALID (S_AXI_HP0_ARVALID), .SAXIHP0AWADDR (S_AXI_HP0_AWADDR), .SAXIHP0AWBURST (S_AXI_HP0_AWBURST), .SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE), .SAXIHP0AWID (S_AXI_HP0_AWID_in), .SAXIHP0AWLEN (S_AXI_HP0_AWLEN), .SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK), .SAXIHP0AWPROT (S_AXI_HP0_AWPROT), .SAXIHP0AWQOS (S_AXI_HP0_AWQOS), .SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]), .SAXIHP0AWVALID (S_AXI_HP0_AWVALID), .SAXIHP0BREADY (S_AXI_HP0_BREADY), .SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN), .SAXIHP0RREADY (S_AXI_HP0_RREADY), .SAXIHP0WDATA (S_AXI_HP0_WDATA_in), .SAXIHP0WID (S_AXI_HP0_WID_in), .SAXIHP0WLAST (S_AXI_HP0_WLAST), .SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN), .SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in), .SAXIHP0WVALID (S_AXI_HP0_WVALID), .SAXIHP1ACLK (S_AXI_HP1_ACLK_temp), .SAXIHP1ARADDR (S_AXI_HP1_ARADDR), .SAXIHP1ARBURST (S_AXI_HP1_ARBURST), .SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE), .SAXIHP1ARID (S_AXI_HP1_ARID_in), .SAXIHP1ARLEN (S_AXI_HP1_ARLEN), .SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK), .SAXIHP1ARPROT (S_AXI_HP1_ARPROT), .SAXIHP1ARQOS (S_AXI_HP1_ARQOS), .SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]), .SAXIHP1ARVALID (S_AXI_HP1_ARVALID), .SAXIHP1AWADDR (S_AXI_HP1_AWADDR), .SAXIHP1AWBURST (S_AXI_HP1_AWBURST), .SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE), .SAXIHP1AWID (S_AXI_HP1_AWID_in), .SAXIHP1AWLEN (S_AXI_HP1_AWLEN), .SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK), .SAXIHP1AWPROT (S_AXI_HP1_AWPROT), .SAXIHP1AWQOS (S_AXI_HP1_AWQOS), .SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]), .SAXIHP1AWVALID (S_AXI_HP1_AWVALID), .SAXIHP1BREADY (S_AXI_HP1_BREADY), .SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN), .SAXIHP1RREADY (S_AXI_HP1_RREADY), .SAXIHP1WDATA (S_AXI_HP1_WDATA_in), .SAXIHP1WID (S_AXI_HP1_WID_in), .SAXIHP1WLAST (S_AXI_HP1_WLAST), .SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN), .SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in), .SAXIHP1WVALID (S_AXI_HP1_WVALID), .SAXIHP2ACLK (S_AXI_HP2_ACLK_temp), .SAXIHP2ARADDR (S_AXI_HP2_ARADDR), .SAXIHP2ARBURST (S_AXI_HP2_ARBURST), .SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE), .SAXIHP2ARID (S_AXI_HP2_ARID_in), .SAXIHP2ARLEN (S_AXI_HP2_ARLEN), .SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK), .SAXIHP2ARPROT (S_AXI_HP2_ARPROT), .SAXIHP2ARQOS (S_AXI_HP2_ARQOS), .SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]), .SAXIHP2ARVALID (S_AXI_HP2_ARVALID), .SAXIHP2AWADDR (S_AXI_HP2_AWADDR), .SAXIHP2AWBURST (S_AXI_HP2_AWBURST), .SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE), .SAXIHP2AWID (S_AXI_HP2_AWID_in), .SAXIHP2AWLEN (S_AXI_HP2_AWLEN), .SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK), .SAXIHP2AWPROT (S_AXI_HP2_AWPROT), .SAXIHP2AWQOS (S_AXI_HP2_AWQOS), .SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]), .SAXIHP2AWVALID (S_AXI_HP2_AWVALID), .SAXIHP2BREADY (S_AXI_HP2_BREADY), .SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN), .SAXIHP2RREADY (S_AXI_HP2_RREADY), .SAXIHP2WDATA (S_AXI_HP2_WDATA_in), .SAXIHP2WID (S_AXI_HP2_WID_in), .SAXIHP2WLAST (S_AXI_HP2_WLAST), .SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN), .SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in), .SAXIHP2WVALID (S_AXI_HP2_WVALID), .SAXIHP3ACLK (S_AXI_HP3_ACLK_temp), .SAXIHP3ARADDR (S_AXI_HP3_ARADDR ), .SAXIHP3ARBURST (S_AXI_HP3_ARBURST), .SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE), .SAXIHP3ARID (S_AXI_HP3_ARID_in ), .SAXIHP3ARLEN (S_AXI_HP3_ARLEN), .SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK), .SAXIHP3ARPROT (S_AXI_HP3_ARPROT), .SAXIHP3ARQOS (S_AXI_HP3_ARQOS), .SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]), .SAXIHP3ARVALID (S_AXI_HP3_ARVALID), .SAXIHP3AWADDR (S_AXI_HP3_AWADDR), .SAXIHP3AWBURST (S_AXI_HP3_AWBURST), .SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE), .SAXIHP3AWID (S_AXI_HP3_AWID_in), .SAXIHP3AWLEN (S_AXI_HP3_AWLEN), .SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK), .SAXIHP3AWPROT (S_AXI_HP3_AWPROT), .SAXIHP3AWQOS (S_AXI_HP3_AWQOS), .SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]), .SAXIHP3AWVALID (S_AXI_HP3_AWVALID), .SAXIHP3BREADY (S_AXI_HP3_BREADY), .SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN), .SAXIHP3RREADY (S_AXI_HP3_RREADY), .SAXIHP3WDATA (S_AXI_HP3_WDATA_in), .SAXIHP3WID (S_AXI_HP3_WID_in), .SAXIHP3WLAST (S_AXI_HP3_WLAST), .SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN), .SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in), .SAXIHP3WVALID (S_AXI_HP3_WVALID), .DDRA (buffered_DDR_Addr), .DDRBA (buffered_DDR_BankAddr), .DDRCASB (buffered_DDR_CAS_n), .DDRCKE (buffered_DDR_CKE), .DDRCKN (buffered_DDR_Clk_n), .DDRCKP (buffered_DDR_Clk), .DDRCSB (buffered_DDR_CS_n), .DDRDM (buffered_DDR_DM), .DDRDQ (buffered_DDR_DQ), .DDRDQSN (buffered_DDR_DQS_n), .DDRDQSP (buffered_DDR_DQS), .DDRDRSTB (buffered_DDR_DRSTB), .DDRODT (buffered_DDR_ODT), .DDRRASB (buffered_DDR_RAS_n), .DDRVRN (buffered_DDR_VRN), .DDRVRP (buffered_DDR_VRP), .DDRWEB (buffered_DDR_WEB), .MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}), .PSCLK (buffered_PS_CLK), .PSPORB (buffered_PS_PORB), .PSSRSTB (buffered_PS_SRSTB) ); end else begin PS7 PS7_i ( .DMA0DATYPE (DMA0_DATYPE ), .DMA0DAVALID (DMA0_DAVALID), .DMA0DRREADY (DMA0_DRREADY), .DMA0RSTN (DMA0_RSTN ), .DMA1DATYPE (DMA1_DATYPE ), .DMA1DAVALID (DMA1_DAVALID), .DMA1DRREADY (DMA1_DRREADY), .DMA1RSTN (DMA1_RSTN ), .DMA2DATYPE (DMA2_DATYPE ), .DMA2DAVALID (DMA2_DAVALID), .DMA2DRREADY (DMA2_DRREADY), .DMA2RSTN (DMA2_RSTN ), .DMA3DATYPE (DMA3_DATYPE ), .DMA3DAVALID (DMA3_DAVALID), .DMA3DRREADY (DMA3_DRREADY), .DMA3RSTN (DMA3_RSTN ), .EMIOCAN0PHYTX (CAN0_PHY_TX ), .EMIOCAN1PHYTX (CAN1_PHY_TX ), .EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ), .EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i), .EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i), .EMIOENET0MDIOMDC (ENET0_MDIO_MDC), .EMIOENET0MDIOO (ENET0_MDIO_O ), .EMIOENET0MDIOTN (ENET0_MDIO_T_n ), .EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX), .EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX), .EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX), .EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX), .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX), .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX), .EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX), .EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX), .EMIOENET0SOFRX (ENET0_SOF_RX), .EMIOENET0SOFTX (ENET0_SOF_TX), .EMIOENET1GMIITXD (ENET1_GMII_TXD_i), // (ENET1_GMII_TXD_i), .EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i), .EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i), .EMIOENET1MDIOMDC (ENET1_MDIO_MDC), .EMIOENET1MDIOO (ENET1_MDIO_O ), .EMIOENET1MDIOTN (ENET1_MDIO_T_n), .EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX), .EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX), .EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX), .EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX), .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX), .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX), .EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX), .EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX), .EMIOENET1SOFRX (ENET1_SOF_RX), .EMIOENET1SOFTX (ENET1_SOF_TX), .EMIOGPIOO (gpio_out), .EMIOGPIOTN (gpio_out_t_n), .EMIOI2C0SCLO (I2C0_SCL_O), .EMIOI2C0SCLTN (I2C0_SCL_T_n), .EMIOI2C0SDAO (I2C0_SDA_O), .EMIOI2C0SDATN (I2C0_SDA_T_n), .EMIOI2C1SCLO (I2C1_SCL_O), .EMIOI2C1SCLTN (I2C1_SCL_T_n), .EMIOI2C1SDAO (I2C1_SDA_O), .EMIOI2C1SDATN (I2C1_SDA_T_n), .EMIOPJTAGTDO (PJTAG_TDO_O), .EMIOPJTAGTDTN (PJTAG_TDO_T_n), .EMIOSDIO0BUSPOW (SDIO0_BUSPOW), .EMIOSDIO0CLK (SDIO0_CLK ), .EMIOSDIO0CMDO (SDIO0_CMD_O ), .EMIOSDIO0CMDTN (SDIO0_CMD_T_n ), .EMIOSDIO0DATAO (SDIO0_DATA_O), .EMIOSDIO0DATATN (SDIO0_DATA_T_n), .EMIOSDIO0LED (SDIO0_LED), .EMIOSDIO1BUSPOW (SDIO1_BUSPOW), .EMIOSDIO1CLK (SDIO1_CLK ), .EMIOSDIO1CMDO (SDIO1_CMD_O ), .EMIOSDIO1CMDTN (SDIO1_CMD_T_n ), .EMIOSDIO1DATAO (SDIO1_DATA_O), .EMIOSDIO1DATATN (SDIO1_DATA_T_n), .EMIOSDIO1LED (SDIO1_LED), .EMIOSPI0MO (SPI0_MOSI_O), .EMIOSPI0MOTN (SPI0_MOSI_T_n), .EMIOSPI0SCLKO (SPI0_SCLK_O), .EMIOSPI0SCLKTN (SPI0_SCLK_T_n), .EMIOSPI0SO (SPI0_MISO_O), .EMIOSPI0STN (SPI0_MISO_T_n), .EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}), .EMIOSPI0SSNTN (SPI0_SS_T_n), .EMIOSPI1MO (SPI1_MOSI_O), .EMIOSPI1MOTN (SPI1_MOSI_T_n), .EMIOSPI1SCLKO (SPI1_SCLK_O), .EMIOSPI1SCLKTN (SPI1_SCLK_T_n), .EMIOSPI1SO (SPI1_MISO_O), .EMIOSPI1STN (SPI1_MISO_T_n), .EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}), .EMIOSPI1SSNTN (SPI1_SS_T_n), .EMIOTRACECTL (TRACE_CTL_i), .EMIOTRACEDATA (TRACE_DATA_i), .EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}), .EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}), .EMIOUART0DTRN (UART0_DTRN), .EMIOUART0RTSN (UART0_RTSN), .EMIOUART0TX (UART0_TX ), .EMIOUART1DTRN (UART1_DTRN), .EMIOUART1RTSN (UART1_RTSN), .EMIOUART1TX (UART1_TX ), .EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL), .EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT), .EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL), .EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT), .EMIOWDTRSTO (WDT_RST_OUT), .EVENTEVENTO (EVENT_EVENTO), .EVENTSTANDBYWFE (EVENT_STANDBYWFE), .EVENTSTANDBYWFI (EVENT_STANDBYWFI), .FCLKCLK (FCLK_CLK_unbuffered), .FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}), .EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT), .EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT), .FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}), .FTMTP2FDEBUG (FTMT_P2F_DEBUG ), .FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}), .IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}), .MAXIGP0ARADDR (M_AXI_GP0_ARADDR), .MAXIGP0ARBURST (M_AXI_GP0_ARBURST), .MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE), .MAXIGP0ARESETN (M_AXI_GP0_ARESETN), .MAXIGP0ARID (M_AXI_GP0_ARID_FULL ), .MAXIGP0ARLEN (M_AXI_GP0_ARLEN ), .MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ), .MAXIGP0ARPROT (M_AXI_GP0_ARPROT ), .MAXIGP0ARQOS (M_AXI_GP0_ARQOS ), .MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ), .MAXIGP0ARVALID (M_AXI_GP0_ARVALID), .MAXIGP0AWADDR (M_AXI_GP0_AWADDR ), .MAXIGP0AWBURST (M_AXI_GP0_AWBURST), .MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE), .MAXIGP0AWID (M_AXI_GP0_AWID_FULL ), .MAXIGP0AWLEN (M_AXI_GP0_AWLEN ), .MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ), .MAXIGP0AWPROT (M_AXI_GP0_AWPROT ), .MAXIGP0AWQOS (M_AXI_GP0_AWQOS ), .MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ), .MAXIGP0AWVALID (M_AXI_GP0_AWVALID), .MAXIGP0BREADY (M_AXI_GP0_BREADY ), .MAXIGP0RREADY (M_AXI_GP0_RREADY ), .MAXIGP0WDATA (M_AXI_GP0_WDATA ), .MAXIGP0WID (M_AXI_GP0_WID_FULL ), .MAXIGP0WLAST (M_AXI_GP0_WLAST ), .MAXIGP0WSTRB (M_AXI_GP0_WSTRB ), .MAXIGP0WVALID (M_AXI_GP0_WVALID ), .MAXIGP1ARADDR (M_AXI_GP1_ARADDR ), .MAXIGP1ARBURST (M_AXI_GP1_ARBURST), .MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE), .MAXIGP1ARESETN (M_AXI_GP1_ARESETN), .MAXIGP1ARID (M_AXI_GP1_ARID_FULL ), .MAXIGP1ARLEN (M_AXI_GP1_ARLEN ), .MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ), .MAXIGP1ARPROT (M_AXI_GP1_ARPROT ), .MAXIGP1ARQOS (M_AXI_GP1_ARQOS ), .MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ), .MAXIGP1ARVALID (M_AXI_GP1_ARVALID), .MAXIGP1AWADDR (M_AXI_GP1_AWADDR ), .MAXIGP1AWBURST (M_AXI_GP1_AWBURST), .MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE), .MAXIGP1AWID (M_AXI_GP1_AWID_FULL ), .MAXIGP1AWLEN (M_AXI_GP1_AWLEN ), .MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ), .MAXIGP1AWPROT (M_AXI_GP1_AWPROT ), .MAXIGP1AWQOS (M_AXI_GP1_AWQOS ), .MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ), .MAXIGP1AWVALID (M_AXI_GP1_AWVALID), .MAXIGP1BREADY (M_AXI_GP1_BREADY ), .MAXIGP1RREADY (M_AXI_GP1_RREADY ), .MAXIGP1WDATA (M_AXI_GP1_WDATA ), .MAXIGP1WID (M_AXI_GP1_WID_FULL ), .MAXIGP1WLAST (M_AXI_GP1_WLAST ), .MAXIGP1WSTRB (M_AXI_GP1_WSTRB ), .MAXIGP1WVALID (M_AXI_GP1_WVALID ), .SAXIACPARESETN (S_AXI_ACP_ARESETN), .SAXIACPARREADY (SAXIACPARREADY_W), .SAXIACPAWREADY (SAXIACPAWREADY_W), .SAXIACPBID (S_AXI_ACP_BID_out ), .SAXIACPBRESP (SAXIACPBRESP_W ), .SAXIACPBVALID (SAXIACPBVALID_W ), .SAXIACPRDATA (SAXIACPRDATA_W ), .SAXIACPRID (S_AXI_ACP_RID_out), .SAXIACPRLAST (SAXIACPRLAST_W ), .SAXIACPRRESP (SAXIACPRRESP_W ), .SAXIACPRVALID (SAXIACPRVALID_W ), .SAXIACPWREADY (SAXIACPWREADY_W ), .SAXIGP0ARESETN (S_AXI_GP0_ARESETN), .SAXIGP0ARREADY (S_AXI_GP0_ARREADY), .SAXIGP0AWREADY (S_AXI_GP0_AWREADY), .SAXIGP0BID (S_AXI_GP0_BID_out), .SAXIGP0BRESP (S_AXI_GP0_BRESP ), .SAXIGP0BVALID (S_AXI_GP0_BVALID ), .SAXIGP0RDATA (S_AXI_GP0_RDATA ), .SAXIGP0RID (S_AXI_GP0_RID_out ), .SAXIGP0RLAST (S_AXI_GP0_RLAST ), .SAXIGP0RRESP (S_AXI_GP0_RRESP ), .SAXIGP0RVALID (S_AXI_GP0_RVALID ), .SAXIGP0WREADY (S_AXI_GP0_WREADY ), .SAXIGP1ARESETN (S_AXI_GP1_ARESETN), .SAXIGP1ARREADY (S_AXI_GP1_ARREADY), .SAXIGP1AWREADY (S_AXI_GP1_AWREADY), .SAXIGP1BID (S_AXI_GP1_BID_out ), .SAXIGP1BRESP (S_AXI_GP1_BRESP ), .SAXIGP1BVALID (S_AXI_GP1_BVALID ), .SAXIGP1RDATA (S_AXI_GP1_RDATA ), .SAXIGP1RID (S_AXI_GP1_RID_out ), .SAXIGP1RLAST (S_AXI_GP1_RLAST ), .SAXIGP1RRESP (S_AXI_GP1_RRESP ), .SAXIGP1RVALID (S_AXI_GP1_RVALID ), .SAXIGP1WREADY (S_AXI_GP1_WREADY ), .SAXIHP0ARESETN (S_AXI_HP0_ARESETN), .SAXIHP0ARREADY (S_AXI_HP0_ARREADY), .SAXIHP0AWREADY (S_AXI_HP0_AWREADY), .SAXIHP0BID (S_AXI_HP0_BID_out ), .SAXIHP0BRESP (S_AXI_HP0_BRESP ), .SAXIHP0BVALID (S_AXI_HP0_BVALID ), .SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT), .SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT), .SAXIHP0RDATA (S_AXI_HP0_RDATA_out), .SAXIHP0RID (S_AXI_HP0_RID_out ), .SAXIHP0RLAST (S_AXI_HP0_RLAST), .SAXIHP0RRESP (S_AXI_HP0_RRESP), .SAXIHP0RVALID (S_AXI_HP0_RVALID), .SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT), .SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT), .SAXIHP0WREADY (S_AXI_HP0_WREADY), .SAXIHP1ARESETN (S_AXI_HP1_ARESETN), .SAXIHP1ARREADY (S_AXI_HP1_ARREADY), .SAXIHP1AWREADY (S_AXI_HP1_AWREADY), .SAXIHP1BID (S_AXI_HP1_BID_out ), .SAXIHP1BRESP (S_AXI_HP1_BRESP ), .SAXIHP1BVALID (S_AXI_HP1_BVALID ), .SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ), .SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ), .SAXIHP1RDATA (S_AXI_HP1_RDATA_out), .SAXIHP1RID (S_AXI_HP1_RID_out ), .SAXIHP1RLAST (S_AXI_HP1_RLAST ), .SAXIHP1RRESP (S_AXI_HP1_RRESP ), .SAXIHP1RVALID (S_AXI_HP1_RVALID), .SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT), .SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT), .SAXIHP1WREADY (S_AXI_HP1_WREADY), .SAXIHP2ARESETN (S_AXI_HP2_ARESETN), .SAXIHP2ARREADY (S_AXI_HP2_ARREADY), .SAXIHP2AWREADY (S_AXI_HP2_AWREADY), .SAXIHP2BID (S_AXI_HP2_BID_out ), .SAXIHP2BRESP (S_AXI_HP2_BRESP), .SAXIHP2BVALID (S_AXI_HP2_BVALID), .SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT), .SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT), .SAXIHP2RDATA (S_AXI_HP2_RDATA_out), .SAXIHP2RID (S_AXI_HP2_RID_out ), .SAXIHP2RLAST (S_AXI_HP2_RLAST), .SAXIHP2RRESP (S_AXI_HP2_RRESP), .SAXIHP2RVALID (S_AXI_HP2_RVALID), .SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT), .SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT), .SAXIHP2WREADY (S_AXI_HP2_WREADY), .SAXIHP3ARESETN (S_AXI_HP3_ARESETN), .SAXIHP3ARREADY (S_AXI_HP3_ARREADY), .SAXIHP3AWREADY (S_AXI_HP3_AWREADY), .SAXIHP3BID (S_AXI_HP3_BID_out), .SAXIHP3BRESP (S_AXI_HP3_BRESP), .SAXIHP3BVALID (S_AXI_HP3_BVALID), .SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT), .SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT), .SAXIHP3RDATA (S_AXI_HP3_RDATA_out), .SAXIHP3RID (S_AXI_HP3_RID_out), .SAXIHP3RLAST (S_AXI_HP3_RLAST), .SAXIHP3RRESP (S_AXI_HP3_RRESP), .SAXIHP3RVALID (S_AXI_HP3_RVALID), .SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT), .SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT), .SAXIHP3WREADY (S_AXI_HP3_WREADY), .DDRARB (DDR_ARB), .DMA0ACLK (DMA0_ACLK ), .DMA0DAREADY (DMA0_DAREADY), .DMA0DRLAST (DMA0_DRLAST ), .DMA0DRTYPE (DMA0_DRTYPE), .DMA0DRVALID (DMA0_DRVALID), .DMA1ACLK (DMA1_ACLK ), .DMA1DAREADY (DMA1_DAREADY), .DMA1DRLAST (DMA1_DRLAST ), .DMA1DRTYPE (DMA1_DRTYPE), .DMA1DRVALID (DMA1_DRVALID), .DMA2ACLK (DMA2_ACLK ), .DMA2DAREADY (DMA2_DAREADY), .DMA2DRLAST (DMA2_DRLAST ), .DMA2DRTYPE (DMA2_DRTYPE), .DMA2DRVALID (DMA2_DRVALID), .DMA3ACLK (DMA3_ACLK ), .DMA3DAREADY (DMA3_DAREADY), .DMA3DRLAST (DMA3_DRLAST ), .DMA3DRTYPE (DMA3_DRTYPE), .DMA3DRVALID (DMA3_DRVALID), .EMIOCAN0PHYRX (CAN0_PHY_RX), .EMIOCAN1PHYRX (CAN1_PHY_RX), .EMIOENET0EXTINTIN (ENET0_EXT_INTIN), .EMIOENET0GMIICOL (ENET0_GMII_COL_i), .EMIOENET0GMIICRS (ENET0_GMII_CRS_i), .EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK), .EMIOENET0GMIIRXD (ENET0_GMII_RXD_i), .EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i), .EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i), .EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK), .EMIOENET0MDIOI (ENET0_MDIO_I), .EMIOENET1EXTINTIN (ENET1_EXT_INTIN), .EMIOENET1GMIICOL (ENET1_GMII_COL_i), .EMIOENET1GMIICRS (ENET1_GMII_CRS_i), .EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK), .EMIOENET1GMIIRXD (ENET1_GMII_RXD_i), .EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i), .EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i), .EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK), .EMIOENET1MDIOI (ENET1_MDIO_I), .EMIOGPIOI (gpio_in63_0 ), .EMIOI2C0SCLI (I2C0_SCL_I), .EMIOI2C0SDAI (I2C0_SDA_I), .EMIOI2C1SCLI (I2C1_SCL_I), .EMIOI2C1SDAI (I2C1_SDA_I), .EMIOPJTAGTCK (PJTAG_TCK), .EMIOPJTAGTDI (PJTAG_TDI), .EMIOPJTAGTMS (PJTAG_TMS), .EMIOSDIO0CDN (SDIO0_CDN), .EMIOSDIO0CLKFB (SDIO0_CLK_FB ), .EMIOSDIO0CMDI (SDIO0_CMD_I ), .EMIOSDIO0DATAI (SDIO0_DATA_I ), .EMIOSDIO0WP (SDIO0_WP), .EMIOSDIO1CDN (SDIO1_CDN), .EMIOSDIO1CLKFB (SDIO1_CLK_FB ), .EMIOSDIO1CMDI (SDIO1_CMD_I ), .EMIOSDIO1DATAI (SDIO1_DATA_I ), .EMIOSDIO1WP (SDIO1_WP), .EMIOSPI0MI (SPI0_MISO_I), .EMIOSPI0SCLKI (SPI0_SCLK_I), .EMIOSPI0SI (SPI0_MOSI_I), .EMIOSPI0SSIN (SPI0_SS_I), .EMIOSPI1MI (SPI1_MISO_I), .EMIOSPI1SCLKI (SPI1_SCLK_I), .EMIOSPI1SI (SPI1_MOSI_I), .EMIOSPI1SSIN (SPI1_SS_I), .EMIOSRAMINTIN (SRAM_INTIN), .EMIOTRACECLK (TRACE_CLK), .EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}), .EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}), .EMIOUART0CTSN (UART0_CTSN), .EMIOUART0DCDN (UART0_DCDN), .EMIOUART0DSRN (UART0_DSRN), .EMIOUART0RIN (UART0_RIN ), .EMIOUART0RX (UART0_RX ), .EMIOUART1CTSN (UART1_CTSN), .EMIOUART1DCDN (UART1_DCDN), .EMIOUART1DSRN (UART1_DSRN), .EMIOUART1RIN (UART1_RIN ), .EMIOUART1RX (UART1_RX ), .EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT), .EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT), .EMIOWDTCLKI (WDT_CLK_IN), .EVENTEVENTI (EVENT_EVENTI), .FCLKCLKTRIGN (fclk_clktrig_gnd), .FPGAIDLEN (FPGA_IDLE_N), .FTMDTRACEINATID (FTMD_TRACEIN_ATID_i), .FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK), .FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i), .FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i), .FTMTF2PDEBUG (FTMT_F2P_DEBUG ), .FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}), .FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}), .IRQF2P (irq_f2p_i), .MAXIGP0ACLK (M_AXI_GP0_ACLK_temp), .MAXIGP0ARREADY (M_AXI_GP0_ARREADY), .MAXIGP0AWREADY (M_AXI_GP0_AWREADY), .MAXIGP0BID (M_AXI_GP0_BID_FULL ), .MAXIGP0BRESP (M_AXI_GP0_BRESP ), .MAXIGP0BVALID (M_AXI_GP0_BVALID ), .MAXIGP0RDATA (M_AXI_GP0_RDATA ), .MAXIGP0RID (M_AXI_GP0_RID_FULL ), .MAXIGP0RLAST (M_AXI_GP0_RLAST ), .MAXIGP0RRESP (M_AXI_GP0_RRESP ), .MAXIGP0RVALID (M_AXI_GP0_RVALID ), .MAXIGP0WREADY (M_AXI_GP0_WREADY ), .MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ), .MAXIGP1ARREADY (M_AXI_GP1_ARREADY), .MAXIGP1AWREADY (M_AXI_GP1_AWREADY), .MAXIGP1BID (M_AXI_GP1_BID_FULL ), .MAXIGP1BRESP (M_AXI_GP1_BRESP ), .MAXIGP1BVALID (M_AXI_GP1_BVALID ), .MAXIGP1RDATA (M_AXI_GP1_RDATA ), .MAXIGP1RID (M_AXI_GP1_RID_FULL ), .MAXIGP1RLAST (M_AXI_GP1_RLAST ), .MAXIGP1RRESP (M_AXI_GP1_RRESP ), .MAXIGP1RVALID (M_AXI_GP1_RVALID ), .MAXIGP1WREADY (M_AXI_GP1_WREADY ), .SAXIACPACLK (S_AXI_ACP_ACLK_temp), .SAXIACPARADDR (SAXIACPARADDR_W ), .SAXIACPARBURST (SAXIACPARBURST_W), .SAXIACPARCACHE (SAXIACPARCACHE_W), .SAXIACPARID (S_AXI_ACP_ARID_in ), .SAXIACPARLEN (SAXIACPARLEN_W ), .SAXIACPARLOCK (SAXIACPARLOCK_W ), .SAXIACPARPROT (SAXIACPARPROT_W ), .SAXIACPARQOS (S_AXI_ACP_ARQOS ), .SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ), .SAXIACPARUSER (SAXIACPARUSER_W ), .SAXIACPARVALID (SAXIACPARVALID_W), .SAXIACPAWADDR (SAXIACPAWADDR_W ), .SAXIACPAWBURST (SAXIACPAWBURST_W), .SAXIACPAWCACHE (SAXIACPAWCACHE_W), .SAXIACPAWID (S_AXI_ACP_AWID_in ), .SAXIACPAWLEN (SAXIACPAWLEN_W ), .SAXIACPAWLOCK (SAXIACPAWLOCK_W ), .SAXIACPAWPROT (SAXIACPAWPROT_W ), .SAXIACPAWQOS (S_AXI_ACP_AWQOS ), .SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ), .SAXIACPAWUSER (SAXIACPAWUSER_W ), .SAXIACPAWVALID (SAXIACPAWVALID_W), .SAXIACPBREADY (SAXIACPBREADY_W ), .SAXIACPRREADY (SAXIACPRREADY_W ), .SAXIACPWDATA (SAXIACPWDATA_W ), .SAXIACPWID (S_AXI_ACP_WID_in ), .SAXIACPWLAST (SAXIACPWLAST_W ), .SAXIACPWSTRB (SAXIACPWSTRB_W ), .SAXIACPWVALID (SAXIACPWVALID_W ), .SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ), .SAXIGP0ARADDR (S_AXI_GP0_ARADDR ), .SAXIGP0ARBURST (S_AXI_GP0_ARBURST), .SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE), .SAXIGP0ARID (S_AXI_GP0_ARID_in ), .SAXIGP0ARLEN (S_AXI_GP0_ARLEN ), .SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ), .SAXIGP0ARPROT (S_AXI_GP0_ARPROT ), .SAXIGP0ARQOS (S_AXI_GP0_ARQOS ), .SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ), .SAXIGP0ARVALID (S_AXI_GP0_ARVALID), .SAXIGP0AWADDR (S_AXI_GP0_AWADDR ), .SAXIGP0AWBURST (S_AXI_GP0_AWBURST), .SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE), .SAXIGP0AWID (S_AXI_GP0_AWID_in ), .SAXIGP0AWLEN (S_AXI_GP0_AWLEN ), .SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ), .SAXIGP0AWPROT (S_AXI_GP0_AWPROT ), .SAXIGP0AWQOS (S_AXI_GP0_AWQOS ), .SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ), .SAXIGP0AWVALID (S_AXI_GP0_AWVALID), .SAXIGP0BREADY (S_AXI_GP0_BREADY ), .SAXIGP0RREADY (S_AXI_GP0_RREADY ), .SAXIGP0WDATA (S_AXI_GP0_WDATA ), .SAXIGP0WID (S_AXI_GP0_WID_in ), .SAXIGP0WLAST (S_AXI_GP0_WLAST ), .SAXIGP0WSTRB (S_AXI_GP0_WSTRB ), .SAXIGP0WVALID (S_AXI_GP0_WVALID ), .SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ), .SAXIGP1ARADDR (S_AXI_GP1_ARADDR ), .SAXIGP1ARBURST (S_AXI_GP1_ARBURST), .SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE), .SAXIGP1ARID (S_AXI_GP1_ARID_in ), .SAXIGP1ARLEN (S_AXI_GP1_ARLEN ), .SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ), .SAXIGP1ARPROT (S_AXI_GP1_ARPROT ), .SAXIGP1ARQOS (S_AXI_GP1_ARQOS ), .SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ), .SAXIGP1ARVALID (S_AXI_GP1_ARVALID), .SAXIGP1AWADDR (S_AXI_GP1_AWADDR ), .SAXIGP1AWBURST (S_AXI_GP1_AWBURST), .SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE), .SAXIGP1AWID (S_AXI_GP1_AWID_in ), .SAXIGP1AWLEN (S_AXI_GP1_AWLEN ), .SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ), .SAXIGP1AWPROT (S_AXI_GP1_AWPROT ), .SAXIGP1AWQOS (S_AXI_GP1_AWQOS ), .SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ), .SAXIGP1AWVALID (S_AXI_GP1_AWVALID), .SAXIGP1BREADY (S_AXI_GP1_BREADY ), .SAXIGP1RREADY (S_AXI_GP1_RREADY ), .SAXIGP1WDATA (S_AXI_GP1_WDATA ), .SAXIGP1WID (S_AXI_GP1_WID_in ), .SAXIGP1WLAST (S_AXI_GP1_WLAST ), .SAXIGP1WSTRB (S_AXI_GP1_WSTRB ), .SAXIGP1WVALID (S_AXI_GP1_WVALID ), .SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ), .SAXIHP0ARADDR (S_AXI_HP0_ARADDR), .SAXIHP0ARBURST (S_AXI_HP0_ARBURST), .SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE), .SAXIHP0ARID (S_AXI_HP0_ARID_in), .SAXIHP0ARLEN (S_AXI_HP0_ARLEN), .SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK), .SAXIHP0ARPROT (S_AXI_HP0_ARPROT), .SAXIHP0ARQOS (S_AXI_HP0_ARQOS), .SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]), .SAXIHP0ARVALID (S_AXI_HP0_ARVALID), .SAXIHP0AWADDR (S_AXI_HP0_AWADDR), .SAXIHP0AWBURST (S_AXI_HP0_AWBURST), .SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE), .SAXIHP0AWID (S_AXI_HP0_AWID_in), .SAXIHP0AWLEN (S_AXI_HP0_AWLEN), .SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK), .SAXIHP0AWPROT (S_AXI_HP0_AWPROT), .SAXIHP0AWQOS (S_AXI_HP0_AWQOS), .SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]), .SAXIHP0AWVALID (S_AXI_HP0_AWVALID), .SAXIHP0BREADY (S_AXI_HP0_BREADY), .SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN), .SAXIHP0RREADY (S_AXI_HP0_RREADY), .SAXIHP0WDATA (S_AXI_HP0_WDATA_in), .SAXIHP0WID (S_AXI_HP0_WID_in), .SAXIHP0WLAST (S_AXI_HP0_WLAST), .SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN), .SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in), .SAXIHP0WVALID (S_AXI_HP0_WVALID), .SAXIHP1ACLK (S_AXI_HP1_ACLK_temp), .SAXIHP1ARADDR (S_AXI_HP1_ARADDR), .SAXIHP1ARBURST (S_AXI_HP1_ARBURST), .SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE), .SAXIHP1ARID (S_AXI_HP1_ARID_in), .SAXIHP1ARLEN (S_AXI_HP1_ARLEN), .SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK), .SAXIHP1ARPROT (S_AXI_HP1_ARPROT), .SAXIHP1ARQOS (S_AXI_HP1_ARQOS), .SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]), .SAXIHP1ARVALID (S_AXI_HP1_ARVALID), .SAXIHP1AWADDR (S_AXI_HP1_AWADDR), .SAXIHP1AWBURST (S_AXI_HP1_AWBURST), .SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE), .SAXIHP1AWID (S_AXI_HP1_AWID_in), .SAXIHP1AWLEN (S_AXI_HP1_AWLEN), .SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK), .SAXIHP1AWPROT (S_AXI_HP1_AWPROT), .SAXIHP1AWQOS (S_AXI_HP1_AWQOS), .SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]), .SAXIHP1AWVALID (S_AXI_HP1_AWVALID), .SAXIHP1BREADY (S_AXI_HP1_BREADY), .SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN), .SAXIHP1RREADY (S_AXI_HP1_RREADY), .SAXIHP1WDATA (S_AXI_HP1_WDATA_in), .SAXIHP1WID (S_AXI_HP1_WID_in), .SAXIHP1WLAST (S_AXI_HP1_WLAST), .SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN), .SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in), .SAXIHP1WVALID (S_AXI_HP1_WVALID), .SAXIHP2ACLK (S_AXI_HP2_ACLK_temp), .SAXIHP2ARADDR (S_AXI_HP2_ARADDR), .SAXIHP2ARBURST (S_AXI_HP2_ARBURST), .SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE), .SAXIHP2ARID (S_AXI_HP2_ARID_in), .SAXIHP2ARLEN (S_AXI_HP2_ARLEN), .SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK), .SAXIHP2ARPROT (S_AXI_HP2_ARPROT), .SAXIHP2ARQOS (S_AXI_HP2_ARQOS), .SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]), .SAXIHP2ARVALID (S_AXI_HP2_ARVALID), .SAXIHP2AWADDR (S_AXI_HP2_AWADDR), .SAXIHP2AWBURST (S_AXI_HP2_AWBURST), .SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE), .SAXIHP2AWID (S_AXI_HP2_AWID_in), .SAXIHP2AWLEN (S_AXI_HP2_AWLEN), .SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK), .SAXIHP2AWPROT (S_AXI_HP2_AWPROT), .SAXIHP2AWQOS (S_AXI_HP2_AWQOS), .SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]), .SAXIHP2AWVALID (S_AXI_HP2_AWVALID), .SAXIHP2BREADY (S_AXI_HP2_BREADY), .SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN), .SAXIHP2RREADY (S_AXI_HP2_RREADY), .SAXIHP2WDATA (S_AXI_HP2_WDATA_in), .SAXIHP2WID (S_AXI_HP2_WID_in), .SAXIHP2WLAST (S_AXI_HP2_WLAST), .SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN), .SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in), .SAXIHP2WVALID (S_AXI_HP2_WVALID), .SAXIHP3ACLK (S_AXI_HP3_ACLK_temp), .SAXIHP3ARADDR (S_AXI_HP3_ARADDR ), .SAXIHP3ARBURST (S_AXI_HP3_ARBURST), .SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE), .SAXIHP3ARID (S_AXI_HP3_ARID_in ), .SAXIHP3ARLEN (S_AXI_HP3_ARLEN), .SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK), .SAXIHP3ARPROT (S_AXI_HP3_ARPROT), .SAXIHP3ARQOS (S_AXI_HP3_ARQOS), .SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]), .SAXIHP3ARVALID (S_AXI_HP3_ARVALID), .SAXIHP3AWADDR (S_AXI_HP3_AWADDR), .SAXIHP3AWBURST (S_AXI_HP3_AWBURST), .SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE), .SAXIHP3AWID (S_AXI_HP3_AWID_in), .SAXIHP3AWLEN (S_AXI_HP3_AWLEN), .SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK), .SAXIHP3AWPROT (S_AXI_HP3_AWPROT), .SAXIHP3AWQOS (S_AXI_HP3_AWQOS), .SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]), .SAXIHP3AWVALID (S_AXI_HP3_AWVALID), .SAXIHP3BREADY (S_AXI_HP3_BREADY), .SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN), .SAXIHP3RREADY (S_AXI_HP3_RREADY), .SAXIHP3WDATA (S_AXI_HP3_WDATA_in), .SAXIHP3WID (S_AXI_HP3_WID_in), .SAXIHP3WLAST (S_AXI_HP3_WLAST), .SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN), .SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in), .SAXIHP3WVALID (S_AXI_HP3_WVALID), .DDRA (buffered_DDR_Addr), .DDRBA (buffered_DDR_BankAddr), .DDRCASB (buffered_DDR_CAS_n), .DDRCKE (buffered_DDR_CKE), .DDRCKN (buffered_DDR_Clk_n), .DDRCKP (buffered_DDR_Clk), .DDRCSB (buffered_DDR_CS_n), .DDRDM (buffered_DDR_DM), .DDRDQ (buffered_DDR_DQ), .DDRDQSN (buffered_DDR_DQS_n), .DDRDQSP (buffered_DDR_DQS), .DDRDRSTB (buffered_DDR_DRSTB), .DDRODT (buffered_DDR_ODT), .DDRRASB (buffered_DDR_RAS_n), .DDRVRN (buffered_DDR_VRN), .DDRVRP (buffered_DDR_VRP), .DDRWEB (buffered_DDR_WEB), .MIO (buffered_MIO), .PSCLK (buffered_PS_CLK), .PSPORB (buffered_PS_PORB), .PSSRSTB (buffered_PS_SRSTB) ); end endgenerate // Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled. // Otherwise a master connected to the ACP port will drive the AxUSER Ports assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER; assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER; assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR; assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST; assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE; assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN; assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK; assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT; assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE; //assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER; assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser; assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ; assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR; assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST; assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE; assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN; assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK; assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT; assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE; //assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER; assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser; assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID; assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY; assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY; assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA; assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST; assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB; assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID; assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID; assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID; assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID; generate if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W; assign S_AXI_ACP_WREADY = SAXIACPWREADY_W; assign S_AXI_ACP_BID = SAXIACPBID_W; assign S_AXI_ACP_BRESP = SAXIACPBRESP_W; assign S_AXI_ACP_BVALID = SAXIACPBVALID_W; assign S_AXI_ACP_RDATA = SAXIACPRDATA_W; assign S_AXI_ACP_RID = SAXIACPRID_W; assign S_AXI_ACP_RLAST = SAXIACPRLAST_W; assign S_AXI_ACP_RRESP = SAXIACPRRESP_W; assign S_AXI_ACP_RVALID = SAXIACPRVALID_W; assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W; end else begin : gen_atc processing_system7_v5_5_atc #( .C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH), .C_AXI_AWUSER_WIDTH (5), .C_AXI_ARUSER_WIDTH (5) ) atc_i ( // Global Signals .ACLK (S_AXI_ACP_ACLK_temp), .ARESETN (S_AXI_ACP_ARESETN), // Slave Interface Write Address Ports .S_AXI_AWID (S_AXI_ACP_AWID), .S_AXI_AWADDR (S_AXI_ACP_AWADDR), .S_AXI_AWLEN (S_AXI_ACP_AWLEN), .S_AXI_AWSIZE (S_AXI_ACP_AWSIZE), .S_AXI_AWBURST (S_AXI_ACP_AWBURST), .S_AXI_AWLOCK (S_AXI_ACP_AWLOCK), .S_AXI_AWCACHE (S_AXI_ACP_AWCACHE), .S_AXI_AWPROT (S_AXI_ACP_AWPROT), //.S_AXI_AWUSER (S_AXI_ACP_AWUSER), .S_AXI_AWUSER (param_awuser), .S_AXI_AWVALID (S_AXI_ACP_AWVALID), .S_AXI_AWREADY (S_AXI_ACP_AWREADY), // Slave Interface Write Data Ports .S_AXI_WID (S_AXI_ACP_WID), .S_AXI_WDATA (S_AXI_ACP_WDATA), .S_AXI_WSTRB (S_AXI_ACP_WSTRB), .S_AXI_WLAST (S_AXI_ACP_WLAST), .S_AXI_WUSER (), .S_AXI_WVALID (S_AXI_ACP_WVALID), .S_AXI_WREADY (S_AXI_ACP_WREADY), // Slave Interface Write Response Ports .S_AXI_BID (S_AXI_ACP_BID), .S_AXI_BRESP (S_AXI_ACP_BRESP), .S_AXI_BUSER (), .S_AXI_BVALID (S_AXI_ACP_BVALID), .S_AXI_BREADY (S_AXI_ACP_BREADY), // Slave Interface Read Address Ports .S_AXI_ARID (S_AXI_ACP_ARID), .S_AXI_ARADDR (S_AXI_ACP_ARADDR), .S_AXI_ARLEN (S_AXI_ACP_ARLEN), .S_AXI_ARSIZE (S_AXI_ACP_ARSIZE), .S_AXI_ARBURST (S_AXI_ACP_ARBURST), .S_AXI_ARLOCK (S_AXI_ACP_ARLOCK), .S_AXI_ARCACHE (S_AXI_ACP_ARCACHE), .S_AXI_ARPROT (S_AXI_ACP_ARPROT), //.S_AXI_ARUSER (S_AXI_ACP_ARUSER), .S_AXI_ARUSER (param_aruser), .S_AXI_ARVALID (S_AXI_ACP_ARVALID), .S_AXI_ARREADY (S_AXI_ACP_ARREADY), // Slave Interface Read Data Ports .S_AXI_RID (S_AXI_ACP_RID), .S_AXI_RDATA (S_AXI_ACP_RDATA), .S_AXI_RRESP (S_AXI_ACP_RRESP), .S_AXI_RLAST (S_AXI_ACP_RLAST), .S_AXI_RUSER (), .S_AXI_RVALID (S_AXI_ACP_RVALID), .S_AXI_RREADY (S_AXI_ACP_RREADY), // Slave Interface Write Address Ports .M_AXI_AWID (S_AXI_ATC_AWID), .M_AXI_AWADDR (S_AXI_ATC_AWADDR), .M_AXI_AWLEN (S_AXI_ATC_AWLEN), .M_AXI_AWSIZE (S_AXI_ATC_AWSIZE), .M_AXI_AWBURST (S_AXI_ATC_AWBURST), .M_AXI_AWLOCK (S_AXI_ATC_AWLOCK), .M_AXI_AWCACHE (S_AXI_ATC_AWCACHE), .M_AXI_AWPROT (S_AXI_ATC_AWPROT), .M_AXI_AWUSER (S_AXI_ATC_AWUSER), .M_AXI_AWVALID (S_AXI_ATC_AWVALID), .M_AXI_AWREADY (SAXIACPAWREADY_W), // Slave Interface Write Data Ports .M_AXI_WID (S_AXI_ATC_WID), .M_AXI_WDATA (S_AXI_ATC_WDATA), .M_AXI_WSTRB (S_AXI_ATC_WSTRB), .M_AXI_WLAST (S_AXI_ATC_WLAST), .M_AXI_WUSER (), .M_AXI_WVALID (S_AXI_ATC_WVALID), .M_AXI_WREADY (SAXIACPWREADY_W), // Slave Interface Write Response Ports .M_AXI_BID (SAXIACPBID_W), .M_AXI_BRESP (SAXIACPBRESP_W), .M_AXI_BUSER (), .M_AXI_BVALID (SAXIACPBVALID_W), .M_AXI_BREADY (S_AXI_ATC_BREADY), // Slave Interface Read Address Ports .M_AXI_ARID (S_AXI_ATC_ARID), .M_AXI_ARADDR (S_AXI_ATC_ARADDR), .M_AXI_ARLEN (S_AXI_ATC_ARLEN), .M_AXI_ARSIZE (S_AXI_ATC_ARSIZE), .M_AXI_ARBURST (S_AXI_ATC_ARBURST), .M_AXI_ARLOCK (S_AXI_ATC_ARLOCK), .M_AXI_ARCACHE (S_AXI_ATC_ARCACHE), .M_AXI_ARPROT (S_AXI_ATC_ARPROT), .M_AXI_ARUSER (S_AXI_ATC_ARUSER), .M_AXI_ARVALID (S_AXI_ATC_ARVALID), .M_AXI_ARREADY (SAXIACPARREADY_W), // Slave Interface Read Data Ports .M_AXI_RID (SAXIACPRID_W), .M_AXI_RDATA (SAXIACPRDATA_W), .M_AXI_RRESP (SAXIACPRRESP_W), .M_AXI_RLAST (SAXIACPRLAST_W), .M_AXI_RUSER (), .M_AXI_RVALID (SAXIACPRVALID_W), .M_AXI_RREADY (S_AXI_ATC_RREADY), .ERROR_TRIGGER(), .ERROR_TRANSACTION_ID() ); end endgenerate endmodule
//----------------------------------------------------------------- // AltOR32 // Alternative Lightweight OpenRisc // V2.1 // Ultra-Embedded.com // Copyright 2011 - 2014 // // Email: [email protected] // // License: LGPL //----------------------------------------------------------------- // // Copyright (C) 2011 - 2014 Ultra-Embedded.com // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // either version 2.1 of the License, or (at your option) any // later version. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, write to the // Free Software Foundation, Inc., 59 Temple Place, Suite 330, // Boston, MA 02111-1307 USA //----------------------------------------------------------------- //----------------------------------------------------------------- // Module - ALU //----------------------------------------------------------------- module altor32_alu ( // ALU operation select input [3:0] op_i /*verilator public*/, // Operands input [31:0] a_i /*verilator public*/, input [31:0] b_i /*verilator public*/, input c_i /*verilator public*/, // Result output [31:0] p_o /*verilator public*/, // Carry output reg c_o /*verilator public*/, output reg c_update_o /*verilator public*/, // Comparison output reg equal_o /*verilator public*/, output reg greater_than_signed_o /*verilator public*/, output reg greater_than_o /*verilator public*/, output reg less_than_signed_o /*verilator public*/, output reg less_than_o /*verilator public*/, output flag_update_o /*verilator public*/ ); //----------------------------------------------------------------- // Includes //----------------------------------------------------------------- `include "altor32_defs.v" `include "altor32_funcs.v" //----------------------------------------------------------------- // Registers //----------------------------------------------------------------- reg [31:0] result_r; reg [31:16] shift_right_fill_r; reg [31:0] shift_right_1_r; reg [31:0] shift_right_2_r; reg [31:0] shift_right_4_r; reg [31:0] shift_right_8_r; reg [31:0] shift_left_1_r; reg [31:0] shift_left_2_r; reg [31:0] shift_left_4_r; reg [31:0] shift_left_8_r; //----------------------------------------------------------------- // ALU //----------------------------------------------------------------- always @ (op_i or a_i or b_i or c_i) begin case (op_i) //---------------------------------------------- // Shift Left //---------------------------------------------- `ALU_SHIFTL : begin if (b_i[0] == 1'b1) shift_left_1_r = {a_i[30:0],1'b0}; else shift_left_1_r = a_i; if (b_i[1] == 1'b1) shift_left_2_r = {shift_left_1_r[29:0],2'b00}; else shift_left_2_r = shift_left_1_r; if (b_i[2] == 1'b1) shift_left_4_r = {shift_left_2_r[27:0],4'b0000}; else shift_left_4_r = shift_left_2_r; if (b_i[3] == 1'b1) shift_left_8_r = {shift_left_4_r[23:0],8'b00000000}; else shift_left_8_r = shift_left_4_r; if (b_i[4] == 1'b1) result_r = {shift_left_8_r[15:0],16'b0000000000000000}; else result_r = shift_left_8_r; c_o = 1'b0; c_update_o = 1'b0; end //---------------------------------------------- // Shift Right //---------------------------------------------- `ALU_SHIFTR, `ALU_SHIRTR_ARITH: begin // Arithmetic shift? Fill with 1's if MSB set if (a_i[31] == 1'b1 && op_i == `ALU_SHIRTR_ARITH) shift_right_fill_r = 16'b1111111111111111; else shift_right_fill_r = 16'b0000000000000000; if (b_i[0] == 1'b1) shift_right_1_r = {shift_right_fill_r[31], a_i[31:1]}; else shift_right_1_r = a_i; if (b_i[1] == 1'b1) shift_right_2_r = {shift_right_fill_r[31:30], shift_right_1_r[31:2]}; else shift_right_2_r = shift_right_1_r; if (b_i[2] == 1'b1) shift_right_4_r = {shift_right_fill_r[31:28], shift_right_2_r[31:4]}; else shift_right_4_r = shift_right_2_r; if (b_i[3] == 1'b1) shift_right_8_r = {shift_right_fill_r[31:24], shift_right_4_r[31:8]}; else shift_right_8_r = shift_right_4_r; if (b_i[4] == 1'b1) result_r = {shift_right_fill_r[31:16], shift_right_8_r[31:16]}; else result_r = shift_right_8_r; c_o = 1'b0; c_update_o = 1'b0; end //---------------------------------------------- // Arithmetic //---------------------------------------------- `ALU_ADD : begin {c_o, result_r} = (a_i + b_i); c_update_o = 1'b1; end `ALU_ADDC : begin {c_o, result_r} = (a_i + b_i) + {31'h00000000, c_i}; c_update_o = 1'b1; end `ALU_SUB : begin result_r = (a_i - b_i); c_o = 1'b0; c_update_o = 1'b0; end //---------------------------------------------- // Logical //---------------------------------------------- `ALU_AND : begin result_r = (a_i & b_i); c_o = 1'b0; c_update_o = 1'b0; end `ALU_OR : begin result_r = (a_i | b_i); c_o = 1'b0; c_update_o = 1'b0; end `ALU_XOR : begin result_r = (a_i ^ b_i); c_o = 1'b0; c_update_o = 1'b0; end default : begin result_r = a_i; c_o = 1'b0; c_update_o = 1'b0; end endcase end assign p_o = result_r; //----------------------------------------------------------------- // Comparisons //----------------------------------------------------------------- always @ * begin if (a_i == b_i) equal_o = 1'b1; else equal_o = 1'b0; if (a_i < b_i) less_than_o = 1'b1; else less_than_o = 1'b0; if (a_i > b_i) greater_than_o = 1'b1; else greater_than_o = 1'b0; less_than_signed_o = less_than_signed(a_i, b_i); greater_than_signed_o = ~(less_than_signed_o | equal_o); end assign flag_update_o = (op_i == `ALU_COMPARE); endmodule
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: Xilinx Inc // Design Name: PYNQ // Module Name: top // Project Name: PYNQ // Target Devices: ZC7020 // Tool Versions: 2016.1 // Description: ////////////////////////////////////////////////////////////////////////////////// module top( DDR_addr, DDR_ba, DDR_cas_n, DDR_ck_n, DDR_ck_p, DDR_cke, DDR_cs_n, DDR_dm, DDR_dq, DDR_dqs_n, DDR_dqs_p, DDR_odt, DDR_ras_n, DDR_reset_n, DDR_we_n, FIXED_IO_ddr_vrn, FIXED_IO_ddr_vrp, FIXED_IO_mio, FIXED_IO_ps_clk, FIXED_IO_ps_porb, FIXED_IO_ps_srstb, Vaux0_v_n, Vaux0_v_p, Vaux12_v_n, Vaux12_v_p, Vaux8_v_n, Vaux8_v_p, Vaux13_v_n, Vaux13_v_p, Vaux15_v_n, Vaux15_v_p, Vaux1_v_n, Vaux1_v_p, Vaux5_v_n, Vaux5_v_p, Vaux6_v_n, Vaux6_v_p, Vaux9_v_n, Vaux9_v_p, Vp_Vn_v_n, Vp_Vn_v_p, btns_4bits_tri_i, gpio_shield_sw_a5_a0_tri_io, gpio_shield_sw_d13_d2_tri_io, gpio_shield_sw_d1_d0_tri_io, ck_an_tri_io, ck_gpio_tri_io, hdmi_in_clk_n, hdmi_in_clk_p, hdmi_in_data_n, hdmi_in_data_p, hdmi_in_ddc_scl_io, hdmi_in_ddc_sda_io, hdmi_in_hpd, hdmi_out_clk_n, hdmi_out_clk_p, hdmi_out_data_n, hdmi_out_data_p, hdmi_out_ddc_scl_io, hdmi_out_ddc_sda_io, hdmi_out_hpd, iic_sw_shield_scl_io, iic_sw_shield_sda_io, leds_4bits_tri_o, spi_sw_shield_io0_io, spi_sw_shield_io1_io, spi_sw_shield_sck_io, spi_sw_shield_ss_io, pmodJA, pmodJB, pdm_audio_shutdown, pdm_m_clk, pdm_m_data_i, pwm_audio_o, rgbleds_6bits_tri_o, sws_2bits_tri_i); inout [14:0]DDR_addr; inout [2:0]DDR_ba; inout DDR_cas_n; inout DDR_ck_n; inout DDR_ck_p; inout DDR_cke; inout DDR_cs_n; inout [3:0]DDR_dm; inout [31:0]DDR_dq; inout [3:0]DDR_dqs_n; inout [3:0]DDR_dqs_p; inout DDR_odt; inout DDR_ras_n; inout DDR_reset_n; inout DDR_we_n; inout FIXED_IO_ddr_vrn; inout FIXED_IO_ddr_vrp; inout [53:0]FIXED_IO_mio; inout FIXED_IO_ps_clk; inout FIXED_IO_ps_porb; inout FIXED_IO_ps_srstb; input Vaux0_v_n; input Vaux0_v_p; input Vaux12_v_n; input Vaux12_v_p; input Vaux8_v_n; input Vaux8_v_p; input Vaux13_v_n; input Vaux13_v_p; input Vaux15_v_n; input Vaux15_v_p; input Vaux1_v_n; input Vaux1_v_p; input Vaux5_v_n; input Vaux5_v_p; input Vaux6_v_n; input Vaux6_v_p; input Vaux9_v_n; input Vaux9_v_p; input Vp_Vn_v_n; input Vp_Vn_v_p; input [3:0]btns_4bits_tri_i; inout [5:0]gpio_shield_sw_a5_a0_tri_io; inout [11:0]gpio_shield_sw_d13_d2_tri_io; inout [1:0]gpio_shield_sw_d1_d0_tri_io; inout [5:0]ck_an_tri_io; inout [15:0]ck_gpio_tri_io; input hdmi_in_clk_n; input hdmi_in_clk_p; input [2:0]hdmi_in_data_n; input [2:0]hdmi_in_data_p; inout hdmi_in_ddc_scl_io; inout hdmi_in_ddc_sda_io; output [0:0]hdmi_in_hpd; output hdmi_out_clk_n; output hdmi_out_clk_p; output [2:0]hdmi_out_data_n; output [2:0]hdmi_out_data_p; inout hdmi_out_ddc_scl_io; inout hdmi_out_ddc_sda_io; output [0:0]hdmi_out_hpd; inout iic_sw_shield_scl_io; inout iic_sw_shield_sda_io; output [3:0]leds_4bits_tri_o; input [1:0]sws_2bits_tri_i; inout spi_sw_shield_io0_io; inout spi_sw_shield_io1_io; inout spi_sw_shield_sck_io; inout spi_sw_shield_ss_io; inout [7:0]pmodJA; inout [7:0]pmodJB; output [0:0]pdm_audio_shutdown; output [0:0]pdm_m_clk; input pdm_m_data_i; output [5:0]rgbleds_6bits_tri_o; output [0:0]pwm_audio_o; wire [14:0]DDR_addr; wire [2:0]DDR_ba; wire DDR_cas_n; wire DDR_ck_n; wire DDR_ck_p; wire DDR_cke; wire DDR_cs_n; wire [3:0]DDR_dm; wire [31:0]DDR_dq; wire [3:0]DDR_dqs_n; wire [3:0]DDR_dqs_p; wire DDR_odt; wire DDR_ras_n; wire DDR_reset_n; wire DDR_we_n; wire FIXED_IO_ddr_vrn; wire FIXED_IO_ddr_vrp; wire [53:0]FIXED_IO_mio; wire FIXED_IO_ps_clk; wire FIXED_IO_ps_porb; wire FIXED_IO_ps_srstb; wire Vaux0_v_n; wire Vaux0_v_p; wire Vaux12_v_n; wire Vaux12_v_p; wire Vaux8_v_n; wire Vaux8_v_p; wire Vaux13_v_n; wire Vaux13_v_p; wire Vaux15_v_n; wire Vaux15_v_p; wire Vaux1_v_n; wire Vaux1_v_p; wire Vaux5_v_n; wire Vaux5_v_p; wire Vaux6_v_n; wire Vaux6_v_p; wire Vaux9_v_n; wire Vaux9_v_p; wire Vp_Vn_v_n; wire Vp_Vn_v_p; wire [3:0]btns_4bits_tri_i; wire [5:0]shield2sw_data_in_a5_a0; wire [11:0]shield2sw_data_in_d13_d2; wire [1:0]shield2sw_data_in_d1_d0; wire [5:0]sw2shield_data_out_a5_a0; wire [11:0]sw2shield_data_out_d13_d2; wire [1:0]sw2shield_data_out_d1_d0; wire [5:0]sw2shield_tri_out_a5_a0; wire [11:0]sw2shield_tri_out_d13_d2; wire [1:0]sw2shield_tri_out_d1_d0; wire [0:0]ck_gpio_tri_i_0; wire [1:1]ck_gpio_tri_i_1; wire [10:10]ck_gpio_tri_i_10; wire [11:11]ck_gpio_tri_i_11; wire [12:12]ck_gpio_tri_i_12; wire [13:13]ck_gpio_tri_i_13; wire [14:14]ck_gpio_tri_i_14; wire [15:15]ck_gpio_tri_i_15; wire [2:2]ck_gpio_tri_i_2; wire [3:3]ck_gpio_tri_i_3; wire [4:4]ck_gpio_tri_i_4; wire [5:5]ck_gpio_tri_i_5; wire [6:6]ck_gpio_tri_i_6; wire [7:7]ck_gpio_tri_i_7; wire [8:8]ck_gpio_tri_i_8; wire [9:9]ck_gpio_tri_i_9; wire [0:0]ck_gpio_tri_io_0; wire [1:1]ck_gpio_tri_io_1; wire [10:10]ck_gpio_tri_io_10; wire [11:11]ck_gpio_tri_io_11; wire [12:12]ck_gpio_tri_io_12; wire [13:13]ck_gpio_tri_io_13; wire [14:14]ck_gpio_tri_io_14; wire [15:15]ck_gpio_tri_io_15; wire [2:2]ck_gpio_tri_io_2; wire [3:3]ck_gpio_tri_io_3; wire [4:4]ck_gpio_tri_io_4; wire [5:5]ck_gpio_tri_io_5; wire [6:6]ck_gpio_tri_io_6; wire [7:7]ck_gpio_tri_io_7; wire [8:8]ck_gpio_tri_io_8; wire [9:9]ck_gpio_tri_io_9; wire [0:0]ck_gpio_tri_o_0; wire [1:1]ck_gpio_tri_o_1; wire [10:10]ck_gpio_tri_o_10; wire [11:11]ck_gpio_tri_o_11; wire [12:12]ck_gpio_tri_o_12; wire [13:13]ck_gpio_tri_o_13; wire [14:14]ck_gpio_tri_o_14; wire [15:15]ck_gpio_tri_o_15; wire [2:2]ck_gpio_tri_o_2; wire [3:3]ck_gpio_tri_o_3; wire [4:4]ck_gpio_tri_o_4; wire [5:5]ck_gpio_tri_o_5; wire [6:6]ck_gpio_tri_o_6; wire [7:7]ck_gpio_tri_o_7; wire [8:8]ck_gpio_tri_o_8; wire [9:9]ck_gpio_tri_o_9; wire [0:0]ck_gpio_tri_t_0; wire [1:1]ck_gpio_tri_t_1; wire [10:10]ck_gpio_tri_t_10; wire [11:11]ck_gpio_tri_t_11; wire [12:12]ck_gpio_tri_t_12; wire [13:13]ck_gpio_tri_t_13; wire [14:14]ck_gpio_tri_t_14; wire [15:15]ck_gpio_tri_t_15; wire [2:2]ck_gpio_tri_t_2; wire [3:3]ck_gpio_tri_t_3; wire [4:4]ck_gpio_tri_t_4; wire [5:5]ck_gpio_tri_t_5; wire [6:6]ck_gpio_tri_t_6; wire [7:7]ck_gpio_tri_t_7; wire [8:8]ck_gpio_tri_t_8; wire [9:9]ck_gpio_tri_t_9; wire hdmi_in_clk_n; wire hdmi_in_clk_p; wire [2:0]hdmi_in_data_n; wire [2:0]hdmi_in_data_p; wire hdmi_in_ddc_scl_i; wire hdmi_in_ddc_scl_io; wire hdmi_in_ddc_scl_o; wire hdmi_in_ddc_scl_t; wire hdmi_in_ddc_sda_i; wire hdmi_in_ddc_sda_io; wire hdmi_in_ddc_sda_o; wire hdmi_in_ddc_sda_t; wire [0:0]hdmi_in_hpd; wire hdmi_out_clk_n; wire hdmi_out_clk_p; wire [2:0]hdmi_out_data_n; wire [2:0]hdmi_out_data_p; wire hdmi_out_ddc_scl_i; wire hdmi_out_ddc_scl_io; wire hdmi_out_ddc_scl_o; wire hdmi_out_ddc_scl_t; wire hdmi_out_ddc_sda_i; wire hdmi_out_ddc_sda_io; wire hdmi_out_ddc_sda_o; wire hdmi_out_ddc_sda_t; wire [0:0]hdmi_out_hpd; wire shield2sw_scl_i_in; wire shield2sw_sda_i_in; wire sw2shield_scl_o_out; wire sw2shield_scl_t_out; wire sw2shield_sda_o_out; wire sw2shield_sda_t_out; // wire iic_sw_shield_scl_i; wire iic_sw_shield_scl_io; // wire iic_sw_shield_scl_o; // wire iic_sw_shield_scl_t; // wire iic_sw_shield_sda_i; wire iic_sw_shield_sda_io; // wire iic_sw_shield_sda_o; // wire iic_sw_shield_sda_t; wire [3:0]leds_4bits_tri_o; wire [7:0]pmodJA_data_in; wire [7:0]pmodJA_data_out; wire [7:0]pmodJA_tri_out; wire [7:0]pmodJB_data_in; wire [7:0]pmodJB_data_out; wire [7:0]pmodJB_tri_out; wire spi_sw_shield_io0_i; wire spi_sw_shield_io0_io; wire spi_sw_shield_io0_o; wire spi_sw_shield_io0_t; wire spi_sw_shield_io1_i; wire spi_sw_shield_io1_io; wire spi_sw_shield_io1_o; wire spi_sw_shield_io1_t; wire spi_sw_shield_sck_i; wire spi_sw_shield_sck_io; wire spi_sw_shield_sck_o; wire spi_sw_shield_sck_t; wire spi_sw_shield_ss_i; wire spi_sw_shield_ss_io; wire spi_sw_shield_ss_o; wire spi_sw_shield_ss_t; wire [1:0]sws_2bits_tri_i; wire [7:0]pmodJA; wire [7:0]pmodJB; wire [0:0]pdm_audio_shutdown; wire [0:0]pdm_m_clk; wire pdm_m_data_i; wire [5:0]rgbleds_6bits_tri_o; wire [0:0]pwm_audio_o; // ChipKit related header signals IOBUF ck_gpio_tri_iobuf_0 (.I(ck_gpio_tri_o_0), .IO(ck_gpio_tri_io[0]), .O(ck_gpio_tri_i_0), .T(ck_gpio_tri_t_0)); IOBUF ck_gpio_tri_iobuf_1 (.I(ck_gpio_tri_o_1), .IO(ck_gpio_tri_io[1]), .O(ck_gpio_tri_i_1), .T(ck_gpio_tri_t_1)); IOBUF ck_gpio_tri_iobuf_10 (.I(ck_gpio_tri_o_10), .IO(ck_gpio_tri_io[10]), .O(ck_gpio_tri_i_10), .T(ck_gpio_tri_t_10)); IOBUF ck_gpio_tri_iobuf_11 (.I(ck_gpio_tri_o_11), .IO(ck_gpio_tri_io[11]), .O(ck_gpio_tri_i_11), .T(ck_gpio_tri_t_11)); IOBUF ck_gpio_tri_iobuf_12 (.I(ck_gpio_tri_o_12), .IO(ck_gpio_tri_io[12]), .O(ck_gpio_tri_i_12), .T(ck_gpio_tri_t_12)); IOBUF ck_gpio_tri_iobuf_13 (.I(ck_gpio_tri_o_13), .IO(ck_gpio_tri_io[13]), .O(ck_gpio_tri_i_13), .T(ck_gpio_tri_t_13)); IOBUF ck_gpio_tri_iobuf_14 (.I(ck_gpio_tri_o_14), .IO(ck_gpio_tri_io[14]), .O(ck_gpio_tri_i_14), .T(ck_gpio_tri_t_14)); IOBUF ck_gpio_tri_iobuf_15 (.I(ck_gpio_tri_o_15), .IO(ck_gpio_tri_io[15]), .O(ck_gpio_tri_i_15), .T(ck_gpio_tri_t_15)); IOBUF ck_gpio_tri_iobuf_2 (.I(ck_gpio_tri_o_2), .IO(ck_gpio_tri_io[2]), .O(ck_gpio_tri_i_2), .T(ck_gpio_tri_t_2)); IOBUF ck_gpio_tri_iobuf_3 (.I(ck_gpio_tri_o_3), .IO(ck_gpio_tri_io[3]), .O(ck_gpio_tri_i_3), .T(ck_gpio_tri_t_3)); IOBUF ck_gpio_tri_iobuf_4 (.I(ck_gpio_tri_o_4), .IO(ck_gpio_tri_io[4]), .O(ck_gpio_tri_i_4), .T(ck_gpio_tri_t_4)); IOBUF ck_gpio_tri_iobuf_5 (.I(ck_gpio_tri_o_5), .IO(ck_gpio_tri_io[5]), .O(ck_gpio_tri_i_5), .T(ck_gpio_tri_t_5)); IOBUF ck_gpio_tri_iobuf_6 (.I(ck_gpio_tri_o_6), .IO(ck_gpio_tri_io[6]), .O(ck_gpio_tri_i_6), .T(ck_gpio_tri_t_6)); IOBUF ck_gpio_tri_iobuf_7 (.I(ck_gpio_tri_o_7), .IO(ck_gpio_tri_io[7]), .O(ck_gpio_tri_i_7), .T(ck_gpio_tri_t_7)); IOBUF ck_gpio_tri_iobuf_8 (.I(ck_gpio_tri_o_8), .IO(ck_gpio_tri_io[8]), .O(ck_gpio_tri_i_8), .T(ck_gpio_tri_t_8)); IOBUF ck_gpio_tri_iobuf_9 (.I(ck_gpio_tri_o_9), .IO(ck_gpio_tri_io[9]), .O(ck_gpio_tri_i_9), .T(ck_gpio_tri_t_9)); // for HDMI in IOBUF hdmi_in_ddc_scl_iobuf (.I(hdmi_in_ddc_scl_o), .IO(hdmi_in_ddc_scl_io), .O(hdmi_in_ddc_scl_i), .T(hdmi_in_ddc_scl_t)); IOBUF hdmi_in_ddc_sda_iobuf (.I(hdmi_in_ddc_sda_o), .IO(hdmi_in_ddc_sda_io), .O(hdmi_in_ddc_sda_i), .T(hdmi_in_ddc_sda_t)); // for HDMI out IOBUF hdmi_out_ddc_scl_iobuf (.I(hdmi_out_ddc_scl_o), .IO(hdmi_out_ddc_scl_io), .O(hdmi_out_ddc_scl_i), .T(hdmi_out_ddc_scl_t)); IOBUF hdmi_out_ddc_sda_iobuf (.I(hdmi_out_ddc_sda_o), .IO(hdmi_out_ddc_sda_io), .O(hdmi_out_ddc_sda_i), .T(hdmi_out_ddc_sda_t)); // pmodJB related iobufs IOBUF pmodJB_data_iobuf_0 (.I(pmodJB_data_out[0]), .IO(pmodJB[0]), .O(pmodJB_data_in[0]), .T(pmodJB_tri_out[0])); IOBUF pmodJB_data_iobuf_1 (.I(pmodJB_data_out[1]), .IO(pmodJB[1]), .O(pmodJB_data_in[1]), .T(pmodJB_tri_out[1])); IOBUF pmodJB_data_iobuf2 (.I(pmodJB_data_out[2]), .IO(pmodJB[2]), .O(pmodJB_data_in[2]), .T(pmodJB_tri_out[2])); IOBUF pmodJB_data_iobuf_3 (.I(pmodJB_data_out[3]), .IO(pmodJB[3]), .O(pmodJB_data_in[3]), .T(pmodJB_tri_out[3])); IOBUF pmodJB_data_iobuf_4 (.I(pmodJB_data_out[4]), .IO(pmodJB[4]), .O(pmodJB_data_in[4]), .T(pmodJB_tri_out[4])); IOBUF pmodJB_data_iobuf_5 (.I(pmodJB_data_out[5]), .IO(pmodJB[5]), .O(pmodJB_data_in[5]), .T(pmodJB_tri_out[5])); IOBUF pmodJB_data_iobuf_6 (.I(pmodJB_data_out[6]), .IO(pmodJB[6]), .O(pmodJB_data_in[6]), .T(pmodJB_tri_out[6])); IOBUF pmodJB_data_iobuf_7 (.I(pmodJB_data_out[7]), .IO(pmodJB[7]), .O(pmodJB_data_in[7]), .T(pmodJB_tri_out[7])); // pmodJA related iobufs IOBUF pmodJA_data_iobuf_0 (.I(pmodJA_data_out[0]), .IO(pmodJA[0]), .O(pmodJA_data_in[0]), .T(pmodJA_tri_out[0])); IOBUF pmodJA_data_iobuf_1 (.I(pmodJA_data_out[1]), .IO(pmodJA[1]), .O(pmodJA_data_in[1]), .T(pmodJA_tri_out[1])); IOBUF pmodJA_data_iobuf2 (.I(pmodJA_data_out[2]), .IO(pmodJA[2]), .O(pmodJA_data_in[2]), .T(pmodJA_tri_out[2])); IOBUF pmodJA_data_iobuf_3 (.I(pmodJA_data_out[3]), .IO(pmodJA[3]), .O(pmodJA_data_in[3]), .T(pmodJA_tri_out[3])); IOBUF pmodJA_data_iobuf_4 (.I(pmodJA_data_out[4]), .IO(pmodJA[4]), .O(pmodJA_data_in[4]), .T(pmodJA_tri_out[4])); IOBUF pmodJA_data_iobuf_5 (.I(pmodJA_data_out[5]), .IO(pmodJA[5]), .O(pmodJA_data_in[5]), .T(pmodJA_tri_out[5])); IOBUF pmodJA_data_iobuf_6 (.I(pmodJA_data_out[6]), .IO(pmodJA[6]), .O(pmodJA_data_in[6]), .T(pmodJA_tri_out[6])); IOBUF pmodJA_data_iobuf_7 (.I(pmodJA_data_out[7]), .IO(pmodJA[7]), .O(pmodJA_data_in[7]), .T(pmodJA_tri_out[7])); // Arduino shield related iobufs IOBUF gpio_shield_sw_a5_a0_tri_iobuf_0 (.I(sw2shield_data_out_a5_a0[0]), .IO(gpio_shield_sw_a5_a0_tri_io[0]), .O(shield2sw_data_in_a5_a0[0]), .T(sw2shield_tri_out_a5_a0[0])); IOBUF gpio_shield_sw_a5_a0_tri_iobuf_1 (.I(sw2shield_data_out_a5_a0[1]), .IO(gpio_shield_sw_a5_a0_tri_io[1]), .O(shield2sw_data_in_a5_a0[1]), .T(sw2shield_tri_out_a5_a0[1])); IOBUF gpio_shield_sw_a5_a0_tri_iobuf_2 (.I(sw2shield_data_out_a5_a0[2]), .IO(gpio_shield_sw_a5_a0_tri_io[2]), .O(shield2sw_data_in_a5_a0[2]), .T(sw2shield_tri_out_a5_a0[2])); IOBUF gpio_shield_sw_a5_a0_tri_iobuf_3 (.I(sw2shield_data_out_a5_a0[3]), .IO(gpio_shield_sw_a5_a0_tri_io[3]), .O(shield2sw_data_in_a5_a0[3]), .T(sw2shield_tri_out_a5_a0[3])); IOBUF gpio_shield_sw_a5_a0_tri_iobuf_4 (.I(sw2shield_data_out_a5_a0[4]), .IO(gpio_shield_sw_a5_a0_tri_io[4]), .O(shield2sw_data_in_a5_a0[4]), .T(sw2shield_tri_out_a5_a0[4])); IOBUF gpio_shield_sw_a5_a0_tri_iobuf_5 (.I(sw2shield_data_out_a5_a0[5]), .IO(gpio_shield_sw_a5_a0_tri_io[5]), .O(shield2sw_data_in_a5_a0[5]), .T(sw2shield_tri_out_a5_a0[5])); IOBUF gpio_shield_sw_d13_d2_tri_iobuf_0 (.I(sw2shield_data_out_d13_d2[0]), .IO(gpio_shield_sw_d13_d2_tri_io[0]), .O(shield2sw_data_in_d13_d2[0]), .T(sw2shield_tri_out_d13_d2[0])); IOBUF gpio_shield_sw_d13_d2_tri_iobuf_1 (.I(sw2shield_data_out_d13_d2[1]), .IO(gpio_shield_sw_d13_d2_tri_io[1]), .O(shield2sw_data_in_d13_d2[1]), .T(sw2shield_tri_out_d13_d2[1])); IOBUF gpio_shield_sw_d13_d2_tri_iobuf_10 (.I(sw2shield_data_out_d13_d2[10]), .IO(gpio_shield_sw_d13_d2_tri_io[10]), .O(shield2sw_data_in_d13_d2[10]), .T(sw2shield_tri_out_d13_d2[10])); IOBUF gpio_shield_sw_d13_d2_tri_iobuf_11 (.I(sw2shield_data_out_d13_d2[11]), .IO(gpio_shield_sw_d13_d2_tri_io[11]), .O(shield2sw_data_in_d13_d2[11]), .T(sw2shield_tri_out_d13_d2[11])); IOBUF gpio_shield_sw_d13_d2_tri_iobuf_2 (.I(sw2shield_data_out_d13_d2[2]), .IO(gpio_shield_sw_d13_d2_tri_io[2]), .O(shield2sw_data_in_d13_d2[2]), .T(sw2shield_tri_out_d13_d2[2])); IOBUF gpio_shield_sw_d13_d2_tri_iobuf_3 (.I(sw2shield_data_out_d13_d2[3]), .IO(gpio_shield_sw_d13_d2_tri_io[3]), .O(shield2sw_data_in_d13_d2[3]), .T(sw2shield_tri_out_d13_d2[3])); IOBUF gpio_shield_sw_d13_d2_tri_iobuf_4 (.I(sw2shield_data_out_d13_d2[4]), .IO(gpio_shield_sw_d13_d2_tri_io[4]), .O(shield2sw_data_in_d13_d2[4]), .T(sw2shield_tri_out_d13_d2[4])); IOBUF gpio_shield_sw_d13_d2_tri_iobuf_5 (.I(sw2shield_data_out_d13_d2[5]), .IO(gpio_shield_sw_d13_d2_tri_io[5]), .O(shield2sw_data_in_d13_d2[5]), .T(sw2shield_tri_out_d13_d2[5])); IOBUF gpio_shield_sw_d13_d2_tri_iobuf_6 (.I(sw2shield_data_out_d13_d2[6]), .IO(gpio_shield_sw_d13_d2_tri_io[6]), .O(shield2sw_data_in_d13_d2[6]), .T(sw2shield_tri_out_d13_d2[6])); IOBUF gpio_shield_sw_d13_d2_tri_iobuf_7 (.I(sw2shield_data_out_d13_d2[7]), .IO(gpio_shield_sw_d13_d2_tri_io[7]), .O(shield2sw_data_in_d13_d2[7]), .T(sw2shield_tri_out_d13_d2[7])); IOBUF gpio_shield_sw_d13_d2_tri_iobuf_8 (.I(sw2shield_data_out_d13_d2[8]), .IO(gpio_shield_sw_d13_d2_tri_io[8]), .O(shield2sw_data_in_d13_d2[8]), .T(sw2shield_tri_out_d13_d2[8])); IOBUF gpio_shield_sw_d13_d2_tri_iobuf_9 (.I(sw2shield_data_out_d13_d2[9]), .IO(gpio_shield_sw_d13_d2_tri_io[9]), .O(shield2sw_data_in_d13_d2[9]), .T(sw2shield_tri_out_d13_d2[9])); IOBUF gpio_shield_sw_d1_d0_tri_iobuf_0 (.I(sw2shield_data_out_d1_d0[0]), .IO(gpio_shield_sw_d1_d0_tri_io[0]), .O(shield2sw_data_in_d1_d0[0]), .T(sw2shield_tri_out_d1_d0[0])); IOBUF gpio_shield_sw_d1_d0_tri_iobuf_1 (.I(sw2shield_data_out_d1_d0[1]), .IO(gpio_shield_sw_d1_d0_tri_io[1]), .O(shield2sw_data_in_d1_d0[1]), .T(sw2shield_tri_out_d1_d0[1])); // Dedicated Arduino IIC shield2sw_scl_i_in IOBUF iic_sw_shield_scl_iobuf (.I(sw2shield_scl_o_out), .IO(iic_sw_shield_scl_io), .O(shield2sw_scl_i_in), .T(sw2shield_scl_t_out)); IOBUF iic_sw_shield_sda_iobuf (.I(sw2shield_sda_o_out), .IO(iic_sw_shield_sda_io), .O(shield2sw_sda_i_in), .T(sw2shield_sda_t_out)); // Dedicated Arduino SPI IOBUF spi_sw_shield_io0_iobuf (.I(spi_sw_shield_io0_o), .IO(spi_sw_shield_io0_io), .O(spi_sw_shield_io0_i), .T(spi_sw_shield_io0_t)); IOBUF spi_sw_shield_io1_iobuf (.I(spi_sw_shield_io1_o), .IO(spi_sw_shield_io1_io), .O(spi_sw_shield_io1_i), .T(spi_sw_shield_io1_t)); IOBUF spi_sw_shield_sck_iobuf (.I(spi_sw_shield_sck_o), .IO(spi_sw_shield_sck_io), .O(spi_sw_shield_sck_i), .T(spi_sw_shield_sck_t)); IOBUF spi_sw_shield_ss_iobuf (.I(spi_sw_shield_ss_o), .IO(spi_sw_shield_ss_io), .O(spi_sw_shield_ss_i), .T(spi_sw_shield_ss_t)); system system_i (.DDR_addr(DDR_addr), .DDR_ba(DDR_ba), .DDR_cas_n(DDR_cas_n), .DDR_ck_n(DDR_ck_n), .DDR_ck_p(DDR_ck_p), .DDR_cke(DDR_cke), .DDR_cs_n(DDR_cs_n), .DDR_dm(DDR_dm), .DDR_dq(DDR_dq), .DDR_dqs_n(DDR_dqs_n), .DDR_dqs_p(DDR_dqs_p), .DDR_odt(DDR_odt), .DDR_ras_n(DDR_ras_n), .DDR_reset_n(DDR_reset_n), .DDR_we_n(DDR_we_n), .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn), .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp), .FIXED_IO_mio(FIXED_IO_mio), .FIXED_IO_ps_clk(FIXED_IO_ps_clk), .FIXED_IO_ps_porb(FIXED_IO_ps_porb), .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb), .Vaux0_v_n(Vaux0_v_n), .Vaux0_v_p(Vaux0_v_p), .Vaux12_v_n(Vaux12_v_n), .Vaux12_v_p(Vaux12_v_p), .Vaux8_v_n(Vaux8_v_n), .Vaux8_v_p(Vaux8_v_p), .Vaux13_v_n(Vaux13_v_n), .Vaux13_v_p(Vaux13_v_p), .Vaux15_v_n(Vaux15_v_n), .Vaux15_v_p(Vaux15_v_p), .Vaux1_v_n(Vaux1_v_n), .Vaux1_v_p(Vaux1_v_p), .Vaux5_v_n(Vaux5_v_n), .Vaux5_v_p(Vaux5_v_p), .Vaux6_v_n(Vaux6_v_n), .Vaux6_v_p(Vaux6_v_p), .Vaux9_v_n(Vaux9_v_n), .Vaux9_v_p(Vaux9_v_p), .Vp_Vn_v_n(Vp_Vn_v_n), .Vp_Vn_v_p(Vp_Vn_v_p), .btns_4bits_tri_i(btns_4bits_tri_i), // .ck_an_tri_i({ck_an_tri_i_5,ck_an_tri_i_4,ck_an_tri_i_3,ck_an_tri_i_2,ck_an_tri_i_1,ck_an_tri_i_0}), // .ck_an_tri_o({ck_an_tri_o_5,ck_an_tri_o_4,ck_an_tri_o_3,ck_an_tri_o_2,ck_an_tri_o_1,ck_an_tri_o_0}), // .ck_an_tri_t({ck_an_tri_t_5,ck_an_tri_t_4,ck_an_tri_t_3,ck_an_tri_t_2,ck_an_tri_t_1,ck_an_tri_t_0}), .ck_gpio_tri_i({ck_gpio_tri_i_15,ck_gpio_tri_i_14,ck_gpio_tri_i_13,ck_gpio_tri_i_12,ck_gpio_tri_i_11,ck_gpio_tri_i_10,ck_gpio_tri_i_9,ck_gpio_tri_i_8,ck_gpio_tri_i_7,ck_gpio_tri_i_6,ck_gpio_tri_i_5,ck_gpio_tri_i_4,ck_gpio_tri_i_3,ck_gpio_tri_i_2,ck_gpio_tri_i_1,ck_gpio_tri_i_0}), .ck_gpio_tri_o({ck_gpio_tri_o_15,ck_gpio_tri_o_14,ck_gpio_tri_o_13,ck_gpio_tri_o_12,ck_gpio_tri_o_11,ck_gpio_tri_o_10,ck_gpio_tri_o_9,ck_gpio_tri_o_8,ck_gpio_tri_o_7,ck_gpio_tri_o_6,ck_gpio_tri_o_5,ck_gpio_tri_o_4,ck_gpio_tri_o_3,ck_gpio_tri_o_2,ck_gpio_tri_o_1,ck_gpio_tri_o_0}), .ck_gpio_tri_t({ck_gpio_tri_t_15,ck_gpio_tri_t_14,ck_gpio_tri_t_13,ck_gpio_tri_t_12,ck_gpio_tri_t_11,ck_gpio_tri_t_10,ck_gpio_tri_t_9,ck_gpio_tri_t_8,ck_gpio_tri_t_7,ck_gpio_tri_t_6,ck_gpio_tri_t_5,ck_gpio_tri_t_4,ck_gpio_tri_t_3,ck_gpio_tri_t_2,ck_gpio_tri_t_1,ck_gpio_tri_t_0}), // .gpio_shield_sw_a5_a0_tri_i({gpio_shield_sw_a5_a0_tri_i_5,gpio_shield_sw_a5_a0_tri_i_4,gpio_shield_sw_a5_a0_tri_i_3,gpio_shield_sw_a5_a0_tri_i_2,gpio_shield_sw_a5_a0_tri_i_1,gpio_shield_sw_a5_a0_tri_i_0}), // .gpio_shield_sw_a5_a0_tri_o({gpio_shield_sw_a5_a0_tri_o_5,gpio_shield_sw_a5_a0_tri_o_4,gpio_shield_sw_a5_a0_tri_o_3,gpio_shield_sw_a5_a0_tri_o_2,gpio_shield_sw_a5_a0_tri_o_1,gpio_shield_sw_a5_a0_tri_o_0}), // .gpio_shield_sw_a5_a0_tri_t({gpio_shield_sw_a5_a0_tri_t_5,gpio_shield_sw_a5_a0_tri_t_4,gpio_shield_sw_a5_a0_tri_t_3,gpio_shield_sw_a5_a0_tri_t_2,gpio_shield_sw_a5_a0_tri_t_1,gpio_shield_sw_a5_a0_tri_t_0}), // .gpio_shield_sw_d13_d2_tri_i({gpio_shield_sw_d13_d2_tri_i_11,gpio_shield_sw_d13_d2_tri_i_10,gpio_shield_sw_d13_d2_tri_i_9,gpio_shield_sw_d13_d2_tri_i_8,gpio_shield_sw_d13_d2_tri_i_7,gpio_shield_sw_d13_d2_tri_i_6,gpio_shield_sw_d13_d2_tri_i_5,gpio_shield_sw_d13_d2_tri_i_4,gpio_shield_sw_d13_d2_tri_i_3,gpio_shield_sw_d13_d2_tri_i_2,gpio_shield_sw_d13_d2_tri_i_1,gpio_shield_sw_d13_d2_tri_i_0}), // .gpio_shield_sw_d13_d2_tri_o({gpio_shield_sw_d13_d2_tri_o_11,gpio_shield_sw_d13_d2_tri_o_10,gpio_shield_sw_d13_d2_tri_o_9,gpio_shield_sw_d13_d2_tri_o_8,gpio_shield_sw_d13_d2_tri_o_7,gpio_shield_sw_d13_d2_tri_o_6,gpio_shield_sw_d13_d2_tri_o_5,gpio_shield_sw_d13_d2_tri_o_4,gpio_shield_sw_d13_d2_tri_o_3,gpio_shield_sw_d13_d2_tri_o_2,gpio_shield_sw_d13_d2_tri_o_1,gpio_shield_sw_d13_d2_tri_o_0}), // .gpio_shield_sw_d13_d2_tri_t({gpio_shield_sw_d13_d2_tri_t_11,gpio_shield_sw_d13_d2_tri_t_10,gpio_shield_sw_d13_d2_tri_t_9,gpio_shield_sw_d13_d2_tri_t_8,gpio_shield_sw_d13_d2_tri_t_7,gpio_shield_sw_d13_d2_tri_t_6,gpio_shield_sw_d13_d2_tri_t_5,gpio_shield_sw_d13_d2_tri_t_4,gpio_shield_sw_d13_d2_tri_t_3,gpio_shield_sw_d13_d2_tri_t_2,gpio_shield_sw_d13_d2_tri_t_1,gpio_shield_sw_d13_d2_tri_t_0}), // .gpio_shield_sw_d1_d0_tri_i({gpio_shield_sw_d1_d0_tri_i_1,gpio_shield_sw_d1_d0_tri_i_0}), // .gpio_shield_sw_d1_d0_tri_o({gpio_shield_sw_d1_d0_tri_o_1,gpio_shield_sw_d1_d0_tri_o_0}), // .gpio_shield_sw_d1_d0_tri_t({gpio_shield_sw_d1_d0_tri_t_1,gpio_shield_sw_d1_d0_tri_t_0}), .shield2sw_data_in_a5_a0(shield2sw_data_in_a5_a0), .shield2sw_data_in_d13_d2(shield2sw_data_in_d13_d2), .shield2sw_data_in_d1_d0(shield2sw_data_in_d1_d0), .sw2shield_data_out_a5_a0(sw2shield_data_out_a5_a0), .sw2shield_data_out_d13_d2(sw2shield_data_out_d13_d2), .sw2shield_data_out_d1_d0(sw2shield_data_out_d1_d0), .sw2shield_tri_out_a5_a0(sw2shield_tri_out_a5_a0), .sw2shield_tri_out_d13_d2(sw2shield_tri_out_d13_d2), .sw2shield_tri_out_d1_d0(sw2shield_tri_out_d1_d0), .hdmi_in_clk_n(hdmi_in_clk_n), .hdmi_in_clk_p(hdmi_in_clk_p), .hdmi_in_data_n(hdmi_in_data_n), .hdmi_in_data_p(hdmi_in_data_p), .hdmi_in_ddc_scl_i(hdmi_in_ddc_scl_i), .hdmi_in_ddc_scl_o(hdmi_in_ddc_scl_o), .hdmi_in_ddc_scl_t(hdmi_in_ddc_scl_t), .hdmi_in_ddc_sda_i(hdmi_in_ddc_sda_i), .hdmi_in_ddc_sda_o(hdmi_in_ddc_sda_o), .hdmi_in_ddc_sda_t(hdmi_in_ddc_sda_t), .hdmi_in_hpd(hdmi_in_hpd), .hdmi_out_clk_n(hdmi_out_clk_n), .hdmi_out_clk_p(hdmi_out_clk_p), .hdmi_out_data_n(hdmi_out_data_n), .hdmi_out_data_p(hdmi_out_data_p), .hdmi_out_ddc_scl_i(hdmi_out_ddc_scl_i), .hdmi_out_ddc_scl_o(hdmi_out_ddc_scl_o), .hdmi_out_ddc_scl_t(hdmi_out_ddc_scl_t), .hdmi_out_ddc_sda_i(hdmi_out_ddc_sda_i), .hdmi_out_ddc_sda_o(hdmi_out_ddc_sda_o), .hdmi_out_ddc_sda_t(hdmi_out_ddc_sda_t), .hdmi_out_hpd(hdmi_out_hpd), // .iic_sw_shield_scl_i(iic_sw_shield_scl_i), // .iic_sw_shield_scl_o(iic_sw_shield_scl_o), // .iic_sw_shield_scl_t(iic_sw_shield_scl_t), // .iic_sw_shield_sda_i(iic_sw_shield_sda_i), // .iic_sw_shield_sda_o(iic_sw_shield_sda_o), // .iic_sw_shield_sda_t(iic_sw_shield_sda_t), .shield2sw_scl_i_in(shield2sw_scl_i_in), .shield2sw_sda_i_in(shield2sw_sda_i_in), .sw2shield_scl_o_out(sw2shield_scl_o_out), .sw2shield_scl_t_out(sw2shield_scl_t_out), .sw2shield_sda_o_out(sw2shield_sda_o_out), .sw2shield_sda_t_out(sw2shield_sda_t_out), .leds_4bits_tri_o(leds_4bits_tri_o), .pmodJB_data_in(pmodJB_data_in), .pmodJB_data_out(pmodJB_data_out), .pmodJB_tri_out(pmodJB_tri_out), .pmodJA_data_in(pmodJA_data_in), .pmodJA_data_out(pmodJA_data_out), .pmodJA_tri_out(pmodJA_tri_out), .pdm_audio_shutdown(pdm_audio_shutdown), .pdm_m_clk(pdm_m_clk), .pdm_m_data_i(pdm_m_data_i), .rgbleds_6bits_tri_o(rgbleds_6bits_tri_o), .pwm_audio_o(pwm_audio_o), .spi_sw_shield_io0_i(spi_sw_shield_io0_i), .spi_sw_shield_io0_o(spi_sw_shield_io0_o), .spi_sw_shield_io0_t(spi_sw_shield_io0_t), .spi_sw_shield_io1_i(spi_sw_shield_io1_i), .spi_sw_shield_io1_o(spi_sw_shield_io1_o), .spi_sw_shield_io1_t(spi_sw_shield_io1_t), .spi_sw_shield_sck_i(spi_sw_shield_sck_i), .spi_sw_shield_sck_o(spi_sw_shield_sck_o), .spi_sw_shield_sck_t(spi_sw_shield_sck_t), .spi_sw_shield_ss_i(spi_sw_shield_ss_i), .spi_sw_shield_ss_o(spi_sw_shield_ss_o), .spi_sw_shield_ss_t(spi_sw_shield_ss_t), .sws_2bits_tri_i(sws_2bits_tri_i)); endmodule
// $Header: $ /////////////////////////////////////////////////////// // Copyright (c) 2011 Xilinx Inc. // All Right Reserved. /////////////////////////////////////////////////////// // // ____ ___ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 13.1 // \ \ Description : // / / // /__/ /\ Filename : GTPE2_CHANNEL.uniprim.v // \ \ / \ // \__\/\__ \ // // 11/8/12 - 686589 - YML default changes // 01/18/13 - 695630 - added drp monitor // 08/29/14 - 821138 - add negedge specify section for IS_INVERTED*CLK* /////////////////////////////////////////////////////// `timescale 1 ps / 1 ps `celldefine module GTPE2_CHANNEL ( DMONITOROUT, DRPDO, DRPRDY, EYESCANDATAERROR, GTPTXN, GTPTXP, PCSRSVDOUT, PHYSTATUS, PMARSVDOUT0, PMARSVDOUT1, RXBUFSTATUS, RXBYTEISALIGNED, RXBYTEREALIGN, RXCDRLOCK, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCHARISCOMMA, RXCHARISK, RXCHBONDO, RXCLKCORCNT, RXCOMINITDET, RXCOMMADET, RXCOMSASDET, RXCOMWAKEDET, RXDATA, RXDATAVALID, RXDISPERR, RXDLYSRESETDONE, RXELECIDLE, RXHEADER, RXHEADERVALID, RXNOTINTABLE, RXOSINTDONE, RXOSINTSTARTED, RXOSINTSTROBEDONE, RXOSINTSTROBESTARTED, RXOUTCLK, RXOUTCLKFABRIC, RXOUTCLKPCS, RXPHALIGNDONE, RXPHMONITOR, RXPHSLIPMONITOR, RXPMARESETDONE, RXPRBSERR, RXRATEDONE, RXRESETDONE, RXSTARTOFSEQ, RXSTATUS, RXSYNCDONE, RXSYNCOUT, RXVALID, TXBUFSTATUS, TXCOMFINISH, TXDLYSRESETDONE, TXGEARBOXREADY, TXOUTCLK, TXOUTCLKFABRIC, TXOUTCLKPCS, TXPHALIGNDONE, TXPHINITDONE, TXPMARESETDONE, TXRATEDONE, TXRESETDONE, TXSYNCDONE, TXSYNCOUT, CFGRESET, CLKRSVD0, CLKRSVD1, DMONFIFORESET, DMONITORCLK, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, EYESCANMODE, EYESCANRESET, EYESCANTRIGGER, GTPRXN, GTPRXP, GTRESETSEL, GTRSVD, GTRXRESET, GTTXRESET, LOOPBACK, PCSRSVDIN, PLL0CLK, PLL0REFCLK, PLL1CLK, PLL1REFCLK, PMARSVDIN0, PMARSVDIN1, PMARSVDIN2, PMARSVDIN3, PMARSVDIN4, RESETOVRD, RX8B10BEN, RXADAPTSELTEST, RXBUFRESET, RXCDRFREQRESET, RXCDRHOLD, RXCDROVRDEN, RXCDRRESET, RXCDRRESETRSV, RXCHBONDEN, RXCHBONDI, RXCHBONDLEVEL, RXCHBONDMASTER, RXCHBONDSLAVE, RXCOMMADETEN, RXDDIEN, RXDFEXYDEN, RXDLYBYPASS, RXDLYEN, RXDLYOVRDEN, RXDLYSRESET, RXELECIDLEMODE, RXGEARBOXSLIP, RXLPMHFHOLD, RXLPMHFOVRDEN, RXLPMLFHOLD, RXLPMLFOVRDEN, RXLPMOSINTNTRLEN, RXLPMRESET, RXMCOMMAALIGNEN, RXOOBRESET, RXOSCALRESET, RXOSHOLD, RXOSINTCFG, RXOSINTEN, RXOSINTHOLD, RXOSINTID0, RXOSINTNTRLEN, RXOSINTOVRDEN, RXOSINTPD, RXOSINTSTROBE, RXOSINTTESTOVRDEN, RXOSOVRDEN, RXOUTCLKSEL, RXPCOMMAALIGNEN, RXPCSRESET, RXPD, RXPHALIGN, RXPHALIGNEN, RXPHDLYPD, RXPHDLYRESET, RXPHOVRDEN, RXPMARESET, RXPOLARITY, RXPRBSCNTRESET, RXPRBSSEL, RXRATE, RXRATEMODE, RXSLIDE, RXSYNCALLIN, RXSYNCIN, RXSYNCMODE, RXSYSCLKSEL, RXUSERRDY, RXUSRCLK, RXUSRCLK2, SETERRSTATUS, SIGVALIDCLK, TSTIN, TX8B10BBYPASS, TX8B10BEN, TXBUFDIFFCTRL, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXCOMINIT, TXCOMSAS, TXCOMWAKE, TXDATA, TXDEEMPH, TXDETECTRX, TXDIFFCTRL, TXDIFFPD, TXDLYBYPASS, TXDLYEN, TXDLYHOLD, TXDLYOVRDEN, TXDLYSRESET, TXDLYUPDOWN, TXELECIDLE, TXHEADER, TXINHIBIT, TXMAINCURSOR, TXMARGIN, TXOUTCLKSEL, TXPCSRESET, TXPD, TXPDELECIDLEMODE, TXPHALIGN, TXPHALIGNEN, TXPHDLYPD, TXPHDLYRESET, TXPHDLYTSTCLK, TXPHINIT, TXPHOVRDEN, TXPIPPMEN, TXPIPPMOVRDEN, TXPIPPMPD, TXPIPPMSEL, TXPIPPMSTEPSIZE, TXPISOPD, TXPMARESET, TXPOLARITY, TXPOSTCURSOR, TXPOSTCURSORINV, TXPRBSFORCEERR, TXPRBSSEL, TXPRECURSOR, TXPRECURSORINV, TXRATE, TXRATEMODE, TXSEQUENCE, TXSTARTSEQ, TXSWING, TXSYNCALLIN, TXSYNCIN, TXSYNCMODE, TXSYSCLKSEL, TXUSERRDY, TXUSRCLK, TXUSRCLK2 ); `ifdef XIL_TIMING //Simprim parameter LOC = "UNPLACED"; `endif parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; parameter [0:0] ACJTAG_MODE = 1'b0; parameter [0:0] ACJTAG_RESET = 1'b0; parameter [19:0] ADAPT_CFG0 = 20'b00000000000000000000; parameter ALIGN_COMMA_DOUBLE = "FALSE"; parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; parameter integer ALIGN_COMMA_WORD = 1; parameter ALIGN_MCOMMA_DET = "TRUE"; parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; parameter ALIGN_PCOMMA_DET = "TRUE"; parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; parameter CBCC_DATA_SOURCE_SEL = "DECODED"; parameter [42:0] CFOK_CFG = 43'b1001001000000000000000001000000111010000000; parameter [6:0] CFOK_CFG2 = 7'b0100000; parameter [6:0] CFOK_CFG3 = 7'b0100000; parameter [0:0] CFOK_CFG4 = 1'b0; parameter [1:0] CFOK_CFG5 = 2'b00; parameter [3:0] CFOK_CFG6 = 4'b0000; parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; parameter integer CHAN_BOND_MAX_SKEW = 7; parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; parameter CHAN_BOND_SEQ_2_USE = "FALSE"; parameter integer CHAN_BOND_SEQ_LEN = 1; parameter [0:0] CLK_COMMON_SWING = 1'b0; parameter CLK_CORRECT_USE = "TRUE"; parameter CLK_COR_KEEP_IDLE = "FALSE"; parameter integer CLK_COR_MAX_LAT = 20; parameter integer CLK_COR_MIN_LAT = 18; parameter CLK_COR_PRECEDENCE = "TRUE"; parameter integer CLK_COR_REPEAT_WAIT = 0; parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; parameter CLK_COR_SEQ_2_USE = "FALSE"; parameter integer CLK_COR_SEQ_LEN = 1; parameter DEC_MCOMMA_DETECT = "TRUE"; parameter DEC_PCOMMA_DETECT = "TRUE"; parameter DEC_VALID_COMMA_ONLY = "TRUE"; parameter [23:0] DMONITOR_CFG = 24'h000A00; parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; parameter [5:0] ES_CONTROL = 6'b000000; parameter ES_ERRDET_EN = "FALSE"; parameter ES_EYE_SCAN_EN = "FALSE"; parameter [11:0] ES_HORZ_OFFSET = 12'h010; parameter [9:0] ES_PMA_CFG = 10'b0000000000; parameter [4:0] ES_PRESCALE = 5'b00000; parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000; parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000; parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000; parameter [8:0] ES_VERT_OFFSET = 9'b000000000; parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; parameter FTS_LANE_DESKEW_EN = "FALSE"; parameter [2:0] GEARBOX_MODE = 3'b000; parameter [0:0] IS_CLKRSVD0_INVERTED = 1'b0; parameter [0:0] IS_CLKRSVD1_INVERTED = 1'b0; parameter [0:0] IS_DMONITORCLK_INVERTED = 1'b0; parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0; parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0; parameter [0:0] IS_SIGVALIDCLK_INVERTED = 1'b0; parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0; parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0; parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0; parameter [0:0] LOOPBACK_CFG = 1'b0; parameter [1:0] OUTREFCLK_SEL_INV = 2'b11; parameter PCS_PCIE_EN = "FALSE"; parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000; parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; parameter [0:0] PMA_LOOPBACK_CFG = 1'b0; parameter [31:0] PMA_RSV = 32'h00000333; parameter [31:0] PMA_RSV2 = 32'h00002050; parameter [1:0] PMA_RSV3 = 2'b00; parameter [3:0] PMA_RSV4 = 4'b0000; parameter [0:0] PMA_RSV5 = 1'b0; parameter [0:0] PMA_RSV6 = 1'b0; parameter [0:0] PMA_RSV7 = 1'b0; parameter [4:0] RXBUFRESET_TIME = 5'b00001; parameter RXBUF_ADDR_MODE = "FULL"; parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; parameter RXBUF_EN = "TRUE"; parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; parameter RXBUF_RESET_ON_EIDLE = "FALSE"; parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; parameter integer RXBUF_THRESH_OVFLW = 61; parameter RXBUF_THRESH_OVRD = "FALSE"; parameter integer RXBUF_THRESH_UNDFLW = 4; parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; parameter [82:0] RXCDR_CFG = 83'h0000107FE406001041010; parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; parameter [5:0] RXCDR_LOCK_CFG = 6'b001001; parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; parameter [15:0] RXDLY_CFG = 16'h0010; parameter [8:0] RXDLY_LCFG = 9'h020; parameter [15:0] RXDLY_TAP_CFG = 16'h0000; parameter RXGEARBOX_EN = "FALSE"; parameter [4:0] RXISCANRESET_TIME = 5'b00001; parameter [6:0] RXLPMRESET_TIME = 7'b0001111; parameter [0:0] RXLPM_BIAS_STARTUP_DISABLE = 1'b0; parameter [3:0] RXLPM_CFG = 4'b0110; parameter [0:0] RXLPM_CFG1 = 1'b0; parameter [0:0] RXLPM_CM_CFG = 1'b0; parameter [8:0] RXLPM_GC_CFG = 9'b111100010; parameter [2:0] RXLPM_GC_CFG2 = 3'b001; parameter [13:0] RXLPM_HF_CFG = 14'b00001111110000; parameter [4:0] RXLPM_HF_CFG2 = 5'b01010; parameter [3:0] RXLPM_HF_CFG3 = 4'b0000; parameter [0:0] RXLPM_HOLD_DURING_EIDLE = 1'b0; parameter [0:0] RXLPM_INCM_CFG = 1'b0; parameter [0:0] RXLPM_IPCM_CFG = 1'b0; parameter [17:0] RXLPM_LF_CFG = 18'b000000001111110000; parameter [4:0] RXLPM_LF_CFG2 = 5'b01010; parameter [2:0] RXLPM_OSINT_CFG = 3'b100; parameter [6:0] RXOOB_CFG = 7'b0000110; parameter RXOOB_CLK_CFG = "PMA"; parameter [4:0] RXOSCALRESET_TIME = 5'b00011; parameter [4:0] RXOSCALRESET_TIMEOUT = 5'b00000; parameter integer RXOUT_DIV = 2; parameter [4:0] RXPCSRESET_TIME = 5'b00001; parameter [23:0] RXPHDLY_CFG = 24'h084000; parameter [23:0] RXPH_CFG = 24'hC00002; parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; parameter [2:0] RXPI_CFG0 = 3'b000; parameter [0:0] RXPI_CFG1 = 1'b0; parameter [0:0] RXPI_CFG2 = 1'b0; parameter [4:0] RXPMARESET_TIME = 5'b00011; parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; parameter integer RXSLIDE_AUTO_WAIT = 7; parameter RXSLIDE_MODE = "OFF"; parameter [0:0] RXSYNC_MULTILANE = 1'b0; parameter [0:0] RXSYNC_OVRD = 1'b0; parameter [0:0] RXSYNC_SKIP_DA = 1'b0; parameter [15:0] RX_BIAS_CFG = 16'b0000111100110011; parameter [5:0] RX_BUFFER_CFG = 6'b000000; parameter integer RX_CLK25_DIV = 7; parameter [0:0] RX_CLKMUX_EN = 1'b1; parameter [1:0] RX_CM_SEL = 2'b11; parameter [3:0] RX_CM_TRIM = 4'b0100; parameter integer RX_DATA_WIDTH = 20; parameter [5:0] RX_DDI_SEL = 6'b000000; parameter [13:0] RX_DEBUG_CFG = 14'b00000000000000; parameter RX_DEFER_RESET_BUF_EN = "TRUE"; parameter RX_DISPERR_SEQ_MATCH = "TRUE"; parameter [12:0] RX_OS_CFG = 13'b0001111110000; parameter integer RX_SIG_VALID_DLY = 10; parameter RX_XCLK_SEL = "RXREC"; parameter integer SAS_MAX_COM = 64; parameter integer SAS_MIN_COM = 36; parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; parameter [2:0] SATA_BURST_VAL = 3'b100; parameter [2:0] SATA_EIDLE_VAL = 3'b100; parameter integer SATA_MAX_BURST = 8; parameter integer SATA_MAX_INIT = 21; parameter integer SATA_MAX_WAKE = 7; parameter integer SATA_MIN_BURST = 4; parameter integer SATA_MIN_INIT = 12; parameter integer SATA_MIN_WAKE = 4; parameter SATA_PLL_CFG = "VCO_3000MHZ"; parameter SHOW_REALIGN_COMMA = "TRUE"; parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; parameter SIM_RESET_SPEEDUP = "TRUE"; parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X"; parameter SIM_VERSION = "1.0"; parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; parameter [2:0] TERM_RCAL_OVRD = 3'b000; parameter [7:0] TRANS_TIME_RATE = 8'h0E; parameter [31:0] TST_RSV = 32'h00000000; parameter TXBUF_EN = "TRUE"; parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; parameter [15:0] TXDLY_CFG = 16'h0010; parameter [8:0] TXDLY_LCFG = 9'h020; parameter [15:0] TXDLY_TAP_CFG = 16'h0000; parameter TXGEARBOX_EN = "FALSE"; parameter [0:0] TXOOB_CFG = 1'b0; parameter integer TXOUT_DIV = 2; parameter [4:0] TXPCSRESET_TIME = 5'b00001; parameter [23:0] TXPHDLY_CFG = 24'h084000; parameter [15:0] TXPH_CFG = 16'h0400; parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; parameter [1:0] TXPI_CFG0 = 2'b00; parameter [1:0] TXPI_CFG1 = 2'b00; parameter [1:0] TXPI_CFG2 = 2'b00; parameter [0:0] TXPI_CFG3 = 1'b0; parameter [0:0] TXPI_CFG4 = 1'b0; parameter [2:0] TXPI_CFG5 = 3'b000; parameter [0:0] TXPI_GREY_SEL = 1'b0; parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; parameter [7:0] TXPI_PPM_CFG = 8'b00000000; parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; parameter [4:0] TXPMARESET_TIME = 5'b00001; parameter [0:0] TXSYNC_MULTILANE = 1'b0; parameter [0:0] TXSYNC_OVRD = 1'b0; parameter [0:0] TXSYNC_SKIP_DA = 1'b0; parameter integer TX_CLK25_DIV = 7; parameter [0:0] TX_CLKMUX_EN = 1'b1; parameter integer TX_DATA_WIDTH = 20; parameter [5:0] TX_DEEMPH0 = 6'b000000; parameter [5:0] TX_DEEMPH1 = 6'b000000; parameter TX_DRIVE_MODE = "DIRECT"; parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; parameter [0:0] TX_PREDRIVER_MODE = 1'b0; parameter [13:0] TX_RXDETECT_CFG = 14'h1832; parameter [2:0] TX_RXDETECT_REF = 3'b100; parameter TX_XCLK_SEL = "TXUSR"; parameter [0:0] UCODEER_CLR = 1'b0; parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; localparam in_delay = 0; localparam out_delay = 0; localparam INCLK_DELAY = 0; localparam OUTCLK_DELAY = 0; output DRPRDY; output EYESCANDATAERROR; output GTPTXN; output GTPTXP; output PHYSTATUS; output PMARSVDOUT0; output PMARSVDOUT1; output RXBYTEISALIGNED; output RXBYTEREALIGN; output RXCDRLOCK; output RXCHANBONDSEQ; output RXCHANISALIGNED; output RXCHANREALIGN; output RXCOMINITDET; output RXCOMMADET; output RXCOMSASDET; output RXCOMWAKEDET; output RXDLYSRESETDONE; output RXELECIDLE; output RXHEADERVALID; output RXOSINTDONE; output RXOSINTSTARTED; output RXOSINTSTROBEDONE; output RXOSINTSTROBESTARTED; output RXOUTCLK; output RXOUTCLKFABRIC; output RXOUTCLKPCS; output RXPHALIGNDONE; output RXPMARESETDONE; output RXPRBSERR; output RXRATEDONE; output RXRESETDONE; output RXSYNCDONE; output RXSYNCOUT; output RXVALID; output TXCOMFINISH; output TXDLYSRESETDONE; output TXGEARBOXREADY; output TXOUTCLK; output TXOUTCLKFABRIC; output TXOUTCLKPCS; output TXPHALIGNDONE; output TXPHINITDONE; output TXPMARESETDONE; output TXRATEDONE; output TXRESETDONE; output TXSYNCDONE; output TXSYNCOUT; output [14:0] DMONITOROUT; output [15:0] DRPDO; output [15:0] PCSRSVDOUT; output [1:0] RXCLKCORCNT; output [1:0] RXDATAVALID; output [1:0] RXSTARTOFSEQ; output [1:0] TXBUFSTATUS; output [2:0] RXBUFSTATUS; output [2:0] RXHEADER; output [2:0] RXSTATUS; output [31:0] RXDATA; output [3:0] RXCHARISCOMMA; output [3:0] RXCHARISK; output [3:0] RXCHBONDO; output [3:0] RXDISPERR; output [3:0] RXNOTINTABLE; output [4:0] RXPHMONITOR; output [4:0] RXPHSLIPMONITOR; input CFGRESET; input CLKRSVD0; input CLKRSVD1; input DMONFIFORESET; input DMONITORCLK; input DRPCLK; input DRPEN; input DRPWE; input EYESCANMODE; input EYESCANRESET; input EYESCANTRIGGER; input GTPRXN; input GTPRXP; input GTRESETSEL; input GTRXRESET; input GTTXRESET; input PLL0CLK; input PLL0REFCLK; input PLL1CLK; input PLL1REFCLK; input PMARSVDIN0; input PMARSVDIN1; input PMARSVDIN2; input PMARSVDIN3; input PMARSVDIN4; input RESETOVRD; input RX8B10BEN; input RXBUFRESET; input RXCDRFREQRESET; input RXCDRHOLD; input RXCDROVRDEN; input RXCDRRESET; input RXCDRRESETRSV; input RXCHBONDEN; input RXCHBONDMASTER; input RXCHBONDSLAVE; input RXCOMMADETEN; input RXDDIEN; input RXDFEXYDEN; input RXDLYBYPASS; input RXDLYEN; input RXDLYOVRDEN; input RXDLYSRESET; input RXGEARBOXSLIP; input RXLPMHFHOLD; input RXLPMHFOVRDEN; input RXLPMLFHOLD; input RXLPMLFOVRDEN; input RXLPMOSINTNTRLEN; input RXLPMRESET; input RXMCOMMAALIGNEN; input RXOOBRESET; input RXOSCALRESET; input RXOSHOLD; input RXOSINTEN; input RXOSINTHOLD; input RXOSINTNTRLEN; input RXOSINTOVRDEN; input RXOSINTPD; input RXOSINTSTROBE; input RXOSINTTESTOVRDEN; input RXOSOVRDEN; input RXPCOMMAALIGNEN; input RXPCSRESET; input RXPHALIGN; input RXPHALIGNEN; input RXPHDLYPD; input RXPHDLYRESET; input RXPHOVRDEN; input RXPMARESET; input RXPOLARITY; input RXPRBSCNTRESET; input RXRATEMODE; input RXSLIDE; input RXSYNCALLIN; input RXSYNCIN; input RXSYNCMODE; input RXUSERRDY; input RXUSRCLK2; input RXUSRCLK; input SETERRSTATUS; input SIGVALIDCLK; input TX8B10BEN; input TXCOMINIT; input TXCOMSAS; input TXCOMWAKE; input TXDEEMPH; input TXDETECTRX; input TXDIFFPD; input TXDLYBYPASS; input TXDLYEN; input TXDLYHOLD; input TXDLYOVRDEN; input TXDLYSRESET; input TXDLYUPDOWN; input TXELECIDLE; input TXINHIBIT; input TXPCSRESET; input TXPDELECIDLEMODE; input TXPHALIGN; input TXPHALIGNEN; input TXPHDLYPD; input TXPHDLYRESET; input TXPHDLYTSTCLK; input TXPHINIT; input TXPHOVRDEN; input TXPIPPMEN; input TXPIPPMOVRDEN; input TXPIPPMPD; input TXPIPPMSEL; input TXPISOPD; input TXPMARESET; input TXPOLARITY; input TXPOSTCURSORINV; input TXPRBSFORCEERR; input TXPRECURSORINV; input TXRATEMODE; input TXSTARTSEQ; input TXSWING; input TXSYNCALLIN; input TXSYNCIN; input TXSYNCMODE; input TXUSERRDY; input TXUSRCLK2; input TXUSRCLK; input [13:0] RXADAPTSELTEST; input [15:0] DRPDI; input [15:0] GTRSVD; input [15:0] PCSRSVDIN; input [19:0] TSTIN; input [1:0] RXELECIDLEMODE; input [1:0] RXPD; input [1:0] RXSYSCLKSEL; input [1:0] TXPD; input [1:0] TXSYSCLKSEL; input [2:0] LOOPBACK; input [2:0] RXCHBONDLEVEL; input [2:0] RXOUTCLKSEL; input [2:0] RXPRBSSEL; input [2:0] RXRATE; input [2:0] TXBUFDIFFCTRL; input [2:0] TXHEADER; input [2:0] TXMARGIN; input [2:0] TXOUTCLKSEL; input [2:0] TXPRBSSEL; input [2:0] TXRATE; input [31:0] TXDATA; input [3:0] RXCHBONDI; input [3:0] RXOSINTCFG; input [3:0] RXOSINTID0; input [3:0] TX8B10BBYPASS; input [3:0] TXCHARDISPMODE; input [3:0] TXCHARDISPVAL; input [3:0] TXCHARISK; input [3:0] TXDIFFCTRL; input [4:0] TXPIPPMSTEPSIZE; input [4:0] TXPOSTCURSOR; input [4:0] TXPRECURSOR; input [6:0] TXMAINCURSOR; input [6:0] TXSEQUENCE; input [8:0] DRPADDR; reg SIM_RECEIVER_DETECT_PASS_BINARY; reg SIM_RESET_SPEEDUP_BINARY; reg SIM_TX_EIDLE_DRIVE_LEVEL_BINARY; reg SIM_VERSION_BINARY; reg [0:0] ACJTAG_DEBUG_MODE_BINARY; reg [0:0] ACJTAG_MODE_BINARY; reg [0:0] ACJTAG_RESET_BINARY; reg [0:0] ALIGN_COMMA_DOUBLE_BINARY; reg [0:0] ALIGN_MCOMMA_DET_BINARY; reg [0:0] ALIGN_PCOMMA_DET_BINARY; reg [0:0] CBCC_DATA_SOURCE_SEL_BINARY; reg [0:0] CFOK_CFG4_BINARY; reg [0:0] CHAN_BOND_KEEP_ALIGN_BINARY; reg [0:0] CHAN_BOND_SEQ_2_USE_BINARY; reg [0:0] CLK_COMMON_SWING_BINARY; reg [0:0] CLK_CORRECT_USE_BINARY; reg [0:0] CLK_COR_KEEP_IDLE_BINARY; reg [0:0] CLK_COR_PRECEDENCE_BINARY; reg [0:0] CLK_COR_SEQ_2_USE_BINARY; reg [0:0] DEC_MCOMMA_DETECT_BINARY; reg [0:0] DEC_PCOMMA_DETECT_BINARY; reg [0:0] DEC_VALID_COMMA_ONLY_BINARY; reg [0:0] ES_CLK_PHASE_SEL_BINARY; reg [0:0] ES_ERRDET_EN_BINARY; reg [0:0] ES_EYE_SCAN_EN_BINARY; reg [0:0] FTS_LANE_DESKEW_EN_BINARY; reg [0:0] LOOPBACK_CFG_BINARY; reg [0:0] PCS_PCIE_EN_BINARY; reg [0:0] PMA_LOOPBACK_CFG_BINARY; reg [0:0] PMA_RSV5_BINARY; reg [0:0] PMA_RSV6_BINARY; reg [0:0] PMA_RSV7_BINARY; reg [0:0] RXBUF_ADDR_MODE_BINARY; reg [0:0] RXBUF_EN_BINARY; reg [0:0] RXBUF_RESET_ON_CB_CHANGE_BINARY; reg [0:0] RXBUF_RESET_ON_COMMAALIGN_BINARY; reg [0:0] RXBUF_RESET_ON_EIDLE_BINARY; reg [0:0] RXBUF_RESET_ON_RATE_CHANGE_BINARY; reg [0:0] RXBUF_THRESH_OVRD_BINARY; reg [0:0] RXCDR_FR_RESET_ON_EIDLE_BINARY; reg [0:0] RXCDR_HOLD_DURING_EIDLE_BINARY; reg [0:0] RXCDR_PH_RESET_ON_EIDLE_BINARY; reg [0:0] RXGEARBOX_EN_BINARY; reg [0:0] RXLPM_BIAS_STARTUP_DISABLE_BINARY; reg [0:0] RXLPM_CFG1_BINARY; reg [0:0] RXLPM_CM_CFG_BINARY; reg [0:0] RXLPM_HOLD_DURING_EIDLE_BINARY; reg [0:0] RXLPM_INCM_CFG_BINARY; reg [0:0] RXLPM_IPCM_CFG_BINARY; reg [0:0] RXOOB_CLK_CFG_BINARY; reg [0:0] RXPI_CFG1_BINARY; reg [0:0] RXPI_CFG2_BINARY; reg [0:0] RXPRBS_ERR_LOOPBACK_BINARY; reg [0:0] RXSYNC_MULTILANE_BINARY; reg [0:0] RXSYNC_OVRD_BINARY; reg [0:0] RXSYNC_SKIP_DA_BINARY; reg [0:0] RX_CLKMUX_EN_BINARY; reg [0:0] RX_DEFER_RESET_BUF_EN_BINARY; reg [0:0] RX_DISPERR_SEQ_MATCH_BINARY; reg [0:0] RX_XCLK_SEL_BINARY; reg [0:0] SHOW_REALIGN_COMMA_BINARY; reg [0:0] TXBUF_EN_BINARY; reg [0:0] TXBUF_RESET_ON_RATE_CHANGE_BINARY; reg [0:0] TXGEARBOX_EN_BINARY; reg [0:0] TXOOB_CFG_BINARY; reg [0:0] TXPI_CFG3_BINARY; reg [0:0] TXPI_CFG4_BINARY; reg [0:0] TXPI_GREY_SEL_BINARY; reg [0:0] TXPI_INVSTROBE_SEL_BINARY; reg [0:0] TXPI_PPMCLK_SEL_BINARY; reg [0:0] TXSYNC_MULTILANE_BINARY; reg [0:0] TXSYNC_OVRD_BINARY; reg [0:0] TXSYNC_SKIP_DA_BINARY; reg [0:0] TX_CLKMUX_EN_BINARY; reg [0:0] TX_LOOPBACK_DRIVE_HIZ_BINARY; reg [0:0] TX_MAINCURSOR_SEL_BINARY; reg [0:0] TX_PREDRIVER_MODE_BINARY; reg [0:0] TX_XCLK_SEL_BINARY; reg [0:0] UCODEER_CLR_BINARY; reg [0:0] USE_PCS_CLK_PHASE_SEL_BINARY; reg [12:0] RX_OS_CFG_BINARY; reg [13:0] RXLPM_HF_CFG_BINARY; reg [13:0] RX_DEBUG_CFG_BINARY; reg [14:0] TERM_RCAL_CFG_BINARY; reg [15:0] RX_BIAS_CFG_BINARY; reg [17:0] RXLPM_LF_CFG_BINARY; reg [19:0] ADAPT_CFG0_BINARY; reg [1:0] ALIGN_COMMA_WORD_BINARY; reg [1:0] CFOK_CFG5_BINARY; reg [1:0] CHAN_BOND_SEQ_LEN_BINARY; reg [1:0] CLK_COR_SEQ_LEN_BINARY; reg [1:0] OUTREFCLK_SEL_INV_BINARY; reg [1:0] PMA_RSV3_BINARY; reg [1:0] RXSLIDE_MODE_BINARY; reg [1:0] RX_CM_SEL_BINARY; reg [1:0] SATA_PLL_CFG_BINARY; reg [1:0] TXPI_CFG0_BINARY; reg [1:0] TXPI_CFG1_BINARY; reg [1:0] TXPI_CFG2_BINARY; reg [2:0] GEARBOX_MODE_BINARY; reg [2:0] RXLPM_GC_CFG2_BINARY; reg [2:0] RXLPM_OSINT_CFG_BINARY; reg [2:0] RXOUT_DIV_BINARY; reg [2:0] RXPI_CFG0_BINARY; reg [2:0] RX_DATA_WIDTH_BINARY; reg [2:0] SATA_BURST_VAL_BINARY; reg [2:0] SATA_EIDLE_VAL_BINARY; reg [2:0] TERM_RCAL_OVRD_BINARY; reg [2:0] TXOUT_DIV_BINARY; reg [2:0] TXPI_CFG5_BINARY; reg [2:0] TXPI_SYNFREQ_PPM_BINARY; reg [2:0] TX_DATA_WIDTH_BINARY; reg [2:0] TX_EIDLE_ASSERT_DELAY_BINARY; reg [2:0] TX_EIDLE_DEASSERT_DELAY_BINARY; reg [2:0] TX_RXDETECT_REF_BINARY; reg [3:0] CFOK_CFG6_BINARY; reg [3:0] CHAN_BOND_MAX_SKEW_BINARY; reg [3:0] CHAN_BOND_SEQ_1_ENABLE_BINARY; reg [3:0] CHAN_BOND_SEQ_2_ENABLE_BINARY; reg [3:0] CLK_COR_SEQ_1_ENABLE_BINARY; reg [3:0] CLK_COR_SEQ_2_ENABLE_BINARY; reg [3:0] FTS_DESKEW_SEQ_ENABLE_BINARY; reg [3:0] FTS_LANE_DESKEW_CFG_BINARY; reg [3:0] PMA_RSV4_BINARY; reg [3:0] RXBUF_EIDLE_HI_CNT_BINARY; reg [3:0] RXBUF_EIDLE_LO_CNT_BINARY; reg [3:0] RXLPM_CFG_BINARY; reg [3:0] RXLPM_HF_CFG3_BINARY; reg [3:0] RXSLIDE_AUTO_WAIT_BINARY; reg [3:0] RX_CM_TRIM_BINARY; reg [3:0] SATA_BURST_SEQ_LEN_BINARY; reg [42:0] CFOK_CFG_BINARY; reg [4:0] CLK_COR_REPEAT_WAIT_BINARY; reg [4:0] ES_PRESCALE_BINARY; reg [4:0] RXBUFRESET_TIME_BINARY; reg [4:0] RXCDRFREQRESET_TIME_BINARY; reg [4:0] RXCDRPHRESET_TIME_BINARY; reg [4:0] RXISCANRESET_TIME_BINARY; reg [4:0] RXLPM_HF_CFG2_BINARY; reg [4:0] RXLPM_LF_CFG2_BINARY; reg [4:0] RXOSCALRESET_TIMEOUT_BINARY; reg [4:0] RXOSCALRESET_TIME_BINARY; reg [4:0] RXPCSRESET_TIME_BINARY; reg [4:0] RXPH_MONITOR_SEL_BINARY; reg [4:0] RXPMARESET_TIME_BINARY; reg [4:0] RX_CLK25_DIV_BINARY; reg [4:0] RX_SIG_VALID_DLY_BINARY; reg [4:0] TXPCSRESET_TIME_BINARY; reg [4:0] TXPH_MONITOR_SEL_BINARY; reg [4:0] TXPMARESET_TIME_BINARY; reg [4:0] TX_CLK25_DIV_BINARY; reg [4:0] TX_DRIVE_MODE_BINARY; reg [5:0] CLK_COR_MAX_LAT_BINARY; reg [5:0] CLK_COR_MIN_LAT_BINARY; reg [5:0] ES_CONTROL_BINARY; reg [5:0] RXBUF_THRESH_OVFLW_BINARY; reg [5:0] RXBUF_THRESH_UNDFLW_BINARY; reg [5:0] RXCDR_LOCK_CFG_BINARY; reg [5:0] RX_BUFFER_CFG_BINARY; reg [5:0] RX_DDI_SEL_BINARY; reg [5:0] SAS_MIN_COM_BINARY; reg [5:0] SATA_MAX_BURST_BINARY; reg [5:0] SATA_MAX_INIT_BINARY; reg [5:0] SATA_MAX_WAKE_BINARY; reg [5:0] SATA_MIN_BURST_BINARY; reg [5:0] SATA_MIN_INIT_BINARY; reg [5:0] SATA_MIN_WAKE_BINARY; reg [5:0] TX_DEEMPH0_BINARY; reg [5:0] TX_DEEMPH1_BINARY; reg [6:0] CFOK_CFG2_BINARY; reg [6:0] CFOK_CFG3_BINARY; reg [6:0] RXLPMRESET_TIME_BINARY; reg [6:0] RXOOB_CFG_BINARY; reg [6:0] SAS_MAX_COM_BINARY; reg [6:0] TX_MARGIN_FULL_0_BINARY; reg [6:0] TX_MARGIN_FULL_1_BINARY; reg [6:0] TX_MARGIN_FULL_2_BINARY; reg [6:0] TX_MARGIN_FULL_3_BINARY; reg [6:0] TX_MARGIN_FULL_4_BINARY; reg [6:0] TX_MARGIN_LOW_0_BINARY; reg [6:0] TX_MARGIN_LOW_1_BINARY; reg [6:0] TX_MARGIN_LOW_2_BINARY; reg [6:0] TX_MARGIN_LOW_3_BINARY; reg [6:0] TX_MARGIN_LOW_4_BINARY; reg [7:0] TXPI_PPM_CFG_BINARY; reg [8:0] ES_VERT_OFFSET_BINARY; reg [8:0] RXLPM_GC_CFG_BINARY; reg [9:0] ALIGN_COMMA_ENABLE_BINARY; reg [9:0] ALIGN_MCOMMA_VALUE_BINARY; reg [9:0] ALIGN_PCOMMA_VALUE_BINARY; reg [9:0] CHAN_BOND_SEQ_1_1_BINARY; reg [9:0] CHAN_BOND_SEQ_1_2_BINARY; reg [9:0] CHAN_BOND_SEQ_1_3_BINARY; reg [9:0] CHAN_BOND_SEQ_1_4_BINARY; reg [9:0] CHAN_BOND_SEQ_2_1_BINARY; reg [9:0] CHAN_BOND_SEQ_2_2_BINARY; reg [9:0] CHAN_BOND_SEQ_2_3_BINARY; reg [9:0] CHAN_BOND_SEQ_2_4_BINARY; reg [9:0] CLK_COR_SEQ_1_1_BINARY; reg [9:0] CLK_COR_SEQ_1_2_BINARY; reg [9:0] CLK_COR_SEQ_1_3_BINARY; reg [9:0] CLK_COR_SEQ_1_4_BINARY; reg [9:0] CLK_COR_SEQ_2_1_BINARY; reg [9:0] CLK_COR_SEQ_2_2_BINARY; reg [9:0] CLK_COR_SEQ_2_3_BINARY; reg [9:0] CLK_COR_SEQ_2_4_BINARY; reg [9:0] ES_PMA_CFG_BINARY; tri0 GSR = glbl.GSR; reg notifier; initial begin case (ALIGN_COMMA_DOUBLE) "FALSE" : ALIGN_COMMA_DOUBLE_BINARY = 1'b0; "TRUE" : ALIGN_COMMA_DOUBLE_BINARY = 1'b1; default : begin $display("Attribute Syntax Error : The Attribute ALIGN_COMMA_DOUBLE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ALIGN_COMMA_DOUBLE); $finish; end endcase case (ALIGN_MCOMMA_DET) "TRUE" : ALIGN_MCOMMA_DET_BINARY = 1'b1; "FALSE" : ALIGN_MCOMMA_DET_BINARY = 1'b0; default : begin $display("Attribute Syntax Error : The Attribute ALIGN_MCOMMA_DET on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ALIGN_MCOMMA_DET); $finish; end endcase case (ALIGN_PCOMMA_DET) "TRUE" : ALIGN_PCOMMA_DET_BINARY = 1'b1; "FALSE" : ALIGN_PCOMMA_DET_BINARY = 1'b0; default : begin $display("Attribute Syntax Error : The Attribute ALIGN_PCOMMA_DET on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ALIGN_PCOMMA_DET); $finish; end endcase case (CBCC_DATA_SOURCE_SEL) "DECODED" : CBCC_DATA_SOURCE_SEL_BINARY = 1'b1; "ENCODED" : CBCC_DATA_SOURCE_SEL_BINARY = 1'b0; default : begin $display("Attribute Syntax Error : The Attribute CBCC_DATA_SOURCE_SEL on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are DECODED, or ENCODED.", CBCC_DATA_SOURCE_SEL); $finish; end endcase case (CHAN_BOND_KEEP_ALIGN) "FALSE" : CHAN_BOND_KEEP_ALIGN_BINARY = 1'b0; "TRUE" : CHAN_BOND_KEEP_ALIGN_BINARY = 1'b1; default : begin $display("Attribute Syntax Error : The Attribute CHAN_BOND_KEEP_ALIGN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CHAN_BOND_KEEP_ALIGN); $finish; end endcase case (CHAN_BOND_SEQ_2_USE) "FALSE" : CHAN_BOND_SEQ_2_USE_BINARY = 1'b0; "TRUE" : CHAN_BOND_SEQ_2_USE_BINARY = 1'b1; default : begin $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_USE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CHAN_BOND_SEQ_2_USE); $finish; end endcase case (CHAN_BOND_SEQ_LEN) 1 : CHAN_BOND_SEQ_LEN_BINARY = 2'b00; 2 : CHAN_BOND_SEQ_LEN_BINARY = 2'b01; 3 : CHAN_BOND_SEQ_LEN_BINARY = 2'b10; 4 : CHAN_BOND_SEQ_LEN_BINARY = 2'b11; default : begin $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_LEN on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 4.", CHAN_BOND_SEQ_LEN, 1); $finish; end endcase case (CLK_CORRECT_USE) "TRUE" : CLK_CORRECT_USE_BINARY = 1'b1; "FALSE" : CLK_CORRECT_USE_BINARY = 1'b0; default : begin $display("Attribute Syntax Error : The Attribute CLK_CORRECT_USE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", CLK_CORRECT_USE); $finish; end endcase case (CLK_COR_KEEP_IDLE) "FALSE" : CLK_COR_KEEP_IDLE_BINARY = 1'b0; "TRUE" : CLK_COR_KEEP_IDLE_BINARY = 1'b1; default : begin $display("Attribute Syntax Error : The Attribute CLK_COR_KEEP_IDLE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CLK_COR_KEEP_IDLE); $finish; end endcase case (CLK_COR_PRECEDENCE) "TRUE" : CLK_COR_PRECEDENCE_BINARY = 1'b1; "FALSE" : CLK_COR_PRECEDENCE_BINARY = 1'b0; default : begin $display("Attribute Syntax Error : The Attribute CLK_COR_PRECEDENCE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", CLK_COR_PRECEDENCE); $finish; end endcase case (CLK_COR_SEQ_2_USE) "FALSE" : CLK_COR_SEQ_2_USE_BINARY = 1'b0; "TRUE" : CLK_COR_SEQ_2_USE_BINARY = 1'b1; default : begin $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_USE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CLK_COR_SEQ_2_USE); $finish; end endcase case (CLK_COR_SEQ_LEN) 1 : CLK_COR_SEQ_LEN_BINARY = 2'b00; 2 : CLK_COR_SEQ_LEN_BINARY = 2'b01; 3 : CLK_COR_SEQ_LEN_BINARY = 2'b10; 4 : CLK_COR_SEQ_LEN_BINARY = 2'b11; default : begin $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_LEN on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 4.", CLK_COR_SEQ_LEN, 1); $finish; end endcase case (DEC_MCOMMA_DETECT) "TRUE" : DEC_MCOMMA_DETECT_BINARY = 1'b1; "FALSE" : DEC_MCOMMA_DETECT_BINARY = 1'b0; default : begin $display("Attribute Syntax Error : The Attribute DEC_MCOMMA_DETECT on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_MCOMMA_DETECT); $finish; end endcase case (DEC_PCOMMA_DETECT) "TRUE" : DEC_PCOMMA_DETECT_BINARY = 1'b1; "FALSE" : DEC_PCOMMA_DETECT_BINARY = 1'b0; default : begin $display("Attribute Syntax Error : The Attribute DEC_PCOMMA_DETECT on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_PCOMMA_DETECT); $finish; end endcase case (DEC_VALID_COMMA_ONLY) "TRUE" : DEC_VALID_COMMA_ONLY_BINARY = 1'b1; "FALSE" : DEC_VALID_COMMA_ONLY_BINARY = 1'b0; default : begin $display("Attribute Syntax Error : The Attribute DEC_VALID_COMMA_ONLY on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEC_VALID_COMMA_ONLY); $finish; end endcase case (ES_ERRDET_EN) "FALSE" : ES_ERRDET_EN_BINARY = 1'b0; "TRUE" : ES_ERRDET_EN_BINARY = 1'b1; default : begin $display("Attribute Syntax Error : The Attribute ES_ERRDET_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ES_ERRDET_EN); $finish; end endcase case (ES_EYE_SCAN_EN) "FALSE" : ES_EYE_SCAN_EN_BINARY = 1'b0; "TRUE" : ES_EYE_SCAN_EN_BINARY = 1'b1; default : begin $display("Attribute Syntax Error : The Attribute ES_EYE_SCAN_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ES_EYE_SCAN_EN); $finish; end endcase case (FTS_LANE_DESKEW_EN) "FALSE" : FTS_LANE_DESKEW_EN_BINARY = 1'b0; "TRUE" : FTS_LANE_DESKEW_EN_BINARY = 1'b1; default : begin $display("Attribute Syntax Error : The Attribute FTS_LANE_DESKEW_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", FTS_LANE_DESKEW_EN); $finish; end endcase case (PCS_PCIE_EN) "FALSE" : PCS_PCIE_EN_BINARY = 1'b0; "TRUE" : PCS_PCIE_EN_BINARY = 1'b1; default : begin $display("Attribute Syntax Error : The Attribute PCS_PCIE_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PCS_PCIE_EN); $finish; end endcase case (RXBUF_ADDR_MODE) "FULL" : RXBUF_ADDR_MODE_BINARY = 1'b0; "FAST" : RXBUF_ADDR_MODE_BINARY = 1'b1; default : begin $display("Attribute Syntax Error : The Attribute RXBUF_ADDR_MODE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FULL, or FAST.", RXBUF_ADDR_MODE); $finish; end endcase case (RXBUF_EN) "TRUE" : RXBUF_EN_BINARY = 1'b1; "FALSE" : RXBUF_EN_BINARY = 1'b0; default : begin $display("Attribute Syntax Error : The Attribute RXBUF_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_EN); $finish; end endcase case (RXBUF_RESET_ON_CB_CHANGE) "TRUE" : RXBUF_RESET_ON_CB_CHANGE_BINARY = 1'b1; "FALSE" : RXBUF_RESET_ON_CB_CHANGE_BINARY = 1'b0; default : begin $display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_CB_CHANGE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_RESET_ON_CB_CHANGE); $finish; end endcase case (RXBUF_RESET_ON_COMMAALIGN) "FALSE" : RXBUF_RESET_ON_COMMAALIGN_BINARY = 1'b0; "TRUE" : RXBUF_RESET_ON_COMMAALIGN_BINARY = 1'b1; default : begin $display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_COMMAALIGN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_RESET_ON_COMMAALIGN); $finish; end endcase case (RXBUF_RESET_ON_EIDLE) "FALSE" : RXBUF_RESET_ON_EIDLE_BINARY = 1'b0; "TRUE" : RXBUF_RESET_ON_EIDLE_BINARY = 1'b1; default : begin $display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_EIDLE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_RESET_ON_EIDLE); $finish; end endcase case (RXBUF_RESET_ON_RATE_CHANGE) "TRUE" : RXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b1; "FALSE" : RXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b0; default : begin $display("Attribute Syntax Error : The Attribute RXBUF_RESET_ON_RATE_CHANGE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RXBUF_RESET_ON_RATE_CHANGE); $finish; end endcase case (RXBUF_THRESH_OVRD) "FALSE" : RXBUF_THRESH_OVRD_BINARY = 1'b0; "TRUE" : RXBUF_THRESH_OVRD_BINARY = 1'b1; default : begin $display("Attribute Syntax Error : The Attribute RXBUF_THRESH_OVRD on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXBUF_THRESH_OVRD); $finish; end endcase case (RXGEARBOX_EN) "FALSE" : RXGEARBOX_EN_BINARY = 1'b0; "TRUE" : RXGEARBOX_EN_BINARY = 1'b1; default : begin $display("Attribute Syntax Error : The Attribute RXGEARBOX_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RXGEARBOX_EN); $finish; end endcase case (RXOOB_CLK_CFG) "PMA" : RXOOB_CLK_CFG_BINARY = 1'b0; "FABRIC" : RXOOB_CLK_CFG_BINARY = 1'b1; default : begin $display("Attribute Syntax Error : The Attribute RXOOB_CLK_CFG on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are PMA, or FABRIC.", RXOOB_CLK_CFG); $finish; end endcase case (RXOUT_DIV) 2 : RXOUT_DIV_BINARY = 3'b001; 1 : RXOUT_DIV_BINARY = 3'b000; 4 : RXOUT_DIV_BINARY = 3'b010; 8 : RXOUT_DIV_BINARY = 3'b011; 16 : RXOUT_DIV_BINARY = 3'b100; default : begin $display("Attribute Syntax Error : The Attribute RXOUT_DIV on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 16.", RXOUT_DIV, 2); $finish; end endcase case (RXSLIDE_MODE) "OFF" : RXSLIDE_MODE_BINARY = 2'b00; "AUTO" : RXSLIDE_MODE_BINARY = 2'b01; "PCS" : RXSLIDE_MODE_BINARY = 2'b10; "PMA" : RXSLIDE_MODE_BINARY = 2'b11; default : begin $display("Attribute Syntax Error : The Attribute RXSLIDE_MODE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are OFF, AUTO, PCS, or PMA.", RXSLIDE_MODE); $finish; end endcase case (RX_CLK25_DIV) 7 : RX_CLK25_DIV_BINARY = 5'b00110; 1 : RX_CLK25_DIV_BINARY = 5'b00000; 2 : RX_CLK25_DIV_BINARY = 5'b00001; 3 : RX_CLK25_DIV_BINARY = 5'b00010; 4 : RX_CLK25_DIV_BINARY = 5'b00011; 5 : RX_CLK25_DIV_BINARY = 5'b00100; 6 : RX_CLK25_DIV_BINARY = 5'b00101; 8 : RX_CLK25_DIV_BINARY = 5'b00111; 9 : RX_CLK25_DIV_BINARY = 5'b01000; 10 : RX_CLK25_DIV_BINARY = 5'b01001; 11 : RX_CLK25_DIV_BINARY = 5'b01010; 12 : RX_CLK25_DIV_BINARY = 5'b01011; 13 : RX_CLK25_DIV_BINARY = 5'b01100; 14 : RX_CLK25_DIV_BINARY = 5'b01101; 15 : RX_CLK25_DIV_BINARY = 5'b01110; 16 : RX_CLK25_DIV_BINARY = 5'b01111; 17 : RX_CLK25_DIV_BINARY = 5'b10000; 18 : RX_CLK25_DIV_BINARY = 5'b10001; 19 : RX_CLK25_DIV_BINARY = 5'b10010; 20 : RX_CLK25_DIV_BINARY = 5'b10011; 21 : RX_CLK25_DIV_BINARY = 5'b10100; 22 : RX_CLK25_DIV_BINARY = 5'b10101; 23 : RX_CLK25_DIV_BINARY = 5'b10110; 24 : RX_CLK25_DIV_BINARY = 5'b10111; 25 : RX_CLK25_DIV_BINARY = 5'b11000; 26 : RX_CLK25_DIV_BINARY = 5'b11001; 27 : RX_CLK25_DIV_BINARY = 5'b11010; 28 : RX_CLK25_DIV_BINARY = 5'b11011; 29 : RX_CLK25_DIV_BINARY = 5'b11100; 30 : RX_CLK25_DIV_BINARY = 5'b11101; 31 : RX_CLK25_DIV_BINARY = 5'b11110; 32 : RX_CLK25_DIV_BINARY = 5'b11111; default : begin $display("Attribute Syntax Error : The Attribute RX_CLK25_DIV on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", RX_CLK25_DIV, 7); $finish; end endcase case (RX_DATA_WIDTH) 20 : RX_DATA_WIDTH_BINARY = 3'b011; 16 : RX_DATA_WIDTH_BINARY = 3'b010; 32 : RX_DATA_WIDTH_BINARY = 3'b100; 40 : RX_DATA_WIDTH_BINARY = 3'b101; default : begin $display("Attribute Syntax Error : The Attribute RX_DATA_WIDTH on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 16 to 40.", RX_DATA_WIDTH, 20); $finish; end endcase case (RX_DEFER_RESET_BUF_EN) "TRUE" : RX_DEFER_RESET_BUF_EN_BINARY = 1'b1; "FALSE" : RX_DEFER_RESET_BUF_EN_BINARY = 1'b0; default : begin $display("Attribute Syntax Error : The Attribute RX_DEFER_RESET_BUF_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RX_DEFER_RESET_BUF_EN); $finish; end endcase case (RX_DISPERR_SEQ_MATCH) "TRUE" : RX_DISPERR_SEQ_MATCH_BINARY = 1'b1; "FALSE" : RX_DISPERR_SEQ_MATCH_BINARY = 1'b0; default : begin $display("Attribute Syntax Error : The Attribute RX_DISPERR_SEQ_MATCH on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", RX_DISPERR_SEQ_MATCH); $finish; end endcase case (RX_SIG_VALID_DLY) 10 : RX_SIG_VALID_DLY_BINARY = 5'b01001; 1 : RX_SIG_VALID_DLY_BINARY = 5'b00000; 2 : RX_SIG_VALID_DLY_BINARY = 5'b00001; 3 : RX_SIG_VALID_DLY_BINARY = 5'b00010; 4 : RX_SIG_VALID_DLY_BINARY = 5'b00011; 5 : RX_SIG_VALID_DLY_BINARY = 5'b00100; 6 : RX_SIG_VALID_DLY_BINARY = 5'b00101; 7 : RX_SIG_VALID_DLY_BINARY = 5'b00110; 8 : RX_SIG_VALID_DLY_BINARY = 5'b00111; 9 : RX_SIG_VALID_DLY_BINARY = 5'b01000; 11 : RX_SIG_VALID_DLY_BINARY = 5'b01010; 12 : RX_SIG_VALID_DLY_BINARY = 5'b01011; 13 : RX_SIG_VALID_DLY_BINARY = 5'b01100; 14 : RX_SIG_VALID_DLY_BINARY = 5'b01101; 15 : RX_SIG_VALID_DLY_BINARY = 5'b01110; 16 : RX_SIG_VALID_DLY_BINARY = 5'b01111; 17 : RX_SIG_VALID_DLY_BINARY = 5'b10000; 18 : RX_SIG_VALID_DLY_BINARY = 5'b10001; 19 : RX_SIG_VALID_DLY_BINARY = 5'b10010; 20 : RX_SIG_VALID_DLY_BINARY = 5'b10011; 21 : RX_SIG_VALID_DLY_BINARY = 5'b10100; 22 : RX_SIG_VALID_DLY_BINARY = 5'b10101; 23 : RX_SIG_VALID_DLY_BINARY = 5'b10110; 24 : RX_SIG_VALID_DLY_BINARY = 5'b10111; 25 : RX_SIG_VALID_DLY_BINARY = 5'b11000; 26 : RX_SIG_VALID_DLY_BINARY = 5'b11001; 27 : RX_SIG_VALID_DLY_BINARY = 5'b11010; 28 : RX_SIG_VALID_DLY_BINARY = 5'b11011; 29 : RX_SIG_VALID_DLY_BINARY = 5'b11100; 30 : RX_SIG_VALID_DLY_BINARY = 5'b11101; 31 : RX_SIG_VALID_DLY_BINARY = 5'b11110; 32 : RX_SIG_VALID_DLY_BINARY = 5'b11111; default : begin $display("Attribute Syntax Error : The Attribute RX_SIG_VALID_DLY on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", RX_SIG_VALID_DLY, 10); $finish; end endcase case (RX_XCLK_SEL) "RXREC" : RX_XCLK_SEL_BINARY = 1'b0; "RXUSR" : RX_XCLK_SEL_BINARY = 1'b1; default : begin $display("Attribute Syntax Error : The Attribute RX_XCLK_SEL on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are RXREC, or RXUSR.", RX_XCLK_SEL); $finish; end endcase case (SATA_PLL_CFG) "VCO_3000MHZ" : SATA_PLL_CFG_BINARY = 2'b00; "VCO_750MHZ" : SATA_PLL_CFG_BINARY = 2'b10; "VCO_1500MHZ" : SATA_PLL_CFG_BINARY = 2'b01; default : begin $display("Attribute Syntax Error : The Attribute SATA_PLL_CFG on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are VCO_3000MHZ, VCO_750MHZ, or VCO_1500MHZ.", SATA_PLL_CFG); $finish; end endcase case (SHOW_REALIGN_COMMA) "TRUE" : SHOW_REALIGN_COMMA_BINARY = 1'b1; "FALSE" : SHOW_REALIGN_COMMA_BINARY = 1'b0; default : begin $display("Attribute Syntax Error : The Attribute SHOW_REALIGN_COMMA on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SHOW_REALIGN_COMMA); $finish; end endcase case (SIM_RECEIVER_DETECT_PASS) "TRUE" : SIM_RECEIVER_DETECT_PASS_BINARY = 0; "FALSE" : SIM_RECEIVER_DETECT_PASS_BINARY = 0; default : begin $display("Attribute Syntax Error : The Attribute SIM_RECEIVER_DETECT_PASS on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RECEIVER_DETECT_PASS); $finish; end endcase case (SIM_RESET_SPEEDUP) "TRUE" : SIM_RESET_SPEEDUP_BINARY = 0; "FALSE" : SIM_RESET_SPEEDUP_BINARY = 0; default : begin $display("Attribute Syntax Error : The Attribute SIM_RESET_SPEEDUP on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RESET_SPEEDUP); $finish; end endcase case (SIM_TX_EIDLE_DRIVE_LEVEL) "X" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0; "0" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0; "1" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0; "Z" : SIM_TX_EIDLE_DRIVE_LEVEL_BINARY = 0; default : begin $display("Attribute Syntax Error : The Attribute SIM_TX_EIDLE_DRIVE_LEVEL on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are X, 0, 1, or Z.", SIM_TX_EIDLE_DRIVE_LEVEL); $finish; end endcase case (SIM_VERSION) "1.0" : SIM_VERSION_BINARY = 0; "1.1" : SIM_VERSION_BINARY = 0; "2.0" : SIM_VERSION_BINARY = 0; default : begin $display("Attribute Syntax Error : The Attribute SIM_VERSION on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are 1.0, 1.1, or 2.0.", SIM_VERSION); $finish; end endcase case (TXBUF_EN) "TRUE" : TXBUF_EN_BINARY = 1'b1; "FALSE" : TXBUF_EN_BINARY = 1'b0; default : begin $display("Attribute Syntax Error : The Attribute TXBUF_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", TXBUF_EN); $finish; end endcase case (TXBUF_RESET_ON_RATE_CHANGE) "FALSE" : TXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b0; "TRUE" : TXBUF_RESET_ON_RATE_CHANGE_BINARY = 1'b1; default : begin $display("Attribute Syntax Error : The Attribute TXBUF_RESET_ON_RATE_CHANGE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TXBUF_RESET_ON_RATE_CHANGE); $finish; end endcase case (TXGEARBOX_EN) "FALSE" : TXGEARBOX_EN_BINARY = 1'b0; "TRUE" : TXGEARBOX_EN_BINARY = 1'b1; default : begin $display("Attribute Syntax Error : The Attribute TXGEARBOX_EN on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TXGEARBOX_EN); $finish; end endcase case (TXOUT_DIV) 2 : TXOUT_DIV_BINARY = 3'b001; 1 : TXOUT_DIV_BINARY = 3'b000; 4 : TXOUT_DIV_BINARY = 3'b010; 8 : TXOUT_DIV_BINARY = 3'b011; 16 : TXOUT_DIV_BINARY = 3'b100; default : begin $display("Attribute Syntax Error : The Attribute TXOUT_DIV on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 16.", TXOUT_DIV, 2); $finish; end endcase case (TXPI_PPMCLK_SEL) "TXUSRCLK2" : TXPI_PPMCLK_SEL_BINARY = 1'b1; "TXUSRCLK" : TXPI_PPMCLK_SEL_BINARY = 1'b0; default : begin $display("Attribute Syntax Error : The Attribute TXPI_PPMCLK_SEL on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TXUSRCLK2, or TXUSRCLK.", TXPI_PPMCLK_SEL); $finish; end endcase case (TX_CLK25_DIV) 7 : TX_CLK25_DIV_BINARY = 5'b00110; 1 : TX_CLK25_DIV_BINARY = 5'b00000; 2 : TX_CLK25_DIV_BINARY = 5'b00001; 3 : TX_CLK25_DIV_BINARY = 5'b00010; 4 : TX_CLK25_DIV_BINARY = 5'b00011; 5 : TX_CLK25_DIV_BINARY = 5'b00100; 6 : TX_CLK25_DIV_BINARY = 5'b00101; 8 : TX_CLK25_DIV_BINARY = 5'b00111; 9 : TX_CLK25_DIV_BINARY = 5'b01000; 10 : TX_CLK25_DIV_BINARY = 5'b01001; 11 : TX_CLK25_DIV_BINARY = 5'b01010; 12 : TX_CLK25_DIV_BINARY = 5'b01011; 13 : TX_CLK25_DIV_BINARY = 5'b01100; 14 : TX_CLK25_DIV_BINARY = 5'b01101; 15 : TX_CLK25_DIV_BINARY = 5'b01110; 16 : TX_CLK25_DIV_BINARY = 5'b01111; 17 : TX_CLK25_DIV_BINARY = 5'b10000; 18 : TX_CLK25_DIV_BINARY = 5'b10001; 19 : TX_CLK25_DIV_BINARY = 5'b10010; 20 : TX_CLK25_DIV_BINARY = 5'b10011; 21 : TX_CLK25_DIV_BINARY = 5'b10100; 22 : TX_CLK25_DIV_BINARY = 5'b10101; 23 : TX_CLK25_DIV_BINARY = 5'b10110; 24 : TX_CLK25_DIV_BINARY = 5'b10111; 25 : TX_CLK25_DIV_BINARY = 5'b11000; 26 : TX_CLK25_DIV_BINARY = 5'b11001; 27 : TX_CLK25_DIV_BINARY = 5'b11010; 28 : TX_CLK25_DIV_BINARY = 5'b11011; 29 : TX_CLK25_DIV_BINARY = 5'b11100; 30 : TX_CLK25_DIV_BINARY = 5'b11101; 31 : TX_CLK25_DIV_BINARY = 5'b11110; 32 : TX_CLK25_DIV_BINARY = 5'b11111; default : begin $display("Attribute Syntax Error : The Attribute TX_CLK25_DIV on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 32.", TX_CLK25_DIV, 7); $finish; end endcase case (TX_DATA_WIDTH) 20 : TX_DATA_WIDTH_BINARY = 3'b011; 16 : TX_DATA_WIDTH_BINARY = 3'b010; 32 : TX_DATA_WIDTH_BINARY = 3'b100; 40 : TX_DATA_WIDTH_BINARY = 3'b101; default : begin $display("Attribute Syntax Error : The Attribute TX_DATA_WIDTH on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 16 to 40.", TX_DATA_WIDTH, 20); $finish; end endcase case (TX_DRIVE_MODE) "DIRECT" : TX_DRIVE_MODE_BINARY = 5'b00000; "PIPE" : TX_DRIVE_MODE_BINARY = 5'b00001; "PIPEGEN3" : TX_DRIVE_MODE_BINARY = 5'b00010; default : begin $display("Attribute Syntax Error : The Attribute TX_DRIVE_MODE on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are DIRECT, PIPE, or PIPEGEN3.", TX_DRIVE_MODE); $finish; end endcase case (TX_LOOPBACK_DRIVE_HIZ) "FALSE" : TX_LOOPBACK_DRIVE_HIZ_BINARY = 1'b0; "TRUE" : TX_LOOPBACK_DRIVE_HIZ_BINARY = 1'b1; default : begin $display("Attribute Syntax Error : The Attribute TX_LOOPBACK_DRIVE_HIZ on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TX_LOOPBACK_DRIVE_HIZ); $finish; end endcase case (TX_XCLK_SEL) "TXUSR" : TX_XCLK_SEL_BINARY = 1'b1; "TXOUT" : TX_XCLK_SEL_BINARY = 1'b0; default : begin $display("Attribute Syntax Error : The Attribute TX_XCLK_SEL on X_GTPE2_CHANNEL instance %m is set to %s. Legal values for this attribute are TXUSR, or TXOUT.", TX_XCLK_SEL); $finish; end endcase if ((ACJTAG_DEBUG_MODE >= 1'b0) && (ACJTAG_DEBUG_MODE <= 1'b1)) ACJTAG_DEBUG_MODE_BINARY = ACJTAG_DEBUG_MODE; else begin $display("Attribute Syntax Error : The Attribute ACJTAG_DEBUG_MODE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ACJTAG_DEBUG_MODE); $finish; end if ((ACJTAG_MODE >= 1'b0) && (ACJTAG_MODE <= 1'b1)) ACJTAG_MODE_BINARY = ACJTAG_MODE; else begin $display("Attribute Syntax Error : The Attribute ACJTAG_MODE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ACJTAG_MODE); $finish; end if ((ACJTAG_RESET >= 1'b0) && (ACJTAG_RESET <= 1'b1)) ACJTAG_RESET_BINARY = ACJTAG_RESET; else begin $display("Attribute Syntax Error : The Attribute ACJTAG_RESET on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ACJTAG_RESET); $finish; end if ((ADAPT_CFG0 >= 20'b00000000000000000000) && (ADAPT_CFG0 <= 20'b11111111111111111111)) ADAPT_CFG0_BINARY = ADAPT_CFG0; else begin $display("Attribute Syntax Error : The Attribute ADAPT_CFG0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 20'b00000000000000000000 to 20'b11111111111111111111.", ADAPT_CFG0); $finish; end if ((ALIGN_COMMA_ENABLE >= 10'b0000000000) && (ALIGN_COMMA_ENABLE <= 10'b1111111111)) ALIGN_COMMA_ENABLE_BINARY = ALIGN_COMMA_ENABLE; else begin $display("Attribute Syntax Error : The Attribute ALIGN_COMMA_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_COMMA_ENABLE); $finish; end if ((ALIGN_COMMA_WORD >= 1) && (ALIGN_COMMA_WORD <= 2)) ALIGN_COMMA_WORD_BINARY = ALIGN_COMMA_WORD; else begin $display("Attribute Syntax Error : The Attribute ALIGN_COMMA_WORD on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 2.", ALIGN_COMMA_WORD); $finish; end if ((ALIGN_MCOMMA_VALUE >= 10'b0000000000) && (ALIGN_MCOMMA_VALUE <= 10'b1111111111)) ALIGN_MCOMMA_VALUE_BINARY = ALIGN_MCOMMA_VALUE; else begin $display("Attribute Syntax Error : The Attribute ALIGN_MCOMMA_VALUE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_MCOMMA_VALUE); $finish; end if ((ALIGN_PCOMMA_VALUE >= 10'b0000000000) && (ALIGN_PCOMMA_VALUE <= 10'b1111111111)) ALIGN_PCOMMA_VALUE_BINARY = ALIGN_PCOMMA_VALUE; else begin $display("Attribute Syntax Error : The Attribute ALIGN_PCOMMA_VALUE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ALIGN_PCOMMA_VALUE); $finish; end if ((CFOK_CFG >= 43'b0000000000000000000000000000000000000000000) && (CFOK_CFG <= 43'b1111111111111111111111111111111111111111111)) CFOK_CFG_BINARY = CFOK_CFG; else begin $display("Attribute Syntax Error : The Attribute CFOK_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 43'b0000000000000000000000000000000000000000000 to 43'b1111111111111111111111111111111111111111111.", CFOK_CFG); $finish; end if ((CFOK_CFG2 >= 7'b0000000) && (CFOK_CFG2 <= 7'b1111111)) CFOK_CFG2_BINARY = CFOK_CFG2; else begin $display("Attribute Syntax Error : The Attribute CFOK_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", CFOK_CFG2); $finish; end if ((CFOK_CFG3 >= 7'b0000000) && (CFOK_CFG3 <= 7'b1111111)) CFOK_CFG3_BINARY = CFOK_CFG3; else begin $display("Attribute Syntax Error : The Attribute CFOK_CFG3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", CFOK_CFG3); $finish; end if ((CFOK_CFG4 >= 1'b0) && (CFOK_CFG4 <= 1'b1)) CFOK_CFG4_BINARY = CFOK_CFG4; else begin $display("Attribute Syntax Error : The Attribute CFOK_CFG4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", CFOK_CFG4); $finish; end if ((CFOK_CFG5 >= 2'b00) && (CFOK_CFG5 <= 2'b11)) CFOK_CFG5_BINARY = CFOK_CFG5; else begin $display("Attribute Syntax Error : The Attribute CFOK_CFG5 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", CFOK_CFG5); $finish; end if ((CFOK_CFG6 >= 4'b0000) && (CFOK_CFG6 <= 4'b1111)) CFOK_CFG6_BINARY = CFOK_CFG6; else begin $display("Attribute Syntax Error : The Attribute CFOK_CFG6 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CFOK_CFG6); $finish; end if ((CHAN_BOND_MAX_SKEW >= 1) && (CHAN_BOND_MAX_SKEW <= 14)) CHAN_BOND_MAX_SKEW_BINARY = CHAN_BOND_MAX_SKEW; else begin $display("Attribute Syntax Error : The Attribute CHAN_BOND_MAX_SKEW on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 14.", CHAN_BOND_MAX_SKEW); $finish; end if ((CHAN_BOND_SEQ_1_1 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_1 <= 10'b1111111111)) CHAN_BOND_SEQ_1_1_BINARY = CHAN_BOND_SEQ_1_1; else begin $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_1); $finish; end if ((CHAN_BOND_SEQ_1_2 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_2 <= 10'b1111111111)) CHAN_BOND_SEQ_1_2_BINARY = CHAN_BOND_SEQ_1_2; else begin $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_2); $finish; end if ((CHAN_BOND_SEQ_1_3 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_3 <= 10'b1111111111)) CHAN_BOND_SEQ_1_3_BINARY = CHAN_BOND_SEQ_1_3; else begin $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_3); $finish; end if ((CHAN_BOND_SEQ_1_4 >= 10'b0000000000) && (CHAN_BOND_SEQ_1_4 <= 10'b1111111111)) CHAN_BOND_SEQ_1_4_BINARY = CHAN_BOND_SEQ_1_4; else begin $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_1_4); $finish; end if ((CHAN_BOND_SEQ_1_ENABLE >= 4'b0000) && (CHAN_BOND_SEQ_1_ENABLE <= 4'b1111)) CHAN_BOND_SEQ_1_ENABLE_BINARY = CHAN_BOND_SEQ_1_ENABLE; else begin $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CHAN_BOND_SEQ_1_ENABLE); $finish; end if ((CHAN_BOND_SEQ_2_1 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_1 <= 10'b1111111111)) CHAN_BOND_SEQ_2_1_BINARY = CHAN_BOND_SEQ_2_1; else begin $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_1); $finish; end if ((CHAN_BOND_SEQ_2_2 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_2 <= 10'b1111111111)) CHAN_BOND_SEQ_2_2_BINARY = CHAN_BOND_SEQ_2_2; else begin $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_2); $finish; end if ((CHAN_BOND_SEQ_2_3 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_3 <= 10'b1111111111)) CHAN_BOND_SEQ_2_3_BINARY = CHAN_BOND_SEQ_2_3; else begin $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_3); $finish; end if ((CHAN_BOND_SEQ_2_4 >= 10'b0000000000) && (CHAN_BOND_SEQ_2_4 <= 10'b1111111111)) CHAN_BOND_SEQ_2_4_BINARY = CHAN_BOND_SEQ_2_4; else begin $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CHAN_BOND_SEQ_2_4); $finish; end if ((CHAN_BOND_SEQ_2_ENABLE >= 4'b0000) && (CHAN_BOND_SEQ_2_ENABLE <= 4'b1111)) CHAN_BOND_SEQ_2_ENABLE_BINARY = CHAN_BOND_SEQ_2_ENABLE; else begin $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CHAN_BOND_SEQ_2_ENABLE); $finish; end if ((CLK_COMMON_SWING >= 1'b0) && (CLK_COMMON_SWING <= 1'b1)) CLK_COMMON_SWING_BINARY = CLK_COMMON_SWING; else begin $display("Attribute Syntax Error : The Attribute CLK_COMMON_SWING on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", CLK_COMMON_SWING); $finish; end if ((CLK_COR_MAX_LAT >= 3) && (CLK_COR_MAX_LAT <= 60)) CLK_COR_MAX_LAT_BINARY = CLK_COR_MAX_LAT; else begin $display("Attribute Syntax Error : The Attribute CLK_COR_MAX_LAT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 3 to 60.", CLK_COR_MAX_LAT); $finish; end if ((CLK_COR_MIN_LAT >= 3) && (CLK_COR_MIN_LAT <= 60)) CLK_COR_MIN_LAT_BINARY = CLK_COR_MIN_LAT; else begin $display("Attribute Syntax Error : The Attribute CLK_COR_MIN_LAT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 3 to 60.", CLK_COR_MIN_LAT); $finish; end if ((CLK_COR_REPEAT_WAIT >= 0) && (CLK_COR_REPEAT_WAIT <= 31)) CLK_COR_REPEAT_WAIT_BINARY = CLK_COR_REPEAT_WAIT; else begin $display("Attribute Syntax Error : The Attribute CLK_COR_REPEAT_WAIT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 31.", CLK_COR_REPEAT_WAIT); $finish; end if ((CLK_COR_SEQ_1_1 >= 10'b0000000000) && (CLK_COR_SEQ_1_1 <= 10'b1111111111)) CLK_COR_SEQ_1_1_BINARY = CLK_COR_SEQ_1_1; else begin $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_1); $finish; end if ((CLK_COR_SEQ_1_2 >= 10'b0000000000) && (CLK_COR_SEQ_1_2 <= 10'b1111111111)) CLK_COR_SEQ_1_2_BINARY = CLK_COR_SEQ_1_2; else begin $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_2); $finish; end if ((CLK_COR_SEQ_1_3 >= 10'b0000000000) && (CLK_COR_SEQ_1_3 <= 10'b1111111111)) CLK_COR_SEQ_1_3_BINARY = CLK_COR_SEQ_1_3; else begin $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_3); $finish; end if ((CLK_COR_SEQ_1_4 >= 10'b0000000000) && (CLK_COR_SEQ_1_4 <= 10'b1111111111)) CLK_COR_SEQ_1_4_BINARY = CLK_COR_SEQ_1_4; else begin $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_1_4); $finish; end if ((CLK_COR_SEQ_1_ENABLE >= 4'b0000) && (CLK_COR_SEQ_1_ENABLE <= 4'b1111)) CLK_COR_SEQ_1_ENABLE_BINARY = CLK_COR_SEQ_1_ENABLE; else begin $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CLK_COR_SEQ_1_ENABLE); $finish; end if ((CLK_COR_SEQ_2_1 >= 10'b0000000000) && (CLK_COR_SEQ_2_1 <= 10'b1111111111)) CLK_COR_SEQ_2_1_BINARY = CLK_COR_SEQ_2_1; else begin $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_1); $finish; end if ((CLK_COR_SEQ_2_2 >= 10'b0000000000) && (CLK_COR_SEQ_2_2 <= 10'b1111111111)) CLK_COR_SEQ_2_2_BINARY = CLK_COR_SEQ_2_2; else begin $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_2); $finish; end if ((CLK_COR_SEQ_2_3 >= 10'b0000000000) && (CLK_COR_SEQ_2_3 <= 10'b1111111111)) CLK_COR_SEQ_2_3_BINARY = CLK_COR_SEQ_2_3; else begin $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_3); $finish; end if ((CLK_COR_SEQ_2_4 >= 10'b0000000000) && (CLK_COR_SEQ_2_4 <= 10'b1111111111)) CLK_COR_SEQ_2_4_BINARY = CLK_COR_SEQ_2_4; else begin $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", CLK_COR_SEQ_2_4); $finish; end if ((CLK_COR_SEQ_2_ENABLE >= 4'b0000) && (CLK_COR_SEQ_2_ENABLE <= 4'b1111)) CLK_COR_SEQ_2_ENABLE_BINARY = CLK_COR_SEQ_2_ENABLE; else begin $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", CLK_COR_SEQ_2_ENABLE); $finish; end if ((ES_CLK_PHASE_SEL >= 1'b0) && (ES_CLK_PHASE_SEL <= 1'b1)) ES_CLK_PHASE_SEL_BINARY = ES_CLK_PHASE_SEL; else begin $display("Attribute Syntax Error : The Attribute ES_CLK_PHASE_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", ES_CLK_PHASE_SEL); $finish; end if ((ES_CONTROL >= 6'b000000) && (ES_CONTROL <= 6'b111111)) ES_CONTROL_BINARY = ES_CONTROL; else begin $display("Attribute Syntax Error : The Attribute ES_CONTROL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", ES_CONTROL); $finish; end if ((ES_PMA_CFG >= 10'b0000000000) && (ES_PMA_CFG <= 10'b1111111111)) ES_PMA_CFG_BINARY = ES_PMA_CFG; else begin $display("Attribute Syntax Error : The Attribute ES_PMA_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", ES_PMA_CFG); $finish; end if ((ES_PRESCALE >= 5'b00000) && (ES_PRESCALE <= 5'b11111)) ES_PRESCALE_BINARY = ES_PRESCALE; else begin $display("Attribute Syntax Error : The Attribute ES_PRESCALE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", ES_PRESCALE); $finish; end if ((ES_VERT_OFFSET >= 9'b000000000) && (ES_VERT_OFFSET <= 9'b111111111)) ES_VERT_OFFSET_BINARY = ES_VERT_OFFSET; else begin $display("Attribute Syntax Error : The Attribute ES_VERT_OFFSET on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111.", ES_VERT_OFFSET); $finish; end if ((FTS_DESKEW_SEQ_ENABLE >= 4'b0000) && (FTS_DESKEW_SEQ_ENABLE <= 4'b1111)) FTS_DESKEW_SEQ_ENABLE_BINARY = FTS_DESKEW_SEQ_ENABLE; else begin $display("Attribute Syntax Error : The Attribute FTS_DESKEW_SEQ_ENABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", FTS_DESKEW_SEQ_ENABLE); $finish; end if ((FTS_LANE_DESKEW_CFG >= 4'b0000) && (FTS_LANE_DESKEW_CFG <= 4'b1111)) FTS_LANE_DESKEW_CFG_BINARY = FTS_LANE_DESKEW_CFG; else begin $display("Attribute Syntax Error : The Attribute FTS_LANE_DESKEW_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", FTS_LANE_DESKEW_CFG); $finish; end if ((GEARBOX_MODE >= 3'b000) && (GEARBOX_MODE <= 3'b111)) GEARBOX_MODE_BINARY = GEARBOX_MODE; else begin $display("Attribute Syntax Error : The Attribute GEARBOX_MODE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", GEARBOX_MODE); $finish; end if ((LOOPBACK_CFG >= 1'b0) && (LOOPBACK_CFG <= 1'b1)) LOOPBACK_CFG_BINARY = LOOPBACK_CFG; else begin $display("Attribute Syntax Error : The Attribute LOOPBACK_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", LOOPBACK_CFG); $finish; end if ((OUTREFCLK_SEL_INV >= 2'b00) && (OUTREFCLK_SEL_INV <= 2'b11)) OUTREFCLK_SEL_INV_BINARY = OUTREFCLK_SEL_INV; else begin $display("Attribute Syntax Error : The Attribute OUTREFCLK_SEL_INV on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", OUTREFCLK_SEL_INV); $finish; end if ((PMA_LOOPBACK_CFG >= 1'b0) && (PMA_LOOPBACK_CFG <= 1'b1)) PMA_LOOPBACK_CFG_BINARY = PMA_LOOPBACK_CFG; else begin $display("Attribute Syntax Error : The Attribute PMA_LOOPBACK_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", PMA_LOOPBACK_CFG); $finish; end if ((PMA_RSV3 >= 2'b00) && (PMA_RSV3 <= 2'b11)) PMA_RSV3_BINARY = PMA_RSV3; else begin $display("Attribute Syntax Error : The Attribute PMA_RSV3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", PMA_RSV3); $finish; end if ((PMA_RSV4 >= 4'b0000) && (PMA_RSV4 <= 4'b1111)) PMA_RSV4_BINARY = PMA_RSV4; else begin $display("Attribute Syntax Error : The Attribute PMA_RSV4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", PMA_RSV4); $finish; end if ((PMA_RSV5 >= 1'b0) && (PMA_RSV5 <= 1'b1)) PMA_RSV5_BINARY = PMA_RSV5; else begin $display("Attribute Syntax Error : The Attribute PMA_RSV5 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", PMA_RSV5); $finish; end if ((PMA_RSV6 >= 1'b0) && (PMA_RSV6 <= 1'b1)) PMA_RSV6_BINARY = PMA_RSV6; else begin $display("Attribute Syntax Error : The Attribute PMA_RSV6 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", PMA_RSV6); $finish; end if ((PMA_RSV7 >= 1'b0) && (PMA_RSV7 <= 1'b1)) PMA_RSV7_BINARY = PMA_RSV7; else begin $display("Attribute Syntax Error : The Attribute PMA_RSV7 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", PMA_RSV7); $finish; end if ((RXBUFRESET_TIME >= 5'b00000) && (RXBUFRESET_TIME <= 5'b11111)) RXBUFRESET_TIME_BINARY = RXBUFRESET_TIME; else begin $display("Attribute Syntax Error : The Attribute RXBUFRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXBUFRESET_TIME); $finish; end if ((RXBUF_EIDLE_HI_CNT >= 4'b0000) && (RXBUF_EIDLE_HI_CNT <= 4'b1111)) RXBUF_EIDLE_HI_CNT_BINARY = RXBUF_EIDLE_HI_CNT; else begin $display("Attribute Syntax Error : The Attribute RXBUF_EIDLE_HI_CNT on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXBUF_EIDLE_HI_CNT); $finish; end if ((RXBUF_EIDLE_LO_CNT >= 4'b0000) && (RXBUF_EIDLE_LO_CNT <= 4'b1111)) RXBUF_EIDLE_LO_CNT_BINARY = RXBUF_EIDLE_LO_CNT; else begin $display("Attribute Syntax Error : The Attribute RXBUF_EIDLE_LO_CNT on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXBUF_EIDLE_LO_CNT); $finish; end if ((RXBUF_THRESH_OVFLW >= 0) && (RXBUF_THRESH_OVFLW <= 63)) RXBUF_THRESH_OVFLW_BINARY = RXBUF_THRESH_OVFLW; else begin $display("Attribute Syntax Error : The Attribute RXBUF_THRESH_OVFLW on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 63.", RXBUF_THRESH_OVFLW); $finish; end if ((RXBUF_THRESH_UNDFLW >= 0) && (RXBUF_THRESH_UNDFLW <= 63)) RXBUF_THRESH_UNDFLW_BINARY = RXBUF_THRESH_UNDFLW; else begin $display("Attribute Syntax Error : The Attribute RXBUF_THRESH_UNDFLW on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 63.", RXBUF_THRESH_UNDFLW); $finish; end if ((RXCDRFREQRESET_TIME >= 5'b00000) && (RXCDRFREQRESET_TIME <= 5'b11111)) RXCDRFREQRESET_TIME_BINARY = RXCDRFREQRESET_TIME; else begin $display("Attribute Syntax Error : The Attribute RXCDRFREQRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXCDRFREQRESET_TIME); $finish; end if ((RXCDRPHRESET_TIME >= 5'b00000) && (RXCDRPHRESET_TIME <= 5'b11111)) RXCDRPHRESET_TIME_BINARY = RXCDRPHRESET_TIME; else begin $display("Attribute Syntax Error : The Attribute RXCDRPHRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXCDRPHRESET_TIME); $finish; end if ((RXCDR_FR_RESET_ON_EIDLE >= 1'b0) && (RXCDR_FR_RESET_ON_EIDLE <= 1'b1)) RXCDR_FR_RESET_ON_EIDLE_BINARY = RXCDR_FR_RESET_ON_EIDLE; else begin $display("Attribute Syntax Error : The Attribute RXCDR_FR_RESET_ON_EIDLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_FR_RESET_ON_EIDLE); $finish; end if ((RXCDR_HOLD_DURING_EIDLE >= 1'b0) && (RXCDR_HOLD_DURING_EIDLE <= 1'b1)) RXCDR_HOLD_DURING_EIDLE_BINARY = RXCDR_HOLD_DURING_EIDLE; else begin $display("Attribute Syntax Error : The Attribute RXCDR_HOLD_DURING_EIDLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_HOLD_DURING_EIDLE); $finish; end if ((RXCDR_LOCK_CFG >= 6'b000000) && (RXCDR_LOCK_CFG <= 6'b111111)) RXCDR_LOCK_CFG_BINARY = RXCDR_LOCK_CFG; else begin $display("Attribute Syntax Error : The Attribute RXCDR_LOCK_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RXCDR_LOCK_CFG); $finish; end if ((RXCDR_PH_RESET_ON_EIDLE >= 1'b0) && (RXCDR_PH_RESET_ON_EIDLE <= 1'b1)) RXCDR_PH_RESET_ON_EIDLE_BINARY = RXCDR_PH_RESET_ON_EIDLE; else begin $display("Attribute Syntax Error : The Attribute RXCDR_PH_RESET_ON_EIDLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXCDR_PH_RESET_ON_EIDLE); $finish; end if ((RXISCANRESET_TIME >= 5'b00000) && (RXISCANRESET_TIME <= 5'b11111)) RXISCANRESET_TIME_BINARY = RXISCANRESET_TIME; else begin $display("Attribute Syntax Error : The Attribute RXISCANRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXISCANRESET_TIME); $finish; end if ((RXLPMRESET_TIME >= 7'b0000000) && (RXLPMRESET_TIME <= 7'b1111111)) RXLPMRESET_TIME_BINARY = RXLPMRESET_TIME; else begin $display("Attribute Syntax Error : The Attribute RXLPMRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", RXLPMRESET_TIME); $finish; end if ((RXLPM_BIAS_STARTUP_DISABLE >= 1'b0) && (RXLPM_BIAS_STARTUP_DISABLE <= 1'b1)) RXLPM_BIAS_STARTUP_DISABLE_BINARY = RXLPM_BIAS_STARTUP_DISABLE; else begin $display("Attribute Syntax Error : The Attribute RXLPM_BIAS_STARTUP_DISABLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_BIAS_STARTUP_DISABLE); $finish; end if ((RXLPM_CFG >= 4'b0000) && (RXLPM_CFG <= 4'b1111)) RXLPM_CFG_BINARY = RXLPM_CFG; else begin $display("Attribute Syntax Error : The Attribute RXLPM_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXLPM_CFG); $finish; end if ((RXLPM_CFG1 >= 1'b0) && (RXLPM_CFG1 <= 1'b1)) RXLPM_CFG1_BINARY = RXLPM_CFG1; else begin $display("Attribute Syntax Error : The Attribute RXLPM_CFG1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_CFG1); $finish; end if ((RXLPM_CM_CFG >= 1'b0) && (RXLPM_CM_CFG <= 1'b1)) RXLPM_CM_CFG_BINARY = RXLPM_CM_CFG; else begin $display("Attribute Syntax Error : The Attribute RXLPM_CM_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_CM_CFG); $finish; end if ((RXLPM_GC_CFG >= 9'b000000000) && (RXLPM_GC_CFG <= 9'b111111111)) RXLPM_GC_CFG_BINARY = RXLPM_GC_CFG; else begin $display("Attribute Syntax Error : The Attribute RXLPM_GC_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111.", RXLPM_GC_CFG); $finish; end if ((RXLPM_GC_CFG2 >= 3'b000) && (RXLPM_GC_CFG2 <= 3'b111)) RXLPM_GC_CFG2_BINARY = RXLPM_GC_CFG2; else begin $display("Attribute Syntax Error : The Attribute RXLPM_GC_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", RXLPM_GC_CFG2); $finish; end if ((RXLPM_HF_CFG >= 14'b00000000000000) && (RXLPM_HF_CFG <= 14'b11111111111111)) RXLPM_HF_CFG_BINARY = RXLPM_HF_CFG; else begin $display("Attribute Syntax Error : The Attribute RXLPM_HF_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 14'b00000000000000 to 14'b11111111111111.", RXLPM_HF_CFG); $finish; end if ((RXLPM_HF_CFG2 >= 5'b00000) && (RXLPM_HF_CFG2 <= 5'b11111)) RXLPM_HF_CFG2_BINARY = RXLPM_HF_CFG2; else begin $display("Attribute Syntax Error : The Attribute RXLPM_HF_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXLPM_HF_CFG2); $finish; end if ((RXLPM_HF_CFG3 >= 4'b0000) && (RXLPM_HF_CFG3 <= 4'b1111)) RXLPM_HF_CFG3_BINARY = RXLPM_HF_CFG3; else begin $display("Attribute Syntax Error : The Attribute RXLPM_HF_CFG3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RXLPM_HF_CFG3); $finish; end if ((RXLPM_HOLD_DURING_EIDLE >= 1'b0) && (RXLPM_HOLD_DURING_EIDLE <= 1'b1)) RXLPM_HOLD_DURING_EIDLE_BINARY = RXLPM_HOLD_DURING_EIDLE; else begin $display("Attribute Syntax Error : The Attribute RXLPM_HOLD_DURING_EIDLE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_HOLD_DURING_EIDLE); $finish; end if ((RXLPM_INCM_CFG >= 1'b0) && (RXLPM_INCM_CFG <= 1'b1)) RXLPM_INCM_CFG_BINARY = RXLPM_INCM_CFG; else begin $display("Attribute Syntax Error : The Attribute RXLPM_INCM_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_INCM_CFG); $finish; end if ((RXLPM_IPCM_CFG >= 1'b0) && (RXLPM_IPCM_CFG <= 1'b1)) RXLPM_IPCM_CFG_BINARY = RXLPM_IPCM_CFG; else begin $display("Attribute Syntax Error : The Attribute RXLPM_IPCM_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXLPM_IPCM_CFG); $finish; end if ((RXLPM_LF_CFG >= 18'b000000000000000000) && (RXLPM_LF_CFG <= 18'b111111111111111111)) RXLPM_LF_CFG_BINARY = RXLPM_LF_CFG; else begin $display("Attribute Syntax Error : The Attribute RXLPM_LF_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 18'b000000000000000000 to 18'b111111111111111111.", RXLPM_LF_CFG); $finish; end if ((RXLPM_LF_CFG2 >= 5'b00000) && (RXLPM_LF_CFG2 <= 5'b11111)) RXLPM_LF_CFG2_BINARY = RXLPM_LF_CFG2; else begin $display("Attribute Syntax Error : The Attribute RXLPM_LF_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXLPM_LF_CFG2); $finish; end if ((RXLPM_OSINT_CFG >= 3'b000) && (RXLPM_OSINT_CFG <= 3'b111)) RXLPM_OSINT_CFG_BINARY = RXLPM_OSINT_CFG; else begin $display("Attribute Syntax Error : The Attribute RXLPM_OSINT_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", RXLPM_OSINT_CFG); $finish; end if ((RXOOB_CFG >= 7'b0000000) && (RXOOB_CFG <= 7'b1111111)) RXOOB_CFG_BINARY = RXOOB_CFG; else begin $display("Attribute Syntax Error : The Attribute RXOOB_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", RXOOB_CFG); $finish; end if ((RXOSCALRESET_TIME >= 5'b00000) && (RXOSCALRESET_TIME <= 5'b11111)) RXOSCALRESET_TIME_BINARY = RXOSCALRESET_TIME; else begin $display("Attribute Syntax Error : The Attribute RXOSCALRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXOSCALRESET_TIME); $finish; end if ((RXOSCALRESET_TIMEOUT >= 5'b00000) && (RXOSCALRESET_TIMEOUT <= 5'b11111)) RXOSCALRESET_TIMEOUT_BINARY = RXOSCALRESET_TIMEOUT; else begin $display("Attribute Syntax Error : The Attribute RXOSCALRESET_TIMEOUT on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXOSCALRESET_TIMEOUT); $finish; end if ((RXPCSRESET_TIME >= 5'b00000) && (RXPCSRESET_TIME <= 5'b11111)) RXPCSRESET_TIME_BINARY = RXPCSRESET_TIME; else begin $display("Attribute Syntax Error : The Attribute RXPCSRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPCSRESET_TIME); $finish; end if ((RXPH_MONITOR_SEL >= 5'b00000) && (RXPH_MONITOR_SEL <= 5'b11111)) RXPH_MONITOR_SEL_BINARY = RXPH_MONITOR_SEL; else begin $display("Attribute Syntax Error : The Attribute RXPH_MONITOR_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPH_MONITOR_SEL); $finish; end if ((RXPI_CFG0 >= 3'b000) && (RXPI_CFG0 <= 3'b111)) RXPI_CFG0_BINARY = RXPI_CFG0; else begin $display("Attribute Syntax Error : The Attribute RXPI_CFG0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", RXPI_CFG0); $finish; end if ((RXPI_CFG1 >= 1'b0) && (RXPI_CFG1 <= 1'b1)) RXPI_CFG1_BINARY = RXPI_CFG1; else begin $display("Attribute Syntax Error : The Attribute RXPI_CFG1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXPI_CFG1); $finish; end if ((RXPI_CFG2 >= 1'b0) && (RXPI_CFG2 <= 1'b1)) RXPI_CFG2_BINARY = RXPI_CFG2; else begin $display("Attribute Syntax Error : The Attribute RXPI_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXPI_CFG2); $finish; end if ((RXPMARESET_TIME >= 5'b00000) && (RXPMARESET_TIME <= 5'b11111)) RXPMARESET_TIME_BINARY = RXPMARESET_TIME; else begin $display("Attribute Syntax Error : The Attribute RXPMARESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", RXPMARESET_TIME); $finish; end if ((RXPRBS_ERR_LOOPBACK >= 1'b0) && (RXPRBS_ERR_LOOPBACK <= 1'b1)) RXPRBS_ERR_LOOPBACK_BINARY = RXPRBS_ERR_LOOPBACK; else begin $display("Attribute Syntax Error : The Attribute RXPRBS_ERR_LOOPBACK on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXPRBS_ERR_LOOPBACK); $finish; end if ((RXSLIDE_AUTO_WAIT >= 0) && (RXSLIDE_AUTO_WAIT <= 15)) RXSLIDE_AUTO_WAIT_BINARY = RXSLIDE_AUTO_WAIT; else begin $display("Attribute Syntax Error : The Attribute RXSLIDE_AUTO_WAIT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 0 to 15.", RXSLIDE_AUTO_WAIT); $finish; end if ((RXSYNC_MULTILANE >= 1'b0) && (RXSYNC_MULTILANE <= 1'b1)) RXSYNC_MULTILANE_BINARY = RXSYNC_MULTILANE; else begin $display("Attribute Syntax Error : The Attribute RXSYNC_MULTILANE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXSYNC_MULTILANE); $finish; end if ((RXSYNC_OVRD >= 1'b0) && (RXSYNC_OVRD <= 1'b1)) RXSYNC_OVRD_BINARY = RXSYNC_OVRD; else begin $display("Attribute Syntax Error : The Attribute RXSYNC_OVRD on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXSYNC_OVRD); $finish; end if ((RXSYNC_SKIP_DA >= 1'b0) && (RXSYNC_SKIP_DA <= 1'b1)) RXSYNC_SKIP_DA_BINARY = RXSYNC_SKIP_DA; else begin $display("Attribute Syntax Error : The Attribute RXSYNC_SKIP_DA on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RXSYNC_SKIP_DA); $finish; end if ((RX_BIAS_CFG >= 16'b0000000000000000) && (RX_BIAS_CFG <= 16'b1111111111111111)) RX_BIAS_CFG_BINARY = RX_BIAS_CFG; else begin $display("Attribute Syntax Error : The Attribute RX_BIAS_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111.", RX_BIAS_CFG); $finish; end if ((RX_BUFFER_CFG >= 6'b000000) && (RX_BUFFER_CFG <= 6'b111111)) RX_BUFFER_CFG_BINARY = RX_BUFFER_CFG; else begin $display("Attribute Syntax Error : The Attribute RX_BUFFER_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RX_BUFFER_CFG); $finish; end if ((RX_CLKMUX_EN >= 1'b0) && (RX_CLKMUX_EN <= 1'b1)) RX_CLKMUX_EN_BINARY = RX_CLKMUX_EN; else begin $display("Attribute Syntax Error : The Attribute RX_CLKMUX_EN on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", RX_CLKMUX_EN); $finish; end if ((RX_CM_SEL >= 2'b00) && (RX_CM_SEL <= 2'b11)) RX_CM_SEL_BINARY = RX_CM_SEL; else begin $display("Attribute Syntax Error : The Attribute RX_CM_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RX_CM_SEL); $finish; end if ((RX_CM_TRIM >= 4'b0000) && (RX_CM_TRIM <= 4'b1111)) RX_CM_TRIM_BINARY = RX_CM_TRIM; else begin $display("Attribute Syntax Error : The Attribute RX_CM_TRIM on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", RX_CM_TRIM); $finish; end if ((RX_DDI_SEL >= 6'b000000) && (RX_DDI_SEL <= 6'b111111)) RX_DDI_SEL_BINARY = RX_DDI_SEL; else begin $display("Attribute Syntax Error : The Attribute RX_DDI_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", RX_DDI_SEL); $finish; end if ((RX_DEBUG_CFG >= 14'b00000000000000) && (RX_DEBUG_CFG <= 14'b11111111111111)) RX_DEBUG_CFG_BINARY = RX_DEBUG_CFG; else begin $display("Attribute Syntax Error : The Attribute RX_DEBUG_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 14'b00000000000000 to 14'b11111111111111.", RX_DEBUG_CFG); $finish; end if ((RX_OS_CFG >= 13'b0000000000000) && (RX_OS_CFG <= 13'b1111111111111)) RX_OS_CFG_BINARY = RX_OS_CFG; else begin $display("Attribute Syntax Error : The Attribute RX_OS_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 13'b0000000000000 to 13'b1111111111111.", RX_OS_CFG); $finish; end if ((SAS_MAX_COM >= 1) && (SAS_MAX_COM <= 127)) SAS_MAX_COM_BINARY = SAS_MAX_COM; else begin $display("Attribute Syntax Error : The Attribute SAS_MAX_COM on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 127.", SAS_MAX_COM); $finish; end if ((SAS_MIN_COM >= 1) && (SAS_MIN_COM <= 63)) SAS_MIN_COM_BINARY = SAS_MIN_COM; else begin $display("Attribute Syntax Error : The Attribute SAS_MIN_COM on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SAS_MIN_COM); $finish; end if ((SATA_BURST_SEQ_LEN >= 4'b0000) && (SATA_BURST_SEQ_LEN <= 4'b1111)) SATA_BURST_SEQ_LEN_BINARY = SATA_BURST_SEQ_LEN; else begin $display("Attribute Syntax Error : The Attribute SATA_BURST_SEQ_LEN on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", SATA_BURST_SEQ_LEN); $finish; end if ((SATA_BURST_VAL >= 3'b000) && (SATA_BURST_VAL <= 3'b111)) SATA_BURST_VAL_BINARY = SATA_BURST_VAL; else begin $display("Attribute Syntax Error : The Attribute SATA_BURST_VAL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", SATA_BURST_VAL); $finish; end if ((SATA_EIDLE_VAL >= 3'b000) && (SATA_EIDLE_VAL <= 3'b111)) SATA_EIDLE_VAL_BINARY = SATA_EIDLE_VAL; else begin $display("Attribute Syntax Error : The Attribute SATA_EIDLE_VAL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", SATA_EIDLE_VAL); $finish; end if ((SATA_MAX_BURST >= 1) && (SATA_MAX_BURST <= 63)) SATA_MAX_BURST_BINARY = SATA_MAX_BURST; else begin $display("Attribute Syntax Error : The Attribute SATA_MAX_BURST on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_BURST); $finish; end if ((SATA_MAX_INIT >= 1) && (SATA_MAX_INIT <= 63)) SATA_MAX_INIT_BINARY = SATA_MAX_INIT; else begin $display("Attribute Syntax Error : The Attribute SATA_MAX_INIT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_INIT); $finish; end if ((SATA_MAX_WAKE >= 1) && (SATA_MAX_WAKE <= 63)) SATA_MAX_WAKE_BINARY = SATA_MAX_WAKE; else begin $display("Attribute Syntax Error : The Attribute SATA_MAX_WAKE on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MAX_WAKE); $finish; end if ((SATA_MIN_BURST >= 1) && (SATA_MIN_BURST <= 61)) SATA_MIN_BURST_BINARY = SATA_MIN_BURST; else begin $display("Attribute Syntax Error : The Attribute SATA_MIN_BURST on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_BURST); $finish; end if ((SATA_MIN_INIT >= 1) && (SATA_MIN_INIT <= 63)) SATA_MIN_INIT_BINARY = SATA_MIN_INIT; else begin $display("Attribute Syntax Error : The Attribute SATA_MIN_INIT on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MIN_INIT); $finish; end if ((SATA_MIN_WAKE >= 1) && (SATA_MIN_WAKE <= 63)) SATA_MIN_WAKE_BINARY = SATA_MIN_WAKE; else begin $display("Attribute Syntax Error : The Attribute SATA_MIN_WAKE on X_GTPE2_CHANNEL instance %m is set to %d. Legal values for this attribute are 1 to 63.", SATA_MIN_WAKE); $finish; end if ((TERM_RCAL_CFG >= 15'b000000000000000) && (TERM_RCAL_CFG <= 15'b111111111111111)) TERM_RCAL_CFG_BINARY = TERM_RCAL_CFG; else begin $display("Attribute Syntax Error : The Attribute TERM_RCAL_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 15'b000000000000000 to 15'b111111111111111.", TERM_RCAL_CFG); $finish; end if ((TERM_RCAL_OVRD >= 3'b000) && (TERM_RCAL_OVRD <= 3'b111)) TERM_RCAL_OVRD_BINARY = TERM_RCAL_OVRD; else begin $display("Attribute Syntax Error : The Attribute TERM_RCAL_OVRD on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TERM_RCAL_OVRD); $finish; end if ((TXOOB_CFG >= 1'b0) && (TXOOB_CFG <= 1'b1)) TXOOB_CFG_BINARY = TXOOB_CFG; else begin $display("Attribute Syntax Error : The Attribute TXOOB_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXOOB_CFG); $finish; end if ((TXPCSRESET_TIME >= 5'b00000) && (TXPCSRESET_TIME <= 5'b11111)) TXPCSRESET_TIME_BINARY = TXPCSRESET_TIME; else begin $display("Attribute Syntax Error : The Attribute TXPCSRESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPCSRESET_TIME); $finish; end if ((TXPH_MONITOR_SEL >= 5'b00000) && (TXPH_MONITOR_SEL <= 5'b11111)) TXPH_MONITOR_SEL_BINARY = TXPH_MONITOR_SEL; else begin $display("Attribute Syntax Error : The Attribute TXPH_MONITOR_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPH_MONITOR_SEL); $finish; end if ((TXPI_CFG0 >= 2'b00) && (TXPI_CFG0 <= 2'b11)) TXPI_CFG0_BINARY = TXPI_CFG0; else begin $display("Attribute Syntax Error : The Attribute TXPI_CFG0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", TXPI_CFG0); $finish; end if ((TXPI_CFG1 >= 2'b00) && (TXPI_CFG1 <= 2'b11)) TXPI_CFG1_BINARY = TXPI_CFG1; else begin $display("Attribute Syntax Error : The Attribute TXPI_CFG1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", TXPI_CFG1); $finish; end if ((TXPI_CFG2 >= 2'b00) && (TXPI_CFG2 <= 2'b11)) TXPI_CFG2_BINARY = TXPI_CFG2; else begin $display("Attribute Syntax Error : The Attribute TXPI_CFG2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", TXPI_CFG2); $finish; end if ((TXPI_CFG3 >= 1'b0) && (TXPI_CFG3 <= 1'b1)) TXPI_CFG3_BINARY = TXPI_CFG3; else begin $display("Attribute Syntax Error : The Attribute TXPI_CFG3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_CFG3); $finish; end if ((TXPI_CFG4 >= 1'b0) && (TXPI_CFG4 <= 1'b1)) TXPI_CFG4_BINARY = TXPI_CFG4; else begin $display("Attribute Syntax Error : The Attribute TXPI_CFG4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_CFG4); $finish; end if ((TXPI_CFG5 >= 3'b000) && (TXPI_CFG5 <= 3'b111)) TXPI_CFG5_BINARY = TXPI_CFG5; else begin $display("Attribute Syntax Error : The Attribute TXPI_CFG5 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TXPI_CFG5); $finish; end if ((TXPI_GREY_SEL >= 1'b0) && (TXPI_GREY_SEL <= 1'b1)) TXPI_GREY_SEL_BINARY = TXPI_GREY_SEL; else begin $display("Attribute Syntax Error : The Attribute TXPI_GREY_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_GREY_SEL); $finish; end if ((TXPI_INVSTROBE_SEL >= 1'b0) && (TXPI_INVSTROBE_SEL <= 1'b1)) TXPI_INVSTROBE_SEL_BINARY = TXPI_INVSTROBE_SEL; else begin $display("Attribute Syntax Error : The Attribute TXPI_INVSTROBE_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXPI_INVSTROBE_SEL); $finish; end if ((TXPI_PPM_CFG >= 8'b00000000) && (TXPI_PPM_CFG <= 8'b11111111)) TXPI_PPM_CFG_BINARY = TXPI_PPM_CFG; else begin $display("Attribute Syntax Error : The Attribute TXPI_PPM_CFG on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 8'b00000000 to 8'b11111111.", TXPI_PPM_CFG); $finish; end if ((TXPI_SYNFREQ_PPM >= 3'b000) && (TXPI_SYNFREQ_PPM <= 3'b111)) TXPI_SYNFREQ_PPM_BINARY = TXPI_SYNFREQ_PPM; else begin $display("Attribute Syntax Error : The Attribute TXPI_SYNFREQ_PPM on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TXPI_SYNFREQ_PPM); $finish; end if ((TXPMARESET_TIME >= 5'b00000) && (TXPMARESET_TIME <= 5'b11111)) TXPMARESET_TIME_BINARY = TXPMARESET_TIME; else begin $display("Attribute Syntax Error : The Attribute TXPMARESET_TIME on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111.", TXPMARESET_TIME); $finish; end if ((TXSYNC_MULTILANE >= 1'b0) && (TXSYNC_MULTILANE <= 1'b1)) TXSYNC_MULTILANE_BINARY = TXSYNC_MULTILANE; else begin $display("Attribute Syntax Error : The Attribute TXSYNC_MULTILANE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXSYNC_MULTILANE); $finish; end if ((TXSYNC_OVRD >= 1'b0) && (TXSYNC_OVRD <= 1'b1)) TXSYNC_OVRD_BINARY = TXSYNC_OVRD; else begin $display("Attribute Syntax Error : The Attribute TXSYNC_OVRD on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXSYNC_OVRD); $finish; end if ((TXSYNC_SKIP_DA >= 1'b0) && (TXSYNC_SKIP_DA <= 1'b1)) TXSYNC_SKIP_DA_BINARY = TXSYNC_SKIP_DA; else begin $display("Attribute Syntax Error : The Attribute TXSYNC_SKIP_DA on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TXSYNC_SKIP_DA); $finish; end if ((TX_CLKMUX_EN >= 1'b0) && (TX_CLKMUX_EN <= 1'b1)) TX_CLKMUX_EN_BINARY = TX_CLKMUX_EN; else begin $display("Attribute Syntax Error : The Attribute TX_CLKMUX_EN on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_CLKMUX_EN); $finish; end if ((TX_DEEMPH0 >= 6'b000000) && (TX_DEEMPH0 <= 6'b111111)) TX_DEEMPH0_BINARY = TX_DEEMPH0; else begin $display("Attribute Syntax Error : The Attribute TX_DEEMPH0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", TX_DEEMPH0); $finish; end if ((TX_DEEMPH1 >= 6'b000000) && (TX_DEEMPH1 <= 6'b111111)) TX_DEEMPH1_BINARY = TX_DEEMPH1; else begin $display("Attribute Syntax Error : The Attribute TX_DEEMPH1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", TX_DEEMPH1); $finish; end if ((TX_EIDLE_ASSERT_DELAY >= 3'b000) && (TX_EIDLE_ASSERT_DELAY <= 3'b111)) TX_EIDLE_ASSERT_DELAY_BINARY = TX_EIDLE_ASSERT_DELAY; else begin $display("Attribute Syntax Error : The Attribute TX_EIDLE_ASSERT_DELAY on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_EIDLE_ASSERT_DELAY); $finish; end if ((TX_EIDLE_DEASSERT_DELAY >= 3'b000) && (TX_EIDLE_DEASSERT_DELAY <= 3'b111)) TX_EIDLE_DEASSERT_DELAY_BINARY = TX_EIDLE_DEASSERT_DELAY; else begin $display("Attribute Syntax Error : The Attribute TX_EIDLE_DEASSERT_DELAY on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_EIDLE_DEASSERT_DELAY); $finish; end if ((TX_MAINCURSOR_SEL >= 1'b0) && (TX_MAINCURSOR_SEL <= 1'b1)) TX_MAINCURSOR_SEL_BINARY = TX_MAINCURSOR_SEL; else begin $display("Attribute Syntax Error : The Attribute TX_MAINCURSOR_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_MAINCURSOR_SEL); $finish; end if ((TX_MARGIN_FULL_0 >= 7'b0000000) && (TX_MARGIN_FULL_0 <= 7'b1111111)) TX_MARGIN_FULL_0_BINARY = TX_MARGIN_FULL_0; else begin $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_0); $finish; end if ((TX_MARGIN_FULL_1 >= 7'b0000000) && (TX_MARGIN_FULL_1 <= 7'b1111111)) TX_MARGIN_FULL_1_BINARY = TX_MARGIN_FULL_1; else begin $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_1); $finish; end if ((TX_MARGIN_FULL_2 >= 7'b0000000) && (TX_MARGIN_FULL_2 <= 7'b1111111)) TX_MARGIN_FULL_2_BINARY = TX_MARGIN_FULL_2; else begin $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_2); $finish; end if ((TX_MARGIN_FULL_3 >= 7'b0000000) && (TX_MARGIN_FULL_3 <= 7'b1111111)) TX_MARGIN_FULL_3_BINARY = TX_MARGIN_FULL_3; else begin $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_3); $finish; end if ((TX_MARGIN_FULL_4 >= 7'b0000000) && (TX_MARGIN_FULL_4 <= 7'b1111111)) TX_MARGIN_FULL_4_BINARY = TX_MARGIN_FULL_4; else begin $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_FULL_4); $finish; end if ((TX_MARGIN_LOW_0 >= 7'b0000000) && (TX_MARGIN_LOW_0 <= 7'b1111111)) TX_MARGIN_LOW_0_BINARY = TX_MARGIN_LOW_0; else begin $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_0 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_0); $finish; end if ((TX_MARGIN_LOW_1 >= 7'b0000000) && (TX_MARGIN_LOW_1 <= 7'b1111111)) TX_MARGIN_LOW_1_BINARY = TX_MARGIN_LOW_1; else begin $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_1 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_1); $finish; end if ((TX_MARGIN_LOW_2 >= 7'b0000000) && (TX_MARGIN_LOW_2 <= 7'b1111111)) TX_MARGIN_LOW_2_BINARY = TX_MARGIN_LOW_2; else begin $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_2 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_2); $finish; end if ((TX_MARGIN_LOW_3 >= 7'b0000000) && (TX_MARGIN_LOW_3 <= 7'b1111111)) TX_MARGIN_LOW_3_BINARY = TX_MARGIN_LOW_3; else begin $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_3 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_3); $finish; end if ((TX_MARGIN_LOW_4 >= 7'b0000000) && (TX_MARGIN_LOW_4 <= 7'b1111111)) TX_MARGIN_LOW_4_BINARY = TX_MARGIN_LOW_4; else begin $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_4 on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111.", TX_MARGIN_LOW_4); $finish; end if ((TX_PREDRIVER_MODE >= 1'b0) && (TX_PREDRIVER_MODE <= 1'b1)) TX_PREDRIVER_MODE_BINARY = TX_PREDRIVER_MODE; else begin $display("Attribute Syntax Error : The Attribute TX_PREDRIVER_MODE on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", TX_PREDRIVER_MODE); $finish; end if ((TX_RXDETECT_REF >= 3'b000) && (TX_RXDETECT_REF <= 3'b111)) TX_RXDETECT_REF_BINARY = TX_RXDETECT_REF; else begin $display("Attribute Syntax Error : The Attribute TX_RXDETECT_REF on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", TX_RXDETECT_REF); $finish; end if ((UCODEER_CLR >= 1'b0) && (UCODEER_CLR <= 1'b1)) UCODEER_CLR_BINARY = UCODEER_CLR; else begin $display("Attribute Syntax Error : The Attribute UCODEER_CLR on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", UCODEER_CLR); $finish; end if ((USE_PCS_CLK_PHASE_SEL >= 1'b0) && (USE_PCS_CLK_PHASE_SEL <= 1'b1)) USE_PCS_CLK_PHASE_SEL_BINARY = USE_PCS_CLK_PHASE_SEL; else begin $display("Attribute Syntax Error : The Attribute USE_PCS_CLK_PHASE_SEL on X_GTPE2_CHANNEL instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", USE_PCS_CLK_PHASE_SEL); $finish; end end wire [14:0] delay_DMONITOROUT; wire [15:0] delay_DRPDO; wire [15:0] delay_PCSRSVDOUT; wire [1:0] delay_RXCLKCORCNT; wire [1:0] delay_RXDATAVALID; wire [1:0] delay_RXSTARTOFSEQ; wire [1:0] delay_TXBUFSTATUS; wire [2:0] delay_RXBUFSTATUS; wire [2:0] delay_RXHEADER; wire [2:0] delay_RXSTATUS; wire [31:0] delay_RXDATA; wire [3:0] delay_RXCHARISCOMMA; wire [3:0] delay_RXCHARISK; wire [3:0] delay_RXCHBONDO; wire [3:0] delay_RXDISPERR; wire [3:0] delay_RXNOTINTABLE; wire [4:0] delay_RXPHMONITOR; wire [4:0] delay_RXPHSLIPMONITOR; wire delay_DRPRDY; wire delay_EYESCANDATAERROR; wire delay_GTPTXN; wire delay_GTPTXP; wire delay_PHYSTATUS; wire delay_PMARSVDOUT0; wire delay_PMARSVDOUT1; wire delay_RXBYTEISALIGNED; wire delay_RXBYTEREALIGN; wire delay_RXCDRLOCK; wire delay_RXCHANBONDSEQ; wire delay_RXCHANISALIGNED; wire delay_RXCHANREALIGN; wire delay_RXCOMINITDET; wire delay_RXCOMMADET; wire delay_RXCOMSASDET; wire delay_RXCOMWAKEDET; wire delay_RXDLYSRESETDONE; wire delay_RXELECIDLE; wire delay_RXHEADERVALID; wire delay_RXOSINTDONE; wire delay_RXOSINTSTARTED; wire delay_RXOSINTSTROBEDONE; wire delay_RXOSINTSTROBESTARTED; wire delay_RXOUTCLK; wire delay_RXOUTCLKFABRIC; wire delay_RXOUTCLKPCS; wire delay_RXPHALIGNDONE; wire delay_RXPMARESETDONE; wire delay_RXPRBSERR; wire delay_RXRATEDONE; wire delay_RXRESETDONE; wire delay_RXSYNCDONE; wire delay_RXSYNCOUT; wire delay_RXVALID; wire delay_TXCOMFINISH; wire delay_TXDLYSRESETDONE; wire delay_TXGEARBOXREADY; wire delay_TXOUTCLK; wire delay_TXOUTCLKFABRIC; wire delay_TXOUTCLKPCS; wire delay_TXPHALIGNDONE; wire delay_TXPHINITDONE; wire delay_TXPMARESETDONE; wire delay_TXRATEDONE; wire delay_TXRESETDONE; wire delay_TXSYNCDONE; wire delay_TXSYNCOUT; wire [13:0] delay_RXADAPTSELTEST; wire [15:0] delay_DRPDI; wire [15:0] delay_GTRSVD; wire [15:0] delay_PCSRSVDIN; wire [19:0] delay_TSTIN; wire [1:0] delay_RXELECIDLEMODE; wire [1:0] delay_RXPD; wire [1:0] delay_RXSYSCLKSEL; wire [1:0] delay_TXPD; wire [1:0] delay_TXSYSCLKSEL; wire [2:0] delay_LOOPBACK; wire [2:0] delay_RXCHBONDLEVEL; wire [2:0] delay_RXOUTCLKSEL; wire [2:0] delay_RXPRBSSEL; wire [2:0] delay_RXRATE; wire [2:0] delay_TXBUFDIFFCTRL; wire [2:0] delay_TXHEADER; wire [2:0] delay_TXMARGIN; wire [2:0] delay_TXOUTCLKSEL; wire [2:0] delay_TXPRBSSEL; wire [2:0] delay_TXRATE; wire [31:0] delay_TXDATA; wire [3:0] delay_RXCHBONDI; wire [3:0] delay_RXOSINTCFG; wire [3:0] delay_RXOSINTID0; wire [3:0] delay_TX8B10BBYPASS; wire [3:0] delay_TXCHARDISPMODE; wire [3:0] delay_TXCHARDISPVAL; wire [3:0] delay_TXCHARISK; wire [3:0] delay_TXDIFFCTRL; wire [4:0] delay_TXPIPPMSTEPSIZE; wire [4:0] delay_TXPOSTCURSOR; wire [4:0] delay_TXPRECURSOR; wire [6:0] delay_TXMAINCURSOR; wire [6:0] delay_TXSEQUENCE; wire [8:0] delay_DRPADDR; wire delay_CFGRESET; wire delay_CLKRSVD0; wire delay_CLKRSVD1; wire delay_DMONFIFORESET; wire delay_DMONITORCLK; wire delay_DRPCLK; wire delay_DRPEN; wire delay_DRPWE; wire delay_EYESCANMODE; wire delay_EYESCANRESET; wire delay_EYESCANTRIGGER; wire delay_GTPRXN; wire delay_GTPRXP; wire delay_GTRESETSEL; wire delay_GTRXRESET; wire delay_GTTXRESET; wire delay_PLL0CLK; wire delay_PLL0REFCLK; wire delay_PLL1CLK; wire delay_PLL1REFCLK; wire delay_PMARSVDIN0; wire delay_PMARSVDIN1; wire delay_PMARSVDIN2; wire delay_PMARSVDIN3; wire delay_PMARSVDIN4; wire delay_RESETOVRD; wire delay_RX8B10BEN; wire delay_RXBUFRESET; wire delay_RXCDRFREQRESET; wire delay_RXCDRHOLD; wire delay_RXCDROVRDEN; wire delay_RXCDRRESET; wire delay_RXCDRRESETRSV; wire delay_RXCHBONDEN; wire delay_RXCHBONDMASTER; wire delay_RXCHBONDSLAVE; wire delay_RXCOMMADETEN; wire delay_RXDDIEN; wire delay_RXDFEXYDEN; wire delay_RXDLYBYPASS; wire delay_RXDLYEN; wire delay_RXDLYOVRDEN; wire delay_RXDLYSRESET; wire delay_RXGEARBOXSLIP; wire delay_RXLPMHFHOLD; wire delay_RXLPMHFOVRDEN; wire delay_RXLPMLFHOLD; wire delay_RXLPMLFOVRDEN; wire delay_RXLPMOSINTNTRLEN; wire delay_RXLPMRESET; wire delay_RXMCOMMAALIGNEN; wire delay_RXOOBRESET; wire delay_RXOSCALRESET; wire delay_RXOSHOLD; wire delay_RXOSINTEN; wire delay_RXOSINTHOLD; wire delay_RXOSINTNTRLEN; wire delay_RXOSINTOVRDEN; wire delay_RXOSINTPD; wire delay_RXOSINTSTROBE; wire delay_RXOSINTTESTOVRDEN; wire delay_RXOSOVRDEN; wire delay_RXPCOMMAALIGNEN; wire delay_RXPCSRESET; wire delay_RXPHALIGN; wire delay_RXPHALIGNEN; wire delay_RXPHDLYPD; wire delay_RXPHDLYRESET; wire delay_RXPHOVRDEN; wire delay_RXPMARESET; wire delay_RXPOLARITY; wire delay_RXPRBSCNTRESET; wire delay_RXRATEMODE; wire delay_RXSLIDE; wire delay_RXSYNCALLIN; wire delay_RXSYNCIN; wire delay_RXSYNCMODE; wire delay_RXUSERRDY; wire delay_RXUSRCLK2; wire delay_RXUSRCLK; wire delay_SETERRSTATUS; wire delay_SIGVALIDCLK; wire delay_TX8B10BEN; wire delay_TXCOMINIT; wire delay_TXCOMSAS; wire delay_TXCOMWAKE; wire delay_TXDEEMPH; wire delay_TXDETECTRX; wire delay_TXDIFFPD; wire delay_TXDLYBYPASS; wire delay_TXDLYEN; wire delay_TXDLYHOLD; wire delay_TXDLYOVRDEN; wire delay_TXDLYSRESET; wire delay_TXDLYUPDOWN; wire delay_TXELECIDLE; wire delay_TXINHIBIT; wire delay_TXPCSRESET; wire delay_TXPDELECIDLEMODE; wire delay_TXPHALIGN; wire delay_TXPHALIGNEN; wire delay_TXPHDLYPD; wire delay_TXPHDLYRESET; wire delay_TXPHDLYTSTCLK; wire delay_TXPHINIT; wire delay_TXPHOVRDEN; wire delay_TXPIPPMEN; wire delay_TXPIPPMOVRDEN; wire delay_TXPIPPMPD; wire delay_TXPIPPMSEL; wire delay_TXPISOPD; wire delay_TXPMARESET; wire delay_TXPOLARITY; wire delay_TXPOSTCURSORINV; wire delay_TXPRBSFORCEERR; wire delay_TXPRECURSORINV; wire delay_TXRATEMODE; wire delay_TXSTARTSEQ; wire delay_TXSWING; wire delay_TXSYNCALLIN; wire delay_TXSYNCIN; wire delay_TXSYNCMODE; wire delay_TXUSERRDY; wire delay_TXUSRCLK2; wire delay_TXUSRCLK; //drp monitor reg drpen_r1 = 1'b0; reg drpen_r2 = 1'b0; reg drpwe_r1 = 1'b0; reg drpwe_r2 = 1'b0; reg [1:0] sfsm = 2'b01; localparam FSM_IDLE = 2'b01; localparam FSM_WAIT = 2'b10; always @(posedge DRPCLK) begin // pipeline the DRPEN and DRPWE drpen_r1 <= DRPEN; drpwe_r1 <= DRPWE; drpen_r2 <= drpen_r1; drpwe_r2 <= drpwe_r1; // Check - if DRPEN or DRPWE is more than 1 DCLK if ((drpen_r1 == 1'b1) && (drpen_r2 == 1'b1)) begin $display("DRC Error : DRPEN is high for more than 1 DRPCLK on %m instance"); $finish; end if ((drpwe_r1 == 1'b1) && (drpwe_r2 == 1'b1)) begin $display("DRC Error : DRPWE is high for more than 1 DRPCLK on %m instance"); $finish; end //After the 1st DRPEN pulse, check the DRPEN and DRPRDY. case (sfsm) FSM_IDLE: begin if(DRPEN == 1'b1) sfsm <= FSM_WAIT; end FSM_WAIT: begin // After the 1st DRPEN, 4 cases can happen // DRPEN DRPRDY NEXT STATE // 0 0 FSM_WAIT - wait for DRPRDY // 0 1 FSM_IDLE - normal operation // 1 0 FSM_WAIT - display error and wait for DRPRDY // 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle. //Add the check for another DPREN pulse if(DRPEN === 1'b1 && delay_DRPRDY === 1'b0) begin $display("DRC Error : DRPEN is enabled before DRPRDY returns on %m instance"); $finish; end //Add the check for another DRPWE pulse if ((DRPWE === 1'b1) && (DRPEN === 1'b0)) begin $display("DRC Error : DRPWE is enabled before DRPRDY returns on %m instance"); $finish; end if ((delay_DRPRDY === 1'b1) && (DRPEN === 1'b0)) begin sfsm <= FSM_IDLE; end if ((delay_DRPRDY === 1'b1)&& (DRPEN === 1'b1)) begin sfsm <= FSM_WAIT; end end default: begin $display("DRC Error : Default state in DRP FSM."); $finish; end endcase end // always @ (posedge DRPCLK) //end drp monitor reg [0:0] IS_CLKRSVD0_INVERTED_REG = IS_CLKRSVD0_INVERTED; reg [0:0] IS_CLKRSVD1_INVERTED_REG = IS_CLKRSVD1_INVERTED; reg [0:0] IS_DMONITORCLK_INVERTED_REG = IS_DMONITORCLK_INVERTED; reg [0:0] IS_DRPCLK_INVERTED_REG = IS_DRPCLK_INVERTED; reg [0:0] IS_RXUSRCLK2_INVERTED_REG = IS_RXUSRCLK2_INVERTED; reg [0:0] IS_RXUSRCLK_INVERTED_REG = IS_RXUSRCLK_INVERTED; reg [0:0] IS_SIGVALIDCLK_INVERTED_REG = IS_SIGVALIDCLK_INVERTED; reg [0:0] IS_TXPHDLYTSTCLK_INVERTED_REG = IS_TXPHDLYTSTCLK_INVERTED; reg [0:0] IS_TXUSRCLK2_INVERTED_REG = IS_TXUSRCLK2_INVERTED; reg [0:0] IS_TXUSRCLK_INVERTED_REG = IS_TXUSRCLK_INVERTED; assign #(OUTCLK_DELAY) RXOUTCLK = delay_RXOUTCLK; assign #(OUTCLK_DELAY) TXOUTCLK = delay_TXOUTCLK; assign #(out_delay) DMONITOROUT = delay_DMONITOROUT; assign #(out_delay) DRPDO = delay_DRPDO; assign #(out_delay) DRPRDY = delay_DRPRDY; assign #(out_delay) EYESCANDATAERROR = delay_EYESCANDATAERROR; assign #(out_delay) GTPTXN = delay_GTPTXN; assign #(out_delay) GTPTXP = delay_GTPTXP; assign #(out_delay) PCSRSVDOUT = delay_PCSRSVDOUT; assign #(out_delay) PHYSTATUS = delay_PHYSTATUS; assign #(out_delay) PMARSVDOUT0 = delay_PMARSVDOUT0; assign #(out_delay) PMARSVDOUT1 = delay_PMARSVDOUT1; assign #(out_delay) RXBUFSTATUS = delay_RXBUFSTATUS; assign #(out_delay) RXBYTEISALIGNED = delay_RXBYTEISALIGNED; assign #(out_delay) RXBYTEREALIGN = delay_RXBYTEREALIGN; assign #(out_delay) RXCDRLOCK = delay_RXCDRLOCK; assign #(out_delay) RXCHANBONDSEQ = delay_RXCHANBONDSEQ; assign #(out_delay) RXCHANISALIGNED = delay_RXCHANISALIGNED; assign #(out_delay) RXCHANREALIGN = delay_RXCHANREALIGN; assign #(out_delay) RXCHARISCOMMA = delay_RXCHARISCOMMA; assign #(out_delay) RXCHARISK = delay_RXCHARISK; assign #(out_delay) RXCHBONDO = delay_RXCHBONDO; assign #(out_delay) RXCLKCORCNT = delay_RXCLKCORCNT; assign #(out_delay) RXCOMINITDET = delay_RXCOMINITDET; assign #(out_delay) RXCOMMADET = delay_RXCOMMADET; assign #(out_delay) RXCOMSASDET = delay_RXCOMSASDET; assign #(out_delay) RXCOMWAKEDET = delay_RXCOMWAKEDET; assign #(out_delay) RXDATA = delay_RXDATA; assign #(out_delay) RXDATAVALID = delay_RXDATAVALID; assign #(out_delay) RXDISPERR = delay_RXDISPERR; assign #(out_delay) RXDLYSRESETDONE = delay_RXDLYSRESETDONE; assign #(out_delay) RXELECIDLE = delay_RXELECIDLE; assign #(out_delay) RXHEADER = delay_RXHEADER; assign #(out_delay) RXHEADERVALID = delay_RXHEADERVALID; assign #(out_delay) RXNOTINTABLE = delay_RXNOTINTABLE; assign #(out_delay) RXOSINTDONE = delay_RXOSINTDONE; assign #(out_delay) RXOSINTSTARTED = delay_RXOSINTSTARTED; assign #(out_delay) RXOSINTSTROBEDONE = delay_RXOSINTSTROBEDONE; assign #(out_delay) RXOSINTSTROBESTARTED = delay_RXOSINTSTROBESTARTED; assign #(out_delay) RXOUTCLKFABRIC = delay_RXOUTCLKFABRIC; assign #(out_delay) RXOUTCLKPCS = delay_RXOUTCLKPCS; assign #(out_delay) RXPHALIGNDONE = delay_RXPHALIGNDONE; assign #(out_delay) RXPHMONITOR = delay_RXPHMONITOR; assign #(out_delay) RXPHSLIPMONITOR = delay_RXPHSLIPMONITOR; assign #(out_delay) RXPMARESETDONE = delay_RXPMARESETDONE; assign #(out_delay) RXPRBSERR = delay_RXPRBSERR; assign #(out_delay) RXRATEDONE = delay_RXRATEDONE; assign #(out_delay) RXRESETDONE = delay_RXRESETDONE; assign #(out_delay) RXSTARTOFSEQ = delay_RXSTARTOFSEQ; assign #(out_delay) RXSTATUS = delay_RXSTATUS; assign #(out_delay) RXSYNCDONE = delay_RXSYNCDONE; assign #(out_delay) RXSYNCOUT = delay_RXSYNCOUT; assign #(out_delay) RXVALID = delay_RXVALID; assign #(out_delay) TXBUFSTATUS = delay_TXBUFSTATUS; assign #(out_delay) TXCOMFINISH = delay_TXCOMFINISH; assign #(out_delay) TXDLYSRESETDONE = delay_TXDLYSRESETDONE; assign #(out_delay) TXGEARBOXREADY = delay_TXGEARBOXREADY; assign #(out_delay) TXOUTCLKFABRIC = delay_TXOUTCLKFABRIC; assign #(out_delay) TXOUTCLKPCS = delay_TXOUTCLKPCS; assign #(out_delay) TXPHALIGNDONE = delay_TXPHALIGNDONE; assign #(out_delay) TXPHINITDONE = delay_TXPHINITDONE; assign #(out_delay) TXPMARESETDONE = delay_TXPMARESETDONE; assign #(out_delay) TXRATEDONE = delay_TXRATEDONE; assign #(out_delay) TXRESETDONE = delay_TXRESETDONE; assign #(out_delay) TXSYNCDONE = delay_TXSYNCDONE; assign #(out_delay) TXSYNCOUT = delay_TXSYNCOUT; `ifndef XIL_TIMING // unisim assign #(INCLK_DELAY) delay_CLKRSVD0 = CLKRSVD0 ^ IS_CLKRSVD0_INVERTED_REG; assign #(INCLK_DELAY) delay_CLKRSVD1 = CLKRSVD1 ^ IS_CLKRSVD1_INVERTED_REG; assign #(INCLK_DELAY) delay_DMONITORCLK = DMONITORCLK ^ IS_DMONITORCLK_INVERTED_REG; assign #(INCLK_DELAY) delay_DRPCLK = DRPCLK ^ IS_DRPCLK_INVERTED_REG; assign #(INCLK_DELAY) delay_PLL0CLK = PLL0CLK; assign #(INCLK_DELAY) delay_PLL1CLK = PLL1CLK; assign #(INCLK_DELAY) delay_RXUSRCLK = RXUSRCLK ^ IS_RXUSRCLK2_INVERTED_REG; assign #(INCLK_DELAY) delay_RXUSRCLK2 = RXUSRCLK2 ^ IS_RXUSRCLK2_INVERTED_REG; assign #(INCLK_DELAY) delay_SIGVALIDCLK = SIGVALIDCLK^ IS_SIGVALIDCLK_INVERTED_REG; assign #(INCLK_DELAY) delay_TXPHDLYTSTCLK = TXPHDLYTSTCLK ^ IS_TXPHDLYTSTCLK_INVERTED_REG; assign #(INCLK_DELAY) delay_TXUSRCLK = TXUSRCLK; assign #(INCLK_DELAY) delay_TXUSRCLK2 = TXUSRCLK2; assign #(in_delay) delay_CFGRESET = CFGRESET; assign #(in_delay) delay_DMONFIFORESET = DMONFIFORESET; assign #(in_delay) delay_DRPADDR = DRPADDR; assign #(in_delay) delay_DRPDI = DRPDI; assign #(in_delay) delay_DRPEN = DRPEN; assign #(in_delay) delay_DRPWE = DRPWE; assign #(in_delay) delay_EYESCANMODE = EYESCANMODE; assign #(in_delay) delay_EYESCANRESET = EYESCANRESET; assign #(in_delay) delay_EYESCANTRIGGER = EYESCANTRIGGER; assign #(in_delay) delay_GTPRXN = GTPRXN; assign #(in_delay) delay_GTPRXP = GTPRXP; assign #(in_delay) delay_GTRESETSEL = GTRESETSEL; assign #(in_delay) delay_GTRSVD = GTRSVD; assign #(in_delay) delay_GTRXRESET = GTRXRESET; assign #(in_delay) delay_GTTXRESET = GTTXRESET; assign #(in_delay) delay_LOOPBACK = LOOPBACK; assign #(in_delay) delay_PCSRSVDIN = PCSRSVDIN; assign #(in_delay) delay_PLL0REFCLK = PLL0REFCLK; assign #(in_delay) delay_PLL1REFCLK = PLL1REFCLK; assign #(in_delay) delay_PMARSVDIN0 = PMARSVDIN0; assign #(in_delay) delay_PMARSVDIN1 = PMARSVDIN1; assign #(in_delay) delay_PMARSVDIN2 = PMARSVDIN2; assign #(in_delay) delay_PMARSVDIN3 = PMARSVDIN3; assign #(in_delay) delay_PMARSVDIN4 = PMARSVDIN4; assign #(in_delay) delay_RESETOVRD = RESETOVRD; assign #(in_delay) delay_RX8B10BEN = RX8B10BEN; assign #(in_delay) delay_RXADAPTSELTEST = RXADAPTSELTEST; assign #(in_delay) delay_RXBUFRESET = RXBUFRESET; assign #(in_delay) delay_RXCDRFREQRESET = RXCDRFREQRESET; assign #(in_delay) delay_RXCDRHOLD = RXCDRHOLD; assign #(in_delay) delay_RXCDROVRDEN = RXCDROVRDEN; assign #(in_delay) delay_RXCDRRESET = RXCDRRESET; assign #(in_delay) delay_RXCDRRESETRSV = RXCDRRESETRSV; assign #(in_delay) delay_RXCHBONDEN = RXCHBONDEN; assign #(in_delay) delay_RXCHBONDI = RXCHBONDI; assign #(in_delay) delay_RXCHBONDLEVEL = RXCHBONDLEVEL; assign #(in_delay) delay_RXCHBONDMASTER = RXCHBONDMASTER; assign #(in_delay) delay_RXCHBONDSLAVE = RXCHBONDSLAVE; assign #(in_delay) delay_RXCOMMADETEN = RXCOMMADETEN; assign #(in_delay) delay_RXDDIEN = RXDDIEN; assign #(in_delay) delay_RXDFEXYDEN = RXDFEXYDEN; assign #(in_delay) delay_RXDLYBYPASS = RXDLYBYPASS; assign #(in_delay) delay_RXDLYEN = RXDLYEN; assign #(in_delay) delay_RXDLYOVRDEN = RXDLYOVRDEN; assign #(in_delay) delay_RXDLYSRESET = RXDLYSRESET; assign #(in_delay) delay_RXELECIDLEMODE = RXELECIDLEMODE; assign #(in_delay) delay_RXGEARBOXSLIP = RXGEARBOXSLIP; assign #(in_delay) delay_RXLPMHFHOLD = RXLPMHFHOLD; assign #(in_delay) delay_RXLPMHFOVRDEN = RXLPMHFOVRDEN; assign #(in_delay) delay_RXLPMLFHOLD = RXLPMLFHOLD; assign #(in_delay) delay_RXLPMLFOVRDEN = RXLPMLFOVRDEN; assign #(in_delay) delay_RXLPMOSINTNTRLEN = RXLPMOSINTNTRLEN; assign #(in_delay) delay_RXLPMRESET = RXLPMRESET; assign #(in_delay) delay_RXMCOMMAALIGNEN = RXMCOMMAALIGNEN; assign #(in_delay) delay_RXOOBRESET = RXOOBRESET; assign #(in_delay) delay_RXOSCALRESET = RXOSCALRESET; assign #(in_delay) delay_RXOSHOLD = RXOSHOLD; assign #(in_delay) delay_RXOSINTCFG = RXOSINTCFG; assign #(in_delay) delay_RXOSINTEN = RXOSINTEN; assign #(in_delay) delay_RXOSINTHOLD = RXOSINTHOLD; assign #(in_delay) delay_RXOSINTID0 = RXOSINTID0; assign #(in_delay) delay_RXOSINTNTRLEN = RXOSINTNTRLEN; assign #(in_delay) delay_RXOSINTOVRDEN = RXOSINTOVRDEN; assign #(in_delay) delay_RXOSINTPD = RXOSINTPD; assign #(in_delay) delay_RXOSINTSTROBE = RXOSINTSTROBE; assign #(in_delay) delay_RXOSINTTESTOVRDEN = RXOSINTTESTOVRDEN; assign #(in_delay) delay_RXOSOVRDEN = RXOSOVRDEN; assign #(in_delay) delay_RXOUTCLKSEL = RXOUTCLKSEL; assign #(in_delay) delay_RXPCOMMAALIGNEN = RXPCOMMAALIGNEN; assign #(in_delay) delay_RXPCSRESET = RXPCSRESET; assign #(in_delay) delay_RXPD = RXPD; assign #(in_delay) delay_RXPHALIGN = RXPHALIGN; assign #(in_delay) delay_RXPHALIGNEN = RXPHALIGNEN; assign #(in_delay) delay_RXPHDLYPD = RXPHDLYPD; assign #(in_delay) delay_RXPHDLYRESET = RXPHDLYRESET; assign #(in_delay) delay_RXPHOVRDEN = RXPHOVRDEN; assign #(in_delay) delay_RXPMARESET = RXPMARESET; assign #(in_delay) delay_RXPOLARITY = RXPOLARITY; assign #(in_delay) delay_RXPRBSCNTRESET = RXPRBSCNTRESET; assign #(in_delay) delay_RXPRBSSEL = RXPRBSSEL; assign #(in_delay) delay_RXRATE = RXRATE; assign #(in_delay) delay_RXRATEMODE = RXRATEMODE; assign #(in_delay) delay_RXSLIDE = RXSLIDE; assign #(in_delay) delay_RXSYNCALLIN = RXSYNCALLIN; assign #(in_delay) delay_RXSYNCIN = RXSYNCIN; assign #(in_delay) delay_RXSYNCMODE = RXSYNCMODE; assign #(in_delay) delay_RXSYSCLKSEL = RXSYSCLKSEL; assign #(in_delay) delay_RXUSERRDY = RXUSERRDY; assign #(in_delay) delay_SETERRSTATUS = SETERRSTATUS; assign #(in_delay) delay_TSTIN = TSTIN; assign #(in_delay) delay_TX8B10BBYPASS = TX8B10BBYPASS; assign #(in_delay) delay_TX8B10BEN = TX8B10BEN; assign #(in_delay) delay_TXBUFDIFFCTRL = TXBUFDIFFCTRL; assign #(in_delay) delay_TXCHARDISPMODE = TXCHARDISPMODE; assign #(in_delay) delay_TXCHARDISPVAL = TXCHARDISPVAL; assign #(in_delay) delay_TXCHARISK = TXCHARISK; assign #(in_delay) delay_TXCOMINIT = TXCOMINIT; assign #(in_delay) delay_TXCOMSAS = TXCOMSAS; assign #(in_delay) delay_TXCOMWAKE = TXCOMWAKE; assign #(in_delay) delay_TXDATA = TXDATA; assign #(in_delay) delay_TXDEEMPH = TXDEEMPH; assign #(in_delay) delay_TXDETECTRX = TXDETECTRX; assign #(in_delay) delay_TXDIFFCTRL = TXDIFFCTRL; assign #(in_delay) delay_TXDIFFPD = TXDIFFPD; assign #(in_delay) delay_TXDLYBYPASS = TXDLYBYPASS; assign #(in_delay) delay_TXDLYEN = TXDLYEN; assign #(in_delay) delay_TXDLYHOLD = TXDLYHOLD; assign #(in_delay) delay_TXDLYOVRDEN = TXDLYOVRDEN; assign #(in_delay) delay_TXDLYSRESET = TXDLYSRESET; assign #(in_delay) delay_TXDLYUPDOWN = TXDLYUPDOWN; assign #(in_delay) delay_TXELECIDLE = TXELECIDLE; assign #(in_delay) delay_TXHEADER = TXHEADER; assign #(in_delay) delay_TXINHIBIT = TXINHIBIT; assign #(in_delay) delay_TXMAINCURSOR = TXMAINCURSOR; assign #(in_delay) delay_TXMARGIN = TXMARGIN; assign #(in_delay) delay_TXOUTCLKSEL = TXOUTCLKSEL; assign #(in_delay) delay_TXPCSRESET = TXPCSRESET; assign #(in_delay) delay_TXPD = TXPD; assign #(in_delay) delay_TXPDELECIDLEMODE = TXPDELECIDLEMODE; assign #(in_delay) delay_TXPHALIGN = TXPHALIGN; assign #(in_delay) delay_TXPHALIGNEN = TXPHALIGNEN; assign #(in_delay) delay_TXPHDLYPD = TXPHDLYPD; assign #(in_delay) delay_TXPHDLYRESET = TXPHDLYRESET; assign #(in_delay) delay_TXPHINIT = TXPHINIT; assign #(in_delay) delay_TXPHOVRDEN = TXPHOVRDEN; assign #(in_delay) delay_TXPIPPMEN = TXPIPPMEN; assign #(in_delay) delay_TXPIPPMOVRDEN = TXPIPPMOVRDEN; assign #(in_delay) delay_TXPIPPMPD = TXPIPPMPD; assign #(in_delay) delay_TXPIPPMSEL = TXPIPPMSEL; assign #(in_delay) delay_TXPIPPMSTEPSIZE = TXPIPPMSTEPSIZE; assign #(in_delay) delay_TXPISOPD = TXPISOPD; assign #(in_delay) delay_TXPMARESET = TXPMARESET; assign #(in_delay) delay_TXPOLARITY = TXPOLARITY; assign #(in_delay) delay_TXPOSTCURSOR = TXPOSTCURSOR; assign #(in_delay) delay_TXPOSTCURSORINV = TXPOSTCURSORINV; assign #(in_delay) delay_TXPRBSFORCEERR = TXPRBSFORCEERR; assign #(in_delay) delay_TXPRBSSEL = TXPRBSSEL; assign #(in_delay) delay_TXPRECURSOR = TXPRECURSOR; assign #(in_delay) delay_TXPRECURSORINV = TXPRECURSORINV; assign #(in_delay) delay_TXRATE = TXRATE; assign #(in_delay) delay_TXRATEMODE = TXRATEMODE; assign #(in_delay) delay_TXSEQUENCE = TXSEQUENCE; assign #(in_delay) delay_TXSTARTSEQ = TXSTARTSEQ; assign #(in_delay) delay_TXSWING = TXSWING; assign #(in_delay) delay_TXSYNCALLIN = TXSYNCALLIN; assign #(in_delay) delay_TXSYNCIN = TXSYNCIN; assign #(in_delay) delay_TXSYNCMODE = TXSYNCMODE; assign #(in_delay) delay_TXSYSCLKSEL = TXSYSCLKSEL; assign #(in_delay) delay_TXUSERRDY = TXUSERRDY; `endif // `ifndef XIL_TIMING `ifdef XIL_TIMING //Simprim assign delay_CFGRESET = CFGRESET; assign delay_CLKRSVD0 = CLKRSVD0; assign delay_CLKRSVD1 = CLKRSVD1; assign delay_DMONFIFORESET = DMONFIFORESET; assign delay_DMONITORCLK = DMONITORCLK; assign delay_EYESCANMODE = EYESCANMODE; assign delay_EYESCANRESET = EYESCANRESET; assign delay_EYESCANTRIGGER = EYESCANTRIGGER; assign delay_GTPRXN = GTPRXN; assign delay_GTPRXP = GTPRXP; assign delay_GTRESETSEL = GTRESETSEL; assign delay_GTRSVD = GTRSVD; assign delay_GTRXRESET = GTRXRESET; assign delay_GTTXRESET = GTTXRESET; assign delay_LOOPBACK = LOOPBACK; assign delay_PCSRSVDIN = PCSRSVDIN; assign delay_PLL0CLK = PLL0CLK; assign delay_PLL0REFCLK = PLL0REFCLK; assign delay_PLL1CLK = PLL1CLK; assign delay_PLL1REFCLK = PLL1REFCLK; assign delay_PMARSVDIN0 = PMARSVDIN0; assign delay_PMARSVDIN1 = PMARSVDIN1; assign delay_PMARSVDIN2 = PMARSVDIN2; assign delay_PMARSVDIN3 = PMARSVDIN3; assign delay_PMARSVDIN4 = PMARSVDIN4; assign delay_RESETOVRD = RESETOVRD; assign delay_RXADAPTSELTEST = RXADAPTSELTEST; assign delay_RXBUFRESET = RXBUFRESET; assign delay_RXCDRFREQRESET = RXCDRFREQRESET; assign delay_RXCDRHOLD = RXCDRHOLD; assign delay_RXCDROVRDEN = RXCDROVRDEN; assign delay_RXCDRRESET = RXCDRRESET; assign delay_RXCDRRESETRSV = RXCDRRESETRSV; assign delay_RXCHBONDI = RXCHBONDI; assign delay_RXDDIEN = RXDDIEN; assign delay_RXDFEXYDEN = RXDFEXYDEN; assign delay_RXDLYBYPASS = RXDLYBYPASS; assign delay_RXDLYEN = RXDLYEN; assign delay_RXDLYOVRDEN = RXDLYOVRDEN; assign delay_RXDLYSRESET = RXDLYSRESET; assign delay_RXELECIDLEMODE = RXELECIDLEMODE; assign delay_RXLPMHFHOLD = RXLPMHFHOLD; assign delay_RXLPMHFOVRDEN = RXLPMHFOVRDEN; assign delay_RXLPMLFHOLD = RXLPMLFHOLD; assign delay_RXLPMLFOVRDEN = RXLPMLFOVRDEN; assign delay_RXLPMOSINTNTRLEN = RXLPMOSINTNTRLEN; assign delay_RXLPMRESET = RXLPMRESET; assign delay_RXOOBRESET = RXOOBRESET; assign delay_RXOSCALRESET = RXOSCALRESET; assign delay_RXOSHOLD = RXOSHOLD; assign delay_RXOSINTCFG = RXOSINTCFG; assign delay_RXOSINTEN = RXOSINTEN; assign delay_RXOSINTHOLD = RXOSINTHOLD; assign delay_RXOSINTID0 = RXOSINTID0; assign delay_RXOSINTNTRLEN = RXOSINTNTRLEN; assign delay_RXOSINTOVRDEN = RXOSINTOVRDEN; assign delay_RXOSINTPD = RXOSINTPD; assign delay_RXOSINTSTROBE = RXOSINTSTROBE; assign delay_RXOSINTTESTOVRDEN = RXOSINTTESTOVRDEN; assign delay_RXOSOVRDEN = RXOSOVRDEN; assign delay_RXOUTCLKSEL = RXOUTCLKSEL; assign delay_RXPCSRESET = RXPCSRESET; assign delay_RXPD = RXPD; assign delay_RXPHALIGN = RXPHALIGN; assign delay_RXPHALIGNEN = RXPHALIGNEN; assign delay_RXPHDLYPD = RXPHDLYPD; assign delay_RXPHDLYRESET = RXPHDLYRESET; assign delay_RXPHOVRDEN = RXPHOVRDEN; assign delay_RXPMARESET = RXPMARESET; assign delay_RXRATEMODE = RXRATEMODE; assign delay_RXSYNCALLIN = RXSYNCALLIN; assign delay_RXSYNCIN = RXSYNCIN; assign delay_RXSYNCMODE = RXSYNCMODE; assign delay_RXSYSCLKSEL = RXSYSCLKSEL; assign delay_RXUSERRDY = RXUSERRDY; assign delay_SIGVALIDCLK = SIGVALIDCLK; assign delay_TSTIN = TSTIN; assign delay_TXBUFDIFFCTRL = TXBUFDIFFCTRL; assign delay_TXDEEMPH = TXDEEMPH; assign delay_TXDIFFCTRL = TXDIFFCTRL; assign delay_TXDIFFPD = TXDIFFPD; assign delay_TXDLYBYPASS = TXDLYBYPASS; assign delay_TXDLYEN = TXDLYEN; assign delay_TXDLYOVRDEN = TXDLYOVRDEN; assign delay_TXDLYSRESET = TXDLYSRESET; assign delay_TXMAINCURSOR = TXMAINCURSOR; assign delay_TXMARGIN = TXMARGIN; assign delay_TXOUTCLKSEL = TXOUTCLKSEL; assign delay_TXPCSRESET = TXPCSRESET; assign delay_TXPDELECIDLEMODE = TXPDELECIDLEMODE; assign delay_TXPHALIGN = TXPHALIGN; assign delay_TXPHALIGNEN = TXPHALIGNEN; assign delay_TXPHDLYPD = TXPHDLYPD; assign delay_TXPHDLYRESET = TXPHDLYRESET; assign delay_TXPHINIT = TXPHINIT; assign delay_TXPHOVRDEN = TXPHOVRDEN; assign delay_TXPIPPMOVRDEN = TXPIPPMOVRDEN; assign delay_TXPIPPMPD = TXPIPPMPD; assign delay_TXPIPPMSEL = TXPIPPMSEL; assign delay_TXPISOPD = TXPISOPD; assign delay_TXPMARESET = TXPMARESET; assign delay_TXPOSTCURSOR = TXPOSTCURSOR; assign delay_TXPOSTCURSORINV = TXPOSTCURSORINV; assign delay_TXPRECURSOR = TXPRECURSOR; assign delay_TXPRECURSORINV = TXPRECURSORINV; assign delay_TXRATEMODE = TXRATEMODE; assign delay_TXSWING = TXSWING; assign delay_TXSYNCALLIN = TXSYNCALLIN; assign delay_TXSYNCIN = TXSYNCIN; assign delay_TXSYNCMODE = TXSYNCMODE; assign delay_TXSYSCLKSEL = TXSYSCLKSEL; assign delay_TXUSERRDY = TXUSERRDY; `endif B_GTPE2_CHANNEL #( .ACJTAG_DEBUG_MODE (ACJTAG_DEBUG_MODE), .ACJTAG_MODE (ACJTAG_MODE), .ACJTAG_RESET (ACJTAG_RESET), .ADAPT_CFG0 (ADAPT_CFG0), .ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE), .ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE), .ALIGN_COMMA_WORD (ALIGN_COMMA_WORD), .ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET), .ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE), .ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET), .ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE), .CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL), .CFOK_CFG (CFOK_CFG), .CFOK_CFG2 (CFOK_CFG2), .CFOK_CFG3 (CFOK_CFG3), .CFOK_CFG4 (CFOK_CFG4), .CFOK_CFG5 (CFOK_CFG5), .CFOK_CFG6 (CFOK_CFG6), .CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN), .CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW), .CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1), .CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2), .CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3), .CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4), .CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE), .CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1), .CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2), .CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3), .CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4), .CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE), .CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE), .CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN), .CLK_COMMON_SWING (CLK_COMMON_SWING), .CLK_CORRECT_USE (CLK_CORRECT_USE), .CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE), .CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), .CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), .CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE), .CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT), .CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1), .CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2), .CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3), .CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4), .CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE), .CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1), .CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2), .CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3), .CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4), .CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE), .CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE), .CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN), .DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT), .DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT), .DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY), .DMONITOR_CFG (DMONITOR_CFG), .ES_CLK_PHASE_SEL (ES_CLK_PHASE_SEL), .ES_CONTROL (ES_CONTROL), .ES_ERRDET_EN (ES_ERRDET_EN), .ES_EYE_SCAN_EN (ES_EYE_SCAN_EN), .ES_HORZ_OFFSET (ES_HORZ_OFFSET), .ES_PMA_CFG (ES_PMA_CFG), .ES_PRESCALE (ES_PRESCALE), .ES_QUALIFIER (ES_QUALIFIER), .ES_QUAL_MASK (ES_QUAL_MASK), .ES_SDATA_MASK (ES_SDATA_MASK), .ES_VERT_OFFSET (ES_VERT_OFFSET), .FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE), .FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG), .FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN), .GEARBOX_MODE (GEARBOX_MODE), .LOOPBACK_CFG (LOOPBACK_CFG), .OUTREFCLK_SEL_INV (OUTREFCLK_SEL_INV), .PCS_PCIE_EN (PCS_PCIE_EN), .PCS_RSVD_ATTR (PCS_RSVD_ATTR), .PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2), .PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2), .PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2), .PMA_LOOPBACK_CFG (PMA_LOOPBACK_CFG), .PMA_RSV (PMA_RSV), .PMA_RSV2 (PMA_RSV2), .PMA_RSV3 (PMA_RSV3), .PMA_RSV4 (PMA_RSV4), .PMA_RSV5 (PMA_RSV5), .PMA_RSV6 (PMA_RSV6), .PMA_RSV7 (PMA_RSV7), .RXBUFRESET_TIME (RXBUFRESET_TIME), .RXBUF_ADDR_MODE (RXBUF_ADDR_MODE), .RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT), .RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT), .RXBUF_EN (RXBUF_EN), .RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE), .RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN), .RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE), .RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE), .RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW), .RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD), .RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW), .RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME), .RXCDRPHRESET_TIME (RXCDRPHRESET_TIME), .RXCDR_CFG (RXCDR_CFG), .RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE), .RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE), .RXCDR_LOCK_CFG (RXCDR_LOCK_CFG), .RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE), .RXDLY_CFG (RXDLY_CFG), .RXDLY_LCFG (RXDLY_LCFG), .RXDLY_TAP_CFG (RXDLY_TAP_CFG), .RXGEARBOX_EN (RXGEARBOX_EN), .RXISCANRESET_TIME (RXISCANRESET_TIME), .RXLPMRESET_TIME (RXLPMRESET_TIME), .RXLPM_BIAS_STARTUP_DISABLE (RXLPM_BIAS_STARTUP_DISABLE), .RXLPM_CFG (RXLPM_CFG), .RXLPM_CFG1 (RXLPM_CFG1), .RXLPM_CM_CFG (RXLPM_CM_CFG), .RXLPM_GC_CFG (RXLPM_GC_CFG), .RXLPM_GC_CFG2 (RXLPM_GC_CFG2), .RXLPM_HF_CFG (RXLPM_HF_CFG), .RXLPM_HF_CFG2 (RXLPM_HF_CFG2), .RXLPM_HF_CFG3 (RXLPM_HF_CFG3), .RXLPM_HOLD_DURING_EIDLE (RXLPM_HOLD_DURING_EIDLE), .RXLPM_INCM_CFG (RXLPM_INCM_CFG), .RXLPM_IPCM_CFG (RXLPM_IPCM_CFG), .RXLPM_LF_CFG (RXLPM_LF_CFG), .RXLPM_LF_CFG2 (RXLPM_LF_CFG2), .RXLPM_OSINT_CFG (RXLPM_OSINT_CFG), .RXOOB_CFG (RXOOB_CFG), .RXOOB_CLK_CFG (RXOOB_CLK_CFG), .RXOSCALRESET_TIME (RXOSCALRESET_TIME), .RXOSCALRESET_TIMEOUT (RXOSCALRESET_TIMEOUT), .RXOUT_DIV (RXOUT_DIV), .RXPCSRESET_TIME (RXPCSRESET_TIME), .RXPHDLY_CFG (RXPHDLY_CFG), .RXPH_CFG (RXPH_CFG), .RXPH_MONITOR_SEL (RXPH_MONITOR_SEL), .RXPI_CFG0 (RXPI_CFG0), .RXPI_CFG1 (RXPI_CFG1), .RXPI_CFG2 (RXPI_CFG2), .RXPMARESET_TIME (RXPMARESET_TIME), .RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK), .RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT), .RXSLIDE_MODE (RXSLIDE_MODE), .RXSYNC_MULTILANE (RXSYNC_MULTILANE), .RXSYNC_OVRD (RXSYNC_OVRD), .RXSYNC_SKIP_DA (RXSYNC_SKIP_DA), .RX_BIAS_CFG (RX_BIAS_CFG), .RX_BUFFER_CFG (RX_BUFFER_CFG), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_CLKMUX_EN (RX_CLKMUX_EN), .RX_CM_SEL (RX_CM_SEL), .RX_CM_TRIM (RX_CM_TRIM), .RX_DATA_WIDTH (RX_DATA_WIDTH), .RX_DDI_SEL (RX_DDI_SEL), .RX_DEBUG_CFG (RX_DEBUG_CFG), .RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN), .RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH), .RX_OS_CFG (RX_OS_CFG), .RX_SIG_VALID_DLY (RX_SIG_VALID_DLY), .RX_XCLK_SEL (RX_XCLK_SEL), .SAS_MAX_COM (SAS_MAX_COM), .SAS_MIN_COM (SAS_MIN_COM), .SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN), .SATA_BURST_VAL (SATA_BURST_VAL), .SATA_EIDLE_VAL (SATA_EIDLE_VAL), .SATA_MAX_BURST (SATA_MAX_BURST), .SATA_MAX_INIT (SATA_MAX_INIT), .SATA_MAX_WAKE (SATA_MAX_WAKE), .SATA_MIN_BURST (SATA_MIN_BURST), .SATA_MIN_INIT (SATA_MIN_INIT), .SATA_MIN_WAKE (SATA_MIN_WAKE), .SATA_PLL_CFG (SATA_PLL_CFG), .SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA), .SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS), .SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP), .SIM_TX_EIDLE_DRIVE_LEVEL (SIM_TX_EIDLE_DRIVE_LEVEL), .SIM_VERSION (SIM_VERSION), .TERM_RCAL_CFG (TERM_RCAL_CFG), .TERM_RCAL_OVRD (TERM_RCAL_OVRD), .TRANS_TIME_RATE (TRANS_TIME_RATE), .TST_RSV (TST_RSV), .TXBUF_EN (TXBUF_EN), .TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE), .TXDLY_CFG (TXDLY_CFG), .TXDLY_LCFG (TXDLY_LCFG), .TXDLY_TAP_CFG (TXDLY_TAP_CFG), .TXGEARBOX_EN (TXGEARBOX_EN), .TXOOB_CFG (TXOOB_CFG), .TXOUT_DIV (TXOUT_DIV), .TXPCSRESET_TIME (TXPCSRESET_TIME), .TXPHDLY_CFG (TXPHDLY_CFG), .TXPH_CFG (TXPH_CFG), .TXPH_MONITOR_SEL (TXPH_MONITOR_SEL), .TXPI_CFG0 (TXPI_CFG0), .TXPI_CFG1 (TXPI_CFG1), .TXPI_CFG2 (TXPI_CFG2), .TXPI_CFG3 (TXPI_CFG3), .TXPI_CFG4 (TXPI_CFG4), .TXPI_CFG5 (TXPI_CFG5), .TXPI_GREY_SEL (TXPI_GREY_SEL), .TXPI_INVSTROBE_SEL (TXPI_INVSTROBE_SEL), .TXPI_PPMCLK_SEL (TXPI_PPMCLK_SEL), .TXPI_PPM_CFG (TXPI_PPM_CFG), .TXPI_SYNFREQ_PPM (TXPI_SYNFREQ_PPM), .TXPMARESET_TIME (TXPMARESET_TIME), .TXSYNC_MULTILANE (TXSYNC_MULTILANE), .TXSYNC_OVRD (TXSYNC_OVRD), .TXSYNC_SKIP_DA (TXSYNC_SKIP_DA), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLKMUX_EN (TX_CLKMUX_EN), .TX_DATA_WIDTH (TX_DATA_WIDTH), .TX_DEEMPH0 (TX_DEEMPH0), .TX_DEEMPH1 (TX_DEEMPH1), .TX_DRIVE_MODE (TX_DRIVE_MODE), .TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY), .TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY), .TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ), .TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL), .TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0), .TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1), .TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2), .TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3), .TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4), .TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0), .TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1), .TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2), .TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3), .TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4), .TX_PREDRIVER_MODE (TX_PREDRIVER_MODE), .TX_RXDETECT_CFG (TX_RXDETECT_CFG), .TX_RXDETECT_REF (TX_RXDETECT_REF), .TX_XCLK_SEL (TX_XCLK_SEL), .UCODEER_CLR (UCODEER_CLR), .USE_PCS_CLK_PHASE_SEL (USE_PCS_CLK_PHASE_SEL)) B_GTPE2_CHANNEL_INST ( .DMONITOROUT (delay_DMONITOROUT), .DRPDO (delay_DRPDO), .DRPRDY (delay_DRPRDY), .EYESCANDATAERROR (delay_EYESCANDATAERROR), .GTPTXN (delay_GTPTXN), .GTPTXP (delay_GTPTXP), .PCSRSVDOUT (delay_PCSRSVDOUT), .PHYSTATUS (delay_PHYSTATUS), .PMARSVDOUT0 (delay_PMARSVDOUT0), .PMARSVDOUT1 (delay_PMARSVDOUT1), .RXBUFSTATUS (delay_RXBUFSTATUS), .RXBYTEISALIGNED (delay_RXBYTEISALIGNED), .RXBYTEREALIGN (delay_RXBYTEREALIGN), .RXCDRLOCK (delay_RXCDRLOCK), .RXCHANBONDSEQ (delay_RXCHANBONDSEQ), .RXCHANISALIGNED (delay_RXCHANISALIGNED), .RXCHANREALIGN (delay_RXCHANREALIGN), .RXCHARISCOMMA (delay_RXCHARISCOMMA), .RXCHARISK (delay_RXCHARISK), .RXCHBONDO (delay_RXCHBONDO), .RXCLKCORCNT (delay_RXCLKCORCNT), .RXCOMINITDET (delay_RXCOMINITDET), .RXCOMMADET (delay_RXCOMMADET), .RXCOMSASDET (delay_RXCOMSASDET), .RXCOMWAKEDET (delay_RXCOMWAKEDET), .RXDATA (delay_RXDATA), .RXDATAVALID (delay_RXDATAVALID), .RXDISPERR (delay_RXDISPERR), .RXDLYSRESETDONE (delay_RXDLYSRESETDONE), .RXELECIDLE (delay_RXELECIDLE), .RXHEADER (delay_RXHEADER), .RXHEADERVALID (delay_RXHEADERVALID), .RXNOTINTABLE (delay_RXNOTINTABLE), .RXOSINTDONE (delay_RXOSINTDONE), .RXOSINTSTARTED (delay_RXOSINTSTARTED), .RXOSINTSTROBEDONE (delay_RXOSINTSTROBEDONE), .RXOSINTSTROBESTARTED (delay_RXOSINTSTROBESTARTED), .RXOUTCLK (delay_RXOUTCLK), .RXOUTCLKFABRIC (delay_RXOUTCLKFABRIC), .RXOUTCLKPCS (delay_RXOUTCLKPCS), .RXPHALIGNDONE (delay_RXPHALIGNDONE), .RXPHMONITOR (delay_RXPHMONITOR), .RXPHSLIPMONITOR (delay_RXPHSLIPMONITOR), .RXPMARESETDONE (delay_RXPMARESETDONE), .RXPRBSERR (delay_RXPRBSERR), .RXRATEDONE (delay_RXRATEDONE), .RXRESETDONE (delay_RXRESETDONE), .RXSTARTOFSEQ (delay_RXSTARTOFSEQ), .RXSTATUS (delay_RXSTATUS), .RXSYNCDONE (delay_RXSYNCDONE), .RXSYNCOUT (delay_RXSYNCOUT), .RXVALID (delay_RXVALID), .TXBUFSTATUS (delay_TXBUFSTATUS), .TXCOMFINISH (delay_TXCOMFINISH), .TXDLYSRESETDONE (delay_TXDLYSRESETDONE), .TXGEARBOXREADY (delay_TXGEARBOXREADY), .TXOUTCLK (delay_TXOUTCLK), .TXOUTCLKFABRIC (delay_TXOUTCLKFABRIC), .TXOUTCLKPCS (delay_TXOUTCLKPCS), .TXPHALIGNDONE (delay_TXPHALIGNDONE), .TXPHINITDONE (delay_TXPHINITDONE), .TXPMARESETDONE (delay_TXPMARESETDONE), .TXRATEDONE (delay_TXRATEDONE), .TXRESETDONE (delay_TXRESETDONE), .TXSYNCDONE (delay_TXSYNCDONE), .TXSYNCOUT (delay_TXSYNCOUT), .CFGRESET (delay_CFGRESET), .CLKRSVD0 (delay_CLKRSVD0), .CLKRSVD1 (delay_CLKRSVD1), .DMONFIFORESET (delay_DMONFIFORESET), .DMONITORCLK (delay_DMONITORCLK), .DRPADDR (delay_DRPADDR), .DRPCLK (delay_DRPCLK), .DRPDI (delay_DRPDI), .DRPEN (delay_DRPEN), .DRPWE (delay_DRPWE), .EYESCANMODE (delay_EYESCANMODE), .EYESCANRESET (delay_EYESCANRESET), .EYESCANTRIGGER (delay_EYESCANTRIGGER), .GTPRXN (delay_GTPRXN), .GTPRXP (delay_GTPRXP), .GTRESETSEL (delay_GTRESETSEL), .GTRSVD (delay_GTRSVD), .GTRXRESET (delay_GTRXRESET), .GTTXRESET (delay_GTTXRESET), .LOOPBACK (delay_LOOPBACK), .PCSRSVDIN (delay_PCSRSVDIN), .PLL0CLK (delay_PLL0CLK), .PLL0REFCLK (delay_PLL0REFCLK), .PLL1CLK (delay_PLL1CLK), .PLL1REFCLK (delay_PLL1REFCLK), .PMARSVDIN0 (delay_PMARSVDIN0), .PMARSVDIN1 (delay_PMARSVDIN1), .PMARSVDIN2 (delay_PMARSVDIN2), .PMARSVDIN3 (delay_PMARSVDIN3), .PMARSVDIN4 (delay_PMARSVDIN4), .RESETOVRD (delay_RESETOVRD), .RX8B10BEN (delay_RX8B10BEN), .RXADAPTSELTEST (delay_RXADAPTSELTEST), .RXBUFRESET (delay_RXBUFRESET), .RXCDRFREQRESET (delay_RXCDRFREQRESET), .RXCDRHOLD (delay_RXCDRHOLD), .RXCDROVRDEN (delay_RXCDROVRDEN), .RXCDRRESET (delay_RXCDRRESET), .RXCDRRESETRSV (delay_RXCDRRESETRSV), .RXCHBONDEN (delay_RXCHBONDEN), .RXCHBONDI (delay_RXCHBONDI), .RXCHBONDLEVEL (delay_RXCHBONDLEVEL), .RXCHBONDMASTER (delay_RXCHBONDMASTER), .RXCHBONDSLAVE (delay_RXCHBONDSLAVE), .RXCOMMADETEN (delay_RXCOMMADETEN), .RXDDIEN (delay_RXDDIEN), .RXDFEXYDEN (delay_RXDFEXYDEN), .RXDLYBYPASS (delay_RXDLYBYPASS), .RXDLYEN (delay_RXDLYEN), .RXDLYOVRDEN (delay_RXDLYOVRDEN), .RXDLYSRESET (delay_RXDLYSRESET), .RXELECIDLEMODE (delay_RXELECIDLEMODE), .RXGEARBOXSLIP (delay_RXGEARBOXSLIP), .RXLPMHFHOLD (delay_RXLPMHFHOLD), .RXLPMHFOVRDEN (delay_RXLPMHFOVRDEN), .RXLPMLFHOLD (delay_RXLPMLFHOLD), .RXLPMLFOVRDEN (delay_RXLPMLFOVRDEN), .RXLPMOSINTNTRLEN (delay_RXLPMOSINTNTRLEN), .RXLPMRESET (delay_RXLPMRESET), .RXMCOMMAALIGNEN (delay_RXMCOMMAALIGNEN), .RXOOBRESET (delay_RXOOBRESET), .RXOSCALRESET (delay_RXOSCALRESET), .RXOSHOLD (delay_RXOSHOLD), .RXOSINTCFG (delay_RXOSINTCFG), .RXOSINTEN (delay_RXOSINTEN), .RXOSINTHOLD (delay_RXOSINTHOLD), .RXOSINTID0 (delay_RXOSINTID0), .RXOSINTNTRLEN (delay_RXOSINTNTRLEN), .RXOSINTOVRDEN (delay_RXOSINTOVRDEN), .RXOSINTPD (delay_RXOSINTPD), .RXOSINTSTROBE (delay_RXOSINTSTROBE), .RXOSINTTESTOVRDEN (delay_RXOSINTTESTOVRDEN), .RXOSOVRDEN (delay_RXOSOVRDEN), .RXOUTCLKSEL (delay_RXOUTCLKSEL), .RXPCOMMAALIGNEN (delay_RXPCOMMAALIGNEN), .RXPCSRESET (delay_RXPCSRESET), .RXPD (delay_RXPD), .RXPHALIGN (delay_RXPHALIGN), .RXPHALIGNEN (delay_RXPHALIGNEN), .RXPHDLYPD (delay_RXPHDLYPD), .RXPHDLYRESET (delay_RXPHDLYRESET), .RXPHOVRDEN (delay_RXPHOVRDEN), .RXPMARESET (delay_RXPMARESET), .RXPOLARITY (delay_RXPOLARITY), .RXPRBSCNTRESET (delay_RXPRBSCNTRESET), .RXPRBSSEL (delay_RXPRBSSEL), .RXRATE (delay_RXRATE), .RXRATEMODE (delay_RXRATEMODE), .RXSLIDE (delay_RXSLIDE), .RXSYNCALLIN (delay_RXSYNCALLIN), .RXSYNCIN (delay_RXSYNCIN), .RXSYNCMODE (delay_RXSYNCMODE), .RXSYSCLKSEL (delay_RXSYSCLKSEL), .RXUSERRDY (delay_RXUSERRDY), .RXUSRCLK (delay_RXUSRCLK), .RXUSRCLK2 (delay_RXUSRCLK2), .SETERRSTATUS (delay_SETERRSTATUS), .SIGVALIDCLK (delay_SIGVALIDCLK), .TSTIN (delay_TSTIN), .TX8B10BBYPASS (delay_TX8B10BBYPASS), .TX8B10BEN (delay_TX8B10BEN), .TXBUFDIFFCTRL (delay_TXBUFDIFFCTRL), .TXCHARDISPMODE (delay_TXCHARDISPMODE), .TXCHARDISPVAL (delay_TXCHARDISPVAL), .TXCHARISK (delay_TXCHARISK), .TXCOMINIT (delay_TXCOMINIT), .TXCOMSAS (delay_TXCOMSAS), .TXCOMWAKE (delay_TXCOMWAKE), .TXDATA (delay_TXDATA), .TXDEEMPH (delay_TXDEEMPH), .TXDETECTRX (delay_TXDETECTRX), .TXDIFFCTRL (delay_TXDIFFCTRL), .TXDIFFPD (delay_TXDIFFPD), .TXDLYBYPASS (delay_TXDLYBYPASS), .TXDLYEN (delay_TXDLYEN), .TXDLYHOLD (delay_TXDLYHOLD), .TXDLYOVRDEN (delay_TXDLYOVRDEN), .TXDLYSRESET (delay_TXDLYSRESET), .TXDLYUPDOWN (delay_TXDLYUPDOWN), .TXELECIDLE (delay_TXELECIDLE), .TXHEADER (delay_TXHEADER), .TXINHIBIT (delay_TXINHIBIT), .TXMAINCURSOR (delay_TXMAINCURSOR), .TXMARGIN (delay_TXMARGIN), .TXOUTCLKSEL (delay_TXOUTCLKSEL), .TXPCSRESET (delay_TXPCSRESET), .TXPD (delay_TXPD), .TXPDELECIDLEMODE (delay_TXPDELECIDLEMODE), .TXPHALIGN (delay_TXPHALIGN), .TXPHALIGNEN (delay_TXPHALIGNEN), .TXPHDLYPD (delay_TXPHDLYPD), .TXPHDLYRESET (delay_TXPHDLYRESET), .TXPHDLYTSTCLK (delay_TXPHDLYTSTCLK), .TXPHINIT (delay_TXPHINIT), .TXPHOVRDEN (delay_TXPHOVRDEN), .TXPIPPMEN (delay_TXPIPPMEN), .TXPIPPMOVRDEN (delay_TXPIPPMOVRDEN), .TXPIPPMPD (delay_TXPIPPMPD), .TXPIPPMSEL (delay_TXPIPPMSEL), .TXPIPPMSTEPSIZE (delay_TXPIPPMSTEPSIZE), .TXPISOPD (delay_TXPISOPD), .TXPMARESET (delay_TXPMARESET), .TXPOLARITY (delay_TXPOLARITY), .TXPOSTCURSOR (delay_TXPOSTCURSOR), .TXPOSTCURSORINV (delay_TXPOSTCURSORINV), .TXPRBSFORCEERR (delay_TXPRBSFORCEERR), .TXPRBSSEL (delay_TXPRBSSEL), .TXPRECURSOR (delay_TXPRECURSOR), .TXPRECURSORINV (delay_TXPRECURSORINV), .TXRATE (delay_TXRATE), .TXRATEMODE (delay_TXRATEMODE), .TXSEQUENCE (delay_TXSEQUENCE), .TXSTARTSEQ (delay_TXSTARTSEQ), .TXSWING (delay_TXSWING), .TXSYNCALLIN (delay_TXSYNCALLIN), .TXSYNCIN (delay_TXSYNCIN), .TXSYNCMODE (delay_TXSYNCMODE), .TXSYSCLKSEL (delay_TXSYSCLKSEL), .TXUSERRDY (delay_TXUSERRDY), .TXUSRCLK (delay_TXUSRCLK), .TXUSRCLK2 (delay_TXUSRCLK2), .GSR (GSR) ); specify `ifdef XIL_TIMING // Simprim $period (posedge CLKRSVD0, 0:0:0, notifier); $period (negedge CLKRSVD0, 0:0:0, notifier); $period (posedge CLKRSVD1, 0:0:0, notifier); $period (negedge CLKRSVD1, 0:0:0, notifier); $period (posedge DMONITORCLK, 0:0:0, notifier); $period (negedge DMONITORCLK, 0:0:0, notifier); $period (posedge DRPCLK, 0:0:0, notifier); $period (negedge DRPCLK, 0:0:0, notifier); $period (posedge PLL0CLK, 0:0:0, notifier); $period (posedge PLL1CLK, 0:0:0, notifier); $period (posedge RXOUTCLK, 0:0:0, notifier); $period (posedge RXOUTCLKFABRIC, 0:0:0, notifier); $period (posedge RXOUTCLKPCS, 0:0:0, notifier); $period (posedge RXUSRCLK, 0:0:0, notifier); $period (negedge RXUSRCLK, 0:0:0, notifier); $period (posedge RXUSRCLK2, 0:0:0, notifier); $period (negedge RXUSRCLK2, 0:0:0, notifier); $period (posedge SIGVALIDCLK, 0:0:0, notifier); $period (negedge SIGVALIDCLK, 0:0:0, notifier); $period (posedge TXOUTCLK, 0:0:0, notifier); $period (posedge TXOUTCLKFABRIC, 0:0:0, notifier); $period (posedge TXOUTCLKPCS, 0:0:0, notifier); $period (posedge TXPHDLYTSTCLK, 0:0:0, notifier); $period (negedge TXPHDLYTSTCLK, 0:0:0, notifier); $period (posedge TXUSRCLK, 0:0:0, notifier); $period (negedge TXUSRCLK, 0:0:0, notifier); $period (posedge TXUSRCLK2, 0:0:0, notifier); $period (negedge TXUSRCLK2, 0:0:0, notifier); $setuphold (posedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR); $setuphold (posedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI); $setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN); $setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE); $setuphold (posedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR); $setuphold (posedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI); $setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN); $setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE); $setuphold (negedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR); $setuphold (negedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI); $setuphold (negedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN); $setuphold (negedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE); $setuphold (negedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR); $setuphold (negedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI); $setuphold (negedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN); $setuphold (negedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE); $setuphold (posedge RXUSRCLK, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK, delay_RXCHBONDI); $setuphold (posedge RXUSRCLK, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK, delay_RXCHBONDI); $setuphold (negedge RXUSRCLK, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK, delay_RXCHBONDI); $setuphold (negedge RXUSRCLK, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK, delay_RXCHBONDI); $setuphold (posedge RXUSRCLK2, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDI); $setuphold (posedge RXUSRCLK2, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDI); $setuphold (posedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RX8B10BEN); $setuphold (posedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDEN); $setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDLEVEL); $setuphold (posedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDMASTER); $setuphold (posedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDSLAVE); $setuphold (posedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCOMMADETEN); $setuphold (posedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXGEARBOXSLIP); $setuphold (posedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN); $setuphold (posedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN); $setuphold (posedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPOLARITY); $setuphold (posedge RXUSRCLK2, negedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPRBSCNTRESET); $setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPRBSSEL); $setuphold (posedge RXUSRCLK2, negedge RXRATE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXRATE); $setuphold (posedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXSLIDE); $setuphold (posedge RXUSRCLK2, negedge SETERRSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_SETERRSTATUS); $setuphold (posedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RX8B10BEN); $setuphold (posedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDEN); $setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDLEVEL); $setuphold (posedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDMASTER); $setuphold (posedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDSLAVE); $setuphold (posedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCOMMADETEN); $setuphold (posedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXGEARBOXSLIP); $setuphold (posedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN); $setuphold (posedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN); $setuphold (posedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPOLARITY); $setuphold (posedge RXUSRCLK2, posedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPRBSCNTRESET); $setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPRBSSEL); $setuphold (posedge RXUSRCLK2, posedge RXRATE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXRATE); $setuphold (posedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXSLIDE); $setuphold (posedge RXUSRCLK2, posedge SETERRSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_SETERRSTATUS); $setuphold (negedge RXUSRCLK2, posedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDI); $setuphold (negedge RXUSRCLK2, negedge RXCHBONDI, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDI); $setuphold (negedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RX8B10BEN); $setuphold (negedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDEN); $setuphold (negedge RXUSRCLK2, negedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDLEVEL); $setuphold (negedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDMASTER); $setuphold (negedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDSLAVE); $setuphold (negedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCOMMADETEN); $setuphold (negedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXGEARBOXSLIP); $setuphold (negedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN); $setuphold (negedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN); $setuphold (negedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPOLARITY); $setuphold (negedge RXUSRCLK2, negedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPRBSCNTRESET); $setuphold (negedge RXUSRCLK2, negedge RXPRBSSEL, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPRBSSEL); $setuphold (negedge RXUSRCLK2, negedge RXRATE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXRATE); $setuphold (negedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXSLIDE); $setuphold (negedge RXUSRCLK2, negedge SETERRSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_SETERRSTATUS); $setuphold (negedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RX8B10BEN); $setuphold (negedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDEN); $setuphold (negedge RXUSRCLK2, posedge RXCHBONDLEVEL, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDLEVEL); $setuphold (negedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDMASTER); $setuphold (negedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCHBONDSLAVE); $setuphold (negedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXCOMMADETEN); $setuphold (negedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXGEARBOXSLIP); $setuphold (negedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXMCOMMAALIGNEN); $setuphold (negedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPCOMMAALIGNEN); $setuphold (negedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPOLARITY); $setuphold (negedge RXUSRCLK2, posedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPRBSCNTRESET); $setuphold (negedge RXUSRCLK2, posedge RXPRBSSEL, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXPRBSSEL); $setuphold (negedge RXUSRCLK2, posedge RXRATE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXRATE); $setuphold (negedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_RXSLIDE); $setuphold (negedge RXUSRCLK2, posedge SETERRSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RXUSRCLK2, delay_SETERRSTATUS); $setuphold (posedge TXPHDLYTSTCLK, negedge TXDLYHOLD, 0:0:0, 0:0:0, notifier,,, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD); $setuphold (posedge TXPHDLYTSTCLK, negedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier,,, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN); $setuphold (posedge TXPHDLYTSTCLK, posedge TXDLYHOLD, 0:0:0, 0:0:0, notifier,,, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD); $setuphold (posedge TXPHDLYTSTCLK, posedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier,,, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN); $setuphold (negedge TXPHDLYTSTCLK, negedge TXDLYHOLD, 0:0:0, 0:0:0, notifier,,, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD); $setuphold (negedge TXPHDLYTSTCLK, negedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier,,, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN); $setuphold (negedge TXPHDLYTSTCLK, posedge TXDLYHOLD, 0:0:0, 0:0:0, notifier,,, delay_TXPHDLYTSTCLK, delay_TXDLYHOLD); $setuphold (negedge TXPHDLYTSTCLK, posedge TXDLYUPDOWN, 0:0:0, 0:0:0, notifier,,, delay_TXPHDLYTSTCLK, delay_TXDLYUPDOWN); $setuphold (posedge TXUSRCLK, negedge TXPIPPMEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK, delay_TXPIPPMEN); $setuphold (posedge TXUSRCLK, negedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK, delay_TXPIPPMSTEPSIZE); $setuphold (posedge TXUSRCLK, posedge TXPIPPMEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK, delay_TXPIPPMEN); $setuphold (posedge TXUSRCLK, posedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK, delay_TXPIPPMSTEPSIZE); $setuphold (negedge TXUSRCLK, negedge TXPIPPMEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK, delay_TXPIPPMEN); $setuphold (negedge TXUSRCLK, negedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK, delay_TXPIPPMSTEPSIZE); $setuphold (negedge TXUSRCLK, posedge TXPIPPMEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK, delay_TXPIPPMEN); $setuphold (negedge TXUSRCLK, posedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK, delay_TXPIPPMSTEPSIZE); $setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TX8B10BBYPASS); $setuphold (posedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TX8B10BEN); $setuphold (posedge TXUSRCLK2, negedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARDISPMODE); $setuphold (posedge TXUSRCLK2, negedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARDISPVAL); $setuphold (posedge TXUSRCLK2, negedge TXCHARISK, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARISK); $setuphold (posedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMINIT); $setuphold (posedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMSAS); $setuphold (posedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMWAKE); $setuphold (posedge TXUSRCLK2, negedge TXDATA, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXDATA); $setuphold (posedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXDETECTRX); $setuphold (posedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXELECIDLE); $setuphold (posedge TXUSRCLK2, negedge TXHEADER, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXHEADER); $setuphold (posedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXINHIBIT); $setuphold (posedge TXUSRCLK2, negedge TXPD, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPD); $setuphold (posedge TXUSRCLK2, negedge TXPIPPMEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPIPPMEN); $setuphold (posedge TXUSRCLK2, negedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPIPPMSTEPSIZE); $setuphold (posedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPOLARITY); $setuphold (posedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPRBSFORCEERR); $setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPRBSSEL); $setuphold (posedge TXUSRCLK2, negedge TXRATE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXRATE); $setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXSEQUENCE); $setuphold (posedge TXUSRCLK2, negedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXSTARTSEQ); $setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TX8B10BBYPASS); $setuphold (posedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TX8B10BEN); $setuphold (posedge TXUSRCLK2, posedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARDISPMODE); $setuphold (posedge TXUSRCLK2, posedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARDISPVAL); $setuphold (posedge TXUSRCLK2, posedge TXCHARISK, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARISK); $setuphold (posedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMINIT); $setuphold (posedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMSAS); $setuphold (posedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMWAKE); $setuphold (posedge TXUSRCLK2, posedge TXDATA, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXDATA); $setuphold (posedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXDETECTRX); $setuphold (posedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXELECIDLE); $setuphold (posedge TXUSRCLK2, posedge TXHEADER, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXHEADER); $setuphold (posedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXINHIBIT); $setuphold (posedge TXUSRCLK2, posedge TXPD, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPD); $setuphold (posedge TXUSRCLK2, posedge TXPIPPMEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPIPPMEN); $setuphold (posedge TXUSRCLK2, posedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPIPPMSTEPSIZE); $setuphold (posedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPOLARITY); $setuphold (posedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPRBSFORCEERR); $setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPRBSSEL); $setuphold (posedge TXUSRCLK2, posedge TXRATE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXRATE); $setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXSEQUENCE); $setuphold (posedge TXUSRCLK2, posedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXSTARTSEQ); $setuphold (negedge TXUSRCLK2, negedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TX8B10BBYPASS); $setuphold (negedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TX8B10BEN); $setuphold (negedge TXUSRCLK2, negedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARDISPMODE); $setuphold (negedge TXUSRCLK2, negedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARDISPVAL); $setuphold (negedge TXUSRCLK2, negedge TXCHARISK, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARISK); $setuphold (negedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMINIT); $setuphold (negedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMSAS); $setuphold (negedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMWAKE); $setuphold (negedge TXUSRCLK2, negedge TXDATA, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXDATA); $setuphold (negedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXDETECTRX); $setuphold (negedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXELECIDLE); $setuphold (negedge TXUSRCLK2, negedge TXHEADER, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXHEADER); $setuphold (negedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXINHIBIT); $setuphold (negedge TXUSRCLK2, negedge TXPD, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPD); $setuphold (negedge TXUSRCLK2, negedge TXPIPPMEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPIPPMEN); $setuphold (negedge TXUSRCLK2, negedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPIPPMSTEPSIZE); $setuphold (negedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPOLARITY); $setuphold (negedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPRBSFORCEERR); $setuphold (negedge TXUSRCLK2, negedge TXPRBSSEL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPRBSSEL); $setuphold (negedge TXUSRCLK2, negedge TXRATE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXRATE); $setuphold (negedge TXUSRCLK2, negedge TXSEQUENCE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXSEQUENCE); $setuphold (negedge TXUSRCLK2, negedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXSTARTSEQ); $setuphold (negedge TXUSRCLK2, posedge TX8B10BBYPASS, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TX8B10BBYPASS); $setuphold (negedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TX8B10BEN); $setuphold (negedge TXUSRCLK2, posedge TXCHARDISPMODE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARDISPMODE); $setuphold (negedge TXUSRCLK2, posedge TXCHARDISPVAL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARDISPVAL); $setuphold (negedge TXUSRCLK2, posedge TXCHARISK, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCHARISK); $setuphold (negedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMINIT); $setuphold (negedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMSAS); $setuphold (negedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXCOMWAKE); $setuphold (negedge TXUSRCLK2, posedge TXDATA, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXDATA); $setuphold (negedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXDETECTRX); $setuphold (negedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXELECIDLE); $setuphold (negedge TXUSRCLK2, posedge TXHEADER, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXHEADER); $setuphold (negedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXINHIBIT); $setuphold (negedge TXUSRCLK2, posedge TXPD, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPD); $setuphold (negedge TXUSRCLK2, posedge TXPIPPMEN, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPIPPMEN); $setuphold (negedge TXUSRCLK2, posedge TXPIPPMSTEPSIZE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPIPPMSTEPSIZE); $setuphold (negedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPOLARITY); $setuphold (negedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPRBSFORCEERR); $setuphold (negedge TXUSRCLK2, posedge TXPRBSSEL, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXPRBSSEL); $setuphold (negedge TXUSRCLK2, posedge TXRATE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXRATE); $setuphold (negedge TXUSRCLK2, posedge TXSEQUENCE, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXSEQUENCE); $setuphold (negedge TXUSRCLK2, posedge TXSTARTSEQ, 0:0:0, 0:0:0, notifier,,, delay_TXUSRCLK2, delay_TXSTARTSEQ); `endif ( DMONITORCLK *> DMONITOROUT) = (0, 0); ( DRPCLK *> DRPDO) = (0, 0); ( DRPCLK *> DRPRDY) = (0, 0); ( RXUSRCLK2 *> PHYSTATUS) = (0, 0); ( RXUSRCLK2 *> RXBUFSTATUS) = (0, 0); ( RXUSRCLK2 *> RXBYTEISALIGNED) = (0, 0); ( RXUSRCLK2 *> RXBYTEREALIGN) = (0, 0); ( RXUSRCLK2 *> RXCHANBONDSEQ) = (0, 0); ( RXUSRCLK2 *> RXCHANISALIGNED) = (0, 0); ( RXUSRCLK2 *> RXCHANREALIGN) = (0, 0); ( RXUSRCLK2 *> RXCHARISCOMMA) = (0, 0); ( RXUSRCLK2 *> RXCHARISK) = (0, 0); ( RXUSRCLK2 *> RXCHBONDO) = (0, 0); ( RXUSRCLK *> RXCHBONDO) = (0, 0); ( RXUSRCLK2 *> RXCLKCORCNT) = (0, 0); ( RXUSRCLK2 *> RXCOMINITDET) = (0, 0); ( RXUSRCLK2 *> RXCOMMADET) = (0, 0); ( RXUSRCLK2 *> RXCOMSASDET) = (0, 0); ( RXUSRCLK2 *> RXCOMWAKEDET) = (0, 0); ( RXUSRCLK2 *> RXDATA) = (0, 0); ( RXUSRCLK2 *> RXDATAVALID) = (0, 0); ( RXUSRCLK2 *> RXDISPERR) = (0, 0); ( RXUSRCLK2 *> RXHEADER) = (0, 0); ( RXUSRCLK2 *> RXHEADERVALID) = (0, 0); ( RXUSRCLK2 *> RXNOTINTABLE) = (0, 0); ( RXUSRCLK2 *> RXPRBSERR) = (0, 0); ( RXUSRCLK2 *> RXRATEDONE) = (0, 0); ( RXUSRCLK2 *> RXRESETDONE) = (0, 0); ( RXUSRCLK2 *> RXSTARTOFSEQ) = (0, 0); ( RXUSRCLK2 *> RXSTATUS) = (0, 0); ( RXUSRCLK2 *> RXVALID) = (0, 0); ( TXUSRCLK2 *> TXBUFSTATUS) = (0, 0); ( TXUSRCLK2 *> TXCOMFINISH) = (0, 0); ( TXUSRCLK2 *> TXGEARBOXREADY) = (0, 0); ( TXUSRCLK2 *> TXRATEDONE) = (0, 0); ( TXUSRCLK2 *> TXRESETDONE) = (0, 0); specparam PATHPULSE$ = 0; endspecify endmodule `endcelldefine
/* ---------------------------------------------------------------------------------- Copyright (c) 2013-2014 Embedded and Network Computing Lab. Open SSD Project Hanyang University All rights reserved. ---------------------------------------------------------------------------------- Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. All advertising materials mentioning features or use of this source code must display the following acknowledgement: This product includes source code developed by the Embedded and Network Computing Lab. and the Open SSD Project. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------------- http://enclab.hanyang.ac.kr/ http://www.openssd-project.org/ http://www.hanyang.ac.kr/ ---------------------------------------------------------------------------------- */ `timescale 1ns / 1ps module pcie_rx_cmd_fifo # ( parameter P_FIFO_DATA_WIDTH = 34, parameter P_FIFO_DEPTH_WIDTH = 5 ) ( input clk, input rst_n, input wr_en, input [P_FIFO_DATA_WIDTH-1:0] wr_data, output full_n, input rd_en, output [P_FIFO_DATA_WIDTH-1:0] rd_data, output empty_n ); localparam P_FIFO_ALLOC_WIDTH = 1; //128 bits reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr; reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1; wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr; reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr; assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH]) & (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH] == r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH])); assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH] == r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]); always @(posedge clk or negedge rst_n) begin if (rst_n == 0) begin r_front_addr <= 0; r_front_addr_p1 <= 1; r_rear_addr <= 0; end else begin if (rd_en == 1) begin r_front_addr <= r_front_addr_p1; r_front_addr_p1 <= r_front_addr_p1 + 1; end if (wr_en == 1) begin r_rear_addr <= r_rear_addr + 1; end end end assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0] : r_front_addr[P_FIFO_DEPTH_WIDTH-1:0]; localparam LP_DEVICE = "7SERIES"; localparam LP_BRAM_SIZE = "18Kb"; localparam LP_DOB_REG = 0; localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH; localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH; localparam LP_WRITE_MODE = "READ_FIRST"; localparam LP_WE_WIDTH = 4; localparam LP_ADDR_TOTAL_WITDH = 9; localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH; generate wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr; wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr; wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0; if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]; assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]; end else begin assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]}; assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]}; end endgenerate BRAM_SDP_MACRO #( .DEVICE (LP_DEVICE), .BRAM_SIZE (LP_BRAM_SIZE), .DO_REG (LP_DOB_REG), .READ_WIDTH (LP_READ_WIDTH), .WRITE_WIDTH (LP_WRITE_WIDTH), .WRITE_MODE (LP_WRITE_MODE) ) ramb18sdp_0( .DO (rd_data[LP_READ_WIDTH-1:0]), .DI (wr_data[LP_WRITE_WIDTH-1:0]), .RDADDR (rdaddr), .RDCLK (clk), .RDEN (1'b1), .REGCE (1'b1), .RST (1'b0), .WE ({LP_WE_WIDTH{1'b1}}), .WRADDR (wraddr), .WRCLK (clk), .WREN (wr_en) ); endmodule
//rgmii to gmii,gmii to rgmii; //by jzc 20100919; `timescale 1ns/1ns module rgmii_gmii ( reset_n, // RGMII Interface rgmii_txd, rgmii_tx_ctl, rgmii_tx_clk, rgmii_rxd, rgmii_rx_ctl, rgmii_rx_clk, // GMII Interface GTX_CLK, GMII_TXD_FROM_CORE, GMII_TX_EN_FROM_CORE, GMII_TX_ER_FROM_CORE, // GRX_CLK, GMII_RXD_TO_CORE, GMII_RX_DV_TO_CORE, GMII_RX_ER_TO_CORE, clk_tx, SPEED_IS_10_100 ); input SPEED_IS_10_100; // Port declarations input reset_n; input GTX_CLK; input clk_tx; // RGMII Interface output [3:0] rgmii_txd; output rgmii_tx_ctl; output rgmii_tx_clk; input [3:0] rgmii_rxd; input rgmii_rx_ctl; input rgmii_rx_clk; // GMII Interface8 input [7:0] GMII_TXD_FROM_CORE; input GMII_TX_EN_FROM_CORE; input GMII_TX_ER_FROM_CORE; output [7:0] GMII_RXD_TO_CORE; output GMII_RX_DV_TO_CORE; output GMII_RX_ER_TO_CORE; reg [3:0] rgmii_txd_rising; reg [3:0] rgmii_txd_falling; reg rgmii_tx_ctl_rising; reg rgmii_tx_ctl_falling; reg [7:0] GMII_RXD_TO_CORE; reg GMII_RX_DV_TO_CORE; reg GMII_RX_ER_TO_CORE; wire [3:0] rgmii_rxd_rising; wire [3:0] rgmii_rxd_falling; wire rgmii_rx_ctl_rising; wire rgmii_rx_ctl_falling; wire rgmii_tx_clk; ddio_out ddio_out_data( .aclr(!reset_n), .datain_h(rgmii_txd_rising), .datain_l(rgmii_txd_falling), .outclock(GTX_CLK), .dataout(rgmii_txd)); ddio_out_1 ddio_out_ctl( .aclr(!reset_n), .datain_h(rgmii_tx_ctl_rising), .datain_l(rgmii_tx_ctl_falling), .outclock(GTX_CLK), .dataout(rgmii_tx_ctl)); ddio_out_1 ddio_out_clk( .aclr(!reset_n), .datain_h(1'b1), .datain_l(1'b0), .outclock(clk_tx), .dataout(rgmii_tx_clk)); ddio_in_4 ddio_in_data( .aclr(!reset_n), .datain(rgmii_rxd), .inclock(rgmii_rx_clk), .dataout_h(rgmii_rxd_rising), .dataout_l(rgmii_rxd_falling)); ddio_in_1 ddio_in_ctl( .aclr(!reset_n), .datain(rgmii_rx_ctl), .inclock(rgmii_rx_clk), .dataout_h(rgmii_rx_ctl_rising), .dataout_l(rgmii_rx_ctl_falling)); //·¢ËÍ¡£GMII½Ó¿Úת»»³ÉRGMII½Ó¿Ú¡£SPEED_IS_10_100Ϊ1 ±íʾMII °ÙÕ×£» Ϊ0±íʾRGMII ǧÕ× always@(posedge GTX_CLK or negedge reset_n) begin if(!reset_n) begin rgmii_txd_rising <= 4'b0; rgmii_txd_falling <= 4'b0; rgmii_tx_ctl_rising <= 1'b0; rgmii_tx_ctl_falling <= 1'b0; end else begin rgmii_txd_rising <= GMII_TXD_FROM_CORE[3:0]; rgmii_tx_ctl_rising <= GMII_TX_EN_FROM_CORE; rgmii_tx_ctl_falling <= GMII_TX_EN_FROM_CORE ^ GMII_TX_ER_FROM_CORE; if(SPEED_IS_10_100)//100M rgmii_txd_falling <= GMII_TXD_FROM_CORE[3:0]; else//1000M rgmii_txd_falling <= GMII_TXD_FROM_CORE[7:4]; end end reg [3:0] rgmii_rxd_rising_r; reg rgmii_rx_ctl_rising_r; //½ÓÊÕ¡£RGMII½Ó¿Úת»»³ÉGMII½Ó¿Ú always@(posedge rgmii_rx_clk or negedge reset_n ) begin if(!reset_n) begin GMII_RXD_TO_CORE <= 8'b0; GMII_RX_DV_TO_CORE <= 1'b0; GMII_RX_ER_TO_CORE <= 1'b0; rgmii_rxd_rising_r <= 4'b0; rgmii_rx_ctl_rising_r <= 1'b0; end else begin GMII_RX_DV_TO_CORE <= rgmii_rx_ctl_rising_r; GMII_RX_ER_TO_CORE <= rgmii_rx_ctl_rising_r ^ rgmii_rx_ctl_falling; GMII_RXD_TO_CORE[7:4] <= rgmii_rxd_falling; GMII_RXD_TO_CORE[3:0] <= rgmii_rxd_rising_r; rgmii_rxd_rising_r <= rgmii_rxd_rising; rgmii_rx_ctl_rising_r <= rgmii_rx_ctl_rising; end end endmodule
/* Copyright (c) 2019 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ // Language: Verilog 2001 `resetall `timescale 1ns / 1ps `default_nettype none /* * AXI4-Stream frame length measurement */ module axis_frame_len # ( // Width of AXI stream interfaces in bits parameter DATA_WIDTH = 64, // Propagate tkeep signal // If disabled, tkeep assumed to be 1'b1 parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) parameter KEEP_WIDTH = (DATA_WIDTH/8), // Width of length counter parameter LEN_WIDTH = 16 ) ( input wire clk, input wire rst, /* * AXI monitor */ input wire [KEEP_WIDTH-1:0] monitor_axis_tkeep, input wire monitor_axis_tvalid, input wire monitor_axis_tready, input wire monitor_axis_tlast, /* * Status */ output wire [LEN_WIDTH-1:0] frame_len, output wire frame_len_valid ); reg [LEN_WIDTH-1:0] frame_len_reg = 0, frame_len_next; reg frame_len_valid_reg = 1'b0, frame_len_valid_next; assign frame_len = frame_len_reg; assign frame_len_valid = frame_len_valid_reg; integer offset, i, bit_cnt; always @* begin frame_len_next = frame_len_reg; frame_len_valid_next = 1'b0; if (frame_len_valid_reg) begin frame_len_next = 0; end if (monitor_axis_tready && monitor_axis_tvalid) begin // valid transfer cycle if (monitor_axis_tlast) begin // end of frame frame_len_valid_next = 1'b1; end // increment frame length by number of words transferred if (KEEP_ENABLE) begin bit_cnt = 0; for (i = 0; i <= KEEP_WIDTH; i = i + 1) begin if (monitor_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) bit_cnt = i; end frame_len_next = frame_len_next + bit_cnt; end else begin frame_len_next = frame_len_next + 1; end end end always @(posedge clk) begin frame_len_reg <= frame_len_next; frame_len_valid_reg <= frame_len_valid_next; if (rst) begin frame_len_reg <= 0; frame_len_valid_reg <= 0; end end endmodule `resetall
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: // Design Name: // Module Name: ACA_II_N16_Q4 // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module ACA_II_N16_Q4( input [15:0] in1, input [15:0] in2, output [16:0] res ); wire [4:0] temp1,temp2,temp3,temp4,temp5,temp6,temp7; assign temp1[4:0] = in1[ 3: 0] + in2[ 3: 0]; assign temp2[4:0] = in1[ 5: 2] + in2[ 5: 2]; assign temp3[4:0] = in1[ 7: 4] + in2[ 7: 4]; assign temp4[4:0] = in1[ 9: 6] + in2[ 9: 6]; assign temp5[4:0] = in1[11: 8] + in2[11: 8]; assign temp6[4:0] = in1[13:10] + in2[13:10]; assign temp7[4:0] = in1[15:12] + in2[15:12]; assign res[16:0] = {temp7[4:2],temp6[3:2],temp5[3:2],temp4[3:2],temp3[3:2],temp2[3:2],temp1[3:0]}; endmodule
/////////////////////////////////////////////////////////////////////////////// // Copyright (c) 2009 Xilinx, Inc. // This design is confidential and proprietary of Xilinx, All Rights Reserved. /////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: 1.0 // \ \ Filename: top_nto1_pll_diff_rx.v // / / Date Last Modified: November 5 2009 // /___/ /\ Date Created: June 1 2009 // \ \ / \ // \___\/\___\ // //Device: Spartan 6 //Purpose: Example differential input receiver for clock and data using PLL // Serdes factor and number of data lines are set by constants in the code //Reference: // //Revision History: // Rev 1.0 - First created (nicks) // /////////////////////////////////////////////////////////////////////////////// // // Disclaimer: // // This disclaimer is not a license and does not grant any rights to the materials // distributed herewith. Except as otherwise provided in a valid license issued to you // by Xilinx, and to the maximum extent permitted by applicable law: // (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, // AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, // INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR // FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract // or tort, including negligence, or under any other theory of liability) for any loss or damage // of any kind or nature related to, arising under or in connection with these materials, // including for any direct, or any indirect, special, incidental, or consequential loss // or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered // as a result of any action brought by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the possibility of the same. // // Critical Applications: // // Xilinx products are not designed or intended to be fail-safe, or for use in any application // requiring fail-safe performance, such as life-support or safety devices or systems, // Class III medical devices, nuclear facilities, applications related to the deployment of airbags, // or any other applications that could lead to death, personal injury, or severe property or // environmental damage (individually and collectively, "Critical Applications"). Customer assumes // the sole risk and liability of any use of Xilinx products in Critical Applications, subject only // to applicable laws and regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. // ////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps module top_nto1_pll_diff_rx ( input reset, // reset (active high) //input [3:0] rx_data_in_fix, // lvds data inputs input [1:0] rx_data_in_fix, // lvds data inputs input x_clk, // lvds clock input //output [27:0] data_out) ; // dummy outputs output [13:0] data_out) ; // dummy outputs // Parameters for serdes factor and number of IO pins parameter integer S = 7 ; // Set the serdes factor to 8 parameter integer D = 4 ; // Set the number of inputs and outputs parameter integer DS = (D*S)-1 ; // Used for bus widths = serdes factor * number of inputs - 1 wire rst ; wire [DS:0] rxd ; // Data from serdeses reg [DS:0] rxr ; // Registered Data from serdeses reg state ; reg bslip ; reg [3:0] count ; wire [6:0] clk_iserdes_data ; assign rst = reset ; // active high reset pin assign data_out = rxr ; // Clock Input. Generate ioclocks via BUFIO2 serdes_1_to_n_clk_pll_s8_diff #( .S (S), .CLKIN_PERIOD (50.000), .PLLD (1), .PLLX (S), .BS ("TRUE")) // Parameter to enable bitslip TRUE or FALSE (has to be true for video applications) inst_clkin ( .x_clk(x_clk), .rxioclk (rx_bufpll_clk_xn), .pattern1 (7'b1100001), // default values for 7:1 video applications .pattern2 (7'b1100011), .rx_serdesstrobe (rx_serdesstrobe), .rx_bufg_pll_x1 (rx_bufg_x1), .bitslip (bitslip), .reset (rst), .datain (clk_iserdes_data), .rx_pll_lckd (), // PLL locked - only used if a 2nd BUFPLL is required .rx_pllout_xs (), // Multiplied PLL clock - only used if a 2nd BUFPLL is required .rx_bufpll_lckd (rx_bufpll_lckd)) ; // Data Inputs assign not_bufpll_lckd = ~rx_bufpll_lckd ; serdes_1_to_n_data_s8_diff #( .S (S), .D (D)) inst_datain ( .use_phase_detector (1'b1), // '1' enables the phase detector logic .rx_data_in_fix(rx_data_in_fix), .rxioclk (rx_bufpll_clk_xn), .rxserdesstrobe (rx_serdesstrobe), .gclk (rx_bufg_x1), .bitslip (bitslip), .reset (not_bufpll_lckd), .data_out (rxd), .debug_in (2'b00), .debug ()); always @ (posedge rx_bufg_x1) // process received data begin rxr <= rxd ; end endmodule
// -*- verilog -*- // // USRP - Universal Software Radio Peripheral // // Copyright (C) 2005,2006 Matt Ettus // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 2 of the License, or // (at your option) any later version. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // `include "../../firmware/include/fpga_regs_common.v" `include "../../firmware/include/fpga_regs_standard.v" module io_pins ( inout wire [15:0] io_0, inout wire [15:0] io_1, input wire [15:0] reg_0, input wire [15:0] reg_1, input clock, input rx_reset, input tx_reset, input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe); reg [15:0] io_0_oe,io_1_oe; bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe),.reg_val(reg_0)); bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe),.reg_val(reg_1)); // Upper 16 bits are mask for lower 16 always @(posedge clock) if(serial_strobe) case(serial_addr) `FR_OE_0 : io_0_oe <= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); `FR_OE_1 : io_1_oe <= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); endcase // case(serial_addr) endmodule // io_pins
// megafunction wizard: %FIFO% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: dcfifo_mixed_widths // ============================================================ // File Name: rxlengthfifo_128x13.v // Megafunction Name(s): // dcfifo_mixed_widths // // Simulation Library Files(s): // altera_mf // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 10.1 Build 197 01/19/2011 SP 1 SJ Full Version // ************************************************************ //Copyright (C) 1991-2011 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module rxlengthfifo_128x13 ( aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, wrfull); input aclr; input [12:0] data; input rdclk; input rdreq; input wrclk; input wrreq; output [12:0] q; output rdempty; output wrfull; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri0 aclr; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif wire sub_wire0; wire [12:0] sub_wire1; wire sub_wire2; wire wrfull = sub_wire0; wire [12:0] q = sub_wire1[12:0]; wire rdempty = sub_wire2; dcfifo_mixed_widths dcfifo_mixed_widths_component ( .rdclk (rdclk), .wrclk (wrclk), .wrreq (wrreq), .aclr (aclr), .data (data), .rdreq (rdreq), .wrfull (sub_wire0), .q (sub_wire1), .rdempty (sub_wire2), .rdfull (), .rdusedw (), .wrempty (), .wrusedw ()); defparam dcfifo_mixed_widths_component.intended_device_family = "Stratix IV", dcfifo_mixed_widths_component.lpm_numwords = 128, dcfifo_mixed_widths_component.lpm_showahead = "OFF", dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths", dcfifo_mixed_widths_component.lpm_width = 13, dcfifo_mixed_widths_component.lpm_widthu = 7, dcfifo_mixed_widths_component.lpm_widthu_r = 7, dcfifo_mixed_widths_component.lpm_width_r = 13, dcfifo_mixed_widths_component.overflow_checking = "ON", dcfifo_mixed_widths_component.rdsync_delaypipe = 4, dcfifo_mixed_widths_component.underflow_checking = "ON", dcfifo_mixed_widths_component.use_eab = "ON", dcfifo_mixed_widths_component.write_aclr_synch = "OFF", dcfifo_mixed_widths_component.wrsync_delaypipe = 4; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" // Retrieval info: PRIVATE: AlmostFull NUMERIC "0" // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" // Retrieval info: PRIVATE: Clock NUMERIC "4" // Retrieval info: PRIVATE: Depth NUMERIC "128" // Retrieval info: PRIVATE: Empty NUMERIC "1" // Retrieval info: PRIVATE: Full NUMERIC "1" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV" // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" // Retrieval info: PRIVATE: Optimize NUMERIC "0" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" // Retrieval info: PRIVATE: UsedW NUMERIC "1" // Retrieval info: PRIVATE: Width NUMERIC "13" // Retrieval info: PRIVATE: dc_aclr NUMERIC "1" // Retrieval info: PRIVATE: diff_widths NUMERIC "1" // Retrieval info: PRIVATE: msb_usedw NUMERIC "0" // Retrieval info: PRIVATE: output_width NUMERIC "13" // Retrieval info: PRIVATE: rsEmpty NUMERIC "1" // Retrieval info: PRIVATE: rsFull NUMERIC "0" // Retrieval info: PRIVATE: rsUsedW NUMERIC "0" // Retrieval info: PRIVATE: sc_aclr NUMERIC "0" // Retrieval info: PRIVATE: sc_sclr NUMERIC "0" // Retrieval info: PRIVATE: wsEmpty NUMERIC "0" // Retrieval info: PRIVATE: wsFull NUMERIC "1" // Retrieval info: PRIVATE: wsUsedW NUMERIC "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV" // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128" // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths" // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "13" // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7" // Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "7" // Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "13" // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" // Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" // Retrieval info: CONSTANT: USE_EAB STRING "ON" // Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" // Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr" // Retrieval info: USED_PORT: data 0 0 13 0 INPUT NODEFVAL "data[12..0]" // Retrieval info: USED_PORT: q 0 0 13 0 OUTPUT NODEFVAL "q[12..0]" // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" // Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty" // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" // Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull" // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 // Retrieval info: CONNECT: @data 0 0 13 0 data 0 0 13 0 // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 // Retrieval info: CONNECT: q 0 0 13 0 @q 0 0 13 0 // Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 // Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 // Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13_inst.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13_bb.v TRUE // Retrieval info: LIB_FILE: altera_mf
module ShiftRows( x, z); input [127:0] x; output [127:0] z; wire [127:0] xr; wire [127:0] zr; generate genvar i; for (i = 0; i < 128; i = i + 1) begin:REV assign xr[127-i] = x[i]; assign z[i] = zr[127-i]; end endgenerate wire w0, w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12, w13, w14, w15, w16, w17, w18, w19, w20, w21, w22, w23, w24, w25, w26, w27, w28, w29, w30, w31, w32, w33, w34, w35, w36, w37, w38, w39, w40, w41, w42, w43, w44, w45, w46, w47, w48, w49, w50, w51, w52, w53, w54, w55, w56, w57, w58, w59, w60, w61, w62, w63, w64, w65, w66, w67, w68, w69, w70, w71, w72, w73, w74, w75, w76, w77, w78, w79, w80, w81, w82, w83, w84, w85, w86, w87, w88, w89, w90, w91, w92, w93, w94, w95, w96, w97, w98, w99, w100, w101, w102, w103, w104, w105, w106, w107, w108, w109, w110, w111, w112, w113, w114, w115, w116, w117, w118, w119, w120, w121, w122, w123, w124, w125, w126, w127, w128; assign {w0, w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12, w13, w14, w15, w16, w17, w18, w19, w20, w21, w22, w23, w24, w25, w26, w27, w28, w29, w30, w31, w32, w33, w34, w35, w36, w37, w38, w39, w40, w41, w42, w43, w44, w45, w46, w47, w48, w49, w50, w51, w52, w53, w54, w55, w56, w57, w58, w59, w60, w61, w62, w63, w64, w65, w66, w67, w68, w69, w70, w71, w72, w73, w74, w75, w76, w77, w78, w79, w80, w81, w82, w83, w84, w85, w86, w87, w88, w89, w90, w91, w92, w93, w94, w95, w96, w97, w98, w99, w100, w101, w102, w103, w104, w105, w106, w107, w108, w109, w110, w111, w112, w113, w114, w115, w116, w117, w118, w119, w120, w121, w122, w123, w124, w125, w126, w127} = xr; assign zr = {w0, w1, w2, w3, w4, w5, w6, w7, w40, w41, w42, w43, w44, w45, w46, w47, w80, w81, w82, w83, w84, w85, w86, w87, w120, w121, w122, w123, w124, w125, w126, w127, w32, w33, w34, w35, w36, w37, w38, w39, w72, w73, w74, w75, w76, w77, w78, w79, w112, w113, w114, w115, w116, w117, w118, w119, w24, w25, w26, w27, w28, w29, w30, w31, w64, w65, w66, w67, w68, w69, w70, w71, w104, w105, w106, w107, w108, w109, w110, w111, w16, w17, w18, w19, w20, w21, w22, w23, w56, w57, w58, w59, w60, w61, w62, w63, w96, w97, w98, w99, w100, w101, w102, w103, w8, w9, w10, w11, w12, w13, w14, w15, w48, w49, w50, w51, w52, w53, w54, w55, w88, w89, w90, w91, w92, w93, w94, w95}; endmodule
`timescale 1ns / 1ps //File: MusicSheetReader.v //Author: Jianjian Song //Date: May 11, 2012 //Purpose: Read a music sheet from memory MusicScore //module MusicScore(ReadOrWrite, Address, KeyInput, KeyOutput, TimeInput, TimeOutput,Clock, Reset); //Start reading when Start=1. Read from StartAddress until the end when Keyoutput=0; module MusicSheetReader(Start, EndofScore, StartAddress, KeyOutput, CurrentAddress, EndofNote, Clock, Reset); input Clock, Reset, Start; output EndofScore; parameter DataLength=4; input [DataLength-1:0] KeyOutput; parameter AddressBits=5; input [AddressBits-1:0] StartAddress; output reg [AddressBits-1:0] CurrentAddress; input EndofNote; reg State; //1 to read or 0 to stop assign EndofScore = ~State; always@(posedge Clock or posedge Reset) if (Reset==1) begin State<=0;end else if(Start==1) begin State<=1;end //start else if(KeyOutput==0) begin State<=0;end //stop else begin State<=State;end always@(posedge Clock or posedge Reset) if(Reset==1) begin CurrentAddress<=0;end else if (State==0) begin CurrentAddress<=StartAddress;end else if (EndofNote==1 && KeyOutput!=0) begin CurrentAddress<=CurrentAddress+1'b1; end else begin CurrentAddress<=CurrentAddress;end endmodule
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HD__CLKINV_PP_BLACKBOX_V `define SKY130_FD_SC_HD__CLKINV_PP_BLACKBOX_V /** * clkinv: Clock tree inverter. * * Verilog stub definition (black box with power pins). * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_hd__clkinv ( Y , A , VPWR, VGND, VPB , VNB ); output Y ; input A ; input VPWR; input VGND; input VPB ; input VNB ; endmodule `default_nettype wire `endif // SKY130_FD_SC_HD__CLKINV_PP_BLACKBOX_V
module main( // clocks input fclk, output clkz_out, input clkz_in, // z80 input iorq_n, input mreq_n, input rd_n, input wr_n, input m1_n, input rfsh_n, input int_n, input nmi_n, input wait_n, output res, inout [7:0] d, output [15:0] a, // zxbus and related output csrom, output romoe_n, output romwe_n, output rompg0_n, output dos_n, // aka rompg1 output rompg2, output rompg3, output rompg4, input iorqge1, input iorqge2, output iorq1_n, output iorq2_n, // DRAM inout [15:0] rd, output [9:0] ra, output rwe_n, output rucas_n, output rlcas_n, output rras0_n, output rras1_n, // video output [1:0] vred, output [1:0] vgrn, output [1:0] vblu, output vhsync, output vvsync, output vcsync, // AY control and audio/tape input ay_clk, output ay_bdir, output ay_bc1, output reg beep, // IDE input [2:0] ide_a, input [15:0] ide_d, output ide_dir, input ide_rdy, output ide_cs0_n, output ide_cs1_n, output ide_rs_n, output ide_rd_n, output ide_wr_n, // VG93 and diskdrive output reg vg_clk, output vg_cs_n, output vg_res_n, input vg_hrdy, input vg_rclk, input vg_rawr, input [1:0] vg_a, // disk drive selection input vg_wrd, input vg_side, input step, input vg_sl, input vg_sr, input vg_tr43, input rdat_b_n, input vg_wf_de, input vg_drq, input vg_irq, input vg_wd, // serial links (atmega-fpga, sdcard) output sdcs_n, output sddo, output sdclk, input sddi, input spics_n, input spick, input spido, output spidi, output reg spiint_n ); //--Dummy---------------------------------------------------------------------- assign iorq1_n = 1'b1; assign iorq2_n = 1'b1; assign res = 1'b1; assign ay_bdir = 1'b0; assign ay_bc1 = 1'b0; assign vg_cs_n = 1'b1; assign vg_res_n = 1'b0; assign ide_dir = 1'b1; assign ide_rs_n = 1'b0; assign ide_cs0_n = 1'b1; assign ide_cs1_n = 1'b1; assign ide_rd_n = 1'b1; assign ide_wr_n = 1'b1; assign a[15:14] = 2'b00; //--INT--------------------------------------------------------------------------- reg enable_covox_int; initial enable_covox_int = 1'b0; reg enable_frame_int; initial enable_frame_int = 1'b0; always @(posedge fclk) begin if ( enable_covox_int ) spiint_n <= cvx_ptr_diff[3]|main_osc[7]; else if ( enable_frame_int ) spiint_n <= vtxtscr; else spiint_n <= 1'b1; end //--clocks--Z80_clk--VG_clk--COVOX--------------------------------------------- reg [9:0] main_osc; reg [2:0] vgclk_div7; reg [7:0] covox [15:0]; initial covox[0] = 8'h7f; reg [8:0] qe; initial qe = 9'h0ff; reg [3:0] cvx_ptr_out; initial cvx_ptr_out = 4'd0; reg [3:0] cvx_ptr_in; initial cvx_ptr_in = 4'd0; wire [3:0] cvx_ptr_iinc; wire [3:0] cvx_ptr_diff; assign cvx_ptr_iinc = cvx_ptr_in + 4'd1; assign cvx_ptr_diff = cvx_ptr_in - cvx_ptr_out; always @(posedge fclk) begin // if ( { 1'b1, covox[cvx_ptr_out] } >= qe ) begin beep <= 1'b1; qe <= 9'h1ff - { 1'b1, covox[cvx_ptr_out] } + qe; end else begin beep <= 1'b0; qe <= 9'h000 - { 1'b1, covox[cvx_ptr_out] } + qe; end // if ( main_osc[7:0] == 8'hff ) begin if ( cvx_ptr_in !== cvx_ptr_out ) cvx_ptr_out <= cvx_ptr_out + 4'd1; end // if ( main_osc[1:0]==2'b00 ) begin if ( vgclk_div7[2:1] == 2'b11 ) begin vgclk_div7 <= 3'd0; vg_clk <= ~vg_clk; end else vgclk_div7 <= vgclk_div7 + 3'd1; end // main_osc <= main_osc + 10'd1; // end assign clkz_out = main_osc[2]; // 3.5 MHz //--Video---------------------------------------------------------------------- // character image - 6x8 // character size - 6x10 // col x row - 53x25 (318x250) // fullscreen test - 360x288 localparam HTXTS_END = 9'd416; localparam CSYNC_CUT = 9'd415; localparam CSYNC_CUT2 = 9'd394; // 9'd395; // 9'd382; localparam HSYNC_BEG = 9'd0; localparam HSYNC_BEG2 = 9'd447; localparam HSYNC_END = 9'd33; localparam HSYNC_END2 = 9'd52; // 9'd53; localparam HTXTS_BEG = 9'd98; localparam HMAX = 9'd447; localparam VTXTS_END = 9'd293; localparam VSYNC_BEG = 9'd0; localparam VSYNC_END = 9'd2; localparam VTXTS_BEG = 9'd43; localparam VMAX = 9'd319; localparam HBORD_BEG = 9'd77; localparam HBORD_END = 9'd437; localparam VBORD_BEG = 9'd24; localparam VBORD_END = 9'd312; // GgRrBb localparam BLACK = 6'b000000; localparam GRAY_1 = 6'b010101; localparam GRAY_2 = 6'b101010; localparam WHITE = 6'b111111; localparam BLUE_3 = 6'b000011; localparam RED_3 = 6'b001100; localparam MAGENTA_3 = 6'b001111; localparam GREEN_3 = 6'b110000; localparam CYAN_3 = 6'b110011; localparam YELLOW_3 = 6'b111100; localparam BLUE_2 = 6'b000010; localparam RED_2 = 6'b001000; localparam MAGENTA_2 = 6'b001010; localparam GREEN_2 = 6'b100000; localparam CYAN_2 = 6'b100010; localparam YELLOW_2 = 6'b101000; localparam BLUE_H = 6'b010110; localparam RED_H = 6'b011001; localparam MAGENTA_H = 6'b011010; localparam GREEN_H = 6'b100101; localparam CYAN_H = 6'b100110; localparam YELLOW_H = 6'b101001; reg [8:0] hcount; initial hcount = 9'd0; reg [2:0] pixptr; reg [8:0] vcount; initial vcount = 9'd0; reg [5:0] hcharcount; wire [2:0] vcharline; reg [10:0] voffset; reg [3:0] vcharlinecount; reg hsync; initial hsync = 1'b1; reg htxtscr; initial htxtscr = 1'b0; reg vsync; initial vsync = 1'b1; reg vtxtscr; initial vtxtscr = 1'b0; reg csync; initial csync = 1'b1; wire [10:0] video_addr; wire [7:0] charcode0, charcode1, charcode2; wire [7:0] charcode; wire [7:0] attrcode0, attrcode1, attrcode2; wire [7:0] attrcode; wire [5:0] charpix; wire pixel; wire [5:0] fcolor, bcolor, image_color; reg [5:0] color; wire fontenable; reg [8:0] hmouse, vmouse; wire mouse_here, mouse_i, mouse_image, mouse_m, mouse_mask; reg vgaff, nextline; reg hbord; initial hbord = 1'b0; reg vbord; initial vbord = 1'b0; reg circle; initial circle = 1'b0; reg uhole; initial uhole = 1'b0; reg hhole; initial hhole = 1'b0; reg vhole; initial vhole = 1'b0; reg [1:0] bcdir; initial bcdir = 2'b00; reg [1:0] scdir; initial scdir = 2'b00; reg [3:0] hsetka, vsetka; reg [4:0] hchess, vchess; reg [1:0] hchss3; reg [2:0] cband; reg [6:0] bccount; reg [4:0] sccount; reg [6:0] schcnt; wire [6:0] cb_val; wire [4:0] cs_val; reg [2:0] clr3; always @(posedge fclk) begin // if ( {(main_osc[1]&scr_tv_mode),main_osc[0]}==2'h0 ) begin if ( scr_mode==2'h0 ) color <= (htxtscr & vtxtscr) ? ( (mouse_image) ? ~image_color : image_color ) : BLACK; else if ( hbord & vbord ) case ( scr_mode ) 3'h2: color <= (hchess[0]^vchess[0]) ? WHITE : BLACK; 3'h3: case (vchess) 5'd0, 5'd19: if (vsetka==5'd14) color <= GRAY_2; else if (hchess[0]) color <= WHITE; else color <= BLACK; 5'd5, 5'd6: case (cband) 3'd0: color <= GRAY_2; 3'd1: color <= YELLOW_H; 3'd2: color <= CYAN_H; 3'd3: color <= GREEN_H; 3'd4: color <= MAGENTA_H; 3'd5: color <= RED_H; 3'd6: color <= BLUE_H; 3'd7: color <= GRAY_1; endcase 5'd13, 5'd14: case (cband) 3'd0: color <= GRAY_2; 3'd1: color <= YELLOW_2; 3'd2: color <= CYAN_2; 3'd3: color <= GREEN_2; 3'd4: color <= MAGENTA_2; 3'd5: color <= RED_2; 3'd6: color <= BLUE_2; 3'd7: color <= BLACK; endcase default begin if (uhole) begin if (pixel) color <= GRAY_2; else color <= GRAY_1; end else if ( (circle) && !(hhole&vhole) ) case (vchess) 5'd2, 5'd17: if ( (hchess==5'd2) || (hchess==5'd3) || (hchess==5'd20) || (hchess==5'd21) ) begin if (hcount[0]) color <= GRAY_2; else color <= GRAY_1; end else color <= GRAY_2; 5'd3: if ( (hchess==5'd2) || ((hchess==5'd3) && (hsetka!=5'd14)) || (hchess==5'd20) || ((hchess==5'd21) && (hsetka!=5'd14)) ) begin if (hcount[0]^vcount[0]) color <= GRAY_1; else color <= GRAY_2; end else color <= GRAY_2; 5'd7: case (cband) //3'd0: color <= WHITE; 3'd1: color <= WHITE; 3'd2: color <= BLACK; 3'd3: color <= GRAY_1; 3'd4: color <= GRAY_2; 3'd5: color <= WHITE; 3'd6: color <= BLACK; //3'd7: color <= BLACK; endcase 5'd8: if (hcount[3]) color <= MAGENTA_H; else color <= GREEN_H; 5'd9, 5'd10: if ( (hcount[8]) ^ (vchess[0]) ^ ( (hchess==5'd4) && (hsetka==4'd14) ) ) color <= GRAY_2; else color <= BLACK; 5'd11: if (hcount[3]) color <= RED_H; else color <= CYAN_H; 5'd12: if (hcount[0]) color <= GRAY_2; else color <= GRAY_1; 5'd15: if ( (hchess[0]) && (schcnt==6'd63) ) color <= BLACK; else color <= GRAY_2; 5'd16: if ( (hchess==5'd2) || ((hchess==5'd3) &&(hsetka!=4'd14)) || (hchess==5'd20) || ((hchess==5'd21)&&(hsetka!=4'd14)) ) begin if (hcount[0]^vcount[0]) color <= GRAY_2; else color <= GRAY_1; end else color <= GRAY_2; default: color <= GRAY_2; endcase else color <= ( (hsetka==4'd14) || (vsetka==4'd14) ) ? GRAY_2 : GRAY_1; end endcase 3'h4: case (cband) 3'd0: color <= GRAY_2; 3'd1: color <= YELLOW_2; 3'd2: color <= CYAN_2; 3'd3: color <= GREEN_2; 3'd4: color <= MAGENTA_2; 3'd5: color <= RED_2; 3'd6: color <= BLUE_2; 3'd7: color <= BLACK; endcase 3'h5: if (vchess[4]==1'b0) begin if (vchess!=5'd15) case (cband) 3'd0: color <= GRAY_2; 3'd1: color <= YELLOW_2; 3'd2: color <= CYAN_2; 3'd3: color <= GREEN_2; 3'd4: color <= MAGENTA_2; 3'd5: color <= RED_2; 3'd6: color <= BLUE_2; 3'd7: color <= BLACK; endcase else case (cband) 3'd0: color <= BLUE_2; 3'd1: color <= BLACK; 3'd2: color <= MAGENTA_2; 3'd3: color <= BLACK; 3'd4: color <= CYAN_2; 3'd5: color <= BLACK; 3'd6: color <= GRAY_2; 3'd7: color <= BLACK; endcase end else case (cband) 3'd0: color <= WHITE; 3'd1: color <= YELLOW_2; 3'd2: color <= CYAN_2; 3'd3: color <= GREEN_2; 3'd4: color <= MAGENTA_2; 3'd5: color <= RED_2; 3'd6: color <= BLUE_2; 3'd7: color <= BLACK; endcase 3'h6: begin if ( (vcount[2:0]==3'd4) || (hcount[2:0]==3'd1) ) begin color[0] <= clr3[0]; color[1] <= clr3[0]; color[2] <= clr3[1]; color[3] <= clr3[1]; color[4] <= clr3[2]; color[5] <= clr3[2]; end else color <= BLACK; end default: color <= (hcount[0]^vcount[0]) ? WHITE : BLACK; endcase else color <= BLACK; hmouse <= hcount - scr_mouse_x; if ( ~htxtscr ) begin hcharcount <= 6'h00; pixptr <= 3'd0; end else begin if ( pixptr==3'd5 ) begin pixptr <= 3'd0; hcharcount <= hcharcount + 6'h01; end else pixptr <= pixptr + 3'd1; end if ( hcount==HMAX ) hcount <= 9'd0; else hcount <= hcount + 9'd1; if ( hcount==HTXTS_END ) htxtscr <= 1'b0; else if ( hcount==HTXTS_BEG ) htxtscr <= 1'b1; if ( hcount==HSYNC_BEG ) begin if ( scr_tv_mode ) hsync <= 1'b1; vgaff <= scr_tv_mode | ~vgaff; if ( vgaff ) begin if ( scr_tv_mode ) csync <= 1'b1; nextline <= 1'b1; end end if ( (~scr_tv_mode) && (hcount==HSYNC_BEG2) ) begin hsync <= 1'b1; if ( vgaff ) csync <= 1'b1; end if ( (~scr_tv_mode) && (hcount==HSYNC_END2) ) begin hsync <= 1'b0; if ( !vsync ) csync <= 1'b0; end if ( scr_tv_mode && (hcount==HSYNC_END) ) begin hsync <= 1'b0; if ( !vsync ) csync <= 1'b0; end if (scr_tv_mode) begin if (hcount==CSYNC_CUT) csync <= 1'b0; end else if ( (vgaff) && (hcount==CSYNC_CUT2) ) csync <= 1'b0; if ( ((hchess==5'd0) || (hchess==5'd18)) && (hsetka==4'd13) ) schcnt <= 6'd0; else if (schcnt!=6'd63) schcnt <= schcnt+6'd1; if ( hcount==HBORD_BEG ) begin hbord <= 1'b1; hsetka <= 4'd0; hchess <= 5'd0; hchss3 <= 2'd0; cband <= 3'd0; end else begin if ( hsetka==4'd14 ) begin hsetka <= 4'd0; hchess <= hchess+5'd1; if ( hchss3==2'd2 ) begin hchss3 <= 2'd0; cband <= cband+3'd1; end else hchss3 <= hchss3+2'd1; end else hsetka <= hsetka+4'd1; if ( hcount==HBORD_END ) hbord <= 1'b0; end if ( !((vcount[2:0]==3'd0)&&vgaff) && (hcount==9'd0) ) clr3 <= { clr3[1:0], clr3[2] }; else if (hcount[2:0]==3'd5) clr3 <= { clr3[1:0], clr3[2] }; end // if ( nextline ) begin nextline <= 1'b0; if ( ~vtxtscr ) begin voffset <= 11'd0; vcharlinecount <= 4'd15; end else begin if ( vcharlinecount==4'd8 ) begin voffset <= voffset + 11'd53; vcharlinecount <= 4'd15; end else vcharlinecount <= vcharlinecount + 4'd1; end if ( vcount==VMAX ) begin vcount <= 9'd0; clr3 <= 3'b001; end else vcount <= vcount + 9'd1; if ( vcount==VTXTS_END ) vtxtscr <= 1'b0; else if ( vcount==VTXTS_BEG ) vtxtscr <= 1'b1; if ( vcount==VSYNC_BEG ) vsync <= 1'b1; else if ( vcount==VSYNC_END ) vsync <= 1'b0; if ( vcount==VBORD_BEG ) begin vbord <= 1'b1; vsetka <= 4'd5; vchess <= 5'd0; circle <= 1'b0; bccount <= 7'd0; sccount <= 5'd0; bcdir <= 2'b00; scdir <= 2'b00; end else begin if (bcdir[0]) bccount <= bccount+7'd1; else if (bcdir[1]) bccount <= bccount-7'd1; if (scdir[0]) sccount <= sccount+5'd1; else if (scdir[1]) sccount <= sccount-5'd1; if ( vsetka==4'd14 ) begin vsetka <= 4'd0; vchess <= vchess+5'd1; end else begin vsetka <= vsetka+4'd1; if ( vsetka==4'd13 ) begin if (vchess==5'd1) bcdir <= 2'b01; else if (vchess==5'd9) bcdir <= 2'b10; else if (vchess==5'd17) bcdir <= 2'b00; if ( (vchess==5'd0) || (vchess==5'd14) ) scdir <= 2'b01; else if ( (vchess==5'd2) || (vchess==5'd16) ) scdir <= 2'b10; else if ( (vchess==5'd4) || (vchess==5'd18) ) scdir <= 2'b00; end end if ( vcount==VBORD_END ) vbord <= 1'b0; end vmouse <= vcount - scr_mouse_y; end // if ( (hchess==5'd2) || (hchess==5'd10) || (hchess==5'd20) ) hhole <= 1'b1; else if ( (hchess==5'd4) || (hchess==5'd14) || (hchess==5'd22) ) hhole <= 1'b0; // if ( (vchess==5'd4) && (schcnt==6'd63) ) begin if (hchess==5'd7) uhole <= 1'b1; else if (hchess==5'd17) uhole <= 1'b0; end // if (hcount==(9'd258+cb_val)) circle <= 1'b0; else if ( (schcnt==(5'd31+cs_val)) && (sccount!=5'd0) ) circle <= 1'b0; else if (hcount==(9'd257-cb_val)) circle <= 1'b1; else if ( (schcnt==(5'd30-cs_val)) && (sccount!=5'd0) ) circle <= 1'b1; // if ( (((vchess==5'd2) || (vchess==5'd16)) && (vsetka==4'd7)) || (vchess==5'd9) ) vhole <= 1'b1; else if ( (((vchess==5'd3) || (vchess==5'd17)) && (vsetka==4'd7)) || (vchess==5'd11) ) vhole <= 1'b0; // end circl_b ccb ( .in_addr(bccount), .out_word(cb_val) ); circl_s ccs ( .in_addr(sccount), .out_word(cs_val) ); lpm_rom_7x2 mouse_cursor ( .address({ vmouse[3:0], hmouse[2:0] }), .q({ mouse_i, mouse_m }) ); assign mouse_here = (hmouse[8:3] == 6'd0) && (vmouse[8:4] == 5'd0); assign mouse_mask = mouse_here & mouse_m; assign mouse_image = mouse_here & mouse_i; assign video_addr = voffset + { 4'h0, hcharcount[5:0] }; lpm_ram_dp_9x8 scrmem0 ( .data(indata), .wraddress(scr_addr[8:0]), .wren((scr_wren_c)&&(scr_addr[10:9]==2'h0)), .rdaddress(video_addr[8:0]), .q(charcode0) ); lpm_ram_dp_9x8 scrmem1 ( .data(indata), .wraddress(scr_addr[8:0]), .wren((scr_wren_c)&&(scr_addr[10:9]==2'h1)), .rdaddress(video_addr[8:0]), .q(charcode1) ); lpm_ram_dp_9x8 scrmem2 ( .data(indata), .wraddress(scr_addr[8:0]), .wren((scr_wren_c)&&(scr_addr[10:9]==2'h2)), .rdaddress(video_addr[8:0]), .q(charcode2) ); assign charcode = (video_addr[10:9]==2'h0) ? charcode0 : (video_addr[10:9]==2'h1) ? charcode1 : charcode2 ; lpm_ram_dp_9x8 attrmem0 ( .data(scr_attr), .wraddress(scr_addr[8:0]), .wren((scr_wren_a)&&(scr_addr[10:9]==2'h0)), .rdaddress(video_addr[8:0]), .q(attrcode0) ); lpm_ram_dp_9x8 attrmem1 ( .data(scr_attr), .wraddress(scr_addr[8:0]), .wren((scr_wren_a)&&(scr_addr[10:9]==2'h1)), .rdaddress(video_addr[8:0]), .q(attrcode1) ); lpm_ram_dp_9x8 attrmem2 ( .data(scr_attr), .wraddress(scr_addr[8:0]), .wren((scr_wren_a)&&(scr_addr[10:9]==2'h2)), .rdaddress(video_addr[8:0]), .q(attrcode2) ); assign attrcode = (video_addr[10:9]==2'h0) ? attrcode0 : (video_addr[10:9]==2'h1) ? attrcode1 : attrcode2 ; assign vcharline = (vcharlinecount[3]) ? ~vcharlinecount[2:0] : vcharlinecount[2:0]; lpm_rom_11x6 chargen ( .address({ charcode, vcharline }), .q(charpix) ); assign fcolor = { attrcode[2], (attrcode[2]&attrcode[3]), attrcode[1], (attrcode[1]&attrcode[3]), attrcode[0], (attrcode[0]&attrcode[3]) }; assign bcolor = { (attrcode[6]&attrcode[7]), (attrcode[6]&(~attrcode[7])), (attrcode[5]&attrcode[7]), (attrcode[5]&(~attrcode[7])), (attrcode[4]&attrcode[7]), (attrcode[4]&(~attrcode[7])) }; assign fontenable = (charcode[7:4]==4'hb)|| (charcode[7:4]==4'hc)|| (charcode[7:4]==4'hd)|| (~vcharlinecount[3]); assign pixel = ( charcode==8'hb0 ) ? ( (vcount[0]^hcount[1])&~hcount[0] ) : ( charcode==8'hb1 ) ? ( vcount[0]^hcount[0] ) : ( charcode==8'hb2 ) ? ( (vcount[0]^hcount[1])| hcount[0] ) : ( fontenable ) ? charpix[3'd5-pixptr] : 1'b0; assign image_color = (mouse_mask) ? BLACK : ( pixel ? fcolor : bcolor ) ; assign { vgrn[1:0], vred[1:0], vblu[1:0] } = color; assign vhsync = hsync; assign vvsync = vsync; assign vcsync = ~csync; //--AVRSPI--FlashROM----------------------------------------------------------- localparam TEMP_REG = 8'ha0; localparam SD_CS0 = 8'ha1; localparam SD_CS1 = 8'ha2; localparam FLASH_LOADDR = 8'ha3; localparam FLASH_MIDADDR = 8'ha4; localparam FLASH_HIADDR = 8'ha5; localparam FLASH_DATA = 8'ha6; localparam FLASH_CTRL = 8'ha7; localparam SCR_LOADDR = 8'ha8; localparam SCR_HIADDR = 8'ha9; localparam SCR_SET_ATTR = 8'haa; // çàïèñü â ATTR localparam SCR_FILL = 8'hab; // ïðåäèíêðåìåíò àäðåñà è çàïèñü â ATTR è â ïàìÿòü // (åñëè òîëüêî äåðãàòü spics_n, òî â ïàìÿòü áóäåò ïèñàòüñÿ ïðåäûäóùåå çíà÷åíèå) localparam SCR_CHAR = 8'hac; // ïðåäèíêðåìåíò àäðåñà è çàïèñü â ïàìÿòü ñèìâîëîâ è ATTR â ïàìÿòü àòðèáóòîâ // (åñëè òîëüêî äåðãàòü spics_n, òî â ïàìÿòü áóäåò ïèñàòüñÿ ïðåäûäóùèå çíà÷åíèÿ) localparam SCR_MOUSE_X = 8'had; localparam SCR_MOUSE_Y = 8'hae; localparam SCR_MODE = 8'haf; // [7] - 0=VGAmode, 1=TVmode; [2:0] - 0=TXT, èíà÷å ScrTESTs localparam MTST_CONTROL = 8'h50; // [0] - òåñò ïàìÿòè (0=ñáðîñ, 1=ðàáîòà) localparam MTST_PASS_CNT0= 8'h51; localparam MTST_PASS_CNT1= TEMP_REG; localparam MTST_FAIL_CNT0= 8'h52; localparam MTST_FAIL_CNT1= TEMP_REG; localparam COVOX = 8'h53; localparam INT_CONTROL = 8'h54; // [0] - ðàçðåøåíèå ïðåðûâàíèé îò covox-à (27343.75 Hz) // [1] - ðàçðåøåíèå êàäðîâûõ ïðåðûâàíèé (~49 Hz) reg [7:0] number; initial number = 8'hff; reg [7:0] indata; initial indata = 8'hff; reg [7:0] outdata; reg [2:0] bitptr; reg prev_spics_n; reg [18:0] flash_addr; reg flash_cs; initial flash_cs = 1'b0; reg flash_oe; initial flash_oe = 1'b0; reg flash_we; initial flash_we = 1'b0; reg flash_postinc; initial flash_postinc = 1'b0; reg [7:0] flash_data_out; reg [10:0] scr_addr; initial scr_addr = 11'h000; reg [7:0] scr_attr; initial scr_attr = 8'h0f; reg scr_wren_c; initial scr_wren_c = 1'b0; reg scr_wren_a; initial scr_wren_a = 1'b0; reg [8:0] scr_mouse_x; initial scr_mouse_x = 9'd0; reg [8:0] scr_mouse_y; initial scr_mouse_y = 9'd0; reg scr_tv_mode; initial scr_tv_mode = 1'b1; reg [2:0] scr_mode; initial scr_mode = 3'b0; wire spicsn_rising; wire spicsn_falling; wire sd_selected; reg cs_trg; reg [7:0] temp_reg; always @(posedge spick) begin if ( spics_n ) number <= { number[6:0], spido }; else indata <= { indata[6:0], spido }; end always @(negedge spick or posedge spics_n) begin if ( spics_n ) bitptr <= 3'b111; else bitptr <= bitptr - 3'b001; end always @(posedge fclk) begin // if ( spicsn_rising ) begin // cs_trg <= 1'b1; // case ( number ) FLASH_LOADDR: flash_addr[7:0] <= indata; FLASH_MIDADDR: flash_addr[15:8] <= indata; FLASH_HIADDR: flash_addr[18:16] <= indata[2:0]; FLASH_DATA: begin flash_data_out <= indata; if (flash_postinc) flash_addr[13:0] <= flash_addr[13:0] + 14'd1; end FLASH_CTRL: begin flash_cs <= indata[0]; flash_oe <= indata[1]; flash_we <= indata[2]; flash_postinc <= indata[3]; end SCR_LOADDR: scr_addr[7:0] <= indata; SCR_HIADDR: scr_addr[10:8] <= indata[2:0]; SCR_SET_ATTR: scr_attr <= indata; SCR_FILL: begin scr_attr <= indata; scr_wren_a <= 1'b1; end SCR_CHAR: begin scr_wren_c <= 1'b1; scr_wren_a <= 1'b1; end TEMP_REG: temp_reg <= indata; SCR_MOUSE_X: scr_mouse_x <= { temp_reg[0], indata }; SCR_MOUSE_Y: scr_mouse_y <= { temp_reg[0], indata }; SCR_MODE: begin scr_tv_mode <= indata[7]; scr_mode <= indata[2:0]; end MTST_CONTROL: mtst_run <= indata[0]; COVOX: begin covox[cvx_ptr_iinc] <= indata; cvx_ptr_in <= cvx_ptr_iinc; end INT_CONTROL: begin enable_covox_int <= indata[0]; enable_frame_int <= indata[1]; end endcase // end else begin // scr_wren_c <= 1'b0; scr_wren_a <= 1'b0; // if ( spicsn_falling ) begin // cs_trg <= 1'b0; // case ( number ) SCR_SET_ATTR: outdata <= ~scr_attr; // for SPI testing SCR_FILL: begin outdata <= 8'hff; scr_addr <= scr_addr + 11'd1; end SCR_CHAR: begin outdata <= 8'hff; scr_addr <= scr_addr + 11'd1; end FLASH_DATA: outdata <= d; MTST_PASS_CNT0:begin outdata <= mtst_pass_counter[7:0]; temp_reg <= mtst_pass_counter[15:8]; end MTST_FAIL_CNT0:begin outdata <= mtst_fail_counter[7:0]; temp_reg <= mtst_fail_counter[15:8]; end COVOX: outdata <= { 4'd0, cvx_ptr_diff }; TEMP_REG: outdata <= temp_reg; // read after MTST_PASS_CNT0, MTST_FAIL_CNT0 default: outdata <= 8'hff; endcase // end // end // prev_spics_n <= spics_n; // end assign spicsn_rising = ( { cs_trg, prev_spics_n, spics_n } == 3'b011 ); assign spicsn_falling = ( { cs_trg, prev_spics_n, spics_n } == 3'b100 ); assign sd_selected = ( ( (number==SD_CS0) || (number==SD_CS1) ) && (~spics_n) ); assign spidi = sd_selected ? sddi : outdata[bitptr]; assign sddo = sd_selected ? spido : 1'b1; assign sdclk = sd_selected ? spick : 1'b0; assign sdcs_n = !( (number==SD_CS0) && (~spics_n) ); assign a[13:0] = flash_addr[13:0]; assign rompg0_n = ~flash_addr[14]; assign { rompg4, rompg3, rompg2, dos_n } = flash_addr[18:15]; assign csrom = flash_cs; assign romoe_n = ~flash_oe; assign romwe_n = ~flash_we; assign d = flash_oe ? 8'bZZZZZZZZ : flash_data_out; //----------------------------------------------------------------------------- reg mtst_run; initial mtst_run = 1'b0; wire [15:0] mtst_pass_counter; wire [15:0] mtst_fail_counter; mem_tester mtst( .clk(fclk), .rst_n(mtst_run), .pass_counter(mtst_pass_counter), .fail_counter(mtst_fail_counter), .DRAM_DQ(rd), .DRAM_MA(ra), .DRAM_RAS0_N(rras0_n), .DRAM_RAS1_N(rras1_n), .DRAM_LCAS_N(rlcas_n), .DRAM_UCAS_N(rucas_n), .DRAM_WE_N(rwe_n) ); //----------------------------------------------------------------------------- endmodule