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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX4_2_V
`define SKY130_FD_SC_MS__MUX4_2_V
/**
* mux4: 4-input multiplexer.
*
* Verilog wrapper for mux4 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__mux4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__mux4_2 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__mux4_2 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX4_2_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// A test of the +1364-1995ext+ and +systemverilogext+ flags.
//
// This source code contains constructs that are valid in SystemVerilog 2009
// but not in Verilog 1995. So it should fail if we set the language to be
// Verilog 1995, but not SystemVerilog 2009.
//
// Compile only test, so no need for "All Finished" output.
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jeremy Bennett.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [1:0] res;
// Instantiate the test
test test_i (/*AUTOINST*/
// Outputs
.res (res),
// Inputs
.clk (clk),
.in (1'b1));
endmodule
module test (// Outputs
res,
// Inputs
clk,
in
);
output [1:0] res;
input clk;
input in;
// This is a SystemVerilog 2009 only test
generate
genvar i;
for (i=0; i<2; i=i+1) begin
always @(posedge clk) begin
unique0 case (i)
0: res[0:0] <= in;
1: res[1:1] <= in;
endcase
end
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_data_broadcast(
dq_data_in,
dm_data_in,
dq_data_out,
dm_data_out
);
parameter NUMBER_OF_DQS_GROUPS = "";
parameter NUMBER_OF_DQ_PER_DQS = "";
parameter AFI_RATIO = "";
parameter MEM_DM_WIDTH = "";
localparam NUMBER_OF_DQ_BITS = NUMBER_OF_DQS_GROUPS * NUMBER_OF_DQ_PER_DQS;
localparam NUMBER_OF_WORDS = 2 * AFI_RATIO;
input [NUMBER_OF_DQ_PER_DQS * NUMBER_OF_WORDS - 1 : 0] dq_data_in;
input [NUMBER_OF_WORDS - 1 : 0] dm_data_in;
output [NUMBER_OF_DQ_BITS * NUMBER_OF_WORDS - 1 : 0] dq_data_out;
output [MEM_DM_WIDTH * 2 * AFI_RATIO - 1 : 0] dm_data_out;
genvar gr, wr, dmbit;
generate
for(wr = 0; wr < NUMBER_OF_WORDS; wr = wr + 1)
begin : word
for(gr = 0; gr < NUMBER_OF_DQS_GROUPS; gr = gr + 1)
begin : group
assign dq_data_out[wr * NUMBER_OF_DQ_BITS + (gr + 1) * NUMBER_OF_DQ_PER_DQS - 1 : wr * NUMBER_OF_DQ_BITS + gr * NUMBER_OF_DQ_PER_DQS] =
dq_data_in[(wr + 1) * NUMBER_OF_DQ_PER_DQS - 1 : wr * NUMBER_OF_DQ_PER_DQS];
end
for(dmbit = 0; dmbit < MEM_DM_WIDTH; dmbit = dmbit + 1)
begin : data_mask_bit
assign dm_data_out[wr * MEM_DM_WIDTH + dmbit] = dm_data_in[wr];
end
end
endgenerate
`ifdef ADD_UNIPHY_SIM_SVA
assert property (@dm_data_in NUMBER_OF_DQS_GROUPS == MEM_DM_WIDTH) else
$error("%t, [DATA BROADCAST ASSERT] NUMBER_OF_DQS_GROUPS and MEM_DM_WIDTH mismatch, NUMBER_OF_DQS_GROUPS = %d, MEM_DM_WIDTH = %d", $time, NUMBER_OF_DQS_GROUPS, MEM_DM_WIDTH);
`endif
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module sounder_rx(clk_i,rst_i,ena_i,sum_strobe_i,ref_strobe_i,
mask_i,degree_i,rx_in_i_i,rx_in_q_i,rx_i_o,rx_q_o);
input clk_i; // Master clock
input rst_i; // Subsystem reset
input ena_i; // Subsystem enable
input sum_strobe_i; // Strobe on last sample per period
input ref_strobe_i; // PN code reference retarded one sample per period
input [15:0] mask_i; // PN code LFSR mask
input [4:0] degree_i; // PN code LFSR sequency degree
input [15:0] rx_in_i_i; // I channel on receive
input [15:0] rx_in_q_i; // Q channel on receive
output [15:0] rx_i_o; // I channel of impulse response
output [15:0] rx_q_o; // Q channel of impulse response
reg [31:0] sum_i, sum_q;
reg [31:0] total_i, total_q;
wire [31:0] i_ext, q_ext;
sign_extend #(16,32) i_extender(rx_in_i_i, i_ext);
sign_extend #(16,32) q_extender(rx_in_q_i, q_ext);
wire pn_ref;
lfsr ref_code
( .clk_i(clk_i),.rst_i(rst_i),.ena_i(ena_i),.strobe_i(ref_strobe_i),.mask_i(mask_i),.pn_o(pn_ref) );
wire [31:0] prod_i = pn_ref ? i_ext : -i_ext;
wire [31:0] prod_q = pn_ref ? q_ext : -q_ext;
always @(posedge clk_i)
if (rst_i | ~ena_i)
begin
sum_i <= #5 0;
sum_q <= #5 0;
total_i <= #5 0;
total_q <= #5 0;
end
else
if (sum_strobe_i)
begin
total_i <= #5 sum_i;
total_q <= #5 sum_q;
sum_i <= #5 prod_i;
sum_q <= #5 prod_q;
end
else
begin
sum_i <= #5 sum_i + prod_i;
sum_q <= #5 sum_q + prod_q;
end
wire [5:0] offset = (5'd16-degree_i);
wire [31:0] scaled_i = total_i << offset;
wire [31:0] scaled_q = total_q << offset;
assign rx_i_o = scaled_i[31:16];
assign rx_q_o = scaled_q[31:16];
endmodule // sounder_rx
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire pick1 = crc[0];
wire [13:0][1:0] data1 = crc[27+1:1];
wire [3:0][2:0][1:0] data2 = crc[23+29:29];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic [15:0] [1:0] datao; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.datao (datao/*[15:0][1:0]*/),
// Inputs
.pick1 (pick1),
.data1 (data1/*[13:0][1:0]*/),
.data2 (data2/*[2:0][3:0][1:0]*/));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, datao};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h3ff4bf0e6407b281
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test
(
input logic pick1,
input logic [13:0] [1:0] data1, // 14 x 2 = 28 bits
input logic [ 3:0] [2:0] [1:0] data2, // 4 x 3 x 2 = 24 bits
output logic [15:0] [1:0] datao // 16 x 2 = 32 bits
);
// verilator lint_off WIDTH
always_comb datao[13: 0] // 28 bits
= (pick1)
? {data1} // 28 bits
: {'0, data2}; // 25-28 bits, perhaps not legal as '0 is unsized
// verilator lint_on WIDTH
always_comb datao[15:14] = '0;
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-------------------------------------------------------------------
// Filename : md_ram.v
// Author : Yanheng Lu
// Created : 2014-09-01
// Description : mode decision(pre_intra) 8x8 ram
//------------------------------------------------------------------
module md_ram (
clk ,
wdata ,
waddr ,
we ,
rd ,
raddr ,
rdata
);
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
input clk ;
input [31:0] wdata ;
input [3:0] waddr ;
input we ;
input rd ;
input [3:0] raddr ;
output [31:0] rdata ;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
rf_2p #(.Addr_Width(4), .Word_Width(32))
rf_2p_32x16 (
.clka ( clk ),
.cena_i ( ~rd ),
.addra_i ( raddr ),
.dataa_o ( rdata ),
.clkb ( clk ),
.cenb_i ( ~we ),
.wenb_i ( ~we ),
.addrb_i ( waddr ),
.datab_i ( wdata )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__MUX2_PP_BLACKBOX_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__mux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2_PP_BLACKBOX_V
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
// megafunction wizard: %DDR3 SDRAM High Performance Controller v10.0%
//GENERATION: XML
//Generated by DDR3 SDRAM High Performance Controller 10.0
//IPFS_FILES:
//RELATED_FILES:
//<< MEGAWIZARD PARSE FILE DDR310.0
//.
//<< START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top (
// inputs:
clock_source,
global_reset_n,
// outputs:
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
mem_odt,
mem_ras_n,
mem_reset_n,
mem_we_n,
pnf,
pnf_per_byte,
test_complete,
test_status
)
;
output [ 13: 0] mem_addr;
output [ 2: 0] mem_ba;
output mem_cas_n;
output [ 0: 0] mem_cke;
inout [ 0: 0] mem_clk;
inout [ 0: 0] mem_clk_n;
output [ 0: 0] mem_cs_n;
output [ 3: 0] mem_dm;
inout [ 31: 0] mem_dq;
inout [ 3: 0] mem_dqs;
inout [ 3: 0] mem_dqsn;
output [ 0: 0] mem_odt;
output mem_ras_n;
output mem_reset_n;
output mem_we_n;
output pnf;
output [ 15: 0] pnf_per_byte;
output test_complete;
output [ 7: 0] test_status;
input clock_source;
input global_reset_n;
wire [ 0: 0] cs_n;
wire dll_reference_clk_sig;
wire [ 5: 0] dqs_delay_ctrl_export_sig;
wire local_burstbegin_sig;
wire [ 13: 0] mem_addr;
wire mem_aux_full_rate_clk;
wire mem_aux_half_rate_clk;
wire [ 2: 0] mem_ba;
wire mem_cas_n;
wire [ 0: 0] mem_cke;
wire [ 0: 0] mem_clk;
wire [ 0: 0] mem_clk_n;
wire [ 0: 0] mem_cs_n;
wire [ 3: 0] mem_dm;
wire [ 31: 0] mem_dq;
wire [ 3: 0] mem_dqs;
wire [ 3: 0] mem_dqsn;
wire [ 24: 0] mem_local_addr;
wire [ 15: 0] mem_local_be;
wire [ 9: 0] mem_local_col_addr;
wire mem_local_cs_addr;
wire [127: 0] mem_local_rdata;
wire mem_local_rdata_valid;
wire mem_local_read_req;
wire mem_local_ready;
wire [ 5: 0] mem_local_size;
wire [127: 0] mem_local_wdata;
wire mem_local_write_req;
wire [ 0: 0] mem_odt;
wire mem_ras_n;
wire mem_reset_n;
wire mem_we_n;
wire phy_clk;
wire pnf;
wire [ 15: 0] pnf_per_byte;
wire reset_phy_clk_n;
wire test_complete;
wire [ 7: 0] test_status;
wire tie_high;
wire tie_low;
//
//
assign mem_cs_n = cs_n;
//<< END MEGAWIZARD INSERT MODULE
assign tie_high = 1'b1;
assign tie_low = 1'b0;
//<< START MEGAWIZARD INSERT WRAPPER_NAME
ddr3_int ddr3_int_inst
(
.aux_full_rate_clk (mem_aux_full_rate_clk),
.aux_half_rate_clk (mem_aux_half_rate_clk),
.dll_reference_clk (dll_reference_clk_sig),
.dqs_delay_ctrl_export (dqs_delay_ctrl_export_sig),
.global_reset_n (global_reset_n),
.local_address (mem_local_addr),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_init_done (),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_refresh_ack (),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_wdata_req (),
.local_write_req (mem_local_write_req),
.mem_addr (mem_addr[13 : 0]),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (cs_n),
.mem_dm (mem_dm[3 : 0]),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs[3 : 0]),
.mem_dqsn (mem_dqsn[3 : 0]),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_reset_n (mem_reset_n),
.mem_we_n (mem_we_n),
.phy_clk (phy_clk),
.pll_ref_clk (clock_source),
.reset_phy_clk_n (reset_phy_clk_n),
.reset_request_n (),
.soft_reset_n (tie_high)
);
//<< END MEGAWIZARD INSERT WRAPPER_NAME
//<< START MEGAWIZARD INSERT CS_ADDR_MAP
//connect up the column address bits, dropping 2 bits from example driver output because of 4:1 data rate
assign mem_local_addr[7 : 0] = mem_local_col_addr[9 : 2];
//<< END MEGAWIZARD INSERT CS_ADDR_MAP
//<< START MEGAWIZARD INSERT EXAMPLE_DRIVER
//Self-test, synthesisable code to exercise the DDR SDRAM Controller
ddr3_int_example_driver driver
(
.clk (phy_clk),
.local_bank_addr (mem_local_addr[24 : 22]),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_col_addr (mem_local_col_addr),
.local_cs_addr (mem_local_cs_addr),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_row_addr (mem_local_addr[21 : 8]),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_write_req (mem_local_write_req),
.pnf_per_byte (pnf_per_byte[15 : 0]),
.pnf_persist (pnf),
.reset_n (reset_phy_clk_n),
.test_complete (test_complete),
.test_status (test_status)
);
//<< END MEGAWIZARD INSERT EXAMPLE_DRIVER
//<< START MEGAWIZARD INSERT DLL
//<< END MEGAWIZARD INSERT DLL
//<< START MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< END MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< start europa
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/12/2016 06:26:54 PM
// Design Name:
// Module Name: shift_mux_array
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module shift_mux_array
#(parameter SWR=26, parameter LEVEL=5)
(
input wire [SWR-1:0] Data_i,
input wire select_i,
input wire bit_shift_i,
output wire [SWR-1:0] Data_o
);
genvar j;
generate for (j=0; j<=SWR-1 ; j=j+1) begin
localparam sh=(2**LEVEL)+j; //value for second mux input. It changes in exponentation by 2 for each level
case (sh>SWR-1)
1'b1:begin
Multiplexer_AC #(.W(1)) rotate_mux(
.ctrl(select_i),
.D0 (Data_i[j]),
.D1 (bit_shift_i),
.S (Data_o[j])
);
end
1'b0:begin
Multiplexer_AC #(.W(1)) rotate_mux(
.ctrl(select_i),
.D0 (Data_i[j]),
.D1 (Data_i[sh]),
.S (Data_o[j])
);
end
endcase
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKBUF_2_V
`define SKY130_FD_SC_HDLL__CLKBUF_2_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkbuf_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkbuf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKBUF_2_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.6
// \ \ Application : MIG
// / / Filename : memc_ui_top_std.v
// /___/ /\ Date Last Modified : $Date: 2011/06/17 11:11:25 $
// \ \ / \ Date Created : Fri Oct 08 2010
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM & DDR3 SDRAM
// Purpose :
// Top level memory interface block. Instantiates a clock and
// reset generator, the memory controller, the phy and the
// user interface blocks.
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
(* X_CORE_INFO = "mig_7series_v2_3_ddr3_7Series, 2013.4" , CORE_GENERATION_INFO = "ddr3_7Series,mig_7series_v2_3,{LANGUAGE=Verilog, SYNTHESIS_TOOL=Vivado, LEVEL=CONTROLLER, AXI_ENABLE=0, NO_OF_CONTROLLERS=1, INTERFACE_TYPE=DDR3, AXI_ENABLE=0, CLK_PERIOD=1250, PHY_RATIO=4, CLKIN_PERIOD=5000, VCCAUX_IO=2.0V, MEMORY_TYPE=SODIMM, MEMORY_PART=mt8ktf51264hz-1g6, DQ_WIDTH=64, ECC=OFF, DATA_MASK=1, ORDERING=NORM, BURST_MODE=8, BURST_TYPE=SEQ, CA_MIRROR=OFF, OUTPUT_DRV=HIGH, USE_CS_PORT=1, USE_ODT_PORT=1, RTT_NOM=40, MEMORY_ADDRESS_MAP=BANK_ROW_COLUMN, REFCLK_FREQ=200, DEBUG_PORT=OFF, INTERNAL_VREF=0, SYSCLK_TYPE=DIFFERENTIAL, REFCLK_TYPE=USE_SYSTEM_CLOCK}" *)
module mig_7series_v2_3_memc_ui_top_std #
(
parameter TCQ = 100,
parameter DDR3_VDD_OP_VOLT = "135", // Voltage mode used for DDR3
parameter PAYLOAD_WIDTH = 64,
parameter ADDR_CMD_MODE = "UNBUF",
parameter AL = "0", // Additive Latency option
parameter BANK_WIDTH = 3, // # of bank bits
parameter BM_CNT_WIDTH = 2, // Bank machine counter width
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory
parameter CL = 5,
parameter COL_WIDTH = 12, // column address width
parameter CMD_PIPE_PLUS1 = "ON", // add pipeline stage between MC and PHY
parameter CS_WIDTH = 1, // # of unique CS outputs
parameter CKE_WIDTH = 1, // # of cke outputs
parameter CWL = 5,
parameter DATA_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of DM (data mask)
parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH))
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ECC = "OFF",
parameter ECC_WIDTH = 8,
parameter ECC_TEST = "OFF",
parameter MC_ERR_ADDR_WIDTH = 31,
parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides
parameter nAL = 0, // Additive latency (in clk cyc)
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter ORDERING = "NORM",
parameter IBUF_LPWR_MODE = "OFF",
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP0 = "IODELAY_MIG0",
parameter IODELAY_GRP1 = "IODELAY_MIG1",
parameter FPGA_SPEED_GRADE = 1,
parameter OUTPUT_DRV = "HIGH",
parameter REG_CTRL = "OFF",
parameter RTT_NOM = "60",
parameter RTT_WR = "120",
parameter STARVE_LIMIT = 2,
parameter tCK = 2500, // pS
parameter tCKE = 10000, // pS
parameter tFAW = 40000, // pS
parameter tPRDI = 1_000_000, // pS
parameter tRAS = 37500, // pS
parameter tRCD = 12500, // pS
parameter tREFI = 7800000, // pS
parameter tRFC = 110000, // pS
parameter tRP = 12500, // pS
parameter tRRD = 10000, // pS
parameter tRTP = 7500, // pS
parameter tWTR = 7500, // pS
parameter tZQI = 128_000_000, // nS
parameter tZQCS = 64, // CKs
parameter USER_REFRESH = "OFF", // Whether user manages REF
parameter TEMP_MON_EN = "ON", // Enable/Disable tempmon
parameter WRLVL = "OFF",
parameter DEBUG_PORT = "OFF",
parameter CAL_WIDTH = "HALF",
parameter RANK_WIDTH = 1,
parameter RANKS = 4,
parameter ODT_WIDTH = 1,
parameter ROW_WIDTH = 16, // DRAM address bus width
parameter ADDR_WIDTH = 32,
parameter APP_MASK_WIDTH = 8,
parameter APP_DATA_WIDTH = 64,
parameter [3:0] BYTE_LANES_B0 = 4'b1111,
parameter [3:0] BYTE_LANES_B1 = 4'b1111,
parameter [3:0] BYTE_LANES_B2 = 4'b1111,
parameter [3:0] BYTE_LANES_B3 = 4'b1111,
parameter [3:0] BYTE_LANES_B4 = 4'b1111,
parameter [3:0] DATA_CTL_B0 = 4'hc,
parameter [3:0] DATA_CTL_B1 = 4'hf,
parameter [3:0] DATA_CTL_B2 = 4'hf,
parameter [3:0] DATA_CTL_B3 = 4'h0,
parameter [3:0] DATA_CTL_B4 = 4'h0,
parameter [47:0] PHY_0_BITLANES = 48'h0000_0000_0000,
parameter [47:0] PHY_1_BITLANES = 48'h0000_0000_0000,
parameter [47:0] PHY_2_BITLANES = 48'h0000_0000_0000,
// control/address/data pin mapping parameters
parameter [143:0] CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter [191:0] ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter [35:0] BANK_MAP = 36'h000_000_000,
parameter [11:0] CAS_MAP = 12'h000,
parameter [7:0] CKE_ODT_BYTE_MAP = 8'h00,
parameter [95:0] CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter [119:0] CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter [11:0] PARITY_MAP = 12'h000,
parameter [11:0] RAS_MAP = 12'h000,
parameter [11:0] WE_MAP = 12'h000,
parameter [143:0] DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter [95:0] DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [107:0] MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter [107:0] MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter [7:0] SLOT_0_CONFIG = 8'b0000_0001,
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter [15:0] CALIB_ROW_ADD = 16'h0000, // Calibration row address
parameter [11:0] CALIB_COL_ADD = 12'h000, // Calibration column address
parameter [2:0] CALIB_BA_ADD = 3'h0, // Calibration bank address
parameter SIM_BYPASS_INIT_CAL = "OFF",
parameter REFCLK_FREQ = 300.0,
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter IDELAY_ADJ = "ON", //ON : IDELAY-1, OFF: No change
parameter FINE_PER_BIT = "ON", //ON : Use per bit calib for complex rdlvl
parameter CENTER_COMP_MODE = "ON", //ON: use PI stg2 tap compensation
parameter PI_VAL_ADJ = "ON", //ON: PI stg2 tap -1 for centering
parameter TAPSPERKCLK = 56
)
(
// Clock and reset ports
input clk,
input [1:0] clk_ref,
input mem_refclk ,
input freq_refclk ,
input pll_lock,
input sync_pulse ,
input mmcm_ps_clk,
input poc_sample_pd,
input rst,
// memory interface ports
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQS_WIDTH-1:0] ddr_dqs,
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CK_WIDTH-1:0] ddr_ck_n,
output [CK_WIDTH-1:0] ddr_ck,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_ras_n,
output ddr_reset_n,
output ddr_parity,
output ddr_we_n,
output [BM_CNT_WIDTH-1:0] bank_mach_next,
// user interface ports
input [ADDR_WIDTH-1:0] app_addr,
input [2:0] app_cmd,
input app_en,
input app_hi_pri,
input [APP_DATA_WIDTH-1:0] app_wdf_data,
input app_wdf_end,
input [APP_MASK_WIDTH-1:0] app_wdf_mask,
input app_wdf_wren,
input app_correct_en_i,
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc,
output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err,
output [APP_DATA_WIDTH-1:0] app_rd_data,
output app_rd_data_end,
output app_rd_data_valid,
output app_rdy,
output app_wdf_rdy,
input app_sr_req,
output app_sr_active,
input app_ref_req,
output app_ref_ack,
input app_zq_req,
output app_zq_ack,
// temperature monitor ports
input [11:0] device_temp,
//phase shift clock control
output psen,
output psincdec,
input psdone,
// debug logic ports
input dbg_idel_down_all,
input dbg_idel_down_cpt,
input dbg_idel_up_all,
input dbg_idel_up_cpt,
input dbg_sel_all_idel_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [1:0] dbg_rdlvl_start,
output [5:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output dbg_wrlvl_start,
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output init_calib_complete,
input dbg_sel_pi_incdec,
input dbg_sel_po_incdec,
input [DQS_CNT_WIDTH:0] dbg_byte_sel,
input dbg_pi_f_inc,
input dbg_pi_f_dec,
input dbg_po_f_inc,
input dbg_po_f_stg23_sel,
input dbg_po_f_dec,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
output dbg_rddata_valid,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output ref_dll_lock,
input rst_phaser_ref,
input iddr_rst,
output [6*RANKS-1:0] dbg_rd_data_offset,
output [255:0] dbg_calib_top,
output [255:0] dbg_phy_wrlvl,
output [255:0] dbg_phy_rdlvl,
output [99:0] dbg_phy_wrcal,
output [255:0] dbg_phy_init,
output [255:0] dbg_prbs_rdlvl,
output [255:0] dbg_dqs_found_cal,
output [5:0] dbg_pi_counter_read_val,
output [8:0] dbg_po_counter_read_val,
output dbg_pi_phaselock_start,
output dbg_pi_phaselocked_done,
output dbg_pi_phaselock_err,
output dbg_pi_dqsfound_start,
output dbg_pi_dqsfound_done,
output dbg_pi_dqsfound_err,
output dbg_wrcal_start,
output dbg_wrcal_done,
output dbg_wrcal_err,
output [11:0] dbg_pi_dqs_found_lanes_phy4lanes,
output [11:0] dbg_pi_phase_locked_phy4lanes,
output [6*RANKS-1:0] dbg_calib_rd_data_offset_1,
output [6*RANKS-1:0] dbg_calib_rd_data_offset_2,
output [5:0] dbg_data_offset,
output [5:0] dbg_data_offset_1,
output [5:0] dbg_data_offset_2,
output dbg_oclkdelay_calib_start,
output dbg_oclkdelay_calib_done,
output [255:0] dbg_phy_oclkdelay_cal,
output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_final_dqs_tap_cnt_r,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps
);
localparam IODELAY_GRP = (tCK <= 1500)? IODELAY_GRP1 : IODELAY_GRP0;
// wire [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r;
// wire [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps;
// wire [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps;
wire correct_en;
wire [2*nCK_PER_CLK-1:0] raw_not_ecc;
wire [2*nCK_PER_CLK-1:0] ecc_single;
wire [2*nCK_PER_CLK-1:0] ecc_multiple;
wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
wire [DQ_WIDTH/8-1:0] fi_xor_we;
wire [DQ_WIDTH-1:0] fi_xor_wrdata;
wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
wire wr_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire rd_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
wire accept;
wire accept_ns;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
wire rd_data_end;
wire use_addr;
wire size;
wire [ROW_WIDTH-1:0] row;
wire [RANK_WIDTH-1:0] rank;
wire hi_priority;
wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;
wire [COL_WIDTH-1:0] col;
wire [2:0] cmd;
wire [BANK_WIDTH-1:0] bank;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH/8-1:0] wr_data_mask;
wire app_sr_req_i;
wire app_sr_active_i;
wire app_ref_req_i;
wire app_ref_ack_i;
wire app_zq_req_i;
wire app_zq_ack_i;
wire rst_tg_mc;
wire error;
wire init_wrcal_complete;
reg reset /* synthesis syn_maxfan = 10 */;
//***************************************************************************
always @(posedge clk)
reset <= #TCQ (rst | rst_tg_mc);
assign fi_xor_we = {DQ_WIDTH/8{1'b0}} ;
assign fi_xor_wrdata = {DQ_WIDTH{1'b0}} ;
mig_7series_v2_3_mem_intfc #
(
.TCQ (TCQ),
.DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.AL (AL),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CA_MIRROR (CA_MIRROR),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.DM_WIDTH (DM_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.nAL (nAL),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.CL (CL),
.CWL (CWL),
.tCK (tCK),
.tCKE (tCKE),
.tFAW (tFAW),
.tPRDI (tPRDI),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.USER_REFRESH (USER_REFRESH),
.TEMP_MON_EN (TEMP_MON_EN),
.WRLVL (WRLVL),
.DEBUG_PORT (DEBUG_PORT),
.CAL_WIDTH (CAL_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CKE_ODT_AUX (CKE_ODT_AUX),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.STARVE_LIMIT (STARVE_LIMIT),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.IDELAY_ADJ (IDELAY_ADJ),
.FINE_PER_BIT (FINE_PER_BIT),
.CENTER_COMP_MODE (CENTER_COMP_MODE),
.PI_VAL_ADJ (PI_VAL_ADJ),
.TAPSPERKCLK (TAPSPERKCLK)
)
mem_intfc0
(
.clk (clk),
.clk_ref (tCK <= 1500 ? clk_ref[1] : clk_ref[0]),
.mem_refclk (mem_refclk), //memory clock
.freq_refclk (freq_refclk),
.pll_lock (pll_lock),
.sync_pulse (sync_pulse),
.mmcm_ps_clk (mmcm_ps_clk),
.poc_sample_pd (poc_sample_pd),
.rst (rst),
.error (error),
.reset (reset),
.rst_tg_mc (rst_tg_mc),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs (ddr_dqs),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck (ddr_ck),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_parity (ddr_parity),
.ddr_we_n (ddr_we_n),
.slot_0_present (SLOT_0_CONFIG),
.slot_1_present (SLOT_1_CONFIG),
.correct_en (correct_en),
.bank (bank),
.cmd (cmd),
.col (col),
.data_buf_addr (data_buf_addr),
.wr_data (wr_data),
.wr_data_mask (wr_data_mask),
.rank (rank),
.raw_not_ecc (raw_not_ecc),
.row (row),
.hi_priority (hi_priority),
.size (size),
.use_addr (use_addr),
.accept (accept),
.accept_ns (accept_ns),
.ecc_single (ecc_single),
.ecc_multiple (ecc_multiple),
.ecc_err_addr (ecc_err_addr),
.rd_data (rd_data),
.rd_data_addr (rd_data_addr),
.rd_data_en (rd_data_en),
.rd_data_end (rd_data_end),
.rd_data_offset (rd_data_offset),
.wr_data_addr (wr_data_addr),
.wr_data_en (wr_data_en),
.wr_data_offset (wr_data_offset),
.bank_mach_next (bank_mach_next),
.init_calib_complete (init_calib_complete),
.init_wrcal_complete (init_wrcal_complete),
.app_sr_req (app_sr_req_i),
.app_sr_active (app_sr_active_i),
.app_ref_req (app_ref_req_i),
.app_ref_ack (app_ref_ack_i),
.app_zq_req (app_zq_req_i),
.app_zq_ack (app_zq_ack_i),
.device_temp (device_temp),
.psen (psen),
.psincdec (psincdec),
.psdone (psdone),
.fi_xor_we (fi_xor_we),
.fi_xor_wrdata (fi_xor_wrdata),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_sel_pi_incdec (dbg_sel_pi_incdec),
.dbg_sel_po_incdec (dbg_sel_po_incdec),
.dbg_byte_sel (dbg_byte_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_rddata_valid (dbg_rddata_valid),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_phy_wrlvl (dbg_phy_wrlvl),
.dbg_pi_counter_read_val (dbg_pi_counter_read_val),
.dbg_po_counter_read_val (dbg_po_counter_read_val),
.ref_dll_lock (ref_dll_lock),
.rst_phaser_ref (rst_phaser_ref),
.iddr_rst (iddr_rst),
.dbg_rd_data_offset (dbg_rd_data_offset),
.dbg_phy_init (dbg_phy_init),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.dbg_dqs_found_cal (dbg_dqs_found_cal),
.dbg_pi_phaselock_start (dbg_pi_phaselock_start),
.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done),
.dbg_pi_phaselock_err (dbg_pi_phaselock_err),
.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err),
.dbg_wrcal_start (dbg_wrcal_start),
.dbg_wrcal_done (dbg_wrcal_done),
.dbg_wrcal_err (dbg_wrcal_err),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1),
.dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2),
.dbg_data_offset (dbg_data_offset),
.dbg_data_offset_1 (dbg_data_offset_1),
.dbg_data_offset_2 (dbg_data_offset_2),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done),
.prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r),
.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps),
.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps)
);
mig_7series_v2_3_ui_top #
(
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.ECC (ECC),
.ECC_TEST (ECC_TEST),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.RANKS (RANKS),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER)
)
u_ui_top
(
.wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),
.wr_data (wr_data[APP_DATA_WIDTH-1:0]),
.use_addr (use_addr),
.size (size),
.row (row),
.raw_not_ecc (raw_not_ecc),
.rank (rank),
.hi_priority (hi_priority),
.data_buf_addr (data_buf_addr),
.col (col),
.cmd (cmd),
.bank (bank),
.app_wdf_rdy (app_wdf_rdy),
.app_rdy (app_rdy),
.app_rd_data_valid (app_rd_data_valid),
.app_rd_data_end (app_rd_data_end),
.app_rd_data (app_rd_data),
.app_ecc_multiple_err (app_ecc_multiple_err),
.correct_en (correct_en),
.wr_data_offset (wr_data_offset),
.wr_data_en (wr_data_en),
.wr_data_addr (wr_data_addr),
.rst (reset),
.rd_data_offset (rd_data_offset),
.rd_data_end (rd_data_end),
.rd_data_en (rd_data_en),
.rd_data_addr (rd_data_addr),
.rd_data (rd_data[APP_DATA_WIDTH-1:0]),
.ecc_multiple (ecc_multiple),
.clk (clk),
.app_wdf_wren (app_wdf_wren),
.app_wdf_mask (app_wdf_mask),
.app_wdf_end (app_wdf_end),
.app_wdf_data (app_wdf_data),
.app_sz (1'b1),
.app_raw_not_ecc (app_raw_not_ecc),
.app_hi_pri (app_hi_pri),
.app_en (app_en),
.app_cmd (app_cmd),
.app_addr (app_addr),
.accept_ns (accept_ns),
.accept (accept),
.app_correct_en (app_correct_en_i),
.app_sr_req (app_sr_req),
.sr_req (app_sr_req_i),
.sr_active (app_sr_active_i),
.app_sr_active (app_sr_active),
.app_ref_req (app_ref_req),
.ref_req (app_ref_req_i),
.ref_ack (app_ref_ack_i),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.zq_req (app_zq_req_i),
.zq_ack (app_zq_ack_i),
.app_zq_ack (app_zq_ack)
);
endmodule
|
module altera_edge_detector #(
parameter PULSE_EXT = 0, // 0, 1 = edge detection generate single cycle pulse, >1 = pulse extended for specified clock cycle
parameter EDGE_TYPE = 0, // 0 = falling edge, 1 or else = rising edge
parameter IGNORE_RST_WHILE_BUSY = 0 // 0 = module internal reset will be default whenever rst_n asserted, 1 = rst_n request will be ignored while generating pulse out
) (
input clk,
input rst_n,
input signal_in,
output pulse_out
);
localparam IDLE = 0, ARM = 1, CAPT = 2;
localparam SIGNAL_ASSERT = EDGE_TYPE ? 1'b1 : 1'b0;
localparam SIGNAL_DEASSERT = EDGE_TYPE ? 1'b0 : 1'b1;
reg [1:0] state, next_state;
reg pulse_detect;
wire busy_pulsing;
assign busy_pulsing = (IGNORE_RST_WHILE_BUSY)? pulse_out : 1'b0;
assign reset_qual_n = rst_n | busy_pulsing;
generate
if (PULSE_EXT > 1) begin: pulse_extend
integer i;
reg [PULSE_EXT-1:0] extend_pulse;
always @(posedge clk or negedge reset_qual_n) begin
if (!reset_qual_n)
extend_pulse <= {{PULSE_EXT}{1'b0}};
else begin
for (i = 1; i < PULSE_EXT; i = i+1) begin
extend_pulse[i] <= extend_pulse[i-1];
end
extend_pulse[0] <= pulse_detect;
end
end
assign pulse_out = |extend_pulse;
end
else begin: single_pulse
reg pulse_reg;
always @(posedge clk or negedge reset_qual_n) begin
if (!reset_qual_n)
pulse_reg <= 1'b0;
else
pulse_reg <= pulse_detect;
end
assign pulse_out = pulse_reg;
end
endgenerate
always @(posedge clk) begin
if (!rst_n)
state <= IDLE;
else
state <= next_state;
end
// edge detect
always @(*) begin
next_state = state;
pulse_detect = 1'b0;
case (state)
IDLE : begin
pulse_detect = 1'b0;
if (signal_in == SIGNAL_DEASSERT) next_state = ARM;
else next_state = IDLE;
end
ARM : begin
pulse_detect = 1'b0;
if (signal_in == SIGNAL_ASSERT) next_state = CAPT;
else next_state = ARM;
end
CAPT : begin
pulse_detect = 1'b1;
if (signal_in == SIGNAL_DEASSERT) next_state = ARM;
else next_state = IDLE;
end
default : begin
pulse_detect = 1'b0;
next_state = IDLE;
end
endcase
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// CRC_checker.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH decoder
// Module Name: CRC_checker
// File Name: CRC_checker.v
//
// Version: v1.0.0
//
// Description: Cyclic redundancy check (CRC) decoder
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module CRC_Checker
#(
parameter DATA_WIDTH = 32,
parameter HASH_LENGTH = 64,
parameter INPUT_COUNT_BITS = 13,
parameter INPUT_COUNT = 4352
)
(
i_clk ,
i_RESET ,
i_execute_crc_chk ,
i_message_valid ,
i_message ,
o_crc_chk_start ,
o_last_message ,
o_crc_chk_complete ,
o_parity_chk
);
input i_clk ;
input i_RESET ;
input i_execute_crc_chk ;
input i_message_valid ;
input [DATA_WIDTH-1:0] i_message ;
output o_crc_chk_start ;
output o_last_message ;
output o_crc_chk_complete ;
output o_parity_chk ;
localparam CRC_CHK_FSM_BIT = 5;
localparam CrcChkReset = 5'b00001;
localparam CrcChkStart = 5'b00010;
localparam CrcChkFeedBack = 5'b00100;
localparam CrcChkMessageTransferPause = 5'b01000;
localparam CrcChkParityCheck = 5'b10000;
reg [DATA_WIDTH-1:0] r_message ;
reg [CRC_CHK_FSM_BIT-1:0] r_cur_state ;
reg [CRC_CHK_FSM_BIT-1:0] r_next_state ;
reg [INPUT_COUNT_BITS-1:0] r_counter ;
reg [HASH_LENGTH-1:0] r_parity_code ;
wire [HASH_LENGTH-1:0] w_next_parity_code ;
wire w_valid_execution ;
CRC_parallel_m_lfs_XOR
#(
.DATA_WIDTH (DATA_WIDTH ),
.HASH_LENGTH (HASH_LENGTH)
)
CRC_mLFSXOR_matrix (
.i_message (r_message ),
.i_cur_parity (r_parity_code ),
.o_next_parity (w_next_parity_code));
assign w_valid_execution = i_execute_crc_chk & i_message_valid;
assign o_crc_chk_start = (r_cur_state == CrcChkStart);
assign o_last_message = (i_message_valid == 1) & (r_counter == INPUT_COUNT-1);
assign o_crc_chk_complete = (r_counter == INPUT_COUNT);
assign o_parity_chk = (r_counter == INPUT_COUNT)? (|w_next_parity_code): 0;
always @ (posedge i_clk)
begin
if (i_RESET)
r_cur_state <= CrcChkReset;
else
r_cur_state <= r_next_state;
end
always @ (*)
begin
case (r_cur_state)
CrcChkReset:
r_next_state <= (w_valid_execution) ? (CrcChkStart) : (CrcChkReset);
CrcChkStart:
r_next_state <= (i_message_valid) ? (CrcChkFeedBack) : (CrcChkMessageTransferPause);
CrcChkFeedBack:
r_next_state <= (o_crc_chk_complete) ? (CrcChkParityCheck) :
((i_message_valid) ? (CrcChkFeedBack) : (CrcChkMessageTransferPause));
CrcChkMessageTransferPause:
r_next_state <= (i_message_valid) ? (CrcChkFeedBack) : (CrcChkMessageTransferPause);
CrcChkParityCheck:
r_next_state <= CrcChkReset;
default:
r_next_state <= CrcChkReset;
endcase
end
always @ (posedge i_clk)
begin
if (i_RESET) begin
r_counter <= 0;
r_message <= 0;
r_parity_code <= 0;
end
else begin
case (r_next_state)
CrcChkReset: begin
r_counter <= 0;
r_message <= 0;
r_parity_code <= 0;
end
CrcChkStart: begin
r_counter <= 1;
r_message <= i_message;
r_parity_code <= 0;
end
CrcChkFeedBack: begin
r_counter <= r_counter + 1'b1;
r_message <= i_message;
r_parity_code <= w_next_parity_code;
end
CrcChkMessageTransferPause: begin
r_counter <= r_counter;
r_message <= r_message;
r_parity_code <= r_parity_code;
end
CrcChkParityCheck: begin
r_counter <= 0;
r_message <= 0;
r_parity_code <= w_next_parity_code;
end
default: begin
r_counter <= 0;
r_message <= 0;
r_parity_code <= 0;
end
endcase
end
end
endmodule |
`timescale 1ns / 1ps
module top_ASCCI(
input clk,
input [76:0] string,
input new_string,
input [7:0]dir,
output [15:0]datoram,
output [6:0] efect,
output run_efect
//abilita y desa el bus de direcion de ram de cada modulo
);
wire [3:0]col;
wire top_col;
wire [3:0]n_ascci;
wire top_ascci;
wire add_ascci;
wire reset_ascci;
wire add_col;
wire reset_col;
wire add_dirram;
wire reset_dirram;
wire leer_rom;
wire leer_ram;
wire [6:0]ascci;
wire [10:0]dir_rom;
wire wram;
wire [15:0]datorom;
wire [10:0]dir_in;
wire [7:0] d_ram;
wire [7:0] dir_ram;
wire done;
select_dir seldir(.clk(clk),.d_ram(d_ram),.dir_ram(dir_ram),.dir(dir),.leer_ram(leer_ram) );
comp_col comcol(.col(col),.top_col(top_col));
compn_ascci camasc (.n_ascci(n_ascci),.top_ascci(top_ascci));
cont_ascci aonasc (.n_ascci(n_ascci),.clk(clk),.add_ascci(add_ascci),.reset_ascci(reset_ascci));
cont_col aoncol(.clk(clk),.add_col(add_col),.reset_col(reset_col),.col(col));
cont_ram conra (.clk(clk),.add_dirram(add_dirram),.reset_dirram(reset_dirram),.dir_ram(dir_ram));
control_ascci contrascc (.clk(clk),.top_ascci(top_ascci),.top_col(top_col),.add_dirram(add_dirram),.reset_dirram(reset_dirram),.add_col(add_col),.reset_col(reset_col),.add_ascci(add_ascci),.reset_ascci(reset_ascci),.leer_rom(leer_rom),.leer_ram(leer_ram),.new_string(new_string),.init(init),.done(done),.run_efect(run_efect));
dir_ascci dirasc (.dir_in(dir_in),.clk(clk),.dir_rom(dir_rom),.col(col),.done(done));
m_plexor mplex(.string(string),.n_ascci(n_ascci),.ascci(ascci),.efect(efect) );
ram ra (.clk(clk),.direccionram(d_ram),.wram(leer_ram),.datorom(datorom),.datoram(datoram));
rom ro (.clk(clk),.leer_rom(leer_rom),.dir_rom(dir_rom),.dato_rom(datorom));
top_multiplicador mult(.clk(clk),.init(init),.A(ascci),.pp(dir_in), .done(done));
endmodule
|
/************************
* Willard Wider
* 6-6-17
* ELEC3725
* alupipe.v
* building a 32 bit ALU
************************/
//the top module, the ALU with piped input and output
module alupipe(S, abus, bbus, clk, Cin, dbus);
input [31:0] abus;
input [31:0] bbus;
input clk;
input [2:0] S;
input Cin;
output [31:0] dbus;
wire [31:0] aInput;//connects register A output to ALU A input
wire [31:0] bInput;//connects register B output to ALU B input
wire [31:0] dInput;//connects register D input to ALU D output
alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));
DflipFlop AFF(.dataIn(abus), .dataOut(aInput), .clk(clk));
DflipFlop BFF(.dataIn(bbus), .dataOut(bInput), .clk(clk));
DflipFlop DFF(.dataIn(dInput), .dataOut(dbus), .clk(clk));
endmodule
//flip flop module. requires a clock cycle to update value
module DflipFlop(dataIn, clk, dataOut);
input [31:0] dataIn;
input clk;
output [31:0] dataOut;
reg [31:0] dataOut;
always @(posedge clk) begin
dataOut = dataIn;
end
endmodule
//Below this point is code from assignment 1//
//The declaration of the entire ALU itself.
module alu32 (d, Cout, V, a, b, Cin, S);
output[31:0] d;//the output bus
output Cout, V;//Cout is the bit for it it needs to carry over to the next circuit/ V is the overflow bit.
input [31:0] a, b;//the two input buses
input Cin;//the bit for marking if it is carrying over from a previous circuit
input [2:0] S;//The select bus. It defines the operation to do with input busses a and b
wire [31:0] c, g, p;
wire gout, pout;
//The core ALU bus
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
//the top Look-Ahead-Carry module.
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
//the overflow module
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule
//The module to handle a single bit operation for the top ALU module
module alu_cell (d, g, p, a, b, c, S);
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;
p = a ^ bint;
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule
//The module to handle the overflow bit
module overflow (Cout, V, g, p, c31, Cin);
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule
//Look-Ahead Carry unit level 1. Used for the root (level 1) and first child leafs (level 2)
module lac(c, gout, pout, Cin, g, p);
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule
//Look-Ahead Carry unit level 2. Contains LACs for the root and level 1. Used in level 3
module lac2 (c, gout, pout, Cin, g, p);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 3. Contains LACs for the root and level 2. Used in level 4
module lac3 (c, gout, pout, Cin, g, p);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 4. Contains LACs for the root and level 3. Used in level 5
module lac4 (c, gout, pout, Cin, g, p);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 1. Caontains LACs for the root and level 4. Used in the core alu32 module
module lac5 (c, gout, pout, Cin, g, p);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_carry #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
input wire DI,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = (CIN & S) | (DI & ~S);
end else begin : USE_FPGA
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (DI),
.S (S)
);
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:02:04 12/01/2014
// Design Name:
// Module Name: MainProyectoFinalPrueba
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MainProyectoFinal #(parameter Width = 32, ConLimitador=0,Magnitud = 7, Precision = 24, Signo = 1/*,
A00= 32'sb11110010000000000000000000000000, A01= 32'sb11110010100000000000000000000000,
A02 = 32'sb11110011000000000000000000000000, A03 = 32'sb11110011100000000000000000000000, A04 = 32'sb11110100000000000000000000000000, A05 = 32'sb11110100100000000000000000000000, A06 = 32'sb11110101000000000000000000000000, A07 = 32'sb11110101100000000000000000000000, A08 = 32'sb11110110000000000000000000000000, A09 = 32'sb11110110100000000000000000000000,
A10= 32'sb11110111000000000000000000000000, A11= 32'sb11110111100000000000000000000000, A12 = 32'sb11111000000000000000000000000000, A13 = 32'sb11111000100000000000000000000000, A14 = 32'sb11111001000000000000000000000000, A15 = 32'sb11111001100000000000000000000000, A16 = 32'sb11111010000000000000000000000000, A17 = 32'sb11111010100000000000000000000000, A18 = 32'sb11111011000000000000000000000000, A19 = 32'sb11111011100000000000000000000000,
A20= 32'sb11111100000000000000000000000000, A21= 32'sb11111100100000000000000000000000,
A22 = 32'sb11111101000000000000000000000000, A23 = 32'sb11111101100000000000000000000000, A24 = 32'sb11111110000000000000000000000000, A25 = 32'sb11111110100000000000000000000000, A26 = 32'sb11111111000000000000000000000000, A27 = 32'sb00000001000000000000000000000000, A28 = 32'sb00000011000000000000000000000000, A29 = 32'sb00001000000000000000000000000000,
A30 = 32'sb00010100000000000000000000000000,
M01= 32'sb00000000000000000000000000010010, M02 = 32'sb00000000000000000000000000011101, M03 = 32'sb00000000000000000000000000110000, M04 = 32'sb00000000000000000000000001010000, M05 = 32'sb00000000000000000000000010000101, M06 = 32'sb00000000000000000000000011011011, M07 = 32'sb00000000000000000000000101101010, M08 = 32'sb00000000000000000000001001010100, M09 = 32'sb00000000000000000000001111011000, M10= 32'sb00000000000000000000011001010110,
M11= 32'sb00000000000000000000101001110010, M12 = 32'sb00000000000000000001000100111000, M13 = 32'sb00000000000000000001110001100001, M14 = 32'sb00000000000000000010111011000100, M15 = 32'sb00000000000000000100110100001000, M16 = 32'sb00000000000000000111111011001110, M17 = 32'sb00000000000000001101000010001010, M18 = 32'sb00000000000000010101011001100010, M19 = 32'sb00000000000000100011000010100000, M20= 32'sb00000000000000111001000111101101,
M21= 32'sb00000000000001011100011100110110,M22 = 32'sb00000000000010010011111001111110, M23 = 32'sb00000000000011101000010010000010, M24 = 32'sb00000000000101100010010111111111, M25 = 32'sb00000000001000000101011001111001, M26 = 32'sb00000000001011000100110111000010, M27 = 32'sb00000000001111010000001011111101, M28 = 32'sb00000000000110111100101101110000, M29 = 32'sb00000000000000011100111000110000, M30 = 32'sb00000000000000000000000011000011,
B01= 32'sb00000000000000000000000100001001, B02 = 32'sb00000000000000000000000110100111, B03 = 32'sb00000000000000000000001010100001, B04 = 32'sb00000000000000000000010000101110, B05 = 32'sb00000000000000000000011010100010, B06 = 32'sb00000000000000000000101010000010, B07 = 32'sb00000000000000000001000010011111, B08 = 32'sb00000000000000000001000010011111, B09 = 32'sb00000000000000000010100101010110,
B10= 32'sb00000000000000000100000011111011, B11= 32'sb00000000000000000110010111100110, B12 = 32'sb00000000000000001001111101011100, B13 = 32'sb00000000000000001111100001110111, B14 = 32'sb00000000000000011000001000001100, B15 = 32'sb00000000000000100101010101101000, B16 = 32'sb00000000000000111001100000100001, B17 = 32'sb00000000000001011000000100101101, B18 = 32'sb00000000000010000101111100100110, B19 = 32'sb00000000000011001001111011010011,
B20= 32'sb00000000000100101100111100011001, B21= 32'sb00000000000110111001101110001101,B22 = 32'sb00000000001001111011000000011110, B23 = 32'sb00000000001101110111000000110110, B24 = 32'sb00000000010010100110110111111101, B25 = 32'sb00000000010111101011101001001001, B26 = 32'sb00000000011100001010010101101101, B27 = 32'sb00000000100000000000000000000000, B28 = 32'sb00000000101001101000100000110000, B29 = 32'sb00000000111100111001100101111101,
B30 = 32'sb00000000111111111111001101111011*/)
(CLK,MasterReset,write,read,address,writedata,readdata);
input CLK;
input MasterReset;
input write;
input read;
input [8:0] address;
input signed [Width-1:0] writedata;
output signed [Width-1:0] readdata;
wire ResetInterfaz,ResetStart,ResetCoeffALUandInput,
EnableCoeffALUandInput,EnableMulX,EnableRegOutMultCoeffX,EnableFuctAct,EnableRegActFunc,
EnableMulY,EnableRegDesplazamiento,EnableSum,SELOffset,EnableAcumulador,ResetAcumulador,
Listo,Start,Error1;
wire signed [Width-1:0] Coeff00,Coeff01,Coeff02,Coeff03,Coeff04,Coeff05,Coeff06,Coeff07,Coeff08,
Coeff09,Coeff10,Coeff11,Coeff12,Coeff13,Coeff14,Coeff15,Coeff16,Coeff17,Coeff18,Coeff19,Offset,
InDato,InDatoALU,Acumulador,OutALU,Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7,Y8,Y9;
wire [3:0] SELCoeffY,SELCoeffX;
reg Error;
FSMNeuralNetwork FSMNeuralNetworkCopia (
.CLK(CLK), //**********************************
.reset(~MasterReset), //**********************************
.Start(Start), //**********************************
.Read(read), //**********************************
.Address(address), //**********************************
.ResetInterfaz(ResetInterfaz), //**********************************
.ResetStart(ResetStart), //**********************************
.ResetCoeffALUandInput(ResetCoeffALUandInput), //**********************************
.EnableCoeffALUandInput(EnableCoeffALUandInput), //**********************************
.EnableMulX(EnableMulX), //**********************************
.SELCoeffX(SELCoeffX), //**********************************
.EnableRegOutMultCoeffX(EnableRegOutMultCoeffX), //**********************************
.EnableFuctAct(EnableFuctAct), //**********************************
.EnableRegActFunc(EnableRegActFunc), //**********************************
.EnableMulY(EnableMulY), //**********************************
.EnableRegDesplazamiento(EnableRegDesplazamiento), //**********************************
.EnableSum(EnableSum), //**********************************
.SELCoeffY(SELCoeffY), //**********************************
.SELOffset(SELOffset), //**********************************
.EnableAcumulador(EnableAcumulador), //**********************************
.ResetAcumulador(ResetAcumulador), //**********************************
.Listo(Listo) //**********************************
);
RegistroCargaInterfaz #(.Width(Width)) RegistroCargaInterfazCopia (
.CLK(CLK), //**********************************
.Reset(ResetInterfaz), //**********************************
.ResetStart(ResetStart), //**********************************
.InDatoMemoria(writedata), //**********************************
.Write(write), //**********************************
.Address(address), //**********************************
.Coeff00(Coeff00), //**********************************
.Coeff01(Coeff01), //**********************************
.Coeff02(Coeff02), //**********************************
.Coeff03(Coeff03), //**********************************
.Coeff04(Coeff04), //**********************************
.Coeff05(Coeff05), //**********************************
.Coeff06(Coeff06), //**********************************
.Coeff07(Coeff07), //**********************************
.Coeff08(Coeff08), //**********************************
.Coeff09(Coeff09), //**********************************
.Coeff10(Coeff10), //**********************************
.Coeff11(Coeff11), //**********************************
.Coeff12(Coeff12), //**********************************
.Coeff13(Coeff13), //**********************************
.Coeff14(Coeff14), //**********************************
.Coeff15(Coeff15), //**********************************
.Coeff16(Coeff16), //**********************************
.Coeff17(Coeff17), //**********************************
.Coeff18(Coeff18), //**********************************
.Coeff19(Coeff19), //**********************************
.Offset(Offset), //**********************************
.InDato(InDato), //**********************************
.Start(Start) //**********************************
);
Registro #(.Width(Width)) RegistroEntrada (
.CLK(CLK), //**********************************
.reset(ResetCoeffALUandInput), //**********************************
.Enable(EnableCoeffALUandInput), //**********************************
.Entrada(InDato), //**********************************
.Salida(InDatoALU) //**********************************
);
ALUNeuralNetwork #(.Width(Width),.Magnitud(Magnitud),.ConLimitador(ConLimitador),.Precision(Precision), .Signo(Signo),
/*.A00(A00),
.A01(A01),.A02(A02),.A03(A03),.A04(A04),.A05(A05),.A06(A06),.A07(A07),.A08(A08),.A09(A09),
.A10(A10),.A11(A11),.A12(A12),.A13(A13),.A14(A14),.A15(A15),.A16(A16),.A17(A17),.A18(A18),.A19(A19),
.A20(A20),.A21(A21),.A22(A22),.A23(A23),.A24(A24),.A25(A25),.A26(A26),.A27(A27),.A28(A28),.A29(A29),
.A30(A30),
.M01(M01),.M02(M02),.M03(M03),.M04(M04),.M05(M05),.M06(M06),.M07(M07),.M08(M08),.M09(M09),
.M10(M10),.M11(M11),.M12(M12),.M13(M13),.M14(M14),.M15(M15),.M16(M16),.M17(M17),.M18(M18),.M19(M19),
.M20(M20),.M21(M21),.M22(M22),.M23(M23),.M24(M24),.M25(M25),.M26(M26),.M27(M27),.M28(M28),.M29(M29),
.M30(M30),
.B01(B01),.B02(B02),.B03(B03),.B04(B04),.B05(B05),.B06(B06),.B07(B07),.B08(B08),.B09(B09),
.B10(B10),.B11(B11),.B12(B12),.B13(B13),.B14(B14),.B15(B15),.B16(B16),.B17(B17),.B18(B18),.B19(B19),
.B20(B20),.B21(B21),.B22(B22),.B23(B23),.B24(B24),.B25(B25),.B26(B26),.B27(B27),.B28(B28),.B29(B29),
.B30(B30)*/
.A00(32'sb11110010000000000000000000000000), .A01(32'sb11110010100000000000000000000000),
.A02(32'sb11110011000000000000000000000000), .A03(32'sb11110011100000000000000000000000), .A04(32'sb11110100000000000000000000000000), .A05(32'sb11110100100000000000000000000000), .A06(32'sb11110101000000000000000000000000), .A07(32'sb11110101100000000000000000000000), .A08(32'sb11110110000000000000000000000000), .A09(32'sb11110110100000000000000000000000),
.A10(32'sb11110111000000000000000000000000), .A11(32'sb11110111100000000000000000000000), .A12(32'sb11111000000000000000000000000000), .A13(32'sb11111000100000000000000000000000), .A14(32'sb11111001000000000000000000000000), .A15(32'sb11111001100000000000000000000000), .A16(32'sb11111010000000000000000000000000), .A17(32'sb11111010100000000000000000000000), .A18(32'sb11111011000000000000000000000000), .A19(32'sb11111011100000000000000000000000),
.A20(32'sb11111100000000000000000000000000), .A21(32'sb11111100100000000000000000000000),
.A22(32'sb11111101000000000000000000000000), .A23(32'sb11111101100000000000000000000000), .A24(32'sb11111110000000000000000000000000), .A25(32'sb11111110100000000000000000000000), .A26(32'sb11111111000000000000000000000000), .A27(32'sb00000001000000000000000000000000), .A28(32'sb00000011000000000000000000000000), .A29(32'sb00001000000000000000000000000000),
.A30(32'sb00010100000000000000000000000000),
.M01(32'sb00000000000000000000000000010010), .M02(32'sb00000000000000000000000000011101), .M03(32'sb00000000000000000000000000110000), .M04(32'sb00000000000000000000000001010000), .M05(32'sb00000000000000000000000010000101), .M06(32'sb00000000000000000000000011011011), .M07(32'sb00000000000000000000000101101010), .M08(32'sb00000000000000000000001001010100), .M09(32'sb00000000000000000000001111011000), .M10(32'sb00000000000000000000011001010110),
.M11(32'sb00000000000000000000101001110010), .M12(32'sb00000000000000000001000100111000), .M13(32'sb00000000000000000001110001100001), .M14(32'sb00000000000000000010111011000100), .M15(32'sb00000000000000000100110100001000), .M16(32'sb00000000000000000111111011001110), .M17(32'sb00000000000000001101000010001010), .M18(32'sb00000000000000010101011001100010), .M19(32'sb00000000000000100011000010100000), .M20(32'sb00000000000000111001000111101101),
.M21(32'sb00000000000001011100011100110110), .M22(32'sb00000000000010010011111001111110), .M23(32'sb00000000000011101000010010000010), .M24(32'sb00000000000101100010010111111111), .M25(32'sb00000000001000000101011001111001), .M26(32'sb00000000001011000100110111000010), .M27(32'sb00000000001111010000001011111101), .M28(32'sb00000000000110111100101101110000), .M29(32'sb00000000000000011100111000110000), .M30(32'sb00000000000000000000000011000011),
.B01(32'sb00000000000000000000000100001001), .B02(32'sb00000000000000000000000110100111), .B03(32'sb00000000000000000000001010100001), .B04(32'sb00000000000000000000010000101110), .B05(32'sb00000000000000000000011010100010), .B06(32'sb00000000000000000000101010000010), .B07(32'sb00000000000000000001000010011111), .B08(32'sb00000000000000000001000010011111), .B09(32'sb00000000000000000010100101010110),
.B10(32'sb00000000000000000100000011111011), .B11(32'sb00000000000000000110010111100110), .B12(32'sb00000000000000001001111101011100), .B13(32'sb00000000000000001111100001110111), .B14(32'sb00000000000000011000001000001100), .B15(32'sb00000000000000100101010101101000), .B16(32'sb00000000000000111001100000100001), .B17(32'sb00000000000001011000000100101101), .B18(32'sb00000000000010000101111100100110), .B19(32'sb00000000000011001001111011010011),
.B20(32'sb00000000000100101100111100011001), .B21(32'sb00000000000110111001101110001101), .B22(32'sb00000000001001111011000000011110), .B23(32'sb00000000001101110111000000110110), .B24(32'sb00000000010010100110110111111101), .B25(32'sb00000000010111101011101001001001), .B26(32'sb00000000011100001010010101101101), .B27(32'sb00000000100000000000000000000000), .B28(32'sb00000000101001101000100000110000), .B29(32'sb00000000111100111001100101111101),
.B30(32'sb00000000111111111111001101111011)
)
ALUNeuralNetworkCopia (
.CLK(CLK), //**********************************
.reset(ResetCoeffALUandInput), //**********************************
.EnableLoadCoeff(EnableCoeffALUandInput), //**********************************
.EnableMulX(EnableMulX), //**********************************
.EnableRegOutMultCoeffX(EnableRegOutMultCoeffX), //**********************************
.EnableFuctAct(EnableFuctAct), //**********************************
.EnableRegActFunc(EnableRegActFunc), //**********************************
.EnableMulY(EnableMulY), //**********************************
.EnableRegDesplazamiento(EnableRegDesplazamiento), //**********************************
.EnableSum(EnableSum), //**********************************
.InDato(InDatoALU), //**********************************
.Acumulador(Acumulador), //**********************************
.SELCoeffX(SELCoeffX), //**********************************
.SELCoeffY(SELCoeffY), //**********************************
.SELOffset(SELOffset), //**********************************
.Coeff00(Coeff00), //**********************************
.Coeff01(Coeff01), //**********************************
.Coeff02(Coeff02), //**********************************
.Coeff03(Coeff03), //**********************************
.Coeff04(Coeff04), //**********************************
.Coeff05(Coeff05), //**********************************
.Coeff06(Coeff06), //**********************************
.Coeff07(Coeff07), //**********************************
.Coeff08(Coeff08), //**********************************
.Coeff09(Coeff09), //**********************************
.Coeff10(Coeff10), //**********************************
.Coeff11(Coeff11), //**********************************
.Coeff12(Coeff12), //**********************************
.Coeff13(Coeff13), //**********************************
.Coeff14(Coeff14), //**********************************
.Coeff15(Coeff15), //**********************************
.Coeff16(Coeff16), //**********************************
.Coeff17(Coeff17), //**********************************
.Coeff18(Coeff18), //**********************************
.Coeff19(Coeff19), //**********************************
.Offset(Offset), //**********************************
.Error(Error1), //**********************************
.OutDato(OutALU), //**********************************
.Y0(Y0), //**********************************
.Y1(Y1), //**********************************
.Y2(Y2), //**********************************
.Y3(Y3), //**********************************
.Y4(Y4), //**********************************
.Y5(Y5), //**********************************
.Y6(Y6), //**********************************
.Y7(Y7), //**********************************
.Y8(Y8), //**********************************
.Y9(Y9) //**********************************
);
Registro #(.Width(Width)) RegistroAcumulador (
.CLK(CLK), //**********************************
.reset(ResetAcumulador), //**********************************
.Enable(EnableAcumulador), //**********************************
.Entrada(OutALU), //**********************************
.Salida(Acumulador) //**********************************
);
EscrituraRegistroToMemoria #(.Width(Width)) EscrituraRegistroToMemoriaPruebaCopia (
.Read(read), //**********************************
.InError(Error), //**********************************
.Address(address), //**********************************
.ListoIn(Listo), //**********************************
.InDato(Acumulador), //**********************************
.Coeff00(Coeff00), //**********************************
.Coeff01(Coeff01), //**********************************
.Coeff02(Coeff02), //**********************************
.Coeff03(Coeff03), //**********************************
.Coeff04(Coeff04), //**********************************
.Coeff05(Coeff05), //**********************************
.Coeff06(Coeff06), //**********************************
.Coeff07(Coeff07), //**********************************
.Coeff08(Coeff08), //**********************************
.Coeff09(Coeff09), //**********************************
.Coeff10(Coeff10), //**********************************
.Coeff11(Coeff11), //**********************************
.Coeff12(Coeff12), //**********************************
.Coeff13(Coeff13), //**********************************
.Coeff14(Coeff14), //**********************************
.Coeff15(Coeff15), //**********************************
.Coeff16(Coeff16), //**********************************
.Coeff17(Coeff17), //**********************************
.Coeff18(Coeff18), //**********************************
.Coeff19(Coeff19), //**********************************
.Offset(Offset), //**********************************
.DatoEntradaSistema(InDatoALU), //**********************************
.Y0(Y0), //**********************************
.Y1(Y1), //**********************************
.Y2(Y2), //**********************************
.Y3(Y3), //**********************************
.Y4(Y4), //**********************************
.Y5(Y5), //**********************************
.Y6(Y6), //**********************************
.Y7(Y7), //**********************************
.Y8(Y8), //**********************************
.Y9(Y9), //**********************************
.OutDato(readdata) //**********************************
);
always @(posedge CLK) begin //***************REGISTRO QUE ALMACENA EN CASO DE QUE HAYA ERRORES
if (ResetStart) begin
Error <= 1'b0;
end else if (Error1) begin
Error <= 1'b1;
end
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: AXI Splitter
// Each transfer received on the AXI handshake slave port is replicated onto
// each of the master ports, and is completed back to the slave (S_READY)
// once all master ports have completed.
//
// M_VALID is asserted combinatorially from S_VALID assertion.
// Each M_VALID is masked off beginning the cycle after each M_READY is
// received (if S_READY remains low) until the cycle after both S_VALID
// and S_READY are asserted.
// S_READY is asserted combinatorially when the last (or all) of the M_READY
// inputs have been received.
// If all M_READYs are asserted when S_VALID is asserted, back-to-back
// handshakes can occur without bubble cycles.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// splitter
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_10_splitter #
(
parameter integer C_NUM_M = 2 // Number of master ports = [2:16]
)
(
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Port
input wire S_VALID,
output wire S_READY,
// Master Ports
output wire [C_NUM_M-1:0] M_VALID,
input wire [C_NUM_M-1:0] M_READY
);
reg [C_NUM_M-1:0] m_ready_d;
wire s_ready_i;
wire [C_NUM_M-1:0] m_valid_i;
always @(posedge ACLK) begin
if (ARESET | s_ready_i) m_ready_d <= {C_NUM_M{1'b0}};
else m_ready_d <= m_ready_d | (m_valid_i & M_READY);
end
assign s_ready_i = &(m_ready_d | M_READY);
assign m_valid_i = {C_NUM_M{S_VALID}} & ~m_ready_d;
assign M_VALID = m_valid_i;
assign S_READY = s_ready_i;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3B_2_V
`define SKY130_FD_SC_HS__NAND3B_2_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog wrapper for nand3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand3b_2 (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand3b_2 (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3B_2_V
|
// (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axisc_downsizer
// Convert from SI data width < MI datawidth.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axis_dwidth_converter_v1_1_axisc_upsizer #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "virtex6",
parameter integer C_S_AXIS_TDATA_WIDTH = 32,
parameter integer C_M_AXIS_TDATA_WIDTH = 96,
parameter integer C_AXIS_TID_WIDTH = 1,
parameter integer C_AXIS_TDEST_WIDTH = 1,
parameter integer C_S_AXIS_TUSER_WIDTH = 1,
parameter integer C_M_AXIS_TUSER_WIDTH = 3,
parameter [31:0] C_AXIS_SIGNAL_SET = 32'hFF ,
// C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
// [0] => TREADY present
// [1] => TDATA present
// [2] => TSTRB present, TDATA must be present
// [3] => TKEEP present, TDATA must be present
// [4] => TLAST present
// [5] => TID present
// [6] => TDEST present
// [7] => TUSER present
parameter integer C_RATIO = 3 // Should always be 1:C_RATIO (upsizer)
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// System Signals
input wire ACLK,
input wire ARESET,
input wire ACLKEN,
// Slave side
input wire S_AXIS_TVALID,
output wire S_AXIS_TREADY,
input wire [C_S_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA,
input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] S_AXIS_TSTRB,
input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] S_AXIS_TKEEP,
input wire S_AXIS_TLAST,
input wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID,
input wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST,
input wire [C_S_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER,
// Master side
output wire M_AXIS_TVALID,
input wire M_AXIS_TREADY,
output wire [C_M_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA,
output wire [C_M_AXIS_TDATA_WIDTH/8-1:0] M_AXIS_TSTRB,
output wire [C_M_AXIS_TDATA_WIDTH/8-1:0] M_AXIS_TKEEP,
output wire M_AXIS_TLAST,
output wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID,
output wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST,
output wire [C_M_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axis_infrastructure_v1_1_axis_infrastructure.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_READY_EXIST = C_AXIS_SIGNAL_SET[0];
localparam P_DATA_EXIST = C_AXIS_SIGNAL_SET[1];
localparam P_STRB_EXIST = C_AXIS_SIGNAL_SET[2];
localparam P_KEEP_EXIST = C_AXIS_SIGNAL_SET[3];
localparam P_LAST_EXIST = C_AXIS_SIGNAL_SET[4];
localparam P_ID_EXIST = C_AXIS_SIGNAL_SET[5];
localparam P_DEST_EXIST = C_AXIS_SIGNAL_SET[6];
localparam P_USER_EXIST = C_AXIS_SIGNAL_SET[7];
localparam P_S_AXIS_TSTRB_WIDTH = C_S_AXIS_TDATA_WIDTH/8;
localparam P_M_AXIS_TSTRB_WIDTH = C_M_AXIS_TDATA_WIDTH/8;
// State Machine possible states. Bits 1:0 used to encode output signals.
// /--- M_AXIS_TVALID state
// |/-- S_AXIS_TREADY state
localparam SM_RESET = 3'b000; // De-assert Ready during reset
localparam SM_IDLE = 3'b001; // R0 reg is empty
localparam SM_ACTIVE = 3'b101; // R0 reg is active
localparam SM_END = 3'b011; // R0 reg is empty and ACC reg is active
localparam SM_END_TO_ACTIVE = 3'b010; // R0/ACC reg are both active.
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [2:0] state;
reg [C_M_AXIS_TDATA_WIDTH-1:0] acc_data;
reg [P_M_AXIS_TSTRB_WIDTH-1:0] acc_strb;
reg [P_M_AXIS_TSTRB_WIDTH-1:0] acc_keep;
reg acc_last;
reg [C_AXIS_TID_WIDTH-1:0] acc_id;
reg [C_AXIS_TDEST_WIDTH-1:0] acc_dest;
reg [C_M_AXIS_TUSER_WIDTH-1:0] acc_user;
wire [C_RATIO-1:0] acc_reg_en;
reg [C_RATIO-1:0] r0_reg_sel;
wire next_xfer_is_end;
reg [C_S_AXIS_TDATA_WIDTH-1:0] r0_data;
reg [P_S_AXIS_TSTRB_WIDTH-1:0] r0_strb;
reg [P_S_AXIS_TSTRB_WIDTH-1:0] r0_keep;
reg r0_last;
reg [C_AXIS_TID_WIDTH-1:0] r0_id;
reg [C_AXIS_TDEST_WIDTH-1:0] r0_dest;
reg [C_S_AXIS_TUSER_WIDTH-1:0] r0_user;
wire id_match;
wire dest_match;
wire id_dest_mismatch;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// S Ready/M Valid outputs are encoded in the current state.
assign S_AXIS_TREADY = state[0];
assign M_AXIS_TVALID = state[1];
// State machine controls M_AXIS_TVALID and S_AXIS_TREADY, and loading
always @(posedge ACLK) begin
if (ARESET) begin
state <= SM_RESET;
end else if (ACLKEN) begin
case (state)
SM_RESET: begin
state <= SM_IDLE;
end
SM_IDLE: begin
if (S_AXIS_TVALID & id_dest_mismatch & ~r0_reg_sel[0]) begin
state <= SM_END_TO_ACTIVE;
end
else if (S_AXIS_TVALID & next_xfer_is_end) begin
state <= SM_END;
end
else if (S_AXIS_TVALID) begin
state <= SM_ACTIVE;
end
else begin
state <= SM_IDLE;
end
end
SM_ACTIVE: begin
if (S_AXIS_TVALID & (id_dest_mismatch | r0_last)) begin
state <= SM_END_TO_ACTIVE;
end
else if ((~S_AXIS_TVALID & r0_last) | (S_AXIS_TVALID & next_xfer_is_end)) begin
state <= SM_END;
end
else if (S_AXIS_TVALID & ~next_xfer_is_end) begin
state <= SM_ACTIVE;
end
else begin
state <= SM_IDLE;
end
end
SM_END: begin
if (M_AXIS_TREADY & S_AXIS_TVALID) begin
state <= SM_ACTIVE;
end
else if ( ~M_AXIS_TREADY & S_AXIS_TVALID) begin
state <= SM_END_TO_ACTIVE;
end
else if ( M_AXIS_TREADY & ~S_AXIS_TVALID) begin
state <= SM_IDLE;
end
else begin
state <= SM_END;
end
end
SM_END_TO_ACTIVE: begin
if (M_AXIS_TREADY) begin
state <= SM_ACTIVE;
end
else begin
state <= SM_END_TO_ACTIVE;
end
end
default: begin
state <= SM_IDLE;
end
endcase // case (state)
end
end
assign M_AXIS_TDATA = acc_data;
assign M_AXIS_TSTRB = acc_strb;
assign M_AXIS_TKEEP = acc_keep;
assign M_AXIS_TUSER = acc_user;
generate
genvar i;
// DATA/USER/STRB/KEEP accumulators
always @(posedge ACLK) begin
if (ACLKEN) begin
acc_data[0*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH] <= acc_reg_en[0] ? r0_data
: acc_data[0*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH];
acc_user[0*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH] <= acc_reg_en[0] ? r0_user
: acc_user[0*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH];
acc_strb[0*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= acc_reg_en[0] ? r0_strb
: acc_strb[0*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
acc_keep[0*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= acc_reg_en[0] ? r0_keep
: acc_keep[0*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
end
end
for (i = 1; i < C_RATIO-1; i = i + 1) begin : gen_data_accumulator
always @(posedge ACLK) begin
if (ACLKEN) begin
acc_data[i*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH] <= acc_reg_en[i] ? r0_data
: acc_data[i*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH];
acc_user[i*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH] <= acc_reg_en[i] ? r0_user
: acc_user[i*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH];
acc_strb[i*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= acc_reg_en[0] ? {P_S_AXIS_TSTRB_WIDTH{1'b0}}
: acc_reg_en[i] ? r0_strb : acc_strb[i*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
acc_keep[i*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= acc_reg_en[0] ? {P_S_AXIS_TSTRB_WIDTH{1'b0}}
: acc_reg_en[i] ? r0_keep : acc_keep[i*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
end
end
end
always @(posedge ACLK) begin
if (ACLKEN) begin
acc_data[(C_RATIO-1)*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH] <= (state == SM_IDLE) | (state == SM_ACTIVE)
? S_AXIS_TDATA : acc_data[(C_RATIO-1)*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH];
acc_user[(C_RATIO-1)*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH] <= (state == SM_IDLE) | (state == SM_ACTIVE)
? S_AXIS_TUSER : acc_user[(C_RATIO-1)*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH];
acc_strb[(C_RATIO-1)*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= (acc_reg_en[0] && C_RATIO > 2) | (state == SM_ACTIVE & r0_last) | (id_dest_mismatch & (state == SM_ACTIVE | state == SM_IDLE))
? {P_S_AXIS_TSTRB_WIDTH{1'b0}} : (state == SM_IDLE) | (state == SM_ACTIVE)
? S_AXIS_TSTRB : acc_strb[(C_RATIO-1)*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
acc_keep[(C_RATIO-1)*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= (acc_reg_en[0] && C_RATIO > 2) | (state == SM_ACTIVE & r0_last) | (id_dest_mismatch & (state == SM_ACTIVE| state == SM_IDLE))
? {P_S_AXIS_TSTRB_WIDTH{1'b0}} : (state == SM_IDLE) | (state == SM_ACTIVE)
? S_AXIS_TKEEP : acc_keep[(C_RATIO-1)*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
end
end
endgenerate
assign acc_reg_en = (state == SM_ACTIVE) ? r0_reg_sel : {C_RATIO{1'b0}};
// Accumulator selector (1 hot left barrel shifter)
always @(posedge ACLK) begin
if (ARESET) begin
r0_reg_sel[0] <= 1'b1;
r0_reg_sel[1+:C_RATIO-1] <= {C_RATIO{1'b0}};
end else if (ACLKEN) begin
r0_reg_sel[0] <= M_AXIS_TVALID & M_AXIS_TREADY ? 1'b1
: (state == SM_ACTIVE) ? 1'b0 : r0_reg_sel[0];
r0_reg_sel[1+:C_RATIO-1] <= M_AXIS_TVALID & M_AXIS_TREADY ? {C_RATIO-1{1'b0}}
: (state == SM_ACTIVE) ? r0_reg_sel[0+:C_RATIO-1] : r0_reg_sel[1+:C_RATIO-1];
end
end
assign next_xfer_is_end = (r0_reg_sel[C_RATIO-2] && (state == SM_ACTIVE)) | r0_reg_sel[C_RATIO-1];
always @(posedge ACLK) begin
if (ACLKEN) begin
r0_data <= S_AXIS_TREADY ? S_AXIS_TDATA : r0_data;
r0_strb <= S_AXIS_TREADY ? S_AXIS_TSTRB : r0_strb;
r0_keep <= S_AXIS_TREADY ? S_AXIS_TKEEP : r0_keep;
r0_last <= (!P_LAST_EXIST) ? 1'b0 : S_AXIS_TREADY ? S_AXIS_TLAST : r0_last;
r0_id <= (S_AXIS_TREADY & S_AXIS_TVALID) ? S_AXIS_TID : r0_id;
r0_dest <= (S_AXIS_TREADY & S_AXIS_TVALID) ? S_AXIS_TDEST : r0_dest;
r0_user <= S_AXIS_TREADY ? S_AXIS_TUSER : r0_user;
end
end
assign M_AXIS_TLAST = acc_last;
always @(posedge ACLK) begin
if (ACLKEN) begin
acc_last <= (state == SM_END | state == SM_END_TO_ACTIVE) ? acc_last :
(state == SM_ACTIVE & r0_last ) ? 1'b1 :
(id_dest_mismatch & (state == SM_IDLE)) ? 1'b0 :
(id_dest_mismatch & (state == SM_ACTIVE)) ? r0_last :
S_AXIS_TLAST;
end
end
assign M_AXIS_TID = acc_id;
assign M_AXIS_TDEST = acc_dest;
always @(posedge ACLK) begin
if (ACLKEN) begin
acc_id <= acc_reg_en[0] ? r0_id : acc_id;
acc_dest <= acc_reg_en[0] ? r0_dest : acc_dest;
end
end
assign id_match = P_ID_EXIST ? (S_AXIS_TID == r0_id) : 1'b1;
assign dest_match = P_DEST_EXIST ? (S_AXIS_TDEST == r0_dest) : 1'b1;
assign id_dest_mismatch = (~id_match | ~dest_match) ? 1'b1 : 1'b0;
endmodule // axisc_upsizer
`default_nettype wire
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_5_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_5_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=533.333313, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=14, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=49.5, PCW_UIPARAM_DDR_T_RAS_MIN=36.0, PCW_UIPARAM_DDR_T_FAW=45.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.025, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.028, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.009, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.061, PCW_UIPARAM_DDR_BOARD_DELAY0=0.41, PCW_UIPARAM_DDR_BOARD_DELAY1=0.411, PCW_UIPARAM_DDR_BOARD_DELAY2=0.341, PCW_UIPARAM_DDR_BOARD_DELAY3=0.358, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=68.4725, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=71.086, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=66.794, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=108.7385, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=64.1705, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=63.686, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=68.46, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=105.4895, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160\
, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666667, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100.000000, PCW_FPGA1_PERIPHERAL_FREQMHZ=150.000000, PCW_FPGA2_PERIPHERAL_FREQMHZ=50, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=32, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1066.667, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100\
, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_FTM_CTI_IN0=DISABLED, PCW_FTM_CTI_IN1=DISABLED, PCW_FTM_CTI_IN2=DISABLED, PCW_FTM_CTI_IN3=DISABLED, PCW_FTM_CTI_OUT0=DISABLED, PCW_FTM_CTI_OUT1=DISABLED, PCW_FTM_CTI_OUT2=DISABLED, PCW_FTM_CTI_OUT3=DISABLED, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41J128M16 HA-15E, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=1, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2\
, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 47, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=MIO 46, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0\
, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=EMIO, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=0, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X\
, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }" *)
(* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *)
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0,
// Enable and disable AFI Secure transaction
parameter C_USE_AXI_NONSECURE = 0,
//parameters for HP enable ports
parameter C_USE_S_AXI_HP0 = 0,
parameter C_USE_S_AXI_HP1 = 0,
parameter C_USE_S_AXI_HP2 = 0,
parameter C_USE_S_AXI_HP3 = 0,
//parameters for GP and ACP enable ports */
parameter C_USE_M_AXI_GP0 = 0,
parameter C_USE_M_AXI_GP1 = 0,
parameter C_USE_S_AXI_GP0 = 0,
parameter C_USE_S_AXI_GP1 = 0,
parameter C_USE_S_AXI_ACP = 0,
parameter C_GP0_EN_MODIFIABLE_TXN=0,
parameter C_GP1_EN_MODIFIABLE_TXN=0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN = 'b0,
output reg ENET0_GMII_TX_ER = 'b0,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN = 'b0,
output reg ENET1_GMII_TX_ER = 'b0,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
wire [3:0] M_AXI_GP0_ARCACHE_t;
wire [3:0] M_AXI_GP1_ARCACHE_t;
wire [3:0] M_AXI_GP0_AWCACHE_t;
wire [3:0] M_AXI_GP1_AWCACHE_t;
// Wires for connecting to the PS7
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
wire FCLK_CLK0_temp;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire S_AXI_HP0_ACLK_temp;
wire S_AXI_HP1_ACLK_temp;
wire S_AXI_HP2_ACLK_temp;
wire S_AXI_HP3_ACLK_temp;
wire M_AXI_GP0_ACLK_temp;
wire M_AXI_GP1_ACLK_temp;
wire S_AXI_GP0_ACLK_temp;
wire S_AXI_GP1_ACLK_temp;
wire S_AXI_ACP_ACLK_temp;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
(* keep = "true" *) reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
(* keep = "true" *) reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
else
begin
always @*
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= 1'b0;
TRACE_DATA_PIPE[j-1] <= 1'b0;
end
TRACE_CLK_OUT <= 1'b0;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
else
always@*
begin
ENET0_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= 'b0;
ENET0_GMII_CRS_i <= 'b0;
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET0_GMII_RXD_i <= 0;
ENET0_GMII_RX_DV_i <= 0;
ENET0_GMII_RX_ER_i <= 0;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
else
begin
always@*
begin
ENET1_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET1_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET1_GMII_COL_i <= 0;
ENET1_GMII_CRS_i <= 0;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET1_GMII_RXD_i <= 'b0;
ENET1_GMII_RX_DV_i <= 'b0;
ENET1_GMII_RX_ER_i <= 'b0;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
else
begin
assign FTMD_TRACEIN_DATA_i = 1'b0;
assign FTMD_TRACEIN_VALID_i = 1'b0;
assign FTMD_TRACEIN_ATID_i = 1'b0;
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
else
begin
assign PJTAG_TDO = 1'b0;
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
assign FCLK_CLK0 = FCLK_CLK0_temp;
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
// Connect FCLK in case of disable the AXI port for non Secure Transaction
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin
assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin
assign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin
assign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin
assign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP3_ACLK_temp = S_AXI_HP3_ACLK;
end
endgenerate
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin
assign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin
assign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin
assign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin
assign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin
assign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK;
end
endgenerate
assign M_AXI_GP0_ARCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_ARCACHE_t[3:2]},{1'b1},{M_AXI_GP0_ARCACHE_t[0]}}:M_AXI_GP0_ARCACHE_t ;
assign M_AXI_GP1_ARCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_ARCACHE_t[3:2]},{1'b1},{M_AXI_GP1_ARCACHE_t[0]}}:M_AXI_GP1_ARCACHE_t ;
assign M_AXI_GP0_AWCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_AWCACHE_t[3:2]},{1'b1},{M_AXI_GP0_AWCACHE_t[0]}}:M_AXI_GP0_AWCACHE_t ;
assign M_AXI_GP1_AWCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_AWCACHE_t[3:2]},{1'b1},{M_AXI_GP1_AWCACHE_t[0]}}:M_AXI_GP1_AWCACHE_t ;
//END
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), //(ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE_t),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE_t),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE_t),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE_t),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), // (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE_t),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE_t),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE_t),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE_t),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK_temp),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t;
// verilator lint_off LITENDIAN
reg [5:0] binary_nostart [2:15];
reg [5:0] binary_start [0:15];
reg [175:0] hex [0:15];
// verilator lint_on LITENDIAN
integer i;
initial begin
begin
$readmemb("t/t_sys_readmem_b.mem", binary_nostart);
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_nostart[i]);
`endif
if (binary_nostart['h2] != 6'h02) $stop;
if (binary_nostart['h3] != 6'h03) $stop;
if (binary_nostart['h4] != 6'h04) $stop;
if (binary_nostart['h5] != 6'h05) $stop;
if (binary_nostart['h6] != 6'h06) $stop;
if (binary_nostart['h7] != 6'h07) $stop;
if (binary_nostart['h8] != 6'h10) $stop;
if (binary_nostart['hc] != 6'h14) $stop;
if (binary_nostart['hd] != 6'h15) $stop;
end
begin
$readmemb("t/t_sys_readmem_b_8.mem", binary_start, 4, 4+7);
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_start[i]);
`endif
if (binary_start['h04] != 6'h10) $stop;
if (binary_start['h05] != 6'h11) $stop;
if (binary_start['h06] != 6'h12) $stop;
if (binary_start['h07] != 6'h13) $stop;
if (binary_start['h08] != 6'h14) $stop;
if (binary_start['h09] != 6'h15) $stop;
if (binary_start['h0a] != 6'h16) $stop;
if (binary_start['h0b] != 6'h17) $stop;
end
begin
$readmemh("t/t_sys_readmem_h.mem", hex, 0);
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, hex[i]);
`endif
if (hex['h04] != 176'h400437654321276543211765432107654321abcdef10) $stop;
if (hex['h0a] != 176'h400a37654321276543211765432107654321abcdef11) $stop;
if (hex['h0b] != 176'h400b37654321276543211765432107654321abcdef12) $stop;
if (hex['h0c] != 176'h400c37654321276543211765432107654321abcdef13) $stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_compare.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// This block stores the request for this bank machine.
//
// All possible new requests are compared against the request stored
// here. The compare results are shared with the bank machines and
// is used to determine where to enqueue a new request.
`timescale 1ps/1ps
module mig_7series_v2_3_bank_compare #
(parameter BANK_WIDTH = 3,
parameter TCQ = 100,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter ECC = "OFF",
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter ROW_WIDTH = 16)
(/*AUTOARG*/
// Outputs
req_data_buf_addr_r, req_periodic_rd_r, req_size_r, rd_wr_r,
req_rank_r, req_bank_r, req_row_r, req_wr_r, req_priority_r,
rb_hit_busy_r, rb_hit_busy_ns, row_hit_r, maint_hit, col_addr,
req_ras, req_cas, row_cmd_wr, row_addr, rank_busy_r,
// Inputs
clk, idle_ns, idle_r, data_buf_addr, periodic_rd_insert, size, cmd,
sending_col, rank, periodic_rd_rank_r, bank, row, col, hi_priority,
maint_rank_r, maint_zq_r, maint_sre_r, auto_pre_r, rd_half_rmw, act_wait_r
);
input clk;
input idle_ns;
input idle_r;
input [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;
output reg [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
wire [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_ns =
idle_r
? data_buf_addr
: req_data_buf_addr_r;
always @(posedge clk) req_data_buf_addr_r <= #TCQ req_data_buf_addr_ns;
input periodic_rd_insert;
reg req_periodic_rd_r_lcl;
wire req_periodic_rd_ns = idle_ns
? periodic_rd_insert
: req_periodic_rd_r_lcl;
always @(posedge clk) req_periodic_rd_r_lcl <= #TCQ req_periodic_rd_ns;
output wire req_periodic_rd_r;
assign req_periodic_rd_r = req_periodic_rd_r_lcl;
input size;
wire req_size_r_lcl;
generate
if (BURST_MODE == "4") begin : burst_mode_4
assign req_size_r_lcl = 1'b0;
end
else
if (BURST_MODE == "8") begin : burst_mode_8
assign req_size_r_lcl = 1'b1;
end
else
if (BURST_MODE == "OTF") begin : burst_mode_otf
reg req_size;
wire req_size_ns = idle_ns
? (periodic_rd_insert || size)
: req_size;
always @(posedge clk) req_size <= #TCQ req_size_ns;
assign req_size_r_lcl = req_size;
end
endgenerate
output wire req_size_r;
assign req_size_r = req_size_r_lcl;
input [2:0] cmd;
reg [2:0] req_cmd_r;
wire [2:0] req_cmd_ns = idle_ns
? (periodic_rd_insert ? 3'b001 : cmd)
: req_cmd_r;
always @(posedge clk) req_cmd_r <= #TCQ req_cmd_ns;
`ifdef MC_SVA
rd_wr_only_wo_ecc: assert property
(@(posedge clk) ((ECC != "OFF") || idle_ns || ~|req_cmd_ns[2:1]));
`endif
input sending_col;
reg rd_wr_r_lcl;
wire rd_wr_ns = idle_ns
? ((req_cmd_ns[1:0] == 2'b11) || req_cmd_ns[0])
: ~sending_col && rd_wr_r_lcl;
always @(posedge clk) rd_wr_r_lcl <= #TCQ rd_wr_ns;
output wire rd_wr_r;
assign rd_wr_r = rd_wr_r_lcl;
input [RANK_WIDTH-1:0] rank;
input [RANK_WIDTH-1:0] periodic_rd_rank_r;
reg [RANK_WIDTH-1:0] req_rank_r_lcl = {RANK_WIDTH{1'b0}};
reg [RANK_WIDTH-1:0] req_rank_ns = {RANK_WIDTH{1'b0}};
generate
if (RANKS != 1) begin
always @(/*AS*/idle_ns or periodic_rd_insert
or periodic_rd_rank_r or rank or req_rank_r_lcl) req_rank_ns = idle_ns
? periodic_rd_insert
? periodic_rd_rank_r
: rank
: req_rank_r_lcl;
always @(posedge clk) req_rank_r_lcl <= #TCQ req_rank_ns;
end
endgenerate
output wire [RANK_WIDTH-1:0] req_rank_r;
assign req_rank_r = req_rank_r_lcl;
input [BANK_WIDTH-1:0] bank;
reg [BANK_WIDTH-1:0] req_bank_r_lcl;
wire [BANK_WIDTH-1:0] req_bank_ns = idle_ns ? bank : req_bank_r_lcl;
always @(posedge clk) req_bank_r_lcl <= #TCQ req_bank_ns;
output wire[BANK_WIDTH-1:0] req_bank_r;
assign req_bank_r = req_bank_r_lcl;
input [ROW_WIDTH-1:0] row;
reg [ROW_WIDTH-1:0] req_row_r_lcl;
wire [ROW_WIDTH-1:0] req_row_ns = idle_ns ? row : req_row_r_lcl;
always @(posedge clk) req_row_r_lcl <= #TCQ req_row_ns;
output wire [ROW_WIDTH-1:0] req_row_r;
assign req_row_r = req_row_r_lcl;
// Make req_col_r as wide as the max row address. This
// makes it easier to deal with indexing different column widths.
input [COL_WIDTH-1:0] col;
reg [15:0] req_col_r = 16'b0;
wire [COL_WIDTH-1:0] req_col_ns = idle_ns ? col : req_col_r[COL_WIDTH-1:0];
always @(posedge clk) req_col_r[COL_WIDTH-1:0] <= #TCQ req_col_ns;
reg req_wr_r_lcl;
wire req_wr_ns = idle_ns
? ((req_cmd_ns[1:0] == 2'b11) || ~req_cmd_ns[0])
: req_wr_r_lcl;
always @(posedge clk) req_wr_r_lcl <= #TCQ req_wr_ns;
output wire req_wr_r;
assign req_wr_r = req_wr_r_lcl;
input hi_priority;
output reg req_priority_r;
wire req_priority_ns = idle_ns ? hi_priority : req_priority_r;
always @(posedge clk) req_priority_r <= #TCQ req_priority_ns;
wire rank_hit = (req_rank_r_lcl == (periodic_rd_insert
? periodic_rd_rank_r
: rank));
wire bank_hit = (req_bank_r_lcl == bank);
wire rank_bank_hit = rank_hit && bank_hit;
output reg rb_hit_busy_r; // rank-bank hit on non idle row machine
wire rb_hit_busy_ns_lcl;
assign rb_hit_busy_ns_lcl = rank_bank_hit && ~idle_ns;
output wire rb_hit_busy_ns;
assign rb_hit_busy_ns = rb_hit_busy_ns_lcl;
wire row_hit_ns = (req_row_r_lcl == row);
output reg row_hit_r;
always @(posedge clk) rb_hit_busy_r <= #TCQ rb_hit_busy_ns_lcl;
always @(posedge clk) row_hit_r <= #TCQ row_hit_ns;
input [RANK_WIDTH-1:0] maint_rank_r;
input maint_zq_r;
input maint_sre_r;
output wire maint_hit;
assign maint_hit = (req_rank_r_lcl == maint_rank_r) || maint_zq_r || maint_sre_r;
// Assemble column address. Structure to be the same
// width as the row address. This makes it easier
// for the downstream muxing. Depending on the sizes
// of the row and column addresses, fill in as appropriate.
input auto_pre_r;
input rd_half_rmw;
reg [15:0] col_addr_template = 16'b0;
always @(/*AS*/auto_pre_r or rd_half_rmw or req_col_r
or req_size_r_lcl) begin
col_addr_template = req_col_r;
col_addr_template[10] = auto_pre_r && ~rd_half_rmw;
col_addr_template[11] = req_col_r[10];
col_addr_template[12] = req_size_r_lcl;
col_addr_template[13] = req_col_r[11];
end
output wire [ROW_WIDTH-1:0] col_addr;
assign col_addr = col_addr_template[ROW_WIDTH-1:0];
output wire req_ras;
output wire req_cas;
output wire row_cmd_wr;
input act_wait_r;
assign req_ras = 1'b0;
assign req_cas = 1'b1;
assign row_cmd_wr = act_wait_r;
output reg [ROW_WIDTH-1:0] row_addr;
always @(/*AS*/act_wait_r or req_row_r_lcl) begin
row_addr = req_row_r_lcl;
// This causes all precharges to be precharge single bank command.
if (~act_wait_r) row_addr[10] = 1'b0;
end
// Indicate which, if any, rank this bank machine is busy with.
// Not registering the result would probably be more accurate, but
// would create timing issues. This is used for refresh banking, perfect
// accuracy is not required.
localparam ONE = 1;
output reg [RANKS-1:0] rank_busy_r;
wire [RANKS-1:0] rank_busy_ns = {RANKS{~idle_ns}} & (ONE[RANKS-1:0] << req_rank_ns);
always @(posedge clk) rank_busy_r <= #TCQ rank_busy_ns;
endmodule // bank_compare
|
`timescale 1ps/1ps
module sim_fsusb_foot
(inout dp,
inout dm);
localparam HALFBIT = 41667;
localparam BIT = 83333;
reg vp_noise_inject;
reg vm_noise_inject;
reg vm_noise, vp_noise;
integer delay_amount;
initial begin
vp_noise = 1'b0;
vp_noise_inject = 1'b0;
#1_200_000_000;
forever begin
vp_noise = ~vp_noise;
vp_noise_inject = 1'b0;
#232238251;
vp_noise_inject = 1'b1;
#1895231;
end
end
initial begin
vm_noise = 1'b0;
vm_noise_inject = 1'b0;
#1_300_000_000;
forever begin
vm_noise = ~vm_noise;
vm_noise_inject = 1'b0;
#158983124;
vm_noise_inject = 1'b1;
#832389;
vm_noise_inject = 1'b0;
end
end
reg oe = 1'b0;
reg vp = 1'b1;
reg vm = 1'b0;
assign dp = vp_noise_inject ? vp_noise : (oe ? vp : 1'bz);
assign dm = vm_noise_inject ? vm_noise : (oe ? vm : 1'bz);
integer i;
wire [7:0] sync = 8'b1101_0101;
reg decoded, prev_state, save_bit;
integer byte_count, bit_count, num_rx_ones;
reg [7:0] rx_byte;
reg [7:0] rx_pkt[63:0];
`include "usb_pids.v"
`include "usb_defs.v"
integer tx_num_ones = 0;
/*
task tx_sync;
integer bit_cnt;
begin
vp = 1'b1;
vm = 1'b0;
oe = 1'b1;
#BIT;
for (bit_cnt = 0; bit_cnt < 8; bit_cnt = bit_cnt + 1) begin
vp = sync[bit_cnt];
vm = ~sync[bit_cnt];
#BIT;
end
tx_nrzi = 1'b1;
tx_prev_bit = 1'b1;
tx_num_ones = 1'b1;
end
endtask
*/
task tx_byte;
input [7:0] byte;
integer bit_cnt;
reg bit;
begin
for (bit_cnt = 0; bit_cnt < 8; bit_cnt = bit_cnt + 1) begin
bit = byte[bit_cnt]; // save some typing
if (bit) begin
tx_num_ones = tx_num_ones + 1'b1;
if (tx_num_ones >= 7) begin
// bit stuffing... throw a bit-flip in there
//nrzi = ~nrzi;
vp = ~vp;
vm = ~vm;
#BIT;
tx_num_ones = 0;
end
#BIT; // to send a "1" we just leave the lines the same
end else begin
// to send a "0" we toggle the lines
vp = ~vp;
vm = ~vm;
#BIT;
tx_num_ones = 0;
end
end
end
endtask
task tx_32bits_be;
input [31:0] bits;
begin
tx_byte(bits[31:24]);
tx_byte(bits[23:16]);
tx_byte(bits[15:8]);
tx_byte(bits[7:0]);
end
endtask
task tx_eop;
begin
vp = 1'b0;
vm = 1'b0;
#BIT;
#BIT;
vp = 1'b1;
#BIT;
oe = 1'b0;
end
endtask
task tx_warmup;
begin
oe = 1'b1;
vp = 1'b1;
vm = 1'b0;
#BIT;
end
endtask
task rx_data0;
integer len;
begin
len = byte_count - 3;
$display("%t rx data0 len %d ", $time, len);
#(2*BIT);
tx_warmup();
tx_byte(USB_SYNC);
tx_byte(PID_ACK);
tx_eop();
end
endtask
integer rx_in_cnt = 0;
task rx_in;
begin
$display("%t rx IN", $time);
#(2*BIT);
tx_warmup();
tx_byte(USB_SYNC);
if (rx_in_cnt == 0) begin
$display("%t sending NAK", $time);
tx_byte(PID_NAK);
end else if (rx_in_cnt == 5) begin
$display("not transmitting anything in response to this IN request...");
end else begin
if (rx_pkt[1] == 8'h91) begin
$display("%t received IN pkt on EP1", $time);
tx_byte(PID_DATA1); // TODO: toggle data0 / data1
tx_foot_pkt();
/*
for (i = 0; i < 64; i = i + 1) begin
//$display("%t tx 0x%02h", $time, 64-i);
tx_byte(64-i);
end
*/
end else if (rx_pkt[1] == 8'h00 | rx_pkt[1] == 8'h01 | rx_pkt[1] == USB_DEV_ADDR) begin
$display("%t responding to IN pkt on EP0", $time);
tx_byte(PID_DATA1);
// for now, always just a zero-length packet
tx_byte(0);
tx_byte(0);
end else begin
$display("%t unhandled IN request!", $time);
for (i = 0; i < 64; i = i + 1) begin
$display("rx %d = 0x%02h", $time, rx_pkt[i]);
//$display("%t tx 0x%02h", $time, 64-i);
//tx_byte(64-i);
end
end
end
tx_eop();
rx_in_cnt = rx_in_cnt + 1;
end
endtask
task tx_foot_pkt;
begin
tx_32bits_be(32'h0000abcd);
tx_32bits_be(32'h12345678);
tx_32bits_be(32'h01000200); // 0
tx_32bits_be(32'h03000400); // 2
tx_32bits_be(32'h05000600); // 4
tx_32bits_be(32'h07000800); // 6
tx_32bits_be(32'h09000a00); // 8
tx_32bits_be(32'h0b000c00); // 10
tx_32bits_be(32'h0d000e00); // 12
tx_32bits_be(32'h0f001000); // 14
tx_32bits_be(32'h00000000);
tx_32bits_be(32'h0);
tx_32bits_be(32'h0);
tx_32bits_be(32'h0);
tx_32bits_be(32'h0);
tx_32bits_be(32'h0);
end
endtask
initial begin
oe = 1'b0;
vp = 1'b0;
vm = 1'b0;
//$printtimescale;
// wait for USB reset
wait(~dp && ~dm);
$display("%t usb reset start", $time);
wait(dp && ~dm);
$display("%t usb reset end", $time); // todo: time reset pulse length
wait(~dp && ~dm);
$display("%t usb reset2 start", $time);
wait(dp && ~dm);
$display("%t usb reset2 end", $time); // todo: time reset pulse length
forever begin
num_rx_ones = 0;
bit_count = 0;
byte_count = 0;
rx_byte = 8'h0;
prev_state = 1;
decoded = 0;
save_bit = 1; // this is set to 0 when we get a stuffed bit
wait(~dp);
//$display("%t fsusb pkt start", $time);
#41667; // shift to the middle of a bit period
for (i = 0; i < 8; i = i + 1) begin
//$display("%t sync bit", $time);
if (dp != ~dm) begin
$display("illegal usb state at %t", $time);
//#1000 $finish();
end
if (sync[i] != dm) begin
$display("sync fail at %t", $time);
//#1000 $finish();
end
#83333; // skip over a full bit
end
//$display("%t sync OK", $time);
// decode the NRZI data
while (~(dp == 0 & dm == 0)) begin
if (dp != ~dm) begin
$display("%t illegal usb state", $time);
//#1000 $finish();
end
if (prev_state != dm) begin
decoded = 0;
prev_state = dm;
if (num_rx_ones == 6) begin
$display("%t stuffed bit detected", $time);
save_bit = 0; // it's a stuffed bit; ignore it
end
else
save_bit = 1;
num_rx_ones = 0;
//$display("%t rx flip @ %d", $time, bit_count);
end else begin
decoded = 1;
num_rx_ones = num_rx_ones + 1;
save_bit = 1; // ones are never stuffed
if (num_rx_ones > 6) begin
$display("%t received more than 6 ones in a row.", $time);
//#100000 $finish();
end
//$display("%t rx same @ %d", $time, bit_count);
end
if (save_bit) begin
rx_byte = { decoded, rx_byte[7:1] };
bit_count = bit_count + 1;
end
if (bit_count == 8) begin
rx_pkt[byte_count] = rx_byte;
if (byte_count == 0) begin
case (rx_byte)
PID_SOF: $display("%t SOF", $time);
PID_SETUP: $display("%t SETUP", $time);
PID_DATA0: $display("%t DATA0", $time);
PID_IN : $display("%t IN", $time);
PID_ACK : $display("%t ACK", $time);
default: begin
$display("%t ERROR: rx unknown PID (0x%02h)", $time, rx_byte);
//$finish();
end
endcase
end
else
$display("%t rx 0x%02h", $time, rx_byte);
byte_count = byte_count + 1;
bit_count = 0;
end
#83333; // skip over a full bit
end
if (num_rx_ones == 6) begin
$display("%t expected to see bit-stuffing right before SE0", $time);
//#100000 $finish();
end
if (bit_count != 0) begin
$display("%t SE0 seen at non-byte boundary", $time);
//#5000 $finish();
end
//$display("%t found SE0", $time);
#83333;
if (dp != 0 | dm != 0) begin
$display("%t SE0 state wasn't two bits long", $time);
//#1000 $finish();
end
#83333;
if (dp != 1 | dm != 0) begin
$display("%t didn't finish EOP with J state", $time);
//#1000 $finish();
end
#83.333;
$display("%t packet RX complete", $time);
case (rx_pkt[0])
PID_SOF: ;
PID_SETUP: ;
PID_DATA0: rx_data0();
PID_IN: rx_in();
PID_ACK: ;
default: begin
$display("%t unknown rx PID (0x%02h)", $time, rx_pkt[0]);
//$finish();
end
endcase
//if (rx_pkt[0] == PID_DATA0)
// rx_data0();
end
end
endmodule
|
/*
Copyright (c) 2014-2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "XILINX"
)
(
/*
* Clock: 156.25MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
output wire [7:0] led_red,
output wire [7:0] led_green,
output wire [1:0] led_bmc,
output wire [1:0] led_exp,
/*
* Ethernet: QSFP28
*/
input wire qsfp_0_tx_clk_0,
input wire qsfp_0_tx_rst_0,
output wire [63:0] qsfp_0_txd_0,
output wire [7:0] qsfp_0_txc_0,
input wire qsfp_0_rx_clk_0,
input wire qsfp_0_rx_rst_0,
input wire [63:0] qsfp_0_rxd_0,
input wire [7:0] qsfp_0_rxc_0,
input wire qsfp_0_tx_clk_1,
input wire qsfp_0_tx_rst_1,
output wire [63:0] qsfp_0_txd_1,
output wire [7:0] qsfp_0_txc_1,
input wire qsfp_0_rx_clk_1,
input wire qsfp_0_rx_rst_1,
input wire [63:0] qsfp_0_rxd_1,
input wire [7:0] qsfp_0_rxc_1,
input wire qsfp_0_tx_clk_2,
input wire qsfp_0_tx_rst_2,
output wire [63:0] qsfp_0_txd_2,
output wire [7:0] qsfp_0_txc_2,
input wire qsfp_0_rx_clk_2,
input wire qsfp_0_rx_rst_2,
input wire [63:0] qsfp_0_rxd_2,
input wire [7:0] qsfp_0_rxc_2,
input wire qsfp_0_tx_clk_3,
input wire qsfp_0_tx_rst_3,
output wire [63:0] qsfp_0_txd_3,
output wire [7:0] qsfp_0_txc_3,
input wire qsfp_0_rx_clk_3,
input wire qsfp_0_rx_rst_3,
input wire [63:0] qsfp_0_rxd_3,
input wire [7:0] qsfp_0_rxc_3,
input wire qsfp_1_tx_clk_0,
input wire qsfp_1_tx_rst_0,
output wire [63:0] qsfp_1_txd_0,
output wire [7:0] qsfp_1_txc_0,
input wire qsfp_1_rx_clk_0,
input wire qsfp_1_rx_rst_0,
input wire [63:0] qsfp_1_rxd_0,
input wire [7:0] qsfp_1_rxc_0,
input wire qsfp_1_tx_clk_1,
input wire qsfp_1_tx_rst_1,
output wire [63:0] qsfp_1_txd_1,
output wire [7:0] qsfp_1_txc_1,
input wire qsfp_1_rx_clk_1,
input wire qsfp_1_rx_rst_1,
input wire [63:0] qsfp_1_rxd_1,
input wire [7:0] qsfp_1_rxc_1,
input wire qsfp_1_tx_clk_2,
input wire qsfp_1_tx_rst_2,
output wire [63:0] qsfp_1_txd_2,
output wire [7:0] qsfp_1_txc_2,
input wire qsfp_1_rx_clk_2,
input wire qsfp_1_rx_rst_2,
input wire [63:0] qsfp_1_rxd_2,
input wire [7:0] qsfp_1_rxc_2,
input wire qsfp_1_tx_clk_3,
input wire qsfp_1_tx_rst_3,
output wire [63:0] qsfp_1_txd_3,
output wire [7:0] qsfp_1_txc_3,
input wire qsfp_1_rx_clk_3,
input wire qsfp_1_rx_rst_3,
input wire [63:0] qsfp_1_rxd_3,
input wire [7:0] qsfp_1_rxc_3
);
// AXI between MAC and Ethernet modules
wire [63:0] rx_axis_tdata;
wire [7:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [63:0] tx_axis_tdata;
wire [7:0] tx_axis_tkeep;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [63:0] rx_eth_payload_axis_tdata;
wire [7:0] rx_eth_payload_axis_tkeep;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [63:0] tx_eth_payload_axis_tdata;
wire [7:0] tx_eth_payload_axis_tkeep;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [63:0] rx_ip_payload_axis_tdata;
wire [7:0] rx_ip_payload_axis_tkeep;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [63:0] tx_ip_payload_axis_tdata;
wire [7:0] tx_ip_payload_axis_tkeep;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [63:0] rx_udp_payload_axis_tdata;
wire [7:0] rx_udp_payload_axis_tkeep;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [63:0] tx_udp_payload_axis_tdata;
wire [7:0] tx_udp_payload_axis_tkeep;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [63:0] rx_fifo_udp_payload_axis_tdata;
wire [7:0] rx_fifo_udp_payload_axis_tkeep;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [63:0] tx_fifo_udp_payload_axis_tdata;
wire [7:0] tx_fifo_udp_payload_axis_tkeep;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tkeep = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
valid_last <= tx_udp_payload_axis_tvalid;
if (tx_udp_payload_axis_tvalid && !valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
end
end
end
assign led_red = led_reg;
assign led_green = led_reg;
assign led_bmc = 2'b00;
assign led_exp = 2'b11;
assign qsfp_0_txd_1 = 64'h0707070707070707;
assign qsfp_0_txc_1 = 8'hff;
assign qsfp_0_txd_2 = 64'h0707070707070707;
assign qsfp_0_txc_2 = 8'hff;
assign qsfp_0_txd_3 = 64'h0707070707070707;
assign qsfp_0_txc_3 = 8'hff;
assign qsfp_1_txd_0 = 64'h0707070707070707;
assign qsfp_1_txc_0 = 8'hff;
assign qsfp_1_txd_1 = 64'h0707070707070707;
assign qsfp_1_txc_1 = 8'hff;
assign qsfp_1_txd_2 = 64'h0707070707070707;
assign qsfp_1_txc_2 = 8'hff;
assign qsfp_1_txd_3 = 64'h0707070707070707;
assign qsfp_1_txc_3 = 8'hff;
eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
.rx_clk(qsfp_0_rx_clk_0),
.rx_rst(qsfp_0_rx_rst_0),
.tx_clk(qsfp_0_tx_clk_0),
.tx_rst(qsfp_0_tx_rst_0),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.xgmii_rxd(qsfp_0_rxd_0),
.xgmii_rxc(qsfp_0_rxc_0),
.xgmii_txd(qsfp_0_txd_0),
.xgmii_txc(qsfp_0_txc_0),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
);
eth_axis_rx #(
.DATA_WIDTH(64)
)
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tkeep(rx_axis_tkeep),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx #(
.DATA_WIDTH(64)
)
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tkeep(tx_axis_tkeep),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete_64
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(1'b0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
`resetall
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module controls VGA output for Altera's DE1 and DE2 Boards. *
* *
******************************************************************************/
module niosII_system_video_vga_controller_0 (
// Inputs
clk,
reset,
data,
startofpacket,
endofpacket,
empty,
valid,
// Bidirectionals
// Outputs
ready,
VGA_CLK,
VGA_BLANK,
VGA_SYNC,
VGA_HS,
VGA_VS,
VGA_R,
VGA_G,
VGA_B
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9;
parameter DW = 29;
parameter R_UI = 29;
parameter R_LI = 20;
parameter G_UI = 19;
parameter G_LI = 10;
parameter B_UI = 9;
parameter B_LI = 0;
/* Number of pixels */
parameter H_ACTIVE = 640;
parameter H_FRONT_PORCH = 16;
parameter H_SYNC = 96;
parameter H_BACK_PORCH = 48;
parameter H_TOTAL = 800;
/* Number of lines */
parameter V_ACTIVE = 480;
parameter V_FRONT_PORCH = 10;
parameter V_SYNC = 2;
parameter V_BACK_PORCH = 33;
parameter V_TOTAL = 525;
parameter LW = 10;
parameter LINE_COUNTER_INCREMENT = 10'h001;
parameter PW = 10;
parameter PIXEL_COUNTER_INCREMENT = 10'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] data;
input startofpacket;
input endofpacket;
input [ 1: 0] empty;
input valid;
// Bidirectionals
// Outputs
output ready;
output VGA_CLK;
output reg VGA_BLANK;
output reg VGA_SYNC;
output reg VGA_HS;
output reg VGA_VS;
output reg [CW: 0] VGA_R;
output reg [CW: 0] VGA_G;
output reg [CW: 0] VGA_B;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
localparam STATE_0_SYNC_FRAME = 1'b0,
STATE_1_DISPLAY = 1'b1;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_enable;
wire end_of_active_frame;
wire vga_blank_sync;
wire vga_c_sync;
wire vga_h_sync;
wire vga_v_sync;
wire vga_data_enable;
wire [CW: 0] vga_red;
wire [CW: 0] vga_green;
wire [CW: 0] vga_blue;
wire [CW: 0] vga_color_data;
// Internal Registers
reg [ 3: 0] color_select; // Use for the TRDB_LCM
// State Machine Registers
reg ns_mode;
reg s_mode;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk) // sync reset
begin
if (reset == 1'b1)
s_mode <= STATE_0_SYNC_FRAME;
else
s_mode <= ns_mode;
end
always @(*)
begin
// Defaults
ns_mode = STATE_0_SYNC_FRAME;
case (s_mode)
STATE_0_SYNC_FRAME:
begin
if (valid & startofpacket)
ns_mode = STATE_1_DISPLAY;
else
ns_mode = STATE_0_SYNC_FRAME;
end
STATE_1_DISPLAY:
begin
if (end_of_active_frame)
ns_mode = STATE_0_SYNC_FRAME;
else
ns_mode = STATE_1_DISPLAY;
end
default:
begin
ns_mode = STATE_0_SYNC_FRAME;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
VGA_BLANK <= vga_blank_sync;
VGA_SYNC <= 1'b0;
VGA_HS <= vga_h_sync;
VGA_VS <= vga_v_sync;
VGA_R <= vga_red;
VGA_G <= vga_green;
VGA_B <= vga_blue;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
color_select <= 4'h1;
else if (s_mode == STATE_0_SYNC_FRAME)
color_select <= 4'h1;
else if (~read_enable)
color_select <= {color_select[2:0], color_select[3]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign ready =
(s_mode == STATE_0_SYNC_FRAME) ?
valid & ~startofpacket :
read_enable;
assign VGA_CLK = ~clk;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_avalon_video_vga_timing VGA_Timing (
// Inputs
.clk (clk),
.reset (reset),
.red_to_vga_display (data[R_UI:R_LI]),
.green_to_vga_display (data[G_UI:G_LI]),
.blue_to_vga_display (data[B_UI:B_LI]),
.color_select (color_select),
// .data_valid (1'b1),
// Bidirectionals
// Outputs
.read_enable (read_enable),
.end_of_active_frame (end_of_active_frame),
.end_of_frame (), // (end_of_frame),
// dac pins
.vga_blank (vga_blank_sync),
.vga_c_sync (vga_c_sync),
.vga_h_sync (vga_h_sync),
.vga_v_sync (vga_v_sync),
.vga_data_enable (vga_data_enable),
.vga_red (vga_red),
.vga_green (vga_green),
.vga_blue (vga_blue),
.vga_color_data (vga_color_data)
);
defparam
VGA_Timing.CW = CW,
VGA_Timing.H_ACTIVE = H_ACTIVE,
VGA_Timing.H_FRONT_PORCH = H_FRONT_PORCH,
VGA_Timing.H_SYNC = H_SYNC,
VGA_Timing.H_BACK_PORCH = H_BACK_PORCH,
VGA_Timing.H_TOTAL = H_TOTAL,
VGA_Timing.V_ACTIVE = V_ACTIVE,
VGA_Timing.V_FRONT_PORCH = V_FRONT_PORCH,
VGA_Timing.V_SYNC = V_SYNC,
VGA_Timing.V_BACK_PORCH = V_BACK_PORCH,
VGA_Timing.V_TOTAL = V_TOTAL,
VGA_Timing.LW = LW,
VGA_Timing.LINE_COUNTER_INCREMENT = LINE_COUNTER_INCREMENT,
VGA_Timing.PW = PW,
VGA_Timing.PIXEL_COUNTER_INCREMENT = PIXEL_COUNTER_INCREMENT;
endmodule
|
module testbench;
localparam width_lp = 4;
localparam els_lp = 2;
logic clk;
bsg_nonsynth_clock_gen #(
.cycle_time_p(1000)
) clock_gen (
.o(clk)
);
logic reset;
bsg_nonsynth_reset_gen #(
.num_clocks_p(1)
,.reset_cycles_lo_p(4)
,.reset_cycles_hi_p(4)
) reset_gen (
.clk_i(clk)
,.async_reset_o(reset)
);
logic [width_lp-1:0] test_data_li;
logic test_v_li, test_ready_lo;
logic [width_lp-1:0] test_data_lo;
logic test_v_lo, test_yumi_li;
logic [width_lp-1:0] fifo_data_li;
logic fifo_v_li, fifo_ready_lo;
logic [width_lp-1:0] fifo_data_lo;
logic fifo_v_lo, fifo_yumi_li;
bsg_fifo_bypass
#(.width_p(width_lp))
DUT
(.data_i(test_data_li)
,.v_i(test_v_li)
,.ready_o(test_ready_lo)
,.data_o(test_data_lo)
,.v_o(test_v_lo)
,.yumi_i(test_yumi_li)
,.fifo_data_o(fifo_data_li)
,.fifo_v_o(fifo_v_li)
,.fifo_ready_i(fifo_ready_lo)
,.fifo_data_i(fifo_data_lo)
,.fifo_v_i(fifo_v_lo)
,.fifo_yumi_o(fifo_yumi_li)
);
bsg_fifo_1r1w_small
#(.width_p(width_lp)
,.els_p(els_lp)
)
fifo
(.clk_i(clk)
,.reset_i(reset)
,.data_i(fifo_data_li)
,.v_i(fifo_v_li)
,.ready_o(fifo_ready_lo)
,.data_o(fifo_data_lo)
,.v_o(fifo_v_lo)
,.yumi_i(fifo_yumi_li)
);
initial
begin
test_data_li = '0;
test_v_li = '0;
test_yumi_li = '0;
@(negedge reset);
@(posedge clk);
$display("Testing bypass");
test_data_li = 4'h3;
test_v_li = 1'b1;
#1
test_yumi_li = test_v_lo;
@(negedge clk);
$display("Checking that data is bypassed");
assert (test_data_lo == test_data_li);
assert (test_v_lo == 1'b1);
@(posedge clk);
test_v_li = 1'b0;
test_yumi_li = 1'b0;
$display("Checking bypassed data did not enqueue in fifo");
@(negedge clk);
assert (fifo_v_lo == 1'b0);
@(posedge clk);
$display("Testing enqueue");
test_data_li = 4'hf;
test_v_li = 1'b1;
#1
test_yumi_li = 1'b0;
@(negedge clk);
$display("Checking that data is bypassed");
assert (test_data_lo == test_data_li);
assert (test_v_lo == 1'b1);
@(posedge clk);
test_v_li = 1'b0;
$display("Checking that data was enqueued on fifo");
@(negedge clk);
assert (fifo_v_lo == 1'b1);
assert (fifo_data_lo == test_data_li);
@(posedge clk);
$display("Testing dequeue during enqueue");
test_data_li = 4'h0;
test_v_li = 1'b1;
#1
test_yumi_li = 1'b1;
@(negedge clk);
$display("Checking that data is coming from fifo, not bypass");
assert (test_data_lo == fifo_data_lo);
assert (test_v_lo == 1'b1);
@(posedge clk);
test_v_li = 1'b0;
test_yumi_li = 1'b0;
$display("Checking that data is coming from next in fifo");
@(negedge clk);
assert (test_data_lo == test_data_li);
assert (test_v_lo == 1'b1);
@(posedge clk);
$display("Testing filling fifo");
test_data_li = 4'hb;
test_v_li = 1'b1;
@(negedge clk);
assert (test_data_lo == fifo_data_lo);
assert (test_v_lo == 1'b1);
@(posedge clk);
test_v_li = 1'b0;
test_yumi_li = 1'b0;
$display("Checking that bypass reflects fullness");
@(negedge clk);
assert (test_ready_lo == 1'b0);
assert (fifo_ready_lo == 1'b0);
@(posedge clk);
$display("Testing emptying fifo");
test_data_li = 4'h6;
test_yumi_li = 1'b1;
@(negedge clk);
@(posedge clk);
@(posedge clk);
$display("Checking that fifo is empty");
@(negedge clk);
assert (fifo_v_lo == 1'b0);
assert (test_v_lo == 1'b0);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
$finish();
end
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: addr_arbiter_sasd.v
//
// Description:
// Hybrid priority + round-robin arbiter.
// Read & write requests combined (read preferred) at each slot
// Muxes AR and AW channel payload inputs based on arbitration results.
//-----------------------------------------------------------------------------
//
// Structure:
// addr_arbiter_sasd
// mux_enc
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_addr_arbiter_sasd #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_S = 1,
parameter integer C_NUM_S_LOG = 1,
parameter integer C_AMESG_WIDTH = 1,
parameter C_GRANT_ENC = 0,
parameter [C_NUM_S*32-1:0] C_ARB_PRIORITY = {C_NUM_S{32'h00000000}}
// Arbitration priority among each SI slot.
// Higher values indicate higher priority.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 'h0-'hF.
)
(
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Ports
input wire [C_NUM_S*C_AMESG_WIDTH-1:0] S_AWMESG,
input wire [C_NUM_S*C_AMESG_WIDTH-1:0] S_ARMESG,
input wire [C_NUM_S-1:0] S_AWVALID,
output wire [C_NUM_S-1:0] S_AWREADY,
input wire [C_NUM_S-1:0] S_ARVALID,
output wire [C_NUM_S-1:0] S_ARREADY,
// Master Ports
output wire [C_AMESG_WIDTH-1:0] M_AMESG,
output wire [C_NUM_S_LOG-1:0] M_GRANT_ENC,
output wire [C_NUM_S-1:0] M_GRANT_HOT,
output wire M_GRANT_RNW,
output wire M_GRANT_ANY,
output wire M_AWVALID,
input wire M_AWREADY,
output wire M_ARVALID,
input wire M_ARREADY
);
// Generates a mask for all input slots that are priority based
function [C_NUM_S-1:0] f_prio_mask
(
input integer null_arg
);
reg [C_NUM_S-1:0] mask;
integer i;
begin
mask = 0;
for (i=0; i < C_NUM_S; i=i+1) begin
mask[i] = (C_ARB_PRIORITY[i*32+:32] != 0);
end
f_prio_mask = mask;
end
endfunction
// Convert 16-bit one-hot to 4-bit binary
function [3:0] f_hot2enc
(
input [15:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 16'b1010101010101010);
f_hot2enc[1] = |(one_hot & 16'b1100110011001100);
f_hot2enc[2] = |(one_hot & 16'b1111000011110000);
f_hot2enc[3] = |(one_hot & 16'b1111111100000000);
end
endfunction
localparam [C_NUM_S-1:0] P_PRIO_MASK = f_prio_mask(0);
reg m_valid_i;
reg [C_NUM_S-1:0] s_ready_i;
reg [C_NUM_S-1:0] s_awvalid_reg;
reg [C_NUM_S-1:0] s_arvalid_reg;
wire [15:0] s_avalid;
wire m_aready;
wire [C_NUM_S-1:0] rnw;
reg grant_rnw;
reg [C_NUM_S_LOG-1:0] m_grant_enc_i;
reg [C_NUM_S-1:0] m_grant_hot_i;
reg [C_NUM_S-1:0] last_rr_hot;
reg any_grant;
reg any_prio;
reg [C_NUM_S-1:0] which_prio_hot;
reg [C_NUM_S_LOG-1:0] which_prio_enc;
reg [4:0] current_highest;
reg [15:0] next_prio_hot;
reg [C_NUM_S_LOG-1:0] next_prio_enc;
reg found_prio;
wire [C_NUM_S-1:0] valid_rr;
reg [15:0] next_rr_hot;
reg [C_NUM_S_LOG-1:0] next_rr_enc;
reg [C_NUM_S*C_NUM_S-1:0] carry_rr;
reg [C_NUM_S*C_NUM_S-1:0] mask_rr;
reg found_rr;
wire [C_NUM_S-1:0] next_hot;
wire [C_NUM_S_LOG-1:0] next_enc;
integer i;
wire [C_AMESG_WIDTH-1:0] amesg_mux;
reg [C_AMESG_WIDTH-1:0] m_amesg_i;
wire [C_NUM_S*C_AMESG_WIDTH-1:0] s_amesg;
genvar gen_si;
always @(posedge ACLK) begin
if (ARESET) begin
s_awvalid_reg <= 0;
s_arvalid_reg <= 0;
end else if (|s_ready_i) begin
s_awvalid_reg <= 0;
s_arvalid_reg <= 0;
end else begin
s_arvalid_reg <= S_ARVALID & ~s_awvalid_reg;
s_awvalid_reg <= S_AWVALID & ~s_arvalid_reg & (~S_ARVALID | s_awvalid_reg);
end
end
assign s_avalid = S_AWVALID | S_ARVALID;
assign M_AWVALID = m_valid_i & ~grant_rnw;
assign M_ARVALID = m_valid_i & grant_rnw;
assign S_AWREADY = s_ready_i & {C_NUM_S{~grant_rnw}};
assign S_ARREADY = s_ready_i & {C_NUM_S{grant_rnw}};
assign M_GRANT_ENC = C_GRANT_ENC ? m_grant_enc_i : 0;
assign M_GRANT_HOT = m_grant_hot_i;
assign M_GRANT_RNW = grant_rnw;
assign rnw = S_ARVALID & ~s_awvalid_reg;
assign M_AMESG = m_amesg_i;
assign m_aready = grant_rnw ? M_ARREADY : M_AWREADY;
generate
for (gen_si=0; gen_si<C_NUM_S; gen_si=gen_si+1) begin : gen_mesg_mux
assign s_amesg[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH] = rnw[gen_si] ? S_ARMESG[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH] : S_AWMESG[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH];
end // gen_mesg_mux
if (C_NUM_S>1) begin : gen_arbiter
/////////////////////////////////////////////////////////////////////////////
// Grant a new request when there is none still pending.
// If no qualified requests found, de-assert M_VALID.
/////////////////////////////////////////////////////////////////////////////
assign M_GRANT_ANY = any_grant;
assign next_hot = found_prio ? next_prio_hot : next_rr_hot;
assign next_enc = found_prio ? next_prio_enc : next_rr_enc;
always @(posedge ACLK) begin
if (ARESET) begin
m_valid_i <= 0;
s_ready_i <= 0;
m_grant_hot_i <= 0;
m_grant_enc_i <= 0;
any_grant <= 1'b0;
last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};
grant_rnw <= 1'b0;
end else begin
s_ready_i <= 0;
if (m_valid_i) begin
// Stall 1 cycle after each master-side completion.
if (m_aready) begin // Master-side completion
m_valid_i <= 1'b0;
m_grant_hot_i <= 0;
any_grant <= 1'b0;
end
end else if (any_grant) begin
m_valid_i <= 1'b1;
s_ready_i <= m_grant_hot_i; // Assert S_AW/READY for 1 cycle to complete SI address transfer
end else begin
if (found_prio | found_rr) begin
m_grant_hot_i <= next_hot;
m_grant_enc_i <= next_enc;
any_grant <= 1'b1;
grant_rnw <= |(rnw & next_hot);
if (~found_prio) begin
last_rr_hot <= next_rr_hot;
end
end
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Fixed Priority arbiter
// Selects next request to grant from among inputs with PRIO > 0, if any.
/////////////////////////////////////////////////////////////////////////////
always @ * begin : ALG_PRIO
integer ip;
any_prio = 1'b0;
which_prio_hot = 0;
which_prio_enc = 0;
current_highest = 0;
for (ip=0; ip < C_NUM_S; ip=ip+1) begin
if (P_PRIO_MASK[ip] & ({1'b0, C_ARB_PRIORITY[ip*32+:4]} > current_highest)) begin
if (s_avalid[ip]) begin
current_highest[0+:4] = C_ARB_PRIORITY[ip*32+:4];
any_prio = 1'b1;
which_prio_hot = 1'b1 << ip;
which_prio_enc = ip;
end
end
end
found_prio = any_prio;
next_prio_hot = which_prio_hot;
next_prio_enc = which_prio_enc;
end
/////////////////////////////////////////////////////////////////////////////
// Round-robin arbiter
// Selects next request to grant from among inputs with PRIO = 0, if any.
/////////////////////////////////////////////////////////////////////////////
assign valid_rr = ~P_PRIO_MASK & s_avalid;
always @ * begin : ALG_RR
integer ir, jr, nr;
next_rr_hot = 0;
for (ir=0;ir<C_NUM_S;ir=ir+1) begin
nr = (ir>0) ? (ir-1) : (C_NUM_S-1);
carry_rr[ir*C_NUM_S] = last_rr_hot[nr];
mask_rr[ir*C_NUM_S] = ~valid_rr[nr];
for (jr=1;jr<C_NUM_S;jr=jr+1) begin
nr = (ir-jr > 0) ? (ir-jr-1) : (C_NUM_S+ir-jr-1);
carry_rr[ir*C_NUM_S+jr] = carry_rr[ir*C_NUM_S+jr-1] | (last_rr_hot[nr] & mask_rr[ir*C_NUM_S+jr-1]);
if (jr < C_NUM_S-1) begin
mask_rr[ir*C_NUM_S+jr] = mask_rr[ir*C_NUM_S+jr-1] & ~valid_rr[nr];
end
end
next_rr_hot[ir] = valid_rr[ir] & carry_rr[(ir+1)*C_NUM_S-1];
end
next_rr_enc = f_hot2enc(next_rr_hot);
found_rr = |(next_rr_hot);
end
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_S),
.C_SEL_WIDTH (C_NUM_S_LOG),
.C_DATA_WIDTH (C_AMESG_WIDTH)
) si_amesg_mux_inst
(
.S (next_enc),
.A (s_amesg),
.O (amesg_mux),
.OE (1'b1)
);
always @(posedge ACLK) begin
if (ARESET) begin
m_amesg_i <= 0;
end else if (~any_grant) begin
m_amesg_i <= amesg_mux;
end
end
end else begin : gen_no_arbiter
assign M_GRANT_ANY = m_grant_hot_i;
always @ (posedge ACLK) begin
if (ARESET) begin
m_valid_i <= 1'b0;
s_ready_i <= 1'b0;
m_grant_enc_i <= 0;
m_grant_hot_i <= 1'b0;
grant_rnw <= 1'b0;
end else begin
s_ready_i <= 1'b0;
if (m_valid_i) begin
if (m_aready) begin
m_valid_i <= 1'b0;
m_grant_hot_i <= 1'b0;
end
end else if (m_grant_hot_i) begin
m_valid_i <= 1'b1;
s_ready_i[0] <= 1'b1; // Assert S_AW/READY for 1 cycle to complete SI address transfer
end else if (s_avalid[0]) begin
m_grant_hot_i <= 1'b1;
grant_rnw <= rnw[0];
end
end
end
always @ (posedge ACLK) begin
if (ARESET) begin
m_amesg_i <= 0;
end else if (~m_grant_hot_i) begin
m_amesg_i <= s_amesg;
end
end
end // gen_arbiter
endgenerate
endmodule
`default_nettype wire
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_adc (
clk,
// control ports
control,
status,
// FIFO interface
src_adc_dwr,
src_adc_dsync,
src_adc_ddata,
src_adc_dovf,
dst_adc_dwr,
dst_adc_dsync,
dst_adc_ddata,
dst_adc_dovf
);
localparam RP_ID = 8'hA0;
parameter CHANNEL_ID = 0;
input clk;
input [31:0] control;
output [31:0] status;
input src_adc_dwr;
input src_adc_dsync;
input [31:0] src_adc_ddata;
output src_adc_dovf;
output dst_adc_dwr;
output dst_adc_dsync;
output [31:0] dst_adc_ddata;
input dst_adc_dovf;
reg dst_adc_dwr;
reg dst_adc_dsync;
reg [31:0] dst_adc_ddata;
reg src_adc_dovf;
assign status = {24'h0, RP_ID};
always @(posedge clk) begin
dst_adc_dwr <= src_adc_dwr;
dst_adc_dsync <= src_adc_dsync;
dst_adc_ddata <= src_adc_ddata;
src_adc_dovf <= dst_adc_dovf;
end
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Import ZAxioms ZMulOrder ZSgnAbs NZDiv.
(** * Euclidean Division for integers (Floor convention)
We use here the convention known as Floor, or Round-Toward-Bottom,
where [a/b] is the closest integer below the exact fraction.
It can be summarized by:
[a = bq+r /\ 0 <= |r| < |b| /\ Sign(r) = Sign(b)]
This is the convention followed historically by [Z.div] in Coq, and
corresponds to convention "F" in the following paper:
R. Boute, "The Euclidean definition of the functions div and mod",
ACM Transactions on Programming Languages and Systems,
Vol. 14, No.2, pp. 127-144, April 1992.
See files [ZDivTrunc] and [ZDivEucl] for others conventions.
*)
Module Type ZDivProp
(Import A : ZAxiomsSig')
(Import B : ZMulOrderProp A)
(Import C : ZSgnAbsProp A B).
(** We benefit from what already exists for NZ *)
Module Import Private_NZDiv := Nop <+ NZDivProp A A B.
(** Another formulation of the main equation *)
Lemma mod_eq :
forall a b, b~=0 -> a mod b == a - b*(a/b).
Proof.
intros.
rewrite <- add_move_l.
symmetry. now apply div_mod.
Qed.
(** We have a general bound for absolute values *)
Lemma mod_bound_abs :
forall a b, b~=0 -> abs (a mod b) < abs b.
Proof.
intros.
destruct (abs_spec b) as [(LE,EQ)|(LE,EQ)]; rewrite EQ.
destruct (mod_pos_bound a b). order. now rewrite abs_eq.
destruct (mod_neg_bound a b). order. rewrite abs_neq; trivial.
now rewrite <- opp_lt_mono.
Qed.
(** Uniqueness theorems *)
Theorem div_mod_unique : forall b q1 q2 r1 r2 : t,
(0<=r1<b \/ b<r1<=0) -> (0<=r2<b \/ b<r2<=0) ->
b*q1+r1 == b*q2+r2 -> q1 == q2 /\ r1 == r2.
Proof.
intros b q1 q2 r1 r2 Hr1 Hr2 EQ.
destruct Hr1; destruct Hr2; try (intuition; order).
apply div_mod_unique with b; trivial.
rewrite <- (opp_inj_wd r1 r2).
apply div_mod_unique with (-b); trivial.
rewrite <- opp_lt_mono, opp_nonneg_nonpos; tauto.
rewrite <- opp_lt_mono, opp_nonneg_nonpos; tauto.
now rewrite 2 mul_opp_l, <- 2 opp_add_distr, opp_inj_wd.
Qed.
Theorem div_unique:
forall a b q r, (0<=r<b \/ b<r<=0) -> a == b*q + r -> q == a/b.
Proof.
intros a b q r Hr EQ.
assert (Hb : b~=0) by (destruct Hr; intuition; order).
destruct (div_mod_unique b q (a/b) r (a mod b)); trivial.
destruct Hr; [left; apply mod_pos_bound|right; apply mod_neg_bound];
intuition order.
now rewrite <- div_mod.
Qed.
Theorem div_unique_pos:
forall a b q r, 0<=r<b -> a == b*q + r -> q == a/b.
Proof. intros; apply div_unique with r; auto. Qed.
Theorem div_unique_neg:
forall a b q r, b<r<=0 -> a == b*q + r -> q == a/b.
Proof. intros; apply div_unique with r; auto. Qed.
Theorem mod_unique:
forall a b q r, (0<=r<b \/ b<r<=0) -> a == b*q + r -> r == a mod b.
Proof.
intros a b q r Hr EQ.
assert (Hb : b~=0) by (destruct Hr; intuition; order).
destruct (div_mod_unique b q (a/b) r (a mod b)); trivial.
destruct Hr; [left; apply mod_pos_bound|right; apply mod_neg_bound];
intuition order.
now rewrite <- div_mod.
Qed.
Theorem mod_unique_pos:
forall a b q r, 0<=r<b -> a == b*q + r -> r == a mod b.
Proof. intros; apply mod_unique with q; auto. Qed.
Theorem mod_unique_neg:
forall a b q r, b<r<=0 -> a == b*q + r -> r == a mod b.
Proof. intros; apply mod_unique with q; auto. Qed.
(** Sign rules *)
Ltac pos_or_neg a :=
let LT := fresh "LT" in
let LE := fresh "LE" in
destruct (le_gt_cases 0 a) as [LE|LT]; [|rewrite <- opp_pos_neg in LT].
Fact mod_bound_or : forall a b, b~=0 -> 0<=a mod b<b \/ b<a mod b<=0.
Proof.
intros.
destruct (lt_ge_cases 0 b); [left|right].
apply mod_pos_bound; trivial. apply mod_neg_bound; order.
Qed.
Fact opp_mod_bound_or : forall a b, b~=0 ->
0 <= -(a mod b) < -b \/ -b < -(a mod b) <= 0.
Proof.
intros.
destruct (lt_ge_cases 0 b); [right|left].
rewrite <- opp_lt_mono, opp_nonpos_nonneg.
destruct (mod_pos_bound a b); intuition; order.
rewrite <- opp_lt_mono, opp_nonneg_nonpos.
destruct (mod_neg_bound a b); intuition; order.
Qed.
Lemma div_opp_opp : forall a b, b~=0 -> -a/-b == a/b.
Proof.
intros. symmetry. apply div_unique with (- (a mod b)).
now apply opp_mod_bound_or.
rewrite mul_opp_l, <- opp_add_distr, <- div_mod; order.
Qed.
Lemma mod_opp_opp : forall a b, b~=0 -> (-a) mod (-b) == - (a mod b).
Proof.
intros. symmetry. apply mod_unique with (a/b).
now apply opp_mod_bound_or.
rewrite mul_opp_l, <- opp_add_distr, <- div_mod; order.
Qed.
(** With the current conventions, the other sign rules are rather complex. *)
Lemma div_opp_l_z :
forall a b, b~=0 -> a mod b == 0 -> (-a)/b == -(a/b).
Proof.
intros a b Hb H. symmetry. apply div_unique with 0.
destruct (lt_ge_cases 0 b); [left|right]; intuition; order.
rewrite <- opp_0, <- H.
rewrite mul_opp_r, <- opp_add_distr, <- div_mod; order.
Qed.
Lemma div_opp_l_nz :
forall a b, b~=0 -> a mod b ~= 0 -> (-a)/b == -(a/b)-1.
Proof.
intros a b Hb H. symmetry. apply div_unique with (b - a mod b).
destruct (lt_ge_cases 0 b); [left|right].
rewrite le_0_sub. rewrite <- (sub_0_r b) at 5. rewrite <- sub_lt_mono_l.
destruct (mod_pos_bound a b); intuition; order.
rewrite le_sub_0. rewrite <- (sub_0_r b) at 1. rewrite <- sub_lt_mono_l.
destruct (mod_neg_bound a b); intuition; order.
rewrite <- (add_opp_r b), mul_sub_distr_l, mul_1_r, sub_add_simpl_r_l.
rewrite mul_opp_r, <-opp_add_distr, <-div_mod; order.
Qed.
Lemma mod_opp_l_z :
forall a b, b~=0 -> a mod b == 0 -> (-a) mod b == 0.
Proof.
intros a b Hb H. symmetry. apply mod_unique with (-(a/b)).
destruct (lt_ge_cases 0 b); [left|right]; intuition; order.
rewrite <- opp_0, <- H.
rewrite mul_opp_r, <- opp_add_distr, <- div_mod; order.
Qed.
Lemma mod_opp_l_nz :
forall a b, b~=0 -> a mod b ~= 0 -> (-a) mod b == b - a mod b.
Proof.
intros a b Hb H. symmetry. apply mod_unique with (-(a/b)-1).
destruct (lt_ge_cases 0 b); [left|right].
rewrite le_0_sub. rewrite <- (sub_0_r b) at 5. rewrite <- sub_lt_mono_l.
destruct (mod_pos_bound a b); intuition; order.
rewrite le_sub_0. rewrite <- (sub_0_r b) at 1. rewrite <- sub_lt_mono_l.
destruct (mod_neg_bound a b); intuition; order.
rewrite <- (add_opp_r b), mul_sub_distr_l, mul_1_r, sub_add_simpl_r_l.
rewrite mul_opp_r, <-opp_add_distr, <-div_mod; order.
Qed.
Lemma div_opp_r_z :
forall a b, b~=0 -> a mod b == 0 -> a/(-b) == -(a/b).
Proof.
intros. rewrite <- (opp_involutive a) at 1.
rewrite div_opp_opp; auto using div_opp_l_z.
Qed.
Lemma div_opp_r_nz :
forall a b, b~=0 -> a mod b ~= 0 -> a/(-b) == -(a/b)-1.
Proof.
intros. rewrite <- (opp_involutive a) at 1.
rewrite div_opp_opp; auto using div_opp_l_nz.
Qed.
Lemma mod_opp_r_z :
forall a b, b~=0 -> a mod b == 0 -> a mod (-b) == 0.
Proof.
intros. rewrite <- (opp_involutive a) at 1.
now rewrite mod_opp_opp, mod_opp_l_z, opp_0.
Qed.
Lemma mod_opp_r_nz :
forall a b, b~=0 -> a mod b ~= 0 -> a mod (-b) == (a mod b) - b.
Proof.
intros. rewrite <- (opp_involutive a) at 1.
rewrite mod_opp_opp, mod_opp_l_nz by trivial.
now rewrite opp_sub_distr, add_comm, add_opp_r.
Qed.
(** The sign of [a mod b] is the one of [b] (when it isn't null) *)
Lemma mod_sign_nz : forall a b, b~=0 -> a mod b ~= 0 ->
sgn (a mod b) == sgn b.
Proof.
intros a b Hb H. destruct (lt_ge_cases 0 b) as [Hb'|Hb'].
destruct (mod_pos_bound a b Hb'). rewrite 2 sgn_pos; order.
destruct (mod_neg_bound a b). order. rewrite 2 sgn_neg; order.
Qed.
Lemma mod_sign : forall a b, b~=0 -> sgn (a mod b) ~= -sgn b.
Proof.
intros a b Hb H.
destruct (eq_decidable (a mod b) 0) as [EQ|NEQ].
apply Hb, sgn_null_iff, opp_inj. now rewrite <- H, opp_0, EQ, sgn_0.
apply Hb, sgn_null_iff. apply eq_mul_0_l with 2; try order'. nzsimpl'.
apply add_move_0_l. rewrite <- H. symmetry. now apply mod_sign_nz.
Qed.
Lemma mod_sign_mul : forall a b, b~=0 -> 0 <= (a mod b) * b.
Proof.
intros. destruct (lt_ge_cases 0 b).
apply mul_nonneg_nonneg; destruct (mod_pos_bound a b); order.
apply mul_nonpos_nonpos; destruct (mod_neg_bound a b); order.
Qed.
(** A division by itself returns 1 *)
Lemma div_same : forall a, a~=0 -> a/a == 1.
Proof.
intros. pos_or_neg a. apply div_same; order.
rewrite <- div_opp_opp by trivial. now apply div_same.
Qed.
Lemma mod_same : forall a, a~=0 -> a mod a == 0.
Proof.
intros. rewrite mod_eq, div_same by trivial. nzsimpl. apply sub_diag.
Qed.
(** A division of a small number by a bigger one yields zero. *)
Theorem div_small: forall a b, 0<=a<b -> a/b == 0.
Proof. exact div_small. Qed.
(** Same situation, in term of modulo: *)
Theorem mod_small: forall a b, 0<=a<b -> a mod b == a.
Proof. exact mod_small. Qed.
(** * Basic values of divisions and modulo. *)
Lemma div_0_l: forall a, a~=0 -> 0/a == 0.
Proof.
intros. pos_or_neg a. apply div_0_l; order.
rewrite <- div_opp_opp, opp_0 by trivial. now apply div_0_l.
Qed.
Lemma mod_0_l: forall a, a~=0 -> 0 mod a == 0.
Proof.
intros; rewrite mod_eq, div_0_l; now nzsimpl.
Qed.
Lemma div_1_r: forall a, a/1 == a.
Proof.
intros. symmetry. apply div_unique with 0. left. split; order || apply lt_0_1.
now nzsimpl.
Qed.
Lemma mod_1_r: forall a, a mod 1 == 0.
Proof.
intros. rewrite mod_eq, div_1_r; nzsimpl; auto using sub_diag.
intro EQ; symmetry in EQ; revert EQ; apply lt_neq; apply lt_0_1.
Qed.
Lemma div_1_l: forall a, 1<a -> 1/a == 0.
Proof. exact div_1_l. Qed.
Lemma mod_1_l: forall a, 1<a -> 1 mod a == 1.
Proof. exact mod_1_l. Qed.
Lemma div_mul : forall a b, b~=0 -> (a*b)/b == a.
Proof.
intros. symmetry. apply div_unique with 0.
destruct (lt_ge_cases 0 b); [left|right]; split; order.
nzsimpl; apply mul_comm.
Qed.
Lemma mod_mul : forall a b, b~=0 -> (a*b) mod b == 0.
Proof.
intros. rewrite mod_eq, div_mul by trivial. rewrite mul_comm; apply sub_diag.
Qed.
Theorem div_unique_exact a b q: b~=0 -> a == b*q -> q == a/b.
Proof.
intros Hb H. rewrite H, mul_comm. symmetry. now apply div_mul.
Qed.
(** * Order results about mod and div *)
(** A modulo cannot grow beyond its starting point. *)
Theorem mod_le: forall a b, 0<=a -> 0<b -> a mod b <= a.
Proof. exact mod_le. Qed.
Theorem div_pos : forall a b, 0<=a -> 0<b -> 0<= a/b.
Proof. exact div_pos. Qed.
Lemma div_str_pos : forall a b, 0<b<=a -> 0 < a/b.
Proof. exact div_str_pos. Qed.
Lemma div_small_iff : forall a b, b~=0 -> (a/b==0 <-> 0<=a<b \/ b<a<=0).
Proof.
intros a b Hb.
split.
intros EQ.
rewrite (div_mod a b Hb), EQ; nzsimpl.
now apply mod_bound_or.
destruct 1. now apply div_small.
rewrite <- div_opp_opp by trivial. apply div_small; trivial.
rewrite <- opp_lt_mono, opp_nonneg_nonpos; tauto.
Qed.
Lemma mod_small_iff : forall a b, b~=0 -> (a mod b == a <-> 0<=a<b \/ b<a<=0).
Proof.
intros.
rewrite <- div_small_iff, mod_eq by trivial.
rewrite sub_move_r, <- (add_0_r a) at 1. rewrite add_cancel_l.
rewrite eq_sym_iff, eq_mul_0. tauto.
Qed.
(** As soon as the divisor is strictly greater than 1,
the division is strictly decreasing. *)
Lemma div_lt : forall a b, 0<a -> 1<b -> a/b < a.
Proof. exact div_lt. Qed.
(** [le] is compatible with a positive division. *)
Lemma div_le_mono : forall a b c, 0<c -> a<=b -> a/c <= b/c.
Proof.
intros a b c Hc Hab.
rewrite lt_eq_cases in Hab. destruct Hab as [LT|EQ];
[|rewrite EQ; order].
rewrite <- lt_succ_r.
rewrite (mul_lt_mono_pos_l c) by order.
nzsimpl.
rewrite (add_lt_mono_r _ _ (a mod c)).
rewrite <- div_mod by order.
apply lt_le_trans with b; trivial.
rewrite (div_mod b c) at 1 by order.
rewrite <- add_assoc, <- add_le_mono_l.
apply le_trans with (c+0).
nzsimpl; destruct (mod_pos_bound b c); order.
rewrite <- add_le_mono_l. destruct (mod_pos_bound a c); order.
Qed.
(** In this convention, [div] performs Rounding-Toward-Bottom.
Since we cannot speak of rational values here, we express this
fact by multiplying back by [b], and this leads to separates
statements according to the sign of [b].
First, [a/b] is below the exact fraction ...
*)
Lemma mul_div_le : forall a b, 0<b -> b*(a/b) <= a.
Proof.
intros.
rewrite (div_mod a b) at 2; try order.
rewrite <- (add_0_r (b*(a/b))) at 1.
rewrite <- add_le_mono_l.
now destruct (mod_pos_bound a b).
Qed.
Lemma mul_div_ge : forall a b, b<0 -> a <= b*(a/b).
Proof.
intros. rewrite <- div_opp_opp, opp_le_mono, <-mul_opp_l by order.
apply mul_div_le. now rewrite opp_pos_neg.
Qed.
(** ... and moreover it is the larger such integer, since [S(a/b)]
is strictly above the exact fraction.
*)
Lemma mul_succ_div_gt: forall a b, 0<b -> a < b*(S (a/b)).
Proof.
intros.
nzsimpl.
rewrite (div_mod a b) at 1; try order.
rewrite <- add_lt_mono_l.
destruct (mod_pos_bound a b); order.
Qed.
Lemma mul_succ_div_lt: forall a b, b<0 -> b*(S (a/b)) < a.
Proof.
intros. rewrite <- div_opp_opp, opp_lt_mono, <-mul_opp_l by order.
apply mul_succ_div_gt. now rewrite opp_pos_neg.
Qed.
(** NB: The four previous properties could be used as
specifications for [div]. *)
(** Inequality [mul_div_le] is exact iff the modulo is zero. *)
Lemma div_exact : forall a b, b~=0 -> (a == b*(a/b) <-> a mod b == 0).
Proof.
intros.
rewrite (div_mod a b) at 1; try order.
rewrite <- (add_0_r (b*(a/b))) at 2.
apply add_cancel_l.
Qed.
(** Some additional inequalities about div. *)
Theorem div_lt_upper_bound:
forall a b q, 0<b -> a < b*q -> a/b < q.
Proof.
intros.
rewrite (mul_lt_mono_pos_l b) by trivial.
apply le_lt_trans with a; trivial.
now apply mul_div_le.
Qed.
Theorem div_le_upper_bound:
forall a b q, 0<b -> a <= b*q -> a/b <= q.
Proof.
intros.
rewrite <- (div_mul q b) by order.
apply div_le_mono; trivial. now rewrite mul_comm.
Qed.
Theorem div_le_lower_bound:
forall a b q, 0<b -> b*q <= a -> q <= a/b.
Proof.
intros.
rewrite <- (div_mul q b) by order.
apply div_le_mono; trivial. now rewrite mul_comm.
Qed.
(** A division respects opposite monotonicity for the divisor *)
Lemma div_le_compat_l: forall p q r, 0<=p -> 0<q<=r -> p/r <= p/q.
Proof. exact div_le_compat_l. Qed.
(** * Relations between usual operations and mod and div *)
Lemma mod_add : forall a b c, c~=0 ->
(a + b * c) mod c == a mod c.
Proof.
intros.
symmetry.
apply mod_unique with (a/c+b); trivial.
now apply mod_bound_or.
rewrite mul_add_distr_l, add_shuffle0, <- div_mod by order.
now rewrite mul_comm.
Qed.
Lemma div_add : forall a b c, c~=0 ->
(a + b * c) / c == a / c + b.
Proof.
intros.
apply (mul_cancel_l _ _ c); try order.
apply (add_cancel_r _ _ ((a+b*c) mod c)).
rewrite <- div_mod, mod_add by order.
rewrite mul_add_distr_l, add_shuffle0, <- div_mod by order.
now rewrite mul_comm.
Qed.
Lemma div_add_l: forall a b c, b~=0 ->
(a * b + c) / b == a + c / b.
Proof.
intros a b c. rewrite (add_comm _ c), (add_comm a).
now apply div_add.
Qed.
(** Cancellations. *)
Lemma div_mul_cancel_r : forall a b c, b~=0 -> c~=0 ->
(a*c)/(b*c) == a/b.
Proof.
intros.
symmetry.
apply div_unique with ((a mod b)*c).
(* ineqs *)
destruct (lt_ge_cases 0 c).
rewrite <-(mul_0_l c), <-2mul_lt_mono_pos_r, <-2mul_le_mono_pos_r by trivial.
now apply mod_bound_or.
rewrite <-(mul_0_l c), <-2mul_lt_mono_neg_r, <-2mul_le_mono_neg_r by order.
destruct (mod_bound_or a b); tauto.
(* equation *)
rewrite (div_mod a b) at 1 by order.
rewrite mul_add_distr_r.
rewrite add_cancel_r.
rewrite <- 2 mul_assoc. now rewrite (mul_comm c).
Qed.
Lemma div_mul_cancel_l : forall a b c, b~=0 -> c~=0 ->
(c*a)/(c*b) == a/b.
Proof.
intros. rewrite !(mul_comm c); now apply div_mul_cancel_r.
Qed.
Lemma mul_mod_distr_l: forall a b c, b~=0 -> c~=0 ->
(c*a) mod (c*b) == c * (a mod b).
Proof.
intros.
rewrite <- (add_cancel_l _ _ ((c*b)* ((c*a)/(c*b)))).
rewrite <- div_mod.
rewrite div_mul_cancel_l by trivial.
rewrite <- mul_assoc, <- mul_add_distr_l, mul_cancel_l by order.
apply div_mod; order.
rewrite <- neq_mul_0; auto.
Qed.
Lemma mul_mod_distr_r: forall a b c, b~=0 -> c~=0 ->
(a*c) mod (b*c) == (a mod b) * c.
Proof.
intros. rewrite !(mul_comm _ c); now rewrite mul_mod_distr_l.
Qed.
(** Operations modulo. *)
Theorem mod_mod: forall a n, n~=0 ->
(a mod n) mod n == a mod n.
Proof.
intros. rewrite mod_small_iff by trivial.
now apply mod_bound_or.
Qed.
Lemma mul_mod_idemp_l : forall a b n, n~=0 ->
((a mod n)*b) mod n == (a*b) mod n.
Proof.
intros a b n Hn. symmetry.
rewrite (div_mod a n) at 1 by order.
rewrite add_comm, (mul_comm n), (mul_comm _ b).
rewrite mul_add_distr_l, mul_assoc.
intros. rewrite mod_add by trivial.
now rewrite mul_comm.
Qed.
Lemma mul_mod_idemp_r : forall a b n, n~=0 ->
(a*(b mod n)) mod n == (a*b) mod n.
Proof.
intros. rewrite !(mul_comm a). now apply mul_mod_idemp_l.
Qed.
Theorem mul_mod: forall a b n, n~=0 ->
(a * b) mod n == ((a mod n) * (b mod n)) mod n.
Proof.
intros. now rewrite mul_mod_idemp_l, mul_mod_idemp_r.
Qed.
Lemma add_mod_idemp_l : forall a b n, n~=0 ->
((a mod n)+b) mod n == (a+b) mod n.
Proof.
intros a b n Hn. symmetry.
rewrite (div_mod a n) at 1 by order.
rewrite <- add_assoc, add_comm, mul_comm.
intros. now rewrite mod_add.
Qed.
Lemma add_mod_idemp_r : forall a b n, n~=0 ->
(a+(b mod n)) mod n == (a+b) mod n.
Proof.
intros. rewrite !(add_comm a). now apply add_mod_idemp_l.
Qed.
Theorem add_mod: forall a b n, n~=0 ->
(a+b) mod n == (a mod n + b mod n) mod n.
Proof.
intros. now rewrite add_mod_idemp_l, add_mod_idemp_r.
Qed.
(** With the current convention, the following result isn't always
true with a negative last divisor. For instance
[ 3/(-2)/(-2) = 1 <> 0 = 3 / (-2*-2) ], or
[ 5/2/(-2) = -1 <> -2 = 5 / (2*-2) ]. *)
Lemma div_div : forall a b c, b~=0 -> 0<c ->
(a/b)/c == a/(b*c).
Proof.
intros a b c Hb Hc.
apply div_unique with (b*((a/b) mod c) + a mod b).
(* begin 0<= ... <b*c \/ ... *)
apply neg_pos_cases in Hb. destruct Hb as [Hb|Hb].
right.
destruct (mod_pos_bound (a/b) c), (mod_neg_bound a b); trivial.
split.
apply le_lt_trans with (b*((a/b) mod c) + b).
now rewrite <- mul_succ_r, <- mul_le_mono_neg_l, le_succ_l.
now rewrite <- add_lt_mono_l.
apply add_nonpos_nonpos; trivial.
apply mul_nonpos_nonneg; order.
left.
destruct (mod_pos_bound (a/b) c), (mod_pos_bound a b); trivial.
split.
apply add_nonneg_nonneg; trivial.
apply mul_nonneg_nonneg; order.
apply lt_le_trans with (b*((a/b) mod c) + b).
now rewrite <- add_lt_mono_l.
now rewrite <- mul_succ_r, <- mul_le_mono_pos_l, le_succ_l.
(* end 0<= ... < b*c \/ ... *)
rewrite (div_mod a b) at 1 by order.
rewrite add_assoc, add_cancel_r.
rewrite <- mul_assoc, <- mul_add_distr_l, mul_cancel_l by order.
apply div_mod; order.
Qed.
(** Similarly, the following result doesn't always hold when [c<0].
For instance [3 mod (-2*-2)) = 3] while
[3 mod (-2) + (-2)*((3/-2) mod -2) = -1].
*)
Lemma rem_mul_r : forall a b c, b~=0 -> 0<c ->
a mod (b*c) == a mod b + b*((a/b) mod c).
Proof.
intros a b c Hb Hc.
apply add_cancel_l with (b*c*(a/(b*c))).
rewrite <- div_mod by (apply neq_mul_0; split; order).
rewrite <- div_div by trivial.
rewrite add_assoc, add_shuffle0, <- mul_assoc, <- mul_add_distr_l.
rewrite <- div_mod by order.
apply div_mod; order.
Qed.
Lemma mod_div: forall a b, b~=0 ->
a mod b / b == 0.
Proof.
intros a b Hb.
rewrite div_small_iff by assumption.
auto using mod_bound_or.
Qed.
(** A last inequality: *)
Theorem div_mul_le:
forall a b c, 0<=a -> 0<b -> 0<=c -> c*(a/b) <= (c*a)/b.
Proof. exact div_mul_le. Qed.
End ZDivProp.
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_pipe_clock.v
// Version : 3.2
//------------------------------------------------------------------------------
// Filename : pipe_clock.v
// Description : PIPE Clock Module for 7 Series Transceiver
// Version : 15.3
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Clock Module -------------------------------------------------
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PCIeGen2x8If128_pipe_clock #
(
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_CLK_SHARING_EN= "FALSE", // Enable Clock Sharing
parameter PCIE_LANE = 1, // PCIe number of lanes
parameter PCIE_LINK_SPEED = 3, // PCIe link speed
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
parameter PCIE_USERCLK1_FREQ = 2, // PCIe user clock 1 frequency
parameter PCIE_USERCLK2_FREQ = 2, // PCIe user clock 2 frequency
parameter PCIE_OOBCLK_MODE = 1, // PCIe oob clock mode
parameter PCIE_DEBUG_MODE = 0 // PCIe Debug mode
)
(
//---------- Input -------------------------------------
input CLK_CLK,
input CLK_TXOUTCLK,
input [PCIE_LANE-1:0] CLK_RXOUTCLK_IN,
input CLK_RST_N,
input [PCIE_LANE-1:0] CLK_PCLK_SEL,
input [PCIE_LANE-1:0] CLK_PCLK_SEL_SLAVE,
input CLK_GEN3,
//---------- Output ------------------------------------
output CLK_PCLK,
output CLK_PCLK_SLAVE,
output CLK_RXUSRCLK,
output [PCIE_LANE-1:0] CLK_RXOUTCLK_OUT,
output CLK_DCLK,
output CLK_OOBCLK,
output CLK_USERCLK1,
output CLK_USERCLK2,
output CLK_MMCM_LOCK
);
//---------- Select Clock Divider ----------------------
localparam DIVCLK_DIVIDE = (PCIE_REFCLK_FREQ == 2) ? 1 :
(PCIE_REFCLK_FREQ == 1) ? 1 : 1;
localparam CLKFBOUT_MULT_F = (PCIE_REFCLK_FREQ == 2) ? 4 :
(PCIE_REFCLK_FREQ == 1) ? 8 : 10;
localparam CLKIN1_PERIOD = (PCIE_REFCLK_FREQ == 2) ? 4 :
(PCIE_REFCLK_FREQ == 1) ? 8 : 10;
localparam CLKOUT0_DIVIDE_F = 8;
localparam CLKOUT1_DIVIDE = 4;
localparam CLKOUT2_DIVIDE = (PCIE_USERCLK1_FREQ == 5) ? 2 :
(PCIE_USERCLK1_FREQ == 4) ? 4 :
(PCIE_USERCLK1_FREQ == 3) ? 8 :
(PCIE_USERCLK1_FREQ == 1) ? 32 : 16;
localparam CLKOUT3_DIVIDE = (PCIE_USERCLK2_FREQ == 5) ? 2 :
(PCIE_USERCLK2_FREQ == 4) ? 4 :
(PCIE_USERCLK2_FREQ == 3) ? 8 :
(PCIE_USERCLK2_FREQ == 1) ? 32 : 16;
localparam CLKOUT4_DIVIDE = 20;
localparam PCIE_GEN1_MODE = 1'b0; // PCIe link speed is GEN1 only
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_reg1 = {PCIE_LANE{1'd0}};
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_slave_reg1 = {PCIE_LANE{1'd0}};
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1 = 1'd0;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_reg2 = {PCIE_LANE{1'd0}};
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_slave_reg2 = {PCIE_LANE{1'd0}};
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2 = 1'd0;
//---------- Internal Signals --------------------------
wire refclk;
wire mmcm_fb;
wire clk_125mhz;
wire clk_125mhz_buf;
wire clk_250mhz;
wire userclk1;
wire userclk2;
wire oobclk;
reg pclk_sel = 1'd0;
reg pclk_sel_slave = 1'd0;
//---------- Output Registers --------------------------
wire pclk_1;
wire pclk;
wire userclk1_1;
wire userclk2_1;
wire mmcm_lock;
//---------- Generate Per-Lane Signals -----------------
genvar i; // Index for per-lane signals
//---------- Input FF ----------------------------------------------------------
always @ (posedge pclk)
begin
if (!CLK_RST_N)
begin
//---------- 1st Stage FF --------------------------
pclk_sel_reg1 <= {PCIE_LANE{1'd0}};
pclk_sel_slave_reg1 <= {PCIE_LANE{1'd0}};
gen3_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
pclk_sel_reg2 <= {PCIE_LANE{1'd0}};
pclk_sel_slave_reg2 <= {PCIE_LANE{1'd0}};
gen3_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
pclk_sel_reg1 <= CLK_PCLK_SEL;
pclk_sel_slave_reg1 <= CLK_PCLK_SEL_SLAVE;
gen3_reg1 <= CLK_GEN3;
//---------- 2nd Stage FF --------------------------
pclk_sel_reg2 <= pclk_sel_reg1;
pclk_sel_slave_reg2 <= pclk_sel_slave_reg1;
gen3_reg2 <= gen3_reg1;
end
end
//---------- Select Reference clock or TXOUTCLK --------------------------------
generate if ((PCIE_TXBUF_EN == "TRUE") && (PCIE_LINK_SPEED != 3))
begin : refclk_i
//---------- Select Reference Clock ----------------------------------------
BUFG refclk_i
(
//---------- Input -------------------------------------
.I (CLK_CLK),
//---------- Output ------------------------------------
.O (refclk)
);
end
else
begin : txoutclk_i
//---------- Select TXOUTCLK -----------------------------------------------
BUFG txoutclk_i
(
//---------- Input -------------------------------------
.I (CLK_TXOUTCLK),
//---------- Output ------------------------------------
.O (refclk)
);
end
endgenerate
//---------- MMCM --------------------------------------------------------------
MMCME2_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_F),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (CLKOUT0_DIVIDE_F),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKOUT4_DIVIDE (CLKOUT4_DIVIDE),
.CLKOUT4_PHASE (0.000),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT4_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (CLKIN1_PERIOD),
.REF_JITTER1 (0.010)
)
mmcm_i
(
//---------- Input ------------------------------------
.CLKIN1 (refclk),
.CLKIN2 (1'd0), // not used, comment out CLKIN2 if it cause implementation issues
//.CLKIN2 (refclk), // not used, comment out CLKIN2 if it cause implementation issues
.CLKINSEL (1'd1),
.CLKFBIN (mmcm_fb),
.RST (!CLK_RST_N),
.PWRDWN (1'd0),
//---------- Output ------------------------------------
.CLKFBOUT (mmcm_fb),
.CLKFBOUTB (),
.CLKOUT0 (clk_125mhz),
.CLKOUT0B (),
.CLKOUT1 (clk_250mhz),
.CLKOUT1B (),
.CLKOUT2 (userclk1),
.CLKOUT2B (),
.CLKOUT3 (userclk2),
.CLKOUT3B (),
.CLKOUT4 (oobclk),
.CLKOUT5 (),
.CLKOUT6 (),
.LOCKED (mmcm_lock),
//---------- Dynamic Reconfiguration -------------------
.DCLK ( 1'd0),
.DADDR ( 7'd0),
.DEN ( 1'd0),
.DWE ( 1'd0),
.DI (16'd0),
.DO (),
.DRDY (),
//---------- Dynamic Phase Shift -----------------------
.PSCLK (1'd0),
.PSEN (1'd0),
.PSINCDEC (1'd0),
.PSDONE (),
//---------- Status ------------------------------------
.CLKINSTOPPED (),
.CLKFBSTOPPED ()
);
//---------- Select PCLK MUX ---------------------------------------------------
generate if (PCIE_LINK_SPEED != 1)
begin : pclk_i1_bufgctrl
//---------- PCLK Mux ----------------------------------
BUFGCTRL pclk_i1
(
//---------- Input ---------------------------------
.CE0 (1'd1),
.CE1 (1'd1),
.I0 (clk_125mhz),
.I1 (clk_250mhz),
.IGNORE0 (1'd0),
.IGNORE1 (1'd0),
.S0 (~pclk_sel),
.S1 ( pclk_sel),
//---------- Output --------------------------------
.O (pclk_1)
);
end
else
//---------- Select PCLK Buffer ------------------------
begin : pclk_i1_bufg
//---------- PCLK Buffer -------------------------------
BUFG pclk_i1
(
//---------- Input ---------------------------------
.I (clk_125mhz),
//---------- Output --------------------------------
.O (clk_125mhz_buf)
);
assign pclk_1 = clk_125mhz_buf;
end
endgenerate
//---------- Select PCLK MUX for Slave---------------------------------------------------
generate if(PCIE_CLK_SHARING_EN == "FALSE")
//---------- PCLK MUX for Slave------------------//
begin : pclk_slave_disable
assign CLK_PCLK_SLAVE = 1'b0;
end
else if (PCIE_LINK_SPEED != 1)
begin : pclk_slave_bufgctrl
//---------- PCLK Mux ----------------------------------
BUFGCTRL pclk_slave
(
//---------- Input ---------------------------------
.CE0 (1'd1),
.CE1 (1'd1),
.I0 (clk_125mhz),
.I1 (clk_250mhz),
.IGNORE0 (1'd0),
.IGNORE1 (1'd0),
.S0 (~pclk_sel_slave),
.S1 ( pclk_sel_slave),
//---------- Output --------------------------------
.O (CLK_PCLK_SLAVE)
);
end
else
//---------- Select PCLK Buffer ------------------------
begin : pclk_slave_bufg
//---------- PCLK Buffer -------------------------------
BUFG pclk_slave
(
//---------- Input ---------------------------------
.I (clk_125mhz),
//---------- Output --------------------------------
.O (CLK_PCLK_SLAVE)
);
end
endgenerate
//---------- Generate RXOUTCLK Buffer for Debug --------------------------------
generate if ((PCIE_DEBUG_MODE == 1) || (PCIE_ASYNC_EN == "TRUE"))
begin : rxoutclk_per_lane
//---------- Generate per Lane -------------------------
for (i=0; i<PCIE_LANE; i=i+1)
begin : rxoutclk_i
//---------- RXOUTCLK Buffer -----------------------
BUFG rxoutclk_i
(
//---------- Input -----------------------------
.I (CLK_RXOUTCLK_IN[i]),
//---------- Output ----------------------------
.O (CLK_RXOUTCLK_OUT[i])
);
end
end
else
//---------- Disable RXOUTCLK Buffer for Normal Operation
begin : rxoutclk_i_disable
assign CLK_RXOUTCLK_OUT = {PCIE_LANE{1'd0}};
end
endgenerate
//---------- Generate DCLK Buffer ----------------------------------------------
//generate if (PCIE_USERCLK2_FREQ <= 3)
//---------- Disable DCLK Buffer -----------------------
// begin : dclk_i
// assign CLK_DCLK = userclk2_1; // always less than 125Mhz
// end
//else
// begin : dclk_i_bufg
//---------- DCLK Buffer -------------------------------
// BUFG dclk_i
// (
//---------- Input ---------------------------------
// .I (clk_125mhz),
//---------- Output --------------------------------
// .O (CLK_DCLK)
// );
// end
//endgenerate
generate if (PCIE_LINK_SPEED != 1)
begin : dclk_i_bufg
//---------- DCLK Buffer -------------------------------
BUFG dclk_i
(
//---------- Input ---------------------------------
.I (clk_125mhz),
//---------- Output --------------------------------
.O (CLK_DCLK)
);
end
else
//---------- Disable DCLK Buffer -----------------------
begin : dclk_i
assign CLK_DCLK = clk_125mhz_buf; // always 125 MHz in Gen1
end
endgenerate
//---------- Generate USERCLK1 Buffer ------------------------------------------
generate if (PCIE_GEN1_MODE == 1'b1 && PCIE_USERCLK1_FREQ == 3)
//---------- USERCLK1 same as PCLK -------------------
begin :userclk1_i1_no_bufg
assign userclk1_1 = pclk_1;
end
else
begin : userclk1_i1
//---------- USERCLK1 Buffer ---------------------------
BUFG usrclk1_i1
(
//---------- Input ---------------------------------
.I (userclk1),
//---------- Output --------------------------------
.O (userclk1_1)
);
end
endgenerate
//---------- Generate USERCLK2 Buffer ------------------------------------------
generate if (PCIE_GEN1_MODE == 1'b1 && PCIE_USERCLK2_FREQ == 3 )
//---------- USERCLK2 same as PCLK -------------------
begin : userclk2_i1_no_bufg0
assign userclk2_1 = pclk_1;
end
else if (PCIE_USERCLK2_FREQ == PCIE_USERCLK1_FREQ )
//---------- USERCLK2 same as USERCLK1 -------------------
begin : userclk2_i1_no_bufg1
assign userclk2_1 = userclk1_1;
end
else
begin : userclk2_i1
//---------- USERCLK2 Buffer ---------------------------
BUFG usrclk2_i1
(
//---------- Input ---------------------------------
.I (userclk2),
//---------- Output --------------------------------
.O (userclk2_1)
);
end
endgenerate
//---------- Generate OOBCLK Buffer --------------------------------------------
generate if (PCIE_OOBCLK_MODE == 2)
begin : oobclk_i1
//---------- OOBCLK Buffer -----------------------------
BUFG oobclk_i1
(
//---------- Input ---------------------------------
.I (oobclk),
//---------- Output --------------------------------
.O (CLK_OOBCLK)
);
end
else
//---------- Disable OOBCLK Buffer ---------------------
begin : oobclk_i1_disable
assign CLK_OOBCLK = pclk;
end
endgenerate
// Disabled Second Stage Buffers
assign pclk = pclk_1;
assign CLK_RXUSRCLK = pclk_1;
assign CLK_USERCLK1 = userclk1_1;
assign CLK_USERCLK2 = userclk2_1;
//---------- Select PCLK -------------------------------------------------------
always @ (posedge pclk)
begin
if (!CLK_RST_N)
pclk_sel <= 1'd0;
else
begin
//---------- Select 250 MHz ------------------------
if (&pclk_sel_reg2)
pclk_sel <= 1'd1;
//---------- Select 125 MHz ------------------------
else if (&(~pclk_sel_reg2))
pclk_sel <= 1'd0;
//---------- Hold PCLK -----------------------------
else
pclk_sel <= pclk_sel;
end
end
always @ (posedge pclk)
begin
if (!CLK_RST_N)
pclk_sel_slave<= 1'd0;
else
begin
//---------- Select 250 MHz ------------------------
if (&pclk_sel_slave_reg2)
pclk_sel_slave <= 1'd1;
//---------- Select 125 MHz ------------------------
else if (&(~pclk_sel_slave_reg2))
pclk_sel_slave <= 1'd0;
//---------- Hold PCLK -----------------------------
else
pclk_sel_slave <= pclk_sel_slave;
end
end
//---------- PIPE Clock Output -------------------------------------------------
assign CLK_PCLK = pclk;
assign CLK_MMCM_LOCK = mmcm_lock;
endmodule
|
//
// Designed by Qiang Wu
// 16K bytes, 32bit interface
`timescale 1ns/1ps
module lr0(clk, addr, data_in, data_out, we, en, reset);
input clk;
input [13:2] addr;
input [31:0] data_in;
output [31:0] data_out;
input [3:0] we;
input en;
input reset;
RAMB16_S4_altera localram0(
//.aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[3:0]),
.wren (we[0]),
.q (data_out[3:0])
);
defparam localram0.init_file = "lr_latest_00.mif";
RAMB16_S4_altera localram1(
//.aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[7:4]),
.wren (we[0]),
.q (data_out[7:4])
);
defparam localram1.init_file = "lr_latest_01.mif";
RAMB16_S4_altera localram2(
//.aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[11:8]),
.wren (we[1]),
.q (data_out[11:8])
);
defparam localram2.init_file = "lr_latest_02.mif";
RAMB16_S4_altera localram3(
//.aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[15:12]),
.wren (we[1]),
.q (data_out[15:12])
);
defparam localram3.init_file = "lr_latest_03.mif";
RAMB16_S4_altera localram4(
//.aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[19:16]),
.wren (we[2]),
.q (data_out[19:16])
);
defparam localram4.init_file = "lr_latest_04.mif";
RAMB16_S4_altera localram5(
//.aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[23:20]),
.wren (we[2]),
.q (data_out[23:20])
);
defparam localram5.init_file = "lr_latest_05.mif";
RAMB16_S4_altera localram6(
// .aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[27:24]),
.wren (we[3]),
.q (data_out[27:24])
);
defparam localram6.init_file = "lr_latest_06.mif";
RAMB16_S4_altera localram7(
// .aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[31:28]),
.wren (we[3]),
.q (data_out[31:28])
);
defparam localram7.init_file = "lr_latest_07.mif";
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#8 $
// $Revision: #8 $
// $Date: 2009/02/18 $
// $Author: pscheidt $
//-----------------------------------------------------------------------------
//
// File: altera_std_synchronizer_nocut.v
//
// Abstract: Single bit clock domain crossing synchronizer. Exactly the same
// as altera_std_synchronizer.v, except that the embedded false
// path constraint is removed in this module. If you use this
// module, you will have to apply the appropriate timing
// constraints.
//
// We expect to make this a standard Quartus atom eventually.
//
// Composed of two or more flip flops connected in series.
// Random metastable condition is simulated when the
// __ALTERA_STD__METASTABLE_SIM macro is defined.
// Use +define+__ALTERA_STD__METASTABLE_SIM argument
// on the Verilog simulator compiler command line to
// enable this mode. In addition, define the macro
// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output
// with every metastable event generated in the synchronizer.
//
// Copyright (C) Altera Corporation 2009, All Rights Reserved
//-----------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_std_synchronizer_nocut (
clk,
reset_n,
din,
dout
);
parameter depth = 3; // This value must be >= 2 !
parameter rst_value = 0;
input clk;
input reset_n;
input din;
output dout;
// QuartusII synthesis directives:
// 1. Preserve all registers ie. do not touch them.
// 2. Do not merge other flip-flops with synchronizer flip-flops.
// QuartusII TimeQuest directives:
// 1. Identify all flip-flops in this module as members of the synchronizer
// to enable automatic metastability MTBF analysis.
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
//synthesis translate_off
initial begin
if (depth <2) begin
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
end
end
// the first synchronizer register is either a simple D flop for synthesis
// and non-metastable simulation or a D flop with a method to inject random
// metastable events resulting in random delay of [0,1] cycles
`ifdef __ALTERA_STD__METASTABLE_SIM
reg[31:0] RANDOM_SEED = 123456;
wire next_din_s1;
wire dout;
reg din_last;
reg random;
event metastable_event; // hook for debug monitoring
initial begin
$display("%m: Info: Metastable event injection simulation mode enabled");
end
always @(posedge clk) begin
if (reset_n == 0)
random <= $random(RANDOM_SEED);
else
random <= $random;
end
assign next_din_s1 = (din_last ^ din) ? random : din;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_last <= (rst_value == 0)? 1'b0 : 1'b1;
else
din_last <= din;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= (rst_value == 0)? 1'b0 : 1'b1;
else
din_s1 <= next_din_s1;
end
`else
//synthesis translate_on
generate if (rst_value == 0)
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= din;
end
endgenerate
generate if (rst_value == 1)
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b1;
else
din_s1 <= din;
end
endgenerate
//synthesis translate_off
`endif
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
always @(*) begin
if (reset_n && (din_last != din) && (random != din)) begin
$display("%m: Verbose Info: metastable event @ time %t", $time);
->metastable_event;
end
end
`endif
//synthesis translate_on
// the remaining synchronizer registers form a simple shift register
// of length depth-1
generate if (rst_value == 0)
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
generate if (rst_value == 1)
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b1}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b1}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
assign dout = dreg[depth-2];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD2_1_V
`define SKY130_FD_SC_LS__DLYGATE4SD2_1_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog wrapper for dlygate4sd2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlygate4sd2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlygate4sd2_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlygate4sd2 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlygate4sd2_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlygate4sd2 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD2_1_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
`define FMT_TXENGUPR32_WR32 7'b10_00000
`define FMT_TXENGUPR32_RD32 7'b00_00000
`define FMT_TXENGUPR32_WR64 7'b11_00000
`define FMT_TXENGUPR32_RD64 7'b01_00000
`define S_TXENGUPR32_MAIN_IDLE 6'b00_0001
`define S_TXENGUPR32_MAIN_RD 6'b00_0010
`define S_TXENGUPR32_MAIN_WR 6'b00_0100
`define S_TXENGUPR32_MAIN_WAIT_0 6'b00_1000
`define S_TXENGUPR32_MAIN_WAIT_1 6'b01_0000
`define S_TXENGUPR32_MAIN_WAIT_2 6'b10_0000
`define S_TXENGUPR32_CAP_RD_WR 4'b0001
`define S_TXENGUPR32_CAP_WR_RD 4'b0010
`define S_TXENGUPR32_CAP_CAP 4'b0100
`define S_TXENGUPR32_CAP_REL 4'b1000
`include "trellis.vh"
`timescale 1ns/1ns
module tx_multiplexer_32
#(
parameter C_PCI_DATA_WIDTH = 9'd32,
parameter C_NUM_CHNL = 4'd12,
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_VENDOR = "XILINX"
)
(
input CLK,
input RST_IN,
input [C_NUM_CHNL-1:0] WR_REQ, // Write request
input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] WR_ADDR, // Write address
input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] WR_LEN, // Write data length
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA, // Write data
output [C_NUM_CHNL-1:0] WR_DATA_REN, // Write data read enable
output [C_NUM_CHNL-1:0] WR_ACK, // Write request has been accepted
input [C_NUM_CHNL-1:0] RD_REQ, // Read request
input [(C_NUM_CHNL*2)-1:0] RD_SG_CHNL, // Read request channel for scatter gather lists
input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] RD_ADDR, // Read request address
input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] RD_LEN, // Read request length
output [C_NUM_CHNL-1:0] RD_ACK, // Read request has been accepted
output [5:0] INT_TAG, // Internal tag to exchange with external
output INT_TAG_VALID, // High to signal tag exchange
input [C_TAG_WIDTH-1:0] EXT_TAG, // External tag to provide in exchange for internal tag
input EXT_TAG_VALID, // High to signal external tag is valid
output TX_ENG_RD_REQ_SENT, // Read completion request issued
input RXBUF_SPACE_AVAIL,
// Interface: TXR Engine
output TXR_DATA_VALID,
output [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
output TXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
output TXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
input TXR_DATA_READY,
output TXR_META_VALID,
output [`SIG_FBE_W-1:0] TXR_META_FDWBE,
output [`SIG_LBE_W-1:0] TXR_META_LDWBE,
output [`SIG_ADDR_W-1:0] TXR_META_ADDR,
output [`SIG_LEN_W-1:0] TXR_META_LENGTH,
output [`SIG_TAG_W-1:0] TXR_META_TAG,
output [`SIG_TC_W-1:0] TXR_META_TC,
output [`SIG_ATTR_W-1:0] TXR_META_ATTR,
output [`SIG_TYPE_W-1:0] TXR_META_TYPE,
output TXR_META_EP,
input TXR_META_READY
);
`include "functions.vh"
// Local parameters
localparam C_DATA_DELAY = 6'd1; // Delays read/write params to accommodate tx_port_buffer delay and tx_engine_formatter delay.
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [5:0] rMainState=`S_TXENGUPR32_MAIN_IDLE, _rMainState=`S_TXENGUPR32_MAIN_IDLE;
reg [3:0] rCountChnl=0, _rCountChnl=0;
reg [C_TAG_WIDTH-1:0] rCountTag=0, _rCountTag=0;
reg [9:0] rCount=0, _rCount=0;
reg rCountDone=0, _rCountDone=0;
reg rCountStart=0, _rCountStart=0;
reg rCount32=0, _rCount32=0;
reg [C_NUM_CHNL-1:0] rWrDataRen=0, _rWrDataRen=0;
reg rTxEngRdReqAck, _rTxEngRdReqAck;
wire wRdReq;
wire [3:0] wRdReqChnl;
wire wWrReq;
wire [3:0] wWrReqChnl;
wire wRdAck;
wire [3:0] wCountChnl;
wire [11:0] wCountChnlShiftDW = (wCountChnl*C_PCI_DATA_WIDTH); // Mult can exceed 9 bits, so make this a wire
wire [63:0] wRdAddr;
wire [9:0] wRdLen;
wire [1:0] wRdSgChnl;
wire [63:0] wWrAddr;
wire [9:0] wWrLen;
wire [C_PCI_DATA_WIDTH-1:0] wWrData;
reg [3:0] rRdChnl=0, _rRdChnl=0;
reg [61:0] rRdAddr=62'd0, _rRdAddr=62'd0;
reg [9:0] rRdLen=0, _rRdLen=0;
reg [1:0] rRdSgChnl=0, _rRdSgChnl=0;
reg [3:0] rWrChnl=0, _rWrChnl=0;
reg [61:0] rWrAddr=62'd0, _rWrAddr=62'd0;
reg [9:0] rWrLen=0, _rWrLen=0;
reg [C_PCI_DATA_WIDTH-1:0] rWrData={C_PCI_DATA_WIDTH{1'd0}}, _rWrData={C_PCI_DATA_WIDTH{1'd0}};
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [3:0] rCapState=`S_TXENGUPR32_CAP_RD_WR, _rCapState=`S_TXENGUPR32_CAP_RD_WR;
reg [C_NUM_CHNL-1:0] rRdAck=0, _rRdAck=0;
reg [C_NUM_CHNL-1:0] rWrAck=0, _rWrAck=0;
reg rIsWr=0, _rIsWr=0;
reg [5:0] rCapChnl=0, _rCapChnl=0;
reg [61:0] rCapAddr=62'd0, _rCapAddr=62'd0;
reg rCapAddr64=0, _rCapAddr64=0;
reg [9:0] rCapLen=0, _rCapLen=0;
reg rCapIsWr=0, _rCapIsWr=0;
reg rExtTagReq=0, _rExtTagReq=0;
reg [C_TAG_WIDTH-1:0] rExtTag=0, _rExtTag=0;
reg [C_DATA_DELAY-1:0] rWnR=0, _rWnR=0;
reg [(C_DATA_DELAY*4)-1:0] rChnl=0, _rChnl=0;
reg [(C_DATA_DELAY*8)-1:0] rTag=0, _rTag=0;
reg [(C_DATA_DELAY*62)-1:0] rAddr=0, _rAddr=0;
reg [C_DATA_DELAY-1:0] rAddr64=0, _rAddr64=0;
reg [(C_DATA_DELAY*10)-1:0] rLen=0, _rLen=0;
reg [C_DATA_DELAY-1:0] rLenEQ1=0, _rLenEQ1=0;
reg [C_DATA_DELAY-1:0] rValid=0, _rValid=0;
reg [C_DATA_DELAY-1:0] rDone=0, _rDone=0;
reg [C_DATA_DELAY-1:0] rStart=0, _rStart=0;
assign wRdAddr = RD_ADDR[wRdReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
assign wRdLen = RD_LEN[wRdReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
assign wRdSgChnl = RD_SG_CHNL[wRdReqChnl * 2 +: 2];
assign wWrAddr = WR_ADDR[wWrReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
assign wWrLen = WR_LEN[wWrReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
assign wWrData = WR_DATA[wCountChnl * C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
assign WR_DATA_REN = rWrDataRen;
assign WR_ACK = rWrAck;
assign RD_ACK = rRdAck;
assign INT_TAG = {rRdSgChnl, rRdChnl};
assign INT_TAG_VALID = rExtTagReq;
assign TX_ENG_RD_REQ_SENT = rTxEngRdReqAck;
assign wRdAck = (wRdReq & EXT_TAG_VALID & RXBUF_SPACE_AVAIL);
// Search for the next request so that we can move onto it immediately after
// the current channel has released its request.
tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selRd (.RST(RST_IN), .CLK(CLK), .REQ_ALL(RD_REQ), .REQ(wRdReq), .CHNL(wRdReqChnl));
tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selWr (.RST(RST_IN), .CLK(CLK), .REQ_ALL(WR_REQ), .REQ(wWrReq), .CHNL(wWrReqChnl));
// Buffer shift-selected channel request signals and FIFO data.
always @ (posedge CLK) begin
rRdChnl <= #1 _rRdChnl;
rRdAddr <= #1 _rRdAddr;
rRdLen <= #1 _rRdLen;
rRdSgChnl <= #1 _rRdSgChnl;
rWrChnl <= #1 _rWrChnl;
rWrAddr <= #1 _rWrAddr;
rWrLen <= #1 _rWrLen;
rWrData <= #1 _rWrData;
end
always @ (*) begin
_rRdChnl = wRdReqChnl;
_rRdAddr = wRdAddr[63:2];
_rRdLen = wRdLen;
_rRdSgChnl = wRdSgChnl;
_rWrChnl = wWrReqChnl;
_rWrAddr = wWrAddr[63:2];
_rWrLen = wWrLen;
_rWrData = wWrData;
end
// Accept requests when the selector indicates. Capture the buffered
// request parameters for hand-off to the formatting pipeline. Then
// acknowledge the receipt to the channel so it can deassert the
// request, and let the selector choose another channel.
always @ (posedge CLK) begin
rCapState <= #1 (RST_IN ? `S_TXENGUPR32_CAP_RD_WR : _rCapState);
rRdAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rRdAck);
rWrAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rWrAck);
rIsWr <= #1 _rIsWr;
rCapChnl <= #1 _rCapChnl;
rCapAddr <= #1 _rCapAddr;
rCapAddr64 <= #1 _rCapAddr64;
rCapLen <= #1 _rCapLen;
rCapIsWr <= #1 _rCapIsWr;
rExtTagReq <= #1 _rExtTagReq;
rExtTag <= #1 _rExtTag;
rTxEngRdReqAck <= #1 _rTxEngRdReqAck;
end
always @ (*) begin
_rCapState = rCapState;
_rRdAck = rRdAck;
_rWrAck = rWrAck;
_rIsWr = rIsWr;
_rCapChnl = rCapChnl;
_rCapAddr = rCapAddr;
_rCapAddr64 = (rCapAddr[61:30] != 0);
_rCapLen = rCapLen;
_rCapIsWr = rCapIsWr;
_rExtTagReq = rExtTagReq;
_rExtTag = rExtTag;
_rTxEngRdReqAck = rTxEngRdReqAck;
case (rCapState)
`S_TXENGUPR32_CAP_RD_WR : begin
_rIsWr = !wRdReq;
_rRdAck = ((wRdAck)<<wRdReqChnl);
_rTxEngRdReqAck = wRdAck;
_rExtTagReq = wRdAck;
_rCapState = (wRdAck ? `S_TXENGUPR32_CAP_CAP : `S_TXENGUPR32_CAP_WR_RD);
end
`S_TXENGUPR32_CAP_WR_RD : begin
_rIsWr = wWrReq;
_rWrAck = (wWrReq<<wWrReqChnl);
_rCapState = (wWrReq ? `S_TXENGUPR32_CAP_CAP : `S_TXENGUPR32_CAP_RD_WR);
end
`S_TXENGUPR32_CAP_CAP : begin
_rTxEngRdReqAck = 0;
_rRdAck = 0;
_rWrAck = 0;
_rCapIsWr = rIsWr;
_rExtTagReq = 0;
_rExtTag = EXT_TAG;
if (rIsWr) begin
_rCapChnl = {2'd0, rWrChnl};
_rCapAddr = rWrAddr;
_rCapLen = rWrLen;
end
else begin
_rCapChnl = {rRdSgChnl, rRdChnl};
_rCapAddr = rRdAddr;
_rCapLen = rRdLen;
end
_rCapState = `S_TXENGUPR32_CAP_REL;
end
`S_TXENGUPR32_CAP_REL : begin
// Push into the formatting pipeline when ready
if (TXR_META_READY & rMainState[0]) // S_TXENGUPR32_MAIN_IDLE
_rCapState = (`S_TXENGUPR32_CAP_WR_RD>>(rCapIsWr)); // Changes to S_TXENGUPR32_CAP_RD_WR
end
default : begin
_rCapState = `S_TXENGUPR32_CAP_RD_WR;
end
endcase
end
// Start the read/write when space is available in the output FIFO and when
// request parameters have been captured (i.e. a pending request).
always @ (posedge CLK) begin
rMainState <= #1 (RST_IN ? `S_TXENGUPR32_MAIN_IDLE : _rMainState);
rCount <= #1 _rCount;
rCountDone <= #1 _rCountDone;
rCountStart <= #1 _rCountStart;
rCountChnl <= #1 _rCountChnl;
rCountTag <= #1 _rCountTag;
rCount32 <= #1 _rCount32;
rWrDataRen <= #1 _rWrDataRen;
end
always @ (*) begin
_rMainState = rMainState;
_rCount = rCount;
_rCountDone = rCountDone;
_rCountChnl = rCountChnl;
_rCountTag = rCountTag;
_rCount32 = rCount32;
_rWrDataRen = rWrDataRen;
_rCountStart = 0;
case (rMainState)
`S_TXENGUPR32_MAIN_IDLE : begin
_rCount = rCapLen;
_rCountDone = (rCapLen == 10'd1);
_rCountChnl = rCapChnl[3:0];
_rCountTag = rExtTag;
_rCount32 = (rCapAddr[61:30] == 0);
_rWrDataRen = ((TXR_META_READY & rCapState[3] & rCapIsWr)<<(rCapChnl[3:0])); // S_TXENGUPR32_CAP_REL
_rCountStart = (TXR_META_READY & rCapState[3]);
if (TXR_META_READY & rCapState[3]) // S_TXENGUPR32_CAP_REL
_rMainState = (`S_TXENGUPR32_MAIN_RD<<(rCapIsWr)); // Change to S_TXENGUPR32_MAIN_WR;
end
`S_TXENGUPR32_MAIN_RD : begin
_rMainState = (`S_TXENGUPR32_MAIN_WAIT_1<<(rCount32)); // Change to S_TXENGUPR32_MAIN_WAIT_2
end
`S_TXENGUPR32_MAIN_WR : begin
_rCount = rCount - 1'd1;
_rCountDone = (rCount == 2'd2);
if (rCountDone) begin
_rWrDataRen = 0;
_rMainState = (`S_TXENGUPR32_MAIN_WAIT_0<<(rCount32)); // Change to S_TXENGUPR32_MAIN_WAIT_1
end
end
`S_TXENGUPR32_MAIN_WAIT_0 : begin
_rMainState = `S_TXENGUPR32_MAIN_WAIT_1;
end
`S_TXENGUPR32_MAIN_WAIT_1 : begin
_rMainState = `S_TXENGUPR32_MAIN_WAIT_2;
end
`S_TXENGUPR32_MAIN_WAIT_2 : begin
_rMainState = `S_TXENGUPR32_MAIN_IDLE;
end
default : begin
_rMainState = `S_TXENGUPR32_MAIN_IDLE;
end
endcase
end
// Shift in the captured parameters and valid signal every cycle.
// This pipeline will keep the formatter busy.
assign wCountChnl = rCountChnl[3:0];
always @ (posedge CLK) begin
rWnR <= #1 _rWnR;
rChnl <= #1 _rChnl;
rTag <= #1 _rTag;
rAddr <= #1 _rAddr;
rAddr64 <= #1 _rAddr64;
rLen <= #1 _rLen;
rLenEQ1 <= #1 _rLenEQ1;
rValid <= #1 _rValid;
end
always @ (*) begin
_rWnR = ((rWnR<<1) | rCapIsWr);
_rChnl = ((rChnl<<4) | rCountChnl);
_rTag = ((rTag<<8) | (8'd0 | rCountTag));
_rAddr = ((rAddr<<62) | rCapAddr);
_rAddr64 = ((rAddr64<<1) | rCapAddr64);
_rLen = ((rLen<<10) | rCapLen);
_rLenEQ1 = ((rLenEQ1<<1) | (rCapLen == 10'd1));
_rValid = ((rValid<<1) | (rMainState[2] | rMainState[1])); // S_TXENGUPR64_MAIN_RD | S_TXENGUPR64_MAIN_WR
_rDone = rDone<<1 | rCountDone;
_rStart = rStart<<1 | rCountStart;
end
assign TXR_DATA = rWrData;
assign TXR_DATA_VALID = rValid[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_START_FLAG = rStart[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_START_OFFSET = 0;
assign TXR_DATA_END_FLAG = rDone[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_END_OFFSET = rLen[(C_DATA_DELAY-1)*10 +:`SIG_OFFSET_W] - 1;
assign TXR_META_VALID = rCountStart;
assign TXR_META_TYPE = rCapIsWr ? `TRLS_REQ_WR : `TRLS_REQ_RD;
assign TXR_META_ADDR = {rCapAddr,2'b00};
assign TXR_META_LENGTH = rCapLen;
assign TXR_META_LDWBE = rCapLen == 10'd1 ? 0 : 4'b1111;
assign TXR_META_FDWBE = 4'b1111;
assign TXR_META_TAG = rCountTag;
assign TXR_META_EP = 1'b0;
assign TXR_META_ATTR = 3'b110;
assign TXR_META_TC = 0;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Fri Mar 31 08:57:14 2017
// Host : Shaun running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/Shaun/Desktop/ip_repo/axi_compression_1.0/src/bram_4096/bram_4096_stub.v
// Design : bram_4096
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module bram_4096(clka, ena, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[11:0],dina[19:0],douta[19:0]" */;
input clka;
input ena;
input [0:0]wea;
input [11:0]addra;
input [19:0]dina;
output [19:0]douta;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD2_SYMBOL_V
`define SKY130_FD_SC_MS__DLYGATE4SD2_SYMBOL_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlygate4sd2 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD2_SYMBOL_V
|
`timescale 1ns / 1ps
/*
Group Members: Nikita Eisenhauer and Warren Seto
Lab Name: Adder Design
Design Description: Verilog Test Fixture to test the behavioral 64-bit adder
*/
module behavioral_full_adder_test;
// Inputs
reg [63:0] A;
reg [63:0] B;
// Outputs
wire [64:0] SUM;
// Instantiate two counter variables for the test loop
integer count;
integer count2;
// Instantiate the Unit Under Test (UUT)
behavioral_full_adder_64 uut
(
.A(A),
.B(B),
.SUM(SUM)
);
initial begin
$monitor("%d + %d = %d", A, B, SUM);
// Iterate through all possible combination of 0-32
count = 0;
count2 = 0;
A = 0;
B = 0;
// Loops over the possible combinations for the inputs A and B
for (count = 0; count <= 32; count = count + 1) begin
{A} = count;
for (count2 = 0; count2 <= 32; count2 = count2 + 1) begin
{B} = count2;
#1;
end
end
end
initial #4000 $finish; // The test will run for a total interval of 4000 nanoseconds
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9_MulnS_0(clk, ce, a, b, p);
input clk;
input ce;
input[16 - 1 : 0] a; // synthesis attribute keep a "true"
input[8 - 1 : 0] b; // synthesis attribute keep b "true"
output[24 - 1 : 0] p;
reg[16 - 1 : 0] a_reg;
reg[8 - 1 : 0] b_reg;
wire [24 - 1 : 0] tmp_product;
reg[24 - 1 : 0] buff0;
reg[24 - 1 : 0] buff1;
reg[24 - 1 : 0] buff2;
reg[24 - 1 : 0] buff3;
reg[24 - 1 : 0] buff4;
reg[24 - 1 : 0] buff5;
reg[24 - 1 : 0] buff6;
assign p = buff6;
assign tmp_product = a_reg * b_reg;
always @ (posedge clk) begin
if (ce) begin
a_reg <= a;
b_reg <= b;
buff0 <= tmp_product;
buff1 <= buff0;
buff2 <= buff1;
buff3 <= buff2;
buff4 <= buff3;
buff5 <= buff4;
buff6 <= buff5;
end
end
endmodule
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9_MulnS_0 nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9_MulnS_0_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
by_width #(1) w1 (.clk(clk));
by_width #(31) w31 (.clk(clk));
by_width #(32) w32 (.clk(clk));
by_width #(33) w33 (.clk(clk));
by_width #(63) w63 (.clk(clk));
by_width #(64) w64 (.clk(clk));
by_width #(65) w65 (.clk(clk));
by_width #(95) w95 (.clk(clk));
by_width #(96) w96 (.clk(clk));
by_width #(97) w97 (.clk(clk));
reg signed [15:0] a;
reg signed [4:0] b;
reg signed [15:0] sr,srs,sl,sls;
reg [15:0] b_s;
reg [15:0] b_us;
task check_s(input signed [7:0] i, input [7:0] expval);
//$display("check_s %x\n", i);
if (i !== expval) $stop;
endtask
task check_us(input signed [7:0] i, input [7:0] expval);
//$display("check_us %x\n", i);
if (i !== expval) $stop;
endtask
always @* begin
sr = a>>b;
srs = copy_signed(a)>>>b;
sl = a<<b;
sls = a<<<b;
// verilator lint_off WIDTH
b_s = b>>>4; // Signed
b_us = b[4:0]>>>4; // Unsigned, due to extract
check_s ( 3'b111, 8'h07);
check_s (3'sb111, 8'hff);
check_us( 3'b111, 8'h07);
check_us(3'sb111, 8'hff); // Note we sign extend ignoring function's input requirements
// verilator lint_on WIDTH
end
reg signed [32:0] bug349;
initial
begin
end
integer i;
initial begin
if ((-1 >>> 3) != -1) $stop; // Decimals are signed
// verilator lint_off WIDTH
if ((3'b111 >>> 3) != 0) $stop; // Based numbers are unsigned
if ((3'sb111 >>> 3) != -1) $stop; // Signed based numbers
// verilator lint_on WIDTH
if ( (3'sb000 > 3'sb000)) $stop;
if (!(3'sb000 > 3'sb111)) $stop;
if ( (3'sb111 > 3'sb000)) $stop;
if ( (3'sb000 < 3'sb000)) $stop;
if ( (3'sb000 < 3'sb111)) $stop;
if (!(3'sb111 < 3'sb000)) $stop;
if (!(3'sb000 >= 3'sb000)) $stop;
if (!(3'sb000 >= 3'sb111)) $stop;
if ( (3'sb111 >= 3'sb000)) $stop;
if (!(3'sb000 <= 3'sb000)) $stop;
if ( (3'sb000 <= 3'sb111)) $stop;
if (!(3'sb111 <= 3'sb000)) $stop;
// When we multiply overflow, the sign bit stays correct.
if ( (4'sd2*4'sd8) != 4'd0) $stop;
// From the spec:
// verilator lint_off WIDTH
i = -12 /3; if (i !== 32'hfffffffc) $stop;
i = -'d12 /3; if (i !== 32'h55555551) $stop;
i = -'sd12 /3; if (i !== 32'hfffffffc) $stop;
i = -4'sd12 /3; if (i !== 32'h00000001) $stop;
// verilator lint_on WIDTH
// verilator lint_off WIDTH
bug349 = 4'sb1111 - 1'b1;
if (bug349 != 32'he) $stop;
end
function signed [15:0] copy_signed;
input [15:0] ai;
copy_signed = ai;
endfunction
integer cyc; initial cyc=0;
wire [31:0] ucyc = cyc;
always @ (posedge clk) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%x %x %x %x %x %x %x\n", cyc, sr,srs,sl,sls, b_s,b_us);
`endif
case (cyc)
0: begin
a <= 16'sh8b1b; b <= 5'sh1f; // -1
end
1: begin
// Check spaces in constants
a <= 16 'sh 8b1b; b <= 5'sh01; // -1
end
2: begin
a <= 16'sh8b1b; b <= 5'sh1e; // shift AMOUNT is really unsigned
if (ucyc / 1 != 32'd2) $stop;
if (ucyc / 2 != 32'd1) $stop;
if (ucyc * 1 != 32'd2) $stop;
if (ucyc * 2 != 32'd4) $stop;
if (ucyc * 3 != 32'd6) $stop;
if (cyc * 32'sd1 != 32'sd2) $stop;
if (cyc * 32'sd2 != 32'sd4) $stop;
if (cyc * 32'sd3 != 32'sd6) $stop;
end
3: begin
a <= 16'sh0048; b <= 5'sh1f;
if (ucyc * 1 != 32'd3) $stop;
if (ucyc * 2 != 32'd6) $stop;
if (ucyc * 3 != 32'd9) $stop;
if (ucyc * 4 != 32'd12) $stop;
if (cyc * 32'sd1 != 32'sd3) $stop;
if (cyc * 32'sd2 != 32'sd6) $stop;
if (cyc * 32'sd3 != 32'sd9) $stop;
end
4: begin
a <= 16'sh4154; b <= 5'sh02;
end
5: begin
a <= 16'shc3e8; b <= 5'sh12;
end
6: begin
a <= 16'sh488b; b <= 5'sh02;
end
9: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: ;
endcase
case (cyc)
0: ;
1: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop;
2: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh458d_c58d_1636_1636_0000_0000) $stop;
3: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop;
4: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_0000_0000_0000_ffff_0001) $stop;
5: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh1055_1055_0550_0550_0000_0000) $stop;
6: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop;
7: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh1222_1222_222c_222c_0000_0000) $stop;
8: ;
9: ;
endcase
end
endmodule
module by_width (
input clk
);
parameter WIDTH=1;
reg signed i1;
reg signed [62:0] i63;
reg signed [64:0] i65;
// verilator lint_off WIDTH
wire signed [WIDTH-1:0] i1extp /*verilator public*/ = i1;
wire signed [WIDTH-1:0] i1ext = i1;
wire signed [WIDTH-1:0] i63ext = i63;
wire signed [WIDTH-1:0] i65ext = i65;
// verilator lint_on WIDTH
integer cyc; initial cyc=0;
always @ (posedge clk) begin
cyc <= cyc + 1;
i1 <= cyc[0];
i63 <= {63{cyc[0]}};
i65 <= {65{cyc[0]}};
case (cyc)
1: begin
if (i1extp != {WIDTH{1'b0}}) $stop;
if (i1ext != {WIDTH{1'b0}}) $stop;
if (i63ext != {WIDTH{1'b0}}) $stop;
if (i65ext != {WIDTH{1'b0}}) $stop;
end
2: begin
if (i1extp != {WIDTH{1'b1}}) $stop;
if (i1ext != {WIDTH{1'b1}}) $stop;
if (i63ext != {WIDTH{1'b1}}) $stop;
if (i65ext != {WIDTH{1'b1}}) $stop;
end
default: ;
endcase
end
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: si_transactor.v
//
// Description:
// This module manages multi-threaded transactions for one SI-slot.
// The module interface consists of a 1-slave to 1-master address channel, plus a
// (M+1)-master (from M MI-slots plus error handler) to 1-slave response channel.
// The module maintains transaction thread control registers that count the
// number of outstanding transations for each thread and the target MI-slot.
// On the address channel, the module decodes addresses to select among MI-slots
// accessible to the SI-slot where it is instantiated.
// It then qualifies whether each received transaction
// should be propagated as a request to the address channel arbiter.
// Transactions are blocked while there is any outstanding transaction to a
// different slave (MI-slot) for the requested ID thread (for deadlock avoidance).
// On the response channel, the module mulitplexes transfers from each of the
// MI-slots whenever a transfer targets the ID of an active thread,
// arbitrating between MI-slots if multiple threads respond concurrently.
//
//--------------------------------------------------------------------------
//
// Structure:
// si_transactor
// addr_decoder
// comparator_static
// mux_enc
// axic_srl_fifo
// arbiter_resp
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_9_si_transactor #
(
parameter C_FAMILY = "none",
parameter integer C_SI = 0, // SI-slot number of current instance.
parameter integer C_DIR = 0, // Direction: 0 = Write; 1 = Read.
parameter integer C_NUM_ADDR_RANGES = 1,
parameter integer C_NUM_M = 2,
parameter integer C_NUM_M_LOG = 1,
parameter integer C_ACCEPTANCE = 1, // Acceptance limit of this SI-slot.
parameter integer C_ACCEPTANCE_LOG = 0, // Width of acceptance counter for this SI-slot.
parameter integer C_ID_WIDTH = 1,
parameter integer C_THREAD_ID_WIDTH = 0,
parameter integer C_ADDR_WIDTH = 32,
parameter integer C_AMESG_WIDTH = 1, // Used for AW or AR channel payload, depending on instantiation.
parameter integer C_RMESG_WIDTH = 1, // Used for B or R channel payload, depending on instantiation.
parameter [C_ID_WIDTH-1:0] C_BASE_ID = {C_ID_WIDTH{1'b0}},
parameter [C_ID_WIDTH-1:0] C_HIGH_ID = {C_ID_WIDTH{1'b0}},
parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b1}},
parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b0}},
parameter integer C_SINGLE_THREAD = 0,
parameter [C_NUM_M-1:0] C_TARGET_QUAL = {C_NUM_M{1'b1}},
parameter [C_NUM_M*32-1:0] C_M_AXI_SECURE = {C_NUM_M{32'h00000000}},
parameter integer C_RANGE_CHECK = 0,
parameter integer C_ADDR_DECODE =0,
parameter [C_NUM_M*32-1:0] C_ERR_MODE = {C_NUM_M{32'h00000000}},
parameter integer C_DEBUG = 1
)
(
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Address Channel Interface Ports
input wire [C_ID_WIDTH-1:0] S_AID,
input wire [C_ADDR_WIDTH-1:0] S_AADDR,
input wire [8-1:0] S_ALEN,
input wire [3-1:0] S_ASIZE,
input wire [2-1:0] S_ABURST,
input wire [2-1:0] S_ALOCK,
input wire [3-1:0] S_APROT,
// input wire [4-1:0] S_AREGION,
input wire [C_AMESG_WIDTH-1:0] S_AMESG,
input wire S_AVALID,
output wire S_AREADY,
// Master Address Channel Interface Ports
output wire [C_ID_WIDTH-1:0] M_AID,
output wire [C_ADDR_WIDTH-1:0] M_AADDR,
output wire [8-1:0] M_ALEN,
output wire [3-1:0] M_ASIZE,
output wire [2-1:0] M_ALOCK,
output wire [3-1:0] M_APROT,
output wire [4-1:0] M_AREGION,
output wire [C_AMESG_WIDTH-1:0] M_AMESG,
output wire [(C_NUM_M+1)-1:0] M_ATARGET_HOT,
output wire [(C_NUM_M_LOG+1)-1:0] M_ATARGET_ENC,
output wire [7:0] M_AERROR,
output wire M_AVALID_QUAL,
output wire M_AVALID,
input wire M_AREADY,
// Slave Response Channel Interface Ports
output wire [C_ID_WIDTH-1:0] S_RID,
output wire [C_RMESG_WIDTH-1:0] S_RMESG,
output wire S_RLAST,
output wire S_RVALID,
input wire S_RREADY,
// Master Response Channel Interface Ports
input wire [(C_NUM_M+1)*C_ID_WIDTH-1:0] M_RID,
input wire [(C_NUM_M+1)*C_RMESG_WIDTH-1:0] M_RMESG,
input wire [(C_NUM_M+1)-1:0] M_RLAST,
input wire [(C_NUM_M+1)-1:0] M_RVALID,
output wire [(C_NUM_M+1)-1:0] M_RREADY,
input wire [(C_NUM_M+1)-1:0] M_RTARGET, // Does response ID from each MI-slot target this SI slot?
input wire [8-1:0] DEBUG_A_TRANS_SEQ
);
localparam integer P_WRITE = 0;
localparam integer P_READ = 1;
localparam integer P_RMUX_MESG_WIDTH = C_ID_WIDTH + C_RMESG_WIDTH + 1;
localparam [31:0] P_AXILITE_ERRMODE = 32'h00000001;
localparam integer P_NONSECURE_BIT = 1;
localparam integer P_NUM_M_LOG_M1 = C_NUM_M_LOG ? C_NUM_M_LOG : 1;
localparam [C_NUM_M-1:0] P_M_AXILITE = f_m_axilite(0); // Mask of AxiLite MI-slots
localparam [1:0] P_FIXED = 2'b00;
localparam integer P_NUM_M_DE_LOG = f_ceil_log2(C_NUM_M+1);
localparam integer P_THREAD_ID_WIDTH_M1 = (C_THREAD_ID_WIDTH > 0) ? C_THREAD_ID_WIDTH : 1;
localparam integer P_NUM_ID_VAL = 2**C_THREAD_ID_WIDTH;
localparam integer P_NUM_THREADS = (P_NUM_ID_VAL < C_ACCEPTANCE) ? P_NUM_ID_VAL : C_ACCEPTANCE;
localparam [C_NUM_M-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE); // Mask of secure MI-slots
// Ceiling of log2(x)
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// AxiLite protocol flag vector
function [C_NUM_M-1:0] f_m_axilite
(
input integer null_arg
);
integer mi;
begin
for (mi=0; mi<C_NUM_M; mi=mi+1) begin
f_m_axilite[mi] = (C_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE);
end
end
endfunction
// Convert Bit32 vector of range [0,1] to Bit1 vector on MI
function [C_NUM_M-1:0] f_bit32to1_mi
(input [C_NUM_M*32-1:0] vec32);
integer mi;
begin
for (mi=0; mi<C_NUM_M; mi=mi+1) begin
f_bit32to1_mi[mi] = vec32[mi*32];
end
end
endfunction
wire [C_NUM_M-1:0] target_mi_hot;
wire [P_NUM_M_LOG_M1-1:0] target_mi_enc;
wire [(C_NUM_M+1)-1:0] m_atarget_hot_i;
wire [(P_NUM_M_DE_LOG)-1:0] m_atarget_enc_i;
wire match;
wire [3:0] target_region;
wire [3:0] m_aregion_i;
wire m_avalid_i;
wire s_aready_i;
wire any_error;
wire s_rvalid_i;
wire [C_ID_WIDTH-1:0] s_rid_i;
wire s_rlast_i;
wire [P_RMUX_MESG_WIDTH-1:0] si_rmux_mesg;
wire [(C_NUM_M+1)*P_RMUX_MESG_WIDTH-1:0] mi_rmux_mesg;
wire [(C_NUM_M+1)-1:0] m_rvalid_qual;
wire [(C_NUM_M+1)-1:0] m_rready_arb;
wire [(C_NUM_M+1)-1:0] m_rready_i;
wire target_secure;
wire target_axilite;
wire m_avalid_qual_i;
wire [7:0] m_aerror_i;
genvar gen_mi;
genvar gen_thread;
generate
if (C_ADDR_DECODE) begin : gen_addr_decoder
axi_crossbar_v2_1_9_addr_decoder #
(
.C_FAMILY (C_FAMILY),
.C_NUM_TARGETS (C_NUM_M),
.C_NUM_TARGETS_LOG (P_NUM_M_LOG_M1),
.C_NUM_RANGES (C_NUM_ADDR_RANGES),
.C_ADDR_WIDTH (C_ADDR_WIDTH),
.C_TARGET_ENC (1),
.C_TARGET_HOT (1),
.C_REGION_ENC (1),
.C_BASE_ADDR (C_BASE_ADDR),
.C_HIGH_ADDR (C_HIGH_ADDR),
.C_TARGET_QUAL (C_TARGET_QUAL),
.C_RESOLUTION (2)
)
addr_decoder_inst
(
.ADDR (S_AADDR),
.TARGET_HOT (target_mi_hot),
.TARGET_ENC (target_mi_enc),
.MATCH (match),
.REGION (target_region)
);
end else begin : gen_no_addr_decoder
assign target_mi_hot = 1;
assign target_mi_enc = 0;
assign match = 1'b1;
assign target_region = 4'b0000;
end
endgenerate
assign target_secure = |(target_mi_hot & P_M_SECURE_MASK);
assign target_axilite = |(target_mi_hot & P_M_AXILITE);
assign any_error = C_RANGE_CHECK && (m_aerror_i != 0); // DECERR if error-detection enabled and any error condition.
assign m_aerror_i[0] = ~match; // Invalid target address
assign m_aerror_i[1] = target_secure && S_APROT[P_NONSECURE_BIT]; // TrustZone violation
assign m_aerror_i[2] = target_axilite && ((S_ALEN != 0) ||
(S_ASIZE[1:0] == 2'b11) || (S_ASIZE[2] == 1'b1)); // AxiLite access violation
assign m_aerror_i[7:3] = 5'b00000; // Reserved
assign M_ATARGET_HOT = m_atarget_hot_i;
assign m_atarget_hot_i = (any_error ? {1'b1, {C_NUM_M{1'b0}}} : {1'b0, target_mi_hot});
assign m_atarget_enc_i = (any_error ? C_NUM_M : target_mi_enc);
assign M_AVALID = m_avalid_i;
assign m_avalid_i = S_AVALID;
assign M_AVALID_QUAL = m_avalid_qual_i;
assign S_AREADY = s_aready_i;
assign s_aready_i = M_AREADY;
assign M_AERROR = m_aerror_i;
assign M_ATARGET_ENC = m_atarget_enc_i;
assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : 4'b0000;
// assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : S_AREGION;
assign M_AREGION = m_aregion_i;
assign M_AID = S_AID;
assign M_AADDR = S_AADDR;
assign M_ALEN = S_ALEN;
assign M_ASIZE = S_ASIZE;
assign M_ALOCK = S_ALOCK;
assign M_APROT = S_APROT;
assign M_AMESG = S_AMESG;
assign S_RVALID = s_rvalid_i;
assign M_RREADY = m_rready_i;
assign s_rid_i = si_rmux_mesg[0+:C_ID_WIDTH];
assign S_RMESG = si_rmux_mesg[C_ID_WIDTH+:C_RMESG_WIDTH];
assign s_rlast_i = si_rmux_mesg[C_ID_WIDTH+C_RMESG_WIDTH+:1];
assign S_RID = s_rid_i;
assign S_RLAST = s_rlast_i;
assign m_rvalid_qual = M_RVALID & M_RTARGET;
assign m_rready_i = m_rready_arb & M_RTARGET;
generate
for (gen_mi=0; gen_mi<(C_NUM_M+1); gen_mi=gen_mi+1) begin : gen_rmesg_mi
// Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order.
assign mi_rmux_mesg[gen_mi*P_RMUX_MESG_WIDTH+:P_RMUX_MESG_WIDTH] = {
M_RLAST[gen_mi],
M_RMESG[gen_mi*C_RMESG_WIDTH+:C_RMESG_WIDTH],
M_RID[gen_mi*C_ID_WIDTH+:C_ID_WIDTH]
};
end // gen_rmesg_mi
if (C_ACCEPTANCE == 1) begin : gen_single_issue
wire cmd_push;
wire cmd_pop;
reg [(C_NUM_M+1)-1:0] active_target_hot;
reg [P_NUM_M_DE_LOG-1:0] active_target_enc;
reg accept_cnt;
reg [8-1:0] debug_r_beat_cnt_i;
wire [8-1:0] debug_r_trans_seq_i;
assign cmd_push = M_AREADY;
assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst
assign m_avalid_qual_i = ~accept_cnt | cmd_pop; // Ready for arbitration if no outstanding transaction or transaction being completed
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 1'b0;
active_target_enc <= 0;
active_target_hot <= 0;
end else begin
if (cmd_push) begin
active_target_enc <= m_atarget_enc_i;
active_target_hot <= m_atarget_hot_i;
accept_cnt <= 1'b1;
end else if (cmd_pop) begin
accept_cnt <= 1'b0;
end
end
end // Clocked process
assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};
assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_single_issue
(
.S (active_target_enc),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
if (C_DEBUG) begin : gen_debug_r_single_issue
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i && S_RREADY) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i <= 0;
end else begin
debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
end
end
end else begin
debug_r_beat_cnt_i <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_7_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_single_issue
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push),
.S_READY (),
.M_MESG (debug_r_trans_seq_i),
.M_VALID (),
.M_READY (cmd_pop)
);
end // gen_debug_r
end else if (C_SINGLE_THREAD || (P_NUM_ID_VAL==1)) begin : gen_single_thread
wire s_avalid_en;
wire cmd_push;
wire cmd_pop;
reg [C_ID_WIDTH-1:0] active_id;
reg [(C_NUM_M+1)-1:0] active_target_hot;
reg [P_NUM_M_DE_LOG-1:0] active_target_enc;
reg [4-1:0] active_region;
reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt;
reg [8-1:0] debug_r_beat_cnt_i;
wire [8-1:0] debug_r_trans_seq_i;
wire accept_limit ;
// Implement single-region-per-ID cyclic dependency avoidance method.
assign s_avalid_en = // This transaction is qualified to request arbitration if ...
(accept_cnt == 0) || // Either there are no outstanding transactions, or ...
(((P_NUM_ID_VAL==1) || (S_AID[P_THREAD_ID_WIDTH_M1-1:0] == active_id[P_THREAD_ID_WIDTH_M1-1:0])) && // the current transaction ID matches the previous, and ...
(active_target_enc == m_atarget_enc_i) && // all outstanding transactions are to the same target MI ...
(active_region == m_aregion_i)); // and to the same REGION.
assign cmd_push = M_AREADY;
assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst
assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~cmd_pop; // Allow next push if a transaction is currently being completed
assign m_avalid_qual_i = s_avalid_en & ~accept_limit;
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 0;
active_id <= 0;
active_target_enc <= 0;
active_target_hot <= 0;
active_region <= 0;
end else begin
if (cmd_push) begin
active_id <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];
active_target_enc <= m_atarget_enc_i;
active_target_hot <= m_atarget_hot_i;
active_region <= m_aregion_i;
if (~cmd_pop) begin
accept_cnt <= accept_cnt + 1;
end
end else begin
if (cmd_pop & (accept_cnt != 0)) begin
accept_cnt <= accept_cnt - 1;
end
end
end
end // Clocked process
assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};
assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_single_thread
(
.S (active_target_enc),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
if (C_DEBUG) begin : gen_debug_r_single_thread
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i && S_RREADY) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i <= 0;
end else begin
debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
end
end
end else begin
debug_r_beat_cnt_i <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_7_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_single_thread
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push),
.S_READY (),
.M_MESG (debug_r_trans_seq_i),
.M_VALID (),
.M_READY (cmd_pop)
);
end // gen_debug_r
end else begin : gen_multi_thread
wire [(P_NUM_M_DE_LOG)-1:0] resp_select;
reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt;
wire [P_NUM_THREADS-1:0] s_avalid_en;
wire [P_NUM_THREADS-1:0] thread_valid;
wire [P_NUM_THREADS-1:0] aid_match;
wire [P_NUM_THREADS-1:0] rid_match;
wire [P_NUM_THREADS-1:0] cmd_push;
wire [P_NUM_THREADS-1:0] cmd_pop;
wire [P_NUM_THREADS:0] accum_push;
reg [P_NUM_THREADS*C_ID_WIDTH-1:0] active_id;
reg [P_NUM_THREADS*8-1:0] active_target;
reg [P_NUM_THREADS*8-1:0] active_region;
reg [P_NUM_THREADS*8-1:0] active_cnt;
reg [P_NUM_THREADS*8-1:0] debug_r_beat_cnt_i;
wire [P_NUM_THREADS*8-1:0] debug_r_trans_seq_i;
wire any_aid_match;
wire any_rid_match;
wire accept_limit;
wire any_push;
wire any_pop;
axi_crossbar_v2_1_9_arbiter_resp # // Multi-thread response arbiter
(
.C_FAMILY (C_FAMILY),
.C_NUM_S (C_NUM_M+1),
.C_NUM_S_LOG (P_NUM_M_DE_LOG),
.C_GRANT_ENC (1),
.C_GRANT_HOT (0)
)
arbiter_resp_inst
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_VALID (m_rvalid_qual),
.S_READY (m_rready_arb),
.M_GRANT_HOT (),
.M_GRANT_ENC (resp_select),
.M_VALID (s_rvalid_i),
.M_READY (S_RREADY)
);
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_multi_thread
(
.S (resp_select),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
assign any_push = M_AREADY;
assign any_pop = s_rvalid_i & S_RREADY & s_rlast_i;
assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~any_pop; // Allow next push if a transaction is currently being completed
assign m_avalid_qual_i = (&s_avalid_en) & ~accept_limit; // The current request is qualified for arbitration when it is qualified against all outstanding transaction threads.
assign any_aid_match = |aid_match;
assign any_rid_match = |rid_match;
assign accum_push[0] = 1'b0;
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 0;
end else begin
if (any_push & ~any_pop) begin
accept_cnt <= accept_cnt + 1;
end else if (any_pop & ~any_push & (accept_cnt != 0)) begin
accept_cnt <= accept_cnt - 1;
end
end
end // Clocked process
for (gen_thread=0; gen_thread<P_NUM_THREADS; gen_thread=gen_thread+1) begin : gen_thread_loop
assign thread_valid[gen_thread] = (active_cnt[gen_thread*8 +: C_ACCEPTANCE_LOG+1] != 0);
assign aid_match[gen_thread] = // The currect thread is active for the requested transaction if
thread_valid[gen_thread] && // this thread slot is not vacant, and
((S_AID[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]); // the requested ID matches the active ID for this thread.
assign s_avalid_en[gen_thread] = // The current request is qualified against this thread slot if
(~aid_match[gen_thread]) || // This thread slot is not active for the requested ID, or
((m_atarget_enc_i == active_target[gen_thread*8+:P_NUM_M_DE_LOG]) && // this outstanding transaction was to the same target and
(m_aregion_i == active_region[gen_thread*8+:4])); // to the same region.
// cmd_push points to the position of either the active thread for the requested ID or the lowest vacant thread slot.
assign accum_push[gen_thread+1] = accum_push[gen_thread] | ~thread_valid[gen_thread];
assign cmd_push[gen_thread] = any_push & (aid_match[gen_thread] | ((~any_aid_match) & ~thread_valid[gen_thread] & ~accum_push[gen_thread]));
// cmd_pop points to the position of the active thread that matches the current RID.
assign rid_match[gen_thread] = thread_valid[gen_thread] & ((s_rid_i[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]);
assign cmd_pop[gen_thread] = any_pop & rid_match[gen_thread];
always @(posedge ACLK) begin
if (ARESET) begin
active_id[gen_thread*C_ID_WIDTH+:C_ID_WIDTH] <= 0;
active_target[gen_thread*8+:8] <= 0;
active_region[gen_thread*8+:8] <= 0;
active_cnt[gen_thread*8+:8] <= 0;
end else begin
if (cmd_push[gen_thread]) begin
active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1] <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];
active_target[gen_thread*8+:P_NUM_M_DE_LOG] <= m_atarget_enc_i;
active_region[gen_thread*8+:4] <= m_aregion_i;
if (~cmd_pop[gen_thread]) begin
active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] + 1;
end
end else if (cmd_pop[gen_thread]) begin
active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] - 1;
end
end
end // Clocked process
if (C_DEBUG) begin : gen_debug_r_multi_thread
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i & S_RREADY & rid_match[gen_thread]) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end else begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= debug_r_beat_cnt_i[gen_thread*8+:8] + 1;
end
end
end else begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_7_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_multi_thread
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push[gen_thread]),
.S_READY (),
.M_MESG (debug_r_trans_seq_i[gen_thread*8+:8]),
.M_VALID (),
.M_READY (cmd_pop[gen_thread])
);
end // gen_debug_r_multi_thread
end // Next gen_thread_loop
end // thread control
endgenerate
endmodule
`default_nettype wire
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`ifdef USE_VPI_NOT_DPI
//We call it via $c so we can verify DPI isn't required - see bug572
`else
import "DPI-C" context function integer mon_check();
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
`ifdef VERILATOR
`systemc_header
extern "C" int mon_check();
`verilog
`endif
input clk;
reg onebit /*verilator public_flat_rw @(posedge clk) */;
reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */;
reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */;
reg [61:0] quads[3:2] /*verilator public_flat_rw @(posedge clk) */;
reg [31:0] count /*verilator public_flat_rd */;
reg [31:0] half_count /*verilator public_flat_rd */;
reg [7:0] text_byte /*verilator public_flat_rw @(posedge clk) */;
reg [15:0] text_half /*verilator public_flat_rw @(posedge clk) */;
reg [31:0] text_word /*verilator public_flat_rw @(posedge clk) */;
reg [63:0] text_long /*verilator public_flat_rw @(posedge clk) */;
reg [511:0] text /*verilator public_flat_rw @(posedge clk) */;
integer status;
sub sub();
// Test loop
initial begin
count = 0;
onebit = 1'b0;
fourthreetwoone[3] = 0; // stop icarus optimizing away
text_byte = "B";
text_half = "Hf";
text_word = "Word";
text_long = "Long64b";
text = "Verilog Test module";
`ifdef VERILATOR
status = $c32("mon_check()");
`endif
`ifdef iverilog
status = $mon_check();
`endif
`ifndef USE_VPI_NOT_DPI
status = mon_check();
`endif
if (status!=0) begin
$write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status);
$stop;
end
$write("%%Info: Checking results\n");
if (onebit != 1'b1) $stop;
if (quads[2] != 62'h12819213_abd31a1c) $stop;
if (quads[3] != 62'h1c77bb9b_3784ea09) $stop;
if (text_byte != "A") $stop;
if (text_half != "T2") $stop;
if (text_word != "Tree") $stop;
if (text_long != "44Four44") $stop;
if (text != "lorem ipsum") $stop;
end
always @(posedge clk) begin
count <= count + 2;
if (count[1])
half_count <= half_count + 2;
if (count == 1000) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
genvar i;
generate
for (i=1; i<=128; i=i+1) begin : arr
arr #(.LENGTH(i)) arr();
end endgenerate
endmodule : t
module sub;
reg subsig1 /*verilator public_flat_rd*/;
reg subsig2 /*verilator public_flat_rd*/;
`ifdef iverilog
// stop icarus optimizing signals away
wire redundant = subsig1 | subsig2;
`endif
endmodule : sub
module arr;
parameter LENGTH = 1;
reg [LENGTH-1:0] sig /*verilator public_flat_rw*/;
reg [LENGTH-1:0] rfr /*verilator public_flat_rw*/;
reg check /*verilator public_flat_rw*/;
reg verbose /*verilator public_flat_rw*/;
initial begin
sig = {LENGTH{1'b0}};
rfr = {LENGTH{1'b0}};
end
always @(posedge check) begin
if (verbose) $display("%m : %x %x", sig, rfr);
if (check && sig != rfr) $stop;
check <= 0;
end
endmodule : arr
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311A_BLACKBOX_V
`define SKY130_FD_SC_LS__O311A_BLACKBOX_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o311a (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311A_BLACKBOX_V
|
`default_nettype none
`timescale 1ns / 1ps
`include "asserts.vh"
module ipa_tb();
reg [11:0] story_to;
reg fault_to;
reg clk_i, reset_i, cyc_i;
reg txd_i, txc_i;
wire ack_o;
wire [15:0] dat_o;
always begin
#5 clk_i <= ~clk_i;
end
`STANDARD_FAULT
`DEFASSERT0(ack, o)
`DEFASSERT(dat, 15, o)
ipa i(
.clk_i(clk_i),
.reset_i(reset_i),
.cyc_i(cyc_i),
.ack_o(ack_o),
.dat_o(dat_o),
.txd_i(txd_i),
.txc_i(txc_i)
);
task send_byte;
input [7:0] b;
begin
txd_i <= 0; txc_i <= 1;
wait(~clk_i); wait(clk_i); #1;
txc_i <= 0;
wait(~clk_i); wait(clk_i); #1;
txd_i <= b[0]; txc_i <= 1;
wait(~clk_i); wait(clk_i); #1;
txc_i <= 0;
wait(~clk_i); wait(clk_i); #1;
txd_i <= b[1]; txc_i <= 1;
wait(~clk_i); wait(clk_i); #1;
txc_i <= 0;
wait(~clk_i); wait(clk_i); #1;
txd_i <= b[2]; txc_i <= 1;
wait(~clk_i); wait(clk_i); #1;
txc_i <= 0;
wait(~clk_i); wait(clk_i); #1;
txd_i <= b[3]; txc_i <= 1;
wait(~clk_i); wait(clk_i); #1;
txc_i <= 0;
wait(~clk_i); wait(clk_i); #1;
txd_i <= b[4]; txc_i <= 1;
wait(~clk_i); wait(clk_i); #1;
txc_i <= 0;
wait(~clk_i); wait(clk_i); #1;
txd_i <= b[5]; txc_i <= 1;
wait(~clk_i); wait(clk_i); #1;
txc_i <= 0;
wait(~clk_i); wait(clk_i); #1;
txd_i <= b[6]; txc_i <= 1;
wait(~clk_i); wait(clk_i); #1;
txc_i <= 0;
wait(~clk_i); wait(clk_i); #1;
txd_i <= b[7]; txc_i <= 1;
wait(~clk_i); wait(clk_i); #1;
txc_i <= 0;
wait(~clk_i); wait(clk_i); #1;
txd_i <= 1; txc_i <= 1;
wait(~clk_i); wait(clk_i); #1;
txc_i <= 0;
wait(~clk_i); wait(clk_i); #1;
wait(~clk_i); wait(clk_i); #1; // Let ACK_O update
end
endtask
task reset_ipa;
begin
wait(~clk_i); wait(clk_i); #1;
reset_i <= 1;
wait(~clk_i); wait(clk_i); #1;
reset_i <= 0;
end
endtask
initial begin
$dumpfile("ipa.vcd");
$dumpvars;
{cyc_i, fault_to, txc_i, clk_i, reset_i} <= 0;
txd_i <= 1;
// Given an IPA that is NOT currently waiting for data,
// the receipt of data should not alter the front-side bus.
story_to <= 12'h000;
reset_ipa;
send_byte(0);
assert_ack(0);
assert_dat(0);
send_byte(0);
assert_ack(0);
assert_dat(0);
send_byte(0);
assert_ack(0);
assert_dat(0);
send_byte(0);
assert_ack(0);
assert_dat(0);
// Given an IPA that is currently addressed,
// the receipt of two bytes should cause ACK to assert.
story_to <= 12'h010;
reset_ipa;
cyc_i <= 1;
send_byte(8'h11);
assert_ack(0);
assert_dat(0);
send_byte(8'h22);
assert_ack(1);
assert_dat(16'h2211);
send_byte(8'h33);
assert_ack(0);
assert_dat(0);
send_byte(8'h44);
assert_ack(1);
assert_dat(16'h4433);
wait(~clk_i); wait(clk_i);
cyc_i <= 0;
#100;
$display("@I Done.");
$stop;
end
endmodule
|
//------------------------------------------------------------------------
//--
//-- Filename : xlconcat.v
//--
//-- Date : 06/05/12
//-
//- Description : Verilog description of a concat block. This
//- block does not use a core.
//-
//-----------------------------------------------------------------------
`timescale 1ps/1ps
module xlconcat_v2_1_1_xlconcat (In0, In1, In2, In3, In4, In5, In6, In7, In8, In9, In10, In11, In12, In13, In14, In15, In16, In17, In18, In19, In20, In21, In22, In23, In24, In25, In26, In27, In28, In29, In30, In31, dout);
parameter IN0_WIDTH = 1;
input [IN0_WIDTH -1:0] In0;
parameter IN1_WIDTH = 1;
input [IN1_WIDTH -1:0] In1;
parameter IN2_WIDTH = 1;
input [IN2_WIDTH -1:0] In2;
parameter IN3_WIDTH = 1;
input [IN3_WIDTH -1:0] In3;
parameter IN4_WIDTH = 1;
input [IN4_WIDTH -1:0] In4;
parameter IN5_WIDTH = 1;
input [IN5_WIDTH -1:0] In5;
parameter IN6_WIDTH = 1;
input [IN6_WIDTH -1:0] In6;
parameter IN7_WIDTH = 1;
input [IN7_WIDTH -1:0] In7;
parameter IN8_WIDTH = 1;
input [IN8_WIDTH -1:0] In8;
parameter IN9_WIDTH = 1;
input [IN9_WIDTH -1:0] In9;
parameter IN10_WIDTH = 1;
input [IN10_WIDTH -1:0] In10;
parameter IN11_WIDTH = 1;
input [IN11_WIDTH -1:0] In11;
parameter IN12_WIDTH = 1;
input [IN12_WIDTH -1:0] In12;
parameter IN13_WIDTH = 1;
input [IN13_WIDTH -1:0] In13;
parameter IN14_WIDTH = 1;
input [IN14_WIDTH -1:0] In14;
parameter IN15_WIDTH = 1;
input [IN15_WIDTH -1:0] In15;
parameter IN16_WIDTH = 1;
input [IN16_WIDTH -1:0] In16;
parameter IN17_WIDTH = 1;
input [IN17_WIDTH -1:0] In17;
parameter IN18_WIDTH = 1;
input [IN18_WIDTH -1:0] In18;
parameter IN19_WIDTH = 1;
input [IN19_WIDTH -1:0] In19;
parameter IN20_WIDTH = 1;
input [IN20_WIDTH -1:0] In20;
parameter IN21_WIDTH = 1;
input [IN21_WIDTH -1:0] In21;
parameter IN22_WIDTH = 1;
input [IN22_WIDTH -1:0] In22;
parameter IN23_WIDTH = 1;
input [IN23_WIDTH -1:0] In23;
parameter IN24_WIDTH = 1;
input [IN24_WIDTH -1:0] In24;
parameter IN25_WIDTH = 1;
input [IN25_WIDTH -1:0] In25;
parameter IN26_WIDTH = 1;
input [IN26_WIDTH -1:0] In26;
parameter IN27_WIDTH = 1;
input [IN27_WIDTH -1:0] In27;
parameter IN28_WIDTH = 1;
input [IN28_WIDTH -1:0] In28;
parameter IN29_WIDTH = 1;
input [IN29_WIDTH -1:0] In29;
parameter IN30_WIDTH = 1;
input [IN30_WIDTH -1:0] In30;
parameter IN31_WIDTH = 1;
input [IN31_WIDTH -1:0] In31;
parameter dout_width = 2;
output [dout_width-1:0] dout;
parameter NUM_PORTS =2;
generate if (NUM_PORTS == 1)
begin : C_NUM_1
assign dout = In0;
end
endgenerate
generate if (NUM_PORTS == 2)
begin : C_NUM_2
assign dout = {In1,In0};
end
endgenerate
generate if (NUM_PORTS == 3)
begin:C_NUM_3
assign dout = {In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 4)
begin:C_NUM_4
assign dout = {In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 5)
begin:C_NUM_5
assign dout = {In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 6)
begin:C_NUM_6
assign dout = {In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 7)
begin:C_NUM_7
assign dout = {In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 8)
begin:C_NUM_8
assign dout = {In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 9)
begin:C_NUM_9
assign dout = {In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 10)
begin:C_NUM_10
assign dout = {In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 11)
begin:C_NUM_11
assign dout = {In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 12)
begin:C_NUM_12
assign dout = {In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 13)
begin:C_NUM_13
assign dout = {In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 14)
begin:C_NUM_14
assign dout = {In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 15)
begin:C_NUM_15
assign dout = {In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 16)
begin:C_NUM_16
assign dout = {In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 17)
begin:C_NUM_17
assign dout = {In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 18)
begin:C_NUM_18
assign dout = {In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 19)
begin:C_NUM_19
assign dout = {In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 20)
begin:C_NUM_20
assign dout = {In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 21)
begin:C_NUM_21
assign dout = {In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 22)
begin:C_NUM_22
assign dout = {In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 23)
begin:C_NUM_23
assign dout = {In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 24)
begin:C_NUM_24
assign dout = {In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 25)
begin:C_NUM_25
assign dout = {In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 26)
begin:C_NUM_26
assign dout = {In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 27)
begin:C_NUM_27
assign dout = {In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 28)
begin:C_NUM_28
assign dout = {In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 29)
begin:C_NUM_29
assign dout = {In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 30)
begin:C_NUM_30
assign dout = {In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 31)
begin:C_NUM_31
assign dout = {In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 32)
begin:C_NUM_32
assign dout = {In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYGATE4S50_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DLYGATE4S50_BEHAVIORAL_PP_V
/**
* dlygate4s50: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__dlygate4s50 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYGATE4S50_BEHAVIORAL_PP_V |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for udp_complete_64
*/
module test_udp_complete_64;
// Parameters
parameter ARP_CACHE_ADDR_WIDTH = 2;
parameter ARP_REQUEST_RETRY_COUNT = 4;
parameter ARP_REQUEST_RETRY_INTERVAL = 150;
parameter ARP_REQUEST_TIMEOUT = 400;
parameter UDP_CHECKSUM_GEN_ENABLE = 1;
parameter UDP_CHECKSUM_PAYLOAD_FIFO_DEPTH = 2048;
parameter UDP_CHECKSUM_HEADER_FIFO_DEPTH = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_eth_hdr_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = 0;
reg [15:0] s_eth_type = 0;
reg [63:0] s_eth_payload_axis_tdata = 0;
reg [7:0] s_eth_payload_axis_tkeep = 0;
reg s_eth_payload_axis_tvalid = 0;
reg s_eth_payload_axis_tlast = 0;
reg s_eth_payload_axis_tuser = 0;
reg arp_response_valid = 0;
reg arp_response_error = 0;
reg [47:0] arp_response_mac = 0;
reg s_ip_hdr_valid = 0;
reg [5:0] s_ip_dscp = 0;
reg [1:0] s_ip_ecn = 0;
reg [15:0] s_ip_length = 0;
reg [7:0] s_ip_ttl = 0;
reg [7:0] s_ip_protocol = 0;
reg [31:0] s_ip_source_ip = 0;
reg [31:0] s_ip_dest_ip = 0;
reg [63:0] s_ip_payload_axis_tdata = 0;
reg [7:0] s_ip_payload_axis_tkeep = 0;
reg s_ip_payload_axis_tvalid = 0;
reg s_ip_payload_axis_tlast = 0;
reg s_ip_payload_axis_tuser = 0;
reg s_udp_hdr_valid = 0;
reg [5:0] s_udp_ip_dscp = 0;
reg [1:0] s_udp_ip_ecn = 0;
reg [7:0] s_udp_ip_ttl = 0;
reg [31:0] s_udp_ip_source_ip = 0;
reg [31:0] s_udp_ip_dest_ip = 0;
reg [15:0] s_udp_source_port = 0;
reg [15:0] s_udp_dest_port = 0;
reg [15:0] s_udp_length = 0;
reg [15:0] s_udp_checksum = 0;
reg [63:0] s_udp_payload_axis_tdata = 0;
reg [7:0] s_udp_payload_axis_tkeep = 0;
reg s_udp_payload_axis_tvalid = 0;
reg s_udp_payload_axis_tlast = 0;
reg s_udp_payload_axis_tuser = 0;
reg m_eth_hdr_ready = 0;
reg m_eth_payload_axis_tready = 0;
reg m_ip_hdr_ready = 0;
reg m_ip_payload_axis_tready = 0;
reg m_udp_hdr_ready = 0;
reg m_udp_payload_axis_tready = 0;
reg [47:0] local_mac = 0;
reg [31:0] local_ip = 0;
reg [31:0] gateway_ip = 0;
reg [31:0] subnet_mask = 0;
reg clear_arp_cache = 0;
// Outputs
wire s_eth_hdr_ready;
wire s_eth_payload_axis_tready;
wire s_ip_hdr_ready;
wire s_ip_payload_axis_tready;
wire s_udp_hdr_ready;
wire s_udp_payload_axis_tready;
wire m_eth_hdr_valid;
wire [47:0] m_eth_dest_mac;
wire [47:0] m_eth_src_mac;
wire [15:0] m_eth_type;
wire [63:0] m_eth_payload_axis_tdata;
wire [7:0] m_eth_payload_axis_tkeep;
wire m_eth_payload_axis_tvalid;
wire m_eth_payload_axis_tlast;
wire m_eth_payload_axis_tuser;
wire arp_request_valid;
wire [31:0] arp_request_ip;
wire m_ip_hdr_valid;
wire [47:0] m_ip_eth_dest_mac;
wire [47:0] m_ip_eth_src_mac;
wire [15:0] m_ip_eth_type;
wire [3:0] m_ip_version;
wire [3:0] m_ip_ihl;
wire [5:0] m_ip_dscp;
wire [1:0] m_ip_ecn;
wire [15:0] m_ip_length;
wire [15:0] m_ip_identification;
wire [2:0] m_ip_flags;
wire [12:0] m_ip_fragment_offset;
wire [7:0] m_ip_ttl;
wire [7:0] m_ip_protocol;
wire [15:0] m_ip_header_checksum;
wire [31:0] m_ip_source_ip;
wire [31:0] m_ip_dest_ip;
wire [63:0] m_ip_payload_axis_tdata;
wire [7:0] m_ip_payload_axis_tkeep;
wire m_ip_payload_axis_tvalid;
wire m_ip_payload_axis_tlast;
wire m_ip_payload_axis_tuser;
wire m_udp_hdr_valid;
wire [47:0] m_udp_eth_dest_mac;
wire [47:0] m_udp_eth_src_mac;
wire [15:0] m_udp_eth_type;
wire [3:0] m_udp_ip_version;
wire [3:0] m_udp_ip_ihl;
wire [5:0] m_udp_ip_dscp;
wire [1:0] m_udp_ip_ecn;
wire [15:0] m_udp_ip_length;
wire [15:0] m_udp_ip_identification;
wire [2:0] m_udp_ip_flags;
wire [12:0] m_udp_ip_fragment_offset;
wire [7:0] m_udp_ip_ttl;
wire [7:0] m_udp_ip_protocol;
wire [15:0] m_udp_ip_header_checksum;
wire [31:0] m_udp_ip_source_ip;
wire [31:0] m_udp_ip_dest_ip;
wire [15:0] m_udp_source_port;
wire [15:0] m_udp_dest_port;
wire [15:0] m_udp_length;
wire [15:0] m_udp_checksum;
wire [63:0] m_udp_payload_axis_tdata;
wire [7:0] m_udp_payload_axis_tkeep;
wire m_udp_payload_axis_tvalid;
wire m_udp_payload_axis_tlast;
wire m_udp_payload_axis_tuser;
wire ip_rx_busy;
wire ip_tx_busy;
wire udp_rx_busy;
wire udp_tx_busy;
wire ip_rx_error_header_early_termination;
wire ip_rx_error_payload_early_termination;
wire ip_rx_error_invalid_header;
wire ip_rx_error_invalid_checksum;
wire ip_tx_error_payload_early_termination;
wire ip_tx_error_arp_failed;
wire udp_rx_error_header_early_termination;
wire udp_rx_error_payload_early_termination;
wire udp_tx_error_payload_early_termination;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_eth_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_eth_payload_axis_tdata,
s_eth_payload_axis_tkeep,
s_eth_payload_axis_tvalid,
s_eth_payload_axis_tlast,
s_eth_payload_axis_tuser,
s_ip_hdr_valid,
s_ip_dscp,
s_ip_ecn,
s_ip_length,
s_ip_ttl,
s_ip_protocol,
s_ip_source_ip,
s_ip_dest_ip,
s_ip_payload_axis_tdata,
s_ip_payload_axis_tkeep,
s_ip_payload_axis_tvalid,
s_ip_payload_axis_tlast,
s_ip_payload_axis_tuser,
s_udp_hdr_valid,
s_udp_ip_dscp,
s_udp_ip_ecn,
s_udp_ip_ttl,
s_udp_ip_source_ip,
s_udp_ip_dest_ip,
s_udp_source_port,
s_udp_dest_port,
s_udp_length,
s_udp_checksum,
s_udp_payload_axis_tdata,
s_udp_payload_axis_tkeep,
s_udp_payload_axis_tvalid,
s_udp_payload_axis_tlast,
s_udp_payload_axis_tuser,
m_eth_hdr_ready,
m_eth_payload_axis_tready,
m_ip_hdr_ready,
m_ip_payload_axis_tready,
m_udp_hdr_ready,
m_udp_payload_axis_tready,
local_mac,
local_ip,
gateway_ip,
subnet_mask,
clear_arp_cache
);
$to_myhdl(
s_eth_hdr_ready,
s_eth_payload_axis_tready,
s_ip_hdr_ready,
s_ip_payload_axis_tready,
s_udp_hdr_ready,
s_udp_payload_axis_tready,
m_eth_hdr_valid,
m_eth_dest_mac,
m_eth_src_mac,
m_eth_type,
m_eth_payload_axis_tdata,
m_eth_payload_axis_tkeep,
m_eth_payload_axis_tvalid,
m_eth_payload_axis_tlast,
m_eth_payload_axis_tuser,
m_ip_hdr_valid,
m_ip_eth_dest_mac,
m_ip_eth_src_mac,
m_ip_eth_type,
m_ip_version,
m_ip_ihl,
m_ip_dscp,
m_ip_ecn,
m_ip_length,
m_ip_identification,
m_ip_flags,
m_ip_fragment_offset,
m_ip_ttl,
m_ip_protocol,
m_ip_header_checksum,
m_ip_source_ip,
m_ip_dest_ip,
m_ip_payload_axis_tdata,
m_ip_payload_axis_tkeep,
m_ip_payload_axis_tvalid,
m_ip_payload_axis_tlast,
m_ip_payload_axis_tuser,
m_udp_hdr_valid,
m_udp_eth_dest_mac,
m_udp_eth_src_mac,
m_udp_eth_type,
m_udp_ip_version,
m_udp_ip_ihl,
m_udp_ip_dscp,
m_udp_ip_ecn,
m_udp_ip_length,
m_udp_ip_identification,
m_udp_ip_flags,
m_udp_ip_fragment_offset,
m_udp_ip_ttl,
m_udp_ip_protocol,
m_udp_ip_header_checksum,
m_udp_ip_source_ip,
m_udp_ip_dest_ip,
m_udp_source_port,
m_udp_dest_port,
m_udp_length,
m_udp_checksum,
m_udp_payload_axis_tdata,
m_udp_payload_axis_tkeep,
m_udp_payload_axis_tvalid,
m_udp_payload_axis_tlast,
m_udp_payload_axis_tuser,
ip_rx_busy,
ip_tx_busy,
udp_rx_busy,
udp_tx_busy,
ip_rx_error_header_early_termination,
ip_rx_error_payload_early_termination,
ip_rx_error_invalid_header,
ip_rx_error_invalid_checksum,
ip_tx_error_payload_early_termination,
ip_tx_error_arp_failed,
udp_rx_error_header_early_termination,
udp_rx_error_payload_early_termination,
udp_tx_error_payload_early_termination
);
// dump file
$dumpfile("test_udp_complete_64.lxt");
$dumpvars(0, test_udp_complete_64);
end
udp_complete_64 #(
.ARP_CACHE_ADDR_WIDTH(ARP_CACHE_ADDR_WIDTH),
.ARP_REQUEST_RETRY_COUNT(ARP_REQUEST_RETRY_COUNT),
.ARP_REQUEST_RETRY_INTERVAL(ARP_REQUEST_RETRY_INTERVAL),
.ARP_REQUEST_TIMEOUT(ARP_REQUEST_TIMEOUT),
.UDP_CHECKSUM_GEN_ENABLE(UDP_CHECKSUM_GEN_ENABLE),
.UDP_CHECKSUM_PAYLOAD_FIFO_DEPTH(UDP_CHECKSUM_PAYLOAD_FIFO_DEPTH),
.UDP_CHECKSUM_HEADER_FIFO_DEPTH(UDP_CHECKSUM_HEADER_FIFO_DEPTH)
)
UUT (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(s_ip_hdr_valid),
.s_ip_hdr_ready(s_ip_hdr_ready),
.s_ip_dscp(s_ip_dscp),
.s_ip_ecn(s_ip_ecn),
.s_ip_length(s_ip_length),
.s_ip_ttl(s_ip_ttl),
.s_ip_protocol(s_ip_protocol),
.s_ip_source_ip(s_ip_source_ip),
.s_ip_dest_ip(s_ip_dest_ip),
.s_ip_payload_axis_tdata(s_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(s_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(s_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(s_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(s_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(s_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(m_ip_hdr_valid),
.m_ip_hdr_ready(m_ip_hdr_ready),
.m_ip_eth_dest_mac(m_ip_eth_dest_mac),
.m_ip_eth_src_mac(m_ip_eth_src_mac),
.m_ip_eth_type(m_ip_eth_type),
.m_ip_version(m_ip_version),
.m_ip_ihl(m_ip_ihl),
.m_ip_dscp(m_ip_dscp),
.m_ip_ecn(m_ip_ecn),
.m_ip_length(m_ip_length),
.m_ip_identification(m_ip_identification),
.m_ip_flags(m_ip_flags),
.m_ip_fragment_offset(m_ip_fragment_offset),
.m_ip_ttl(m_ip_ttl),
.m_ip_protocol(m_ip_protocol),
.m_ip_header_checksum(m_ip_header_checksum),
.m_ip_source_ip(m_ip_source_ip),
.m_ip_dest_ip(m_ip_dest_ip),
.m_ip_payload_axis_tdata(m_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(m_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(m_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(m_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(m_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(m_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(s_udp_hdr_valid),
.s_udp_hdr_ready(s_udp_hdr_ready),
.s_udp_ip_dscp(s_udp_ip_dscp),
.s_udp_ip_ecn(s_udp_ip_ecn),
.s_udp_ip_ttl(s_udp_ip_ttl),
.s_udp_ip_source_ip(s_udp_ip_source_ip),
.s_udp_ip_dest_ip(s_udp_ip_dest_ip),
.s_udp_source_port(s_udp_source_port),
.s_udp_dest_port(s_udp_dest_port),
.s_udp_length(s_udp_length),
.s_udp_checksum(s_udp_checksum),
.s_udp_payload_axis_tdata(s_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(s_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(s_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(s_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(s_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(s_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(m_udp_hdr_valid),
.m_udp_hdr_ready(m_udp_hdr_ready),
.m_udp_eth_dest_mac(m_udp_eth_dest_mac),
.m_udp_eth_src_mac(m_udp_eth_src_mac),
.m_udp_eth_type(m_udp_eth_type),
.m_udp_ip_version(m_udp_ip_version),
.m_udp_ip_ihl(m_udp_ip_ihl),
.m_udp_ip_dscp(m_udp_ip_dscp),
.m_udp_ip_ecn(m_udp_ip_ecn),
.m_udp_ip_length(m_udp_ip_length),
.m_udp_ip_identification(m_udp_ip_identification),
.m_udp_ip_flags(m_udp_ip_flags),
.m_udp_ip_fragment_offset(m_udp_ip_fragment_offset),
.m_udp_ip_ttl(m_udp_ip_ttl),
.m_udp_ip_protocol(m_udp_ip_protocol),
.m_udp_ip_header_checksum(m_udp_ip_header_checksum),
.m_udp_ip_source_ip(m_udp_ip_source_ip),
.m_udp_ip_dest_ip(m_udp_ip_dest_ip),
.m_udp_source_port(m_udp_source_port),
.m_udp_dest_port(m_udp_dest_port),
.m_udp_length(m_udp_length),
.m_udp_checksum(m_udp_checksum),
.m_udp_payload_axis_tdata(m_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(m_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(m_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(m_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(m_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(m_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(ip_rx_busy),
.ip_tx_busy(ip_tx_busy),
.udp_rx_busy(udp_rx_busy),
.udp_tx_busy(udp_tx_busy),
.ip_rx_error_header_early_termination(ip_rx_error_header_early_termination),
.ip_rx_error_payload_early_termination(ip_rx_error_payload_early_termination),
.ip_rx_error_invalid_header(ip_rx_error_invalid_header),
.ip_rx_error_invalid_checksum(ip_rx_error_invalid_checksum),
.ip_tx_error_payload_early_termination(ip_tx_error_payload_early_termination),
.ip_tx_error_arp_failed(ip_tx_error_arp_failed),
.udp_rx_error_header_early_termination(udp_rx_error_header_early_termination),
.udp_rx_error_payload_early_termination(udp_rx_error_payload_early_termination),
.udp_tx_error_payload_early_termination(udp_tx_error_payload_early_termination),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(clear_arp_cache)
);
endmodule
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : DDR controller ECC Decoder
//
// File : alt_ddrx_decoder.v
//
// Abstract : Decode ECC information
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_ddrx_decoder #
( parameter
INPUT_DATA_WIDTH = 72,
OUTPUT_DATA_WIDTH = 64
)
(
ctl_clk,
input_data,
err_corrected,
err_detected,
err_fatal,
output_data
);
input ctl_clk;
input [INPUT_DATA_WIDTH - 1 : 0] input_data;
output [OUTPUT_DATA_WIDTH - 1 : 0] output_data;
output err_corrected;
output err_detected;
output err_fatal;
wire [OUTPUT_DATA_WIDTH - 1 : 0] output_data;
wire err_corrected;
wire err_detected;
wire err_fatal;
generate
if (INPUT_DATA_WIDTH == 40)
begin
// encoder only have 32/29 combination
alt_ddrx_decoder_40 decoder_40_inst
(
.clock (ctl_clk),
.data (input_data [INPUT_DATA_WIDTH - 2 : 0]),
.err_corrected (err_corrected),
.err_detected (err_detected),
.err_fatal (err_fatal),
.q (output_data)
);
end
else if (INPUT_DATA_WIDTH == 72)
begin
alt_ddrx_decoder_72 decoder_72_inst
(
.clock (ctl_clk),
.data (input_data),
.err_corrected (err_corrected),
.err_detected (err_detected),
.err_fatal (err_fatal),
.q (output_data)
);
end
endgenerate
endmodule
|
//-----------------------------------------------------------------------------
//-- Generacion de baudios
//-- Señal cuadrada, de periodo igual a la frecuencia de los baudios indicados
//-- El ancho del pulso positivo es de 1 ciclo de reloj
//--
//-- (c) BQ. August 2015. written by Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
`include "baudgen.vh"
//-- ENTRADAS:
//-- -clk: Senal de reloj del sistema (12 MHZ en la iceStick)
//-- -clk_ena: Habilitacion.
//-- 1. funcionamiento normal. Emitiendo pulsos
//-- 0: Inicializado y parado. No se emiten pulsos
//
//-- SALIDAS:
//-- - clk_out. Señal de salida para lograr la velocidad en baudios indicada
//-- Anchura de 1 periodo de clk. SALIDA NO REGISTRADA
module baudgen(input wire clk,
input wire clk_ena,
output wire clk_out);
//-- Valor por defecto de la velocidad en baudios
parameter M = `B115200;
//-- Numero de bits para almacenar el divisor de baudios
localparam N = $clog2(M);
//-- Registro para implementar el contador modulo M
reg [N-1:0] divcounter = 0;
//-- Contador módulo M
always @(posedge clk)
if (clk_ena)
//-- Funcionamiento normal
divcounter <= (divcounter == M - 1) ? 0 : divcounter + 1;
else
//-- Contador "congelado" al valor maximo
divcounter <= M - 1;
//-- Sacar un pulso de anchura 1 ciclo de reloj si el generador
//-- esta habilitado (clk_ena == 1)
//-- en caso contrario se saca 0
assign clk_out = (divcounter == 0) ? clk_ena : 0;
endmodule
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012, Ameer M. Abdelhadi; [email protected]. All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// FreqPhaseSweeping.v: Dynamic clock freqyency/phase sweep testing //
// using Altera's DE-115 board with Cyclone IV //
// //
// Ameer M.S. Abdelhadi ([email protected]; [email protected]), Sept. 2012 //
////////////////////////////////////////////////////////////////////////////////////
module FreqPhaseSweeping (
// PORT declarations
input CLOCK_50, // 50MHz clock 1
output [8:0] LEDG , // green LED
output [17:0] LEDR , // red LED
input [3:0] KEY , // keys
input [17:0] SW , // switches
output [6:0] HEX0 , // 7-segments 0
output [6:0] HEX1 , // 7-segments 1
output [6:0] HEX2 , // 7-segments 2
output [6:0] HEX3 , // 7-segments 3
output [6:0] HEX4 , // 7-segments 4
output [6:0] HEX5 , // 7-segments 5
output [6:0] HEX6 , // 7-segments 6
output [6:0] HEX7 // 7-segments 7
);
// assign high-Z for unused output ports
assign {LEDG[8],LEDG[5],LEDG[3:0]} = { 4{1'bz}};
// assign SW to LEDR
assign LEDR[17:0] = SW[17:0];
// reset generators
wire rst ; rstgen #(20) rstgen_sys (CLOCK_50, 1'b0, rst ); // system reset generator
wire rstpll; rstgen #(17) rstgen_pll (CLOCK_50, 1'b0, rstpll); // pll reset (longer than system reset)
// instantiate PLL for 500MHz clock generation
wire clk_500 ;
wire [3:0] NC;
pll #( .MUL0(10 ), // clk0 parameters : multiply
.DIV0(1 ), // clk0 parameters : divide
.PHS0("-200" )) // clk0 parameters : phase shift (ps)
pll_inst ( .rst (rstpll ), // asynchronous reset
.clki(CLOCK_50 ), // pll input clock // 50MHz
.clko({NC,clk_500})); // pll output clocks // details above
// instantiate PLL for dynamic frequency/phase sweeping
wire clk_ref,clk_phs;
pll_dyn #(
.INIT_FRQ("2"), // initial frequency - MHz
.INIT_PHS("0") // initial clock phase shift - ps(clk_phs only)
)pll_dyn_inst (
.areset (rstpll ), // asynchronous reset
.clk_50 (CLOCK_50), // 50Mhz clock source
.phasestep (fkey[2] ), // shift phase one step forward
.freq (SW[8:0] ), // new frequeny value to be changed
.write_freq(fkey[3] ), // performe frequeny change
.clk_ref (clk_ref ), // reference output clock
.clk_phs (clk_phs ), // output clock with phase shifting
.busy (LEDG[7] ) // PLL busy, operation not done yet
);
// filtered keys
wire [3:0] fkey;
keyfilter keyfilter_02 (CLOCK_50,KEY[2],fkey[2]);
keyfilter keyfilter_03 (CLOCK_50,KEY[3],fkey[3]);
assign {LEDG[6],LEDG[4]} = {fkey[3],fkey[2]};
//phase meter
wire phs_sgn;
wire [11:0] phs_bcd;
phasemeter
phasemeter_inst ( .clk_500(clk_500), // sampling clock, 500Mhz
.clk_ref(clk_ref), // reference clock
.clk_phs(clk_phs), // phase-shifted clock, same frequency as reference clock
.phs_sgn(phs_sgn), // measured pahse shift / sign
.phs_bcd(phs_bcd)); // measured pahse shift / BCD {ones,tens,hundreds}
hex7seg hex7seg_00 (phs_bcd[3 :0 ],HEX0);
hex7seg hex7seg_01 (phs_bcd[7 :4 ],HEX1);
hex7seg hex7seg_02 (phs_bcd[11:8 ],HEX2);
assign HEX3 = {phs_sgn,6'b111111};
// frequency meter
wire [15:0] frq_bcd;
freqmeter
freqmeter_inst
( .clk_50 (CLOCK_50), // sampling clock, 50Mhz
.clk_ref(clk_phs ), // reference clock / frequency to measure
.frq_bcd(frq_bcd )); // measured frequency / BCD {thousands,hundreds,tens,ones}
hex7seg hex7seg_04 (frq_bcd[3 :0 ],HEX4);
hex7seg hex7seg_05 (frq_bcd[7 :4 ],HEX5);
hex7seg hex7seg_06 (frq_bcd[11:8 ],HEX6);
hex7seg hex7seg_07 (frq_bcd[15:12],HEX7);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
// $Id: mac_grp_regs.v 5374 2009-04-28 18:21:20Z g9coving $
//
// Module: mac_grp_hdr_regs.v
// Project: NF2.1
// Description: Demultiplexes, stores and serves register requests
//
// Note: only works when the ENABLE_HEADER option is set
//
// The "deltas" in this block are designed to store the updates that need to
// be applied to the registers in RAM. An example would be the number of
// packets that have arrived since the appropriate register in RAM was last
// updated. These deltas are applied periodically to RAM (in which case the
// deltas are reset).
//
//
// To add registers to this block the following steps should be followed:
// 1. Add the register to the appropriate defines file
// 2. Create a new delta register. The delta register should hold the
// changes since the previous update
// 3. Add code to update the delta register. This code should:
// i) reset the delta register on reset
// ii) set the delta register to the current input when the real
// register in RAM is being updated (this is so that the update is
// not lost)
// iii) set the delta register to its current value + the input during
// other cycles
// eg.
// if (reset)
// tx_pkt_stored_delta <= 'h0;
// else if (!new_reg_req && reg_cnt == `MAC_GRP_TX_QUEUE_NUM_PKTS_ENQUEUED)
// tx_pkt_stored_delta <= tx_pkt_stored;
// else
// tx_pkt_stored_delta <= tx_pkt_stored_delta + tx_pkt_stored;
//
// 4. Update the number of registers
// 5. Add a line to the case statement in the main state machine that
// applies the delta when reg_cnt is at the correct address.
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module eth_queue_regs
#( parameter CTRL_WIDTH = 8 )
( input mac_grp_reg_req,
input mac_grp_reg_rd_wr_L,
input [`MAC_GRP_REG_ADDR_WIDTH-1:0] mac_grp_reg_addr,
input [`CPCI_NF2_DATA_WIDTH-1:0] mac_grp_reg_wr_data,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] mac_grp_reg_rd_data,
output reg mac_grp_reg_ack,
// interface to mac controller
output reset_MAC,
output disable_crc_check,
output disable_crc_gen,
output enable_jumbo_rx,
output enable_jumbo_tx,
output rx_mac_en,
output tx_mac_en,
// interface to rx queue
input rx_pkt_good,
input rx_pkt_bad,
input rx_pkt_dropped,
input [11:0] rx_pkt_byte_cnt,
input [9:0] rx_pkt_word_cnt,
input rx_pkt_pulled,
output rx_queue_en,
// interface to tx queue
output tx_queue_en,
input tx_pkt_sent,
input tx_pkt_stored,
input [11:0] tx_pkt_byte_cnt,
input [9:0] tx_pkt_word_cnt,
input clk,
input reset
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// ------------- Internal parameters --------------
localparam NUM_REGS_USED = 13; /* don't forget to update this when adding regs */
localparam REG_FILE_ADDR_WIDTH = log2(NUM_REGS_USED);
//localparam REG_FILE_DEPTH = 2 ** REG_FILE_ADDR_WIDTH;
// Calculations for register sizes
// -------------------------------
//
// A cycle is 16 clocks max
// (13 reg + 1 reg read/write < 16)
//
// Min packet size: is 8 words
//
// Max packets per period = 2 (16 / 8)
// Word/byte count widths. Should support 2k packets -- i.e. up to 2048
// bytes per packet
//
// Note: don't need to increase the size to allow for multiple packets
// in a single cycle since we can't fit large packets in a single cycle
localparam WORD_CNT_WIDTH = 10; // 2^10 = 1024 [0..1023]
localparam BYTE_CNT_WIDTH = 12; // 2^12 = 4096 [0..4095]
localparam DELTA_WIDTH = BYTE_CNT_WIDTH + 1;
// States
localparam RESET = 0;
localparam NORMAL = 1;
// ------------- Wires/reg ------------------
// Register file and related registers
reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_file [0:NUM_REGS_USED-1];
reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_file_in;
wire [`CPCI_NF2_DATA_WIDTH-1:0] reg_file_out;
reg reg_file_wr;
reg [REG_FILE_ADDR_WIDTH-1:0] reg_file_addr;
reg [`CPCI_NF2_DATA_WIDTH-1:0] control_reg;
reg [`CPCI_NF2_DATA_WIDTH-1:0] control_reg_nxt;
wire [REG_FILE_ADDR_WIDTH-1:0] addr;
wire addr_good;
reg [3:0] reset_long;
reg mac_grp_reg_req_d1;
reg [REG_FILE_ADDR_WIDTH-1:0] reg_cnt;
reg [REG_FILE_ADDR_WIDTH-1:0] reg_cnt_nxt;
reg state;
reg state_nxt;
// Signals for temporarily storing the deltas for the registers
reg [WORD_CNT_WIDTH-1:0] rx_word_cnt_delta;
reg [BYTE_CNT_WIDTH-1:0] rx_byte_cnt_delta;
reg [WORD_CNT_WIDTH-1:0] tx_word_cnt_delta;
reg [BYTE_CNT_WIDTH-1:0] tx_byte_cnt_delta;
// Can't receive multiple packets less than a single cycle
reg rx_pkt_dropped_full_delta;
reg rx_pkt_dropped_bad_delta;
reg rx_pkt_stored_delta;
// Can't send multiple packets in less than a single cycle
reg tx_pkt_sent_delta;
reg [1:0] tx_pkt_stored_delta;
reg [1:0] rx_pkt_pulled_delta;
reg [2:0] tx_queue_delta;
reg [2:0] rx_queue_delta;
wire new_reg_req;
reg [DELTA_WIDTH-1:0] delta;
// -------------------------------------------
// Register file RAM
// -------------------------------------------
always @(posedge clk) begin
if (reg_file_wr)
reg_file[reg_file_addr] <= reg_file_in;
end
assign reg_file_out = reg_file[reg_file_addr];
// -------------- Logic --------------------
// Track the deltas
//
// These are committed later to the register file
always @(posedge clk) begin
if (reset)
rx_pkt_dropped_full_delta <= 'h0;
else if (!new_reg_req && reg_cnt == `MAC_GRP_RX_QUEUE_NUM_PKTS_DROPPED_FULL)
rx_pkt_dropped_full_delta <= rx_pkt_dropped;
else
rx_pkt_dropped_full_delta <= rx_pkt_dropped_full_delta || rx_pkt_dropped;
if (reset)
rx_pkt_dropped_bad_delta <= 'h0;
else if (!new_reg_req && reg_cnt == `MAC_GRP_RX_QUEUE_NUM_PKTS_DROPPED_BAD)
rx_pkt_dropped_bad_delta <= rx_pkt_bad;
else
rx_pkt_dropped_bad_delta <= rx_pkt_dropped_bad_delta || rx_pkt_bad;
if (reset)
rx_pkt_stored_delta <= 'h0;
else if (!new_reg_req && reg_cnt == `MAC_GRP_RX_QUEUE_NUM_PKTS_STORED )
rx_pkt_stored_delta <= rx_pkt_good;
else
rx_pkt_stored_delta <= rx_pkt_stored_delta || rx_pkt_good;
if (reset)
rx_word_cnt_delta <= 'h0;
else if (!new_reg_req && reg_cnt == `MAC_GRP_RX_QUEUE_NUM_WORDS_PUSHED)
rx_word_cnt_delta <= rx_pkt_pulled ? rx_pkt_word_cnt : 'h0;
else if (rx_pkt_pulled)
rx_word_cnt_delta <= rx_word_cnt_delta + rx_pkt_word_cnt;
if (reset)
rx_byte_cnt_delta <= 'h0;
else if (!new_reg_req && reg_cnt == `MAC_GRP_RX_QUEUE_NUM_BYTES_PUSHED)
rx_byte_cnt_delta <= rx_pkt_pulled ? rx_pkt_byte_cnt : 'h0;
else if (rx_pkt_pulled)
rx_byte_cnt_delta <= rx_byte_cnt_delta + rx_pkt_byte_cnt;
if (reset)
tx_pkt_sent_delta <= 'h0;
else if (!new_reg_req && reg_cnt == `MAC_GRP_TX_QUEUE_NUM_PKTS_SENT)
tx_pkt_sent_delta <= tx_pkt_sent;
else
tx_pkt_sent_delta <= tx_pkt_sent_delta || tx_pkt_sent;
if (reset)
tx_word_cnt_delta <= 'h0;
else if (!new_reg_req && reg_cnt == `MAC_GRP_TX_QUEUE_NUM_WORDS_PUSHED)
tx_word_cnt_delta <= tx_pkt_stored ? tx_pkt_word_cnt : 'h0;
else if (tx_pkt_stored)
tx_word_cnt_delta <= tx_word_cnt_delta + tx_pkt_word_cnt;
if (reset)
tx_byte_cnt_delta <= 'h0;
else if (!new_reg_req && reg_cnt == `MAC_GRP_TX_QUEUE_NUM_BYTES_PUSHED)
tx_byte_cnt_delta <= tx_pkt_stored ? tx_pkt_byte_cnt : 'h0;
else if (tx_pkt_stored)
tx_byte_cnt_delta <= tx_byte_cnt_delta + tx_pkt_byte_cnt;
if (reset)
tx_queue_delta <= 'h0;
else if (!new_reg_req && reg_cnt == `MAC_GRP_TX_QUEUE_NUM_PKTS_IN_QUEUE) begin
case({tx_pkt_sent, tx_pkt_stored})
2'b01 : tx_queue_delta <= 'h1;
2'b10 : tx_queue_delta <= - 'h1;
default : tx_queue_delta <= 'h0;
endcase
end
else begin
case({tx_pkt_sent, tx_pkt_stored})
2'b01 : tx_queue_delta <= tx_queue_delta + 'h1;
2'b10 : tx_queue_delta <= tx_queue_delta - 'h1;
default : tx_queue_delta <= tx_queue_delta;
endcase
end
if (reset)
tx_pkt_stored_delta <= 'h0;
else if (!new_reg_req && reg_cnt == `MAC_GRP_TX_QUEUE_NUM_PKTS_ENQUEUED)
tx_pkt_stored_delta <= tx_pkt_stored;
else
tx_pkt_stored_delta <= tx_pkt_stored_delta + tx_pkt_stored;
if (reset)
rx_pkt_pulled_delta <= 'h0;
else if (!new_reg_req && reg_cnt == `MAC_GRP_RX_QUEUE_NUM_PKTS_DEQUEUED)
rx_pkt_pulled_delta <= rx_pkt_pulled;
else
rx_pkt_pulled_delta <= rx_pkt_pulled_delta + rx_pkt_pulled;
if (reset)
rx_queue_delta <= 'h0;
else if (!new_reg_req && reg_cnt == `MAC_GRP_RX_QUEUE_NUM_PKTS_IN_QUEUE) begin
case ({rx_pkt_pulled, rx_pkt_good})
2'b01 : rx_queue_delta <= 'h1;
2'b10 : rx_queue_delta <= - 'h1;
default : rx_queue_delta <= 'h0;
endcase
end
else begin
case ({rx_pkt_pulled, rx_pkt_good})
2'b01 : rx_queue_delta <= rx_queue_delta + 'h1;
2'b10 : rx_queue_delta <= rx_queue_delta - 'h1;
default : rx_queue_delta <= rx_queue_delta;
endcase
end
end // always block for delta logic
/* extend the reset */
always @(posedge clk) begin
/*if (reset) reset_long <= 4'hf;
else reset_long <= {reset_long[2:0], 1'b0};*/
reset_long <= {reset_long[2:0], reset};
end
//assign control_reg = reg_file[`MAC_GRP_CONTROL];
assign rx_queue_en = !control_reg[`MAC_GRP_RX_QUEUE_DISABLE_BIT_NUM];
assign tx_queue_en = !control_reg[`MAC_GRP_TX_QUEUE_DISABLE_BIT_NUM];
assign reset_MAC = control_reg[`MAC_GRP_RESET_MAC_BIT_NUM] | (|reset_long);
assign enable_jumbo_tx = !control_reg[`MAC_GRP_MAC_DIS_JUMBO_TX_BIT_NUM];
assign enable_jumbo_rx = !control_reg[`MAC_GRP_MAC_DIS_JUMBO_RX_BIT_NUM];
assign disable_crc_check = control_reg[`MAC_GRP_MAC_DIS_CRC_CHECK_BIT_NUM];
assign disable_crc_gen = control_reg[`MAC_GRP_MAC_DIS_CRC_GEN_BIT_NUM];
assign rx_mac_en = !control_reg[`MAC_GRP_MAC_DISABLE_RX_BIT_NUM];
assign tx_mac_en = !control_reg[`MAC_GRP_MAC_DISABLE_TX_BIT_NUM];
assign addr = mac_grp_reg_addr[REG_FILE_ADDR_WIDTH-1:0];
assign addr_good = mac_grp_reg_addr[`MAC_GRP_REG_ADDR_WIDTH-1:REG_FILE_ADDR_WIDTH] == 'h0 &&
addr < NUM_REGS_USED;
assign new_reg_req = mac_grp_reg_req && !mac_grp_reg_req_d1;
always @*
begin
// Set the defaults
state_nxt = state;
control_reg_nxt = control_reg;
reg_file_in = reg_file_out;
reg_cnt_nxt = reg_cnt;
reg_file_addr = 'h0;
reg_file_wr = 1'b0;
delta = 1'b0;
if (reset) begin
state_nxt = RESET;
reg_cnt_nxt = 'h0;
reg_file_in = 'h0;
reg_file_addr = 'h0;
control_reg_nxt = 'h0;
end
else begin
case (state)
RESET : begin
if (reg_cnt == NUM_REGS_USED - 1) begin
state_nxt = NORMAL;
reg_cnt_nxt = 'h0;
end
else
reg_cnt_nxt = reg_cnt + 'h1;
reg_file_in = 'h0;
reg_file_wr = 1'b1;
reg_file_addr = reg_cnt;
end
NORMAL : begin
if(new_reg_req) begin // read request
reg_file_addr = addr;
reg_file_wr = addr_good && !mac_grp_reg_rd_wr_L;
reg_file_in = mac_grp_reg_wr_data;
if (addr == `MAC_GRP_CONTROL) begin
if (!mac_grp_reg_rd_wr_L)
control_reg_nxt = mac_grp_reg_wr_data;
end
// The following code does reset on read
//
//reg_file_wr = addr_good;
//if (addr == `MAC_GRP_CONTROL) begin
// if (mac_grp_reg_rd_wr_L)
// reg_file_in = reg_file_out;
// else begin
// reg_file_in = mac_grp_reg_wr_data;
// control_reg_nxt = mac_grp_reg_wr_data;
// end
//end
//else
// reg_file_in = 'h0;
end
else begin
reg_file_wr = 1'b1;
reg_file_addr = reg_cnt;
if (reg_cnt == NUM_REGS_USED - 1)
reg_cnt_nxt = 'h0;
else
reg_cnt_nxt = reg_cnt + 'h1;
case (reg_cnt)
`MAC_GRP_RX_QUEUE_NUM_PKTS_DROPPED_FULL : delta = rx_pkt_dropped_full_delta;
`MAC_GRP_RX_QUEUE_NUM_PKTS_DROPPED_BAD : delta = rx_pkt_dropped_bad_delta;
`MAC_GRP_RX_QUEUE_NUM_PKTS_STORED : delta = rx_pkt_stored_delta;
`MAC_GRP_RX_QUEUE_NUM_WORDS_PUSHED : delta = rx_word_cnt_delta;
`MAC_GRP_RX_QUEUE_NUM_BYTES_PUSHED : delta = rx_byte_cnt_delta;
`MAC_GRP_TX_QUEUE_NUM_PKTS_SENT : delta = tx_pkt_sent_delta;
`MAC_GRP_TX_QUEUE_NUM_WORDS_PUSHED : delta = tx_word_cnt_delta;
`MAC_GRP_TX_QUEUE_NUM_BYTES_PUSHED : delta = tx_byte_cnt_delta;
`MAC_GRP_CONTROL : delta = 0;
`MAC_GRP_TX_QUEUE_NUM_PKTS_IN_QUEUE : delta = {{(DELTA_WIDTH - 3){tx_queue_delta[2]}}, tx_queue_delta};
`MAC_GRP_TX_QUEUE_NUM_PKTS_ENQUEUED : delta = tx_pkt_stored_delta;
`MAC_GRP_RX_QUEUE_NUM_PKTS_DEQUEUED : delta = rx_pkt_pulled_delta;
`MAC_GRP_RX_QUEUE_NUM_PKTS_IN_QUEUE : delta = {{(DELTA_WIDTH - 3){rx_queue_delta[2]}}, rx_queue_delta};
default : delta = 0;
endcase // case (reg_cnt)
reg_file_in = reg_file_out + {{(`CPCI_NF2_DATA_WIDTH - DELTA_WIDTH){delta[DELTA_WIDTH-1]}}, delta};
end // if () else
end // NORMAL
endcase // case (state)
end
end
always @(posedge clk) begin
state <= state_nxt;
reg_cnt <= reg_cnt_nxt;
mac_grp_reg_req_d1 <= mac_grp_reg_req;
control_reg <= control_reg_nxt;
if( reset ) begin
mac_grp_reg_rd_data <= 0;
mac_grp_reg_ack <= 0;
end
else begin
// Register access logic
if(new_reg_req) begin // read request
if(addr_good) begin
mac_grp_reg_rd_data <= reg_file_out;
end
else begin
mac_grp_reg_rd_data <= 32'hdead_beef;
end
end
// requests complete after one cycle
mac_grp_reg_ack <= new_reg_req;
end // else: !if( reset )
end // always @ (posedge clk)
endmodule // mac_grp_hdr_regs
|
// $Id: vcr_la_routing_logic.v 1922 2010-04-15 03:47:49Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// lookahead routing logic for VC router
module vcr_la_routing_logic
(clk, reset, router_address, route_port, inc_rc, hop_route_info,
la_route_info);
`include "c_functions.v"
`include "c_constants.v"
// nuber of resource classes (e.g. minimal, adaptive)
parameter num_resource_classes = 2;
// number of routers in each dimension
parameter num_routers_per_dim = 4;
// width required to select individual router in a dimension
localparam dim_addr_width = clogb(num_routers_per_dim);
// number of dimensions in network
parameter num_dimensions = 2;
// width required to select individual router in network
localparam router_addr_width = num_dimensions * dim_addr_width;
// number of nodes per router (a.k.a. consentration factor)
parameter num_nodes_per_router = 1;
// width required to select individual node at current router
localparam node_addr_width = clogb(num_nodes_per_router);
// width of global addresses
localparam addr_width = router_addr_width + node_addr_width;
// connectivity within each dimension
parameter connectivity = `CONNECTIVITY_LINE;
// number of adjacent routers in each dimension
localparam num_neighbors_per_dim
= ((connectivity == `CONNECTIVITY_LINE) ||
(connectivity == `CONNECTIVITY_RING)) ?
2 :
(connectivity == `CONNECTIVITY_FULL) ?
(num_routers_per_dim - 1) :
-1;
// number of input and output ports on router
localparam num_ports
= num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
// width required to select an individual port
localparam port_idx_width = clogb(num_ports);
// width required for lookahead routing information
localparam la_route_info_width
= port_idx_width + ((num_resource_classes > 1) ? 1 : 0);
// select routing function type
parameter routing_type = `ROUTING_TYPE_DOR;
// select order of dimension traversal
parameter dim_order = `DIM_ORDER_ASCENDING;
// current resource class
parameter resource_class = 0;
// total number of bits required for storing routing information
localparam hop_route_info_width
= (resource_class == (num_resource_classes - 1)) ?
addr_width :
(resource_class == (num_resource_classes - 2)) ?
(router_addr_width + addr_width) :
(2 * router_addr_width);
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// current router's address
input [0:router_addr_width-1] router_address;
// port on which the packet will leave the current router
input [0:port_idx_width-1] route_port;
// will the resource class be incremented at the current router?
input inc_rc;
// routing data
input [0:hop_route_info_width-1] hop_route_info;
// lookahead routing information for next router
output [0:la_route_info_width-1] la_route_info;
wire [0:la_route_info_width-1] la_route_info;
// address of destination router for current resource class
wire [0:router_addr_width-1] dest_router_address;
// address of the downstream router
wire [0:router_addr_width-1] next_router_address;
wire [0:num_dimensions-1] dim_addr_match;
wire [0:num_ports-1] next_route_op;
generate
if(num_resource_classes > 1)
begin
wire next_inc_rc;
if(resource_class == (num_resource_classes - 1))
begin
assign dest_router_address
= hop_route_info[0:router_addr_width-1];
assign next_inc_rc = 1'b0;
end
else
begin
assign dest_router_address
= inc_rc ?
hop_route_info[router_addr_width:2*router_addr_width-1] :
hop_route_info[0:router_addr_width-1];
assign next_inc_rc
= (next_router_address == dest_router_address);
end
assign la_route_info[port_idx_width] = next_inc_rc;
end
else
assign dest_router_address = hop_route_info[0:router_addr_width-1];
case(routing_type)
`ROUTING_TYPE_DOR:
begin
genvar dim;
for(dim = 0; dim < num_dimensions; dim = dim + 1)
begin:dims
wire [0:dim_addr_width-1] dest_dim_addr;
assign dest_dim_addr
= dest_router_address[dim*dim_addr_width:
(dim+1)*dim_addr_width-1];
wire [0:dim_addr_width-1] curr_dim_addr;
assign curr_dim_addr
= router_address[dim*dim_addr_width:
(dim+1)*dim_addr_width-1];
wire [0:dim_addr_width-1] next_dim_addr;
assign dim_addr_match[dim] = (next_dim_addr == dest_dim_addr);
wire dim_sel;
case(dim_order)
`DIM_ORDER_ASCENDING:
begin
if(dim == 0)
assign dim_sel = ~dim_addr_match[dim];
else
assign dim_sel = &dim_addr_match[0:dim-1] &
~dim_addr_match[dim];
end
`DIM_ORDER_DESCENDING:
begin
if(dim == (num_dimensions - 1))
assign dim_sel = ~dim_addr_match[dim];
else
assign dim_sel = ~dim_addr_match[dim] &
dim_addr_match[(dim+1):
(num_dimensions-1)];
end
endcase
wire [0:num_neighbors_per_dim-1] port_dec;
assign next_router_address[dim*dim_addr_width:
(dim+1)*dim_addr_width-1]
= next_dim_addr;
case(connectivity)
`CONNECTIVITY_LINE, `CONNECTIVITY_RING:
begin
wire route_down;
assign route_down
= (route_port == dim*num_neighbors_per_dim);
wire route_up;
assign route_up
= (route_port == dim*num_neighbors_per_dim+1);
// Assemble a delta value for the address segment
// corresponding to the current dimension; the delta
// can have the values -1 (i.e., all ones in two's
// complement), 0 or 1
wire [0:dim_addr_width-1] addr_delta;
if(dim_addr_width > 1)
assign addr_delta[0:dim_addr_width-2]
= {(dim_addr_width-1){route_down}};
assign addr_delta[dim_addr_width-1]
= route_down | route_up;
assign next_dim_addr = curr_dim_addr + addr_delta;
case(connectivity)
`CONNECTIVITY_LINE:
begin
assign port_dec
= {dest_dim_addr < next_dim_addr,
dest_dim_addr > next_dim_addr};
end
`CONNECTIVITY_RING:
begin
// FIXME: add implementation here!
// synopsys translate_off
initial
begin
$display({"ERROR: The lookahead routing ",
"logic module %m does not yet ",
"support ring connectivity ",
"within each dimension."});
$stop;
end
// synopsys translate_on
end
endcase
end
`CONNECTIVITY_FULL:
begin
wire route_dest;
assign route_dest
= (route_port >= (dim*num_neighbors_per_dim)) &&
(route_port <= ((dim+1)*num_neighbors_per_dim-1));
assign next_dim_addr
= route_dest ? dest_dim_addr : curr_dim_addr;
wire [0:num_routers_per_dim-1] dest_dim_addr_dec;
c_decoder
#(.num_ports(num_routers_per_dim))
dest_dim_addr_dec_dec
(.data_in(dest_dim_addr),
.data_out(dest_dim_addr_dec));
wire [0:(2*num_routers_per_dim-1)-1]
dest_dim_addr_dec_repl;
assign dest_dim_addr_dec_repl
= {dest_dim_addr_dec,
dest_dim_addr_dec[0:(num_routers_per_dim-1)-1]};
assign port_dec
= dest_dim_addr_dec_repl[(next_dim_addr+1) +:
num_neighbors_per_dim];
end
endcase
assign next_route_op[dim*num_neighbors_per_dim:
(dim+1)*num_neighbors_per_dim-1]
= port_dec & {num_neighbors_per_dim{dim_sel}};
end
end
endcase
wire eject;
if(resource_class == (num_resource_classes - 1))
assign eject = &dim_addr_match;
else if(resource_class == (num_resource_classes - 2))
assign eject = &dim_addr_match & inc_rc;
else
assign eject = 1'b0;
if(num_nodes_per_router > 1)
begin
wire [0:node_addr_width-1] dest_node_address;
assign dest_node_address
= hop_route_info[hop_route_info_width-node_addr_width:
hop_route_info_width-1];
wire [0:num_nodes_per_router-1] node_sel;
c_decoder
#(.num_ports(num_nodes_per_router))
node_sel_dec
(.data_in(dest_node_address),
.data_out(node_sel));
assign next_route_op[num_ports-num_nodes_per_router:num_ports-1]
= node_sel & {num_nodes_per_router{eject}};
end
else
assign next_route_op[num_ports-1] = eject;
endgenerate
wire [0:port_idx_width-1] next_route_port;
c_encoder
#(.num_ports(num_ports))
next_route_port_enc
(.data_in(next_route_op),
.data_out(next_route_port));
assign la_route_info[0:port_idx_width-1] = next_route_port;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// parameters for array sizes
localparam WA = 8; // address dimension size
localparam WB = 8; // bit dimension size
localparam NO = 10; // number of access events
// 2D packed arrays
logic [WA-1:0] [WB-1:0] array_bg; // big endian array
/* verilator lint_off LITENDIAN */
logic [0:WA-1] [0:WB-1] array_lt; // little endian array
/* verilator lint_on LITENDIAN */
integer cnt = 0;
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin
$write("*-* All Finished *-*\n");
$finish;
end
// big endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaaults (all bits to x)
if (cnt[30:2]==0) array_bg <= {WA *WB{1'bx} };
else if (cnt[30:2]==1) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==2) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==3) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==4) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==5) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==6) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==7) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==8) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==9) array_bg <= {WA{ {WB{1'bx}} }};
end else if (cnt[1:0]==2'd1) begin
// write value to array
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) array_bg <= {WA *WB +0{1'b1}};
else if (cnt[30:2]==2) array_bg [WA/2-1:0 ] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==3) array_bg [WA -1:WA/2] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==4) array_bg [ 0 ] <= {1 *WB +0{1'b1}};
else if (cnt[30:2]==5) array_bg [WA -1 ] <= {1 *WB +0{1'b1}};
else if (cnt[30:2]==6) array_bg [ 0 ][WB/2-1:0 ] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==7) array_bg [WA -1 ][WB -1:WB/2] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==8) array_bg [ 0 ][ 0 ] <= {1 *1 +0{1'b1}};
else if (cnt[30:2]==9) array_bg [WA -1 ][WB -1 ] <= {1 *1 +0{1'b1}};
end else if (cnt[1:0]==2'd2) begin
// check array value
if (cnt[30:2]==0) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==1) begin if (array_bg !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==2) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111111111111111111111111111) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==3) begin if (array_bg !== 64'b11111111111111111111111111111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==4) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==5) begin if (array_bg !== 64'b11111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==6) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1111) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==7) begin if (array_bg !== 64'b1111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==8) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==9) begin if (array_bg !== 64'b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_bg); $stop(); end end
end else if (cnt[1:0]==2'd3) begin
// read value from array (not a very good test for now)
if (cnt[30:2]==0) begin if (array_bg !== {WA *WB {1'bx}}) $stop(); end
else if (cnt[30:2]==1) begin if (array_bg !== {WA *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==2) begin if (array_bg [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==3) begin if (array_bg [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==4) begin if (array_bg [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==5) begin if (array_bg [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==6) begin if (array_bg [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==7) begin if (array_bg [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==8) begin if (array_bg [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end
else if (cnt[30:2]==9) begin if (array_bg [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end
end
// little endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaaults (all bits to x)
if (cnt[30:2]==0) array_lt <= {WA *WB{1'bx} };
else if (cnt[30:2]==1) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==2) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==3) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==4) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==5) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==6) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==7) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==8) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==9) array_lt <= {WA{ {WB{1'bx}} }};
end else if (cnt[1:0]==2'd1) begin
// write value to array
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) array_lt <= {WA *WB +0{1'b1}};
else if (cnt[30:2]==2) array_lt [0 :WA/2-1] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==3) array_lt [WA/2:WA -1] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==4) array_lt [0 ] <= {1 *WB +0{1'b1}};
else if (cnt[30:2]==5) array_lt [ WA -1] <= {1 *WB +0{1'b1}};
else if (cnt[30:2]==6) array_lt [0 ][0 :WB/2-1] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==7) array_lt [ WA -1][WB/2:WB -1] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==8) array_lt [0 ][0 ] <= {1 *1 +0{1'b1}};
else if (cnt[30:2]==9) array_lt [ WA -1][ WB -1] <= {1 *1 +0{1'b1}};
end else if (cnt[1:0]==2'd2) begin
// check array value
if (cnt[30:2]==0) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==1) begin if (array_lt !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==2) begin if (array_lt !== 64'b11111111111111111111111111111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==3) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111111111111111111111111111) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==4) begin if (array_lt !== 64'b11111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==5) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==6) begin if (array_lt !== 64'b1111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==7) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1111) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==8) begin if (array_lt !== 64'b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==9) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1) begin $display("%b", array_lt); $stop(); end end
end else if (cnt[1:0]==2'd3) begin
// read value from array (not a very good test for now)
if (cnt[30:2]==0) begin if (array_lt !== {WA *WB {1'bx}}) $stop(); end
else if (cnt[30:2]==1) begin if (array_lt !== {WA *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==2) begin if (array_lt [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==3) begin if (array_lt [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==4) begin if (array_lt [0 ] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==5) begin if (array_lt [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==6) begin if (array_lt [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==7) begin if (array_lt [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==8) begin if (array_lt [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end
else if (cnt[30:2]==9) begin if (array_lt [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2009 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`ifdef VCS
`define NO_SHORTREAL
`endif
`ifdef NC
`define NO_SHORTREAL
`endif
`ifdef VERILATOR // Unsupported
`define NO_SHORTREAL
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Allowed import return types:
// void, byte, shortint, int, longint, real, shortreal, chandle, and string
// Scalar bit and logic
//
// Allowed argument types:
// Same as above plus packed arrays
import "DPI-C" pure function bit dpii_f_bit (input bit i);
import "DPI-C" pure function bit [8-1:0] dpii_f_bit8 (input bit [8-1:0] i);
import "DPI-C" pure function bit [9-1:0] dpii_f_bit9 (input bit [9-1:0] i);
import "DPI-C" pure function bit [16-1:0] dpii_f_bit16 (input bit [16-1:0] i);
import "DPI-C" pure function bit [17-1:0] dpii_f_bit17 (input bit [17-1:0] i);
import "DPI-C" pure function bit [32-1:0] dpii_f_bit32 (input bit [32-1:0] i);
// Illegal to return > 32 bits, so we use longint
import "DPI-C" pure function longint dpii_f_bit33 (input bit [33-1:0] i);
import "DPI-C" pure function longint dpii_f_bit64 (input bit [64-1:0] i);
import "DPI-C" pure function int dpii_f_int (input int i);
import "DPI-C" pure function byte dpii_f_byte (input byte i);
import "DPI-C" pure function shortint dpii_f_shortint (input shortint i);
import "DPI-C" pure function longint dpii_f_longint (input longint i);
import "DPI-C" pure function chandle dpii_f_chandle (input chandle i);
import "DPI-C" pure function string dpii_f_string (input string i);
import "DPI-C" pure function real dpii_f_real (input real i);
`ifndef NO_SHORTREAL
import "DPI-C" pure function shortreal dpii_f_shortreal(input shortreal i);
`endif
import "DPI-C" pure function void dpii_v_bit (input bit i, output bit o);
import "DPI-C" pure function void dpii_v_int (input int i, output int o);
import "DPI-C" pure function void dpii_v_byte (input byte i, output byte o);
import "DPI-C" pure function void dpii_v_shortint (input shortint i, output shortint o);
import "DPI-C" pure function void dpii_v_longint (input longint i, output longint o);
import "DPI-C" pure function void dpii_v_chandle (input chandle i, output chandle o);
import "DPI-C" pure function void dpii_v_string (input string i, output string o);
import "DPI-C" pure function void dpii_v_real (input real i, output real o);
import "DPI-C" pure function void dpii_v_uint (input int unsigned i, output int unsigned o);
import "DPI-C" pure function void dpii_v_ushort (input shortint unsigned i, output shortint unsigned o);
import "DPI-C" pure function void dpii_v_ulong (input longint unsigned i, output longint unsigned o);
`ifndef NO_SHORTREAL
import "DPI-C" pure function void dpii_v_shortreal(input shortreal i, output shortreal o);
`endif
import "DPI-C" pure function void dpii_v_bit64 (input bit [64-1:0] i, output bit [64-1:0] o);
import "DPI-C" pure function void dpii_v_bit95 (input bit [95-1:0] i, output bit [95-1:0] o);
import "DPI-C" pure function void dpii_v_bit96 (input bit [96-1:0] i, output bit [96-1:0] o);
import "DPI-C" pure function int dpii_f_strlen (input string i);
import "DPI-C" function void dpii_f_void ();
// Try a task
import "DPI-C" task dpii_t_void ();
import "DPI-C" context task dpii_t_void_context ();
import "DPI-C" task dpii_t_int (input int i, output int o);
// Try non-pure, aliasing with name
import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i);
import "DPI-C" dpii_fa_bit = function int oth_f_int2(input int i);
bit i_b, o_b;
bit [7:0] i_b8;
bit [8:0] i_b9;
bit [15:0] i_b16;
bit [16:0] i_b17;
bit [31:0] i_b32;
bit [32:0] i_b33, o_b33;
bit [63:0] i_b64, o_b64;
bit [94:0] i_b95, o_b95;
bit [95:0] i_b96, o_b96;
int i_i, o_i;
byte i_y, o_y;
shortint i_s, o_s;
longint i_l, o_l;
int unsigned i_iu, o_iu;
shortint unsigned i_su, o_su;
longint unsigned i_lu, o_lu;
// verilator lint_off UNDRIVEN
chandle i_c, o_c;
string i_n, o_n;
// verilator lint_on UNDRIVEN
real i_d, o_d;
`ifndef NO_SHORTREAL
shortreal i_f, o_f;
`endif
bit [94:0] wide;
bit [6*8:1] string6;
initial begin
wide = 95'h15caff7a73c48afee4ffcb57;
i_b = 1'b1;
i_b8 = {1'b1,wide[8-2:0]};
i_b9 = {1'b1,wide[9-2:0]};
i_b16 = {1'b1,wide[16-2:0]};
i_b17 = {1'b1,wide[17-2:0]};
i_b32 = {1'b1,wide[32-2:0]};
i_b33 = {1'b1,wide[33-2:0]};
i_b64 = {1'b1,wide[64-2:0]};
i_b95 = {1'b1,wide[95-2:0]};
i_b96 = {1'b1,wide[96-2:0]};
i_i = {1'b1,wide[32-2:0]};
i_iu= {1'b1,wide[32-2:0]};
i_y = {1'b1,wide[8-2:0]};
i_s = {1'b1,wide[16-2:0]};
i_su= {1'b1,wide[16-2:0]};
i_l = {1'b1,wide[64-2:0]};
i_lu= {1'b1,wide[64-2:0]};
i_d = 32.1;
`ifndef NO_SHORTREAL
i_f = 30.2;
`endif
if (dpii_f_bit (i_b) !== ~i_b) $stop;
if (dpii_f_bit8 (i_b8) !== ~i_b8) $stop;
if (dpii_f_bit9 (i_b9) !== ~i_b9) $stop;
if (dpii_f_bit16 (i_b16) !== ~i_b16) $stop;
if (dpii_f_bit17 (i_b17) !== ~i_b17) $stop;
if (dpii_f_bit32 (i_b32) !== ~i_b32) $stop;
// These return different sizes, so we need to truncate
// verilator lint_off WIDTH
o_b33 = dpii_f_bit33 (i_b33);
o_b64 = dpii_f_bit64 (i_b64);
// verilator lint_on WIDTH
if (o_b33 !== ~i_b33) $stop;
if (o_b64 !== ~i_b64) $stop;
if (dpii_f_bit (i_b) !== ~i_b) $stop;
if (dpii_f_int (i_i) !== ~i_i) $stop;
if (dpii_f_byte (i_y) !== ~i_y) $stop;
if (dpii_f_shortint (i_s) !== ~i_s) $stop;
if (dpii_f_longint (i_l) !== ~i_l) $stop;
if (dpii_f_chandle (i_c) !== i_c) $stop;
if (dpii_f_string (i_n) != i_n) $stop;
if (dpii_f_real (i_d) != i_d+1.5) $stop;
`ifndef NO_SHORTREAL
if (dpii_f_shortreal(i_f) != i_f+1.5) $stop;
`endif
dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop;
dpii_v_int (i_i,o_i); if (o_i !== ~i_i) $stop;
dpii_v_byte (i_y,o_y); if (o_y !== ~i_y) $stop;
dpii_v_shortint (i_s,o_s); if (o_s !== ~i_s) $stop;
dpii_v_longint (i_l,o_l); if (o_l !== ~i_l) $stop;
dpii_v_uint (i_iu,o_iu); if (o_iu !== ~i_iu) $stop;
dpii_v_ushort (i_su,o_su); if (o_su !== ~i_su) $stop;
dpii_v_ulong (i_lu,o_lu); if (o_lu !== ~i_lu) $stop;
dpii_v_chandle (i_c,o_c); if (o_c !== i_c) $stop;
dpii_v_string (i_n,o_n); if (o_n != i_n) $stop;
dpii_v_real (i_d,o_d); if (o_d != i_d+1.5) $stop;
`ifndef NO_SHORTREAL
dpii_v_shortreal(i_f,o_f); if (o_f != i_f+1.5) $stop;
`endif
dpii_v_bit64 (i_b64,o_b64); if (o_b64 !== ~i_b64) $stop;
dpii_v_bit95 (i_b95,o_b95); if (o_b95 !== ~i_b95) $stop;
dpii_v_bit96 (i_b96,o_b96); if (o_b96 !== ~i_b96) $stop;
if (dpii_f_strlen ("")!=0) $stop;
if (dpii_f_strlen ("s")!=1) $stop;
if (dpii_f_strlen ("st")!=2) $stop;
if (dpii_f_strlen ("str")!=3) $stop;
if (dpii_f_strlen ("stri")!=4) $stop;
if (dpii_f_strlen ("string_l")!=8) $stop;
if (dpii_f_strlen ("string_len")!=10) $stop;
string6 = "hello6";
`ifdef VERILATOR
string6 = $c48(string6); // Don't optimize away - want to see the constant conversion function
`endif
if (dpii_f_strlen (string6) != 6) $stop;
dpii_f_void();
dpii_t_void();
dpii_t_void_context();
i_i = 32'h456789ab;
dpii_t_int (i_i,o_i); if (o_b !== ~i_b) $stop;
// Check alias
if (oth_f_int1(32'd123) !== ~32'd123) $stop;
if (oth_f_int2(32'd124) !== ~32'd124) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge clk) begin
i_b <= ~i_b;
// This once mis-threw a BLKSEQ warning
dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop;
end
endmodule
|
module SeletorClock(
input wire clock,
input wire reset,
input wire sel_1hz,
input wire clock_1hz,
input wire sel_10hz,
input wire clock_10hz,
input wire sel_100hz,
input wire clock_100hz,
input wire sel_1khz,
input wire clock_1khz,
input wire sel_10khz,
input wire clock_10khz,
input wire sel_100khz,
input wire clock_100khz,
input wire sel_1mhz,
input wire clock_1mhz,
input wire sel_12mhz,
input wire clock_12mhz,
input wire sel_25mhz,
output reg clock_saida
);
always @ (posedge clock or posedge reset)
begin
if(reset) begin
clock_saida <= 1'b0;
end
else if( (sel_1hz == 1'b1) && (sel_10hz == 1'b0) && (sel_100hz == 1'b0) && (sel_1khz == 1'b0) && (sel_10khz == 1'b0) && (sel_100khz == 1'b0) && (sel_1mhz == 1'b0) && (sel_12mhz == 1'b0) && (sel_25mhz == 1'b0) ) begin
clock_saida <= clock_1hz;
end
else if( (sel_1hz == 1'b0) && (sel_10hz == 1'b1) && (sel_100hz == 1'b0) && (sel_1khz == 1'b0) && (sel_10khz == 1'b0) && (sel_100khz == 1'b0) && (sel_1mhz == 1'b0) && (sel_12mhz == 1'b0) && (sel_25mhz == 1'b0) ) begin
clock_saida <= clock_10hz;
end
else if( (sel_1hz == 1'b0) && (sel_10hz == 1'b0) && (sel_100hz == 1'b1) && (sel_1khz == 1'b0) && (sel_10khz == 1'b0) && (sel_100khz == 1'b0) && (sel_1mhz == 1'b0) && (sel_12mhz == 1'b0) && (sel_25mhz == 1'b0)) begin
clock_saida <= clock_100hz;
end
else if( (sel_1hz == 1'b0) && (sel_10hz == 1'b0) && (sel_100hz == 1'b0) && (sel_1khz == 1'b1) && (sel_10khz == 1'b0) && (sel_100khz == 1'b0) && (sel_1mhz == 1'b0) && (sel_12mhz == 1'b0) && (sel_25mhz == 1'b0)) begin
clock_saida <= clock_1khz;
end
else if( (sel_1hz == 1'b0) && (sel_10hz == 1'b0) && (sel_100hz == 1'b0) && (sel_1khz == 1'b0) && (sel_10khz == 1'b1) && (sel_100khz == 1'b0) && (sel_1mhz == 1'b0) && (sel_12mhz == 1'b0) && (sel_25mhz == 1'b0)) begin
clock_saida <= clock_10khz;
end
else if( (sel_1hz == 1'b0) && (sel_10hz == 1'b0) && (sel_100hz == 1'b0) && (sel_1khz == 1'b0) && (sel_10khz == 1'b0) && (sel_100khz == 1'b1) && (sel_1mhz == 1'b0) && (sel_12mhz == 1'b0) && (sel_25mhz == 1'b0)) begin
clock_saida <= clock_100khz;
end
else if( (sel_1hz == 1'b0) && (sel_10hz == 1'b0) && (sel_100hz == 1'b0) && (sel_1khz == 1'b0) && (sel_10khz == 1'b0) && (sel_100khz == 1'b0) && (sel_1mhz == 1'b1) && (sel_12mhz == 1'b0) && (sel_25mhz == 1'b0)) begin
clock_saida <= clock_1mhz;
end
else if( (sel_1hz == 1'b0) && (sel_10hz == 1'b0) && (sel_100hz == 1'b0) && (sel_1khz == 1'b0) && (sel_10khz == 1'b0) && (sel_100khz == 1'b0) && (sel_1mhz == 1'b0) && (sel_12mhz == 1'b1) && (sel_25mhz == 1'b0)) begin
clock_saida <= clock_12mhz;
end
else if( (sel_1hz == 1'b0) && (sel_10hz == 1'b0) && (sel_100hz == 1'b0) && (sel_1khz == 1'b0) && (sel_10khz == 1'b0) && (sel_100khz == 1'b0) && (sel_1mhz == 1'b0) && (sel_12mhz == 1'b0) && (sel_25mhz == 1'b1)) begin
clock_saida <= clock;
end
else begin
clock_saida <= 1'b0;
end
end
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg _ranit;
reg [2:0] xor3;
reg [1:0] xor2;
reg [0:0] xor1;
reg [2:0] ma, mb;
reg [9:0] mc;
reg [4:0] mr1;
reg [30:0] mr2;
reg [67:0] sh1;
reg [67:0] shq;
wire foo, bar; assign {foo,bar} = 2'b1_0;
// surefire lint_off STMINI
initial _ranit = 0;
wire [4:0] cond_check = (( xor2 == 2'b11) ? 5'h1
: (xor2 == 2'b00) ? 5'h2
: (xor2 == 2'b01) ? 5'h3
: 5'h4);
wire ctrue = 1'b1 ? cond_check[1] : cond_check[0];
wire cfalse = 1'b0 ? cond_check[1] : cond_check[0];
wire cif = cond_check[2] ? cond_check[1] : cond_check[0];
wire cifn = (!cond_check[2]) ? cond_check[1] : cond_check[0];
wire [4:0] doubleconc = {1'b0, 1'b1, 1'b0, cond_check[0], 1'b1};
wire zero = 1'b0;
wire one = 1'b1;
wire [5:0] rep6 = {6{one}};
// verilator lint_off WIDTH
localparam [3:0] bug764_p11 = 1'bx;
// verilator lint_on WIDTH
always @ (posedge clk) begin
if (!_ranit) begin
_ranit <= 1;
if (rep6 != 6'b111111) $stop;
if (!one) $stop;
if (~one) $stop;
if (( 1'b0 ? 3'h3 : 1'b0 ? 3'h2 : 1'b1 ? 3'h1 : 3'h0) !== 3'h1) $stop;
// verilator lint_off WIDTH
if (( 8'h10 + 1'b0 ? 8'he : 8'hf) !== 8'he) $stop; // + is higher than ?
// verilator lint_on WIDTH
// surefire lint_off SEQASS
xor1 = 1'b1;
xor2 = 2'b11;
xor3 = 3'b111;
// verilator lint_off WIDTH
if (1'b1 & | (!xor3)) $stop;
// verilator lint_on WIDTH
if ({1{xor1}} != 1'b1) $stop;
if ({4{xor1}} != 4'b1111) $stop;
if (!(~xor1) !== ~(!xor1)) $stop;
if ((^xor1) !== 1'b1) $stop;
if ((^xor2) !== 1'b0) $stop;
if ((^xor3) !== 1'b1) $stop;
if (~(^xor2) !== 1'b1) $stop;
if (~(^xor3) !== 1'b0) $stop;
if ((^~xor1) !== 1'b0) $stop;
if ((^~xor2) !== 1'b1) $stop;
if ((^~xor3) !== 1'b0) $stop;
if ((~^xor1) !== 1'b0) $stop;
if ((~^xor2) !== 1'b1) $stop;
if ((~^xor3) !== 1'b0) $stop;
xor1 = 1'b0;
xor2 = 2'b10;
xor3 = 3'b101;
if ((^xor1) !== 1'b0) $stop;
if ((^xor2) !== 1'b1) $stop;
if ((^xor3) !== 1'b0) $stop;
if (~(^xor2) !== 1'b0) $stop;
if (~(^xor3) !== 1'b1) $stop;
if ((^~xor1) !== 1'b1) $stop;
if ((^~xor2) !== 1'b0) $stop;
if ((^~xor3) !== 1'b1) $stop;
if ((~^xor1) !== 1'b1) $stop;
if ((~^xor2) !== 1'b0) $stop;
if ((~^xor3) !== 1'b1) $stop;
ma = 3'h3;
mb = 3'h4;
mc = 10'h5;
mr1 = ma * mb; // Lint ASWESB: Assignment width mismatch
mr2 = 30'h5 * mc; // Lint ASWESB: Assignment width mismatch
if (mr1 !== 5'd12) $stop;
if (mr2 !== 31'd25) $stop; // Lint CWECBB: Comparison width mismatch
sh1 = 68'hf_def1_9abc_5678_1234;
shq = sh1 >> 16;
if (shq !== 68'hf_def1_9abc_5678) $stop;
shq = sh1 << 16; // Lint ASWESB: Assignment width mismatch
if (shq !== 68'h1_9abc_5678_1234_0000) $stop;
// surefire lint_on SEQASS
// Test display extraction widthing
$display("[%0t] %x %x %x(%d)", $time, shq[2:0], shq[2:0]<<2, xor3[2:0], xor3[2:0]);
// bug736
//verilator lint_off WIDTH
if ((~| 4'b0000) != 4'b0001) $stop;
if ((~| 4'b0010) != 4'b0000) $stop;
if ((~& 4'b1111) != 4'b0000) $stop;
if ((~& 4'b1101) != 4'b0001) $stop;
//verilator lint_on WIDTH
// bug764
//verilator lint_off WIDTH
// X does not sign extend
if (bug764_p11 !== 4'b000x) $stop;
if (~& bug764_p11 !== 1'b1) $stop;
//verilator lint_on WIDTH
// However IEEE says for constants in 2012 5.7.1 that smaller-sizes do extend
if (4'bx !== 4'bxxxx) $stop;
if (4'bz !== 4'bzzzz) $stop;
if (4'b1 !== 4'b0001) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
reg [63:0] m_data_pipe2_r;
reg [31:0] m_corr_data_w0, m_corr_data_w1;
reg [7:0] m_corr_data_b8;
initial begin
m_data_pipe2_r = 64'h1234_5678_9abc_def0;
{m_corr_data_b8, m_corr_data_w1, m_corr_data_w0} = { m_data_pipe2_r[63:57], 1'b0, //m_corr_data_b8 [7:0]
m_data_pipe2_r[56:26], 1'b0, //m_corr_data_w1 [31:0]
m_data_pipe2_r[25:11], 1'b0, //m_corr_data_w0 [31:16]
m_data_pipe2_r[10:04], 1'b0, //m_corr_data_w0 [15:8]
m_data_pipe2_r[03:01], 1'b0, //m_corr_data_w0 [7:4]
m_data_pipe2_r[0], 3'b000 //m_corr_data_w0 [3:0]
};
if (m_corr_data_w0 != 32'haf36de00) $stop;
if (m_corr_data_w1 != 32'h1a2b3c4c) $stop;
if (m_corr_data_b8 != 8'h12) $stop;
end
endmodule
|
(** * MoreCoq: More About Coq *)
Require Export Poly.
(** This chapter introduces several more Coq tactics that,
together, allow us to prove many more theorems about the
functional programs we are writing. *)
(* ###################################################### *)
(** * The [apply] Tactic *)
(** We often encounter situations where the goal to be proved is
exactly the same as some hypothesis in the context or some
previously proved lemma. *)
Theorem silly1 : forall (n m o p : nat),
n = m ->
[n;o] = [n;p] ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
rewrite <- eq1.
(* At this point, we could finish with
"[rewrite -> eq2. reflexivity.]" as we have
done several times above. But we can achieve the
same effect in a single step by using the
[apply] tactic instead: *)
apply eq2. Qed.
(** The [apply] tactic also works with _conditional_ hypotheses
and lemmas: if the statement being applied is an implication, then
the premises of this implication will be added to the list of
subgoals needing to be proved. *)
Theorem silly2 : forall (n m o p : nat),
n = m ->
(forall (q r : nat), q = r -> [q;o] = [r;p]) ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
apply eq2. apply eq1. Qed.
(** You may find it instructive to experiment with this proof
and see if there is a way to complete it using just [rewrite]
instead of [apply]. *)
(** Typically, when we use [apply H], the statement [H] will
begin with a [forall] binding some _universal variables_. When
Coq matches the current goal against the conclusion of [H], it
will try to find appropriate values for these variables. For
example, when we do [apply eq2] in the following proof, the
universal variable [q] in [eq2] gets instantiated with [n] and [r]
gets instantiated with [m]. *)
Theorem silly2a : forall (n m : nat),
(n,n) = (m,m) ->
(forall (q r : nat), (q,q) = (r,r) -> [q] = [r]) ->
[n] = [m].
Proof.
intros n m eq1 eq2.
apply eq2. apply eq1. Qed.
(** **** Exercise: 2 stars, optional (silly_ex) *)
(** Complete the following proof without using [simpl]. *)
Theorem silly_ex :
(forall n, evenb n = true -> oddb (S n) = true) ->
evenb 3 = true ->
oddb 4 = true.
Proof.
intros. apply H. apply H0. Qed.
(** [] *)
(** To use the [apply] tactic, the (conclusion of the) fact
being applied must match the goal _exactly_ -- for example, [apply]
will not work if the left and right sides of the equality are
swapped. *)
Theorem silly3_firsttry : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
simpl.
(* Here we cannot use [apply] directly *)
Abort.
(** In this case we can use the [symmetry] tactic, which switches the
left and right sides of an equality in the goal. *)
Theorem silly3 : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
symmetry.
simpl. (* Actually, this [simpl] is unnecessary, since
[apply] will perform simplification first. *)
apply H. Qed.
(** **** Exercise: 3 stars (apply_exercise1) *)
(** Hint: you can use [apply] with previously defined lemmas, not
just hypotheses in the context. Remember that [SearchAbout] is
your friend. *)
Theorem rev_exercise1 : forall (l l' : list nat),
l = rev l' ->
l' = rev l.
Proof.
intros. rewrite H. symmetry. apply rev_involutive. Qed.
(** [] *)
(** **** Exercise: 1 star, optional (apply_rewrite) *)
(** Briefly explain the difference between the tactics [apply] and
[rewrite]. Are there situations where both can usefully be
applied?
Apply seems to be like using another theorem as if it were a function, so that
if it's result is Qed, then the current branch is proven. rewrite rewrites
terms, but does not resolve the proof obligation.
*)
(** [] *)
(* ###################################################### *)
(** * The [apply ... with ...] Tactic *)
(** The following silly example uses two rewrites in a row to
get from [[a,b]] to [[e,f]]. *)
Example trans_eq_example : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
rewrite -> eq1. rewrite -> eq2. reflexivity. Qed.
(** Since this is a common pattern, we might
abstract it out as a lemma recording once and for all
the fact that equality is transitive. *)
Theorem trans_eq : forall (X:Type) (n m o : X),
n = m -> m = o -> n = o.
Proof.
intros X n m o eq1 eq2. rewrite -> eq1. rewrite -> eq2.
reflexivity. Qed.
(** Now, we should be able to use [trans_eq] to
prove the above example. However, to do this we need
a slight refinement of the [apply] tactic. *)
Example trans_eq_example' : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
(* If we simply tell Coq [apply trans_eq] at this point,
it can tell (by matching the goal against the
conclusion of the lemma) that it should instantiate [X]
with [[nat]], [n] with [[a,b]], and [o] with [[e,f]].
However, the matching process doesn't determine an
instantiation for [m]: we have to supply one explicitly
by adding [with (m:=[c,d])] to the invocation of
[apply]. *)
apply trans_eq with (m:=[c;d]). apply eq1. apply eq2. Qed.
(** Actually, we usually don't have to include the name [m]
in the [with] clause; Coq is often smart enough to
figure out which instantiation we're giving. We could
instead write: [apply trans_eq with [c,d]]. *)
(** **** Exercise: 3 stars, optional (apply_with_exercise) *)
Example trans_eq_exercise : forall (n m o p : nat),
m = (minustwo o) ->
(n + p) = m ->
(n + p) = (minustwo o).
Proof.
intros. rewrite H0. apply H. Qed.
(** [] *)
(* ###################################################### *)
(** * The [inversion] tactic *)
(** Recall the definition of natural numbers:
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
It is clear from this definition that every number has one of two
forms: either it is the constructor [O] or it is built by applying
the constructor [S] to another number. But there is more here than
meets the eye: implicit in the definition (and in our informal
understanding of how datatype declarations work in other
programming languages) are two other facts:
- The constructor [S] is _injective_. That is, the only way we can
have [S n = S m] is if [n = m].
- The constructors [O] and [S] are _disjoint_. That is, [O] is not
equal to [S n] for any [n]. *)
(** Similar principles apply to all inductively defined types: all
constructors are injective, and the values built from distinct
constructors are never equal. For lists, the [cons] constructor is
injective and [nil] is different from every non-empty list. For
booleans, [true] and [false] are unequal. (Since neither [true]
nor [false] take any arguments, their injectivity is not an issue.) *)
(** Coq provides a tactic called [inversion] that allows us to exploit
these principles in proofs.
The [inversion] tactic is used like this. Suppose [H] is a
hypothesis in the context (or a previously proven lemma) of the
form
c a1 a2 ... an = d b1 b2 ... bm
for some constructors [c] and [d] and arguments [a1 ... an] and
[b1 ... bm]. Then [inversion H] instructs Coq to "invert" this
equality to extract the information it contains about these terms:
- If [c] and [d] are the same constructor, then we know, by the
injectivity of this constructor, that [a1 = b1], [a2 = b2],
etc.; [inversion H] adds these facts to the context, and tries
to use them to rewrite the goal.
- If [c] and [d] are different constructors, then the hypothesis
[H] is contradictory. That is, a false assumption has crept
into the context, and this means that any goal whatsoever is
provable! In this case, [inversion H] marks the current goal as
completed and pops it off the goal stack. *)
(** The [inversion] tactic is probably easier to understand by
seeing it in action than from general descriptions like the above.
Below you will find example theorems that demonstrate the use of
[inversion] and exercises to test your understanding. *)
Theorem eq_add_S : forall (n m : nat),
S n = S m ->
n = m.
Proof.
intros n m eq. inversion eq. reflexivity. Qed.
Theorem silly4 : forall (n m : nat),
[n] = [m] ->
n = m.
Proof.
intros n o eq. inversion eq. reflexivity. Qed.
(** As a convenience, the [inversion] tactic can also
destruct equalities between complex values, binding
multiple variables as it goes. *)
Theorem silly5 : forall (n m o : nat),
[n;m] = [o;o] ->
[n] = [m].
Proof.
intros n m o eq. inversion eq. reflexivity. Qed.
(** **** Exercise: 1 star (sillyex1) *)
Example sillyex1 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = z :: j ->
y :: l = x :: j ->
x = y.
Proof.
intros. inversion H0. reflexivity. Qed.
(** [] *)
Theorem silly6 : forall (n : nat),
S n = O ->
2 + 2 = 5.
Proof.
intros n contra. inversion contra. Qed.
Theorem silly7 : forall (n m : nat),
false = true ->
[n] = [m].
Proof.
intros n m contra. inversion contra. Qed.
(** **** Exercise: 1 star (sillyex2) *)
Example sillyex2 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = [] ->
y :: l = z :: j ->
x = z.
Proof.
intros. inversion H. Qed.
(** [] *)
(** While the injectivity of constructors allows us to reason
[forall (n m : nat), S n = S m -> n = m], the reverse direction of
the implication is an instance of a more general fact about
constructors and functions, which we will often find useful: *)
Theorem f_equal : forall (A B : Type) (f: A -> B) (x y: A),
x = y -> f x = f y.
Proof. intros A B f x y eq. rewrite eq. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (practice) *)
(** A couple more nontrivial but not-too-complicated proofs to work
together in class, or for you to work as exercises. *)
Theorem beq_nat_0_l : forall n,
beq_nat 0 n = true -> n = 0.
Proof.
intros. destruct n as [| n'].
reflexivity.
inversion H. Qed.
Theorem beq_nat_0_r : forall n,
beq_nat n 0 = true -> n = 0.
Proof.
intros. destruct n as [| n'].
reflexivity.
inversion H. Qed.
(** [] *)
(* ###################################################### *)
(** * Using Tactics on Hypotheses *)
(** By default, most tactics work on the goal formula and leave
the context unchanged. However, most tactics also have a variant
that performs a similar operation on a statement in the context.
For example, the tactic [simpl in H] performs simplification in
the hypothesis named [H] in the context. *)
Theorem S_inj : forall (n m : nat) (b : bool),
beq_nat (S n) (S m) = b ->
beq_nat n m = b.
Proof.
intros n m b H. simpl in H. apply H. Qed.
(** Similarly, the tactic [apply L in H] matches some
conditional statement [L] (of the form [L1 -> L2], say) against a
hypothesis [H] in the context. However, unlike ordinary
[apply] (which rewrites a goal matching [L2] into a subgoal [L1]),
[apply L in H] matches [H] against [L1] and, if successful,
replaces it with [L2].
In other words, [apply L in H] gives us a form of "forward
reasoning" -- from [L1 -> L2] and a hypothesis matching [L1], it
gives us a hypothesis matching [L2]. By contrast, [apply L] is
"backward reasoning" -- it says that if we know [L1->L2] and we
are trying to prove [L2], it suffices to prove [L1].
Here is a variant of a proof from above, using forward reasoning
throughout instead of backward reasoning. *)
Theorem silly3' : forall (n : nat),
(beq_nat n 5 = true -> beq_nat (S (S n)) 7 = true) ->
true = beq_nat n 5 ->
true = beq_nat (S (S n)) 7.
Proof.
intros n eq H.
symmetry in H. apply eq in H. symmetry in H.
apply H. Qed.
(** Forward reasoning starts from what is _given_ (premises,
previously proven theorems) and iteratively draws conclusions from
them until the goal is reached. Backward reasoning starts from
the _goal_, and iteratively reasons about what would imply the
goal, until premises or previously proven theorems are reached.
If you've seen informal proofs before (for example, in a math or
computer science class), they probably used forward reasoning. In
general, Coq tends to favor backward reasoning, but in some
situations the forward style can be easier to use or to think
about. *)
(** **** Exercise: 3 stars (plus_n_n_injective) *)
(** Practice using "in" variants in this exercise. *)
Theorem plus_n_n_injective : forall n m,
n + n = m + m ->
n = m.
Proof.
intros n. induction n as [| n'].
(* Hint: use the plus_n_Sm lemma *)
Case "n = 0".
intros. destruct m. reflexivity. inversion H.
Case "n = S n'".
intros. destruct m. inversion H.
simpl in H.
rewrite <- plus_n_Sm in H.
rewrite <- plus_n_Sm in H.
inversion H.
apply IHn' in H1. rewrite H1. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** * Varying the Induction Hypothesis *)
(** Sometimes it is important to control the exact form of the
induction hypothesis when carrying out inductive proofs in Coq.
In particular, we need to be careful about which of the
assumptions we move (using [intros]) from the goal to the context
before invoking the [induction] tactic. For example, suppose
we want to show that the [double] function is injective -- i.e.,
that it always maps different arguments to different results:
Theorem double_injective: forall n m, double n = double m -> n = m.
The way we _start_ this proof is a little bit delicate: if we
begin it with
intros n. induction n.
]]
all is well. But if we begin it with
intros n m. induction n.
we get stuck in the middle of the inductive case... *)
Theorem double_injective_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction n as [| n'].
Case "n = O". simpl. intros eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'". intros eq. destruct m as [| m'].
SCase "m = O". inversion eq.
SCase "m = S m'". apply f_equal.
(* Here we are stuck. The induction hypothesis, [IHn'], does
not give us [n' = m'] -- there is an extra [S] in the
way -- so the goal is not provable. *)
Abort.
(** What went wrong? *)
(** The problem is that, at the point we invoke the induction
hypothesis, we have already introduced [m] into the context --
intuitively, we have told Coq, "Let's consider some particular
[n] and [m]..." and we now have to prove that, if [double n =
double m] for _this particular_ [n] and [m], then [n = m].
The next tactic, [induction n] says to Coq: We are going to show
the goal by induction on [n]. That is, we are going to prove that
the proposition
- [P n] = "if [double n = double m], then [n = m]"
holds for all [n] by showing
- [P O]
(i.e., "if [double O = double m] then [O = m]")
- [P n -> P (S n)]
(i.e., "if [double n = double m] then [n = m]" implies "if
[double (S n) = double m] then [S n = m]").
If we look closely at the second statement, it is saying something
rather strange: it says that, for a _particular_ [m], if we know
- "if [double n = double m] then [n = m]"
then we can prove
- "if [double (S n) = double m] then [S n = m]".
To see why this is strange, let's think of a particular [m] --
say, [5]. The statement is then saying that, if we know
- [Q] = "if [double n = 10] then [n = 5]"
then we can prove
- [R] = "if [double (S n) = 10] then [S n = 5]".
But knowing [Q] doesn't give us any help with proving [R]! (If we
tried to prove [R] from [Q], we would say something like "Suppose
[double (S n) = 10]..." but then we'd be stuck: knowing that
[double (S n)] is [10] tells us nothing about whether [double n]
is [10], so [Q] is useless at this point.) *)
(** To summarize: Trying to carry out this proof by induction on [n]
when [m] is already in the context doesn't work because we are
trying to prove a relation involving _every_ [n] but just a
_single_ [m]. *)
(** The good proof of [double_injective] leaves [m] in the goal
statement at the point where the [induction] tactic is invoked on
[n]: *)
Theorem double_injective : forall n m,
double n = double m ->
n = m.
Proof.
intros n. induction n as [| n'].
Case "n = O". simpl. intros m eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'".
(* Notice that both the goal and the induction
hypothesis have changed: the goal asks us to prove
something more general (i.e., to prove the
statement for _every_ [m]), but the IH is
correspondingly more flexible, allowing us to
choose any [m] we like when we apply the IH. *)
intros m eq.
(* Now we choose a particular [m] and introduce the
assumption that [double n = double m]. Since we
are doing a case analysis on [n], we need a case
analysis on [m] to keep the two "in sync." *)
destruct m as [| m'].
SCase "m = O".
(* The 0 case is trivial *)
inversion eq.
SCase "m = S m'".
apply f_equal.
(* At this point, since we are in the second
branch of the [destruct m], the [m'] mentioned
in the context at this point is actually the
predecessor of the one we started out talking
about. Since we are also in the [S] branch of
the induction, this is perfect: if we
instantiate the generic [m] in the IH with the
[m'] that we are talking about right now (this
instantiation is performed automatically by
[apply]), then [IHn'] gives us exactly what we
need to finish the proof. *)
apply IHn'. inversion eq. reflexivity. Qed.
(** What this teaches us is that we need to be careful about using
induction to try to prove something too specific: If we're proving
a property of [n] and [m] by induction on [n], we may need to
leave [m] generic. *)
(** The proof of this theorem (left as an exercise) has to be treated similarly: *)
(** **** Exercise: 2 stars (beq_nat_true) *)
Theorem beq_nat_true : forall n m,
beq_nat n m = true -> n = m.
Proof.
intros n. induction n as [| n'].
Case "n = 0".
intros. destruct m as [| m'].
reflexivity. inversion H.
Case "n = S n'".
intros. destruct m as [| m'].
inversion H. apply IHn' in H. rewrite H. reflexivity. Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced (beq_nat_true_informal) *)
(** Give a careful informal proof of [beq_nat_true], being as explicit
as possible about quantifiers. *)
(*SKIPPED*)
(** [] *)
(** The strategy of doing fewer [intros] before an [induction] doesn't
always work directly; sometimes a little _rearrangement_ of
quantified variables is needed. Suppose, for example, that we
wanted to prove [double_injective] by induction on [m] instead of
[n]. *)
Theorem double_injective_take2_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction m as [| m'].
Case "m = O". simpl. intros eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'". apply f_equal.
(* Stuck again here, just like before. *)
Abort.
(** The problem is that, to do induction on [m], we must first
introduce [n]. (If we simply say [induction m] without
introducing anything first, Coq will automatically introduce
[n] for us!) *)
(** What can we do about this? One possibility is to rewrite the
statement of the lemma so that [m] is quantified before [n]. This
will work, but it's not nice: We don't want to have to mangle the
statements of lemmas to fit the needs of a particular strategy for
proving them -- we want to state them in the most clear and
natural way. *)
(** What we can do instead is to first introduce all the
quantified variables and then _re-generalize_ one or more of
them, taking them out of the context and putting them back at
the beginning of the goal. The [generalize dependent] tactic
does this. *)
Theorem double_injective_take2 : forall n m,
double n = double m ->
n = m.
Proof.
intros n m.
(* [n] and [m] are both in the context *)
generalize dependent n.
(* Now [n] is back in the goal and we can do induction on
[m] and get a sufficiently general IH. *)
induction m as [| m'].
Case "m = O". simpl. intros n eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros n eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'". apply f_equal.
apply IHm'. inversion eq. reflexivity. Qed.
(** Let's look at an informal proof of this theorem. Note that
the proposition we prove by induction leaves [n] quantified,
corresponding to the use of generalize dependent in our formal
proof.
_Theorem_: For any nats [n] and [m], if [double n = double m], then
[n = m].
_Proof_: Let [m] be a [nat]. We prove by induction on [m] that, for
any [n], if [double n = double m] then [n = m].
- First, suppose [m = 0], and suppose [n] is a number such
that [double n = double m]. We must show that [n = 0].
Since [m = 0], by the definition of [double] we have [double n =
0]. There are two cases to consider for [n]. If [n = 0] we are
done, since this is what we wanted to show. Otherwise, if [n = S
n'] for some [n'], we derive a contradiction: by the definition of
[double] we would have [double n = S (S (double n'))], but this
contradicts the assumption that [double n = 0].
- Otherwise, suppose [m = S m'] and that [n] is again a number such
that [double n = double m]. We must show that [n = S m'], with
the induction hypothesis that for every number [s], if [double s =
double m'] then [s = m'].
By the fact that [m = S m'] and the definition of [double], we
have [double n = S (S (double m'))]. There are two cases to
consider for [n].
If [n = 0], then by definition [double n = 0], a contradiction.
Thus, we may assume that [n = S n'] for some [n'], and again by
the definition of [double] we have [S (S (double n')) = S (S
(double m'))], which implies by inversion that [double n' = double
m'].
Instantiating the induction hypothesis with [n'] thus allows us to
conclude that [n' = m'], and it follows immediately that [S n' = S
m']. Since [S n' = n] and [S m' = m], this is just what we wanted
to show. [] *)
(** Here's another illustration of [inversion] and using an
appropriately general induction hypothesis. This is a slightly
roundabout way of stating a fact that we have already proved
above. The extra equalities force us to do a little more
equational reasoning and exercise some of the tactics we've seen
recently. *)
Theorem length_snoc' : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l. induction l as [| v' l'].
Case "l = []".
intros n eq. rewrite <- eq. reflexivity.
Case "l = v' :: l'".
intros n eq. simpl. destruct n as [| n'].
SCase "n = 0". inversion eq.
SCase "n = S n'".
apply f_equal. apply IHl'. inversion eq. reflexivity. Qed.
(** It might be tempting to start proving the above theorem
by introducing [n] and [eq] at the outset. However, this leads
to an induction hypothesis that is not strong enough. Compare
the above to the following (aborted) attempt: *)
Theorem length_snoc_bad : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l n eq. induction l as [| v' l'].
Case "l = []".
rewrite <- eq. reflexivity.
Case "l = v' :: l'".
simpl. destruct n as [| n'].
SCase "n = 0". inversion eq.
SCase "n = S n'".
apply f_equal. Abort. (* apply IHl'. *) (* The IH doesn't apply! *)
(** As in the double examples, the problem is that by
introducing [n] before doing induction on [l], the induction
hypothesis is specialized to one particular natural number, namely
[n]. In the induction case, however, we need to be able to use
the induction hypothesis on some other natural number [n'].
Retaining the more general form of the induction hypothesis thus
gives us more flexibility.
In general, a good rule of thumb is to make the induction hypothesis
as general as possible. *)
(** **** Exercise: 3 stars (gen_dep_practice) *)
(** Prove this by induction on [l]. *)
Theorem index_after_last: forall (n : nat) (X : Type) (l : list X),
length l = n ->
index n l = None.
Proof.
intros.
generalize dependent n.
induction l as [| x xs].
Case "nil".
reflexivity.
Case "cons".
destruct n as [| n'].
intros. inversion H.
intros. inversion H.
rewrite H1. apply IHxs. simpl. rewrite H1. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (index_after_last_informal) *)
(** Write an informal proof corresponding to your Coq proof
of [index_after_last]:
_Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index n l = None].
_Proof_:
SKIPPED
[]
*)
(** **** Exercise: 3 stars, optional (gen_dep_practice_more) *)
(** Prove this by induction on [l]. *)
Theorem length_snoc''' : forall (n : nat) (X : Type)
(v : X) (l : list X),
length l = n ->
length (snoc l v) = S n.
Proof.
intros.
generalize dependent n.
induction l as [| x xs].
Case "l = []".
intros. destruct n as [| n'].
reflexivity.
simpl. inversion H.
Case "l = x :: xs".
intros. apply length_snoc'. apply H. Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (app_length_cons) *)
(** Prove this by induction on [l1], without using [app_length]. *)
Theorem eq_remove_S : forall (n m : nat),
n = m -> S n = S m.
Proof.
intros. inversion H. reflexivity. Qed.
Theorem app_length_cons : forall (X : Type) (l1 l2 : list X)
(x : X) (n : nat),
length (l1 ++ (x :: l2)) = n -> S (length (l1 ++ l2)) = n.
Proof.
intros.
generalize dependent n.
generalize dependent l2.
induction l1 as [| y ys].
Case "l1 = nil".
intros. simpl. simpl in H. apply H.
Case "l1 = cons".
intros. simpl. destruct n as [| n'].
inversion H.
apply eq_remove_S. apply IHys. simpl in H.
inversion H. reflexivity. Qed.
(** [] *)
(** **** Exercise: 4 stars, optional (app_length_twice) *)
(** Prove this by induction on [l], without using app_length. *)
Theorem app_length_cons_r : forall (X : Type) (l1 l2 : list X)
(x : X) (n : nat),
S (length (l1 ++ l2)) = n -> length (l1 ++ (x :: l2)) = n.
Proof.
intros.
generalize dependent n.
generalize dependent l2.
induction l1 as [| y ys].
Case "l1 = nil".
intros. simpl. simpl in H. apply H.
Case "l1 = cons".
intros. simpl. destruct n as [| n'].
inversion H.
apply eq_remove_S. apply IHys. simpl in H.
inversion H. reflexivity. Qed.
Theorem app_length_twice : forall (X:Type) (n:nat) (l:list X),
length l = n ->
length (l ++ l) = n + n.
Proof.
intros X n l.
generalize dependent n.
induction l.
simpl. intros n eq. inversion eq. reflexivity.
simpl. intros n eq. destruct n.
inversion eq.
simpl. inversion eq.
rewrite H0. rewrite <- plus_n_Sm.
apply eq_remove_S.
apply app_length_cons_r.
apply eq_remove_S.
apply IHl. apply H0. Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (double_induction) *)
(** Prove the following principle of induction over two naturals. *)
Theorem double_induction: forall (P : nat -> nat -> Prop),
P 0 0 ->
(forall m, P m 0 -> P (S m) 0) ->
(forall n, P 0 n -> P 0 (S n)) ->
(forall m n, P m n -> P (S m) (S n)) ->
forall m n, P m n.
Proof.
intros.
generalize dependent n.
generalize dependent P.
induction m as [| m'].
intros. induction n as [| n'].
apply H.
apply H1. apply IHn'.
intros. induction n as [| n'].
apply H0. apply IHm'. apply H. apply H0. apply H1. apply H2.
apply H2. apply IHm'. apply H. apply H0. apply H1. apply H2. Qed.
(** [] *)
(* ###################################################### *)
(** * Using [destruct] on Compound Expressions *)
(** We have seen many examples where the [destruct] tactic is
used to perform case analysis of the value of some variable. But
sometimes we need to reason by cases on the result of some
_expression_. We can also do this with [destruct].
Here are some examples: *)
Definition sillyfun (n : nat) : bool :=
if beq_nat n 3 then false
else if beq_nat n 5 then false
else false.
Theorem sillyfun_false : forall (n : nat),
sillyfun n = false.
Proof.
intros n. unfold sillyfun.
destruct (beq_nat n 3).
Case "beq_nat n 3 = true". reflexivity.
Case "beq_nat n 3 = false". destruct (beq_nat n 5).
SCase "beq_nat n 5 = true". reflexivity.
SCase "beq_nat n 5 = false". reflexivity. Qed.
(** After unfolding [sillyfun] in the above proof, we find that
we are stuck on [if (beq_nat n 3) then ... else ...]. Well,
either [n] is equal to [3] or it isn't, so we use [destruct
(beq_nat n 3)] to let us reason about the two cases.
In general, the [destruct] tactic can be used to perform case
analysis of the results of arbitrary computations. If [e] is an
expression whose type is some inductively defined type [T], then,
for each constructor [c] of [T], [destruct e] generates a subgoal
in which all occurrences of [e] (in the goal and in the context)
are replaced by [c].
*)
(** **** Exercise: 1 star (override_shadow) *)
Theorem override_shadow : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
(override (override f k1 x2) k1 x1) k2 = (override f k1 x1) k2.
Proof.
intros. unfold override. destruct (beq_nat k1 k2).
reflexivity. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (combine_split) *)
(** Complete the proof below *)
Theorem combine_split : forall X Y (l : list (X * Y)) l1 l2,
split l = (l1, l2) -> combine l1 l2 = l.
Proof.
intros X Y l.
induction l as [| x xs].
Case "l = nil".
intros. simpl in H. inversion H. reflexivity.
Case "l = cons".
intros l1 l2. simpl. destruct x. destruct (split xs).
destruct l1 as [| i is].
simpl. destruct l2 as [| j js].
intros. inversion H.
intros. inversion H.
simpl. destruct l2 as [| j js].
intros. inversion H.
intros. rewrite IHxs.
inversion H. reflexivity.
inversion H. reflexivity. Qed.
(** [] *)
(** Sometimes, doing a [destruct] on a compound expression (a
non-variable) will erase information we need to complete a proof. *)
(** For example, suppose
we define a function [sillyfun1] like this: *)
Definition sillyfun1 (n : nat) : bool :=
if beq_nat n 3 then true
else if beq_nat n 5 then true
else false.
(** And suppose that we want to convince Coq of the rather
obvious observation that [sillyfun1 n] yields [true] only when [n]
is odd. By analogy with the proofs we did with [sillyfun] above,
it is natural to start the proof like this: *)
Theorem sillyfun1_odd_FAILED : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3).
(* stuck... *)
Abort.
(** We get stuck at this point because the context does not
contain enough information to prove the goal! The problem is that
the substitution peformed by [destruct] is too brutal -- it threw
away every occurrence of [beq_nat n 3], but we need to keep some
memory of this expression and how it was destructed, because we
need to be able to reason that since, in this branch of the case
analysis, [beq_nat n 3 = true], it must be that [n = 3], from
which it follows that [n] is odd.
What we would really like is to substitute away all existing
occurences of [beq_nat n 3], but at the same time add an equation
to the context that records which case we are in. The [eqn:]
qualifier allows us to introduce such an equation (with whatever
name we choose). *)
Theorem sillyfun1_odd : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3) eqn:Heqe3.
(* Now we have the same state as at the point where we got stuck
above, except that the context contains an extra equality
assumption, which is exactly what we need to make progress. *)
Case "e3 = true". apply beq_nat_true in Heqe3.
rewrite -> Heqe3. reflexivity.
Case "e3 = false".
(* When we come to the second equality test in the body of the
function we are reasoning about, we can use [eqn:] again in the
same way, allow us to finish the proof. *)
destruct (beq_nat n 5) eqn:Heqe5.
SCase "e5 = true".
apply beq_nat_true in Heqe5.
rewrite -> Heqe5. reflexivity.
SCase "e5 = false". inversion eq. Qed.
(** **** Exercise: 2 stars (destruct_eqn_practice) *)
Theorem bool_fn_applied_thrice :
forall (f : bool -> bool) (b : bool),
f (f (f b)) = f b.
Proof.
intros. destruct b.
destruct (f true) eqn:Heqe.
rewrite Heqe. apply Heqe.
destruct (f false) eqn:Heqe2.
apply Heqe.
apply Heqe2.
destruct (f false) eqn:Heqe.
destruct (f true) eqn:Heqe2.
apply Heqe2.
apply Heqe.
rewrite Heqe. apply Heqe. Qed.
(** [] *)
(** **** Exercise: 2 stars (override_same) *)
Theorem override_same : forall (X:Type) x1 k1 k2 (f : nat->X),
f k1 = x1 -> (override f k1 x1) k2 = f k2.
Proof.
intros. unfold override. destruct (beq_nat k1 k2) eqn:Heqe.
rewrite <- H. apply beq_nat_true in Heqe.
inversion Heqe. reflexivity. reflexivity. Qed.
(** [] *)
(* ################################################################## *)
(** * Review *)
(** We've now seen a bunch of Coq's fundamental tactics. We'll
introduce a few more as we go along through the coming lectures,
and later in the course we'll introduce some more powerful
_automation_ tactics that make Coq do more of the low-level work
in many cases. But basically we've got what we need to get work
done.
Here are the ones we've seen:
- [intros]:
move hypotheses/variables from goal to context
- [reflexivity]:
finish the proof (when the goal looks like [e = e])
- [apply]:
prove goal using a hypothesis, lemma, or constructor
- [apply... in H]:
apply a hypothesis, lemma, or constructor to a hypothesis in
the context (forward reasoning)
- [apply... with...]:
explicitly specify values for variables that cannot be
determined by pattern matching
- [simpl]:
simplify computations in the goal
- [simpl in H]:
... or a hypothesis
- [rewrite]:
use an equality hypothesis (or lemma) to rewrite the goal
- [rewrite ... in H]:
... or a hypothesis
- [symmetry]:
changes a goal of the form [t=u] into [u=t]
- [symmetry in H]:
changes a hypothesis of the form [t=u] into [u=t]
- [unfold]:
replace a defined constant by its right-hand side in the goal
- [unfold... in H]:
... or a hypothesis
- [destruct... as...]:
case analysis on values of inductively defined types
- [destruct... eqn:...]:
specify the name of an equation to be added to the context,
recording the result of the case analysis
- [induction... as...]:
induction on values of inductively defined types
- [inversion]:
reason by injectivity and distinctness of constructors
- [assert (e) as H]:
introduce a "local lemma" [e] and call it [H]
- [generalize dependent x]:
move the variable [x] (and anything else that depends on it)
from the context back to an explicit hypothesis in the goal
formula
*)
(* ###################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (beq_nat_sym) *)
Theorem beq_nat_sym : forall (n m : nat),
beq_nat n m = beq_nat m n.
Proof.
intros.
generalize dependent m.
induction n as [| n'].
Case "n = 0".
destruct m as [| m'].
reflexivity. reflexivity.
Case "n = S n'".
destruct m as [| m'].
compute. reflexivity.
apply IHn'. Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (beq_nat_sym_informal) *)
(** Give an informal proof of this lemma that corresponds to your
formal proof above:
Theorem: For any [nat]s [n] [m], [beq_nat n m = beq_nat m n].
Proof:
SKIPPED
[]
*)
(** **** Exercise: 3 stars, optional (beq_nat_trans) *)
Theorem beq_nat_trans : forall n m p,
beq_nat n m = true ->
beq_nat m p = true ->
beq_nat n p = true.
Proof.
intros. apply beq_nat_true in H. apply beq_nat_true in H0.
rewrite H. rewrite <- H0. symmetry. apply beq_nat_refl. Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (split_combine) *)
(** We have just proven that for all lists of pairs, [combine] is the
inverse of [split]. How would you formalize the statement that
[split] is the inverse of [combine]?
Complete the definition of [split_combine_statement] below with a
property that states that [split] is the inverse of
[combine]. Then, prove that the property holds. (Be sure to leave
your induction hypothesis general by not doing [intros] on more
things than necessary. Hint: what property do you need of [l1]
and [l2] for [split] [combine l1 l2 = (l1,l2)] to be true?) *)
Definition split_combine_statement : Prop :=
forall (X : Type) (l1 l2 : list X),
length l1 = length l2 -> split (combine l1 l2) = (l1, l2).
Theorem split_combine : split_combine_statement.
Proof.
unfold split_combine_statement. intros X l1.
induction l1 as [| l1'].
Case "l1 = 0".
intros. destruct l2 as [| l2'].
reflexivity.
simpl. inversion H.
Case "l1 = S l1'".
intros. destruct l2 as [| l2'].
simpl. inversion H.
simpl. rewrite IHl1. reflexivity. inversion H. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars (override_permute) *)
Theorem override_permute : forall (X:Type) x1 x2 k1 k2 k3 (f : nat->X),
beq_nat k2 k1 = false ->
(override (override f k2 x2) k1 x1) k3 = (override (override f k1 x1) k2 x2) k3.
Proof.
intros. unfold override. destruct (beq_nat k1 k3) eqn:Heqe.
apply beq_nat_true in Heqe. rewrite <- Heqe. rewrite H. reflexivity.
destruct (beq_nat k2 k3) eqn:Heqe2. reflexivity. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (filter_exercise) *)
(** This one is a bit challenging. Pay attention to the form of your IH. *)
Theorem filter_exercise : forall (X : Type) (test : X -> bool)
(x : X) (l lf : list X),
filter test l = x :: lf ->
test x = true.
Proof.
intros. generalize dependent lf.
induction l as [| y ys].
Case "l = 0".
intros. inversion H.
Case "l = S l'".
simpl. intros. destruct (test y) eqn:Heqe.
inversion H. rewrite <- H1. apply Heqe.
apply IHys in H. apply H. Qed.
(** [] *)
(** **** Exercise: 4 stars, advanced (forall_exists_challenge) *)
(** Define two recursive [Fixpoints], [forallb] and [existsb]. The
first checks whether every element in a list satisfies a given
predicate:
forallb oddb [1;3;5;7;9] = true
forallb negb [false;false] = true
forallb evenb [0;2;4;5] = false
forallb (beq_nat 5) [] = true
The second checks whether there exists an element in the list that
satisfies a given predicate:
existsb (beq_nat 5) [0;2;3;6] = false
existsb (andb true) [true;true;false] = true
existsb oddb [1;0;0;0;0;3] = true
existsb evenb [] = false
Next, define a _nonrecursive_ version of [existsb] -- call it
[existsb'] -- using [forallb] and [negb].
Prove that [existsb'] and [existsb] have the same behavior.
*)
Fixpoint forallb {X : Type} (f : X -> bool) (l : list X) : bool :=
match l with
| nil => true
| cons x x0 => if f x then forallb f x0 else false
end.
Example test_forallb1: forallb oddb [1;3;5;7;9] = true.
Proof. reflexivity. Qed.
Example test_forallb2: forallb negb [false;false] = true.
Proof. reflexivity. Qed.
Example test_forallb3: forallb evenb [0;2;4;5] = false.
Proof. reflexivity. Qed.
Example test_forallb4: forallb (beq_nat 5) [] = true.
Proof. reflexivity. Qed.
Fixpoint existsb {X : Type} (f : X -> bool) (l : list X) : bool :=
match l with
| nil => false
| cons x x0 => if f x then true else existsb f x0
end.
Example test_existsb1: existsb (beq_nat 5) [0;2;3;6] = false.
Proof. reflexivity. Qed.
Example test_existsb2: existsb (andb true) [true;true;false] = true.
Proof. reflexivity. Qed.
Example test_existsb3: existsb oddb [1;0;0;0;0;3] = true.
Proof. reflexivity. Qed.
Example test_existsb4: existsb evenb [] = false.
Proof. reflexivity. Qed.
Definition existsb' {X : Type} (f : X -> bool) (l : list X) : bool :=
negb (forallb (fun x => negb (f x)) l).
Theorem existsb'_matches : forall {X : Type} (f : X -> bool) (l : list X),
existsb f l = existsb' f l.
Proof.
intros. induction l as [| l'].
Case "l = 0".
reflexivity.
Case "l = S l'".
simpl. rewrite IHl. unfold existsb'. unfold forallb.
destruct (f l'). reflexivity. reflexivity. Qed.
(** [] *)
(* $Date: 2014-02-04 07:15:43 -0500 (Tue, 04 Feb 2014) $ *)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/12/2016 06:18:20 PM
// Design Name:
// Module Name: Mux_Array
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Mux_Array
#(parameter SWR=26, parameter EWR=5)
(
input wire clk,
input wire rst,
input wire load_i,
input wire [SWR-1:0] Data_i,
input wire FSM_left_right_i,
input wire [EWR-1:0] Shift_Value_i,
input wire bit_shift_i,
output wire [SWR-1:0] Data_o
);
////
wire [SWR-1:0] Data_array[EWR+1:0];
//////////////////7
genvar k;//Level
///////////////////77777
Rotate_Mux_Array #(.SWR(SWR)) first_rotate(
.Data_i(Data_i),
.select_i(FSM_left_right_i),
.Data_o(Data_array [0][SWR-1:0])
);
generate for (k=0; k < 3; k=k+1) begin
shift_mux_array #(.SWR(SWR), .LEVEL(k)) shift_mux_array(
.Data_i(Data_array[k]),
.select_i(Shift_Value_i[k]),
.bit_shift_i(bit_shift_i),
.Data_o(Data_array[k+1])
);
end
endgenerate
RegisterAdd #(.W(SWR)) Mid_Reg(
.clk(clk),
.rst(rst),
.load(1'b1),
.D(Data_array[3]),
.Q(Data_array[4])
);
generate for (k=3; k < EWR; k=k+1) begin
shift_mux_array #(.SWR(SWR), .LEVEL(k)) shift_mux_array(
.Data_i(Data_array[k+1]),
.select_i(Shift_Value_i[k]),
.bit_shift_i(bit_shift_i),
.Data_o(Data_array[k+2])
);
end
endgenerate
Rotate_Mux_Array #(.SWR(SWR)) last_rotate(
.Data_i(Data_array[EWR+1]),
.select_i(FSM_left_right_i),
.Data_o(Data_o)
);
endmodule
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module accum32 (
data,
clock,
clken,
aclr,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] data;
input clock;
input clken;
input aclr;
output [31:0] result;
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
`include "def_axi.vh"
module m_axi_read # (
parameter C_M_AXI_ADDR_WIDTH = 32,
parameter C_M_AXI_DATA_WIDTH = 64,
parameter C_M_AXI_ID_WIDTH = 1,
parameter C_M_AXI_ARUSER_WIDTH = 1,
parameter C_M_AXI_RUSER_WIDTH = 1
)
(
////////////////////////////////////////////////////////////////
//AXI4 master read channel signals
input m_axi_aclk,
input m_axi_aresetn,
// Read address channel
output [C_M_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_M_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [7:0] m_axi_arlen,
output [2:0] m_axi_arsize,
output [1:0] m_axi_arburst,
output [1:0] m_axi_arlock,
output [3:0] m_axi_arcache,
output [2:0] m_axi_arprot,
output [3:0] m_axi_arregion,
output [3:0] m_axi_arqos,
output [C_M_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
// Read data channel
input [C_M_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_M_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [1:0] m_axi_rresp,
input m_axi_rlast,
input [C_M_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
output m_axi_rresp_err,
output dev_tx_cmd_rd_en,
input [29:0] dev_tx_cmd_rd_data,
input dev_tx_cmd_empty_n,
output pcie_tx_fifo_alloc_en,
output [9:4] pcie_tx_fifo_alloc_len,
output pcie_tx_fifo_wr_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
input pcie_tx_fifo_full_n
);
localparam LP_AR_DELAY = 7;
localparam S_IDLE = 8'b00000001;
localparam S_CMD_0 = 8'b00000010;
localparam S_CMD_1 = 8'b00000100;
localparam S_WAIT_FULL_N = 8'b00001000;
localparam S_AR_REQ = 8'b00010000;
localparam S_AR_WAIT = 8'b00100000;
localparam S_AR_DONE = 8'b01000000;
localparam S_AR_DELAY = 8'b10000000;
reg [7:0] cur_state;
reg [7:0] next_state;
reg [31:2] r_dev_addr;
reg [12:2] r_dev_dma_len;
reg [9:2] r_dev_cur_len;
reg [9:2] r_m_axi_arlen;
reg [4:0] r_ar_delay;
reg r_dev_tx_cmd_rd_en;
reg r_pcie_tx_fifo_alloc_en;
wire w_axi_ar_req_gnt;
reg [2:0] r_axi_ar_req_gnt;
reg r_axi_ar_req;
reg r_m_axi_arvalid;
reg [C_M_AXI_DATA_WIDTH-1 : 0] r_m_axi_rdata;
reg r_m_axi_rlast;
//reg r_m_axi_rlast_d1;
//wire w_m_axi_rlast;
reg r_m_axi_rvalid;
reg [C_M_AXI_ID_WIDTH-1:0] r_m_axi_rid;
reg [1:0] r_m_axi_rresp;
reg r_m_axi_rresp_err;
reg r_m_axi_rresp_err_d1;
reg r_m_axi_rresp_err_d2;
assign m_axi_arid = 0;
assign m_axi_araddr = {r_dev_addr, 2'b0};
assign m_axi_arlen = {1'b0, r_m_axi_arlen[9:3]};
assign m_axi_arsize = `D_AXSIZE_008_BYTES;
assign m_axi_arburst = `D_AXBURST_INCR;
assign m_axi_arlock = `D_AXLOCK_NORMAL;
assign m_axi_arcache = `D_AXCACHE_NON_CACHE;
assign m_axi_arprot = `D_AXPROT_SECURE;
assign m_axi_arregion = 0;
assign m_axi_arqos = 0;
assign m_axi_aruser = 0;
assign m_axi_arvalid = r_m_axi_arvalid;
assign m_axi_rready = 1;
assign m_axi_rresp_err = r_m_axi_rresp_err_d2;
assign dev_tx_cmd_rd_en = r_dev_tx_cmd_rd_en;
assign pcie_tx_fifo_alloc_en = r_pcie_tx_fifo_alloc_en;
assign pcie_tx_fifo_alloc_len = r_dev_cur_len[9:4];
assign pcie_tx_fifo_wr_en = r_m_axi_rvalid;
assign pcie_tx_fifo_wr_data = r_m_axi_rdata;
always @ (posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(m_axi_aresetn == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(dev_tx_cmd_empty_n == 1)
next_state <= S_CMD_0;
else
next_state <= S_IDLE;
end
S_CMD_0: begin
next_state <= S_CMD_1;
end
S_CMD_1: begin
next_state <= S_WAIT_FULL_N;
end
S_WAIT_FULL_N: begin
if(pcie_tx_fifo_full_n == 1 && w_axi_ar_req_gnt == 1)
next_state <= S_AR_REQ;
else
next_state <= S_WAIT_FULL_N;
end
S_AR_REQ: begin
if(m_axi_arready == 1)
next_state <= S_AR_DONE;
else
next_state <= S_AR_WAIT;
end
S_AR_WAIT: begin
if(m_axi_arready == 1)
next_state <= S_AR_DONE;
else
next_state <= S_AR_WAIT;
end
S_AR_DONE: begin
if(r_dev_dma_len == 0)
next_state <= S_IDLE;
else
next_state <= S_AR_DELAY;
end
S_AR_DELAY: begin
if(r_ar_delay == 0)
next_state <= S_WAIT_FULL_N;
else
next_state <= S_AR_DELAY;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge m_axi_aclk)
begin
case(cur_state)
S_IDLE: begin
end
S_CMD_0: begin
r_dev_dma_len <= {dev_tx_cmd_rd_data[10:2], 2'b0};
end
S_CMD_1: begin
if(r_dev_dma_len[8:2] == 0)
r_dev_cur_len[9] <= 1;
else
r_dev_cur_len[9] <= 0;
r_dev_cur_len[8:2] <= r_dev_dma_len[8:2];
r_dev_addr <= {dev_tx_cmd_rd_data[29:2], 2'b0};
end
S_WAIT_FULL_N: begin
r_m_axi_arlen <= r_dev_cur_len - 2;
end
S_AR_REQ: begin
r_dev_dma_len <= r_dev_dma_len - r_dev_cur_len;
end
S_AR_WAIT: begin
end
S_AR_DONE: begin
r_dev_cur_len <= 8'h80;
r_dev_addr <= r_dev_addr + r_dev_cur_len;
r_ar_delay <= LP_AR_DELAY;
end
S_AR_DELAY: begin
r_ar_delay <= r_ar_delay - 1;
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_CMD_0: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 1;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_CMD_1: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 1;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_WAIT_FULL_N: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_AR_REQ: begin
r_m_axi_arvalid <= 1;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 1;
r_axi_ar_req <= 1;
end
S_AR_WAIT: begin
r_m_axi_arvalid <= 1;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_AR_DONE: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_AR_DELAY: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
default: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
endcase
end
//assign w_m_axi_rlast = r_m_axi_rlast & ~r_m_axi_rlast_d1;
always @ (posedge m_axi_aclk)
begin
r_m_axi_rid <= m_axi_rid;
r_m_axi_rdata <= m_axi_rdata;
r_m_axi_rlast <= m_axi_rlast & m_axi_rvalid;
//r_m_axi_rlast_d1 <= r_m_axi_rlast;
r_m_axi_rvalid <= m_axi_rvalid;
r_m_axi_rresp <= m_axi_rresp;
r_m_axi_rresp_err_d1 <= r_m_axi_rresp_err;
r_m_axi_rresp_err_d2 <= r_m_axi_rresp_err | r_m_axi_rresp_err_d1;
end
always @ (*)
begin
if(r_m_axi_rvalid == 1 && (r_m_axi_rresp != `D_AXI_RESP_OKAY || r_m_axi_rid != 0))
r_m_axi_rresp_err <= 1;
else
r_m_axi_rresp_err <= 0;
end
assign w_axi_ar_req_gnt = r_axi_ar_req_gnt[2];
always @ (posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(m_axi_aresetn == 0) begin
r_axi_ar_req_gnt <= 3'b110;
end
else begin
case({r_m_axi_rlast, r_axi_ar_req})
2'b01: begin
r_axi_ar_req_gnt <= {r_axi_ar_req_gnt[1:0], r_axi_ar_req_gnt[2]};
end
2'b10: begin
r_axi_ar_req_gnt <= {r_axi_ar_req_gnt[0], r_axi_ar_req_gnt[2:1]};
end
default: begin
end
endcase
end
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O41AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__O41AI_BEHAVIORAL_PP_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o41ai (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O41AI_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hvl__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( RESET_B_delayed === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) & cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) & cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) & cond0 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_V |
// $Id: vcr_alloc_mac.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// VC and switch allocators for VC router
//==============================================================================
module vcr_alloc_mac
(clk, reset, route_ip_ivc_op, route_ip_ivc_orc, allocated_ip_ivc,
flit_valid_ip_ivc, flit_head_ip_ivc, flit_tail_ip_ivc, elig_op_ovc,
free_nonspec_ip_ivc, vc_active_op, vc_gnt_ip_ivc, vc_sel_ip_ivc_ovc,
vc_gnt_op_ovc, vc_sel_op_ovc_ip, vc_sel_op_ovc_ivc, sw_active_op,
sw_gnt_ip, sw_sel_ip_ivc, sw_gnt_op, sw_sel_op_ip, sw_sel_op_ivc,
flit_head_op, flit_tail_op, xbr_ctrl_op_ip);
`include "c_functions.v"
`include "c_constants.v"
`include "vcr_constants.v"
// number of message classes (e.g. request, reply)
parameter num_message_classes = 2;
// number of resource classes (e.g. minimal, adaptive)
parameter num_resource_classes = 2;
// total number of packet classes
localparam num_packet_classes = num_message_classes * num_resource_classes;
// number of VCs per class
parameter num_vcs_per_class = 1;
// number of VCs
localparam num_vcs = num_packet_classes * num_vcs_per_class;
// number of input and output ports on router
parameter num_ports = 5;
// width required to select an individual port
localparam port_idx_width = clogb(num_ports);
// select implementation variant for VC allocator
parameter vc_allocator_type = `SW_ALLOC_TYPE_SEP_IF;
// select which arbiter type to use in VC allocator
parameter vc_arbiter_type = `ARBITER_TYPE_ROUND_ROBIN_BINARY;
// select implementation variant for VC switch allocator
parameter sw_allocator_type = `VC_ALLOC_TYPE_SEP_IF;
// select which arbiter type to use in switch allocator
parameter sw_arbiter_type = `ARBITER_TYPE_ROUND_ROBIN_BINARY;
// select speculation type
parameter spec_type = `SW_ALLOC_SPEC_TYPE_REQ;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// destination port selects
input [0:num_ports*num_vcs*num_ports-1] route_ip_ivc_op;
// select next resource class
input [0:num_ports*num_vcs*num_resource_classes-1] route_ip_ivc_orc;
// VC has output VC allocated to it
input [0:num_ports*num_vcs-1] allocated_ip_ivc;
// VC has flit available
input [0:num_ports*num_vcs-1] flit_valid_ip_ivc;
// flit is head flit
input [0:num_ports*num_vcs-1] flit_head_ip_ivc;
// flit is tail flit
input [0:num_ports*num_vcs-1] flit_tail_ip_ivc;
// output VC is eligible for allocation (i.e., not currently allocated)
input [0:num_ports*num_vcs-1] elig_op_ovc;
// credit availability if output VC has been allocated
input [0:num_ports*num_vcs-1] free_nonspec_ip_ivc;
// VC allocation activity (to output controller)
output [0:num_ports-1] vc_active_op;
wire [0:num_ports-1] vc_active_op;
// VC allocation successful (to input controller)
output [0:num_ports*num_vcs-1] vc_gnt_ip_ivc;
wire [0:num_ports*num_vcs-1] vc_gnt_ip_ivc;
// granted output VC (to input controller)
output [0:num_ports*num_vcs*num_vcs-1] vc_sel_ip_ivc_ovc;
wire [0:num_ports*num_vcs*num_vcs-1] vc_sel_ip_ivc_ovc;
// output VC was granted (to output controller)
output [0:num_ports*num_vcs-1] vc_gnt_op_ovc;
wire [0:num_ports*num_vcs-1] vc_gnt_op_ovc;
// input port that each output VC was granted to (to output controller)
output [0:num_ports*num_vcs*num_ports-1] vc_sel_op_ovc_ip;
wire [0:num_ports*num_vcs*num_ports-1] vc_sel_op_ovc_ip;
// input VC that each output VC was granted to (to output controller)
output [0:num_ports*num_vcs*num_vcs-1] vc_sel_op_ovc_ivc;
wire [0:num_ports*num_vcs*num_vcs-1] vc_sel_op_ovc_ivc;
// switch allocation activity (to output controller)
output [0:num_ports-1] sw_active_op;
wire [0:num_ports-1] sw_active_op;
// port grants (to input controller)
output [0:num_ports-1] sw_gnt_ip;
wire [0:num_ports-1] sw_gnt_ip;
// indicate which VC at a given port is granted (to input controller)
output [0:num_ports*num_vcs-1] sw_sel_ip_ivc;
wire [0:num_ports*num_vcs-1] sw_sel_ip_ivc;
// output port grants
output [0:num_ports-1] sw_gnt_op;
wire [0:num_ports-1] sw_gnt_op;
// selected output ports for grants
output [0:num_ports*num_ports-1] sw_sel_op_ip;
wire [0:num_ports*num_ports-1] sw_sel_op_ip;
// selected output VCs for grants
output [0:num_ports*num_vcs-1] sw_sel_op_ivc;
wire [0:num_ports*num_vcs-1] sw_sel_op_ivc;
// which grants are for head flits
output [0:num_ports-1] flit_head_op;
wire [0:num_ports-1] flit_head_op;
// which grants are for tail flits
output [0:num_ports-1] flit_tail_op;
wire [0:num_ports-1] flit_tail_op;
// crossbar control signals
output [0:num_ports*num_ports-1] xbr_ctrl_op_ip;
wire [0:num_ports*num_ports-1] xbr_ctrl_op_ip;
wire [0:num_ports*num_vcs-1] vc_req_ip_ivc;
assign vc_req_ip_ivc = flit_valid_ip_ivc & ~allocated_ip_ivc;
wire [0:num_ports-1] vc_active_ip;
c_reduce_bits
#(.num_ports(num_ports),
.width(num_vcs),
.op(`BINARY_OP_OR))
vc_active_ip_rb
(.data_in(vc_req_ip_ivc),
.data_out(vc_active_ip));
c_select_mofn
#(.num_ports(num_ports*num_vcs),
.width(num_ports))
vc_active_op_sel
(.select(vc_req_ip_ivc),
.data_in(route_ip_ivc_op),
.data_out(vc_active_op));
generate
if(vc_allocator_type == `VC_ALLOC_TYPE_SEP_IF)
begin
vcr_vc_alloc_sep_if
#(.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_ports(num_ports),
.arbiter_type(vc_arbiter_type),
.reset_type(reset_type))
vc_core_sep_if
(.clk(clk),
.reset(reset),
.active_ip(vc_active_ip),
.active_op(vc_active_op),
.route_ip_ivc_op(route_ip_ivc_op),
.route_ip_ivc_orc(route_ip_ivc_orc),
.elig_op_ovc(elig_op_ovc),
.req_ip_ivc(vc_req_ip_ivc),
.gnt_ip_ivc(vc_gnt_ip_ivc),
.sel_ip_ivc_ovc(vc_sel_ip_ivc_ovc),
.gnt_op_ovc(vc_gnt_op_ovc),
.sel_op_ovc_ip(vc_sel_op_ovc_ip),
.sel_op_ovc_ivc(vc_sel_op_ovc_ivc));
end
else if(vc_allocator_type == `VC_ALLOC_TYPE_SEP_OF)
begin
vcr_vc_alloc_sep_of
#(.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_ports(num_ports),
.arbiter_type(vc_arbiter_type),
.reset_type(reset_type))
vc_core_sep_of
(.clk(clk),
.reset(reset),
.active_ip(vc_active_ip),
.active_op(vc_active_op),
.route_ip_ivc_op(route_ip_ivc_op),
.route_ip_ivc_orc(route_ip_ivc_orc),
.elig_op_ovc(elig_op_ovc),
.req_ip_ivc(vc_req_ip_ivc),
.gnt_ip_ivc(vc_gnt_ip_ivc),
.sel_ip_ivc_ovc(vc_sel_ip_ivc_ovc),
.gnt_op_ovc(vc_gnt_op_ovc),
.sel_op_ovc_ip(vc_sel_op_ovc_ip),
.sel_op_ovc_ivc(vc_sel_op_ovc_ivc));
end
else if((vc_allocator_type >= `VC_ALLOC_TYPE_WF_BASE) &&
(vc_allocator_type <= `VC_ALLOC_TYPE_WF_LIMIT))
begin
wire vc_active;
assign vc_active = |vc_active_ip;
vcr_vc_alloc_wf
#(.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_ports(num_ports),
.wf_alloc_type(vc_allocator_type - `VC_ALLOC_TYPE_WF_BASE),
.reset_type(reset_type))
vc_core_wf
(.clk(clk),
.reset(reset),
.active(vc_active),
.route_ip_ivc_op(route_ip_ivc_op),
.route_ip_ivc_orc(route_ip_ivc_orc),
.elig_op_ovc(elig_op_ovc),
.req_ip_ivc(vc_req_ip_ivc),
.gnt_ip_ivc(vc_gnt_ip_ivc),
.sel_ip_ivc_ovc(vc_sel_ip_ivc_ovc),
.gnt_op_ovc(vc_gnt_op_ovc),
.sel_op_ovc_ip(vc_sel_op_ovc_ip),
.sel_op_ovc_ivc(vc_sel_op_ovc_ivc));
end
endgenerate
wire [0:num_ports*num_vcs-1] sw_req_nonspec_ip_ivc;
assign sw_req_nonspec_ip_ivc
= allocated_ip_ivc & flit_valid_ip_ivc & free_nonspec_ip_ivc;
wire [0:num_ports*num_vcs-1] sw_req_spec_ip_ivc;
assign sw_req_spec_ip_ivc = ~allocated_ip_ivc & flit_valid_ip_ivc;
wire [0:num_ports-1] sw_active_ip;
c_reduce_bits
#(.num_ports(num_ports),
.width(num_vcs),
.op(`BINARY_OP_OR))
sw_active_ip_rb
(.data_in(flit_valid_ip_ivc),
.data_out(sw_active_ip));
c_select_mofn
#(.num_ports(num_ports*num_vcs),
.width(num_ports))
sw_active_op_sel
(.select(flit_valid_ip_ivc),
.data_in(route_ip_ivc_op),
.data_out(sw_active_op));
generate
if(sw_allocator_type == `SW_ALLOC_TYPE_SEP_IF)
begin
vcr_sw_alloc_sep_if
#(.num_vcs(num_vcs),
.num_ports(num_ports),
.arbiter_type(sw_arbiter_type),
.spec_type(spec_type),
.reset_type(reset_type))
sw_core_sep_if
(.clk(clk),
.reset(reset),
.active_ip(sw_active_ip),
.active_op(sw_active_op),
.route_ip_ivc_op(route_ip_ivc_op),
.req_nonspec_ip_ivc(sw_req_nonspec_ip_ivc),
.req_spec_ip_ivc(sw_req_spec_ip_ivc),
.sel_ip_ivc(sw_sel_ip_ivc),
.gnt_ip(sw_gnt_ip),
.gnt_op(sw_gnt_op),
.sel_op_ip(sw_sel_op_ip),
.sel_op_ivc(sw_sel_op_ivc));
end
else if(sw_allocator_type == `SW_ALLOC_TYPE_SEP_OF)
begin
vcr_sw_alloc_sep_of
#(.num_vcs(num_vcs),
.num_ports(num_ports),
.arbiter_type(sw_arbiter_type),
.spec_type(spec_type),
.reset_type(reset_type))
sw_core_sep_of
(.clk(clk),
.reset(reset),
.active_ip(sw_active_ip),
.active_op(sw_active_op),
.route_ip_ivc_op(route_ip_ivc_op),
.req_nonspec_ip_ivc(sw_req_nonspec_ip_ivc),
.req_spec_ip_ivc(sw_req_spec_ip_ivc),
.sel_ip_ivc(sw_sel_ip_ivc),
.gnt_ip(sw_gnt_ip),
.gnt_op(sw_gnt_op),
.sel_op_ip(sw_sel_op_ip),
.sel_op_ivc(sw_sel_op_ivc));
end
else if((sw_allocator_type >= `SW_ALLOC_TYPE_WF_BASE) &&
(sw_allocator_type <= `SW_ALLOC_TYPE_WF_LIMIT))
begin
vcr_sw_alloc_wf
#(.num_vcs(num_vcs),
.num_ports(num_ports),
.wf_alloc_type(sw_allocator_type - `SW_ALLOC_TYPE_WF_BASE),
.arbiter_type(sw_arbiter_type),
.spec_type(spec_type),
.reset_type(reset_type))
sw_core_wf
(.clk(clk),
.reset(reset),
.active_ip(sw_active_ip),
.route_ip_ivc_op(route_ip_ivc_op),
.req_nonspec_ip_ivc(sw_req_nonspec_ip_ivc),
.req_spec_ip_ivc(sw_req_spec_ip_ivc),
.sel_ip_ivc(sw_sel_ip_ivc),
.gnt_ip(sw_gnt_ip),
.gnt_op(sw_gnt_op),
.sel_op_ip(sw_sel_op_ip),
.sel_op_ivc(sw_sel_op_ivc));
end
endgenerate
wire [0:num_ports-1] flit_head_ip;
wire [0:num_ports-1] flit_tail_ip;
genvar ip;
generate
for(ip = 0; ip < num_ports; ip = ip + 1)
begin:ips
wire [0:num_vcs-1] sw_sel_ivc;
assign sw_sel_ivc = sw_sel_ip_ivc[ip*num_vcs:(ip+1)*num_vcs-1];
wire [0:num_vcs-1] flit_head_ivc;
assign flit_head_ivc = flit_head_ip_ivc[ip*num_vcs:(ip+1)*num_vcs-1];
wire flit_head;
c_select_1ofn
#(.num_ports(num_vcs),
.width(1))
flit_head_sel
(.select(sw_sel_ivc),
.data_in(flit_head_ivc),
.data_out(flit_head));
assign flit_head_ip[ip] = flit_head;
wire [0:num_vcs-1] flit_tail_ivc;
assign flit_tail_ivc = flit_tail_ip_ivc[ip*num_vcs:(ip+1)*num_vcs-1];
wire flit_tail;
c_select_1ofn
#(.num_ports(num_vcs),
.width(1))
flit_tail_sel
(.select(sw_sel_ivc),
.data_in(flit_tail_ivc),
.data_out(flit_tail));
assign flit_tail_ip[ip] = flit_tail;
end
endgenerate
genvar op;
generate
for(op = 0; op < num_ports; op = op + 1)
begin:ops
wire [0:num_ports-1] sw_sel_ip;
assign sw_sel_ip = sw_sel_op_ip[op*num_ports:(op+1)*num_ports-1];
wire flit_head;
c_select_1ofn
#(.num_ports(num_ports),
.width(1))
flit_head_sel
(.select(sw_sel_ip),
.data_in(flit_head_ip),
.data_out(flit_head));
assign flit_head_op[op] = flit_head;
wire flit_tail;
c_select_1ofn
#(.num_ports(num_ports),
.width(1))
flit_tail_sel
(.select(sw_sel_ip),
.data_in(flit_tail_ip),
.data_out(flit_tail));
assign flit_tail_op[op] = flit_tail;
wire [0:num_ports-1] xbr_ctrl_ip;
wire sw_active;
assign sw_active = sw_active_op[op];
wire active;
assign active = sw_active | (|xbr_ctrl_ip);
wire [0:num_ports-1] xbr_ctrl_ip_s, xbr_ctrl_ip_q;
assign xbr_ctrl_ip_s = sw_sel_ip;
c_dff
#(.width(num_ports),
.reset_type(reset_type))
xbr_ctrl_ipq
(.clk(clk),
.reset(reset),
.active(active),
.d(xbr_ctrl_ip_s),
.q(xbr_ctrl_ip_q));
assign xbr_ctrl_ip = xbr_ctrl_ip_q;
assign xbr_ctrl_op_ip[op*num_ports:(op+1)*num_ports-1] = xbr_ctrl_ip;
end
endgenerate
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: wdata_mux.v
//
// Description:
// Contains MI-side write command queue.
// SI-slot index selected by AW arbiter is pushed onto queue when S_AVALID transfer is received.
// Queue is popped when WLAST data beat is transferred.
// W-channel input from SI-slot selected by queue output is transferred to MI-side output .
//--------------------------------------------------------------------------
//
// Structure:
// wdata_mux
// axic_reg_srl_fifo
// mux_enc
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_wdata_mux #
(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of W-channel payload.
parameter integer C_NUM_SLAVE_SLOTS = 1, // Number of S_* ports.
parameter integer C_SELECT_WIDTH = 1, // Width of ASELECT.
parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_WMESG_WIDTH-1:0] S_WMESG,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_WLAST,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_WVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_WREADY,
// Master Data Ports
output wire [C_WMESG_WIDTH-1:0] M_WMESG,
output wire M_WLAST,
output wire M_WVALID,
input wire M_WREADY,
// Write Command Ports
input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // SI-slot index from AW arbiter
input wire S_AVALID,
output wire S_AREADY
);
localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32
// Decode select input to 1-hot
function [C_NUM_SLAVE_SLOTS-1:0] f_decoder (
input [C_SELECT_WIDTH-1:0] sel
);
integer i;
begin
for (i=0; i<C_NUM_SLAVE_SLOTS; i=i+1) begin
f_decoder[i] = (sel == i);
end
end
endfunction
wire m_valid_i;
wire m_last_i;
wire [C_NUM_SLAVE_SLOTS-1:0] m_select_hot;
wire [C_SELECT_WIDTH-1:0] m_select_enc;
wire m_avalid;
wire m_aready;
generate
if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux
// SI-side write command queue
axi_data_fifo_v2_1_axic_reg_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (C_SELECT_WIDTH),
.C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG),
.C_USE_FULL (0)
)
wmux_aw_fifo
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (S_ASELECT),
.S_VALID (S_AVALID),
.S_READY (S_AREADY),
.M_MESG (m_select_enc),
.M_VALID (m_avalid),
.M_READY (m_aready)
);
assign m_select_hot = f_decoder(m_select_enc);
// Instantiate MUX
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_SLAVE_SLOTS),
.C_SEL_WIDTH (C_SELECT_WIDTH),
.C_DATA_WIDTH (C_WMESG_WIDTH)
) mux_w
(
.S (m_select_enc),
.A (S_WMESG),
.O (M_WMESG),
.OE (1'b1)
);
assign m_last_i = |(S_WLAST & m_select_hot);
assign m_valid_i = |(S_WVALID & m_select_hot);
assign m_aready = m_valid_i & m_avalid & m_last_i & M_WREADY;
assign M_WLAST = m_last_i;
assign M_WVALID = m_valid_i & m_avalid;
assign S_WREADY = m_select_hot & {C_NUM_SLAVE_SLOTS{m_avalid & M_WREADY}};
end else begin : gen_no_wmux
assign S_AREADY = 1'b1;
assign M_WVALID = S_WVALID;
assign S_WREADY = M_WREADY;
assign M_WLAST = S_WLAST;
assign M_WMESG = S_WMESG;
end
endgenerate
endmodule
`default_nettype wire
|
module dest_shift_reg (
alu_vgpr_dest_data,
alu_sgpr_dest_data,
alu_dest_vcc_value,
alu_dest_exec_value,
dest_buffer_wr_en,
dest_buffer_shift_en,
vgpr_dest_data,
sgpr_dest_data,
exec_wr_vcc_value,
vgpr_wr_mask,
clk,
rst
);
input [511:0] alu_vgpr_dest_data;
input [15:0] alu_sgpr_dest_data;
input [15:0] alu_dest_vcc_value;
input [15:0] alu_dest_exec_value;
input dest_buffer_wr_en;
input dest_buffer_shift_en;
output [2047:0] vgpr_dest_data;
output [63:0] sgpr_dest_data;
output [63:0] exec_wr_vcc_value;
output [63:0] vgpr_wr_mask;
input clk;
input rst;
shift_out #(32) vgpr_dest_shift(
.data_in(alu_vgpr_dest_data),
.wr_en(dest_buffer_wr_en),
.shift_en(dest_buffer_shift_en),
.data_out(vgpr_dest_data),
.clk(clk),
.rst(rst)
);
shift_out #(1) sgpr_dest_shift(
.data_in(alu_sgpr_dest_data),
.wr_en(dest_buffer_wr_en),
.shift_en(dest_buffer_shift_en),
.data_out(sgpr_dest_data),
.clk(clk),
.rst(rst)
);
shift_out #(1) exec_shift(
.data_in(alu_dest_exec_value),
.wr_en(dest_buffer_wr_en),
.shift_en(dest_buffer_shift_en),
.data_out(vgpr_wr_mask),
.clk(clk),
.rst(rst)
);
shift_out #(1) vcc_shift(
.data_in(alu_dest_vcc_value),
.wr_en(dest_buffer_wr_en),
.shift_en(dest_buffer_shift_en),
.data_out(exec_wr_vcc_value),
.clk(clk),
.rst(rst)
);
endmodule
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_mac.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_mac.v,v $
//
// $Revision: #1 $
// $Date: 2010/04/12 $
// Check in by : $Author: max $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet
//
// Description :
//
// Top level module for Triple Speed Ethernet MAC
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_mac /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
clk, // Avalon slave - clock
read, // Avalon slave - read
write, // Avalon slave - write
address, // Avalon slave - address
writedata, // Avalon slave - writedata
readdata, // Avalon slave - readdata
waitrequest, // Avalon slave - waitrequest
reset, // Avalon slave - reset
reset_rx_clk,
reset_tx_clk,
reset_ff_rx_clk,
reset_ff_tx_clk,
ff_rx_clk, // AtlanticII source - clk
ff_rx_data, // AtlanticII source - data
ff_rx_mod, // Will not exists in SoPC Model as the 8-bit version is used
ff_rx_sop, // AtlanticII source - startofpacket
ff_rx_eop, // AtlanticII source - endofpacket
rx_err, // AtlanticII source - error
rx_err_stat, // AtlanticII source - component_specific_signal(eop)
rx_frm_type, // AtlanticII source - component_specific_signal(data)
ff_rx_rdy, // AtlanticII source - ready
ff_rx_dval, // AtlanticII source - valid
ff_rx_dsav, // AtlanticII source - component_specific_signal(data)
ff_tx_clk, // AtlanticII sink - clk
ff_tx_data, // AtlanticII sink - data
ff_tx_mod, // Will not exists in SoPC Model as the 8-bit version is used
ff_tx_sop, // AtlanticII sink - startofpacket
ff_tx_eop, // AtlanticII sink - endofpacket
ff_tx_err, // AtlanticII sink - error
ff_tx_wren, // AtlanticII sink - valid
ff_tx_crc_fwd, // AtlanticII sink - component_specific_signal(eop)
ff_tx_rdy, // AtlanticII sink - ready
ff_tx_septy, // AtlanticII source - component_specific_signal(data)
tx_ff_uflow, // AtlanticII source - component_specific_signal(data)
ff_rx_a_full,
ff_rx_a_empty,
ff_tx_a_full,
ff_tx_a_empty,
xoff_gen,
xon_gen,
magic_sleep_n,
magic_wakeup,
rx_clk,
tx_clk,
gm_rx_d,
gm_rx_dv,
gm_rx_err,
gm_tx_d,
gm_tx_en,
gm_tx_err,
m_rx_d,
m_rx_en,
m_rx_err,
m_tx_d,
m_tx_en,
m_tx_err,
m_rx_crs,
m_rx_col,
eth_mode,
ena_10,
set_10,
set_1000,
mdc,
mdio_in,
mdio_out,
mdio_oen,
tx_control,
rx_control,
rgmii_in,
rgmii_out
);
parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1; // ENA_HASH Enable Hash Table
parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
parameter EG_FIFO = 256 ; // Egress FIFO Depth
parameter EG_ADDR = 8 ; // Egress FIFO Depth
parameter ING_FIFO = 256 ; // Ingress FIFO Depth
parameter ING_ADDR = 8 ; // Egress FIFO Depth
parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3; // ALTERA Core Version
parameter CUST_VERSION = 1 ; // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 1; // Enable the RGMII Interface
parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
parameter ENABLE_MIN_FIFO = 1; // Enable minimun FIFO (Reduced functionality)
parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
parameter RAM_TYPE = "AUTO"; // Specify the RAM type
parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
input clk; // 25MHz Host Interface Clock
input read; // Register Read Strobe
input write; // Register Write Strobe
input [7:0] address; // Register Address
input [31:0] writedata; // Write Data for Host Bus
output [31:0] readdata; // Read Data to Host Bus
output waitrequest; // Interface Busy
input reset; // Asynchronous Reset
input reset_rx_clk; // Asynchronous Reset - rx_clk Domain
input reset_tx_clk; // Asynchronous Reset - tx_clk Domain
input reset_ff_rx_clk; // Asynchronous Reset - ff_rx_clk Domain
input reset_ff_tx_clk; // Asynchronous Reset - ff_tx_clk Domain
input ff_rx_clk; // Transmit Local Clock
output [ENABLE_ENA-1:0] ff_rx_data; // Data Out
output [1:0] ff_rx_mod; // Data Modulo
output ff_rx_sop; // Start of Packet
output ff_rx_eop; // End of Packet
output [5:0] rx_err; // Errored Packet Indication
output [17:0] rx_err_stat; // Packet Length and Status Word
output [3:0] rx_frm_type; // Unicast Frame Indication
input ff_rx_rdy; // PHY Application Ready
output ff_rx_dval; // Data Valid Strobe
output ff_rx_dsav; // Data Available
input ff_tx_clk; // Transmit Local Clock
input [ENABLE_ENA-1:0] ff_tx_data; // Data Out
input [1:0] ff_tx_mod; // Data Modulo
input ff_tx_sop; // Start of Packet
input ff_tx_eop; // End of Packet
input ff_tx_err; // Errored Packet
input ff_tx_wren; // Write Enable
input ff_tx_crc_fwd; // Forward Current Frame with CRC from Application
output ff_tx_rdy; // FIFO Ready
output ff_tx_septy; // FIFO has space for at least one section
output tx_ff_uflow; // TX FIFO underflow occured (Synchronous with tx_clk)
output ff_rx_a_full; // Receive FIFO Almost Full
output ff_rx_a_empty; // Receive FIFO Almost Empty
output ff_tx_a_full; // Transmit FIFO Almost Full
output ff_tx_a_empty; // Transmit FIFO Almost Empty
input xoff_gen; // Xoff Pause frame generate
input xon_gen; // Xon Pause frame generate
input magic_sleep_n; // Enable Sleep Mode
output magic_wakeup; // Wake Up Request
input rx_clk; // Receive Clock
input tx_clk; // Transmit Clock
input [7:0] gm_rx_d; // GMII Receive Data
input gm_rx_dv; // GMII Receive Frame Enable
input gm_rx_err; // GMII Receive Frame Error
output [7:0] gm_tx_d; // GMII Transmit Data
output gm_tx_en; // GMII Transmit Frame Enable
output gm_tx_err; // GMII Transmit Frame Error
input [3:0] m_rx_d; // MII Receive Data
input m_rx_en; // MII Receive Frame Enable
input m_rx_err; // MII Receive Drame Error
output [3:0] m_tx_d; // MII Transmit Data
output m_tx_en; // MII Transmit Frame Enable
output m_tx_err; // MII Transmit Frame Error
input m_rx_crs; // Carrier Sense
input m_rx_col; // Collition
output eth_mode; // Ethernet Mode
output ena_10; // Enable 10Mbps Mode
input set_1000; // Gigabit Mode Enable
input set_10; // 10Mbps Mode Enable
output mdc; // 2.5MHz Inteface
input mdio_in; // MDIO Input
output mdio_out; // MDIO Output
output mdio_oen; // MDIO Output Enable
output tx_control;
output [3:0] rgmii_out;
input [3:0] rgmii_in;
input rx_control;
wire [31:0] reg_data_out;
wire reg_busy;
wire [ENABLE_ENA-1:0] ff_rx_data;
wire [1:0] ff_rx_mod;
wire ff_rx_sop;
wire ff_rx_eop;
wire ff_rx_dval;
wire ff_rx_dsav;
wire ff_tx_rdy;
wire ff_tx_septy;
wire tx_ff_uflow;
wire magic_wakeup;
wire ff_rx_a_full;
wire ff_rx_a_empty;
wire ff_tx_a_full;
wire ff_tx_a_empty;
wire [7:0] gm_tx_d;
wire gm_tx_en;
wire gm_tx_err;
wire [3:0] m_tx_d;
wire m_tx_en;
wire m_tx_err;
wire eth_mode;
wire ena_10;
wire mdc;
wire mdio_out;
wire mdio_oen;
wire tx_control;
wire [3:0] rgmii_out;
wire [5:0] rx_err;
wire [17:0] rx_err_stat;
wire [3:0] rx_frm_type;
// Reset Lines
// -----------
wire reset_rx_clk_int; // Asynchronous Reset - rx_clk Domain
wire reset_tx_clk_int; // Asynchronous Reset - tx_clk Domain
wire reset_ff_rx_clk_int; // Asynchronous Reset - ff_rx_clk Domain
wire reset_ff_tx_clk_int; // Asynchronous Reset - ff_tx_clk Domain
wire reset_reg_clk_int; // Asynchronous Reset - reg_clk Domain
// Programmable Reset Options
// --------------------------
generate if (USE_SYNC_RESET == 1)
begin
assign reset_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset_rx_clk : !reset_rx_clk ;
assign reset_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset_tx_clk : !reset_tx_clk ;
assign reset_ff_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset_ff_rx_clk : !reset_ff_rx_clk ;
assign reset_ff_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset_ff_tx_clk : !reset_ff_tx_clk ;
assign reset_reg_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
end
else
begin
assign reset_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_ff_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_ff_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_reg_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
end
endgenerate
// --------------------------
altera_tse_top_gen_host top_gen_host_inst(
.reset_ff_rx_clk(reset_ff_rx_clk_int),
.reset_ff_tx_clk(reset_ff_tx_clk_int),
.reset_reg_clk(reset_reg_clk_int),
.reset_rx_clk(reset_rx_clk_int),
.reset_tx_clk(reset_tx_clk_int),
.rx_clk(rx_clk),
.tx_clk(tx_clk),
.rx_clkena(1'b1),
.tx_clkena(1'b1),
.gm_rx_dv(gm_rx_dv),
.gm_rx_d(gm_rx_d),
.gm_rx_err(gm_rx_err),
.m_rx_en(m_rx_en),
.m_rx_d(m_rx_d),
.m_rx_err(m_rx_err),
.m_rx_col(m_rx_col),
.m_rx_crs(m_rx_crs),
.set_1000(set_1000),
.set_10(set_10),
.ff_rx_clk(ff_rx_clk),
.ff_rx_rdy(ff_rx_rdy),
.ff_tx_clk(ff_tx_clk),
.ff_tx_wren(ff_tx_wren),
.ff_tx_data(ff_tx_data),
.ff_tx_mod(ff_tx_mod),
.ff_tx_sop(ff_tx_sop),
.ff_tx_eop(ff_tx_eop),
.ff_tx_err(ff_tx_err),
.ff_tx_crc_fwd(ff_tx_crc_fwd),
.reg_clk(clk),
.reg_addr(address),
.reg_data_in(writedata),
.reg_rd(read),
.reg_wr(write),
.mdio_in(mdio_in),
.gm_tx_en(gm_tx_en),
.gm_tx_d(gm_tx_d),
.gm_tx_err(gm_tx_err),
.m_tx_en(m_tx_en),
.m_tx_d(m_tx_d),
.m_tx_err(m_tx_err),
.eth_mode(eth_mode),
.ena_10(ena_10),
.ff_rx_dval(ff_rx_dval),
.ff_rx_data(ff_rx_data),
.ff_rx_mod(ff_rx_mod),
.ff_rx_sop(ff_rx_sop),
.ff_rx_eop(ff_rx_eop),
.ff_rx_dsav(ff_rx_dsav),
.rx_err(rx_err),
.rx_err_stat(rx_err_stat),
.rx_frm_type(rx_frm_type),
.ff_tx_rdy(ff_tx_rdy),
.ff_tx_septy(ff_tx_septy),
.tx_ff_uflow(tx_ff_uflow),
.rx_a_full(ff_rx_a_full),
.rx_a_empty(ff_rx_a_empty),
.tx_a_full(ff_tx_a_full),
.tx_a_empty(ff_tx_a_empty),
.xoff_gen(xoff_gen),
.xon_gen(xon_gen),
.reg_data_out(readdata),
.reg_busy(waitrequest),
.reg_sleepN(magic_sleep_n),
.reg_wakeup(magic_wakeup),
.mdc(mdc),
.mdio_out(mdio_out),
.mdio_oen(mdio_oen),
.tx_control(tx_control),
.rgmii_out(rgmii_out),
.rgmii_in(rgmii_in),
.rx_control(rx_control));
defparam
top_gen_host_inst.EG_FIFO = EG_FIFO,
top_gen_host_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
top_gen_host_inst.CORE_VERSION = CORE_VERSION,
top_gen_host_inst.CRC32GENDELAY = CRC32GENDELAY,
top_gen_host_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
top_gen_host_inst.EG_ADDR = EG_ADDR,
top_gen_host_inst.ENA_HASH = ENA_HASH,
top_gen_host_inst.STAT_CNT_ENA = STAT_CNT_ENA,
top_gen_host_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
top_gen_host_inst.ING_FIFO = ING_FIFO,
top_gen_host_inst.ENABLE_ENA = ENABLE_ENA,
top_gen_host_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
top_gen_host_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
top_gen_host_inst.ENABLE_MDIO = ENABLE_MDIO,
top_gen_host_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
top_gen_host_inst.ENABLE_MIN_FIFO = ENABLE_MIN_FIFO,
top_gen_host_inst.ENABLE_PADDING = !ENABLE_MACLITE, //1,
top_gen_host_inst.ENABLE_LGTH_CHECK = !ENABLE_MACLITE, //1,
top_gen_host_inst.GBIT_ONLY = !ENABLE_MACLITE | MACLITE_GIGE, //1,
top_gen_host_inst.MBIT_ONLY = !ENABLE_MACLITE | !MACLITE_GIGE, //1,
top_gen_host_inst.REDUCED_CONTROL = ENABLE_MACLITE, //0,
top_gen_host_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
top_gen_host_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
top_gen_host_inst.ING_ADDR = ING_ADDR,
top_gen_host_inst.CRC32DWIDTH = CRC32DWIDTH,
top_gen_host_inst.CUST_VERSION = CUST_VERSION,
top_gen_host_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
top_gen_host_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
top_gen_host_inst.INSERT_TA = INSERT_TA,
top_gen_host_inst.RAM_TYPE = RAM_TYPE,
top_gen_host_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
top_gen_host_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
top_gen_host_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
top_gen_host_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
top_gen_host_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
endmodule
|
//======================================================================
//
// tb_fpga_entropy.v
// -----------------
// Testbench for the FPGA Entropy generator core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
//------------------------------------------------------------------
// Simulator directives.
//------------------------------------------------------------------
`timescale 1ns/10ps
module tb_fpga_entropy();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 1;
parameter VERBOSE = 0;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = CLK_HALF_PERIOD * 2;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
reg tb_init;
reg tb_update;
reg tb_seed;
wire [31 : 0] tb_rnd;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
fpga_entropy_core dut(
// Clock and reset.
.clk(),
.reset_n(),
.init(tb_init),
.update(tb_update),
.seed(tb_seed),
.rnd(tb_rnd)
);
//----------------------------------------------------------------
// clk_gen
//
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor
//
// System monitor. Can display status about the dut and TB
// every cycle.
//----------------------------------------------------------------
always
begin : sys_monitor
#(CLK_PERIOD);
if (DEBUG)
begin
dump_dut_state();
$display("");
end
if (VERBOSE)
begin
$display("cycle: 0x%016x", cycle_ctr);
end
cycle_ctr = cycle_ctr + 1;
end
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dut when needed.
//----------------------------------------------------------------
task dump_dut_state();
begin
$display("State of DUT");
$display("------------");
$display("Inputs and outputs:");
$display("init = 0x%01x, update = 0x%01x, seed = 0x%01x",
tb_init, tb_update, tb_seed);
$display("rnd= 0x%08x", tb_rnd);
$display("");
$display("Internal values:");
$display("shift_reg = 0x%08x, rnd_reg = 0x%08x, bit_ctr_reg = 0x%02x",
dut.shift_reg, dut.rnd_reg, dut.bit_ctr_reg);
$display("l5d = 0x%01x, l7d = 0x%01x, l13d = 0x%01x, l41d = 0x01x, l43d = 0x%01x",
dut.l5d, dut.l7d, dut.l13d, dut.l41d, dut.l43d);
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// reset_dut()
//----------------------------------------------------------------
task reset_dut();
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim();
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_init = 1;
tb_seed = 1;
tb_update = 0;
end
endtask // init_sim
//----------------------------------------------------------------
// fpga_entropy_test
//
// The main test functionality.
//----------------------------------------------------------------
initial
begin : fpga_entropy_test
$display(" -- Testbench for fpga entropy core started --");
init_sim();
dump_dut_state();
reset_dut();
dump_dut_state();
tb_update = 1;
#(64 * CLK_PERIOD);
tb_init = 0;
#(1000 * CLK_PERIOD);
$display("*** Simulation done. ***");
$finish;
end // fpga_entropy_test
endmodule // tb_fpga_entropy
//======================================================================
// EOF tb_fpga_entropy.v
//======================================================================
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD2_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DLYGATE4SD2_PP_BLACKBOX_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlygate4sd2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD2_PP_BLACKBOX_V
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: pfcache.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: Keeping our CPU fed with instructions, at one per clock and
// with no stalls. An unusual feature of this cache is the
// requirement that the entire cache may be cleared (if necessary).
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
module pfcache(i_clk, i_rst, i_new_pc, i_clear_cache,
// i_early_branch, i_from_addr,
i_stall_n, i_pc, o_i, o_pc, o_v,
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
o_illegal);
parameter LGCACHELEN = 8, ADDRESS_WIDTH=24,
LGLINES=5; // Log of the number of separate cache lines
localparam CACHELEN=(1<<LGCACHELEN); // Size of our cache memory
localparam CW=LGCACHELEN; // Short hand for LGCACHELEN
localparam PW=LGCACHELEN-LGLINES; // Size of a cache line
localparam BUSW = 32; // Number of data lines on the bus
localparam AW=ADDRESS_WIDTH; // Shorthand for ADDRESS_WIDTH
input wire i_clk, i_rst, i_new_pc;
input wire i_clear_cache;
input wire i_stall_n;
input wire [(AW-1):0] i_pc;
output wire [(BUSW-1):0] o_i;
output wire [(AW-1):0] o_pc;
output wire o_v;
//
output reg o_wb_cyc, o_wb_stb;
output wire o_wb_we;
output reg [(AW-1):0] o_wb_addr;
output wire [(BUSW-1):0] o_wb_data;
//
input wire i_wb_ack, i_wb_stall, i_wb_err;
input wire [(BUSW-1):0] i_wb_data;
//
output reg o_illegal;
// Fixed bus outputs: we read from the bus only, never write.
// Thus the output data is ... irrelevant and don't care. We set it
// to zero just to set it to something.
assign o_wb_we = 1'b0;
assign o_wb_data = 0;
wire r_v;
reg [(BUSW-1):0] cache [0:((1<<CW)-1)];
reg [(AW-CW-1):0] tags [0:((1<<(LGLINES))-1)];
reg [((1<<(LGLINES))-1):0] vmask;
reg [(AW-1):0] lastpc;
reg [(CW-1):0] rdaddr;
reg [(AW-1):CW] tagvalipc, tagvallst;
wire [(AW-1):CW] tagval;
wire [(AW-1):PW] lasttag;
reg illegal_valid;
reg [(AW-1):PW] illegal_cache;
// initial o_i = 32'h76_00_00_00; // A NOOP instruction
// initial o_pc = 0;
reg [(BUSW-1):0] r_pc_cache, r_last_cache;
reg [(AW-1):0] r_pc, r_lastpc;
reg isrc;
always @(posedge i_clk)
begin
// We don't have the logic to select what to read, we must
// read both the value at i_pc and lastpc. cache[i_pc] is
// the value we return if the cache is good, cacne[lastpc] is
// the value we return if we've been stalled, weren't valid,
// or had to wait a clock or two. (Remember i_pc can't stop
// changing for a clock, so we need to keep track of the last
// one from before it stopped.)
//
// Here we keep track of which answer we want/need
isrc <= ((r_v)&&(i_stall_n))||(i_new_pc);
// Here we read both, and select which was write using isrc
// on the next clock.
r_pc_cache <= cache[i_pc[(CW-1):0]];
r_last_cache <= cache[lastpc[(CW-1):0]];
r_pc <= i_pc;
r_lastpc <= lastpc;
end
assign o_pc = (isrc) ? r_pc : r_lastpc;
assign o_i = (isrc) ? r_pc_cache : r_last_cache;
reg tagsrc;
always @(posedge i_clk)
// It may be possible to recover a clock once the cache line
// has been filled, but our prior attempt to do so has lead
// to a race condition, so we keep this logic simple.
if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
tagsrc <= 1'b1;
else
tagsrc <= 1'b0;
initial tagvalipc = 0;
always @(posedge i_clk)
tagvalipc <= tags[i_pc[(CW-1):PW]];
initial tagvallst = 0;
always @(posedge i_clk)
tagvallst <= tags[lastpc[(CW-1):PW]];
assign tagval = (tagsrc)?tagvalipc : tagvallst;
// i_pc will only increment when everything else isn't stalled, thus
// we can set it without worrying about that. Doing this enables
// us to work in spite of stalls. For example, if the next address
// isn't valid, but the decoder is stalled, get the next address
// anyway.
initial lastpc = 0;
always @(posedge i_clk)
if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
lastpc <= i_pc;
assign lasttag = lastpc[(AW-1):PW];
wire w_v_from_pc, w_v_from_last;
assign w_v_from_pc = ((i_pc[(AW-1):PW] == lasttag)
&&(tagvalipc == i_pc[(AW-1):CW])
&&(vmask[i_pc[(CW-1):PW]]));
assign w_v_from_last = (
//(lastpc[(AW-1):PW] == lasttag)&&
(tagval == lastpc[(AW-1):CW])
&&(vmask[lastpc[(CW-1):PW]]));
reg [1:0] delay;
initial delay = 2'h3;
reg rvsrc;
always @(posedge i_clk)
if ((i_rst)||(i_clear_cache)||(i_new_pc)||((r_v)&&(i_stall_n)))
begin
// r_v <= r_v_from_pc;
rvsrc <= 1'b1;
delay <= 2'h2;
end else if (~r_v) begin // Otherwise, r_v was true and we were
// stalled, hence only if ~r_v
rvsrc <= 1'b0;
if (o_wb_cyc)
delay <= 2'h2;
else if (delay != 0)
delay <= delay + 2'b11; // i.e. delay -= 1;
end
reg r_v_from_pc, r_v_from_last;
always @(posedge i_clk)
r_v_from_pc <= w_v_from_pc;
always @(posedge i_clk)
r_v_from_last <= w_v_from_last;
assign r_v = ((rvsrc)?(r_v_from_pc):(r_v_from_last));
assign o_v = (((rvsrc)?(r_v_from_pc):(r_v_from_last))
||((o_illegal)&&(~o_wb_cyc)))
&&(~i_new_pc)&&(~i_rst);
reg last_ack;
initial last_ack = 1'b0;
always @(posedge i_clk)
last_ack <= (o_wb_cyc)&&(
(rdaddr[(PW-1):1]=={(PW-1){1'b1}})
&&((rdaddr[0])||(i_wb_ack)));
reg needload;
initial needload = 1'b0;
always @(posedge i_clk)
needload <= ((~r_v)&&(delay==0)
&&((tagvallst != lastpc[(AW-1):CW])
||(~vmask[lastpc[(CW-1):PW]]))
&&((~illegal_valid)
||(lastpc[(AW-1):PW] != illegal_cache)));
reg last_addr;
initial last_addr = 1'b0;
always @(posedge i_clk)
last_addr <= (o_wb_cyc)&&(o_wb_addr[(PW-1):1] == {(PW-1){1'b1}})
&&((~i_wb_stall)|(o_wb_addr[0]));
initial o_wb_cyc = 1'b0;
initial o_wb_stb = 1'b0;
initial o_wb_addr = {(AW){1'b0}};
initial rdaddr = 0;
always @(posedge i_clk)
if ((i_rst)||(i_clear_cache))
begin
o_wb_cyc <= 1'b0;
o_wb_stb <= 1'b0;
end else if (o_wb_cyc)
begin
if (i_wb_err)
o_wb_stb <= 1'b0;
else if ((o_wb_stb)&&(~i_wb_stall)&&(last_addr))
o_wb_stb <= 1'b0;
if (((i_wb_ack)&&(last_ack))||(i_wb_err))
o_wb_cyc <= 1'b0;
// else if (rdaddr[(PW-1):1] == {(PW-1){1'b1}})
// tags[lastpc[(CW-1):PW]] <= lastpc[(AW-1):CW];
end else if (needload)
begin
o_wb_cyc <= 1'b1;
o_wb_stb <= 1'b1;
end
always @(posedge i_clk)
if (o_wb_cyc) // &&(i_wb_ack)
tags[o_wb_addr[(CW-1):PW]] <= o_wb_addr[(AW-1):CW];
always @(posedge i_clk)
if ((o_wb_cyc)&&(i_wb_ack))
rdaddr <= rdaddr + 1;
else if (~o_wb_cyc)
rdaddr <= { lastpc[(CW-1):PW], {(PW){1'b0}} };
always @(posedge i_clk)
if ((o_wb_stb)&&(~i_wb_stall)&&(~last_addr))
o_wb_addr[(PW-1):0] <= o_wb_addr[(PW-1):0]+1;
else if (~o_wb_cyc)
o_wb_addr <= { lastpc[(AW-1):PW], {(PW){1'b0}} };
// Can't initialize an array, so leave cache uninitialized
// We'll also never get an ack without sys being active, so skip
// that check. Or rather, let's just use o_wb_cyc instead. This
// will work because multiple writes to the same address, ending with
// a valid write, aren't a problem.
always @(posedge i_clk)
if (o_wb_cyc) // &&(i_wb_ack)
cache[rdaddr] <= i_wb_data;
// VMask ... is a section loaded?
// Note "svmask". It's purpose is to delay the vmask setting by one
// clock, so that we can insure the right value of the cache is loaded
// before declaring that the cache line is valid. Without this, the
// cache line would get read, and the instruction would read from the
// last cache line.
reg svmask;
initial vmask = 0;
initial svmask = 1'b0;
reg [(LGLINES-1):0] saddr;
always @(posedge i_clk)
if ((i_rst)||(i_clear_cache))
begin
vmask <= 0;
svmask<= 1'b0;
end
else begin
svmask <= ((o_wb_cyc)&&(i_wb_ack)&&(last_ack));
if (svmask)
vmask[saddr] <= 1'b1;
if ((~o_wb_cyc)&&(needload))
vmask[lastpc[(CW-1):PW]] <= 1'b0;
end
always @(posedge i_clk)
if ((o_wb_cyc)&&(i_wb_ack))
saddr <= rdaddr[(CW-1):PW];
initial illegal_cache = 0;
initial illegal_valid = 0;
always @(posedge i_clk)
if ((i_rst)||(i_clear_cache))
begin
illegal_cache <= 0;
illegal_valid <= 0;
end else if ((o_wb_cyc)&&(i_wb_err))
begin
illegal_cache <= o_wb_addr[(AW-1):PW];
illegal_valid <= 1'b1;
end
initial o_illegal = 1'b0;
always @(posedge i_clk)
if ((i_rst)||(i_clear_cache)||(o_wb_cyc))
o_illegal <= 1'b0;
else
o_illegal <= (illegal_valid)
&&(illegal_cache == i_pc[(AW-1):PW]);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [3:0] drv_a = crc[3:0];
wire [3:0] drv_b = crc[7:4];
wire [3:0] drv_e = crc[19:16];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [8:0] match1; // From test1 of Test1.v
wire [8:0] match2; // From test2 of Test2.v
// End of automatics
Test1 test1 (/*AUTOINST*/
// Outputs
.match1 (match1[8:0]),
// Inputs
.drv_a (drv_a[3:0]),
.drv_e (drv_e[3:0]));
Test2 test2 (/*AUTOINST*/
// Outputs
.match2 (match2[8:0]),
// Inputs
.drv_a (drv_a[3:0]),
.drv_e (drv_e[3:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {39'h0, match2, 7'h0, match1};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x m1=%x m2=%x (%b??%b:%b)\n",$time, cyc, crc, match1, match2, drv_e,drv_a,drv_b);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hc0c4a2b9aea7c4b4
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test1
(
input wire [3:0] drv_a,
input wire [3:0] drv_e,
output wire [8:0] match1
);
wire [2:1] drv_all;
bufif1 bufa [2:1] (drv_all, drv_a[2:1], drv_e[2:1]);
`ifdef VERILATOR
// At present Verilator only allows comparisons with Zs
assign match1[0] = (drv_a[2:1]== 2'b00 && drv_e[2:1]==2'b11);
assign match1[1] = (drv_a[2:1]== 2'b01 && drv_e[2:1]==2'b11);
assign match1[2] = (drv_a[2:1]== 2'b10 && drv_e[2:1]==2'b11);
assign match1[3] = (drv_a[2:1]== 2'b11 && drv_e[2:1]==2'b11);
`else
assign match1[0] = drv_all === 2'b00;
assign match1[1] = drv_all === 2'b01;
assign match1[2] = drv_all === 2'b10;
assign match1[3] = drv_all === 2'b11;
`endif
assign match1[4] = drv_all === 2'bz0;
assign match1[5] = drv_all === 2'bz1;
assign match1[6] = drv_all === 2'bzz;
assign match1[7] = drv_all === 2'b0z;
assign match1[8] = drv_all === 2'b1z;
endmodule
module Test2
(
input wire [3:0] drv_a,
input wire [3:0] drv_e,
output wire [8:0] match2
);
wire [2:1] drv_all;
bufif1 bufa [2:1] (drv_all, drv_a[2:1], drv_e[2:1]);
`ifdef VERILATOR
assign match2[0] = (drv_all !== 2'b00 || drv_e[2:1]!=2'b11);
assign match2[1] = (drv_all !== 2'b01 || drv_e[2:1]!=2'b11);
assign match2[2] = (drv_all !== 2'b10 || drv_e[2:1]!=2'b11);
assign match2[3] = (drv_all !== 2'b11 || drv_e[2:1]!=2'b11);
`else
assign match2[0] = drv_all !== 2'b00;
assign match2[1] = drv_all !== 2'b01;
assign match2[2] = drv_all !== 2'b10;
assign match2[3] = drv_all !== 2'b11;
`endif
assign match2[4] = drv_all !== 2'bz0;
assign match2[5] = drv_all !== 2'bz1;
assign match2[6] = drv_all !== 2'bzz;
assign match2[7] = drv_all !== 2'b0z;
assign match2[8] = drv_all !== 2'b1z;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: AXI4Lite Upizer
// Converts 32-bit AXI4Lite on Slave Interface to 64-bit AXI4Lite on Master Interface.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axi4lite_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_axi4lite_upsizer #
(
parameter C_FAMILY = "none",
// FPGA Family.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI.
// Range 3 - 64.
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1
)
(
// Global Signals
input wire aresetn,
input wire aclk,
// Slave Interface Write Address Ports
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [3-1:0] s_axi_awprot,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [32-1:0] s_axi_wdata,
input wire [32/8-1:0] s_axi_wstrb,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [2-1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [3-1:0] s_axi_arprot,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [32-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [3-1:0] m_axi_awprot,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [64-1:0] m_axi_wdata,
output wire [64/8-1:0] m_axi_wstrb,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [2-1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [3-1:0] m_axi_arprot,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [64-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rvalid,
output wire m_axi_rready
);
reg s_axi_arready_i ;
reg m_axi_arvalid_i ;
reg m_axi_rready_i ;
reg s_axi_rvalid_i ;
reg ar_done ;
reg araddr2 ;
reg s_axi_awready_i ;
reg s_axi_bvalid_i ;
reg m_axi_awvalid_i ;
reg m_axi_wvalid_i ;
reg m_axi_bready_i ;
reg aw_done ;
reg w_done ;
generate
if (C_AXI_SUPPORTS_READ != 0) begin : gen_read
always @(posedge aclk) begin
if (~aresetn) begin
s_axi_arready_i <= 1'b0 ;
m_axi_arvalid_i <= 1'b0 ;
s_axi_rvalid_i <= 1'b0;
m_axi_rready_i <= 1'b1;
ar_done <= 1'b0 ;
araddr2 <= 1'b0 ;
end else begin
s_axi_arready_i <= 1'b0 ; // end single-cycle pulse
m_axi_rready_i <= 1'b0; // end single-cycle pulse
if (s_axi_rvalid_i) begin
if (s_axi_rready) begin
s_axi_rvalid_i <= 1'b0;
m_axi_rready_i <= 1'b1; // begin single-cycle pulse
ar_done <= 1'b0;
end
end else if (m_axi_rvalid & ar_done) begin
s_axi_rvalid_i <= 1'b1;
end else if (m_axi_arvalid_i) begin
if (m_axi_arready) begin
m_axi_arvalid_i <= 1'b0;
s_axi_arready_i <= 1'b1 ; // begin single-cycle pulse
araddr2 <= s_axi_araddr[2];
ar_done <= 1'b1;
end
end else if (s_axi_arvalid & ~ar_done) begin
m_axi_arvalid_i <= 1'b1;
end
end
end
assign m_axi_arvalid = m_axi_arvalid_i ;
assign s_axi_arready = s_axi_arready_i ;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arprot = s_axi_arprot;
assign s_axi_rvalid = s_axi_rvalid_i ;
assign m_axi_rready = m_axi_rready_i ;
assign s_axi_rdata = araddr2 ? m_axi_rdata[63:32] : m_axi_rdata[31:0];
assign s_axi_rresp = m_axi_rresp;
end else begin : gen_noread
assign m_axi_arvalid = 1'b0 ;
assign s_axi_arready = 1'b0 ;
assign m_axi_araddr = {C_AXI_ADDR_WIDTH{1'b0}} ;
assign m_axi_arprot = 3'b0 ;
assign s_axi_rvalid = 1'b0 ;
assign m_axi_rready = 1'b0 ;
assign s_axi_rresp = 2'b0 ;
assign s_axi_rdata = 32'b0 ;
end
if (C_AXI_SUPPORTS_WRITE != 0) begin : gen_write
always @(posedge aclk) begin
if (~aresetn) begin
m_axi_awvalid_i <= 1'b0 ;
s_axi_awready_i <= 1'b0 ;
m_axi_wvalid_i <= 1'b0 ;
s_axi_bvalid_i <= 1'b0 ;
m_axi_bready_i <= 1'b0 ;
aw_done <= 1'b0 ;
w_done <= 1'b0 ;
end else begin
m_axi_bready_i <= 1'b0; // end single-cycle pulse
if (s_axi_bvalid_i) begin
if (s_axi_bready) begin
s_axi_bvalid_i <= 1'b0;
m_axi_bready_i <= 1'b1; // begin single-cycle pulse
aw_done <= 1'b0;
w_done <= 1'b0;
end
end else if (s_axi_awready_i) begin
s_axi_awready_i <= 1'b0; // end single-cycle pulse
s_axi_bvalid_i <= 1'b1;
end else if (aw_done & w_done) begin
if (m_axi_bvalid) begin
s_axi_awready_i <= 1'b1; // begin single-cycle pulse
end
end else begin
if (m_axi_awvalid_i) begin
if (m_axi_awready) begin
m_axi_awvalid_i <= 1'b0;
aw_done <= 1'b1;
end
end else if (s_axi_awvalid & ~aw_done) begin
m_axi_awvalid_i <= 1'b1;
end
if (m_axi_wvalid_i) begin
if (m_axi_wready) begin
m_axi_wvalid_i <= 1'b0;
w_done <= 1'b1;
end
end else if (s_axi_wvalid & (m_axi_awvalid_i | aw_done) & ~w_done) begin
m_axi_wvalid_i <= 1'b1;
end
end
end
end
assign m_axi_awvalid = m_axi_awvalid_i ;
assign s_axi_awready = s_axi_awready_i ;
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_wvalid = m_axi_wvalid_i ;
assign s_axi_wready = s_axi_awready_i ;
assign m_axi_wdata = {s_axi_wdata,s_axi_wdata};
assign m_axi_wstrb = s_axi_awaddr[2] ? {s_axi_wstrb, 4'b0} : {4'b0, s_axi_wstrb};
assign s_axi_bvalid = s_axi_bvalid_i ;
assign m_axi_bready = m_axi_bready_i ;
assign s_axi_bresp = m_axi_bresp;
end else begin : gen_nowrite
assign m_axi_awvalid = 1'b0 ;
assign s_axi_awready = 1'b0 ;
assign m_axi_awaddr = {C_AXI_ADDR_WIDTH{1'b0}} ;
assign m_axi_awprot = 3'b0 ;
assign m_axi_wvalid = 1'b0 ;
assign s_axi_wready = 1'b0 ;
assign m_axi_wdata = 64'b0 ;
assign m_axi_wstrb = 8'b0 ;
assign s_axi_bvalid = 1'b0 ;
assign m_axi_bready = 1'b0 ;
assign s_axi_bresp = 2'b0 ;
end
endgenerate
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_mem_backbone.v
//
// *Module Description:
// Memory interface backbone (decoder + arbiter)
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_mem_backbone (
// OUTPUTs
cpu_halt_cmd, // Halt CPU command
dbg_mem_din, // Debug unit Memory data input
dmem_addr, // Data Memory address
dmem_cen, // Data Memory chip enable (low active)
dmem_din, // Data Memory data input
dmem_wen, // Data Memory write enable (low active)
eu_mdb_in, // Execution Unit Memory data bus input
fe_mdb_in, // Frontend Memory data bus input
fe_pmem_wait, // Frontend wait for Instruction fetch
dma_dout, // Direct Memory Access data output
dma_ready, // Direct Memory Access is complete
dma_resp, // Direct Memory Access response (0:Okay / 1:Error)
per_addr, // Peripheral address
per_din, // Peripheral data input
per_we, // Peripheral write enable (high active)
per_en, // Peripheral enable (high active)
pmem_addr, // Program Memory address
pmem_cen, // Program Memory chip enable (low active)
pmem_din, // Program Memory data input (optional)
pmem_wen, // Program Memory write enable (low active) (optional)
// INPUTs
cpu_halt_st, // Halt/Run status from CPU
dbg_halt_cmd, // Debug interface Halt CPU command
dbg_mem_addr, // Debug address for rd/wr access
dbg_mem_dout, // Debug unit data output
dbg_mem_en, // Debug unit memory enable
dbg_mem_wr, // Debug unit memory write
dmem_dout, // Data Memory data output
eu_mab, // Execution Unit Memory address bus
eu_mb_en, // Execution Unit Memory bus enable
eu_mb_wr, // Execution Unit Memory bus write transfer
eu_mdb_out, // Execution Unit Memory data bus output
fe_mab, // Frontend Memory address bus
fe_mb_en, // Frontend Memory bus enable
mclk, // Main system clock
dma_addr, // Direct Memory Access address
dma_din, // Direct Memory Access data input
dma_en, // Direct Memory Access enable (high active)
dma_priority, // Direct Memory Access priority (0:low / 1:high)
dma_we, // Direct Memory Access write byte enable (high active)
per_dout, // Peripheral data output
pmem_dout, // Program Memory data output
puc_rst, // Main system reset
scan_enable // Scan enable (active during scan shifting)
);
// OUTPUTs
//=========
output cpu_halt_cmd; // Halt CPU command
output [15:0] dbg_mem_din; // Debug unit Memory data input
output [`DMEM_MSB:0] dmem_addr; // Data Memory address
output dmem_cen; // Data Memory chip enable (low active)
output [15:0] dmem_din; // Data Memory data input
output [1:0] dmem_wen; // Data Memory write enable (low active)
output [15:0] eu_mdb_in; // Execution Unit Memory data bus input
output [15:0] fe_mdb_in; // Frontend Memory data bus input
output fe_pmem_wait; // Frontend wait for Instruction fetch
output [15:0] dma_dout; // Direct Memory Access data output
output dma_ready; // Direct Memory Access is complete
output dma_resp; // Direct Memory Access response (0:Okay / 1:Error)
output [13:0] per_addr; // Peripheral address
output [15:0] per_din; // Peripheral data input
output [1:0] per_we; // Peripheral write enable (high active)
output per_en; // Peripheral enable (high active)
output [`PMEM_MSB:0] pmem_addr; // Program Memory address
output pmem_cen; // Program Memory chip enable (low active)
output [15:0] pmem_din; // Program Memory data input (optional)
output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
// INPUTs
//=========
input cpu_halt_st; // Halt/Run status from CPU
input dbg_halt_cmd; // Debug interface Halt CPU command
input [15:1] dbg_mem_addr; // Debug address for rd/wr access
input [15:0] dbg_mem_dout; // Debug unit data output
input dbg_mem_en; // Debug unit memory enable
input [1:0] dbg_mem_wr; // Debug unit memory write
input [15:0] dmem_dout; // Data Memory data output
input [14:0] eu_mab; // Execution Unit Memory address bus
input eu_mb_en; // Execution Unit Memory bus enable
input [1:0] eu_mb_wr; // Execution Unit Memory bus write transfer
input [15:0] eu_mdb_out; // Execution Unit Memory data bus output
input [14:0] fe_mab; // Frontend Memory address bus
input fe_mb_en; // Frontend Memory bus enable
input mclk; // Main system clock
input [15:1] dma_addr; // Direct Memory Access address
input [15:0] dma_din; // Direct Memory Access data input
input dma_en; // Direct Memory Access enable (high active)
input dma_priority; // Direct Memory Access priority (0:low / 1:high)
input [1:0] dma_we; // Direct Memory Access write byte enable (high active)
input [15:0] per_dout; // Peripheral data output
input [15:0] pmem_dout; // Program Memory data output
input puc_rst; // Main system reset
input scan_enable; // Scan enable (active during scan shifting)
wire ext_mem_en;
wire [15:0] ext_mem_din;
wire ext_dmem_sel;
wire ext_dmem_en;
wire ext_pmem_sel;
wire ext_pmem_en;
wire ext_per_sel;
wire ext_per_en;
//=============================================================================
// 1) DECODER
//=============================================================================
//------------------------------------------
// Arbiter between DMA and Debug interface
//------------------------------------------
`ifdef DMA_IF_EN
// Debug-interface always stops the CPU
// Master interface stops the CPU in priority mode
assign cpu_halt_cmd = dbg_halt_cmd | (dma_en & dma_priority);
// Return ERROR response if address lays outside the memory spaces (Peripheral, Data & Program memories)
assign dma_resp = ~dbg_mem_en & ~(ext_dmem_sel | ext_pmem_sel | ext_per_sel) & dma_en;
// Master interface access is ready when the memory access occures
assign dma_ready = ~dbg_mem_en & (ext_dmem_en | ext_pmem_en | ext_per_en | dma_resp);
// Use delayed version of 'dma_ready' to mask the 'dma_dout' data output
// when not accessed and reduce toggle rate (thus power consumption)
reg dma_ready_dly;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) dma_ready_dly <= 1'b0;
else dma_ready_dly <= dma_ready;
// Mux between debug and master interface
assign ext_mem_en = dbg_mem_en | dma_en;
wire [1:0] ext_mem_wr = dbg_mem_en ? dbg_mem_wr : dma_we;
wire [15:1] ext_mem_addr = dbg_mem_en ? dbg_mem_addr : dma_addr;
wire [15:0] ext_mem_dout = dbg_mem_en ? dbg_mem_dout : dma_din;
// External interface read data
assign dbg_mem_din = ext_mem_din;
assign dma_dout = ext_mem_din & {16{dma_ready_dly}};
`else
// Debug-interface always stops the CPU
assign cpu_halt_cmd = dbg_halt_cmd;
// Master interface access is always ready with error response when excluded
assign dma_resp = 1'b1;
assign dma_ready = 1'b1;
// Debug interface only
assign ext_mem_en = dbg_mem_en;
wire [1:0] ext_mem_wr = dbg_mem_wr;
wire [15:1] ext_mem_addr = dbg_mem_addr;
wire [15:0] ext_mem_dout = dbg_mem_dout;
// External interface read data
assign dbg_mem_din = ext_mem_din;
assign dma_dout = 16'h0000;
// LINT Cleanup
wire [15:1] UNUSED_dma_addr = dma_addr;
wire [15:0] UNUSED_dma_din = dma_din;
wire UNUSED_dma_en = dma_en;
wire UNUSED_dma_priority = dma_priority;
wire [1:0] UNUSED_dma_we = dma_we;
`endif
//------------------------------------------
// DATA-MEMORY Interface
//------------------------------------------
parameter DMEM_END = `DMEM_BASE+`DMEM_SIZE;
// Execution unit access
wire eu_dmem_sel = (eu_mab>=(`DMEM_BASE>>1)) &
(eu_mab< ( DMEM_END >>1));
wire eu_dmem_en = eu_mb_en & eu_dmem_sel;
wire [15:0] eu_dmem_addr = {1'b0, eu_mab}-(`DMEM_BASE>>1);
// Front-end access
// -- not allowed to execute from data memory --
// External Master/Debug interface access
assign ext_dmem_sel = (ext_mem_addr[15:1]>=(`DMEM_BASE>>1)) &
(ext_mem_addr[15:1]< ( DMEM_END >>1));
assign ext_dmem_en = ext_mem_en & ext_dmem_sel & ~eu_dmem_en;
wire [15:0] ext_dmem_addr = {1'b0, ext_mem_addr[15:1]}-(`DMEM_BASE>>1);
// Data-Memory Interface
wire dmem_cen = ~(ext_dmem_en | eu_dmem_en);
wire [1:0] dmem_wen = ext_dmem_en ? ~ext_mem_wr : ~eu_mb_wr;
wire [`DMEM_MSB:0] dmem_addr = ext_dmem_en ? ext_dmem_addr[`DMEM_MSB:0] : eu_dmem_addr[`DMEM_MSB:0];
wire [15:0] dmem_din = ext_dmem_en ? ext_mem_dout : eu_mdb_out;
//------------------------------------------
// PROGRAM-MEMORY Interface
//------------------------------------------
parameter PMEM_OFFSET = (16'hFFFF-`PMEM_SIZE+1);
// Execution unit access (only read access are accepted)
wire eu_pmem_sel = (eu_mab>=(PMEM_OFFSET>>1));
wire eu_pmem_en = eu_mb_en & ~|eu_mb_wr & eu_pmem_sel;
wire [15:0] eu_pmem_addr = eu_mab-(PMEM_OFFSET>>1);
// Front-end access
wire fe_pmem_sel = (fe_mab>=(PMEM_OFFSET>>1));
wire fe_pmem_en = fe_mb_en & fe_pmem_sel;
wire [15:0] fe_pmem_addr = fe_mab-(PMEM_OFFSET>>1);
// External Master/Debug interface access
assign ext_pmem_sel = (ext_mem_addr[15:1]>=(PMEM_OFFSET>>1));
assign ext_pmem_en = ext_mem_en & ext_pmem_sel & ~eu_pmem_en & ~fe_pmem_en;
wire [15:0] ext_pmem_addr = {1'b0, ext_mem_addr[15:1]}-(PMEM_OFFSET>>1);
// Program-Memory Interface (Execution unit has priority over the Front-end)
wire pmem_cen = ~(fe_pmem_en | eu_pmem_en | ext_pmem_en);
wire [1:0] pmem_wen = ext_pmem_en ? ~ext_mem_wr : 2'b11;
wire [`PMEM_MSB:0] pmem_addr = ext_pmem_en ? ext_pmem_addr[`PMEM_MSB:0] :
eu_pmem_en ? eu_pmem_addr[`PMEM_MSB:0] : fe_pmem_addr[`PMEM_MSB:0];
wire [15:0] pmem_din = ext_mem_dout;
wire fe_pmem_wait = (fe_pmem_en & eu_pmem_en);
//------------------------------------------
// PERIPHERALS Interface
//------------------------------------------
// Execution unit access
wire eu_per_sel = (eu_mab<(`PER_SIZE>>1));
wire eu_per_en = eu_mb_en & eu_per_sel;
// Front-end access
// -- not allowed to execute from peripherals memory space --
// External Master/Debug interface access
assign ext_per_sel = (ext_mem_addr[15:1]<(`PER_SIZE>>1));
assign ext_per_en = ext_mem_en & ext_per_sel & ~eu_per_en;
// Peripheral Interface
wire per_en = ext_per_en | eu_per_en;
wire [1:0] per_we = ext_per_en ? ext_mem_wr : eu_mb_wr;
wire [`PER_MSB:0] per_addr_mux = ext_per_en ? ext_mem_addr[`PER_MSB+1:1] : eu_mab[`PER_MSB:0];
wire [14:0] per_addr_ful = {{15-`PER_AWIDTH{1'b0}}, per_addr_mux};
wire [13:0] per_addr = per_addr_ful[13:0];
wire [15:0] per_din = ext_per_en ? ext_mem_dout : eu_mdb_out;
// Register peripheral data read path
reg [15:0] per_dout_val;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) per_dout_val <= 16'h0000;
else per_dout_val <= per_dout;
//------------------------------------------
// Frontend data Mux
//------------------------------------------
// Whenever the frontend doesn't access the program memory, backup the data
// Detect whenever the data should be backuped and restored
reg fe_pmem_en_dly;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) fe_pmem_en_dly <= 1'b0;
else fe_pmem_en_dly <= fe_pmem_en;
wire fe_pmem_save = (~fe_pmem_en & fe_pmem_en_dly) & ~cpu_halt_st;
wire fe_pmem_restore = ( fe_pmem_en & ~fe_pmem_en_dly) | cpu_halt_st;
`ifdef CLOCK_GATING
wire mclk_bckup_gated;
omsp_clock_gate clock_gate_bckup (.gclk(mclk_bckup_gated),
.clk (mclk), .enable(fe_pmem_save), .scan_enable(scan_enable));
`define MCLK_BCKUP mclk_bckup_gated
`else
wire UNUSED_scan_enable = scan_enable;
`define MCLK_BCKUP mclk // use macro to solve delta cycle issues with some mixed VHDL/Verilog simulators
`endif
reg [15:0] pmem_dout_bckup;
always @(posedge `MCLK_BCKUP or posedge puc_rst)
if (puc_rst) pmem_dout_bckup <= 16'h0000;
`ifdef CLOCK_GATING
else pmem_dout_bckup <= pmem_dout;
`else
else if (fe_pmem_save) pmem_dout_bckup <= pmem_dout;
`endif
// Mux between the Program memory data and the backup
reg pmem_dout_bckup_sel;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) pmem_dout_bckup_sel <= 1'b0;
else if (fe_pmem_save) pmem_dout_bckup_sel <= 1'b1;
else if (fe_pmem_restore) pmem_dout_bckup_sel <= 1'b0;
assign fe_mdb_in = pmem_dout_bckup_sel ? pmem_dout_bckup : pmem_dout;
//------------------------------------------
// Execution-Unit data Mux
//------------------------------------------
// Select between Peripherals, Program and Data memories
reg [1:0] eu_mdb_in_sel;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) eu_mdb_in_sel <= 2'b00;
else eu_mdb_in_sel <= {eu_pmem_en, eu_per_en};
// Mux
assign eu_mdb_in = eu_mdb_in_sel[1] ? pmem_dout :
eu_mdb_in_sel[0] ? per_dout_val : dmem_dout;
//------------------------------------------
// External Master/Debug interface data Mux
//------------------------------------------
// Select between Peripherals, Program and Data memories
reg [1:0] ext_mem_din_sel;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) ext_mem_din_sel <= 2'b00;
else ext_mem_din_sel <= {ext_pmem_en, ext_per_en};
// Mux
assign ext_mem_din = ext_mem_din_sel[1] ? pmem_dout :
ext_mem_din_sel[0] ? per_dout_val : dmem_dout;
endmodule // omsp_mem_backbone
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
// Date : Sat Jan 21 22:59:39 2017
// Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
// Command : write_verilog -force -mode synth_stub
// /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mul_16_32/mul_16_32_stub.v
// Design : mul_16_32
// Purpose : Stub declaration of top-level module interface
// Device : xcku035-fbva676-3-e
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "mult_gen_v12_0_12,Vivado 2016.4" *)
module mul_16_32(CLK, A, B, P)
/* synthesis syn_black_box black_box_pad_pin="CLK,A[15:0],B[31:0],P[47:0]" */;
input CLK;
input [15:0]A;
input [31:0]B;
output [47:0]P;
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module sample_iterator_get_offset (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
indices_stride_req_din,
indices_stride_req_full_n,
indices_stride_req_write,
indices_stride_rsp_empty_n,
indices_stride_rsp_read,
indices_stride_address,
indices_stride_datain,
indices_stride_dataout,
indices_stride_size,
indices_begin_req_din,
indices_begin_req_full_n,
indices_begin_req_write,
indices_begin_rsp_empty_n,
indices_begin_rsp_read,
indices_begin_address,
indices_begin_datain,
indices_begin_dataout,
indices_begin_size,
ap_ce,
i_index,
i_sample,
indices_samples_req_din,
indices_samples_req_full_n,
indices_samples_req_write,
indices_samples_rsp_empty_n,
indices_samples_rsp_read,
indices_samples_address,
indices_samples_datain,
indices_samples_dataout,
indices_samples_size,
sample_buffer_size,
sample_length,
ap_return
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
output indices_stride_req_din;
input indices_stride_req_full_n;
output indices_stride_req_write;
input indices_stride_rsp_empty_n;
output indices_stride_rsp_read;
output [31:0] indices_stride_address;
input [7:0] indices_stride_datain;
output [7:0] indices_stride_dataout;
output [31:0] indices_stride_size;
output indices_begin_req_din;
input indices_begin_req_full_n;
output indices_begin_req_write;
input indices_begin_rsp_empty_n;
output indices_begin_rsp_read;
output [31:0] indices_begin_address;
input [31:0] indices_begin_datain;
output [31:0] indices_begin_dataout;
output [31:0] indices_begin_size;
input ap_ce;
input [15:0] i_index;
input [15:0] i_sample;
output indices_samples_req_din;
input indices_samples_req_full_n;
output indices_samples_req_write;
input indices_samples_rsp_empty_n;
output indices_samples_rsp_read;
output [31:0] indices_samples_address;
input [15:0] indices_samples_datain;
output [15:0] indices_samples_dataout;
output [31:0] indices_samples_size;
input [31:0] sample_buffer_size;
input [15:0] sample_length;
output [31:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg indices_stride_req_write;
reg indices_stride_rsp_read;
reg indices_begin_req_write;
reg indices_begin_rsp_read;
reg [0:0] ap_CS_fsm = 1'b0;
wire ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it1 = 1'b0;
reg ap_reg_ppiten_pp0_it2 = 1'b0;
reg ap_reg_ppiten_pp0_it3 = 1'b0;
reg ap_reg_ppiten_pp0_it4 = 1'b0;
reg ap_reg_ppiten_pp0_it5 = 1'b0;
reg ap_reg_ppiten_pp0_it6 = 1'b0;
reg ap_reg_ppiten_pp0_it7 = 1'b0;
reg ap_reg_ppiten_pp0_it8 = 1'b0;
reg ap_reg_ppiten_pp0_it9 = 1'b0;
reg ap_reg_ppiten_pp0_it10 = 1'b0;
reg ap_reg_ppiten_pp0_it11 = 1'b0;
reg ap_reg_ppiten_pp0_it12 = 1'b0;
reg ap_reg_ppiten_pp0_it13 = 1'b0;
reg ap_reg_ppiten_pp0_it14 = 1'b0;
reg ap_reg_ppiten_pp0_it15 = 1'b0;
reg ap_reg_ppiten_pp0_it16 = 1'b0;
reg ap_reg_ppiten_pp0_it17 = 1'b0;
reg [15:0] i_sample_read_reg_130;
reg [15:0] ap_reg_ppstg_i_sample_read_reg_130_pp0_it1;
reg [15:0] ap_reg_ppstg_i_sample_read_reg_130_pp0_it2;
reg [15:0] ap_reg_ppstg_i_sample_read_reg_130_pp0_it3;
reg [15:0] ap_reg_ppstg_i_sample_read_reg_130_pp0_it4;
reg [15:0] ap_reg_ppstg_i_sample_read_reg_130_pp0_it5;
reg [31:0] indices_begin_addr_reg_135;
reg [31:0] ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1;
reg [31:0] ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2;
reg [31:0] ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3;
reg [7:0] indices_stride_addr_read_reg_147;
reg [31:0] indices_begin_addr_read_reg_162;
wire [23:0] grp_fu_116_p2;
reg [23:0] tmp_2_reg_167;
wire [63:0] tmp_fu_93_p1;
wire [15:0] grp_fu_116_p0;
wire [7:0] grp_fu_116_p1;
wire [31:0] grp_fu_125_p0;
wire [31:0] grp_fu_125_p1;
reg grp_fu_116_ce;
wire [31:0] grp_fu_125_p2;
reg grp_fu_125_ce;
reg [0:0] ap_NS_fsm;
reg ap_sig_pprstidle_pp0;
wire [23:0] grp_fu_116_p00;
wire [23:0] grp_fu_116_p10;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_pp0_stg0_fsm_0 = 1'b0;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv8_0 = 8'b00000000;
parameter ap_const_lv16_0 = 16'b0000000000000000;
parameter ap_true = 1'b1;
nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 #(
.ID( 0 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 16 ),
.din1_WIDTH( 8 ),
.dout_WIDTH( 24 ))
nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_U0(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_116_p0 ),
.din1( grp_fu_116_p1 ),
.ce( grp_fu_116_ce ),
.dout( grp_fu_116_p2 )
);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U1(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_125_p0 ),
.din1( grp_fu_125_p1 ),
.ce( grp_fu_125_ce ),
.dout( grp_fu_125_p2 )
);
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end
end
end
/// ap_reg_ppiten_pp0_it10 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it10
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end
end
end
/// ap_reg_ppiten_pp0_it11 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it11
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end
end
end
/// ap_reg_ppiten_pp0_it12 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it12
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
end
end
end
/// ap_reg_ppiten_pp0_it13 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it13
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it13 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12;
end
end
end
/// ap_reg_ppiten_pp0_it14 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it14
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it14 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it14 <= ap_reg_ppiten_pp0_it13;
end
end
end
/// ap_reg_ppiten_pp0_it15 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it15
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it15 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it15 <= ap_reg_ppiten_pp0_it14;
end
end
end
/// ap_reg_ppiten_pp0_it16 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it16
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it16 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it16 <= ap_reg_ppiten_pp0_it15;
end
end
end
/// ap_reg_ppiten_pp0_it17 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it17
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it17 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it17 <= ap_reg_ppiten_pp0_it16;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end
end
end
/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end
end
end
/// ap_reg_ppiten_pp0_it4 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end
end
end
/// ap_reg_ppiten_pp0_it5 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end
end
end
/// ap_reg_ppiten_pp0_it6 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end
end
end
/// ap_reg_ppiten_pp0_it7 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it7
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end
end
end
/// ap_reg_ppiten_pp0_it8 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it8
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end
end
end
/// ap_reg_ppiten_pp0_it9 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it9
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 <= i_sample_read_reg_130;
ap_reg_ppstg_i_sample_read_reg_130_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it1;
ap_reg_ppstg_i_sample_read_reg_130_pp0_it3 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it2;
ap_reg_ppstg_i_sample_read_reg_130_pp0_it4 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it3;
ap_reg_ppstg_i_sample_read_reg_130_pp0_it5 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it4;
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[0] <= indices_begin_addr_reg_135[0];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[1] <= indices_begin_addr_reg_135[1];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[2] <= indices_begin_addr_reg_135[2];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[3] <= indices_begin_addr_reg_135[3];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[4] <= indices_begin_addr_reg_135[4];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[5] <= indices_begin_addr_reg_135[5];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[6] <= indices_begin_addr_reg_135[6];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[7] <= indices_begin_addr_reg_135[7];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[8] <= indices_begin_addr_reg_135[8];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[9] <= indices_begin_addr_reg_135[9];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[10] <= indices_begin_addr_reg_135[10];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[11] <= indices_begin_addr_reg_135[11];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[12] <= indices_begin_addr_reg_135[12];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[13] <= indices_begin_addr_reg_135[13];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[14] <= indices_begin_addr_reg_135[14];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[15] <= indices_begin_addr_reg_135[15];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[0] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[0];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[1] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[1];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[2] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[2];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[3] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[3];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[4] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[4];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[5] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[5];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[6] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[6];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[7] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[7];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[8] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[8];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[9] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[9];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[10] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[10];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[11] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[11];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[12] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[12];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[13] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[13];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[14] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[14];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[15] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[15];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3[0] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[0];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3[1] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[1];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3[2] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[2];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3[3] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[3];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3[4] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[4];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3[5] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[5];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3[6] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[6];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3[7] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[7];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3[8] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[8];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3[9] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[9];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3[10] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[10];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3[11] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[11];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3[12] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[12];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3[13] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[13];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3[14] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[14];
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3[15] <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[15];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
i_sample_read_reg_130 <= i_sample;
indices_begin_addr_reg_135[0] <= tmp_fu_93_p1[0];
indices_begin_addr_reg_135[1] <= tmp_fu_93_p1[1];
indices_begin_addr_reg_135[2] <= tmp_fu_93_p1[2];
indices_begin_addr_reg_135[3] <= tmp_fu_93_p1[3];
indices_begin_addr_reg_135[4] <= tmp_fu_93_p1[4];
indices_begin_addr_reg_135[5] <= tmp_fu_93_p1[5];
indices_begin_addr_reg_135[6] <= tmp_fu_93_p1[6];
indices_begin_addr_reg_135[7] <= tmp_fu_93_p1[7];
indices_begin_addr_reg_135[8] <= tmp_fu_93_p1[8];
indices_begin_addr_reg_135[9] <= tmp_fu_93_p1[9];
indices_begin_addr_reg_135[10] <= tmp_fu_93_p1[10];
indices_begin_addr_reg_135[11] <= tmp_fu_93_p1[11];
indices_begin_addr_reg_135[12] <= tmp_fu_93_p1[12];
indices_begin_addr_reg_135[13] <= tmp_fu_93_p1[13];
indices_begin_addr_reg_135[14] <= tmp_fu_93_p1[14];
indices_begin_addr_reg_135[15] <= tmp_fu_93_p1[15];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_begin_addr_read_reg_162 <= indices_begin_datain;
tmp_2_reg_167 <= grp_fu_116_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_stride_addr_read_reg_147 <= indices_stride_datain;
end
end
/// ap_done assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it5 or ap_reg_ppiten_pp0_it9 or ap_reg_ppiten_pp0_it17 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((~(ap_const_logic_1 == ap_start) & (ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0)) | ((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it17) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it4 or ap_reg_ppiten_pp0_it5 or ap_reg_ppiten_pp0_it6 or ap_reg_ppiten_pp0_it7 or ap_reg_ppiten_pp0_it8 or ap_reg_ppiten_pp0_it9 or ap_reg_ppiten_pp0_it10 or ap_reg_ppiten_pp0_it11 or ap_reg_ppiten_pp0_it12 or ap_reg_ppiten_pp0_it13 or ap_reg_ppiten_pp0_it14 or ap_reg_ppiten_pp0_it15 or ap_reg_ppiten_pp0_it16 or ap_reg_ppiten_pp0_it17)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it1) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it2) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it3) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it4) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it5) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it6) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it7) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it8) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it9) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it10) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it11) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it12) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it13) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it14) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it15) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it16) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it17))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it5 or ap_reg_ppiten_pp0_it9 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_pprstidle_pp0 assign process. ///
always @ (ap_start or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it4 or ap_reg_ppiten_pp0_it5 or ap_reg_ppiten_pp0_it6 or ap_reg_ppiten_pp0_it7 or ap_reg_ppiten_pp0_it8 or ap_reg_ppiten_pp0_it9 or ap_reg_ppiten_pp0_it10 or ap_reg_ppiten_pp0_it11 or ap_reg_ppiten_pp0_it12 or ap_reg_ppiten_pp0_it13 or ap_reg_ppiten_pp0_it14 or ap_reg_ppiten_pp0_it15 or ap_reg_ppiten_pp0_it16)
begin
if (((ap_const_logic_0 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it1) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it2) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it3) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it4) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it5) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it6) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it7) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it8) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it9) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it10) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it11) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it12) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it13) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it14) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it15) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it16) & (ap_const_logic_0 == ap_start))) begin
ap_sig_pprstidle_pp0 = ap_const_logic_1;
end else begin
ap_sig_pprstidle_pp0 = ap_const_logic_0;
end
end
/// grp_fu_116_ce assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it5 or ap_reg_ppiten_pp0_it9 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
grp_fu_116_ce = ap_const_logic_1;
end else begin
grp_fu_116_ce = ap_const_logic_0;
end
end
/// grp_fu_125_ce assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it5 or ap_reg_ppiten_pp0_it9 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
grp_fu_125_ce = ap_const_logic_1;
end else begin
grp_fu_125_ce = ap_const_logic_0;
end
end
/// indices_begin_req_write assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it4 or ap_reg_ppiten_pp0_it5 or ap_reg_ppiten_pp0_it9 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_begin_req_write = ap_const_logic_1;
end else begin
indices_begin_req_write = ap_const_logic_0;
end
end
/// indices_begin_rsp_read assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it5 or ap_reg_ppiten_pp0_it9 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_begin_rsp_read = ap_const_logic_1;
end else begin
indices_begin_rsp_read = ap_const_logic_0;
end
end
/// indices_stride_req_write assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it5 or ap_reg_ppiten_pp0_it9 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_stride_req_write = ap_const_logic_1;
end else begin
indices_stride_req_write = ap_const_logic_0;
end
end
/// indices_stride_rsp_read assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it5 or ap_reg_ppiten_pp0_it9 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_stride_rsp_read = ap_const_logic_1;
end else begin
indices_stride_rsp_read = ap_const_logic_0;
end
end
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it5 or ap_reg_ppiten_pp0_it9 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce or ap_sig_pprstidle_pp0)
begin
case (ap_CS_fsm)
ap_ST_pp0_stg0_fsm_0 :
ap_NS_fsm = ap_ST_pp0_stg0_fsm_0;
default :
ap_NS_fsm = 'bx;
endcase
end
assign ap_reg_ppiten_pp0_it0 = ap_start;
assign ap_return = grp_fu_125_p2;
assign grp_fu_116_p0 = grp_fu_116_p00;
assign grp_fu_116_p00 = $unsigned(ap_reg_ppstg_i_sample_read_reg_130_pp0_it5);
assign grp_fu_116_p1 = grp_fu_116_p10;
assign grp_fu_116_p10 = $unsigned(indices_stride_addr_read_reg_147);
assign grp_fu_125_p0 = $unsigned(tmp_2_reg_167);
assign grp_fu_125_p1 = indices_begin_addr_read_reg_162;
assign indices_begin_address = ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3;
assign indices_begin_dataout = ap_const_lv32_0;
assign indices_begin_req_din = ap_const_logic_0;
assign indices_begin_size = ap_const_lv32_1;
assign indices_samples_address = ap_const_lv32_0;
assign indices_samples_dataout = ap_const_lv16_0;
assign indices_samples_req_din = ap_const_logic_0;
assign indices_samples_req_write = ap_const_logic_0;
assign indices_samples_rsp_read = ap_const_logic_0;
assign indices_samples_size = ap_const_lv32_0;
assign indices_stride_address = tmp_fu_93_p1;
assign indices_stride_dataout = ap_const_lv8_0;
assign indices_stride_req_din = ap_const_logic_0;
assign indices_stride_size = ap_const_lv32_1;
assign tmp_fu_93_p1 = $unsigned(i_index);
always @ (posedge ap_clk)
begin
indices_begin_addr_reg_135[31:16] <= 16'b0000000000000000;
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1[31:16] <= 16'b0000000000000000;
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2[31:16] <= 16'b0000000000000000;
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3[31:16] <= 16'b0000000000000000;
end
endmodule //sample_iterator_get_offset
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:06:00 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7_51 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13_50 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_6 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_5 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_8 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire enable_Pipeline_input, Shift_reg_FLAGS_7_6, Shift_reg_FLAGS_7_5,
OP_FLAG_INIT, SIGN_FLAG_INIT, ZERO_FLAG_INIT, SIGN_FLAG_EXP,
OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1,
ZERO_FLAG_SHT1, ADD_OVRFLW_NRM, n_7_net_, left_right_SHT2,
bit_shift_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2,
ADD_OVRFLW_NRM2, SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2,
SIGN_FLAG_NRM, ZERO_FLAG_NRM, n_21_net_, SIGN_FLAG_SFG, ZERO_FLAG_SFG,
N59, N60, ADD_OVRFLW_SGF, inst_ShiftRegister_net3663114,
SFT2FRMT_STAGE_VARS_net3663024, FRMT_STAGE_DATAOUT_net3662952,
SGF_STAGE_DMP_net3663006, NRM_STAGE_Raw_mant_net3662988,
INPUT_STAGE_OPERANDY_net3662952, EXP_STAGE_DMP_net3663006,
SHT1_STAGE_DMP_net3663006, SHT2_STAGE_DMP_net3663006,
SHT2_SHIFT_DATA_net3662988, array_comparators_GTComparator_N0,
array_comparators_LTComparator_N0, n388, n389, n390,
DP_OP_15J181_122_6956_n18, DP_OP_15J181_122_6956_n17,
DP_OP_15J181_122_6956_n16, DP_OP_15J181_122_6956_n15,
DP_OP_15J181_122_6956_n14, DP_OP_15J181_122_6956_n8,
DP_OP_15J181_122_6956_n7, DP_OP_15J181_122_6956_n6,
DP_OP_15J181_122_6956_n5, DP_OP_15J181_122_6956_n4,
DP_OP_15J181_122_6956_n3, DP_OP_15J181_122_6956_n2,
DP_OP_15J181_122_6956_n1, intadd_429_CI, intadd_429_SUM_2_,
intadd_429_SUM_1_, intadd_429_SUM_0_, intadd_429_n3, intadd_429_n2,
intadd_429_n1, n393, n395, n396, n397, n398, n399, n400, n401, n402,
n403, n404, n405, n406, n407, n408, n409, n410, n411, n412, n413,
n414, n415, n416, n417, n418, n419, n420, n421, n422, n423, n424,
n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435,
n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, n446,
n447, n448, n449, n450, n451, n452, n453, n454, n455, n456, n457,
n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, n468,
n469, n470, n471, n472, n473, n474, n475, n476, n477, n478, n479,
n480, n481, n482, n483, n484, n485, n486, n487, n488, n489, n490,
n491, n492, n493, n494, n495, n496, n497, n498, n499, n500, n501,
n502, n503, n504, n505, n506, n507, n508, n509, n510, n511, n512,
n513, n514, n515, n516, n517, n518, n519, n520, n521, n522, n523,
n524, n525, n526, n527, n528, n529, n530, n531, n532, n533, n534,
n535, n536, n537, n538, n539, n540, n541, n542, n543, n544, n545,
n546, n547, n548, n549, n550, n551, n552, n553, n554, n555, n556,
n557, n558, n559, n560, n561, n562, n563, n564, n565, n566, n567,
n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, n578,
n579, n580, n581, n582, n583, n584, n585, n586, n587, n588, n589,
n590, n591, n592, n593, n594, n595, n596, n597, n598, n599, n600,
n601, n602, n603, n604, n605, n606, n607, n608, n609, n610, n611,
n612, n613, n615, n616, n617, n618, n619, n620, n621, n622, n623,
n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634,
n635, n636, n637, n638, n639, n640, n641, n642, n643, n644, n645,
n646, n647, n648, n649, n650, n651, n652, n653, n654, n655, n656,
n657, n658, n659, n660, n661, n662, n663, n664, n665, n666, n667,
n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678,
n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689,
n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700,
n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711,
n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722,
n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733,
n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744,
n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, n755,
n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n766,
n767, n768, n769, n770, n771, n772, n773, n774, n775, n776, n777,
n778, n779, n780, n781, n782, n783, n784, n785, n786, n787, n788,
n789, n790, n791, n792, n793, n794, n795, n796, n797, n798, n799,
n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, n810,
n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, n821,
n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832,
n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843,
n844, n845, n846, n847, n848, n849, n850, n851, n852, n853, n854,
n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, n865,
n866, n867, n868, n869, n870, n871, n872, n873, n874, n875, n876,
n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, n887,
n888, n889, n890, n891, n892, n893, n894, n895, n896, n897, n898,
n899, n900, n901, n902, n903, n904, n905, n906, n907, n908, n909,
n910, n911, n912, n913, n914, n915, n916, n917, n918, n919, n920,
n921, n922, n923, n924, n925, n926, n927, n928, n929, n930, n931,
n932, n933, n934, n935, n936, n937, n938, n939, n940, n941, n942,
n943, n944, n945, n946, n947, n948, n949, n950, n951, n952, n953,
n954, n955, n956, n957, n958, n959, n960, n961, n962, n963, n964,
n965, n966, n967, n968, n969, n970, n971, n972, n973, n974, n975,
n976, n977, n978, n979, n980, n981, n982, n983, n984, n985, n986,
n987, n988, n989, n990, n991, n992, n993, n994, n995, n996, n997,
n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007,
n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017,
n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027,
n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037,
n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047,
n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057,
n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067;
wire [3:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [30:0] intDY_EWSW;
wire [30:0] DMP_INIT_EWSW;
wire [27:0] DmP_INIT_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [4:0] Shift_amount_EXP_EW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [4:0] LZD_raw_out_EWR;
wire [4:2] shft_value_mux_o_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [51:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [25:0] sftr_odat_SHT2_SWR;
wire [4:0] LZD_output_NRM2_EW;
wire [7:0] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [24:2] DmP_mant_SFG_SWR;
wire [25:1] Raw_mant_SGF;
wire [31:0] formatted_number_W;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7_51 inst_ShiftRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n390), .ENCLK(inst_ShiftRegister_net3663114), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13_50 SFT2FRMT_STAGE_VARS_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7[1]), .ENCLK(
SFT2FRMT_STAGE_VARS_net3663024), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_6 FRMT_STAGE_DATAOUT_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7[0]), .ENCLK(
FRMT_STAGE_DATAOUT_net3662952), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_5 SGF_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(n_21_net_), .ENCLK(SGF_STAGE_DMP_net3663006), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_1 NRM_STAGE_Raw_mant_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7[2]), .ENCLK(
NRM_STAGE_Raw_mant_net3662988), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_7 INPUT_STAGE_OPERANDY_clk_gate_Q_reg (
.CLK(clk), .EN(enable_Pipeline_input), .ENCLK(
INPUT_STAGE_OPERANDY_net3662952), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_9 EXP_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7_6), .ENCLK(EXP_STAGE_DMP_net3663006),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_8 SHT1_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7_5), .ENCLK(SHT1_STAGE_DMP_net3663006),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_7 SHT2_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(busy), .ENCLK(SHT2_STAGE_DMP_net3663006), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_4 SHT2_SHIFT_DATA_clk_gate_Q_reg (
.CLK(clk), .EN(n_7_net_), .ENCLK(SHT2_SHIFT_DATA_net3662988), .TE(1'b0) );
DFFRXLTS inst_ShiftRegister_Q_reg_6_ ( .D(n1067), .CK(
inst_ShiftRegister_net3663114), .RN(n1037), .Q(Shift_reg_FLAGS_7_6) );
DFFRXLTS inst_ShiftRegister_Q_reg_5_ ( .D(Shift_reg_FLAGS_7_6), .CK(
inst_ShiftRegister_net3663114), .RN(n1036), .Q(Shift_reg_FLAGS_7_5) );
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(busy), .CK(
inst_ShiftRegister_net3663114), .RN(n1035), .Q(Shift_reg_FLAGS_7[3])
);
DFFRXLTS inst_ShiftRegister_Q_reg_2_ ( .D(Shift_reg_FLAGS_7[3]), .CK(
inst_ShiftRegister_net3663114), .RN(n1034), .Q(Shift_reg_FLAGS_7[2])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(Shift_amount_EXP_EW[0]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1055), .Q(Shift_amount_SHT1_EWR[0])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(Shift_amount_EXP_EW[1]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1035), .Q(Shift_amount_SHT1_EWR[1])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(Shift_amount_EXP_EW[2]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1055), .Q(Shift_amount_SHT1_EWR[2])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(Shift_amount_EXP_EW[3]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1034), .Q(Shift_amount_SHT1_EWR[3])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(Shift_amount_EXP_EW[4]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1040), .Q(Shift_amount_SHT1_EWR[4])
);
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1044),
.Q(ready) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(formatted_number_W[23]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1049), .Q(final_result_ieee[23])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(formatted_number_W[24]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1062), .Q(final_result_ieee[24])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(formatted_number_W[25]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1050), .Q(final_result_ieee[25])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(formatted_number_W[26]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1049), .Q(final_result_ieee[26])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(formatted_number_W[27]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1062), .Q(final_result_ieee[27])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(formatted_number_W[28]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1050), .Q(final_result_ieee[28])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(formatted_number_W[29]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1061), .Q(final_result_ieee[29])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(formatted_number_W[30]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1061), .Q(final_result_ieee[30])
);
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(array_comparators_LTComparator_N0),
.CK(FRMT_STAGE_DATAOUT_net3662952), .RN(n1061), .Q(underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(array_comparators_GTComparator_N0),
.CK(FRMT_STAGE_DATAOUT_net3662952), .RN(n1061), .Q(overflow_flag) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(Data_X[28]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1040), .Q(intDX_EWSW[28]), .QN(
n403) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(DmP_INIT_EWSW[0]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1038), .Q(DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(DmP_EXP_EWSW[0]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1054), .Q(DmP_mant_SHT1_SW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(DmP_INIT_EWSW[1]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1052), .Q(DmP_EXP_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(DmP_EXP_EWSW[1]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1046), .Q(DmP_mant_SHT1_SW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(DmP_INIT_EWSW[2]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1038), .Q(DmP_EXP_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(DmP_EXP_EWSW[2]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1054), .Q(DmP_mant_SHT1_SW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(DmP_INIT_EWSW[3]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1039), .Q(DmP_EXP_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(DmP_EXP_EWSW[3]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1039), .Q(DmP_mant_SHT1_SW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(DmP_INIT_EWSW[4]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1039), .Q(DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(DmP_EXP_EWSW[4]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1039), .Q(DmP_mant_SHT1_SW[4]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(DmP_INIT_EWSW[5]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1039), .Q(DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(DmP_EXP_EWSW[5]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1039), .Q(DmP_mant_SHT1_SW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(DmP_INIT_EWSW[6]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1039), .Q(DmP_EXP_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(DmP_EXP_EWSW[6]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1039), .Q(DmP_mant_SHT1_SW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(DmP_INIT_EWSW[7]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1039), .Q(DmP_EXP_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(DmP_EXP_EWSW[7]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1035), .Q(DmP_mant_SHT1_SW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(DmP_INIT_EWSW[8]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1055), .Q(DmP_EXP_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(DmP_EXP_EWSW[8]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1034), .Q(DmP_mant_SHT1_SW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(DmP_INIT_EWSW[9]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1040), .Q(DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(DmP_EXP_EWSW[9]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1044), .Q(DmP_mant_SHT1_SW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(DmP_INIT_EWSW[10]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1037), .Q(DmP_EXP_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(DmP_EXP_EWSW[10]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1036), .Q(DmP_mant_SHT1_SW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(DmP_INIT_EWSW[11]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1035), .Q(DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(DmP_EXP_EWSW[11]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1041), .Q(DmP_mant_SHT1_SW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(DmP_INIT_EWSW[12]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1041), .Q(DmP_EXP_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(DmP_EXP_EWSW[12]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1041), .Q(DmP_mant_SHT1_SW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(DmP_INIT_EWSW[13]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1041), .Q(DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(DmP_EXP_EWSW[13]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1041), .Q(DmP_mant_SHT1_SW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(DmP_INIT_EWSW[14]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1041), .Q(DmP_EXP_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(DmP_EXP_EWSW[14]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1041), .Q(DmP_mant_SHT1_SW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(DmP_INIT_EWSW[15]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1041), .Q(DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(DmP_EXP_EWSW[15]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1050), .Q(DmP_mant_SHT1_SW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(DmP_INIT_EWSW[16]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1042), .Q(DmP_EXP_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(DmP_EXP_EWSW[16]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1042), .Q(DmP_mant_SHT1_SW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(DmP_INIT_EWSW[17]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1042), .Q(DmP_EXP_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(DmP_EXP_EWSW[17]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1042), .Q(DmP_mant_SHT1_SW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(DmP_INIT_EWSW[18]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1042), .Q(DmP_EXP_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(DmP_EXP_EWSW[18]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1042), .Q(DmP_mant_SHT1_SW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(DmP_INIT_EWSW[19]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1042), .Q(DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(DmP_EXP_EWSW[19]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1047), .Q(DmP_mant_SHT1_SW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(DmP_INIT_EWSW[20]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1053), .Q(DmP_EXP_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(DmP_EXP_EWSW[20]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1043), .Q(DmP_mant_SHT1_SW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(DmP_INIT_EWSW[21]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1047), .Q(DmP_EXP_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(DmP_EXP_EWSW[21]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1053), .Q(DmP_mant_SHT1_SW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(DmP_INIT_EWSW[22]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1043), .Q(DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(DmP_EXP_EWSW[22]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1047), .Q(DmP_mant_SHT1_SW[22]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(DmP_INIT_EWSW[23]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1053), .Q(DmP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_24_ ( .D(DmP_INIT_EWSW[24]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1044), .Q(DmP_EXP_EWSW[24]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_25_ ( .D(DmP_INIT_EWSW[25]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1037), .Q(DmP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_26_ ( .D(DmP_INIT_EWSW[26]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1036), .Q(DmP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_27_ ( .D(DmP_INIT_EWSW[27]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1035), .Q(DmP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(DMP_INIT_EWSW[0]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1063), .Q(DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(DMP_INIT_EWSW[1]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1060), .Q(DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(DMP_INIT_EWSW[2]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1048), .Q(DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(DMP_INIT_EWSW[3]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n395), .Q(DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(DMP_INIT_EWSW[4]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1059), .Q(DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(DMP_INIT_EWSW[5]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1059), .Q(DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(DMP_INIT_EWSW[6]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n395), .Q(DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(DMP_INIT_EWSW[7]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1060), .Q(DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(DMP_INIT_EWSW[8]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1063), .Q(DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(DMP_INIT_EWSW[9]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n395), .Q(DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(DMP_INIT_EWSW[10]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1048), .Q(DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(DMP_INIT_EWSW[11]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1059), .Q(DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(DMP_INIT_EWSW[12]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1045), .Q(DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(DMP_INIT_EWSW[13]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n437), .Q(DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(DMP_INIT_EWSW[14]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1056), .Q(DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(DMP_INIT_EWSW[15]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1045), .Q(DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(DMP_INIT_EWSW[16]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n437), .Q(DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(DMP_INIT_EWSW[17]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1056), .Q(DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(DMP_INIT_EWSW[18]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1045), .Q(DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(DMP_INIT_EWSW[19]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n437), .Q(DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(DMP_INIT_EWSW[20]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1056), .Q(DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(DMP_INIT_EWSW[21]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1045), .Q(DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(DMP_INIT_EWSW[22]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1035), .Q(DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_23_ ( .D(DMP_INIT_EWSW[23]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1056), .Q(DMP_EXP_EWSW[23]), .QN(n406)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_24_ ( .D(DMP_INIT_EWSW[24]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1063), .Q(DMP_EXP_EWSW[24]), .QN(n1006) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_25_ ( .D(DMP_INIT_EWSW[25]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1047), .Q(DMP_EXP_EWSW[25]), .QN(n1032) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_26_ ( .D(DMP_INIT_EWSW[26]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1050), .Q(DMP_EXP_EWSW[26]), .QN(n1031) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(DMP_INIT_EWSW[27]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n437), .Q(DMP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(DMP_INIT_EWSW[28]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1046), .Q(DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(DMP_INIT_EWSW[29]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1050), .Q(DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(DMP_INIT_EWSW[30]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1053), .Q(DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_INIT), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1062), .Q(ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_INIT), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1056), .Q(OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_INIT), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1049), .Q(SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(DMP_EXP_EWSW[0]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1045), .Q(DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(DMP_EXP_EWSW[1]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1038), .Q(DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(DMP_EXP_EWSW[2]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n437), .Q(DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(DMP_EXP_EWSW[3]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1062), .Q(DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(DMP_EXP_EWSW[4]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1045), .Q(DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(DMP_EXP_EWSW[5]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1052), .Q(DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(DMP_EXP_EWSW[6]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1057), .Q(DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(DMP_EXP_EWSW[7]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1043), .Q(DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(DMP_EXP_EWSW[8]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1049), .Q(DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(DMP_EXP_EWSW[9]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1045), .Q(DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(DMP_EXP_EWSW[10]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1050), .Q(DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(DMP_EXP_EWSW[11]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n437), .Q(DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(DMP_EXP_EWSW[12]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1054), .Q(DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(DMP_EXP_EWSW[13]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1056), .Q(DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(DMP_EXP_EWSW[14]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1043), .Q(DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(DMP_EXP_EWSW[15]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1047), .Q(DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(DMP_EXP_EWSW[16]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1053), .Q(DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(DMP_EXP_EWSW[17]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1043), .Q(DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(DMP_EXP_EWSW[18]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1047), .Q(DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(DMP_EXP_EWSW[19]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1053), .Q(DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(DMP_EXP_EWSW[20]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1043), .Q(DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(DMP_EXP_EWSW[21]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1047), .Q(DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(DMP_EXP_EWSW[22]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1053), .Q(DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(DMP_EXP_EWSW[23]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1043), .Q(DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(DMP_EXP_EWSW[24]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1047), .Q(DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(DMP_EXP_EWSW[25]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1053), .Q(DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(DMP_EXP_EWSW[26]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1048), .Q(DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(DMP_EXP_EWSW[27]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1048), .Q(DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(DMP_EXP_EWSW[28]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1048), .Q(DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(DMP_EXP_EWSW[29]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1048), .Q(DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(DMP_EXP_EWSW[30]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1048), .Q(DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_EXP), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1048), .Q(ZERO_FLAG_SHT1) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_EXP), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1048), .Q(OP_FLAG_SHT1) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_EXP), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1048), .Q(SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(DMP_SHT1_EWSW[0]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1048), .Q(DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(DMP_SHT1_EWSW[1]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1048), .Q(DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(DMP_SHT1_EWSW[2]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1045), .Q(DMP_SHT2_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(DMP_SHT1_EWSW[3]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1049), .Q(DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(DMP_SHT1_EWSW[4]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1045), .Q(DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(DMP_SHT1_EWSW[5]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1052), .Q(DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(DMP_SHT1_EWSW[6]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1060), .Q(DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(DMP_SHT1_EWSW[7]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1049), .Q(DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(DMP_SHT1_EWSW[8]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1062), .Q(DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(DMP_SHT1_EWSW[9]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n437), .Q(DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(DMP_SHT1_EWSW[10]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1046), .Q(DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(DMP_SHT1_EWSW[11]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1057), .Q(DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(DMP_SHT1_EWSW[12]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1053), .Q(DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(DMP_SHT1_EWSW[13]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1062), .Q(DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(DMP_SHT1_EWSW[14]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n437), .Q(DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(DMP_SHT1_EWSW[15]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1058), .Q(DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(DMP_SHT1_EWSW[16]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1057), .Q(DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(DMP_SHT1_EWSW[17]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1059), .Q(DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(DMP_SHT1_EWSW[18]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n395), .Q(DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(DMP_SHT1_EWSW[19]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1063), .Q(DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(DMP_SHT1_EWSW[20]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1052), .Q(DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(DMP_SHT1_EWSW[21]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1046), .Q(DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(DMP_SHT1_EWSW[22]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1038), .Q(DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(DMP_SHT1_EWSW[23]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1054), .Q(DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(DMP_SHT2_EWSW[23]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1052), .Q(DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(DMP_SFG[23]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n395), .Q(DMP_exp_NRM_EW[0]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(DMP_exp_NRM_EW[0]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1059), .Q(DMP_exp_NRM2_EW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(DMP_SHT1_EWSW[24]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1046), .Q(DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(DMP_SHT2_EWSW[24]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1038), .Q(DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(DMP_SFG[24]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1058), .Q(DMP_exp_NRM_EW[1]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(DMP_exp_NRM_EW[1]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1063), .Q(DMP_exp_NRM2_EW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(DMP_SHT1_EWSW[25]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1054), .Q(DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(DMP_SHT2_EWSW[25]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1052), .Q(DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(DMP_SFG[25]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1057), .Q(DMP_exp_NRM_EW[2]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(DMP_exp_NRM_EW[2]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1051), .Q(DMP_exp_NRM2_EW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(DMP_SHT1_EWSW[26]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1043), .Q(DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(DMP_SHT2_EWSW[26]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1062), .Q(DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(DMP_SFG[26]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n438), .Q(DMP_exp_NRM_EW[3]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(DMP_exp_NRM_EW[3]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n395), .Q(DMP_exp_NRM2_EW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(DMP_SHT1_EWSW[27]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1056), .Q(DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(DMP_SHT2_EWSW[27]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1049), .Q(DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(DMP_SFG[27]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n395), .Q(DMP_exp_NRM_EW[4]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(DMP_exp_NRM_EW[4]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1057), .Q(DMP_exp_NRM2_EW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(DMP_SHT1_EWSW[28]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1056), .Q(DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(DMP_SHT2_EWSW[28]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1038), .Q(DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(DMP_SFG[28]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1059), .Q(DMP_exp_NRM_EW[5]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(DMP_exp_NRM_EW[5]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1058), .Q(DMP_exp_NRM2_EW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(DMP_SHT1_EWSW[29]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1063), .Q(DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(DMP_SHT2_EWSW[29]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1047), .Q(DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(DMP_SFG[29]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1063), .Q(DMP_exp_NRM_EW[6]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(DMP_exp_NRM_EW[6]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n395), .Q(DMP_exp_NRM2_EW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(DMP_SHT1_EWSW[30]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1050), .Q(DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(DMP_SHT2_EWSW[30]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n437), .Q(DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(DMP_SFG[30]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1051), .Q(DMP_exp_NRM_EW[7]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(DMP_exp_NRM_EW[7]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1058), .Q(DMP_exp_NRM2_EW[7]) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SHT1), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1059), .Q(ZERO_FLAG_SHT2) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_SHT1), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1050), .Q(OP_FLAG_SHT2) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_SHT1), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1054), .Q(SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SHT2), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1056), .Q(ZERO_FLAG_SFG) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(LZD_raw_out_EWR[3]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1050), .Q(LZD_output_NRM2_EW[3])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(LZD_raw_out_EWR[0]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1050), .Q(LZD_output_NRM2_EW[0])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(LZD_raw_out_EWR[2]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1049), .Q(LZD_output_NRM2_EW[2])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(LZD_raw_out_EWR[1]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1062), .Q(LZD_output_NRM2_EW[1])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(LZD_raw_out_EWR[4]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1062), .Q(LZD_output_NRM2_EW[4])
);
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_SHT2), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1059), .Q(SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SFG), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n395), .Q(ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_NRM), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1063), .Q(ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SHT1SHT2), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1058), .Q(zero_flag) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(SIGN_FLAG_SFG), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1051), .Q(SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(SIGN_FLAG_NRM), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n395), .Q(SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(formatted_number_W[31]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n438), .Q(final_result_ieee[31])
);
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(Data_array_SWR[3]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1050), .Q(Data_array_SWR[29]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(Data_array_SWR[2]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1051), .Q(Data_array_SWR[28]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(Data_array_SWR[1]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1057), .Q(Data_array_SWR[27]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(Data_array_SWR[0]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n395), .Q(Data_array_SWR[26]) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n1064), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n438), .Q(left_right_SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(formatted_number_W[8]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n437), .Q(final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(formatted_number_W[9]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1058), .Q(final_result_ieee[9])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(formatted_number_W[10]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1058), .Q(final_result_ieee[10])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(formatted_number_W[11]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1051), .Q(final_result_ieee[11])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(formatted_number_W[12]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1057), .Q(final_result_ieee[12])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(formatted_number_W[13]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n395), .Q(final_result_ieee[13])
);
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(sftr_odat_SHT2_SWR[1]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n438), .Q(N60) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(formatted_number_W[0]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1035), .Q(final_result_ieee[0])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(formatted_number_W[1]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1035), .Q(final_result_ieee[1])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(formatted_number_W[2]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n437), .Q(final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(formatted_number_W[3]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1057), .Q(final_result_ieee[3])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(formatted_number_W[4]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1063), .Q(final_result_ieee[4])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(formatted_number_W[5]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1058), .Q(final_result_ieee[5])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(formatted_number_W[6]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1051), .Q(final_result_ieee[6])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(formatted_number_W[7]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1060), .Q(final_result_ieee[7])
);
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(sftr_odat_SHT2_SWR[25]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1060), .QN(n405) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(formatted_number_W[14]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1060), .Q(final_result_ieee[14])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(formatted_number_W[15]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1060), .Q(final_result_ieee[15])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(formatted_number_W[16]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1060), .Q(final_result_ieee[16])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(formatted_number_W[17]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1060), .Q(final_result_ieee[17])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(formatted_number_W[18]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1060), .Q(final_result_ieee[18])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(formatted_number_W[19]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1061), .Q(final_result_ieee[19])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(formatted_number_W[20]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1061), .Q(final_result_ieee[20])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(formatted_number_W[21]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1061), .Q(final_result_ieee[21])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(formatted_number_W[22]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1061), .Q(final_result_ieee[22])
);
CMPR32X2TS DP_OP_15J181_122_6956_U9 ( .A(DMP_exp_NRM2_EW[0]), .B(n920), .C(
DP_OP_15J181_122_6956_n18), .CO(DP_OP_15J181_122_6956_n8), .S(
exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_15J181_122_6956_U8 ( .A(DP_OP_15J181_122_6956_n17), .B(
DMP_exp_NRM2_EW[1]), .C(DP_OP_15J181_122_6956_n8), .CO(
DP_OP_15J181_122_6956_n7), .S(exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_15J181_122_6956_U7 ( .A(DP_OP_15J181_122_6956_n16), .B(
DMP_exp_NRM2_EW[2]), .C(DP_OP_15J181_122_6956_n7), .CO(
DP_OP_15J181_122_6956_n6), .S(exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_15J181_122_6956_U6 ( .A(DP_OP_15J181_122_6956_n15), .B(
DMP_exp_NRM2_EW[3]), .C(DP_OP_15J181_122_6956_n6), .CO(
DP_OP_15J181_122_6956_n5), .S(exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS intadd_429_U4 ( .A(DmP_EXP_EWSW[24]), .B(n1006), .C(intadd_429_CI), .CO(intadd_429_n3), .S(intadd_429_SUM_0_) );
CMPR32X2TS intadd_429_U3 ( .A(DmP_EXP_EWSW[25]), .B(n1032), .C(intadd_429_n3), .CO(intadd_429_n2), .S(intadd_429_SUM_1_) );
CMPR32X2TS intadd_429_U2 ( .A(DmP_EXP_EWSW[26]), .B(n1031), .C(intadd_429_n2), .CO(intadd_429_n1), .S(intadd_429_SUM_2_) );
DFFSX2TS R_0 ( .D(n1033), .CK(INPUT_STAGE_OPERANDY_net3662952), .SN(n1035),
.Q(n1066) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(N59), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1052), .Q(Raw_mant_NRM_SWR[0]),
.QN(n1030) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(Data_Y[0]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1046), .Q(intDY_EWSW[0]), .QN(
n1029) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(Data_Y[26]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1040), .Q(intDY_EWSW[26]), .QN(
n1028) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(Data_Y[15]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1056), .Q(intDY_EWSW[15]), .QN(
n1027) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(Data_Y[3]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1054), .Q(intDY_EWSW[3]), .QN(
n1026) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(Data_Y[1]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1038), .Q(intDY_EWSW[1]), .QN(
n1025) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(Data_Y[11]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1037), .Q(intDY_EWSW[11]), .QN(
n1024) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(Data_Y[25]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1034), .Q(intDY_EWSW[25]), .QN(
n1023) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(Data_Y[18]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1042), .Q(intDY_EWSW[18]), .QN(
n1022) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(Data_Y[17]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1042), .Q(intDY_EWSW[17]), .QN(
n1021) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(Data_Y[8]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1035), .Q(intDY_EWSW[8]), .QN(
n1020) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(Data_Y[12]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1041), .Q(intDY_EWSW[12]), .QN(
n1019) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(Data_Y[27]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1044), .Q(intDY_EWSW[27]), .QN(
n1018) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(Data_Y[9]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1040), .Q(intDY_EWSW[9]), .QN(
n1017) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(Data_Y[22]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1053), .Q(intDY_EWSW[22]), .QN(
n1016) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(Data_Y[20]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1043), .Q(intDY_EWSW[20]), .QN(
n1015) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(Data_Y[2]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1052), .Q(intDY_EWSW[2]), .QN(
n1014) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(Data_Y[21]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1047), .Q(intDY_EWSW[21]), .QN(
n1013) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(Data_Y[13]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1041), .Q(intDY_EWSW[13]), .QN(
n1012) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(Data_Y[24]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1055), .Q(intDY_EWSW[24]), .QN(
n1011) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(Data_Y[10]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1044), .Q(intDY_EWSW[10]), .QN(
n1010) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(Data_Y[4]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1039), .Q(intDY_EWSW[4]), .QN(
n1009) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(Data_Y[16]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1042), .Q(intDY_EWSW[16]), .QN(
n1008) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(Data_Y[6]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1039), .Q(intDY_EWSW[6]), .QN(
n1007) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(Data_Y[5]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1054), .Q(intDY_EWSW[5]), .QN(
n1005) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(Data_Y[7]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1054), .Q(intDY_EWSW[7]), .QN(
n1004) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(Raw_mant_SGF[5]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1050), .Q(Raw_mant_NRM_SWR[5]),
.QN(n1003) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n389), .CK(clk), .RN(
n1035), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1002) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(DMP_SHT2_EWSW[22]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1054), .Q(DMP_SFG[22]), .QN(n1001) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(Data_array_SWR[21]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1037), .Q(Data_array_SWR[47]), .QN(
n1000) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(Data_array_SWR[20]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1035), .Q(Data_array_SWR[46]), .QN(
n999) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(Data_array_SWR[23]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1035), .Q(Data_array_SWR[49]), .QN(
n998) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(Data_array_SWR[22]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1036), .Q(Data_array_SWR[48]), .QN(
n997) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(sftr_odat_SHT2_SWR[23]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1061), .Q(DmP_mant_SFG_SWR[23]), .QN(
n996) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_20_ ( .D(DMP_SHT2_EWSW[20]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1046), .Q(DMP_SFG[20]), .QN(n995) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(Data_X[23]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1055), .Q(intDX_EWSW[23]), .QN(
n994) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(Data_X[7]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1037), .QN(n993) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(Data_X[5]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1055), .QN(n992) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(Data_X[16]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1034), .Q(intDX_EWSW[16]), .QN(
n991) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(Data_X[30]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1035), .Q(intDX_EWSW[30]), .QN(
n990) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(Data_X[29]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1035), .Q(intDX_EWSW[29]), .QN(
n989) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(Data_X[21]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1035), .Q(intDX_EWSW[21]), .QN(
n988) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(Data_X[13]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1040), .Q(intDX_EWSW[13]), .QN(
n987) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(Data_X[26]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1037), .Q(intDX_EWSW[26]), .QN(
n986) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(Data_X[19]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1037), .Q(intDX_EWSW[19]), .QN(
n985) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(Data_X[14]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1037), .Q(intDX_EWSW[14]), .QN(
n984) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(Data_X[12]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1035), .Q(intDX_EWSW[12]), .QN(
n983) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(Data_X[11]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1036), .Q(intDX_EWSW[11]), .QN(
n982) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(Data_X[25]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1044), .Q(intDX_EWSW[25]), .QN(
n981) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(Data_X[17]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1055), .Q(intDX_EWSW[17]), .QN(
n980) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(Data_X[10]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1055), .Q(intDX_EWSW[10]), .QN(
n979) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(Data_X[1]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1034), .Q(intDX_EWSW[1]), .QN(
n978) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(shft_value_mux_o_EWR[2]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1057), .Q(shift_value_SHT2_EWR[2]),
.QN(n977) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(sftr_odat_SHT2_SWR[21]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1061), .Q(DmP_mant_SFG_SWR[21]), .QN(
n975) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_18_ ( .D(DMP_SHT2_EWSW[18]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1059), .Q(DMP_SFG[18]), .QN(n974) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(Data_Y[29]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1037), .Q(intDY_EWSW[29]), .QN(
n973) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(sftr_odat_SHT2_SWR[19]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1060), .Q(DmP_mant_SFG_SWR[19]), .QN(
n972) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_16_ ( .D(DMP_SHT2_EWSW[16]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1051), .Q(DMP_SFG[16]), .QN(n971) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(Raw_mant_SGF[20]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1052), .Q(Raw_mant_NRM_SWR[20]),
.QN(n970) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(Raw_mant_SGF[12]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1054), .Q(Raw_mant_NRM_SWR[12]),
.QN(n969) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(Raw_mant_SGF[14]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1052), .Q(Raw_mant_NRM_SWR[14]),
.QN(n968) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(sftr_odat_SHT2_SWR[17]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1060), .Q(DmP_mant_SFG_SWR[17]), .QN(
n967) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(Raw_mant_SGF[17]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1038), .Q(Raw_mant_NRM_SWR[17]),
.QN(n966) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(Raw_mant_SGF[25]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1059), .Q(Raw_mant_NRM_SWR[25]),
.QN(n965) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(Raw_mant_SGF[18]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1046), .Q(Raw_mant_NRM_SWR[18]),
.QN(n964) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(sftr_odat_SHT2_SWR[15]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n395), .Q(DmP_mant_SFG_SWR[15]), .QN(
n963) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_14_ ( .D(DMP_SHT2_EWSW[14]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1063), .Q(DMP_SFG[14]), .QN(n962) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(Raw_mant_SGF[1]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1043), .Q(Raw_mant_NRM_SWR[1]),
.QN(n961) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(Raw_mant_SGF[3]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1045), .Q(Raw_mant_NRM_SWR[3]),
.QN(n960) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_12_ ( .D(DMP_SHT2_EWSW[12]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1038), .Q(DMP_SFG[12]), .QN(n959) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(sftr_odat_SHT2_SWR[13]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1063), .Q(DmP_mant_SFG_SWR[13]), .QN(
n958) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_10_ ( .D(DMP_SHT2_EWSW[10]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1049), .Q(DMP_SFG[10]), .QN(n957) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(Raw_mant_SGF[6]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1056), .Q(Raw_mant_NRM_SWR[6]),
.QN(n956) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(DMP_SHT2_EWSW[8]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1053), .Q(DMP_SFG[8]), .QN(n955) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_6_ ( .D(DMP_SHT2_EWSW[6]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1058), .Q(DMP_SFG[6]), .QN(n954) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(sftr_odat_SHT2_SWR[11]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n395), .Q(DmP_mant_SFG_SWR[11]), .QN(
n953) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(DMP_SHT2_EWSW[4]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1056), .Q(DMP_SFG[4]), .QN(n952) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_2_ ( .D(DMP_SHT2_EWSW[2]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1050), .Q(DMP_SFG[2]), .QN(n951) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(DMP_SHT2_EWSW[0]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1048), .Q(DMP_SFG[0]), .QN(n950) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(sftr_odat_SHT2_SWR[9]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1057), .Q(DmP_mant_SFG_SWR[9]), .QN(
n949) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(sftr_odat_SHT2_SWR[7]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n395), .Q(DmP_mant_SFG_SWR[7]), .QN(
n948) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(sftr_odat_SHT2_SWR[5]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1059), .Q(DmP_mant_SFG_SWR[5]), .QN(
n947) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(DMP_SHT2_EWSW[1]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1048), .Q(DMP_SFG[1]), .QN(n946) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(Data_Y[14]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1041), .Q(intDY_EWSW[14]), .QN(
n945) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(Data_Y[19]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1042), .Q(intDY_EWSW[19]), .QN(
n944) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n388), .CK(clk), .RN(
n1055), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]), .QN(n943) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(Data_Y[23]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1053), .Q(intDY_EWSW[23]), .QN(
n942) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(Data_array_SWR[24]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1055), .Q(Data_array_SWR[50]), .QN(
n941) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(Data_array_SWR[25]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1034), .Q(Data_array_SWR[51]), .QN(
n940) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_21_ ( .D(DMP_SHT2_EWSW[21]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1038), .Q(DMP_SFG[21]), .QN(n939) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(Data_X[0]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1055), .Q(intDX_EWSW[0]), .QN(
n938) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(Data_X[24]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1040), .Q(intDX_EWSW[24]), .QN(
n937) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(Data_X[6]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1036), .Q(intDX_EWSW[6]), .QN(
n936) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(Data_X[4]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1034), .Q(intDX_EWSW[4]), .QN(
n935) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(Data_X[2]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1040), .Q(intDX_EWSW[2]), .QN(
n934) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(Data_X[15]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1044), .Q(intDX_EWSW[15]), .QN(
n933) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(Data_X[3]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1044), .Q(intDX_EWSW[3]), .QN(
n932) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(Data_X[27]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1036), .Q(intDX_EWSW[27]), .QN(
n931) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(Data_X[22]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1034), .Q(intDX_EWSW[22]), .QN(
n930) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(Data_X[20]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1036), .Q(intDX_EWSW[20]), .QN(
n929) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(Data_X[18]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1034), .Q(intDX_EWSW[18]), .QN(
n928) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(Data_Y[30]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1036), .Q(intDY_EWSW[30]), .QN(
n927) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_19_ ( .D(DMP_SHT2_EWSW[19]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n395), .Q(DMP_SFG[19]), .QN(n926) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_17_ ( .D(DMP_SHT2_EWSW[17]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1057), .Q(DMP_SFG[17]), .QN(n925) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(Raw_mant_SGF[22]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n395), .Q(Raw_mant_NRM_SWR[22]),
.QN(n923) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_15_ ( .D(DMP_SHT2_EWSW[15]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1058), .Q(DMP_SFG[15]), .QN(n922) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_13_ ( .D(DMP_SHT2_EWSW[13]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1060), .Q(DMP_SFG[13]), .QN(n921) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_11_ ( .D(DMP_SHT2_EWSW[11]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1056), .Q(DMP_SFG[11]), .QN(n919) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(DMP_SHT2_EWSW[9]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1056), .Q(DMP_SFG[9]), .QN(n918) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(DMP_SHT2_EWSW[7]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1046), .Q(DMP_SFG[7]), .QN(n917) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(DMP_SHT2_EWSW[5]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1062), .Q(DMP_SFG[5]), .QN(n916) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_3_ ( .D(DMP_SHT2_EWSW[3]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1047), .Q(DMP_SFG[3]), .QN(n915) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(sftr_odat_SHT2_SWR[3]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n438), .Q(DmP_mant_SFG_SWR[3]), .QN(
n914) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(n1067), .CK(clk), .RN(
n1035), .Q(inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n913) );
CMPR32X2TS DP_OP_15J181_122_6956_U5 ( .A(DP_OP_15J181_122_6956_n14), .B(
DMP_exp_NRM2_EW[4]), .C(DP_OP_15J181_122_6956_n5), .CO(
DP_OP_15J181_122_6956_n4), .S(exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_15J181_122_6956_U4 ( .A(n920), .B(DMP_exp_NRM2_EW[5]), .C(
DP_OP_15J181_122_6956_n4), .CO(DP_OP_15J181_122_6956_n3), .S(
exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_15J181_122_6956_U3 ( .A(n920), .B(DMP_exp_NRM2_EW[6]), .C(
DP_OP_15J181_122_6956_n3), .CO(DP_OP_15J181_122_6956_n2), .S(
exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_15J181_122_6956_U2 ( .A(n920), .B(DMP_exp_NRM2_EW[7]), .C(
DP_OP_15J181_122_6956_n2), .CO(DP_OP_15J181_122_6956_n1), .S(
exp_rslt_NRM2_EW1[7]) );
DFFSX2TS SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n404), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .SN(n1049), .Q(n920), .QN(
ADD_OVRFLW_NRM2) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(Raw_mant_SGF[11]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1046), .Q(Raw_mant_NRM_SWR[11])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(Raw_mant_SGF[23]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1057), .Q(Raw_mant_NRM_SWR[23])
);
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(sftr_odat_SHT2_SWR[24]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1053), .Q(DmP_mant_SFG_SWR[24]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(Raw_mant_SGF[24]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1059), .Q(Raw_mant_NRM_SWR[24])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(Raw_mant_SGF[10]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1054), .Q(Raw_mant_NRM_SWR[10])
);
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(sftr_odat_SHT2_SWR[8]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1058), .Q(DmP_mant_SFG_SWR[8]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(sftr_odat_SHT2_SWR[6]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n395), .Q(DmP_mant_SFG_SWR[6]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(sftr_odat_SHT2_SWR[4]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n438), .Q(DmP_mant_SFG_SWR[4]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(sftr_odat_SHT2_SWR[10]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1051), .Q(DmP_mant_SFG_SWR[10]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(sftr_odat_SHT2_SWR[22]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1061), .Q(DmP_mant_SFG_SWR[22]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(sftr_odat_SHT2_SWR[20]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1060), .Q(DmP_mant_SFG_SWR[20]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(sftr_odat_SHT2_SWR[18]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1060), .Q(DmP_mant_SFG_SWR[18]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(sftr_odat_SHT2_SWR[16]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1060), .Q(DmP_mant_SFG_SWR[16]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(sftr_odat_SHT2_SWR[14]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1051), .Q(DmP_mant_SFG_SWR[14]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(sftr_odat_SHT2_SWR[12]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1058), .Q(DmP_mant_SFG_SWR[12]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(Raw_mant_SGF[21]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n395), .Q(Raw_mant_NRM_SWR[21]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(shft_value_mux_o_EWR[3]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1057), .Q(shift_value_SHT2_EWR[3])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(Raw_mant_SGF[16]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1054), .Q(Raw_mant_NRM_SWR[16])
);
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(Data_Y[28]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1044), .Q(intDY_EWSW[28]) );
DFFRX4TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_SHT2), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1048), .Q(n407), .QN(n1065) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(Data_array_SWR[16]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1040), .Q(Data_array_SWR[42]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(Data_array_SWR[17]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1044), .Q(Data_array_SWR[43]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(Raw_mant_SGF[7]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1056), .Q(Raw_mant_NRM_SWR[7]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(Raw_mant_SGF[19]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1046), .Q(Raw_mant_NRM_SWR[19])
);
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(sftr_odat_SHT2_SWR[2]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1058), .Q(DmP_mant_SFG_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(Data_array_SWR[18]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1037), .Q(Data_array_SWR[44]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(Data_array_SWR[19]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1036), .Q(Data_array_SWR[45]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(Raw_mant_SGF[8]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1050), .Q(Raw_mant_NRM_SWR[8]) );
DFFRX1TS inst_ShiftRegister_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[1]), .CK(
inst_ShiftRegister_net3663114), .RN(n1040), .Q(Shift_reg_FLAGS_7[0])
);
DFFRX1TS inst_ShiftRegister_Q_reg_4_ ( .D(Shift_reg_FLAGS_7_5), .CK(
inst_ShiftRegister_net3663114), .RN(n1044), .Q(busy) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(Data_array_SWR[9]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1053), .Q(Data_array_SWR[35]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(Data_array_SWR[8]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1058), .Q(Data_array_SWR[34]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(Data_array_SWR[10]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1062), .Q(Data_array_SWR[36]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(Data_array_SWR[11]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1045), .Q(Data_array_SWR[37]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(Data_X[8]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1036), .Q(intDX_EWSW[8]), .QN(
n396) );
DFFRX1TS SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n401), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1035), .Q(bit_shift_SHT2) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(Data_X[9]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1035), .Q(intDX_EWSW[9]), .QN(
n397) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(sftr_odat_SHT2_SWR[0]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n395), .Q(N59) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(Raw_mant_SGF[4]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1050), .Q(Raw_mant_NRM_SWR[4]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(Data_X[31]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1054), .Q(intDX_EWSW[31]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(Raw_mant_SGF[13]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1054), .Q(Raw_mant_NRM_SWR[13])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(Raw_mant_SGF[2]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1053), .Q(Raw_mant_NRM_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(Data_array_SWR[13]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1054), .Q(Data_array_SWR[39]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(Data_array_SWR[12]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1059), .Q(Data_array_SWR[38]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(Data_array_SWR[14]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1050), .Q(Data_array_SWR[40]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(Data_array_SWR[15]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1034), .Q(Data_array_SWR[41]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(Raw_mant_SGF[9]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1038), .Q(Raw_mant_NRM_SWR[9]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(Raw_mant_SGF[15]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1052), .Q(Raw_mant_NRM_SWR[15])
);
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(shft_value_mux_o_EWR[4]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1063), .Q(shift_value_SHT2_EWR[4]),
.QN(n976) );
DFFRX1TS NRM_STAGE_FLAGS_Q_reg_2_ ( .D(ADD_OVRFLW_SGF), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1057), .Q(ADD_OVRFLW_NRM), .QN(
n404) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(Data_array_SWR[6]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1043), .Q(Data_array_SWR[32]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(Data_array_SWR[7]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1057), .Q(Data_array_SWR[33]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(Data_array_SWR[5]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1049), .Q(Data_array_SWR[31]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(Data_array_SWR[4]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1056), .Q(Data_array_SWR[30]) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(Shift_reg_FLAGS_7[2]), .CK(
inst_ShiftRegister_net3663114), .RN(n1040), .Q(Shift_reg_FLAGS_7[1]),
.QN(n924) );
AOI32X4TS U582 ( .A0(n840), .A1(n839), .A2(n838), .B0(n837), .B1(n840), .Y(
n895) );
AOI211X2TS U583 ( .A0(Data_array_SWR[42]), .A1(n439), .B0(n485), .C0(n456),
.Y(n531) );
AOI211X2TS U584 ( .A0(Data_array_SWR[43]), .A1(n439), .B0(n485), .C0(n440),
.Y(n489) );
AOI222X4TS U585 ( .A0(DMP_SFG[18]), .A1(DmP_mant_SFG_SWR[20]), .B0(
DMP_SFG[18]), .B1(n701), .C0(DmP_mant_SFG_SWR[20]), .C1(n701), .Y(n879) );
AOI222X4TS U586 ( .A0(DMP_SFG[16]), .A1(DmP_mant_SFG_SWR[18]), .B0(
DMP_SFG[16]), .B1(n695), .C0(DmP_mant_SFG_SWR[18]), .C1(n695), .Y(n874) );
AOI222X2TS U587 ( .A0(DMP_SFG[12]), .A1(DmP_mant_SFG_SWR[14]), .B0(
DMP_SFG[12]), .B1(n683), .C0(DmP_mant_SFG_SWR[14]), .C1(n683), .Y(n864) );
AOI222X2TS U588 ( .A0(DMP_SFG[10]), .A1(DmP_mant_SFG_SWR[12]), .B0(
DMP_SFG[10]), .B1(n677), .C0(DmP_mant_SFG_SWR[12]), .C1(n677), .Y(n859) );
CLKINVX6TS U589 ( .A(n672), .Y(n583) );
INVX4TS U590 ( .A(n643), .Y(n592) );
NAND4XLTS U591 ( .A(n712), .B(n431), .C(n430), .D(n429), .Y(
LZD_raw_out_EWR[0]) );
NAND4XLTS U592 ( .A(n729), .B(n421), .C(n420), .D(n419), .Y(
LZD_raw_out_EWR[1]) );
NOR2X1TS U593 ( .A(array_comparators_LTComparator_N0), .B(
array_comparators_GTComparator_N0), .Y(n450) );
BUFX6TS U594 ( .A(n899), .Y(n393) );
NOR2X1TS U595 ( .A(Raw_mant_NRM_SWR[10]), .B(n723), .Y(n408) );
NAND2BX1TS U596 ( .AN(n723), .B(Raw_mant_NRM_SWR[10]), .Y(n718) );
NAND2X4TS U597 ( .A(n560), .B(n976), .Y(n441) );
NOR2X4TS U598 ( .A(n560), .B(n482), .Y(n452) );
NOR2X6TS U599 ( .A(shift_value_SHT2_EWR[4]), .B(n493), .Y(n444) );
NOR2X6TS U600 ( .A(shift_value_SHT2_EWR[4]), .B(n455), .Y(n443) );
NAND2X4TS U601 ( .A(n564), .B(n976), .Y(n451) );
CLKINVX3TS U602 ( .A(n505), .Y(n442) );
INVX3TS U603 ( .A(n890), .Y(n855) );
NOR2X4TS U604 ( .A(n564), .B(n482), .Y(n448) );
NOR2X6TS U605 ( .A(shift_value_SHT2_EWR[3]), .B(shift_value_SHT2_EWR[2]),
.Y(n439) );
BUFX6TS U606 ( .A(n437), .Y(n395) );
NAND2BXLTS U607 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n802) );
CLKAND2X2TS U608 ( .A(DmP_mant_SFG_SWR[4]), .B(n951), .Y(n525) );
CLKAND2X2TS U609 ( .A(DmP_mant_SFG_SWR[8]), .B(n954), .Y(n577) );
CLKAND2X2TS U610 ( .A(DmP_mant_SFG_SWR[10]), .B(n955), .Y(n587) );
AOI211X1TS U611 ( .A0(n443), .A1(Data_array_SWR[45]), .B0(n507), .C0(n499),
.Y(n512) );
CLKAND2X2TS U612 ( .A(DmP_mant_SFG_SWR[6]), .B(n952), .Y(n546) );
AOI211X1TS U613 ( .A0(Data_array_SWR[44]), .A1(n443), .B0(n507), .C0(n484),
.Y(n514) );
AOI222X4TS U614 ( .A0(n924), .A1(DmP_mant_SHT1_SW[0]), .B0(n611), .B1(
Raw_mant_NRM_SWR[23]), .C0(Raw_mant_NRM_SWR[2]), .C1(n401), .Y(n631)
);
AOI222X4TS U615 ( .A0(n924), .A1(DmP_mant_SHT1_SW[1]), .B0(n611), .B1(
Raw_mant_NRM_SWR[22]), .C0(Raw_mant_NRM_SWR[3]), .C1(n401), .Y(n627)
);
NAND2BXLTS U616 ( .AN(n713), .B(Raw_mant_NRM_SWR[4]), .Y(n722) );
NAND2BXLTS U617 ( .AN(Raw_mant_NRM_SWR[23]), .B(n923), .Y(n412) );
AO22XLTS U618 ( .A0(n1064), .A1(LZD_raw_out_EWR[4]), .B0(
Shift_amount_SHT1_EWR[4]), .B1(n912), .Y(shft_value_mux_o_EWR[4]) );
OAI21XLTS U619 ( .A0(n652), .A1(n399), .B0(n639), .Y(Data_array_SWR[19]) );
OAI21XLTS U620 ( .A0(n652), .A1(n904), .B0(n605), .Y(Data_array_SWR[18]) );
XOR2XLTS U621 ( .A(n878), .B(n877), .Y(Raw_mant_SGF[19]) );
OAI21XLTS U622 ( .A0(n651), .A1(n399), .B0(n624), .Y(Data_array_SWR[17]) );
OAI21XLTS U623 ( .A0(n656), .A1(n399), .B0(n655), .Y(Data_array_SWR[16]) );
OAI21XLTS U624 ( .A0(n686), .A1(n688), .B0(n685), .Y(n684) );
AO22XLTS U625 ( .A0(n1064), .A1(LZD_raw_out_EWR[3]), .B0(
Shift_amount_SHT1_EWR[3]), .B1(n912), .Y(shft_value_mux_o_EWR[3]) );
XOR2XLTS U626 ( .A(n883), .B(n882), .Y(Raw_mant_SGF[21]) );
XOR2XLTS U627 ( .A(n894), .B(n893), .Y(Raw_mant_SGF[24]) );
XOR2XLTS U628 ( .A(n888), .B(n887), .Y(Raw_mant_SGF[23]) );
OAI21XLTS U629 ( .A0(n704), .A1(n732), .B0(n703), .Y(n702) );
OAI21XLTS U630 ( .A0(n692), .A1(n694), .B0(n691), .Y(n690) );
XOR2XLTS U631 ( .A(n735), .B(n405), .Y(Raw_mant_SGF[25]) );
XOR2XLTS U632 ( .A(n873), .B(n872), .Y(Raw_mant_SGF[17]) );
OAI21XLTS U633 ( .A0(n698), .A1(n700), .B0(n697), .Y(n696) );
AO22XLTS U634 ( .A0(n1064), .A1(LZD_raw_out_EWR[2]), .B0(
Shift_amount_SHT1_EWR[2]), .B1(n912), .Y(shft_value_mux_o_EWR[2]) );
OAI21XLTS U635 ( .A0(n906), .A1(n592), .B0(n599), .Y(Data_array_SWR[22]) );
OAI21XLTS U636 ( .A0(n674), .A1(n399), .B0(n673), .Y(Data_array_SWR[20]) );
OAI21XLTS U637 ( .A0(n669), .A1(n399), .B0(n630), .Y(Data_array_SWR[21]) );
OAI211XLTS U638 ( .A0(n631), .A1(n583), .B0(n635), .C0(n585), .Y(
Data_array_SWR[0]) );
OAI21XLTS U639 ( .A0(n635), .A1(n399), .B0(n634), .Y(Data_array_SWR[1]) );
OAI21XLTS U640 ( .A0(n631), .A1(n399), .B0(n616), .Y(Data_array_SWR[2]) );
OAI21XLTS U641 ( .A0(n627), .A1(n399), .B0(n626), .Y(Data_array_SWR[3]) );
AOI211X1TS U642 ( .A0(n717), .A1(n716), .B0(n715), .C0(n726), .Y(n719) );
CLKINVX6TS U643 ( .A(rst), .Y(n437) );
OAI221X1TS U644 ( .A0(n979), .A1(intDY_EWSW[10]), .B0(n934), .B1(
intDY_EWSW[2]), .C0(n741), .Y(n744) );
OAI221X1TS U645 ( .A0(n932), .A1(intDY_EWSW[3]), .B0(n986), .B1(
intDY_EWSW[26]), .C0(n749), .Y(n752) );
OAI221X1TS U646 ( .A0(n931), .A1(intDY_EWSW[27]), .B0(n985), .B1(
intDY_EWSW[19]), .C0(n757), .Y(n760) );
OAI221X1TS U647 ( .A0(n980), .A1(intDY_EWSW[17]), .B0(n991), .B1(
intDY_EWSW[16]), .C0(n765), .Y(n768) );
OAI221X1TS U648 ( .A0(n929), .A1(intDY_EWSW[20]), .B0(n990), .B1(
intDY_EWSW[30]), .C0(n763), .Y(n770) );
OAI21X1TS U649 ( .A0(n493), .A1(n998), .B0(n492), .Y(n465) );
OAI21X1TS U650 ( .A0(n493), .A1(n997), .B0(n492), .Y(n494) );
OAI21XLTS U651 ( .A0(n650), .A1(n399), .B0(n649), .Y(Data_array_SWR[4]) );
OAI21XLTS U652 ( .A0(n645), .A1(n399), .B0(n618), .Y(Data_array_SWR[5]) );
OAI21XLTS U653 ( .A0(n646), .A1(n904), .B0(n608), .Y(Data_array_SWR[6]) );
NOR2X2TS U654 ( .A(n492), .B(n977), .Y(n485) );
OAI211X1TS U655 ( .A0(n976), .A1(n535), .B0(n458), .C0(n457), .Y(n480) );
AOI21X2TS U656 ( .A0(n439), .A1(Data_array_SWR[51]), .B0(n491), .Y(n535) );
OAI211X1TS U657 ( .A0(n976), .A1(n538), .B0(n447), .C0(n446), .Y(n453) );
AOI21X2TS U658 ( .A0(n439), .A1(Data_array_SWR[50]), .B0(n491), .Y(n538) );
BUFX4TS U659 ( .A(n1051), .Y(n1060) );
BUFX4TS U660 ( .A(n1051), .Y(n1048) );
BUFX4TS U661 ( .A(n437), .Y(n1063) );
BUFX4TS U662 ( .A(n437), .Y(n1059) );
BUFX6TS U663 ( .A(n437), .Y(n1057) );
BUFX4TS U664 ( .A(n437), .Y(n1058) );
OAI211X1TS U665 ( .A0(n976), .A1(n552), .B0(n551), .C0(n550), .Y(n559) );
AOI21X2TS U666 ( .A0(n439), .A1(Data_array_SWR[49]), .B0(n491), .Y(n552) );
BUFX6TS U667 ( .A(n1063), .Y(n1035) );
BUFX4TS U668 ( .A(n1057), .Y(n1054) );
AOI21X2TS U669 ( .A0(Data_array_SWR[48]), .A1(n439), .B0(n491), .Y(n557) );
AOI21X2TS U670 ( .A0(n439), .A1(Data_array_SWR[46]), .B0(n460), .Y(n473) );
OAI21X1TS U671 ( .A0(n493), .A1(n941), .B0(n492), .Y(n460) );
AOI21X2TS U672 ( .A0(n439), .A1(Data_array_SWR[47]), .B0(n461), .Y(n479) );
OAI21X1TS U673 ( .A0(n493), .A1(n940), .B0(n492), .Y(n461) );
BUFX4TS U674 ( .A(n1059), .Y(n1053) );
BUFX4TS U675 ( .A(n1063), .Y(n1050) );
BUFX4TS U676 ( .A(n1058), .Y(n1056) );
CLKINVX6TS U677 ( .A(n564), .Y(n560) );
BUFX6TS U678 ( .A(left_right_SHT2), .Y(n564) );
INVX2TS U679 ( .A(n582), .Y(n398) );
INVX4TS U680 ( .A(n398), .Y(n399) );
OAI21X2TS U681 ( .A0(n968), .A1(n610), .B0(n609), .Y(n660) );
OAI21X2TS U682 ( .A0(n964), .A1(n610), .B0(n603), .Y(n654) );
OAI21X2TS U683 ( .A0(n956), .A1(n610), .B0(n606), .Y(n648) );
OAI21X2TS U684 ( .A0(n594), .A1(n960), .B0(n593), .Y(n671) );
CLKINVX3TS U685 ( .A(n610), .Y(n400) );
INVX3TS U686 ( .A(n610), .Y(n401) );
BUFX4TS U687 ( .A(n445), .Y(n554) );
BUFX4TS U688 ( .A(n924), .Y(n912) );
INVX2TS U689 ( .A(n895), .Y(n902) );
INVX4TS U690 ( .A(n895), .Y(n901) );
INVX4TS U691 ( .A(n895), .Y(n897) );
INVX3TS U692 ( .A(n594), .Y(n611) );
NOR3X1TS U693 ( .A(Raw_mant_NRM_SWR[15]), .B(Raw_mant_NRM_SWR[16]), .C(
Raw_mant_NRM_SWR[17]), .Y(n714) );
OAI2BB1X1TS U694 ( .A0N(n1064), .A1N(Raw_mant_NRM_SWR[15]), .B0(n600), .Y(
n666) );
NOR2X1TS U695 ( .A(Raw_mant_NRM_SWR[9]), .B(Raw_mant_NRM_SWR[8]), .Y(n724)
);
NOR4X1TS U696 ( .A(Raw_mant_NRM_SWR[9]), .B(Raw_mant_NRM_SWR[13]), .C(
Raw_mant_NRM_SWR[11]), .D(n720), .Y(n427) );
OAI21XLTS U697 ( .A0(n658), .A1(n582), .B0(n641), .Y(Data_array_SWR[15]) );
OAI21XLTS U698 ( .A0(n658), .A1(n904), .B0(n613), .Y(Data_array_SWR[14]) );
OAI21XLTS U699 ( .A0(n662), .A1(n582), .B0(n661), .Y(Data_array_SWR[12]) );
OAI21XLTS U700 ( .A0(n657), .A1(n399), .B0(n620), .Y(Data_array_SWR[13]) );
NOR3X1TS U701 ( .A(Raw_mant_NRM_SWR[12]), .B(Raw_mant_NRM_SWR[13]), .C(
Raw_mant_NRM_SWR[11]), .Y(n721) );
OAI221X1TS U702 ( .A0(n993), .A1(intDY_EWSW[7]), .B0(n984), .B1(
intDY_EWSW[14]), .C0(n747), .Y(n754) );
INVX1TS U703 ( .A(n575), .Y(enable_Pipeline_input) );
AOI221X1TS U704 ( .A0(intDX_EWSW[30]), .A1(n927), .B0(intDX_EWSW[29]), .B1(
n973), .C0(n782), .Y(n784) );
AOI31XLTS U705 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n426), .A2(n416), .B0(n715),
.Y(n420) );
NOR2X2TS U706 ( .A(n968), .B(n415), .Y(n715) );
OAI211X2TS U707 ( .A0(intDX_EWSW[12]), .A1(n1019), .B0(n812), .C0(n798), .Y(
n814) );
AOI211XLTS U708 ( .A0(intDY_EWSW[16]), .A1(n991), .B0(n826), .C0(n827), .Y(
n818) );
OAI211X2TS U709 ( .A0(intDX_EWSW[20]), .A1(n1015), .B0(n832), .C0(n817), .Y(
n826) );
NOR3X6TS U710 ( .A(n436), .B(exp_rslt_NRM2_EW1[7]), .C(n433), .Y(
array_comparators_LTComparator_N0) );
XNOR2X2TS U711 ( .A(DP_OP_15J181_122_6956_n1), .B(ADD_OVRFLW_NRM2), .Y(n436)
);
CLKINVX6TS U712 ( .A(n895), .Y(n898) );
NOR3X2TS U713 ( .A(Raw_mant_NRM_SWR[5]), .B(Raw_mant_NRM_SWR[4]), .C(n713),
.Y(n710) );
OR2X1TS U714 ( .A(N60), .B(N59), .Y(n845) );
OAI21XLTS U715 ( .A0(n664), .A1(n399), .B0(n637), .Y(Data_array_SWR[11]) );
OAI21XLTS U716 ( .A0(n664), .A1(n904), .B0(n602), .Y(Data_array_SWR[10]) );
OAI21XLTS U717 ( .A0(n668), .A1(n399), .B0(n667), .Y(Data_array_SWR[8]) );
OAI21XLTS U718 ( .A0(n663), .A1(n582), .B0(n622), .Y(Data_array_SWR[9]) );
NOR2X4TS U719 ( .A(n596), .B(n595), .Y(n672) );
NOR2X4TS U720 ( .A(n584), .B(n596), .Y(n643) );
AOI22X2TS U721 ( .A0(n611), .A1(LZD_raw_out_EWR[1]), .B0(
Shift_amount_SHT1_EWR[1]), .B1(n924), .Y(n596) );
CLKBUFX2TS U722 ( .A(n907), .Y(n402) );
NAND2X2TS U723 ( .A(Shift_reg_FLAGS_7[1]), .B(ADD_OVRFLW_NRM), .Y(n610) );
OAI22X2TS U724 ( .A0(Shift_reg_FLAGS_7[1]), .A1(Shift_amount_SHT1_EWR[0]),
.B0(LZD_raw_out_EWR[0]), .B1(n594), .Y(n584) );
AOI21X2TS U725 ( .A0(n439), .A1(Data_array_SWR[45]), .B0(n465), .Y(n566) );
AOI21X2TS U726 ( .A0(n439), .A1(Data_array_SWR[44]), .B0(n494), .Y(n562) );
AOI222X4TS U727 ( .A0(DmP_mant_SFG_SWR[2]), .A1(n950), .B0(
DmP_mant_SFG_SWR[2]), .B1(n845), .C0(n950), .C1(n845), .Y(n520) );
NOR3X1TS U728 ( .A(Raw_mant_NRM_SWR[19]), .B(Raw_mant_NRM_SWR[20]), .C(
Raw_mant_NRM_SWR[21]), .Y(n708) );
NOR2X2TS U729 ( .A(Raw_mant_NRM_SWR[7]), .B(n409), .Y(n727) );
NOR3X1TS U730 ( .A(n403), .B(n781), .C(intDY_EWSW[28]), .Y(n782) );
OAI221X1TS U731 ( .A0(n900), .A1(intDY_EWSW[28]), .B0(n936), .B1(
intDY_EWSW[6]), .C0(n755), .Y(n762) );
AOI31XLTS U732 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n426), .A2(n966), .B0(n715),
.Y(n431) );
NAND2X2TS U733 ( .A(bit_shift_SHT2), .B(shift_value_SHT2_EWR[3]), .Y(n492)
);
NAND3X2TS U734 ( .A(shift_value_SHT2_EWR[3]), .B(shift_value_SHT2_EWR[2]),
.C(n976), .Y(n505) );
OAI32X1TS U735 ( .A0(Raw_mant_NRM_SWR[23]), .A1(Raw_mant_NRM_SWR[21]), .A2(
n970), .B0(n923), .B1(Raw_mant_NRM_SWR[23]), .Y(n428) );
AOI222X4TS U736 ( .A0(DMP_SFG[14]), .A1(DmP_mant_SFG_SWR[16]), .B0(
DMP_SFG[14]), .B1(n689), .C0(DmP_mant_SFG_SWR[16]), .C1(n689), .Y(n869) );
AOI222X4TS U737 ( .A0(DMP_SFG[20]), .A1(DmP_mant_SFG_SWR[22]), .B0(
DMP_SFG[20]), .B1(n733), .C0(DmP_mant_SFG_SWR[22]), .C1(n733), .Y(n884) );
AOI222X4TS U738 ( .A0(DMP_SFG[8]), .A1(DmP_mant_SFG_SWR[10]), .B0(DMP_SFG[8]), .B1(n588), .C0(DmP_mant_SFG_SWR[10]), .C1(n588), .Y(n853) );
AOI222X4TS U739 ( .A0(DMP_SFG[2]), .A1(DmP_mant_SFG_SWR[4]), .B0(DMP_SFG[2]),
.B1(n526), .C0(DmP_mant_SFG_SWR[4]), .C1(n526), .Y(n541) );
AOI222X4TS U740 ( .A0(DMP_SFG[4]), .A1(DmP_mant_SFG_SWR[6]), .B0(DMP_SFG[4]),
.B1(n547), .C0(DmP_mant_SFG_SWR[6]), .C1(n547), .Y(n571) );
AOI222X4TS U741 ( .A0(DMP_SFG[6]), .A1(DmP_mant_SFG_SWR[8]), .B0(DMP_SFG[6]),
.B1(n578), .C0(DmP_mant_SFG_SWR[8]), .C1(n578), .Y(n848) );
NOR4X2TS U742 ( .A(Raw_mant_NRM_SWR[24]), .B(Raw_mant_NRM_SWR[25]), .C(
Raw_mant_NRM_SWR[22]), .D(Raw_mant_NRM_SWR[23]), .Y(n705) );
AOI222X4TS U743 ( .A0(DMP_SFG[22]), .A1(DmP_mant_SFG_SWR[24]), .B0(
DMP_SFG[22]), .B1(n891), .C0(DmP_mant_SFG_SWR[24]), .C1(n891), .Y(n775) );
AOI31XLTS U744 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n425), .A2(n969), .B0(n424),
.Y(n419) );
INVX2TS U745 ( .A(intDX_EWSW[28]), .Y(n900) );
OAI21XLTS U746 ( .A0(intDX_EWSW[1]), .A1(n1025), .B0(intDX_EWSW[0]), .Y(n788) );
OAI21XLTS U747 ( .A0(intDX_EWSW[15]), .A1(n1027), .B0(intDX_EWSW[14]), .Y(
n808) );
NOR2XLTS U748 ( .A(n821), .B(intDY_EWSW[16]), .Y(n822) );
OAI21XLTS U749 ( .A0(intDX_EWSW[21]), .A1(n1013), .B0(intDX_EWSW[20]), .Y(
n820) );
OAI21XLTS U750 ( .A0(n505), .A1(n998), .B0(n498), .Y(n499) );
OAI211XLTS U751 ( .A0(n913), .A1(n908), .B0(n909), .C0(beg_OP), .Y(n575) );
OAI21XLTS U752 ( .A0(n581), .A1(n587), .B0(n580), .Y(n579) );
OAI21XLTS U753 ( .A0(n523), .A1(n525), .B0(n522), .Y(n521) );
OAI21XLTS U754 ( .A0(n906), .A1(n399), .B0(n610), .Y(Data_array_SWR[25]) );
OAI21XLTS U755 ( .A0(n646), .A1(n399), .B0(n644), .Y(Data_array_SWR[7]) );
OR2X1TS U756 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[4]), .Y(formatted_number_W[27]) );
NAND2X1TS U757 ( .A(n708), .B(n705), .Y(n418) );
NOR2X1TS U758 ( .A(Raw_mant_NRM_SWR[18]), .B(n418), .Y(n717) );
NAND2X1TS U759 ( .A(n717), .B(n714), .Y(n415) );
NOR2X1TS U760 ( .A(Raw_mant_NRM_SWR[14]), .B(n415), .Y(n417) );
NAND2X1TS U761 ( .A(n721), .B(n417), .Y(n723) );
NAND2X1TS U762 ( .A(n724), .B(n408), .Y(n409) );
NAND2X1TS U763 ( .A(n727), .B(n956), .Y(n713) );
OA21XLTS U764 ( .A0(Raw_mant_NRM_SWR[3]), .A1(Raw_mant_NRM_SWR[2]), .B0(n710), .Y(n411) );
INVX2TS U765 ( .A(n409), .Y(n410) );
OAI31X1TS U766 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n411), .A2(
Raw_mant_NRM_SWR[6]), .B0(n410), .Y(n729) );
NOR2XLTS U767 ( .A(Raw_mant_NRM_SWR[20]), .B(Raw_mant_NRM_SWR[21]), .Y(n414)
);
NOR2X1TS U768 ( .A(Raw_mant_NRM_SWR[24]), .B(Raw_mant_NRM_SWR[25]), .Y(n413)
);
AOI32X1TS U769 ( .A0(n414), .A1(n413), .A2(Raw_mant_NRM_SWR[19]), .B0(n412),
.B1(n413), .Y(n421) );
INVX2TS U770 ( .A(n418), .Y(n426) );
NOR2XLTS U771 ( .A(Raw_mant_NRM_SWR[16]), .B(Raw_mant_NRM_SWR[17]), .Y(n416)
);
INVX2TS U772 ( .A(n417), .Y(n720) );
NOR2X1TS U773 ( .A(Raw_mant_NRM_SWR[13]), .B(n720), .Y(n425) );
OAI21X1TS U774 ( .A0(n418), .A1(n964), .B0(n718), .Y(n424) );
AOI21X1TS U775 ( .A0(Raw_mant_NRM_SWR[0]), .A1(n961), .B0(
Raw_mant_NRM_SWR[2]), .Y(n422) );
NAND2X1TS U776 ( .A(n710), .B(n960), .Y(n730) );
OAI22X1TS U777 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n722), .B0(n422), .B1(n730),
.Y(n423) );
AOI211X1TS U778 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n425), .B0(n424), .C0(n423),
.Y(n712) );
AOI22X1TS U779 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n427), .B0(
Raw_mant_NRM_SWR[6]), .B1(n727), .Y(n430) );
OAI21XLTS U780 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n428), .B0(n965), .Y(n429)
);
OR4X2TS U781 ( .A(exp_rslt_NRM2_EW1[3]), .B(exp_rslt_NRM2_EW1[2]), .C(
exp_rslt_NRM2_EW1[1]), .D(exp_rslt_NRM2_EW1[0]), .Y(n432) );
OR4X2TS U782 ( .A(exp_rslt_NRM2_EW1[6]), .B(exp_rslt_NRM2_EW1[5]), .C(
exp_rslt_NRM2_EW1[4]), .D(n432), .Y(n433) );
AND4X1TS U783 ( .A(exp_rslt_NRM2_EW1[3]), .B(exp_rslt_NRM2_EW1[2]), .C(
exp_rslt_NRM2_EW1[1]), .D(exp_rslt_NRM2_EW1[0]), .Y(n434) );
AND4X1TS U784 ( .A(exp_rslt_NRM2_EW1[6]), .B(exp_rslt_NRM2_EW1[5]), .C(
exp_rslt_NRM2_EW1[4]), .D(n434), .Y(n435) );
AND3X1TS U785 ( .A(n436), .B(exp_rslt_NRM2_EW1[7]), .C(n435), .Y(
array_comparators_GTComparator_N0) );
AOI33XLTS U786 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[2]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(n943), .B1(n913), .B2(n1002),
.Y(n390) );
CLKBUFX2TS U787 ( .A(n437), .Y(n438) );
BUFX3TS U788 ( .A(n1057), .Y(n1046) );
BUFX3TS U789 ( .A(n1059), .Y(n1047) );
BUFX3TS U790 ( .A(n437), .Y(n1055) );
BUFX3TS U791 ( .A(n1057), .Y(n1052) );
BUFX3TS U792 ( .A(n1048), .Y(n1034) );
BUFX3TS U793 ( .A(n437), .Y(n1051) );
BUFX3TS U794 ( .A(n1063), .Y(n1049) );
BUFX3TS U795 ( .A(n1051), .Y(n1037) );
BUFX3TS U796 ( .A(n437), .Y(n1036) );
BUFX3TS U797 ( .A(n1058), .Y(n1045) );
BUFX3TS U798 ( .A(n1063), .Y(n1062) );
BUFX3TS U799 ( .A(n1059), .Y(n1061) );
BUFX3TS U800 ( .A(n1057), .Y(n1038) );
BUFX3TS U801 ( .A(n1058), .Y(n1041) );
BUFX3TS U802 ( .A(n1063), .Y(n1042) );
BUFX3TS U803 ( .A(n1053), .Y(n1044) );
BUFX3TS U804 ( .A(n1057), .Y(n1039) );
BUFX3TS U805 ( .A(n1059), .Y(n1043) );
BUFX3TS U806 ( .A(n1049), .Y(n1040) );
NAND2BX2TS U807 ( .AN(shift_value_SHT2_EWR[3]), .B(shift_value_SHT2_EWR[2]),
.Y(n493) );
NAND2X1TS U808 ( .A(shift_value_SHT2_EWR[3]), .B(n977), .Y(n455) );
OAI22X1TS U809 ( .A0(n493), .A1(n1000), .B0(n455), .B1(n940), .Y(n440) );
NOR2BX2TS U810 ( .AN(bit_shift_SHT2), .B(n439), .Y(n491) );
AOI22X1TS U811 ( .A0(n442), .A1(Data_array_SWR[46]), .B0(n443), .B1(
Data_array_SWR[42]), .Y(n447) );
NOR2BX1TS U812 ( .AN(n439), .B(shift_value_SHT2_EWR[4]), .Y(n445) );
AOI22X1TS U813 ( .A0(n444), .A1(Data_array_SWR[38]), .B0(n554), .B1(
Data_array_SWR[34]), .Y(n446) );
NAND2X1TS U814 ( .A(shift_value_SHT2_EWR[4]), .B(bit_shift_SHT2), .Y(n482)
);
AOI21X1TS U815 ( .A0(n564), .A1(n453), .B0(n448), .Y(n449) );
OAI21X1TS U816 ( .A0(n489), .A1(n441), .B0(n449), .Y(sftr_odat_SHT2_SWR[17])
);
BUFX4TS U817 ( .A(n450), .Y(n907) );
CLKAND2X2TS U818 ( .A(n907), .B(sftr_odat_SHT2_SWR[17]), .Y(
formatted_number_W[15]) );
AOI21X1TS U819 ( .A0(n560), .A1(n453), .B0(n452), .Y(n454) );
OAI21X1TS U820 ( .A0(n489), .A1(n451), .B0(n454), .Y(sftr_odat_SHT2_SWR[8])
);
CLKAND2X2TS U821 ( .A(n907), .B(sftr_odat_SHT2_SWR[8]), .Y(
formatted_number_W[6]) );
OAI22X1TS U822 ( .A0(n493), .A1(n999), .B0(n455), .B1(n941), .Y(n456) );
AOI22X1TS U823 ( .A0(n444), .A1(Data_array_SWR[39]), .B0(n443), .B1(
Data_array_SWR[43]), .Y(n458) );
AOI22X1TS U824 ( .A0(n554), .A1(Data_array_SWR[35]), .B0(n442), .B1(
Data_array_SWR[47]), .Y(n457) );
AOI21X1TS U825 ( .A0(n560), .A1(n480), .B0(n452), .Y(n459) );
OAI21X1TS U826 ( .A0(n531), .A1(n451), .B0(n459), .Y(sftr_odat_SHT2_SWR[9])
);
CLKAND2X2TS U827 ( .A(n907), .B(sftr_odat_SHT2_SWR[9]), .Y(
formatted_number_W[7]) );
AOI22X1TS U828 ( .A0(n442), .A1(Data_array_SWR[43]), .B0(n443), .B1(
Data_array_SWR[39]), .Y(n463) );
AOI22X1TS U829 ( .A0(n444), .A1(Data_array_SWR[35]), .B0(n554), .B1(
Data_array_SWR[31]), .Y(n462) );
OAI211X1TS U830 ( .A0(n479), .A1(n976), .B0(n463), .C0(n462), .Y(n469) );
AOI21X1TS U831 ( .A0(n560), .A1(n469), .B0(n452), .Y(n464) );
OAI21X1TS U832 ( .A0(n473), .A1(n451), .B0(n464), .Y(sftr_odat_SHT2_SWR[5])
);
CLKAND2X2TS U833 ( .A(n907), .B(sftr_odat_SHT2_SWR[5]), .Y(
formatted_number_W[3]) );
AOI22X1TS U834 ( .A0(n442), .A1(Data_array_SWR[41]), .B0(n443), .B1(
Data_array_SWR[37]), .Y(n467) );
AOI22X1TS U835 ( .A0(n444), .A1(Data_array_SWR[33]), .B0(n554), .B1(
Data_array_SWR[29]), .Y(n466) );
OAI211X1TS U836 ( .A0(n566), .A1(n976), .B0(n467), .C0(n466), .Y(n475) );
AOI21X1TS U837 ( .A0(n564), .A1(n475), .B0(n448), .Y(n468) );
OAI21X1TS U838 ( .A0(n557), .A1(n441), .B0(n468), .Y(sftr_odat_SHT2_SWR[22])
);
CLKAND2X2TS U839 ( .A(n907), .B(sftr_odat_SHT2_SWR[22]), .Y(
formatted_number_W[20]) );
AOI21X1TS U840 ( .A0(n564), .A1(n469), .B0(n448), .Y(n470) );
OAI21X1TS U841 ( .A0(n473), .A1(n441), .B0(n470), .Y(sftr_odat_SHT2_SWR[20])
);
CLKAND2X2TS U842 ( .A(n907), .B(sftr_odat_SHT2_SWR[20]), .Y(
formatted_number_W[18]) );
AOI22X1TS U843 ( .A0(n442), .A1(Data_array_SWR[42]), .B0(n443), .B1(
Data_array_SWR[38]), .Y(n472) );
AOI22X1TS U844 ( .A0(n444), .A1(Data_array_SWR[34]), .B0(n554), .B1(
Data_array_SWR[30]), .Y(n471) );
OAI211X1TS U845 ( .A0(n473), .A1(n976), .B0(n472), .C0(n471), .Y(n477) );
AOI21X1TS U846 ( .A0(n560), .A1(n477), .B0(n452), .Y(n474) );
OAI21X1TS U847 ( .A0(n479), .A1(n451), .B0(n474), .Y(sftr_odat_SHT2_SWR[4])
);
CLKAND2X2TS U848 ( .A(n907), .B(sftr_odat_SHT2_SWR[4]), .Y(
formatted_number_W[2]) );
AOI21X1TS U849 ( .A0(n560), .A1(n475), .B0(n452), .Y(n476) );
OAI21X1TS U850 ( .A0(n451), .A1(n557), .B0(n476), .Y(sftr_odat_SHT2_SWR[3])
);
CLKAND2X2TS U851 ( .A(n907), .B(sftr_odat_SHT2_SWR[3]), .Y(
formatted_number_W[1]) );
AOI21X1TS U852 ( .A0(n564), .A1(n477), .B0(n448), .Y(n478) );
OAI21X1TS U853 ( .A0(n479), .A1(n441), .B0(n478), .Y(sftr_odat_SHT2_SWR[21])
);
CLKAND2X2TS U854 ( .A(n907), .B(sftr_odat_SHT2_SWR[21]), .Y(
formatted_number_W[19]) );
AOI21X1TS U855 ( .A0(n564), .A1(n480), .B0(n448), .Y(n481) );
OAI21X1TS U856 ( .A0(n531), .A1(n441), .B0(n481), .Y(sftr_odat_SHT2_SWR[16])
);
CLKAND2X2TS U857 ( .A(n907), .B(sftr_odat_SHT2_SWR[16]), .Y(
formatted_number_W[14]) );
INVX2TS U858 ( .A(n482), .Y(n507) );
AOI22X1TS U859 ( .A0(n444), .A1(Data_array_SWR[40]), .B0(n554), .B1(
Data_array_SWR[36]), .Y(n483) );
OAI21XLTS U860 ( .A0(n997), .A1(n505), .B0(n483), .Y(n484) );
OR2X1TS U861 ( .A(n485), .B(n507), .Y(n501) );
AO22XLTS U862 ( .A0(n444), .A1(Data_array_SWR[45]), .B0(n554), .B1(
Data_array_SWR[41]), .Y(n486) );
AOI211X1TS U863 ( .A0(n443), .A1(Data_array_SWR[49]), .B0(n501), .C0(n486),
.Y(n515) );
AOI22X1TS U864 ( .A0(n564), .A1(n514), .B0(n515), .B1(n560), .Y(
sftr_odat_SHT2_SWR[15]) );
CLKAND2X2TS U865 ( .A(n907), .B(sftr_odat_SHT2_SWR[15]), .Y(
formatted_number_W[13]) );
AOI22X1TS U866 ( .A0(n444), .A1(Data_array_SWR[31]), .B0(n554), .B1(
Data_array_SWR[27]), .Y(n488) );
AOI22X1TS U867 ( .A0(n442), .A1(Data_array_SWR[39]), .B0(n443), .B1(
Data_array_SWR[35]), .Y(n487) );
OAI211X1TS U868 ( .A0(n489), .A1(n976), .B0(n488), .C0(n487), .Y(n536) );
AOI21X1TS U869 ( .A0(n564), .A1(n536), .B0(n448), .Y(n490) );
OAI21X1TS U870 ( .A0(n538), .A1(n441), .B0(n490), .Y(sftr_odat_SHT2_SWR[24])
);
CLKAND2X2TS U871 ( .A(n907), .B(sftr_odat_SHT2_SWR[24]), .Y(
formatted_number_W[22]) );
AOI22X1TS U872 ( .A0(n442), .A1(Data_array_SWR[40]), .B0(n443), .B1(
Data_array_SWR[36]), .Y(n496) );
AOI22X1TS U873 ( .A0(n444), .A1(Data_array_SWR[32]), .B0(n554), .B1(
Data_array_SWR[28]), .Y(n495) );
OAI211X1TS U874 ( .A0(n562), .A1(n976), .B0(n496), .C0(n495), .Y(n508) );
AOI21X1TS U875 ( .A0(n564), .A1(n508), .B0(n448), .Y(n497) );
OAI21X1TS U876 ( .A0(n552), .A1(n441), .B0(n497), .Y(sftr_odat_SHT2_SWR[23])
);
CLKAND2X2TS U877 ( .A(n907), .B(sftr_odat_SHT2_SWR[23]), .Y(
formatted_number_W[21]) );
AOI22X1TS U878 ( .A0(n444), .A1(Data_array_SWR[41]), .B0(n554), .B1(
Data_array_SWR[37]), .Y(n498) );
AO22XLTS U879 ( .A0(Data_array_SWR[44]), .A1(n444), .B0(n554), .B1(
Data_array_SWR[40]), .Y(n500) );
AOI211X1TS U880 ( .A0(Data_array_SWR[48]), .A1(n443), .B0(n501), .C0(n500),
.Y(n513) );
AOI22X1TS U881 ( .A0(n564), .A1(n512), .B0(n513), .B1(n560), .Y(
sftr_odat_SHT2_SWR[14]) );
CLKAND2X2TS U882 ( .A(n907), .B(sftr_odat_SHT2_SWR[14]), .Y(
formatted_number_W[12]) );
AOI22X1TS U883 ( .A0(n444), .A1(Data_array_SWR[42]), .B0(n554), .B1(
Data_array_SWR[38]), .Y(n502) );
OAI21XLTS U884 ( .A0(n505), .A1(n941), .B0(n502), .Y(n503) );
AOI211X1TS U885 ( .A0(n443), .A1(Data_array_SWR[46]), .B0(n507), .C0(n503),
.Y(n510) );
AOI22X1TS U886 ( .A0(n444), .A1(Data_array_SWR[43]), .B0(n554), .B1(
Data_array_SWR[39]), .Y(n504) );
OAI21XLTS U887 ( .A0(n505), .A1(n940), .B0(n504), .Y(n506) );
AOI211X1TS U888 ( .A0(n443), .A1(Data_array_SWR[47]), .B0(n507), .C0(n506),
.Y(n511) );
AOI22X1TS U889 ( .A0(n564), .A1(n510), .B0(n511), .B1(n560), .Y(
sftr_odat_SHT2_SWR[13]) );
CLKAND2X2TS U890 ( .A(n907), .B(sftr_odat_SHT2_SWR[13]), .Y(
formatted_number_W[11]) );
AOI21X1TS U891 ( .A0(n560), .A1(n508), .B0(n452), .Y(n509) );
OAI21X1TS U892 ( .A0(n552), .A1(n451), .B0(n509), .Y(sftr_odat_SHT2_SWR[2])
);
CLKAND2X2TS U893 ( .A(n907), .B(sftr_odat_SHT2_SWR[2]), .Y(
formatted_number_W[0]) );
AOI22X1TS U894 ( .A0(n564), .A1(n511), .B0(n510), .B1(n560), .Y(
sftr_odat_SHT2_SWR[12]) );
CLKAND2X2TS U895 ( .A(n907), .B(sftr_odat_SHT2_SWR[12]), .Y(
formatted_number_W[10]) );
AOI22X1TS U896 ( .A0(n564), .A1(n513), .B0(n512), .B1(n560), .Y(
sftr_odat_SHT2_SWR[11]) );
CLKAND2X2TS U897 ( .A(n907), .B(sftr_odat_SHT2_SWR[11]), .Y(
formatted_number_W[9]) );
AOI22X1TS U898 ( .A0(n564), .A1(n515), .B0(n514), .B1(n560), .Y(
sftr_odat_SHT2_SWR[10]) );
CLKAND2X2TS U899 ( .A(n402), .B(sftr_odat_SHT2_SWR[10]), .Y(
formatted_number_W[8]) );
OR2X2TS U900 ( .A(ADD_OVRFLW_NRM), .B(n912), .Y(n594) );
INVX4TS U901 ( .A(n594), .Y(n1064) );
NAND2X1TS U902 ( .A(DmP_EXP_EWSW[23]), .B(n406), .Y(n516) );
OAI21XLTS U903 ( .A0(DmP_EXP_EWSW[23]), .A1(n406), .B0(n516), .Y(
Shift_amount_EXP_EW[0]) );
NAND2X1TS U904 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n913), .Y(n909)
);
NAND2X1TS U905 ( .A(n943), .B(inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n908)
);
OAI21XLTS U906 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(n909), .B0(
n908), .Y(n388) );
INVX2TS U907 ( .A(intadd_429_SUM_0_), .Y(Shift_amount_EXP_EW[1]) );
INVX2TS U908 ( .A(intadd_429_SUM_1_), .Y(Shift_amount_EXP_EW[2]) );
INVX2TS U909 ( .A(intadd_429_SUM_2_), .Y(Shift_amount_EXP_EW[3]) );
INVX2TS U910 ( .A(n516), .Y(intadd_429_CI) );
CLKBUFX2TS U911 ( .A(n1065), .Y(n890) );
NAND2X1TS U912 ( .A(DMP_SFG[0]), .B(DmP_mant_SFG_SWR[2]), .Y(n844) );
AOI22X1TS U913 ( .A0(n855), .A1(n520), .B0(n844), .B1(n890), .Y(n518) );
NAND2X1TS U914 ( .A(DmP_mant_SFG_SWR[3]), .B(n946), .Y(n519) );
OAI21XLTS U915 ( .A0(DmP_mant_SFG_SWR[3]), .A1(n946), .B0(n519), .Y(n517) );
XOR2XLTS U916 ( .A(n518), .B(n517), .Y(Raw_mant_SGF[3]) );
NOR2X1TS U917 ( .A(DmP_mant_SFG_SWR[4]), .B(n951), .Y(n523) );
AOI22X1TS U918 ( .A0(DMP_SFG[1]), .A1(n914), .B0(n520), .B1(n519), .Y(n524)
);
AOI222X4TS U919 ( .A0(n946), .A1(n844), .B0(n946), .B1(n914), .C0(n844),
.C1(n914), .Y(n526) );
AOI22X1TS U920 ( .A0(n855), .A1(n524), .B0(n526), .B1(n1065), .Y(n522) );
OAI31X1TS U921 ( .A0(n523), .A1(n522), .A2(n525), .B0(n521), .Y(
Raw_mant_SGF[4]) );
OAI22X1TS U922 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n951), .B0(n525), .B1(n524),
.Y(n539) );
AOI22X1TS U923 ( .A0(n855), .A1(n539), .B0(n541), .B1(n1065), .Y(n528) );
NAND2X1TS U924 ( .A(DmP_mant_SFG_SWR[5]), .B(n915), .Y(n540) );
OAI21XLTS U925 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n915), .B0(n540), .Y(n527) );
XOR2XLTS U926 ( .A(n528), .B(n527), .Y(Raw_mant_SGF[5]) );
AOI22X1TS U927 ( .A0(n444), .A1(Data_array_SWR[30]), .B0(n443), .B1(
Data_array_SWR[34]), .Y(n530) );
AOI22X1TS U928 ( .A0(n554), .A1(Data_array_SWR[26]), .B0(n442), .B1(
Data_array_SWR[38]), .Y(n529) );
OAI211X1TS U929 ( .A0(n531), .A1(n976), .B0(n530), .C0(n529), .Y(n533) );
AOI21X1TS U930 ( .A0(n564), .A1(n533), .B0(n448), .Y(n532) );
OAI21XLTS U931 ( .A0(n535), .A1(n441), .B0(n532), .Y(sftr_odat_SHT2_SWR[25])
);
AOI21X1TS U932 ( .A0(n560), .A1(n533), .B0(n452), .Y(n534) );
OAI21XLTS U933 ( .A0(n451), .A1(n535), .B0(n534), .Y(sftr_odat_SHT2_SWR[0])
);
AOI21X1TS U934 ( .A0(n560), .A1(n536), .B0(n452), .Y(n537) );
OAI21XLTS U935 ( .A0(n451), .A1(n538), .B0(n537), .Y(sftr_odat_SHT2_SWR[1])
);
NOR2X1TS U936 ( .A(DmP_mant_SFG_SWR[6]), .B(n952), .Y(n544) );
AOI22X1TS U937 ( .A0(DMP_SFG[3]), .A1(n947), .B0(n540), .B1(n539), .Y(n545)
);
AOI222X4TS U938 ( .A0(n541), .A1(n915), .B0(n541), .B1(n947), .C0(n915),
.C1(n947), .Y(n547) );
AOI22X1TS U939 ( .A0(n855), .A1(n545), .B0(n547), .B1(n1065), .Y(n543) );
OAI21XLTS U940 ( .A0(n544), .A1(n546), .B0(n543), .Y(n542) );
OAI31X1TS U941 ( .A0(n544), .A1(n543), .A2(n546), .B0(n542), .Y(
Raw_mant_SGF[6]) );
OAI22X1TS U942 ( .A0(DmP_mant_SFG_SWR[6]), .A1(n952), .B0(n546), .B1(n545),
.Y(n569) );
AOI22X1TS U943 ( .A0(n855), .A1(n569), .B0(n571), .B1(n1065), .Y(n549) );
NAND2X1TS U944 ( .A(DmP_mant_SFG_SWR[7]), .B(n916), .Y(n570) );
OAI21XLTS U945 ( .A0(DmP_mant_SFG_SWR[7]), .A1(n916), .B0(n570), .Y(n548) );
XOR2XLTS U946 ( .A(n549), .B(n548), .Y(Raw_mant_SGF[7]) );
OR2X1TS U947 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[3]), .Y(formatted_number_W[26]) );
OR2X1TS U948 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[5]), .Y(formatted_number_W[28]) );
OR2X1TS U949 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[0]), .Y(formatted_number_W[23]) );
OR2X1TS U950 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[6]), .Y(formatted_number_W[29]) );
OR2X1TS U951 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[2]), .Y(formatted_number_W[25]) );
OR2X1TS U952 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[1]), .Y(formatted_number_W[24]) );
AOI22X1TS U953 ( .A0(n442), .A1(Data_array_SWR[45]), .B0(n443), .B1(
Data_array_SWR[41]), .Y(n551) );
AOI22X1TS U954 ( .A0(n444), .A1(Data_array_SWR[37]), .B0(n554), .B1(
Data_array_SWR[33]), .Y(n550) );
AOI21X1TS U955 ( .A0(n564), .A1(n559), .B0(n448), .Y(n553) );
OAI21X1TS U956 ( .A0(n562), .A1(n441), .B0(n553), .Y(sftr_odat_SHT2_SWR[18])
);
AOI22X1TS U957 ( .A0(Data_array_SWR[44]), .A1(n442), .B0(Data_array_SWR[40]),
.B1(n443), .Y(n556) );
AOI22X1TS U958 ( .A0(n444), .A1(Data_array_SWR[36]), .B0(Data_array_SWR[32]),
.B1(n554), .Y(n555) );
OAI211X1TS U959 ( .A0(n976), .A1(n557), .B0(n556), .C0(n555), .Y(n563) );
AOI21X1TS U960 ( .A0(n560), .A1(n563), .B0(n452), .Y(n558) );
OAI21X1TS U961 ( .A0(n566), .A1(n451), .B0(n558), .Y(sftr_odat_SHT2_SWR[6])
);
AOI21X1TS U962 ( .A0(n560), .A1(n559), .B0(n452), .Y(n561) );
OAI21X1TS U963 ( .A0(n562), .A1(n451), .B0(n561), .Y(sftr_odat_SHT2_SWR[7])
);
AOI21X1TS U964 ( .A0(n564), .A1(n563), .B0(n448), .Y(n565) );
OAI21X1TS U965 ( .A0(n566), .A1(n441), .B0(n565), .Y(sftr_odat_SHT2_SWR[19])
);
NOR2BX1TS U966 ( .AN(LZD_output_NRM2_EW[3]), .B(ADD_OVRFLW_NRM2), .Y(n567)
);
XOR2X1TS U967 ( .A(n920), .B(n567), .Y(DP_OP_15J181_122_6956_n15) );
NOR2BX1TS U968 ( .AN(LZD_output_NRM2_EW[4]), .B(ADD_OVRFLW_NRM2), .Y(n568)
);
XOR2X1TS U969 ( .A(n920), .B(n568), .Y(DP_OP_15J181_122_6956_n14) );
NOR2X1TS U970 ( .A(DmP_mant_SFG_SWR[8]), .B(n954), .Y(n574) );
AOI22X1TS U971 ( .A0(DMP_SFG[5]), .A1(n948), .B0(n570), .B1(n569), .Y(n576)
);
AOI222X4TS U972 ( .A0(n571), .A1(n916), .B0(n571), .B1(n948), .C0(n916),
.C1(n948), .Y(n578) );
AOI22X1TS U973 ( .A0(n855), .A1(n576), .B0(n578), .B1(n1065), .Y(n573) );
OAI21XLTS U974 ( .A0(n574), .A1(n577), .B0(n573), .Y(n572) );
OAI31X1TS U975 ( .A0(n574), .A1(n573), .A2(n577), .B0(n572), .Y(
Raw_mant_SGF[8]) );
NOR2X1TS U976 ( .A(DmP_mant_SFG_SWR[10]), .B(n955), .Y(n581) );
NAND2X1TS U977 ( .A(DmP_mant_SFG_SWR[9]), .B(n917), .Y(n850) );
OAI22X1TS U978 ( .A0(DmP_mant_SFG_SWR[8]), .A1(n954), .B0(n577), .B1(n576),
.Y(n849) );
AOI22X1TS U979 ( .A0(DMP_SFG[7]), .A1(n949), .B0(n850), .B1(n849), .Y(n586)
);
AOI222X4TS U980 ( .A0(n848), .A1(n917), .B0(n848), .B1(n949), .C0(n917),
.C1(n949), .Y(n588) );
AOI22X1TS U981 ( .A0(n855), .A1(n586), .B0(n588), .B1(n1065), .Y(n580) );
OAI31X1TS U982 ( .A0(n581), .A1(n580), .A2(n587), .B0(n579), .Y(
Raw_mant_SGF[10]) );
AOI221X4TS U983 ( .A0(Raw_mant_NRM_SWR[0]), .A1(n611), .B0(
Raw_mant_NRM_SWR[25]), .B1(n594), .C0(n924), .Y(n906) );
NAND2X1TS U984 ( .A(n596), .B(n584), .Y(n582) );
INVX2TS U985 ( .A(n584), .Y(n595) );
AOI22X1TS U986 ( .A0(n611), .A1(Raw_mant_NRM_SWR[24]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n401), .Y(n635) );
INVX2TS U987 ( .A(n627), .Y(n633) );
AOI22X1TS U988 ( .A0(n611), .A1(Raw_mant_NRM_SWR[25]), .B0(n643), .B1(n633),
.Y(n585) );
NOR2X1TS U989 ( .A(DmP_mant_SFG_SWR[12]), .B(n957), .Y(n591) );
NAND2X1TS U990 ( .A(DmP_mant_SFG_SWR[11]), .B(n918), .Y(n856) );
OAI22X1TS U991 ( .A0(DmP_mant_SFG_SWR[10]), .A1(n955), .B0(n587), .B1(n586),
.Y(n854) );
AOI22X1TS U992 ( .A0(DMP_SFG[9]), .A1(n953), .B0(n856), .B1(n854), .Y(n675)
);
AOI222X4TS U993 ( .A0(n853), .A1(n918), .B0(n853), .B1(n953), .C0(n918),
.C1(n953), .Y(n677) );
AOI22X1TS U994 ( .A0(n407), .A1(n675), .B0(n677), .B1(n1065), .Y(n590) );
CLKAND2X2TS U995 ( .A(DmP_mant_SFG_SWR[12]), .B(n957), .Y(n676) );
OAI21XLTS U996 ( .A0(n591), .A1(n676), .B0(n590), .Y(n589) );
OAI31X1TS U997 ( .A0(n591), .A1(n590), .A2(n676), .B0(n589), .Y(
Raw_mant_SGF[12]) );
AOI22X1TS U998 ( .A0(n400), .A1(Raw_mant_NRM_SWR[22]), .B0(
DmP_mant_SHT1_SW[20]), .B1(n924), .Y(n593) );
AOI222X4TS U999 ( .A0(n912), .A1(DmP_mant_SHT1_SW[22]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n401), .C0(Raw_mant_NRM_SWR[1]), .C1(n1064),
.Y(n903) );
AOI222X4TS U1000 ( .A0(n912), .A1(DmP_mant_SHT1_SW[21]), .B0(
Raw_mant_NRM_SWR[23]), .B1(n401), .C0(Raw_mant_NRM_SWR[2]), .C1(n1064),
.Y(n905) );
NAND2X1TS U1001 ( .A(n596), .B(n595), .Y(n597) );
BUFX4TS U1002 ( .A(n597), .Y(n904) );
OAI22X1TS U1003 ( .A0(n903), .A1(n583), .B0(n905), .B1(n904), .Y(n598) );
AOI21X1TS U1004 ( .A0(n398), .A1(n671), .B0(n598), .Y(n599) );
AOI222X4TS U1005 ( .A0(n912), .A1(DmP_mant_SHT1_SW[9]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n400), .C0(Raw_mant_NRM_SWR[14]), .C1(n1064), .Y(n664) );
AOI22X1TS U1006 ( .A0(n400), .A1(Raw_mant_NRM_SWR[10]), .B0(
DmP_mant_SHT1_SW[8]), .B1(n924), .Y(n600) );
AOI222X4TS U1007 ( .A0(n912), .A1(DmP_mant_SHT1_SW[11]), .B0(n1064), .B1(
Raw_mant_NRM_SWR[12]), .C0(Raw_mant_NRM_SWR[13]), .C1(n400), .Y(n657)
);
AOI222X4TS U1008 ( .A0(n912), .A1(DmP_mant_SHT1_SW[10]), .B0(
Raw_mant_NRM_SWR[12]), .B1(n400), .C0(Raw_mant_NRM_SWR[13]), .C1(n1064), .Y(n662) );
OAI22X1TS U1009 ( .A0(n657), .A1(n592), .B0(n662), .B1(n583), .Y(n601) );
AOI21X1TS U1010 ( .A0(n398), .A1(n666), .B0(n601), .Y(n602) );
AOI222X4TS U1011 ( .A0(n912), .A1(DmP_mant_SHT1_SW[17]), .B0(
Raw_mant_NRM_SWR[19]), .B1(n401), .C0(Raw_mant_NRM_SWR[6]), .C1(n1064),
.Y(n652) );
AOI22X1TS U1012 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n611), .B0(
DmP_mant_SHT1_SW[16]), .B1(n924), .Y(n603) );
AOI222X4TS U1013 ( .A0(n912), .A1(DmP_mant_SHT1_SW[19]), .B0(
Raw_mant_NRM_SWR[21]), .B1(n401), .C0(Raw_mant_NRM_SWR[4]), .C1(n1064),
.Y(n669) );
AOI222X4TS U1014 ( .A0(n912), .A1(DmP_mant_SHT1_SW[18]), .B0(
Raw_mant_NRM_SWR[20]), .B1(n401), .C0(Raw_mant_NRM_SWR[5]), .C1(n1064),
.Y(n674) );
OAI22X1TS U1015 ( .A0(n669), .A1(n592), .B0(n674), .B1(n583), .Y(n604) );
AOI21X1TS U1016 ( .A0(n398), .A1(n654), .B0(n604), .Y(n605) );
AOI222X4TS U1017 ( .A0(n924), .A1(DmP_mant_SHT1_SW[5]), .B0(n611), .B1(
Raw_mant_NRM_SWR[18]), .C0(Raw_mant_NRM_SWR[7]), .C1(n401), .Y(n646)
);
AOI22X1TS U1018 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n611), .B0(
DmP_mant_SHT1_SW[4]), .B1(n924), .Y(n606) );
AOI222X4TS U1019 ( .A0(n924), .A1(DmP_mant_SHT1_SW[7]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n400), .C0(Raw_mant_NRM_SWR[16]), .C1(n1064),
.Y(n663) );
AOI222X4TS U1020 ( .A0(n912), .A1(DmP_mant_SHT1_SW[6]), .B0(
Raw_mant_NRM_SWR[8]), .B1(n400), .C0(Raw_mant_NRM_SWR[17]), .C1(n1064),
.Y(n668) );
OAI22X1TS U1021 ( .A0(n663), .A1(n592), .B0(n668), .B1(n583), .Y(n607) );
AOI21X1TS U1022 ( .A0(n398), .A1(n648), .B0(n607), .Y(n608) );
AOI222X4TS U1023 ( .A0(n912), .A1(DmP_mant_SHT1_SW[13]), .B0(n611), .B1(
Raw_mant_NRM_SWR[10]), .C0(Raw_mant_NRM_SWR[15]), .C1(n400), .Y(n658)
);
AOI22X1TS U1024 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n611), .B0(
DmP_mant_SHT1_SW[12]), .B1(n924), .Y(n609) );
AOI222X4TS U1025 ( .A0(n912), .A1(DmP_mant_SHT1_SW[15]), .B0(n611), .B1(
Raw_mant_NRM_SWR[8]), .C0(Raw_mant_NRM_SWR[17]), .C1(n400), .Y(n651)
);
AOI222X4TS U1026 ( .A0(n912), .A1(DmP_mant_SHT1_SW[14]), .B0(n611), .B1(
Raw_mant_NRM_SWR[9]), .C0(Raw_mant_NRM_SWR[16]), .C1(n400), .Y(n656)
);
OAI22X1TS U1027 ( .A0(n651), .A1(n592), .B0(n656), .B1(n583), .Y(n612) );
AOI21X1TS U1028 ( .A0(n398), .A1(n660), .B0(n612), .Y(n613) );
INVX2TS U1029 ( .A(n904), .Y(n629) );
AOI222X4TS U1030 ( .A0(n924), .A1(DmP_mant_SHT1_SW[3]), .B0(n1064), .B1(
Raw_mant_NRM_SWR[20]), .C0(Raw_mant_NRM_SWR[5]), .C1(n401), .Y(n645)
);
AOI222X4TS U1031 ( .A0(n924), .A1(DmP_mant_SHT1_SW[2]), .B0(n1064), .B1(
Raw_mant_NRM_SWR[21]), .C0(Raw_mant_NRM_SWR[4]), .C1(n401), .Y(n650)
);
OAI22X1TS U1032 ( .A0(n645), .A1(n592), .B0(n650), .B1(n583), .Y(n615) );
AOI21X1TS U1033 ( .A0(n629), .A1(n633), .B0(n615), .Y(n616) );
OAI22X1TS U1034 ( .A0(n668), .A1(n592), .B0(n646), .B1(n583), .Y(n617) );
AOI21X1TS U1035 ( .A0(n629), .A1(n648), .B0(n617), .Y(n618) );
OAI22X1TS U1036 ( .A0(n656), .A1(n592), .B0(n658), .B1(n583), .Y(n619) );
AOI21X1TS U1037 ( .A0(n629), .A1(n660), .B0(n619), .Y(n620) );
OAI22X1TS U1038 ( .A0(n662), .A1(n592), .B0(n664), .B1(n583), .Y(n621) );
AOI21X1TS U1039 ( .A0(n629), .A1(n666), .B0(n621), .Y(n622) );
OAI22X1TS U1040 ( .A0(n674), .A1(n592), .B0(n652), .B1(n583), .Y(n623) );
AOI21X1TS U1041 ( .A0(n629), .A1(n654), .B0(n623), .Y(n624) );
OAI22X1TS U1042 ( .A0(n645), .A1(n583), .B0(n650), .B1(n904), .Y(n625) );
AOI21X1TS U1043 ( .A0(n643), .A1(n648), .B0(n625), .Y(n626) );
OAI22X1TS U1044 ( .A0(n903), .A1(n592), .B0(n905), .B1(n583), .Y(n628) );
AOI21X1TS U1045 ( .A0(n629), .A1(n671), .B0(n628), .Y(n630) );
OAI22X1TS U1046 ( .A0(n650), .A1(n592), .B0(n631), .B1(n904), .Y(n632) );
AOI21X1TS U1047 ( .A0(n672), .A1(n633), .B0(n632), .Y(n634) );
OAI22X1TS U1048 ( .A0(n657), .A1(n583), .B0(n662), .B1(n904), .Y(n636) );
AOI21X1TS U1049 ( .A0(n643), .A1(n660), .B0(n636), .Y(n637) );
OAI22X1TS U1050 ( .A0(n669), .A1(n583), .B0(n674), .B1(n904), .Y(n638) );
AOI21X1TS U1051 ( .A0(n643), .A1(n671), .B0(n638), .Y(n639) );
OAI22X1TS U1052 ( .A0(n651), .A1(n583), .B0(n656), .B1(n904), .Y(n640) );
AOI21X1TS U1053 ( .A0(n643), .A1(n654), .B0(n640), .Y(n641) );
OAI22X1TS U1054 ( .A0(n663), .A1(n583), .B0(n668), .B1(n904), .Y(n642) );
AOI21X1TS U1055 ( .A0(n643), .A1(n666), .B0(n642), .Y(n644) );
OAI22X1TS U1056 ( .A0(n646), .A1(n592), .B0(n645), .B1(n904), .Y(n647) );
AOI21X1TS U1057 ( .A0(n672), .A1(n648), .B0(n647), .Y(n649) );
OAI22X1TS U1058 ( .A0(n652), .A1(n592), .B0(n651), .B1(n904), .Y(n653) );
AOI21X1TS U1059 ( .A0(n672), .A1(n654), .B0(n653), .Y(n655) );
OAI22X1TS U1060 ( .A0(n658), .A1(n592), .B0(n657), .B1(n904), .Y(n659) );
AOI21X1TS U1061 ( .A0(n672), .A1(n660), .B0(n659), .Y(n661) );
OAI22X1TS U1062 ( .A0(n664), .A1(n592), .B0(n663), .B1(n904), .Y(n665) );
AOI21X1TS U1063 ( .A0(n672), .A1(n666), .B0(n665), .Y(n667) );
OAI22X1TS U1064 ( .A0(n905), .A1(n592), .B0(n669), .B1(n904), .Y(n670) );
AOI21X1TS U1065 ( .A0(n672), .A1(n671), .B0(n670), .Y(n673) );
NOR2X1TS U1066 ( .A(DmP_mant_SFG_SWR[14]), .B(n959), .Y(n680) );
NAND2X1TS U1067 ( .A(DmP_mant_SFG_SWR[13]), .B(n919), .Y(n861) );
OAI22X1TS U1068 ( .A0(DmP_mant_SFG_SWR[12]), .A1(n957), .B0(n676), .B1(n675),
.Y(n860) );
AOI22X1TS U1069 ( .A0(DMP_SFG[11]), .A1(n958), .B0(n861), .B1(n860), .Y(n681) );
AOI222X4TS U1070 ( .A0(n859), .A1(n919), .B0(n859), .B1(n958), .C0(n919),
.C1(n958), .Y(n683) );
AOI22X1TS U1071 ( .A0(n407), .A1(n681), .B0(n683), .B1(n1065), .Y(n679) );
CLKAND2X2TS U1072 ( .A(DmP_mant_SFG_SWR[14]), .B(n959), .Y(n682) );
OAI21XLTS U1073 ( .A0(n680), .A1(n682), .B0(n679), .Y(n678) );
OAI31X1TS U1074 ( .A0(n680), .A1(n679), .A2(n682), .B0(n678), .Y(
Raw_mant_SGF[14]) );
NOR2X1TS U1075 ( .A(DmP_mant_SFG_SWR[16]), .B(n962), .Y(n686) );
NAND2X1TS U1076 ( .A(DmP_mant_SFG_SWR[15]), .B(n921), .Y(n866) );
OAI22X1TS U1077 ( .A0(DmP_mant_SFG_SWR[14]), .A1(n959), .B0(n682), .B1(n681),
.Y(n865) );
AOI22X1TS U1078 ( .A0(DMP_SFG[13]), .A1(n963), .B0(n866), .B1(n865), .Y(n687) );
AOI222X4TS U1079 ( .A0(n864), .A1(n921), .B0(n864), .B1(n963), .C0(n921),
.C1(n963), .Y(n689) );
AOI22X1TS U1080 ( .A0(n407), .A1(n687), .B0(n689), .B1(n1065), .Y(n685) );
CLKAND2X2TS U1081 ( .A(DmP_mant_SFG_SWR[16]), .B(n962), .Y(n688) );
OAI31X1TS U1082 ( .A0(n686), .A1(n685), .A2(n688), .B0(n684), .Y(
Raw_mant_SGF[16]) );
NOR2X1TS U1083 ( .A(DmP_mant_SFG_SWR[18]), .B(n971), .Y(n692) );
NAND2X1TS U1084 ( .A(DmP_mant_SFG_SWR[17]), .B(n922), .Y(n871) );
OAI22X1TS U1085 ( .A0(DmP_mant_SFG_SWR[16]), .A1(n962), .B0(n688), .B1(n687),
.Y(n870) );
AOI22X1TS U1086 ( .A0(DMP_SFG[15]), .A1(n967), .B0(n871), .B1(n870), .Y(n693) );
AOI222X4TS U1087 ( .A0(n869), .A1(n922), .B0(n869), .B1(n967), .C0(n922),
.C1(n967), .Y(n695) );
AOI22X1TS U1088 ( .A0(n407), .A1(n693), .B0(n695), .B1(n1065), .Y(n691) );
CLKAND2X2TS U1089 ( .A(DmP_mant_SFG_SWR[18]), .B(n971), .Y(n694) );
OAI31X1TS U1090 ( .A0(n692), .A1(n691), .A2(n694), .B0(n690), .Y(
Raw_mant_SGF[18]) );
NOR2X1TS U1091 ( .A(DmP_mant_SFG_SWR[20]), .B(n974), .Y(n698) );
NAND2X1TS U1092 ( .A(DmP_mant_SFG_SWR[19]), .B(n925), .Y(n876) );
OAI22X1TS U1093 ( .A0(DmP_mant_SFG_SWR[18]), .A1(n971), .B0(n694), .B1(n693),
.Y(n875) );
AOI22X1TS U1094 ( .A0(DMP_SFG[17]), .A1(n972), .B0(n876), .B1(n875), .Y(n699) );
AOI222X4TS U1095 ( .A0(n874), .A1(n925), .B0(n874), .B1(n972), .C0(n925),
.C1(n972), .Y(n701) );
AOI22X1TS U1096 ( .A0(n407), .A1(n699), .B0(n701), .B1(n1065), .Y(n697) );
CLKAND2X2TS U1097 ( .A(DmP_mant_SFG_SWR[20]), .B(n974), .Y(n700) );
OAI31X1TS U1098 ( .A0(n698), .A1(n697), .A2(n700), .B0(n696), .Y(
Raw_mant_SGF[20]) );
NOR2X1TS U1099 ( .A(DmP_mant_SFG_SWR[22]), .B(n995), .Y(n704) );
NAND2X1TS U1100 ( .A(DmP_mant_SFG_SWR[21]), .B(n926), .Y(n881) );
OAI22X1TS U1101 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n974), .B0(n700), .B1(n699),
.Y(n880) );
AOI22X1TS U1102 ( .A0(DMP_SFG[19]), .A1(n975), .B0(n881), .B1(n880), .Y(n731) );
AOI222X4TS U1103 ( .A0(n879), .A1(n926), .B0(n879), .B1(n975), .C0(n926),
.C1(n975), .Y(n733) );
AOI22X1TS U1104 ( .A0(n407), .A1(n731), .B0(n733), .B1(n890), .Y(n703) );
CLKAND2X2TS U1105 ( .A(DmP_mant_SFG_SWR[22]), .B(n995), .Y(n732) );
OAI31X1TS U1106 ( .A0(n704), .A1(n703), .A2(n732), .B0(n702), .Y(
Raw_mant_SGF[22]) );
INVX2TS U1107 ( .A(n705), .Y(n707) );
NOR2XLTS U1108 ( .A(Raw_mant_NRM_SWR[13]), .B(Raw_mant_NRM_SWR[11]), .Y(n706) );
OAI22X1TS U1109 ( .A0(n708), .A1(n707), .B0(n706), .B1(n720), .Y(n709) );
AOI21X1TS U1110 ( .A0(n710), .A1(Raw_mant_NRM_SWR[3]), .B0(n709), .Y(n711)
);
OAI211X1TS U1111 ( .A0(n713), .A1(n1003), .B0(n712), .C0(n711), .Y(
LZD_raw_out_EWR[2]) );
INVX2TS U1112 ( .A(n714), .Y(n716) );
NOR3X1TS U1113 ( .A(Raw_mant_NRM_SWR[2]), .B(n730), .C(n961), .Y(n726) );
OAI211X1TS U1114 ( .A0(n721), .A1(n720), .B0(n719), .C0(n718), .Y(
LZD_raw_out_EWR[3]) );
OAI31X1TS U1115 ( .A0(n724), .A1(Raw_mant_NRM_SWR[10]), .A2(n723), .B0(n722),
.Y(n725) );
AOI211X1TS U1116 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n727), .B0(n726), .C0(n725),
.Y(n728) );
OAI211X1TS U1117 ( .A0(n1030), .A1(n730), .B0(n729), .C0(n728), .Y(
LZD_raw_out_EWR[4]) );
NOR2X1TS U1118 ( .A(DmP_mant_SFG_SWR[24]), .B(n1001), .Y(n889) );
NAND2X1TS U1119 ( .A(DmP_mant_SFG_SWR[23]), .B(n939), .Y(n886) );
OAI22X1TS U1120 ( .A0(DmP_mant_SFG_SWR[22]), .A1(n995), .B0(n732), .B1(n731),
.Y(n885) );
AOI22X1TS U1121 ( .A0(DMP_SFG[21]), .A1(n996), .B0(n886), .B1(n885), .Y(n892) );
AOI21X1TS U1122 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n1001), .B0(n892), .Y(n734)
);
AOI222X4TS U1123 ( .A0(n884), .A1(n939), .B0(n884), .B1(n996), .C0(n939),
.C1(n996), .Y(n891) );
OAI32X1TS U1124 ( .A0(n890), .A1(n889), .A2(n734), .B0(n775), .B1(n855), .Y(
n735) );
NOR2BX1TS U1125 ( .AN(LZD_output_NRM2_EW[2]), .B(ADD_OVRFLW_NRM2), .Y(n736)
);
XOR2X1TS U1126 ( .A(n920), .B(n736), .Y(DP_OP_15J181_122_6956_n16) );
NOR2BX1TS U1127 ( .AN(LZD_output_NRM2_EW[1]), .B(ADD_OVRFLW_NRM2), .Y(n737)
);
XOR2X1TS U1128 ( .A(n920), .B(n737), .Y(DP_OP_15J181_122_6956_n17) );
OR2X1TS U1129 ( .A(ADD_OVRFLW_NRM2), .B(LZD_output_NRM2_EW[0]), .Y(n738) );
XOR2X1TS U1130 ( .A(n920), .B(n738), .Y(DP_OP_15J181_122_6956_n18) );
NOR2BX1TS U1131 ( .AN(exp_rslt_NRM2_EW1[7]), .B(
array_comparators_GTComparator_N0), .Y(formatted_number_W[30]) );
AOI2BB1XLTS U1132 ( .A0N(array_comparators_LTComparator_N0), .A1N(
SIGN_FLAG_SHT1SHT2), .B0(array_comparators_GTComparator_N0), .Y(
formatted_number_W[31]) );
XOR2XLTS U1133 ( .A(DMP_EXP_EWSW[27]), .B(DmP_EXP_EWSW[27]), .Y(n739) );
XOR2XLTS U1134 ( .A(intadd_429_n1), .B(n739), .Y(Shift_amount_EXP_EW[4]) );
AOI22X1TS U1135 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n908), .B1(n913), .Y(n1067)
);
XNOR2X1TS U1136 ( .A(add_subt), .B(Data_Y[31]), .Y(n1033) );
XNOR2X1TS U1137 ( .A(intDX_EWSW[31]), .B(n1066), .Y(OP_FLAG_INIT) );
AOI22X1TS U1138 ( .A0(intDX_EWSW[23]), .A1(intDY_EWSW[23]), .B0(n942), .B1(
n994), .Y(n746) );
AOI22X1TS U1139 ( .A0(n933), .A1(intDY_EWSW[15]), .B0(n987), .B1(
intDY_EWSW[13]), .Y(n740) );
OAI221XLTS U1140 ( .A0(n933), .A1(intDY_EWSW[15]), .B0(n987), .B1(
intDY_EWSW[13]), .C0(n740), .Y(n745) );
AOI22X1TS U1141 ( .A0(n979), .A1(intDY_EWSW[10]), .B0(n934), .B1(
intDY_EWSW[2]), .Y(n741) );
AOI22X1TS U1142 ( .A0(n397), .A1(intDY_EWSW[9]), .B0(n982), .B1(
intDY_EWSW[11]), .Y(n742) );
OAI221XLTS U1143 ( .A0(n397), .A1(intDY_EWSW[9]), .B0(n982), .B1(
intDY_EWSW[11]), .C0(n742), .Y(n743) );
NOR4X1TS U1144 ( .A(n746), .B(n745), .C(n744), .D(n743), .Y(n774) );
AOI22X1TS U1145 ( .A0(n993), .A1(intDY_EWSW[7]), .B0(n984), .B1(
intDY_EWSW[14]), .Y(n747) );
AOI22X1TS U1146 ( .A0(n992), .A1(intDY_EWSW[5]), .B0(n935), .B1(
intDY_EWSW[4]), .Y(n748) );
OAI221XLTS U1147 ( .A0(n992), .A1(intDY_EWSW[5]), .B0(n935), .B1(
intDY_EWSW[4]), .C0(n748), .Y(n753) );
AOI22X1TS U1148 ( .A0(n932), .A1(intDY_EWSW[3]), .B0(n986), .B1(
intDY_EWSW[26]), .Y(n749) );
AOI22X1TS U1149 ( .A0(n978), .A1(intDY_EWSW[1]), .B0(n938), .B1(
intDY_EWSW[0]), .Y(n750) );
OAI221XLTS U1150 ( .A0(n978), .A1(intDY_EWSW[1]), .B0(n938), .B1(
intDY_EWSW[0]), .C0(n750), .Y(n751) );
NOR4X1TS U1151 ( .A(n754), .B(n753), .C(n752), .D(n751), .Y(n773) );
AOI22X1TS U1152 ( .A0(n900), .A1(intDY_EWSW[28]), .B0(n936), .B1(
intDY_EWSW[6]), .Y(n755) );
AOI22X1TS U1153 ( .A0(n928), .A1(intDY_EWSW[18]), .B0(n989), .B1(
intDY_EWSW[29]), .Y(n756) );
OAI221XLTS U1154 ( .A0(n928), .A1(intDY_EWSW[18]), .B0(n989), .B1(
intDY_EWSW[29]), .C0(n756), .Y(n761) );
AOI22X1TS U1155 ( .A0(n931), .A1(intDY_EWSW[27]), .B0(n985), .B1(
intDY_EWSW[19]), .Y(n757) );
AOI22X1TS U1156 ( .A0(n981), .A1(intDY_EWSW[25]), .B0(n937), .B1(
intDY_EWSW[24]), .Y(n758) );
OAI221XLTS U1157 ( .A0(n981), .A1(intDY_EWSW[25]), .B0(n937), .B1(
intDY_EWSW[24]), .C0(n758), .Y(n759) );
NOR4X1TS U1158 ( .A(n762), .B(n761), .C(n760), .D(n759), .Y(n772) );
AOI22X1TS U1159 ( .A0(n929), .A1(intDY_EWSW[20]), .B0(n990), .B1(
intDY_EWSW[30]), .Y(n763) );
AOI22X1TS U1160 ( .A0(n396), .A1(intDY_EWSW[8]), .B0(n988), .B1(
intDY_EWSW[21]), .Y(n764) );
OAI221XLTS U1161 ( .A0(n396), .A1(intDY_EWSW[8]), .B0(n988), .B1(
intDY_EWSW[21]), .C0(n764), .Y(n769) );
AOI22X1TS U1162 ( .A0(n980), .A1(intDY_EWSW[17]), .B0(n991), .B1(
intDY_EWSW[16]), .Y(n765) );
AOI22X1TS U1163 ( .A0(n930), .A1(intDY_EWSW[22]), .B0(n983), .B1(
intDY_EWSW[12]), .Y(n766) );
OAI221XLTS U1164 ( .A0(n930), .A1(intDY_EWSW[22]), .B0(n983), .B1(
intDY_EWSW[12]), .C0(n766), .Y(n767) );
NOR4X1TS U1165 ( .A(n770), .B(n769), .C(n768), .D(n767), .Y(n771) );
NAND4XLTS U1166 ( .A(n774), .B(n773), .C(n772), .D(n771), .Y(n841) );
NOR2BX1TS U1167 ( .AN(OP_FLAG_INIT), .B(n841), .Y(ZERO_FLAG_INIT) );
NOR2BX1TS U1168 ( .AN(Shift_reg_FLAGS_7[3]), .B(Shift_reg_FLAGS_7[0]), .Y(
n_21_net_) );
AOI21X1TS U1169 ( .A0(n775), .A1(n405), .B0(n855), .Y(ADD_OVRFLW_SGF) );
NOR2X1TS U1170 ( .A(n1023), .B(intDX_EWSW[25]), .Y(n835) );
NOR2XLTS U1171 ( .A(n835), .B(intDY_EWSW[24]), .Y(n776) );
AOI22X1TS U1172 ( .A0(intDX_EWSW[25]), .A1(n1023), .B0(intDX_EWSW[24]), .B1(
n776), .Y(n780) );
NAND2BXLTS U1173 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n777) );
OAI21X1TS U1174 ( .A0(intDX_EWSW[26]), .A1(n1028), .B0(n777), .Y(n836) );
NAND3XLTS U1175 ( .A(n1028), .B(n777), .C(intDX_EWSW[26]), .Y(n779) );
NAND2BXLTS U1176 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n778) );
OAI211XLTS U1177 ( .A0(n780), .A1(n836), .B0(n779), .C0(n778), .Y(n785) );
NOR2X1TS U1178 ( .A(n927), .B(intDX_EWSW[30]), .Y(n783) );
NOR2X1TS U1179 ( .A(n973), .B(intDX_EWSW[29]), .Y(n781) );
AOI211X1TS U1180 ( .A0(intDY_EWSW[28]), .A1(n900), .B0(n783), .C0(n781), .Y(
n834) );
AOI2BB2X1TS U1181 ( .B0(n785), .B1(n834), .A0N(n784), .A1N(n783), .Y(n840)
);
NOR2X1TS U1182 ( .A(n1021), .B(intDX_EWSW[17]), .Y(n821) );
NOR2X1TS U1183 ( .A(n1024), .B(intDX_EWSW[11]), .Y(n800) );
AOI21X1TS U1184 ( .A0(intDY_EWSW[10]), .A1(n979), .B0(n800), .Y(n805) );
OAI211XLTS U1185 ( .A0(intDX_EWSW[8]), .A1(n1020), .B0(n802), .C0(n805), .Y(
n816) );
OAI2BB1X1TS U1186 ( .A0N(n992), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]), .Y(
n786) );
OAI22X1TS U1187 ( .A0(intDY_EWSW[4]), .A1(n786), .B0(n992), .B1(
intDY_EWSW[5]), .Y(n797) );
OAI2BB1X1TS U1188 ( .A0N(n993), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]), .Y(
n787) );
OAI22X1TS U1189 ( .A0(intDY_EWSW[6]), .A1(n787), .B0(n993), .B1(
intDY_EWSW[7]), .Y(n796) );
OAI2BB2XLTS U1190 ( .B0(intDY_EWSW[0]), .B1(n788), .A0N(intDX_EWSW[1]),
.A1N(n1025), .Y(n790) );
NAND2BXLTS U1191 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n789) );
OAI211XLTS U1192 ( .A0(n1026), .A1(intDX_EWSW[3]), .B0(n790), .C0(n789), .Y(
n793) );
OAI21XLTS U1193 ( .A0(intDX_EWSW[3]), .A1(n1026), .B0(intDX_EWSW[2]), .Y(
n791) );
AOI2BB2XLTS U1194 ( .B0(intDX_EWSW[3]), .B1(n1026), .A0N(intDY_EWSW[2]),
.A1N(n791), .Y(n792) );
AOI222X1TS U1195 ( .A0(intDY_EWSW[4]), .A1(n935), .B0(n793), .B1(n792), .C0(
intDY_EWSW[5]), .C1(n992), .Y(n795) );
AOI22X1TS U1196 ( .A0(intDY_EWSW[7]), .A1(n993), .B0(intDY_EWSW[6]), .B1(
n936), .Y(n794) );
OAI32X1TS U1197 ( .A0(n797), .A1(n796), .A2(n795), .B0(n794), .B1(n796), .Y(
n815) );
OA22X1TS U1198 ( .A0(n945), .A1(intDX_EWSW[14]), .B0(n1027), .B1(
intDX_EWSW[15]), .Y(n812) );
NAND2BXLTS U1199 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n798) );
OAI21XLTS U1200 ( .A0(intDX_EWSW[13]), .A1(n1012), .B0(intDX_EWSW[12]), .Y(
n799) );
OAI2BB2XLTS U1201 ( .B0(intDY_EWSW[12]), .B1(n799), .A0N(intDX_EWSW[13]),
.A1N(n1012), .Y(n811) );
NOR2XLTS U1202 ( .A(n800), .B(intDY_EWSW[10]), .Y(n801) );
AOI22X1TS U1203 ( .A0(intDX_EWSW[11]), .A1(n1024), .B0(intDX_EWSW[10]), .B1(
n801), .Y(n807) );
NAND2BXLTS U1204 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n804) );
NAND3XLTS U1205 ( .A(n1020), .B(n802), .C(intDX_EWSW[8]), .Y(n803) );
AOI21X1TS U1206 ( .A0(n804), .A1(n803), .B0(n814), .Y(n806) );
OAI2BB2XLTS U1207 ( .B0(n807), .B1(n814), .A0N(n806), .A1N(n805), .Y(n810)
);
OAI2BB2XLTS U1208 ( .B0(intDY_EWSW[14]), .B1(n808), .A0N(intDX_EWSW[15]),
.A1N(n1027), .Y(n809) );
AOI211X1TS U1209 ( .A0(n812), .A1(n811), .B0(n810), .C0(n809), .Y(n813) );
OAI31X1TS U1210 ( .A0(n816), .A1(n815), .A2(n814), .B0(n813), .Y(n819) );
OA22X1TS U1211 ( .A0(n1016), .A1(intDX_EWSW[22]), .B0(n942), .B1(
intDX_EWSW[23]), .Y(n832) );
NAND2BXLTS U1212 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n817) );
NAND2BXLTS U1213 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n823) );
OAI21X1TS U1214 ( .A0(intDX_EWSW[18]), .A1(n1022), .B0(n823), .Y(n827) );
NAND3BXLTS U1215 ( .AN(n821), .B(n819), .C(n818), .Y(n839) );
OAI2BB2XLTS U1216 ( .B0(intDY_EWSW[20]), .B1(n820), .A0N(intDX_EWSW[21]),
.A1N(n1013), .Y(n831) );
AOI22X1TS U1217 ( .A0(intDX_EWSW[17]), .A1(n1021), .B0(intDX_EWSW[16]), .B1(
n822), .Y(n825) );
AOI32X1TS U1218 ( .A0(n1022), .A1(n823), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n944), .Y(n824) );
OAI32X1TS U1219 ( .A0(n827), .A1(n826), .A2(n825), .B0(n824), .B1(n826), .Y(
n830) );
OAI21XLTS U1220 ( .A0(intDX_EWSW[23]), .A1(n942), .B0(intDX_EWSW[22]), .Y(
n828) );
OAI2BB2XLTS U1221 ( .B0(intDY_EWSW[22]), .B1(n828), .A0N(intDX_EWSW[23]),
.A1N(n942), .Y(n829) );
AOI211X1TS U1222 ( .A0(n832), .A1(n831), .B0(n830), .C0(n829), .Y(n838) );
NAND2BXLTS U1223 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n833) );
NAND4BBX1TS U1224 ( .AN(n836), .BN(n835), .C(n834), .D(n833), .Y(n837) );
AOI21X1TS U1225 ( .A0(n841), .A1(n902), .B0(intDX_EWSW[31]), .Y(n842) );
AOI21X1TS U1226 ( .A0(n1066), .A1(n897), .B0(n842), .Y(SIGN_FLAG_INIT) );
NAND2X1TS U1227 ( .A(N59), .B(n855), .Y(n843) );
XNOR2X1TS U1228 ( .A(n843), .B(N60), .Y(Raw_mant_SGF[1]) );
OAI21XLTS U1229 ( .A0(DMP_SFG[0]), .A1(DmP_mant_SFG_SWR[2]), .B0(n844), .Y(
n847) );
NAND2X1TS U1230 ( .A(n845), .B(n855), .Y(n846) );
XOR2XLTS U1231 ( .A(n847), .B(n846), .Y(Raw_mant_SGF[2]) );
AOI22X1TS U1232 ( .A0(n855), .A1(n849), .B0(n848), .B1(n1065), .Y(n852) );
OAI21XLTS U1233 ( .A0(DmP_mant_SFG_SWR[9]), .A1(n917), .B0(n850), .Y(n851)
);
XOR2XLTS U1234 ( .A(n852), .B(n851), .Y(Raw_mant_SGF[9]) );
AOI22X1TS U1235 ( .A0(n855), .A1(n854), .B0(n853), .B1(n1065), .Y(n858) );
OAI21XLTS U1236 ( .A0(DmP_mant_SFG_SWR[11]), .A1(n918), .B0(n856), .Y(n857)
);
XOR2XLTS U1237 ( .A(n858), .B(n857), .Y(Raw_mant_SGF[11]) );
AOI22X1TS U1238 ( .A0(n407), .A1(n860), .B0(n859), .B1(n1065), .Y(n863) );
OAI21XLTS U1239 ( .A0(DmP_mant_SFG_SWR[13]), .A1(n919), .B0(n861), .Y(n862)
);
XOR2XLTS U1240 ( .A(n863), .B(n862), .Y(Raw_mant_SGF[13]) );
AOI22X1TS U1241 ( .A0(n407), .A1(n865), .B0(n864), .B1(n1065), .Y(n868) );
OAI21XLTS U1242 ( .A0(DmP_mant_SFG_SWR[15]), .A1(n921), .B0(n866), .Y(n867)
);
XOR2XLTS U1243 ( .A(n868), .B(n867), .Y(Raw_mant_SGF[15]) );
AOI22X1TS U1244 ( .A0(n407), .A1(n870), .B0(n869), .B1(n1065), .Y(n873) );
OAI21XLTS U1245 ( .A0(DmP_mant_SFG_SWR[17]), .A1(n922), .B0(n871), .Y(n872)
);
AOI22X1TS U1246 ( .A0(n407), .A1(n875), .B0(n874), .B1(n890), .Y(n878) );
OAI21XLTS U1247 ( .A0(DmP_mant_SFG_SWR[19]), .A1(n925), .B0(n876), .Y(n877)
);
AOI22X1TS U1248 ( .A0(n407), .A1(n880), .B0(n879), .B1(n1065), .Y(n883) );
OAI21XLTS U1249 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n926), .B0(n881), .Y(n882)
);
AOI22X1TS U1250 ( .A0(n407), .A1(n885), .B0(n884), .B1(n1065), .Y(n888) );
OAI21XLTS U1251 ( .A0(DmP_mant_SFG_SWR[23]), .A1(n939), .B0(n886), .Y(n887)
);
AOI21X1TS U1252 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n1001), .B0(n889), .Y(n894)
);
AOI22X1TS U1253 ( .A0(n407), .A1(n892), .B0(n891), .B1(n890), .Y(n893) );
CLKBUFX3TS U1254 ( .A(n895), .Y(n896) );
AOI22X1TS U1255 ( .A0(n896), .A1(n1029), .B0(n938), .B1(n902), .Y(
DmP_INIT_EWSW[0]) );
AOI22X1TS U1256 ( .A0(n896), .A1(n1025), .B0(n978), .B1(n902), .Y(
DmP_INIT_EWSW[1]) );
AOI22X1TS U1257 ( .A0(n896), .A1(n1014), .B0(n934), .B1(n902), .Y(
DmP_INIT_EWSW[2]) );
AOI22X1TS U1258 ( .A0(n896), .A1(n1026), .B0(n932), .B1(n901), .Y(
DmP_INIT_EWSW[3]) );
AOI22X1TS U1259 ( .A0(n896), .A1(n1009), .B0(n935), .B1(n897), .Y(
DmP_INIT_EWSW[4]) );
AOI22X1TS U1260 ( .A0(n896), .A1(n1005), .B0(n992), .B1(n898), .Y(
DmP_INIT_EWSW[5]) );
AOI22X1TS U1261 ( .A0(n896), .A1(n1007), .B0(n936), .B1(n898), .Y(
DmP_INIT_EWSW[6]) );
AOI22X1TS U1262 ( .A0(n896), .A1(n1004), .B0(n993), .B1(n897), .Y(
DmP_INIT_EWSW[7]) );
AOI22X1TS U1263 ( .A0(n896), .A1(n1020), .B0(n396), .B1(n898), .Y(
DmP_INIT_EWSW[8]) );
AOI22X1TS U1264 ( .A0(n896), .A1(n1017), .B0(n397), .B1(n901), .Y(
DmP_INIT_EWSW[9]) );
AOI22X1TS U1265 ( .A0(n895), .A1(n1010), .B0(n979), .B1(n898), .Y(
DmP_INIT_EWSW[10]) );
AOI22X1TS U1266 ( .A0(n895), .A1(n1024), .B0(n982), .B1(n897), .Y(
DmP_INIT_EWSW[11]) );
AOI22X1TS U1267 ( .A0(n895), .A1(n1019), .B0(n983), .B1(n901), .Y(
DmP_INIT_EWSW[12]) );
AOI22X1TS U1268 ( .A0(n895), .A1(n1012), .B0(n987), .B1(n901), .Y(
DmP_INIT_EWSW[13]) );
AOI22X1TS U1269 ( .A0(n895), .A1(n945), .B0(n984), .B1(n897), .Y(
DmP_INIT_EWSW[14]) );
AOI22X1TS U1270 ( .A0(n895), .A1(n1027), .B0(n933), .B1(n897), .Y(
DmP_INIT_EWSW[15]) );
AOI22X1TS U1271 ( .A0(n895), .A1(n1008), .B0(n991), .B1(n898), .Y(
DmP_INIT_EWSW[16]) );
AOI22X1TS U1272 ( .A0(n895), .A1(n1021), .B0(n980), .B1(n898), .Y(
DmP_INIT_EWSW[17]) );
AOI22X1TS U1273 ( .A0(n895), .A1(n1022), .B0(n928), .B1(n897), .Y(
DmP_INIT_EWSW[18]) );
AOI22X1TS U1274 ( .A0(n895), .A1(n944), .B0(n985), .B1(n901), .Y(
DmP_INIT_EWSW[19]) );
BUFX4TS U1275 ( .A(n895), .Y(n899) );
AOI22X1TS U1276 ( .A0(n393), .A1(n1015), .B0(n929), .B1(n901), .Y(
DmP_INIT_EWSW[20]) );
AOI22X1TS U1277 ( .A0(n393), .A1(n1013), .B0(n988), .B1(n898), .Y(
DmP_INIT_EWSW[21]) );
AOI22X1TS U1278 ( .A0(n393), .A1(n1016), .B0(n930), .B1(n901), .Y(
DmP_INIT_EWSW[22]) );
AOI22X1TS U1279 ( .A0(n393), .A1(n942), .B0(n994), .B1(n897), .Y(
DmP_INIT_EWSW[23]) );
AOI22X1TS U1280 ( .A0(n393), .A1(n1011), .B0(n937), .B1(n898), .Y(
DmP_INIT_EWSW[24]) );
AOI22X1TS U1281 ( .A0(n393), .A1(n1023), .B0(n981), .B1(n901), .Y(
DmP_INIT_EWSW[25]) );
AOI22X1TS U1282 ( .A0(n393), .A1(n1028), .B0(n986), .B1(n897), .Y(
DmP_INIT_EWSW[26]) );
AOI22X1TS U1283 ( .A0(n393), .A1(n1018), .B0(n931), .B1(n898), .Y(
DmP_INIT_EWSW[27]) );
AOI22X1TS U1284 ( .A0(n393), .A1(n938), .B0(n1029), .B1(n897), .Y(
DMP_INIT_EWSW[0]) );
AOI22X1TS U1285 ( .A0(n393), .A1(n978), .B0(n1025), .B1(n901), .Y(
DMP_INIT_EWSW[1]) );
AOI22X1TS U1286 ( .A0(n393), .A1(n934), .B0(n1014), .B1(n898), .Y(
DMP_INIT_EWSW[2]) );
AOI22X1TS U1287 ( .A0(n393), .A1(n932), .B0(n1026), .B1(n898), .Y(
DMP_INIT_EWSW[3]) );
AOI22X1TS U1288 ( .A0(n393), .A1(n935), .B0(n1009), .B1(n898), .Y(
DMP_INIT_EWSW[4]) );
AOI22X1TS U1289 ( .A0(n393), .A1(n992), .B0(n1005), .B1(n898), .Y(
DMP_INIT_EWSW[5]) );
AOI22X1TS U1290 ( .A0(n393), .A1(n936), .B0(n1007), .B1(n898), .Y(
DMP_INIT_EWSW[6]) );
AOI22X1TS U1291 ( .A0(n393), .A1(n993), .B0(n1004), .B1(n901), .Y(
DMP_INIT_EWSW[7]) );
AOI22X1TS U1292 ( .A0(n393), .A1(n396), .B0(n1020), .B1(n897), .Y(
DMP_INIT_EWSW[8]) );
AOI22X1TS U1293 ( .A0(n393), .A1(n397), .B0(n1017), .B1(n898), .Y(
DMP_INIT_EWSW[9]) );
AOI22X1TS U1294 ( .A0(n393), .A1(n979), .B0(n1010), .B1(n901), .Y(
DMP_INIT_EWSW[10]) );
AOI22X1TS U1295 ( .A0(n393), .A1(n982), .B0(n1024), .B1(n897), .Y(
DMP_INIT_EWSW[11]) );
AOI22X1TS U1296 ( .A0(n899), .A1(n983), .B0(n1019), .B1(n898), .Y(
DMP_INIT_EWSW[12]) );
AOI22X1TS U1297 ( .A0(n899), .A1(n987), .B0(n1012), .B1(n901), .Y(
DMP_INIT_EWSW[13]) );
AOI22X1TS U1298 ( .A0(n899), .A1(n984), .B0(n945), .B1(n897), .Y(
DMP_INIT_EWSW[14]) );
AOI22X1TS U1299 ( .A0(n899), .A1(n933), .B0(n1027), .B1(n897), .Y(
DMP_INIT_EWSW[15]) );
AOI22X1TS U1300 ( .A0(n899), .A1(n991), .B0(n1008), .B1(n898), .Y(
DMP_INIT_EWSW[16]) );
AOI22X1TS U1301 ( .A0(n899), .A1(n980), .B0(n1021), .B1(n901), .Y(
DMP_INIT_EWSW[17]) );
AOI22X1TS U1302 ( .A0(n899), .A1(n928), .B0(n1022), .B1(n898), .Y(
DMP_INIT_EWSW[18]) );
AOI22X1TS U1303 ( .A0(n899), .A1(n985), .B0(n944), .B1(n901), .Y(
DMP_INIT_EWSW[19]) );
AOI22X1TS U1304 ( .A0(n899), .A1(n929), .B0(n1015), .B1(n898), .Y(
DMP_INIT_EWSW[20]) );
AOI22X1TS U1305 ( .A0(n899), .A1(n988), .B0(n1013), .B1(n901), .Y(
DMP_INIT_EWSW[21]) );
AOI22X1TS U1306 ( .A0(n899), .A1(n930), .B0(n1016), .B1(n901), .Y(
DMP_INIT_EWSW[22]) );
AOI22X1TS U1307 ( .A0(n899), .A1(n994), .B0(n942), .B1(n898), .Y(
DMP_INIT_EWSW[23]) );
AOI22X1TS U1308 ( .A0(n899), .A1(n937), .B0(n1011), .B1(n901), .Y(
DMP_INIT_EWSW[24]) );
AOI22X1TS U1309 ( .A0(n899), .A1(n981), .B0(n1023), .B1(n897), .Y(
DMP_INIT_EWSW[25]) );
AOI22X1TS U1310 ( .A0(n899), .A1(n986), .B0(n1028), .B1(n897), .Y(
DMP_INIT_EWSW[26]) );
AOI22X1TS U1311 ( .A0(n899), .A1(n931), .B0(n1018), .B1(n897), .Y(
DMP_INIT_EWSW[27]) );
OAI2BB2XLTS U1312 ( .B0(n902), .B1(n900), .A0N(n902), .A1N(intDY_EWSW[28]),
.Y(DMP_INIT_EWSW[28]) );
OAI2BB2XLTS U1313 ( .B0(n902), .B1(n989), .A0N(n902), .A1N(intDY_EWSW[29]),
.Y(DMP_INIT_EWSW[29]) );
OAI2BB2XLTS U1314 ( .B0(n902), .B1(n990), .A0N(n902), .A1N(intDY_EWSW[30]),
.Y(DMP_INIT_EWSW[30]) );
OAI22X1TS U1315 ( .A0(n903), .A1(n399), .B0(n906), .B1(n904), .Y(
Data_array_SWR[24]) );
OAI222X1TS U1316 ( .A0(n583), .A1(n906), .B0(n399), .B1(n905), .C0(n904),
.C1(n903), .Y(Data_array_SWR[23]) );
CLKAND2X2TS U1317 ( .A(n402), .B(sftr_odat_SHT2_SWR[6]), .Y(
formatted_number_W[4]) );
CLKAND2X2TS U1318 ( .A(n402), .B(sftr_odat_SHT2_SWR[7]), .Y(
formatted_number_W[5]) );
CLKAND2X2TS U1319 ( .A(n402), .B(sftr_odat_SHT2_SWR[18]), .Y(
formatted_number_W[16]) );
CLKAND2X2TS U1320 ( .A(n402), .B(sftr_odat_SHT2_SWR[19]), .Y(
formatted_number_W[17]) );
INVX2TS U1322 ( .A(n908), .Y(n911) );
AOI22X1TS U1323 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n943), .B0(
beg_OP), .B1(n913), .Y(n910) );
OAI22X1TS U1324 ( .A0(n911), .A1(n910), .B0(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B1(n909), .Y(n389) );
NAND2BXLTS U1325 ( .AN(busy), .B(n912), .Y(n_7_net_) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
|
// hps_sdram.v
// This file was auto-generated from altera_mem_if_hps_emif_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module hps_sdram (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire [0:0] mem_ck, // .mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [3:0] mem_dm, // .mem_dm
output wire [0:0] mem_ras_n, // .mem_ras_n
output wire [0:0] mem_cas_n, // .mem_cas_n
output wire [0:0] mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire [0:0] mem_odt, // .mem_odt
input wire oct_rzqin // oct.rzqin
);
wire pll_afi_clk_clk; // pll:afi_clk -> [c0:afi_clk, p0:afi_clk]
wire pll_afi_half_clk_clk; // pll:afi_half_clk -> [c0:afi_half_clk, p0:afi_half_clk]
wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire p0_afi_reset_reset; // p0:afi_reset_n -> c0:afi_reset_n
wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd
wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig
wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth
wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi
wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl
wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc
wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat
wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr
wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat
wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk
wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n
wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail
wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess
wire [15:0] oct_oct_sharing_parallelterminationcontrol; // oct:parallelterminationcontrol -> p0:parallelterminationcontrol
wire [15:0] oct_oct_sharing_seriesterminationcontrol; // oct:seriesterminationcontrol -> p0:seriesterminationcontrol
wire pll_pll_sharing_pll_write_clk; // pll:pll_write_clk -> p0:pll_write_clk
wire pll_pll_sharing_pll_avl_clk; // pll:pll_avl_clk -> p0:pll_avl_clk
wire pll_pll_sharing_pll_write_clk_pre_phy_clk; // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk
wire pll_pll_sharing_pll_addr_cmd_clk; // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk
wire pll_pll_sharing_pll_config_clk; // pll:pll_config_clk -> p0:pll_config_clk
wire pll_pll_sharing_pll_avl_phy_clk; // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk
wire pll_pll_sharing_afi_phy_clk; // pll:afi_phy_clk -> p0:afi_phy_clk
wire pll_pll_sharing_pll_mem_clk; // pll:pll_mem_clk -> p0:pll_mem_clk
wire pll_pll_sharing_pll_locked; // pll:pll_locked -> p0:pll_locked
wire pll_pll_sharing_pll_mem_phy_clk; // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk
wire p0_dll_clk_clk; // p0:dll_clk -> dll:clk
wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll:dll_pll_locked
wire [6:0] dll_dll_sharing_dll_delayctrl; // dll:dll_delayctrl -> p0:dll_delayctrl
hps_sdram_pll pll (
.global_reset_n (global_reset_n), // global_reset.reset_n
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk) // .pll_avl_phy_clk
);
hps_sdram_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.afi_reset_export_n (), // afi_reset_export.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.avl_clk (), // avl_clk.clk
.avl_reset_n (), // avl_reset.reset_n
.scc_clk (), // scc_clk.clk
.scc_reset_n (), // scc_reset.reset_n
.avl_address (), // avl.address
.avl_write (), // .write
.avl_writedata (), // .writedata
.avl_read (), // .read
.avl_readdata (), // .readdata
.avl_waitrequest (), // .waitrequest
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.scc_data (), // scc.scc_data
.scc_dqs_ena (), // .scc_dqs_ena
.scc_dqs_io_ena (), // .scc_dqs_io_ena
.scc_dq_ena (), // .scc_dq_ena
.scc_dm_ena (), // .scc_dm_ena
.capture_strobe_tracking (), // .capture_strobe_tracking
.scc_upd (), // .scc_upd
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk), // .pll_avl_phy_clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl), // .dll_delayctrl
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.csr_soft_reset_req (1'b0), // (terminated)
.io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intbadout (12'b000000000000), // (terminated)
.io_intcasndout (4'b0000), // (terminated)
.io_intckdout (4'b0000), // (terminated)
.io_intckedout (8'b00000000), // (terminated)
.io_intckndout (4'b0000), // (terminated)
.io_intcsndout (8'b00000000), // (terminated)
.io_intdmdout (20'b00000000000000000000), // (terminated)
.io_intdqdin (), // (terminated)
.io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqsbdout (20'b00000000000000000000), // (terminated)
.io_intdqsboe (10'b0000000000), // (terminated)
.io_intdqsdout (20'b00000000000000000000), // (terminated)
.io_intdqslogicdqsena (10'b0000000000), // (terminated)
.io_intdqslogicfiforeset (5'b00000), // (terminated)
.io_intdqslogicincrdataen (10'b0000000000), // (terminated)
.io_intdqslogicincwrptr (10'b0000000000), // (terminated)
.io_intdqslogicoct (10'b0000000000), // (terminated)
.io_intdqslogicrdatavalid (), // (terminated)
.io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated)
.io_intdqsoe (10'b0000000000), // (terminated)
.io_intodtdout (8'b00000000), // (terminated)
.io_intrasndout (4'b0000), // (terminated)
.io_intresetndout (4'b0000), // (terminated)
.io_intwendout (4'b0000), // (terminated)
.io_intafirlat (), // (terminated)
.io_intafiwlat () // (terminated)
);
altera_mem_if_hhp_qseq_synth_top #(
.MEM_IF_DM_WIDTH (4),
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_DQ_WIDTH (32)
) seq (
);
altera_mem_if_hard_memory_controller_top_cyclonev #(
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_CLK_PAIR_COUNT (1),
.CSR_ADDR_WIDTH (10),
.CSR_DATA_WIDTH (8),
.CSR_BE_WIDTH (1),
.AVL_ADDR_WIDTH (27),
.AVL_DATA_WIDTH (64),
.AVL_SIZE_WIDTH (3),
.AVL_DATA_WIDTH_PORT_0 (1),
.AVL_ADDR_WIDTH_PORT_0 (1),
.AVL_NUM_SYMBOLS_PORT_0 (1),
.LSB_WFIFO_PORT_0 (5),
.MSB_WFIFO_PORT_0 (5),
.LSB_RFIFO_PORT_0 (5),
.MSB_RFIFO_PORT_0 (5),
.AVL_DATA_WIDTH_PORT_1 (1),
.AVL_ADDR_WIDTH_PORT_1 (1),
.AVL_NUM_SYMBOLS_PORT_1 (1),
.LSB_WFIFO_PORT_1 (5),
.MSB_WFIFO_PORT_1 (5),
.LSB_RFIFO_PORT_1 (5),
.MSB_RFIFO_PORT_1 (5),
.AVL_DATA_WIDTH_PORT_2 (1),
.AVL_ADDR_WIDTH_PORT_2 (1),
.AVL_NUM_SYMBOLS_PORT_2 (1),
.LSB_WFIFO_PORT_2 (5),
.MSB_WFIFO_PORT_2 (5),
.LSB_RFIFO_PORT_2 (5),
.MSB_RFIFO_PORT_2 (5),
.AVL_DATA_WIDTH_PORT_3 (1),
.AVL_ADDR_WIDTH_PORT_3 (1),
.AVL_NUM_SYMBOLS_PORT_3 (1),
.LSB_WFIFO_PORT_3 (5),
.MSB_WFIFO_PORT_3 (5),
.LSB_RFIFO_PORT_3 (5),
.MSB_RFIFO_PORT_3 (5),
.AVL_DATA_WIDTH_PORT_4 (1),
.AVL_ADDR_WIDTH_PORT_4 (1),
.AVL_NUM_SYMBOLS_PORT_4 (1),
.LSB_WFIFO_PORT_4 (5),
.MSB_WFIFO_PORT_4 (5),
.LSB_RFIFO_PORT_4 (5),
.MSB_RFIFO_PORT_4 (5),
.AVL_DATA_WIDTH_PORT_5 (1),
.AVL_ADDR_WIDTH_PORT_5 (1),
.AVL_NUM_SYMBOLS_PORT_5 (1),
.LSB_WFIFO_PORT_5 (5),
.MSB_WFIFO_PORT_5 (5),
.LSB_RFIFO_PORT_5 (5),
.MSB_RFIFO_PORT_5 (5),
.ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"),
.ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"),
.ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"),
.ENUM_CAL_REQ ("DISABLED"),
.ENUM_CFG_BURST_LENGTH ("BL_8"),
.ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_32"),
.ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"),
.ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"),
.ENUM_CFG_TYPE ("DDR3"),
.ENUM_CLOCK_OFF_0 ("DISABLED"),
.ENUM_CLOCK_OFF_1 ("DISABLED"),
.ENUM_CLOCK_OFF_2 ("DISABLED"),
.ENUM_CLOCK_OFF_3 ("DISABLED"),
.ENUM_CLOCK_OFF_4 ("DISABLED"),
.ENUM_CLOCK_OFF_5 ("DISABLED"),
.ENUM_CLR_INTR ("NO_CLR_INTR"),
.ENUM_CMD_PORT_IN_USE_0 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_1 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_2 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_3 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_4 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_5 ("FALSE"),
.ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT0_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT0_TYPE ("DISABLE"),
.ENUM_CPORT0_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT1_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_TYPE ("DISABLE"),
.ENUM_CPORT1_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT2_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_TYPE ("DISABLE"),
.ENUM_CPORT2_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT3_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_TYPE ("DISABLE"),
.ENUM_CPORT3_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT4_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_TYPE ("DISABLE"),
.ENUM_CPORT4_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT5_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_TYPE ("DISABLE"),
.ENUM_CPORT5_WFIFO_MAP ("FIFO_0"),
.ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"),
.ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"),
.ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"),
.ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"),
.ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"),
.ENUM_CTRL_WIDTH ("DATA_WIDTH_64_BIT"),
.ENUM_DELAY_BONDING ("BONDING_LATENCY_0"),
.ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"),
.ENUM_DISABLE_MERGING ("MERGING_ENABLED"),
.ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"),
.ENUM_ENABLE_ATPG ("DISABLED"),
.ENUM_ENABLE_BONDING_0 ("DISABLED"),
.ENUM_ENABLE_BONDING_1 ("DISABLED"),
.ENUM_ENABLE_BONDING_2 ("DISABLED"),
.ENUM_ENABLE_BONDING_3 ("DISABLED"),
.ENUM_ENABLE_BONDING_4 ("DISABLED"),
.ENUM_ENABLE_BONDING_5 ("DISABLED"),
.ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"),
.ENUM_ENABLE_DQS_TRACKING ("ENABLED"),
.ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"),
.ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"),
.ENUM_ENABLE_INTR ("DISABLED"),
.ENUM_ENABLE_NO_DM ("DISABLED"),
.ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"),
.ENUM_GANGED_ARF ("DISABLED"),
.ENUM_GEN_DBE ("GEN_DBE_DISABLED"),
.ENUM_GEN_SBE ("GEN_SBE_DISABLED"),
.ENUM_INC_SYNC ("FIFO_SET_2"),
.ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"),
.ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"),
.ENUM_MASK_DBE_INTR ("DISABLED"),
.ENUM_MASK_SBE_INTR ("DISABLED"),
.ENUM_MEM_IF_AL ("AL_0"),
.ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"),
.ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"),
.ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"),
.ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"),
.ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"),
.ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"),
.ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_4"),
.ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_32"),
.ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"),
.ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_15"),
.ENUM_MEM_IF_SPEEDBIN ("DDR3_1600_8_8_8"),
.ENUM_MEM_IF_TCCD ("TCCD_4"),
.ENUM_MEM_IF_TCL ("TCL_11"),
.ENUM_MEM_IF_TCWL ("TCWL_8"),
.ENUM_MEM_IF_TFAW ("TFAW_12"),
.ENUM_MEM_IF_TMRD ("TMRD_4"),
.ENUM_MEM_IF_TRAS ("TRAS_14"),
.ENUM_MEM_IF_TRC ("TRC_20"),
.ENUM_MEM_IF_TRCD ("TRCD_6"),
.ENUM_MEM_IF_TRP ("TRP_6"),
.ENUM_MEM_IF_TRRD ("TRRD_3"),
.ENUM_MEM_IF_TRTP ("TRTP_3"),
.ENUM_MEM_IF_TWR ("TWR_6"),
.ENUM_MEM_IF_TWTR ("TWTR_4"),
.ENUM_MMR_CFG_MEM_BL ("MP_BL_8"),
.ENUM_OUTPUT_REGD ("DISABLED"),
.ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"),
.ENUM_PORT0_WIDTH ("PORT_32_BIT"),
.ENUM_PORT1_WIDTH ("PORT_32_BIT"),
.ENUM_PORT2_WIDTH ("PORT_32_BIT"),
.ENUM_PORT3_WIDTH ("PORT_32_BIT"),
.ENUM_PORT4_WIDTH ("PORT_32_BIT"),
.ENUM_PORT5_WIDTH ("PORT_32_BIT"),
.ENUM_PRIORITY_0_0 ("WEIGHT_0"),
.ENUM_PRIORITY_0_1 ("WEIGHT_0"),
.ENUM_PRIORITY_0_2 ("WEIGHT_0"),
.ENUM_PRIORITY_0_3 ("WEIGHT_0"),
.ENUM_PRIORITY_0_4 ("WEIGHT_0"),
.ENUM_PRIORITY_0_5 ("WEIGHT_0"),
.ENUM_PRIORITY_1_0 ("WEIGHT_0"),
.ENUM_PRIORITY_1_1 ("WEIGHT_0"),
.ENUM_PRIORITY_1_2 ("WEIGHT_0"),
.ENUM_PRIORITY_1_3 ("WEIGHT_0"),
.ENUM_PRIORITY_1_4 ("WEIGHT_0"),
.ENUM_PRIORITY_1_5 ("WEIGHT_0"),
.ENUM_PRIORITY_2_0 ("WEIGHT_0"),
.ENUM_PRIORITY_2_1 ("WEIGHT_0"),
.ENUM_PRIORITY_2_2 ("WEIGHT_0"),
.ENUM_PRIORITY_2_3 ("WEIGHT_0"),
.ENUM_PRIORITY_2_4 ("WEIGHT_0"),
.ENUM_PRIORITY_2_5 ("WEIGHT_0"),
.ENUM_PRIORITY_3_0 ("WEIGHT_0"),
.ENUM_PRIORITY_3_1 ("WEIGHT_0"),
.ENUM_PRIORITY_3_2 ("WEIGHT_0"),
.ENUM_PRIORITY_3_3 ("WEIGHT_0"),
.ENUM_PRIORITY_3_4 ("WEIGHT_0"),
.ENUM_PRIORITY_3_5 ("WEIGHT_0"),
.ENUM_PRIORITY_4_0 ("WEIGHT_0"),
.ENUM_PRIORITY_4_1 ("WEIGHT_0"),
.ENUM_PRIORITY_4_2 ("WEIGHT_0"),
.ENUM_PRIORITY_4_3 ("WEIGHT_0"),
.ENUM_PRIORITY_4_4 ("WEIGHT_0"),
.ENUM_PRIORITY_4_5 ("WEIGHT_0"),
.ENUM_PRIORITY_5_0 ("WEIGHT_0"),
.ENUM_PRIORITY_5_1 ("WEIGHT_0"),
.ENUM_PRIORITY_5_2 ("WEIGHT_0"),
.ENUM_PRIORITY_5_3 ("WEIGHT_0"),
.ENUM_PRIORITY_5_4 ("WEIGHT_0"),
.ENUM_PRIORITY_5_5 ("WEIGHT_0"),
.ENUM_PRIORITY_6_0 ("WEIGHT_0"),
.ENUM_PRIORITY_6_1 ("WEIGHT_0"),
.ENUM_PRIORITY_6_2 ("WEIGHT_0"),
.ENUM_PRIORITY_6_3 ("WEIGHT_0"),
.ENUM_PRIORITY_6_4 ("WEIGHT_0"),
.ENUM_PRIORITY_6_5 ("WEIGHT_0"),
.ENUM_PRIORITY_7_0 ("WEIGHT_0"),
.ENUM_PRIORITY_7_1 ("WEIGHT_0"),
.ENUM_PRIORITY_7_2 ("WEIGHT_0"),
.ENUM_PRIORITY_7_3 ("WEIGHT_0"),
.ENUM_PRIORITY_7_4 ("WEIGHT_0"),
.ENUM_PRIORITY_7_5 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_RD_DWIDTH_0 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_1 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_2 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_3 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_4 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_5 ("DWIDTH_0"),
.ENUM_RD_FIFO_IN_USE_0 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_1 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_2 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_3 ("FALSE"),
.ENUM_RD_PORT_INFO_0 ("USE_NO"),
.ENUM_RD_PORT_INFO_1 ("USE_NO"),
.ENUM_RD_PORT_INFO_2 ("USE_NO"),
.ENUM_RD_PORT_INFO_3 ("USE_NO"),
.ENUM_RD_PORT_INFO_4 ("USE_NO"),
.ENUM_RD_PORT_INFO_5 ("USE_NO"),
.ENUM_READ_ODT_CHIP ("ODT_DISABLED"),
.ENUM_REORDER_DATA ("DATA_REORDERING"),
.ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"),
.ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"),
.ENUM_TEST_MODE ("NORMAL_MODE"),
.ENUM_THLD_JAR1_0 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_1 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_2 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_3 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_4 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_5 ("THRESHOLD_32"),
.ENUM_THLD_JAR2_0 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_1 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_2 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_3 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_4 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_5 ("THRESHOLD_16"),
.ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"),
.ENUM_USER_ECC_EN ("DISABLE"),
.ENUM_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WR_DWIDTH_0 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_1 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_2 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_3 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_4 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_5 ("DWIDTH_0"),
.ENUM_WR_FIFO_IN_USE_0 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_1 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_2 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_3 ("FALSE"),
.ENUM_WR_PORT_INFO_0 ("USE_NO"),
.ENUM_WR_PORT_INFO_1 ("USE_NO"),
.ENUM_WR_PORT_INFO_2 ("USE_NO"),
.ENUM_WR_PORT_INFO_3 ("USE_NO"),
.ENUM_WR_PORT_INFO_4 ("USE_NO"),
.ENUM_WR_PORT_INFO_5 ("USE_NO"),
.ENUM_WRITE_ODT_CHIP ("WRITE_CHIP0_ODT0_CHIP1"),
.INTG_MEM_AUTO_PD_CYCLES (0),
.INTG_CYC_TO_RLD_JARS_0 (1),
.INTG_CYC_TO_RLD_JARS_1 (1),
.INTG_CYC_TO_RLD_JARS_2 (1),
.INTG_CYC_TO_RLD_JARS_3 (1),
.INTG_CYC_TO_RLD_JARS_4 (1),
.INTG_CYC_TO_RLD_JARS_5 (1),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0),
.INTG_EXTRA_CTL_CLK_ARF_PERIOD (0),
.INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PDN_PERIOD (0),
.INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0),
.INTG_EXTRA_CTL_CLK_RD_TO_WR (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2),
.INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0),
.INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_WR_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_WR_TO_RD (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3),
.INTG_EXTRA_CTL_CLK_WR_TO_WR (0),
.INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0),
.INTG_MEM_IF_TREFI (3120),
.INTG_MEM_IF_TRFC (104),
.INTG_RCFG_SUM_WT_PRIORITY_0 (0),
.INTG_RCFG_SUM_WT_PRIORITY_1 (0),
.INTG_RCFG_SUM_WT_PRIORITY_2 (0),
.INTG_RCFG_SUM_WT_PRIORITY_3 (0),
.INTG_RCFG_SUM_WT_PRIORITY_4 (0),
.INTG_RCFG_SUM_WT_PRIORITY_5 (0),
.INTG_RCFG_SUM_WT_PRIORITY_6 (0),
.INTG_RCFG_SUM_WT_PRIORITY_7 (0),
.INTG_SUM_WT_PRIORITY_0 (0),
.INTG_SUM_WT_PRIORITY_1 (0),
.INTG_SUM_WT_PRIORITY_2 (0),
.INTG_SUM_WT_PRIORITY_3 (0),
.INTG_SUM_WT_PRIORITY_4 (0),
.INTG_SUM_WT_PRIORITY_5 (0),
.INTG_SUM_WT_PRIORITY_6 (0),
.INTG_SUM_WT_PRIORITY_7 (0),
.INTG_POWER_SAVING_EXIT_CYCLES (5),
.INTG_MEM_CLK_ENTRY_CYCLES (10),
.ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"),
.ENUM_ENABLE_BURST_TERMINATE ("DISABLED"),
.AFI_RATE_RATIO (1),
.AFI_ADDR_WIDTH (15),
.AFI_BANKADDR_WIDTH (3),
.AFI_CONTROL_WIDTH (1),
.AFI_CS_WIDTH (1),
.AFI_DM_WIDTH (8),
.AFI_DQ_WIDTH (64),
.AFI_ODT_WIDTH (1),
.AFI_WRITE_DQS_WIDTH (4),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6),
.HARD_PHY (1)
) c0 (
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.local_init_done (), // status.local_init_done
.local_cal_success (), // .local_cal_success
.local_cal_fail (), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (), // .afi_init_req
.afi_cal_req (), // .afi_cal_req
.afi_seq_busy (), // .afi_seq_busy
.afi_ctl_refresh_done (), // .afi_ctl_refresh_done
.afi_ctl_long_idle (), // .afi_ctl_long_idle
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.mp_cmd_clk_0 (1'b0), // (terminated)
.mp_cmd_reset_n_0 (1'b1), // (terminated)
.mp_cmd_clk_1 (1'b0), // (terminated)
.mp_cmd_reset_n_1 (1'b1), // (terminated)
.mp_cmd_clk_2 (1'b0), // (terminated)
.mp_cmd_reset_n_2 (1'b1), // (terminated)
.mp_cmd_clk_3 (1'b0), // (terminated)
.mp_cmd_reset_n_3 (1'b1), // (terminated)
.mp_cmd_clk_4 (1'b0), // (terminated)
.mp_cmd_reset_n_4 (1'b1), // (terminated)
.mp_cmd_clk_5 (1'b0), // (terminated)
.mp_cmd_reset_n_5 (1'b1), // (terminated)
.mp_rfifo_clk_0 (1'b0), // (terminated)
.mp_rfifo_reset_n_0 (1'b1), // (terminated)
.mp_wfifo_clk_0 (1'b0), // (terminated)
.mp_wfifo_reset_n_0 (1'b1), // (terminated)
.mp_rfifo_clk_1 (1'b0), // (terminated)
.mp_rfifo_reset_n_1 (1'b1), // (terminated)
.mp_wfifo_clk_1 (1'b0), // (terminated)
.mp_wfifo_reset_n_1 (1'b1), // (terminated)
.mp_rfifo_clk_2 (1'b0), // (terminated)
.mp_rfifo_reset_n_2 (1'b1), // (terminated)
.mp_wfifo_clk_2 (1'b0), // (terminated)
.mp_wfifo_reset_n_2 (1'b1), // (terminated)
.mp_rfifo_clk_3 (1'b0), // (terminated)
.mp_rfifo_reset_n_3 (1'b1), // (terminated)
.mp_wfifo_clk_3 (1'b0), // (terminated)
.mp_wfifo_reset_n_3 (1'b1), // (terminated)
.csr_clk (1'b0), // (terminated)
.csr_reset_n (1'b1), // (terminated)
.avl_ready_0 (), // (terminated)
.avl_burstbegin_0 (1'b0), // (terminated)
.avl_addr_0 (1'b0), // (terminated)
.avl_rdata_valid_0 (), // (terminated)
.avl_rdata_0 (), // (terminated)
.avl_wdata_0 (1'b0), // (terminated)
.avl_be_0 (1'b0), // (terminated)
.avl_read_req_0 (1'b0), // (terminated)
.avl_write_req_0 (1'b0), // (terminated)
.avl_size_0 (3'b000), // (terminated)
.avl_ready_1 (), // (terminated)
.avl_burstbegin_1 (1'b0), // (terminated)
.avl_addr_1 (1'b0), // (terminated)
.avl_rdata_valid_1 (), // (terminated)
.avl_rdata_1 (), // (terminated)
.avl_wdata_1 (1'b0), // (terminated)
.avl_be_1 (1'b0), // (terminated)
.avl_read_req_1 (1'b0), // (terminated)
.avl_write_req_1 (1'b0), // (terminated)
.avl_size_1 (3'b000), // (terminated)
.avl_ready_2 (), // (terminated)
.avl_burstbegin_2 (1'b0), // (terminated)
.avl_addr_2 (1'b0), // (terminated)
.avl_rdata_valid_2 (), // (terminated)
.avl_rdata_2 (), // (terminated)
.avl_wdata_2 (1'b0), // (terminated)
.avl_be_2 (1'b0), // (terminated)
.avl_read_req_2 (1'b0), // (terminated)
.avl_write_req_2 (1'b0), // (terminated)
.avl_size_2 (3'b000), // (terminated)
.avl_ready_3 (), // (terminated)
.avl_burstbegin_3 (1'b0), // (terminated)
.avl_addr_3 (1'b0), // (terminated)
.avl_rdata_valid_3 (), // (terminated)
.avl_rdata_3 (), // (terminated)
.avl_wdata_3 (1'b0), // (terminated)
.avl_be_3 (1'b0), // (terminated)
.avl_read_req_3 (1'b0), // (terminated)
.avl_write_req_3 (1'b0), // (terminated)
.avl_size_3 (3'b000), // (terminated)
.avl_ready_4 (), // (terminated)
.avl_burstbegin_4 (1'b0), // (terminated)
.avl_addr_4 (1'b0), // (terminated)
.avl_rdata_valid_4 (), // (terminated)
.avl_rdata_4 (), // (terminated)
.avl_wdata_4 (1'b0), // (terminated)
.avl_be_4 (1'b0), // (terminated)
.avl_read_req_4 (1'b0), // (terminated)
.avl_write_req_4 (1'b0), // (terminated)
.avl_size_4 (3'b000), // (terminated)
.avl_ready_5 (), // (terminated)
.avl_burstbegin_5 (1'b0), // (terminated)
.avl_addr_5 (1'b0), // (terminated)
.avl_rdata_valid_5 (), // (terminated)
.avl_rdata_5 (), // (terminated)
.avl_wdata_5 (1'b0), // (terminated)
.avl_be_5 (1'b0), // (terminated)
.avl_read_req_5 (1'b0), // (terminated)
.avl_write_req_5 (1'b0), // (terminated)
.avl_size_5 (3'b000), // (terminated)
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (10'b0000000000), // (terminated)
.csr_be (1'b0), // (terminated)
.csr_wdata (8'b00000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_deep_powerdn_req (1'b0), // (terminated)
.local_deep_powerdn_chip (1'b0), // (terminated)
.local_deep_powerdn_ack (), // (terminated)
.local_powerdn_ack (), // (terminated)
.local_priority (1'b0), // (terminated)
.bonding_in_1 (4'b0000), // (terminated)
.bonding_in_2 (6'b000000), // (terminated)
.bonding_in_3 (6'b000000), // (terminated)
.bonding_out_1 (), // (terminated)
.bonding_out_2 (), // (terminated)
.bonding_out_3 () // (terminated)
);
altera_mem_if_oct_cyclonev #(
.OCT_TERM_CONTROL_WIDTH (16)
) oct (
.oct_rzqin (oct_rzqin), // oct.rzqin
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
);
altera_mem_if_dll_cyclonev #(
.DLL_DELAY_CTRL_WIDTH (7),
.DLL_OFFSET_CTRL_WIDTH (6),
.DELAY_BUFFER_MODE ("HIGH"),
.DELAY_CHAIN_LENGTH (8),
.DLL_INPUT_FREQUENCY_PS_STR ("2500 ps")
) dll (
.clk (p0_dll_clk_clk), // clk.clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl) // .dll_delayctrl
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MAJ3_FUNCTIONAL_V
`define SKY130_FD_SC_LP__MAJ3_FUNCTIONAL_V
/**
* maj3: 3-input majority vote.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__maj3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire or1_out_X;
// Name Output Other arguments
or or0 (or0_out , B, A );
and and0 (and0_out , or0_out, C );
and and1 (and1_out , A, B );
or or1 (or1_out_X, and1_out, and0_out);
buf buf0 (X , or1_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__MAJ3_FUNCTIONAL_V |
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: mig_7series_v4_0_poc_meta.v
// /___/ /\ Date Last Modified: $$
// \ \ / \ Date Created:Tue 15 Jan 2014
// \___\/\___\
//
//Device: Virtex-7
//Design Name: DDR3 SDRAM
//Purpose: Phaser output calibration meta controller.
//
// Compute center of the window set up with with the ktap_left,
// ktap_right dance (hereafter "the window"). Also compute center of the
// edge (hereafter "the edge") to be aligned in the center
// of this window.
//
// Following the ktap_left/right dance, the to be centered edge is
// always left at the right edge of the window
// if SCANFROMRIGHT == 1, and the left edge otherwise.
//
// An assumption is the rise(0) case has a window wider than the noise on the
// edge. The noise case with the possibly narrow window
// will always be shifted by 90. And the fall(180) case is shifted by
// 90 twice. Hence when we start, we can assume the center of the
// edge is to the right/left of the the window center.
//
// The actual hardware does not necessarily monotonically appear to
// move the window centers. Because of noise, it is possible for the
// centered edge to move opposite the expected direction with a tap increment.
//
// This problem is solved by computing the absolute difference between
// the centers and the circular distance between the centers. These will
// be the same until the difference transits through zero. Then the circular
// difference will jump to almost the value of TAPSPERKCLK.
//
// The window center computation is done at 1/2 tap increments to maintain
// resolution through the divide by 2 for centering.
//
// There is a corner case of when the shift is greater than 180 degress. In
// this case the absolute difference and the circular difference will be
// unequal at the beginning of the alignment. This is solved by latching
// if they are equal at the end of each cycle. The completion must see
// that they were equal in the previous cycle, but are not equal in this cycle.
//
// Since the phaser out steps are of unknown size, it is possible to overshoot
// the center. The previous difference is recorded and if its less than the current
// difference, poc_backup is driven high.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v4_0_poc_meta #
(parameter SCANFROMRIGHT = 0,
parameter TCQ = 100,
parameter TAPCNTRWIDTH = 7,
parameter TAPSPERKCLK = 112)
(/*AUTOARG*/
// Outputs
run_ends, mmcm_edge_detect_done, edge_center, left, right,
window_center, diff, poc_backup, mmcm_lbclk_edge_aligned,
// Inputs
rst, clk, mmcm_edge_detect_rdy, run_too_small, run, run_end,
run_polarity, rise_lead_right, rise_trail_left, rise_lead_center,
rise_trail_center, rise_trail_right, rise_lead_left, ninety_offsets,
use_noise_window, ktap_at_right_edge, ktap_at_left_edge
);
localparam NINETY = TAPSPERKCLK/4;
function [TAPCNTRWIDTH-1:0] offset (input [TAPCNTRWIDTH-1:0] a,
input [1:0] b,
input integer base);
integer offset_ii;
begin
offset_ii = (a + b * NINETY) < base
? (a + b * NINETY)
: (a + b * NINETY - base);
offset = offset_ii[TAPCNTRWIDTH-1:0];
end
endfunction // offset
function [TAPCNTRWIDTH-1:0] mod_sub (input [TAPCNTRWIDTH-1:0] a,
input [TAPCNTRWIDTH-1:0] b,
input integer base);
begin
mod_sub = (a>=b) ? a-b : a+base-b;
end
endfunction // mod_sub
function [TAPCNTRWIDTH:0] center (input [TAPCNTRWIDTH-1:0] left,
input [TAPCNTRWIDTH-1:0] diff,
input integer base);
integer center_ii;
begin
center_ii = ({left, 1'b0} + diff < base * 2)
? {left, 1'b0} + diff + 32'h0
: {left, 1'b0} + diff - base * 2;
center = center_ii[TAPCNTRWIDTH:0];
end
endfunction // center
input rst;
input clk;
input mmcm_edge_detect_rdy;
reg [1:0] run_ends_r;
input run_too_small;
reg run_too_small_r1, run_too_small_r2, run_too_small_r3;
always @ (posedge clk) run_too_small_r1 <= #TCQ run_too_small & (run_ends_r == 'd1); //align with run_end_r1;
always @ (posedge clk) run_too_small_r2 <= #TCQ run_too_small_r1;
always @ (posedge clk) run_too_small_r3 <= #TCQ run_too_small_r2;
wire reset_run_ends = rst || ~mmcm_edge_detect_rdy || run_too_small_r3 ;
// This input used only for the SVA.
input [TAPCNTRWIDTH-1:0] run;
input run_end;
reg run_end_r, run_end_r1, run_end_r2, run_end_r3;
always @(posedge clk) run_end_r <= #TCQ run_end;
always @(posedge clk) run_end_r1 <= #TCQ run_end_r;
always @(posedge clk) run_end_r2 <= #TCQ run_end_r1;
always @(posedge clk) run_end_r3 <= #TCQ run_end_r2;
input run_polarity;
reg run_polarity_held_ns, run_polarity_held_r;
always @(posedge clk) run_polarity_held_r <= #TCQ run_polarity_held_ns;
always @(*) run_polarity_held_ns = run_end ? run_polarity : run_polarity_held_r;
reg [1:0] run_ends_ns;
always @(posedge clk) run_ends_r <= #TCQ run_ends_ns;
always @(*) begin
run_ends_ns = run_ends_r;
if (reset_run_ends) run_ends_ns = 2'b0;
else case (run_ends_r)
2'b00 : run_ends_ns = run_ends_r + {1'b0, run_end_r3 && run_polarity_held_r};
2'b01, 2'b10 : run_ends_ns = run_ends_r + {1'b0, run_end_r3};
endcase // case (run_ends_r)
end // always @ begin
output [1:0] run_ends;
assign run_ends = run_ends_r;
reg done_r;
wire done_ns = mmcm_edge_detect_rdy && &run_ends_r;
always @(posedge clk) done_r <= #TCQ done_ns;
output mmcm_edge_detect_done;
assign mmcm_edge_detect_done = done_r;
input [TAPCNTRWIDTH-1:0] rise_lead_right;
input [TAPCNTRWIDTH-1:0] rise_trail_left;
input [TAPCNTRWIDTH-1:0] rise_lead_center;
input [TAPCNTRWIDTH-1:0] rise_trail_center;
input [TAPCNTRWIDTH-1:0] rise_trail_right;
input [TAPCNTRWIDTH-1:0] rise_lead_left;
input [1:0] ninety_offsets;
wire [1:0] offsets = SCANFROMRIGHT == 1 ? ninety_offsets : 2'b00 - ninety_offsets;
wire [TAPCNTRWIDTH-1:0] rise_lead_center_offset_ns = offset(rise_lead_center, offsets, TAPSPERKCLK);
wire [TAPCNTRWIDTH-1:0] rise_trail_center_offset_ns = offset(rise_trail_center, offsets, TAPSPERKCLK);
reg [TAPCNTRWIDTH-1:0] rise_lead_center_offset_r, rise_trail_center_offset_r;
always @(posedge clk) rise_lead_center_offset_r <= #TCQ rise_lead_center_offset_ns;
always @(posedge clk) rise_trail_center_offset_r <= #TCQ rise_trail_center_offset_ns;
wire [TAPCNTRWIDTH-1:0] edge_diff_ns = mod_sub(rise_trail_center_offset_r, rise_lead_center_offset_r, TAPSPERKCLK);
reg [TAPCNTRWIDTH-1:0] edge_diff_r;
always @(posedge clk) edge_diff_r <= #TCQ edge_diff_ns;
wire [TAPCNTRWIDTH:0] edge_center_ns = center(rise_lead_center_offset_r, edge_diff_r, TAPSPERKCLK);
reg [TAPCNTRWIDTH:0] edge_center_r;
always @(posedge clk) edge_center_r <= #TCQ edge_center_ns;
output [TAPCNTRWIDTH:0] edge_center;
assign edge_center = edge_center_r;
input use_noise_window;
output [TAPCNTRWIDTH-1:0] left, right;
assign left = use_noise_window ? rise_lead_left : rise_trail_left;
assign right = use_noise_window ? rise_trail_right : rise_lead_right;
wire [TAPCNTRWIDTH-1:0] center_diff_ns = mod_sub(right, left, TAPSPERKCLK);
reg [TAPCNTRWIDTH-1:0] center_diff_r;
always @(posedge clk) center_diff_r <= #TCQ center_diff_ns;
wire [TAPCNTRWIDTH:0] window_center_ns = center(left, center_diff_r, TAPSPERKCLK);
reg [TAPCNTRWIDTH:0] window_center_r;
always @(posedge clk) window_center_r <= #TCQ window_center_ns;
output [TAPCNTRWIDTH:0] window_center;
assign window_center = window_center_r;
localparam TAPSPERKCLKX2 = TAPSPERKCLK * 2;
wire [TAPCNTRWIDTH+1:0] left_center = {1'b0, SCANFROMRIGHT == 1 ? window_center_r : edge_center_r};
wire [TAPCNTRWIDTH+1:0] right_center = {1'b0, SCANFROMRIGHT == 1 ? edge_center_r : window_center_r};
wire [TAPCNTRWIDTH+1:0] diff_ns = right_center >= left_center
? right_center - left_center
: right_center + TAPSPERKCLKX2[TAPCNTRWIDTH+1:0] - left_center;
reg [TAPCNTRWIDTH+1:0] diff_r;
always @(posedge clk) diff_r <= #TCQ diff_ns;
output [TAPCNTRWIDTH+1:0] diff;
assign diff = diff_r;
wire [TAPCNTRWIDTH+1:0] abs_diff = diff_r > TAPSPERKCLKX2[TAPCNTRWIDTH+1:0]/2
? TAPSPERKCLKX2[TAPCNTRWIDTH+1:0] - diff_r
: diff_r;
reg [TAPCNTRWIDTH+1:0] prev_ns, prev_r;
always @(posedge clk) prev_r <= #TCQ prev_ns;
always @(*) prev_ns = done_ns ? diff_r : prev_r;
input ktap_at_right_edge;
input ktap_at_left_edge;
wire centering = !(ktap_at_right_edge || ktap_at_left_edge);
wire diffs_eq = abs_diff == diff_r;
reg diffs_eq_ns, diffs_eq_r;
always @(*) diffs_eq_ns = centering && ((done_r && done_ns) ? diffs_eq : diffs_eq_r);
always @(posedge clk) diffs_eq_r <= #TCQ diffs_eq_ns;
reg edge_aligned_r;
reg prev_valid_ns, prev_valid_r;
always @(posedge clk) prev_valid_r <= #TCQ prev_valid_ns;
always @(*) prev_valid_ns = (~rst && ~ktap_at_right_edge && ~ktap_at_left_edge && ~edge_aligned_r) && prev_valid_r | done_ns;
wire indicate_alignment = ~rst && centering && done_ns;
wire edge_aligned_ns = indicate_alignment && (~|diff_r || ~diffs_eq & diffs_eq_r);
always @(posedge clk) edge_aligned_r <= #TCQ edge_aligned_ns;
reg poc_backup_r;
wire poc_backup_ns = edge_aligned_ns && abs_diff > prev_r;
always @(posedge clk) poc_backup_r <= #TCQ poc_backup_ns;
output poc_backup;
assign poc_backup = poc_backup_r;
output mmcm_lbclk_edge_aligned;
assign mmcm_lbclk_edge_aligned = edge_aligned_r;
endmodule // mig_7series_v4_0_poc_meta
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-extensions:(".v")
// End:
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : arb_mux.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_arb_mux #
(
parameter TCQ = 100,
parameter EVEN_CWL_2T_MODE = "OFF",
parameter ADDR_CMD_MODE = "1T",
parameter BANK_VECT_INDX = 11,
parameter BANK_WIDTH = 3,
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter CL = 5,
parameter CWL = 5,
parameter DATA_BUF_ADDR_VECT_INDX = 31,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2, // # DRAM CKs per fabric CLKs
parameter nCS_PER_RANK = 1,
parameter nRAS = 37500, // ACT->PRE cmd period (CKs)
parameter nRCD = 12500, // ACT->R/W delay (CKs)
parameter nSLOTS = 2,
parameter nWR = 6, // Write recovery (CKs)
parameter RANKS = 1,
parameter RANK_VECT_INDX = 15,
parameter RANK_WIDTH = 2,
parameter ROW_VECT_INDX = 63,
parameter ROW_WIDTH = 16,
parameter RTT_NOM = "40",
parameter RTT_WR = "120",
parameter SLOT_0_CONFIG = 8'b0000_0101,
parameter SLOT_1_CONFIG = 8'b0000_1010
)
(/*AUTOARG*/
// Outputs
output [ROW_WIDTH-1:0] col_a, // From arb_select0 of arb_select.v
output [BANK_WIDTH-1:0] col_ba, // From arb_select0 of arb_select.v
output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_select0 of arb_select.v
output col_periodic_rd, // From arb_select0 of arb_select.v
output [RANK_WIDTH-1:0] col_ra, // From arb_select0 of arb_select.v
output col_rmw, // From arb_select0 of arb_select.v
output col_rd_wr,
output [ROW_WIDTH-1:0] col_row, // From arb_select0 of arb_select.v
output col_size, // From arb_select0 of arb_select.v
output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_select0 of arb_select.v
output wire [nCK_PER_CLK-1:0] mc_ras_n,
output wire [nCK_PER_CLK-1:0] mc_cas_n,
output wire [nCK_PER_CLK-1:0] mc_we_n,
output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
output wire [1:0] mc_odt,
output wire [nCK_PER_CLK-1:0] mc_cke,
output wire [3:0] mc_aux_out0,
output wire [3:0] mc_aux_out1,
output [2:0] mc_cmd,
output [5:0] mc_data_offset,
output [5:0] mc_data_offset_1,
output [5:0] mc_data_offset_2,
output [1:0] mc_cas_slot,
output [RANK_WIDTH-1:0] rnk_config, // From arb_select0 of arb_select.v
output rnk_config_valid_r, // From arb_row_col0 of arb_row_col.v
output [nBANK_MACHS-1:0] sending_row, // From arb_row_col0 of arb_row_col.v
output [nBANK_MACHS-1:0] sending_pre,
output sent_col, // From arb_row_col0 of arb_row_col.v
output sent_col_r, // From arb_row_col0 of arb_row_col.v
output sent_row, // From arb_row_col0 of arb_row_col.v
output [nBANK_MACHS-1:0] sending_col,
output rnk_config_strobe,
output insert_maint_r1,
output rnk_config_kill_rts_col,
// Inputs
input clk,
input rst,
input init_calib_complete,
input [6*RANKS-1:0] calib_rddata_offset,
input [6*RANKS-1:0] calib_rddata_offset_1,
input [6*RANKS-1:0] calib_rddata_offset_2,
input [ROW_VECT_INDX:0] col_addr, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] col_rdy_wr, // To arb_row_col0 of arb_row_col.v
input insert_maint_r, // To arb_row_col0 of arb_row_col.v
input [RANK_WIDTH-1:0] maint_rank_r, // To arb_select0 of arb_select.v
input maint_zq_r, // To arb_select0 of arb_select.v
input maint_sre_r, // To arb_select0 of arb_select.v
input maint_srx_r, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] rd_wr_r, // To arb_select0 of arb_select.v
input [BANK_VECT_INDX:0] req_bank_r, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_cas, // To arb_select0 of arb_select.v
input [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r,// To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_periodic_rd_r, // To arb_select0 of arb_select.v
input [RANK_VECT_INDX:0] req_rank_r, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_ras, // To arb_select0 of arb_select.v
input [ROW_VECT_INDX:0] req_row_r, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_size_r, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_wr_r, // To arb_select0 of arb_select.v
input [ROW_VECT_INDX:0] row_addr, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] row_cmd_wr, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] rtc, // To arb_row_col0 of arb_row_col.v
input [nBANK_MACHS-1:0] rts_col, // To arb_row_col0 of arb_row_col.v
input [nBANK_MACHS-1:0] rts_row, // To arb_row_col0 of arb_row_col.v
input [nBANK_MACHS-1:0] rts_pre, // To arb_row_col0 of arb_row_col.v
input [7:0] slot_0_present, // To arb_select0 of arb_select.v
input [7:0] slot_1_present // To arb_select0 of arb_select.v
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire cs_en0; // From arb_row_col0 of arb_row_col.v
wire cs_en1; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_col_r; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_col_wr; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_config_r; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_row_r; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_pre_r; // From arb_row_col0 of arb_row_col.v
wire send_cmd0_row; // From arb_row_col0 of arb_row_col.v
wire send_cmd0_col; // From arb_row_col0 of arb_row_col.v
wire send_cmd1_row; // From arb_row_col0 of arb_row_col.v
wire send_cmd1_col;
wire send_cmd2_row;
wire send_cmd2_col;
wire send_cmd2_pre;
wire send_cmd3_col;
wire [5:0] col_channel_offset;
// End of automatics
wire sent_col_i;
wire cs_en2;
wire cs_en3;
assign sent_col = sent_col_i;
mig_7series_v2_3_arb_row_col #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.CWL (CWL),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nRAS (nRAS),
.nRCD (nRCD),
.nWR (nWR))
arb_row_col0
(/*AUTOINST*/
// Outputs
.grant_row_r (grant_row_r[nBANK_MACHS-1:0]),
.grant_pre_r (grant_pre_r[nBANK_MACHS-1:0]),
.sent_row (sent_row),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.sending_pre (sending_pre[nBANK_MACHS-1:0]),
.grant_config_r (grant_config_r[nBANK_MACHS-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.rnk_config_valid_r (rnk_config_valid_r),
.grant_col_r (grant_col_r[nBANK_MACHS-1:0]),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.sent_col (sent_col_i),
.sent_col_r (sent_col_r),
.grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]),
.send_cmd0_row (send_cmd0_row),
.send_cmd0_col (send_cmd0_col),
.send_cmd1_row (send_cmd1_row),
.send_cmd1_col (send_cmd1_col),
.send_cmd2_row (send_cmd2_row),
.send_cmd2_col (send_cmd2_col),
.send_cmd2_pre (send_cmd2_pre),
.send_cmd3_col (send_cmd3_col),
.col_channel_offset (col_channel_offset),
.cs_en0 (cs_en0),
.cs_en1 (cs_en1),
.cs_en2 (cs_en2),
.cs_en3 (cs_en3),
.insert_maint_r1 (insert_maint_r1),
// Inputs
.clk (clk),
.rst (rst),
.rts_row (rts_row[nBANK_MACHS-1:0]),
.rts_pre (rts_pre[nBANK_MACHS-1:0]),
.insert_maint_r (insert_maint_r),
.rts_col (rts_col[nBANK_MACHS-1:0]),
.rtc (rtc[nBANK_MACHS-1:0]),
.col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0]));
mig_7series_v2_3_arb_select #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_VECT_INDX (BANK_VECT_INDX),
.BANK_WIDTH (BANK_WIDTH),
.BURST_MODE (BURST_MODE),
.CS_WIDTH (CS_WIDTH),
.CL (CL),
.CWL (CWL),
.DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.ECC (ECC),
.CKE_ODT_AUX (CKE_ODT_AUX),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCS_PER_RANK (nCS_PER_RANK),
.nSLOTS (nSLOTS),
.RANKS (RANKS),
.RANK_VECT_INDX (RANK_VECT_INDX),
.RANK_WIDTH (RANK_WIDTH),
.ROW_VECT_INDX (ROW_VECT_INDX),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG))
arb_select0
(/*AUTOINST*/
// Outputs
.col_periodic_rd (col_periodic_rd),
.col_ra (col_ra[RANK_WIDTH-1:0]),
.col_ba (col_ba[BANK_WIDTH-1:0]),
.col_a (col_a[ROW_WIDTH-1:0]),
.col_rmw (col_rmw),
.col_rd_wr (col_rd_wr),
.col_size (col_size),
.col_row (col_row[ROW_WIDTH-1:0]),
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.mc_bank (mc_bank),
.mc_address (mc_address),
.mc_ras_n (mc_ras_n),
.mc_cas_n (mc_cas_n),
.mc_we_n (mc_we_n),
.mc_cs_n (mc_cs_n),
.mc_odt (mc_odt),
.mc_cke (mc_cke),
.mc_aux_out0 (mc_aux_out0),
.mc_aux_out1 (mc_aux_out1),
.mc_cmd (mc_cmd),
.mc_data_offset (mc_data_offset),
.mc_data_offset_1 (mc_data_offset_1),
.mc_data_offset_2 (mc_data_offset_2),
.mc_cas_slot (mc_cas_slot),
.col_channel_offset (col_channel_offset),
.rnk_config (rnk_config),
// Inputs
.clk (clk),
.rst (rst),
.init_calib_complete (init_calib_complete),
.calib_rddata_offset (calib_rddata_offset),
.calib_rddata_offset_1 (calib_rddata_offset_1),
.calib_rddata_offset_2 (calib_rddata_offset_2),
.req_rank_r (req_rank_r[RANK_VECT_INDX:0]),
.req_bank_r (req_bank_r[BANK_VECT_INDX:0]),
.req_ras (req_ras[nBANK_MACHS-1:0]),
.req_cas (req_cas[nBANK_MACHS-1:0]),
.req_wr_r (req_wr_r[nBANK_MACHS-1:0]),
.grant_row_r (grant_row_r[nBANK_MACHS-1:0]),
.grant_pre_r (grant_pre_r[nBANK_MACHS-1:0]),
.row_addr (row_addr[ROW_VECT_INDX:0]),
.row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]),
.insert_maint_r1 (insert_maint_r1),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]),
.req_size_r (req_size_r[nBANK_MACHS-1:0]),
.rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]),
.req_row_r (req_row_r[ROW_VECT_INDX:0]),
.col_addr (col_addr[ROW_VECT_INDX:0]),
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]),
.grant_col_r (grant_col_r[nBANK_MACHS-1:0]),
.grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]),
.send_cmd0_row (send_cmd0_row),
.send_cmd0_col (send_cmd0_col),
.send_cmd1_row (send_cmd1_row),
.send_cmd1_col (send_cmd1_col),
.send_cmd2_row (send_cmd2_row),
.send_cmd2_col (send_cmd2_col),
.send_cmd2_pre (send_cmd2_pre),
.send_cmd3_col (send_cmd3_col),
.sent_col (EVEN_CWL_2T_MODE == "ON" ? sent_col_r : sent_col),
.cs_en0 (cs_en0),
.cs_en1 (cs_en1),
.cs_en2 (cs_en2),
.cs_en3 (cs_en3),
.grant_config_r (grant_config_r[nBANK_MACHS-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]));
endmodule
|
//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_reset O 1
// RDY_set_verbosity O 1 const
// v_from_masters_0_awready O 1 reg
// v_from_masters_0_wready O 1 reg
// v_from_masters_0_bvalid O 1 reg
// v_from_masters_0_bid O 4 reg
// v_from_masters_0_bresp O 2 reg
// v_from_masters_0_arready O 1 reg
// v_from_masters_0_rvalid O 1 reg
// v_from_masters_0_rid O 4 reg
// v_from_masters_0_rdata O 64 reg
// v_from_masters_0_rresp O 2 reg
// v_from_masters_0_rlast O 1 reg
// v_from_masters_1_awready O 1 reg
// v_from_masters_1_wready O 1 reg
// v_from_masters_1_bvalid O 1 reg
// v_from_masters_1_bid O 4 reg
// v_from_masters_1_bresp O 2 reg
// v_from_masters_1_arready O 1 reg
// v_from_masters_1_rvalid O 1 reg
// v_from_masters_1_rid O 4 reg
// v_from_masters_1_rdata O 64 reg
// v_from_masters_1_rresp O 2 reg
// v_from_masters_1_rlast O 1 reg
// v_to_slaves_0_awvalid O 1 reg
// v_to_slaves_0_awid O 4 reg
// v_to_slaves_0_awaddr O 64 reg
// v_to_slaves_0_awlen O 8 reg
// v_to_slaves_0_awsize O 3 reg
// v_to_slaves_0_awburst O 2 reg
// v_to_slaves_0_awlock O 1 reg
// v_to_slaves_0_awcache O 4 reg
// v_to_slaves_0_awprot O 3 reg
// v_to_slaves_0_awqos O 4 reg
// v_to_slaves_0_awregion O 4 reg
// v_to_slaves_0_wvalid O 1 reg
// v_to_slaves_0_wdata O 64 reg
// v_to_slaves_0_wstrb O 8 reg
// v_to_slaves_0_wlast O 1 reg
// v_to_slaves_0_bready O 1 reg
// v_to_slaves_0_arvalid O 1 reg
// v_to_slaves_0_arid O 4 reg
// v_to_slaves_0_araddr O 64 reg
// v_to_slaves_0_arlen O 8 reg
// v_to_slaves_0_arsize O 3 reg
// v_to_slaves_0_arburst O 2 reg
// v_to_slaves_0_arlock O 1 reg
// v_to_slaves_0_arcache O 4 reg
// v_to_slaves_0_arprot O 3 reg
// v_to_slaves_0_arqos O 4 reg
// v_to_slaves_0_arregion O 4 reg
// v_to_slaves_0_rready O 1 reg
// v_to_slaves_1_awvalid O 1 reg
// v_to_slaves_1_awid O 4 reg
// v_to_slaves_1_awaddr O 64 reg
// v_to_slaves_1_awlen O 8 reg
// v_to_slaves_1_awsize O 3 reg
// v_to_slaves_1_awburst O 2 reg
// v_to_slaves_1_awlock O 1 reg
// v_to_slaves_1_awcache O 4 reg
// v_to_slaves_1_awprot O 3 reg
// v_to_slaves_1_awqos O 4 reg
// v_to_slaves_1_awregion O 4 reg
// v_to_slaves_1_wvalid O 1 reg
// v_to_slaves_1_wdata O 64 reg
// v_to_slaves_1_wstrb O 8 reg
// v_to_slaves_1_wlast O 1 reg
// v_to_slaves_1_bready O 1 reg
// v_to_slaves_1_arvalid O 1 reg
// v_to_slaves_1_arid O 4 reg
// v_to_slaves_1_araddr O 64 reg
// v_to_slaves_1_arlen O 8 reg
// v_to_slaves_1_arsize O 3 reg
// v_to_slaves_1_arburst O 2 reg
// v_to_slaves_1_arlock O 1 reg
// v_to_slaves_1_arcache O 4 reg
// v_to_slaves_1_arprot O 3 reg
// v_to_slaves_1_arqos O 4 reg
// v_to_slaves_1_arregion O 4 reg
// v_to_slaves_1_rready O 1 reg
// v_to_slaves_2_awvalid O 1 reg
// v_to_slaves_2_awid O 4 reg
// v_to_slaves_2_awaddr O 64 reg
// v_to_slaves_2_awlen O 8 reg
// v_to_slaves_2_awsize O 3 reg
// v_to_slaves_2_awburst O 2 reg
// v_to_slaves_2_awlock O 1 reg
// v_to_slaves_2_awcache O 4 reg
// v_to_slaves_2_awprot O 3 reg
// v_to_slaves_2_awqos O 4 reg
// v_to_slaves_2_awregion O 4 reg
// v_to_slaves_2_wvalid O 1 reg
// v_to_slaves_2_wdata O 64 reg
// v_to_slaves_2_wstrb O 8 reg
// v_to_slaves_2_wlast O 1 reg
// v_to_slaves_2_bready O 1 reg
// v_to_slaves_2_arvalid O 1 reg
// v_to_slaves_2_arid O 4 reg
// v_to_slaves_2_araddr O 64 reg
// v_to_slaves_2_arlen O 8 reg
// v_to_slaves_2_arsize O 3 reg
// v_to_slaves_2_arburst O 2 reg
// v_to_slaves_2_arlock O 1 reg
// v_to_slaves_2_arcache O 4 reg
// v_to_slaves_2_arprot O 3 reg
// v_to_slaves_2_arqos O 4 reg
// v_to_slaves_2_arregion O 4 reg
// v_to_slaves_2_rready O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4 reg
// v_from_masters_0_awvalid I 1
// v_from_masters_0_awid I 4 reg
// v_from_masters_0_awaddr I 64 reg
// v_from_masters_0_awlen I 8 reg
// v_from_masters_0_awsize I 3 reg
// v_from_masters_0_awburst I 2 reg
// v_from_masters_0_awlock I 1 reg
// v_from_masters_0_awcache I 4 reg
// v_from_masters_0_awprot I 3 reg
// v_from_masters_0_awqos I 4 reg
// v_from_masters_0_awregion I 4 reg
// v_from_masters_0_wvalid I 1
// v_from_masters_0_wdata I 64 reg
// v_from_masters_0_wstrb I 8 reg
// v_from_masters_0_wlast I 1 reg
// v_from_masters_0_bready I 1
// v_from_masters_0_arvalid I 1
// v_from_masters_0_arid I 4 reg
// v_from_masters_0_araddr I 64 reg
// v_from_masters_0_arlen I 8 reg
// v_from_masters_0_arsize I 3 reg
// v_from_masters_0_arburst I 2 reg
// v_from_masters_0_arlock I 1 reg
// v_from_masters_0_arcache I 4 reg
// v_from_masters_0_arprot I 3 reg
// v_from_masters_0_arqos I 4 reg
// v_from_masters_0_arregion I 4 reg
// v_from_masters_0_rready I 1
// v_from_masters_1_awvalid I 1
// v_from_masters_1_awid I 4 reg
// v_from_masters_1_awaddr I 64 reg
// v_from_masters_1_awlen I 8 reg
// v_from_masters_1_awsize I 3 reg
// v_from_masters_1_awburst I 2 reg
// v_from_masters_1_awlock I 1 reg
// v_from_masters_1_awcache I 4 reg
// v_from_masters_1_awprot I 3 reg
// v_from_masters_1_awqos I 4 reg
// v_from_masters_1_awregion I 4 reg
// v_from_masters_1_wvalid I 1
// v_from_masters_1_wdata I 64 reg
// v_from_masters_1_wstrb I 8 reg
// v_from_masters_1_wlast I 1 reg
// v_from_masters_1_bready I 1
// v_from_masters_1_arvalid I 1
// v_from_masters_1_arid I 4 reg
// v_from_masters_1_araddr I 64 reg
// v_from_masters_1_arlen I 8 reg
// v_from_masters_1_arsize I 3 reg
// v_from_masters_1_arburst I 2 reg
// v_from_masters_1_arlock I 1 reg
// v_from_masters_1_arcache I 4 reg
// v_from_masters_1_arprot I 3 reg
// v_from_masters_1_arqos I 4 reg
// v_from_masters_1_arregion I 4 reg
// v_from_masters_1_rready I 1
// v_to_slaves_0_awready I 1
// v_to_slaves_0_wready I 1
// v_to_slaves_0_bvalid I 1
// v_to_slaves_0_bid I 4 reg
// v_to_slaves_0_bresp I 2 reg
// v_to_slaves_0_arready I 1
// v_to_slaves_0_rvalid I 1
// v_to_slaves_0_rid I 4 reg
// v_to_slaves_0_rdata I 64 reg
// v_to_slaves_0_rresp I 2 reg
// v_to_slaves_0_rlast I 1 reg
// v_to_slaves_1_awready I 1
// v_to_slaves_1_wready I 1
// v_to_slaves_1_bvalid I 1
// v_to_slaves_1_bid I 4 reg
// v_to_slaves_1_bresp I 2 reg
// v_to_slaves_1_arready I 1
// v_to_slaves_1_rvalid I 1
// v_to_slaves_1_rid I 4 reg
// v_to_slaves_1_rdata I 64 reg
// v_to_slaves_1_rresp I 2 reg
// v_to_slaves_1_rlast I 1 reg
// v_to_slaves_2_awready I 1
// v_to_slaves_2_wready I 1
// v_to_slaves_2_bvalid I 1
// v_to_slaves_2_bid I 4 reg
// v_to_slaves_2_bresp I 2 reg
// v_to_slaves_2_arready I 1
// v_to_slaves_2_rvalid I 1
// v_to_slaves_2_rid I 4 reg
// v_to_slaves_2_rdata I 64 reg
// v_to_slaves_2_rresp I 2 reg
// v_to_slaves_2_rlast I 1 reg
// EN_reset I 1
// EN_set_verbosity I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFabric_2x3(CLK,
RST_N,
EN_reset,
RDY_reset,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
v_from_masters_0_awvalid,
v_from_masters_0_awid,
v_from_masters_0_awaddr,
v_from_masters_0_awlen,
v_from_masters_0_awsize,
v_from_masters_0_awburst,
v_from_masters_0_awlock,
v_from_masters_0_awcache,
v_from_masters_0_awprot,
v_from_masters_0_awqos,
v_from_masters_0_awregion,
v_from_masters_0_awready,
v_from_masters_0_wvalid,
v_from_masters_0_wdata,
v_from_masters_0_wstrb,
v_from_masters_0_wlast,
v_from_masters_0_wready,
v_from_masters_0_bvalid,
v_from_masters_0_bid,
v_from_masters_0_bresp,
v_from_masters_0_bready,
v_from_masters_0_arvalid,
v_from_masters_0_arid,
v_from_masters_0_araddr,
v_from_masters_0_arlen,
v_from_masters_0_arsize,
v_from_masters_0_arburst,
v_from_masters_0_arlock,
v_from_masters_0_arcache,
v_from_masters_0_arprot,
v_from_masters_0_arqos,
v_from_masters_0_arregion,
v_from_masters_0_arready,
v_from_masters_0_rvalid,
v_from_masters_0_rid,
v_from_masters_0_rdata,
v_from_masters_0_rresp,
v_from_masters_0_rlast,
v_from_masters_0_rready,
v_from_masters_1_awvalid,
v_from_masters_1_awid,
v_from_masters_1_awaddr,
v_from_masters_1_awlen,
v_from_masters_1_awsize,
v_from_masters_1_awburst,
v_from_masters_1_awlock,
v_from_masters_1_awcache,
v_from_masters_1_awprot,
v_from_masters_1_awqos,
v_from_masters_1_awregion,
v_from_masters_1_awready,
v_from_masters_1_wvalid,
v_from_masters_1_wdata,
v_from_masters_1_wstrb,
v_from_masters_1_wlast,
v_from_masters_1_wready,
v_from_masters_1_bvalid,
v_from_masters_1_bid,
v_from_masters_1_bresp,
v_from_masters_1_bready,
v_from_masters_1_arvalid,
v_from_masters_1_arid,
v_from_masters_1_araddr,
v_from_masters_1_arlen,
v_from_masters_1_arsize,
v_from_masters_1_arburst,
v_from_masters_1_arlock,
v_from_masters_1_arcache,
v_from_masters_1_arprot,
v_from_masters_1_arqos,
v_from_masters_1_arregion,
v_from_masters_1_arready,
v_from_masters_1_rvalid,
v_from_masters_1_rid,
v_from_masters_1_rdata,
v_from_masters_1_rresp,
v_from_masters_1_rlast,
v_from_masters_1_rready,
v_to_slaves_0_awvalid,
v_to_slaves_0_awid,
v_to_slaves_0_awaddr,
v_to_slaves_0_awlen,
v_to_slaves_0_awsize,
v_to_slaves_0_awburst,
v_to_slaves_0_awlock,
v_to_slaves_0_awcache,
v_to_slaves_0_awprot,
v_to_slaves_0_awqos,
v_to_slaves_0_awregion,
v_to_slaves_0_awready,
v_to_slaves_0_wvalid,
v_to_slaves_0_wdata,
v_to_slaves_0_wstrb,
v_to_slaves_0_wlast,
v_to_slaves_0_wready,
v_to_slaves_0_bvalid,
v_to_slaves_0_bid,
v_to_slaves_0_bresp,
v_to_slaves_0_bready,
v_to_slaves_0_arvalid,
v_to_slaves_0_arid,
v_to_slaves_0_araddr,
v_to_slaves_0_arlen,
v_to_slaves_0_arsize,
v_to_slaves_0_arburst,
v_to_slaves_0_arlock,
v_to_slaves_0_arcache,
v_to_slaves_0_arprot,
v_to_slaves_0_arqos,
v_to_slaves_0_arregion,
v_to_slaves_0_arready,
v_to_slaves_0_rvalid,
v_to_slaves_0_rid,
v_to_slaves_0_rdata,
v_to_slaves_0_rresp,
v_to_slaves_0_rlast,
v_to_slaves_0_rready,
v_to_slaves_1_awvalid,
v_to_slaves_1_awid,
v_to_slaves_1_awaddr,
v_to_slaves_1_awlen,
v_to_slaves_1_awsize,
v_to_slaves_1_awburst,
v_to_slaves_1_awlock,
v_to_slaves_1_awcache,
v_to_slaves_1_awprot,
v_to_slaves_1_awqos,
v_to_slaves_1_awregion,
v_to_slaves_1_awready,
v_to_slaves_1_wvalid,
v_to_slaves_1_wdata,
v_to_slaves_1_wstrb,
v_to_slaves_1_wlast,
v_to_slaves_1_wready,
v_to_slaves_1_bvalid,
v_to_slaves_1_bid,
v_to_slaves_1_bresp,
v_to_slaves_1_bready,
v_to_slaves_1_arvalid,
v_to_slaves_1_arid,
v_to_slaves_1_araddr,
v_to_slaves_1_arlen,
v_to_slaves_1_arsize,
v_to_slaves_1_arburst,
v_to_slaves_1_arlock,
v_to_slaves_1_arcache,
v_to_slaves_1_arprot,
v_to_slaves_1_arqos,
v_to_slaves_1_arregion,
v_to_slaves_1_arready,
v_to_slaves_1_rvalid,
v_to_slaves_1_rid,
v_to_slaves_1_rdata,
v_to_slaves_1_rresp,
v_to_slaves_1_rlast,
v_to_slaves_1_rready,
v_to_slaves_2_awvalid,
v_to_slaves_2_awid,
v_to_slaves_2_awaddr,
v_to_slaves_2_awlen,
v_to_slaves_2_awsize,
v_to_slaves_2_awburst,
v_to_slaves_2_awlock,
v_to_slaves_2_awcache,
v_to_slaves_2_awprot,
v_to_slaves_2_awqos,
v_to_slaves_2_awregion,
v_to_slaves_2_awready,
v_to_slaves_2_wvalid,
v_to_slaves_2_wdata,
v_to_slaves_2_wstrb,
v_to_slaves_2_wlast,
v_to_slaves_2_wready,
v_to_slaves_2_bvalid,
v_to_slaves_2_bid,
v_to_slaves_2_bresp,
v_to_slaves_2_bready,
v_to_slaves_2_arvalid,
v_to_slaves_2_arid,
v_to_slaves_2_araddr,
v_to_slaves_2_arlen,
v_to_slaves_2_arsize,
v_to_slaves_2_arburst,
v_to_slaves_2_arlock,
v_to_slaves_2_arcache,
v_to_slaves_2_arprot,
v_to_slaves_2_arqos,
v_to_slaves_2_arregion,
v_to_slaves_2_arready,
v_to_slaves_2_rvalid,
v_to_slaves_2_rid,
v_to_slaves_2_rdata,
v_to_slaves_2_rresp,
v_to_slaves_2_rlast,
v_to_slaves_2_rready);
input CLK;
input RST_N;
// action method reset
input EN_reset;
output RDY_reset;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method v_from_masters_0_m_awvalid
input v_from_masters_0_awvalid;
input [3 : 0] v_from_masters_0_awid;
input [63 : 0] v_from_masters_0_awaddr;
input [7 : 0] v_from_masters_0_awlen;
input [2 : 0] v_from_masters_0_awsize;
input [1 : 0] v_from_masters_0_awburst;
input v_from_masters_0_awlock;
input [3 : 0] v_from_masters_0_awcache;
input [2 : 0] v_from_masters_0_awprot;
input [3 : 0] v_from_masters_0_awqos;
input [3 : 0] v_from_masters_0_awregion;
// value method v_from_masters_0_m_awready
output v_from_masters_0_awready;
// action method v_from_masters_0_m_wvalid
input v_from_masters_0_wvalid;
input [63 : 0] v_from_masters_0_wdata;
input [7 : 0] v_from_masters_0_wstrb;
input v_from_masters_0_wlast;
// value method v_from_masters_0_m_wready
output v_from_masters_0_wready;
// value method v_from_masters_0_m_bvalid
output v_from_masters_0_bvalid;
// value method v_from_masters_0_m_bid
output [3 : 0] v_from_masters_0_bid;
// value method v_from_masters_0_m_bresp
output [1 : 0] v_from_masters_0_bresp;
// value method v_from_masters_0_m_buser
// action method v_from_masters_0_m_bready
input v_from_masters_0_bready;
// action method v_from_masters_0_m_arvalid
input v_from_masters_0_arvalid;
input [3 : 0] v_from_masters_0_arid;
input [63 : 0] v_from_masters_0_araddr;
input [7 : 0] v_from_masters_0_arlen;
input [2 : 0] v_from_masters_0_arsize;
input [1 : 0] v_from_masters_0_arburst;
input v_from_masters_0_arlock;
input [3 : 0] v_from_masters_0_arcache;
input [2 : 0] v_from_masters_0_arprot;
input [3 : 0] v_from_masters_0_arqos;
input [3 : 0] v_from_masters_0_arregion;
// value method v_from_masters_0_m_arready
output v_from_masters_0_arready;
// value method v_from_masters_0_m_rvalid
output v_from_masters_0_rvalid;
// value method v_from_masters_0_m_rid
output [3 : 0] v_from_masters_0_rid;
// value method v_from_masters_0_m_rdata
output [63 : 0] v_from_masters_0_rdata;
// value method v_from_masters_0_m_rresp
output [1 : 0] v_from_masters_0_rresp;
// value method v_from_masters_0_m_rlast
output v_from_masters_0_rlast;
// value method v_from_masters_0_m_ruser
// action method v_from_masters_0_m_rready
input v_from_masters_0_rready;
// action method v_from_masters_1_m_awvalid
input v_from_masters_1_awvalid;
input [3 : 0] v_from_masters_1_awid;
input [63 : 0] v_from_masters_1_awaddr;
input [7 : 0] v_from_masters_1_awlen;
input [2 : 0] v_from_masters_1_awsize;
input [1 : 0] v_from_masters_1_awburst;
input v_from_masters_1_awlock;
input [3 : 0] v_from_masters_1_awcache;
input [2 : 0] v_from_masters_1_awprot;
input [3 : 0] v_from_masters_1_awqos;
input [3 : 0] v_from_masters_1_awregion;
// value method v_from_masters_1_m_awready
output v_from_masters_1_awready;
// action method v_from_masters_1_m_wvalid
input v_from_masters_1_wvalid;
input [63 : 0] v_from_masters_1_wdata;
input [7 : 0] v_from_masters_1_wstrb;
input v_from_masters_1_wlast;
// value method v_from_masters_1_m_wready
output v_from_masters_1_wready;
// value method v_from_masters_1_m_bvalid
output v_from_masters_1_bvalid;
// value method v_from_masters_1_m_bid
output [3 : 0] v_from_masters_1_bid;
// value method v_from_masters_1_m_bresp
output [1 : 0] v_from_masters_1_bresp;
// value method v_from_masters_1_m_buser
// action method v_from_masters_1_m_bready
input v_from_masters_1_bready;
// action method v_from_masters_1_m_arvalid
input v_from_masters_1_arvalid;
input [3 : 0] v_from_masters_1_arid;
input [63 : 0] v_from_masters_1_araddr;
input [7 : 0] v_from_masters_1_arlen;
input [2 : 0] v_from_masters_1_arsize;
input [1 : 0] v_from_masters_1_arburst;
input v_from_masters_1_arlock;
input [3 : 0] v_from_masters_1_arcache;
input [2 : 0] v_from_masters_1_arprot;
input [3 : 0] v_from_masters_1_arqos;
input [3 : 0] v_from_masters_1_arregion;
// value method v_from_masters_1_m_arready
output v_from_masters_1_arready;
// value method v_from_masters_1_m_rvalid
output v_from_masters_1_rvalid;
// value method v_from_masters_1_m_rid
output [3 : 0] v_from_masters_1_rid;
// value method v_from_masters_1_m_rdata
output [63 : 0] v_from_masters_1_rdata;
// value method v_from_masters_1_m_rresp
output [1 : 0] v_from_masters_1_rresp;
// value method v_from_masters_1_m_rlast
output v_from_masters_1_rlast;
// value method v_from_masters_1_m_ruser
// action method v_from_masters_1_m_rready
input v_from_masters_1_rready;
// value method v_to_slaves_0_m_awvalid
output v_to_slaves_0_awvalid;
// value method v_to_slaves_0_m_awid
output [3 : 0] v_to_slaves_0_awid;
// value method v_to_slaves_0_m_awaddr
output [63 : 0] v_to_slaves_0_awaddr;
// value method v_to_slaves_0_m_awlen
output [7 : 0] v_to_slaves_0_awlen;
// value method v_to_slaves_0_m_awsize
output [2 : 0] v_to_slaves_0_awsize;
// value method v_to_slaves_0_m_awburst
output [1 : 0] v_to_slaves_0_awburst;
// value method v_to_slaves_0_m_awlock
output v_to_slaves_0_awlock;
// value method v_to_slaves_0_m_awcache
output [3 : 0] v_to_slaves_0_awcache;
// value method v_to_slaves_0_m_awprot
output [2 : 0] v_to_slaves_0_awprot;
// value method v_to_slaves_0_m_awqos
output [3 : 0] v_to_slaves_0_awqos;
// value method v_to_slaves_0_m_awregion
output [3 : 0] v_to_slaves_0_awregion;
// value method v_to_slaves_0_m_awuser
// action method v_to_slaves_0_m_awready
input v_to_slaves_0_awready;
// value method v_to_slaves_0_m_wvalid
output v_to_slaves_0_wvalid;
// value method v_to_slaves_0_m_wdata
output [63 : 0] v_to_slaves_0_wdata;
// value method v_to_slaves_0_m_wstrb
output [7 : 0] v_to_slaves_0_wstrb;
// value method v_to_slaves_0_m_wlast
output v_to_slaves_0_wlast;
// value method v_to_slaves_0_m_wuser
// action method v_to_slaves_0_m_wready
input v_to_slaves_0_wready;
// action method v_to_slaves_0_m_bvalid
input v_to_slaves_0_bvalid;
input [3 : 0] v_to_slaves_0_bid;
input [1 : 0] v_to_slaves_0_bresp;
// value method v_to_slaves_0_m_bready
output v_to_slaves_0_bready;
// value method v_to_slaves_0_m_arvalid
output v_to_slaves_0_arvalid;
// value method v_to_slaves_0_m_arid
output [3 : 0] v_to_slaves_0_arid;
// value method v_to_slaves_0_m_araddr
output [63 : 0] v_to_slaves_0_araddr;
// value method v_to_slaves_0_m_arlen
output [7 : 0] v_to_slaves_0_arlen;
// value method v_to_slaves_0_m_arsize
output [2 : 0] v_to_slaves_0_arsize;
// value method v_to_slaves_0_m_arburst
output [1 : 0] v_to_slaves_0_arburst;
// value method v_to_slaves_0_m_arlock
output v_to_slaves_0_arlock;
// value method v_to_slaves_0_m_arcache
output [3 : 0] v_to_slaves_0_arcache;
// value method v_to_slaves_0_m_arprot
output [2 : 0] v_to_slaves_0_arprot;
// value method v_to_slaves_0_m_arqos
output [3 : 0] v_to_slaves_0_arqos;
// value method v_to_slaves_0_m_arregion
output [3 : 0] v_to_slaves_0_arregion;
// value method v_to_slaves_0_m_aruser
// action method v_to_slaves_0_m_arready
input v_to_slaves_0_arready;
// action method v_to_slaves_0_m_rvalid
input v_to_slaves_0_rvalid;
input [3 : 0] v_to_slaves_0_rid;
input [63 : 0] v_to_slaves_0_rdata;
input [1 : 0] v_to_slaves_0_rresp;
input v_to_slaves_0_rlast;
// value method v_to_slaves_0_m_rready
output v_to_slaves_0_rready;
// value method v_to_slaves_1_m_awvalid
output v_to_slaves_1_awvalid;
// value method v_to_slaves_1_m_awid
output [3 : 0] v_to_slaves_1_awid;
// value method v_to_slaves_1_m_awaddr
output [63 : 0] v_to_slaves_1_awaddr;
// value method v_to_slaves_1_m_awlen
output [7 : 0] v_to_slaves_1_awlen;
// value method v_to_slaves_1_m_awsize
output [2 : 0] v_to_slaves_1_awsize;
// value method v_to_slaves_1_m_awburst
output [1 : 0] v_to_slaves_1_awburst;
// value method v_to_slaves_1_m_awlock
output v_to_slaves_1_awlock;
// value method v_to_slaves_1_m_awcache
output [3 : 0] v_to_slaves_1_awcache;
// value method v_to_slaves_1_m_awprot
output [2 : 0] v_to_slaves_1_awprot;
// value method v_to_slaves_1_m_awqos
output [3 : 0] v_to_slaves_1_awqos;
// value method v_to_slaves_1_m_awregion
output [3 : 0] v_to_slaves_1_awregion;
// value method v_to_slaves_1_m_awuser
// action method v_to_slaves_1_m_awready
input v_to_slaves_1_awready;
// value method v_to_slaves_1_m_wvalid
output v_to_slaves_1_wvalid;
// value method v_to_slaves_1_m_wdata
output [63 : 0] v_to_slaves_1_wdata;
// value method v_to_slaves_1_m_wstrb
output [7 : 0] v_to_slaves_1_wstrb;
// value method v_to_slaves_1_m_wlast
output v_to_slaves_1_wlast;
// value method v_to_slaves_1_m_wuser
// action method v_to_slaves_1_m_wready
input v_to_slaves_1_wready;
// action method v_to_slaves_1_m_bvalid
input v_to_slaves_1_bvalid;
input [3 : 0] v_to_slaves_1_bid;
input [1 : 0] v_to_slaves_1_bresp;
// value method v_to_slaves_1_m_bready
output v_to_slaves_1_bready;
// value method v_to_slaves_1_m_arvalid
output v_to_slaves_1_arvalid;
// value method v_to_slaves_1_m_arid
output [3 : 0] v_to_slaves_1_arid;
// value method v_to_slaves_1_m_araddr
output [63 : 0] v_to_slaves_1_araddr;
// value method v_to_slaves_1_m_arlen
output [7 : 0] v_to_slaves_1_arlen;
// value method v_to_slaves_1_m_arsize
output [2 : 0] v_to_slaves_1_arsize;
// value method v_to_slaves_1_m_arburst
output [1 : 0] v_to_slaves_1_arburst;
// value method v_to_slaves_1_m_arlock
output v_to_slaves_1_arlock;
// value method v_to_slaves_1_m_arcache
output [3 : 0] v_to_slaves_1_arcache;
// value method v_to_slaves_1_m_arprot
output [2 : 0] v_to_slaves_1_arprot;
// value method v_to_slaves_1_m_arqos
output [3 : 0] v_to_slaves_1_arqos;
// value method v_to_slaves_1_m_arregion
output [3 : 0] v_to_slaves_1_arregion;
// value method v_to_slaves_1_m_aruser
// action method v_to_slaves_1_m_arready
input v_to_slaves_1_arready;
// action method v_to_slaves_1_m_rvalid
input v_to_slaves_1_rvalid;
input [3 : 0] v_to_slaves_1_rid;
input [63 : 0] v_to_slaves_1_rdata;
input [1 : 0] v_to_slaves_1_rresp;
input v_to_slaves_1_rlast;
// value method v_to_slaves_1_m_rready
output v_to_slaves_1_rready;
// value method v_to_slaves_2_m_awvalid
output v_to_slaves_2_awvalid;
// value method v_to_slaves_2_m_awid
output [3 : 0] v_to_slaves_2_awid;
// value method v_to_slaves_2_m_awaddr
output [63 : 0] v_to_slaves_2_awaddr;
// value method v_to_slaves_2_m_awlen
output [7 : 0] v_to_slaves_2_awlen;
// value method v_to_slaves_2_m_awsize
output [2 : 0] v_to_slaves_2_awsize;
// value method v_to_slaves_2_m_awburst
output [1 : 0] v_to_slaves_2_awburst;
// value method v_to_slaves_2_m_awlock
output v_to_slaves_2_awlock;
// value method v_to_slaves_2_m_awcache
output [3 : 0] v_to_slaves_2_awcache;
// value method v_to_slaves_2_m_awprot
output [2 : 0] v_to_slaves_2_awprot;
// value method v_to_slaves_2_m_awqos
output [3 : 0] v_to_slaves_2_awqos;
// value method v_to_slaves_2_m_awregion
output [3 : 0] v_to_slaves_2_awregion;
// value method v_to_slaves_2_m_awuser
// action method v_to_slaves_2_m_awready
input v_to_slaves_2_awready;
// value method v_to_slaves_2_m_wvalid
output v_to_slaves_2_wvalid;
// value method v_to_slaves_2_m_wdata
output [63 : 0] v_to_slaves_2_wdata;
// value method v_to_slaves_2_m_wstrb
output [7 : 0] v_to_slaves_2_wstrb;
// value method v_to_slaves_2_m_wlast
output v_to_slaves_2_wlast;
// value method v_to_slaves_2_m_wuser
// action method v_to_slaves_2_m_wready
input v_to_slaves_2_wready;
// action method v_to_slaves_2_m_bvalid
input v_to_slaves_2_bvalid;
input [3 : 0] v_to_slaves_2_bid;
input [1 : 0] v_to_slaves_2_bresp;
// value method v_to_slaves_2_m_bready
output v_to_slaves_2_bready;
// value method v_to_slaves_2_m_arvalid
output v_to_slaves_2_arvalid;
// value method v_to_slaves_2_m_arid
output [3 : 0] v_to_slaves_2_arid;
// value method v_to_slaves_2_m_araddr
output [63 : 0] v_to_slaves_2_araddr;
// value method v_to_slaves_2_m_arlen
output [7 : 0] v_to_slaves_2_arlen;
// value method v_to_slaves_2_m_arsize
output [2 : 0] v_to_slaves_2_arsize;
// value method v_to_slaves_2_m_arburst
output [1 : 0] v_to_slaves_2_arburst;
// value method v_to_slaves_2_m_arlock
output v_to_slaves_2_arlock;
// value method v_to_slaves_2_m_arcache
output [3 : 0] v_to_slaves_2_arcache;
// value method v_to_slaves_2_m_arprot
output [2 : 0] v_to_slaves_2_arprot;
// value method v_to_slaves_2_m_arqos
output [3 : 0] v_to_slaves_2_arqos;
// value method v_to_slaves_2_m_arregion
output [3 : 0] v_to_slaves_2_arregion;
// value method v_to_slaves_2_m_aruser
// action method v_to_slaves_2_m_arready
input v_to_slaves_2_arready;
// action method v_to_slaves_2_m_rvalid
input v_to_slaves_2_rvalid;
input [3 : 0] v_to_slaves_2_rid;
input [63 : 0] v_to_slaves_2_rdata;
input [1 : 0] v_to_slaves_2_rresp;
input v_to_slaves_2_rlast;
// value method v_to_slaves_2_m_rready
output v_to_slaves_2_rready;
// signals for module outputs
wire [63 : 0] v_from_masters_0_rdata,
v_from_masters_1_rdata,
v_to_slaves_0_araddr,
v_to_slaves_0_awaddr,
v_to_slaves_0_wdata,
v_to_slaves_1_araddr,
v_to_slaves_1_awaddr,
v_to_slaves_1_wdata,
v_to_slaves_2_araddr,
v_to_slaves_2_awaddr,
v_to_slaves_2_wdata;
wire [7 : 0] v_to_slaves_0_arlen,
v_to_slaves_0_awlen,
v_to_slaves_0_wstrb,
v_to_slaves_1_arlen,
v_to_slaves_1_awlen,
v_to_slaves_1_wstrb,
v_to_slaves_2_arlen,
v_to_slaves_2_awlen,
v_to_slaves_2_wstrb;
wire [3 : 0] v_from_masters_0_bid,
v_from_masters_0_rid,
v_from_masters_1_bid,
v_from_masters_1_rid,
v_to_slaves_0_arcache,
v_to_slaves_0_arid,
v_to_slaves_0_arqos,
v_to_slaves_0_arregion,
v_to_slaves_0_awcache,
v_to_slaves_0_awid,
v_to_slaves_0_awqos,
v_to_slaves_0_awregion,
v_to_slaves_1_arcache,
v_to_slaves_1_arid,
v_to_slaves_1_arqos,
v_to_slaves_1_arregion,
v_to_slaves_1_awcache,
v_to_slaves_1_awid,
v_to_slaves_1_awqos,
v_to_slaves_1_awregion,
v_to_slaves_2_arcache,
v_to_slaves_2_arid,
v_to_slaves_2_arqos,
v_to_slaves_2_arregion,
v_to_slaves_2_awcache,
v_to_slaves_2_awid,
v_to_slaves_2_awqos,
v_to_slaves_2_awregion;
wire [2 : 0] v_to_slaves_0_arprot,
v_to_slaves_0_arsize,
v_to_slaves_0_awprot,
v_to_slaves_0_awsize,
v_to_slaves_1_arprot,
v_to_slaves_1_arsize,
v_to_slaves_1_awprot,
v_to_slaves_1_awsize,
v_to_slaves_2_arprot,
v_to_slaves_2_arsize,
v_to_slaves_2_awprot,
v_to_slaves_2_awsize;
wire [1 : 0] v_from_masters_0_bresp,
v_from_masters_0_rresp,
v_from_masters_1_bresp,
v_from_masters_1_rresp,
v_to_slaves_0_arburst,
v_to_slaves_0_awburst,
v_to_slaves_1_arburst,
v_to_slaves_1_awburst,
v_to_slaves_2_arburst,
v_to_slaves_2_awburst;
wire RDY_reset,
RDY_set_verbosity,
v_from_masters_0_arready,
v_from_masters_0_awready,
v_from_masters_0_bvalid,
v_from_masters_0_rlast,
v_from_masters_0_rvalid,
v_from_masters_0_wready,
v_from_masters_1_arready,
v_from_masters_1_awready,
v_from_masters_1_bvalid,
v_from_masters_1_rlast,
v_from_masters_1_rvalid,
v_from_masters_1_wready,
v_to_slaves_0_arlock,
v_to_slaves_0_arvalid,
v_to_slaves_0_awlock,
v_to_slaves_0_awvalid,
v_to_slaves_0_bready,
v_to_slaves_0_rready,
v_to_slaves_0_wlast,
v_to_slaves_0_wvalid,
v_to_slaves_1_arlock,
v_to_slaves_1_arvalid,
v_to_slaves_1_awlock,
v_to_slaves_1_awvalid,
v_to_slaves_1_bready,
v_to_slaves_1_rready,
v_to_slaves_1_wlast,
v_to_slaves_1_wvalid,
v_to_slaves_2_arlock,
v_to_slaves_2_arvalid,
v_to_slaves_2_awlock,
v_to_slaves_2_awvalid,
v_to_slaves_2_bready,
v_to_slaves_2_rready,
v_to_slaves_2_wlast,
v_to_slaves_2_wvalid;
// register fabric_cfg_verbosity
reg [3 : 0] fabric_cfg_verbosity;
wire [3 : 0] fabric_cfg_verbosity$D_IN;
wire fabric_cfg_verbosity$EN;
// register fabric_rg_reset
reg fabric_rg_reset;
wire fabric_rg_reset$D_IN, fabric_rg_reset$EN;
// register fabric_v_rg_r_beat_count_0
reg [7 : 0] fabric_v_rg_r_beat_count_0;
reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN;
wire fabric_v_rg_r_beat_count_0$EN;
// register fabric_v_rg_r_beat_count_1
reg [7 : 0] fabric_v_rg_r_beat_count_1;
reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN;
wire fabric_v_rg_r_beat_count_1$EN;
// register fabric_v_rg_r_beat_count_2
reg [7 : 0] fabric_v_rg_r_beat_count_2;
reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN;
wire fabric_v_rg_r_beat_count_2$EN;
// register fabric_v_rg_r_err_beat_count_0
reg [7 : 0] fabric_v_rg_r_err_beat_count_0;
wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN;
wire fabric_v_rg_r_err_beat_count_0$EN;
// register fabric_v_rg_r_err_beat_count_1
reg [7 : 0] fabric_v_rg_r_err_beat_count_1;
wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN;
wire fabric_v_rg_r_err_beat_count_1$EN;
// register fabric_v_rg_wd_beat_count_0
reg [7 : 0] fabric_v_rg_wd_beat_count_0;
wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN;
wire fabric_v_rg_wd_beat_count_0$EN;
// register fabric_v_rg_wd_beat_count_1
reg [7 : 0] fabric_v_rg_wd_beat_count_1;
wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN;
wire fabric_v_rg_wd_beat_count_1$EN;
// ports of submodule fabric_v_f_rd_err_info_0
wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT;
wire fabric_v_f_rd_err_info_0$CLR,
fabric_v_f_rd_err_info_0$DEQ,
fabric_v_f_rd_err_info_0$EMPTY_N,
fabric_v_f_rd_err_info_0$ENQ;
// ports of submodule fabric_v_f_rd_err_info_1
wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT;
wire fabric_v_f_rd_err_info_1$CLR,
fabric_v_f_rd_err_info_1$DEQ,
fabric_v_f_rd_err_info_1$EMPTY_N,
fabric_v_f_rd_err_info_1$ENQ;
// ports of submodule fabric_v_f_rd_mis_0
wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT;
wire fabric_v_f_rd_mis_0$CLR,
fabric_v_f_rd_mis_0$DEQ,
fabric_v_f_rd_mis_0$EMPTY_N,
fabric_v_f_rd_mis_0$ENQ,
fabric_v_f_rd_mis_0$FULL_N;
// ports of submodule fabric_v_f_rd_mis_1
wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT;
wire fabric_v_f_rd_mis_1$CLR,
fabric_v_f_rd_mis_1$DEQ,
fabric_v_f_rd_mis_1$EMPTY_N,
fabric_v_f_rd_mis_1$ENQ,
fabric_v_f_rd_mis_1$FULL_N;
// ports of submodule fabric_v_f_rd_mis_2
wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT;
wire fabric_v_f_rd_mis_2$CLR,
fabric_v_f_rd_mis_2$DEQ,
fabric_v_f_rd_mis_2$EMPTY_N,
fabric_v_f_rd_mis_2$ENQ,
fabric_v_f_rd_mis_2$FULL_N;
// ports of submodule fabric_v_f_rd_sjs_0
reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN;
wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT;
wire fabric_v_f_rd_sjs_0$CLR,
fabric_v_f_rd_sjs_0$DEQ,
fabric_v_f_rd_sjs_0$EMPTY_N,
fabric_v_f_rd_sjs_0$ENQ,
fabric_v_f_rd_sjs_0$FULL_N;
// ports of submodule fabric_v_f_rd_sjs_1
reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN;
wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT;
wire fabric_v_f_rd_sjs_1$CLR,
fabric_v_f_rd_sjs_1$DEQ,
fabric_v_f_rd_sjs_1$EMPTY_N,
fabric_v_f_rd_sjs_1$ENQ,
fabric_v_f_rd_sjs_1$FULL_N;
// ports of submodule fabric_v_f_wd_tasks_0
reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN;
wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT;
wire fabric_v_f_wd_tasks_0$CLR,
fabric_v_f_wd_tasks_0$DEQ,
fabric_v_f_wd_tasks_0$EMPTY_N,
fabric_v_f_wd_tasks_0$ENQ,
fabric_v_f_wd_tasks_0$FULL_N;
// ports of submodule fabric_v_f_wd_tasks_1
reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN;
wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT;
wire fabric_v_f_wd_tasks_1$CLR,
fabric_v_f_wd_tasks_1$DEQ,
fabric_v_f_wd_tasks_1$EMPTY_N,
fabric_v_f_wd_tasks_1$ENQ,
fabric_v_f_wd_tasks_1$FULL_N;
// ports of submodule fabric_v_f_wr_err_info_0
wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT;
wire fabric_v_f_wr_err_info_0$CLR,
fabric_v_f_wr_err_info_0$DEQ,
fabric_v_f_wr_err_info_0$EMPTY_N,
fabric_v_f_wr_err_info_0$ENQ;
// ports of submodule fabric_v_f_wr_err_info_1
wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT;
wire fabric_v_f_wr_err_info_1$CLR,
fabric_v_f_wr_err_info_1$DEQ,
fabric_v_f_wr_err_info_1$EMPTY_N,
fabric_v_f_wr_err_info_1$ENQ;
// ports of submodule fabric_v_f_wr_mis_0
wire fabric_v_f_wr_mis_0$CLR,
fabric_v_f_wr_mis_0$DEQ,
fabric_v_f_wr_mis_0$D_IN,
fabric_v_f_wr_mis_0$D_OUT,
fabric_v_f_wr_mis_0$EMPTY_N,
fabric_v_f_wr_mis_0$ENQ,
fabric_v_f_wr_mis_0$FULL_N;
// ports of submodule fabric_v_f_wr_mis_1
wire fabric_v_f_wr_mis_1$CLR,
fabric_v_f_wr_mis_1$DEQ,
fabric_v_f_wr_mis_1$D_IN,
fabric_v_f_wr_mis_1$D_OUT,
fabric_v_f_wr_mis_1$EMPTY_N,
fabric_v_f_wr_mis_1$ENQ,
fabric_v_f_wr_mis_1$FULL_N;
// ports of submodule fabric_v_f_wr_mis_2
wire fabric_v_f_wr_mis_2$CLR,
fabric_v_f_wr_mis_2$DEQ,
fabric_v_f_wr_mis_2$D_IN,
fabric_v_f_wr_mis_2$D_OUT,
fabric_v_f_wr_mis_2$EMPTY_N,
fabric_v_f_wr_mis_2$ENQ,
fabric_v_f_wr_mis_2$FULL_N;
// ports of submodule fabric_v_f_wr_sjs_0
reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN;
wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT;
wire fabric_v_f_wr_sjs_0$CLR,
fabric_v_f_wr_sjs_0$DEQ,
fabric_v_f_wr_sjs_0$EMPTY_N,
fabric_v_f_wr_sjs_0$ENQ,
fabric_v_f_wr_sjs_0$FULL_N;
// ports of submodule fabric_v_f_wr_sjs_1
reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN;
wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT;
wire fabric_v_f_wr_sjs_1$CLR,
fabric_v_f_wr_sjs_1$DEQ,
fabric_v_f_wr_sjs_1$EMPTY_N,
fabric_v_f_wr_sjs_1$ENQ,
fabric_v_f_wr_sjs_1$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_rd_addr
wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN,
fabric_xactors_from_masters_0_f_rd_addr$D_OUT;
wire fabric_xactors_from_masters_0_f_rd_addr$CLR,
fabric_xactors_from_masters_0_f_rd_addr$DEQ,
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N,
fabric_xactors_from_masters_0_f_rd_addr$ENQ,
fabric_xactors_from_masters_0_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_rd_data
reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN;
wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT;
wire fabric_xactors_from_masters_0_f_rd_data$CLR,
fabric_xactors_from_masters_0_f_rd_data$DEQ,
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N,
fabric_xactors_from_masters_0_f_rd_data$ENQ,
fabric_xactors_from_masters_0_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_addr
wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN,
fabric_xactors_from_masters_0_f_wr_addr$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_addr$CLR,
fabric_xactors_from_masters_0_f_wr_addr$DEQ,
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_addr$ENQ,
fabric_xactors_from_masters_0_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_data
wire [72 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN,
fabric_xactors_from_masters_0_f_wr_data$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_data$CLR,
fabric_xactors_from_masters_0_f_wr_data$DEQ,
fabric_xactors_from_masters_0_f_wr_data$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_data$ENQ,
fabric_xactors_from_masters_0_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_resp
reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN;
wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_resp$CLR,
fabric_xactors_from_masters_0_f_wr_resp$DEQ,
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_resp$ENQ,
fabric_xactors_from_masters_0_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_rd_addr
wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN,
fabric_xactors_from_masters_1_f_rd_addr$D_OUT;
wire fabric_xactors_from_masters_1_f_rd_addr$CLR,
fabric_xactors_from_masters_1_f_rd_addr$DEQ,
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N,
fabric_xactors_from_masters_1_f_rd_addr$ENQ,
fabric_xactors_from_masters_1_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_rd_data
reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN;
wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT;
wire fabric_xactors_from_masters_1_f_rd_data$CLR,
fabric_xactors_from_masters_1_f_rd_data$DEQ,
fabric_xactors_from_masters_1_f_rd_data$EMPTY_N,
fabric_xactors_from_masters_1_f_rd_data$ENQ,
fabric_xactors_from_masters_1_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_wr_addr
wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN,
fabric_xactors_from_masters_1_f_wr_addr$D_OUT;
wire fabric_xactors_from_masters_1_f_wr_addr$CLR,
fabric_xactors_from_masters_1_f_wr_addr$DEQ,
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N,
fabric_xactors_from_masters_1_f_wr_addr$ENQ,
fabric_xactors_from_masters_1_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_wr_data
wire [72 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN,
fabric_xactors_from_masters_1_f_wr_data$D_OUT;
wire fabric_xactors_from_masters_1_f_wr_data$CLR,
fabric_xactors_from_masters_1_f_wr_data$DEQ,
fabric_xactors_from_masters_1_f_wr_data$EMPTY_N,
fabric_xactors_from_masters_1_f_wr_data$ENQ,
fabric_xactors_from_masters_1_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_wr_resp
reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN;
wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT;
wire fabric_xactors_from_masters_1_f_wr_resp$CLR,
fabric_xactors_from_masters_1_f_wr_resp$DEQ,
fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N,
fabric_xactors_from_masters_1_f_wr_resp$ENQ,
fabric_xactors_from_masters_1_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_rd_addr
wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN,
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_0_f_rd_addr$CLR,
fabric_xactors_to_slaves_0_f_rd_addr$DEQ,
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_0_f_rd_addr$ENQ,
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_rd_data
wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN,
fabric_xactors_to_slaves_0_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_0_f_rd_data$CLR,
fabric_xactors_to_slaves_0_f_rd_data$DEQ,
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_0_f_rd_data$ENQ,
fabric_xactors_to_slaves_0_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_addr
wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN,
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_addr$CLR,
fabric_xactors_to_slaves_0_f_wr_addr$DEQ,
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_addr$ENQ,
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN,
fabric_xactors_to_slaves_0_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_data$CLR,
fabric_xactors_to_slaves_0_f_wr_data$DEQ,
fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_data$ENQ,
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_resp
wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN,
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_resp$CLR,
fabric_xactors_to_slaves_0_f_wr_resp$DEQ,
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_resp$ENQ,
fabric_xactors_to_slaves_0_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_rd_addr
wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN,
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_1_f_rd_addr$CLR,
fabric_xactors_to_slaves_1_f_rd_addr$DEQ,
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_1_f_rd_addr$ENQ,
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_rd_data
wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN,
fabric_xactors_to_slaves_1_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_1_f_rd_data$CLR,
fabric_xactors_to_slaves_1_f_rd_data$DEQ,
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_1_f_rd_data$ENQ,
fabric_xactors_to_slaves_1_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_addr
wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN,
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_addr$CLR,
fabric_xactors_to_slaves_1_f_wr_addr$DEQ,
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_addr$ENQ,
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN,
fabric_xactors_to_slaves_1_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_data$CLR,
fabric_xactors_to_slaves_1_f_wr_data$DEQ,
fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_data$ENQ,
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_resp
wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN,
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_resp$CLR,
fabric_xactors_to_slaves_1_f_wr_resp$DEQ,
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_resp$ENQ,
fabric_xactors_to_slaves_1_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_rd_addr
wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN,
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_2_f_rd_addr$CLR,
fabric_xactors_to_slaves_2_f_rd_addr$DEQ,
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_2_f_rd_addr$ENQ,
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_rd_data
wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN,
fabric_xactors_to_slaves_2_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_2_f_rd_data$CLR,
fabric_xactors_to_slaves_2_f_rd_data$DEQ,
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_2_f_rd_data$ENQ,
fabric_xactors_to_slaves_2_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_addr
wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN,
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_addr$CLR,
fabric_xactors_to_slaves_2_f_wr_addr$DEQ,
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_addr$ENQ,
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN,
fabric_xactors_to_slaves_2_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_data$CLR,
fabric_xactors_to_slaves_2_f_wr_data$DEQ,
fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_data$ENQ,
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_resp
wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN,
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_resp$CLR,
fabric_xactors_to_slaves_2_f_wr_resp$DEQ,
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_resp$ENQ,
fabric_xactors_to_slaves_2_f_wr_resp$FULL_N;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr,
soc_map$m_near_mem_io_addr_base,
soc_map$m_near_mem_io_addr_lim,
soc_map$m_plic_addr_base,
soc_map$m_plic_addr_lim;
// rule scheduling signals
wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master,
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5,
CAN_FIRE_RL_fabric_rl_reset,
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master,
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1,
CAN_FIRE_reset,
CAN_FIRE_set_verbosity,
CAN_FIRE_v_from_masters_0_m_arvalid,
CAN_FIRE_v_from_masters_0_m_awvalid,
CAN_FIRE_v_from_masters_0_m_bready,
CAN_FIRE_v_from_masters_0_m_rready,
CAN_FIRE_v_from_masters_0_m_wvalid,
CAN_FIRE_v_from_masters_1_m_arvalid,
CAN_FIRE_v_from_masters_1_m_awvalid,
CAN_FIRE_v_from_masters_1_m_bready,
CAN_FIRE_v_from_masters_1_m_rready,
CAN_FIRE_v_from_masters_1_m_wvalid,
CAN_FIRE_v_to_slaves_0_m_arready,
CAN_FIRE_v_to_slaves_0_m_awready,
CAN_FIRE_v_to_slaves_0_m_bvalid,
CAN_FIRE_v_to_slaves_0_m_rvalid,
CAN_FIRE_v_to_slaves_0_m_wready,
CAN_FIRE_v_to_slaves_1_m_arready,
CAN_FIRE_v_to_slaves_1_m_awready,
CAN_FIRE_v_to_slaves_1_m_bvalid,
CAN_FIRE_v_to_slaves_1_m_rvalid,
CAN_FIRE_v_to_slaves_1_m_wready,
CAN_FIRE_v_to_slaves_2_m_arready,
CAN_FIRE_v_to_slaves_2_m_awready,
CAN_FIRE_v_to_slaves_2_m_bvalid,
CAN_FIRE_v_to_slaves_2_m_rvalid,
CAN_FIRE_v_to_slaves_2_m_wready,
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master,
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5,
WILL_FIRE_RL_fabric_rl_reset,
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master,
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1,
WILL_FIRE_reset,
WILL_FIRE_set_verbosity,
WILL_FIRE_v_from_masters_0_m_arvalid,
WILL_FIRE_v_from_masters_0_m_awvalid,
WILL_FIRE_v_from_masters_0_m_bready,
WILL_FIRE_v_from_masters_0_m_rready,
WILL_FIRE_v_from_masters_0_m_wvalid,
WILL_FIRE_v_from_masters_1_m_arvalid,
WILL_FIRE_v_from_masters_1_m_awvalid,
WILL_FIRE_v_from_masters_1_m_bready,
WILL_FIRE_v_from_masters_1_m_rready,
WILL_FIRE_v_from_masters_1_m_wvalid,
WILL_FIRE_v_to_slaves_0_m_arready,
WILL_FIRE_v_to_slaves_0_m_awready,
WILL_FIRE_v_to_slaves_0_m_bvalid,
WILL_FIRE_v_to_slaves_0_m_rvalid,
WILL_FIRE_v_to_slaves_0_m_wready,
WILL_FIRE_v_to_slaves_1_m_arready,
WILL_FIRE_v_to_slaves_1_m_awready,
WILL_FIRE_v_to_slaves_1_m_bvalid,
WILL_FIRE_v_to_slaves_1_m_rvalid,
WILL_FIRE_v_to_slaves_1_m_wready,
WILL_FIRE_v_to_slaves_2_m_arready,
WILL_FIRE_v_to_slaves_2_m_awready,
WILL_FIRE_v_to_slaves_2_m_bvalid,
WILL_FIRE_v_to_slaves_2_m_rvalid,
WILL_FIRE_v_to_slaves_2_m_wready;
// inputs to muxes for submodule ports
wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4,
MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4;
wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3;
wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1,
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2;
wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2,
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2,
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2,
MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2,
MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2;
wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4,
MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4;
wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1,
MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1,
MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h8688;
reg [31 : 0] v__h9063;
reg [31 : 0] v__h9438;
reg [31 : 0] v__h9883;
reg [31 : 0] v__h10252;
reg [31 : 0] v__h10621;
reg [31 : 0] v__h11780;
reg [31 : 0] v__h12243;
reg [31 : 0] v__h12618;
reg [31 : 0] v__h12910;
reg [31 : 0] v__h13202;
reg [31 : 0] v__h13505;
reg [31 : 0] v__h13771;
reg [31 : 0] v__h14037;
reg [31 : 0] v__h14301;
reg [31 : 0] v__h14527;
reg [31 : 0] v__h14956;
reg [31 : 0] v__h15312;
reg [31 : 0] v__h15668;
reg [31 : 0] v__h16085;
reg [31 : 0] v__h16417;
reg [31 : 0] v__h16749;
reg [31 : 0] v__h17765;
reg [31 : 0] v__h18016;
reg [31 : 0] v__h18391;
reg [31 : 0] v__h18632;
reg [31 : 0] v__h19007;
reg [31 : 0] v__h19248;
reg [31 : 0] v__h19610;
reg [31 : 0] v__h19861;
reg [31 : 0] v__h20191;
reg [31 : 0] v__h20432;
reg [31 : 0] v__h20762;
reg [31 : 0] v__h21003;
reg [31 : 0] v__h21516;
reg [31 : 0] v__h21917;
reg [31 : 0] v__h5717;
reg [31 : 0] v__h5711;
reg [31 : 0] v__h8682;
reg [31 : 0] v__h9057;
reg [31 : 0] v__h9432;
reg [31 : 0] v__h9877;
reg [31 : 0] v__h10246;
reg [31 : 0] v__h10615;
reg [31 : 0] v__h11774;
reg [31 : 0] v__h12237;
reg [31 : 0] v__h12612;
reg [31 : 0] v__h12904;
reg [31 : 0] v__h13196;
reg [31 : 0] v__h13499;
reg [31 : 0] v__h13765;
reg [31 : 0] v__h14031;
reg [31 : 0] v__h14295;
reg [31 : 0] v__h14521;
reg [31 : 0] v__h14950;
reg [31 : 0] v__h15306;
reg [31 : 0] v__h15662;
reg [31 : 0] v__h16079;
reg [31 : 0] v__h16411;
reg [31 : 0] v__h16743;
reg [31 : 0] v__h17759;
reg [31 : 0] v__h18010;
reg [31 : 0] v__h18385;
reg [31 : 0] v__h18626;
reg [31 : 0] v__h19001;
reg [31 : 0] v__h19242;
reg [31 : 0] v__h19604;
reg [31 : 0] v__h19855;
reg [31 : 0] v__h20185;
reg [31 : 0] v__h20426;
reg [31 : 0] v__h20756;
reg [31 : 0] v__h20997;
reg [31 : 0] v__h21510;
reg [31 : 0] v__h21911;
// synopsys translate_on
// remaining internal signals
reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1,
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2;
wire [7 : 0] x__h11685,
x__h12148,
x__h17902,
x__h18528,
x__h19144,
x__h21448,
x__h21849;
wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396,
IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435,
IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474,
x1_avValue_rresp__h17880,
x1_avValue_rresp__h18506,
x1_avValue_rresp__h19122;
wire _dor1fabric_v_f_rd_mis_0$EN_deq,
_dor1fabric_v_f_rd_mis_1$EN_deq,
_dor1fabric_v_f_rd_mis_2$EN_deq,
fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130,
fabric_v_f_wd_tasks_1_i_notEmpty__49_AND_fabri_ETC___d155,
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369,
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409,
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448,
fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520,
fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538,
fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138,
fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29,
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325,
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330,
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83,
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88,
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19,
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d273,
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d323,
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81,
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26,
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d278,
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d328,
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d86;
// action method reset
assign RDY_reset = !fabric_rg_reset ;
assign CAN_FIRE_reset = !fabric_rg_reset ;
assign WILL_FIRE_reset = EN_reset ;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method v_from_masters_0_m_awvalid
assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ;
// value method v_from_masters_0_m_awready
assign v_from_masters_0_awready =
fabric_xactors_from_masters_0_f_wr_addr$FULL_N ;
// action method v_from_masters_0_m_wvalid
assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ;
// value method v_from_masters_0_m_wready
assign v_from_masters_0_wready =
fabric_xactors_from_masters_0_f_wr_data$FULL_N ;
// value method v_from_masters_0_m_bvalid
assign v_from_masters_0_bvalid =
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ;
// value method v_from_masters_0_m_bid
assign v_from_masters_0_bid =
fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ;
// value method v_from_masters_0_m_bresp
assign v_from_masters_0_bresp =
fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ;
// action method v_from_masters_0_m_bready
assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ;
// action method v_from_masters_0_m_arvalid
assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ;
// value method v_from_masters_0_m_arready
assign v_from_masters_0_arready =
fabric_xactors_from_masters_0_f_rd_addr$FULL_N ;
// value method v_from_masters_0_m_rvalid
assign v_from_masters_0_rvalid =
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ;
// value method v_from_masters_0_m_rid
assign v_from_masters_0_rid =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ;
// value method v_from_masters_0_m_rdata
assign v_from_masters_0_rdata =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ;
// value method v_from_masters_0_m_rresp
assign v_from_masters_0_rresp =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ;
// value method v_from_masters_0_m_rlast
assign v_from_masters_0_rlast =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ;
// action method v_from_masters_0_m_rready
assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ;
// action method v_from_masters_1_m_awvalid
assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ;
// value method v_from_masters_1_m_awready
assign v_from_masters_1_awready =
fabric_xactors_from_masters_1_f_wr_addr$FULL_N ;
// action method v_from_masters_1_m_wvalid
assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ;
// value method v_from_masters_1_m_wready
assign v_from_masters_1_wready =
fabric_xactors_from_masters_1_f_wr_data$FULL_N ;
// value method v_from_masters_1_m_bvalid
assign v_from_masters_1_bvalid =
fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ;
// value method v_from_masters_1_m_bid
assign v_from_masters_1_bid =
fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ;
// value method v_from_masters_1_m_bresp
assign v_from_masters_1_bresp =
fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ;
// action method v_from_masters_1_m_bready
assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ;
// action method v_from_masters_1_m_arvalid
assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ;
// value method v_from_masters_1_m_arready
assign v_from_masters_1_arready =
fabric_xactors_from_masters_1_f_rd_addr$FULL_N ;
// value method v_from_masters_1_m_rvalid
assign v_from_masters_1_rvalid =
fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ;
// value method v_from_masters_1_m_rid
assign v_from_masters_1_rid =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ;
// value method v_from_masters_1_m_rdata
assign v_from_masters_1_rdata =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ;
// value method v_from_masters_1_m_rresp
assign v_from_masters_1_rresp =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ;
// value method v_from_masters_1_m_rlast
assign v_from_masters_1_rlast =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ;
// action method v_from_masters_1_m_rready
assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ;
// value method v_to_slaves_0_m_awvalid
assign v_to_slaves_0_awvalid =
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_0_m_awid
assign v_to_slaves_0_awid =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ;
// value method v_to_slaves_0_m_awaddr
assign v_to_slaves_0_awaddr =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_0_m_awlen
assign v_to_slaves_0_awlen =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_0_m_awsize
assign v_to_slaves_0_awsize =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_0_m_awburst
assign v_to_slaves_0_awburst =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_0_m_awlock
assign v_to_slaves_0_awlock =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_0_m_awcache
assign v_to_slaves_0_awcache =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_0_m_awprot
assign v_to_slaves_0_awprot =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_0_m_awqos
assign v_to_slaves_0_awqos =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_0_m_awregion
assign v_to_slaves_0_awregion =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_0_m_awready
assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ;
// value method v_to_slaves_0_m_wvalid
assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ;
// value method v_to_slaves_0_m_wdata
assign v_to_slaves_0_wdata =
fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_0_m_wstrb
assign v_to_slaves_0_wstrb =
fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_0_m_wlast
assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_0_m_wready
assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ;
// action method v_to_slaves_0_m_bvalid
assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ;
// value method v_to_slaves_0_m_bready
assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ;
// value method v_to_slaves_0_m_arvalid
assign v_to_slaves_0_arvalid =
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_0_m_arid
assign v_to_slaves_0_arid =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ;
// value method v_to_slaves_0_m_araddr
assign v_to_slaves_0_araddr =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_0_m_arlen
assign v_to_slaves_0_arlen =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_0_m_arsize
assign v_to_slaves_0_arsize =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_0_m_arburst
assign v_to_slaves_0_arburst =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_0_m_arlock
assign v_to_slaves_0_arlock =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_0_m_arcache
assign v_to_slaves_0_arcache =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_0_m_arprot
assign v_to_slaves_0_arprot =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_0_m_arqos
assign v_to_slaves_0_arqos =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_0_m_arregion
assign v_to_slaves_0_arregion =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_0_m_arready
assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ;
// action method v_to_slaves_0_m_rvalid
assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ;
// value method v_to_slaves_0_m_rready
assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ;
// value method v_to_slaves_1_m_awvalid
assign v_to_slaves_1_awvalid =
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_1_m_awid
assign v_to_slaves_1_awid =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ;
// value method v_to_slaves_1_m_awaddr
assign v_to_slaves_1_awaddr =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_1_m_awlen
assign v_to_slaves_1_awlen =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_1_m_awsize
assign v_to_slaves_1_awsize =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_1_m_awburst
assign v_to_slaves_1_awburst =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_1_m_awlock
assign v_to_slaves_1_awlock =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_1_m_awcache
assign v_to_slaves_1_awcache =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_1_m_awprot
assign v_to_slaves_1_awprot =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_1_m_awqos
assign v_to_slaves_1_awqos =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_1_m_awregion
assign v_to_slaves_1_awregion =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_1_m_awready
assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ;
// value method v_to_slaves_1_m_wvalid
assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ;
// value method v_to_slaves_1_m_wdata
assign v_to_slaves_1_wdata =
fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_1_m_wstrb
assign v_to_slaves_1_wstrb =
fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_1_m_wlast
assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_1_m_wready
assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ;
// action method v_to_slaves_1_m_bvalid
assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ;
// value method v_to_slaves_1_m_bready
assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ;
// value method v_to_slaves_1_m_arvalid
assign v_to_slaves_1_arvalid =
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_1_m_arid
assign v_to_slaves_1_arid =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ;
// value method v_to_slaves_1_m_araddr
assign v_to_slaves_1_araddr =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_1_m_arlen
assign v_to_slaves_1_arlen =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_1_m_arsize
assign v_to_slaves_1_arsize =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_1_m_arburst
assign v_to_slaves_1_arburst =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_1_m_arlock
assign v_to_slaves_1_arlock =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_1_m_arcache
assign v_to_slaves_1_arcache =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_1_m_arprot
assign v_to_slaves_1_arprot =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_1_m_arqos
assign v_to_slaves_1_arqos =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_1_m_arregion
assign v_to_slaves_1_arregion =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_1_m_arready
assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ;
// action method v_to_slaves_1_m_rvalid
assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ;
// value method v_to_slaves_1_m_rready
assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ;
// value method v_to_slaves_2_m_awvalid
assign v_to_slaves_2_awvalid =
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_2_m_awid
assign v_to_slaves_2_awid =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ;
// value method v_to_slaves_2_m_awaddr
assign v_to_slaves_2_awaddr =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_2_m_awlen
assign v_to_slaves_2_awlen =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_2_m_awsize
assign v_to_slaves_2_awsize =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_2_m_awburst
assign v_to_slaves_2_awburst =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_2_m_awlock
assign v_to_slaves_2_awlock =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_2_m_awcache
assign v_to_slaves_2_awcache =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_2_m_awprot
assign v_to_slaves_2_awprot =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_2_m_awqos
assign v_to_slaves_2_awqos =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_2_m_awregion
assign v_to_slaves_2_awregion =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_2_m_awready
assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ;
// value method v_to_slaves_2_m_wvalid
assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ;
// value method v_to_slaves_2_m_wdata
assign v_to_slaves_2_wdata =
fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_2_m_wstrb
assign v_to_slaves_2_wstrb =
fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_2_m_wlast
assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_2_m_wready
assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ;
// action method v_to_slaves_2_m_bvalid
assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ;
// value method v_to_slaves_2_m_bready
assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ;
// value method v_to_slaves_2_m_arvalid
assign v_to_slaves_2_arvalid =
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_2_m_arid
assign v_to_slaves_2_arid =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ;
// value method v_to_slaves_2_m_araddr
assign v_to_slaves_2_araddr =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_2_m_arlen
assign v_to_slaves_2_arlen =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_2_m_arsize
assign v_to_slaves_2_arsize =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_2_m_arburst
assign v_to_slaves_2_arburst =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_2_m_arlock
assign v_to_slaves_2_arlock =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_2_m_arcache
assign v_to_slaves_2_arcache =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_2_m_arprot
assign v_to_slaves_2_arprot =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_2_m_arqos
assign v_to_slaves_2_arqos =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_2_m_arregion
assign v_to_slaves_2_arregion =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_2_m_arready
assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ;
// action method v_to_slaves_2_m_rvalid
assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ;
// value method v_to_slaves_2_m_rready
assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ;
// submodule fabric_v_f_rd_err_info_0
SizedFIFO #(.p1width(32'd12),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_err_info_0$D_IN),
.ENQ(fabric_v_f_rd_err_info_0$ENQ),
.DEQ(fabric_v_f_rd_err_info_0$DEQ),
.CLR(fabric_v_f_rd_err_info_0$CLR),
.D_OUT(fabric_v_f_rd_err_info_0$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N));
// submodule fabric_v_f_rd_err_info_1
SizedFIFO #(.p1width(32'd12),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_err_info_1$D_IN),
.ENQ(fabric_v_f_rd_err_info_1$ENQ),
.DEQ(fabric_v_f_rd_err_info_1$DEQ),
.CLR(fabric_v_f_rd_err_info_1$CLR),
.D_OUT(fabric_v_f_rd_err_info_1$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N));
// submodule fabric_v_f_rd_mis_0
SizedFIFO #(.p1width(32'd9),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_0$D_IN),
.ENQ(fabric_v_f_rd_mis_0$ENQ),
.DEQ(fabric_v_f_rd_mis_0$DEQ),
.CLR(fabric_v_f_rd_mis_0$CLR),
.D_OUT(fabric_v_f_rd_mis_0$D_OUT),
.FULL_N(fabric_v_f_rd_mis_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N));
// submodule fabric_v_f_rd_mis_1
SizedFIFO #(.p1width(32'd9),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_1$D_IN),
.ENQ(fabric_v_f_rd_mis_1$ENQ),
.DEQ(fabric_v_f_rd_mis_1$DEQ),
.CLR(fabric_v_f_rd_mis_1$CLR),
.D_OUT(fabric_v_f_rd_mis_1$D_OUT),
.FULL_N(fabric_v_f_rd_mis_1$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N));
// submodule fabric_v_f_rd_mis_2
SizedFIFO #(.p1width(32'd9),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_2$D_IN),
.ENQ(fabric_v_f_rd_mis_2$ENQ),
.DEQ(fabric_v_f_rd_mis_2$DEQ),
.CLR(fabric_v_f_rd_mis_2$CLR),
.D_OUT(fabric_v_f_rd_mis_2$D_OUT),
.FULL_N(fabric_v_f_rd_mis_2$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N));
// submodule fabric_v_f_rd_sjs_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_sjs_0$D_IN),
.ENQ(fabric_v_f_rd_sjs_0$ENQ),
.DEQ(fabric_v_f_rd_sjs_0$DEQ),
.CLR(fabric_v_f_rd_sjs_0$CLR),
.D_OUT(fabric_v_f_rd_sjs_0$D_OUT),
.FULL_N(fabric_v_f_rd_sjs_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N));
// submodule fabric_v_f_rd_sjs_1
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_sjs_1$D_IN),
.ENQ(fabric_v_f_rd_sjs_1$ENQ),
.DEQ(fabric_v_f_rd_sjs_1$DEQ),
.CLR(fabric_v_f_rd_sjs_1$CLR),
.D_OUT(fabric_v_f_rd_sjs_1$D_OUT),
.FULL_N(fabric_v_f_rd_sjs_1$FULL_N),
.EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N));
// submodule fabric_v_f_wd_tasks_0
FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wd_tasks_0$D_IN),
.ENQ(fabric_v_f_wd_tasks_0$ENQ),
.DEQ(fabric_v_f_wd_tasks_0$DEQ),
.CLR(fabric_v_f_wd_tasks_0$CLR),
.D_OUT(fabric_v_f_wd_tasks_0$D_OUT),
.FULL_N(fabric_v_f_wd_tasks_0$FULL_N),
.EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N));
// submodule fabric_v_f_wd_tasks_1
FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wd_tasks_1$D_IN),
.ENQ(fabric_v_f_wd_tasks_1$ENQ),
.DEQ(fabric_v_f_wd_tasks_1$DEQ),
.CLR(fabric_v_f_wd_tasks_1$CLR),
.D_OUT(fabric_v_f_wd_tasks_1$D_OUT),
.FULL_N(fabric_v_f_wd_tasks_1$FULL_N),
.EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N));
// submodule fabric_v_f_wr_err_info_0
SizedFIFO #(.p1width(32'd4),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_err_info_0$D_IN),
.ENQ(fabric_v_f_wr_err_info_0$ENQ),
.DEQ(fabric_v_f_wr_err_info_0$DEQ),
.CLR(fabric_v_f_wr_err_info_0$CLR),
.D_OUT(fabric_v_f_wr_err_info_0$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N));
// submodule fabric_v_f_wr_err_info_1
SizedFIFO #(.p1width(32'd4),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_err_info_1$D_IN),
.ENQ(fabric_v_f_wr_err_info_1$ENQ),
.DEQ(fabric_v_f_wr_err_info_1$DEQ),
.CLR(fabric_v_f_wr_err_info_1$CLR),
.D_OUT(fabric_v_f_wr_err_info_1$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N));
// submodule fabric_v_f_wr_mis_0
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_0$D_IN),
.ENQ(fabric_v_f_wr_mis_0$ENQ),
.DEQ(fabric_v_f_wr_mis_0$DEQ),
.CLR(fabric_v_f_wr_mis_0$CLR),
.D_OUT(fabric_v_f_wr_mis_0$D_OUT),
.FULL_N(fabric_v_f_wr_mis_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N));
// submodule fabric_v_f_wr_mis_1
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_1$D_IN),
.ENQ(fabric_v_f_wr_mis_1$ENQ),
.DEQ(fabric_v_f_wr_mis_1$DEQ),
.CLR(fabric_v_f_wr_mis_1$CLR),
.D_OUT(fabric_v_f_wr_mis_1$D_OUT),
.FULL_N(fabric_v_f_wr_mis_1$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N));
// submodule fabric_v_f_wr_mis_2
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_2$D_IN),
.ENQ(fabric_v_f_wr_mis_2$ENQ),
.DEQ(fabric_v_f_wr_mis_2$DEQ),
.CLR(fabric_v_f_wr_mis_2$CLR),
.D_OUT(fabric_v_f_wr_mis_2$D_OUT),
.FULL_N(fabric_v_f_wr_mis_2$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N));
// submodule fabric_v_f_wr_sjs_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_sjs_0$D_IN),
.ENQ(fabric_v_f_wr_sjs_0$ENQ),
.DEQ(fabric_v_f_wr_sjs_0$DEQ),
.CLR(fabric_v_f_wr_sjs_0$CLR),
.D_OUT(fabric_v_f_wr_sjs_0$D_OUT),
.FULL_N(fabric_v_f_wr_sjs_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N));
// submodule fabric_v_f_wr_sjs_1
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_sjs_1$D_IN),
.ENQ(fabric_v_f_wr_sjs_1$ENQ),
.DEQ(fabric_v_f_wr_sjs_1$DEQ),
.CLR(fabric_v_f_wr_sjs_1$CLR),
.D_OUT(fabric_v_f_wr_sjs_1$D_OUT),
.FULL_N(fabric_v_f_wr_sjs_1$FULL_N),
.EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ),
.CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ),
.CLR(fabric_xactors_from_masters_0_f_rd_data$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_data$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ),
.CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ),
.CLR(fabric_xactors_from_masters_1_f_rd_data$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ),
.CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ),
.CLR(fabric_xactors_from_masters_1_f_wr_data$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ),
.CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim),
.m_plic_addr_base(soc_map$m_plic_addr_base),
.m_plic_addr_size(),
.m_plic_addr_lim(soc_map$m_plic_addr_lim),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// rule RL_fabric_rl_wr_xaction_master_to_slave
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_mis_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22) &&
(!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29) ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_1
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_1$FULL_N &&
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_2
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_2$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22) &&
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_3
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 =
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_0$FULL_N &&
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) &&
(!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d86 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88) ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_4
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 =
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_1$FULL_N &&
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81 &&
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_5
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 =
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_2$FULL_N &&
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) &&
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d86 &&
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_data
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data =
fabric_xactors_from_masters_0_f_wr_data$EMPTY_N &&
fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_data_1
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 =
fabric_xactors_from_masters_1_f_wr_data$EMPTY_N &&
fabric_v_f_wd_tasks_1_i_notEmpty__49_AND_fabri_ETC___d155 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
// rule RL_fabric_rl_wr_resp_slave_to_master
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master =
fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
!fabric_v_f_wr_mis_0$D_OUT &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
// rule RL_fabric_rl_wr_resp_slave_to_master_1
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N &&
!fabric_v_f_wr_mis_1$D_OUT &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_2
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N &&
!fabric_v_f_wr_mis_2$D_OUT &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_3
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 =
fabric_v_f_wr_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_0$D_OUT &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_4
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 =
fabric_v_f_wr_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_1$D_OUT &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_5
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 =
fabric_v_f_wr_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_2$D_OUT &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ;
// rule RL_fabric_rl_wr_resp_err_to_master
assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_err_info_0$EMPTY_N &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
// rule RL_fabric_rl_wr_resp_err_to_master_1
assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 =
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_err_info_1$EMPTY_N &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_0$FULL_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d273 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275) &&
(!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d278 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280) ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_1
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_1$FULL_N &&
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d273 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_2
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_2$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d273 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275) &&
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d278 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_3
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 =
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_0$FULL_N &&
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d323 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325) &&
(!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d328 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330) ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
!WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_4
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 =
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_1$FULL_N &&
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d323 &&
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
!WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_5
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 =
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_2$FULL_N &&
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d323 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325) &&
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d328 &&
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
!WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_rd_resp_slave_to_master
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master =
fabric_v_f_rd_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
(fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) &&
(!fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 ||
fabric_v_f_rd_sjs_0$EMPTY_N) &&
!fabric_v_f_rd_mis_0$D_OUT[8] &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
// rule RL_fabric_rl_rd_resp_slave_to_master_1
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 =
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N &&
(fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) &&
(!fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 ||
fabric_v_f_rd_sjs_0$EMPTY_N) &&
!fabric_v_f_rd_mis_1$D_OUT[8] &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_2
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 =
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N &&
(fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) &&
(!fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 ||
fabric_v_f_rd_sjs_0$EMPTY_N) &&
!fabric_v_f_rd_mis_2$D_OUT[8] &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_3
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 =
fabric_v_f_rd_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_v_f_rd_mis_0$D_OUT[8] &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_4
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 =
fabric_v_f_rd_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_v_f_rd_mis_1$D_OUT[8] &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_5
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 =
fabric_v_f_rd_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_v_f_rd_mis_2$D_OUT[8] &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ;
// rule RL_fabric_rl_rd_resp_err_to_master
assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master =
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_err_info_0$EMPTY_N &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
// rule RL_fabric_rl_rd_resp_err_to_master_1
assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 =
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_err_info_1$EMPTY_N &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ;
// rule RL_fabric_rl_reset
assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ;
assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ;
// inputs to muxes for submodule ports
assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ;
assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ;
assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ;
assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 =
{ 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 =
{ 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 =
{ 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 =
{ 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 =
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 ?
8'd0 :
x__h17902 ;
assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 =
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 ?
8'd0 :
x__h18528 ;
assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 =
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 ?
8'd0 :
x__h19144 ;
assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 =
fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ?
8'd0 :
x__h11685 ;
assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 =
fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 ?
8'd0 :
x__h12148 ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 =
{ fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3],
IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396,
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 =
{ fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3],
IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435,
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 =
{ fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3],
IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474,
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 =
{ fabric_v_f_rd_err_info_0$D_OUT[3:0],
66'd3,
fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 } ;
assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 =
{ fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ;
assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 =
{ fabric_v_f_rd_err_info_1$D_OUT[3:0],
66'd3,
fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 } ;
assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 =
{ fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ;
// register fabric_cfg_verbosity
assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign fabric_cfg_verbosity$EN = EN_set_verbosity ;
// register fabric_rg_reset
assign fabric_rg_reset$D_IN = !fabric_rg_reset ;
assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ;
// register fabric_v_rg_r_beat_count_0
always@(fabric_rg_reset or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master)
case (1'b1)
fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3:
fabric_v_rg_r_beat_count_0$D_IN =
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master:
fabric_v_rg_r_beat_count_0$D_IN =
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2;
default: fabric_v_rg_r_beat_count_0$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
assign fabric_v_rg_r_beat_count_0$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ||
fabric_rg_reset ;
// register fabric_v_rg_r_beat_count_1
always@(fabric_rg_reset or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1)
case (1'b1)
fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4:
fabric_v_rg_r_beat_count_1$D_IN =
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1:
fabric_v_rg_r_beat_count_1$D_IN =
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2;
default: fabric_v_rg_r_beat_count_1$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
assign fabric_v_rg_r_beat_count_1$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ||
fabric_rg_reset ;
// register fabric_v_rg_r_beat_count_2
always@(fabric_rg_reset or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2)
case (1'b1)
fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5:
fabric_v_rg_r_beat_count_2$D_IN =
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2:
fabric_v_rg_r_beat_count_2$D_IN =
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2;
default: fabric_v_rg_r_beat_count_2$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
assign fabric_v_rg_r_beat_count_2$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ||
fabric_rg_reset ;
// register fabric_v_rg_r_err_beat_count_0
assign fabric_v_rg_r_err_beat_count_0$D_IN =
fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 ?
8'd0 :
x__h21448 ;
assign fabric_v_rg_r_err_beat_count_0$EN =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
// register fabric_v_rg_r_err_beat_count_1
assign fabric_v_rg_r_err_beat_count_1$D_IN =
fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 ?
8'd0 :
x__h21849 ;
assign fabric_v_rg_r_err_beat_count_1$EN =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ;
// register fabric_v_rg_wd_beat_count_0
assign fabric_v_rg_wd_beat_count_0$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ;
assign fabric_v_rg_wd_beat_count_0$EN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ||
fabric_rg_reset ;
// register fabric_v_rg_wd_beat_count_1
assign fabric_v_rg_wd_beat_count_1$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ;
assign fabric_v_rg_wd_beat_count_1$EN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ||
fabric_rg_reset ;
// submodule fabric_v_f_rd_err_info_0
assign fabric_v_f_rd_err_info_0$D_IN = 12'h0 ;
assign fabric_v_f_rd_err_info_0$ENQ = 1'b0 ;
assign fabric_v_f_rd_err_info_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 ;
assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_err_info_1
assign fabric_v_f_rd_err_info_1$D_IN = 12'h0 ;
assign fabric_v_f_rd_err_info_1$ENQ = 1'b0 ;
assign fabric_v_f_rd_err_info_1$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 ;
assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_0
assign fabric_v_f_rd_mis_0$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ?
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 :
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ;
assign fabric_v_f_rd_mis_0$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ;
assign fabric_v_f_rd_mis_0$DEQ =
_dor1fabric_v_f_rd_mis_0$EN_deq &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 ;
assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_1
assign fabric_v_f_rd_mis_1$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ?
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 :
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ;
assign fabric_v_f_rd_mis_1$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ;
assign fabric_v_f_rd_mis_1$DEQ =
_dor1fabric_v_f_rd_mis_1$EN_deq &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 ;
assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_2
assign fabric_v_f_rd_mis_2$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ?
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 :
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ;
assign fabric_v_f_rd_mis_2$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ;
assign fabric_v_f_rd_mis_2$DEQ =
_dor1fabric_v_f_rd_mis_2$EN_deq &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 ;
assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_sjs_0
always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave:
fabric_v_f_rd_sjs_0$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1:
fabric_v_f_rd_sjs_0$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2:
fabric_v_f_rd_sjs_0$D_IN = 2'd2;
default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_rd_sjs_0$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
assign fabric_v_f_rd_sjs_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 ;
assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_sjs_1
always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3:
fabric_v_f_rd_sjs_1$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4:
fabric_v_f_rd_sjs_1$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5:
fabric_v_f_rd_sjs_1$D_IN = 2'd2;
default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_rd_sjs_1$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ;
assign fabric_v_f_rd_sjs_1$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 ;
assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wd_tasks_0
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3;
default: fabric_v_f_wd_tasks_0$D_IN =
10'b1010101010 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wd_tasks_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_v_f_wd_tasks_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ;
assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wd_tasks_1
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3;
default: fabric_v_f_wd_tasks_1$D_IN =
10'b1010101010 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wd_tasks_1$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ;
assign fabric_v_f_wd_tasks_1$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 ;
assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_err_info_0
assign fabric_v_f_wr_err_info_0$D_IN = 4'h0 ;
assign fabric_v_f_wr_err_info_0$ENQ = 1'b0 ;
assign fabric_v_f_wr_err_info_0$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_err_info_1
assign fabric_v_f_wr_err_info_1$D_IN = 4'h0 ;
assign fabric_v_f_wr_err_info_1$ENQ = 1'b0 ;
assign fabric_v_f_wr_err_info_1$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ;
assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_0
assign fabric_v_f_wr_mis_0$D_IN =
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
assign fabric_v_f_wr_mis_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ;
assign fabric_v_f_wr_mis_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_1
assign fabric_v_f_wr_mis_1$D_IN =
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
assign fabric_v_f_wr_mis_1$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ;
assign fabric_v_f_wr_mis_1$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_2
assign fabric_v_f_wr_mis_2$D_IN =
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_v_f_wr_mis_2$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ;
assign fabric_v_f_wr_mis_2$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_sjs_0
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave:
fabric_v_f_wr_sjs_0$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1:
fabric_v_f_wr_sjs_0$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2:
fabric_v_f_wr_sjs_0$D_IN = 2'd2;
default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wr_sjs_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_v_f_wr_sjs_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_sjs_1
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3:
fabric_v_f_wr_sjs_1$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4:
fabric_v_f_wr_sjs_1$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5:
fabric_v_f_wr_sjs_1$D_IN = 2'd2;
default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wr_sjs_1$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ;
assign fabric_v_f_wr_sjs_1$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ;
assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_rd_addr
assign fabric_xactors_from_masters_0_f_rd_addr$D_IN =
{ v_from_masters_0_arid,
v_from_masters_0_araddr,
v_from_masters_0_arlen,
v_from_masters_0_arsize,
v_from_masters_0_arburst,
v_from_masters_0_arlock,
v_from_masters_0_arcache,
v_from_masters_0_arprot,
v_from_masters_0_arqos,
v_from_masters_0_arregion } ;
assign fabric_xactors_from_masters_0_f_rd_addr$ENQ =
v_from_masters_0_arvalid &&
fabric_xactors_from_masters_0_f_rd_addr$FULL_N ;
assign fabric_xactors_from_masters_0_f_rd_addr$DEQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_rd_data
always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4;
default: fabric_xactors_from_masters_0_f_rd_data$D_IN =
71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_0_f_rd_data$ENQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
assign fabric_xactors_from_masters_0_f_rd_data$DEQ =
v_from_masters_0_rready &&
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ;
assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_addr
assign fabric_xactors_from_masters_0_f_wr_addr$D_IN =
{ v_from_masters_0_awid,
v_from_masters_0_awaddr,
v_from_masters_0_awlen,
v_from_masters_0_awsize,
v_from_masters_0_awburst,
v_from_masters_0_awlock,
v_from_masters_0_awcache,
v_from_masters_0_awprot,
v_from_masters_0_awqos,
v_from_masters_0_awregion } ;
assign fabric_xactors_from_masters_0_f_wr_addr$ENQ =
v_from_masters_0_awvalid &&
fabric_xactors_from_masters_0_f_wr_addr$FULL_N ;
assign fabric_xactors_from_masters_0_f_wr_addr$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_data
assign fabric_xactors_from_masters_0_f_wr_data$D_IN =
{ v_from_masters_0_wdata,
v_from_masters_0_wstrb,
v_from_masters_0_wlast } ;
assign fabric_xactors_from_masters_0_f_wr_data$ENQ =
v_from_masters_0_wvalid &&
fabric_xactors_from_masters_0_f_wr_data$FULL_N ;
assign fabric_xactors_from_masters_0_f_wr_data$DEQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_resp
always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or
MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4;
default: fabric_xactors_from_masters_0_f_wr_resp$D_IN =
6'b101010 /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_0_f_wr_resp$ENQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
assign fabric_xactors_from_masters_0_f_wr_resp$DEQ =
v_from_masters_0_bready &&
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ;
assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_rd_addr
assign fabric_xactors_from_masters_1_f_rd_addr$D_IN =
{ v_from_masters_1_arid,
v_from_masters_1_araddr,
v_from_masters_1_arlen,
v_from_masters_1_arsize,
v_from_masters_1_arburst,
v_from_masters_1_arlock,
v_from_masters_1_arcache,
v_from_masters_1_arprot,
v_from_masters_1_arqos,
v_from_masters_1_arregion } ;
assign fabric_xactors_from_masters_1_f_rd_addr$ENQ =
v_from_masters_1_arvalid &&
fabric_xactors_from_masters_1_f_rd_addr$FULL_N ;
assign fabric_xactors_from_masters_1_f_rd_addr$DEQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ;
assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_rd_data
always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or
MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4;
default: fabric_xactors_from_masters_1_f_rd_data$D_IN =
71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_1_f_rd_data$ENQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ;
assign fabric_xactors_from_masters_1_f_rd_data$DEQ =
v_from_masters_1_rready &&
fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ;
assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_wr_addr
assign fabric_xactors_from_masters_1_f_wr_addr$D_IN =
{ v_from_masters_1_awid,
v_from_masters_1_awaddr,
v_from_masters_1_awlen,
v_from_masters_1_awsize,
v_from_masters_1_awburst,
v_from_masters_1_awlock,
v_from_masters_1_awcache,
v_from_masters_1_awprot,
v_from_masters_1_awqos,
v_from_masters_1_awregion } ;
assign fabric_xactors_from_masters_1_f_wr_addr$ENQ =
v_from_masters_1_awvalid &&
fabric_xactors_from_masters_1_f_wr_addr$FULL_N ;
assign fabric_xactors_from_masters_1_f_wr_addr$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ;
assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_wr_data
assign fabric_xactors_from_masters_1_f_wr_data$D_IN =
{ v_from_masters_1_wdata,
v_from_masters_1_wstrb,
v_from_masters_1_wlast } ;
assign fabric_xactors_from_masters_1_f_wr_data$ENQ =
v_from_masters_1_wvalid &&
fabric_xactors_from_masters_1_f_wr_data$FULL_N ;
assign fabric_xactors_from_masters_1_f_wr_data$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ;
assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_wr_resp
always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or
MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4;
default: fabric_xactors_from_masters_1_f_wr_resp$D_IN =
6'b101010 /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_1_f_wr_resp$ENQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ;
assign fabric_xactors_from_masters_1_f_wr_resp$DEQ =
v_from_masters_1_bready &&
fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ;
assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_rd_addr
assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ?
fabric_xactors_from_masters_0_f_rd_addr$D_OUT :
fabric_xactors_from_masters_1_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ;
assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ =
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N &&
v_to_slaves_0_arready ;
assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_rd_data
assign fabric_xactors_to_slaves_0_f_rd_data$D_IN =
{ v_to_slaves_0_rid,
v_to_slaves_0_rdata,
v_to_slaves_0_rresp,
v_to_slaves_0_rlast } ;
assign fabric_xactors_to_slaves_0_f_rd_data$ENQ =
v_to_slaves_0_rvalid &&
fabric_xactors_to_slaves_0_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_0_f_rd_data$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_addr
assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ?
fabric_xactors_from_masters_0_f_wr_addr$D_OUT :
fabric_xactors_from_masters_1_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ;
assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ =
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N &&
v_to_slaves_0_awready ;
assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_data
assign fabric_xactors_to_slaves_0_f_wr_data$D_IN =
MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ?
fabric_xactors_from_masters_0_f_wr_data$D_OUT :
fabric_xactors_from_masters_1_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_0_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ;
assign fabric_xactors_to_slaves_0_f_wr_data$DEQ =
fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N &&
v_to_slaves_0_wready ;
assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_resp
assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN =
{ v_to_slaves_0_bid, v_to_slaves_0_bresp } ;
assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ =
v_to_slaves_0_bvalid &&
fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_rd_addr
assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ?
fabric_xactors_from_masters_0_f_rd_addr$D_OUT :
fabric_xactors_from_masters_1_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ;
assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ =
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N &&
v_to_slaves_1_arready ;
assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_rd_data
assign fabric_xactors_to_slaves_1_f_rd_data$D_IN =
{ v_to_slaves_1_rid,
v_to_slaves_1_rdata,
v_to_slaves_1_rresp,
v_to_slaves_1_rlast } ;
assign fabric_xactors_to_slaves_1_f_rd_data$ENQ =
v_to_slaves_1_rvalid &&
fabric_xactors_to_slaves_1_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_1_f_rd_data$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_addr
assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ?
fabric_xactors_from_masters_0_f_wr_addr$D_OUT :
fabric_xactors_from_masters_1_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ;
assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ =
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N &&
v_to_slaves_1_awready ;
assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_data
assign fabric_xactors_to_slaves_1_f_wr_data$D_IN =
MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ?
fabric_xactors_from_masters_0_f_wr_data$D_OUT :
fabric_xactors_from_masters_1_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_1_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ;
assign fabric_xactors_to_slaves_1_f_wr_data$DEQ =
fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N &&
v_to_slaves_1_wready ;
assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_resp
assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN =
{ v_to_slaves_1_bid, v_to_slaves_1_bresp } ;
assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ =
v_to_slaves_1_bvalid &&
fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_rd_addr
assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ?
fabric_xactors_from_masters_0_f_rd_addr$D_OUT :
fabric_xactors_from_masters_1_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ;
assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ =
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N &&
v_to_slaves_2_arready ;
assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_rd_data
assign fabric_xactors_to_slaves_2_f_rd_data$D_IN =
{ v_to_slaves_2_rid,
v_to_slaves_2_rdata,
v_to_slaves_2_rresp,
v_to_slaves_2_rlast } ;
assign fabric_xactors_to_slaves_2_f_rd_data$ENQ =
v_to_slaves_2_rvalid &&
fabric_xactors_to_slaves_2_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_2_f_rd_data$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_addr
assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ?
fabric_xactors_from_masters_0_f_wr_addr$D_OUT :
fabric_xactors_from_masters_1_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ;
assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ =
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N &&
v_to_slaves_2_awready ;
assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_data
assign fabric_xactors_to_slaves_2_f_wr_data$D_IN =
MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ?
fabric_xactors_from_masters_0_f_wr_data$D_OUT :
fabric_xactors_from_masters_1_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_2_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ;
assign fabric_xactors_to_slaves_2_f_wr_data$DEQ =
fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N &&
v_to_slaves_2_wready ;
assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_resp
assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN =
{ v_to_slaves_2_bid, v_to_slaves_2_bresp } ;
assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ =
v_to_slaves_2_bvalid &&
fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
assign IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396 =
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 ?
x1_avValue_rresp__h17880 :
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ;
assign IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435 =
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 ?
x1_avValue_rresp__h18506 :
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ;
assign IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474 =
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 ?
x1_avValue_rresp__h19122 :
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ;
assign _dor1fabric_v_f_rd_mis_0$EN_deq =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
assign _dor1fabric_v_f_rd_mis_1$EN_deq =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
assign _dor1fabric_v_f_rd_mis_2$EN_deq =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
assign fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 =
fabric_v_f_wd_tasks_0$EMPTY_N &&
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ;
assign fabric_v_f_wd_tasks_1_i_notEmpty__49_AND_fabri_ETC___d155 =
fabric_v_f_wd_tasks_1$EMPTY_N &&
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ;
assign fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 =
fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ;
assign fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 =
fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ;
assign fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 =
fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ;
assign fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 =
fabric_v_rg_r_err_beat_count_0 ==
fabric_v_f_rd_err_info_0$D_OUT[11:4] ;
assign fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 =
fabric_v_rg_r_err_beat_count_1 ==
fabric_v_f_rd_err_info_1$D_OUT[11:4] ;
assign fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 =
fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ;
assign fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 =
fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
soc_map$m_near_mem_io_addr_lim ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
soc_map$m_plic_addr_lim ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
soc_map$m_near_mem_io_addr_lim ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
soc_map$m_plic_addr_lim ;
assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325 =
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] <
soc_map$m_near_mem_io_addr_lim ;
assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330 =
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] <
soc_map$m_plic_addr_lim ;
assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] <
soc_map$m_near_mem_io_addr_lim ;
assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] <
soc_map$m_plic_addr_lim ;
assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 =
soc_map$m_near_mem_io_addr_base <=
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d273 =
soc_map$m_near_mem_io_addr_base <=
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d323 =
soc_map$m_near_mem_io_addr_base <=
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81 =
soc_map$m_near_mem_io_addr_base <=
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26 =
soc_map$m_plic_addr_base <=
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d278 =
soc_map$m_plic_addr_base <=
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d328 =
soc_map$m_plic_addr_base <=
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d86 =
soc_map$m_plic_addr_base <=
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ;
assign x1_avValue_rresp__h17880 =
(fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ;
assign x1_avValue_rresp__h18506 =
(fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ;
assign x1_avValue_rresp__h19122 =
(fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ;
assign x__h11685 = fabric_v_rg_wd_beat_count_0 + 8'd1 ;
assign x__h12148 = fabric_v_rg_wd_beat_count_1 + 8'd1 ;
assign x__h17902 = fabric_v_rg_r_beat_count_0 + 8'd1 ;
assign x__h18528 = fabric_v_rg_r_beat_count_1 + 8'd1 ;
assign x__h19144 = fabric_v_rg_r_beat_count_2 + 8'd1 ;
assign x__h21448 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ;
assign x__h21849 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ;
always@(fabric_v_f_wd_tasks_0$D_OUT or
fabric_xactors_to_slaves_0_f_wr_data$FULL_N or
fabric_xactors_to_slaves_1_f_wr_data$FULL_N or
fabric_xactors_to_slaves_2_f_wr_data$FULL_N)
begin
case (fabric_v_f_wd_tasks_0$D_OUT[9:8])
2'd0:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
2'd1:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
2'd2:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1;
endcase
end
always@(fabric_v_f_wd_tasks_1$D_OUT or
fabric_xactors_to_slaves_0_f_wr_data$FULL_N or
fabric_xactors_to_slaves_1_f_wr_data$FULL_N or
fabric_xactors_to_slaves_2_f_wr_data$FULL_N)
begin
case (fabric_v_f_wd_tasks_1$D_OUT[9:8])
2'd0:
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 =
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
2'd1:
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 =
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
2'd2:
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 =
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1;
fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
end
else
begin
if (fabric_cfg_verbosity$EN)
fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY
fabric_cfg_verbosity$D_IN;
if (fabric_rg_reset$EN)
fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN;
if (fabric_v_rg_r_beat_count_0$EN)
fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_0$D_IN;
if (fabric_v_rg_r_beat_count_1$EN)
fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_1$D_IN;
if (fabric_v_rg_r_beat_count_2$EN)
fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_2$D_IN;
if (fabric_v_rg_r_err_beat_count_0$EN)
fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_err_beat_count_0$D_IN;
if (fabric_v_rg_r_err_beat_count_1$EN)
fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_err_beat_count_1$D_IN;
if (fabric_v_rg_wd_beat_count_0$EN)
fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_wd_beat_count_0$D_IN;
if (fabric_v_rg_wd_beat_count_1$EN)
fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_wd_beat_count_1$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
fabric_cfg_verbosity = 4'hA;
fabric_rg_reset = 1'h0;
fabric_v_rg_r_beat_count_0 = 8'hAA;
fabric_v_rg_r_beat_count_1 = 8'hAA;
fabric_v_rg_r_beat_count_2 = 8'hAA;
fabric_v_rg_r_err_beat_count_0 = 8'hAA;
fabric_v_rg_r_err_beat_count_1 = 8'hAA;
fabric_v_rg_wd_beat_count_0 = 8'hAA;
fabric_v_rg_wd_beat_count_1 = 8'hAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h8688 = $stime;
#0;
end
v__h8682 = v__h8688 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h8682,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9063 = $stime;
#0;
end
v__h9057 = v__h9063 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h9057,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9438 = $stime;
#0;
end
v__h9432 = v__h9438 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h9432,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9883 = $stime;
#0;
end
v__h9877 = v__h9883 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h9877,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10252 = $stime;
#0;
end
v__h10246 = v__h10252 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h10246,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10621 = $stime;
#0;
end
v__h10615 = v__h10621 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h10615,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
begin
v__h11780 = $stime;
#0;
end
v__h11774 = v__h11780 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d",
v__h11774,
$signed(32'd0),
fabric_v_f_wd_tasks_0$D_OUT[9:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$display(" WLAST not set on final data beat (awlen = %0d)",
fabric_v_f_wd_tasks_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
begin
v__h12243 = $stime;
#0;
end
v__h12237 = v__h12243 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d",
v__h12237,
$signed(32'd1),
fabric_v_f_wd_tasks_1$D_OUT[9:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$display(" WLAST not set on final data beat (awlen = %0d)",
fabric_v_f_wd_tasks_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12618 = $stime;
#0;
end
v__h12612 = v__h12618 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h12612,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12910 = $stime;
#0;
end
v__h12904 = v__h12910 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h12904,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13202 = $stime;
#0;
end
v__h13196 = v__h13202 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h13196,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13505 = $stime;
#0;
end
v__h13499 = v__h13505 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h13499,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13771 = $stime;
#0;
end
v__h13765 = v__h13771 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h13765,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14037 = $stime;
#0;
end
v__h14031 = v__h14037 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h14031,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14301 = $stime;
#0;
end
v__h14295 = v__h14301 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err",
v__h14295,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_wr_err_info_0$D_OUT);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14527 = $stime;
#0;
end
v__h14521 = v__h14527 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err",
v__h14521,
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_wr_err_info_1$D_OUT);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14956 = $stime;
#0;
end
v__h14950 = v__h14956 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h14950,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h15312 = $stime;
#0;
end
v__h15306 = v__h15312 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h15306,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h15668 = $stime;
#0;
end
v__h15662 = v__h15668 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h15662,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h16085 = $stime;
#0;
end
v__h16079 = v__h16085 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h16079,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h16417 = $stime;
#0;
end
v__h16411 = v__h16417 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h16411,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h16749 = $stime;
#0;
end
v__h16743 = v__h16749 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h16743,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
begin
v__h17765 = $stime;
#0;
end
v__h17759 = v__h17765 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h17759,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h18016 = $stime;
#0;
end
v__h18010 = v__h18016 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h18010,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
begin
v__h18391 = $stime;
#0;
end
v__h18385 = v__h18391 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h18385,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h18632 = $stime;
#0;
end
v__h18626 = v__h18632 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h18626,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
begin
v__h19007 = $stime;
#0;
end
v__h19001 = v__h19007 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h19001,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_2$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h19248 = $stime;
#0;
end
v__h19242 = v__h19248 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h19242,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
begin
v__h19610 = $stime;
#0;
end
v__h19604 = v__h19610 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h19604,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h19861 = $stime;
#0;
end
v__h19855 = v__h19861 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h19855,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
begin
v__h20191 = $stime;
#0;
end
v__h20185 = v__h20191 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h20185,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h20432 = $stime;
#0;
end
v__h20426 = v__h20432 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h20426,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
begin
v__h20762 = $stime;
#0;
end
v__h20756 = v__h20762 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h20756,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_2$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h21003 = $stime;
#0;
end
v__h20997 = v__h21003 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h20997,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h21516 = $stime;
#0;
end
v__h21510 = v__h21516 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err",
v__h21510,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0 &&
fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h21917 = $stime;
#0;
end
v__h21911 = v__h21917 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err",
v__h21911,
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0)
begin
v__h5717 = $stime;
#0;
end
v__h5711 = v__h5717 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_reset", v__h5711);
end
// synopsys translate_on
endmodule // mkFabric_2x3
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module tracking_camera_system_nios2_qsys_0_test_bench (
// inputs:
A_bstatus_reg,
A_cmp_result,
A_ctrl_exception,
A_ctrl_ld_non_bypass,
A_dst_regnum,
A_en,
A_estatus_reg,
A_ienable_reg,
A_ipending_reg,
A_iw,
A_mem_byte_en,
A_op_hbreak,
A_op_intr,
A_pcb,
A_st_data,
A_status_reg,
A_valid,
A_wr_data_unfiltered,
A_wr_dst_reg,
E_add_br_to_taken_history_unfiltered,
E_logic_result,
E_valid,
M_bht_ptr_unfiltered,
M_bht_wr_data_unfiltered,
M_bht_wr_en_unfiltered,
M_mem_baddr,
M_target_pcb,
M_valid,
W_dst_regnum,
W_iw,
W_iw_op,
W_iw_opx,
W_pcb,
W_valid,
W_vinst,
W_wr_dst_reg,
clk,
d_address,
d_byteenable,
d_read,
d_write,
i_address,
i_read,
i_readdatavalid,
reset_n,
// outputs:
A_wr_data_filtered,
E_add_br_to_taken_history_filtered,
E_src1_eq_src2,
M_bht_ptr_filtered,
M_bht_wr_data_filtered,
M_bht_wr_en_filtered,
test_has_ended
)
;
output [ 31: 0] A_wr_data_filtered;
output E_add_br_to_taken_history_filtered;
output E_src1_eq_src2;
output [ 7: 0] M_bht_ptr_filtered;
output [ 1: 0] M_bht_wr_data_filtered;
output M_bht_wr_en_filtered;
output test_has_ended;
input [ 31: 0] A_bstatus_reg;
input A_cmp_result;
input A_ctrl_exception;
input A_ctrl_ld_non_bypass;
input [ 4: 0] A_dst_regnum;
input A_en;
input [ 31: 0] A_estatus_reg;
input [ 31: 0] A_ienable_reg;
input [ 31: 0] A_ipending_reg;
input [ 31: 0] A_iw;
input [ 3: 0] A_mem_byte_en;
input A_op_hbreak;
input A_op_intr;
input [ 24: 0] A_pcb;
input [ 31: 0] A_st_data;
input [ 31: 0] A_status_reg;
input A_valid;
input [ 31: 0] A_wr_data_unfiltered;
input A_wr_dst_reg;
input E_add_br_to_taken_history_unfiltered;
input [ 31: 0] E_logic_result;
input E_valid;
input [ 7: 0] M_bht_ptr_unfiltered;
input [ 1: 0] M_bht_wr_data_unfiltered;
input M_bht_wr_en_unfiltered;
input [ 24: 0] M_mem_baddr;
input [ 24: 0] M_target_pcb;
input M_valid;
input [ 4: 0] W_dst_regnum;
input [ 31: 0] W_iw;
input [ 5: 0] W_iw_op;
input [ 5: 0] W_iw_opx;
input [ 24: 0] W_pcb;
input W_valid;
input [ 55: 0] W_vinst;
input W_wr_dst_reg;
input clk;
input [ 24: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write;
input [ 24: 0] i_address;
input i_read;
input i_readdatavalid;
input reset_n;
reg [ 24: 0] A_mem_baddr;
reg [ 24: 0] A_target_pcb;
wire [ 31: 0] A_wr_data_filtered;
wire A_wr_data_unfiltered_0_is_x;
wire A_wr_data_unfiltered_10_is_x;
wire A_wr_data_unfiltered_11_is_x;
wire A_wr_data_unfiltered_12_is_x;
wire A_wr_data_unfiltered_13_is_x;
wire A_wr_data_unfiltered_14_is_x;
wire A_wr_data_unfiltered_15_is_x;
wire A_wr_data_unfiltered_16_is_x;
wire A_wr_data_unfiltered_17_is_x;
wire A_wr_data_unfiltered_18_is_x;
wire A_wr_data_unfiltered_19_is_x;
wire A_wr_data_unfiltered_1_is_x;
wire A_wr_data_unfiltered_20_is_x;
wire A_wr_data_unfiltered_21_is_x;
wire A_wr_data_unfiltered_22_is_x;
wire A_wr_data_unfiltered_23_is_x;
wire A_wr_data_unfiltered_24_is_x;
wire A_wr_data_unfiltered_25_is_x;
wire A_wr_data_unfiltered_26_is_x;
wire A_wr_data_unfiltered_27_is_x;
wire A_wr_data_unfiltered_28_is_x;
wire A_wr_data_unfiltered_29_is_x;
wire A_wr_data_unfiltered_2_is_x;
wire A_wr_data_unfiltered_30_is_x;
wire A_wr_data_unfiltered_31_is_x;
wire A_wr_data_unfiltered_3_is_x;
wire A_wr_data_unfiltered_4_is_x;
wire A_wr_data_unfiltered_5_is_x;
wire A_wr_data_unfiltered_6_is_x;
wire A_wr_data_unfiltered_7_is_x;
wire A_wr_data_unfiltered_8_is_x;
wire A_wr_data_unfiltered_9_is_x;
wire E_add_br_to_taken_history_filtered;
wire E_src1_eq_src2;
wire [ 7: 0] M_bht_ptr_filtered;
wire [ 1: 0] M_bht_wr_data_filtered;
wire M_bht_wr_en_filtered;
wire W_op_add;
wire W_op_addi;
wire W_op_and;
wire W_op_andhi;
wire W_op_andi;
wire W_op_beq;
wire W_op_bge;
wire W_op_bgeu;
wire W_op_blt;
wire W_op_bltu;
wire W_op_bne;
wire W_op_br;
wire W_op_break;
wire W_op_bret;
wire W_op_call;
wire W_op_callr;
wire W_op_cmpeq;
wire W_op_cmpeqi;
wire W_op_cmpge;
wire W_op_cmpgei;
wire W_op_cmpgeu;
wire W_op_cmpgeui;
wire W_op_cmplt;
wire W_op_cmplti;
wire W_op_cmpltu;
wire W_op_cmpltui;
wire W_op_cmpne;
wire W_op_cmpnei;
wire W_op_crst;
wire W_op_custom;
wire W_op_div;
wire W_op_divu;
wire W_op_eret;
wire W_op_flushd;
wire W_op_flushda;
wire W_op_flushi;
wire W_op_flushp;
wire W_op_hbreak;
wire W_op_initd;
wire W_op_initda;
wire W_op_initi;
wire W_op_intr;
wire W_op_jmp;
wire W_op_jmpi;
wire W_op_ldb;
wire W_op_ldbio;
wire W_op_ldbu;
wire W_op_ldbuio;
wire W_op_ldh;
wire W_op_ldhio;
wire W_op_ldhu;
wire W_op_ldhuio;
wire W_op_ldl;
wire W_op_ldw;
wire W_op_ldwio;
wire W_op_mul;
wire W_op_muli;
wire W_op_mulxss;
wire W_op_mulxsu;
wire W_op_mulxuu;
wire W_op_nextpc;
wire W_op_nor;
wire W_op_opx;
wire W_op_or;
wire W_op_orhi;
wire W_op_ori;
wire W_op_rdctl;
wire W_op_rdprs;
wire W_op_ret;
wire W_op_rol;
wire W_op_roli;
wire W_op_ror;
wire W_op_rsv02;
wire W_op_rsv09;
wire W_op_rsv10;
wire W_op_rsv17;
wire W_op_rsv18;
wire W_op_rsv25;
wire W_op_rsv26;
wire W_op_rsv33;
wire W_op_rsv34;
wire W_op_rsv41;
wire W_op_rsv42;
wire W_op_rsv49;
wire W_op_rsv57;
wire W_op_rsv61;
wire W_op_rsv62;
wire W_op_rsv63;
wire W_op_rsvx00;
wire W_op_rsvx10;
wire W_op_rsvx15;
wire W_op_rsvx17;
wire W_op_rsvx21;
wire W_op_rsvx25;
wire W_op_rsvx33;
wire W_op_rsvx34;
wire W_op_rsvx35;
wire W_op_rsvx42;
wire W_op_rsvx43;
wire W_op_rsvx44;
wire W_op_rsvx47;
wire W_op_rsvx50;
wire W_op_rsvx51;
wire W_op_rsvx55;
wire W_op_rsvx56;
wire W_op_rsvx60;
wire W_op_rsvx63;
wire W_op_sll;
wire W_op_slli;
wire W_op_sra;
wire W_op_srai;
wire W_op_srl;
wire W_op_srli;
wire W_op_stb;
wire W_op_stbio;
wire W_op_stc;
wire W_op_sth;
wire W_op_sthio;
wire W_op_stw;
wire W_op_stwio;
wire W_op_sub;
wire W_op_sync;
wire W_op_trap;
wire W_op_wrctl;
wire W_op_wrprs;
wire W_op_xor;
wire W_op_xorhi;
wire W_op_xori;
wire test_has_ended;
assign W_op_call = W_iw_op == 0;
assign W_op_jmpi = W_iw_op == 1;
assign W_op_ldbu = W_iw_op == 3;
assign W_op_addi = W_iw_op == 4;
assign W_op_stb = W_iw_op == 5;
assign W_op_br = W_iw_op == 6;
assign W_op_ldb = W_iw_op == 7;
assign W_op_cmpgei = W_iw_op == 8;
assign W_op_ldhu = W_iw_op == 11;
assign W_op_andi = W_iw_op == 12;
assign W_op_sth = W_iw_op == 13;
assign W_op_bge = W_iw_op == 14;
assign W_op_ldh = W_iw_op == 15;
assign W_op_cmplti = W_iw_op == 16;
assign W_op_initda = W_iw_op == 19;
assign W_op_ori = W_iw_op == 20;
assign W_op_stw = W_iw_op == 21;
assign W_op_blt = W_iw_op == 22;
assign W_op_ldw = W_iw_op == 23;
assign W_op_cmpnei = W_iw_op == 24;
assign W_op_flushda = W_iw_op == 27;
assign W_op_xori = W_iw_op == 28;
assign W_op_stc = W_iw_op == 29;
assign W_op_bne = W_iw_op == 30;
assign W_op_ldl = W_iw_op == 31;
assign W_op_cmpeqi = W_iw_op == 32;
assign W_op_ldbuio = W_iw_op == 35;
assign W_op_muli = W_iw_op == 36;
assign W_op_stbio = W_iw_op == 37;
assign W_op_beq = W_iw_op == 38;
assign W_op_ldbio = W_iw_op == 39;
assign W_op_cmpgeui = W_iw_op == 40;
assign W_op_ldhuio = W_iw_op == 43;
assign W_op_andhi = W_iw_op == 44;
assign W_op_sthio = W_iw_op == 45;
assign W_op_bgeu = W_iw_op == 46;
assign W_op_ldhio = W_iw_op == 47;
assign W_op_cmpltui = W_iw_op == 48;
assign W_op_initd = W_iw_op == 51;
assign W_op_orhi = W_iw_op == 52;
assign W_op_stwio = W_iw_op == 53;
assign W_op_bltu = W_iw_op == 54;
assign W_op_ldwio = W_iw_op == 55;
assign W_op_rdprs = W_iw_op == 56;
assign W_op_flushd = W_iw_op == 59;
assign W_op_xorhi = W_iw_op == 60;
assign W_op_rsv02 = W_iw_op == 2;
assign W_op_rsv09 = W_iw_op == 9;
assign W_op_rsv10 = W_iw_op == 10;
assign W_op_rsv17 = W_iw_op == 17;
assign W_op_rsv18 = W_iw_op == 18;
assign W_op_rsv25 = W_iw_op == 25;
assign W_op_rsv26 = W_iw_op == 26;
assign W_op_rsv33 = W_iw_op == 33;
assign W_op_rsv34 = W_iw_op == 34;
assign W_op_rsv41 = W_iw_op == 41;
assign W_op_rsv42 = W_iw_op == 42;
assign W_op_rsv49 = W_iw_op == 49;
assign W_op_rsv57 = W_iw_op == 57;
assign W_op_rsv61 = W_iw_op == 61;
assign W_op_rsv62 = W_iw_op == 62;
assign W_op_rsv63 = W_iw_op == 63;
assign W_op_eret = W_op_opx & (W_iw_opx == 1);
assign W_op_roli = W_op_opx & (W_iw_opx == 2);
assign W_op_rol = W_op_opx & (W_iw_opx == 3);
assign W_op_flushp = W_op_opx & (W_iw_opx == 4);
assign W_op_ret = W_op_opx & (W_iw_opx == 5);
assign W_op_nor = W_op_opx & (W_iw_opx == 6);
assign W_op_mulxuu = W_op_opx & (W_iw_opx == 7);
assign W_op_cmpge = W_op_opx & (W_iw_opx == 8);
assign W_op_bret = W_op_opx & (W_iw_opx == 9);
assign W_op_ror = W_op_opx & (W_iw_opx == 11);
assign W_op_flushi = W_op_opx & (W_iw_opx == 12);
assign W_op_jmp = W_op_opx & (W_iw_opx == 13);
assign W_op_and = W_op_opx & (W_iw_opx == 14);
assign W_op_cmplt = W_op_opx & (W_iw_opx == 16);
assign W_op_slli = W_op_opx & (W_iw_opx == 18);
assign W_op_sll = W_op_opx & (W_iw_opx == 19);
assign W_op_wrprs = W_op_opx & (W_iw_opx == 20);
assign W_op_or = W_op_opx & (W_iw_opx == 22);
assign W_op_mulxsu = W_op_opx & (W_iw_opx == 23);
assign W_op_cmpne = W_op_opx & (W_iw_opx == 24);
assign W_op_srli = W_op_opx & (W_iw_opx == 26);
assign W_op_srl = W_op_opx & (W_iw_opx == 27);
assign W_op_nextpc = W_op_opx & (W_iw_opx == 28);
assign W_op_callr = W_op_opx & (W_iw_opx == 29);
assign W_op_xor = W_op_opx & (W_iw_opx == 30);
assign W_op_mulxss = W_op_opx & (W_iw_opx == 31);
assign W_op_cmpeq = W_op_opx & (W_iw_opx == 32);
assign W_op_divu = W_op_opx & (W_iw_opx == 36);
assign W_op_div = W_op_opx & (W_iw_opx == 37);
assign W_op_rdctl = W_op_opx & (W_iw_opx == 38);
assign W_op_mul = W_op_opx & (W_iw_opx == 39);
assign W_op_cmpgeu = W_op_opx & (W_iw_opx == 40);
assign W_op_initi = W_op_opx & (W_iw_opx == 41);
assign W_op_trap = W_op_opx & (W_iw_opx == 45);
assign W_op_wrctl = W_op_opx & (W_iw_opx == 46);
assign W_op_cmpltu = W_op_opx & (W_iw_opx == 48);
assign W_op_add = W_op_opx & (W_iw_opx == 49);
assign W_op_break = W_op_opx & (W_iw_opx == 52);
assign W_op_hbreak = W_op_opx & (W_iw_opx == 53);
assign W_op_sync = W_op_opx & (W_iw_opx == 54);
assign W_op_sub = W_op_opx & (W_iw_opx == 57);
assign W_op_srai = W_op_opx & (W_iw_opx == 58);
assign W_op_sra = W_op_opx & (W_iw_opx == 59);
assign W_op_intr = W_op_opx & (W_iw_opx == 61);
assign W_op_crst = W_op_opx & (W_iw_opx == 62);
assign W_op_rsvx00 = W_op_opx & (W_iw_opx == 0);
assign W_op_rsvx10 = W_op_opx & (W_iw_opx == 10);
assign W_op_rsvx15 = W_op_opx & (W_iw_opx == 15);
assign W_op_rsvx17 = W_op_opx & (W_iw_opx == 17);
assign W_op_rsvx21 = W_op_opx & (W_iw_opx == 21);
assign W_op_rsvx25 = W_op_opx & (W_iw_opx == 25);
assign W_op_rsvx33 = W_op_opx & (W_iw_opx == 33);
assign W_op_rsvx34 = W_op_opx & (W_iw_opx == 34);
assign W_op_rsvx35 = W_op_opx & (W_iw_opx == 35);
assign W_op_rsvx42 = W_op_opx & (W_iw_opx == 42);
assign W_op_rsvx43 = W_op_opx & (W_iw_opx == 43);
assign W_op_rsvx44 = W_op_opx & (W_iw_opx == 44);
assign W_op_rsvx47 = W_op_opx & (W_iw_opx == 47);
assign W_op_rsvx50 = W_op_opx & (W_iw_opx == 50);
assign W_op_rsvx51 = W_op_opx & (W_iw_opx == 51);
assign W_op_rsvx55 = W_op_opx & (W_iw_opx == 55);
assign W_op_rsvx56 = W_op_opx & (W_iw_opx == 56);
assign W_op_rsvx60 = W_op_opx & (W_iw_opx == 60);
assign W_op_rsvx63 = W_op_opx & (W_iw_opx == 63);
assign W_op_opx = W_iw_op == 58;
assign W_op_custom = W_iw_op == 50;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
A_target_pcb <= 0;
else if (A_en)
A_target_pcb <= M_target_pcb;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
A_mem_baddr <= 0;
else if (A_en)
A_mem_baddr <= M_mem_baddr;
end
assign E_src1_eq_src2 = E_logic_result == 0;
//Propagating 'X' data bits
assign E_add_br_to_taken_history_filtered = E_add_br_to_taken_history_unfiltered;
//Propagating 'X' data bits
assign M_bht_wr_en_filtered = M_bht_wr_en_unfiltered;
//Propagating 'X' data bits
assign M_bht_wr_data_filtered = M_bht_wr_data_unfiltered;
//Propagating 'X' data bits
assign M_bht_ptr_filtered = M_bht_ptr_unfiltered;
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign A_wr_data_unfiltered_0_is_x = ^(A_wr_data_unfiltered[0]) === 1'bx;
assign A_wr_data_filtered[0] = (A_wr_data_unfiltered_0_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[0];
assign A_wr_data_unfiltered_1_is_x = ^(A_wr_data_unfiltered[1]) === 1'bx;
assign A_wr_data_filtered[1] = (A_wr_data_unfiltered_1_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[1];
assign A_wr_data_unfiltered_2_is_x = ^(A_wr_data_unfiltered[2]) === 1'bx;
assign A_wr_data_filtered[2] = (A_wr_data_unfiltered_2_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[2];
assign A_wr_data_unfiltered_3_is_x = ^(A_wr_data_unfiltered[3]) === 1'bx;
assign A_wr_data_filtered[3] = (A_wr_data_unfiltered_3_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[3];
assign A_wr_data_unfiltered_4_is_x = ^(A_wr_data_unfiltered[4]) === 1'bx;
assign A_wr_data_filtered[4] = (A_wr_data_unfiltered_4_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[4];
assign A_wr_data_unfiltered_5_is_x = ^(A_wr_data_unfiltered[5]) === 1'bx;
assign A_wr_data_filtered[5] = (A_wr_data_unfiltered_5_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[5];
assign A_wr_data_unfiltered_6_is_x = ^(A_wr_data_unfiltered[6]) === 1'bx;
assign A_wr_data_filtered[6] = (A_wr_data_unfiltered_6_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[6];
assign A_wr_data_unfiltered_7_is_x = ^(A_wr_data_unfiltered[7]) === 1'bx;
assign A_wr_data_filtered[7] = (A_wr_data_unfiltered_7_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[7];
assign A_wr_data_unfiltered_8_is_x = ^(A_wr_data_unfiltered[8]) === 1'bx;
assign A_wr_data_filtered[8] = (A_wr_data_unfiltered_8_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[8];
assign A_wr_data_unfiltered_9_is_x = ^(A_wr_data_unfiltered[9]) === 1'bx;
assign A_wr_data_filtered[9] = (A_wr_data_unfiltered_9_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[9];
assign A_wr_data_unfiltered_10_is_x = ^(A_wr_data_unfiltered[10]) === 1'bx;
assign A_wr_data_filtered[10] = (A_wr_data_unfiltered_10_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[10];
assign A_wr_data_unfiltered_11_is_x = ^(A_wr_data_unfiltered[11]) === 1'bx;
assign A_wr_data_filtered[11] = (A_wr_data_unfiltered_11_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[11];
assign A_wr_data_unfiltered_12_is_x = ^(A_wr_data_unfiltered[12]) === 1'bx;
assign A_wr_data_filtered[12] = (A_wr_data_unfiltered_12_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[12];
assign A_wr_data_unfiltered_13_is_x = ^(A_wr_data_unfiltered[13]) === 1'bx;
assign A_wr_data_filtered[13] = (A_wr_data_unfiltered_13_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[13];
assign A_wr_data_unfiltered_14_is_x = ^(A_wr_data_unfiltered[14]) === 1'bx;
assign A_wr_data_filtered[14] = (A_wr_data_unfiltered_14_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[14];
assign A_wr_data_unfiltered_15_is_x = ^(A_wr_data_unfiltered[15]) === 1'bx;
assign A_wr_data_filtered[15] = (A_wr_data_unfiltered_15_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[15];
assign A_wr_data_unfiltered_16_is_x = ^(A_wr_data_unfiltered[16]) === 1'bx;
assign A_wr_data_filtered[16] = (A_wr_data_unfiltered_16_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[16];
assign A_wr_data_unfiltered_17_is_x = ^(A_wr_data_unfiltered[17]) === 1'bx;
assign A_wr_data_filtered[17] = (A_wr_data_unfiltered_17_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[17];
assign A_wr_data_unfiltered_18_is_x = ^(A_wr_data_unfiltered[18]) === 1'bx;
assign A_wr_data_filtered[18] = (A_wr_data_unfiltered_18_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[18];
assign A_wr_data_unfiltered_19_is_x = ^(A_wr_data_unfiltered[19]) === 1'bx;
assign A_wr_data_filtered[19] = (A_wr_data_unfiltered_19_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[19];
assign A_wr_data_unfiltered_20_is_x = ^(A_wr_data_unfiltered[20]) === 1'bx;
assign A_wr_data_filtered[20] = (A_wr_data_unfiltered_20_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[20];
assign A_wr_data_unfiltered_21_is_x = ^(A_wr_data_unfiltered[21]) === 1'bx;
assign A_wr_data_filtered[21] = (A_wr_data_unfiltered_21_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[21];
assign A_wr_data_unfiltered_22_is_x = ^(A_wr_data_unfiltered[22]) === 1'bx;
assign A_wr_data_filtered[22] = (A_wr_data_unfiltered_22_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[22];
assign A_wr_data_unfiltered_23_is_x = ^(A_wr_data_unfiltered[23]) === 1'bx;
assign A_wr_data_filtered[23] = (A_wr_data_unfiltered_23_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[23];
assign A_wr_data_unfiltered_24_is_x = ^(A_wr_data_unfiltered[24]) === 1'bx;
assign A_wr_data_filtered[24] = (A_wr_data_unfiltered_24_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[24];
assign A_wr_data_unfiltered_25_is_x = ^(A_wr_data_unfiltered[25]) === 1'bx;
assign A_wr_data_filtered[25] = (A_wr_data_unfiltered_25_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[25];
assign A_wr_data_unfiltered_26_is_x = ^(A_wr_data_unfiltered[26]) === 1'bx;
assign A_wr_data_filtered[26] = (A_wr_data_unfiltered_26_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[26];
assign A_wr_data_unfiltered_27_is_x = ^(A_wr_data_unfiltered[27]) === 1'bx;
assign A_wr_data_filtered[27] = (A_wr_data_unfiltered_27_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[27];
assign A_wr_data_unfiltered_28_is_x = ^(A_wr_data_unfiltered[28]) === 1'bx;
assign A_wr_data_filtered[28] = (A_wr_data_unfiltered_28_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[28];
assign A_wr_data_unfiltered_29_is_x = ^(A_wr_data_unfiltered[29]) === 1'bx;
assign A_wr_data_filtered[29] = (A_wr_data_unfiltered_29_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[29];
assign A_wr_data_unfiltered_30_is_x = ^(A_wr_data_unfiltered[30]) === 1'bx;
assign A_wr_data_filtered[30] = (A_wr_data_unfiltered_30_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[30];
assign A_wr_data_unfiltered_31_is_x = ^(A_wr_data_unfiltered[31]) === 1'bx;
assign A_wr_data_filtered[31] = (A_wr_data_unfiltered_31_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(W_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: tracking_camera_system_nios2_qsys_0_test_bench/W_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_wr_dst_reg)
if (^(W_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: tracking_camera_system_nios2_qsys_0_test_bench/W_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: tracking_camera_system_nios2_qsys_0_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(W_pcb) === 1'bx)
begin
$write("%0d ns: ERROR: tracking_camera_system_nios2_qsys_0_test_bench/W_pcb is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(W_iw) === 1'bx)
begin
$write("%0d ns: ERROR: tracking_camera_system_nios2_qsys_0_test_bench/W_iw is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_en) === 1'bx)
begin
$write("%0d ns: ERROR: tracking_camera_system_nios2_qsys_0_test_bench/A_en is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(E_valid) === 1'bx)
begin
$write("%0d ns: ERROR: tracking_camera_system_nios2_qsys_0_test_bench/E_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(M_valid) === 1'bx)
begin
$write("%0d ns: ERROR: tracking_camera_system_nios2_qsys_0_test_bench/M_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_valid) === 1'bx)
begin
$write("%0d ns: ERROR: tracking_camera_system_nios2_qsys_0_test_bench/A_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (A_valid & A_en & A_wr_dst_reg)
if (^(A_wr_data_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: tracking_camera_system_nios2_qsys_0_test_bench/A_wr_data_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_status_reg) === 1'bx)
begin
$write("%0d ns: ERROR: tracking_camera_system_nios2_qsys_0_test_bench/A_status_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_estatus_reg) === 1'bx)
begin
$write("%0d ns: ERROR: tracking_camera_system_nios2_qsys_0_test_bench/A_estatus_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_bstatus_reg) === 1'bx)
begin
$write("%0d ns: ERROR: tracking_camera_system_nios2_qsys_0_test_bench/A_bstatus_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: tracking_camera_system_nios2_qsys_0_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: tracking_camera_system_nios2_qsys_0_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_readdatavalid) === 1'bx)
begin
$write("%0d ns: ERROR: tracking_camera_system_nios2_qsys_0_test_bench/i_readdatavalid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: tracking_camera_system_nios2_qsys_0_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: tracking_camera_system_nios2_qsys_0_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: tracking_camera_system_nios2_qsys_0_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: tracking_camera_system_nios2_qsys_0_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
reg [31:0] trace_handle; // for $fopen
initial
begin
trace_handle = $fopen("tracking_camera_system_nios2_qsys_0.tr");
$fwrite(trace_handle, "version 3\nnumThreads 1\n");
end
always @(posedge clk)
begin
if ((~reset_n || (A_valid & A_en)) && ~test_has_ended)
$fwrite(trace_handle, "%0d ns: %0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h\n", $time, ~reset_n, A_pcb, 0, A_op_intr, A_op_hbreak, A_iw, ~(A_op_intr | A_op_hbreak), A_wr_dst_reg, A_dst_regnum, 0, A_wr_data_filtered, A_mem_baddr, A_st_data, A_mem_byte_en, A_cmp_result, A_target_pcb, A_status_reg, A_estatus_reg, A_bstatus_reg, A_ienable_reg, A_ipending_reg, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, A_ctrl_exception ? 1 : 0, 0, 0, 0, 0);
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign A_wr_data_filtered = A_wr_data_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire5;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire locked = sub_wire5;
altpll altpll_component (
.areset (areset),
.inclk (sub_wire1),
.clk (sub_wire3),
.locked (sub_wire5),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 4,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 41666,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "96.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/13/2015 09:33:31 AM
// Design Name:
// Module Name: Components
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// module MicroToAngle(
// input wire [RC_SIGNAL_WIDTH-1:0] pos,
// output reg [RC_SIGNAL_WIDTH-1:0] out_pos
// );
// integer i;
// integer at5;
// always @(*) begin
// for(i = 0; i < 1000; i)
// end
module PositionMux(
input wire [1:0] ctrl,
input wire [RC_SIGNAL_WIDTH-1:0] sweep_pos,
input wire [PIN_POS_WIDTH-1:0] pin_pos,
input wire [RC_SIGNAL_WIDTH-1:0] ser_pos,
output reg [RC_SIGNAL_WIDTH-1:0] out_pos
);
parameter RC_SIGNAL_WIDTH = 11;
parameter PIN_POS_WIDTH = 10;
parameter BCD_WIDTH = 4;
parameter POSITION_FILE_WIDTH = 32;
parameter POSITION_WIDTH = 11;
parameter PWMS = 4;
wire valid;
wire [RC_SIGNAL_WIDTH-1:0] segment_pos;
Segment U0 (
.in(pin_pos),
.out(segment_pos),
.valid(valid)
);
always @(*) begin
case(ctrl)
0: out_pos = sweep_pos;
1: out_pos = (pin_pos << 1) | 1'b1;
2: out_pos = segment_pos;
3: out_pos = ser_pos;
default: out_pos = sweep_pos;
endcase
end
endmodule
module SweepPosition(
input wire clk200Hz,
input wire rst,
input wire [2:0] speed,
output reg [RC_SIGNAL_WIDTH-1:0] pos
);
parameter RC_SIGNAL_WIDTH = 11;
parameter PIN_POS_WIDTH = 10;
parameter BCD_WIDTH = 4;
parameter POSITION_FILE_WIDTH = 32;
parameter POSITION_WIDTH = 11;
parameter PWMS = 4;
reg dir;
/* Will sweep from 0 degrees to 180 degrees and back with 1000 degrees of precision.
* Will take 5 seconds to do one sweep.
*
*/
always @(posedge clk200Hz or posedge rst) begin
if (rst) begin
pos = 10'd0;
dir = 0;
end
else if(dir == 0) begin
pos = pos + (speed << 1);
// max of 1000 positions
if(pos >= 2000) begin
dir = 1;
end
end
else if(dir == 1) begin
pos = pos - (speed << 1);
// Check Position to determine
if (pos <= 0) begin
dir = 0;
end
end
end
endmodule
module AngleToPWM(
input wire [RC_SIGNAL_WIDTH-1:0] pos,
input wire clk1MHz,
input wire rst,
output reg pwm
);
parameter RC_SIGNAL_WIDTH = 11;
parameter PIN_POS_WIDTH = 10;
parameter BCD_WIDTH = 4;
parameter POSITION_FILE_WIDTH = 32;
parameter POSITION_WIDTH = 11;
parameter PWMS = 4;
parameter time_width = 20000; // 20 ms = 20000 us
parameter pos_time_min = 500; // 1 ms = 1000 us
parameter pos_time_max = 2500; // 2 ms = 2000 us
integer current_time;
reg [10:0] stored_pos;
reg [1:0] state;
always @(posedge clk1MHz or posedge rst) begin
if (rst) begin
pwm = 1'b1;
state = 3'b0;
current_time = 0;
stored_pos = 0;
end
else if(pos > 2500 || pos < 0) begin
pwm = 1'b1;
end
else begin
case(state)
// Set inital pulse
// Set pulse high for 1ms
0: begin
pwm = 1;
//if (current_time >= pos_time_min) begin
stored_pos = pos;
state = 3'h1;
//end
end
// Set Positive Angle portion of pulse
1: begin
pwm = 1;
if (current_time >= stored_pos) begin
state = 3'h2;
end
end
// Set Negative Angle portion of pulse
// Wait until 20ms is up!
2: begin
pwm = 0;
if (current_time >= time_width) begin
state = 3'h0;
current_time = 0;
end
end
endcase
current_time = current_time + 1;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps/sky130_fd_sc_hd__udp_dff_ps.v"
`celldefine
module sky130_fd_sc_hd__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hd__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_V |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_fcmp(clock, resetn,
i_dataa, i_dataa_valid, o_dataa_stall,
i_datab, i_datab_valid, o_datab_stall,
o_dataout, o_dataout_valid, i_stall,
i_settings);
parameter DATA_WIDTH = 32;
parameter LATENCY = 3;
parameter MODE_WIDTH = 4;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [DATA_WIDTH-1:0] i_dataa;
input [DATA_WIDTH-1:0] i_datab;
input i_dataa_valid, i_datab_valid;
output o_dataa_stall, o_datab_stall;
output o_dataout;
output o_dataout_valid;
input i_stall;
input [MODE_WIDTH-1:0] i_settings;
reg [LATENCY-1:0] shift_reg_valid;
wire [DATA_WIDTH-1:0] dataa;
wire [DATA_WIDTH-1:0] datab;
wire is_fifo_a_valid;
wire is_fifo_b_valid;
wire is_stalled;
wire is_fifo_stalled;
wire aeb, agb, ageb, alb, aleb, aneb, unordered;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(i_dataa), .data_out(dataa), .valid_in(i_dataa_valid),
.valid_out( is_fifo_a_valid ), .stall_in(is_fifo_stalled), .stall_out(o_dataa_stall) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_b ( .clock(clock), .resetn(resetn),
.data_in(i_datab), .data_out(datab), .valid_in(i_datab_valid),
.valid_out( is_fifo_b_valid ), .stall_in(is_fifo_stalled), .stall_out(o_datab_stall) );
defparam fifo_b.DATA_WIDTH = DATA_WIDTH;
defparam fifo_b.DEPTH = FIFO_DEPTH;
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
shift_reg_valid <= {LATENCY{1'b0}};
end
else
begin
if(~is_stalled)
shift_reg_valid <= { is_fifo_a_valid & is_fifo_b_valid, shift_reg_valid[LATENCY-1:1] };
end
end
assign is_stalled = (shift_reg_valid[0] & i_stall);
assign is_fifo_stalled = (shift_reg_valid[0] & i_stall) | !(is_fifo_a_valid & is_fifo_b_valid);
acl_fp_cmp_altfp_compare_6me fcmp_unit(.clock(clock), .clk_en(~is_stalled),
.dataa(dataa), .datab(datab),
.aeb(aeb), .agb(agb), .ageb(ageb),
.alb(alb), .aleb(aleb), .aneb(aneb),
.unordered(unordered));
// need to figure out what the output value should be, depending on the i_settings
always @(*)
begin
case (i_settings)
4'h0: // FCMP_FALSE
begin
o_dataout <= 1'b0;
end
4'h1: // FCMP_OEQ - True if ordered and equal
begin
o_dataout <= (~unordered && aeb);
end
4'h2: // FCMP_OGT
begin
o_dataout <= (~unordered && agb);
end
4'h3: // FCMP_OGE
begin
o_dataout <= (~unordered && ageb);
end
4'h4: // FCMP_OLT
begin
o_dataout <= (~unordered && alb);
end
4'h5: // FCMP_OLE
begin
o_dataout <= (~unordered && aleb);
end
4'h6: // FCMP_ONE
begin
o_dataout <= (~unordered && aneb);
end
4'h7: // FCMP_ORD - True if ordered (no nans)
begin
o_dataout <= (~unordered);
end
4'h8: // FCMP_UNO - True if unordered: isnan(X) | isnan(Y)
begin
o_dataout <= unordered;
end
4'h9: // FCMP_UEQ - True if unordered or equal
begin
o_dataout <= (unordered || aeb);
end
4'hA: // FCMP_UGT
begin
o_dataout <= (unordered || agb);
end
4'hB: // FCMP_UGE
begin
o_dataout <= (unordered || ageb);
end
4'hC: // FCMP_ULT
begin
o_dataout <= (unordered || alb);
end
4'hD: // FCMP_ULE
begin
o_dataout <= (unordered || aleb);
end
4'hE: // FCMP_UNE
begin
o_dataout <= (unordered || aneb);
end
4'hF: // FCMP_TRUE
begin
o_dataout <= 1'b1;
end
default:
begin
o_dataout <= 1'b0;
end
endcase
end
assign o_dataout_valid = shift_reg_valid[0];
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [3:0] datai = crc[3:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic [3:0] datao; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.datao (datao[3:0]),
// Inputs
.clk (clk),
.datai (datai[3:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, datao};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h3db7bc8bfe61f983
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test
(
input logic clk,
input logic [3:0] datai,
output logic [3:0] datao
);
genvar i;
parameter SIZE = 4;
logic [SIZE:1][3:0] delay;
always_ff @(posedge clk) begin
delay[1][3:0] <= datai;
end
generate
for (i = 2; i < (SIZE+1); i++) begin
always_ff @(posedge clk) begin
delay[i][3:0] <= delay[i-1][3:0];
end
end
endgenerate
always_comb datao = delay[SIZE][3:0];
endmodule
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Mon Nov 14 15:54:44 EST 2016
//
// Method conflict info:
// Method: allocate
// Sequenced before: next
// Sequenced before (restricted): allocate
//
// Method: next
// Sequenced after: allocate
// Conflicts: next
//
//
// Ports:
// Name I/O size props
// allocate O 25
// pipeline I 1
// CLK I 1 clock
// RST_N I 1 reset
// allocate_alloc_input I 25
// EN_next I 1
// EN_allocate I 1
//
// Combinational paths from inputs to outputs:
// (allocate_alloc_input, pipeline) -> allocate
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkSepRouterAllocator(pipeline,
CLK,
RST_N,
allocate_alloc_input,
EN_allocate,
allocate,
EN_next);
input pipeline;
input CLK;
input RST_N;
// actionvalue method allocate
input [24 : 0] allocate_alloc_input;
input EN_allocate;
output [24 : 0] allocate;
// action method next
input EN_next;
// signals for module outputs
wire [24 : 0] allocate;
// register as_inputArbGrants_reg_0
reg as_inputArbGrants_reg_0;
wire as_inputArbGrants_reg_0$D_IN, as_inputArbGrants_reg_0$EN;
// register as_inputArbGrants_reg_0_1
reg as_inputArbGrants_reg_0_1;
wire as_inputArbGrants_reg_0_1$D_IN, as_inputArbGrants_reg_0_1$EN;
// register as_inputArbGrants_reg_0_2
reg as_inputArbGrants_reg_0_2;
wire as_inputArbGrants_reg_0_2$D_IN, as_inputArbGrants_reg_0_2$EN;
// register as_inputArbGrants_reg_0_3
reg as_inputArbGrants_reg_0_3;
wire as_inputArbGrants_reg_0_3$D_IN, as_inputArbGrants_reg_0_3$EN;
// register as_inputArbGrants_reg_0_4
reg as_inputArbGrants_reg_0_4;
wire as_inputArbGrants_reg_0_4$D_IN, as_inputArbGrants_reg_0_4$EN;
// register as_inputArbGrants_reg_1
reg as_inputArbGrants_reg_1;
wire as_inputArbGrants_reg_1$D_IN, as_inputArbGrants_reg_1$EN;
// register as_inputArbGrants_reg_1_1
reg as_inputArbGrants_reg_1_1;
wire as_inputArbGrants_reg_1_1$D_IN, as_inputArbGrants_reg_1_1$EN;
// register as_inputArbGrants_reg_1_2
reg as_inputArbGrants_reg_1_2;
wire as_inputArbGrants_reg_1_2$D_IN, as_inputArbGrants_reg_1_2$EN;
// register as_inputArbGrants_reg_1_3
reg as_inputArbGrants_reg_1_3;
wire as_inputArbGrants_reg_1_3$D_IN, as_inputArbGrants_reg_1_3$EN;
// register as_inputArbGrants_reg_1_4
reg as_inputArbGrants_reg_1_4;
wire as_inputArbGrants_reg_1_4$D_IN, as_inputArbGrants_reg_1_4$EN;
// register as_inputArbGrants_reg_2
reg as_inputArbGrants_reg_2;
wire as_inputArbGrants_reg_2$D_IN, as_inputArbGrants_reg_2$EN;
// register as_inputArbGrants_reg_2_1
reg as_inputArbGrants_reg_2_1;
wire as_inputArbGrants_reg_2_1$D_IN, as_inputArbGrants_reg_2_1$EN;
// register as_inputArbGrants_reg_2_2
reg as_inputArbGrants_reg_2_2;
wire as_inputArbGrants_reg_2_2$D_IN, as_inputArbGrants_reg_2_2$EN;
// register as_inputArbGrants_reg_2_3
reg as_inputArbGrants_reg_2_3;
wire as_inputArbGrants_reg_2_3$D_IN, as_inputArbGrants_reg_2_3$EN;
// register as_inputArbGrants_reg_2_4
reg as_inputArbGrants_reg_2_4;
wire as_inputArbGrants_reg_2_4$D_IN, as_inputArbGrants_reg_2_4$EN;
// register as_inputArbGrants_reg_3
reg as_inputArbGrants_reg_3;
wire as_inputArbGrants_reg_3$D_IN, as_inputArbGrants_reg_3$EN;
// register as_inputArbGrants_reg_3_1
reg as_inputArbGrants_reg_3_1;
wire as_inputArbGrants_reg_3_1$D_IN, as_inputArbGrants_reg_3_1$EN;
// register as_inputArbGrants_reg_3_2
reg as_inputArbGrants_reg_3_2;
wire as_inputArbGrants_reg_3_2$D_IN, as_inputArbGrants_reg_3_2$EN;
// register as_inputArbGrants_reg_3_3
reg as_inputArbGrants_reg_3_3;
wire as_inputArbGrants_reg_3_3$D_IN, as_inputArbGrants_reg_3_3$EN;
// register as_inputArbGrants_reg_3_4
reg as_inputArbGrants_reg_3_4;
wire as_inputArbGrants_reg_3_4$D_IN, as_inputArbGrants_reg_3_4$EN;
// register as_inputArbGrants_reg_4
reg as_inputArbGrants_reg_4;
wire as_inputArbGrants_reg_4$D_IN, as_inputArbGrants_reg_4$EN;
// register as_inputArbGrants_reg_4_1
reg as_inputArbGrants_reg_4_1;
wire as_inputArbGrants_reg_4_1$D_IN, as_inputArbGrants_reg_4_1$EN;
// register as_inputArbGrants_reg_4_2
reg as_inputArbGrants_reg_4_2;
wire as_inputArbGrants_reg_4_2$D_IN, as_inputArbGrants_reg_4_2$EN;
// register as_inputArbGrants_reg_4_3
reg as_inputArbGrants_reg_4_3;
wire as_inputArbGrants_reg_4_3$D_IN, as_inputArbGrants_reg_4_3$EN;
// register as_inputArbGrants_reg_4_4
reg as_inputArbGrants_reg_4_4;
wire as_inputArbGrants_reg_4_4$D_IN, as_inputArbGrants_reg_4_4$EN;
// ports of submodule inputArbs
wire [4 : 0] inputArbs$input_arbs_0_select,
inputArbs$input_arbs_0_select_requests,
inputArbs$input_arbs_1_select,
inputArbs$input_arbs_1_select_requests,
inputArbs$input_arbs_2_select,
inputArbs$input_arbs_2_select_requests,
inputArbs$input_arbs_3_select,
inputArbs$input_arbs_3_select_requests,
inputArbs$input_arbs_4_select,
inputArbs$input_arbs_4_select_requests;
wire inputArbs$EN_input_arbs_0_next,
inputArbs$EN_input_arbs_1_next,
inputArbs$EN_input_arbs_2_next,
inputArbs$EN_input_arbs_3_next,
inputArbs$EN_input_arbs_4_next;
// ports of submodule outputArbs
wire [4 : 0] outputArbs$output_arbs_0_select,
outputArbs$output_arbs_0_select_requests,
outputArbs$output_arbs_1_select,
outputArbs$output_arbs_1_select_requests,
outputArbs$output_arbs_2_select,
outputArbs$output_arbs_2_select_requests,
outputArbs$output_arbs_3_select,
outputArbs$output_arbs_3_select_requests,
outputArbs$output_arbs_4_select,
outputArbs$output_arbs_4_select_requests;
wire outputArbs$EN_output_arbs_0_next,
outputArbs$EN_output_arbs_1_next,
outputArbs$EN_output_arbs_2_next,
outputArbs$EN_output_arbs_3_next,
outputArbs$EN_output_arbs_4_next;
// actionvalue method allocate
assign allocate =
{ outputArbs$output_arbs_4_select[4],
outputArbs$output_arbs_3_select[4],
outputArbs$output_arbs_2_select[4],
outputArbs$output_arbs_1_select[4],
outputArbs$output_arbs_0_select[4],
outputArbs$output_arbs_4_select[3],
outputArbs$output_arbs_3_select[3],
outputArbs$output_arbs_2_select[3],
outputArbs$output_arbs_1_select[3],
outputArbs$output_arbs_0_select[3],
outputArbs$output_arbs_4_select[2],
outputArbs$output_arbs_3_select[2],
outputArbs$output_arbs_2_select[2],
outputArbs$output_arbs_1_select[2],
outputArbs$output_arbs_0_select[2],
outputArbs$output_arbs_4_select[1],
outputArbs$output_arbs_3_select[1],
outputArbs$output_arbs_2_select[1],
outputArbs$output_arbs_1_select[1],
outputArbs$output_arbs_0_select[1],
outputArbs$output_arbs_4_select[0],
outputArbs$output_arbs_3_select[0],
outputArbs$output_arbs_2_select[0],
outputArbs$output_arbs_1_select[0],
outputArbs$output_arbs_0_select[0] } ;
// submodule inputArbs
mkRouterInputArbitersRoundRobin inputArbs(.CLK(CLK),
.RST_N(RST_N),
.input_arbs_0_select_requests(inputArbs$input_arbs_0_select_requests),
.input_arbs_1_select_requests(inputArbs$input_arbs_1_select_requests),
.input_arbs_2_select_requests(inputArbs$input_arbs_2_select_requests),
.input_arbs_3_select_requests(inputArbs$input_arbs_3_select_requests),
.input_arbs_4_select_requests(inputArbs$input_arbs_4_select_requests),
.EN_input_arbs_0_next(inputArbs$EN_input_arbs_0_next),
.EN_input_arbs_1_next(inputArbs$EN_input_arbs_1_next),
.EN_input_arbs_2_next(inputArbs$EN_input_arbs_2_next),
.EN_input_arbs_3_next(inputArbs$EN_input_arbs_3_next),
.EN_input_arbs_4_next(inputArbs$EN_input_arbs_4_next),
.input_arbs_0_select(inputArbs$input_arbs_0_select),
.input_arbs_1_select(inputArbs$input_arbs_1_select),
.input_arbs_2_select(inputArbs$input_arbs_2_select),
.input_arbs_3_select(inputArbs$input_arbs_3_select),
.input_arbs_4_select(inputArbs$input_arbs_4_select));
// submodule outputArbs
mkRouterOutputArbitersRoundRobin outputArbs(.CLK(CLK),
.RST_N(RST_N),
.output_arbs_0_select_requests(outputArbs$output_arbs_0_select_requests),
.output_arbs_1_select_requests(outputArbs$output_arbs_1_select_requests),
.output_arbs_2_select_requests(outputArbs$output_arbs_2_select_requests),
.output_arbs_3_select_requests(outputArbs$output_arbs_3_select_requests),
.output_arbs_4_select_requests(outputArbs$output_arbs_4_select_requests),
.EN_output_arbs_0_next(outputArbs$EN_output_arbs_0_next),
.EN_output_arbs_1_next(outputArbs$EN_output_arbs_1_next),
.EN_output_arbs_2_next(outputArbs$EN_output_arbs_2_next),
.EN_output_arbs_3_next(outputArbs$EN_output_arbs_3_next),
.EN_output_arbs_4_next(outputArbs$EN_output_arbs_4_next),
.output_arbs_0_select(outputArbs$output_arbs_0_select),
.output_arbs_1_select(outputArbs$output_arbs_1_select),
.output_arbs_2_select(outputArbs$output_arbs_2_select),
.output_arbs_3_select(outputArbs$output_arbs_3_select),
.output_arbs_4_select(outputArbs$output_arbs_4_select));
// register as_inputArbGrants_reg_0
assign as_inputArbGrants_reg_0$D_IN = inputArbs$input_arbs_0_select[0] ;
assign as_inputArbGrants_reg_0$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_0_1
assign as_inputArbGrants_reg_0_1$D_IN = inputArbs$input_arbs_0_select[1] ;
assign as_inputArbGrants_reg_0_1$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_0_2
assign as_inputArbGrants_reg_0_2$D_IN = inputArbs$input_arbs_0_select[2] ;
assign as_inputArbGrants_reg_0_2$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_0_3
assign as_inputArbGrants_reg_0_3$D_IN = inputArbs$input_arbs_0_select[3] ;
assign as_inputArbGrants_reg_0_3$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_0_4
assign as_inputArbGrants_reg_0_4$D_IN = inputArbs$input_arbs_0_select[4] ;
assign as_inputArbGrants_reg_0_4$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_1
assign as_inputArbGrants_reg_1$D_IN = inputArbs$input_arbs_1_select[0] ;
assign as_inputArbGrants_reg_1$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_1_1
assign as_inputArbGrants_reg_1_1$D_IN = inputArbs$input_arbs_1_select[1] ;
assign as_inputArbGrants_reg_1_1$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_1_2
assign as_inputArbGrants_reg_1_2$D_IN = inputArbs$input_arbs_1_select[2] ;
assign as_inputArbGrants_reg_1_2$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_1_3
assign as_inputArbGrants_reg_1_3$D_IN = inputArbs$input_arbs_1_select[3] ;
assign as_inputArbGrants_reg_1_3$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_1_4
assign as_inputArbGrants_reg_1_4$D_IN = inputArbs$input_arbs_1_select[4] ;
assign as_inputArbGrants_reg_1_4$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_2
assign as_inputArbGrants_reg_2$D_IN = inputArbs$input_arbs_2_select[0] ;
assign as_inputArbGrants_reg_2$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_2_1
assign as_inputArbGrants_reg_2_1$D_IN = inputArbs$input_arbs_2_select[1] ;
assign as_inputArbGrants_reg_2_1$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_2_2
assign as_inputArbGrants_reg_2_2$D_IN = inputArbs$input_arbs_2_select[2] ;
assign as_inputArbGrants_reg_2_2$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_2_3
assign as_inputArbGrants_reg_2_3$D_IN = inputArbs$input_arbs_2_select[3] ;
assign as_inputArbGrants_reg_2_3$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_2_4
assign as_inputArbGrants_reg_2_4$D_IN = inputArbs$input_arbs_2_select[4] ;
assign as_inputArbGrants_reg_2_4$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_3
assign as_inputArbGrants_reg_3$D_IN = inputArbs$input_arbs_3_select[0] ;
assign as_inputArbGrants_reg_3$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_3_1
assign as_inputArbGrants_reg_3_1$D_IN = inputArbs$input_arbs_3_select[1] ;
assign as_inputArbGrants_reg_3_1$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_3_2
assign as_inputArbGrants_reg_3_2$D_IN = inputArbs$input_arbs_3_select[2] ;
assign as_inputArbGrants_reg_3_2$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_3_3
assign as_inputArbGrants_reg_3_3$D_IN = inputArbs$input_arbs_3_select[3] ;
assign as_inputArbGrants_reg_3_3$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_3_4
assign as_inputArbGrants_reg_3_4$D_IN = inputArbs$input_arbs_3_select[4] ;
assign as_inputArbGrants_reg_3_4$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_4
assign as_inputArbGrants_reg_4$D_IN = inputArbs$input_arbs_4_select[0] ;
assign as_inputArbGrants_reg_4$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_4_1
assign as_inputArbGrants_reg_4_1$D_IN = inputArbs$input_arbs_4_select[1] ;
assign as_inputArbGrants_reg_4_1$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_4_2
assign as_inputArbGrants_reg_4_2$D_IN = inputArbs$input_arbs_4_select[2] ;
assign as_inputArbGrants_reg_4_2$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_4_3
assign as_inputArbGrants_reg_4_3$D_IN = inputArbs$input_arbs_4_select[3] ;
assign as_inputArbGrants_reg_4_3$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_4_4
assign as_inputArbGrants_reg_4_4$D_IN = inputArbs$input_arbs_4_select[4] ;
assign as_inputArbGrants_reg_4_4$EN = EN_allocate && pipeline ;
// submodule inputArbs
assign inputArbs$input_arbs_0_select_requests = allocate_alloc_input[4:0] ;
assign inputArbs$input_arbs_1_select_requests = allocate_alloc_input[9:5] ;
assign inputArbs$input_arbs_2_select_requests =
allocate_alloc_input[14:10] ;
assign inputArbs$input_arbs_3_select_requests =
allocate_alloc_input[19:15] ;
assign inputArbs$input_arbs_4_select_requests =
allocate_alloc_input[24:20] ;
assign inputArbs$EN_input_arbs_0_next = EN_next ;
assign inputArbs$EN_input_arbs_1_next = EN_next ;
assign inputArbs$EN_input_arbs_2_next = EN_next ;
assign inputArbs$EN_input_arbs_3_next = EN_next ;
assign inputArbs$EN_input_arbs_4_next = EN_next ;
// submodule outputArbs
assign outputArbs$output_arbs_0_select_requests =
pipeline ?
{ as_inputArbGrants_reg_4,
as_inputArbGrants_reg_3,
as_inputArbGrants_reg_2,
as_inputArbGrants_reg_1,
as_inputArbGrants_reg_0 } :
{ inputArbs$input_arbs_4_select[0],
inputArbs$input_arbs_3_select[0],
inputArbs$input_arbs_2_select[0],
inputArbs$input_arbs_1_select[0],
inputArbs$input_arbs_0_select[0] } ;
assign outputArbs$output_arbs_1_select_requests =
pipeline ?
{ as_inputArbGrants_reg_4_1,
as_inputArbGrants_reg_3_1,
as_inputArbGrants_reg_2_1,
as_inputArbGrants_reg_1_1,
as_inputArbGrants_reg_0_1 } :
{ inputArbs$input_arbs_4_select[1],
inputArbs$input_arbs_3_select[1],
inputArbs$input_arbs_2_select[1],
inputArbs$input_arbs_1_select[1],
inputArbs$input_arbs_0_select[1] } ;
assign outputArbs$output_arbs_2_select_requests =
pipeline ?
{ as_inputArbGrants_reg_4_2,
as_inputArbGrants_reg_3_2,
as_inputArbGrants_reg_2_2,
as_inputArbGrants_reg_1_2,
as_inputArbGrants_reg_0_2 } :
{ inputArbs$input_arbs_4_select[2],
inputArbs$input_arbs_3_select[2],
inputArbs$input_arbs_2_select[2],
inputArbs$input_arbs_1_select[2],
inputArbs$input_arbs_0_select[2] } ;
assign outputArbs$output_arbs_3_select_requests =
pipeline ?
{ as_inputArbGrants_reg_4_3,
as_inputArbGrants_reg_3_3,
as_inputArbGrants_reg_2_3,
as_inputArbGrants_reg_1_3,
as_inputArbGrants_reg_0_3 } :
{ inputArbs$input_arbs_4_select[3],
inputArbs$input_arbs_3_select[3],
inputArbs$input_arbs_2_select[3],
inputArbs$input_arbs_1_select[3],
inputArbs$input_arbs_0_select[3] } ;
assign outputArbs$output_arbs_4_select_requests =
pipeline ?
{ as_inputArbGrants_reg_4_4,
as_inputArbGrants_reg_3_4,
as_inputArbGrants_reg_2_4,
as_inputArbGrants_reg_1_4,
as_inputArbGrants_reg_0_4 } :
{ inputArbs$input_arbs_4_select[4],
inputArbs$input_arbs_3_select[4],
inputArbs$input_arbs_2_select[4],
inputArbs$input_arbs_1_select[4],
inputArbs$input_arbs_0_select[4] } ;
assign outputArbs$EN_output_arbs_0_next = EN_next ;
assign outputArbs$EN_output_arbs_1_next = EN_next ;
assign outputArbs$EN_output_arbs_2_next = EN_next ;
assign outputArbs$EN_output_arbs_3_next = EN_next ;
assign outputArbs$EN_output_arbs_4_next = EN_next ;
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
as_inputArbGrants_reg_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_0_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_0_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_0_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_0_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_1_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_1_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_1_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_2_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_2_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_2_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_2_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_3_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_3_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_3_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_3_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_4_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_4_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_4_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_4_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (as_inputArbGrants_reg_0$EN)
as_inputArbGrants_reg_0 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_0$D_IN;
if (as_inputArbGrants_reg_0_1$EN)
as_inputArbGrants_reg_0_1 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_0_1$D_IN;
if (as_inputArbGrants_reg_0_2$EN)
as_inputArbGrants_reg_0_2 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_0_2$D_IN;
if (as_inputArbGrants_reg_0_3$EN)
as_inputArbGrants_reg_0_3 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_0_3$D_IN;
if (as_inputArbGrants_reg_0_4$EN)
as_inputArbGrants_reg_0_4 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_0_4$D_IN;
if (as_inputArbGrants_reg_1$EN)
as_inputArbGrants_reg_1 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_1$D_IN;
if (as_inputArbGrants_reg_1_1$EN)
as_inputArbGrants_reg_1_1 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_1_1$D_IN;
if (as_inputArbGrants_reg_1_2$EN)
as_inputArbGrants_reg_1_2 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_1_2$D_IN;
if (as_inputArbGrants_reg_1_3$EN)
as_inputArbGrants_reg_1_3 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_1_3$D_IN;
if (as_inputArbGrants_reg_1_4$EN)
as_inputArbGrants_reg_1_4 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_1_4$D_IN;
if (as_inputArbGrants_reg_2$EN)
as_inputArbGrants_reg_2 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_2$D_IN;
if (as_inputArbGrants_reg_2_1$EN)
as_inputArbGrants_reg_2_1 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_2_1$D_IN;
if (as_inputArbGrants_reg_2_2$EN)
as_inputArbGrants_reg_2_2 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_2_2$D_IN;
if (as_inputArbGrants_reg_2_3$EN)
as_inputArbGrants_reg_2_3 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_2_3$D_IN;
if (as_inputArbGrants_reg_2_4$EN)
as_inputArbGrants_reg_2_4 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_2_4$D_IN;
if (as_inputArbGrants_reg_3$EN)
as_inputArbGrants_reg_3 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_3$D_IN;
if (as_inputArbGrants_reg_3_1$EN)
as_inputArbGrants_reg_3_1 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_3_1$D_IN;
if (as_inputArbGrants_reg_3_2$EN)
as_inputArbGrants_reg_3_2 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_3_2$D_IN;
if (as_inputArbGrants_reg_3_3$EN)
as_inputArbGrants_reg_3_3 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_3_3$D_IN;
if (as_inputArbGrants_reg_3_4$EN)
as_inputArbGrants_reg_3_4 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_3_4$D_IN;
if (as_inputArbGrants_reg_4$EN)
as_inputArbGrants_reg_4 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_4$D_IN;
if (as_inputArbGrants_reg_4_1$EN)
as_inputArbGrants_reg_4_1 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_4_1$D_IN;
if (as_inputArbGrants_reg_4_2$EN)
as_inputArbGrants_reg_4_2 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_4_2$D_IN;
if (as_inputArbGrants_reg_4_3$EN)
as_inputArbGrants_reg_4_3 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_4_3$D_IN;
if (as_inputArbGrants_reg_4_4$EN)
as_inputArbGrants_reg_4_4 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_4_4$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
as_inputArbGrants_reg_0 = 1'h0;
as_inputArbGrants_reg_0_1 = 1'h0;
as_inputArbGrants_reg_0_2 = 1'h0;
as_inputArbGrants_reg_0_3 = 1'h0;
as_inputArbGrants_reg_0_4 = 1'h0;
as_inputArbGrants_reg_1 = 1'h0;
as_inputArbGrants_reg_1_1 = 1'h0;
as_inputArbGrants_reg_1_2 = 1'h0;
as_inputArbGrants_reg_1_3 = 1'h0;
as_inputArbGrants_reg_1_4 = 1'h0;
as_inputArbGrants_reg_2 = 1'h0;
as_inputArbGrants_reg_2_1 = 1'h0;
as_inputArbGrants_reg_2_2 = 1'h0;
as_inputArbGrants_reg_2_3 = 1'h0;
as_inputArbGrants_reg_2_4 = 1'h0;
as_inputArbGrants_reg_3 = 1'h0;
as_inputArbGrants_reg_3_1 = 1'h0;
as_inputArbGrants_reg_3_2 = 1'h0;
as_inputArbGrants_reg_3_3 = 1'h0;
as_inputArbGrants_reg_3_4 = 1'h0;
as_inputArbGrants_reg_4 = 1'h0;
as_inputArbGrants_reg_4_1 = 1'h0;
as_inputArbGrants_reg_4_2 = 1'h0;
as_inputArbGrants_reg_4_3 = 1'h0;
as_inputArbGrants_reg_4_4 = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkSepRouterAllocator
|
// Double pumped single precision floating point add
// Latency = 9 kernel clocks
//
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_add_dbl_pumped
#( parameter WIDTH = 32 )
(
input clock,
input clock2x,
input enable,
input resetn,
input [WIDTH-1:0] a1,
input [WIDTH-1:0] b1,
input [WIDTH-1:0] a2,
input [WIDTH-1:0] b2,
output reg [WIDTH-1:0] y1,
output reg [WIDTH-1:0] y2
);
reg [WIDTH-1:0] a1_reg;
reg [WIDTH-1:0] b1_reg;
reg [WIDTH-1:0] a2_reg;
reg [WIDTH-1:0] b2_reg;
// Prevent sharing of these registers across different instances
// (and even kernels!). The sharing may cause very long paths
// across the chip, which limits fmax of clock2x.
reg sel2x /* synthesis preserve */;
wire [WIDTH-1:0] fp_add_sub_inp_a;
wire [WIDTH-1:0] fp_add_sub_inp_b;
wire [WIDTH-1:0] fp_add_sub_res;
initial
begin
sel2x = 1'b0;
end
always@(posedge clock2x)
if (enable)
sel2x<=~sel2x;
//Register before double pumping
reg selector, selector_2x;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
a1_reg <= {WIDTH{1'b0}};
a2_reg <= {WIDTH{1'b0}};
b1_reg <= {WIDTH{1'b0}};
b2_reg <= {WIDTH{1'b0}};
selector <= 1'b0;
end
else if (enable)
begin
a1_reg <= a1;
a2_reg <= a2;
b1_reg <= b1;
b2_reg <= b2;
selector <= sel2x;
end
end
reg [WIDTH-1:0] a1_reg_2x;
reg [WIDTH-1:0] a2_reg_2x;
reg [WIDTH-1:0] b1_reg_2x;
reg [WIDTH-1:0] b2_reg_2x;
// Clock domain transfer
always@(posedge clock2x)
if (enable)
begin
a1_reg_2x <= a1_reg;
a2_reg_2x <= a2_reg;
b1_reg_2x <= b1_reg;
b2_reg_2x <= b2_reg;
selector_2x <= selector;
end
assign fp_add_sub_inp_a = (sel2x) ? a2_reg_2x : a1_reg_2x;
assign fp_add_sub_inp_b = (sel2x) ? b2_reg_2x : b1_reg_2x;
acl_fp_custom_add the_add(
.resetn(resetn),
.enable(enable),
.clock(clock2x),
.dataa(fp_add_sub_inp_a),
.datab(fp_add_sub_inp_b),
.result(fp_add_sub_res));
//For testing purposes
//always@(posedge clk2x)
//begin
// fp_sub_res1 <= fp_sub_inp_a + fp_sub_inp_b;
// fp_sub_res <= fp_sub_res1;
//end
reg [WIDTH-1:0] res1;
reg [WIDTH-1:0] res2;
reg [WIDTH-1:0] temp;
always@(posedge clock2x)
begin
if (enable)
begin
if (~sel2x == selector_2x)
begin
res1 <= (~selector_2x) ? temp : fp_add_sub_res;
res2 <= (~selector_2x) ? fp_add_sub_res : temp;
end
temp <= fp_add_sub_res;
end
end
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
y1 <= {WIDTH{1'b0}};
y2 <= {WIDTH{1'b0}};
end
else if (enable)
begin
y1 <= res1;
y2 <= res2;
end
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module config_switch1(clock, clock2x, resetn,
i_datain, i_datain_valid, o_datain_stall,
o_dataout, o_dataout_valid, i_dataout_stall,
i_config_settings);
parameter DATA_WIDTH = 1;
parameter NUM_CONFIG_BITS = 59;
parameter NUM_FANINS = 20;
parameter NUM_FANOUTS = 20;
parameter CONFIG_SWITCH_ID = 1;
parameter NUM_CONNECTED_INPUTS = 20;
parameter IMPLEMENTATION_MODE = "RAM";
input clock, clock2x, resetn;
input [NUM_FANINS*DATA_WIDTH-1:0] i_datain;
input [NUM_FANINS-1:0] i_datain_valid;
output [NUM_FANINS-1:0] o_datain_stall;
output [NUM_FANOUTS*DATA_WIDTH-1:0] o_dataout;
output [NUM_FANOUTS-1:0] o_dataout_valid;
input [NUM_FANOUTS-1:0] i_dataout_stall;
input [NUM_CONFIG_BITS-1:0] i_config_settings;
// i_config_settings is currently a concatentation of
// 1 bit (to specify that we are in config mode) and
// 58 bits (from what we wrote in from cra)
// - 7 bits is the config switch ID
// - 1 bit to specify this is fwd or bkwd
// - 10 bits is for the wr_addr for the ram
// - 20 bits data to write to upper ram
// - 20 bits data to write to lower ram
wire to_config_me;
wire to_config_fwd_path, to_config_bkwd_path;
assign to_config_me = i_config_settings[NUM_CONFIG_BITS-1] &
(i_config_settings[57:51] == CONFIG_SWITCH_ID );
assign to_config_fwd_path = to_config_me & ~i_config_settings[50];
assign to_config_bkwd_path = to_config_me & i_config_settings[50];
// double pump the data signal alongside the valid signal
wire [NUM_FANOUTS*DATA_WIDTH-1:0] lower_data_out, upper_data_out;
wire [NUM_FANOUTS-1:0] lower_valid_out, upper_valid_out;
switch10x20_top lower_data ( .clock(clock), .clock2x(clock2x), .resetn(resetn),
.wren(to_config_fwd_path), .data(i_config_settings[19:0]),
.wraddress(i_config_settings[49:40]),
.rdaddress1(i_datain[9:0]),
.rdaddress2(i_datain_valid[9:0]),
.q1(lower_data_out[19:0]),
.q2(lower_valid_out));
defparam lower_data.IMPLEMENTATION_MODE = "MLAB";//IMPLEMENTATION_MODE;
generate
if (NUM_CONNECTED_INPUTS > 10)
begin
switch10x20_top upper_data ( .clock(clock), .clock2x(clock2x), .resetn(resetn),
.wren(to_config_fwd_path), .data(i_config_settings[39:20]),
.wraddress(i_config_settings[49:40]),
.rdaddress1(i_datain[19:10]),
.rdaddress2(i_datain_valid[19:10]),
.q1(upper_data_out[19:0]),
.q2(upper_valid_out));
defparam upper_data.IMPLEMENTATION_MODE = "MLAB"; //IMPLEMENTATION_MODE;
end
else
begin
assign upper_data_out = {DATA_WIDTH*NUM_FANOUTS{1'b0}};
assign upper_valid_out = {NUM_FANOUTS{1'b0}};
end
endgenerate
assign o_dataout = lower_data_out | upper_data_out;
assign o_dataout_valid = lower_valid_out | upper_valid_out;
wire [NUM_FANINS-1:0] temp_stalla, temp_stallb;
// make the stall signal
switch10x20 tstalla( .clock(clock), .wren(to_config_bkwd_path),
.data(i_config_settings[19:0]),
.wraddress(i_config_settings[49:40]),
.rdaddress(i_dataout_stall[9:0]),
.q(temp_stalla));
defparam tstalla.IMPLEMENTATION_MODE = "MLAB"; //IMPLEMENTATION_MODE;
switch10x20 tstallb( .clock(clock), .wren(to_config_bkwd_path),
.data(i_config_settings[39:20]),
.wraddress(i_config_settings[49:40]),
.rdaddress(i_dataout_stall[19:10]),
.q(temp_stallb));
defparam tstallb.IMPLEMENTATION_MODE = "MLAB"; //IMPLEMENTATION_MODE;
assign o_datain_stall = temp_stalla | temp_stallb;
endmodule
|
module ForwardingJudgment(
input [1:0] twobeforeop1,
input [2:0] twobeforeop2,twobeforecond,
input [3:0] twobeforeop3,
input [1:0] beforeop1,
input [2:0] beforeop2,beforecond,
input [3:0] beforeop3,
input [1:0] op1,
input [2:0] op2,cond,
input [3:0] op3,
output one_A, one_B, two_A, two_B, MW_One, MW_Two);
reg oA, oB, tA, tB, mwo, mwt;
//one_A
always @ (op1 or op2 or cond or op3 or beforeop1 or beforeop2 or beforecond or beforeop3) begin
if (((beforeop1 == 2'b11
&& beforeop3 >= 4'b0000
&& beforeop3 <= 4'b1100
&& beforeop3 != 4'b0101
&& beforeop3 != 4'b0111)
|| (beforeop1 == 2'b10 && beforeop2 == 3'b001))
&& ((op1 == 2'b11 && ((op3 >= 4'b0000
&& op3 <= 4'b0110)
|| op3 == 4'b1101)))
&& op2 == beforecond)
oA <= 1'b1;
else
oA <= 1'b0;
end
//two_A
always @ (op1 or op2 or cond or op3 or twobeforeop1 or twobeforeop2 or twobeforecond or twobeforeop3) begin
if (((twobeforeop1 == 2'b11
&& twobeforeop3 >= 4'b0000
&& twobeforeop3 <= 4'b1100
&& twobeforeop3 != 4'b0101
&& twobeforeop3 != 4'b0111)
|| (twobeforeop1 == 2'b10 && twobeforeop2 == 3'b001))
&& ((op1 == 2'b11 && ((op3 >= 4'b0000
&& op3 <= 4'b0110)
|| op3 == 4'b1101)))
&& op2 == twobeforecond)
tA <= 1'b1;
else
tA <= 1'b0;
end
//one_B
always @ (op1 or op2 or cond or op3 or beforeop1 or beforeop2 or beforecond or beforeop3) begin
if (((beforeop1 == 2'b11
&& beforeop3 >= 4'b0000
&& beforeop3 <= 4'b1100
&& beforeop3 != 4'b0101
&& beforeop3 != 4'b0111)
|| (beforeop1 == 2'b10 && (beforeop2 == 3'b001 || beforeop2 == 3'b000)))
&& ((op1 == 2'b11 && ((op3 >= 4'b0000
&& op3 <= 4'b0101)
|| (op3 >= 4'b1000
&& op3 <= 4'b1011)))
|| (op1 == 2'b01)
|| (op1 == 2'b00)
|| (op1 == 2'b10 && (op2 == 3'b001
|| op2 == 3'b010
|| op2 == 3'b110)))
&& cond == beforecond)
oB <= 1'b1;
else
oB <= 1'b0;
end
//two_B
always @ (op1 or op2 or cond or op3 or twobeforeop1 or twobeforeop2 or twobeforecond or twobeforeop3) begin
if (((twobeforeop1 == 2'b11
&& twobeforeop3 >= 4'b0000
&& twobeforeop3 <= 4'b1100
&& twobeforeop3 != 4'b0101
&& twobeforeop3 != 4'b0111)
|| (twobeforeop1 == 2'b10 && (twobeforeop2 == 3'b001 || twobeforeop2 == 3'b000)))
&& ((op1 == 2'b11 && ((op3 >= 4'b0000
&& op3 <= 4'b0101)
|| (op3 >= 4'b1000
&& op3 <= 4'b1011)))
|| (op1 == 2'b01)
|| (op1 == 2'b00)
|| (op1 == 2'b10 && (op2 == 3'b001
|| op2 == 3'b010
|| op2 == 3'b110)))
&& cond == twobeforecond)
tB <= 1'b1;
else
tB <= 1'b0;
end
//MW_One
always @ (op1 or op2 or cond or op3 or beforeop1 or beforeop2 or beforecond or beforeop3) begin
if (((beforeop1 == 2'b11
&& beforeop3 >= 4'b0000
&& beforeop3 <= 4'b1100
&& beforeop3 != 4'b0101
&& beforeop3 != 4'b0111)
|| (beforeop1 == 2'b10 && (beforeop2 == 3'b001 || beforeop2 == 3'b000)))
&& (op1 == 2'b01 && op2 == beforecond)
|| (((op1 == 2'b10 && op2 == 3'b010)
|| (op1 == 2'b10 && op2 == 3'b110))
&& cond == beforecond))
mwo <= 1'b1;
else
mwo <= 1'b0;
end
//MW_Two
always @ (op1 or op2 or cond or op3 or twobeforeop1 or twobeforeop2 or twobeforecond or twobeforeop3) begin
if (((twobeforeop1 == 2'b11
&& twobeforeop3 >= 4'b0000
&& twobeforeop3 <= 4'b1100
&& twobeforeop3 != 4'b0101
&& twobeforeop3 != 4'b0111)
|| (twobeforeop1 == 2'b10 && (twobeforeop2 == 3'b001 || twobeforeop2 == 3'b000)))
&& (op1 == 2'b01 && op2 == twobeforecond)
|| (((op1 == 2'b10 && op2 == 3'b010)
|| (op1 == 2'b10 && op2 == 3'b110))
&& cond == twobeforecond))
mwt <= 1'b1;
else
mwt <= 1'b0;
end
assign one_A = oA;
assign one_B = oB;
assign two_A = tA;
assign two_B = tB;
assign MW_One = mwo;
assign MW_Two = mwt;
endmodule // ForwardingJudgement
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_txethmac.v ////
/// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2003/01/30 13:33:24 mohor
// When padding was enabled and crc disabled, frame was not ended correctly.
//
// Revision 1.7 2002/02/26 16:24:01 mohor
// RetryCntLatched was unused and removed from design
//
// Revision 1.6 2002/02/22 12:56:35 mohor
// Retry is not activated when a Tx Underrun occured
//
// Revision 1.5 2002/02/11 09:18:22 mohor
// Tx status is written back to the BD.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:08 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:58 mohor
// TxEthMAC initial release.
//
//
//
`include "timescale.v"
module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
LateCollision, DeferIndication, StatePreamble, StateData
);
parameter Tp = 1;
input MTxClk; // Transmit clock (from PHY)
input Reset; // Reset
input TxStartFrm; // Transmit packet start frame
input TxEndFrm; // Transmit packet end frame
input TxUnderRun; // Transmit packet under-run
input [7:0] TxData; // Transmit packet data byte
input CarrierSense; // Carrier sense (synchronized)
input Collision; // Collision (synchronized)
input Pad; // Pad enable (from register)
input CrcEn; // Crc enable (from register)
input FullD; // Full duplex (from register)
input HugEn; // Huge packets enable (from register)
input DlyCrcEn; // Delayed Crc enabled (from register)
input [15:0] MinFL; // Minimum frame length (from register)
input [15:0] MaxFL; // Maximum frame length (from register)
input [6:0] IPGT; // Back to back transmit inter packet gap parameter (from register)
input [6:0] IPGR1; // Non back to back transmit inter packet gap parameter IPGR1 (from register)
input [6:0] IPGR2; // Non back to back transmit inter packet gap parameter IPGR2 (from register)
input [5:0] CollValid; // Valid collision window (from register)
input [3:0] MaxRet; // Maximum retry number (from register)
input NoBckof; // No backoff (from register)
input ExDfrEn; // Excessive defferal enable (from register)
output [3:0] MTxD; // Transmit nibble (to PHY)
output MTxEn; // Transmit enable (to PHY)
output MTxErr; // Transmit error (to PHY)
output TxDone; // Transmit packet done (to RISC)
output TxRetry; // Transmit packet retry (to RISC)
output TxAbort; // Transmit packet abort (to RISC)
output TxUsedData; // Transmit packet used data (to RISC)
output WillTransmit; // Will transmit (to RxEthMAC)
output ResetCollision; // Reset Collision (for synchronizing collision)
output [3:0] RetryCnt; // Latched Retry Counter for tx status purposes
output StartTxDone;
output StartTxAbort;
output MaxCollisionOccured;
output LateCollision;
output DeferIndication;
output StatePreamble;
output [1:0] StateData;
reg [3:0] MTxD;
reg MTxEn;
reg MTxErr;
reg TxDone;
reg TxRetry;
reg TxAbort;
reg TxUsedData;
reg WillTransmit;
reg ColWindow;
reg StopExcessiveDeferOccured;
reg [3:0] RetryCnt;
reg [3:0] MTxD_d;
reg StatusLatch;
reg PacketFinished_q;
reg PacketFinished;
wire ExcessiveDeferOccured;
wire StartIPG;
wire StartPreamble;
wire [1:0] StartData;
wire StartFCS;
wire StartJam;
wire StartDefer;
wire StartBackoff;
wire StateDefer;
wire StateIPG;
wire StateIdle;
wire StatePAD;
wire StateFCS;
wire StateJam;
wire StateJam_q;
wire StateBackOff;
wire StateSFD;
wire StartTxRetry;
wire UnderRun;
wire TooBig;
wire [31:0] Crc;
wire CrcError;
wire [2:0] DlyCrcCnt;
wire [15:0] NibCnt;
wire NibCntEq7;
wire NibCntEq15;
wire NibbleMinFl;
wire ExcessiveDefer;
wire [15:0] ByteCnt;
wire MaxFrame;
wire RetryMax;
wire RandomEq0;
wire RandomEqByteCnt;
wire PacketFinished_d;
assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & ~CrcEn);
assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
// assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
assign StateSFD = StatePreamble & NibCntEq15;
assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
// StopExcessiveDeferOccured
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
StopExcessiveDeferOccured <= #Tp 1'b0;
else
begin
if(~TxStartFrm)
StopExcessiveDeferOccured <= #Tp 1'b0;
else
if(ExcessiveDeferOccured)
StopExcessiveDeferOccured <= #Tp 1'b1;
end
end
// Collision Window
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ColWindow <= #Tp 1'b1;
else
begin
if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
ColWindow <= #Tp 1'b0;
else
if(StateIdle | StateIPG)
ColWindow <= #Tp 1'b1;
end
end
// Start Window
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
StatusLatch <= #Tp 1'b0;
else
begin
if(~TxStartFrm)
StatusLatch <= #Tp 1'b0;
else
if(ExcessiveDeferOccured | StateIdle)
StatusLatch <= #Tp 1'b1;
end
end
// Transmit packet used data
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxUsedData <= #Tp 1'b0;
else
TxUsedData <= #Tp |StartData;
end
// Transmit packet done
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxDone <= #Tp 1'b0;
else
begin
if(TxStartFrm & ~StatusLatch)
TxDone <= #Tp 1'b0;
else
if(StartTxDone)
TxDone <= #Tp 1'b1;
end
end
// Transmit packet retry
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxRetry <= #Tp 1'b0;
else
begin
if(TxStartFrm & ~StatusLatch)
TxRetry <= #Tp 1'b0;
else
if(StartTxRetry)
TxRetry <= #Tp 1'b1;
end
end
// Transmit packet abort
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxAbort <= #Tp 1'b0;
else
begin
if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
TxAbort <= #Tp 1'b0;
else
if(StartTxAbort)
TxAbort <= #Tp 1'b1;
end
end
// Retry counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RetryCnt[3:0] <= #Tp 4'h0;
else
begin
if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
| StateJam & NibCntEq7 & (~ColWindow | RetryMax))
RetryCnt[3:0] <= #Tp 4'h0;
else
if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
RetryCnt[3:0] <= #Tp RetryCnt[3:0] + 1'b1;
end
end
assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
// Transmit nibble
always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
Crc or NibCntEq15)
begin
if(StateData[0])
MTxD_d[3:0] = TxData[3:0]; // Lower nibble
else
if(StateData[1])
MTxD_d[3:0] = TxData[7:4]; // Higher nibble
else
if(StateFCS)
MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]}; // Crc
else
if(StateJam)
MTxD_d[3:0] = 4'h9; // Jam pattern
else
if(StatePreamble)
if(NibCntEq15)
MTxD_d[3:0] = 4'hd; // SFD
else
MTxD_d[3:0] = 4'h5; // Preamble
else
MTxD_d[3:0] = 4'h0;
end
// Transmit Enable
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxEn <= #Tp 1'b0;
else
MTxEn <= #Tp StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
end
// Transmit nibble
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxD[3:0] <= #Tp 4'h0;
else
MTxD[3:0] <= #Tp MTxD_d[3:0];
end
// Transmit error
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxErr <= #Tp 1'b0;
else
MTxErr <= #Tp TooBig | UnderRun;
end
// WillTransmit
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
WillTransmit <= #Tp 1'b0;
else
WillTransmit <= #Tp StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
end
assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
// Packet finished
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
begin
PacketFinished <= #Tp 1'b0;
PacketFinished_q <= #Tp 1'b0;
end
else
begin
PacketFinished <= #Tp PacketFinished_d;
PacketFinished_q <= #Tp PacketFinished;
end
end
// Connecting module Counters
eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
.StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
.StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
.StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
.Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
.PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
.StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
.NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
.DlyCrcCnt(DlyCrcCnt)
);
// Connecting module StateM
eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
.NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
.TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
.UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
.NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
.NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
.NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
.StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
.StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
.StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
.StartDefer(StartDefer), .DeferIndication(DeferIndication), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
);
wire Enable_Crc;
wire [3:0] Data_Crc;
wire Initialize_Crc;
assign Enable_Crc = ~StateFCS;
assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
// Connecting module Crc
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
.Crc(Crc), .CrcError(CrcError)
);
// Connecting module Random
eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
.NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
// verilator lint_off MULTIDRIVEN
wire [31:0] outb0c0;
wire [31:0] outb0c1;
wire [31:0] outb1c0;
wire [31:0] outb1c1;
reg [7:0] lclmem [7:0];
ma ma0 (.outb0c0(outb0c0), .outb0c1(outb0c1),
.outb1c0(outb1c0), .outb1c1(outb1c1)
);
global_mod #(32'hf00d) global_cell ();
global_mod #(32'hf22d) global_cell2 ();
input clk;
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("[%0t] cyc%0d: %0x %0x %0x %0x\n", $time, cyc, outb0c0, outb0c1, outb1c0, outb1c1);
`endif
if (cyc==2) begin
if (global_cell.globali != 32'hf00d) $stop;
if (global_cell2.globali != 32'hf22d) $stop;
if (outb0c0 != 32'h00) $stop;
if (outb0c1 != 32'h01) $stop;
if (outb1c0 != 32'h10) $stop;
if (outb1c1 != 32'h11) $stop;
end
if (cyc==3) begin
// Can we scope down and read and write vars?
ma0.mb0.mc0.out <= ma0.mb0.mc0.out + 32'h100;
ma0.mb0.mc1.out <= ma0.mb0.mc1.out + 32'h100;
ma0.mb1.mc0.out <= ma0.mb1.mc0.out + 32'h100;
ma0.mb1.mc1.out <= ma0.mb1.mc1.out + 32'h100;
end
if (cyc==4) begin
// Can we do dotted's inside array sels?
ma0.rmtmem[ma0.mb0.mc0.out[2:0]] = 8'h12;
lclmem[ma0.mb0.mc0.out[2:0]] = 8'h24;
if (outb0c0 != 32'h100) $stop;
if (outb0c1 != 32'h101) $stop;
if (outb1c0 != 32'h110) $stop;
if (outb1c1 != 32'h111) $stop;
end
if (cyc==5) begin
if (ma0.rmtmem[ma0.mb0.mc0.out[2:0]] != 8'h12) $stop;
if (lclmem[ma0.mb0.mc0.out[2:0]] != 8'h24) $stop;
if (outb0c0 != 32'h1100) $stop;
if (outb0c1 != 32'h2101) $stop;
if (outb1c0 != 32'h2110) $stop;
if (outb1c1 != 32'h3111) $stop;
end
if (cyc==6) begin
if (outb0c0 != 32'h31100) $stop;
if (outb0c1 != 32'h02101) $stop;
if (outb1c0 != 32'h42110) $stop;
if (outb1c1 != 32'h03111) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
`ifdef USE_INLINE_MID
`define INLINE_MODULE /*verilator inline_module*/
`define INLINE_MID_MODULE /*verilator no_inline_module*/
`else
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`define INLINE_MID_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`define INLINE_MID_MODULE /*verilator public_module*/
`endif
`endif
module global_mod;
`INLINE_MODULE
parameter INITVAL = 0;
integer globali;
initial globali = INITVAL;
endmodule
module ma (
output wire [31:0] outb0c0,
output wire [31:0] outb0c1,
output wire [31:0] outb1c0,
output wire [31:0] outb1c1
);
`INLINE_MODULE
reg [7:0] rmtmem [7:0];
mb #(0) mb0 (.outc0(outb0c0), .outc1(outb0c1));
mb #(1) mb1 (.outc0(outb1c0), .outc1(outb1c1));
endmodule
module mb (
output wire [31:0] outc0,
output wire [31:0] outc1
);
`INLINE_MID_MODULE
parameter P2 = 0;
mc #(P2,0) mc0 (.out(outc0));
mc #(P2,1) mc1 (.out(outc1));
global_mod #(32'hf33d) global_cell2 ();
wire reach_up_clk = t.clk;
always @(reach_up_clk) begin
if (P2==0) begin // Only for mb0
if (outc0 !== t.ma0.mb0.mc0.out) $stop; // Top module name and lower instances
if (outc0 !== ma0.mb0.mc0.out) $stop; // Upper module name and lower instances
if (outc0 !== ma .mb0.mc0.out) $stop; // Upper module name and lower instances
if (outc0 !== mb.mc0.out) $stop; // This module name and lower instances
if (outc0 !== mb0.mc0.out) $stop; // Upper instance name and lower instances
if (outc0 !== mc0.out) $stop; // Lower instances
if (outc1 !== t.ma0.mb0.mc1.out) $stop; // Top module name and lower instances
if (outc1 !== ma0.mb0.mc1.out) $stop; // Upper module name and lower instances
if (outc1 !== ma .mb0.mc1.out) $stop; // Upper module name and lower instances
if (outc1 !== mb.mc1.out) $stop; // This module name and lower instances
if (outc1 !== mb0.mc1.out) $stop; // Upper instance name and lower instances
if (outc1 !== mc1.out) $stop; // Lower instances
end
end
endmodule
module mc (output reg [31:0] out);
`INLINE_MODULE
parameter P2 = 0;
parameter P3 = 0;
initial begin
out = {24'h0,P2[3:0],P3[3:0]};
//$write("%m P2=%0x p3=%0x out=%x\n",P2, P3, out);
end
// Can we look from the top module name down?
wire [31:0] reach_up_cyc = t.cyc;
always @ (posedge t.clk) begin
//$write("[%0t] %m: Got reachup, cyc=%0d\n", $time, reach_up_cyc);
if (reach_up_cyc==2) begin
if (global_cell.globali != 32'hf00d) $stop;
if (global_cell2.globali != 32'hf33d) $stop;
end
if (reach_up_cyc==4) begin
out[15:12] <= {P2[3:0]+P3[3:0]+4'd1};
end
if (reach_up_cyc==5) begin
// Can we set another instance?
if (P3==1) begin // Without this, there are two possible correct answers...
mc0.out[19:16] <= {mc0.out[19:16]+P2[3:0]+P3[3:0]+4'd2};
$display("%m Set %x->%x %x %x %x %x",mc0.out, {mc0.out[19:16]+P2[3:0]+P3[3:0]+4'd2}, mc0.out[19:16],P2[3:0],P3[3:0],4'd2);
end
end
end
endmodule
|
/*
* Copyright (c) 2015, Ziliang Guo
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Wisconsin Robotics nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL WISCONSIN ROBOTICS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module camera_deserializer
(
fmc_la00p_i,
fmc_la00n_i,
fmc_la02p_i,
fmc_la02n_i,
fmc_la03p_i,
fmc_la03n_i,
fmc_la04p_i,
fmc_la04n_i,
fmc_la05p_i,
fmc_la05n_i,
fmc_la14p_i,
fmc_la14n_i,
fmc_la15p_i,
fmc_la15n_i,
fmc_la18p_i,
fmc_la18n_i,
fmc_la19p_i,
fmc_la19n_i,
fmc_la20p_i,
fmc_la20n_i,
fmc_la21p_i,
fmc_la21n_i,
init_camera,
reset_camera,
take_photo,
stop_photo,
cl_locked,
cl_clk_debug,
cl_rd_addr,
cl_data,
uart_cfg_busy,
uart_tx_start_debug,
capture_state_debug,
cmd_gen_state_debug,
counter_debug,
rx_data_debug,
sys_clk_250,
sys_clk_50,
rst
);
input fmc_la00p_i;
input fmc_la00n_i;
input fmc_la02p_i;
input fmc_la02n_i;
input fmc_la03p_i;
input fmc_la03n_i;
input fmc_la04p_i;
input fmc_la04n_i;
input fmc_la05p_i;
input fmc_la05n_i;
input fmc_la14p_i;
input fmc_la14n_i;
output fmc_la15p_i;
output fmc_la15n_i;
output fmc_la18p_i;
output fmc_la18n_i;
output fmc_la19p_i;
output fmc_la19n_i;
output fmc_la20p_i;
output fmc_la20n_i;
output fmc_la21p_i;
output fmc_la21n_i;
input init_camera;
input reset_camera;
input take_photo;
input stop_photo;
output cl_locked;
output [6:0] cl_clk_debug;
input [9:0] cl_rd_addr;
output [15:0] cl_data;
output uart_cfg_busy;
output uart_tx_start_debug;
output [2:0] capture_state_debug;
output [4:0] cmd_gen_state_debug;
output [3:0] counter_debug;
output [7:0] rx_data_debug;
input sys_clk_250;
input sys_clk_50;
input rst;
parameter integer S = 7 ; // Set the serdes factor to 8
parameter integer D = 4 ; // Set the number of inputs and outputs
parameter integer DS = (D*S)-1 ; // Used for bus widths = serdes factor * number of inputs - 1
wire xclk;
wire [3:0] x_net;
wire ser_tfg;
wire ser_tc;
wire [DS:0] rxd ; // Data from serdeses
reg [DS:0] rxr ; // Registered Data from serdeses
wire bitslip;
reg [3:0] count ;
wire [6:0] clk_iserdes_data ;
wire rx_bufpll_lckd;
wire not_bufpll_lckd;
wire rx_serdesstrobe;
wire rx_bufpll_clk_xn;
wire rx_bufg_x1;
wire [7:0] uart_rx_data;
wire [7:0] uart_tx_data;
wire uart_tx_start;
wire uart_tx_busy;
wire uart_rx_valid;
wire uart_rx_idle;
assign uart_tx_start_debug = uart_tx_start;
assign not_bufpll_lckd = ~rx_bufpll_lckd;
assign cl_clk_debug = clk_iserdes_data;
assign cl_locked = rx_bufpll_lckd;
always @ (posedge rx_bufg_x1) // process received data
begin
rxr <= rxd ;
end
camera_link_fmc_bridge camera_link_inst
(
.fmc_la00p_i(fmc_la00p_i),
.fmc_la00n_i(fmc_la00n_i),
.fmc_la02p_i(fmc_la02p_i),
.fmc_la02n_i(fmc_la02n_i),
.fmc_la03p_i(fmc_la03p_i),
.fmc_la03n_i(fmc_la03n_i),
.fmc_la04p_i(fmc_la04p_i),
.fmc_la04n_i(fmc_la04n_i),
.fmc_la05p_i(fmc_la05p_i),
.fmc_la05n_i(fmc_la05n_i),
.fmc_la14p_i(fmc_la14p_i),
.fmc_la14n_i(fmc_la14n_i),
.fmc_la15p_i(fmc_la15p_i),
.fmc_la15n_i(fmc_la15n_i),
.fmc_la18p_i(fmc_la18p_i),
.fmc_la18n_i(fmc_la18n_i),
.fmc_la19p_i(fmc_la19p_i),
.fmc_la19n_i(fmc_la19n_i),
.fmc_la20p_i(fmc_la20p_i),
.fmc_la20n_i(fmc_la20n_i),
.fmc_la21p_i(fmc_la21p_i),
.fmc_la21n_i(fmc_la21n_i),
.xclk(xclk),
.x(x_net),
.cc(4'd0),
.ser_tfg(ser_tfg),
.ser_tc(ser_tc)
);
serdes_1_to_n_clk_pll_s8_diff #(
.S (S),
.CLKIN_PERIOD (11.000),
.PLLD (1),
.PLLX (S),
.BS ("TRUE")) // Parameter to enable bitslip TRUE or FALSE (has to be true for video applications)
inst_clkin (
.x_clk(xclk),
.rxioclk (rx_bufpll_clk_xn),
.pattern1 (7'b1100001), // default values for 7:1 video applications
.pattern2 (7'b1100011),
.rx_serdesstrobe (rx_serdesstrobe),
.rx_bufg_pll_x1 (rx_bufg_x1),
.bitslip (bitslip),
.reset (rst),
.datain (clk_iserdes_data),
.rx_pll_lckd (), // PLL locked - only used if a 2nd BUFPLL is required
.rx_pllout_xs (), // Multiplied PLL clock - only used if a 2nd BUFPLL is required
.rx_bufpll_lckd (rx_bufpll_lckd)) ;
serdes_1_to_n_data_s8_diff #(
.S (S),
.D (D))
inst_datain (
.use_phase_detector (1'b1), // '1' enables the phase detector logic
.input_data(x_net),
.rxioclk (rx_bufpll_clk_xn),
.rxserdesstrobe (rx_serdesstrobe),
.gclk (rx_bufg_x1),
.bitslip (bitslip),
.reset (not_bufpll_lckd),
.data_out (rxd),
.debug_in (2'b00),
.debug ());
cameralink_parser cameralink_parser_inst
(
.take_photo(take_photo),
.reset_state(reset_camera),
.xdata(rxr),
.cl_clk(rx_bufg_x1),
.sys_clk(sys_clk_50),
.rst(rst),
.pixel_rd_addr(cl_rd_addr),
.pixel_rd_data(cl_data),
.capture_state_debug(capture_state_debug)
);
uart cl_uart
(
.clk(sys_clk_50),
.txd(uart_tx_data),
.tx_start(uart_tx_start),
.tx_busy(uart_tx_busy),
.tx_out(ser_tc),
.rxd(uart_rx_data),
.rx_valid(uart_rx_valid),
.rx_in(ser_tfg),
.rx_idle(uart_rx_idle)
);
camera_serial_command_generator camera_serial_command_generator_inst
(
.init_camera(init_camera),
.take_photo(take_photo),
.stop_photo(stop_photo),
.tx_data(uart_tx_data),
.tx_en(uart_tx_start),
.tx_busy(uart_tx_busy),
.rx_data(uart_rx_data),
.rx_done(uart_rx_valid),
.sys_clk_50(sys_clk_50),
.rst(reset_camera),
.busy(uart_cfg_busy),
.cmd_gen_state_debug(cmd_gen_state_debug),
.counter_debug(counter_debug),
.rx_data_debug(rx_data_debug)
);
endmodule |
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_sysid_qsys (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1494178640 : 2899645186;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKBUF_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__CLKBUF_PP_SYMBOL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__clkbuf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKBUF_PP_SYMBOL_V
|
/*
* @Author: tmh
* @Date: 2017-07-24 21:35:44
* @File Name: ControlUnit.v
*/
`include "define.v"
module ControlUnit (
input clk , // Clock
input rst_n , // Asynchronous reset active low
input [ `INST_WIDTH-1:0] instIn , // Instruction in
output [ `FE_STATE_BITS-1:0] fetchState , // Fetch state
output [ `EX_STATE_BITS-1:0] executeState, // Execute State
output [`ALU_FUNC_WIDTH-1:0] aluFuncOut , // ALU out
output [ 1:0] stackCommand // Stack control command
);
// Fetch & EXecute State Control
reg[`FE_STATE_BITS - 1 : 0] currentFetchState;
reg[`EX_STATE_BITS - 1 : 0] currentExecuteState;
reg[`FE_STATE_BITS - 1 : 0] nextFetchState;
reg[`EX_STATE_BITS - 1 : 0] nextExecuteState;
//execute, fetch state transition
assign fetchState = currentFetchState;
assign executeState = currentExecuteState;
assign stackCommand =
currentExecuteState == `EX_Q4_CALL ?
`STK_PUSH : (currentExecuteState == `EX_Q4_RETLW ? `STK_POP : `STK_NOP);
always @(posedge clk) begin
if(!rst_n) begin
currentFetchState <= `FE_Q3;
currentExecuteState <= `EX_Q3;
end
else begin
currentFetchState <= nextFetchState;
currentExecuteState <= nextExecuteState;
end
end
//ALU function loading
reg[`ALU_FUNC_WIDTH - 1 : 0] aluFuncRetain;
reg [`ALU_FUNC_WIDTH - 1 : 0] aluFunc;
assign aluFuncOut = aluFuncRetain;
always @(posedge clk) begin
if (!rst_n) begin
aluFuncRetain <= `ALU_IDLE;
end
else if (nextExecuteState == `EX_Q3) begin
aluFuncRetain <= aluFunc;
end
end
//Next execute state logic
always @(*) begin
aluFunc = `ALU_IDLE;
case (currentExecuteState)
`EX_Q1: begin
nextExecuteState = `EX_Q2;
end
`EX_Q2: begin
nextExecuteState = `EX_Q3;
casex (instIn[11:6])
`I_ADDWF_6 : aluFunc = `ALU_ADDWF;
`I_ANDWF_6 : aluFunc = `ALU_ANDWF;
`I_COMF_6 : aluFunc = `ALU_COMF;
`I_DECF_6 : aluFunc = `ALU_DECF;
`I_DECFSZ_6 : aluFunc = `ALU_DECF;
`I_INCF_6 : aluFunc = `ALU_INCF;
`I_INCFSZ_6 : aluFunc = `ALU_INCF;
`I_IORWF_6 : aluFunc = `ALU_IORWF;
`I_RLF_6 : aluFunc = `ALU_RLF;
`I_RRF_6 : aluFunc = `ALU_RRF;
`I_SUBWF_6 : aluFunc = `ALU_SUBWF;
`I_SWAPF_6 : aluFunc = `ALU_SWAPF;
`I_XORWF_6 : aluFunc = `ALU_XORWF;
`I_MOVF_6 : aluFunc = `ALU_MOVF;
{`I_BCF_4 , 2'bxx} : aluFunc = `ALU_BCF;
{`I_BSF_4 , 2'bxx} : aluFunc = `ALU_BSF;
{`I_ANDLW_4 , 2'bxx} : aluFunc = `ALU_ANDLW;
{`I_IORLW_4 , 2'bxx} : aluFunc = `ALU_IORLW;
{`I_XORLW_4 , 2'bxx} : aluFunc = `ALU_XORLW;
default : aluFunc = `ALU_IDLE;
endcase
end
`EX_Q3: begin
casex(instIn)
{`I_CLRF_7,5'bx_xxxx}: begin
nextExecuteState = `EX_Q4_CLRF;
end
{`I_CLRW_12}: begin
nextExecuteState = `EX_Q4_CLRW;
end
{`I_DECFSZ_6,6'bxx_xxx},
{`I_INCFSZ_6,6'bxx_xxx}: begin
nextExecuteState = `EX_Q4_FSZ;
end
{`I_MOVF_6,6'bxx_xxxx}: begin
nextExecuteState = `EX_Q4_MOVF;
end
{`I_MOVWF_7,5'bx_xxxx}: begin
nextExecuteState = `EX_Q4_MOVWF;
end
{`I_BTFSC_4,8'bxxxx_xxxx},
{`I_BTFSS_4,8'bxxxx_xxxx}: begin
nextExecuteState = `EX_Q4_BTFSX;
end
{`I_CALL_4,8'bxxxx_xxxx}: begin
nextExecuteState = `EX_Q4_CALL;
end
{`I_CLRWDT_12}: begin
nextExecuteState = `EX_Q4_CLRWDT;
end
{`I_GOTO_3,9'bx_xxxx_xxxx}: begin
nextExecuteState = `EX_Q4_GOTO;
end
{`I_MOVLW_4,8'bxxxx_xxxx}: begin
nextExecuteState = `EX_Q4_MOVLW;
end
{`I_OPTION_12}: begin
nextExecuteState = `EX_Q4_OPTION;
end
{`I_RETLW_4,8'bxxxx_xxxx}: begin
nextExecuteState = `EX_Q4_RETLW;
end
{`I_SLEEP_12}: begin
nextExecuteState = `EX_Q4_SLEEP;
end
{`I_TRIS_9,3'b101},{`I_TRIS_9,3'b110},{`I_TRIS_9,3'b111}: begin
nextExecuteState = `EX_Q4_TRIS;
end
{`I_ADDWF_6,6'bxx_xxxx}: begin
nextExecuteState = `EX_Q4_ELSE;
end
{`I_ANDWF_6,6'bxx_xxxx}: begin
nextExecuteState = `EX_Q4_ELSE;
end
{`I_COMF_6,6'bxx_xxxx}: begin
nextExecuteState = `EX_Q4_ELSE;
end
{`I_DECF_6,6'bxx_xxxx}: begin
nextExecuteState = `EX_Q4_ELSE;
end
{`I_INCF_6,6'bxx_xxxx}: begin
nextExecuteState = `EX_Q4_ELSE;
end
{`I_IORWF_6,6'bxx_xxxx}: begin
nextExecuteState = `EX_Q4_ELSE;
end
{`I_RLF_6,6'bxx_xxxx}: begin
nextExecuteState = `EX_Q4_ELSE;
end
{`I_RRF_6 ,6'bxx_xxxx}: begin
nextExecuteState = `EX_Q4_ELSE;
end
{`I_SUBWF_6,6'bxx_xxxx}: begin
nextExecuteState = `EX_Q4_ELSE;
end
{`I_SWAPF_6,6'bxx_xxxx}: begin
nextExecuteState = `EX_Q4_ELSE;
end
{`I_XORWF_6,6'bxx_xxxx}: begin
nextExecuteState = `EX_Q4_ELSE;
end
{`I_BCF_4,8'bxxxx_xxxx}: begin
nextExecuteState = `EX_Q4_BXF;
end
{`I_BSF_4,8'bxxxx_xxxx}: begin
nextExecuteState = `EX_Q4_BXF;
end
{`I_ANDLW_4,8'bxxxx_xxxx}: begin
nextExecuteState = `EX_Q4_ALUXLW;
end
{`I_IORLW_4,8'bxxxx_xxxx}: begin
nextExecuteState = `EX_Q4_ALUXLW;
end
{`I_XORLW_4,8'bxxxx_xxxx}: begin
nextExecuteState = `EX_Q4_ALUXLW;
end
default: nextExecuteState = `EX_Q4_NOP;
endcase
end
`EX_Q4_CLRF,`EX_Q4_CLRW,`EX_Q4_FSZ,`EX_Q4_MOVF,`EX_Q4_MOVWF,
`EX_Q4_BXF,`EX_Q4_BTFSX,`EX_Q4_CALL,`EX_Q4_CLRWDT,`EX_Q4_GOTO,
`EX_Q4_MOVLW,`EX_Q4_OPTION,`EX_Q4_RETLW,`EX_Q4_SLEEP,`EX_Q4_TRIS,
`EX_Q4_ELSE, `EX_Q4_ALUXLW,`EX_Q4_NOP: begin
nextExecuteState= `EX_Q1;
end
default nextExecuteState = `EX_Q3;
endcase
end
//next fetch state logic
always @(*) begin
case (currentFetchState)
`FE_Q1: begin
nextFetchState = `FE_Q2;
end
`FE_Q2: begin
nextFetchState = `FE_Q3;
end
`FE_Q3: begin
nextFetchState = `FE_Q4;
end
`FE_Q4: begin
nextFetchState = `FE_Q1;
end
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Use this file as a template for submitting bugs, etc.
// This module takes a single clock input, and should either
// $write("*-* All Finished *-*\n");
// $finish;
// on success, or $stop.
//
// The code as shown applies a random vector to the Test
// module, then calculates a CRC on the Test module's outputs.
//
// **If you do not wish for your code to be released to the public
// please note it here, otherwise:**
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by ____YOUR_NAME_HERE____.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
// Replace this module with the device under test.
//
// Change the code in the t module to apply values to the inputs and
// merge the output values into the result vector.
input clk;
input [31:0] in;
output reg [31:0] out;
always @(posedge clk) begin
out <= in;
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_0_core_top_pipe_rate.v
// Version : 3.0
//------------------------------------------------------------------------------
// Filename : pipe_rate.v
// Description : PIPE Rate Module for 7 Series Transceiver
// Version : 20.1
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Rate Module --------------------------------------------------
(* DowngradeIPIdentifiedWarnings = "yes" *)
module pcie_7x_0_core_top_pipe_rate #
(
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
parameter TXDATA_WAIT_MAX = 4'd15 // TXDATA wait max
)
(
//---------- Input -------------------------------------
input RATE_CLK,
input RATE_RST_N,
input RATE_RST_IDLE,
input RATE_ACTIVE_LANE,
input [ 1:0] RATE_RATE_IN,
input RATE_CPLLLOCK,
input RATE_QPLLLOCK,
input RATE_MMCM_LOCK,
input RATE_DRP_DONE,
input RATE_RXPMARESETDONE,
input RATE_TXRESETDONE,
input RATE_RXRESETDONE,
input RATE_TXRATEDONE,
input RATE_RXRATEDONE,
input RATE_PHYSTATUS,
input RATE_RESETOVRD_DONE,
input RATE_TXSYNC_DONE,
input RATE_RXSYNC_DONE,
//---------- Output ------------------------------------
output RATE_CPLLPD,
output RATE_QPLLPD,
output RATE_CPLLRESET,
output RATE_QPLLRESET,
output RATE_TXPMARESET,
output RATE_RXPMARESET,
output RATE_DRP_START,
output [ 1:0] RATE_SYSCLKSEL,
output RATE_PCLK_SEL,
output RATE_GEN3,
output RATE_DRP_X16X20_MODE,
output RATE_DRP_X16,
output [ 2:0] RATE_RATE_OUT,
output RATE_RESETOVRD_START,
output RATE_TXSYNC_START,
output RATE_DONE,
output RATE_RXSYNC_START,
output RATE_RXSYNC,
output RATE_IDLE,
output [ 4:0] RATE_FSM
);
//---------- Input FF or Buffer ------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg cplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg cplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_done_reg2;
//---------- Internal Signals --------------------------
wire pll_lock;
wire [ 2:0] rate;
reg [ 3:0] txdata_wait_cnt = 4'd0;
reg txratedone = 1'd0;
reg rxratedone = 1'd0;
reg phystatus = 1'd0;
reg ratedone = 1'd0;
reg gen3_exit = 1'd0;
//---------- Output FF or Buffer -----------------------
reg cpllpd = 1'd0;
reg qpllpd = 1'd0;
reg cpllreset = 1'd0;
reg qpllreset = 1'd0;
reg txpmareset = 1'd0;
reg rxpmareset = 1'd0;
reg [ 1:0] sysclksel = (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
reg gen3 = 1'd0;
reg pclk_sel = 1'd0;
reg [ 2:0] rate_out = 3'd0;
reg drp_start = 1'd0;
reg drp_x16x20_mode = 1'd0;
reg drp_x16 = 1'd0;
reg [4:0] fsm = 0;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 0;
localparam FSM_PLL_PU = 1; // Gen 3 only
localparam FSM_PLL_PURESET = 2; // Gen 3 only
localparam FSM_PLL_LOCK = 3; // Gen 3 or reset only
localparam FSM_DRP_X16_GEN3_START = 4;
localparam FSM_DRP_X16_GEN3_DONE = 5;
localparam FSM_PMARESET_HOLD = 6; // Gen 3 or reset only
localparam FSM_PLL_SEL = 7; // Gen 3 or reset only
localparam FSM_MMCM_LOCK = 8; // Gen 3 or reset only
localparam FSM_DRP_START = 9; // Gen 3 or reset only
localparam FSM_DRP_DONE = 10; // Gen 3 or reset only
localparam FSM_PMARESET_RELEASE = 11; // Gen 3 only
localparam FSM_PMARESET_DONE = 12; // Gen 3 only
localparam FSM_TXDATA_WAIT = 13;
localparam FSM_PCLK_SEL = 14;
localparam FSM_DRP_X16_START = 15;
localparam FSM_DRP_X16_DONE = 16;
localparam FSM_RATE_SEL = 17;
localparam FSM_RXPMARESETDONE = 18;
localparam FSM_DRP_X20_START = 19;
localparam FSM_DRP_X20_DONE = 20;
localparam FSM_RATE_DONE = 21;
localparam FSM_RESETOVRD_START = 22; // PCIe use mode 1.0 only
localparam FSM_RESETOVRD_DONE = 23; // PCIe use mode 1.0 only
localparam FSM_PLL_PDRESET = 24;
localparam FSM_PLL_PD = 25;
localparam FSM_TXSYNC_START = 26;
localparam FSM_TXSYNC_DONE = 27;
localparam FSM_DONE = 28; // Must sync value to pipe_user.v
localparam FSM_RXSYNC_START = 29; // Gen 3 only
localparam FSM_RXSYNC_DONE = 30; // Gen 3 only
//---------- Input FF ----------------------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
//---------- 1st Stage FF --------------------------
rst_idle_reg1 <= 1'd0;
rate_in_reg1 <= 2'd0;
cplllock_reg1 <= 1'd0;
qplllock_reg1 <= 1'd0;
mmcm_lock_reg1 <= 1'd0;
drp_done_reg1 <= 1'd0;
rxpmaresetdone_reg1 <= 1'd0;
txresetdone_reg1 <= 1'd0;
rxresetdone_reg1 <= 1'd0;
txratedone_reg1 <= 1'd0;
rxratedone_reg1 <= 1'd0;
phystatus_reg1 <= 1'd0;
resetovrd_done_reg1 <= 1'd0;
txsync_done_reg1 <= 1'd0;
rxsync_done_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
rst_idle_reg2 <= 1'd0;
rate_in_reg2 <= 2'd0;
cplllock_reg2 <= 1'd0;
qplllock_reg2 <= 1'd0;
mmcm_lock_reg2 <= 1'd0;
drp_done_reg2 <= 1'd0;
rxpmaresetdone_reg2 <= 1'd0;
txresetdone_reg2 <= 1'd0;
rxresetdone_reg2 <= 1'd0;
txratedone_reg2 <= 1'd0;
rxratedone_reg2 <= 1'd0;
phystatus_reg2 <= 1'd0;
resetovrd_done_reg2 <= 1'd0;
txsync_done_reg2 <= 1'd0;
rxsync_done_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
rst_idle_reg1 <= RATE_RST_IDLE;
rate_in_reg1 <= RATE_RATE_IN;
cplllock_reg1 <= RATE_CPLLLOCK;
qplllock_reg1 <= RATE_QPLLLOCK;
mmcm_lock_reg1 <= RATE_MMCM_LOCK;
drp_done_reg1 <= RATE_DRP_DONE;
rxpmaresetdone_reg1 <= RATE_RXPMARESETDONE;
txresetdone_reg1 <= RATE_TXRESETDONE;
rxresetdone_reg1 <= RATE_RXRESETDONE;
txratedone_reg1 <= RATE_TXRATEDONE;
rxratedone_reg1 <= RATE_RXRATEDONE;
phystatus_reg1 <= RATE_PHYSTATUS;
resetovrd_done_reg1 <= RATE_RESETOVRD_DONE;
txsync_done_reg1 <= RATE_TXSYNC_DONE;
rxsync_done_reg1 <= RATE_RXSYNC_DONE;
//---------- 2nd Stage FF --------------------------
rst_idle_reg2 <= rst_idle_reg1;
rate_in_reg2 <= rate_in_reg1;
cplllock_reg2 <= cplllock_reg1;
qplllock_reg2 <= qplllock_reg1;
mmcm_lock_reg2 <= mmcm_lock_reg1;
drp_done_reg2 <= drp_done_reg1;
rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
txresetdone_reg2 <= txresetdone_reg1;
rxresetdone_reg2 <= rxresetdone_reg1;
txratedone_reg2 <= txratedone_reg1;
rxratedone_reg2 <= rxratedone_reg1;
phystatus_reg2 <= phystatus_reg1;
resetovrd_done_reg2 <= resetovrd_done_reg1;
txsync_done_reg2 <= txsync_done_reg1;
rxsync_done_reg2 <= rxsync_done_reg1;
end
end
//---------- Select CPLL or QPLL Lock ------------------------------------------
// Gen1 : Wait for QPLL lock if QPLL is used for Gen1/Gen2, else wait for CPLL lock
// Gen2 : Wait for QPLL lock if QPLL is used for Gen1/Gen2, else wait for CPLL lock
// Gen3 : Wait for QPLL lock
//------------------------------------------------------------------------------
assign pll_lock = (rate_in_reg2 == 2'd2) || (PCIE_PLL_SEL == "QPLL") ? qplllock_reg2 : cplllock_reg2;
//---------- Select Rate -------------------------------------------------------
// Gen1 : Div 4 using [TX/RX]OUT_DIV = 4 if QPLL is used for Gen1/Gen2, else div 2 using [TX/RX]OUT_DIV = 2
// Gen2 : Div 2 using [TX/RX]RATE = 3'd2 if QPLL is used for Gen1/Gen2, else div 1 using [TX/RX]RATE = 3'd1
// Gen3 : Div 1 using [TX/RX]OUT_DIV = 1
//------------------------------------------------------------------------------
assign rate = (rate_in_reg2 == 2'd1) && (PCIE_PLL_SEL == "QPLL") ? 3'd2 :
(rate_in_reg2 == 2'd1) && (PCIE_PLL_SEL == "CPLL") ? 3'd1 : 3'd0;
//---------- TXDATA Wait Counter -----------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
txdata_wait_cnt <= 4'd0;
else
//---------- Increment Wait Counter ----------------
if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt < TXDATA_WAIT_MAX))
txdata_wait_cnt <= txdata_wait_cnt + 4'd1;
//---------- Hold Wait Counter ---------------------
else if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt == TXDATA_WAIT_MAX))
txdata_wait_cnt <= txdata_wait_cnt;
//---------- Reset Wait Counter --------------------
else
txdata_wait_cnt <= 4'd0;
end
//---------- Latch TXRATEDONE, RXRATEDONE, and PHYSTATUS -----------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
txratedone <= 1'd0;
rxratedone <= 1'd0;
phystatus <= 1'd0;
ratedone <= 1'd0;
end
else
begin
if (fsm == FSM_RATE_DONE)
begin
//---------- Latch TXRATEDONE ------------------
if (txratedone_reg2)
txratedone <= 1'd1;
else
txratedone <= txratedone;
//---------- Latch RXRATEDONE ------------------
if (rxratedone_reg2)
rxratedone <= 1'd1;
else
rxratedone <= rxratedone;
//---------- Latch PHYSTATUS -------------------
if (phystatus_reg2)
phystatus <= 1'd1;
else
phystatus <= phystatus;
//---------- Latch Rate Done -------------------
if (rxratedone && txratedone && phystatus)
ratedone <= 1'd1;
else
ratedone <= ratedone;
end
else
begin
txratedone <= 1'd0;
rxratedone <= 1'd0;
phystatus <= 1'd0;
ratedone <= 1'd0;
end
end
end
//---------- PIPE Rate FSM -----------------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
fsm <= FSM_PLL_LOCK;
gen3_exit <= 1'd0;
cpllpd <= 1'd0;
qpllpd <= 1'd0;
cpllreset <= 1'd0;
qpllreset <= 1'd0;
txpmareset <= 1'd0;
rxpmareset <= 1'd0;
sysclksel <= (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
pclk_sel <= 1'd0;
gen3 <= 1'd0;
rate_out <= 3'd0;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
//---------- Detect Rate Change ----------------
if (rate_in_reg2 != rate_in_reg1)
begin
fsm <= ((rate_in_reg2 == 2'd2) || (rate_in_reg1 == 2'd2)) ? FSM_PLL_PU : FSM_TXDATA_WAIT;
gen3_exit <= (rate_in_reg2 == 2'd2);
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
end
//---------- Power-up PLL --------------------------
FSM_PLL_PU :
begin
fsm <= FSM_PLL_PURESET;
gen3_exit <= gen3_exit;
cpllpd <= (PCIE_PLL_SEL == "QPLL");
qpllpd <= 1'd0;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Release PLL Resets --------------------
FSM_PLL_PURESET :
begin
fsm <= FSM_PLL_LOCK;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= (PCIE_PLL_SEL == "QPLL");
qpllreset <= 1'd0;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for PLL Lock ---------------------
FSM_PLL_LOCK :
begin
fsm <= (pll_lock ? ((!rst_idle_reg2 || (rate_in_reg2 == 2'd1)) ? FSM_PMARESET_HOLD : FSM_DRP_X16_GEN3_START) : FSM_PLL_LOCK);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP x16 -------------------------
FSM_DRP_X16_GEN3_START :
begin
fsm <= (!drp_done_reg2) ? FSM_DRP_X16_GEN3_DONE : FSM_DRP_X16_GEN3_START;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Wait for DRP x16 Done -----------------
FSM_DRP_X16_GEN3_DONE :
begin
fsm <= drp_done_reg2 ? FSM_PMARESET_HOLD : FSM_DRP_X16_GEN3_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Hold both PMA in Reset ----------------
// Gen1 : Release PMA Reset
// Gen2 : Release PMA Reset
// Gen3 : Hold PMA Reset
//--------------------------------------------------
FSM_PMARESET_HOLD :
begin
fsm <= FSM_PLL_SEL;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= ((rate_in_reg2 == 2'd2) || gen3_exit);
rxpmareset <= ((rate_in_reg2 == 2'd2) || gen3_exit);
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Select PLL ----------------------------
// Gen1 : QPLL if PCIE_PLL_SEL = QPLL, else CPLL
// Gen2 : QPLL if PCIE_PLL_SEL = QPLL, else CPLL
// Gen3 : QPLL
//--------------------------------------------------
FSM_PLL_SEL :
begin
fsm <= FSM_MMCM_LOCK;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= ((rate_in_reg2 == 2'd2) || (PCIE_PLL_SEL == "QPLL")) ? 2'd1 : 2'd0;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Check for MMCM Lock -------------------
FSM_MMCM_LOCK :
begin
fsm <= (mmcm_lock_reg2 && !rxpmaresetdone_reg2 ? FSM_DRP_START : FSM_MMCM_LOCK);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP -----------------------------
FSM_DRP_START:
begin
fsm <= (!drp_done_reg2 ? FSM_DRP_DONE : FSM_DRP_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= ((rate_in_reg2 == 2'd1) || (rate_in_reg2 == 2'd2));
gen3 <= (rate_in_reg2 == 2'd2);
rate_out <= (((rate_in_reg2 == 2'd2) || gen3_exit) ? rate : rate_out);
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for DRP Done ---------------------
FSM_DRP_DONE :
begin
fsm <= ((drp_done_reg2 && pll_lock) ? (rst_idle_reg2 ? FSM_PMARESET_RELEASE : FSM_IDLE): FSM_DRP_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Release PMA Resets --------------------
FSM_PMARESET_RELEASE :
begin
fsm <= FSM_PMARESET_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= 1'd0;
rxpmareset <= 1'd0;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for both TX/RX PMA Reset Dones and PHYSTATUS Deassertion
FSM_PMARESET_DONE :
begin
fsm <= (((rxresetdone_reg2 && txresetdone_reg2 && !phystatus_reg2) || !RATE_ACTIVE_LANE) ? FSM_TXDATA_WAIT : FSM_PMARESET_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for TXDATA to TX[P/N] Latency ----
FSM_TXDATA_WAIT :
begin
fsm <= (txdata_wait_cnt == TXDATA_WAIT_MAX) ? FSM_PCLK_SEL : FSM_TXDATA_WAIT;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Select PCLK Frequency -----------------
// Gen1 : PCLK = 125 MHz
// Gen2 : PCLK = 250 MHz
// Gen3 : PCLK = 250 MHz
//--------------------------------------------------
FSM_PCLK_SEL :
begin
fsm <= ((PCIE_GT_DEVICE == "GTH") && ((rate_in_reg2 == 2'd1) || ((!gen3_exit) && (rate_in_reg2 == 2'd0)))) ? FSM_DRP_X16_START : FSM_RATE_SEL;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= ((rate_in_reg2 == 2'd1) || (rate_in_reg2 == 2'd2));
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP x16 -------------------------
FSM_DRP_X16_START :
begin
fsm <= (!drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Wait for DRP x16 Done -----------------
FSM_DRP_X16_DONE :
begin
fsm <= drp_done_reg2 ? FSM_RATE_SEL : FSM_DRP_X16_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Select Rate ---------------------------
FSM_RATE_SEL :
begin
fsm <= ((PCIE_GT_DEVICE == "GTH") && ((rate_in_reg2 == 2'd1) || ((!gen3_exit) && (rate_in_reg2 == 2'd0)))) ? FSM_RXPMARESETDONE : FSM_RATE_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate; // Update [TX/RX]RATE
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for RXPMARESETDONE De-assertion --
FSM_RXPMARESETDONE :
begin
fsm <= (!rxpmaresetdone_reg2) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP x20 -------------------------
FSM_DRP_X20_START :
begin
fsm <= (!drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd0;
end
//---------- Wait for DRP x20 Done -----------------
FSM_DRP_X20_DONE :
begin
fsm <= drp_done_reg2 ? FSM_RATE_DONE : FSM_DRP_X20_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd0;
end
//---------- Wait for Rate Change Done -------------
FSM_RATE_DONE :
begin
if (ratedone || (rate_in_reg2 == 2'd2) || (gen3_exit) || !RATE_ACTIVE_LANE)
if ((PCIE_USE_MODE == "1.0") && (rate_in_reg2 != 2'd2) && (!gen3_exit))
fsm <= FSM_RESETOVRD_START;
else
fsm <= FSM_PLL_PDRESET;
else
fsm <= FSM_RATE_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Reset Override Start ------------------
FSM_RESETOVRD_START:
begin
fsm <= (!resetovrd_done_reg2 ? FSM_RESETOVRD_DONE : FSM_RESETOVRD_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Reset Override Done -------------------
FSM_RESETOVRD_DONE :
begin
fsm <= (resetovrd_done_reg2 ? FSM_PLL_PDRESET : FSM_RESETOVRD_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Hold PLL Not Used in Reset ------------
FSM_PLL_PDRESET :
begin
fsm <= FSM_PLL_PD;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= (PCIE_PLL_SEL == "QPLL") ? 1'd1 : (rate_in_reg2 == 2'd2);
qpllreset <= (PCIE_PLL_SEL == "QPLL") ? 1'd0 : (rate_in_reg2 != 2'd2);
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Power-Down PLL Not Used ---------------
FSM_PLL_PD :
begin
fsm <= (((rate_in_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? FSM_TXSYNC_START : FSM_DONE);
gen3_exit <= gen3_exit;
cpllpd <= (PCIE_PLL_SEL == "QPLL") ? 1'd1 : (rate_in_reg2 == 2'd2);
qpllpd <= (PCIE_PLL_SEL == "QPLL") ? 1'd0 : (rate_in_reg2 != 2'd2);
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start TX Sync -------------------------
FSM_TXSYNC_START:
begin
fsm <= (!txsync_done_reg2 ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for TX Sync Done -----------------
FSM_TXSYNC_DONE:
begin
fsm <= (txsync_done_reg2 ? FSM_DONE : FSM_TXSYNC_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Rate Change Done ----------------------
FSM_DONE :
begin
fsm <= (((rate_in_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE") && (PCIE_ASYNC_EN == "TRUE")) ? FSM_RXSYNC_START : FSM_IDLE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start RX Sync -------------------------
FSM_RXSYNC_START:
begin
fsm <= (!rxsync_done_reg2 ? FSM_RXSYNC_DONE : FSM_RXSYNC_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for RX Sync Done -----------------
FSM_RXSYNC_DONE:
begin
fsm <= (rxsync_done_reg2 ? FSM_IDLE : FSM_RXSYNC_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
gen3_exit <= 1'd0;
cpllpd <= 1'd0;
qpllpd <= 1'd0;
cpllreset <= 1'd0;
qpllreset <= 1'd0;
txpmareset <= 1'd0;
rxpmareset <= 1'd0;
sysclksel <= (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
pclk_sel <= 1'd0;
gen3 <= 1'd0;
rate_out <= 3'd0;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
endcase
end
end
//---------- PIPE Rate Output --------------------------------------------------
assign RATE_CPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllpd);
assign RATE_QPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllpd);
assign RATE_CPLLRESET = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllreset);
assign RATE_QPLLRESET = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllreset);
assign RATE_TXPMARESET = txpmareset;
assign RATE_RXPMARESET = rxpmareset;
assign RATE_SYSCLKSEL = sysclksel;
//assign RATE_DRP_START = (fsm == FSM_DRP_START) || (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
assign RATE_DRP_START = drp_start;
//assign RATE_DRP_X16X20_MODE = (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_GEN3_DONE) ||
// (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE) ||
// (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE);
assign RATE_DRP_X16X20_MODE = drp_x16x20_mode;
//assign RATE_DRP_X16 = (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_GEN3_DONE) ||
// (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
assign RATE_DRP_X16 = drp_x16;
assign RATE_PCLK_SEL = pclk_sel;
assign RATE_GEN3 = gen3;
assign RATE_RATE_OUT = rate_out;
assign RATE_RESETOVRD_START = (fsm == FSM_RESETOVRD_START);
assign RATE_TXSYNC_START = (fsm == FSM_TXSYNC_START);
assign RATE_DONE = (fsm == FSM_DONE);
assign RATE_RXSYNC_START = (fsm == FSM_RXSYNC_START);
assign RATE_RXSYNC = ((fsm == FSM_RXSYNC_START) || (fsm == FSM_RXSYNC_DONE));
assign RATE_IDLE = (fsm == FSM_IDLE);
assign RATE_FSM = fsm;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/07/2015 06:36:58 PM
// Design Name:
// Module Name: m_port_ultra_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module m_port_ultra_top (
input CLK100MHZ,
input [15:0] SW,
input BTNC, BTNU, BTND, BTNL, BTNR,
input CPU_RESETN,
output [15:0] LED,
output CA, output CB, output CC, output CD, output CE, output CF, output CG, output DP,
output [7:0] AN
);
// Wire declarations -- Ouputs for FSM
wire [4095:0] convexPoints;
wire [7:0] convexSetSize;
//SSD
reg [4:0] SSD;
reg [7:0] SSD_CATHODES;
reg [3:0] count;
wire [31:0] outputResult;
reg scan_ca;
assign AN[0] = scan_ca;
//DP is always off, thus 1'b1
assign {CA, CB, CC, CD, CE, CF, CG, DP} = { SSD_CATHODES, 1'b1};
// Clock divider
reg [26:0] DIV_CLK;
always @(posedge CLK100MHZ, negedge CPU_RESETN) begin
if (!CPU_RESETN) begin
DIV_CLK <= 0;
end
else begin
DIV_CLK <= DIV_CLK + 1'b1;
end
end
// Module declaration
m_port_ultra portableUltrasoundFSM (
.clk (CLK100MHZ),
.slowClk (DIV_CLK[25:24]),
.reset_n (CPU_RESETN),
.ack (BTNC),
.shiftRight (BTNR),
.shiftLeft (BTNL),
.convexPoints (convexPoints),
.convexSetSize (convexSetSize)
);
//BCD calculatios
wire [3:0] BCD0, BCD1, BCD2, BCD3, BCD4;
assign BCD4 = (convexSetSize / 10000);
assign BCD3 = (((convexSetSize % 10000) - (convexSetSize % 1000)) / 1000);
assign BCD2 = (((convexSetSize % 1000) - (convexSetSize % 100)) / 100);
assign BCD1 = (((convexSetSize % 100) - (convexSetSize % 10)) / 10);
assign BCD0 = (((convexSetSize % 10) - (convexSetSize % 1)) / 1);
// SSD Display Cycler
assign outputResult [31:28] = 4'b0000;
assign outputResult [27:24] = 4'b0000;
assign outputResult [23:20] = 4'b0000;
assign outputResult [19:16] = BCD4;
assign outputResult [15:12] = BCD3;
assign outputResult [11:8] = BCD2;
assign outputResult [7:4] = BCD1;
assign outputResult [3:0] = BCD0;
//SSD display code
wire[2:0] ssdscan_clk;
assign ssdscan_clk = DIV_CLK[19:17];
assign AN[0] = !( (~(ssdscan_clk[2])) && ~(ssdscan_clk[1]) && ~(ssdscan_clk[0]) );
assign AN[1] = !( (~(ssdscan_clk[2])) && ~(ssdscan_clk[1]) && (ssdscan_clk[0]) );
assign AN[2] = !( (~(ssdscan_clk[2])) && (ssdscan_clk[1]) && ~(ssdscan_clk[0]) );
assign AN[3] = !( (~(ssdscan_clk[2])) && (ssdscan_clk[1]) && (ssdscan_clk[0]) );
assign AN[4] = !( ( (ssdscan_clk[2])) && ~(ssdscan_clk[1]) && ~(ssdscan_clk[0]) );
assign AN[5] = !( ( (ssdscan_clk[2])) && ~(ssdscan_clk[1]) && (ssdscan_clk[0]) );
assign AN[6] = !( ( (ssdscan_clk[2])) && (ssdscan_clk[1]) && ~(ssdscan_clk[0]) );
assign AN[7] = !( ( (ssdscan_clk[2])) && (ssdscan_clk[1]) && (ssdscan_clk[0]) );
wire[3:0] SSD7, SSD6, SSD5, SSD4, SSD3, SSD2, SSD1, SSD0;
assign SSD7 = outputResult[31:28];
assign SSD6 = outputResult[27:24];
assign SSD5 = outputResult[23:20];
assign SSD4 = outputResult[19:16];
assign SSD3 = outputResult[15:12];
assign SSD2 = outputResult[11:8];
assign SSD1 = outputResult[7:4];
assign SSD0 = outputResult[3:0];
always @ (ssdscan_clk, SSD0, SSD1, SSD2, SSD3, SSD4, SSD5, SSD6, SSD7)
begin : SSD_SCAN_OUT
case (ssdscan_clk)
3'b000: SSD = SSD0;
3'b001: SSD = SSD1;
3'b010: SSD = SSD2;
3'b011: SSD = SSD3;
3'b100: SSD = SSD4;
3'b101: SSD = SSD5;
3'b110: SSD = SSD6;
3'b111: SSD = SSD7;
endcase
end
always @ (SSD) begin
case (SSD)
4'b1010: SSD_CATHODES = 7'b0001000 ; // A
4'b1011: SSD_CATHODES = 7'b1100000 ; // B
4'b1100: SSD_CATHODES = 7'b0110001 ; // C
4'b1101: SSD_CATHODES = 7'b1000010 ; // D
4'b1110: SSD_CATHODES = 7'b0110000 ; // E
4'b1111: SSD_CATHODES = 7'b0111000 ; // F
4'b0000: SSD_CATHODES = 7'b0000001 ; // 0
4'b0001: SSD_CATHODES = 7'b1001111 ; // 1
4'b0010: SSD_CATHODES = 7'b0010010 ; // 2
4'b0011: SSD_CATHODES = 7'b0000110 ; // 3
4'b0100: SSD_CATHODES = 7'b1001100 ; // 4
4'b0101: SSD_CATHODES = 7'b0100100 ; // 5
4'b0110: SSD_CATHODES = 7'b0100000 ; // 6
4'b0111: SSD_CATHODES = 7'b0001111 ; // 7
4'b1000: SSD_CATHODES = 7'b0000000 ; // 8
4'b1001: SSD_CATHODES = 7'b0001100 ; // 9
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [3:0] drv_a = crc[3:0];
wire [3:0] drv_b = crc[7:4];
wire [3:0] drv_e = crc[19:16];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [8:0] match1; // From test1 of Test1.v
wire [8:0] match2; // From test2 of Test2.v
// End of automatics
Test1 test1 (/*AUTOINST*/
// Outputs
.match1 (match1[8:0]),
// Inputs
.drv_a (drv_a[3:0]),
.drv_e (drv_e[3:0]));
Test2 test2 (/*AUTOINST*/
// Outputs
.match2 (match2[8:0]),
// Inputs
.drv_a (drv_a[3:0]),
.drv_e (drv_e[3:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {39'h0, match2, 7'h0, match1};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x m1=%x m2=%x (%b??%b:%b)\n",$time, cyc, crc, match1, match2, drv_e,drv_a,drv_b);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hc0c4a2b9aea7c4b4
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test1
(
input wire [3:0] drv_a,
input wire [3:0] drv_e,
output wire [8:0] match1
);
wire [2:1] drv_all;
bufif1 bufa [2:1] (drv_all, drv_a[2:1], drv_e[2:1]);
`ifdef VERILATOR
// At present Verilator only allows comparisons with Zs
assign match1[0] = (drv_a[2:1]== 2'b00 && drv_e[2:1]==2'b11);
assign match1[1] = (drv_a[2:1]== 2'b01 && drv_e[2:1]==2'b11);
assign match1[2] = (drv_a[2:1]== 2'b10 && drv_e[2:1]==2'b11);
assign match1[3] = (drv_a[2:1]== 2'b11 && drv_e[2:1]==2'b11);
`else
assign match1[0] = drv_all === 2'b00;
assign match1[1] = drv_all === 2'b01;
assign match1[2] = drv_all === 2'b10;
assign match1[3] = drv_all === 2'b11;
`endif
assign match1[4] = drv_all === 2'bz0;
assign match1[5] = drv_all === 2'bz1;
assign match1[6] = drv_all === 2'bzz;
assign match1[7] = drv_all === 2'b0z;
assign match1[8] = drv_all === 2'b1z;
endmodule
module Test2
(
input wire [3:0] drv_a,
input wire [3:0] drv_e,
output wire [8:0] match2
);
wire [2:1] drv_all;
bufif1 bufa [2:1] (drv_all, drv_a[2:1], drv_e[2:1]);
`ifdef VERILATOR
assign match2[0] = (drv_all !== 2'b00 || drv_e[2:1]!=2'b11);
assign match2[1] = (drv_all !== 2'b01 || drv_e[2:1]!=2'b11);
assign match2[2] = (drv_all !== 2'b10 || drv_e[2:1]!=2'b11);
assign match2[3] = (drv_all !== 2'b11 || drv_e[2:1]!=2'b11);
`else
assign match2[0] = drv_all !== 2'b00;
assign match2[1] = drv_all !== 2'b01;
assign match2[2] = drv_all !== 2'b10;
assign match2[3] = drv_all !== 2'b11;
`endif
assign match2[4] = drv_all !== 2'bz0;
assign match2[5] = drv_all !== 2'bz1;
assign match2[6] = drv_all !== 2'bzz;
assign match2[7] = drv_all !== 2'b0z;
assign match2[8] = drv_all !== 2'b1z;
endmodule
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