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/***************************************************************************************************
** fpga_nes/hw/src/ppu/ppu_vga.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* VGA output PPU sub-block.
***************************************************************************************************/
module ppu_vga
(
input wire clk_in, // 100MHz system clock signal
input wire rst_in, // reset signal
input wire [5:0] sys_palette_idx_in, // system palette index (selects output color)
output wire hsync_out, // vga hsync signal
output wire vsync_out, // vga vsync signal
output wire [2:0] r_out, // vga red signal
output wire [2:0] g_out, // vga green signal
output wire [1:0] b_out, // vga blue signal
output wire [9:0] nes_x_out, // nes x coordinate
output wire [9:0] nes_y_out, // nes y coordinate
output wire [9:0] nes_y_next_out, // next line's nes y coordinate
output wire pix_pulse_out, // 1 clk pulse prior to nes_x update
output wire vblank_out // indicates a vblank is occuring (no PPU vram access)
);
// Display dimensions (640x480).
localparam [9:0] DISPLAY_W = 10'h280,
DISPLAY_H = 10'h1E0;
// NES screen dimensions (256x240).
localparam [9:0] NES_W = 10'h100,
NES_H = 10'h0F0;
// Border color (surrounding NES screen).
localparam [7:0] BORDER_COLOR = 8'h49;
//
// VGA_SYNC: VGA synchronization control block.
//
wire sync_en; // vga enable signal
wire [9:0] sync_x; // current vga x coordinate
wire [9:0] sync_y; // current vga y coordinate
wire [9:0] sync_x_next; // vga x coordinate for next clock
wire [9:0] sync_y_next; // vga y coordinate for next line
vga_sync vga_sync_blk(
.clk(clk_in),
.hsync(hsync_out),
.vsync(vsync_out),
.en(sync_en),
.x(sync_x),
.y(sync_y),
.x_next(sync_x_next),
.y_next(sync_y_next)
);
//
// Registers.
//
reg [7:0] q_rgb; // output color latch (1 clk delay required by vga_sync)
reg [7:0] d_rgb;
reg q_vblank; // current vblank state
wire d_vblank;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_rgb <= 8'h00;
q_vblank <= 1'h0;
end
else
begin
q_rgb <= d_rgb;
q_vblank <= d_vblank;
end
end
//
// Coord and timing signals.
//
wire [9:0] nes_x_next; // nes x coordinate for next clock
wire border; // indicates we are displaying a vga pixel outside the nes extents
assign nes_x_out = (sync_x - 10'h040) >> 1;
assign nes_y_out = sync_y >> 1;
assign nes_x_next = (sync_x_next - 10'h040) >> 1;
assign nes_y_next_out = sync_y_next >> 1;
assign border = (nes_x_out >= NES_W) || (nes_y_out < 8) || (nes_y_out >= (NES_H - 8));
//
// Lookup RGB values based on sys_palette_idx.
//
always @*
begin
if (!sync_en)
begin
d_rgb = 8'h00;
end
else if (border)
begin
d_rgb = BORDER_COLOR;
end
else
begin
// Lookup RGB values based on sys_palette_idx. Table is an approximation of the NES
// system palette. Taken from http://nesdev.parodius.com/NESTechFAQ.htm#nessnescompat.
case (sys_palette_idx_in)
6'h00: d_rgb = { 3'h3, 3'h3, 2'h1 };
6'h01: d_rgb = { 3'h1, 3'h0, 2'h2 };
6'h02: d_rgb = { 3'h0, 3'h0, 2'h2 };
6'h03: d_rgb = { 3'h2, 3'h0, 2'h2 };
6'h04: d_rgb = { 3'h4, 3'h0, 2'h1 };
6'h05: d_rgb = { 3'h5, 3'h0, 2'h0 };
6'h06: d_rgb = { 3'h5, 3'h0, 2'h0 };
6'h07: d_rgb = { 3'h3, 3'h0, 2'h0 };
6'h08: d_rgb = { 3'h2, 3'h1, 2'h0 };
6'h09: d_rgb = { 3'h0, 3'h2, 2'h0 };
6'h0a: d_rgb = { 3'h0, 3'h2, 2'h0 };
6'h0b: d_rgb = { 3'h0, 3'h1, 2'h0 };
6'h0c: d_rgb = { 3'h0, 3'h1, 2'h1 };
6'h0d: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h0e: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h0f: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h10: d_rgb = { 3'h5, 3'h5, 2'h2 };
6'h11: d_rgb = { 3'h0, 3'h3, 2'h3 };
6'h12: d_rgb = { 3'h1, 3'h1, 2'h3 };
6'h13: d_rgb = { 3'h4, 3'h0, 2'h3 };
6'h14: d_rgb = { 3'h5, 3'h0, 2'h2 };
6'h15: d_rgb = { 3'h7, 3'h0, 2'h1 };
6'h16: d_rgb = { 3'h6, 3'h1, 2'h0 };
6'h17: d_rgb = { 3'h6, 3'h2, 2'h0 };
6'h18: d_rgb = { 3'h4, 3'h3, 2'h0 };
6'h19: d_rgb = { 3'h0, 3'h4, 2'h0 };
6'h1a: d_rgb = { 3'h0, 3'h5, 2'h0 };
6'h1b: d_rgb = { 3'h0, 3'h4, 2'h0 };
6'h1c: d_rgb = { 3'h0, 3'h4, 2'h2 };
6'h1d: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h1e: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h1f: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h20: d_rgb = { 3'h7, 3'h7, 2'h3 };
6'h21: d_rgb = { 3'h1, 3'h5, 2'h3 };
6'h22: d_rgb = { 3'h2, 3'h4, 2'h3 };
6'h23: d_rgb = { 3'h5, 3'h4, 2'h3 };
6'h24: d_rgb = { 3'h7, 3'h3, 2'h3 };
6'h25: d_rgb = { 3'h7, 3'h3, 2'h2 };
6'h26: d_rgb = { 3'h7, 3'h3, 2'h1 };
6'h27: d_rgb = { 3'h7, 3'h4, 2'h0 };
6'h28: d_rgb = { 3'h7, 3'h5, 2'h0 };
6'h29: d_rgb = { 3'h4, 3'h6, 2'h0 };
6'h2a: d_rgb = { 3'h2, 3'h6, 2'h1 };
6'h2b: d_rgb = { 3'h2, 3'h7, 2'h2 };
6'h2c: d_rgb = { 3'h0, 3'h7, 2'h3 };
6'h2d: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h2e: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h2f: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h30: d_rgb = { 3'h7, 3'h7, 2'h3 };
6'h31: d_rgb = { 3'h5, 3'h7, 2'h3 };
6'h32: d_rgb = { 3'h6, 3'h6, 2'h3 };
6'h33: d_rgb = { 3'h6, 3'h6, 2'h3 };
6'h34: d_rgb = { 3'h7, 3'h6, 2'h3 };
6'h35: d_rgb = { 3'h7, 3'h6, 2'h3 };
6'h36: d_rgb = { 3'h7, 3'h5, 2'h2 };
6'h37: d_rgb = { 3'h7, 3'h6, 2'h2 };
6'h38: d_rgb = { 3'h7, 3'h7, 2'h2 };
6'h39: d_rgb = { 3'h7, 3'h7, 2'h2 };
6'h3a: d_rgb = { 3'h5, 3'h7, 2'h2 };
6'h3b: d_rgb = { 3'h5, 3'h7, 2'h3 };
6'h3c: d_rgb = { 3'h4, 3'h7, 2'h3 };
6'h3d: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h3e: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h3f: d_rgb = { 3'h0, 3'h0, 2'h0 };
endcase
end
end
assign { r_out, g_out, b_out } = q_rgb;
assign pix_pulse_out = nes_x_next != nes_x_out;
// Clear the VBLANK signal immediately before starting processing of the pre-0 garbage line. From
// here. Set the vblank approximately 2270 CPU cycles before it will be cleared. This is done
// in order to pass vbl_clear_time.nes. It eats into the visible portion of the playfield, but we
// currently hide that portion of the screen anyway.
assign d_vblank = ((sync_x == 730) && (sync_y == 477)) ? 1'b1 :
((sync_x == 64) && (sync_y == 519)) ? 1'b0 : q_vblank;
assign vblank_out = q_vblank;
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
Pan
:Function
Panning a image from your given offset.
Give the first output after 2 cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-26
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
[email protected]
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module Pan(
clk,
rst_n,
offset_x,
offset_y,
in_enable,
in_data,
in_count_x,
in_count_y,
out_ready,
out_data,
out_count_x,
out_count_y);
/*
::description
This module's working mode.
::range
0 for Pipline, 1 for Req-ack
*/
parameter work_mode = 0;
/*
::description
Data bit width.
*/
parameter data_width = 8;
/*
::description
Width of image.
::range
1 - 4096
*/
parameter im_width = 320;
/*
::description
Height of image.
::range
1 - 4096
*/
parameter im_height = 240;
/*
::description
The bits of width of image.
::range
Depend on width of image
*/
parameter im_width_bits = 9;
/*
::description
Clock.
*/
input clk;
/*
::description
Reset, active low.
*/
input rst_n;
/*
::description
Offset for horizontal.
::range
The value must be true code if offset is positive, if negative, must be complemental code.
*/
input signed [im_width_bits : 0] offset_x;
/*
::description
::description
Offset for vertical.
::range
The value must be true code if offset is positive, if negative, must be complemental code.
*/
input signed [im_width_bits : 0] offset_y;
/*
::description
Input data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
*/
input in_enable;
/*
::description
Input data, it must be synchronous with in_enable.
*/
input [data_width - 1 : 0] in_data;
/*
::description
Input pixel count for width.
*/
input[im_width_bits - 1 : 0] in_count_x;
/*
::description
Input pixel count for height.
*/
input[im_width_bits - 1 : 0] in_count_y;
/*
::description
Output data ready, in both two mode, it will be high while the out_data can be read.
*/
output out_ready;
/*
::description
Output data, it will be synchronous with out_ready.
*/
output[data_width - 1 : 0] out_data;
/*
::description
Output pixel count for height.
*/
output[im_width_bits - 1 : 0] out_count_x;
/*
::description
Output pixel count for height.
*/
output[im_width_bits - 1 : 0] out_count_y;
reg[2 : 0] con_enable;
reg signed [im_width_bits : 0] addr_sum_x, addr_sum_y;
reg signed [im_width_bits : 0] tmp_sum_x, tmp_sum_y;
reg signed [im_width_bits : 0] addr_sp_x, addr_sp_y;
reg in_range_t, in_range_b, in_range_l, in_range_r;
genvar i;
generate
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
con_enable <= 0;
else if(con_enable == 2)
con_enable <= con_enable;
else
con_enable <= con_enable + 1;
end
assign out_ready = con_enable == 2 ? 1 : 0;
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable) begin
addr_sum_x <= 0;
addr_sum_y <= 0;
tmp_sum_x <= 0;
tmp_sum_y <= 0;
end else begin
addr_sum_x <= in_count_x + offset_x;
addr_sum_y <= in_count_y + offset_y;
tmp_sum_x <= addr_sum_x;
tmp_sum_y <= addr_sum_y;
end
end
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable) begin
addr_sp_x <= 0;
addr_sp_y <= 0;
end else begin
addr_sp_x <= addr_sum_x < 0 ? addr_sum_x + im_width : addr_sum_x - im_width;
addr_sp_y <= addr_sum_y < 0 ? addr_sum_y + im_height : addr_sum_y - im_height;
end
end
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable) begin
in_range_t <= 0;
in_range_b <= 0;
in_range_l <= 0;
in_range_r <= 0;
end else begin
in_range_t <= addr_sum_y >= 0 ? 1 : 0;
in_range_b <= addr_sum_y < im_height ? 1 : 0;
in_range_l <= addr_sum_x >= 0 ? 1 : 0;
in_range_r <= addr_sum_x < im_width ? 1 : 0;
end
end
assign out_count_x = in_range_l & in_range_r & out_ready ? tmp_sum_x : addr_sp_x;
assign out_count_y = in_range_t & in_range_b & out_ready ? tmp_sum_y : addr_sp_y;
if(work_mode == 0) begin
for (i = 0; i < 2; i = i + 1) begin : buffer
reg[data_width - 1 : 0] b;
if(i == 0) begin
always @(posedge clk)
b <= in_data;
end else begin
always @(posedge clk)
b <= buffer[i - 1].b;
end
end
assign out_data = out_ready & in_range_t & in_range_b & in_range_l & in_range_r ? buffer[1].b : 0;
end else begin
reg[data_width - 1 : 0] reg_in_data;
always @(posedge in_enable)
reg_in_data <= in_data;
assign out_data = out_ready & in_range_t & in_range_b & in_range_l & in_range_r ? reg_in_data : 0;
end
endgenerate
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Rose-Hulman Institute of Technology
// Engineer: Adam and Mohammad
// Create Date: 20:16:03 10/24/2015
// Design Name: The top-level data unit of the design
// Module Name: MasterDataUnitI2C
// Summary: This holds all of the data that is read and written.
//////////////////////////////////////////////////////////////////////////////////
module MasterDataUnitI2C(BaudRate,ClockFrequency,SentData,BaudEnable,Clock,ReadOrWrite,Reset,Select,ShiftOrHold,StartStopAck,WriteLoad,ReceivedData,SCL,SDA);
input [19:0] BaudRate; // up to 1000000
input [29:0] ClockFrequency; // up to 1GHz
input [LENGTH-1:0] SentData;
input BaudEnable;
input Clock;
input ReadOrWrite;
input Reset;
input Select;
input ShiftOrHold;
input StartStopAck;
input WriteLoad;
output [LENGTH-1:0] ReceivedData;
output SCL;
inout SDA;
parameter LENGTH = 8;
assign SCL = ClockI2C;
wire ClockI2C;
BaudRateGeneratorI2C BaudUnit(BaudEnable,ClockI2C,Reset,Clock,BaudRate,ClockFrequency);
wire ShiftDataIn, ShiftDataOut;
ShiftRegisterI2C2015fall ShiftUnit(SentData,Clock,Reset,ShiftDataIn,ShiftOrHold,WriteLoad,ReceivedData,ShiftDataOut,ClockI2C);
SDAmodule SDAUnit(SDA,ReadOrWrite,Select,StartStopAck,ShiftDataIn,ShiftDataOut);
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
* adjusted to FML 8x16 by Zeus Gomez Marmolejo <[email protected]>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_mgmt #(
parameter sdram_depth = 26,
parameter sdram_columndepth = 9,
parameter sdram_addrdepth = sdram_depth-1-1-(sdram_columndepth+2)+1
) (
input sys_clk,
input sdram_rst,
input [2:0] tim_rp,
input [2:0] tim_rcd,
input [10:0] tim_refi,
input [3:0] tim_rfc,
input stb,
input we,
input [sdram_depth-1-1:0] address, /* in 16-bit words */
output reg ack,
output reg read,
output reg write,
output [3:0] concerned_bank,
input read_safe,
input write_safe,
input [3:0] precharge_safe,
output sdram_cs_n,
output sdram_we_n,
output sdram_cas_n,
output sdram_ras_n,
output [sdram_addrdepth-1:0] sdram_adr,
output [1:0] sdram_ba
);
/*
* Address Mapping :
* | ROW ADDRESS | BANK NUMBER | COL ADDRESS | for 16-bit words
* |depth-1 coldepth+2|coldepth+1 coldepth|coldepth-1 0|
* (depth for 16-bit words, which is sdram_depth-1)
*/
localparam rowdepth = sdram_depth-1-1-(sdram_columndepth+2)+1;
localparam sdram_addrdepth_o1024 = sdram_addrdepth-11;
wire [sdram_depth-1-1:0] address16 = address;
wire [sdram_columndepth-1:0] col_address = address16[sdram_columndepth-1:0];
wire [1:0] bank_address = address16[sdram_columndepth+1:sdram_columndepth];
wire [rowdepth-1:0] row_address = address16[sdram_depth-1-1:sdram_columndepth+2];
reg [3:0] bank_address_onehot;
always @(*) begin
case(bank_address)
2'b00: bank_address_onehot <= 4'b0001;
2'b01: bank_address_onehot <= 4'b0010;
2'b10: bank_address_onehot <= 4'b0100;
2'b11: bank_address_onehot <= 4'b1000;
endcase
end
/* Track open rows */
reg [3:0] has_openrow;
reg [rowdepth-1:0] openrows[0:3];
reg [3:0] track_close;
reg [3:0] track_open;
always @(posedge sys_clk) begin
if(sdram_rst) begin
has_openrow <= 4'h0;
end else begin
has_openrow <= (has_openrow | track_open) & ~track_close;
if(track_open[0]) openrows[0] <= row_address;
if(track_open[1]) openrows[1] <= row_address;
if(track_open[2]) openrows[2] <= row_address;
if(track_open[3]) openrows[3] <= row_address;
end
end
/* Bank precharge safety */
assign concerned_bank = bank_address_onehot;
wire current_precharge_safe =
(precharge_safe[0] | ~bank_address_onehot[0])
&(precharge_safe[1] | ~bank_address_onehot[1])
&(precharge_safe[2] | ~bank_address_onehot[2])
&(precharge_safe[3] | ~bank_address_onehot[3]);
/* Check for page hits */
wire bank_open = has_openrow[bank_address];
wire page_hit = bank_open & (openrows[bank_address] == row_address);
/* Address drivers */
reg sdram_adr_loadrow;
reg sdram_adr_loadcol;
reg sdram_adr_loadA10;
assign sdram_adr =
({sdram_addrdepth{sdram_adr_loadrow}} & row_address)
|({sdram_addrdepth{sdram_adr_loadcol}} & col_address)
|({sdram_addrdepth{sdram_adr_loadA10}}
& { {sdram_addrdepth_o1024{1'b0}} , 11'd1024});
assign sdram_ba = bank_address;
/* Command drivers */
reg sdram_cs;
reg sdram_we;
reg sdram_cas;
reg sdram_ras;
assign sdram_cs_n = ~sdram_cs;
assign sdram_we_n = ~sdram_we;
assign sdram_cas_n = ~sdram_cas;
assign sdram_ras_n = ~sdram_ras;
/* Timing counters */
/* The number of clocks we must wait following a PRECHARGE command (usually tRP). */
reg [2:0] precharge_counter;
reg reload_precharge_counter;
wire precharge_done = (precharge_counter == 3'd0);
always @(posedge sys_clk) begin
if(reload_precharge_counter)
precharge_counter <= tim_rp;
else if(~precharge_done)
precharge_counter <= precharge_counter - 3'd1;
end
/* The number of clocks we must wait following an ACTIVATE command (usually tRCD). */
reg [2:0] activate_counter;
reg reload_activate_counter;
wire activate_done = (activate_counter == 3'd0);
always @(posedge sys_clk) begin
if(reload_activate_counter)
activate_counter <= tim_rcd;
else if(~activate_done)
activate_counter <= activate_counter - 3'd1;
end
/* The number of clocks we have left before we must refresh one row in the SDRAM array (usually tREFI). */
reg [10:0] refresh_counter;
reg reload_refresh_counter;
wire must_refresh = refresh_counter == 11'd0;
always @(posedge sys_clk) begin
if(sdram_rst)
refresh_counter <= 11'd0;
else begin
if(reload_refresh_counter)
refresh_counter <= tim_refi;
else if(~must_refresh)
refresh_counter <= refresh_counter - 11'd1;
end
end
/* The number of clocks we must wait following an AUTO REFRESH command (usually tRFC). */
reg [3:0] autorefresh_counter;
reg reload_autorefresh_counter;
wire autorefresh_done = (autorefresh_counter == 4'd0);
always @(posedge sys_clk) begin
if(reload_autorefresh_counter)
autorefresh_counter <= tim_rfc;
else if(~autorefresh_done)
autorefresh_counter <= autorefresh_counter - 4'd1;
end
/* FSM that pushes commands into the SDRAM */
reg [3:0] state;
reg [3:0] next_state;
localparam [3:0]
IDLE = 4'd0,
ACTIVATE = 4'd1,
READ = 4'd2,
WRITE = 4'd3,
PRECHARGEALL = 4'd4,
AUTOREFRESH = 4'd5,
AUTOREFRESH_WAIT = 4'd6;
always @(posedge sys_clk) begin
if(sdram_rst)
state <= IDLE;
else begin
//$display("state: %d -> %d", state, next_state);
state <= next_state;
end
end
always @(*) begin
next_state = state;
reload_precharge_counter = 1'b0;
reload_activate_counter = 1'b0;
reload_refresh_counter = 1'b0;
reload_autorefresh_counter = 1'b0;
sdram_cs = 1'b0;
sdram_we = 1'b0;
sdram_cas = 1'b0;
sdram_ras = 1'b0;
sdram_adr_loadrow = 1'b0;
sdram_adr_loadcol = 1'b0;
sdram_adr_loadA10 = 1'b0;
track_close = 4'b0000;
track_open = 4'b0000;
read = 1'b0;
write = 1'b0;
ack = 1'b0;
case(state)
IDLE: begin
if(must_refresh)
next_state = PRECHARGEALL;
else begin
if(stb) begin
if(page_hit) begin
if(we) begin
if(write_safe) begin
/* Write */
sdram_cs = 1'b1;
sdram_ras = 1'b0;
sdram_cas = 1'b1;
sdram_we = 1'b1;
sdram_adr_loadcol = 1'b1;
write = 1'b1;
ack = 1'b1;
end
end else begin
if(read_safe) begin
/* Read */
sdram_cs = 1'b1;
sdram_ras = 1'b0;
sdram_cas = 1'b1;
sdram_we = 1'b0;
sdram_adr_loadcol = 1'b1;
read = 1'b1;
ack = 1'b1;
end
end
end else begin
if(bank_open) begin
if(current_precharge_safe) begin
/* Precharge Bank */
sdram_cs = 1'b1;
sdram_ras = 1'b1;
sdram_cas = 1'b0;
sdram_we = 1'b1;
track_close = bank_address_onehot;
reload_precharge_counter = 1'b1;
next_state = ACTIVATE;
end
end else begin
/* Activate */
sdram_cs = 1'b1;
sdram_ras = 1'b1;
sdram_cas = 1'b0;
sdram_we = 1'b0;
sdram_adr_loadrow = 1'b1;
track_open = bank_address_onehot;
reload_activate_counter = 1'b1;
if(we)
next_state = WRITE;
else
next_state = READ;
end
end
end
end
end
ACTIVATE: begin
if(precharge_done) begin
sdram_cs = 1'b1;
sdram_ras = 1'b1;
sdram_cas = 1'b0;
sdram_we = 1'b0;
sdram_adr_loadrow = 1'b1;
track_open = bank_address_onehot;
reload_activate_counter = 1'b1;
if(we)
next_state = WRITE;
else
next_state = READ;
end
end
READ: begin
if(activate_done) begin
if(read_safe) begin
sdram_cs = 1'b1;
sdram_ras = 1'b0;
sdram_cas = 1'b1;
sdram_we = 1'b0;
sdram_adr_loadcol = 1'b1;
read = 1'b1;
ack = 1'b1;
next_state = IDLE;
end
end
end
WRITE: begin
if(activate_done) begin
if(write_safe) begin
sdram_cs = 1'b1;
sdram_ras = 1'b0;
sdram_cas = 1'b1;
sdram_we = 1'b1;
sdram_adr_loadcol = 1'b1;
write = 1'b1;
ack = 1'b1;
next_state = IDLE;
end
end
end
PRECHARGEALL: begin
if(precharge_safe == 4'b1111) begin
sdram_cs = 1'b1;
sdram_ras = 1'b1;
sdram_cas = 1'b0;
sdram_we = 1'b1;
sdram_adr_loadA10 = 1'b1;
reload_precharge_counter = 1'b1;
track_close = 4'b1111;
next_state = AUTOREFRESH;
end
end
AUTOREFRESH: begin
if(precharge_done) begin
sdram_cs = 1'b1;
sdram_ras = 1'b1;
sdram_cas = 1'b1;
sdram_we = 1'b0;
reload_refresh_counter = 1'b1;
reload_autorefresh_counter = 1'b1;
next_state = AUTOREFRESH_WAIT;
end
end
AUTOREFRESH_WAIT: begin
if(autorefresh_done)
next_state = IDLE;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111OI_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A2111OI_PP_BLACKBOX_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a2111oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111OI_PP_BLACKBOX_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 4
(* X_CORE_INFO = "axi_protocol_converter_v2_1_axi_protocol_converter,Vivado 2014.4.1" *)
(* CHECK_LICENSE_TYPE = "OpenSSD2_auto_pc_0,axi_protocol_converter_v2_1_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "OpenSSD2_auto_pc_0,axi_protocol_converter_v2_1_axi_protocol_converter,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module OpenSSD2_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//
// Computes the ECC for an 32-bit data stream based on the data and address of
// data in the stream.
//
// data_i - 32-bit input data
// addr_i - address of data in stream
// ecc_o - 24-bit ecc value for the current 8-bit value
//
module hamm_4096x1_1x32 (
input wire [31:0] data_i,
input wire [6:0] addr_i,
output wire [23:0] ecc_o
);
wire [31:0] d = data_i;
// compute xor of all bits in data_i
wire [7:0] data_xor = ^d;
// calculate even bits for bit addresses then byte addresses
assign ecc_o[0] = d[0] ^ d[2] ^ d[4] ^ d[6] ^ d[8] ^ d[10] ^ d[12] ^ d[14] ^ d[16] ^ d[18] ^ d[20] ^ d[22] ^ d[24] ^ d[26] ^ d[28] ^ d[30];
assign ecc_o[1] = d[0] ^ d[1] ^ d[4] ^ d[5] ^ d[8] ^ d[9] ^ d[12] ^ d[13] ^ d[16] ^ d[17] ^ d[20] ^ d[21] ^ d[24] ^ d[25] ^ d[28] ^ d[29];
assign ecc_o[2] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[24] ^ d[25] ^ d[26] ^ d[27];
assign ecc_o[3] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23];
assign ecc_o[4] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15];
assign ecc_o[5] = ~addr_i[0] & data_xor;
assign ecc_o[6] = ~addr_i[1] & data_xor;
assign ecc_o[7] = ~addr_i[2] & data_xor;
assign ecc_o[8] = ~addr_i[3] & data_xor;
assign ecc_o[9] = ~addr_i[4] & data_xor;
assign ecc_o[10] = ~addr_i[5] & data_xor;
assign ecc_o[11] = ~addr_i[6] & data_xor;
// calculate odd bits for bit addresses then byte addresses
assign ecc_o[12+0] = d[1] ^ d[3] ^ d[5] ^ d[7] ^ d[9] ^ d[11] ^ d[13] ^ d[15] ^ d[17] ^ d[19] ^ d[21] ^ d[23] ^ d[25] ^ d[27] ^ d[29] ^ d[31];
assign ecc_o[12+1] = d[2] ^ d[3] ^ d[6] ^ d[7] ^ d[10] ^ d[11] ^ d[14] ^ d[15] ^ d[18] ^ d[19] ^ d[22] ^ d[23] ^ d[26] ^ d[27] ^ d[30] ^ d[31];
assign ecc_o[12+2] = d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ d[28] ^ d[29] ^ d[30] ^ d[31];
assign ecc_o[12+3] = d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31];
assign ecc_o[12+4] = d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31];
assign ecc_o[12+5] = addr_i[0] & data_xor;
assign ecc_o[12+6] = addr_i[1] & data_xor;
assign ecc_o[12+7] = addr_i[2] & data_xor;
assign ecc_o[12+8] = addr_i[3] & data_xor;
assign ecc_o[12+9] = addr_i[4] & data_xor;
assign ecc_o[12+10] = addr_i[5] & data_xor;
assign ecc_o[12+11] = addr_i[6] & data_xor;
endmodule
//
// Performs hamming calculations on up to 4096 bits (512 bytes) and computes a
// 24-bit hamming ECC
//
// clk, rst -
// standard clocking and reset signals
// data_i, valid_i, sof_i, eof_i -
// 8-bit input data bus on its way to/from the flash device
// data_o, valid_o, sof_o, eof_o, ecc_o -
// 8-bit output data bus and ecc on its way to/from the flash device
// pipelined one clock cycle after input
//
module hamm_4096x1_512x32 (
input wire clk,
input wire rst,
input wire [31:0] data_i,
input wire valid_i,
input wire sof_i,
input wire eof_i,
output wire [31:0] data_o,
output wire valid_o,
output wire sof_o,
output wire eof_o,
output wire [23:0] ecc_o
);
// register all inputs to ease timing
reg [31:0] data_r;
reg valid_r;
reg sof_r;
reg eof_r;
always @(posedge clk) begin
data_r <= data_i;
valid_r <= valid_i;
sof_r <= sof_i;
eof_r <= eof_i;
end
reg [6:0] addr_r;
wire [23:0] byte_ecc;
hamm_4096x1_1x32 hamm_4096x1_1x32 (
.data_i ( data_r ),
.addr_i ( addr_r ),
.ecc_o ( byte_ecc )
);
reg [23:0] ecc_r;
always @(posedge clk) begin
// sync reset all registers to 0
if(rst) begin
addr_r <= 0;
ecc_r <= 0;
end else begin
if(valid_r) begin
// clear ecc when sof_i is asserted
if(sof_r) begin
// computed for addr_r == 0
ecc_r <= byte_ecc;
addr_r <= 1;
// otherwise keep computing ecc
end else begin
// computed for addr_r++
ecc_r <= ecc_r ^ byte_ecc;
// reset addr_r on eof
addr_r <= eof_r ? 0 : addr_r + 1;
end
end
end
end
// output data_o one clock cycle after data_i
assign data_o = data_r;
assign valid_o = valid_r;
assign sof_o = sof_r;
assign eof_o = eof_r;
// ecc_o is output when eof_o is high
assign ecc_o = eof_r ? ecc_r ^ byte_ecc : 0;
endmodule
|
// system_acl_iface_acl_kernel_interface_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.05.04.18:11:56
`timescale 1 ps / 1 ps
module system_acl_iface_acl_kernel_interface_mm_interconnect_0 (
input wire kernel_clk_out_clk_clk, // kernel_clk_out_clk.clk
input wire address_span_extender_0_reset_reset_bridge_in_reset_reset, // address_span_extender_0_reset_reset_bridge_in_reset.reset
input wire kernel_cra_reset_reset_bridge_in_reset_reset, // kernel_cra_reset_reset_bridge_in_reset.reset
input wire [29:0] address_span_extender_0_expanded_master_address, // address_span_extender_0_expanded_master.address
output wire address_span_extender_0_expanded_master_waitrequest, // .waitrequest
input wire [0:0] address_span_extender_0_expanded_master_burstcount, // .burstcount
input wire [3:0] address_span_extender_0_expanded_master_byteenable, // .byteenable
input wire address_span_extender_0_expanded_master_read, // .read
output wire [31:0] address_span_extender_0_expanded_master_readdata, // .readdata
output wire address_span_extender_0_expanded_master_readdatavalid, // .readdatavalid
input wire address_span_extender_0_expanded_master_write, // .write
input wire [31:0] address_span_extender_0_expanded_master_writedata, // .writedata
output wire [29:0] kernel_cra_s0_address, // kernel_cra_s0.address
output wire kernel_cra_s0_write, // .write
output wire kernel_cra_s0_read, // .read
input wire [63:0] kernel_cra_s0_readdata, // .readdata
output wire [63:0] kernel_cra_s0_writedata, // .writedata
output wire [0:0] kernel_cra_s0_burstcount, // .burstcount
output wire [7:0] kernel_cra_s0_byteenable, // .byteenable
input wire kernel_cra_s0_readdatavalid, // .readdatavalid
input wire kernel_cra_s0_waitrequest, // .waitrequest
output wire kernel_cra_s0_debugaccess // .debugaccess
);
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest; // address_span_extender_0_expanded_master_agent:av_waitrequest -> address_span_extender_0_expanded_master_translator:uav_waitrequest
wire [2:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount; // address_span_extender_0_expanded_master_translator:uav_burstcount -> address_span_extender_0_expanded_master_agent:av_burstcount
wire [31:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata; // address_span_extender_0_expanded_master_translator:uav_writedata -> address_span_extender_0_expanded_master_agent:av_writedata
wire [29:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address; // address_span_extender_0_expanded_master_translator:uav_address -> address_span_extender_0_expanded_master_agent:av_address
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock; // address_span_extender_0_expanded_master_translator:uav_lock -> address_span_extender_0_expanded_master_agent:av_lock
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write; // address_span_extender_0_expanded_master_translator:uav_write -> address_span_extender_0_expanded_master_agent:av_write
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read; // address_span_extender_0_expanded_master_translator:uav_read -> address_span_extender_0_expanded_master_agent:av_read
wire [31:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata; // address_span_extender_0_expanded_master_agent:av_readdata -> address_span_extender_0_expanded_master_translator:uav_readdata
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess; // address_span_extender_0_expanded_master_translator:uav_debugaccess -> address_span_extender_0_expanded_master_agent:av_debugaccess
wire [3:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable; // address_span_extender_0_expanded_master_translator:uav_byteenable -> address_span_extender_0_expanded_master_agent:av_byteenable
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid; // address_span_extender_0_expanded_master_agent:av_readdatavalid -> address_span_extender_0_expanded_master_translator:uav_readdatavalid
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> address_span_extender_0_expanded_master_agent:rp_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> address_span_extender_0_expanded_master_agent:rp_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> address_span_extender_0_expanded_master_agent:rp_startofpacket
wire [100:0] rsp_mux_src_data; // rsp_mux:src_data -> address_span_extender_0_expanded_master_agent:rp_data
wire [0:0] rsp_mux_src_channel; // rsp_mux:src_channel -> address_span_extender_0_expanded_master_agent:rp_channel
wire rsp_mux_src_ready; // address_span_extender_0_expanded_master_agent:rp_ready -> rsp_mux:src_ready
wire kernel_cra_s0_agent_m0_waitrequest; // kernel_cra_s0_translator:uav_waitrequest -> kernel_cra_s0_agent:m0_waitrequest
wire [3:0] kernel_cra_s0_agent_m0_burstcount; // kernel_cra_s0_agent:m0_burstcount -> kernel_cra_s0_translator:uav_burstcount
wire [63:0] kernel_cra_s0_agent_m0_writedata; // kernel_cra_s0_agent:m0_writedata -> kernel_cra_s0_translator:uav_writedata
wire [29:0] kernel_cra_s0_agent_m0_address; // kernel_cra_s0_agent:m0_address -> kernel_cra_s0_translator:uav_address
wire kernel_cra_s0_agent_m0_write; // kernel_cra_s0_agent:m0_write -> kernel_cra_s0_translator:uav_write
wire kernel_cra_s0_agent_m0_lock; // kernel_cra_s0_agent:m0_lock -> kernel_cra_s0_translator:uav_lock
wire kernel_cra_s0_agent_m0_read; // kernel_cra_s0_agent:m0_read -> kernel_cra_s0_translator:uav_read
wire [63:0] kernel_cra_s0_agent_m0_readdata; // kernel_cra_s0_translator:uav_readdata -> kernel_cra_s0_agent:m0_readdata
wire kernel_cra_s0_agent_m0_readdatavalid; // kernel_cra_s0_translator:uav_readdatavalid -> kernel_cra_s0_agent:m0_readdatavalid
wire kernel_cra_s0_agent_m0_debugaccess; // kernel_cra_s0_agent:m0_debugaccess -> kernel_cra_s0_translator:uav_debugaccess
wire [7:0] kernel_cra_s0_agent_m0_byteenable; // kernel_cra_s0_agent:m0_byteenable -> kernel_cra_s0_translator:uav_byteenable
wire kernel_cra_s0_agent_rf_source_endofpacket; // kernel_cra_s0_agent:rf_source_endofpacket -> kernel_cra_s0_agent_rsp_fifo:in_endofpacket
wire kernel_cra_s0_agent_rf_source_valid; // kernel_cra_s0_agent:rf_source_valid -> kernel_cra_s0_agent_rsp_fifo:in_valid
wire kernel_cra_s0_agent_rf_source_startofpacket; // kernel_cra_s0_agent:rf_source_startofpacket -> kernel_cra_s0_agent_rsp_fifo:in_startofpacket
wire [137:0] kernel_cra_s0_agent_rf_source_data; // kernel_cra_s0_agent:rf_source_data -> kernel_cra_s0_agent_rsp_fifo:in_data
wire kernel_cra_s0_agent_rf_source_ready; // kernel_cra_s0_agent_rsp_fifo:in_ready -> kernel_cra_s0_agent:rf_source_ready
wire kernel_cra_s0_agent_rsp_fifo_out_endofpacket; // kernel_cra_s0_agent_rsp_fifo:out_endofpacket -> kernel_cra_s0_agent:rf_sink_endofpacket
wire kernel_cra_s0_agent_rsp_fifo_out_valid; // kernel_cra_s0_agent_rsp_fifo:out_valid -> kernel_cra_s0_agent:rf_sink_valid
wire kernel_cra_s0_agent_rsp_fifo_out_startofpacket; // kernel_cra_s0_agent_rsp_fifo:out_startofpacket -> kernel_cra_s0_agent:rf_sink_startofpacket
wire [137:0] kernel_cra_s0_agent_rsp_fifo_out_data; // kernel_cra_s0_agent_rsp_fifo:out_data -> kernel_cra_s0_agent:rf_sink_data
wire kernel_cra_s0_agent_rsp_fifo_out_ready; // kernel_cra_s0_agent:rf_sink_ready -> kernel_cra_s0_agent_rsp_fifo:out_ready
wire kernel_cra_s0_agent_rdata_fifo_src_valid; // kernel_cra_s0_agent:rdata_fifo_src_valid -> kernel_cra_s0_agent:rdata_fifo_sink_valid
wire [65:0] kernel_cra_s0_agent_rdata_fifo_src_data; // kernel_cra_s0_agent:rdata_fifo_src_data -> kernel_cra_s0_agent:rdata_fifo_sink_data
wire kernel_cra_s0_agent_rdata_fifo_src_ready; // kernel_cra_s0_agent:rdata_fifo_sink_ready -> kernel_cra_s0_agent:rdata_fifo_src_ready
wire address_span_extender_0_expanded_master_agent_cp_endofpacket; // address_span_extender_0_expanded_master_agent:cp_endofpacket -> router:sink_endofpacket
wire address_span_extender_0_expanded_master_agent_cp_valid; // address_span_extender_0_expanded_master_agent:cp_valid -> router:sink_valid
wire address_span_extender_0_expanded_master_agent_cp_startofpacket; // address_span_extender_0_expanded_master_agent:cp_startofpacket -> router:sink_startofpacket
wire [100:0] address_span_extender_0_expanded_master_agent_cp_data; // address_span_extender_0_expanded_master_agent:cp_data -> router:sink_data
wire address_span_extender_0_expanded_master_agent_cp_ready; // router:sink_ready -> address_span_extender_0_expanded_master_agent:cp_ready
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire [100:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire [0:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire kernel_cra_s0_agent_rp_endofpacket; // kernel_cra_s0_agent:rp_endofpacket -> router_001:sink_endofpacket
wire kernel_cra_s0_agent_rp_valid; // kernel_cra_s0_agent:rp_valid -> router_001:sink_valid
wire kernel_cra_s0_agent_rp_startofpacket; // kernel_cra_s0_agent:rp_startofpacket -> router_001:sink_startofpacket
wire [136:0] kernel_cra_s0_agent_rp_data; // kernel_cra_s0_agent:rp_data -> router_001:sink_data
wire kernel_cra_s0_agent_rp_ready; // router_001:sink_ready -> kernel_cra_s0_agent:rp_ready
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire [100:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire [0:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire [100:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire [0:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> kernel_cra_s0_cmd_width_adapter:in_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> kernel_cra_s0_cmd_width_adapter:in_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> kernel_cra_s0_cmd_width_adapter:in_startofpacket
wire [100:0] cmd_mux_src_data; // cmd_mux:src_data -> kernel_cra_s0_cmd_width_adapter:in_data
wire [0:0] cmd_mux_src_channel; // cmd_mux:src_channel -> kernel_cra_s0_cmd_width_adapter:in_channel
wire cmd_mux_src_ready; // kernel_cra_s0_cmd_width_adapter:in_ready -> cmd_mux:src_ready
wire kernel_cra_s0_cmd_width_adapter_src_endofpacket; // kernel_cra_s0_cmd_width_adapter:out_endofpacket -> kernel_cra_s0_agent:cp_endofpacket
wire kernel_cra_s0_cmd_width_adapter_src_valid; // kernel_cra_s0_cmd_width_adapter:out_valid -> kernel_cra_s0_agent:cp_valid
wire kernel_cra_s0_cmd_width_adapter_src_startofpacket; // kernel_cra_s0_cmd_width_adapter:out_startofpacket -> kernel_cra_s0_agent:cp_startofpacket
wire [136:0] kernel_cra_s0_cmd_width_adapter_src_data; // kernel_cra_s0_cmd_width_adapter:out_data -> kernel_cra_s0_agent:cp_data
wire kernel_cra_s0_cmd_width_adapter_src_ready; // kernel_cra_s0_agent:cp_ready -> kernel_cra_s0_cmd_width_adapter:out_ready
wire [0:0] kernel_cra_s0_cmd_width_adapter_src_channel; // kernel_cra_s0_cmd_width_adapter:out_channel -> kernel_cra_s0_agent:cp_channel
wire router_001_src_endofpacket; // router_001:src_endofpacket -> kernel_cra_s0_rsp_width_adapter:in_endofpacket
wire router_001_src_valid; // router_001:src_valid -> kernel_cra_s0_rsp_width_adapter:in_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> kernel_cra_s0_rsp_width_adapter:in_startofpacket
wire [136:0] router_001_src_data; // router_001:src_data -> kernel_cra_s0_rsp_width_adapter:in_data
wire [0:0] router_001_src_channel; // router_001:src_channel -> kernel_cra_s0_rsp_width_adapter:in_channel
wire router_001_src_ready; // kernel_cra_s0_rsp_width_adapter:in_ready -> router_001:src_ready
wire kernel_cra_s0_rsp_width_adapter_src_endofpacket; // kernel_cra_s0_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
wire kernel_cra_s0_rsp_width_adapter_src_valid; // kernel_cra_s0_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
wire kernel_cra_s0_rsp_width_adapter_src_startofpacket; // kernel_cra_s0_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
wire [100:0] kernel_cra_s0_rsp_width_adapter_src_data; // kernel_cra_s0_rsp_width_adapter:out_data -> rsp_demux:sink_data
wire kernel_cra_s0_rsp_width_adapter_src_ready; // rsp_demux:sink_ready -> kernel_cra_s0_rsp_width_adapter:out_ready
wire [0:0] kernel_cra_s0_rsp_width_adapter_src_channel; // kernel_cra_s0_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
altera_merlin_master_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) address_span_extender_0_expanded_master_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read), // .read
.uav_write (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (address_span_extender_0_expanded_master_address), // avalon_anti_master_0.address
.av_waitrequest (address_span_extender_0_expanded_master_waitrequest), // .waitrequest
.av_burstcount (address_span_extender_0_expanded_master_burstcount), // .burstcount
.av_byteenable (address_span_extender_0_expanded_master_byteenable), // .byteenable
.av_read (address_span_extender_0_expanded_master_read), // .read
.av_readdata (address_span_extender_0_expanded_master_readdata), // .readdata
.av_readdatavalid (address_span_extender_0_expanded_master_readdatavalid), // .readdatavalid
.av_write (address_span_extender_0_expanded_master_write), // .write
.av_writedata (address_span_extender_0_expanded_master_writedata), // .writedata
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) kernel_cra_s0_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (kernel_cra_s0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (kernel_cra_s0_agent_m0_burstcount), // .burstcount
.uav_read (kernel_cra_s0_agent_m0_read), // .read
.uav_write (kernel_cra_s0_agent_m0_write), // .write
.uav_waitrequest (kernel_cra_s0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (kernel_cra_s0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (kernel_cra_s0_agent_m0_byteenable), // .byteenable
.uav_readdata (kernel_cra_s0_agent_m0_readdata), // .readdata
.uav_writedata (kernel_cra_s0_agent_m0_writedata), // .writedata
.uav_lock (kernel_cra_s0_agent_m0_lock), // .lock
.uav_debugaccess (kernel_cra_s0_agent_m0_debugaccess), // .debugaccess
.av_address (kernel_cra_s0_address), // avalon_anti_slave_0.address
.av_write (kernel_cra_s0_write), // .write
.av_read (kernel_cra_s0_read), // .read
.av_readdata (kernel_cra_s0_readdata), // .readdata
.av_writedata (kernel_cra_s0_writedata), // .writedata
.av_burstcount (kernel_cra_s0_burstcount), // .burstcount
.av_byteenable (kernel_cra_s0_byteenable), // .byteenable
.av_readdatavalid (kernel_cra_s0_readdatavalid), // .readdatavalid
.av_waitrequest (kernel_cra_s0_waitrequest), // .waitrequest
.av_debugaccess (kernel_cra_s0_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BEGIN_BURST (84),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (76),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (72),
.PKT_ADDR_H (65),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (66),
.PKT_TRANS_POSTED (67),
.PKT_TRANS_WRITE (68),
.PKT_TRANS_READ (69),
.PKT_TRANS_LOCK (70),
.PKT_TRANS_EXCLUSIVE (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (86),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (87),
.PKT_THREAD_ID_H (88),
.PKT_THREAD_ID_L (88),
.PKT_CACHE_H (95),
.PKT_CACHE_L (92),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.PKT_QOS_H (85),
.PKT_QOS_L (85),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_ORI_BURST_SIZE_H (100),
.ST_DATA_W (101),
.ST_CHANNEL_W (1),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_0_expanded_master_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address), // av.address
.av_write (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write), // .write
.av_read (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (address_span_extender_0_expanded_master_agent_cp_valid), // cp.valid
.cp_data (address_span_extender_0_expanded_master_agent_cp_data), // .data
.cp_startofpacket (address_span_extender_0_expanded_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (address_span_extender_0_expanded_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (address_span_extender_0_expanded_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (120),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (101),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (102),
.PKT_TRANS_POSTED (103),
.PKT_TRANS_WRITE (104),
.PKT_TRANS_READ (105),
.PKT_TRANS_LOCK (106),
.PKT_SRC_ID_H (122),
.PKT_SRC_ID_L (122),
.PKT_DEST_ID_H (123),
.PKT_DEST_ID_L (123),
.PKT_BURSTWRAP_H (112),
.PKT_BURSTWRAP_L (112),
.PKT_BYTE_CNT_H (111),
.PKT_BYTE_CNT_L (108),
.PKT_PROTECTION_H (127),
.PKT_PROTECTION_L (125),
.PKT_RESPONSE_STATUS_H (133),
.PKT_RESPONSE_STATUS_L (132),
.PKT_BURST_SIZE_H (115),
.PKT_BURST_SIZE_L (113),
.PKT_ORI_BURST_SIZE_L (134),
.PKT_ORI_BURST_SIZE_H (136),
.ST_CHANNEL_W (1),
.ST_DATA_W (137),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) kernel_cra_s0_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (kernel_cra_s0_agent_m0_address), // m0.address
.m0_burstcount (kernel_cra_s0_agent_m0_burstcount), // .burstcount
.m0_byteenable (kernel_cra_s0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (kernel_cra_s0_agent_m0_debugaccess), // .debugaccess
.m0_lock (kernel_cra_s0_agent_m0_lock), // .lock
.m0_readdata (kernel_cra_s0_agent_m0_readdata), // .readdata
.m0_readdatavalid (kernel_cra_s0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (kernel_cra_s0_agent_m0_read), // .read
.m0_waitrequest (kernel_cra_s0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (kernel_cra_s0_agent_m0_writedata), // .writedata
.m0_write (kernel_cra_s0_agent_m0_write), // .write
.rp_endofpacket (kernel_cra_s0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (kernel_cra_s0_agent_rp_ready), // .ready
.rp_valid (kernel_cra_s0_agent_rp_valid), // .valid
.rp_data (kernel_cra_s0_agent_rp_data), // .data
.rp_startofpacket (kernel_cra_s0_agent_rp_startofpacket), // .startofpacket
.cp_ready (kernel_cra_s0_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (kernel_cra_s0_cmd_width_adapter_src_valid), // .valid
.cp_data (kernel_cra_s0_cmd_width_adapter_src_data), // .data
.cp_startofpacket (kernel_cra_s0_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (kernel_cra_s0_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (kernel_cra_s0_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (kernel_cra_s0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (kernel_cra_s0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (kernel_cra_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (kernel_cra_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (kernel_cra_s0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (kernel_cra_s0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (kernel_cra_s0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (kernel_cra_s0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (kernel_cra_s0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (kernel_cra_s0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (kernel_cra_s0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (kernel_cra_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (kernel_cra_s0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (kernel_cra_s0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (kernel_cra_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (kernel_cra_s0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (138),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) kernel_cra_s0_agent_rsp_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (kernel_cra_s0_agent_rf_source_data), // in.data
.in_valid (kernel_cra_s0_agent_rf_source_valid), // .valid
.in_ready (kernel_cra_s0_agent_rf_source_ready), // .ready
.in_startofpacket (kernel_cra_s0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (kernel_cra_s0_agent_rf_source_endofpacket), // .endofpacket
.out_data (kernel_cra_s0_agent_rsp_fifo_out_data), // out.data
.out_valid (kernel_cra_s0_agent_rsp_fifo_out_valid), // .valid
.out_ready (kernel_cra_s0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (kernel_cra_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (kernel_cra_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_router router (
.sink_ready (address_span_extender_0_expanded_master_agent_cp_ready), // sink.ready
.sink_valid (address_span_extender_0_expanded_master_agent_cp_valid), // .valid
.sink_data (address_span_extender_0_expanded_master_agent_cp_data), // .data
.sink_startofpacket (address_span_extender_0_expanded_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_expanded_master_agent_cp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_router_001 router_001 (
.sink_ready (kernel_cra_s0_agent_rp_ready), // sink.ready
.sink_valid (kernel_cra_s0_agent_rp_valid), // .valid
.sink_data (kernel_cra_s0_agent_rp_data), // .data
.sink_startofpacket (kernel_cra_s0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cra_s0_agent_rp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_demux cmd_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_mux cmd_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_demux rsp_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (kernel_cra_s0_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (kernel_cra_s0_rsp_width_adapter_src_channel), // .channel
.sink_data (kernel_cra_s0_rsp_width_adapter_src_data), // .data
.sink_startofpacket (kernel_cra_s0_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cra_s0_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (kernel_cra_s0_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_rsp_mux rsp_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (65),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (75),
.IN_PKT_BYTE_CNT_L (72),
.IN_PKT_TRANS_COMPRESSED_READ (66),
.IN_PKT_BURSTWRAP_H (76),
.IN_PKT_BURSTWRAP_L (76),
.IN_PKT_BURST_SIZE_H (79),
.IN_PKT_BURST_SIZE_L (77),
.IN_PKT_RESPONSE_STATUS_H (97),
.IN_PKT_RESPONSE_STATUS_L (96),
.IN_PKT_TRANS_EXCLUSIVE (71),
.IN_PKT_BURST_TYPE_H (81),
.IN_PKT_BURST_TYPE_L (80),
.IN_PKT_ORI_BURST_SIZE_L (98),
.IN_PKT_ORI_BURST_SIZE_H (100),
.IN_ST_DATA_W (101),
.OUT_PKT_ADDR_H (101),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (111),
.OUT_PKT_BYTE_CNT_L (108),
.OUT_PKT_TRANS_COMPRESSED_READ (102),
.OUT_PKT_BURST_SIZE_H (115),
.OUT_PKT_BURST_SIZE_L (113),
.OUT_PKT_RESPONSE_STATUS_H (133),
.OUT_PKT_RESPONSE_STATUS_L (132),
.OUT_PKT_TRANS_EXCLUSIVE (107),
.OUT_PKT_BURST_TYPE_H (117),
.OUT_PKT_BURST_TYPE_L (116),
.OUT_PKT_ORI_BURST_SIZE_L (134),
.OUT_PKT_ORI_BURST_SIZE_H (136),
.OUT_ST_DATA_W (137),
.ST_CHANNEL_W (1),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) kernel_cra_s0_cmd_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_src_valid), // sink.valid
.in_channel (cmd_mux_src_channel), // .channel
.in_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_src_ready), // .ready
.in_data (cmd_mux_src_data), // .data
.out_endofpacket (kernel_cra_s0_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (kernel_cra_s0_cmd_width_adapter_src_data), // .data
.out_channel (kernel_cra_s0_cmd_width_adapter_src_channel), // .channel
.out_valid (kernel_cra_s0_cmd_width_adapter_src_valid), // .valid
.out_ready (kernel_cra_s0_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (kernel_cra_s0_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (101),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (111),
.IN_PKT_BYTE_CNT_L (108),
.IN_PKT_TRANS_COMPRESSED_READ (102),
.IN_PKT_BURSTWRAP_H (112),
.IN_PKT_BURSTWRAP_L (112),
.IN_PKT_BURST_SIZE_H (115),
.IN_PKT_BURST_SIZE_L (113),
.IN_PKT_RESPONSE_STATUS_H (133),
.IN_PKT_RESPONSE_STATUS_L (132),
.IN_PKT_TRANS_EXCLUSIVE (107),
.IN_PKT_BURST_TYPE_H (117),
.IN_PKT_BURST_TYPE_L (116),
.IN_PKT_ORI_BURST_SIZE_L (134),
.IN_PKT_ORI_BURST_SIZE_H (136),
.IN_ST_DATA_W (137),
.OUT_PKT_ADDR_H (65),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (75),
.OUT_PKT_BYTE_CNT_L (72),
.OUT_PKT_TRANS_COMPRESSED_READ (66),
.OUT_PKT_BURST_SIZE_H (79),
.OUT_PKT_BURST_SIZE_L (77),
.OUT_PKT_RESPONSE_STATUS_H (97),
.OUT_PKT_RESPONSE_STATUS_L (96),
.OUT_PKT_TRANS_EXCLUSIVE (71),
.OUT_PKT_BURST_TYPE_H (81),
.OUT_PKT_BURST_TYPE_L (80),
.OUT_PKT_ORI_BURST_SIZE_L (98),
.OUT_PKT_ORI_BURST_SIZE_H (100),
.OUT_ST_DATA_W (101),
.ST_CHANNEL_W (1),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) kernel_cra_s0_rsp_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_001_src_valid), // sink.valid
.in_channel (router_001_src_channel), // .channel
.in_startofpacket (router_001_src_startofpacket), // .startofpacket
.in_endofpacket (router_001_src_endofpacket), // .endofpacket
.in_ready (router_001_src_ready), // .ready
.in_data (router_001_src_data), // .data
.out_endofpacket (kernel_cra_s0_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (kernel_cra_s0_rsp_width_adapter_src_data), // .data
.out_channel (kernel_cra_s0_rsp_width_adapter_src_channel), // .channel
.out_valid (kernel_cra_s0_rsp_width_adapter_src_valid), // .valid
.out_ready (kernel_cra_s0_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (kernel_cra_s0_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
`define ENABLE_VCD
module tb_fmlbrg();
reg clk;
initial clk = 1'b0;
always #5 clk = ~clk;
reg rst;
reg [19:1] wb_adr_i;
reg [2:0] wb_cti_i;
reg [15:0] wb_dat_i;
wire [15:0] wb_dat_o;
reg [1:0] wb_sel_i;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
wire wb_ack_o;
wire [19:0] fml_adr;
wire fml_stb;
wire fml_we;
reg fml_ack;
wire [1:0] fml_sel;
wire [15:0] fml_dw;
reg [15:0] fml_dr;
reg dcb_stb;
reg [19:0] dcb_adr;
wire [15:0] dcb_dat;
wire dcb_hit;
/* Process FML requests */
reg [2:0] fml_wcount;
reg [2:0] fml_rcount;
initial begin
fml_ack = 1'b0;
fml_wcount = 0;
fml_rcount = 0;
end
always @(posedge clk) begin
if(fml_stb & (fml_wcount == 0) & (fml_rcount == 0)) begin
fml_ack <= 1'b1;
if(fml_we) begin
$display("%t FML W addr %x data %x", $time, fml_adr, fml_dw);
fml_wcount <= 7;
end else begin
fml_dr = 16'hbeef;
$display("%t FML R addr %x data %x", $time, fml_adr, fml_dr);
fml_rcount <= 7;
end
end else
fml_ack <= 1'b0;
if(fml_wcount != 0) begin
#1 $display("%t FML W continuing %x / %d", $time, fml_dw, fml_wcount);
fml_wcount <= fml_wcount - 1;
end
if(fml_rcount != 0) begin
fml_dr = #1 {13'h1eba, fml_rcount};
$display("%t FML R continuing %x / %d", $time, fml_dr, fml_rcount);
fml_rcount <= fml_rcount - 1;
end
end
fmlbrg #(
.fml_depth (20), // 8086 can only address 1 MB
.cache_depth (10) // 1 Kbyte cache
) dut (
.sys_clk(clk),
.sys_rst(rst),
.wb_adr_i(wb_adr_i),
.wb_cti_i(wb_cti_i),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_sel_i(wb_sel_i),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.wb_we_i(wb_we_i),
.wb_ack_o(wb_ack_o),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_we(fml_we),
.fml_ack(fml_ack),
.fml_sel(fml_sel),
.fml_do(fml_dw),
.fml_di(fml_dr),
.dcb_stb(dcb_stb),
.dcb_adr(dcb_adr),
.dcb_dat(dcb_dat),
.dcb_hit(dcb_hit)
);
task waitclock;
begin
@(posedge clk);
#1;
end
endtask
task wbwrite;
input [19:1] address;
input [1:0] sel;
input [15:0] data;
integer i;
begin
wb_adr_i = address;
wb_cti_i = 3'b000;
wb_dat_i = data;
wb_sel_i = sel;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b1;
i = 0;
while(~wb_ack_o) begin
i = i+1;
waitclock;
end
waitclock;
$display("WB Write: %x=%x sel=%b acked in %d clocks", address, data, sel, i);
wb_adr_i = 19'hx;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
task wbread;
input [19:1] address;
integer i;
begin
wb_adr_i = address;
wb_cti_i = 3'b000;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b0;
i = 0;
while(~wb_ack_o) begin
i = i+1;
waitclock;
end
$display("WB Read : %x=%x acked in %d clocks", address, wb_dat_o, i);
waitclock;
wb_adr_i = 19'hx;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
task wbwriteburst;
input [19:1] address;
input [15:0] data;
integer i;
begin
wb_adr_i = address;
wb_cti_i = 3'b010;
wb_dat_i = data;
wb_sel_i = 2'b11;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b1;
i = 0;
while(~wb_ack_o) begin
i = i+1;
waitclock;
end
waitclock;
$display("WB Write: %x=%x acked in %d clocks", address, data, i);
wb_dat_i = data+1;
waitclock;
wb_dat_i = data+2;
waitclock;
wb_dat_i = data+3;
wb_cti_i = 3'b111;
waitclock;
wb_adr_i = 19'hx;
wb_cti_i = 3'b000;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
task wbreadburst;
input [19:1] address;
integer i;
begin
wb_adr_i = address;
wb_cti_i = 3'b010;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b0;
i = 0;
while(~wb_ack_o) begin
i = i+1;
waitclock;
end
$display("WB Read : %x=%x acked in %d clocks", address, wb_dat_o, i);
waitclock;
$display("read burst(1): %x", wb_dat_o);
waitclock;
$display("read burst(2): %x", wb_dat_o);
waitclock;
wb_cti_i = 3'b111;
$display("read burst(3): %x", wb_dat_o);
waitclock;
wb_adr_i = 19'hx;
wb_cti_i = 3'b000;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
always begin
`ifdef ENABLE_VCD
$dumpfile("fmlbrg.vcd");
$dumpvars(0, dut);
`endif
rst = 1'b1;
wb_adr_i = 19'd0;
wb_dat_i = 16'd0;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
dcb_stb = 1'b0;
dcb_adr = 20'd0;
waitclock;
rst = 1'b0;
waitclock;
$display("Testing: read miss");
wbread(19'h0);
$display("Testing: write hit");
wbwrite(19'h0, 2'b11, 16'h5678);
wbread(19'h0);
$display("Testing: read miss on a dirty line");
wbread(19'h01000);
$display("Testing: read hit");
wbread(19'h01004);
$display("Testing: write miss");
wbwrite(19'h0, 2'b11, 16'hface);
wbread(27'h0);
wbread(27'h4);
$display("Testing: read burst");
wbreadburst(19'h40);
$display("Testing: write burst");
wbwriteburst(19'h40, 16'hcaf0);
$display("Testing: read burst");
wbreadburst(19'h40);
$display("Testing: DCB miss");
dcb_adr = 20'hfeba;
dcb_stb = 1'b1;
waitclock;
$display("Result: hit=%b dat=%x", dcb_hit, dcb_dat);
$display("Testing: DCB hit");
dcb_adr = 20'h0;
dcb_stb = 1'b1;
waitclock;
$display("Result: hit=%b dat=%x", dcb_hit, dcb_dat);
$display("Testing: DCB hit");
dcb_adr = 20'h0;
dcb_stb = 1'b1;
waitclock;
$display("Result: hit=%b dat=%x", dcb_hit, dcb_dat);
$display("Testing: DCB hit");
dcb_adr = 20'h1;
dcb_stb = 1'b1;
waitclock;
$display("Result: hit=%b dat=%x", dcb_hit, dcb_dat);
$display("Testing: DCB hit");
dcb_adr = 20'h2;
dcb_stb = 1'b1;
waitclock;
$display("Result: hit=%b dat=%x", dcb_hit, dcb_dat);
$stop;
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// sign_extender.v
// Created: 5.16.2012
// Modified: 5.16.2012
//
// Generic sign extension module
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module sign_extender
#(
parameter
INPUT_WIDTH = 8,
OUTPUT_WIDTH = 16
)
(
input [INPUT_WIDTH-1:0] original,
output reg [OUTPUT_WIDTH-1:0] sign_extended_original
);
wire [OUTPUT_WIDTH-INPUT_WIDTH-1:0] sign_extend;
generate
genvar i;
for (i = 0; i < OUTPUT_WIDTH-INPUT_WIDTH; i = i + 1) begin : gen_sign_extend
assign sign_extend[i] = (original[INPUT_WIDTH-1]) ? 1'b1 : 1'b0;
end
endgenerate
always @ * begin
sign_extended_original = {sign_extend,original};
end
endmodule
|
/*---------------------------------------------------------------
Ultrasound Interface
features: Measure the distance
This code is designed by Gang Chen and is verified by Biao Hu.
Author: Gang CHEN @ TUM
Copyritht: the copyright of this IP is belong to Gang CHEN.
Correspongding: [email protected] [email protected]
-----------------------------------------------------------------*/
module Ultrasound_interface(clk,reset_n,chipselect,address,write,writedata,read,byteenable,readdata,trigger_out,feedback_in);
parameter idle=4'b0001, trigger=4'b0010, wait_feedback=4'b0100, measure_feedback=4'b1000;
input clk;
input reset_n;
input chipselect;
input [1:0]address;
input write;
input [31:0] writedata;
input read;
input [3:0] byteenable;
output reg [31:0] readdata;
input feedback_in;
output reg trigger_out;
reg [31:0] control_reg;
reg [31:0] distance_count;
reg [31:0] state_reg;
reg control_reg_sel;
reg distance_count_sel;
reg state_reg_sel;
reg feedback_in1;
reg feedback_in2;
wire start_bit;
assign start_bit=control_reg[0];
reg trig0, trig1;
reg [31:0] tri_count; //20us 50*20=1000
reg [3:0] state;
//function apart
always@(posedge clk or negedge reset_n)
begin
if(!reset_n)
begin
trig0<=0;
trig1<=0;
end
else
begin
trig0<=start_bit;
trig1<=trig0;
end
end
always@(posedge clk or negedge reset_n)
begin
if(!reset_n)
begin
feedback_in1<=0;
feedback_in2<=0;
end
else
begin
feedback_in1<=feedback_in;
feedback_in2<=feedback_in1;
end
end
always@(posedge clk or negedge reset_n)
begin
if(!reset_n)
begin
state<=idle;
tri_count<=0;
trigger_out<=0;
state_reg<=2;
end
else
begin
case(state)
idle:
begin
tri_count<=0;
trigger_out<=0;
state_reg<=2;
if(trig0==1&&trig1==0)
begin
state<=trigger;
end
else
begin
state<=idle;
end
end
trigger:
begin
state_reg<=1; //bit 0: busy state; bit 1: data is ready
if(tri_count[10]) //1024 count is greater than 10us, 50*20=1000
begin
trigger_out<=0;
tri_count<=0;
state<=wait_feedback;
end
else
begin
trigger_out<=1;
tri_count<=tri_count+1;
state<=trigger;
end
end
wait_feedback:
begin
state_reg<=1; //bit 0: busy state; bit 1: data is ready
trigger_out<=0;
if(feedback_in1==1&&feedback_in2==0)
begin
tri_count<=tri_count+1;
state<=measure_feedback;
end
else
begin
state<=wait_feedback;
tri_count<=0;
end
end
measure_feedback:
begin
trigger_out<=0;
if(feedback_in1==1)
begin
if(tri_count[19]&&tri_count[18]&&tri_count[17])
begin
distance_count<=-1;
tri_count<=0;
state<=idle;
state_reg<=2;
end
else
begin
tri_count<=tri_count+1;
state<=measure_feedback;
state_reg<=1;//data is ready
end
end
else
begin
distance_count<=tri_count;
tri_count<=0;
state<=idle;
state_reg<=2;//bit 0: busy state; bit 1: data is ready
end
end
default:
begin
state<=idle;
tri_count<=0;
trigger_out<=0;
state_reg<=2;
end
endcase
end
end
//bus interface
always @ (address)
begin
control_reg_sel<=0;
distance_count_sel<=0;
state_reg_sel<=0;
case(address)
2'b00:control_reg_sel<=1;
2'b01:distance_count_sel<=1;
2'b10:state_reg_sel<=1;
2'b11:state_reg_sel<=1; //default value
endcase
end
//wirte control register
always @ (posedge clk or negedge reset_n)
begin
if(!reset_n)
control_reg<=0;
else
begin
if(write & chipselect & control_reg_sel)
begin
if(byteenable[0]) control_reg[7:0]<=writedata[7:0];
if(byteenable[1]) control_reg[15:8]<=writedata[15:8];
if(byteenable[2]) control_reg[23:16]<=writedata[23:16];
if(byteenable[3]) control_reg[31:24]<=writedata[31:24];
end
end
end
//read register
always @ (address or read or control_reg or distance_count or state_reg or chipselect)
begin
if(read & chipselect)
case(address)
2'b00:
begin
readdata<=control_reg;
end
2'b01:
begin
readdata<=distance_count;
end
2'b10:
begin
readdata<=state_reg;
end
2'b11:
begin
readdata<=state_reg; //default value
end
endcase
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016
// Date : Fri Sep 09 11:36:24 2016
// Host : RDS1 running 64-bit major release (build 9200)
// Command : write_verilog -mode timesim -nolib -sdf_anno true -force -file
// C:/Users/jsequeira/Proyectos/Add_Sub/Add_Sub_FPGA_Viv/Dry_runs.sim/sim_1/synth/timing/Testbench_FPU_Add_Subt_time_synth.v
// Design : FPU_Add_Subtract_Function
// Purpose : This verilog netlist is a timing simulation representation of the design and should not be modified or
// synthesized. Please ensure that this netlist is used with the corresponding SDF file.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
`define XIL_TIMING
(* SWR = "26" *)
module Add_Subt
(clk,
rst,
load_i,
Add_Sub_op_i,
Data_A_i,
PreData_B_i,
Data_Result_o,
FSM_C_o);
input clk;
input rst;
input load_i;
input Add_Sub_op_i;
input [25:0]Data_A_i;
input [25:0]PreData_B_i;
output [25:0]Data_Result_o;
output FSM_C_o;
wire Add_Sub_op_i;
wire [25:0]Data_A_i;
wire [25:0]Data_Result_o;
wire FSM_C_o;
wire [25:0]PreData_B_i;
wire [26:0]S_to_D;
wire clk;
wire load_i;
wire rst;
(* W = "26" *)
RegisterAdd__parameterized8 Add_Subt_Result
(.D(S_to_D[25:0]),
.Q(Data_Result_o),
.clk(clk),
.load(load_i),
.rst(rst));
(* W = "1" *)
RegisterAdd Add_overflow_Result
(.D(S_to_D[26]),
.Q(FSM_C_o),
.clk(clk),
.load(load_i),
.rst(rst));
(* W = "26" *)
add_sub_carry_out__parameterized0 Sgf_AS
(.Data_A(Data_A_i),
.Data_B(PreData_B_i),
.Data_S(S_to_D),
.op_mode(Add_Sub_op_i));
endmodule
(* EWR = "5" *) (* SWR = "26" *)
module Barrel_Shifter
(clk,
rst,
load_i,
Shift_Value_i,
Shift_Data_i,
Left_Right_i,
Bit_Shift_i,
N_mant_o);
input clk;
input rst;
input load_i;
input [4:0]Shift_Value_i;
input [25:0]Shift_Data_i;
input Left_Right_i;
input Bit_Shift_i;
output [25:0]N_mant_o;
wire Bit_Shift_i;
wire [25:0]Data_Reg;
wire Left_Right_i;
wire [25:0]N_mant_o;
wire [25:0]Shift_Data_i;
wire [4:0]Shift_Value_i;
wire clk;
wire load_i;
wire rst;
(* EWR = "5" *)
(* SWR = "26" *)
Mux_Array Mux_Array
(.Data_i(Shift_Data_i),
.Data_o(Data_Reg),
.FSM_left_right_i(Left_Right_i),
.Shift_Value_i(Shift_Value_i),
.bit_shift_i(Bit_Shift_i),
.clk(clk),
.load_i(1'b0),
.rst(rst));
(* W = "26" *)
RegisterAdd__parameterized7 Output_Reg
(.D(Data_Reg),
.Q(N_mant_o),
.clk(clk),
.load(load_i),
.rst(rst));
endmodule
(* W = "31" *)
module Comparator
(Data_X_i,
Data_Y_i,
gtXY_o,
eqXY_o);
input [30:0]Data_X_i;
input [30:0]Data_Y_i;
output gtXY_o;
output eqXY_o;
wire [30:0]Data_X_i;
wire [30:0]Data_Y_i;
wire eqXY_o;
wire eqXY_o_INST_0_i_10_n_0;
wire eqXY_o_INST_0_i_11_n_0;
wire eqXY_o_INST_0_i_12_n_0;
wire eqXY_o_INST_0_i_13_n_0;
wire eqXY_o_INST_0_i_1_n_0;
wire eqXY_o_INST_0_i_1_n_1;
wire eqXY_o_INST_0_i_1_n_2;
wire eqXY_o_INST_0_i_1_n_3;
wire eqXY_o_INST_0_i_2_n_0;
wire eqXY_o_INST_0_i_3_n_0;
wire eqXY_o_INST_0_i_4_n_0;
wire eqXY_o_INST_0_i_5_n_0;
wire eqXY_o_INST_0_i_5_n_1;
wire eqXY_o_INST_0_i_5_n_2;
wire eqXY_o_INST_0_i_5_n_3;
wire eqXY_o_INST_0_i_6_n_0;
wire eqXY_o_INST_0_i_7_n_0;
wire eqXY_o_INST_0_i_8_n_0;
wire eqXY_o_INST_0_i_9_n_0;
wire eqXY_o_INST_0_n_2;
wire eqXY_o_INST_0_n_3;
wire gtXY_o;
wire gtXY_o_INST_0_i_10_n_0;
wire gtXY_o_INST_0_i_10_n_1;
wire gtXY_o_INST_0_i_10_n_2;
wire gtXY_o_INST_0_i_10_n_3;
wire gtXY_o_INST_0_i_11_n_0;
wire gtXY_o_INST_0_i_12_n_0;
wire gtXY_o_INST_0_i_13_n_0;
wire gtXY_o_INST_0_i_14_n_0;
wire gtXY_o_INST_0_i_15_n_0;
wire gtXY_o_INST_0_i_16_n_0;
wire gtXY_o_INST_0_i_17_n_0;
wire gtXY_o_INST_0_i_18_n_0;
wire gtXY_o_INST_0_i_19_n_0;
wire gtXY_o_INST_0_i_19_n_1;
wire gtXY_o_INST_0_i_19_n_2;
wire gtXY_o_INST_0_i_19_n_3;
wire gtXY_o_INST_0_i_1_n_0;
wire gtXY_o_INST_0_i_1_n_1;
wire gtXY_o_INST_0_i_1_n_2;
wire gtXY_o_INST_0_i_1_n_3;
wire gtXY_o_INST_0_i_20_n_0;
wire gtXY_o_INST_0_i_21_n_0;
wire gtXY_o_INST_0_i_22_n_0;
wire gtXY_o_INST_0_i_23_n_0;
wire gtXY_o_INST_0_i_24_n_0;
wire gtXY_o_INST_0_i_25_n_0;
wire gtXY_o_INST_0_i_26_n_0;
wire gtXY_o_INST_0_i_27_n_0;
wire gtXY_o_INST_0_i_28_n_0;
wire gtXY_o_INST_0_i_29_n_0;
wire gtXY_o_INST_0_i_2_n_0;
wire gtXY_o_INST_0_i_30_n_0;
wire gtXY_o_INST_0_i_31_n_0;
wire gtXY_o_INST_0_i_32_n_0;
wire gtXY_o_INST_0_i_33_n_0;
wire gtXY_o_INST_0_i_34_n_0;
wire gtXY_o_INST_0_i_35_n_0;
wire gtXY_o_INST_0_i_3_n_0;
wire gtXY_o_INST_0_i_4_n_0;
wire gtXY_o_INST_0_i_5_n_0;
wire gtXY_o_INST_0_i_6_n_0;
wire gtXY_o_INST_0_i_7_n_0;
wire gtXY_o_INST_0_i_8_n_0;
wire gtXY_o_INST_0_i_9_n_0;
wire gtXY_o_INST_0_n_1;
wire gtXY_o_INST_0_n_2;
wire gtXY_o_INST_0_n_3;
wire [3:3]NLW_eqXY_o_INST_0_CO_UNCONNECTED;
wire [3:0]NLW_eqXY_o_INST_0_O_UNCONNECTED;
wire [3:0]NLW_eqXY_o_INST_0_i_1_O_UNCONNECTED;
wire [3:0]NLW_eqXY_o_INST_0_i_5_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_INST_0_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_INST_0_i_1_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_INST_0_i_10_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_INST_0_i_19_O_UNCONNECTED;
CARRY4 eqXY_o_INST_0
(.CI(eqXY_o_INST_0_i_1_n_0),
.CO({NLW_eqXY_o_INST_0_CO_UNCONNECTED[3],eqXY_o,eqXY_o_INST_0_n_2,eqXY_o_INST_0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_INST_0_O_UNCONNECTED[3:0]),
.S({1'b0,eqXY_o_INST_0_i_2_n_0,eqXY_o_INST_0_i_3_n_0,eqXY_o_INST_0_i_4_n_0}));
CARRY4 eqXY_o_INST_0_i_1
(.CI(eqXY_o_INST_0_i_5_n_0),
.CO({eqXY_o_INST_0_i_1_n_0,eqXY_o_INST_0_i_1_n_1,eqXY_o_INST_0_i_1_n_2,eqXY_o_INST_0_i_1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_INST_0_i_1_O_UNCONNECTED[3:0]),
.S({eqXY_o_INST_0_i_6_n_0,eqXY_o_INST_0_i_7_n_0,eqXY_o_INST_0_i_8_n_0,eqXY_o_INST_0_i_9_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_INST_0_i_10
(.I0(Data_X_i[9]),
.I1(Data_Y_i[9]),
.I2(Data_Y_i[11]),
.I3(Data_X_i[11]),
.I4(Data_Y_i[10]),
.I5(Data_X_i[10]),
.O(eqXY_o_INST_0_i_10_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_INST_0_i_11
(.I0(Data_X_i[6]),
.I1(Data_Y_i[6]),
.I2(Data_Y_i[8]),
.I3(Data_X_i[8]),
.I4(Data_Y_i[7]),
.I5(Data_X_i[7]),
.O(eqXY_o_INST_0_i_11_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_INST_0_i_12
(.I0(Data_X_i[3]),
.I1(Data_Y_i[3]),
.I2(Data_Y_i[5]),
.I3(Data_X_i[5]),
.I4(Data_Y_i[4]),
.I5(Data_X_i[4]),
.O(eqXY_o_INST_0_i_12_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_INST_0_i_13
(.I0(Data_X_i[0]),
.I1(Data_Y_i[0]),
.I2(Data_Y_i[2]),
.I3(Data_X_i[2]),
.I4(Data_Y_i[1]),
.I5(Data_X_i[1]),
.O(eqXY_o_INST_0_i_13_n_0));
LUT2 #(
.INIT(4'h9))
eqXY_o_INST_0_i_2
(.I0(Data_Y_i[30]),
.I1(Data_X_i[30]),
.O(eqXY_o_INST_0_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_INST_0_i_3
(.I0(Data_X_i[27]),
.I1(Data_Y_i[27]),
.I2(Data_Y_i[29]),
.I3(Data_X_i[29]),
.I4(Data_Y_i[28]),
.I5(Data_X_i[28]),
.O(eqXY_o_INST_0_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_INST_0_i_4
(.I0(Data_X_i[24]),
.I1(Data_Y_i[24]),
.I2(Data_Y_i[26]),
.I3(Data_X_i[26]),
.I4(Data_Y_i[25]),
.I5(Data_X_i[25]),
.O(eqXY_o_INST_0_i_4_n_0));
CARRY4 eqXY_o_INST_0_i_5
(.CI(1'b0),
.CO({eqXY_o_INST_0_i_5_n_0,eqXY_o_INST_0_i_5_n_1,eqXY_o_INST_0_i_5_n_2,eqXY_o_INST_0_i_5_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_INST_0_i_5_O_UNCONNECTED[3:0]),
.S({eqXY_o_INST_0_i_10_n_0,eqXY_o_INST_0_i_11_n_0,eqXY_o_INST_0_i_12_n_0,eqXY_o_INST_0_i_13_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_INST_0_i_6
(.I0(Data_X_i[21]),
.I1(Data_Y_i[21]),
.I2(Data_Y_i[23]),
.I3(Data_X_i[23]),
.I4(Data_Y_i[22]),
.I5(Data_X_i[22]),
.O(eqXY_o_INST_0_i_6_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_INST_0_i_7
(.I0(Data_X_i[18]),
.I1(Data_Y_i[18]),
.I2(Data_Y_i[20]),
.I3(Data_X_i[20]),
.I4(Data_Y_i[19]),
.I5(Data_X_i[19]),
.O(eqXY_o_INST_0_i_7_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_INST_0_i_8
(.I0(Data_X_i[15]),
.I1(Data_Y_i[15]),
.I2(Data_Y_i[17]),
.I3(Data_X_i[17]),
.I4(Data_Y_i[16]),
.I5(Data_X_i[16]),
.O(eqXY_o_INST_0_i_8_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_INST_0_i_9
(.I0(Data_X_i[12]),
.I1(Data_Y_i[12]),
.I2(Data_Y_i[14]),
.I3(Data_X_i[14]),
.I4(Data_Y_i[13]),
.I5(Data_X_i[13]),
.O(eqXY_o_INST_0_i_9_n_0));
CARRY4 gtXY_o_INST_0
(.CI(gtXY_o_INST_0_i_1_n_0),
.CO({gtXY_o,gtXY_o_INST_0_n_1,gtXY_o_INST_0_n_2,gtXY_o_INST_0_n_3}),
.CYINIT(1'b0),
.DI({gtXY_o_INST_0_i_2_n_0,gtXY_o_INST_0_i_3_n_0,gtXY_o_INST_0_i_4_n_0,gtXY_o_INST_0_i_5_n_0}),
.O(NLW_gtXY_o_INST_0_O_UNCONNECTED[3:0]),
.S({gtXY_o_INST_0_i_6_n_0,gtXY_o_INST_0_i_7_n_0,gtXY_o_INST_0_i_8_n_0,gtXY_o_INST_0_i_9_n_0}));
CARRY4 gtXY_o_INST_0_i_1
(.CI(gtXY_o_INST_0_i_10_n_0),
.CO({gtXY_o_INST_0_i_1_n_0,gtXY_o_INST_0_i_1_n_1,gtXY_o_INST_0_i_1_n_2,gtXY_o_INST_0_i_1_n_3}),
.CYINIT(1'b0),
.DI({gtXY_o_INST_0_i_11_n_0,gtXY_o_INST_0_i_12_n_0,gtXY_o_INST_0_i_13_n_0,gtXY_o_INST_0_i_14_n_0}),
.O(NLW_gtXY_o_INST_0_i_1_O_UNCONNECTED[3:0]),
.S({gtXY_o_INST_0_i_15_n_0,gtXY_o_INST_0_i_16_n_0,gtXY_o_INST_0_i_17_n_0,gtXY_o_INST_0_i_18_n_0}));
CARRY4 gtXY_o_INST_0_i_10
(.CI(gtXY_o_INST_0_i_19_n_0),
.CO({gtXY_o_INST_0_i_10_n_0,gtXY_o_INST_0_i_10_n_1,gtXY_o_INST_0_i_10_n_2,gtXY_o_INST_0_i_10_n_3}),
.CYINIT(1'b0),
.DI({gtXY_o_INST_0_i_20_n_0,gtXY_o_INST_0_i_21_n_0,gtXY_o_INST_0_i_22_n_0,gtXY_o_INST_0_i_23_n_0}),
.O(NLW_gtXY_o_INST_0_i_10_O_UNCONNECTED[3:0]),
.S({gtXY_o_INST_0_i_24_n_0,gtXY_o_INST_0_i_25_n_0,gtXY_o_INST_0_i_26_n_0,gtXY_o_INST_0_i_27_n_0}));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_11
(.I0(Data_X_i[22]),
.I1(Data_Y_i[22]),
.I2(Data_Y_i[23]),
.I3(Data_X_i[23]),
.O(gtXY_o_INST_0_i_11_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_12
(.I0(Data_X_i[20]),
.I1(Data_Y_i[20]),
.I2(Data_Y_i[21]),
.I3(Data_X_i[21]),
.O(gtXY_o_INST_0_i_12_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_13
(.I0(Data_X_i[18]),
.I1(Data_Y_i[18]),
.I2(Data_Y_i[19]),
.I3(Data_X_i[19]),
.O(gtXY_o_INST_0_i_13_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_14
(.I0(Data_X_i[16]),
.I1(Data_Y_i[16]),
.I2(Data_Y_i[17]),
.I3(Data_X_i[17]),
.O(gtXY_o_INST_0_i_14_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_15
(.I0(Data_X_i[22]),
.I1(Data_Y_i[22]),
.I2(Data_X_i[23]),
.I3(Data_Y_i[23]),
.O(gtXY_o_INST_0_i_15_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_16
(.I0(Data_X_i[20]),
.I1(Data_Y_i[20]),
.I2(Data_X_i[21]),
.I3(Data_Y_i[21]),
.O(gtXY_o_INST_0_i_16_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_17
(.I0(Data_X_i[18]),
.I1(Data_Y_i[18]),
.I2(Data_X_i[19]),
.I3(Data_Y_i[19]),
.O(gtXY_o_INST_0_i_17_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_18
(.I0(Data_X_i[16]),
.I1(Data_Y_i[16]),
.I2(Data_X_i[17]),
.I3(Data_Y_i[17]),
.O(gtXY_o_INST_0_i_18_n_0));
CARRY4 gtXY_o_INST_0_i_19
(.CI(1'b0),
.CO({gtXY_o_INST_0_i_19_n_0,gtXY_o_INST_0_i_19_n_1,gtXY_o_INST_0_i_19_n_2,gtXY_o_INST_0_i_19_n_3}),
.CYINIT(1'b0),
.DI({gtXY_o_INST_0_i_28_n_0,gtXY_o_INST_0_i_29_n_0,gtXY_o_INST_0_i_30_n_0,gtXY_o_INST_0_i_31_n_0}),
.O(NLW_gtXY_o_INST_0_i_19_O_UNCONNECTED[3:0]),
.S({gtXY_o_INST_0_i_32_n_0,gtXY_o_INST_0_i_33_n_0,gtXY_o_INST_0_i_34_n_0,gtXY_o_INST_0_i_35_n_0}));
LUT2 #(
.INIT(4'h2))
gtXY_o_INST_0_i_2
(.I0(Data_X_i[30]),
.I1(Data_Y_i[30]),
.O(gtXY_o_INST_0_i_2_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_20
(.I0(Data_X_i[14]),
.I1(Data_Y_i[14]),
.I2(Data_Y_i[15]),
.I3(Data_X_i[15]),
.O(gtXY_o_INST_0_i_20_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_21
(.I0(Data_X_i[12]),
.I1(Data_Y_i[12]),
.I2(Data_Y_i[13]),
.I3(Data_X_i[13]),
.O(gtXY_o_INST_0_i_21_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_22
(.I0(Data_X_i[10]),
.I1(Data_Y_i[10]),
.I2(Data_Y_i[11]),
.I3(Data_X_i[11]),
.O(gtXY_o_INST_0_i_22_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_23
(.I0(Data_X_i[8]),
.I1(Data_Y_i[8]),
.I2(Data_Y_i[9]),
.I3(Data_X_i[9]),
.O(gtXY_o_INST_0_i_23_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_24
(.I0(Data_X_i[14]),
.I1(Data_Y_i[14]),
.I2(Data_X_i[15]),
.I3(Data_Y_i[15]),
.O(gtXY_o_INST_0_i_24_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_25
(.I0(Data_X_i[12]),
.I1(Data_Y_i[12]),
.I2(Data_X_i[13]),
.I3(Data_Y_i[13]),
.O(gtXY_o_INST_0_i_25_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_26
(.I0(Data_X_i[10]),
.I1(Data_Y_i[10]),
.I2(Data_X_i[11]),
.I3(Data_Y_i[11]),
.O(gtXY_o_INST_0_i_26_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_27
(.I0(Data_X_i[8]),
.I1(Data_Y_i[8]),
.I2(Data_X_i[9]),
.I3(Data_Y_i[9]),
.O(gtXY_o_INST_0_i_27_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_28
(.I0(Data_X_i[6]),
.I1(Data_Y_i[6]),
.I2(Data_Y_i[7]),
.I3(Data_X_i[7]),
.O(gtXY_o_INST_0_i_28_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_29
(.I0(Data_X_i[4]),
.I1(Data_Y_i[4]),
.I2(Data_Y_i[5]),
.I3(Data_X_i[5]),
.O(gtXY_o_INST_0_i_29_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_3
(.I0(Data_X_i[28]),
.I1(Data_Y_i[28]),
.I2(Data_Y_i[29]),
.I3(Data_X_i[29]),
.O(gtXY_o_INST_0_i_3_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_30
(.I0(Data_X_i[2]),
.I1(Data_Y_i[2]),
.I2(Data_Y_i[3]),
.I3(Data_X_i[3]),
.O(gtXY_o_INST_0_i_30_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_31
(.I0(Data_X_i[0]),
.I1(Data_Y_i[0]),
.I2(Data_Y_i[1]),
.I3(Data_X_i[1]),
.O(gtXY_o_INST_0_i_31_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_32
(.I0(Data_X_i[6]),
.I1(Data_Y_i[6]),
.I2(Data_X_i[7]),
.I3(Data_Y_i[7]),
.O(gtXY_o_INST_0_i_32_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_33
(.I0(Data_X_i[4]),
.I1(Data_Y_i[4]),
.I2(Data_X_i[5]),
.I3(Data_Y_i[5]),
.O(gtXY_o_INST_0_i_33_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_34
(.I0(Data_X_i[2]),
.I1(Data_Y_i[2]),
.I2(Data_X_i[3]),
.I3(Data_Y_i[3]),
.O(gtXY_o_INST_0_i_34_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_35
(.I0(Data_X_i[0]),
.I1(Data_Y_i[0]),
.I2(Data_X_i[1]),
.I3(Data_Y_i[1]),
.O(gtXY_o_INST_0_i_35_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_4
(.I0(Data_X_i[26]),
.I1(Data_Y_i[26]),
.I2(Data_Y_i[27]),
.I3(Data_X_i[27]),
.O(gtXY_o_INST_0_i_4_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_5
(.I0(Data_X_i[24]),
.I1(Data_Y_i[24]),
.I2(Data_Y_i[25]),
.I3(Data_X_i[25]),
.O(gtXY_o_INST_0_i_5_n_0));
LUT2 #(
.INIT(4'h9))
gtXY_o_INST_0_i_6
(.I0(Data_Y_i[30]),
.I1(Data_X_i[30]),
.O(gtXY_o_INST_0_i_6_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_7
(.I0(Data_X_i[28]),
.I1(Data_Y_i[28]),
.I2(Data_X_i[29]),
.I3(Data_Y_i[29]),
.O(gtXY_o_INST_0_i_7_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_8
(.I0(Data_X_i[26]),
.I1(Data_Y_i[26]),
.I2(Data_X_i[27]),
.I3(Data_Y_i[27]),
.O(gtXY_o_INST_0_i_8_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_9
(.I0(Data_X_i[24]),
.I1(Data_Y_i[24]),
.I2(Data_X_i[25]),
.I3(Data_Y_i[25]),
.O(gtXY_o_INST_0_i_9_n_0));
endmodule
(* W = "9" *)
module Comparator_Less
(Data_A,
Data_B,
less);
input [8:0]Data_A;
input [8:0]Data_B;
output less;
wire [8:0]Data_A;
wire less;
wire less_INST_0_i_1_n_0;
wire less_INST_0_i_1_n_1;
wire less_INST_0_i_1_n_2;
wire less_INST_0_i_1_n_3;
wire less_INST_0_i_2_n_0;
wire less_INST_0_i_3_n_0;
wire less_INST_0_i_4_n_0;
wire less_INST_0_i_5_n_0;
wire less_INST_0_i_6_n_0;
wire less_INST_0_i_7_n_0;
wire [3:1]NLW_less_INST_0_CO_UNCONNECTED;
wire [3:0]NLW_less_INST_0_O_UNCONNECTED;
wire [3:0]NLW_less_INST_0_i_1_O_UNCONNECTED;
CARRY4 less_INST_0
(.CI(less_INST_0_i_1_n_0),
.CO({NLW_less_INST_0_CO_UNCONNECTED[3:1],less}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_less_INST_0_O_UNCONNECTED[3:0]),
.S({1'b0,1'b0,1'b0,less_INST_0_i_2_n_0}));
CARRY4 less_INST_0_i_1
(.CI(1'b0),
.CO({less_INST_0_i_1_n_0,less_INST_0_i_1_n_1,less_INST_0_i_1_n_2,less_INST_0_i_1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,less_INST_0_i_3_n_0}),
.O(NLW_less_INST_0_i_1_O_UNCONNECTED[3:0]),
.S({less_INST_0_i_4_n_0,less_INST_0_i_5_n_0,less_INST_0_i_6_n_0,less_INST_0_i_7_n_0}));
LUT1 #(
.INIT(2'h1))
less_INST_0_i_2
(.I0(Data_A[8]),
.O(less_INST_0_i_2_n_0));
LUT2 #(
.INIT(4'h1))
less_INST_0_i_3
(.I0(Data_A[0]),
.I1(Data_A[1]),
.O(less_INST_0_i_3_n_0));
LUT2 #(
.INIT(4'h1))
less_INST_0_i_4
(.I0(Data_A[6]),
.I1(Data_A[7]),
.O(less_INST_0_i_4_n_0));
LUT2 #(
.INIT(4'h1))
less_INST_0_i_5
(.I0(Data_A[4]),
.I1(Data_A[5]),
.O(less_INST_0_i_5_n_0));
LUT2 #(
.INIT(4'h1))
less_INST_0_i_6
(.I0(Data_A[2]),
.I1(Data_A[3]),
.O(less_INST_0_i_6_n_0));
LUT2 #(
.INIT(4'h2))
less_INST_0_i_7
(.I0(Data_A[0]),
.I1(Data_A[1]),
.O(less_INST_0_i_7_n_0));
endmodule
(* W_Exp = "9" *)
module Comparators
(exp,
overflow,
underflow);
input [8:0]exp;
output overflow;
output underflow;
wire [8:0]exp;
wire overflow;
wire underflow;
(* W = "9" *)
Greater_Comparator GTComparator
(.Data_A(exp),
.Data_B({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.gthan(overflow));
(* W = "9" *)
Comparator_Less LTComparator
(.Data_A(exp),
.Data_B({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.less(underflow));
endmodule
(* EW = "8" *)
module Exp_Operation
(clk,
rst,
load_a_i,
load_b_i,
Data_A_i,
Data_B_i,
Add_Subt_i,
Data_Result_o,
Overflow_flag_o,
Underflow_flag_o);
input clk;
input rst;
input load_a_i;
input load_b_i;
input [7:0]Data_A_i;
input [7:0]Data_B_i;
input Add_Subt_i;
output [7:0]Data_Result_o;
output Overflow_flag_o;
output Underflow_flag_o;
wire Add_Subt_i;
wire [7:0]Data_A_i;
wire [7:0]Data_B_i;
wire [7:0]Data_Result_o;
wire [8:0]Data_S;
wire Overflow_flag;
wire Overflow_flag_o;
wire Underflow_flag;
wire Underflow_flag_o;
wire clk;
wire load_a_i;
wire load_b_i;
wire rst;
(* W = "1" *)
RegisterAdd__6 Overflow
(.D(Overflow_flag),
.Q(Overflow_flag_o),
.clk(clk),
.load(load_a_i),
.rst(rst));
(* W = "1" *)
RegisterAdd__7 Underflow
(.D(Underflow_flag),
.Q(Underflow_flag_o),
.clk(clk),
.load(load_b_i),
.rst(rst));
(* W_Exp = "9" *)
Comparators array_comparators
(.exp(Data_S),
.overflow(Overflow_flag),
.underflow(Underflow_flag));
(* W = "8" *)
add_sub_carry_out exp_add_subt
(.Data_A(Data_A_i),
.Data_B(Data_B_i),
.Data_S(Data_S),
.op_mode(Add_Subt_i));
(* W = "8" *)
RegisterAdd__parameterized5 exp_result
(.D(Data_S[7:0]),
.Q(Data_Result_o),
.clk(clk),
.load(load_a_i),
.rst(rst));
endmodule
(* EW = "8" *) (* EWR = "5" *) (* SW = "23" *)
(* SWR = "26" *) (* W = "32" *)
(* NotValidForBitStream *)
module FPU_Add_Subtract_Function
(clk,
rst,
beg_FSM,
ack_FSM,
Data_X,
Data_Y,
add_subt,
r_mode,
overflow_flag,
underflow_flag,
ready,
final_result_ieee);
input clk;
input rst;
input beg_FSM;
input ack_FSM;
input [31:0]Data_X;
input [31:0]Data_Y;
input add_subt;
input [1:0]r_mode;
output overflow_flag;
output underflow_flag;
output ready;
output [31:0]final_result_ieee;
wire [25:0]Add_Subt_LZD;
wire [25:0]Add_Subt_result;
wire [30:0]DMP;
wire [31:0]Data_X;
wire [31:0]Data_X_IBUF;
wire [31:0]Data_Y;
wire [31:0]Data_Y_IBUF;
wire [30:0]DmP;
wire FSM_Add_Subt_Sgf_load;
wire FSM_Final_Result_load;
wire FSM_LZA_load;
wire FSM_barrel_shifter_B_S;
wire FSM_barrel_shifter_L_R;
wire FSM_barrel_shifter_load;
wire FSM_exp_operation_A_S;
wire FSM_exp_operation_load_OU;
wire FSM_exp_operation_load_diff;
wire FSM_op_start_in_load_a;
wire FSM_op_start_in_load_b;
wire FSM_selector_A;
wire [1:0]FSM_selector_B;
wire FSM_selector_C;
wire FSM_selector_D;
wire [4:0]LZA_output;
wire [25:0]S_A_S_Oper_A;
wire [25:0]S_A_S_Oper_B;
wire S_A_S_op;
wire [25:0]S_Data_Shift;
wire [7:0]S_Oper_A_exp;
wire [7:0]S_Oper_B_exp;
wire [4:0]S_Shift_Value;
wire [25:0]Sgf_normalized_result;
wire ack_FSM;
wire ack_FSM_IBUF;
wire add_overflow_flag;
wire add_subt;
wire add_subt_IBUF;
wire beg_FSM;
wire beg_FSM_IBUF;
wire clk;
wire clk_IBUF;
wire clk_IBUF_BUFG;
wire [7:0]exp_oper_result;
wire [31:0]final_result_ieee;
wire [31:0]final_result_ieee_OBUF;
wire load_b;
wire overflow_flag;
wire overflow_flag_OBUF;
wire [1:0]r_mode;
wire [1:0]r_mode_IBUF;
wire ready;
wire ready_OBUF;
wire real_op;
wire round_flag;
wire rst;
wire rst_IBUF;
wire rst_int;
wire [1:0]selector_B;
wire selector_C;
wire selector_D;
wire sign_final_result;
wire underflow_flag;
wire underflow_flag_OBUF;
wire zero_flag;
wire NLW_FS_Module_ctrl_a_o_UNCONNECTED;
initial begin
$sdf_annotate("Testbench_FPU_Add_Subt_time_synth.sdf",,,,"tool_control");
end
(* W = "26" *)
Multiplexer_AC__parameterized158 Add_Sub_Sgf_Oper_A_mux
(.D0({1'b0,DMP[22:0],1'b0,1'b0}),
.D1(Sgf_normalized_result),
.S(S_A_S_Oper_A),
.ctrl(FSM_selector_D));
(* W = "26" *)
Multiplexer_AC__parameterized159 Add_Sub_Sgf_Oper_B_mux
(.D0(Sgf_normalized_result),
.D1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S(S_A_S_Oper_B),
.ctrl(FSM_selector_D));
(* W = "1" *)
Multiplexer_AC__parameterized157 Add_Sub_Sgf_op_mux
(.D0(real_op),
.D1(1'b0),
.S(S_A_S_op),
.ctrl(FSM_selector_D));
(* SWR = "26" *)
Add_Subt Add_Subt_Sgf_module
(.Add_Sub_op_i(S_A_S_op),
.Data_A_i(S_A_S_Oper_A),
.Data_Result_o(Add_Subt_result),
.FSM_C_o(add_overflow_flag),
.PreData_B_i(S_A_S_Oper_B),
.clk(clk_IBUF_BUFG),
.load_i(FSM_Add_Subt_Sgf_load),
.rst(rst_int));
(* W = "26" *)
Multiplexer_AC__parameterized0 Barrel_Shifter_D_I_mux
(.D0({1'b0,DmP[22:0],1'b0,1'b0}),
.D1(Add_Subt_result),
.S(S_Data_Shift),
.ctrl(FSM_selector_C));
(* W = "5" *)
Mux_3x1__parameterized0 Barrel_Shifter_S_V_mux
(.D0(exp_oper_result[4:0]),
.D1(LZA_output),
.D2({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S(S_Shift_Value),
.ctrl(FSM_selector_B));
(* EWR = "5" *)
(* SWR = "26" *)
Barrel_Shifter Barrel_Shifter_module
(.Bit_Shift_i(FSM_barrel_shifter_B_S),
.Left_Right_i(FSM_barrel_shifter_L_R),
.N_mant_o(Sgf_normalized_result),
.Shift_Data_i(S_Data_Shift),
.Shift_Value_i(S_Shift_Value),
.clk(clk_IBUF_BUFG),
.load_i(FSM_barrel_shifter_load),
.rst(rst_int));
IBUF \Data_X_IBUF[0]_inst
(.I(Data_X[0]),
.O(Data_X_IBUF[0]));
IBUF \Data_X_IBUF[10]_inst
(.I(Data_X[10]),
.O(Data_X_IBUF[10]));
IBUF \Data_X_IBUF[11]_inst
(.I(Data_X[11]),
.O(Data_X_IBUF[11]));
IBUF \Data_X_IBUF[12]_inst
(.I(Data_X[12]),
.O(Data_X_IBUF[12]));
IBUF \Data_X_IBUF[13]_inst
(.I(Data_X[13]),
.O(Data_X_IBUF[13]));
IBUF \Data_X_IBUF[14]_inst
(.I(Data_X[14]),
.O(Data_X_IBUF[14]));
IBUF \Data_X_IBUF[15]_inst
(.I(Data_X[15]),
.O(Data_X_IBUF[15]));
IBUF \Data_X_IBUF[16]_inst
(.I(Data_X[16]),
.O(Data_X_IBUF[16]));
IBUF \Data_X_IBUF[17]_inst
(.I(Data_X[17]),
.O(Data_X_IBUF[17]));
IBUF \Data_X_IBUF[18]_inst
(.I(Data_X[18]),
.O(Data_X_IBUF[18]));
IBUF \Data_X_IBUF[19]_inst
(.I(Data_X[19]),
.O(Data_X_IBUF[19]));
IBUF \Data_X_IBUF[1]_inst
(.I(Data_X[1]),
.O(Data_X_IBUF[1]));
IBUF \Data_X_IBUF[20]_inst
(.I(Data_X[20]),
.O(Data_X_IBUF[20]));
IBUF \Data_X_IBUF[21]_inst
(.I(Data_X[21]),
.O(Data_X_IBUF[21]));
IBUF \Data_X_IBUF[22]_inst
(.I(Data_X[22]),
.O(Data_X_IBUF[22]));
IBUF \Data_X_IBUF[23]_inst
(.I(Data_X[23]),
.O(Data_X_IBUF[23]));
IBUF \Data_X_IBUF[24]_inst
(.I(Data_X[24]),
.O(Data_X_IBUF[24]));
IBUF \Data_X_IBUF[25]_inst
(.I(Data_X[25]),
.O(Data_X_IBUF[25]));
IBUF \Data_X_IBUF[26]_inst
(.I(Data_X[26]),
.O(Data_X_IBUF[26]));
IBUF \Data_X_IBUF[27]_inst
(.I(Data_X[27]),
.O(Data_X_IBUF[27]));
IBUF \Data_X_IBUF[28]_inst
(.I(Data_X[28]),
.O(Data_X_IBUF[28]));
IBUF \Data_X_IBUF[29]_inst
(.I(Data_X[29]),
.O(Data_X_IBUF[29]));
IBUF \Data_X_IBUF[2]_inst
(.I(Data_X[2]),
.O(Data_X_IBUF[2]));
IBUF \Data_X_IBUF[30]_inst
(.I(Data_X[30]),
.O(Data_X_IBUF[30]));
IBUF \Data_X_IBUF[31]_inst
(.I(Data_X[31]),
.O(Data_X_IBUF[31]));
IBUF \Data_X_IBUF[3]_inst
(.I(Data_X[3]),
.O(Data_X_IBUF[3]));
IBUF \Data_X_IBUF[4]_inst
(.I(Data_X[4]),
.O(Data_X_IBUF[4]));
IBUF \Data_X_IBUF[5]_inst
(.I(Data_X[5]),
.O(Data_X_IBUF[5]));
IBUF \Data_X_IBUF[6]_inst
(.I(Data_X[6]),
.O(Data_X_IBUF[6]));
IBUF \Data_X_IBUF[7]_inst
(.I(Data_X[7]),
.O(Data_X_IBUF[7]));
IBUF \Data_X_IBUF[8]_inst
(.I(Data_X[8]),
.O(Data_X_IBUF[8]));
IBUF \Data_X_IBUF[9]_inst
(.I(Data_X[9]),
.O(Data_X_IBUF[9]));
IBUF \Data_Y_IBUF[0]_inst
(.I(Data_Y[0]),
.O(Data_Y_IBUF[0]));
IBUF \Data_Y_IBUF[10]_inst
(.I(Data_Y[10]),
.O(Data_Y_IBUF[10]));
IBUF \Data_Y_IBUF[11]_inst
(.I(Data_Y[11]),
.O(Data_Y_IBUF[11]));
IBUF \Data_Y_IBUF[12]_inst
(.I(Data_Y[12]),
.O(Data_Y_IBUF[12]));
IBUF \Data_Y_IBUF[13]_inst
(.I(Data_Y[13]),
.O(Data_Y_IBUF[13]));
IBUF \Data_Y_IBUF[14]_inst
(.I(Data_Y[14]),
.O(Data_Y_IBUF[14]));
IBUF \Data_Y_IBUF[15]_inst
(.I(Data_Y[15]),
.O(Data_Y_IBUF[15]));
IBUF \Data_Y_IBUF[16]_inst
(.I(Data_Y[16]),
.O(Data_Y_IBUF[16]));
IBUF \Data_Y_IBUF[17]_inst
(.I(Data_Y[17]),
.O(Data_Y_IBUF[17]));
IBUF \Data_Y_IBUF[18]_inst
(.I(Data_Y[18]),
.O(Data_Y_IBUF[18]));
IBUF \Data_Y_IBUF[19]_inst
(.I(Data_Y[19]),
.O(Data_Y_IBUF[19]));
IBUF \Data_Y_IBUF[1]_inst
(.I(Data_Y[1]),
.O(Data_Y_IBUF[1]));
IBUF \Data_Y_IBUF[20]_inst
(.I(Data_Y[20]),
.O(Data_Y_IBUF[20]));
IBUF \Data_Y_IBUF[21]_inst
(.I(Data_Y[21]),
.O(Data_Y_IBUF[21]));
IBUF \Data_Y_IBUF[22]_inst
(.I(Data_Y[22]),
.O(Data_Y_IBUF[22]));
IBUF \Data_Y_IBUF[23]_inst
(.I(Data_Y[23]),
.O(Data_Y_IBUF[23]));
IBUF \Data_Y_IBUF[24]_inst
(.I(Data_Y[24]),
.O(Data_Y_IBUF[24]));
IBUF \Data_Y_IBUF[25]_inst
(.I(Data_Y[25]),
.O(Data_Y_IBUF[25]));
IBUF \Data_Y_IBUF[26]_inst
(.I(Data_Y[26]),
.O(Data_Y_IBUF[26]));
IBUF \Data_Y_IBUF[27]_inst
(.I(Data_Y[27]),
.O(Data_Y_IBUF[27]));
IBUF \Data_Y_IBUF[28]_inst
(.I(Data_Y[28]),
.O(Data_Y_IBUF[28]));
IBUF \Data_Y_IBUF[29]_inst
(.I(Data_Y[29]),
.O(Data_Y_IBUF[29]));
IBUF \Data_Y_IBUF[2]_inst
(.I(Data_Y[2]),
.O(Data_Y_IBUF[2]));
IBUF \Data_Y_IBUF[30]_inst
(.I(Data_Y[30]),
.O(Data_Y_IBUF[30]));
IBUF \Data_Y_IBUF[31]_inst
(.I(Data_Y[31]),
.O(Data_Y_IBUF[31]));
IBUF \Data_Y_IBUF[3]_inst
(.I(Data_Y[3]),
.O(Data_Y_IBUF[3]));
IBUF \Data_Y_IBUF[4]_inst
(.I(Data_Y[4]),
.O(Data_Y_IBUF[4]));
IBUF \Data_Y_IBUF[5]_inst
(.I(Data_Y[5]),
.O(Data_Y_IBUF[5]));
IBUF \Data_Y_IBUF[6]_inst
(.I(Data_Y[6]),
.O(Data_Y_IBUF[6]));
IBUF \Data_Y_IBUF[7]_inst
(.I(Data_Y[7]),
.O(Data_Y_IBUF[7]));
IBUF \Data_Y_IBUF[8]_inst
(.I(Data_Y[8]),
.O(Data_Y_IBUF[8]));
IBUF \Data_Y_IBUF[9]_inst
(.I(Data_Y[9]),
.O(Data_Y_IBUF[9]));
(* W = "8" *)
Multiplexer_AC__1 Exp_Oper_A_mux
(.D0(DMP[30:23]),
.D1(exp_oper_result),
.S(S_Oper_A_exp),
.ctrl(FSM_selector_A));
(* W = "8" *)
Mux_3x1 Exp_Oper_B_mux
(.D0(DmP[30:23]),
.D1({1'b0,1'b0,1'b0,LZA_output}),
.D2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S(S_Oper_B_exp),
.ctrl(FSM_selector_B));
(* EW = "8" *)
Exp_Operation Exp_Operation_Module
(.Add_Subt_i(FSM_exp_operation_A_S),
.Data_A_i(S_Oper_A_exp),
.Data_B_i(S_Oper_B_exp),
.Data_Result_o(exp_oper_result),
.Overflow_flag_o(overflow_flag_OBUF),
.Underflow_flag_o(underflow_flag_OBUF),
.clk(clk_IBUF_BUFG),
.load_a_i(FSM_exp_operation_load_diff),
.load_b_i(FSM_exp_operation_load_OU),
.rst(rst_int));
(* add_subt = "4'b0110" *)
(* add_subt_r = "4'b0111" *)
(* extra1_64 = "4'b0100" *)
(* extra2_64 = "4'b1011" *)
(* load_diff_exp = "4'b0011" *)
(* load_final_result = "4'b1101" *)
(* load_oper = "4'b0001" *)
(* norm_sgf_first = "4'b0101" *)
(* norm_sgf_r = "4'b1100" *)
(* overflow_add = "4'b1000" *)
(* overflow_add_r = "4'b1010" *)
(* ready_flag = "4'b1110" *)
(* round_sgf = "4'b1001" *)
(* start = "4'b0000" *)
(* zero_info_state = "4'b0010" *)
FSM_Add_Subtract FS_Module
(.A_S_op_o(FSM_exp_operation_A_S),
.add_overflow_i(add_overflow_flag),
.beg_FSM(beg_FSM_IBUF),
.bit_shift_o(FSM_barrel_shifter_B_S),
.clk(clk_IBUF_BUFG),
.ctrl_a_o(NLW_FS_Module_ctrl_a_o_UNCONNECTED),
.ctrl_b_load_o(load_b),
.ctrl_b_o(selector_B),
.ctrl_c_o(selector_C),
.ctrl_d_o(selector_D),
.left_right_o(FSM_barrel_shifter_L_R),
.load_1_o(FSM_op_start_in_load_a),
.load_2_o(FSM_op_start_in_load_b),
.load_3_o(FSM_exp_operation_load_diff),
.load_4_o(FSM_barrel_shifter_load),
.load_5_o(FSM_Add_Subt_Sgf_load),
.load_6_o(FSM_LZA_load),
.load_7_o(FSM_Final_Result_load),
.load_8_o(FSM_exp_operation_load_OU),
.norm_iteration_i(FSM_selector_C),
.ready(ready_OBUF),
.round_i(round_flag),
.rst(rst_IBUF),
.rst_FSM(ack_FSM_IBUF),
.rst_int(rst_int),
.zero_flag_i(zero_flag));
(* EWR = "5" *)
(* SWR = "26" *)
LZD Leading_Zero_Detector_Module
(.Add_subt_result_i(Add_Subt_LZD),
.Shift_Value_o(LZA_output),
.clk(clk_IBUF_BUFG),
.load_i(FSM_LZA_load),
.rst(rst_int));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_1
(.I0(Add_Subt_result[25]),
.O(Add_Subt_LZD[25]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_10
(.I0(Add_Subt_result[16]),
.O(Add_Subt_LZD[16]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_11
(.I0(Add_Subt_result[15]),
.O(Add_Subt_LZD[15]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_12
(.I0(Add_Subt_result[14]),
.O(Add_Subt_LZD[14]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_13
(.I0(Add_Subt_result[13]),
.O(Add_Subt_LZD[13]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_14
(.I0(Add_Subt_result[12]),
.O(Add_Subt_LZD[12]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_15
(.I0(Add_Subt_result[11]),
.O(Add_Subt_LZD[11]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_16
(.I0(Add_Subt_result[10]),
.O(Add_Subt_LZD[10]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_17
(.I0(Add_Subt_result[9]),
.O(Add_Subt_LZD[9]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_18
(.I0(Add_Subt_result[8]),
.O(Add_Subt_LZD[8]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_19
(.I0(Add_Subt_result[7]),
.O(Add_Subt_LZD[7]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_2
(.I0(Add_Subt_result[24]),
.O(Add_Subt_LZD[24]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_20
(.I0(Add_Subt_result[6]),
.O(Add_Subt_LZD[6]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_21
(.I0(Add_Subt_result[5]),
.O(Add_Subt_LZD[5]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_22
(.I0(Add_Subt_result[4]),
.O(Add_Subt_LZD[4]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_23
(.I0(Add_Subt_result[3]),
.O(Add_Subt_LZD[3]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_24
(.I0(Add_Subt_result[2]),
.O(Add_Subt_LZD[2]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_25
(.I0(Add_Subt_result[1]),
.O(Add_Subt_LZD[1]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_26
(.I0(Add_Subt_result[0]),
.O(Add_Subt_LZD[0]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_3
(.I0(Add_Subt_result[23]),
.O(Add_Subt_LZD[23]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_4
(.I0(Add_Subt_result[22]),
.O(Add_Subt_LZD[22]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_5
(.I0(Add_Subt_result[21]),
.O(Add_Subt_LZD[21]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_6
(.I0(Add_Subt_result[20]),
.O(Add_Subt_LZD[20]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_7
(.I0(Add_Subt_result[19]),
.O(Add_Subt_LZD[19]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_8
(.I0(Add_Subt_result[18]),
.O(Add_Subt_LZD[18]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_9
(.I0(Add_Subt_result[17]),
.O(Add_Subt_LZD[17]));
(* W = "32" *)
Oper_Start_In Oper_Start_in_module
(.DMP_o(DMP),
.Data_X_i(Data_X_IBUF),
.Data_Y_i(Data_Y_IBUF),
.DmP_o(DmP),
.add_subt_i(add_subt_IBUF),
.clk(clk_IBUF_BUFG),
.load_a_i(FSM_op_start_in_load_a),
.load_b_i(FSM_op_start_in_load_b),
.real_op_o(real_op),
.rst(rst_int),
.sign_final_result_o(sign_final_result),
.zero_flag_o(zero_flag));
Round_Sgf_Dec Rounding_Decoder
(.Data_i(Sgf_normalized_result[1:0]),
.Round_Flag_o(round_flag),
.Round_Type_i(r_mode_IBUF),
.Sign_Result_i(sign_final_result));
(* W = "1" *)
RegisterAdd__1 Sel_A
(.D(1'b0),
.Q(FSM_selector_A),
.clk(clk_IBUF_BUFG),
.load(selector_D),
.rst(rst_int));
(* W = "2" *)
RegisterAdd__parameterized0 Sel_B
(.D(selector_B),
.Q(FSM_selector_B),
.clk(clk_IBUF_BUFG),
.load(load_b),
.rst(rst_int));
(* W = "1" *)
RegisterAdd__2 Sel_C
(.D(1'b0),
.Q(FSM_selector_C),
.clk(clk_IBUF_BUFG),
.load(selector_C),
.rst(rst_int));
(* W = "1" *)
RegisterAdd__3 Sel_D
(.D(1'b0),
.Q(FSM_selector_D),
.clk(clk_IBUF_BUFG),
.load(selector_D),
.rst(rst_int));
IBUF ack_FSM_IBUF_inst
(.I(ack_FSM),
.O(ack_FSM_IBUF));
IBUF add_subt_IBUF_inst
(.I(add_subt),
.O(add_subt_IBUF));
IBUF beg_FSM_IBUF_inst
(.I(beg_FSM),
.O(beg_FSM_IBUF));
BUFG clk_IBUF_BUFG_inst
(.I(clk_IBUF),
.O(clk_IBUF_BUFG));
IBUF clk_IBUF_inst
(.I(clk),
.O(clk_IBUF));
(* EW = "8" *)
(* SW = "23" *)
(* W = "32" *)
Tenth_Phase final_result_ieee_Module
(.clk(clk_IBUF_BUFG),
.exp_ieee_i(exp_oper_result),
.final_result_ieee_o(final_result_ieee_OBUF),
.load_i(FSM_Final_Result_load),
.rst(rst_int),
.sel_a_i(overflow_flag_OBUF),
.sel_b_i(underflow_flag_OBUF),
.sgf_ieee_i(Sgf_normalized_result[24:2]),
.sign_i(sign_final_result));
OBUF \final_result_ieee_OBUF[0]_inst
(.I(final_result_ieee_OBUF[0]),
.O(final_result_ieee[0]));
OBUF \final_result_ieee_OBUF[10]_inst
(.I(final_result_ieee_OBUF[10]),
.O(final_result_ieee[10]));
OBUF \final_result_ieee_OBUF[11]_inst
(.I(final_result_ieee_OBUF[11]),
.O(final_result_ieee[11]));
OBUF \final_result_ieee_OBUF[12]_inst
(.I(final_result_ieee_OBUF[12]),
.O(final_result_ieee[12]));
OBUF \final_result_ieee_OBUF[13]_inst
(.I(final_result_ieee_OBUF[13]),
.O(final_result_ieee[13]));
OBUF \final_result_ieee_OBUF[14]_inst
(.I(final_result_ieee_OBUF[14]),
.O(final_result_ieee[14]));
OBUF \final_result_ieee_OBUF[15]_inst
(.I(final_result_ieee_OBUF[15]),
.O(final_result_ieee[15]));
OBUF \final_result_ieee_OBUF[16]_inst
(.I(final_result_ieee_OBUF[16]),
.O(final_result_ieee[16]));
OBUF \final_result_ieee_OBUF[17]_inst
(.I(final_result_ieee_OBUF[17]),
.O(final_result_ieee[17]));
OBUF \final_result_ieee_OBUF[18]_inst
(.I(final_result_ieee_OBUF[18]),
.O(final_result_ieee[18]));
OBUF \final_result_ieee_OBUF[19]_inst
(.I(final_result_ieee_OBUF[19]),
.O(final_result_ieee[19]));
OBUF \final_result_ieee_OBUF[1]_inst
(.I(final_result_ieee_OBUF[1]),
.O(final_result_ieee[1]));
OBUF \final_result_ieee_OBUF[20]_inst
(.I(final_result_ieee_OBUF[20]),
.O(final_result_ieee[20]));
OBUF \final_result_ieee_OBUF[21]_inst
(.I(final_result_ieee_OBUF[21]),
.O(final_result_ieee[21]));
OBUF \final_result_ieee_OBUF[22]_inst
(.I(final_result_ieee_OBUF[22]),
.O(final_result_ieee[22]));
OBUF \final_result_ieee_OBUF[23]_inst
(.I(final_result_ieee_OBUF[23]),
.O(final_result_ieee[23]));
OBUF \final_result_ieee_OBUF[24]_inst
(.I(final_result_ieee_OBUF[24]),
.O(final_result_ieee[24]));
OBUF \final_result_ieee_OBUF[25]_inst
(.I(final_result_ieee_OBUF[25]),
.O(final_result_ieee[25]));
OBUF \final_result_ieee_OBUF[26]_inst
(.I(final_result_ieee_OBUF[26]),
.O(final_result_ieee[26]));
OBUF \final_result_ieee_OBUF[27]_inst
(.I(final_result_ieee_OBUF[27]),
.O(final_result_ieee[27]));
OBUF \final_result_ieee_OBUF[28]_inst
(.I(final_result_ieee_OBUF[28]),
.O(final_result_ieee[28]));
OBUF \final_result_ieee_OBUF[29]_inst
(.I(final_result_ieee_OBUF[29]),
.O(final_result_ieee[29]));
OBUF \final_result_ieee_OBUF[2]_inst
(.I(final_result_ieee_OBUF[2]),
.O(final_result_ieee[2]));
OBUF \final_result_ieee_OBUF[30]_inst
(.I(final_result_ieee_OBUF[30]),
.O(final_result_ieee[30]));
OBUF \final_result_ieee_OBUF[31]_inst
(.I(final_result_ieee_OBUF[31]),
.O(final_result_ieee[31]));
OBUF \final_result_ieee_OBUF[3]_inst
(.I(final_result_ieee_OBUF[3]),
.O(final_result_ieee[3]));
OBUF \final_result_ieee_OBUF[4]_inst
(.I(final_result_ieee_OBUF[4]),
.O(final_result_ieee[4]));
OBUF \final_result_ieee_OBUF[5]_inst
(.I(final_result_ieee_OBUF[5]),
.O(final_result_ieee[5]));
OBUF \final_result_ieee_OBUF[6]_inst
(.I(final_result_ieee_OBUF[6]),
.O(final_result_ieee[6]));
OBUF \final_result_ieee_OBUF[7]_inst
(.I(final_result_ieee_OBUF[7]),
.O(final_result_ieee[7]));
OBUF \final_result_ieee_OBUF[8]_inst
(.I(final_result_ieee_OBUF[8]),
.O(final_result_ieee[8]));
OBUF \final_result_ieee_OBUF[9]_inst
(.I(final_result_ieee_OBUF[9]),
.O(final_result_ieee[9]));
OBUF overflow_flag_OBUF_inst
(.I(overflow_flag_OBUF),
.O(overflow_flag));
IBUF \r_mode_IBUF[0]_inst
(.I(r_mode[0]),
.O(r_mode_IBUF[0]));
IBUF \r_mode_IBUF[1]_inst
(.I(r_mode[1]),
.O(r_mode_IBUF[1]));
OBUF ready_OBUF_inst
(.I(ready_OBUF),
.O(ready));
IBUF rst_IBUF_inst
(.I(rst),
.O(rst_IBUF));
OBUF underflow_flag_OBUF_inst
(.I(underflow_flag_OBUF),
.O(underflow_flag));
endmodule
(* add_subt = "4'b0110" *) (* add_subt_r = "4'b0111" *) (* extra1_64 = "4'b0100" *)
(* extra2_64 = "4'b1011" *) (* load_diff_exp = "4'b0011" *) (* load_final_result = "4'b1101" *)
(* load_oper = "4'b0001" *) (* norm_sgf_first = "4'b0101" *) (* norm_sgf_r = "4'b1100" *)
(* overflow_add = "4'b1000" *) (* overflow_add_r = "4'b1010" *) (* ready_flag = "4'b1110" *)
(* round_sgf = "4'b1001" *) (* start = "4'b0000" *) (* zero_info_state = "4'b0010" *)
module FSM_Add_Subtract
(clk,
rst,
rst_FSM,
beg_FSM,
zero_flag_i,
norm_iteration_i,
add_overflow_i,
round_i,
load_1_o,
load_2_o,
load_3_o,
load_8_o,
A_S_op_o,
load_4_o,
left_right_o,
bit_shift_o,
load_5_o,
load_6_o,
load_7_o,
ctrl_a_o,
ctrl_b_o,
ctrl_b_load_o,
ctrl_c_o,
ctrl_d_o,
rst_int,
ready);
input clk;
input rst;
input rst_FSM;
input beg_FSM;
input zero_flag_i;
input norm_iteration_i;
input add_overflow_i;
input round_i;
output load_1_o;
output load_2_o;
output load_3_o;
output load_8_o;
output A_S_op_o;
output load_4_o;
output left_right_o;
output bit_shift_o;
output load_5_o;
output load_6_o;
output load_7_o;
output ctrl_a_o;
output [1:0]ctrl_b_o;
output ctrl_b_load_o;
output ctrl_c_o;
output ctrl_d_o;
output rst_int;
output ready;
wire \<const0> ;
wire A_S_op_o;
wire add_overflow_i;
wire beg_FSM;
wire bit_shift_o;
wire clk;
wire ctrl_b_load_o;
wire [1:0]ctrl_b_o;
wire ctrl_c_o;
wire ctrl_d_o;
wire left_right_o;
wire load_1_o;
wire load_2_o;
wire load_3_o;
wire load_4_o;
wire load_5_o;
wire load_6_o;
wire load_7_o;
wire load_8_o;
wire norm_iteration_i;
wire ready;
wire round_i;
wire rst;
wire rst_FSM;
wire rst_int;
wire [3:0]state_next;
wire [3:0]state_reg;
wire \state_reg[3]_i_1_n_0 ;
wire \state_reg[3]_i_3_n_0 ;
wire \state_reg[3]_i_4_n_0 ;
wire zero_flag_i;
assign ctrl_a_o = \<const0> ;
LUT6 #(
.INIT(64'hDFDFFBFFFFFFFFFF))
A_S_op_o_INST_0
(.I0(state_reg[3]),
.I1(state_reg[2]),
.I2(state_reg[1]),
.I3(norm_iteration_i),
.I4(state_reg[0]),
.I5(add_overflow_i),
.O(A_S_op_o));
GND GND
(.G(\<const0> ));
LUT6 #(
.INIT(64'h0704000080800000))
bit_shift_o_INST_0
(.I0(state_reg[0]),
.I1(state_reg[3]),
.I2(state_reg[1]),
.I3(norm_iteration_i),
.I4(add_overflow_i),
.I5(state_reg[2]),
.O(bit_shift_o));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h10))
ctrl_b_load_o_INST_0
(.I0(state_reg[2]),
.I1(state_reg[0]),
.I2(state_reg[3]),
.O(ctrl_b_load_o));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0010))
\ctrl_b_o[0]_INST_0
(.I0(state_reg[0]),
.I1(state_reg[2]),
.I2(state_reg[3]),
.I3(add_overflow_i),
.O(ctrl_b_o[0]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h10101000))
\ctrl_b_o[1]_INST_0
(.I0(state_reg[0]),
.I1(state_reg[2]),
.I2(state_reg[3]),
.I3(add_overflow_i),
.I4(state_reg[1]),
.O(ctrl_b_o[1]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h1000))
ctrl_c_o_INST_0
(.I0(state_reg[3]),
.I1(state_reg[0]),
.I2(state_reg[1]),
.I3(state_reg[2]),
.O(ctrl_c_o));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00400000))
ctrl_d_o_INST_0
(.I0(state_reg[2]),
.I1(state_reg[0]),
.I2(round_i),
.I3(state_reg[1]),
.I4(state_reg[3]),
.O(ctrl_d_o));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00001000))
left_right_o_INST_0
(.I0(state_reg[1]),
.I1(state_reg[3]),
.I2(state_reg[2]),
.I3(norm_iteration_i),
.I4(add_overflow_i),
.O(left_right_o));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0004))
load_1_o_INST_0
(.I0(state_reg[2]),
.I1(state_reg[0]),
.I2(state_reg[1]),
.I3(state_reg[3]),
.O(load_1_o));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0002))
load_2_o_INST_0
(.I0(state_reg[1]),
.I1(state_reg[0]),
.I2(state_reg[3]),
.I3(state_reg[2]),
.O(load_2_o));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h0188))
load_3_o_INST_0
(.I0(state_reg[1]),
.I1(state_reg[0]),
.I2(state_reg[3]),
.I3(state_reg[2]),
.O(load_3_o));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h1400))
load_4_o_INST_0
(.I0(state_reg[1]),
.I1(state_reg[0]),
.I2(state_reg[3]),
.I3(state_reg[2]),
.O(load_4_o));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h20))
load_5_o_INST_0
(.I0(state_reg[1]),
.I1(state_reg[3]),
.I2(state_reg[2]),
.O(load_5_o));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0100))
load_6_o_INST_0
(.I0(state_reg[1]),
.I1(state_reg[2]),
.I2(state_reg[0]),
.I3(state_reg[3]),
.O(load_6_o));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h4000))
load_7_o_INST_0
(.I0(state_reg[1]),
.I1(state_reg[2]),
.I2(state_reg[0]),
.I3(state_reg[3]),
.O(load_7_o));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h01800080))
load_8_o_INST_0
(.I0(state_reg[1]),
.I1(state_reg[0]),
.I2(state_reg[3]),
.I3(state_reg[2]),
.I4(norm_iteration_i),
.O(load_8_o));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h2000))
ready_INST_0
(.I0(state_reg[2]),
.I1(state_reg[0]),
.I2(state_reg[3]),
.I3(state_reg[1]),
.O(ready));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h0001))
rst_int_INST_0
(.I0(state_reg[3]),
.I1(state_reg[0]),
.I2(state_reg[1]),
.I3(state_reg[2]),
.O(rst_int));
LUT6 #(
.INIT(64'h00004A4A0A0FF5F5))
\state_reg[0]_i_1
(.I0(state_reg[3]),
.I1(norm_iteration_i),
.I2(state_reg[2]),
.I3(zero_flag_i),
.I4(state_reg[1]),
.I5(state_reg[0]),
.O(state_next[0]));
LUT6 #(
.INIT(64'h3300CFBB00FF0000))
\state_reg[1]_i_1
(.I0(round_i),
.I1(state_reg[3]),
.I2(norm_iteration_i),
.I3(state_reg[2]),
.I4(state_reg[1]),
.I5(state_reg[0]),
.O(state_next[1]));
LUT6 #(
.INIT(64'h0FBA0FBA05FA00FA))
\state_reg[2]_i_1
(.I0(state_reg[3]),
.I1(norm_iteration_i),
.I2(state_reg[2]),
.I3(state_reg[1]),
.I4(zero_flag_i),
.I5(state_reg[0]),
.O(state_next[2]));
LUT6 #(
.INIT(64'hEFEFFFFFFFFFFFFA))
\state_reg[3]_i_1
(.I0(state_reg[0]),
.I1(rst_FSM),
.I2(state_reg[3]),
.I3(beg_FSM),
.I4(state_reg[1]),
.I5(state_reg[2]),
.O(\state_reg[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hC8F0C8C0))
\state_reg[3]_i_3
(.I0(norm_iteration_i),
.I1(state_reg[2]),
.I2(state_reg[1]),
.I3(state_reg[0]),
.I4(zero_flag_i),
.O(\state_reg[3]_i_3_n_0 ));
LUT4 #(
.INIT(16'h0FF4))
\state_reg[3]_i_4
(.I0(round_i),
.I1(state_reg[0]),
.I2(state_reg[2]),
.I3(state_reg[1]),
.O(\state_reg[3]_i_4_n_0 ));
FDCE #(
.INIT(1'b0))
\state_reg_reg[0]
(.C(clk),
.CE(\state_reg[3]_i_1_n_0 ),
.CLR(rst),
.D(state_next[0]),
.Q(state_reg[0]));
FDCE #(
.INIT(1'b0))
\state_reg_reg[1]
(.C(clk),
.CE(\state_reg[3]_i_1_n_0 ),
.CLR(rst),
.D(state_next[1]),
.Q(state_reg[1]));
FDCE #(
.INIT(1'b0))
\state_reg_reg[2]
(.C(clk),
.CE(\state_reg[3]_i_1_n_0 ),
.CLR(rst),
.D(state_next[2]),
.Q(state_reg[2]));
FDCE #(
.INIT(1'b0))
\state_reg_reg[3]
(.C(clk),
.CE(\state_reg[3]_i_1_n_0 ),
.CLR(rst),
.D(state_next[3]),
.Q(state_reg[3]));
MUXF7 \state_reg_reg[3]_i_2
(.I0(\state_reg[3]_i_3_n_0 ),
.I1(\state_reg[3]_i_4_n_0 ),
.O(state_next[3]),
.S(state_reg[3]));
endmodule
(* W = "9" *)
module Greater_Comparator
(Data_A,
Data_B,
gthan);
input [8:0]Data_A;
input [8:0]Data_B;
output gthan;
wire [8:0]Data_A;
wire gthan;
wire gthan_INST_0_i_1_n_0;
wire gthan_INST_0_i_1_n_1;
wire gthan_INST_0_i_1_n_2;
wire gthan_INST_0_i_1_n_3;
wire gthan_INST_0_i_2_n_0;
wire gthan_INST_0_i_3_n_0;
wire gthan_INST_0_i_4_n_0;
wire gthan_INST_0_i_5_n_0;
wire gthan_INST_0_i_6_n_0;
wire gthan_INST_0_i_7_n_0;
wire [3:1]NLW_gthan_INST_0_CO_UNCONNECTED;
wire [3:0]NLW_gthan_INST_0_O_UNCONNECTED;
wire [3:0]NLW_gthan_INST_0_i_1_O_UNCONNECTED;
CARRY4 gthan_INST_0
(.CI(gthan_INST_0_i_1_n_0),
.CO({NLW_gthan_INST_0_CO_UNCONNECTED[3:1],gthan}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,Data_A[8]}),
.O(NLW_gthan_INST_0_O_UNCONNECTED[3:0]),
.S({1'b0,1'b0,1'b0,gthan_INST_0_i_2_n_0}));
CARRY4 gthan_INST_0_i_1
(.CI(1'b0),
.CO({gthan_INST_0_i_1_n_0,gthan_INST_0_i_1_n_1,gthan_INST_0_i_1_n_2,gthan_INST_0_i_1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,gthan_INST_0_i_3_n_0}),
.O(NLW_gthan_INST_0_i_1_O_UNCONNECTED[3:0]),
.S({gthan_INST_0_i_4_n_0,gthan_INST_0_i_5_n_0,gthan_INST_0_i_6_n_0,gthan_INST_0_i_7_n_0}));
LUT1 #(
.INIT(2'h1))
gthan_INST_0_i_2
(.I0(Data_A[8]),
.O(gthan_INST_0_i_2_n_0));
LUT2 #(
.INIT(4'h8))
gthan_INST_0_i_3
(.I0(Data_A[0]),
.I1(Data_A[1]),
.O(gthan_INST_0_i_3_n_0));
LUT2 #(
.INIT(4'h8))
gthan_INST_0_i_4
(.I0(Data_A[6]),
.I1(Data_A[7]),
.O(gthan_INST_0_i_4_n_0));
LUT2 #(
.INIT(4'h8))
gthan_INST_0_i_5
(.I0(Data_A[4]),
.I1(Data_A[5]),
.O(gthan_INST_0_i_5_n_0));
LUT2 #(
.INIT(4'h8))
gthan_INST_0_i_6
(.I0(Data_A[2]),
.I1(Data_A[3]),
.O(gthan_INST_0_i_6_n_0));
LUT2 #(
.INIT(4'h2))
gthan_INST_0_i_7
(.I0(Data_A[1]),
.I1(Data_A[0]),
.O(gthan_INST_0_i_7_n_0));
endmodule
(* EWR = "5" *) (* SWR = "26" *)
module LZD
(clk,
rst,
load_i,
Add_subt_result_i,
Shift_Value_o);
input clk;
input rst;
input load_i;
input [25:0]Add_subt_result_i;
output [4:0]Shift_Value_o;
wire [25:0]Add_subt_result_i;
wire [4:0]Codec_to_Reg;
wire [4:0]Shift_Value_o;
wire clk;
wire load_i;
wire rst;
(* W = "5" *)
RegisterAdd__parameterized9 Output_Reg
(.D(Codec_to_Reg),
.Q(Shift_Value_o),
.clk(clk),
.load(load_i),
.rst(rst));
Priority_Codec_32 \genblk1.Codec_32
(.Data_Bin_o(Codec_to_Reg),
.Data_Dec_i(Add_subt_result_i));
endmodule
(* W = "31" *)
module MultiplexTxT
(select,
D0_i,
D1_i,
S0_o,
S1_o);
input select;
input [30:0]D0_i;
input [30:0]D1_i;
output [30:0]S0_o;
output [30:0]S1_o;
wire [30:0]D0_i;
wire [30:0]D1_i;
wire [30:0]S0_o;
wire [30:0]S1_o;
wire select;
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[0]_INST_0
(.I0(D0_i[0]),
.I1(select),
.I2(D1_i[0]),
.O(S0_o[0]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[10]_INST_0
(.I0(D0_i[10]),
.I1(select),
.I2(D1_i[10]),
.O(S0_o[10]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[11]_INST_0
(.I0(D0_i[11]),
.I1(select),
.I2(D1_i[11]),
.O(S0_o[11]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[12]_INST_0
(.I0(D0_i[12]),
.I1(select),
.I2(D1_i[12]),
.O(S0_o[12]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[13]_INST_0
(.I0(D0_i[13]),
.I1(select),
.I2(D1_i[13]),
.O(S0_o[13]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[14]_INST_0
(.I0(D0_i[14]),
.I1(select),
.I2(D1_i[14]),
.O(S0_o[14]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[15]_INST_0
(.I0(D0_i[15]),
.I1(select),
.I2(D1_i[15]),
.O(S0_o[15]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[16]_INST_0
(.I0(D0_i[16]),
.I1(select),
.I2(D1_i[16]),
.O(S0_o[16]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[17]_INST_0
(.I0(D0_i[17]),
.I1(select),
.I2(D1_i[17]),
.O(S0_o[17]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[18]_INST_0
(.I0(D0_i[18]),
.I1(select),
.I2(D1_i[18]),
.O(S0_o[18]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[19]_INST_0
(.I0(D0_i[19]),
.I1(select),
.I2(D1_i[19]),
.O(S0_o[19]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[1]_INST_0
(.I0(D0_i[1]),
.I1(select),
.I2(D1_i[1]),
.O(S0_o[1]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[20]_INST_0
(.I0(D0_i[20]),
.I1(select),
.I2(D1_i[20]),
.O(S0_o[20]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[21]_INST_0
(.I0(D0_i[21]),
.I1(select),
.I2(D1_i[21]),
.O(S0_o[21]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[22]_INST_0
(.I0(D0_i[22]),
.I1(select),
.I2(D1_i[22]),
.O(S0_o[22]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[23]_INST_0
(.I0(D0_i[23]),
.I1(select),
.I2(D1_i[23]),
.O(S0_o[23]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[24]_INST_0
(.I0(D0_i[24]),
.I1(select),
.I2(D1_i[24]),
.O(S0_o[24]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[25]_INST_0
(.I0(D0_i[25]),
.I1(select),
.I2(D1_i[25]),
.O(S0_o[25]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[26]_INST_0
(.I0(D0_i[26]),
.I1(select),
.I2(D1_i[26]),
.O(S0_o[26]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[27]_INST_0
(.I0(D0_i[27]),
.I1(select),
.I2(D1_i[27]),
.O(S0_o[27]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[28]_INST_0
(.I0(D0_i[28]),
.I1(select),
.I2(D1_i[28]),
.O(S0_o[28]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[29]_INST_0
(.I0(D0_i[29]),
.I1(select),
.I2(D1_i[29]),
.O(S0_o[29]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[2]_INST_0
(.I0(D0_i[2]),
.I1(select),
.I2(D1_i[2]),
.O(S0_o[2]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[30]_INST_0
(.I0(D0_i[30]),
.I1(select),
.I2(D1_i[30]),
.O(S0_o[30]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[3]_INST_0
(.I0(D0_i[3]),
.I1(select),
.I2(D1_i[3]),
.O(S0_o[3]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[4]_INST_0
(.I0(D0_i[4]),
.I1(select),
.I2(D1_i[4]),
.O(S0_o[4]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[5]_INST_0
(.I0(D0_i[5]),
.I1(select),
.I2(D1_i[5]),
.O(S0_o[5]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[6]_INST_0
(.I0(D0_i[6]),
.I1(select),
.I2(D1_i[6]),
.O(S0_o[6]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[7]_INST_0
(.I0(D0_i[7]),
.I1(select),
.I2(D1_i[7]),
.O(S0_o[7]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[8]_INST_0
(.I0(D0_i[8]),
.I1(select),
.I2(D1_i[8]),
.O(S0_o[8]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[9]_INST_0
(.I0(D0_i[9]),
.I1(select),
.I2(D1_i[9]),
.O(S0_o[9]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[0]_INST_0
(.I0(D0_i[0]),
.I1(select),
.I2(D1_i[0]),
.O(S1_o[0]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[10]_INST_0
(.I0(D0_i[10]),
.I1(select),
.I2(D1_i[10]),
.O(S1_o[10]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[11]_INST_0
(.I0(D0_i[11]),
.I1(select),
.I2(D1_i[11]),
.O(S1_o[11]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[12]_INST_0
(.I0(D0_i[12]),
.I1(select),
.I2(D1_i[12]),
.O(S1_o[12]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[13]_INST_0
(.I0(D0_i[13]),
.I1(select),
.I2(D1_i[13]),
.O(S1_o[13]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[14]_INST_0
(.I0(D0_i[14]),
.I1(select),
.I2(D1_i[14]),
.O(S1_o[14]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[15]_INST_0
(.I0(D0_i[15]),
.I1(select),
.I2(D1_i[15]),
.O(S1_o[15]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[16]_INST_0
(.I0(D0_i[16]),
.I1(select),
.I2(D1_i[16]),
.O(S1_o[16]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[17]_INST_0
(.I0(D0_i[17]),
.I1(select),
.I2(D1_i[17]),
.O(S1_o[17]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[18]_INST_0
(.I0(D0_i[18]),
.I1(select),
.I2(D1_i[18]),
.O(S1_o[18]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[19]_INST_0
(.I0(D0_i[19]),
.I1(select),
.I2(D1_i[19]),
.O(S1_o[19]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[1]_INST_0
(.I0(D0_i[1]),
.I1(select),
.I2(D1_i[1]),
.O(S1_o[1]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[20]_INST_0
(.I0(D0_i[20]),
.I1(select),
.I2(D1_i[20]),
.O(S1_o[20]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[21]_INST_0
(.I0(D0_i[21]),
.I1(select),
.I2(D1_i[21]),
.O(S1_o[21]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[22]_INST_0
(.I0(D0_i[22]),
.I1(select),
.I2(D1_i[22]),
.O(S1_o[22]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[23]_INST_0
(.I0(D0_i[23]),
.I1(select),
.I2(D1_i[23]),
.O(S1_o[23]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[24]_INST_0
(.I0(D0_i[24]),
.I1(select),
.I2(D1_i[24]),
.O(S1_o[24]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[25]_INST_0
(.I0(D0_i[25]),
.I1(select),
.I2(D1_i[25]),
.O(S1_o[25]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[26]_INST_0
(.I0(D0_i[26]),
.I1(select),
.I2(D1_i[26]),
.O(S1_o[26]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[27]_INST_0
(.I0(D0_i[27]),
.I1(select),
.I2(D1_i[27]),
.O(S1_o[27]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[28]_INST_0
(.I0(D0_i[28]),
.I1(select),
.I2(D1_i[28]),
.O(S1_o[28]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[29]_INST_0
(.I0(D0_i[29]),
.I1(select),
.I2(D1_i[29]),
.O(S1_o[29]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[2]_INST_0
(.I0(D0_i[2]),
.I1(select),
.I2(D1_i[2]),
.O(S1_o[2]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[30]_INST_0
(.I0(D0_i[30]),
.I1(select),
.I2(D1_i[30]),
.O(S1_o[30]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[3]_INST_0
(.I0(D0_i[3]),
.I1(select),
.I2(D1_i[3]),
.O(S1_o[3]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[4]_INST_0
(.I0(D0_i[4]),
.I1(select),
.I2(D1_i[4]),
.O(S1_o[4]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[5]_INST_0
(.I0(D0_i[5]),
.I1(select),
.I2(D1_i[5]),
.O(S1_o[5]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[6]_INST_0
(.I0(D0_i[6]),
.I1(select),
.I2(D1_i[6]),
.O(S1_o[6]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[7]_INST_0
(.I0(D0_i[7]),
.I1(select),
.I2(D1_i[7]),
.O(S1_o[7]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[8]_INST_0
(.I0(D0_i[8]),
.I1(select),
.I2(D1_i[8]),
.O(S1_o[8]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[9]_INST_0
(.I0(D0_i[9]),
.I1(select),
.I2(D1_i[9]),
.O(S1_o[9]));
endmodule
(* W = "8" *)
module Multiplexer_AC
(ctrl,
D0,
D1,
S);
input ctrl;
input [7:0]D0;
input [7:0]D1;
output [7:0]S;
wire [7:0]D0;
wire [7:0]S;
wire ctrl;
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT2 #(
.INIT(4'hE))
\S[0]_INST_0
(.I0(ctrl),
.I1(D0[0]),
.O(S[0]));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT2 #(
.INIT(4'hE))
\S[1]_INST_0
(.I0(ctrl),
.I1(D0[1]),
.O(S[1]));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT2 #(
.INIT(4'hE))
\S[2]_INST_0
(.I0(ctrl),
.I1(D0[2]),
.O(S[2]));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT2 #(
.INIT(4'hE))
\S[3]_INST_0
(.I0(ctrl),
.I1(D0[3]),
.O(S[3]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT2 #(
.INIT(4'hE))
\S[4]_INST_0
(.I0(ctrl),
.I1(D0[4]),
.O(S[4]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT2 #(
.INIT(4'hE))
\S[5]_INST_0
(.I0(ctrl),
.I1(D0[5]),
.O(S[5]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT2 #(
.INIT(4'hE))
\S[6]_INST_0
(.I0(ctrl),
.I1(D0[6]),
.O(S[6]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT2 #(
.INIT(4'hE))
\S[7]_INST_0
(.I0(ctrl),
.I1(D0[7]),
.O(S[7]));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "8" *)
module Multiplexer_AC__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [7:0]D0;
input [7:0]D1;
output [7:0]S;
wire [7:0]D0;
wire [7:0]D1;
wire [7:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1[0]),
.I1(ctrl),
.I2(D0[0]),
.O(S[0]));
LUT3 #(
.INIT(8'hB8))
\S[1]_INST_0
(.I0(D1[1]),
.I1(ctrl),
.I2(D0[1]),
.O(S[1]));
LUT3 #(
.INIT(8'hB8))
\S[2]_INST_0
(.I0(D1[2]),
.I1(ctrl),
.I2(D0[2]),
.O(S[2]));
LUT3 #(
.INIT(8'hB8))
\S[3]_INST_0
(.I0(D1[3]),
.I1(ctrl),
.I2(D0[3]),
.O(S[3]));
LUT3 #(
.INIT(8'hB8))
\S[4]_INST_0
(.I0(D1[4]),
.I1(ctrl),
.I2(D0[4]),
.O(S[4]));
LUT3 #(
.INIT(8'hB8))
\S[5]_INST_0
(.I0(D1[5]),
.I1(ctrl),
.I2(D0[5]),
.O(S[5]));
LUT3 #(
.INIT(8'hB8))
\S[6]_INST_0
(.I0(D1[6]),
.I1(ctrl),
.I2(D0[6]),
.O(S[6]));
LUT3 #(
.INIT(8'hB8))
\S[7]_INST_0
(.I0(D1[7]),
.I1(ctrl),
.I2(D0[7]),
.O(S[7]));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "26" *)
module Multiplexer_AC__parameterized0
(ctrl,
D0,
D1,
S);
input ctrl;
input [25:0]D0;
input [25:0]D1;
output [25:0]S;
wire [25:0]D0;
wire [25:0]D1;
wire [25:0]S;
wire ctrl;
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT2 #(
.INIT(4'h8))
\S[0]_INST_0
(.I0(ctrl),
.I1(D1[0]),
.O(S[0]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\S[10]_INST_0
(.I0(D1[10]),
.I1(ctrl),
.I2(D0[10]),
.O(S[10]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hD8))
\S[11]_INST_0
(.I0(ctrl),
.I1(D1[11]),
.I2(D0[11]),
.O(S[11]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\S[12]_INST_0
(.I0(D1[12]),
.I1(ctrl),
.I2(D0[12]),
.O(S[12]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hD8))
\S[13]_INST_0
(.I0(ctrl),
.I1(D1[13]),
.I2(D0[13]),
.O(S[13]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\S[14]_INST_0
(.I0(D1[14]),
.I1(ctrl),
.I2(D0[14]),
.O(S[14]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hD8))
\S[15]_INST_0
(.I0(ctrl),
.I1(D1[15]),
.I2(D0[15]),
.O(S[15]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\S[16]_INST_0
(.I0(D1[16]),
.I1(ctrl),
.I2(D0[16]),
.O(S[16]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hD8))
\S[17]_INST_0
(.I0(ctrl),
.I1(D1[17]),
.I2(D0[17]),
.O(S[17]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\S[18]_INST_0
(.I0(D1[18]),
.I1(ctrl),
.I2(D0[18]),
.O(S[18]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hD8))
\S[19]_INST_0
(.I0(ctrl),
.I1(D1[19]),
.I2(D0[19]),
.O(S[19]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT2 #(
.INIT(4'h8))
\S[1]_INST_0
(.I0(ctrl),
.I1(D1[1]),
.O(S[1]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\S[20]_INST_0
(.I0(D1[20]),
.I1(ctrl),
.I2(D0[20]),
.O(S[20]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hD8))
\S[21]_INST_0
(.I0(ctrl),
.I1(D1[21]),
.I2(D0[21]),
.O(S[21]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\S[22]_INST_0
(.I0(D1[22]),
.I1(ctrl),
.I2(D0[22]),
.O(S[22]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hD8))
\S[23]_INST_0
(.I0(ctrl),
.I1(D1[23]),
.I2(D0[23]),
.O(S[23]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\S[24]_INST_0
(.I0(D1[24]),
.I1(ctrl),
.I2(D0[24]),
.O(S[24]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT2 #(
.INIT(4'hD))
\S[25]_INST_0
(.I0(ctrl),
.I1(D1[25]),
.O(S[25]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\S[2]_INST_0
(.I0(D1[2]),
.I1(ctrl),
.I2(D0[2]),
.O(S[2]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hD8))
\S[3]_INST_0
(.I0(ctrl),
.I1(D1[3]),
.I2(D0[3]),
.O(S[3]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\S[4]_INST_0
(.I0(D1[4]),
.I1(ctrl),
.I2(D0[4]),
.O(S[4]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hD8))
\S[5]_INST_0
(.I0(ctrl),
.I1(D1[5]),
.I2(D0[5]),
.O(S[5]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\S[6]_INST_0
(.I0(D1[6]),
.I1(ctrl),
.I2(D0[6]),
.O(S[6]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hD8))
\S[7]_INST_0
(.I0(ctrl),
.I1(D1[7]),
.I2(D0[7]),
.O(S[7]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\S[8]_INST_0
(.I0(D1[8]),
.I1(ctrl),
.I2(D0[8]),
.O(S[8]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hD8))
\S[9]_INST_0
(.I0(ctrl),
.I1(D1[9]),
.I2(D0[9]),
.O(S[9]));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized10
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized100
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized101
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized102
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized103
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized104
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized105
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized106
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized107
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized108
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized109
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized11
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized110
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized111
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized112
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized113
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized114
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized115
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized116
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized117
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized118
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized119
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized12
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized120
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized121
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized122
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized123
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized124
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized125
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized126
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized127
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized128
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized129
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized13
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized130
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized131
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized131__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized132
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized132__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized133
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized133__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized134
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized134__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized135
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized135__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized136
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized136__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized137
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized137__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized138
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized138__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized139
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized139__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized14
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized140
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized140__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized141
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized141__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized142
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized142__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized143
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized143__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized144
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized144__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized145
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized145__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized146
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized146__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized147
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized147__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized148
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized148__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized149
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized149__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized15
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized150
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized150__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized151
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized151__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized152
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized152__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized153
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized153__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized154
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized154__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized155
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized155__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized156
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized156__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized157
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]S;
wire ctrl;
LUT2 #(
.INIT(4'h2))
\S[0]_INST_0
(.I0(D0),
.I1(ctrl),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "26" *)
module Multiplexer_AC__parameterized158
(ctrl,
D0,
D1,
S);
input ctrl;
input [25:0]D0;
input [25:0]D1;
output [25:0]S;
wire [25:0]D0;
wire [25:0]D1;
wire [25:0]S;
wire ctrl;
LUT2 #(
.INIT(4'h8))
\S[0]_INST_0
(.I0(ctrl),
.I1(D1[0]),
.O(S[0]));
LUT3 #(
.INIT(8'hB8))
\S[10]_INST_0
(.I0(D1[10]),
.I1(ctrl),
.I2(D0[10]),
.O(S[10]));
LUT3 #(
.INIT(8'hB8))
\S[11]_INST_0
(.I0(D1[11]),
.I1(ctrl),
.I2(D0[11]),
.O(S[11]));
LUT3 #(
.INIT(8'hB8))
\S[12]_INST_0
(.I0(D1[12]),
.I1(ctrl),
.I2(D0[12]),
.O(S[12]));
LUT3 #(
.INIT(8'hB8))
\S[13]_INST_0
(.I0(D1[13]),
.I1(ctrl),
.I2(D0[13]),
.O(S[13]));
LUT3 #(
.INIT(8'hB8))
\S[14]_INST_0
(.I0(D1[14]),
.I1(ctrl),
.I2(D0[14]),
.O(S[14]));
LUT3 #(
.INIT(8'hB8))
\S[15]_INST_0
(.I0(D1[15]),
.I1(ctrl),
.I2(D0[15]),
.O(S[15]));
LUT3 #(
.INIT(8'hB8))
\S[16]_INST_0
(.I0(D1[16]),
.I1(ctrl),
.I2(D0[16]),
.O(S[16]));
LUT3 #(
.INIT(8'hB8))
\S[17]_INST_0
(.I0(D1[17]),
.I1(ctrl),
.I2(D0[17]),
.O(S[17]));
LUT3 #(
.INIT(8'hB8))
\S[18]_INST_0
(.I0(D1[18]),
.I1(ctrl),
.I2(D0[18]),
.O(S[18]));
LUT3 #(
.INIT(8'hB8))
\S[19]_INST_0
(.I0(D1[19]),
.I1(ctrl),
.I2(D0[19]),
.O(S[19]));
LUT2 #(
.INIT(4'h8))
\S[1]_INST_0
(.I0(ctrl),
.I1(D1[1]),
.O(S[1]));
LUT3 #(
.INIT(8'hB8))
\S[20]_INST_0
(.I0(D1[20]),
.I1(ctrl),
.I2(D0[20]),
.O(S[20]));
LUT3 #(
.INIT(8'hB8))
\S[21]_INST_0
(.I0(D1[21]),
.I1(ctrl),
.I2(D0[21]),
.O(S[21]));
LUT3 #(
.INIT(8'hB8))
\S[22]_INST_0
(.I0(D1[22]),
.I1(ctrl),
.I2(D0[22]),
.O(S[22]));
LUT3 #(
.INIT(8'hB8))
\S[23]_INST_0
(.I0(D1[23]),
.I1(ctrl),
.I2(D0[23]),
.O(S[23]));
LUT3 #(
.INIT(8'hB8))
\S[24]_INST_0
(.I0(D1[24]),
.I1(ctrl),
.I2(D0[24]),
.O(S[24]));
LUT2 #(
.INIT(4'hB))
\S[25]_INST_0
(.I0(D1[25]),
.I1(ctrl),
.O(S[25]));
LUT3 #(
.INIT(8'hB8))
\S[2]_INST_0
(.I0(D1[2]),
.I1(ctrl),
.I2(D0[2]),
.O(S[2]));
LUT3 #(
.INIT(8'hB8))
\S[3]_INST_0
(.I0(D1[3]),
.I1(ctrl),
.I2(D0[3]),
.O(S[3]));
LUT3 #(
.INIT(8'hB8))
\S[4]_INST_0
(.I0(D1[4]),
.I1(ctrl),
.I2(D0[4]),
.O(S[4]));
LUT3 #(
.INIT(8'hB8))
\S[5]_INST_0
(.I0(D1[5]),
.I1(ctrl),
.I2(D0[5]),
.O(S[5]));
LUT3 #(
.INIT(8'hB8))
\S[6]_INST_0
(.I0(D1[6]),
.I1(ctrl),
.I2(D0[6]),
.O(S[6]));
LUT3 #(
.INIT(8'hB8))
\S[7]_INST_0
(.I0(D1[7]),
.I1(ctrl),
.I2(D0[7]),
.O(S[7]));
LUT3 #(
.INIT(8'hB8))
\S[8]_INST_0
(.I0(D1[8]),
.I1(ctrl),
.I2(D0[8]),
.O(S[8]));
LUT3 #(
.INIT(8'hB8))
\S[9]_INST_0
(.I0(D1[9]),
.I1(ctrl),
.I2(D0[9]),
.O(S[9]));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "26" *)
module Multiplexer_AC__parameterized159
(ctrl,
D0,
D1,
S);
input ctrl;
input [25:0]D0;
input [25:0]D1;
output [25:0]S;
wire [25:0]D0;
wire [25:0]S;
wire ctrl;
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT2 #(
.INIT(4'h4))
\S[0]_INST_0
(.I0(ctrl),
.I1(D0[0]),
.O(S[0]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT2 #(
.INIT(4'h4))
\S[10]_INST_0
(.I0(ctrl),
.I1(D0[10]),
.O(S[10]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT2 #(
.INIT(4'h2))
\S[11]_INST_0
(.I0(D0[11]),
.I1(ctrl),
.O(S[11]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT2 #(
.INIT(4'h4))
\S[12]_INST_0
(.I0(ctrl),
.I1(D0[12]),
.O(S[12]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT2 #(
.INIT(4'h2))
\S[13]_INST_0
(.I0(D0[13]),
.I1(ctrl),
.O(S[13]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT2 #(
.INIT(4'h4))
\S[14]_INST_0
(.I0(ctrl),
.I1(D0[14]),
.O(S[14]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT2 #(
.INIT(4'h2))
\S[15]_INST_0
(.I0(D0[15]),
.I1(ctrl),
.O(S[15]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT2 #(
.INIT(4'h4))
\S[16]_INST_0
(.I0(ctrl),
.I1(D0[16]),
.O(S[16]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT2 #(
.INIT(4'h2))
\S[17]_INST_0
(.I0(D0[17]),
.I1(ctrl),
.O(S[17]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT2 #(
.INIT(4'h4))
\S[18]_INST_0
(.I0(ctrl),
.I1(D0[18]),
.O(S[18]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT2 #(
.INIT(4'h2))
\S[19]_INST_0
(.I0(D0[19]),
.I1(ctrl),
.O(S[19]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT2 #(
.INIT(4'h2))
\S[1]_INST_0
(.I0(D0[1]),
.I1(ctrl),
.O(S[1]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT2 #(
.INIT(4'h4))
\S[20]_INST_0
(.I0(ctrl),
.I1(D0[20]),
.O(S[20]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT2 #(
.INIT(4'h2))
\S[21]_INST_0
(.I0(D0[21]),
.I1(ctrl),
.O(S[21]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT2 #(
.INIT(4'h4))
\S[22]_INST_0
(.I0(ctrl),
.I1(D0[22]),
.O(S[22]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT2 #(
.INIT(4'h2))
\S[23]_INST_0
(.I0(D0[23]),
.I1(ctrl),
.O(S[23]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT2 #(
.INIT(4'h4))
\S[24]_INST_0
(.I0(ctrl),
.I1(D0[24]),
.O(S[24]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT2 #(
.INIT(4'h2))
\S[25]_INST_0
(.I0(D0[25]),
.I1(ctrl),
.O(S[25]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT2 #(
.INIT(4'hE))
\S[2]_INST_0
(.I0(ctrl),
.I1(D0[2]),
.O(S[2]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT2 #(
.INIT(4'h2))
\S[3]_INST_0
(.I0(D0[3]),
.I1(ctrl),
.O(S[3]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT2 #(
.INIT(4'h4))
\S[4]_INST_0
(.I0(ctrl),
.I1(D0[4]),
.O(S[4]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT2 #(
.INIT(4'h2))
\S[5]_INST_0
(.I0(D0[5]),
.I1(ctrl),
.O(S[5]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT2 #(
.INIT(4'h4))
\S[6]_INST_0
(.I0(ctrl),
.I1(D0[6]),
.O(S[6]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT2 #(
.INIT(4'h2))
\S[7]_INST_0
(.I0(D0[7]),
.I1(ctrl),
.O(S[7]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT2 #(
.INIT(4'h4))
\S[8]_INST_0
(.I0(ctrl),
.I1(D0[8]),
.O(S[8]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT2 #(
.INIT(4'h2))
\S[9]_INST_0
(.I0(D0[9]),
.I1(ctrl),
.O(S[9]));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized16
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "23" *)
module Multiplexer_AC__parameterized160
(ctrl,
D0,
D1,
S);
input ctrl;
input [22:0]D0;
input [22:0]D1;
output [22:0]S;
wire [22:0]D0;
wire [22:0]S;
wire ctrl;
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT2 #(
.INIT(4'h2))
\S[0]_INST_0
(.I0(D0[0]),
.I1(ctrl),
.O(S[0]));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT2 #(
.INIT(4'h2))
\S[10]_INST_0
(.I0(D0[10]),
.I1(ctrl),
.O(S[10]));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT2 #(
.INIT(4'h4))
\S[11]_INST_0
(.I0(ctrl),
.I1(D0[11]),
.O(S[11]));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT2 #(
.INIT(4'h2))
\S[12]_INST_0
(.I0(D0[12]),
.I1(ctrl),
.O(S[12]));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT2 #(
.INIT(4'h4))
\S[13]_INST_0
(.I0(ctrl),
.I1(D0[13]),
.O(S[13]));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT2 #(
.INIT(4'h2))
\S[14]_INST_0
(.I0(D0[14]),
.I1(ctrl),
.O(S[14]));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT2 #(
.INIT(4'h4))
\S[15]_INST_0
(.I0(ctrl),
.I1(D0[15]),
.O(S[15]));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT2 #(
.INIT(4'h2))
\S[16]_INST_0
(.I0(D0[16]),
.I1(ctrl),
.O(S[16]));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT2 #(
.INIT(4'h4))
\S[17]_INST_0
(.I0(ctrl),
.I1(D0[17]),
.O(S[17]));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT2 #(
.INIT(4'h2))
\S[18]_INST_0
(.I0(D0[18]),
.I1(ctrl),
.O(S[18]));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT2 #(
.INIT(4'h4))
\S[19]_INST_0
(.I0(ctrl),
.I1(D0[19]),
.O(S[19]));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT2 #(
.INIT(4'h4))
\S[1]_INST_0
(.I0(ctrl),
.I1(D0[1]),
.O(S[1]));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT2 #(
.INIT(4'h2))
\S[20]_INST_0
(.I0(D0[20]),
.I1(ctrl),
.O(S[20]));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT2 #(
.INIT(4'h4))
\S[21]_INST_0
(.I0(ctrl),
.I1(D0[21]),
.O(S[21]));
LUT2 #(
.INIT(4'h2))
\S[22]_INST_0
(.I0(D0[22]),
.I1(ctrl),
.O(S[22]));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT2 #(
.INIT(4'h2))
\S[2]_INST_0
(.I0(D0[2]),
.I1(ctrl),
.O(S[2]));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT2 #(
.INIT(4'h4))
\S[3]_INST_0
(.I0(ctrl),
.I1(D0[3]),
.O(S[3]));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT2 #(
.INIT(4'h2))
\S[4]_INST_0
(.I0(D0[4]),
.I1(ctrl),
.O(S[4]));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT2 #(
.INIT(4'h4))
\S[5]_INST_0
(.I0(ctrl),
.I1(D0[5]),
.O(S[5]));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT2 #(
.INIT(4'h2))
\S[6]_INST_0
(.I0(D0[6]),
.I1(ctrl),
.O(S[6]));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT2 #(
.INIT(4'h4))
\S[7]_INST_0
(.I0(ctrl),
.I1(D0[7]),
.O(S[7]));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT2 #(
.INIT(4'h2))
\S[8]_INST_0
(.I0(D0[8]),
.I1(ctrl),
.O(S[8]));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT2 #(
.INIT(4'h4))
\S[9]_INST_0
(.I0(ctrl),
.I1(D0[9]),
.O(S[9]));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized17
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized18
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized19
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized2
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized20
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized21
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized22
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized23
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized24
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized25
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized26
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized27
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized28
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized29
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized3
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized30
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized31
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized32
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized33
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized34
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized35
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized36
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized37
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized38
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized39
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized4
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized40
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized41
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized42
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized43
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized44
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized45
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized46
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized47
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized48
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized49
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized5
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized50
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized51
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized52
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized53
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized54
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized55
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized56
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized57
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized58
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized59
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized6
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized60
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized61
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized62
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized63
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized64
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized65
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized66
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized67
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized68
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized69
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized7
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized70
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized71
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized72
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized73
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized74
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized75
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized76
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized77
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized78
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized79
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized8
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized80
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized81
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized82
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized83
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized84
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized85
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized86
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized87
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized88
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized89
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized9
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized90
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized91
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized92
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized93
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized94
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized95
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized96
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized97
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized98
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized99
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* W = "8" *)
module Mux_3x1
(ctrl,
D0,
D1,
D2,
S);
input [1:0]ctrl;
input [7:0]D0;
input [7:0]D1;
input [7:0]D2;
output [7:0]S;
wire [7:0]D0;
wire [7:0]D1;
wire [7:0]S;
wire [1:0]ctrl;
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT4 #(
.INIT(16'h3B38))
\S[0]_INST_0
(.I0(D1[0]),
.I1(ctrl[0]),
.I2(ctrl[1]),
.I3(D0[0]),
.O(S[0]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT4 #(
.INIT(16'h00B8))
\S[1]_INST_0
(.I0(D1[1]),
.I1(ctrl[0]),
.I2(D0[1]),
.I3(ctrl[1]),
.O(S[1]));
LUT4 #(
.INIT(16'h00B8))
\S[2]_INST_0
(.I0(D1[2]),
.I1(ctrl[0]),
.I2(D0[2]),
.I3(ctrl[1]),
.O(S[2]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT4 #(
.INIT(16'h00B8))
\S[3]_INST_0
(.I0(D1[3]),
.I1(ctrl[0]),
.I2(D0[3]),
.I3(ctrl[1]),
.O(S[3]));
LUT4 #(
.INIT(16'h00B8))
\S[4]_INST_0
(.I0(D1[4]),
.I1(ctrl[0]),
.I2(D0[4]),
.I3(ctrl[1]),
.O(S[4]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'h10))
\S[5]_INST_0
(.I0(ctrl[0]),
.I1(ctrl[1]),
.I2(D0[5]),
.O(S[5]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'h10))
\S[6]_INST_0
(.I0(ctrl[0]),
.I1(ctrl[1]),
.I2(D0[6]),
.O(S[6]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'h10))
\S[7]_INST_0
(.I0(ctrl[0]),
.I1(ctrl[1]),
.I2(D0[7]),
.O(S[7]));
endmodule
(* ORIG_REF_NAME = "Mux_3x1" *) (* W = "5" *)
module Mux_3x1__parameterized0
(ctrl,
D0,
D1,
D2,
S);
input [1:0]ctrl;
input [4:0]D0;
input [4:0]D1;
input [4:0]D2;
output [4:0]S;
wire [4:0]D0;
wire [4:0]D1;
wire [4:0]S;
wire [1:0]ctrl;
LUT4 #(
.INIT(16'h3B38))
\S[0]_INST_0
(.I0(D1[0]),
.I1(ctrl[0]),
.I2(ctrl[1]),
.I3(D0[0]),
.O(S[0]));
LUT4 #(
.INIT(16'h00B8))
\S[1]_INST_0
(.I0(D1[1]),
.I1(ctrl[0]),
.I2(D0[1]),
.I3(ctrl[1]),
.O(S[1]));
LUT4 #(
.INIT(16'h00B8))
\S[2]_INST_0
(.I0(D1[2]),
.I1(ctrl[0]),
.I2(D0[2]),
.I3(ctrl[1]),
.O(S[2]));
LUT4 #(
.INIT(16'h00B8))
\S[3]_INST_0
(.I0(D1[3]),
.I1(ctrl[0]),
.I2(D0[3]),
.I3(ctrl[1]),
.O(S[3]));
LUT4 #(
.INIT(16'h00B8))
\S[4]_INST_0
(.I0(D1[4]),
.I1(ctrl[0]),
.I2(D0[4]),
.I3(ctrl[1]),
.O(S[4]));
endmodule
(* ORIG_REF_NAME = "Mux_3x1" *) (* W = "1" *)
module Mux_3x1__parameterized1
(ctrl,
D0,
D1,
D2,
S);
input [1:0]ctrl;
input [0:0]D0;
input [0:0]D1;
input [0:0]D2;
output [0:0]S;
wire [0:0]D0;
wire [0:0]S;
wire [1:0]ctrl;
LUT3 #(
.INIT(8'h0E))
\S[0]_INST_0
(.I0(ctrl[0]),
.I1(D0),
.I2(ctrl[1]),
.O(S));
endmodule
(* EWR = "5" *) (* SWR = "26" *)
module Mux_Array
(clk,
rst,
load_i,
Shift_Value_i,
Data_i,
FSM_left_right_i,
bit_shift_i,
Data_o);
input clk;
input rst;
input load_i;
input [4:0]Shift_Value_i;
input [25:0]Data_i;
input FSM_left_right_i;
input bit_shift_i;
output [25:0]Data_o;
wire [25:0]\Data_array[0] ;
wire [25:0]\Data_array[1] ;
wire [25:0]\Data_array[2] ;
wire [25:0]\Data_array[3] ;
wire [25:0]\Data_array[4] ;
wire [25:0]\Data_array[5] ;
wire [25:0]\Data_array[6] ;
wire [25:0]Data_i;
wire [25:0]Data_o;
wire FSM_left_right_i;
wire [4:0]Shift_Value_i;
wire bit_shift_i;
wire clk;
wire rst;
(* W = "26" *)
RegisterAdd__parameterized6 Mid_Reg
(.D(\Data_array[3] ),
.Q(\Data_array[4] ),
.clk(clk),
.load(1'b0),
.rst(rst));
(* SWR = "26" *)
Rotate_Mux_Array__1 first_rotate
(.Data_i(Data_i),
.Data_o(\Data_array[0] ),
.select_i(FSM_left_right_i));
(* LEVEL = "0" *)
(* SWR = "26" *)
shift_mux_array \genblk1[0].shift_mux_array
(.Data_i(\Data_array[0] ),
.Data_o(\Data_array[1] ),
.bit_shift_i(bit_shift_i),
.select_i(Shift_Value_i[0]));
(* LEVEL = "1" *)
(* SWR = "26" *)
shift_mux_array__parameterized0 \genblk1[1].shift_mux_array
(.Data_i(\Data_array[1] ),
.Data_o(\Data_array[2] ),
.bit_shift_i(bit_shift_i),
.select_i(Shift_Value_i[1]));
(* LEVEL = "2" *)
(* SWR = "26" *)
shift_mux_array__parameterized1 \genblk1[2].shift_mux_array
(.Data_i(\Data_array[2] ),
.Data_o(\Data_array[3] ),
.bit_shift_i(bit_shift_i),
.select_i(Shift_Value_i[2]));
(* LEVEL = "3" *)
(* SWR = "26" *)
shift_mux_array__parameterized2 \genblk2[3].shift_mux_array
(.Data_i(\Data_array[4] ),
.Data_o(\Data_array[5] ),
.bit_shift_i(bit_shift_i),
.select_i(Shift_Value_i[3]));
(* LEVEL = "4" *)
(* SWR = "26" *)
shift_mux_array__parameterized3 \genblk2[4].shift_mux_array
(.Data_i(\Data_array[5] ),
.Data_o(\Data_array[6] ),
.bit_shift_i(bit_shift_i),
.select_i(Shift_Value_i[4]));
(* SWR = "26" *)
Rotate_Mux_Array last_rotate
(.Data_i(\Data_array[6] ),
.Data_o(Data_o),
.select_i(FSM_left_right_i));
endmodule
(* W = "32" *)
module Oper_Start_In
(clk,
rst,
load_a_i,
load_b_i,
add_subt_i,
Data_X_i,
Data_Y_i,
DMP_o,
DmP_o,
zero_flag_o,
real_op_o,
sign_final_result_o);
input clk;
input rst;
input load_a_i;
input load_b_i;
input add_subt_i;
input [31:0]Data_X_i;
input [31:0]Data_Y_i;
output [30:0]DMP_o;
output [30:0]DmP_o;
output zero_flag_o;
output real_op_o;
output sign_final_result_o;
wire [30:0]DMP_o;
wire [31:0]Data_X_i;
wire [31:0]Data_Y_i;
wire [30:0]DmP_o;
wire add_subt_i;
wire clk;
wire eqXY;
wire gtXY;
wire intAS;
wire [31:0]intDX;
wire [31:0]intDY;
wire [30:0]intM;
wire [30:0]intm;
wire load_a_i;
wire load_b_i;
wire real_op_o;
wire rst;
wire sign_final_result_o;
wire sign_result;
wire zero_flag_o;
(* W = "1" *)
RegisterAdd__4 ASRegister
(.D(add_subt_i),
.Q(intAS),
.clk(clk),
.load(load_a_i),
.rst(rst));
(* W = "31" *)
RegisterAdd__parameterized3 MRegister
(.D(intM),
.Q(DMP_o),
.clk(clk),
.load(load_b_i),
.rst(rst));
(* W = "31" *)
Comparator Magnitude_Comparator
(.Data_X_i(intDX[30:0]),
.Data_Y_i(intDY[30:0]),
.eqXY_o(eqXY),
.gtXY_o(gtXY));
(* W = "31" *)
MultiplexTxT MuxXY
(.D0_i(intDX[30:0]),
.D1_i(intDY[30:0]),
.S0_o(intM),
.S1_o(intm),
.select(gtXY));
(* W = "32" *)
xor_tri Op_verification
(.A_i(intDX[31]),
.B_i(intDY[31]),
.C_i(intAS),
.Z_o(real_op_o));
(* W = "1" *)
RegisterAdd__5 SignRegister
(.D(sign_result),
.Q(sign_final_result_o),
.clk(clk),
.load(load_b_i),
.rst(rst));
(* W = "32" *)
RegisterAdd__parameterized1 XRegister
(.D(Data_X_i),
.Q(intDX),
.clk(clk),
.load(load_a_i),
.rst(rst));
(* W = "32" *)
RegisterAdd__parameterized2 YRegister
(.D(Data_Y_i),
.Q(intDY),
.clk(clk),
.load(load_a_i),
.rst(rst));
(* W = "31" *)
RegisterAdd__parameterized4 mRegister
(.D(intm),
.Q(DmP_o),
.clk(clk),
.load(load_b_i),
.rst(rst));
sgn_result result_sign_bit
(.Add_Subt_i(intAS),
.eqXY_i(eqXY),
.gtXY_i(gtXY),
.sgn_X_i(intDX[31]),
.sgn_Y_i(intDY[31]),
.sgn_result_o(sign_result));
LUT2 #(
.INIT(4'h8))
zero_flag_o_INST_0
(.I0(real_op_o),
.I1(eqXY),
.O(zero_flag_o));
endmodule
module Priority_Codec_32
(Data_Dec_i,
Data_Bin_o);
input [25:0]Data_Dec_i;
output [4:0]Data_Bin_o;
wire [4:0]Data_Bin_o;
wire \Data_Bin_o[0]_INST_0_i_1_n_0 ;
wire \Data_Bin_o[0]_INST_0_i_2_n_0 ;
wire \Data_Bin_o[0]_INST_0_i_3_n_0 ;
wire \Data_Bin_o[0]_INST_0_i_4_n_0 ;
wire \Data_Bin_o[0]_INST_0_i_5_n_0 ;
wire \Data_Bin_o[0]_INST_0_i_6_n_0 ;
wire \Data_Bin_o[0]_INST_0_i_7_n_0 ;
wire \Data_Bin_o[0]_INST_0_i_8_n_0 ;
wire \Data_Bin_o[1]_INST_0_i_1_n_0 ;
wire \Data_Bin_o[1]_INST_0_i_2_n_0 ;
wire \Data_Bin_o[1]_INST_0_i_3_n_0 ;
wire \Data_Bin_o[1]_INST_0_i_4_n_0 ;
wire \Data_Bin_o[1]_INST_0_i_5_n_0 ;
wire \Data_Bin_o[1]_INST_0_i_6_n_0 ;
wire \Data_Bin_o[1]_INST_0_i_7_n_0 ;
wire \Data_Bin_o[1]_INST_0_i_8_n_0 ;
wire \Data_Bin_o[2]_INST_0_i_1_n_0 ;
wire \Data_Bin_o[2]_INST_0_i_2_n_0 ;
wire \Data_Bin_o[3]_INST_0_i_1_n_0 ;
wire \Data_Bin_o[3]_INST_0_i_2_n_0 ;
wire \Data_Bin_o[3]_INST_0_i_3_n_0 ;
wire \Data_Bin_o[3]_INST_0_i_4_n_0 ;
wire \Data_Bin_o[3]_INST_0_i_5_n_0 ;
wire \Data_Bin_o[4]_INST_0_i_1_n_0 ;
wire \Data_Bin_o[4]_INST_0_i_2_n_0 ;
wire \Data_Bin_o[4]_INST_0_i_3_n_0 ;
wire \Data_Bin_o[4]_INST_0_i_4_n_0 ;
wire \Data_Bin_o[4]_INST_0_i_5_n_0 ;
wire [25:0]Data_Dec_i;
LUT6 #(
.INIT(64'hFE00FFFFFE00FE00))
\Data_Bin_o[0]_INST_0
(.I0(\Data_Bin_o[0]_INST_0_i_1_n_0 ),
.I1(\Data_Bin_o[0]_INST_0_i_2_n_0 ),
.I2(\Data_Bin_o[0]_INST_0_i_3_n_0 ),
.I3(\Data_Bin_o[0]_INST_0_i_4_n_0 ),
.I4(Data_Dec_i[24]),
.I5(Data_Dec_i[25]),
.O(Data_Bin_o[0]));
LUT5 #(
.INIT(32'h5DFFFFFF))
\Data_Bin_o[0]_INST_0_i_1
(.I0(Data_Dec_i[18]),
.I1(Data_Dec_i[17]),
.I2(Data_Dec_i[16]),
.I3(Data_Dec_i[22]),
.I4(Data_Dec_i[20]),
.O(\Data_Bin_o[0]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'h5555444455554044))
\Data_Bin_o[0]_INST_0_i_2
(.I0(\Data_Bin_o[0]_INST_0_i_5_n_0 ),
.I1(Data_Dec_i[9]),
.I2(\Data_Bin_o[0]_INST_0_i_6_n_0 ),
.I3(Data_Dec_i[8]),
.I4(\Data_Bin_o[0]_INST_0_i_7_n_0 ),
.I5(\Data_Bin_o[0]_INST_0_i_8_n_0 ),
.O(\Data_Bin_o[0]_INST_0_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'h40))
\Data_Bin_o[0]_INST_0_i_3
(.I0(Data_Dec_i[14]),
.I1(Data_Dec_i[15]),
.I2(Data_Dec_i[17]),
.O(\Data_Bin_o[0]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'h8888088808080808))
\Data_Bin_o[0]_INST_0_i_4
(.I0(Data_Dec_i[23]),
.I1(Data_Dec_i[25]),
.I2(Data_Dec_i[22]),
.I3(Data_Dec_i[20]),
.I4(Data_Dec_i[19]),
.I5(Data_Dec_i[21]),
.O(\Data_Bin_o[0]_INST_0_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT5 #(
.INIT(32'h7FFF7F7F))
\Data_Bin_o[0]_INST_0_i_5
(.I0(Data_Dec_i[13]),
.I1(Data_Dec_i[17]),
.I2(Data_Dec_i[15]),
.I3(Data_Dec_i[11]),
.I4(Data_Dec_i[12]),
.O(\Data_Bin_o[0]_INST_0_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT4 #(
.INIT(16'h4F00))
\Data_Bin_o[0]_INST_0_i_6
(.I0(Data_Dec_i[4]),
.I1(Data_Dec_i[5]),
.I2(Data_Dec_i[6]),
.I3(Data_Dec_i[7]),
.O(\Data_Bin_o[0]_INST_0_i_6_n_0 ));
LUT3 #(
.INIT(8'h4F))
\Data_Bin_o[0]_INST_0_i_7
(.I0(Data_Dec_i[10]),
.I1(Data_Dec_i[11]),
.I2(Data_Dec_i[12]),
.O(\Data_Bin_o[0]_INST_0_i_7_n_0 ));
LUT6 #(
.INIT(64'h0080008080800080))
\Data_Bin_o[0]_INST_0_i_8
(.I0(Data_Dec_i[3]),
.I1(Data_Dec_i[5]),
.I2(Data_Dec_i[7]),
.I3(Data_Dec_i[2]),
.I4(Data_Dec_i[1]),
.I5(Data_Dec_i[0]),
.O(\Data_Bin_o[0]_INST_0_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFF800000000000))
\Data_Bin_o[1]_INST_0
(.I0(\Data_Bin_o[1]_INST_0_i_1_n_0 ),
.I1(Data_Dec_i[20]),
.I2(Data_Dec_i[21]),
.I3(\Data_Bin_o[1]_INST_0_i_2_n_0 ),
.I4(\Data_Bin_o[1]_INST_0_i_3_n_0 ),
.I5(\Data_Bin_o[1]_INST_0_i_4_n_0 ),
.O(Data_Bin_o[1]));
LUT6 #(
.INIT(64'hFFFFFFFFFF40FFFF))
\Data_Bin_o[1]_INST_0_i_1
(.I0(\Data_Bin_o[1]_INST_0_i_5_n_0 ),
.I1(\Data_Bin_o[4]_INST_0_i_4_n_0 ),
.I2(\Data_Bin_o[1]_INST_0_i_6_n_0 ),
.I3(\Data_Bin_o[1]_INST_0_i_7_n_0 ),
.I4(Data_Dec_i[15]),
.I5(\Data_Bin_o[1]_INST_0_i_8_n_0 ),
.O(\Data_Bin_o[1]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT4 #(
.INIT(16'h8FFF))
\Data_Bin_o[1]_INST_0_i_2
(.I0(Data_Dec_i[17]),
.I1(Data_Dec_i[16]),
.I2(Data_Dec_i[19]),
.I3(Data_Dec_i[18]),
.O(\Data_Bin_o[1]_INST_0_i_2_n_0 ));
LUT2 #(
.INIT(4'h7))
\Data_Bin_o[1]_INST_0_i_3
(.I0(Data_Dec_i[22]),
.I1(Data_Dec_i[23]),
.O(\Data_Bin_o[1]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT2 #(
.INIT(4'h8))
\Data_Bin_o[1]_INST_0_i_4
(.I0(Data_Dec_i[24]),
.I1(Data_Dec_i[25]),
.O(\Data_Bin_o[1]_INST_0_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT2 #(
.INIT(4'h7))
\Data_Bin_o[1]_INST_0_i_5
(.I0(Data_Dec_i[13]),
.I1(Data_Dec_i[12]),
.O(\Data_Bin_o[1]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'h7000FFFFFFFFFFFF))
\Data_Bin_o[1]_INST_0_i_6
(.I0(Data_Dec_i[3]),
.I1(Data_Dec_i[2]),
.I2(Data_Dec_i[4]),
.I3(Data_Dec_i[5]),
.I4(Data_Dec_i[7]),
.I5(Data_Dec_i[6]),
.O(\Data_Bin_o[1]_INST_0_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT2 #(
.INIT(4'h7))
\Data_Bin_o[1]_INST_0_i_7
(.I0(Data_Dec_i[19]),
.I1(Data_Dec_i[18]),
.O(\Data_Bin_o[1]_INST_0_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT5 #(
.INIT(32'h0888FFFF))
\Data_Bin_o[1]_INST_0_i_8
(.I0(Data_Dec_i[12]),
.I1(Data_Dec_i[13]),
.I2(Data_Dec_i[10]),
.I3(Data_Dec_i[11]),
.I4(Data_Dec_i[14]),
.O(\Data_Bin_o[1]_INST_0_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFF00F800000000))
\Data_Bin_o[2]_INST_0
(.I0(\Data_Bin_o[2]_INST_0_i_1_n_0 ),
.I1(\Data_Bin_o[2]_INST_0_i_2_n_0 ),
.I2(\Data_Bin_o[3]_INST_0_i_4_n_0 ),
.I3(\Data_Bin_o[3]_INST_0_i_5_n_0 ),
.I4(\Data_Bin_o[4]_INST_0_i_3_n_0 ),
.I5(\Data_Bin_o[3]_INST_0_i_1_n_0 ),
.O(Data_Bin_o[2]));
LUT6 #(
.INIT(64'h5DFFFFFFFFFFFFFF))
\Data_Bin_o[2]_INST_0_i_1
(.I0(Data_Dec_i[5]),
.I1(Data_Dec_i[1]),
.I2(Data_Dec_i[0]),
.I3(Data_Dec_i[4]),
.I4(Data_Dec_i[3]),
.I5(Data_Dec_i[2]),
.O(\Data_Bin_o[2]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT4 #(
.INIT(16'h8000))
\Data_Bin_o[2]_INST_0_i_2
(.I0(Data_Dec_i[7]),
.I1(Data_Dec_i[6]),
.I2(Data_Dec_i[9]),
.I3(Data_Dec_i[8]),
.O(\Data_Bin_o[2]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'h4444444444440040))
\Data_Bin_o[3]_INST_0
(.I0(\Data_Bin_o[4]_INST_0_i_3_n_0 ),
.I1(\Data_Bin_o[3]_INST_0_i_1_n_0 ),
.I2(\Data_Bin_o[3]_INST_0_i_2_n_0 ),
.I3(\Data_Bin_o[3]_INST_0_i_3_n_0 ),
.I4(\Data_Bin_o[3]_INST_0_i_4_n_0 ),
.I5(\Data_Bin_o[3]_INST_0_i_5_n_0 ),
.O(Data_Bin_o[3]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT4 #(
.INIT(16'h8000))
\Data_Bin_o[3]_INST_0_i_1
(.I0(Data_Dec_i[24]),
.I1(Data_Dec_i[25]),
.I2(Data_Dec_i[23]),
.I3(Data_Dec_i[22]),
.O(\Data_Bin_o[3]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'h0080000000000000))
\Data_Bin_o[3]_INST_0_i_2
(.I0(Data_Dec_i[5]),
.I1(Data_Dec_i[7]),
.I2(Data_Dec_i[6]),
.I3(Data_Dec_i[1]),
.I4(Data_Dec_i[9]),
.I5(Data_Dec_i[8]),
.O(\Data_Bin_o[3]_INST_0_i_2_n_0 ));
LUT3 #(
.INIT(8'h7F))
\Data_Bin_o[3]_INST_0_i_3
(.I0(Data_Dec_i[2]),
.I1(Data_Dec_i[3]),
.I2(Data_Dec_i[4]),
.O(\Data_Bin_o[3]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT4 #(
.INIT(16'h7FFF))
\Data_Bin_o[3]_INST_0_i_4
(.I0(Data_Dec_i[12]),
.I1(Data_Dec_i[13]),
.I2(Data_Dec_i[10]),
.I3(Data_Dec_i[11]),
.O(\Data_Bin_o[3]_INST_0_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT4 #(
.INIT(16'h7FFF))
\Data_Bin_o[3]_INST_0_i_5
(.I0(Data_Dec_i[14]),
.I1(Data_Dec_i[16]),
.I2(Data_Dec_i[15]),
.I3(Data_Dec_i[17]),
.O(\Data_Bin_o[3]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000000020000000))
\Data_Bin_o[4]_INST_0
(.I0(\Data_Bin_o[4]_INST_0_i_1_n_0 ),
.I1(\Data_Bin_o[4]_INST_0_i_2_n_0 ),
.I2(Data_Dec_i[24]),
.I3(Data_Dec_i[22]),
.I4(Data_Dec_i[23]),
.I5(\Data_Bin_o[4]_INST_0_i_3_n_0 ),
.O(Data_Bin_o[4]));
LUT6 #(
.INIT(64'h0000000080000000))
\Data_Bin_o[4]_INST_0_i_1
(.I0(Data_Dec_i[11]),
.I1(Data_Dec_i[10]),
.I2(Data_Dec_i[13]),
.I3(Data_Dec_i[12]),
.I4(Data_Dec_i[25]),
.I5(\Data_Bin_o[3]_INST_0_i_5_n_0 ),
.O(\Data_Bin_o[4]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000080000000))
\Data_Bin_o[4]_INST_0_i_2
(.I0(Data_Dec_i[6]),
.I1(Data_Dec_i[1]),
.I2(Data_Dec_i[0]),
.I3(\Data_Bin_o[4]_INST_0_i_4_n_0 ),
.I4(\Data_Bin_o[4]_INST_0_i_5_n_0 ),
.I5(\Data_Bin_o[3]_INST_0_i_3_n_0 ),
.O(\Data_Bin_o[4]_INST_0_i_2_n_0 ));
LUT4 #(
.INIT(16'h7FFF))
\Data_Bin_o[4]_INST_0_i_3
(.I0(Data_Dec_i[21]),
.I1(Data_Dec_i[18]),
.I2(Data_Dec_i[19]),
.I3(Data_Dec_i[20]),
.O(\Data_Bin_o[4]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT2 #(
.INIT(4'h8))
\Data_Bin_o[4]_INST_0_i_4
(.I0(Data_Dec_i[9]),
.I1(Data_Dec_i[8]),
.O(\Data_Bin_o[4]_INST_0_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT2 #(
.INIT(4'h8))
\Data_Bin_o[4]_INST_0_i_5
(.I0(Data_Dec_i[5]),
.I1(Data_Dec_i[7]),
.O(\Data_Bin_o[4]_INST_0_i_5_n_0 ));
endmodule
(* W = "1" *)
module RegisterAdd
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [0:0]D;
output [0:0]Q;
wire [0:0]D;
wire [0:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D),
.Q(Q));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "1" *)
module RegisterAdd__1
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [0:0]D;
output [0:0]Q;
wire [0:0]Q;
wire \Q[0]_i_1_n_0 ;
wire clk;
wire load;
wire rst;
LUT2 #(
.INIT(4'hE))
\Q[0]_i_1
(.I0(load),
.I1(Q),
.O(\Q[0]_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(\Q[0]_i_1_n_0 ),
.Q(Q));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "1" *)
module RegisterAdd__2
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [0:0]D;
output [0:0]Q;
wire [0:0]Q;
wire \Q[0]_i_1_n_0 ;
wire clk;
wire load;
wire rst;
LUT2 #(
.INIT(4'hE))
\Q[0]_i_1
(.I0(load),
.I1(Q),
.O(\Q[0]_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(\Q[0]_i_1_n_0 ),
.Q(Q));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "1" *)
module RegisterAdd__3
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [0:0]D;
output [0:0]Q;
wire [0:0]Q;
wire \Q[0]_i_1_n_0 ;
wire clk;
wire load;
wire rst;
LUT2 #(
.INIT(4'hE))
\Q[0]_i_1
(.I0(load),
.I1(Q),
.O(\Q[0]_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(\Q[0]_i_1_n_0 ),
.Q(Q));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "1" *)
module RegisterAdd__4
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [0:0]D;
output [0:0]Q;
wire [0:0]D;
wire [0:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D),
.Q(Q));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "1" *)
module RegisterAdd__5
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [0:0]D;
output [0:0]Q;
wire [0:0]D;
wire [0:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D),
.Q(Q));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "1" *)
module RegisterAdd__6
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [0:0]D;
output [0:0]Q;
wire [0:0]D;
wire [0:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D),
.Q(Q));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "1" *)
module RegisterAdd__7
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [0:0]D;
output [0:0]Q;
wire [0:0]D;
wire [0:0]Q;
wire \Q[0]_i_1_n_0 ;
wire clk;
wire load;
wire rst;
LUT3 #(
.INIT(8'hB8))
\Q[0]_i_1
(.I0(D),
.I1(load),
.I2(Q),
.O(\Q[0]_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(\Q[0]_i_1_n_0 ),
.Q(Q));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "2" *)
module RegisterAdd__parameterized0
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [1:0]D;
output [1:0]Q;
wire [1:0]D;
wire [1:0]Q;
wire \Q[0]_i_1_n_0 ;
wire \Q[1]_i_1_n_0 ;
wire clk;
wire load;
wire rst;
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hD8))
\Q[0]_i_1
(.I0(load),
.I1(D[0]),
.I2(Q[0]),
.O(\Q[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\Q[1]_i_1
(.I0(D[1]),
.I1(load),
.I2(Q[1]),
.O(\Q[1]_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(\Q[0]_i_1_n_0 ),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(\Q[1]_i_1_n_0 ),
.Q(Q[1]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "32" *)
module RegisterAdd__parameterized1
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [31:0]D;
output [31:0]Q;
wire [31:0]D;
wire [31:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "32" *)
module RegisterAdd__parameterized10
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [31:0]D;
output [31:0]Q;
wire [31:0]D;
wire [31:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "32" *)
module RegisterAdd__parameterized2
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [31:0]D;
output [31:0]Q;
wire [31:0]D;
wire [31:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "31" *)
module RegisterAdd__parameterized3
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [30:0]D;
output [30:0]Q;
wire [30:0]D;
wire [30:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "31" *)
module RegisterAdd__parameterized4
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [30:0]D;
output [30:0]Q;
wire [30:0]D;
wire [30:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "8" *)
module RegisterAdd__parameterized5
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [7:0]D;
output [7:0]Q;
wire [7:0]D;
wire [7:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[7]),
.Q(Q[7]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "26" *)
module RegisterAdd__parameterized6
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [25:0]D;
output [25:0]Q;
wire [25:0]D;
wire [25:0]Q;
wire clk;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "26" *)
module RegisterAdd__parameterized7
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [25:0]D;
output [25:0]Q;
wire [25:0]D;
wire [25:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "26" *)
module RegisterAdd__parameterized8
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [25:0]D;
output [25:0]Q;
wire [25:0]D;
wire [25:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "5" *)
module RegisterAdd__parameterized9
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [4:0]D;
output [4:0]Q;
wire [4:0]D;
wire [4:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[4]),
.Q(Q[4]));
endmodule
(* SWR = "26" *)
module Rotate_Mux_Array
(Data_i,
select_i,
Data_o);
input [25:0]Data_i;
input select_i;
output [25:0]Data_o;
wire [25:0]Data_i;
wire [25:0]Data_o;
wire select_i;
(* W = "1" *)
Multiplexer_AC__parameterized131 \genblk1[0].genblk1_0.rotate_mux
(.D0(Data_i[0]),
.D1(Data_i[25]),
.S(Data_o[0]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized141 \genblk1[10].genblk1_0.rotate_mux
(.D0(Data_i[10]),
.D1(Data_i[15]),
.S(Data_o[10]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized142 \genblk1[11].genblk1_0.rotate_mux
(.D0(Data_i[11]),
.D1(Data_i[14]),
.S(Data_o[11]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized143 \genblk1[12].genblk1_0.rotate_mux
(.D0(Data_i[12]),
.D1(Data_i[13]),
.S(Data_o[12]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized144 \genblk1[13].genblk1_0.rotate_mux
(.D0(Data_i[13]),
.D1(Data_i[12]),
.S(Data_o[13]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized145 \genblk1[14].genblk1_0.rotate_mux
(.D0(Data_i[14]),
.D1(Data_i[11]),
.S(Data_o[14]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized146 \genblk1[15].genblk1_0.rotate_mux
(.D0(Data_i[15]),
.D1(Data_i[10]),
.S(Data_o[15]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized147 \genblk1[16].genblk1_0.rotate_mux
(.D0(Data_i[16]),
.D1(Data_i[9]),
.S(Data_o[16]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized148 \genblk1[17].genblk1_0.rotate_mux
(.D0(Data_i[17]),
.D1(Data_i[8]),
.S(Data_o[17]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized149 \genblk1[18].genblk1_0.rotate_mux
(.D0(Data_i[18]),
.D1(Data_i[7]),
.S(Data_o[18]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized150 \genblk1[19].genblk1_0.rotate_mux
(.D0(Data_i[19]),
.D1(Data_i[6]),
.S(Data_o[19]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized132 \genblk1[1].genblk1_0.rotate_mux
(.D0(Data_i[1]),
.D1(Data_i[24]),
.S(Data_o[1]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized151 \genblk1[20].genblk1_0.rotate_mux
(.D0(Data_i[20]),
.D1(Data_i[5]),
.S(Data_o[20]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized152 \genblk1[21].genblk1_0.rotate_mux
(.D0(Data_i[21]),
.D1(Data_i[4]),
.S(Data_o[21]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized153 \genblk1[22].genblk1_0.rotate_mux
(.D0(Data_i[22]),
.D1(Data_i[3]),
.S(Data_o[22]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized154 \genblk1[23].genblk1_0.rotate_mux
(.D0(Data_i[23]),
.D1(Data_i[2]),
.S(Data_o[23]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized155 \genblk1[24].genblk1_0.rotate_mux
(.D0(Data_i[24]),
.D1(Data_i[1]),
.S(Data_o[24]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized156 \genblk1[25].genblk1_0.rotate_mux
(.D0(Data_i[25]),
.D1(Data_i[0]),
.S(Data_o[25]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized133 \genblk1[2].genblk1_0.rotate_mux
(.D0(Data_i[2]),
.D1(Data_i[23]),
.S(Data_o[2]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized134 \genblk1[3].genblk1_0.rotate_mux
(.D0(Data_i[3]),
.D1(Data_i[22]),
.S(Data_o[3]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized135 \genblk1[4].genblk1_0.rotate_mux
(.D0(Data_i[4]),
.D1(Data_i[21]),
.S(Data_o[4]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized136 \genblk1[5].genblk1_0.rotate_mux
(.D0(Data_i[5]),
.D1(Data_i[20]),
.S(Data_o[5]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized137 \genblk1[6].genblk1_0.rotate_mux
(.D0(Data_i[6]),
.D1(Data_i[19]),
.S(Data_o[6]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized138 \genblk1[7].genblk1_0.rotate_mux
(.D0(Data_i[7]),
.D1(Data_i[18]),
.S(Data_o[7]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized139 \genblk1[8].genblk1_0.rotate_mux
(.D0(Data_i[8]),
.D1(Data_i[17]),
.S(Data_o[8]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized140 \genblk1[9].genblk1_0.rotate_mux
(.D0(Data_i[9]),
.D1(Data_i[16]),
.S(Data_o[9]),
.ctrl(select_i));
endmodule
(* ORIG_REF_NAME = "Rotate_Mux_Array" *) (* SWR = "26" *)
module Rotate_Mux_Array__1
(Data_i,
select_i,
Data_o);
input [25:0]Data_i;
input select_i;
output [25:0]Data_o;
wire [25:0]Data_i;
wire [25:0]Data_o;
wire select_i;
(* W = "1" *)
Multiplexer_AC__parameterized131__1 \genblk1[0].genblk1_0.rotate_mux
(.D0(Data_i[0]),
.D1(Data_i[25]),
.S(Data_o[0]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized141__1 \genblk1[10].genblk1_0.rotate_mux
(.D0(Data_i[10]),
.D1(Data_i[15]),
.S(Data_o[10]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized142__1 \genblk1[11].genblk1_0.rotate_mux
(.D0(Data_i[11]),
.D1(Data_i[14]),
.S(Data_o[11]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized143__1 \genblk1[12].genblk1_0.rotate_mux
(.D0(Data_i[12]),
.D1(Data_i[13]),
.S(Data_o[12]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized144__1 \genblk1[13].genblk1_0.rotate_mux
(.D0(Data_i[13]),
.D1(Data_i[12]),
.S(Data_o[13]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized145__1 \genblk1[14].genblk1_0.rotate_mux
(.D0(Data_i[14]),
.D1(Data_i[11]),
.S(Data_o[14]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized146__1 \genblk1[15].genblk1_0.rotate_mux
(.D0(Data_i[15]),
.D1(Data_i[10]),
.S(Data_o[15]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized147__1 \genblk1[16].genblk1_0.rotate_mux
(.D0(Data_i[16]),
.D1(Data_i[9]),
.S(Data_o[16]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized148__1 \genblk1[17].genblk1_0.rotate_mux
(.D0(Data_i[17]),
.D1(Data_i[8]),
.S(Data_o[17]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized149__1 \genblk1[18].genblk1_0.rotate_mux
(.D0(Data_i[18]),
.D1(Data_i[7]),
.S(Data_o[18]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized150__1 \genblk1[19].genblk1_0.rotate_mux
(.D0(Data_i[19]),
.D1(Data_i[6]),
.S(Data_o[19]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized132__1 \genblk1[1].genblk1_0.rotate_mux
(.D0(Data_i[1]),
.D1(Data_i[24]),
.S(Data_o[1]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized151__1 \genblk1[20].genblk1_0.rotate_mux
(.D0(Data_i[20]),
.D1(Data_i[5]),
.S(Data_o[20]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized152__1 \genblk1[21].genblk1_0.rotate_mux
(.D0(Data_i[21]),
.D1(Data_i[4]),
.S(Data_o[21]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized153__1 \genblk1[22].genblk1_0.rotate_mux
(.D0(Data_i[22]),
.D1(Data_i[3]),
.S(Data_o[22]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized154__1 \genblk1[23].genblk1_0.rotate_mux
(.D0(Data_i[23]),
.D1(Data_i[2]),
.S(Data_o[23]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized155__1 \genblk1[24].genblk1_0.rotate_mux
(.D0(Data_i[24]),
.D1(Data_i[1]),
.S(Data_o[24]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized156__1 \genblk1[25].genblk1_0.rotate_mux
(.D0(Data_i[25]),
.D1(Data_i[0]),
.S(Data_o[25]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized133__1 \genblk1[2].genblk1_0.rotate_mux
(.D0(Data_i[2]),
.D1(Data_i[23]),
.S(Data_o[2]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized134__1 \genblk1[3].genblk1_0.rotate_mux
(.D0(Data_i[3]),
.D1(Data_i[22]),
.S(Data_o[3]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized135__1 \genblk1[4].genblk1_0.rotate_mux
(.D0(Data_i[4]),
.D1(Data_i[21]),
.S(Data_o[4]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized136__1 \genblk1[5].genblk1_0.rotate_mux
(.D0(Data_i[5]),
.D1(Data_i[20]),
.S(Data_o[5]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized137__1 \genblk1[6].genblk1_0.rotate_mux
(.D0(Data_i[6]),
.D1(Data_i[19]),
.S(Data_o[6]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized138__1 \genblk1[7].genblk1_0.rotate_mux
(.D0(Data_i[7]),
.D1(Data_i[18]),
.S(Data_o[7]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized139__1 \genblk1[8].genblk1_0.rotate_mux
(.D0(Data_i[8]),
.D1(Data_i[17]),
.S(Data_o[8]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized140__1 \genblk1[9].genblk1_0.rotate_mux
(.D0(Data_i[9]),
.D1(Data_i[16]),
.S(Data_o[9]),
.ctrl(select_i));
endmodule
module Round_Sgf_Dec
(Data_i,
Round_Type_i,
Sign_Result_i,
Round_Flag_o);
input [1:0]Data_i;
input [1:0]Round_Type_i;
input Sign_Result_i;
output Round_Flag_o;
wire [1:0]Data_i;
wire Round_Flag_o;
wire [1:0]Round_Type_i;
wire Sign_Result_i;
LUT5 #(
.INIT(32'h00E00E00))
Round_Flag_o_INST_0
(.I0(Data_i[1]),
.I1(Data_i[0]),
.I2(Sign_Result_i),
.I3(Round_Type_i[1]),
.I4(Round_Type_i[0]),
.O(Round_Flag_o));
endmodule
(* EW = "8" *) (* SW = "23" *) (* W = "32" *)
module Tenth_Phase
(clk,
rst,
load_i,
sel_a_i,
sel_b_i,
sign_i,
exp_ieee_i,
sgf_ieee_i,
final_result_ieee_o);
input clk;
input rst;
input load_i;
input sel_a_i;
input sel_b_i;
input sign_i;
input [7:0]exp_ieee_i;
input [22:0]sgf_ieee_i;
output [31:0]final_result_ieee_o;
wire [7:0]Exp_S_mux;
wire [22:0]Sgf_S_mux;
wire Sign_S_mux;
wire clk;
wire [7:0]exp_ieee_i;
wire [31:0]final_result_ieee_o;
wire load_i;
wire overunder;
wire rst;
wire sel_a_i;
wire sel_b_i;
wire [22:0]sgf_ieee_i;
wire sign_i;
(* W = "8" *)
Multiplexer_AC Exp_Mux
(.D0(exp_ieee_i),
.D1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S(Exp_S_mux),
.ctrl(overunder));
LUT2 #(
.INIT(4'hE))
Exp_Mux_i_1
(.I0(sel_a_i),
.I1(sel_b_i),
.O(overunder));
(* W = "32" *)
RegisterAdd__parameterized10 Final_Result_IEEE
(.D({Sign_S_mux,Exp_S_mux,Sgf_S_mux}),
.Q(final_result_ieee_o),
.clk(clk),
.load(load_i),
.rst(rst));
(* W = "23" *)
Multiplexer_AC__parameterized160 Sgf_Mux
(.D0(sgf_ieee_i),
.D1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S(Sgf_S_mux),
.ctrl(overunder));
(* W = "1" *)
Mux_3x1__parameterized1 Sign_Mux
(.D0(sign_i),
.D1(1'b0),
.D2(1'b0),
.S(Sign_S_mux),
.ctrl({sel_a_i,sel_b_i}));
endmodule
(* W = "8" *)
module add_sub_carry_out
(op_mode,
Data_A,
Data_B,
Data_S);
input op_mode;
input [7:0]Data_A;
input [7:0]Data_B;
output [8:0]Data_S;
wire [7:0]Data_A;
wire [7:0]Data_B;
wire [8:0]Data_S;
wire \Data_S[0]_INST_0_i_1_n_0 ;
wire \Data_S[0]_INST_0_i_2_n_0 ;
wire \Data_S[0]_INST_0_i_3_n_0 ;
wire \Data_S[0]_INST_0_n_0 ;
wire \Data_S[0]_INST_0_n_1 ;
wire \Data_S[0]_INST_0_n_2 ;
wire \Data_S[0]_INST_0_n_3 ;
wire \Data_S[4]_INST_0_i_1_n_0 ;
wire \Data_S[4]_INST_0_i_2_n_0 ;
wire \Data_S[4]_INST_0_i_3_n_0 ;
wire \Data_S[4]_INST_0_i_4_n_0 ;
wire \Data_S[4]_INST_0_n_0 ;
wire \Data_S[4]_INST_0_n_1 ;
wire \Data_S[4]_INST_0_n_2 ;
wire \Data_S[4]_INST_0_n_3 ;
wire op_mode;
wire [3:0]\NLW_Data_S[8]_INST_0_CO_UNCONNECTED ;
wire [3:1]\NLW_Data_S[8]_INST_0_O_UNCONNECTED ;
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Data_S[0]_INST_0
(.CI(1'b0),
.CO({\Data_S[0]_INST_0_n_0 ,\Data_S[0]_INST_0_n_1 ,\Data_S[0]_INST_0_n_2 ,\Data_S[0]_INST_0_n_3 }),
.CYINIT(Data_A[0]),
.DI({Data_A[3:1],op_mode}),
.O(Data_S[3:0]),
.S({\Data_S[0]_INST_0_i_1_n_0 ,\Data_S[0]_INST_0_i_2_n_0 ,\Data_S[0]_INST_0_i_3_n_0 ,Data_B[0]}));
LUT3 #(
.INIT(8'h96))
\Data_S[0]_INST_0_i_1
(.I0(Data_B[3]),
.I1(op_mode),
.I2(Data_A[3]),
.O(\Data_S[0]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[0]_INST_0_i_2
(.I0(Data_B[2]),
.I1(op_mode),
.I2(Data_A[2]),
.O(\Data_S[0]_INST_0_i_2_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[0]_INST_0_i_3
(.I0(Data_B[1]),
.I1(op_mode),
.I2(Data_A[1]),
.O(\Data_S[0]_INST_0_i_3_n_0 ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Data_S[4]_INST_0
(.CI(\Data_S[0]_INST_0_n_0 ),
.CO({\Data_S[4]_INST_0_n_0 ,\Data_S[4]_INST_0_n_1 ,\Data_S[4]_INST_0_n_2 ,\Data_S[4]_INST_0_n_3 }),
.CYINIT(1'b0),
.DI(Data_A[7:4]),
.O(Data_S[7:4]),
.S({\Data_S[4]_INST_0_i_1_n_0 ,\Data_S[4]_INST_0_i_2_n_0 ,\Data_S[4]_INST_0_i_3_n_0 ,\Data_S[4]_INST_0_i_4_n_0 }));
LUT3 #(
.INIT(8'h96))
\Data_S[4]_INST_0_i_1
(.I0(Data_B[7]),
.I1(op_mode),
.I2(Data_A[7]),
.O(\Data_S[4]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[4]_INST_0_i_2
(.I0(Data_B[6]),
.I1(op_mode),
.I2(Data_A[6]),
.O(\Data_S[4]_INST_0_i_2_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[4]_INST_0_i_3
(.I0(Data_B[5]),
.I1(op_mode),
.I2(Data_A[5]),
.O(\Data_S[4]_INST_0_i_3_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[4]_INST_0_i_4
(.I0(Data_B[4]),
.I1(op_mode),
.I2(Data_A[4]),
.O(\Data_S[4]_INST_0_i_4_n_0 ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Data_S[8]_INST_0
(.CI(\Data_S[4]_INST_0_n_0 ),
.CO(\NLW_Data_S[8]_INST_0_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_Data_S[8]_INST_0_O_UNCONNECTED [3:1],Data_S[8]}),
.S({1'b0,1'b0,1'b0,op_mode}));
endmodule
(* ORIG_REF_NAME = "add_sub_carry_out" *) (* W = "26" *)
module add_sub_carry_out__parameterized0
(op_mode,
Data_A,
Data_B,
Data_S);
input op_mode;
input [25:0]Data_A;
input [25:0]Data_B;
output [26:0]Data_S;
wire [25:0]Data_A;
wire [25:0]Data_B;
wire [26:0]Data_S;
wire \Data_S[0]_INST_0_i_1_n_0 ;
wire \Data_S[0]_INST_0_i_2_n_0 ;
wire \Data_S[0]_INST_0_i_3_n_0 ;
wire \Data_S[0]_INST_0_n_0 ;
wire \Data_S[0]_INST_0_n_1 ;
wire \Data_S[0]_INST_0_n_2 ;
wire \Data_S[0]_INST_0_n_3 ;
wire \Data_S[12]_INST_0_i_1_n_0 ;
wire \Data_S[12]_INST_0_i_2_n_0 ;
wire \Data_S[12]_INST_0_i_3_n_0 ;
wire \Data_S[12]_INST_0_i_4_n_0 ;
wire \Data_S[12]_INST_0_n_0 ;
wire \Data_S[12]_INST_0_n_1 ;
wire \Data_S[12]_INST_0_n_2 ;
wire \Data_S[12]_INST_0_n_3 ;
wire \Data_S[16]_INST_0_i_1_n_0 ;
wire \Data_S[16]_INST_0_i_2_n_0 ;
wire \Data_S[16]_INST_0_i_3_n_0 ;
wire \Data_S[16]_INST_0_i_4_n_0 ;
wire \Data_S[16]_INST_0_n_0 ;
wire \Data_S[16]_INST_0_n_1 ;
wire \Data_S[16]_INST_0_n_2 ;
wire \Data_S[16]_INST_0_n_3 ;
wire \Data_S[20]_INST_0_i_1_n_0 ;
wire \Data_S[20]_INST_0_i_2_n_0 ;
wire \Data_S[20]_INST_0_i_3_n_0 ;
wire \Data_S[20]_INST_0_i_4_n_0 ;
wire \Data_S[20]_INST_0_n_0 ;
wire \Data_S[20]_INST_0_n_1 ;
wire \Data_S[20]_INST_0_n_2 ;
wire \Data_S[20]_INST_0_n_3 ;
wire \Data_S[24]_INST_0_i_2_n_0 ;
wire \Data_S[24]_INST_0_i_3_n_0 ;
wire \Data_S[24]_INST_0_n_2 ;
wire \Data_S[24]_INST_0_n_3 ;
wire \Data_S[4]_INST_0_i_1_n_0 ;
wire \Data_S[4]_INST_0_i_2_n_0 ;
wire \Data_S[4]_INST_0_i_3_n_0 ;
wire \Data_S[4]_INST_0_i_4_n_0 ;
wire \Data_S[4]_INST_0_n_0 ;
wire \Data_S[4]_INST_0_n_1 ;
wire \Data_S[4]_INST_0_n_2 ;
wire \Data_S[4]_INST_0_n_3 ;
wire \Data_S[8]_INST_0_i_1_n_0 ;
wire \Data_S[8]_INST_0_i_2_n_0 ;
wire \Data_S[8]_INST_0_i_3_n_0 ;
wire \Data_S[8]_INST_0_i_4_n_0 ;
wire \Data_S[8]_INST_0_n_0 ;
wire \Data_S[8]_INST_0_n_1 ;
wire \Data_S[8]_INST_0_n_2 ;
wire \Data_S[8]_INST_0_n_3 ;
wire op_mode;
wire [3:2]\NLW_Data_S[24]_INST_0_CO_UNCONNECTED ;
wire [3:3]\NLW_Data_S[24]_INST_0_O_UNCONNECTED ;
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Data_S[0]_INST_0
(.CI(1'b0),
.CO({\Data_S[0]_INST_0_n_0 ,\Data_S[0]_INST_0_n_1 ,\Data_S[0]_INST_0_n_2 ,\Data_S[0]_INST_0_n_3 }),
.CYINIT(Data_A[0]),
.DI({Data_A[3:1],op_mode}),
.O(Data_S[3:0]),
.S({\Data_S[0]_INST_0_i_1_n_0 ,\Data_S[0]_INST_0_i_2_n_0 ,\Data_S[0]_INST_0_i_3_n_0 ,Data_B[0]}));
LUT3 #(
.INIT(8'h96))
\Data_S[0]_INST_0_i_1
(.I0(Data_B[3]),
.I1(op_mode),
.I2(Data_A[3]),
.O(\Data_S[0]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[0]_INST_0_i_2
(.I0(Data_B[2]),
.I1(op_mode),
.I2(Data_A[2]),
.O(\Data_S[0]_INST_0_i_2_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[0]_INST_0_i_3
(.I0(Data_B[1]),
.I1(op_mode),
.I2(Data_A[1]),
.O(\Data_S[0]_INST_0_i_3_n_0 ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Data_S[12]_INST_0
(.CI(\Data_S[8]_INST_0_n_0 ),
.CO({\Data_S[12]_INST_0_n_0 ,\Data_S[12]_INST_0_n_1 ,\Data_S[12]_INST_0_n_2 ,\Data_S[12]_INST_0_n_3 }),
.CYINIT(1'b0),
.DI(Data_A[15:12]),
.O(Data_S[15:12]),
.S({\Data_S[12]_INST_0_i_1_n_0 ,\Data_S[12]_INST_0_i_2_n_0 ,\Data_S[12]_INST_0_i_3_n_0 ,\Data_S[12]_INST_0_i_4_n_0 }));
LUT3 #(
.INIT(8'h96))
\Data_S[12]_INST_0_i_1
(.I0(Data_B[15]),
.I1(op_mode),
.I2(Data_A[15]),
.O(\Data_S[12]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[12]_INST_0_i_2
(.I0(Data_B[14]),
.I1(op_mode),
.I2(Data_A[14]),
.O(\Data_S[12]_INST_0_i_2_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[12]_INST_0_i_3
(.I0(Data_B[13]),
.I1(op_mode),
.I2(Data_A[13]),
.O(\Data_S[12]_INST_0_i_3_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[12]_INST_0_i_4
(.I0(Data_B[12]),
.I1(op_mode),
.I2(Data_A[12]),
.O(\Data_S[12]_INST_0_i_4_n_0 ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Data_S[16]_INST_0
(.CI(\Data_S[12]_INST_0_n_0 ),
.CO({\Data_S[16]_INST_0_n_0 ,\Data_S[16]_INST_0_n_1 ,\Data_S[16]_INST_0_n_2 ,\Data_S[16]_INST_0_n_3 }),
.CYINIT(1'b0),
.DI(Data_A[19:16]),
.O(Data_S[19:16]),
.S({\Data_S[16]_INST_0_i_1_n_0 ,\Data_S[16]_INST_0_i_2_n_0 ,\Data_S[16]_INST_0_i_3_n_0 ,\Data_S[16]_INST_0_i_4_n_0 }));
LUT3 #(
.INIT(8'h96))
\Data_S[16]_INST_0_i_1
(.I0(Data_B[19]),
.I1(op_mode),
.I2(Data_A[19]),
.O(\Data_S[16]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[16]_INST_0_i_2
(.I0(Data_B[18]),
.I1(op_mode),
.I2(Data_A[18]),
.O(\Data_S[16]_INST_0_i_2_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[16]_INST_0_i_3
(.I0(Data_B[17]),
.I1(op_mode),
.I2(Data_A[17]),
.O(\Data_S[16]_INST_0_i_3_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[16]_INST_0_i_4
(.I0(Data_B[16]),
.I1(op_mode),
.I2(Data_A[16]),
.O(\Data_S[16]_INST_0_i_4_n_0 ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Data_S[20]_INST_0
(.CI(\Data_S[16]_INST_0_n_0 ),
.CO({\Data_S[20]_INST_0_n_0 ,\Data_S[20]_INST_0_n_1 ,\Data_S[20]_INST_0_n_2 ,\Data_S[20]_INST_0_n_3 }),
.CYINIT(1'b0),
.DI(Data_A[23:20]),
.O(Data_S[23:20]),
.S({\Data_S[20]_INST_0_i_1_n_0 ,\Data_S[20]_INST_0_i_2_n_0 ,\Data_S[20]_INST_0_i_3_n_0 ,\Data_S[20]_INST_0_i_4_n_0 }));
LUT3 #(
.INIT(8'h96))
\Data_S[20]_INST_0_i_1
(.I0(Data_B[23]),
.I1(op_mode),
.I2(Data_A[23]),
.O(\Data_S[20]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[20]_INST_0_i_2
(.I0(Data_B[22]),
.I1(op_mode),
.I2(Data_A[22]),
.O(\Data_S[20]_INST_0_i_2_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[20]_INST_0_i_3
(.I0(Data_B[21]),
.I1(op_mode),
.I2(Data_A[21]),
.O(\Data_S[20]_INST_0_i_3_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[20]_INST_0_i_4
(.I0(Data_B[20]),
.I1(op_mode),
.I2(Data_A[20]),
.O(\Data_S[20]_INST_0_i_4_n_0 ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Data_S[24]_INST_0
(.CI(\Data_S[20]_INST_0_n_0 ),
.CO({\NLW_Data_S[24]_INST_0_CO_UNCONNECTED [3:2],\Data_S[24]_INST_0_n_2 ,\Data_S[24]_INST_0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,Data_A[25:24]}),
.O({\NLW_Data_S[24]_INST_0_O_UNCONNECTED [3],Data_S[26:24]}),
.S({1'b0,op_mode,\Data_S[24]_INST_0_i_2_n_0 ,\Data_S[24]_INST_0_i_3_n_0 }));
LUT3 #(
.INIT(8'h96))
\Data_S[24]_INST_0_i_2
(.I0(Data_B[25]),
.I1(op_mode),
.I2(Data_A[25]),
.O(\Data_S[24]_INST_0_i_2_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[24]_INST_0_i_3
(.I0(Data_B[24]),
.I1(op_mode),
.I2(Data_A[24]),
.O(\Data_S[24]_INST_0_i_3_n_0 ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Data_S[4]_INST_0
(.CI(\Data_S[0]_INST_0_n_0 ),
.CO({\Data_S[4]_INST_0_n_0 ,\Data_S[4]_INST_0_n_1 ,\Data_S[4]_INST_0_n_2 ,\Data_S[4]_INST_0_n_3 }),
.CYINIT(1'b0),
.DI(Data_A[7:4]),
.O(Data_S[7:4]),
.S({\Data_S[4]_INST_0_i_1_n_0 ,\Data_S[4]_INST_0_i_2_n_0 ,\Data_S[4]_INST_0_i_3_n_0 ,\Data_S[4]_INST_0_i_4_n_0 }));
LUT3 #(
.INIT(8'h96))
\Data_S[4]_INST_0_i_1
(.I0(Data_B[7]),
.I1(op_mode),
.I2(Data_A[7]),
.O(\Data_S[4]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[4]_INST_0_i_2
(.I0(Data_B[6]),
.I1(op_mode),
.I2(Data_A[6]),
.O(\Data_S[4]_INST_0_i_2_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[4]_INST_0_i_3
(.I0(Data_B[5]),
.I1(op_mode),
.I2(Data_A[5]),
.O(\Data_S[4]_INST_0_i_3_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[4]_INST_0_i_4
(.I0(Data_B[4]),
.I1(op_mode),
.I2(Data_A[4]),
.O(\Data_S[4]_INST_0_i_4_n_0 ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Data_S[8]_INST_0
(.CI(\Data_S[4]_INST_0_n_0 ),
.CO({\Data_S[8]_INST_0_n_0 ,\Data_S[8]_INST_0_n_1 ,\Data_S[8]_INST_0_n_2 ,\Data_S[8]_INST_0_n_3 }),
.CYINIT(1'b0),
.DI(Data_A[11:8]),
.O(Data_S[11:8]),
.S({\Data_S[8]_INST_0_i_1_n_0 ,\Data_S[8]_INST_0_i_2_n_0 ,\Data_S[8]_INST_0_i_3_n_0 ,\Data_S[8]_INST_0_i_4_n_0 }));
LUT3 #(
.INIT(8'h96))
\Data_S[8]_INST_0_i_1
(.I0(Data_B[11]),
.I1(op_mode),
.I2(Data_A[11]),
.O(\Data_S[8]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[8]_INST_0_i_2
(.I0(Data_B[10]),
.I1(op_mode),
.I2(Data_A[10]),
.O(\Data_S[8]_INST_0_i_2_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[8]_INST_0_i_3
(.I0(Data_B[9]),
.I1(op_mode),
.I2(Data_A[9]),
.O(\Data_S[8]_INST_0_i_3_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[8]_INST_0_i_4
(.I0(Data_B[8]),
.I1(op_mode),
.I2(Data_A[8]),
.O(\Data_S[8]_INST_0_i_4_n_0 ));
endmodule
module sgn_result
(Add_Subt_i,
sgn_X_i,
sgn_Y_i,
gtXY_i,
eqXY_i,
sgn_result_o);
input Add_Subt_i;
input sgn_X_i;
input sgn_Y_i;
input gtXY_i;
input eqXY_i;
output sgn_result_o;
wire Add_Subt_i;
wire eqXY_i;
wire gtXY_i;
wire sgn_X_i;
wire sgn_Y_i;
wire sgn_result_o;
LUT5 #(
.INIT(32'hFF3C0014))
sgn_result_o_INST_0
(.I0(eqXY_i),
.I1(sgn_Y_i),
.I2(Add_Subt_i),
.I3(gtXY_i),
.I4(sgn_X_i),
.O(sgn_result_o));
endmodule
(* LEVEL = "0" *) (* SWR = "26" *)
module shift_mux_array
(Data_i,
select_i,
bit_shift_i,
Data_o);
input [25:0]Data_i;
input select_i;
input bit_shift_i;
output [25:0]Data_o;
wire [25:0]Data_i;
wire [25:0]Data_o;
wire bit_shift_i;
wire select_i;
(* W = "1" *)
Multiplexer_AC__parameterized1 \genblk1[0].genblk1_0.rotate_mux
(.D0(Data_i[0]),
.D1(Data_i[1]),
.S(Data_o[0]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized11 \genblk1[10].genblk1_0.rotate_mux
(.D0(Data_i[10]),
.D1(Data_i[11]),
.S(Data_o[10]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized12 \genblk1[11].genblk1_0.rotate_mux
(.D0(Data_i[11]),
.D1(Data_i[12]),
.S(Data_o[11]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized13 \genblk1[12].genblk1_0.rotate_mux
(.D0(Data_i[12]),
.D1(Data_i[13]),
.S(Data_o[12]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized14 \genblk1[13].genblk1_0.rotate_mux
(.D0(Data_i[13]),
.D1(Data_i[14]),
.S(Data_o[13]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized15 \genblk1[14].genblk1_0.rotate_mux
(.D0(Data_i[14]),
.D1(Data_i[15]),
.S(Data_o[14]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized16 \genblk1[15].genblk1_0.rotate_mux
(.D0(Data_i[15]),
.D1(Data_i[16]),
.S(Data_o[15]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized17 \genblk1[16].genblk1_0.rotate_mux
(.D0(Data_i[16]),
.D1(Data_i[17]),
.S(Data_o[16]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized18 \genblk1[17].genblk1_0.rotate_mux
(.D0(Data_i[17]),
.D1(Data_i[18]),
.S(Data_o[17]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized19 \genblk1[18].genblk1_0.rotate_mux
(.D0(Data_i[18]),
.D1(Data_i[19]),
.S(Data_o[18]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized20 \genblk1[19].genblk1_0.rotate_mux
(.D0(Data_i[19]),
.D1(Data_i[20]),
.S(Data_o[19]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized2 \genblk1[1].genblk1_0.rotate_mux
(.D0(Data_i[1]),
.D1(Data_i[2]),
.S(Data_o[1]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized21 \genblk1[20].genblk1_0.rotate_mux
(.D0(Data_i[20]),
.D1(Data_i[21]),
.S(Data_o[20]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized22 \genblk1[21].genblk1_0.rotate_mux
(.D0(Data_i[21]),
.D1(Data_i[22]),
.S(Data_o[21]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized23 \genblk1[22].genblk1_0.rotate_mux
(.D0(Data_i[22]),
.D1(Data_i[23]),
.S(Data_o[22]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized24 \genblk1[23].genblk1_0.rotate_mux
(.D0(Data_i[23]),
.D1(Data_i[24]),
.S(Data_o[23]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized25 \genblk1[24].genblk1_0.rotate_mux
(.D0(Data_i[24]),
.D1(Data_i[25]),
.S(Data_o[24]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized26 \genblk1[25].genblk1.rotate_mux
(.D0(Data_i[25]),
.D1(bit_shift_i),
.S(Data_o[25]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized3 \genblk1[2].genblk1_0.rotate_mux
(.D0(Data_i[2]),
.D1(Data_i[3]),
.S(Data_o[2]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized4 \genblk1[3].genblk1_0.rotate_mux
(.D0(Data_i[3]),
.D1(Data_i[4]),
.S(Data_o[3]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized5 \genblk1[4].genblk1_0.rotate_mux
(.D0(Data_i[4]),
.D1(Data_i[5]),
.S(Data_o[4]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized6 \genblk1[5].genblk1_0.rotate_mux
(.D0(Data_i[5]),
.D1(Data_i[6]),
.S(Data_o[5]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized7 \genblk1[6].genblk1_0.rotate_mux
(.D0(Data_i[6]),
.D1(Data_i[7]),
.S(Data_o[6]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized8 \genblk1[7].genblk1_0.rotate_mux
(.D0(Data_i[7]),
.D1(Data_i[8]),
.S(Data_o[7]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized9 \genblk1[8].genblk1_0.rotate_mux
(.D0(Data_i[8]),
.D1(Data_i[9]),
.S(Data_o[8]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized10 \genblk1[9].genblk1_0.rotate_mux
(.D0(Data_i[9]),
.D1(Data_i[10]),
.S(Data_o[9]),
.ctrl(select_i));
endmodule
(* LEVEL = "1" *) (* ORIG_REF_NAME = "shift_mux_array" *) (* SWR = "26" *)
module shift_mux_array__parameterized0
(Data_i,
select_i,
bit_shift_i,
Data_o);
input [25:0]Data_i;
input select_i;
input bit_shift_i;
output [25:0]Data_o;
wire [25:0]Data_i;
wire [25:0]Data_o;
wire bit_shift_i;
wire select_i;
(* W = "1" *)
Multiplexer_AC__parameterized27 \genblk1[0].genblk1_0.rotate_mux
(.D0(Data_i[0]),
.D1(Data_i[2]),
.S(Data_o[0]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized37 \genblk1[10].genblk1_0.rotate_mux
(.D0(Data_i[10]),
.D1(Data_i[12]),
.S(Data_o[10]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized38 \genblk1[11].genblk1_0.rotate_mux
(.D0(Data_i[11]),
.D1(Data_i[13]),
.S(Data_o[11]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized39 \genblk1[12].genblk1_0.rotate_mux
(.D0(Data_i[12]),
.D1(Data_i[14]),
.S(Data_o[12]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized40 \genblk1[13].genblk1_0.rotate_mux
(.D0(Data_i[13]),
.D1(Data_i[15]),
.S(Data_o[13]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized41 \genblk1[14].genblk1_0.rotate_mux
(.D0(Data_i[14]),
.D1(Data_i[16]),
.S(Data_o[14]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized42 \genblk1[15].genblk1_0.rotate_mux
(.D0(Data_i[15]),
.D1(Data_i[17]),
.S(Data_o[15]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized43 \genblk1[16].genblk1_0.rotate_mux
(.D0(Data_i[16]),
.D1(Data_i[18]),
.S(Data_o[16]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized44 \genblk1[17].genblk1_0.rotate_mux
(.D0(Data_i[17]),
.D1(Data_i[19]),
.S(Data_o[17]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized45 \genblk1[18].genblk1_0.rotate_mux
(.D0(Data_i[18]),
.D1(Data_i[20]),
.S(Data_o[18]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized46 \genblk1[19].genblk1_0.rotate_mux
(.D0(Data_i[19]),
.D1(Data_i[21]),
.S(Data_o[19]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized28 \genblk1[1].genblk1_0.rotate_mux
(.D0(Data_i[1]),
.D1(Data_i[3]),
.S(Data_o[1]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized47 \genblk1[20].genblk1_0.rotate_mux
(.D0(Data_i[20]),
.D1(Data_i[22]),
.S(Data_o[20]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized48 \genblk1[21].genblk1_0.rotate_mux
(.D0(Data_i[21]),
.D1(Data_i[23]),
.S(Data_o[21]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized49 \genblk1[22].genblk1_0.rotate_mux
(.D0(Data_i[22]),
.D1(Data_i[24]),
.S(Data_o[22]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized50 \genblk1[23].genblk1_0.rotate_mux
(.D0(Data_i[23]),
.D1(Data_i[25]),
.S(Data_o[23]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized51 \genblk1[24].genblk1.rotate_mux
(.D0(Data_i[24]),
.D1(bit_shift_i),
.S(Data_o[24]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized52 \genblk1[25].genblk1.rotate_mux
(.D0(Data_i[25]),
.D1(bit_shift_i),
.S(Data_o[25]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized29 \genblk1[2].genblk1_0.rotate_mux
(.D0(Data_i[2]),
.D1(Data_i[4]),
.S(Data_o[2]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized30 \genblk1[3].genblk1_0.rotate_mux
(.D0(Data_i[3]),
.D1(Data_i[5]),
.S(Data_o[3]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized31 \genblk1[4].genblk1_0.rotate_mux
(.D0(Data_i[4]),
.D1(Data_i[6]),
.S(Data_o[4]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized32 \genblk1[5].genblk1_0.rotate_mux
(.D0(Data_i[5]),
.D1(Data_i[7]),
.S(Data_o[5]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized33 \genblk1[6].genblk1_0.rotate_mux
(.D0(Data_i[6]),
.D1(Data_i[8]),
.S(Data_o[6]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized34 \genblk1[7].genblk1_0.rotate_mux
(.D0(Data_i[7]),
.D1(Data_i[9]),
.S(Data_o[7]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized35 \genblk1[8].genblk1_0.rotate_mux
(.D0(Data_i[8]),
.D1(Data_i[10]),
.S(Data_o[8]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized36 \genblk1[9].genblk1_0.rotate_mux
(.D0(Data_i[9]),
.D1(Data_i[11]),
.S(Data_o[9]),
.ctrl(select_i));
endmodule
(* LEVEL = "2" *) (* ORIG_REF_NAME = "shift_mux_array" *) (* SWR = "26" *)
module shift_mux_array__parameterized1
(Data_i,
select_i,
bit_shift_i,
Data_o);
input [25:0]Data_i;
input select_i;
input bit_shift_i;
output [25:0]Data_o;
wire [25:0]Data_i;
wire [25:0]Data_o;
wire bit_shift_i;
wire select_i;
(* W = "1" *)
Multiplexer_AC__parameterized53 \genblk1[0].genblk1_0.rotate_mux
(.D0(Data_i[0]),
.D1(Data_i[4]),
.S(Data_o[0]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized63 \genblk1[10].genblk1_0.rotate_mux
(.D0(Data_i[10]),
.D1(Data_i[14]),
.S(Data_o[10]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized64 \genblk1[11].genblk1_0.rotate_mux
(.D0(Data_i[11]),
.D1(Data_i[15]),
.S(Data_o[11]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized65 \genblk1[12].genblk1_0.rotate_mux
(.D0(Data_i[12]),
.D1(Data_i[16]),
.S(Data_o[12]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized66 \genblk1[13].genblk1_0.rotate_mux
(.D0(Data_i[13]),
.D1(Data_i[17]),
.S(Data_o[13]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized67 \genblk1[14].genblk1_0.rotate_mux
(.D0(Data_i[14]),
.D1(Data_i[18]),
.S(Data_o[14]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized68 \genblk1[15].genblk1_0.rotate_mux
(.D0(Data_i[15]),
.D1(Data_i[19]),
.S(Data_o[15]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized69 \genblk1[16].genblk1_0.rotate_mux
(.D0(Data_i[16]),
.D1(Data_i[20]),
.S(Data_o[16]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized70 \genblk1[17].genblk1_0.rotate_mux
(.D0(Data_i[17]),
.D1(Data_i[21]),
.S(Data_o[17]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized71 \genblk1[18].genblk1_0.rotate_mux
(.D0(Data_i[18]),
.D1(Data_i[22]),
.S(Data_o[18]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized72 \genblk1[19].genblk1_0.rotate_mux
(.D0(Data_i[19]),
.D1(Data_i[23]),
.S(Data_o[19]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized54 \genblk1[1].genblk1_0.rotate_mux
(.D0(Data_i[1]),
.D1(Data_i[5]),
.S(Data_o[1]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized73 \genblk1[20].genblk1_0.rotate_mux
(.D0(Data_i[20]),
.D1(Data_i[24]),
.S(Data_o[20]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized74 \genblk1[21].genblk1_0.rotate_mux
(.D0(Data_i[21]),
.D1(Data_i[25]),
.S(Data_o[21]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized75 \genblk1[22].genblk1.rotate_mux
(.D0(Data_i[22]),
.D1(bit_shift_i),
.S(Data_o[22]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized76 \genblk1[23].genblk1.rotate_mux
(.D0(Data_i[23]),
.D1(bit_shift_i),
.S(Data_o[23]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized77 \genblk1[24].genblk1.rotate_mux
(.D0(Data_i[24]),
.D1(bit_shift_i),
.S(Data_o[24]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized78 \genblk1[25].genblk1.rotate_mux
(.D0(Data_i[25]),
.D1(bit_shift_i),
.S(Data_o[25]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized55 \genblk1[2].genblk1_0.rotate_mux
(.D0(Data_i[2]),
.D1(Data_i[6]),
.S(Data_o[2]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized56 \genblk1[3].genblk1_0.rotate_mux
(.D0(Data_i[3]),
.D1(Data_i[7]),
.S(Data_o[3]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized57 \genblk1[4].genblk1_0.rotate_mux
(.D0(Data_i[4]),
.D1(Data_i[8]),
.S(Data_o[4]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized58 \genblk1[5].genblk1_0.rotate_mux
(.D0(Data_i[5]),
.D1(Data_i[9]),
.S(Data_o[5]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized59 \genblk1[6].genblk1_0.rotate_mux
(.D0(Data_i[6]),
.D1(Data_i[10]),
.S(Data_o[6]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized60 \genblk1[7].genblk1_0.rotate_mux
(.D0(Data_i[7]),
.D1(Data_i[11]),
.S(Data_o[7]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized61 \genblk1[8].genblk1_0.rotate_mux
(.D0(Data_i[8]),
.D1(Data_i[12]),
.S(Data_o[8]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized62 \genblk1[9].genblk1_0.rotate_mux
(.D0(Data_i[9]),
.D1(Data_i[13]),
.S(Data_o[9]),
.ctrl(select_i));
endmodule
(* LEVEL = "3" *) (* ORIG_REF_NAME = "shift_mux_array" *) (* SWR = "26" *)
module shift_mux_array__parameterized2
(Data_i,
select_i,
bit_shift_i,
Data_o);
input [25:0]Data_i;
input select_i;
input bit_shift_i;
output [25:0]Data_o;
wire [25:0]Data_i;
wire [25:0]Data_o;
wire bit_shift_i;
wire select_i;
(* W = "1" *)
Multiplexer_AC__parameterized79 \genblk1[0].genblk1_0.rotate_mux
(.D0(Data_i[0]),
.D1(Data_i[8]),
.S(Data_o[0]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized89 \genblk1[10].genblk1_0.rotate_mux
(.D0(Data_i[10]),
.D1(Data_i[18]),
.S(Data_o[10]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized90 \genblk1[11].genblk1_0.rotate_mux
(.D0(Data_i[11]),
.D1(Data_i[19]),
.S(Data_o[11]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized91 \genblk1[12].genblk1_0.rotate_mux
(.D0(Data_i[12]),
.D1(Data_i[20]),
.S(Data_o[12]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized92 \genblk1[13].genblk1_0.rotate_mux
(.D0(Data_i[13]),
.D1(Data_i[21]),
.S(Data_o[13]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized93 \genblk1[14].genblk1_0.rotate_mux
(.D0(Data_i[14]),
.D1(Data_i[22]),
.S(Data_o[14]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized94 \genblk1[15].genblk1_0.rotate_mux
(.D0(Data_i[15]),
.D1(Data_i[23]),
.S(Data_o[15]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized95 \genblk1[16].genblk1_0.rotate_mux
(.D0(Data_i[16]),
.D1(Data_i[24]),
.S(Data_o[16]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized96 \genblk1[17].genblk1_0.rotate_mux
(.D0(Data_i[17]),
.D1(Data_i[25]),
.S(Data_o[17]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized97 \genblk1[18].genblk1.rotate_mux
(.D0(Data_i[18]),
.D1(bit_shift_i),
.S(Data_o[18]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized98 \genblk1[19].genblk1.rotate_mux
(.D0(Data_i[19]),
.D1(bit_shift_i),
.S(Data_o[19]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized80 \genblk1[1].genblk1_0.rotate_mux
(.D0(Data_i[1]),
.D1(Data_i[9]),
.S(Data_o[1]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized99 \genblk1[20].genblk1.rotate_mux
(.D0(Data_i[20]),
.D1(bit_shift_i),
.S(Data_o[20]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized100 \genblk1[21].genblk1.rotate_mux
(.D0(Data_i[21]),
.D1(bit_shift_i),
.S(Data_o[21]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized101 \genblk1[22].genblk1.rotate_mux
(.D0(Data_i[22]),
.D1(bit_shift_i),
.S(Data_o[22]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized102 \genblk1[23].genblk1.rotate_mux
(.D0(Data_i[23]),
.D1(bit_shift_i),
.S(Data_o[23]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized103 \genblk1[24].genblk1.rotate_mux
(.D0(Data_i[24]),
.D1(bit_shift_i),
.S(Data_o[24]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized104 \genblk1[25].genblk1.rotate_mux
(.D0(Data_i[25]),
.D1(bit_shift_i),
.S(Data_o[25]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized81 \genblk1[2].genblk1_0.rotate_mux
(.D0(Data_i[2]),
.D1(Data_i[10]),
.S(Data_o[2]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized82 \genblk1[3].genblk1_0.rotate_mux
(.D0(Data_i[3]),
.D1(Data_i[11]),
.S(Data_o[3]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized83 \genblk1[4].genblk1_0.rotate_mux
(.D0(Data_i[4]),
.D1(Data_i[12]),
.S(Data_o[4]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized84 \genblk1[5].genblk1_0.rotate_mux
(.D0(Data_i[5]),
.D1(Data_i[13]),
.S(Data_o[5]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized85 \genblk1[6].genblk1_0.rotate_mux
(.D0(Data_i[6]),
.D1(Data_i[14]),
.S(Data_o[6]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized86 \genblk1[7].genblk1_0.rotate_mux
(.D0(Data_i[7]),
.D1(Data_i[15]),
.S(Data_o[7]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized87 \genblk1[8].genblk1_0.rotate_mux
(.D0(Data_i[8]),
.D1(Data_i[16]),
.S(Data_o[8]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized88 \genblk1[9].genblk1_0.rotate_mux
(.D0(Data_i[9]),
.D1(Data_i[17]),
.S(Data_o[9]),
.ctrl(select_i));
endmodule
(* LEVEL = "4" *) (* ORIG_REF_NAME = "shift_mux_array" *) (* SWR = "26" *)
module shift_mux_array__parameterized3
(Data_i,
select_i,
bit_shift_i,
Data_o);
input [25:0]Data_i;
input select_i;
input bit_shift_i;
output [25:0]Data_o;
wire [25:0]Data_i;
wire [25:0]Data_o;
wire bit_shift_i;
wire select_i;
(* W = "1" *)
Multiplexer_AC__parameterized105 \genblk1[0].genblk1_0.rotate_mux
(.D0(Data_i[0]),
.D1(Data_i[16]),
.S(Data_o[0]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized115 \genblk1[10].genblk1.rotate_mux
(.D0(Data_i[10]),
.D1(bit_shift_i),
.S(Data_o[10]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized116 \genblk1[11].genblk1.rotate_mux
(.D0(Data_i[11]),
.D1(bit_shift_i),
.S(Data_o[11]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized117 \genblk1[12].genblk1.rotate_mux
(.D0(Data_i[12]),
.D1(bit_shift_i),
.S(Data_o[12]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized118 \genblk1[13].genblk1.rotate_mux
(.D0(Data_i[13]),
.D1(bit_shift_i),
.S(Data_o[13]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized119 \genblk1[14].genblk1.rotate_mux
(.D0(Data_i[14]),
.D1(bit_shift_i),
.S(Data_o[14]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized120 \genblk1[15].genblk1.rotate_mux
(.D0(Data_i[15]),
.D1(bit_shift_i),
.S(Data_o[15]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized121 \genblk1[16].genblk1.rotate_mux
(.D0(Data_i[16]),
.D1(bit_shift_i),
.S(Data_o[16]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized122 \genblk1[17].genblk1.rotate_mux
(.D0(Data_i[17]),
.D1(bit_shift_i),
.S(Data_o[17]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized123 \genblk1[18].genblk1.rotate_mux
(.D0(Data_i[18]),
.D1(bit_shift_i),
.S(Data_o[18]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized124 \genblk1[19].genblk1.rotate_mux
(.D0(Data_i[19]),
.D1(bit_shift_i),
.S(Data_o[19]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized106 \genblk1[1].genblk1_0.rotate_mux
(.D0(Data_i[1]),
.D1(Data_i[17]),
.S(Data_o[1]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized125 \genblk1[20].genblk1.rotate_mux
(.D0(Data_i[20]),
.D1(bit_shift_i),
.S(Data_o[20]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized126 \genblk1[21].genblk1.rotate_mux
(.D0(Data_i[21]),
.D1(bit_shift_i),
.S(Data_o[21]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized127 \genblk1[22].genblk1.rotate_mux
(.D0(Data_i[22]),
.D1(bit_shift_i),
.S(Data_o[22]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized128 \genblk1[23].genblk1.rotate_mux
(.D0(Data_i[23]),
.D1(bit_shift_i),
.S(Data_o[23]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized129 \genblk1[24].genblk1.rotate_mux
(.D0(Data_i[24]),
.D1(bit_shift_i),
.S(Data_o[24]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized130 \genblk1[25].genblk1.rotate_mux
(.D0(Data_i[25]),
.D1(bit_shift_i),
.S(Data_o[25]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized107 \genblk1[2].genblk1_0.rotate_mux
(.D0(Data_i[2]),
.D1(Data_i[18]),
.S(Data_o[2]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized108 \genblk1[3].genblk1_0.rotate_mux
(.D0(Data_i[3]),
.D1(Data_i[19]),
.S(Data_o[3]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized109 \genblk1[4].genblk1_0.rotate_mux
(.D0(Data_i[4]),
.D1(Data_i[20]),
.S(Data_o[4]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized110 \genblk1[5].genblk1_0.rotate_mux
(.D0(Data_i[5]),
.D1(Data_i[21]),
.S(Data_o[5]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized111 \genblk1[6].genblk1_0.rotate_mux
(.D0(Data_i[6]),
.D1(Data_i[22]),
.S(Data_o[6]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized112 \genblk1[7].genblk1_0.rotate_mux
(.D0(Data_i[7]),
.D1(Data_i[23]),
.S(Data_o[7]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized113 \genblk1[8].genblk1_0.rotate_mux
(.D0(Data_i[8]),
.D1(Data_i[24]),
.S(Data_o[8]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized114 \genblk1[9].genblk1_0.rotate_mux
(.D0(Data_i[9]),
.D1(Data_i[25]),
.S(Data_o[9]),
.ctrl(select_i));
endmodule
(* W = "32" *)
module xor_tri
(A_i,
B_i,
C_i,
Z_o);
input A_i;
input B_i;
input C_i;
output Z_o;
wire A_i;
wire B_i;
wire C_i;
wire Z_o;
LUT3 #(
.INIT(8'h96))
Z_o_INST_0
(.I0(A_i),
.I1(B_i),
.I2(C_i),
.O(Z_o));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 256 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : Complex Multiplier by 0.7071
// FUNCTION: Constant multiplier
// FILES: MPU707.v
// PROPERTIES: 1) Is based on shifts right and add
// 2) for short input bit width 0.7071 is approximated as 10110101 then rounding is not used
// 3) for long input bit width 0.7071 is approximated as 10110101000000101
// 4) hardware is 4 or 5 adders
// 5) MPYJ switches multiply by j
// 6) A complex data is multiplied for 2 cycles
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`include "FFT256_CONFIG.inc"
module MPUC707 ( CLK,EI ,ED, MPYJ,DR,DI ,DOR ,DOI );
`FFT256paramnb
input CLK ;
wire CLK ;
input EI ; //slowdown
wire EI ;
input ED; //data strobe
input MPYJ ; //the result is multiplied by -j
wire MPYJ ;
input [nb-1:0] DR ;
wire signed [nb-1:0] DR ;
input [nb-1:0] DI ;
wire signed [nb-1:0] DI ;
output [nb-1:0] DOR ;
reg [nb-1:0] DOR ;
output [nb-1:0] DOI ;
reg [nb-1:0] DOI ;
reg signed [nb+1 :0] dx5;
reg signed [nb : 0] dt;
reg signed [nb-1 : 0] dii;
wire signed [nb+2 : 0] dx5p;
wire signed [nb+3 : 0] dot;
reg edd,edd2, edd3; //delayed data enable impulse
reg mpyjd,mpyjd2,mpyjd3;
reg [nb-1:0] doo ;
reg [nb-1:0] droo ;
always @(posedge CLK)
begin
if (EI) begin
edd<=ED;
edd2<=edd;
edd3<=edd2;
mpyjd<=MPYJ;
mpyjd2<=mpyjd;
mpyjd3<=mpyjd2;
if (ED) begin
dx5<=DR+(DR <<2); //multiply by 5
dt<=DR;
dii<=DI;
end
else begin
dx5<=dii+(dii <<2); //multiply by 5
dt<=dii;
end
doo<=(dot >>>4) ;
droo<=doo;
if (edd3)
if (mpyjd3) begin
DOR<=doo;
DOI<= - droo; end
else begin
DOR<=droo;
DOI<= doo; end
end
end
assign dx5p=(dx5<<1)+(dx5>>>2); // multiply by 101101
`ifdef FFT256bitwidth_coef_high
assign dot= dx5p+(dt>>>4)+(dx5>>>13); // multiply by 10110101000000101
`else
assign dot= dx5p+(dt>>>4) ; // multiply by 10110101
`endif
endmodule
|
//
// busctrl.v -- bus controller
//
module busctrl(cpu_en, cpu_wr, cpu_size, cpu_addr,
cpu_data_out, cpu_data_in, cpu_wt,
ram_en, ram_wr, ram_size, ram_addr,
ram_data_in, ram_data_out, ram_wt,
rom_en, rom_wr, rom_size, rom_addr,
rom_data_out, rom_wt,
tmr0_en, tmr0_wr, tmr0_addr,
tmr0_data_in, tmr0_data_out, tmr0_wt,
tmr1_en, tmr1_wr, tmr1_addr,
tmr1_data_in, tmr1_data_out, tmr1_wt,
dsp_en, dsp_wr, dsp_addr,
dsp_data_in, dsp_data_out, dsp_wt,
kbd_en, kbd_wr, kbd_addr,
kbd_data_in, kbd_data_out, kbd_wt,
ser0_en, ser0_wr, ser0_addr,
ser0_data_in, ser0_data_out, ser0_wt,
ser1_en, ser1_wr, ser1_addr,
ser1_data_in, ser1_data_out, ser1_wt,
dsk_en, dsk_wr, dsk_addr,
dsk_data_in, dsk_data_out, dsk_wt);
// cpu
input cpu_en;
input cpu_wr;
input [1:0] cpu_size;
input [31:0] cpu_addr;
input [31:0] cpu_data_out;
output [31:0] cpu_data_in;
output cpu_wt;
// ram
output ram_en;
output ram_wr;
output [1:0] ram_size;
output [24:0] ram_addr;
output [31:0] ram_data_in;
input [31:0] ram_data_out;
input ram_wt;
// rom
output rom_en;
output rom_wr;
output [1:0] rom_size;
output [20:0] rom_addr;
input [31:0] rom_data_out;
input rom_wt;
// tmr0
output tmr0_en;
output tmr0_wr;
output [3:2] tmr0_addr;
output [31:0] tmr0_data_in;
input [31:0] tmr0_data_out;
input tmr0_wt;
// tmr1
output tmr1_en;
output tmr1_wr;
output [3:2] tmr1_addr;
output [31:0] tmr1_data_in;
input [31:0] tmr1_data_out;
input tmr1_wt;
// dsp
output dsp_en;
output dsp_wr;
output [13:2] dsp_addr;
output [15:0] dsp_data_in;
input [15:0] dsp_data_out;
input dsp_wt;
// kbd
output kbd_en;
output kbd_wr;
output kbd_addr;
output [7:0] kbd_data_in;
input [7:0] kbd_data_out;
input kbd_wt;
// ser0
output ser0_en;
output ser0_wr;
output [3:2] ser0_addr;
output [7:0] ser0_data_in;
input [7:0] ser0_data_out;
input ser0_wt;
// ser1
output ser1_en;
output ser1_wr;
output [3:2] ser1_addr;
output [7:0] ser1_data_in;
input [7:0] ser1_data_out;
input ser1_wt;
// dsk
output dsk_en;
output dsk_wr;
output [19:2] dsk_addr;
output [31:0] dsk_data_in;
input [31:0] dsk_data_out;
input dsk_wt;
wire i_o_en;
//
// address decoder
//
// RAM: architectural limit = 512 MB
// board limit = 32 MB
assign ram_en =
(cpu_en == 1 && cpu_addr[31:29] == 3'b000
&& cpu_addr[28:25] == 4'b0000) ? 1 : 0;
// ROM: architectural limit = 256 MB
// board limit = 2 MB
assign rom_en =
(cpu_en == 1 && cpu_addr[31:28] == 4'b0010
&& cpu_addr[27:21] == 7'b0000000) ? 1 : 0;
// I/O: architectural limit = 256 MB
assign i_o_en =
(cpu_en == 1 && cpu_addr[31:28] == 4'b0011) ? 1 : 0;
assign tmr0_en =
(i_o_en == 1 && cpu_addr[27:20] == 8'h00
&& cpu_addr[19:12] == 8'h00) ? 1 : 0;
assign tmr1_en =
(i_o_en == 1 && cpu_addr[27:20] == 8'h00
&& cpu_addr[19:12] == 8'h01) ? 1 : 0;
assign dsp_en =
(i_o_en == 1 && cpu_addr[27:20] == 8'h01) ? 1 : 0;
assign kbd_en =
(i_o_en == 1 && cpu_addr[27:20] == 8'h02) ? 1 : 0;
assign ser0_en =
(i_o_en == 1 && cpu_addr[27:20] == 8'h03
&& cpu_addr[19:12] == 8'h00) ? 1 : 0;
assign ser1_en =
(i_o_en == 1 && cpu_addr[27:20] == 8'h03
&& cpu_addr[19:12] == 8'h01) ? 1 : 0;
assign dsk_en =
(i_o_en == 1 && cpu_addr[27:20] == 8'h04) ? 1 : 0;
// to cpu
assign cpu_wt =
(ram_en == 1) ? ram_wt :
(rom_en == 1) ? rom_wt :
(tmr0_en == 1) ? tmr0_wt :
(tmr1_en == 1) ? tmr1_wt :
(dsp_en == 1) ? dsp_wt :
(kbd_en == 1) ? kbd_wt :
(ser0_en == 1) ? ser0_wt :
(ser1_en == 1) ? ser1_wt :
(dsk_en == 1) ? dsk_wt :
1;
assign cpu_data_in[31:0] =
(ram_en == 1) ? ram_data_out[31:0] :
(rom_en == 1) ? rom_data_out[31:0] :
(tmr0_en == 1) ? tmr0_data_out[31:0] :
(tmr1_en == 1) ? tmr1_data_out[31:0] :
(dsp_en == 1) ? { 16'h0000, dsp_data_out[15:0] } :
(kbd_en == 1) ? { 24'h000000, kbd_data_out[7:0] } :
(ser0_en == 1) ? { 24'h000000, ser0_data_out[7:0] } :
(ser1_en == 1) ? { 24'h000000, ser1_data_out[7:0] } :
(dsk_en == 1) ? dsk_data_out[31:0] :
32'h00000000;
// to ram
assign ram_wr = cpu_wr;
assign ram_size[1:0] = cpu_size[1:0];
assign ram_addr[24:0] = cpu_addr[24:0];
assign ram_data_in[31:0] = cpu_data_out[31:0];
// to rom
assign rom_wr = cpu_wr;
assign rom_size[1:0] = cpu_size[1:0];
assign rom_addr[20:0] = cpu_addr[20:0];
// to tmr0
assign tmr0_wr = cpu_wr;
assign tmr0_addr[3:2] = cpu_addr[3:2];
assign tmr0_data_in[31:0] = cpu_data_out[31:0];
// to tmr1
assign tmr1_wr = cpu_wr;
assign tmr1_addr[3:2] = cpu_addr[3:2];
assign tmr1_data_in[31:0] = cpu_data_out[31:0];
// to dsp
assign dsp_wr = cpu_wr;
assign dsp_addr[13:2] = cpu_addr[13:2];
assign dsp_data_in[15:0] = cpu_data_out[15:0];
// to kbd
assign kbd_wr = cpu_wr;
assign kbd_addr = cpu_addr[2];
assign kbd_data_in[7:0] = cpu_data_out[7:0];
// to ser0
assign ser0_wr = cpu_wr;
assign ser0_addr[3:2] = cpu_addr[3:2];
assign ser0_data_in[7:0] = cpu_data_out[7:0];
// to ser1
assign ser1_wr = cpu_wr;
assign ser1_addr[3:2] = cpu_addr[3:2];
assign ser1_data_in[7:0] = cpu_data_out[7:0];
// to dsk
assign dsk_wr = cpu_wr;
assign dsk_addr[19:2] = cpu_addr[19:2];
assign dsk_data_in[31:0] = cpu_data_out[31:0];
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2009 - All rights reserved
//
// This File is copyright Silicon Spectrum Corporation and is licensed for
// use by Conexant Systems, Inc., hereafter the "licensee", as defined by the NDA and the
// license agreement.
//
// This code may not be used as a basis for new development without a written
// agreement between Silicon Spectrum and the licensee.
//
// New development includes, but is not limited to new designs based on this
// code, using this code to aid verification or using this code to test code
// developed independently by the licensee.
//
// This copyright notice must be maintained as written, modifying or removing
// this copyright header will be considered a breach of the license agreement.
//
// The licensee may modify the code for the licensed project.
// Silicon Spectrum does not give up the copyright to the original
// file or encumber in any way.
//
// Use of this file is restricted by the license agreement between the
// licensee and Silicon Spectrum, Inc.
//
///////////////////////////////////////////////////////////////////////////////
//
// Title : 2D Cache Control Read
// File : ded_cactrl_rd.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module ded_cactrl_rd
#(parameter BYTES = 4)
(
input de_rstn,
input de_clk,
input mc_read_4,
input ld_rad,
input ld_rad_e,
input mclock,
input mc_popen,
input mc_acken,
input [9:0] din,
input [8:0] srcx,
input [4:0] dsty,
input [6:0] dstx,
input [1:0] stpl_2,
input [1:0] stpl_4,
input [1:0] apat_2,
input [1:0] apat_4,
input ps8_2,
input ps16_2,
input ps32_2,
input [2:0] psize_4,
input lt_actv_4,
input eol_4,
input mc_eop,
input [2:0] ofset,
input [2:0] frst8_4,
input sol_3,
input mem_req, /* mem_req. */
input mem_rd, /* mem_rd. */
input [4:0] xpat_ofs,
input [4:0] ypat_ofs,
input ca_src_2,
input rad_flg_3,
input [2:0] strt_wrd_3,
input [3:0] strt_byt_3,
input [2:0] strt_bit_3,
input [2:0] strt_wrd_4,
input [3:0] strt_byt_4,
input [2:0] strt_bit_4,
output reg rad_flg_2,
output [2:0] strt_wrd_2,
output [3:0] strt_byt_2,
output [2:0] strt_bit_2,
output reg [9:0] rad
);
reg [2:0] strt_wrd;
reg [2:0] strt_wrd_2a;
reg [3:0] strt_byt;
reg [3:0] strt_byt_2a;
reg [2:0] strt_bit;
reg [2:0] strt_bit_2a;
reg [9:0] inc;
reg mc_eopp1;
reg nx_ld_rad_e;
wire ps32_4,ps16_4,ps8_4;
localparam
MINUS2_BYTES = 10'h3C0,
MINUS4_BYTES = 10'h3A0,
ZERO_BYTES = 10'h0,
ONE_BIT = 10'h1,
TWO_BITS = 10'h2,
HALF_BYTE = 10'h4,
ONE_BYTE = 10'h8,
TWO_BYTES = 10'h10,
FOUR_BYTES = 10'h20,
EIGHT_BYTES = 10'h40,
SIXTEEN_BYTES = 10'h80,
TWENTY_BYTES = 10'hA0,
TWENTYFOUR_BYTES = 10'hC0,
THIRTYTWO_BYTES = 10'h100,
SIXTYFOUR_BYTES = 10'h200;
assign {ps32_4,ps16_4,ps8_4} = psize_4;
always @(posedge mclock)
mc_eopp1 <= mc_eop & mc_popen & eol_4;
// calculate the cache read increment.
always @(posedge mclock) begin
if (stpl_4[1]) begin
// Packed Stipple
casex (apat_4)
2'bx1: begin
// 8x8 packed stipple
if (eol_4 && mc_eop && !lt_actv_4) inc <= ONE_BYTE;
else if (ps32_4) inc <= 10'h7 & (ONE_BIT * (BYTES[9:0]/10'h4));
else if (ps16_4) inc <= 10'h7 & (ONE_BIT * (BYTES[9:0]/10'h2));
else inc <= 10'h7 & (ONE_BIT * (BYTES[9:0]));
end
2'b10: begin
// 32x32 packed stipple.
if(eol_4 && mc_eop && !lt_actv_4) inc <= FOUR_BYTES;
else if (ps32_4) inc <= ONE_BIT * (BYTES[9:0]/10'h4);
else if (ps16_4) inc <= ONE_BIT * (BYTES[9:0]/10'h2);
else inc <= ONE_BIT * (BYTES[9:0]);
end
default: begin
if (ps32_4) inc <= ONE_BIT * (BYTES[9:0]/10'h4);
else if (ps16_4) inc <= ONE_BIT * (BYTES[9:0]/10'h2);
else inc <= ONE_BIT * (BYTES[9:0]);
end
endcase
end
// 32x32 Full Color.
else if (apat_4[1] && eol_4 && mc_eop) inc <= THIRTYTWO_BYTES;
//////////////////////////////////
// 8x8 Full Color.
`ifdef BYTE16
else if (apat_4[0] && eol_4 && mc_eop && ps32_4) inc <= SIXTYFOUR_BYTES;
else if (apat_4[0] && eol_4 && mc_eop) inc <= THIRTYTWO_BYTES;
`endif
`ifdef BYTE8
else if (apat_4[0] && eol_4 && mc_eop && ps32_4) inc <= SIXTYFOUR_BYTES;
else if (apat_4[0] && eol_4 && mc_eop) inc <= THIRTYTWO_BYTES;
`endif
`ifdef BYTE4
else if (apat_4[0] && eol_4 && mc_eop) inc <= {1'b0, ps32_4, ~rad[7], 1'b0, 1'b1, 5'b0};
`endif
//////////////////////////////////
/* rds_neq_wrs src < dst not_sngl */
`ifdef BYTE16 else if (eol_4 && mc_eop && !frst8_4[2] && frst8_4[1]) inc <= ZERO_BYTES; `endif
`ifdef BYTE8 else if (eol_4 && mc_eop && !frst8_4[2] && frst8_4[1]) inc <= MINUS2_BYTES; `endif
`ifdef BYTE4 else if (eol_4 && mc_eop && !frst8_4[2] && frst8_4[1]) inc <= MINUS4_BYTES; `endif
/* rds_neq_wrs src > dst */
`ifdef BYTE16 else if(eol_4 && mc_eop && !frst8_4[2] && !frst8_4[1]) inc <= THIRTYTWO_BYTES; `endif
`ifdef BYTE8 else if(eol_4 && mc_eop && !frst8_4[2] && !frst8_4[1]) inc <= TWENTYFOUR_BYTES; `endif
`ifdef BYTE4 else if(eol_4 && mc_eop && !frst8_4[2] && !frst8_4[1]) inc <= TWENTY_BYTES; `endif
//
else inc <= ONE_BYTE * BYTES[9:0];
end
always @(posedge de_clk or negedge de_rstn) begin
if (!de_rstn) rad_flg_2 <= 1'b0;
else if (mem_req & ~mem_rd) rad_flg_2 <= 1'b0;
else if (ld_rad | ld_rad_e) rad_flg_2 <= 1'b1;
end
/* pattern offset control. */
wire [4:0] new_dstx;
wire [4:0] xofs;
wire [4:0] yofs;
assign new_dstx = (ps32_2) ? {dstx[6:4],2'b0} :
(ps16_2) ? {dstx[5:4],3'b0} : {dstx[4],4'b0};
assign yofs = dsty[4:0];
assign xofs = new_dstx;
wire [6:0] srcx_us = (ps32_2) ? srcx[8:2] :
(ps16_2) ? srcx[7:1] : srcx[6:0];
/* register for cache unload pointer. */
/* loaded by the drawing engine state machines. */
always @* begin
// packed modes.
if (stpl_2[1]) begin
casex (apat_2)
2'b00: strt_wrd=din[9:7]; /* linear or wxfer */
2'b1x: strt_wrd=yofs[4:2]; /* 32x32 */
2'b01: strt_wrd=srcx_us[6:4] & {3{ca_src_2}}; /* 8x8 */
endcase // casex(apat_2)
end else if (apat_2[1]) begin
// planar or full color patterns.
casex ({ps8_2, ps16_2}) // synopsys parallel_case
2'b10: strt_wrd = {2'b00,dstx[4]};
2'b01: strt_wrd = {1'b0,dstx[5:4]};
default: strt_wrd = dstx[6:4];
endcase // casex({ps8_2, ps16_2})
end else begin
// all other modes.
if(|ca_src_2)strt_wrd=srcx_us[6:4];
else if(!din[4] && !stpl_2[1] && (~|apat_2))strt_wrd=3'b000;
else if(din[4] && !stpl_2[1] && (~|apat_2))strt_wrd=3'b111;
else if(!stpl_2[1] && !stpl_2[0] && apat_2[0] && ps32_2)strt_wrd={2'b00,dstx[4]};
else strt_wrd=3'b000;
end
end
always @* begin
// packed modes.
if(stpl_2[1] && apat_2[0])strt_byt={(srcx[5] & ps32_2) |
(srcx[4] & ps16_2) |
(srcx[3] & ps8_2),yofs[2:0]}; /* 8x8 */
else if(stpl_2[1] && apat_2[1]) strt_byt={yofs[1:0],xofs[4:3]}; /* 32x32 */
else if(stpl_2[1]) strt_byt=din[6:3];
// planar or full color patterns.
else if(|apat_2)strt_byt = 4'b0;
// all other modes.
else if(|ca_src_2)strt_byt=srcx_us[3:0];
else strt_byt=din[3:0];
end
always @* begin
if((|stpl_2) && (|apat_2))strt_bit=xofs[2:0];
else strt_bit=din[2:0];
end
always @(posedge de_clk or negedge de_rstn) begin
if (!de_rstn) begin
strt_wrd_2a <= 3'b0;
strt_byt_2a <= 4'b0;
strt_bit_2a <= 3'b0;
end else if (ld_rad) begin
strt_wrd_2a <= strt_wrd;
strt_byt_2a <= strt_byt;
strt_bit_2a <= strt_bit;
end
end
always @(posedge de_clk) nx_ld_rad_e <= ld_rad_e;
assign strt_wrd_2 = (nx_ld_rad_e) ? strt_wrd : strt_wrd_2a;
assign strt_byt_2 = (nx_ld_rad_e) ? strt_byt : strt_byt_2a;
assign strt_bit_2 = (nx_ld_rad_e) ? strt_bit : strt_bit_2a;
// counter for cache unload pointer.
always @(posedge mclock or negedge de_rstn)
begin
if (!de_rstn) rad[9:0] <= 10'h0;
/* LOAD NEW POINTER */
else if(rad_flg_3 & mc_acken & sol_3 & ~mc_read_4)
rad[9:0] <= {strt_wrd_3,strt_byt_3,strt_bit_3};
//////////////////////////////////////////////////////////////////
/* INCREMENT POINTER */
else if(((mc_popen && !eol_4) || (mc_popen && !mc_eop)) || mc_eopp1)
begin
/* 8X8 STIPPLE PACKED AREA PATTERN. */
if(stpl_4[1] && apat_4[0])
begin
if (eol_4 && mc_eopp1) rad[2:0] <= strt_bit_4;
else rad[2:0] <= rad[2:0] + inc[2:0];
rad[5:3] <= rad[5:3] + inc[5:3];
end
/* 32X32 STIPPLE PACKED AREA PATTERN. */
else if(stpl_4[1] && apat_4[1])
begin
rad[9:5] <= rad[9:5] + inc[9:5]; /* word,byte pointer */
if (eol_4 && mc_eopp1) rad[4:0] <= {strt_byt_4[1:0],strt_bit_4};
`ifdef BYTE16 else rad[4:2] <= rad[4:2] + inc[4:2];
`elsif BYTE8 else rad[4:1] <= rad[4:1] + inc[4:1];
`else else rad[4:0] <= rad[4:0] + inc[4:0];
`endif
end
/* STIPPLE WRITE TRANSFER. */
else if(stpl_4[1])
begin
/* stipple packed. */
`ifdef BYTE16 if(!mc_eopp1) rad[9:2] <= rad[9:2] + inc[9:2]; `endif
`ifdef BYTE8 if(!mc_eopp1) rad[9:1] <= rad[9:1] + inc[9:1]; `endif
`ifdef BYTE4 if(!mc_eopp1) rad[9:0] <= rad[9:0] + inc[9:0]; `endif
end
/* 32x32 STIPPLE PLANAR OR FULL COLOR. */
/* word pointer */
else if(apat_4[1])
begin
`ifdef BYTE16
if(eol_4 && ps8_4 && mc_eopp1) rad[9:7] <= {~rad[9],1'b0,strt_wrd_4[0]};
else if (eol_4 && mc_eopp1) rad[9:7] <= strt_wrd_4;
else if (ps8_4) rad[7] <= ~rad[7]; // word pointer
else rad[9:7] <= rad[9:7] + inc[9:7];
rad[6:3] <= rad[6:3] + inc[6:3]; /* word pointer */
`endif
`ifdef BYTE8
if(eol_4 && ps8_4 && mc_eopp1) rad[9:6] <= {~rad[9],1'b0,strt_wrd_4[0], strt_byt_4[3]};
else if (eol_4 && mc_eopp1) rad[9:6] <= {strt_wrd_4, strt_byt_4[3]};
else if (ps8_4) rad[7:3] <= rad[7:3] + inc[7:3]; // Mod 32.
else if (ps16_4) rad[8:3] <= rad[8:3] + inc[8:3]; // Mod 64.
else rad[9:3] <= rad[9:3] + inc[9:3]; // Mod 128.
`endif
`ifdef BYTE4
if(eol_4 && ps8_4 && mc_eopp1) rad[9:5] <= {~rad[9],1'b0,strt_wrd_4[0],strt_byt_4[3:2]};
else if (eol_4 && mc_eopp1) rad[9:5] <= {strt_wrd_4, strt_byt_4[3:2]};
else if (ps8_4) rad[7:5] <= rad[7:5] + inc[7:5];
else rad[9:3] <= rad[9:3] + inc[9:3];
`endif
end
/* 8x8 STIPPLE PLANAR OR FULL COLOR. */
else if(apat_4[0])
begin
`ifdef BYTE16
if (mc_eopp1) rad[9:7] <= {rad[9:8],strt_wrd_4[0]} + inc[9:7];
else if (ps32_4) rad[7:3] <= rad[7:3] + inc[7:3];
else rad[6:3] <= rad[6:3] + inc[6:3];
`endif
`ifdef BYTE8
if (mc_eopp1 & ps32_4) rad[9:3] <= {rad[9:8],strt_wrd[0], strt_byt_4[3:0]} + inc[9:3];
else if (mc_eopp1) rad[9:3] <= {rad[9:7],strt_byt_4[3:0]} + inc[9:3];
else if (ps32_4) rad[7:3] <= rad[7:3] + inc[7:3];
else if (ps16_4) rad[6:3] <= rad[6:3] + inc[6:3];
else rad[5:3] <= rad[5:3] + inc[5:3];
`endif
`ifdef BYTE4
if (mc_eopp1) rad[9:5] <= rad[9:5] + inc[9:5];
else rad[7:3] <= rad[7:3] + inc[7:3];
`endif
end
/* ALL OTHERS. */
else rad[9:5] <= rad[9:5] + inc[9:5]; /* word pointer */
// int_rad[9:0] <= nxt_rad;
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : rank_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level rank machine structural block. This block
// instantiates a configurable number of rank controller blocks.
`timescale 1ps/1ps
module mig_7series_v1_9_rank_mach #
(
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter DRAM_TYPE = "DDR3",
parameter MAINT_PRESCALER_DIV = 40,
parameter nBANK_MACHS = 4,
parameter nCKESR = 4,
parameter nCK_PER_CLK = 2,
parameter CL = 5,
parameter CWL = 5,
parameter DQRD2DQWR_DLY = 2,
parameter nFAW = 30,
parameter nREFRESH_BANK = 8,
parameter nRRD = 4,
parameter nWTR = 4,
parameter PERIODIC_RD_TIMER_DIV = 20,
parameter RANK_BM_BV_WIDTH = 16,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter REFRESH_TIMER_DIV = 39,
parameter ZQ_TIMER_DIV = 640000
)
(/*AUTOARG*/
// Outputs
periodic_rd_rank_r, periodic_rd_r, maint_req_r, inhbt_act_faw_r, inhbt_rd,
inhbt_wr, maint_rank_r, maint_zq_r, maint_sre_r, maint_srx_r, app_sr_active,
app_ref_ack, app_zq_ack, col_rd_wr, maint_ref_zq_wip,
// Inputs
wr_this_rank_r, slot_1_present, slot_0_present, sending_row,
sending_col, rst, rd_this_rank_r, rank_busy_r, periodic_rd_ack_r,
maint_wip_r, insert_maint_r1, init_calib_complete, clk, app_zq_req,
app_sr_req, app_ref_req, app_periodic_rd_req, act_this_rank_r
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input app_periodic_rd_req; // To rank_cntrl0 of rank_cntrl.v
input app_ref_req; // To rank_cntrl0 of rank_cntrl.v
input app_zq_req; // To rank_common0 of rank_common.v
input app_sr_req; // To rank_common0 of rank_common.v
input clk; // To rank_cntrl0 of rank_cntrl.v, ...
input col_rd_wr; // To rank_cntrl0 of rank_cntrl.v, ...
input init_calib_complete; // To rank_cntrl0 of rank_cntrl.v, ...
input insert_maint_r1; // To rank_cntrl0 of rank_cntrl.v, ...
input maint_wip_r; // To rank_common0 of rank_common.v
input periodic_rd_ack_r; // To rank_common0 of rank_common.v
input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r; // To rank_cntrl0 of rank_cntrl.v
input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input rst; // To rank_cntrl0 of rank_cntrl.v, ...
input [nBANK_MACHS-1:0] sending_col; // To rank_cntrl0 of rank_cntrl.v
input [nBANK_MACHS-1:0] sending_row; // To rank_cntrl0 of rank_cntrl.v
input [7:0] slot_0_present; // To rank_common0 of rank_common.v
input [7:0] slot_1_present; // To rank_common0 of rank_common.v
input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output maint_req_r; // From rank_common0 of rank_common.v
output periodic_rd_r; // From rank_common0 of rank_common.v
output [RANK_WIDTH-1:0] periodic_rd_rank_r; // From rank_common0 of rank_common.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire maint_prescaler_tick_r; // From rank_common0 of rank_common.v
wire refresh_tick; // From rank_common0 of rank_common.v
// End of automatics
output [RANKS-1:0] inhbt_act_faw_r;
output [RANKS-1:0] inhbt_rd;
output [RANKS-1:0] inhbt_wr;
output [RANK_WIDTH-1:0] maint_rank_r;
output maint_zq_r;
output maint_sre_r;
output maint_srx_r;
output app_sr_active;
output app_ref_ack;
output app_zq_ack;
output maint_ref_zq_wip;
wire [RANKS-1:0] refresh_request;
wire [RANKS-1:0] periodic_rd_request;
wire [RANKS-1:0] clear_periodic_rd_request;
genvar ID;
generate
for (ID=0; ID<RANKS; ID=ID+1) begin:rank_cntrl
mig_7series_v1_9_rank_cntrl #
(/*AUTOINSTPARAM*/
// Parameters
.BURST_MODE (BURST_MODE),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.CL (CL),
.CWL (CWL),
.DQRD2DQWR_DLY (DQRD2DQWR_DLY),
.nFAW (nFAW),
.nREFRESH_BANK (nREFRESH_BANK),
.nRRD (nRRD),
.nWTR (nWTR),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV))
rank_cntrl0
(.clear_periodic_rd_request (clear_periodic_rd_request[ID]),
.inhbt_act_faw_r (inhbt_act_faw_r[ID]),
.inhbt_rd (inhbt_rd[ID]),
.inhbt_wr (inhbt_wr[ID]),
.periodic_rd_request (periodic_rd_request[ID]),
.refresh_request (refresh_request[ID]),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst),
.col_rd_wr (col_rd_wr),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.app_ref_req (app_ref_req),
.init_calib_complete (init_calib_complete),
.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
.refresh_tick (refresh_tick),
.insert_maint_r1 (insert_maint_r1),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.app_periodic_rd_req (app_periodic_rd_req),
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]));
end
endgenerate
mig_7series_v1_9_rank_common #
(/*AUTOINSTPARAM*/
// Parameters
.DRAM_TYPE (DRAM_TYPE),
.MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV),
.nBANK_MACHS (nBANK_MACHS),
.nCKESR (nCKESR),
.nCK_PER_CLK (nCK_PER_CLK),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV),
.ZQ_TIMER_DIV (ZQ_TIMER_DIV))
rank_common0
(.clear_periodic_rd_request (clear_periodic_rd_request[RANKS-1:0]),
/*AUTOINST*/
// Outputs
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.refresh_tick (refresh_tick),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_req_r (maint_req_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_ref_zq_wip (maint_ref_zq_wip),
.periodic_rd_r (periodic_rd_r),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.init_calib_complete (init_calib_complete),
.app_ref_req (app_ref_req),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.app_zq_ack (app_zq_ack),
.app_sr_req (app_sr_req),
.app_sr_active (app_sr_active),
.insert_maint_r1 (insert_maint_r1),
.refresh_request (refresh_request[RANKS-1:0]),
.maint_wip_r (maint_wip_r),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.periodic_rd_request (periodic_rd_request[RANKS-1:0]),
.periodic_rd_ack_r (periodic_rd_ack_r));
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of aou
//
// Generated
// by: wig
// on: Mon Jun 26 16:38:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../nreset2.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: aou.v,v 1.3 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: aou.v,v $
// Revision 1.3 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of aou
//
// No user `defines in this module
module aou
//
// Generated Module aou_i1
//
(
reset_i_n // Async. Reset (CGU,PAD)
);
// Generated Module Inputs:
input reset_i_n;
// Generated Wires:
wire reset_i_n;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of aou
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7:5.5
// IP Revision: 3
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.4" *)
(* CHECK_LICENSE_TYPE = "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *)
(* CORE_GENERATION_INFO = "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CHECK=0\
,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M_AX\
I_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_HP0=0,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=TRUE,C_FCLK_CLK1_BUF=FALSE,C_FCLK_CLK2_BUF=FALSE,C_FCLK_CLK3_BUF=FALSE,C_PACKAGE_NAME=clg484,C_GP0_EN_MODIFIABLE_TXN=0,C_GP1_EN_MODIFIABLE\
_TXN=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_processing_system7_0_0 (
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
output wire TTC0_WAVE0_OUT;
output wire TTC0_WAVE1_OUT;
output wire TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *)
output wire [1 : 0] USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *)
output wire USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *)
input wire USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *)
output wire M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *)
output wire M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *)
output wire M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *)
output wire M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *)
output wire M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *)
output wire M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *)
output wire [11 : 0] M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *)
output wire [11 : 0] M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *)
output wire [11 : 0] M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *)
output wire [1 : 0] M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *)
output wire [1 : 0] M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *)
output wire [2 : 0] M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *)
output wire [1 : 0] M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *)
output wire [1 : 0] M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *)
output wire [2 : 0] M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *)
output wire [2 : 0] M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *)
output wire [2 : 0] M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *)
output wire [31 : 0] M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *)
output wire [31 : 0] M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *)
output wire [31 : 0] M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *)
output wire [3 : 0] M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *)
output wire [3 : 0] M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *)
output wire [3 : 0] M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *)
output wire [3 : 0] M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *)
output wire [3 : 0] M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *)
output wire [3 : 0] M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
output wire [3 : 0] M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
input wire M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
input wire M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *)
input wire M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *)
input wire M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *)
input wire M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *)
input wire M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *)
input wire M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *)
input wire [11 : 0] M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *)
input wire [11 : 0] M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *)
input wire [1 : 0] M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
input wire [1 : 0] M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
input wire [31 : 0] M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_5_processing_system7 #(
.C_EN_EMIO_PJTAG(0),
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_PIPELINE_WIDTH(8),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(64),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(1),
.C_IRQ_F2P_MODE("DIRECT"),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_TRACE_INTERNAL_WIDTH(2),
.C_USE_AXI_NONSECURE(0),
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_USE_S_AXI_ACP(0),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("TRUE"),
.C_FCLK_CLK1_BUF("FALSE"),
.C_FCLK_CLK2_BUF("FALSE"),
.C_FCLK_CLK3_BUF("FALSE"),
.C_PACKAGE_NAME("clg484"),
.C_GP0_EN_MODIFIABLE_TXN(0),
.C_GP1_EN_MODIFIABLE_TXN(0)
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(),
.ENET0_PTP_DELAY_REQ_TX(),
.ENET0_PTP_PDELAY_REQ_RX(),
.ENET0_PTP_PDELAY_REQ_TX(),
.ENET0_PTP_PDELAY_RESP_RX(),
.ENET0_PTP_PDELAY_RESP_TX(),
.ENET0_PTP_SYNC_FRAME_RX(),
.ENET0_PTP_SYNC_FRAME_TX(),
.ENET0_SOF_RX(),
.ENET0_SOF_TX(),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(64'B0),
.GPIO_O(),
.GPIO_T(),
.I2C0_SDA_I(1'B0),
.I2C0_SDA_O(),
.I2C0_SDA_T(),
.I2C0_SCL_I(1'B0),
.I2C0_SCL_O(),
.I2C0_SCL_T(),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TDI(1'B0),
.PJTAG_TDO(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(1'B0),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B1),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B1),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC0_CLK0_IN(1'B0),
.TTC0_CLK1_IN(1'B0),
.TTC0_CLK2_IN(1'B0),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CLK_OUT(),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB1_PORT_INDCTL(),
.USB1_VBUS_PWRSELECT(),
.USB1_VBUS_PWRFAULT(1'B0),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_RCOUNT(),
.S_AXI_HP0_WCOUNT(),
.S_AXI_HP0_RACOUNT(),
.S_AXI_HP0_WACOUNT(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RDISSUECAP1_EN(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WRISSUECAP1_EN(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_RCOUNT(),
.S_AXI_HP1_WCOUNT(),
.S_AXI_HP1_RACOUNT(),
.S_AXI_HP1_WACOUNT(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(1'B0),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG_0(1'B0),
.FTMT_F2P_TRIGACK_0(),
.FTMT_F2P_TRIG_1(1'B0),
.FTMT_F2P_TRIGACK_1(),
.FTMT_F2P_TRIG_2(1'B0),
.FTMT_F2P_TRIGACK_2(),
.FTMT_F2P_TRIG_3(1'B0),
.FTMT_F2P_TRIGACK_3(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK_0(1'B0),
.FTMT_P2F_TRIG_0(),
.FTMT_P2F_TRIGACK_1(1'B0),
.FTMT_P2F_TRIG_1(),
.FTMT_P2F_TRIGACK_2(1'B0),
.FTMT_P2F_TRIG_2(),
.FTMT_P2F_TRIGACK_3(1'B0),
.FTMT_P2F_TRIG_3(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41A_FUNCTIONAL_V
`define SKY130_FD_SC_LS__O41A_FUNCTIONAL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o41a (
X ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41A_FUNCTIONAL_V |
/******************************************************************************/
/* FPGA Sort on VC707 Ryohei Kobayashi */
/* 2016-08-01 */
/******************************************************************************/
`include "trellis.vh"
`include "riffa.vh"
`include "tlp.vh"
`include "xilinx.vh"
`include "define.vh"
`timescale 1ps / 1ps
module top #(parameter C_NUM_CHNL = 1, // Number of RIFFA Channels
parameter C_NUM_LANES = 8, // Number of PCIe Lanes
/* Settings from Vivado IP Generator */
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 6)
(output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN,
output [3:0] LED,
input PCIE_REFCLK_P,
input PCIE_REFCLK_N,
input PCIE_RESET_N,
// DRAM
input wire CLK_P,
input wire CLK_N,
inout wire [`DDR3_DATA] DDR3DQ,
inout wire [7:0] DDR3DQS_N,
inout wire [7:0] DDR3DQS_P,
output wire [`DDR3_ADDR] DDR3ADDR,
output wire [2:0] DDR3BA,
output wire DDR3RAS_N,
output wire DDR3CAS_N,
output wire DDR3WE_N,
output wire DDR3RESET_N,
output wire [0:0] DDR3CK_P,
output wire [0:0] DDR3CK_N,
output wire [0:0] DDR3CKE,
output wire [0:0] DDR3CS_N,
output wire [7:0] DDR3DM,
output wire [0:0] DDR3ODT);
wire pcie_refclk;
wire pcie_reset_n;
wire user_clk;
wire user_reset;
wire user_lnk_up;
wire user_app_rdy;
wire s_axis_tx_tready;
wire [C_PCI_DATA_WIDTH-1:0] s_axis_tx_tdata;
wire [(C_PCI_DATA_WIDTH/8)-1:0] s_axis_tx_tkeep;
wire s_axis_tx_tlast;
wire s_axis_tx_tvalid;
wire [`SIG_XIL_TX_TUSER_W:0] s_axis_tx_tuser;
wire [C_PCI_DATA_WIDTH-1:0] m_axis_rx_tdata;
wire [(C_PCI_DATA_WIDTH/8)-1:0] m_axis_rx_tkeep;
wire m_axis_rx_tlast;
wire m_axis_rx_tvalid;
wire m_axis_rx_tready;
wire [`SIG_XIL_RX_TUSER_W-1:0] m_axis_rx_tuser;
wire tx_cfg_gnt;
wire rx_np_ok;
wire rx_np_req;
wire cfg_turnoff_ok;
wire cfg_trn_pending;
wire cfg_pm_halt_aspm_l0s;
wire cfg_pm_halt_aspm_l1;
wire cfg_pm_force_state_en;
wire [ 1:0] cfg_pm_force_state;
wire cfg_pm_wake;
wire [63:0] cfg_dsn;
wire [11:0] fc_cpld;
wire [ 7:0] fc_cplh;
wire [11:0] fc_npd;
wire [ 7:0] fc_nph;
wire [11:0] fc_pd;
wire [ 7:0] fc_ph;
wire [ 2:0] fc_sel;
wire [15:0] cfg_status;
wire [15:0] cfg_command;
wire [15:0] cfg_dstatus;
wire [15:0] cfg_dcommand;
wire [15:0] cfg_lstatus;
wire [15:0] cfg_lcommand;
wire [15:0] cfg_dcommand2;
wire [2:0] cfg_pcie_link_state;
wire cfg_pmcsr_pme_en;
wire [1:0] cfg_pmcsr_powerstate;
wire cfg_pmcsr_pme_status;
wire cfg_received_func_lvl_rst;
wire [4:0] cfg_pciecap_interrupt_msgnum;
wire cfg_to_turnoff;
wire [7:0] cfg_bus_number;
wire [4:0] cfg_device_number;
wire [2:0] cfg_function_number;
wire cfg_interrupt;
wire cfg_interrupt_rdy;
wire cfg_interrupt_assert;
wire [7:0] cfg_interrupt_di;
wire [7:0] cfg_interrupt_do;
wire [2:0] cfg_interrupt_mmenable;
wire cfg_interrupt_msien;
wire cfg_interrupt_msixenable;
wire cfg_interrupt_msixfm;
wire cfg_interrupt_stat;
wire rst_out;
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
assign cfg_turnoff_ok = 0;
assign cfg_trn_pending = 0;
assign cfg_pm_halt_aspm_l0s = 0;
assign cfg_pm_halt_aspm_l1 = 0;
assign cfg_pm_force_state_en = 0;
assign cfg_pm_force_state = 0;
assign cfg_dsn = 0;
assign cfg_interrupt_assert = 0;
assign cfg_interrupt_di = 0;
assign cfg_interrupt_stat = 0;
assign cfg_pciecap_interrupt_msgnum = 0;
assign cfg_turnoff_ok = 0;
assign cfg_pm_wake = 0;
IBUF
#()
pci_reset_n_ibuf
(.O(pcie_reset_n),
.I(PCIE_RESET_N));
IBUFDS_GTE2
#()
refclk_ibuf
(.O(pcie_refclk),
.ODIV2(),
.I(PCIE_REFCLK_P),
.CEB(1'b0),
.IB(PCIE_REFCLK_N));
// Core Top Level Wrapper
PCIeGen2x8If128 PCIeGen2x8If128_i
(//---------------------------------------------------------------------
// PCI Express (pci_exp) Interface
//---------------------------------------------------------------------
// Tx
.pci_exp_txn ( PCI_EXP_TXN ),
.pci_exp_txp ( PCI_EXP_TXP ),
// Rx
.pci_exp_rxn ( PCI_EXP_RXN ),
.pci_exp_rxp ( PCI_EXP_RXP ),
//---------------------------------------------------------------------
// AXI-S Interface
//---------------------------------------------------------------------
// Common
.user_clk_out ( user_clk ),
.user_reset_out ( user_reset ),
.user_lnk_up ( user_lnk_up ),
.user_app_rdy ( user_app_rdy ),
// TX
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
.s_axis_tx_tlast ( s_axis_tx_tlast ),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
// Rx
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.tx_cfg_gnt ( tx_cfg_gnt ),
.rx_np_ok ( rx_np_ok ),
.rx_np_req ( rx_np_req ),
.cfg_trn_pending ( cfg_trn_pending ),
.cfg_pm_halt_aspm_l0s ( cfg_pm_halt_aspm_l0s ),
.cfg_pm_halt_aspm_l1 ( cfg_pm_halt_aspm_l1 ),
.cfg_pm_force_state_en ( cfg_pm_force_state_en ),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_dsn ( cfg_dsn ),
.cfg_turnoff_ok ( cfg_turnoff_ok ),
.cfg_pm_wake ( cfg_pm_wake ),
.cfg_pm_send_pme_to ( 1'b0 ),
.cfg_ds_bus_number ( 8'b0 ),
.cfg_ds_device_number ( 5'b0 ),
.cfg_ds_function_number ( 3'b0 ),
//---------------------------------------------------------------------
// Flow Control Interface
//---------------------------------------------------------------------
.fc_cpld ( fc_cpld ),
.fc_cplh ( fc_cplh ),
.fc_npd ( fc_npd ),
.fc_nph ( fc_nph ),
.fc_pd ( fc_pd ),
.fc_ph ( fc_ph ),
.fc_sel ( fc_sel ),
//---------------------------------------------------------------------
// Configuration (CFG) Interface
//---------------------------------------------------------------------
.cfg_device_number ( cfg_device_number ),
.cfg_dcommand2 ( cfg_dcommand2 ),
.cfg_pmcsr_pme_status ( cfg_pmcsr_pme_status ),
.cfg_status ( cfg_status ),
.cfg_to_turnoff ( cfg_to_turnoff ),
.cfg_received_func_lvl_rst ( cfg_received_func_lvl_rst ),
.cfg_dcommand ( cfg_dcommand ),
.cfg_bus_number ( cfg_bus_number ),
.cfg_function_number ( cfg_function_number ),
.cfg_command ( cfg_command ),
.cfg_dstatus ( cfg_dstatus ),
.cfg_lstatus ( cfg_lstatus ),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_lcommand ( cfg_lcommand ),
.cfg_pmcsr_pme_en ( cfg_pmcsr_pme_en ),
.cfg_pmcsr_powerstate ( cfg_pmcsr_powerstate ),
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
.cfg_interrupt ( cfg_interrupt ),
.cfg_interrupt_rdy ( cfg_interrupt_rdy ),
.cfg_interrupt_assert ( cfg_interrupt_assert ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msien ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_stat ( cfg_interrupt_stat ),
.cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ),
//---------------------------------------------------------------------
// System (SYS) Interface
//---------------------------------------------------------------------
.sys_clk ( pcie_refclk ),
.sys_rst_n ( pcie_reset_n )
);
riffa_wrapper_vc707
#(/*AUTOINSTPARAM*/
// Parameters
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_NUM_CHNL (C_NUM_CHNL),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES))
riffa
(
// Outputs
.CFG_INTERRUPT (cfg_interrupt),
.M_AXIS_RX_TREADY (m_axis_rx_tready),
.S_AXIS_TX_TDATA (s_axis_tx_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_TX_TKEEP (s_axis_tx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]),
.S_AXIS_TX_TLAST (s_axis_tx_tlast),
.S_AXIS_TX_TVALID (s_axis_tx_tvalid),
.S_AXIS_TX_TUSER (s_axis_tx_tuser[`SIG_XIL_TX_TUSER_W-1:0]),
.FC_SEL (fc_sel[`SIG_FC_SEL_W-1:0]),
.RST_OUT (rst_out),
.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
// Inputs
.M_AXIS_RX_TDATA (m_axis_rx_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RX_TKEEP (m_axis_rx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]),
.M_AXIS_RX_TLAST (m_axis_rx_tlast),
.M_AXIS_RX_TVALID (m_axis_rx_tvalid),
.M_AXIS_RX_TUSER (m_axis_rx_tuser[`SIG_XIL_RX_TUSER_W-1:0]),
.S_AXIS_TX_TREADY (s_axis_tx_tready),
.CFG_BUS_NUMBER (cfg_bus_number[`SIG_BUSID_W-1:0]),
.CFG_DEVICE_NUMBER (cfg_device_number[`SIG_DEVID_W-1:0]),
.CFG_FUNCTION_NUMBER (cfg_function_number[`SIG_FNID_W-1:0]),
.CFG_COMMAND (cfg_command[`SIG_CFGREG_W-1:0]),
.CFG_DCOMMAND (cfg_dcommand[`SIG_CFGREG_W-1:0]),
.CFG_LSTATUS (cfg_lstatus[`SIG_CFGREG_W-1:0]),
.CFG_LCOMMAND (cfg_lcommand[`SIG_CFGREG_W-1:0]),
.FC_CPLD (fc_cpld[`SIG_FC_CPLD_W-1:0]),
.FC_CPLH (fc_cplh[`SIG_FC_CPLH_W-1:0]),
.CFG_INTERRUPT_MSIEN (cfg_interrupt_msien),
.CFG_INTERRUPT_RDY (cfg_interrupt_rdy),
.USER_CLK (user_clk),
.USER_RESET (user_reset),
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0]),
.RX_NP_OK (rx_np_ok),
.TX_CFG_GNT (tx_cfg_gnt),
.RX_NP_REQ (rx_np_req)
/*AUTOINST*/);
// DRAM //////////////////////////////////////////////////////////////////////
// Wires and Registers of DRAM Controller
// ###########################################################################
wire CLK_DRAM_USER;
wire RST_DRAM_USER;
wire d_busy;
wire [`APPDATA_WIDTH-1:0] d_din;
wire d_w;
wire [`APPDATA_WIDTH-1:0] d_dout;
wire d_douten;
wire [1:0] d_req;
wire [31:0] d_initadr;
wire [31:0] d_blocks;
/* DRAM Controller Instantiation */
/******************************************************************************/
DRAMCON dramcon(.CLK_P(CLK_P),
.CLK_N(CLK_N),
.RST_X_IN(rst_out),
////////// User logic interface ports //////////
.D_REQ(d_req),
.D_INITADR(d_initadr),
.D_ELEM(d_blocks),
.D_BUSY(d_busy),
.D_DIN(d_din),
.D_W(d_w),
.D_DOUT(d_dout),
.D_DOUTEN(d_douten),
.USERCLK(CLK_DRAM_USER),
.RST_O(RST_DRAM_USER),
////////// Memory interface ports //////////
.DDR3DQ(DDR3DQ),
.DDR3DQS_N(DDR3DQS_N),
.DDR3DQS_P(DDR3DQS_P),
.DDR3ADDR(DDR3ADDR),
.DDR3BA(DDR3BA),
.DDR3RAS_N(DDR3RAS_N),
.DDR3CAS_N(DDR3CAS_N),
.DDR3WE_N(DDR3WE_N),
.DDR3RESET_N(DDR3RESET_N),
.DDR3CK_P(DDR3CK_P),
.DDR3CK_N(DDR3CK_N),
.DDR3CKE(DDR3CKE),
.DDR3CS_N(DDR3CS_N),
.DDR3DM(DDR3DM),
.DDR3ODT(DDR3ODT));
// DRAM //////////////////////////////////////////////////////////////////////
/* User Logic Instantiation */
/******************************************************************************/
USER_LOGIC #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
user_logic
(.CLK(CLK_DRAM_USER),
.RST(RST_DRAM_USER),
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk),
.CHNL_RX(chnl_rx),
.CHNL_RX_ACK(chnl_rx_ack),
.CHNL_RX_LAST(chnl_rx_last),
.CHNL_RX_LEN(chnl_rx_len),
.CHNL_RX_OFF(chnl_rx_off),
.CHNL_RX_DATA(chnl_rx_data),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid),
.CHNL_RX_DATA_REN(chnl_rx_data_ren),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk),
.CHNL_TX(chnl_tx),
.CHNL_TX_ACK(chnl_tx_ack),
.CHNL_TX_LAST(chnl_tx_last),
.CHNL_TX_LEN(chnl_tx_len),
.CHNL_TX_OFF(chnl_tx_off),
.CHNL_TX_DATA(chnl_tx_data),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid),
.CHNL_TX_DATA_REN(chnl_tx_data_ren),
// DRAM
.d_busy(d_busy),
.d_din(d_din),
.d_w(d_w),
.d_dout(d_dout),
.d_douten(d_douten),
.d_req(d_req),
.d_initadr(d_initadr),
.d_blocks(d_blocks)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_prbs_gen.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:10 $
// \ \ / \ Date Created: 05/12/10
// \___\/\___\
//
//Device: 7 Series
//Design Name: ddr_prbs_gen
// Overview:
// Implements a "pseudo-PRBS" generator. Basically this is a standard
// PRBS generator (using an linear feedback shift register) along with
// logic to force the repetition of the sequence after 2^PRBS_WIDTH
// samples (instead of 2^PRBS_WIDTH - 1). The LFSR is based on the design
// from Table 1 of XAPP 210. Note that only 8- and 10-tap long LFSR chains
// are supported in this code
// Parameter Requirements:
// 1. PRBS_WIDTH = 8 or 10
// 2. PRBS_WIDTH >= 2*nCK_PER_CLK
// Output notes:
// The output of this module consists of 2*nCK_PER_CLK bits, these contain
// the value of the LFSR output for the next 2*CK_PER_CLK bit times. Note
// that prbs_o[0] contains the bit value for the "earliest" bit time.
//
//Reference:
//Revision History:
//
//*****************************************************************************
/******************************************************************************
**$Id: ddr_prbs_gen.v,v 1.1 2011/06/02 08:35:10 mishra Exp $
**$Date: 2011/06/02 08:35:10 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_prbs_gen.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_prbs_gen #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter PRBS_WIDTH = 64, // LFSR shift register length
parameter DQS_CNT_WIDTH = 5,
parameter DQ_WIDTH = 72,
parameter VCCO_PAT_EN = 1,
parameter VCCAUX_PAT_EN = 1,
parameter ISI_PAT_EN = 1,
parameter FIXED_VICTIM = "TRUE"
)
(
input clk_i, // input clock
input clk_en_i, // clock enable
input rst_i, // synchronous reset
input [PRBS_WIDTH-1:0] prbs_seed_i, // initial LFSR seed
input phy_if_empty, // IN_FIFO empty flag
input prbs_rdlvl_start, // PRBS read lveling start
input prbs_rdlvl_done,
input complex_wr_done,
input [2:0] victim_sel,
input [DQS_CNT_WIDTH:0] byte_cnt,
//output [PRBS_WIDTH-1:0] prbs_o // generated pseudo random data
output [8*DQ_WIDTH-1:0] prbs_o,
output [9:0] dbg_prbs_gen,
input reset_rd_addr,
output prbs_ignore_first_byte,
output prbs_ignore_last_bytes
);
//***************************************************************************
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction
// Number of internal clock cycles before the PRBS sequence will repeat
localparam PRBS_SEQ_LEN_CYCLES = 128;
localparam PRBS_SEQ_LEN_CYCLES_BITS = clogb2(PRBS_SEQ_LEN_CYCLES);
reg phy_if_empty_r;
reg reseed_prbs_r;
reg [PRBS_SEQ_LEN_CYCLES_BITS-1:0] sample_cnt_r;
reg [PRBS_WIDTH - 1 :0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
//***************************************************************************
always @(posedge clk_i) begin
phy_if_empty_r <= #TCQ phy_if_empty;
end
//***************************************************************************
// Generate PRBS reset signal to ensure that PRBS sequence repeats after
// every 2**PRBS_WIDTH samples. Basically what happens is that we let the
// LFSR run for an extra cycle after "truly PRBS" 2**PRBS_WIDTH - 1
// samples have past. Once that extra cycle is finished, we reseed the LFSR
always @(posedge clk_i)
begin
if (rst_i || ~clk_en_i) begin
sample_cnt_r <= #TCQ 'b0;
reseed_prbs_r <= #TCQ 1'b0;
end else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin
// The rollver count should always be [(power of 2) - 1]
sample_cnt_r <= #TCQ sample_cnt_r + 1;
// Assert PRBS reset signal so that it is simultaneously with the
// last sample of the sequence
if (sample_cnt_r == PRBS_SEQ_LEN_CYCLES - 2)
reseed_prbs_r <= #TCQ 1'b1;
else
reseed_prbs_r <= #TCQ 1'b0;
end
end
always @ (posedge clk_i)
begin
//reset it to a known good state to prevent it locks up
if ((reseed_prbs_r && clk_en_i) || rst_i || ~clk_en_i) begin
lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5;
lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4];
end
else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin
lfsr_q[PRBS_WIDTH:31] <= #TCQ lfsr_q[PRBS_WIDTH-1:30];
lfsr_q[30] <= #TCQ lfsr_q[16] ^ lfsr_q[13] ^ lfsr_q[5] ^ lfsr_q[1];
lfsr_q[29:9] <= #TCQ lfsr_q[28:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
always @ (lfsr_q[PRBS_WIDTH:1]) begin
prbs = lfsr_q[PRBS_WIDTH:1];
end
//******************************************************************************
// Complex pattern BRAM
//******************************************************************************
localparam BRAM_ADDR_WIDTH = 8;
localparam BRAM_DATA_WIDTH = 18;
localparam BRAM_DEPTH = 256;
integer i;
(* RAM_STYLE = "distributed" *) reg [BRAM_ADDR_WIDTH - 1:0] rd_addr;
//reg [BRAM_DATA_WIDTH - 1:0] mem[0:BRAM_DEPTH - 1];
reg [BRAM_DATA_WIDTH - 1:0] mem_out;
reg [BRAM_DATA_WIDTH - 3:0] dout_o;
reg [DQ_WIDTH-1:0] sel;
reg [DQ_WIDTH-1:0] dout_rise0;
reg [DQ_WIDTH-1:0] dout_fall0;
reg [DQ_WIDTH-1:0] dout_rise1;
reg [DQ_WIDTH-1:0] dout_fall1;
reg [DQ_WIDTH-1:0] dout_rise2;
reg [DQ_WIDTH-1:0] dout_fall2;
reg [DQ_WIDTH-1:0] dout_rise3;
reg [DQ_WIDTH-1:0] dout_fall3;
// VCCO noise injection pattern with matching victim (reads with gaps)
// content format
// {aggressor pattern, victim pattern}
always @ (rd_addr) begin
case (rd_addr)
8'd0 : mem_out = {2'b11, 8'b10101010,8'b10101010}; //1 read
8'd1 : mem_out = {2'b01, 8'b11001100,8'b11001100}; //2 reads
8'd2 : mem_out = {2'b10, 8'b11001100,8'b11001100}; //2 reads
8'd3 : mem_out = {2'b01, 8'b11100011,8'b11100011}; //3 reads
8'd4 : mem_out = {2'b00, 8'b10001110,8'b10001110}; //3 reads
8'd5 : mem_out = {2'b10, 8'b00111000,8'b00111000}; //3 reads
8'd6 : mem_out = {2'b01, 8'b11110000,8'b11110000}; //4 reads
8'd7 : mem_out = {2'b00, 8'b11110000,8'b11110000}; //4 reads
8'd8 : mem_out = {2'b00, 8'b11110000,8'b11110000}; //4 reads
8'd9 : mem_out = {2'b10, 8'b11110000,8'b11110000}; //4 reads
8'd10 : mem_out = {2'b01, 8'b11111000,8'b11111000}; //5 reads
8'd11 : mem_out = {2'b00, 8'b00111110,8'b00111110}; //5 reads
8'd12 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //5 reads
8'd13 : mem_out = {2'b00, 8'b10000011,8'b10000011}; //5 reads
8'd14 : mem_out = {2'b10, 8'b11100000,8'b11100000}; //5 reads
8'd15 : mem_out = {2'b01, 8'b11111100,8'b11111100}; //6 reads
8'd16 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //6 reads
8'd17 : mem_out = {2'b00, 8'b11000000,8'b11000000}; //6 reads
8'd18 : mem_out = {2'b00, 8'b11111100,8'b11111100}; //6 reads
8'd19 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //6 reads
8'd20 : mem_out = {2'b10, 8'b11000000,8'b11000000}; //6 reads
// VCCO noise injection pattern with non-matching victim (reads with gaps)
// content format
// {aggressor pattern, victim pattern}
8'd21 : mem_out = {2'b11, 8'b10101010,8'b01010101}; //1 read
8'd22 : mem_out = {2'b01, 8'b11001100,8'b00110011}; //2 reads
8'd23 : mem_out = {2'b10, 8'b11001100,8'b00110011}; //2 reads
8'd24 : mem_out = {2'b01, 8'b11100011,8'b00011100}; //3 reads
8'd25 : mem_out = {2'b00, 8'b10001110,8'b01110001}; //3 reads
8'd26 : mem_out = {2'b10, 8'b00111000,8'b11000111}; //3 reads
8'd27 : mem_out = {2'b01, 8'b11110000,8'b00001111}; //4 reads
8'd28 : mem_out = {2'b00, 8'b11110000,8'b00001111}; //4 reads
8'd29 : mem_out = {2'b00, 8'b11110000,8'b00001111}; //4 reads
8'd30 : mem_out = {2'b10, 8'b11110000,8'b00001111}; //4 reads
8'd31 : mem_out = {2'b01, 8'b11111000,8'b00000111}; //5 reads
8'd32 : mem_out = {2'b00, 8'b00111110,8'b11000001}; //5 reads
8'd33 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //5 reads
8'd34 : mem_out = {2'b00, 8'b10000011,8'b01111100}; //5 reads
8'd35 : mem_out = {2'b10, 8'b11100000,8'b00011111}; //5 reads
8'd36 : mem_out = {2'b01, 8'b11111100,8'b00000011}; //6 reads
8'd37 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //6 reads
8'd38 : mem_out = {2'b00, 8'b11000000,8'b00111111}; //6 reads
8'd39 : mem_out = {2'b00, 8'b11111100,8'b00000011}; //6 reads
8'd40 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //6 reads
8'd41 : mem_out = {2'b10, 8'b11000000,8'b00111111}; //6 reads
// VCCAUX noise injection pattern with ISI pattern on victim (reads with gaps)
// content format
// {aggressor pattern, victim pattern}
8'd42 : mem_out = {2'b01, 8'b10110100,8'b01010111}; //3 reads
8'd43 : mem_out = {2'b00, 8'b10110100,8'b01101111}; //3 reads
8'd44 : mem_out = {2'b10, 8'b10110100,8'b11000000}; //3 reads
8'd45 : mem_out = {2'b01, 8'b10100010,8'b10000100}; //4 reads
8'd46 : mem_out = {2'b00, 8'b10001010,8'b00110001}; //4 reads
8'd47 : mem_out = {2'b00, 8'b00101000,8'b01000111}; //4 reads
8'd48 : mem_out = {2'b10, 8'b10100010,8'b00100101}; //4 reads
8'd49 : mem_out = {2'b01, 8'b10101111,8'b10011010}; //5 reads
8'd50 : mem_out = {2'b00, 8'b01010000,8'b01111010}; //5 reads
8'd51 : mem_out = {2'b00, 8'b10101111,8'b10010101}; //5 reads
8'd52 : mem_out = {2'b00, 8'b01010000,8'b11011011}; //5 reads
8'd53 : mem_out = {2'b10, 8'b10101111,8'b11110000}; //5 reads
8'd54 : mem_out = {2'b01, 8'b10101000,8'b00100001}; //7 reads
8'd55 : mem_out = {2'b00, 8'b00101010,8'b10001010}; //7 reads
8'd56 : mem_out = {2'b00, 8'b00001010,8'b00100101}; //7 reads
8'd57 : mem_out = {2'b00, 8'b10000010,8'b10011010}; //7 reads
8'd58 : mem_out = {2'b00, 8'b10100000,8'b01111010}; //7 reads
8'd59 : mem_out = {2'b00, 8'b10101000,8'b10111111}; //7 reads
8'd60 : mem_out = {2'b10, 8'b00101010,8'b01010111}; //7 reads
8'd61 : mem_out = {2'b01, 8'b10101011,8'b01101111}; //8 reads
8'd62 : mem_out = {2'b00, 8'b11110101,8'b11000000}; //8 reads
8'd63 : mem_out = {2'b00, 8'b01000000,8'b10000100}; //8 reads
8'd64 : mem_out = {2'b00, 8'b10101011,8'b00110001}; //8 reads
8'd65 : mem_out = {2'b00, 8'b11110101,8'b01000111}; //8 reads
8'd66 : mem_out = {2'b00, 8'b01000000,8'b00100101}; //8 reads
8'd67 : mem_out = {2'b00, 8'b10101011,8'b10011010}; //8 reads
8'd68 : mem_out = {2'b10, 8'b11110101,8'b01111010}; //8 reads
8'd69 : mem_out = {2'b01, 8'b10101010,8'b10010101}; //9 reads
8'd70 : mem_out = {2'b00, 8'b00000010,8'b11011011}; //9 reads
8'd71 : mem_out = {2'b00, 8'b10101000,8'b11110000}; //9 reads
8'd72 : mem_out = {2'b00, 8'b00001010,8'b00100001}; //9 reads
8'd73 : mem_out = {2'b00, 8'b10100000,8'b10001010}; //9 reads
8'd74 : mem_out = {2'b00, 8'b00101010,8'b00100101}; //9 reads
8'd75 : mem_out = {2'b00, 8'b10000000,8'b10011010}; //9 reads
8'd76 : mem_out = {2'b00, 8'b10101010,8'b01111010}; //9 reads
8'd77 : mem_out = {2'b10, 8'b00000010,8'b10111111}; //9 reads
8'd78 : mem_out = {2'b01, 8'b10101010,8'b01010111}; //10 reads
8'd79 : mem_out = {2'b00, 8'b11111111,8'b01101111}; //10 reads
8'd80 : mem_out = {2'b00, 8'b01010101,8'b11000000}; //10 reads
8'd81 : mem_out = {2'b00, 8'b00000000,8'b10000100}; //10 reads
8'd82 : mem_out = {2'b00, 8'b10101010,8'b00110001}; //10 reads
8'd83 : mem_out = {2'b00, 8'b11111111,8'b01000111}; //10 reads
8'd84 : mem_out = {2'b00, 8'b01010101,8'b00100101}; //10 reads
8'd85 : mem_out = {2'b00, 8'b00000000,8'b10011010}; //10 reads
8'd86 : mem_out = {2'b00, 8'b10101010,8'b01111010}; //10 reads
8'd87 : mem_out = {2'b10, 8'b11111111,8'b10010101}; //10 reads
8'd88 : mem_out = {2'b01, 8'b10101010,8'b11011011}; //12 reads
8'd89 : mem_out = {2'b00, 8'b10000000,8'b11110000}; //12 reads
8'd90 : mem_out = {2'b00, 8'b00101010,8'b00100001}; //12 reads
8'd91 : mem_out = {2'b00, 8'b10100000,8'b10001010}; //12 reads
8'd92 : mem_out = {2'b00, 8'b00001010,8'b00100101}; //12 reads
8'd93 : mem_out = {2'b00, 8'b10101000,8'b10011010}; //12 reads
8'd94 : mem_out = {2'b00, 8'b00000010,8'b01111010}; //12 reads
8'd95 : mem_out = {2'b00, 8'b10101010,8'b10111111}; //12 reads
8'd96 : mem_out = {2'b00, 8'b00000000,8'b01010111}; //12 reads
8'd97 : mem_out = {2'b00, 8'b10101010,8'b01101111}; //12 reads
8'd98 : mem_out = {2'b00, 8'b10000000,8'b11000000}; //12 reads
8'd99 : mem_out = {2'b10, 8'b00101010,8'b10000100}; //12 reads
8'd100 : mem_out = {2'b01, 8'b10101010,8'b00110001}; //13 reads
8'd101 : mem_out = {2'b00, 8'b10111111,8'b01000111}; //13 reads
8'd102 : mem_out = {2'b00, 8'b11110101,8'b00100101}; //13 reads
8'd103 : mem_out = {2'b00, 8'b01010100,8'b10011010}; //13 reads
8'd104 : mem_out = {2'b00, 8'b00000000,8'b01111010}; //13 reads
8'd105 : mem_out = {2'b00, 8'b10101010,8'b10010101}; //13 reads
8'd106 : mem_out = {2'b00, 8'b10111111,8'b11011011}; //13 reads
8'd107 : mem_out = {2'b00, 8'b11110101,8'b11110000}; //13 reads
8'd108 : mem_out = {2'b00, 8'b01010100,8'b00100001}; //13 reads
8'd109 : mem_out = {2'b00, 8'b00000000,8'b10001010}; //13 reads
8'd110 : mem_out = {2'b00, 8'b10101010,8'b00100101}; //13 reads
8'd111 : mem_out = {2'b00, 8'b10111111,8'b10011010}; //13 reads
8'd112 : mem_out = {2'b10, 8'b11110101,8'b01111010}; //13 reads
8'd113 : mem_out = {2'b01, 8'b10101010,8'b10111111}; //14 reads
8'd114 : mem_out = {2'b00, 8'b10100000,8'b01010111}; //14 reads
8'd115 : mem_out = {2'b00, 8'b00000010,8'b01101111}; //14 reads
8'd116 : mem_out = {2'b00, 8'b10101010,8'b11000000}; //14 reads
8'd117 : mem_out = {2'b00, 8'b10000000,8'b10000100}; //14 reads
8'd118 : mem_out = {2'b00, 8'b00001010,8'b00110001}; //14 reads
8'd119 : mem_out = {2'b00, 8'b10101010,8'b01000111}; //14 reads
8'd120 : mem_out = {2'b00, 8'b00000000,8'b00100101}; //14 reads
8'd121 : mem_out = {2'b00, 8'b00101010,8'b10011010}; //14 reads
8'd122 : mem_out = {2'b00, 8'b10101000,8'b01111010}; //14 reads
8'd123 : mem_out = {2'b00, 8'b00000000,8'b10010101}; //14 reads
8'd124 : mem_out = {2'b00, 8'b10101010,8'b11011011}; //14 reads
8'd125 : mem_out = {2'b00, 8'b10100000,8'b11110000}; //14 reads
8'd126 : mem_out = {2'b10, 8'b00000010,8'b00100001}; //14 reads
// ISI pattern (Back-to-back reads)
// content format
// {aggressor pattern, victim pattern}
8'd127 : mem_out = {2'b01, 8'b01010111,8'b01010111};
8'd128 : mem_out = {2'b00, 8'b01101111,8'b01101111};
8'd129 : mem_out = {2'b00, 8'b11000000,8'b11000000};
8'd130 : mem_out = {2'b00, 8'b10000110,8'b10000100};
8'd131 : mem_out = {2'b00, 8'b00101000,8'b00110001};
8'd132 : mem_out = {2'b00, 8'b11100100,8'b01000111};
8'd133 : mem_out = {2'b00, 8'b10110011,8'b00100101};
8'd134 : mem_out = {2'b00, 8'b01001111,8'b10011011};
8'd135 : mem_out = {2'b00, 8'b10110101,8'b01010101};
8'd136 : mem_out = {2'b00, 8'b10110101,8'b01010101};
8'd137 : mem_out = {2'b00, 8'b10000111,8'b10011000};
8'd138 : mem_out = {2'b00, 8'b11100011,8'b00011100};
8'd139 : mem_out = {2'b00, 8'b00001010,8'b11110101};
8'd140 : mem_out = {2'b00, 8'b11010100,8'b00101011};
8'd141 : mem_out = {2'b00, 8'b01001000,8'b10110111};
8'd142 : mem_out = {2'b00, 8'b00011111,8'b11100000};
8'd143 : mem_out = {2'b00, 8'b10111100,8'b01000011};
8'd144 : mem_out = {2'b00, 8'b10001111,8'b00010100};
8'd145 : mem_out = {2'b00, 8'b10110100,8'b01001011};
8'd146 : mem_out = {2'b00, 8'b11001011,8'b00110100};
8'd147 : mem_out = {2'b00, 8'b00001010,8'b11110101};
8'd148 : mem_out = {2'b00, 8'b10000000,8'b00000000};
//Additional for ISI
8'd149 : mem_out = {2'b00, 8'b00000000,8'b00000000};
8'd150 : mem_out = {2'b00, 8'b01010101,8'b01010101};
8'd151 : mem_out = {2'b00, 8'b01010101,8'b01010101};
8'd152 : mem_out = {2'b00, 8'b00000000,8'b00000000};
8'd153 : mem_out = {2'b00, 8'b00000000,8'b00000000};
8'd154 : mem_out = {2'b00, 8'b01010101,8'b00101010};
8'd155 : mem_out = {2'b00, 8'b01010101,8'b10101010};
8'd156 : mem_out = {2'b10, 8'b00000000,8'b10000000};
//Available
8'd157 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd158 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd159 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd160 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd161 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd162 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd163 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd164 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd165 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd166 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd167 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd168 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd169 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd170 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd171 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd172 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd173 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd174 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd175 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd176 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd177 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd178 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd179 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd180 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd181 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd182 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd183 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd184 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd185 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd186 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd187 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd188 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd189 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd190 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd191 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd192 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd193 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd194 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd195 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd196 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd197 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd198 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd199 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd200 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd201 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd202 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd203 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd204 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd205 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd206 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd207 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd208 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd209 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd210 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd211 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd212 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd213 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd214 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd215 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd216 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd217 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd218 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd219 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd220 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd221 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd222 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd223 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd224 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd225 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd226 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd227 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd228 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd229 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd230 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd231 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd232 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd233 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd234 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd235 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd236 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd237 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd238 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd239 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd240 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd241 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd242 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd243 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd244 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd245 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd246 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd247 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd248 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd249 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd250 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd251 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd252 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd253 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd254 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd255 : mem_out = {2'b00, 8'b00000001,8'b00000001};
endcase
end
always @ (posedge clk_i) begin
if (rst_i | reset_rd_addr)
rd_addr <= #TCQ 'b0;
//rd_addr for complex oclkdelay calib
else if (clk_en_i && prbs_rdlvl_done && (~phy_if_empty_r || ~complex_wr_done)) begin
if (rd_addr == 'd156) rd_addr <= #TCQ 'b0;
else rd_addr <= #TCQ rd_addr + 1;
end
//rd_addr for complex rdlvl
else if (clk_en_i && (~phy_if_empty_r || (~prbs_rdlvl_start && ~complex_wr_done))) begin
if (rd_addr == 'd148) rd_addr <= #TCQ 'b0;
else rd_addr <= #TCQ rd_addr+1;
end
end
// Each pattern can be disabled independently
// When disabled zeros are written to and read from the DRAM
always @ (posedge clk_i) begin
if ((rd_addr < 42) && VCCO_PAT_EN)
dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0];
else if ((rd_addr < 127) && VCCAUX_PAT_EN)
dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0];
else if (ISI_PAT_EN && (rd_addr > 126))
dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0];
else
dout_o <= #TCQ 'd0;
end
reg prbs_ignore_first_byte_r;
always @(posedge clk_i) prbs_ignore_first_byte_r <= #TCQ mem_out[16];
assign prbs_ignore_first_byte = prbs_ignore_first_byte_r;
reg prbs_ignore_last_bytes_r;
always @(posedge clk_i) prbs_ignore_last_bytes_r <= #TCQ mem_out[17];
assign prbs_ignore_last_bytes = prbs_ignore_last_bytes_r;
generate
if (FIXED_VICTIM == "TRUE") begin: victim_sel_fixed
// Fixed victim bit 3
always @(posedge clk_i)
sel <= #TCQ {DQ_WIDTH/8{8'h08}};
end else begin: victim_sel_rotate
// One-hot victim select
always @(posedge clk_i)
if (rst_i)
sel <= #TCQ 'd0;
else begin
for (i = 0; i < DQ_WIDTH; i = i+1) begin
if (i == byte_cnt*8+victim_sel)
sel[i] <= #TCQ 1'b1;
else
sel[i] <= #TCQ 1'b0;
end
end
end
endgenerate
// construct 8 X DATA_WIDTH output bus
always @(*)
for (i = 0; i < DQ_WIDTH; i = i+1) begin
dout_rise0[i] = (dout_o[7]&&sel[i] || dout_o[15]&&~sel[i]);
dout_fall0[i] = (dout_o[6]&&sel[i] || dout_o[14]&&~sel[i]);
dout_rise1[i] = (dout_o[5]&&sel[i] || dout_o[13]&&~sel[i]);
dout_fall1[i] = (dout_o[4]&&sel[i] || dout_o[12]&&~sel[i]);
dout_rise2[i] = (dout_o[3]&&sel[i] || dout_o[11]&&~sel[i]);
dout_fall2[i] = (dout_o[2]&&sel[i] || dout_o[10]&&~sel[i]);
dout_rise3[i] = (dout_o[1]&&sel[i] || dout_o[9]&&~sel[i]);
dout_fall3[i] = (dout_o[0]&&sel[i] || dout_o[8]&&~sel[i]);
end
assign prbs_o = {dout_fall3, dout_rise3, dout_fall2, dout_rise2, dout_fall1, dout_rise1, dout_fall0, dout_rise0};
assign dbg_prbs_gen[9] = phy_if_empty_r;
assign dbg_prbs_gen[8] = clk_en_i;
assign dbg_prbs_gen[7:0] = rd_addr[7:0];
endmodule
|
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_set_verbosity O 1 const
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1
// valid O 1
// addr O 32 reg
// word64 O 64
// st_amo_val O 64
// exc O 1
// exc_code O 4 reg
// RDY_server_flush_request_put O 1 reg
// RDY_server_flush_response_get O 1
// RDY_tlb_flush O 1 const
// mem_master_awvalid O 1 reg
// mem_master_awid O 4 reg
// mem_master_awaddr O 64 reg
// mem_master_awlen O 8 reg
// mem_master_awsize O 3 reg
// mem_master_awburst O 2 reg
// mem_master_awlock O 1 reg
// mem_master_awcache O 4 reg
// mem_master_awprot O 3 reg
// mem_master_awqos O 4 reg
// mem_master_awregion O 4 reg
// mem_master_wvalid O 1 reg
// mem_master_wdata O 64 reg
// mem_master_wstrb O 8 reg
// mem_master_wlast O 1 reg
// mem_master_bready O 1 reg
// mem_master_arvalid O 1 reg
// mem_master_arid O 4 reg
// mem_master_araddr O 64 reg
// mem_master_arlen O 8 reg
// mem_master_arsize O 3 reg
// mem_master_arburst O 2 reg
// mem_master_arlock O 1 reg
// mem_master_arcache O 4 reg
// mem_master_arprot O 3 reg
// mem_master_arqos O 4 reg
// mem_master_arregion O 4 reg
// mem_master_rready O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4 reg
// req_op I 2
// req_f3 I 3
// req_amo_funct7 I 7 reg
// req_addr I 32
// req_st_value I 64
// req_priv I 2 unused
// req_sstatus_SUM I 1 unused
// req_mstatus_MXR I 1 unused
// req_satp I 32 unused
// mem_master_awready I 1
// mem_master_wready I 1
// mem_master_bvalid I 1
// mem_master_bid I 4 reg
// mem_master_bresp I 2 reg
// mem_master_arready I 1
// mem_master_rvalid I 1
// mem_master_rid I 4 reg
// mem_master_rdata I 64 reg
// mem_master_rresp I 2 reg
// mem_master_rlast I 1 reg
// EN_set_verbosity I 1
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_req I 1
// EN_server_flush_request_put I 1
// EN_server_flush_response_get I 1
// EN_tlb_flush I 1 unused
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkMMU_Cache(CLK,
RST_N,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
req_op,
req_f3,
req_amo_funct7,
req_addr,
req_st_value,
req_priv,
req_sstatus_SUM,
req_mstatus_MXR,
req_satp,
EN_req,
valid,
addr,
word64,
st_amo_val,
exc,
exc_code,
EN_server_flush_request_put,
RDY_server_flush_request_put,
EN_server_flush_response_get,
RDY_server_flush_response_get,
EN_tlb_flush,
RDY_tlb_flush,
mem_master_awvalid,
mem_master_awid,
mem_master_awaddr,
mem_master_awlen,
mem_master_awsize,
mem_master_awburst,
mem_master_awlock,
mem_master_awcache,
mem_master_awprot,
mem_master_awqos,
mem_master_awregion,
mem_master_awready,
mem_master_wvalid,
mem_master_wdata,
mem_master_wstrb,
mem_master_wlast,
mem_master_wready,
mem_master_bvalid,
mem_master_bid,
mem_master_bresp,
mem_master_bready,
mem_master_arvalid,
mem_master_arid,
mem_master_araddr,
mem_master_arlen,
mem_master_arsize,
mem_master_arburst,
mem_master_arlock,
mem_master_arcache,
mem_master_arprot,
mem_master_arqos,
mem_master_arregion,
mem_master_arready,
mem_master_rvalid,
mem_master_rid,
mem_master_rdata,
mem_master_rresp,
mem_master_rlast,
mem_master_rready);
parameter [0 : 0] dmem_not_imem = 1'b0;
input CLK;
input RST_N;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// action method req
input [1 : 0] req_op;
input [2 : 0] req_f3;
input [6 : 0] req_amo_funct7;
input [31 : 0] req_addr;
input [63 : 0] req_st_value;
input [1 : 0] req_priv;
input req_sstatus_SUM;
input req_mstatus_MXR;
input [31 : 0] req_satp;
input EN_req;
// value method valid
output valid;
// value method addr
output [31 : 0] addr;
// value method word64
output [63 : 0] word64;
// value method st_amo_val
output [63 : 0] st_amo_val;
// value method exc
output exc;
// value method exc_code
output [3 : 0] exc_code;
// action method server_flush_request_put
input EN_server_flush_request_put;
output RDY_server_flush_request_put;
// action method server_flush_response_get
input EN_server_flush_response_get;
output RDY_server_flush_response_get;
// action method tlb_flush
input EN_tlb_flush;
output RDY_tlb_flush;
// value method mem_master_m_awvalid
output mem_master_awvalid;
// value method mem_master_m_awid
output [3 : 0] mem_master_awid;
// value method mem_master_m_awaddr
output [63 : 0] mem_master_awaddr;
// value method mem_master_m_awlen
output [7 : 0] mem_master_awlen;
// value method mem_master_m_awsize
output [2 : 0] mem_master_awsize;
// value method mem_master_m_awburst
output [1 : 0] mem_master_awburst;
// value method mem_master_m_awlock
output mem_master_awlock;
// value method mem_master_m_awcache
output [3 : 0] mem_master_awcache;
// value method mem_master_m_awprot
output [2 : 0] mem_master_awprot;
// value method mem_master_m_awqos
output [3 : 0] mem_master_awqos;
// value method mem_master_m_awregion
output [3 : 0] mem_master_awregion;
// value method mem_master_m_awuser
// action method mem_master_m_awready
input mem_master_awready;
// value method mem_master_m_wvalid
output mem_master_wvalid;
// value method mem_master_m_wdata
output [63 : 0] mem_master_wdata;
// value method mem_master_m_wstrb
output [7 : 0] mem_master_wstrb;
// value method mem_master_m_wlast
output mem_master_wlast;
// value method mem_master_m_wuser
// action method mem_master_m_wready
input mem_master_wready;
// action method mem_master_m_bvalid
input mem_master_bvalid;
input [3 : 0] mem_master_bid;
input [1 : 0] mem_master_bresp;
// value method mem_master_m_bready
output mem_master_bready;
// value method mem_master_m_arvalid
output mem_master_arvalid;
// value method mem_master_m_arid
output [3 : 0] mem_master_arid;
// value method mem_master_m_araddr
output [63 : 0] mem_master_araddr;
// value method mem_master_m_arlen
output [7 : 0] mem_master_arlen;
// value method mem_master_m_arsize
output [2 : 0] mem_master_arsize;
// value method mem_master_m_arburst
output [1 : 0] mem_master_arburst;
// value method mem_master_m_arlock
output mem_master_arlock;
// value method mem_master_m_arcache
output [3 : 0] mem_master_arcache;
// value method mem_master_m_arprot
output [2 : 0] mem_master_arprot;
// value method mem_master_m_arqos
output [3 : 0] mem_master_arqos;
// value method mem_master_m_arregion
output [3 : 0] mem_master_arregion;
// value method mem_master_m_aruser
// action method mem_master_m_arready
input mem_master_arready;
// action method mem_master_m_rvalid
input mem_master_rvalid;
input [3 : 0] mem_master_rid;
input [63 : 0] mem_master_rdata;
input [1 : 0] mem_master_rresp;
input mem_master_rlast;
// value method mem_master_m_rready
output mem_master_rready;
// signals for module outputs
reg [63 : 0] word64;
wire [63 : 0] mem_master_araddr,
mem_master_awaddr,
mem_master_wdata,
st_amo_val;
wire [31 : 0] addr;
wire [7 : 0] mem_master_arlen, mem_master_awlen, mem_master_wstrb;
wire [3 : 0] exc_code,
mem_master_arcache,
mem_master_arid,
mem_master_arqos,
mem_master_arregion,
mem_master_awcache,
mem_master_awid,
mem_master_awqos,
mem_master_awregion;
wire [2 : 0] mem_master_arprot,
mem_master_arsize,
mem_master_awprot,
mem_master_awsize;
wire [1 : 0] mem_master_arburst, mem_master_awburst;
wire RDY_server_flush_request_put,
RDY_server_flush_response_get,
RDY_server_reset_request_put,
RDY_server_reset_response_get,
RDY_set_verbosity,
RDY_tlb_flush,
exc,
mem_master_arlock,
mem_master_arvalid,
mem_master_awlock,
mem_master_awvalid,
mem_master_bready,
mem_master_rready,
mem_master_wlast,
mem_master_wvalid,
valid;
// inlined wires
wire [3 : 0] ctr_wr_rsps_pending_crg$port0__write_1,
ctr_wr_rsps_pending_crg$port1__write_1,
ctr_wr_rsps_pending_crg$port2__read,
ctr_wr_rsps_pending_crg$port3__read;
wire ctr_wr_rsps_pending_crg$EN_port2__write, dw_valid$whas;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register ctr_wr_rsps_pending_crg
reg [3 : 0] ctr_wr_rsps_pending_crg;
wire [3 : 0] ctr_wr_rsps_pending_crg$D_IN;
wire ctr_wr_rsps_pending_crg$EN;
// register rg_addr
reg [31 : 0] rg_addr;
wire [31 : 0] rg_addr$D_IN;
wire rg_addr$EN;
// register rg_amo_funct7
reg [6 : 0] rg_amo_funct7;
wire [6 : 0] rg_amo_funct7$D_IN;
wire rg_amo_funct7$EN;
// register rg_cset_in_cache
reg [6 : 0] rg_cset_in_cache;
wire [6 : 0] rg_cset_in_cache$D_IN;
wire rg_cset_in_cache$EN;
// register rg_error_during_refill
reg rg_error_during_refill;
wire rg_error_during_refill$D_IN, rg_error_during_refill$EN;
// register rg_exc_code
reg [3 : 0] rg_exc_code;
reg [3 : 0] rg_exc_code$D_IN;
wire rg_exc_code$EN;
// register rg_f3
reg [2 : 0] rg_f3;
wire [2 : 0] rg_f3$D_IN;
wire rg_f3$EN;
// register rg_ld_val
reg [63 : 0] rg_ld_val;
reg [63 : 0] rg_ld_val$D_IN;
wire rg_ld_val$EN;
// register rg_lower_word32
reg [31 : 0] rg_lower_word32;
wire [31 : 0] rg_lower_word32$D_IN;
wire rg_lower_word32$EN;
// register rg_lower_word32_full
reg rg_lower_word32_full;
wire rg_lower_word32_full$D_IN, rg_lower_word32_full$EN;
// register rg_lrsc_pa
reg [31 : 0] rg_lrsc_pa;
wire [31 : 0] rg_lrsc_pa$D_IN;
wire rg_lrsc_pa$EN;
// register rg_lrsc_valid
reg rg_lrsc_valid;
wire rg_lrsc_valid$D_IN, rg_lrsc_valid$EN;
// register rg_op
reg [1 : 0] rg_op;
wire [1 : 0] rg_op$D_IN;
wire rg_op$EN;
// register rg_pa
reg [31 : 0] rg_pa;
wire [31 : 0] rg_pa$D_IN;
wire rg_pa$EN;
// register rg_pte_pa
reg [31 : 0] rg_pte_pa;
wire [31 : 0] rg_pte_pa$D_IN;
wire rg_pte_pa$EN;
// register rg_st_amo_val
reg [63 : 0] rg_st_amo_val;
wire [63 : 0] rg_st_amo_val$D_IN;
wire rg_st_amo_val$EN;
// register rg_state
reg [3 : 0] rg_state;
reg [3 : 0] rg_state$D_IN;
wire rg_state$EN;
// register rg_victim_way
reg rg_victim_way;
wire rg_victim_way$D_IN, rg_victim_way$EN;
// register rg_word64_set_in_cache
reg [8 : 0] rg_word64_set_in_cache;
wire [8 : 0] rg_word64_set_in_cache$D_IN;
wire rg_word64_set_in_cache$EN;
// ports of submodule f_fabric_write_reqs
reg [98 : 0] f_fabric_write_reqs$D_IN;
wire [98 : 0] f_fabric_write_reqs$D_OUT;
wire f_fabric_write_reqs$CLR,
f_fabric_write_reqs$DEQ,
f_fabric_write_reqs$EMPTY_N,
f_fabric_write_reqs$ENQ,
f_fabric_write_reqs$FULL_N;
// ports of submodule f_reset_reqs
wire f_reset_reqs$CLR,
f_reset_reqs$DEQ,
f_reset_reqs$D_IN,
f_reset_reqs$D_OUT,
f_reset_reqs$EMPTY_N,
f_reset_reqs$ENQ,
f_reset_reqs$FULL_N;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$D_IN,
f_reset_rsps$D_OUT,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule master_xactor_f_rd_addr
wire [96 : 0] master_xactor_f_rd_addr$D_IN, master_xactor_f_rd_addr$D_OUT;
wire master_xactor_f_rd_addr$CLR,
master_xactor_f_rd_addr$DEQ,
master_xactor_f_rd_addr$EMPTY_N,
master_xactor_f_rd_addr$ENQ,
master_xactor_f_rd_addr$FULL_N;
// ports of submodule master_xactor_f_rd_data
wire [70 : 0] master_xactor_f_rd_data$D_IN, master_xactor_f_rd_data$D_OUT;
wire master_xactor_f_rd_data$CLR,
master_xactor_f_rd_data$DEQ,
master_xactor_f_rd_data$EMPTY_N,
master_xactor_f_rd_data$ENQ,
master_xactor_f_rd_data$FULL_N;
// ports of submodule master_xactor_f_wr_addr
wire [96 : 0] master_xactor_f_wr_addr$D_IN, master_xactor_f_wr_addr$D_OUT;
wire master_xactor_f_wr_addr$CLR,
master_xactor_f_wr_addr$DEQ,
master_xactor_f_wr_addr$EMPTY_N,
master_xactor_f_wr_addr$ENQ,
master_xactor_f_wr_addr$FULL_N;
// ports of submodule master_xactor_f_wr_data
wire [72 : 0] master_xactor_f_wr_data$D_IN, master_xactor_f_wr_data$D_OUT;
wire master_xactor_f_wr_data$CLR,
master_xactor_f_wr_data$DEQ,
master_xactor_f_wr_data$EMPTY_N,
master_xactor_f_wr_data$ENQ,
master_xactor_f_wr_data$FULL_N;
// ports of submodule master_xactor_f_wr_resp
wire [5 : 0] master_xactor_f_wr_resp$D_IN, master_xactor_f_wr_resp$D_OUT;
wire master_xactor_f_wr_resp$CLR,
master_xactor_f_wr_resp$DEQ,
master_xactor_f_wr_resp$EMPTY_N,
master_xactor_f_wr_resp$ENQ,
master_xactor_f_wr_resp$FULL_N;
// ports of submodule ram_state_and_ctag_cset
wire [45 : 0] ram_state_and_ctag_cset$DIA,
ram_state_and_ctag_cset$DIB,
ram_state_and_ctag_cset$DOB;
wire [6 : 0] ram_state_and_ctag_cset$ADDRA, ram_state_and_ctag_cset$ADDRB;
wire ram_state_and_ctag_cset$ENA,
ram_state_and_ctag_cset$ENB,
ram_state_and_ctag_cset$WEA,
ram_state_and_ctag_cset$WEB;
// ports of submodule ram_word64_set
reg [127 : 0] ram_word64_set$DIB;
reg [8 : 0] ram_word64_set$ADDRB;
wire [127 : 0] ram_word64_set$DIA, ram_word64_set$DOB;
wire [8 : 0] ram_word64_set$ADDRA;
wire ram_word64_set$ENA,
ram_word64_set$ENB,
ram_word64_set$WEA,
ram_word64_set$WEB;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr;
wire soc_map$m_is_mem_addr;
// rule scheduling signals
wire CAN_FIRE_RL_rl_ST_AMO_response,
CAN_FIRE_RL_rl_cache_refill_rsps_loop,
CAN_FIRE_RL_rl_discard_write_rsp,
CAN_FIRE_RL_rl_drive_exception_rsp,
CAN_FIRE_RL_rl_fabric_send_write_req,
CAN_FIRE_RL_rl_io_AMO_SC_req,
CAN_FIRE_RL_rl_io_AMO_op_req,
CAN_FIRE_RL_rl_io_AMO_read_rsp,
CAN_FIRE_RL_rl_io_read_req,
CAN_FIRE_RL_rl_io_read_rsp,
CAN_FIRE_RL_rl_io_write_req,
CAN_FIRE_RL_rl_maintain_io_read_rsp,
CAN_FIRE_RL_rl_probe_and_immed_rsp,
CAN_FIRE_RL_rl_rereq,
CAN_FIRE_RL_rl_reset,
CAN_FIRE_RL_rl_start_cache_refill,
CAN_FIRE_RL_rl_start_reset,
CAN_FIRE_mem_master_m_arready,
CAN_FIRE_mem_master_m_awready,
CAN_FIRE_mem_master_m_bvalid,
CAN_FIRE_mem_master_m_rvalid,
CAN_FIRE_mem_master_m_wready,
CAN_FIRE_req,
CAN_FIRE_server_flush_request_put,
CAN_FIRE_server_flush_response_get,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_set_verbosity,
CAN_FIRE_tlb_flush,
WILL_FIRE_RL_rl_ST_AMO_response,
WILL_FIRE_RL_rl_cache_refill_rsps_loop,
WILL_FIRE_RL_rl_discard_write_rsp,
WILL_FIRE_RL_rl_drive_exception_rsp,
WILL_FIRE_RL_rl_fabric_send_write_req,
WILL_FIRE_RL_rl_io_AMO_SC_req,
WILL_FIRE_RL_rl_io_AMO_op_req,
WILL_FIRE_RL_rl_io_AMO_read_rsp,
WILL_FIRE_RL_rl_io_read_req,
WILL_FIRE_RL_rl_io_read_rsp,
WILL_FIRE_RL_rl_io_write_req,
WILL_FIRE_RL_rl_maintain_io_read_rsp,
WILL_FIRE_RL_rl_probe_and_immed_rsp,
WILL_FIRE_RL_rl_rereq,
WILL_FIRE_RL_rl_reset,
WILL_FIRE_RL_rl_start_cache_refill,
WILL_FIRE_RL_rl_start_reset,
WILL_FIRE_mem_master_m_arready,
WILL_FIRE_mem_master_m_awready,
WILL_FIRE_mem_master_m_bvalid,
WILL_FIRE_mem_master_m_rvalid,
WILL_FIRE_mem_master_m_wready,
WILL_FIRE_req,
WILL_FIRE_server_flush_request_put,
WILL_FIRE_server_flush_response_get,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_set_verbosity,
WILL_FIRE_tlb_flush;
// inputs to muxes for submodule ports
wire [127 : 0] MUX_ram_word64_set$a_put_3__VAL_1,
MUX_ram_word64_set$a_put_3__VAL_2;
wire [98 : 0] MUX_f_fabric_write_reqs$enq_1__VAL_1,
MUX_f_fabric_write_reqs$enq_1__VAL_2,
MUX_f_fabric_write_reqs$enq_1__VAL_3;
wire [96 : 0] MUX_master_xactor_f_rd_addr$enq_1__VAL_1,
MUX_master_xactor_f_rd_addr$enq_1__VAL_2;
wire [63 : 0] MUX_dw_output_ld_val$wset_1__VAL_3,
MUX_rg_ld_val$write_1__VAL_2;
wire [45 : 0] MUX_ram_state_and_ctag_cset$a_put_3__VAL_1;
wire [8 : 0] MUX_ram_word64_set$b_put_2__VAL_2,
MUX_ram_word64_set$b_put_2__VAL_4;
wire [6 : 0] MUX_rg_cset_in_cache$write_1__VAL_1;
wire [3 : 0] MUX_rg_exc_code$write_1__VAL_1,
MUX_rg_state$write_1__VAL_1,
MUX_rg_state$write_1__VAL_10,
MUX_rg_state$write_1__VAL_12,
MUX_rg_state$write_1__VAL_3;
wire MUX_dw_output_ld_val$wset_1__SEL_1,
MUX_dw_output_ld_val$wset_1__SEL_2,
MUX_dw_output_ld_val$wset_1__SEL_3,
MUX_dw_output_ld_val$wset_1__SEL_4,
MUX_f_fabric_write_reqs$enq_1__SEL_2,
MUX_master_xactor_f_rd_addr$enq_1__SEL_1,
MUX_ram_state_and_ctag_cset$a_put_1__SEL_1,
MUX_ram_state_and_ctag_cset$b_put_1__SEL_1,
MUX_ram_word64_set$a_put_1__SEL_1,
MUX_ram_word64_set$b_put_1__SEL_2,
MUX_rg_error_during_refill$write_1__SEL_1,
MUX_rg_exc_code$write_1__SEL_1,
MUX_rg_exc_code$write_1__SEL_2,
MUX_rg_exc_code$write_1__SEL_3,
MUX_rg_ld_val$write_1__SEL_2,
MUX_rg_lrsc_valid$write_1__SEL_2,
MUX_rg_state$write_1__SEL_10,
MUX_rg_state$write_1__SEL_12,
MUX_rg_state$write_1__SEL_13,
MUX_rg_state$write_1__SEL_2,
MUX_rg_state$write_1__SEL_3;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h4093;
reg [31 : 0] v__h4192;
reg [31 : 0] v__h4341;
reg [31 : 0] v__h19635;
reg [31 : 0] v__h23351;
reg [31 : 0] v__h26669;
reg [31 : 0] v__h27408;
reg [31 : 0] v__h27649;
reg [31 : 0] v__h30045;
reg [31 : 0] v__h30395;
reg [31 : 0] v__h31495;
reg [31 : 0] v__h31602;
reg [31 : 0] v__h31707;
reg [31 : 0] v__h31787;
reg [31 : 0] v__h31997;
reg [31 : 0] v__h32115;
reg [31 : 0] v__h32409;
reg [31 : 0] v__h32584;
reg [31 : 0] v__h34843;
reg [31 : 0] v__h32680;
reg [31 : 0] v__h35450;
reg [31 : 0] v__h35411;
reg [31 : 0] v__h3625;
reg [31 : 0] v__h35798;
reg [31 : 0] v__h3619;
reg [31 : 0] v__h4087;
reg [31 : 0] v__h4186;
reg [31 : 0] v__h4335;
reg [31 : 0] v__h19629;
reg [31 : 0] v__h23345;
reg [31 : 0] v__h26663;
reg [31 : 0] v__h27402;
reg [31 : 0] v__h27643;
reg [31 : 0] v__h30039;
reg [31 : 0] v__h30389;
reg [31 : 0] v__h31489;
reg [31 : 0] v__h31596;
reg [31 : 0] v__h31701;
reg [31 : 0] v__h31781;
reg [31 : 0] v__h31991;
reg [31 : 0] v__h32109;
reg [31 : 0] v__h32403;
reg [31 : 0] v__h32578;
reg [31 : 0] v__h32674;
reg [31 : 0] v__h34837;
reg [31 : 0] v__h35405;
reg [31 : 0] v__h35444;
reg [31 : 0] v__h35792;
// synopsys translate_on
// remaining internal signals
reg [63 : 0] CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q30,
CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q33,
CASE_rg_addr_BITS_2_TO_0_0x0_result1275_0x4_re_ETC__q34,
CASE_rg_addr_BITS_2_TO_0_0x0_result1340_0x4_re_ETC__q35,
CASE_rg_addr_BITS_2_TO_0_0x0_result4551_0x4_re_ETC__q50,
CASE_rg_addr_BITS_2_TO_0_0x0_result9455_0x4_re_ETC__q29,
CASE_rg_f3_0b0_IF_rg_addr_9_BITS_2_TO_0_31_EQ__ETC__q52,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d338,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d711,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d731,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d850,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d428,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d437,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d505,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d514,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d695,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d723,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832,
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347,
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386,
_theResult_____2__h23875,
_theResult_____2__h32756,
ld_val__h30504,
mem_req_wr_data_wdata__h2818,
n__h20801,
n__h23737,
new_ld_val__h32710,
old_word64__h20790,
w1__h23867,
w1__h32744,
w1__h32748;
reg [7 : 0] mem_req_wr_data_wstrb__h2819;
reg [2 : 0] value__h32296, x__h2639;
wire [63 : 0] IF_NOT_ram_state_and_ctag_cset_b_read__05_BIT__ETC___d448,
IF_NOT_ram_state_and_ctag_cset_b_read__05_BIT__ETC___d525,
IF_ram_state_and_ctag_cset_b_read__05_BIT_45_1_ETC___d447,
IF_ram_state_and_ctag_cset_b_read__05_BIT_45_1_ETC___d524,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_1_E_ETC___d355,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_IF__ETC___d851,
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_ram_ETC___d340,
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_rg_st_amo_val_ETC___d455,
IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d532,
_theResult___snd_fst__h2826,
cline_fabric_addr__h26722,
fabric_addr__h32167,
mem_req_wr_addr_awaddr__h2592,
new_st_val__h23573,
new_st_val__h23879,
new_st_val__h23970,
new_st_val__h24950,
new_st_val__h24954,
new_st_val__h24958,
new_st_val__h24962,
new_st_val__h24967,
new_st_val__h24973,
new_st_val__h24978,
new_st_val__h32760,
new_st_val__h32851,
new_st_val__h34711,
new_st_val__h34715,
new_st_val__h34719,
new_st_val__h34723,
new_st_val__h34728,
new_st_val__h34734,
new_st_val__h34739,
new_value__h22441,
new_value__h6012,
result__h18723,
result__h18751,
result__h18779,
result__h18807,
result__h18835,
result__h18863,
result__h18891,
result__h18919,
result__h18964,
result__h18992,
result__h19020,
result__h19048,
result__h19076,
result__h19104,
result__h19132,
result__h19160,
result__h19205,
result__h19233,
result__h19261,
result__h19289,
result__h19330,
result__h19358,
result__h19386,
result__h19414,
result__h19455,
result__h19483,
result__h19522,
result__h19550,
result__h30564,
result__h30594,
result__h30621,
result__h30648,
result__h30675,
result__h30702,
result__h30729,
result__h30756,
result__h30800,
result__h30827,
result__h30854,
result__h30881,
result__h30908,
result__h30935,
result__h30962,
result__h30989,
result__h31033,
result__h31060,
result__h31087,
result__h31114,
result__h31154,
result__h31181,
result__h31208,
result__h31235,
result__h31275,
result__h31302,
result__h31340,
result__h31367,
result__h32939,
result__h33847,
result__h33875,
result__h33903,
result__h33931,
result__h33959,
result__h33987,
result__h34015,
result__h34060,
result__h34088,
result__h34116,
result__h34144,
result__h34172,
result__h34200,
result__h34228,
result__h34256,
result__h34301,
result__h34329,
result__h34357,
result__h34385,
result__h34426,
result__h34454,
result__h34482,
result__h34510,
result__h34551,
result__h34579,
result__h34618,
result__h34646,
w1___1__h23938,
w1___1__h32819,
w2___1__h32820,
w2__h32750,
word64__h5847,
x__h20022,
x__h32739,
x__h6037,
y__h12367,
y__h6038,
y__h6052;
wire [31 : 0] IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC__q31,
cline_addr__h26721,
ld_val0504_BITS_31_TO_0__q38,
ld_val0504_BITS_63_TO_32__q45,
master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3,
master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10,
rg_st_amo_val_BITS_31_TO_0__q32,
w12744_BITS_31_TO_0__q51,
word64847_BITS_31_TO_0__q17,
word64847_BITS_63_TO_32__q24;
wire [21 : 0] n_ctag__h27950, pa_ctag__h5533;
wire [15 : 0] ld_val0504_BITS_15_TO_0__q37,
ld_val0504_BITS_31_TO_16__q41,
ld_val0504_BITS_47_TO_32__q44,
ld_val0504_BITS_63_TO_48__q48,
master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2,
master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q7,
master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9,
master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13,
word64847_BITS_15_TO_0__q16,
word64847_BITS_31_TO_16__q20,
word64847_BITS_47_TO_32__q23,
word64847_BITS_63_TO_48__q27;
wire [7 : 0] ld_val0504_BITS_15_TO_8__q39,
ld_val0504_BITS_23_TO_16__q40,
ld_val0504_BITS_31_TO_24__q42,
ld_val0504_BITS_39_TO_32__q43,
ld_val0504_BITS_47_TO_40__q46,
ld_val0504_BITS_55_TO_48__q47,
ld_val0504_BITS_63_TO_56__q49,
ld_val0504_BITS_7_TO_0__q36,
master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1,
master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4,
master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q6,
master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q8,
master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q5,
master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11,
master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12,
master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14,
strobe64__h2756,
strobe64__h2758,
strobe64__h2760,
word64847_BITS_15_TO_8__q18,
word64847_BITS_23_TO_16__q19,
word64847_BITS_31_TO_24__q21,
word64847_BITS_39_TO_32__q22,
word64847_BITS_47_TO_40__q25,
word64847_BITS_55_TO_48__q26,
word64847_BITS_63_TO_56__q28,
word64847_BITS_7_TO_0__q15;
wire [5 : 0] shift_bits__h2606;
wire [3 : 0] IF_NOT_ram_state_and_ctag_cset_b_read__05_BIT__ETC___d152,
IF_rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d154,
IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d153,
access_exc_code__h2374,
b__h26623;
wire [1 : 0] tmp__h26884, tmp__h26885;
wire IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d122,
NOT_cfg_verbosity_read__0_ULE_1_1___d42,
NOT_cfg_verbosity_read__0_ULE_2_99___d600,
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d162,
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d361,
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d369,
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d372,
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d378,
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d382,
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d393,
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d535,
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d547,
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d577,
NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d121,
NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d168,
NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d370,
NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d375,
NOT_req_f3_BITS_1_TO_0_36_EQ_0b0_37_38_AND_NOT_ETC___d957,
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d149,
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d530,
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d550,
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d558,
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d570,
NOT_rg_op_4_EQ_1_2_74_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d390,
NOT_rg_op_4_EQ_1_2_74_AND_ram_state_and_ctag_c_ETC___d379,
NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d388,
NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d548,
NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d552,
NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d556,
dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_0__ETC___d124,
lrsc_result__h20012,
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111,
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117,
ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d165,
ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d176,
ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d359,
ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d572,
req_f3_BITS_1_TO_0_36_EQ_0b0_37_OR_req_f3_BITS_ETC___d966,
rg_addr_9_EQ_rg_lrsc_pa_8___d166,
rg_amo_funct7_7_BITS_6_TO_2_8_EQ_0b10_9_AND_ra_ETC___d364,
rg_lrsc_pa_8_EQ_rg_addr_9___d99,
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d139,
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d170,
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d180,
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d182,
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d185,
rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d178,
rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d391,
rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d528,
rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d562,
rg_state_5_EQ_12_50_AND_rg_op_4_EQ_0_5_OR_rg_o_ETC___d652;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method server_reset_request_put
assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get =
!f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get =
!f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// action method req
assign CAN_FIRE_req = 1'd1 ;
assign WILL_FIRE_req = EN_req ;
// value method valid
assign valid = dw_valid$whas ;
// value method addr
assign addr = rg_addr ;
// value method word64
always@(MUX_dw_output_ld_val$wset_1__SEL_1 or
ld_val__h30504 or
MUX_dw_output_ld_val$wset_1__SEL_2 or
new_ld_val__h32710 or
MUX_dw_output_ld_val$wset_1__SEL_3 or
MUX_dw_output_ld_val$wset_1__VAL_3 or
MUX_dw_output_ld_val$wset_1__SEL_4 or rg_ld_val)
begin
case (1'b1) // synopsys parallel_case
MUX_dw_output_ld_val$wset_1__SEL_1: word64 = ld_val__h30504;
MUX_dw_output_ld_val$wset_1__SEL_2: word64 = new_ld_val__h32710;
MUX_dw_output_ld_val$wset_1__SEL_3:
word64 = MUX_dw_output_ld_val$wset_1__VAL_3;
MUX_dw_output_ld_val$wset_1__SEL_4: word64 = rg_ld_val;
default: word64 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
// value method st_amo_val
assign st_amo_val =
MUX_dw_output_ld_val$wset_1__SEL_3 ? 64'd0 : rg_st_amo_val ;
// value method exc
assign exc = rg_state == 4'd4 ;
// value method exc_code
assign exc_code = rg_exc_code ;
// action method server_flush_request_put
assign RDY_server_flush_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_server_flush_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_server_flush_request_put = EN_server_flush_request_put ;
// action method server_flush_response_get
assign RDY_server_flush_response_get =
f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_flush_response_get =
f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_flush_response_get = EN_server_flush_response_get ;
// action method tlb_flush
assign RDY_tlb_flush = 1'd1 ;
assign CAN_FIRE_tlb_flush = 1'd1 ;
assign WILL_FIRE_tlb_flush = EN_tlb_flush ;
// value method mem_master_m_awvalid
assign mem_master_awvalid = master_xactor_f_wr_addr$EMPTY_N ;
// value method mem_master_m_awid
assign mem_master_awid = master_xactor_f_wr_addr$D_OUT[96:93] ;
// value method mem_master_m_awaddr
assign mem_master_awaddr = master_xactor_f_wr_addr$D_OUT[92:29] ;
// value method mem_master_m_awlen
assign mem_master_awlen = master_xactor_f_wr_addr$D_OUT[28:21] ;
// value method mem_master_m_awsize
assign mem_master_awsize = master_xactor_f_wr_addr$D_OUT[20:18] ;
// value method mem_master_m_awburst
assign mem_master_awburst = master_xactor_f_wr_addr$D_OUT[17:16] ;
// value method mem_master_m_awlock
assign mem_master_awlock = master_xactor_f_wr_addr$D_OUT[15] ;
// value method mem_master_m_awcache
assign mem_master_awcache = master_xactor_f_wr_addr$D_OUT[14:11] ;
// value method mem_master_m_awprot
assign mem_master_awprot = master_xactor_f_wr_addr$D_OUT[10:8] ;
// value method mem_master_m_awqos
assign mem_master_awqos = master_xactor_f_wr_addr$D_OUT[7:4] ;
// value method mem_master_m_awregion
assign mem_master_awregion = master_xactor_f_wr_addr$D_OUT[3:0] ;
// action method mem_master_m_awready
assign CAN_FIRE_mem_master_m_awready = 1'd1 ;
assign WILL_FIRE_mem_master_m_awready = 1'd1 ;
// value method mem_master_m_wvalid
assign mem_master_wvalid = master_xactor_f_wr_data$EMPTY_N ;
// value method mem_master_m_wdata
assign mem_master_wdata = master_xactor_f_wr_data$D_OUT[72:9] ;
// value method mem_master_m_wstrb
assign mem_master_wstrb = master_xactor_f_wr_data$D_OUT[8:1] ;
// value method mem_master_m_wlast
assign mem_master_wlast = master_xactor_f_wr_data$D_OUT[0] ;
// action method mem_master_m_wready
assign CAN_FIRE_mem_master_m_wready = 1'd1 ;
assign WILL_FIRE_mem_master_m_wready = 1'd1 ;
// action method mem_master_m_bvalid
assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ;
// value method mem_master_m_bready
assign mem_master_bready = master_xactor_f_wr_resp$FULL_N ;
// value method mem_master_m_arvalid
assign mem_master_arvalid = master_xactor_f_rd_addr$EMPTY_N ;
// value method mem_master_m_arid
assign mem_master_arid = master_xactor_f_rd_addr$D_OUT[96:93] ;
// value method mem_master_m_araddr
assign mem_master_araddr = master_xactor_f_rd_addr$D_OUT[92:29] ;
// value method mem_master_m_arlen
assign mem_master_arlen = master_xactor_f_rd_addr$D_OUT[28:21] ;
// value method mem_master_m_arsize
assign mem_master_arsize = master_xactor_f_rd_addr$D_OUT[20:18] ;
// value method mem_master_m_arburst
assign mem_master_arburst = master_xactor_f_rd_addr$D_OUT[17:16] ;
// value method mem_master_m_arlock
assign mem_master_arlock = master_xactor_f_rd_addr$D_OUT[15] ;
// value method mem_master_m_arcache
assign mem_master_arcache = master_xactor_f_rd_addr$D_OUT[14:11] ;
// value method mem_master_m_arprot
assign mem_master_arprot = master_xactor_f_rd_addr$D_OUT[10:8] ;
// value method mem_master_m_arqos
assign mem_master_arqos = master_xactor_f_rd_addr$D_OUT[7:4] ;
// value method mem_master_m_arregion
assign mem_master_arregion = master_xactor_f_rd_addr$D_OUT[3:0] ;
// action method mem_master_m_arready
assign CAN_FIRE_mem_master_m_arready = 1'd1 ;
assign WILL_FIRE_mem_master_m_arready = 1'd1 ;
// action method mem_master_m_rvalid
assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ;
// value method mem_master_m_rready
assign mem_master_rready = master_xactor_f_rd_data$FULL_N ;
// submodule f_fabric_write_reqs
FIFO2 #(.width(32'd99), .guarded(32'd1)) f_fabric_write_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_fabric_write_reqs$D_IN),
.ENQ(f_fabric_write_reqs$ENQ),
.DEQ(f_fabric_write_reqs$DEQ),
.CLR(f_fabric_write_reqs$CLR),
.D_OUT(f_fabric_write_reqs$D_OUT),
.FULL_N(f_fabric_write_reqs$FULL_N),
.EMPTY_N(f_fabric_write_reqs$EMPTY_N));
// submodule f_reset_reqs
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_reqs$D_IN),
.ENQ(f_reset_reqs$ENQ),
.DEQ(f_reset_reqs$DEQ),
.CLR(f_reset_reqs$CLR),
.D_OUT(f_reset_reqs$D_OUT),
.FULL_N(f_reset_reqs$FULL_N),
.EMPTY_N(f_reset_reqs$EMPTY_N));
// submodule f_reset_rsps
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_rsps$D_IN),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.D_OUT(f_reset_rsps$D_OUT),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule master_xactor_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) master_xactor_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_rd_addr$D_IN),
.ENQ(master_xactor_f_rd_addr$ENQ),
.DEQ(master_xactor_f_rd_addr$DEQ),
.CLR(master_xactor_f_rd_addr$CLR),
.D_OUT(master_xactor_f_rd_addr$D_OUT),
.FULL_N(master_xactor_f_rd_addr$FULL_N),
.EMPTY_N(master_xactor_f_rd_addr$EMPTY_N));
// submodule master_xactor_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) master_xactor_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_rd_data$D_IN),
.ENQ(master_xactor_f_rd_data$ENQ),
.DEQ(master_xactor_f_rd_data$DEQ),
.CLR(master_xactor_f_rd_data$CLR),
.D_OUT(master_xactor_f_rd_data$D_OUT),
.FULL_N(master_xactor_f_rd_data$FULL_N),
.EMPTY_N(master_xactor_f_rd_data$EMPTY_N));
// submodule master_xactor_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) master_xactor_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_addr$D_IN),
.ENQ(master_xactor_f_wr_addr$ENQ),
.DEQ(master_xactor_f_wr_addr$DEQ),
.CLR(master_xactor_f_wr_addr$CLR),
.D_OUT(master_xactor_f_wr_addr$D_OUT),
.FULL_N(master_xactor_f_wr_addr$FULL_N),
.EMPTY_N(master_xactor_f_wr_addr$EMPTY_N));
// submodule master_xactor_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) master_xactor_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_data$D_IN),
.ENQ(master_xactor_f_wr_data$ENQ),
.DEQ(master_xactor_f_wr_data$DEQ),
.CLR(master_xactor_f_wr_data$CLR),
.D_OUT(master_xactor_f_wr_data$D_OUT),
.FULL_N(master_xactor_f_wr_data$FULL_N),
.EMPTY_N(master_xactor_f_wr_data$EMPTY_N));
// submodule master_xactor_f_wr_resp
FIFO2 #(.width(32'd6), .guarded(32'd1)) master_xactor_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_resp$D_IN),
.ENQ(master_xactor_f_wr_resp$ENQ),
.DEQ(master_xactor_f_wr_resp$DEQ),
.CLR(master_xactor_f_wr_resp$CLR),
.D_OUT(master_xactor_f_wr_resp$D_OUT),
.FULL_N(master_xactor_f_wr_resp$FULL_N),
.EMPTY_N(master_xactor_f_wr_resp$EMPTY_N));
// submodule ram_state_and_ctag_cset
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd7),
.DATA_WIDTH(32'd46),
.MEMSIZE(8'd128)) ram_state_and_ctag_cset(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(ram_state_and_ctag_cset$ADDRA),
.ADDRB(ram_state_and_ctag_cset$ADDRB),
.DIA(ram_state_and_ctag_cset$DIA),
.DIB(ram_state_and_ctag_cset$DIB),
.WEA(ram_state_and_ctag_cset$WEA),
.WEB(ram_state_and_ctag_cset$WEB),
.ENA(ram_state_and_ctag_cset$ENA),
.ENB(ram_state_and_ctag_cset$ENB),
.DOA(),
.DOB(ram_state_and_ctag_cset$DOB));
// submodule ram_word64_set
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd9),
.DATA_WIDTH(32'd128),
.MEMSIZE(10'd512)) ram_word64_set(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(ram_word64_set$ADDRA),
.ADDRB(ram_word64_set$ADDRB),
.DIA(ram_word64_set$DIA),
.DIB(ram_word64_set$DIB),
.WEA(ram_word64_set$WEA),
.WEB(ram_word64_set$WEB),
.ENA(ram_word64_set$ENA),
.ENB(ram_word64_set$ENB),
.DOA(),
.DOB(ram_word64_set$DOB));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(),
.m_plic_addr_base(),
.m_plic_addr_size(),
.m_plic_addr_lim(),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(soc_map$m_is_mem_addr),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// rule RL_rl_fabric_send_write_req
assign CAN_FIRE_RL_rl_fabric_send_write_req =
ctr_wr_rsps_pending_crg != 4'd15 &&
f_fabric_write_reqs$EMPTY_N &&
master_xactor_f_wr_addr$FULL_N &&
master_xactor_f_wr_data$FULL_N ;
assign WILL_FIRE_RL_rl_fabric_send_write_req =
CAN_FIRE_RL_rl_fabric_send_write_req ;
// rule RL_rl_reset
assign CAN_FIRE_RL_rl_reset =
(rg_cset_in_cache != 7'd127 ||
f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N) &&
rg_state == 4'd1 ;
assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ;
// rule RL_rl_probe_and_immed_rsp
assign CAN_FIRE_RL_rl_probe_and_immed_rsp =
dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_0__ETC___d124 &&
rg_state == 4'd3 ;
assign WILL_FIRE_RL_rl_probe_and_immed_rsp =
CAN_FIRE_RL_rl_probe_and_immed_rsp &&
!WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_start_cache_refill
assign CAN_FIRE_RL_rl_start_cache_refill =
master_xactor_f_rd_addr$FULL_N && rg_state == 4'd8 &&
b__h26623 == 4'd0 ;
assign WILL_FIRE_RL_rl_start_cache_refill =
CAN_FIRE_RL_rl_start_cache_refill &&
!WILL_FIRE_RL_rl_start_reset &&
!EN_req ;
// rule RL_rl_cache_refill_rsps_loop
assign CAN_FIRE_RL_rl_cache_refill_rsps_loop =
master_xactor_f_rd_data$EMPTY_N && rg_state == 4'd9 ;
assign WILL_FIRE_RL_rl_cache_refill_rsps_loop =
CAN_FIRE_RL_rl_cache_refill_rsps_loop &&
!WILL_FIRE_RL_rl_start_reset &&
!EN_req ;
// rule RL_rl_rereq
assign CAN_FIRE_RL_rl_rereq = rg_state == 4'd10 ;
assign WILL_FIRE_RL_rl_rereq =
CAN_FIRE_RL_rl_rereq && !WILL_FIRE_RL_rl_start_reset && !EN_req ;
// rule RL_rl_ST_AMO_response
assign CAN_FIRE_RL_rl_ST_AMO_response = rg_state == 4'd11 ;
assign WILL_FIRE_RL_rl_ST_AMO_response = CAN_FIRE_RL_rl_ST_AMO_response ;
// rule RL_rl_io_read_req
assign CAN_FIRE_RL_rl_io_read_req =
master_xactor_f_rd_addr$FULL_N &&
rg_state_5_EQ_12_50_AND_rg_op_4_EQ_0_5_OR_rg_o_ETC___d652 ;
assign WILL_FIRE_RL_rl_io_read_req =
CAN_FIRE_RL_rl_io_read_req && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_io_read_rsp
assign CAN_FIRE_RL_rl_io_read_rsp =
master_xactor_f_rd_data$EMPTY_N && rg_state == 4'd13 ;
assign WILL_FIRE_RL_rl_io_read_rsp =
CAN_FIRE_RL_rl_io_read_rsp && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_maintain_io_read_rsp
assign CAN_FIRE_RL_rl_maintain_io_read_rsp = rg_state == 4'd14 ;
assign WILL_FIRE_RL_rl_maintain_io_read_rsp =
CAN_FIRE_RL_rl_maintain_io_read_rsp ;
// rule RL_rl_io_write_req
assign CAN_FIRE_RL_rl_io_write_req =
f_fabric_write_reqs$FULL_N && rg_state == 4'd12 &&
rg_op == 2'd1 ;
assign WILL_FIRE_RL_rl_io_write_req =
CAN_FIRE_RL_rl_io_write_req && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_io_AMO_SC_req
assign CAN_FIRE_RL_rl_io_AMO_SC_req =
rg_state == 4'd12 && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 ;
assign WILL_FIRE_RL_rl_io_AMO_SC_req =
CAN_FIRE_RL_rl_io_AMO_SC_req && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_io_AMO_op_req
assign CAN_FIRE_RL_rl_io_AMO_op_req =
master_xactor_f_rd_addr$FULL_N && rg_state == 4'd12 &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] != 5'b00010 &&
rg_amo_funct7[6:2] != 5'b00011 ;
assign WILL_FIRE_RL_rl_io_AMO_op_req =
CAN_FIRE_RL_rl_io_AMO_op_req && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_io_AMO_read_rsp
assign CAN_FIRE_RL_rl_io_AMO_read_rsp =
master_xactor_f_rd_data$EMPTY_N &&
(master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
f_fabric_write_reqs$FULL_N) &&
rg_state == 4'd15 ;
assign WILL_FIRE_RL_rl_io_AMO_read_rsp = MUX_rg_state$write_1__SEL_3 ;
// rule RL_rl_discard_write_rsp
assign CAN_FIRE_RL_rl_discard_write_rsp =
b__h26623 != 4'd0 && master_xactor_f_wr_resp$EMPTY_N ;
assign WILL_FIRE_RL_rl_discard_write_rsp =
CAN_FIRE_RL_rl_discard_write_rsp ;
// rule RL_rl_drive_exception_rsp
assign CAN_FIRE_RL_rl_drive_exception_rsp = rg_state == 4'd4 ;
assign WILL_FIRE_RL_rl_drive_exception_rsp = rg_state == 4'd4 ;
// rule RL_rl_start_reset
assign CAN_FIRE_RL_rl_start_reset = MUX_rg_state$write_1__SEL_2 ;
assign WILL_FIRE_RL_rl_start_reset = MUX_rg_state$write_1__SEL_2 ;
// inputs to muxes for submodule ports
assign MUX_dw_output_ld_val$wset_1__SEL_1 =
WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
assign MUX_dw_output_ld_val$wset_1__SEL_2 =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
assign MUX_dw_output_ld_val$wset_1__SEL_3 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d185 ;
assign MUX_dw_output_ld_val$wset_1__SEL_4 =
WILL_FIRE_RL_rl_maintain_io_read_rsp ||
WILL_FIRE_RL_rl_ST_AMO_response ;
assign MUX_f_fabric_write_reqs$enq_1__SEL_2 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d530 ;
assign MUX_master_xactor_f_rd_addr$enq_1__SEL_1 =
WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ;
assign MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[1:0] == 2'd0 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
assign MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 =
EN_req &&
req_f3_BITS_1_TO_0_36_EQ_0b0_37_OR_req_f3_BITS_ETC___d966 ;
assign MUX_ram_word64_set$a_put_1__SEL_1 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
assign MUX_ram_word64_set$b_put_1__SEL_2 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[1:0] != 2'd3 ;
assign MUX_rg_error_during_refill$write_1__SEL_1 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
assign MUX_rg_exc_code$write_1__SEL_1 =
EN_req &&
NOT_req_f3_BITS_1_TO_0_36_EQ_0b0_37_38_AND_NOT_ETC___d957 ;
assign MUX_rg_exc_code$write_1__SEL_2 =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
assign MUX_rg_exc_code$write_1__SEL_3 =
WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
assign MUX_rg_ld_val$write_1__SEL_2 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d382 ;
assign MUX_rg_lrsc_valid$write_1__SEL_2 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d180 ;
assign MUX_rg_state$write_1__SEL_2 =
f_reset_reqs$EMPTY_N && rg_state != 4'd1 ;
assign MUX_rg_state$write_1__SEL_3 =
CAN_FIRE_RL_rl_io_AMO_read_rsp && !WILL_FIRE_RL_rl_start_reset ;
assign MUX_rg_state$write_1__SEL_10 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[1:0] == 2'd3 ;
assign MUX_rg_state$write_1__SEL_12 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(dmem_not_imem && !soc_map$m_is_mem_addr ||
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d139 ||
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d149) ;
assign MUX_rg_state$write_1__SEL_13 =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 ;
assign MUX_dw_output_ld_val$wset_1__VAL_3 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
new_value__h6012 :
new_value__h22441 ;
assign MUX_f_fabric_write_reqs$enq_1__VAL_1 = { rg_f3, rg_pa, x__h32739 } ;
assign MUX_f_fabric_write_reqs$enq_1__VAL_2 =
{ rg_f3,
rg_addr,
IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d532 } ;
assign MUX_f_fabric_write_reqs$enq_1__VAL_3 =
{ rg_f3, rg_pa, rg_st_amo_val } ;
assign MUX_master_xactor_f_rd_addr$enq_1__VAL_1 =
{ 4'd0, fabric_addr__h32167, 8'd0, value__h32296, 18'd65536 } ;
assign MUX_master_xactor_f_rd_addr$enq_1__VAL_2 =
{ 4'd0, cline_fabric_addr__h26722, 29'd7143424 } ;
assign MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 =
{ rg_victim_way || ram_state_and_ctag_cset$DOB[45],
rg_victim_way ?
n_ctag__h27950 :
ram_state_and_ctag_cset$DOB[44:23],
!rg_victim_way || ram_state_and_ctag_cset$DOB[22],
rg_victim_way ?
ram_state_and_ctag_cset$DOB[21:0] :
n_ctag__h27950 } ;
assign MUX_ram_word64_set$a_put_3__VAL_1 =
rg_victim_way ?
{ master_xactor_f_rd_data$D_OUT[66:3],
ram_word64_set$DOB[63:0] } :
{ ram_word64_set$DOB[127:64],
master_xactor_f_rd_data$D_OUT[66:3] } ;
assign MUX_ram_word64_set$a_put_3__VAL_2 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
{ IF_ram_state_and_ctag_cset_b_read__05_BIT_45_1_ETC___d447,
IF_NOT_ram_state_and_ctag_cset_b_read__05_BIT__ETC___d448 } :
{ IF_ram_state_and_ctag_cset_b_read__05_BIT_45_1_ETC___d524,
IF_NOT_ram_state_and_ctag_cset_b_read__05_BIT__ETC___d525 } ;
assign MUX_ram_word64_set$b_put_2__VAL_2 = rg_word64_set_in_cache + 9'd1 ;
assign MUX_ram_word64_set$b_put_2__VAL_4 = { rg_addr[11:5], 2'd0 } ;
assign MUX_rg_cset_in_cache$write_1__VAL_1 = rg_cset_in_cache + 7'd1 ;
assign MUX_rg_exc_code$write_1__VAL_1 = (req_op == 2'd0) ? 4'd4 : 4'd6 ;
assign MUX_rg_ld_val$write_1__VAL_2 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
x__h20022 :
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 ;
assign MUX_rg_state$write_1__VAL_1 =
NOT_req_f3_BITS_1_TO_0_36_EQ_0b0_37_38_AND_NOT_ETC___d957 ?
4'd4 :
4'd3 ;
assign MUX_rg_state$write_1__VAL_3 =
(master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ? 4'd14 : 4'd4 ;
assign MUX_rg_state$write_1__VAL_10 =
(master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
rg_error_during_refill) ?
4'd4 :
4'd10 ;
assign MUX_rg_state$write_1__VAL_12 =
(dmem_not_imem && !soc_map$m_is_mem_addr) ?
4'd12 :
IF_rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d154 ;
// inlined wires
assign dw_valid$whas =
(WILL_FIRE_RL_rl_io_AMO_read_rsp ||
WILL_FIRE_RL_rl_io_read_rsp) &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d185 ||
WILL_FIRE_RL_rl_drive_exception_rsp ||
WILL_FIRE_RL_rl_maintain_io_read_rsp ||
WILL_FIRE_RL_rl_ST_AMO_response ;
assign ctr_wr_rsps_pending_crg$port0__write_1 =
ctr_wr_rsps_pending_crg + 4'd1 ;
assign ctr_wr_rsps_pending_crg$port1__write_1 = b__h26623 - 4'd1 ;
assign ctr_wr_rsps_pending_crg$port2__read =
CAN_FIRE_RL_rl_discard_write_rsp ?
ctr_wr_rsps_pending_crg$port1__write_1 :
b__h26623 ;
assign ctr_wr_rsps_pending_crg$EN_port2__write =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
assign ctr_wr_rsps_pending_crg$port3__read =
ctr_wr_rsps_pending_crg$EN_port2__write ?
4'd0 :
ctr_wr_rsps_pending_crg$port2__read ;
// register cfg_verbosity
assign cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign cfg_verbosity$EN = EN_set_verbosity ;
// register ctr_wr_rsps_pending_crg
assign ctr_wr_rsps_pending_crg$D_IN = ctr_wr_rsps_pending_crg$port3__read ;
assign ctr_wr_rsps_pending_crg$EN = 1'b1 ;
// register rg_addr
assign rg_addr$D_IN = req_addr ;
assign rg_addr$EN = EN_req ;
// register rg_amo_funct7
assign rg_amo_funct7$D_IN = req_amo_funct7 ;
assign rg_amo_funct7$EN = EN_req ;
// register rg_cset_in_cache
assign rg_cset_in_cache$D_IN =
WILL_FIRE_RL_rl_reset ?
MUX_rg_cset_in_cache$write_1__VAL_1 :
7'd0 ;
assign rg_cset_in_cache$EN =
WILL_FIRE_RL_rl_reset || WILL_FIRE_RL_rl_start_reset ;
// register rg_error_during_refill
assign rg_error_during_refill$D_IN =
MUX_rg_error_during_refill$write_1__SEL_1 ;
assign rg_error_during_refill$EN =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
WILL_FIRE_RL_rl_start_cache_refill ;
// register rg_exc_code
always@(MUX_rg_exc_code$write_1__SEL_1 or
MUX_rg_exc_code$write_1__VAL_1 or
MUX_rg_exc_code$write_1__SEL_2 or
MUX_rg_exc_code$write_1__SEL_3 or
MUX_rg_error_during_refill$write_1__SEL_1 or access_exc_code__h2374)
case (1'b1)
MUX_rg_exc_code$write_1__SEL_1:
rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_1;
MUX_rg_exc_code$write_1__SEL_2: rg_exc_code$D_IN = 4'd7;
MUX_rg_exc_code$write_1__SEL_3: rg_exc_code$D_IN = 4'd5;
MUX_rg_error_during_refill$write_1__SEL_1:
rg_exc_code$D_IN = access_exc_code__h2374;
default: rg_exc_code$D_IN = 4'b1010 /* unspecified value */ ;
endcase
assign rg_exc_code$EN =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
EN_req &&
NOT_req_f3_BITS_1_TO_0_36_EQ_0b0_37_38_AND_NOT_ETC___d957 ;
// register rg_f3
assign rg_f3$D_IN = req_f3 ;
assign rg_f3$EN = EN_req ;
// register rg_ld_val
always@(MUX_dw_output_ld_val$wset_1__SEL_2 or
new_ld_val__h32710 or
MUX_rg_ld_val$write_1__SEL_2 or
MUX_rg_ld_val$write_1__VAL_2 or
WILL_FIRE_RL_rl_io_read_rsp or
ld_val__h30504 or WILL_FIRE_RL_rl_io_AMO_SC_req)
begin
case (1'b1) // synopsys parallel_case
MUX_dw_output_ld_val$wset_1__SEL_2: rg_ld_val$D_IN = new_ld_val__h32710;
MUX_rg_ld_val$write_1__SEL_2:
rg_ld_val$D_IN = MUX_rg_ld_val$write_1__VAL_2;
WILL_FIRE_RL_rl_io_read_rsp: rg_ld_val$D_IN = ld_val__h30504;
WILL_FIRE_RL_rl_io_AMO_SC_req: rg_ld_val$D_IN = 64'd1;
default: rg_ld_val$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign rg_ld_val$EN =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d382 ||
WILL_FIRE_RL_rl_io_read_rsp ||
WILL_FIRE_RL_rl_io_AMO_SC_req ;
// register rg_lower_word32
assign rg_lower_word32$D_IN = 32'h0 ;
assign rg_lower_word32$EN = 1'b0 ;
// register rg_lower_word32_full
assign rg_lower_word32_full$D_IN = 1'd0 ;
assign rg_lower_word32_full$EN =
WILL_FIRE_RL_rl_start_cache_refill ||
WILL_FIRE_RL_rl_start_reset ;
// register rg_lrsc_pa
assign rg_lrsc_pa$D_IN = rg_addr ;
assign rg_lrsc_pa$EN =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op == 2'd2 &&
rg_amo_funct7_7_BITS_6_TO_2_8_EQ_0b10_9_AND_ra_ETC___d364 ;
// register rg_lrsc_valid
assign rg_lrsc_valid$D_IN =
MUX_rg_lrsc_valid$write_1__SEL_2 &&
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d182 ;
assign rg_lrsc_valid$EN =
WILL_FIRE_RL_rl_io_read_req && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d180 ||
WILL_FIRE_RL_rl_start_reset ;
// register rg_op
assign rg_op$D_IN = req_op ;
assign rg_op$EN = EN_req ;
// register rg_pa
assign rg_pa$D_IN = EN_req ? req_addr : rg_addr ;
assign rg_pa$EN = EN_req || WILL_FIRE_RL_rl_probe_and_immed_rsp ;
// register rg_pte_pa
assign rg_pte_pa$D_IN = 32'h0 ;
assign rg_pte_pa$EN = 1'b0 ;
// register rg_st_amo_val
assign rg_st_amo_val$D_IN = EN_req ? req_st_value : new_st_val__h23573 ;
assign rg_st_amo_val$EN =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d577 ||
EN_req ;
// register rg_state
always@(EN_req or
MUX_rg_state$write_1__VAL_1 or
WILL_FIRE_RL_rl_start_reset or
WILL_FIRE_RL_rl_io_AMO_read_rsp or
MUX_rg_state$write_1__VAL_3 or
WILL_FIRE_RL_rl_io_AMO_op_req or
WILL_FIRE_RL_rl_io_AMO_SC_req or
WILL_FIRE_RL_rl_io_write_req or
WILL_FIRE_RL_rl_io_read_rsp or
WILL_FIRE_RL_rl_io_read_req or
WILL_FIRE_RL_rl_rereq or
MUX_rg_state$write_1__SEL_10 or
MUX_rg_state$write_1__VAL_10 or
WILL_FIRE_RL_rl_start_cache_refill or
MUX_rg_state$write_1__SEL_12 or
MUX_rg_state$write_1__VAL_12 or MUX_rg_state$write_1__SEL_13)
case (1'b1)
EN_req: rg_state$D_IN = MUX_rg_state$write_1__VAL_1;
WILL_FIRE_RL_rl_start_reset: rg_state$D_IN = 4'd1;
WILL_FIRE_RL_rl_io_AMO_read_rsp:
rg_state$D_IN = MUX_rg_state$write_1__VAL_3;
WILL_FIRE_RL_rl_io_AMO_op_req: rg_state$D_IN = 4'd15;
WILL_FIRE_RL_rl_io_AMO_SC_req || WILL_FIRE_RL_rl_io_write_req:
rg_state$D_IN = 4'd11;
WILL_FIRE_RL_rl_io_read_rsp: rg_state$D_IN = MUX_rg_state$write_1__VAL_3;
WILL_FIRE_RL_rl_io_read_req: rg_state$D_IN = 4'd13;
WILL_FIRE_RL_rl_rereq: rg_state$D_IN = 4'd3;
MUX_rg_state$write_1__SEL_10:
rg_state$D_IN = MUX_rg_state$write_1__VAL_10;
WILL_FIRE_RL_rl_start_cache_refill: rg_state$D_IN = 4'd9;
MUX_rg_state$write_1__SEL_12:
rg_state$D_IN = MUX_rg_state$write_1__VAL_12;
MUX_rg_state$write_1__SEL_13: rg_state$D_IN = 4'd2;
default: rg_state$D_IN = 4'b1010 /* unspecified value */ ;
endcase
assign rg_state$EN =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 ||
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[1:0] == 2'd3 ||
MUX_rg_state$write_1__SEL_12 ||
WILL_FIRE_RL_rl_io_AMO_read_rsp ||
WILL_FIRE_RL_rl_io_read_rsp ||
EN_req ||
WILL_FIRE_RL_rl_start_reset ||
WILL_FIRE_RL_rl_rereq ||
WILL_FIRE_RL_rl_start_cache_refill ||
WILL_FIRE_RL_rl_io_AMO_SC_req ||
WILL_FIRE_RL_rl_io_write_req ||
WILL_FIRE_RL_rl_io_read_req ||
WILL_FIRE_RL_rl_io_AMO_op_req ;
// register rg_victim_way
assign rg_victim_way$D_IN = tmp__h26885[0] ;
assign rg_victim_way$EN = WILL_FIRE_RL_rl_start_cache_refill ;
// register rg_word64_set_in_cache
assign rg_word64_set_in_cache$D_IN =
MUX_ram_word64_set$b_put_1__SEL_2 ?
MUX_ram_word64_set$b_put_2__VAL_2 :
MUX_ram_word64_set$b_put_2__VAL_4 ;
assign rg_word64_set_in_cache$EN =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[1:0] != 2'd3 ||
WILL_FIRE_RL_rl_start_cache_refill ;
// submodule f_fabric_write_reqs
always@(MUX_dw_output_ld_val$wset_1__SEL_2 or
MUX_f_fabric_write_reqs$enq_1__VAL_1 or
MUX_f_fabric_write_reqs$enq_1__SEL_2 or
MUX_f_fabric_write_reqs$enq_1__VAL_2 or
WILL_FIRE_RL_rl_io_write_req or
MUX_f_fabric_write_reqs$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_dw_output_ld_val$wset_1__SEL_2:
f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_1;
MUX_f_fabric_write_reqs$enq_1__SEL_2:
f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_2;
WILL_FIRE_RL_rl_io_write_req:
f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_3;
default: f_fabric_write_reqs$D_IN =
99'h2AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign f_fabric_write_reqs$ENQ =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d530 ||
WILL_FIRE_RL_rl_io_write_req ;
assign f_fabric_write_reqs$DEQ = CAN_FIRE_RL_rl_fabric_send_write_req ;
assign f_fabric_write_reqs$CLR = 1'b0 ;
// submodule f_reset_reqs
assign f_reset_reqs$D_IN = !EN_server_reset_request_put ;
assign f_reset_reqs$ENQ =
EN_server_reset_request_put || EN_server_flush_request_put ;
assign f_reset_reqs$DEQ =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 ;
assign f_reset_reqs$CLR = 1'b0 ;
// submodule f_reset_rsps
assign f_reset_rsps$D_IN = f_reset_reqs$D_OUT ;
assign f_reset_rsps$ENQ =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 ;
assign f_reset_rsps$DEQ =
EN_server_flush_response_get || EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule master_xactor_f_rd_addr
assign master_xactor_f_rd_addr$D_IN =
MUX_master_xactor_f_rd_addr$enq_1__SEL_1 ?
MUX_master_xactor_f_rd_addr$enq_1__VAL_1 :
MUX_master_xactor_f_rd_addr$enq_1__VAL_2 ;
assign master_xactor_f_rd_addr$ENQ =
WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ||
WILL_FIRE_RL_rl_start_cache_refill ;
assign master_xactor_f_rd_addr$DEQ =
master_xactor_f_rd_addr$EMPTY_N && mem_master_arready ;
assign master_xactor_f_rd_addr$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule master_xactor_f_rd_data
assign master_xactor_f_rd_data$D_IN =
{ mem_master_rid,
mem_master_rdata,
mem_master_rresp,
mem_master_rlast } ;
assign master_xactor_f_rd_data$ENQ =
mem_master_rvalid && master_xactor_f_rd_data$FULL_N ;
assign master_xactor_f_rd_data$DEQ =
WILL_FIRE_RL_rl_io_AMO_read_rsp || WILL_FIRE_RL_rl_io_read_rsp ||
WILL_FIRE_RL_rl_cache_refill_rsps_loop ;
assign master_xactor_f_rd_data$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule master_xactor_f_wr_addr
assign master_xactor_f_wr_addr$D_IN =
{ 4'd0,
mem_req_wr_addr_awaddr__h2592,
8'd0,
x__h2639,
18'd65536 } ;
assign master_xactor_f_wr_addr$ENQ = CAN_FIRE_RL_rl_fabric_send_write_req ;
assign master_xactor_f_wr_addr$DEQ =
master_xactor_f_wr_addr$EMPTY_N && mem_master_awready ;
assign master_xactor_f_wr_addr$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule master_xactor_f_wr_data
assign master_xactor_f_wr_data$D_IN =
{ mem_req_wr_data_wdata__h2818,
mem_req_wr_data_wstrb__h2819,
1'd1 } ;
assign master_xactor_f_wr_data$ENQ = CAN_FIRE_RL_rl_fabric_send_write_req ;
assign master_xactor_f_wr_data$DEQ =
master_xactor_f_wr_data$EMPTY_N && mem_master_wready ;
assign master_xactor_f_wr_data$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule master_xactor_f_wr_resp
assign master_xactor_f_wr_resp$D_IN = { mem_master_bid, mem_master_bresp } ;
assign master_xactor_f_wr_resp$ENQ =
mem_master_bvalid && master_xactor_f_wr_resp$FULL_N ;
assign master_xactor_f_wr_resp$DEQ = CAN_FIRE_RL_rl_discard_write_rsp ;
assign master_xactor_f_wr_resp$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule ram_state_and_ctag_cset
assign ram_state_and_ctag_cset$ADDRA =
MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 ?
rg_addr[11:5] :
rg_cset_in_cache ;
assign ram_state_and_ctag_cset$ADDRB =
MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ?
req_addr[11:5] :
rg_addr[11:5] ;
assign ram_state_and_ctag_cset$DIA =
MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 ?
MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 :
46'h1555552AAAAA ;
assign ram_state_and_ctag_cset$DIB =
MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ?
46'h2AAAAAAAAAAA /* unspecified value */ :
46'h2AAAAAAAAAAA /* unspecified value */ ;
assign ram_state_and_ctag_cset$WEA = 1'd1 ;
assign ram_state_and_ctag_cset$WEB = 1'd0 ;
assign ram_state_and_ctag_cset$ENA =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[1:0] == 2'd0 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_reset ;
assign ram_state_and_ctag_cset$ENB =
EN_req &&
req_f3_BITS_1_TO_0_36_EQ_0b0_37_OR_req_f3_BITS_ETC___d966 ||
WILL_FIRE_RL_rl_rereq ;
// submodule ram_word64_set
assign ram_word64_set$ADDRA =
MUX_ram_word64_set$a_put_1__SEL_1 ?
rg_word64_set_in_cache :
rg_addr[11:3] ;
always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or
req_addr or
MUX_ram_word64_set$b_put_1__SEL_2 or
MUX_ram_word64_set$b_put_2__VAL_2 or
WILL_FIRE_RL_rl_rereq or
rg_addr or
WILL_FIRE_RL_rl_start_cache_refill or
MUX_ram_word64_set$b_put_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_ram_state_and_ctag_cset$b_put_1__SEL_1:
ram_word64_set$ADDRB = req_addr[11:3];
MUX_ram_word64_set$b_put_1__SEL_2:
ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_2;
WILL_FIRE_RL_rl_rereq: ram_word64_set$ADDRB = rg_addr[11:3];
WILL_FIRE_RL_rl_start_cache_refill:
ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_4;
default: ram_word64_set$ADDRB = 9'b010101010 /* unspecified value */ ;
endcase
end
assign ram_word64_set$DIA =
MUX_ram_word64_set$a_put_1__SEL_1 ?
MUX_ram_word64_set$a_put_3__VAL_1 :
MUX_ram_word64_set$a_put_3__VAL_2 ;
always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or
MUX_ram_word64_set$b_put_1__SEL_2 or
WILL_FIRE_RL_rl_rereq or WILL_FIRE_RL_rl_start_cache_refill)
begin
case (1'b1) // synopsys parallel_case
MUX_ram_state_and_ctag_cset$b_put_1__SEL_1:
ram_word64_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
MUX_ram_word64_set$b_put_1__SEL_2:
ram_word64_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
WILL_FIRE_RL_rl_rereq:
ram_word64_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
WILL_FIRE_RL_rl_start_cache_refill:
ram_word64_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
default: ram_word64_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign ram_word64_set$WEA = 1'd1 ;
assign ram_word64_set$WEB = 1'd0 ;
assign ram_word64_set$ENA =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d393 ;
assign ram_word64_set$ENB =
EN_req &&
req_f3_BITS_1_TO_0_36_EQ_0b0_37_OR_req_f3_BITS_ETC___d966 ||
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[1:0] != 2'd3 ||
WILL_FIRE_RL_rl_rereq ||
WILL_FIRE_RL_rl_start_cache_refill ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = { 32'd0, rg_addr } ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
assign IF_NOT_ram_state_and_ctag_cset_b_read__05_BIT__ETC___d152 =
((!ram_state_and_ctag_cset$DOB[22] ||
!ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111) &&
(!ram_state_and_ctag_cset$DOB[45] ||
!ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117)) ?
4'd8 :
4'd11 ;
assign IF_NOT_ram_state_and_ctag_cset_b_read__05_BIT__ETC___d448 =
(!ram_state_and_ctag_cset$DOB[45] ||
!ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) ?
n__h20801 :
ram_word64_set$DOB[63:0] ;
assign IF_NOT_ram_state_and_ctag_cset_b_read__05_BIT__ETC___d525 =
(!ram_state_and_ctag_cset$DOB[45] ||
!ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) ?
n__h23737 :
ram_word64_set$DOB[63:0] ;
assign IF_ram_state_and_ctag_cset_b_read__05_BIT_45_1_ETC___d447 =
(ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) ?
n__h20801 :
ram_word64_set$DOB[127:64] ;
assign IF_ram_state_and_ctag_cset_b_read__05_BIT_45_1_ETC___d524 =
(ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) ?
n__h23737 :
ram_word64_set$DOB[127:64] ;
assign IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_1_E_ETC___d355 =
(rg_addr[2:0] == 3'h0) ? 64'd1 : 64'd0 ;
assign IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_IF__ETC___d851 =
(rg_addr[2:0] == 3'h0) ? ld_val__h30504 : 64'd0 ;
assign IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_ram_ETC___d340 =
(rg_addr[2:0] == 3'h0) ? word64__h5847 : 64'd0 ;
assign IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC__q31 =
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347[31:0] ;
assign IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_rg_st_amo_val_ETC___d455 =
(rg_f3 == 3'b010) ?
{ {32{rg_st_amo_val_BITS_31_TO_0__q32[31]}},
rg_st_amo_val_BITS_31_TO_0__q32 } :
rg_st_amo_val ;
assign IF_rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d154 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
4'd8 :
IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d153 ;
assign IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d122 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
lrsc_result__h20012 ||
f_fabric_write_reqs$FULL_N :
NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d121 ;
assign IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d153 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
4'd11 :
IF_NOT_ram_state_and_ctag_cset_b_read__05_BIT__ETC___d152 ;
assign IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d532 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
rg_st_amo_val :
new_st_val__h23573 ;
assign NOT_cfg_verbosity_read__0_ULE_1_1___d42 = cfg_verbosity > 4'd1 ;
assign NOT_cfg_verbosity_read__0_ULE_2_99___d600 = cfg_verbosity > 4'd2 ;
assign NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d162 =
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
ram_state_and_ctag_cset$DOB[22] &&
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111 &&
ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117 ;
assign NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d361 =
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d359 ;
assign NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d369 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 &&
ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d359 ;
assign NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d372 =
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d370 ;
assign NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d378 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 &&
NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d375 ;
assign NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d382 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
(rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
NOT_rg_op_4_EQ_1_2_74_AND_ram_state_and_ctag_c_ETC___d379) ;
assign NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d393 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d391 ;
assign NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d535 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd1 &&
rg_addr_9_EQ_rg_lrsc_pa_8___d166 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 ;
assign NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d547 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 ;
assign NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d577 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
NOT_rg_op_4_EQ_1_2_74_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d390 ;
assign NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d121 =
(!ram_state_and_ctag_cset$DOB[22] ||
!ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111) &&
(!ram_state_and_ctag_cset$DOB[45] ||
!ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) ||
f_fabric_write_reqs$FULL_N ;
assign NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d168 =
(!ram_state_and_ctag_cset$DOB[22] ||
!ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111) &&
(!ram_state_and_ctag_cset$DOB[45] ||
!ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 &&
rg_addr_9_EQ_rg_lrsc_pa_8___d166 ;
assign NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d370 =
(!ram_state_and_ctag_cset$DOB[22] ||
!ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111) &&
(!ram_state_and_ctag_cset$DOB[45] ||
!ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 ;
assign NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d375 =
(!ram_state_and_ctag_cset$DOB[22] ||
!ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111) &&
(!ram_state_and_ctag_cset$DOB[45] ||
!ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) &&
rg_addr_9_EQ_rg_lrsc_pa_8___d166 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 ;
assign NOT_req_f3_BITS_1_TO_0_36_EQ_0b0_37_38_AND_NOT_ETC___d957 =
req_f3[1:0] != 2'b0 && (req_f3[1:0] != 2'b01 || req_addr[0]) &&
(req_f3[1:0] != 2'b10 || req_addr[1:0] != 2'b0) &&
(req_f3[1:0] != 2'b11 || req_addr[2:0] != 3'b0) ;
assign NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d149 =
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_9___d99) ;
assign NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d530 =
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
(rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d528 ||
NOT_rg_op_4_EQ_1_2_74_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d390) ;
assign NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d550 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d548 ;
assign NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d558 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d556 ;
assign NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d570 =
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d359 ;
assign NOT_rg_op_4_EQ_1_2_74_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d390 =
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
(ram_state_and_ctag_cset$DOB[22] &&
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111 ||
ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) ;
assign NOT_rg_op_4_EQ_1_2_74_AND_ram_state_and_ctag_c_ETC___d379 =
rg_op != 2'd1 &&
(ram_state_and_ctag_cset$DOB[22] &&
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111 ||
ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) ;
assign NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d388 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_9___d99) &&
(ram_state_and_ctag_cset$DOB[22] &&
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111 ||
ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) ;
assign NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d548 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_9___d99) &&
ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d359 ;
assign NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d552 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_9___d99) &&
NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d370 ;
assign NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d556 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_9___d99) &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 ;
assign _theResult___snd_fst__h2826 =
f_fabric_write_reqs$D_OUT[63:0] << shift_bits__h2606 ;
assign access_exc_code__h2374 =
dmem_not_imem ?
((rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
4'd5 :
4'd7) :
4'd1 ;
assign b__h26623 =
CAN_FIRE_RL_rl_fabric_send_write_req ?
ctr_wr_rsps_pending_crg$port0__write_1 :
ctr_wr_rsps_pending_crg ;
assign cline_addr__h26721 = { rg_pa[31:5], 5'd0 } ;
assign cline_fabric_addr__h26722 = { 32'd0, cline_addr__h26721 } ;
assign dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_0__ETC___d124 =
dmem_not_imem && !soc_map$m_is_mem_addr || rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ||
IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d122 ;
assign fabric_addr__h32167 = { 32'd0, rg_pa } ;
assign ld_val0504_BITS_15_TO_0__q37 = ld_val__h30504[15:0] ;
assign ld_val0504_BITS_15_TO_8__q39 = ld_val__h30504[15:8] ;
assign ld_val0504_BITS_23_TO_16__q40 = ld_val__h30504[23:16] ;
assign ld_val0504_BITS_31_TO_0__q38 = ld_val__h30504[31:0] ;
assign ld_val0504_BITS_31_TO_16__q41 = ld_val__h30504[31:16] ;
assign ld_val0504_BITS_31_TO_24__q42 = ld_val__h30504[31:24] ;
assign ld_val0504_BITS_39_TO_32__q43 = ld_val__h30504[39:32] ;
assign ld_val0504_BITS_47_TO_32__q44 = ld_val__h30504[47:32] ;
assign ld_val0504_BITS_47_TO_40__q46 = ld_val__h30504[47:40] ;
assign ld_val0504_BITS_55_TO_48__q47 = ld_val__h30504[55:48] ;
assign ld_val0504_BITS_63_TO_32__q45 = ld_val__h30504[63:32] ;
assign ld_val0504_BITS_63_TO_48__q48 = ld_val__h30504[63:48] ;
assign ld_val0504_BITS_63_TO_56__q49 = ld_val__h30504[63:56] ;
assign ld_val0504_BITS_7_TO_0__q36 = ld_val__h30504[7:0] ;
assign lrsc_result__h20012 =
!rg_lrsc_valid || !rg_lrsc_pa_8_EQ_rg_addr_9___d99 ;
assign master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1 =
master_xactor_f_rd_data$D_OUT[10:3] ;
assign master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4 =
master_xactor_f_rd_data$D_OUT[18:11] ;
assign master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2 =
master_xactor_f_rd_data$D_OUT[18:3] ;
assign master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q6 =
master_xactor_f_rd_data$D_OUT[26:19] ;
assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q7 =
master_xactor_f_rd_data$D_OUT[34:19] ;
assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q8 =
master_xactor_f_rd_data$D_OUT[34:27] ;
assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3 =
master_xactor_f_rd_data$D_OUT[34:3] ;
assign master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q5 =
master_xactor_f_rd_data$D_OUT[42:35] ;
assign master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9 =
master_xactor_f_rd_data$D_OUT[50:35] ;
assign master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11 =
master_xactor_f_rd_data$D_OUT[50:43] ;
assign master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12 =
master_xactor_f_rd_data$D_OUT[58:51] ;
assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10 =
master_xactor_f_rd_data$D_OUT[66:35] ;
assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13 =
master_xactor_f_rd_data$D_OUT[66:51] ;
assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14 =
master_xactor_f_rd_data$D_OUT[66:59] ;
assign mem_req_wr_addr_awaddr__h2592 =
{ 32'd0, f_fabric_write_reqs$D_OUT[95:64] } ;
assign n_ctag__h27950 = { 2'd0, rg_pa[31:12] } ;
assign new_st_val__h23573 =
(rg_f3 == 3'b010) ?
new_st_val__h23879 :
_theResult_____2__h23875 ;
assign new_st_val__h23879 = { 32'd0, _theResult_____2__h23875[31:0] } ;
assign new_st_val__h23970 =
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 +
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_rg_st_amo_val_ETC___d455 ;
assign new_st_val__h24950 = w1__h23867 ^ w2__h32750 ;
assign new_st_val__h24954 = w1__h23867 & w2__h32750 ;
assign new_st_val__h24958 = w1__h23867 | w2__h32750 ;
assign new_st_val__h24962 =
(w1__h23867 < w2__h32750) ? w1__h23867 : w2__h32750 ;
assign new_st_val__h24967 =
(w1__h23867 <= w2__h32750) ? w2__h32750 : w1__h23867 ;
assign new_st_val__h24973 =
((IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 ^
64'h8000000000000000) <
(IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_rg_st_amo_val_ETC___d455 ^
64'h8000000000000000)) ?
w1__h23867 :
w2__h32750 ;
assign new_st_val__h24978 =
((IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 ^
64'h8000000000000000) <=
(IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_rg_st_amo_val_ETC___d455 ^
64'h8000000000000000)) ?
w2__h32750 :
w1__h23867 ;
assign new_st_val__h32760 = { 32'd0, _theResult_____2__h32756[31:0] } ;
assign new_st_val__h32851 =
new_ld_val__h32710 +
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_rg_st_amo_val_ETC___d455 ;
assign new_st_val__h34711 = w1__h32748 ^ w2__h32750 ;
assign new_st_val__h34715 = w1__h32748 & w2__h32750 ;
assign new_st_val__h34719 = w1__h32748 | w2__h32750 ;
assign new_st_val__h34723 =
(w1__h32748 < w2__h32750) ? w1__h32748 : w2__h32750 ;
assign new_st_val__h34728 =
(w1__h32748 <= w2__h32750) ? w2__h32750 : w1__h32748 ;
assign new_st_val__h34734 =
((new_ld_val__h32710 ^ 64'h8000000000000000) <
(IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_rg_st_amo_val_ETC___d455 ^
64'h8000000000000000)) ?
w1__h32748 :
w2__h32750 ;
assign new_st_val__h34739 =
((new_ld_val__h32710 ^ 64'h8000000000000000) <=
(IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_rg_st_amo_val_ETC___d455 ^
64'h8000000000000000)) ?
w2__h32750 :
w1__h32748 ;
assign new_value__h22441 =
(rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
64'd1 :
CASE_rg_f3_0b0_IF_rg_addr_9_BITS_2_TO_0_31_EQ__ETC__q52 ;
assign new_value__h6012 =
(rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
word64__h5847 :
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347 ;
assign pa_ctag__h5533 = { 2'd0, rg_addr[31:12] } ;
assign ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111 =
ram_state_and_ctag_cset$DOB[21:0] == pa_ctag__h5533 ;
assign ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117 =
ram_state_and_ctag_cset$DOB[44:23] == pa_ctag__h5533 ;
assign ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d165 =
(ram_state_and_ctag_cset$DOB[22] &&
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111 ||
ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 ;
assign ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d176 =
(ram_state_and_ctag_cset$DOB[22] &&
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111 ||
ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) &&
rg_addr_9_EQ_rg_lrsc_pa_8___d166 ;
assign ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d359 =
(ram_state_and_ctag_cset$DOB[22] &&
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111 ||
ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 ;
assign ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d572 =
(ram_state_and_ctag_cset$DOB[22] &&
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111 ||
ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) &&
rg_addr_9_EQ_rg_lrsc_pa_8___d166 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 ;
assign req_f3_BITS_1_TO_0_36_EQ_0b0_37_OR_req_f3_BITS_ETC___d966 =
req_f3[1:0] == 2'b0 || req_f3[1:0] == 2'b01 && !req_addr[0] ||
req_f3[1:0] == 2'b10 && req_addr[1:0] == 2'b0 ||
req_f3[1:0] == 2'b11 && req_addr[2:0] == 3'b0 ;
assign result__h18723 =
{ {56{word64847_BITS_7_TO_0__q15[7]}},
word64847_BITS_7_TO_0__q15 } ;
assign result__h18751 =
{ {56{word64847_BITS_15_TO_8__q18[7]}},
word64847_BITS_15_TO_8__q18 } ;
assign result__h18779 =
{ {56{word64847_BITS_23_TO_16__q19[7]}},
word64847_BITS_23_TO_16__q19 } ;
assign result__h18807 =
{ {56{word64847_BITS_31_TO_24__q21[7]}},
word64847_BITS_31_TO_24__q21 } ;
assign result__h18835 =
{ {56{word64847_BITS_39_TO_32__q22[7]}},
word64847_BITS_39_TO_32__q22 } ;
assign result__h18863 =
{ {56{word64847_BITS_47_TO_40__q25[7]}},
word64847_BITS_47_TO_40__q25 } ;
assign result__h18891 =
{ {56{word64847_BITS_55_TO_48__q26[7]}},
word64847_BITS_55_TO_48__q26 } ;
assign result__h18919 =
{ {56{word64847_BITS_63_TO_56__q28[7]}},
word64847_BITS_63_TO_56__q28 } ;
assign result__h18964 = { 56'd0, word64__h5847[7:0] } ;
assign result__h18992 = { 56'd0, word64__h5847[15:8] } ;
assign result__h19020 = { 56'd0, word64__h5847[23:16] } ;
assign result__h19048 = { 56'd0, word64__h5847[31:24] } ;
assign result__h19076 = { 56'd0, word64__h5847[39:32] } ;
assign result__h19104 = { 56'd0, word64__h5847[47:40] } ;
assign result__h19132 = { 56'd0, word64__h5847[55:48] } ;
assign result__h19160 = { 56'd0, word64__h5847[63:56] } ;
assign result__h19205 =
{ {48{word64847_BITS_15_TO_0__q16[15]}},
word64847_BITS_15_TO_0__q16 } ;
assign result__h19233 =
{ {48{word64847_BITS_31_TO_16__q20[15]}},
word64847_BITS_31_TO_16__q20 } ;
assign result__h19261 =
{ {48{word64847_BITS_47_TO_32__q23[15]}},
word64847_BITS_47_TO_32__q23 } ;
assign result__h19289 =
{ {48{word64847_BITS_63_TO_48__q27[15]}},
word64847_BITS_63_TO_48__q27 } ;
assign result__h19330 = { 48'd0, word64__h5847[15:0] } ;
assign result__h19358 = { 48'd0, word64__h5847[31:16] } ;
assign result__h19386 = { 48'd0, word64__h5847[47:32] } ;
assign result__h19414 = { 48'd0, word64__h5847[63:48] } ;
assign result__h19455 =
{ {32{word64847_BITS_31_TO_0__q17[31]}},
word64847_BITS_31_TO_0__q17 } ;
assign result__h19483 =
{ {32{word64847_BITS_63_TO_32__q24[31]}},
word64847_BITS_63_TO_32__q24 } ;
assign result__h19522 = { 32'd0, word64__h5847[31:0] } ;
assign result__h19550 = { 32'd0, word64__h5847[63:32] } ;
assign result__h30564 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1[7]}},
master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1 } ;
assign result__h30594 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4[7]}},
master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4 } ;
assign result__h30621 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q6[7]}},
master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q6 } ;
assign result__h30648 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q8[7]}},
master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q8 } ;
assign result__h30675 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q5[7]}},
master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q5 } ;
assign result__h30702 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11[7]}},
master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11 } ;
assign result__h30729 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12[7]}},
master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12 } ;
assign result__h30756 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14[7]}},
master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14 } ;
assign result__h30800 = { 56'd0, master_xactor_f_rd_data$D_OUT[10:3] } ;
assign result__h30827 = { 56'd0, master_xactor_f_rd_data$D_OUT[18:11] } ;
assign result__h30854 = { 56'd0, master_xactor_f_rd_data$D_OUT[26:19] } ;
assign result__h30881 = { 56'd0, master_xactor_f_rd_data$D_OUT[34:27] } ;
assign result__h30908 = { 56'd0, master_xactor_f_rd_data$D_OUT[42:35] } ;
assign result__h30935 = { 56'd0, master_xactor_f_rd_data$D_OUT[50:43] } ;
assign result__h30962 = { 56'd0, master_xactor_f_rd_data$D_OUT[58:51] } ;
assign result__h30989 = { 56'd0, master_xactor_f_rd_data$D_OUT[66:59] } ;
assign result__h31033 =
{ {48{master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2[15]}},
master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2 } ;
assign result__h31060 =
{ {48{master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q7[15]}},
master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q7 } ;
assign result__h31087 =
{ {48{master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9[15]}},
master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9 } ;
assign result__h31114 =
{ {48{master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13[15]}},
master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13 } ;
assign result__h31154 = { 48'd0, master_xactor_f_rd_data$D_OUT[18:3] } ;
assign result__h31181 = { 48'd0, master_xactor_f_rd_data$D_OUT[34:19] } ;
assign result__h31208 = { 48'd0, master_xactor_f_rd_data$D_OUT[50:35] } ;
assign result__h31235 = { 48'd0, master_xactor_f_rd_data$D_OUT[66:51] } ;
assign result__h31275 =
{ {32{master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3[31]}},
master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3 } ;
assign result__h31302 =
{ {32{master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10[31]}},
master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10 } ;
assign result__h31340 = { 32'd0, master_xactor_f_rd_data$D_OUT[34:3] } ;
assign result__h31367 = { 32'd0, master_xactor_f_rd_data$D_OUT[66:35] } ;
assign result__h32939 =
{ {56{ld_val0504_BITS_7_TO_0__q36[7]}},
ld_val0504_BITS_7_TO_0__q36 } ;
assign result__h33847 =
{ {56{ld_val0504_BITS_15_TO_8__q39[7]}},
ld_val0504_BITS_15_TO_8__q39 } ;
assign result__h33875 =
{ {56{ld_val0504_BITS_23_TO_16__q40[7]}},
ld_val0504_BITS_23_TO_16__q40 } ;
assign result__h33903 =
{ {56{ld_val0504_BITS_31_TO_24__q42[7]}},
ld_val0504_BITS_31_TO_24__q42 } ;
assign result__h33931 =
{ {56{ld_val0504_BITS_39_TO_32__q43[7]}},
ld_val0504_BITS_39_TO_32__q43 } ;
assign result__h33959 =
{ {56{ld_val0504_BITS_47_TO_40__q46[7]}},
ld_val0504_BITS_47_TO_40__q46 } ;
assign result__h33987 =
{ {56{ld_val0504_BITS_55_TO_48__q47[7]}},
ld_val0504_BITS_55_TO_48__q47 } ;
assign result__h34015 =
{ {56{ld_val0504_BITS_63_TO_56__q49[7]}},
ld_val0504_BITS_63_TO_56__q49 } ;
assign result__h34060 = { 56'd0, ld_val__h30504[7:0] } ;
assign result__h34088 = { 56'd0, ld_val__h30504[15:8] } ;
assign result__h34116 = { 56'd0, ld_val__h30504[23:16] } ;
assign result__h34144 = { 56'd0, ld_val__h30504[31:24] } ;
assign result__h34172 = { 56'd0, ld_val__h30504[39:32] } ;
assign result__h34200 = { 56'd0, ld_val__h30504[47:40] } ;
assign result__h34228 = { 56'd0, ld_val__h30504[55:48] } ;
assign result__h34256 = { 56'd0, ld_val__h30504[63:56] } ;
assign result__h34301 =
{ {48{ld_val0504_BITS_15_TO_0__q37[15]}},
ld_val0504_BITS_15_TO_0__q37 } ;
assign result__h34329 =
{ {48{ld_val0504_BITS_31_TO_16__q41[15]}},
ld_val0504_BITS_31_TO_16__q41 } ;
assign result__h34357 =
{ {48{ld_val0504_BITS_47_TO_32__q44[15]}},
ld_val0504_BITS_47_TO_32__q44 } ;
assign result__h34385 =
{ {48{ld_val0504_BITS_63_TO_48__q48[15]}},
ld_val0504_BITS_63_TO_48__q48 } ;
assign result__h34426 = { 48'd0, ld_val__h30504[15:0] } ;
assign result__h34454 = { 48'd0, ld_val__h30504[31:16] } ;
assign result__h34482 = { 48'd0, ld_val__h30504[47:32] } ;
assign result__h34510 = { 48'd0, ld_val__h30504[63:48] } ;
assign result__h34551 =
{ {32{ld_val0504_BITS_31_TO_0__q38[31]}},
ld_val0504_BITS_31_TO_0__q38 } ;
assign result__h34579 =
{ {32{ld_val0504_BITS_63_TO_32__q45[31]}},
ld_val0504_BITS_63_TO_32__q45 } ;
assign result__h34618 = { 32'd0, ld_val__h30504[31:0] } ;
assign result__h34646 = { 32'd0, ld_val__h30504[63:32] } ;
assign rg_addr_9_EQ_rg_lrsc_pa_8___d166 = rg_addr == rg_lrsc_pa ;
assign rg_amo_funct7_7_BITS_6_TO_2_8_EQ_0b10_9_AND_ra_ETC___d364 =
rg_amo_funct7[6:2] == 5'b00010 &&
(ram_state_and_ctag_cset$DOB[22] &&
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111 ||
ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) ;
assign rg_lrsc_pa_8_EQ_rg_addr_9___d99 = rg_lrsc_pa == rg_addr ;
assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d139 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
(!ram_state_and_ctag_cset$DOB[22] ||
!ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111) &&
(!ram_state_and_ctag_cset$DOB[45] ||
!ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) ;
assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d170 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
(ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d165 ||
NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d168) ;
assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d180 =
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d170 ||
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d178 ;
assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d182 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
(ram_state_and_ctag_cset$DOB[22] &&
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111 ||
ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117) ;
assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d185 =
rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d182 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
lrsc_result__h20012 ;
assign rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d178 =
rg_op == 2'd1 && rg_addr_9_EQ_rg_lrsc_pa_8___d166 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d176 ;
assign rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d391 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d388 ||
NOT_rg_op_4_EQ_1_2_74_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d390 ;
assign rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d528 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_9___d99) ;
assign rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d562 =
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
lrsc_result__h20012 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 ;
assign rg_st_amo_val_BITS_31_TO_0__q32 = rg_st_amo_val[31:0] ;
assign rg_state_5_EQ_12_50_AND_rg_op_4_EQ_0_5_OR_rg_o_ETC___d652 =
rg_state == 4'd12 &&
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
b__h26623 == 4'd0 ;
assign shift_bits__h2606 = { f_fabric_write_reqs$D_OUT[66:64], 3'b0 } ;
assign strobe64__h2756 = 8'b00000001 << f_fabric_write_reqs$D_OUT[66:64] ;
assign strobe64__h2758 = 8'b00000011 << f_fabric_write_reqs$D_OUT[66:64] ;
assign strobe64__h2760 = 8'b00001111 << f_fabric_write_reqs$D_OUT[66:64] ;
assign tmp__h26884 = { 1'd0, rg_victim_way } ;
assign tmp__h26885 = tmp__h26884 + 2'd1 ;
assign w12744_BITS_31_TO_0__q51 = w1__h32744[31:0] ;
assign w1___1__h23938 =
{ 32'd0,
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347[31:0] } ;
assign w1___1__h32819 = { 32'd0, w1__h32744[31:0] } ;
assign w2___1__h32820 = { 32'd0, rg_st_amo_val[31:0] } ;
assign w2__h32750 = (rg_f3 == 3'b010) ? w2___1__h32820 : rg_st_amo_val ;
assign word64847_BITS_15_TO_0__q16 = word64__h5847[15:0] ;
assign word64847_BITS_15_TO_8__q18 = word64__h5847[15:8] ;
assign word64847_BITS_23_TO_16__q19 = word64__h5847[23:16] ;
assign word64847_BITS_31_TO_0__q17 = word64__h5847[31:0] ;
assign word64847_BITS_31_TO_16__q20 = word64__h5847[31:16] ;
assign word64847_BITS_31_TO_24__q21 = word64__h5847[31:24] ;
assign word64847_BITS_39_TO_32__q22 = word64__h5847[39:32] ;
assign word64847_BITS_47_TO_32__q23 = word64__h5847[47:32] ;
assign word64847_BITS_47_TO_40__q25 = word64__h5847[47:40] ;
assign word64847_BITS_55_TO_48__q26 = word64__h5847[55:48] ;
assign word64847_BITS_63_TO_32__q24 = word64__h5847[63:32] ;
assign word64847_BITS_63_TO_48__q27 = word64__h5847[63:48] ;
assign word64847_BITS_63_TO_56__q28 = word64__h5847[63:56] ;
assign word64847_BITS_7_TO_0__q15 = word64__h5847[7:0] ;
assign word64__h5847 = x__h6037 | y__h6038 ;
assign x__h20022 = { 63'd0, lrsc_result__h20012 } ;
assign x__h32739 =
(rg_f3 == 3'b010) ?
new_st_val__h32760 :
_theResult_____2__h32756 ;
assign x__h6037 = ram_word64_set$DOB[63:0] & y__h6052 ;
assign y__h12367 =
{64{ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117}} ;
assign y__h6038 = ram_word64_set$DOB[127:64] & y__h12367 ;
assign y__h6052 =
{64{ram_state_and_ctag_cset$DOB[22] &&
ram_state_and_ctag_cset_b_read__05_BITS_21_TO__ETC___d111}} ;
always@(f_fabric_write_reqs$D_OUT)
begin
case (f_fabric_write_reqs$D_OUT[97:96])
2'b0: x__h2639 = 3'b0;
2'b01: x__h2639 = 3'b001;
2'b10: x__h2639 = 3'b010;
2'b11: x__h2639 = 3'b011;
endcase
end
always@(rg_f3)
begin
case (rg_f3[1:0])
2'b0: value__h32296 = 3'b0;
2'b01: value__h32296 = 3'b001;
2'b10: value__h32296 = 3'b010;
2'd3: value__h32296 = 3'b011;
endcase
end
always@(f_fabric_write_reqs$D_OUT or
strobe64__h2756 or strobe64__h2758 or strobe64__h2760)
begin
case (f_fabric_write_reqs$D_OUT[97:96])
2'b0: mem_req_wr_data_wstrb__h2819 = strobe64__h2756;
2'b01: mem_req_wr_data_wstrb__h2819 = strobe64__h2758;
2'b10: mem_req_wr_data_wstrb__h2819 = strobe64__h2760;
2'b11: mem_req_wr_data_wstrb__h2819 = 8'b11111111;
endcase
end
always@(f_fabric_write_reqs$D_OUT or _theResult___snd_fst__h2826)
begin
case (f_fabric_write_reqs$D_OUT[97:96])
2'b0, 2'b01, 2'b10:
mem_req_wr_data_wdata__h2818 = _theResult___snd_fst__h2826;
2'd3: mem_req_wr_data_wdata__h2818 = f_fabric_write_reqs$D_OUT[63:0];
endcase
end
always@(ram_state_and_ctag_cset$DOB or
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117 or
ram_word64_set$DOB)
begin
case (ram_state_and_ctag_cset$DOB[45] &&
ram_state_and_ctag_cset_b_read__05_BITS_44_TO__ETC___d117)
1'd0: old_word64__h20790 = ram_word64_set$DOB[63:0];
1'd1: old_word64__h20790 = ram_word64_set$DOB[127:64];
endcase
end
always@(rg_addr or
result__h18723 or
result__h18751 or
result__h18779 or
result__h18807 or
result__h18835 or
result__h18863 or result__h18891 or result__h18919)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287 =
result__h18723;
3'h1:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287 =
result__h18751;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287 =
result__h18779;
3'h3:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287 =
result__h18807;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287 =
result__h18835;
3'h5:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287 =
result__h18863;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287 =
result__h18891;
3'h7:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287 =
result__h18919;
endcase
end
always@(rg_addr or
result__h18964 or
result__h18992 or
result__h19020 or
result__h19048 or
result__h19076 or
result__h19104 or result__h19132 or result__h19160)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304 =
result__h18964;
3'h1:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304 =
result__h18992;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304 =
result__h19020;
3'h3:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304 =
result__h19048;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304 =
result__h19076;
3'h5:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304 =
result__h19104;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304 =
result__h19132;
3'h7:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304 =
result__h19160;
endcase
end
always@(rg_addr or
result__h19205 or
result__h19233 or result__h19261 or result__h19289)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317 =
result__h19205;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317 =
result__h19233;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317 =
result__h19261;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317 =
result__h19289;
default: IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317 =
64'd0;
endcase
end
always@(rg_addr or
result__h19330 or
result__h19358 or result__h19386 or result__h19414)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326 =
result__h19330;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326 =
result__h19358;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326 =
result__h19386;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326 =
result__h19414;
default: IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326 =
64'd0;
endcase
end
always@(rg_addr or result__h19522 or result__h19550)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d338 =
result__h19522;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d338 =
result__h19550;
default: IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d338 =
64'd0;
endcase
end
always@(rg_addr or result__h19455 or result__h19483)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result9455_0x4_re_ETC__q29 =
result__h19455;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result9455_0x4_re_ETC__q29 =
result__h19483;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result9455_0x4_re_ETC__q29 =
64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317 or
CASE_rg_addr_BITS_2_TO_0_0x0_result9455_0x4_re_ETC__q29 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_ram_ETC___d340 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d338)
begin
case (rg_f3)
3'b0:
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287;
3'b001:
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317;
3'b010:
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347 =
CASE_rg_addr_BITS_2_TO_0_0x0_result9455_0x4_re_ETC__q29;
3'b011:
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_ram_ETC___d340;
3'b100:
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304;
3'b101:
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326;
3'b110:
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d338;
3'd7: IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC___d347 = 64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317 or
w1___1__h23938 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_ram_ETC___d340 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d338)
begin
case (rg_f3)
3'b0:
w1__h23867 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287;
3'b001:
w1__h23867 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317;
3'b010: w1__h23867 = w1___1__h23938;
3'b011:
w1__h23867 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_ram_ETC___d340;
3'b100:
w1__h23867 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304;
3'b101:
w1__h23867 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326;
3'b110:
w1__h23867 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d338;
3'd7: w1__h23867 = 64'd0;
endcase
end
always@(rg_addr or old_word64__h20790 or rg_st_amo_val)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d437 =
{ old_word64__h20790[63:16], rg_st_amo_val[15:0] };
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d437 =
{ old_word64__h20790[63:32],
rg_st_amo_val[15:0],
old_word64__h20790[15:0] };
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d437 =
{ old_word64__h20790[63:48],
rg_st_amo_val[15:0],
old_word64__h20790[31:0] };
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d437 =
{ rg_st_amo_val[15:0], old_word64__h20790[47:0] };
default: IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d437 =
old_word64__h20790;
endcase
end
always@(rg_addr or old_word64__h20790 or rg_st_amo_val)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d428 =
{ old_word64__h20790[63:8], rg_st_amo_val[7:0] };
3'h1:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d428 =
{ old_word64__h20790[63:16],
rg_st_amo_val[7:0],
old_word64__h20790[7:0] };
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d428 =
{ old_word64__h20790[63:24],
rg_st_amo_val[7:0],
old_word64__h20790[15:0] };
3'h3:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d428 =
{ old_word64__h20790[63:32],
rg_st_amo_val[7:0],
old_word64__h20790[23:0] };
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d428 =
{ old_word64__h20790[63:40],
rg_st_amo_val[7:0],
old_word64__h20790[31:0] };
3'h5:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d428 =
{ old_word64__h20790[63:48],
rg_st_amo_val[7:0],
old_word64__h20790[39:0] };
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d428 =
{ old_word64__h20790[63:56],
rg_st_amo_val[7:0],
old_word64__h20790[47:0] };
3'h7:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d428 =
{ rg_st_amo_val[7:0], old_word64__h20790[55:0] };
endcase
end
always@(rg_addr or old_word64__h20790 or rg_st_amo_val)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q30 =
{ old_word64__h20790[63:32], rg_st_amo_val[31:0] };
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q30 =
{ rg_st_amo_val[31:0], old_word64__h20790[31:0] };
default: CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q30 =
old_word64__h20790;
endcase
end
always@(rg_f3 or
old_word64__h20790 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d428 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d437 or
CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q30 or
rg_st_amo_val)
begin
case (rg_f3)
3'b0:
n__h20801 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d428;
3'b001:
n__h20801 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d437;
3'b010:
n__h20801 = CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q30;
3'b011: n__h20801 = rg_st_amo_val;
default: n__h20801 = old_word64__h20790;
endcase
end
always@(rg_f3 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317 or
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC__q31 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_ram_ETC___d340 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d338)
begin
case (rg_f3)
3'b0:
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d287;
3'b001:
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d317;
3'b010:
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 =
{ {32{IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC__q31[31]}},
IF_rg_f3_54_EQ_0b0_55_THEN_IF_rg_addr_9_BITS_2_ETC__q31 };
3'b011:
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_ram_ETC___d340;
3'b100:
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d304;
3'b101:
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d326;
3'b110:
IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d338;
3'd7: IF_rg_f3_54_EQ_0b10_27_THEN_SEXT_IF_rg_f3_54_E_ETC___d386 = 64'd0;
endcase
end
always@(rg_amo_funct7 or
new_st_val__h24978 or
new_st_val__h23970 or
w2__h32750 or
new_st_val__h24950 or
new_st_val__h24958 or
new_st_val__h24954 or
new_st_val__h24973 or new_st_val__h24962 or new_st_val__h24967)
begin
case (rg_amo_funct7[6:2])
5'b0: _theResult_____2__h23875 = new_st_val__h23970;
5'b00001: _theResult_____2__h23875 = w2__h32750;
5'b00100: _theResult_____2__h23875 = new_st_val__h24950;
5'b01000: _theResult_____2__h23875 = new_st_val__h24958;
5'b01100: _theResult_____2__h23875 = new_st_val__h24954;
5'b10000: _theResult_____2__h23875 = new_st_val__h24973;
5'b11000: _theResult_____2__h23875 = new_st_val__h24962;
5'b11100: _theResult_____2__h23875 = new_st_val__h24967;
default: _theResult_____2__h23875 = new_st_val__h24978;
endcase
end
always@(rg_addr or old_word64__h20790 or new_st_val__h23573)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d514 =
{ old_word64__h20790[63:16], new_st_val__h23573[15:0] };
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d514 =
{ old_word64__h20790[63:32],
new_st_val__h23573[15:0],
old_word64__h20790[15:0] };
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d514 =
{ old_word64__h20790[63:48],
new_st_val__h23573[15:0],
old_word64__h20790[31:0] };
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d514 =
{ new_st_val__h23573[15:0], old_word64__h20790[47:0] };
default: IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d514 =
old_word64__h20790;
endcase
end
always@(rg_addr or old_word64__h20790 or new_st_val__h23573)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d505 =
{ old_word64__h20790[63:8], new_st_val__h23573[7:0] };
3'h1:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d505 =
{ old_word64__h20790[63:16],
new_st_val__h23573[7:0],
old_word64__h20790[7:0] };
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d505 =
{ old_word64__h20790[63:24],
new_st_val__h23573[7:0],
old_word64__h20790[15:0] };
3'h3:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d505 =
{ old_word64__h20790[63:32],
new_st_val__h23573[7:0],
old_word64__h20790[23:0] };
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d505 =
{ old_word64__h20790[63:40],
new_st_val__h23573[7:0],
old_word64__h20790[31:0] };
3'h5:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d505 =
{ old_word64__h20790[63:48],
new_st_val__h23573[7:0],
old_word64__h20790[39:0] };
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d505 =
{ old_word64__h20790[63:56],
new_st_val__h23573[7:0],
old_word64__h20790[47:0] };
3'h7:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d505 =
{ new_st_val__h23573[7:0], old_word64__h20790[55:0] };
endcase
end
always@(rg_addr or old_word64__h20790 or new_st_val__h23573)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q33 =
{ old_word64__h20790[63:32], new_st_val__h23573[31:0] };
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q33 =
{ new_st_val__h23573[31:0], old_word64__h20790[31:0] };
default: CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q33 =
old_word64__h20790;
endcase
end
always@(rg_f3 or
old_word64__h20790 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d505 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d514 or
CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q33 or
new_st_val__h23573)
begin
case (rg_f3)
3'b0:
n__h23737 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d505;
3'b001:
n__h23737 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEL_ETC___d514;
3'b010:
n__h23737 = CASE_rg_addr_BITS_2_TO_0_0x0_old_word640790_BI_ETC__q33;
3'b011: n__h23737 = new_st_val__h23573;
default: n__h23737 = old_word64__h20790;
endcase
end
always@(rg_addr or
result__h31154 or
result__h31181 or result__h31208 or result__h31235)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d731 =
result__h31154;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d731 =
result__h31181;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d731 =
result__h31208;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d731 =
result__h31235;
default: IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d731 =
64'd0;
endcase
end
always@(rg_addr or
result__h31033 or
result__h31060 or result__h31087 or result__h31114)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d723 =
result__h31033;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d723 =
result__h31060;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d723 =
result__h31087;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d723 =
result__h31114;
default: IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d723 =
64'd0;
endcase
end
always@(rg_addr or
result__h30800 or
result__h30827 or
result__h30854 or
result__h30881 or
result__h30908 or
result__h30935 or result__h30962 or result__h30989)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d711 =
result__h30800;
3'h1:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d711 =
result__h30827;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d711 =
result__h30854;
3'h3:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d711 =
result__h30881;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d711 =
result__h30908;
3'h5:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d711 =
result__h30935;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d711 =
result__h30962;
3'h7:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d711 =
result__h30989;
endcase
end
always@(rg_addr or
result__h30564 or
result__h30594 or
result__h30621 or
result__h30648 or
result__h30675 or
result__h30702 or result__h30729 or result__h30756)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d695 =
result__h30564;
3'h1:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d695 =
result__h30594;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d695 =
result__h30621;
3'h3:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d695 =
result__h30648;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d695 =
result__h30675;
3'h5:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d695 =
result__h30702;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d695 =
result__h30729;
3'h7:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d695 =
result__h30756;
endcase
end
always@(rg_addr or result__h31275 or result__h31302)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result1275_0x4_re_ETC__q34 =
result__h31275;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result1275_0x4_re_ETC__q34 =
result__h31302;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result1275_0x4_re_ETC__q34 =
64'd0;
endcase
end
always@(rg_addr or result__h31340 or result__h31367)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result1340_0x4_re_ETC__q35 =
result__h31340;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result1340_0x4_re_ETC__q35 =
result__h31367;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result1340_0x4_re_ETC__q35 =
64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d695 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d723 or
CASE_rg_addr_BITS_2_TO_0_0x0_result1275_0x4_re_ETC__q34 or
rg_addr or
master_xactor_f_rd_data$D_OUT or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d711 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d731 or
CASE_rg_addr_BITS_2_TO_0_0x0_result1340_0x4_re_ETC__q35)
begin
case (rg_f3)
3'b0:
ld_val__h30504 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d695;
3'b001:
ld_val__h30504 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d723;
3'b010:
ld_val__h30504 =
CASE_rg_addr_BITS_2_TO_0_0x0_result1275_0x4_re_ETC__q34;
3'b011:
ld_val__h30504 =
(rg_addr[2:0] == 3'h0) ?
master_xactor_f_rd_data$D_OUT[66:3] :
64'd0;
3'b100:
ld_val__h30504 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d711;
3'b101:
ld_val__h30504 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d731;
3'b110:
ld_val__h30504 =
CASE_rg_addr_BITS_2_TO_0_0x0_result1340_0x4_re_ETC__q35;
3'd7: ld_val__h30504 = 64'd0;
endcase
end
always@(rg_addr or result__h34618 or result__h34646)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d850 =
result__h34618;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d850 =
result__h34646;
default: IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d850 =
64'd0;
endcase
end
always@(rg_addr or
result__h34426 or
result__h34454 or result__h34482 or result__h34510)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840 =
result__h34426;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840 =
result__h34454;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840 =
result__h34482;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840 =
result__h34510;
default: IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840 =
64'd0;
endcase
end
always@(rg_addr or
result__h34301 or
result__h34329 or result__h34357 or result__h34385)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832 =
result__h34301;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832 =
result__h34329;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832 =
result__h34357;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832 =
result__h34385;
default: IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832 =
64'd0;
endcase
end
always@(rg_addr or
result__h34060 or
result__h34088 or
result__h34116 or
result__h34144 or
result__h34172 or
result__h34200 or result__h34228 or result__h34256)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820 =
result__h34060;
3'h1:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820 =
result__h34088;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820 =
result__h34116;
3'h3:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820 =
result__h34144;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820 =
result__h34172;
3'h5:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820 =
result__h34200;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820 =
result__h34228;
3'h7:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820 =
result__h34256;
endcase
end
always@(rg_addr or
result__h32939 or
result__h33847 or
result__h33875 or
result__h33903 or
result__h33931 or
result__h33959 or result__h33987 or result__h34015)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804 =
result__h32939;
3'h1:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804 =
result__h33847;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804 =
result__h33875;
3'h3:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804 =
result__h33903;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804 =
result__h33931;
3'h5:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804 =
result__h33959;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804 =
result__h33987;
3'h7:
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804 =
result__h34015;
endcase
end
always@(rg_addr or result__h34551 or result__h34579)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result4551_0x4_re_ETC__q50 =
result__h34551;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result4551_0x4_re_ETC__q50 =
result__h34579;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result4551_0x4_re_ETC__q50 =
64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832 or
CASE_rg_addr_BITS_2_TO_0_0x0_result4551_0x4_re_ETC__q50 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_IF__ETC___d851 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d850)
begin
case (rg_f3)
3'b0:
w1__h32744 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804;
3'b001:
w1__h32744 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832;
3'b010:
w1__h32744 =
CASE_rg_addr_BITS_2_TO_0_0x0_result4551_0x4_re_ETC__q50;
3'b011:
w1__h32744 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_IF__ETC___d851;
3'b100:
w1__h32744 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820;
3'b101:
w1__h32744 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840;
3'b110:
w1__h32744 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d850;
3'd7: w1__h32744 = 64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832 or
w1___1__h32819 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_IF__ETC___d851 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d850)
begin
case (rg_f3)
3'b0:
w1__h32748 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804;
3'b001:
w1__h32748 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832;
3'b010: w1__h32748 = w1___1__h32819;
3'b011:
w1__h32748 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_IF__ETC___d851;
3'b100:
w1__h32748 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820;
3'b101:
w1__h32748 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840;
3'b110:
w1__h32748 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d850;
3'd7: w1__h32748 = 64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832 or
w12744_BITS_31_TO_0__q51 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_IF__ETC___d851 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840 or
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d850)
begin
case (rg_f3)
3'b0:
new_ld_val__h32710 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d804;
3'b001:
new_ld_val__h32710 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_SEX_ETC___d832;
3'b010:
new_ld_val__h32710 =
{ {32{w12744_BITS_31_TO_0__q51[31]}},
w12744_BITS_31_TO_0__q51 };
3'b011:
new_ld_val__h32710 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_IF__ETC___d851;
3'b100:
new_ld_val__h32710 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d820;
3'b101:
new_ld_val__h32710 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d840;
3'b110:
new_ld_val__h32710 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_0_C_ETC___d850;
3'd7: new_ld_val__h32710 = 64'd0;
endcase
end
always@(rg_amo_funct7 or
new_st_val__h34739 or
new_st_val__h32851 or
w2__h32750 or
new_st_val__h34711 or
new_st_val__h34719 or
new_st_val__h34715 or
new_st_val__h34734 or new_st_val__h34723 or new_st_val__h34728)
begin
case (rg_amo_funct7[6:2])
5'b0: _theResult_____2__h32756 = new_st_val__h32851;
5'b00001: _theResult_____2__h32756 = w2__h32750;
5'b00100: _theResult_____2__h32756 = new_st_val__h34711;
5'b01000: _theResult_____2__h32756 = new_st_val__h34719;
5'b01100: _theResult_____2__h32756 = new_st_val__h34715;
5'b10000: _theResult_____2__h32756 = new_st_val__h34734;
5'b11000: _theResult_____2__h32756 = new_st_val__h34723;
5'b11100: _theResult_____2__h32756 = new_st_val__h34728;
default: _theResult_____2__h32756 = new_st_val__h34739;
endcase
end
always@(rg_f3 or IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_1_E_ETC___d355)
begin
case (rg_f3)
3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110:
CASE_rg_f3_0b0_IF_rg_addr_9_BITS_2_TO_0_31_EQ__ETC__q52 =
IF_rg_addr_9_BITS_2_TO_0_31_EQ_0x0_56_THEN_1_E_ETC___d355;
3'd7: CASE_rg_f3_0b0_IF_rg_addr_9_BITS_2_TO_0_31_EQ__ETC__q52 = 64'd0;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0;
rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY 7'd0;
rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0;
end
else
begin
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (ctr_wr_rsps_pending_crg$EN)
ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
ctr_wr_rsps_pending_crg$D_IN;
if (rg_cset_in_cache$EN)
rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY rg_cset_in_cache$D_IN;
if (rg_lower_word32_full$EN)
rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY
rg_lower_word32_full$D_IN;
if (rg_lrsc_valid$EN)
rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY rg_lrsc_valid$D_IN;
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
end
if (rg_addr$EN) rg_addr <= `BSV_ASSIGNMENT_DELAY rg_addr$D_IN;
if (rg_amo_funct7$EN)
rg_amo_funct7 <= `BSV_ASSIGNMENT_DELAY rg_amo_funct7$D_IN;
if (rg_error_during_refill$EN)
rg_error_during_refill <= `BSV_ASSIGNMENT_DELAY
rg_error_during_refill$D_IN;
if (rg_exc_code$EN) rg_exc_code <= `BSV_ASSIGNMENT_DELAY rg_exc_code$D_IN;
if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN;
if (rg_ld_val$EN) rg_ld_val <= `BSV_ASSIGNMENT_DELAY rg_ld_val$D_IN;
if (rg_lower_word32$EN)
rg_lower_word32 <= `BSV_ASSIGNMENT_DELAY rg_lower_word32$D_IN;
if (rg_lrsc_pa$EN) rg_lrsc_pa <= `BSV_ASSIGNMENT_DELAY rg_lrsc_pa$D_IN;
if (rg_op$EN) rg_op <= `BSV_ASSIGNMENT_DELAY rg_op$D_IN;
if (rg_pa$EN) rg_pa <= `BSV_ASSIGNMENT_DELAY rg_pa$D_IN;
if (rg_pte_pa$EN) rg_pte_pa <= `BSV_ASSIGNMENT_DELAY rg_pte_pa$D_IN;
if (rg_st_amo_val$EN)
rg_st_amo_val <= `BSV_ASSIGNMENT_DELAY rg_st_amo_val$D_IN;
if (rg_victim_way$EN)
rg_victim_way <= `BSV_ASSIGNMENT_DELAY rg_victim_way$D_IN;
if (rg_word64_set_in_cache$EN)
rg_word64_set_in_cache <= `BSV_ASSIGNMENT_DELAY
rg_word64_set_in_cache$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_verbosity = 4'hA;
ctr_wr_rsps_pending_crg = 4'hA;
rg_addr = 32'hAAAAAAAA;
rg_amo_funct7 = 7'h2A;
rg_cset_in_cache = 7'h2A;
rg_error_during_refill = 1'h0;
rg_exc_code = 4'hA;
rg_f3 = 3'h2;
rg_ld_val = 64'hAAAAAAAAAAAAAAAA;
rg_lower_word32 = 32'hAAAAAAAA;
rg_lower_word32_full = 1'h0;
rg_lrsc_pa = 32'hAAAAAAAA;
rg_lrsc_valid = 1'h0;
rg_op = 2'h2;
rg_pa = 32'hAAAAAAAA;
rg_pte_pa = 32'hAAAAAAAA;
rg_st_amo_val = 64'hAAAAAAAAAAAAAAAA;
rg_state = 4'hA;
rg_victim_way = 1'h0;
rg_word64_set_in_cache = 9'h0AA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", mem_req_wr_addr_awaddr__h2592);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", x__h2639);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", mem_req_wr_data_wdata__h2818);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", mem_req_wr_data_wstrb__h2819);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 &&
cfg_verbosity != 4'd0 &&
!f_reset_reqs$D_OUT)
begin
v__h4093 = $stime;
#0;
end
v__h4087 = v__h4093 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 &&
cfg_verbosity != 4'd0 &&
!f_reset_reqs$D_OUT)
if (dmem_not_imem)
$display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY",
v__h4087,
"D_MMU_Cache",
$signed(32'd128),
$signed(32'd2));
else
$display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY",
v__h4087,
"I_MMU_Cache",
$signed(32'd128),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
f_reset_reqs$D_OUT)
begin
v__h4192 = $stime;
#0;
end
v__h4186 = v__h4192 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
f_reset_reqs$D_OUT)
if (dmem_not_imem)
$display("%0d: %s.rl_reset: Flushed", v__h4186, "D_MMU_Cache");
else
$display("%0d: %s.rl_reset: Flushed", v__h4186, "I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h4341 = $stime;
#0;
end
v__h4335 = v__h4341 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h",
v__h4335,
"D_MMU_Cache",
rg_addr);
else
$display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h",
v__h4335,
"I_MMU_Cache",
rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" eaddr = {CTag 0x%0h CSet 0x%0h Word64 0x%0h Byte 0x%0h}",
pa_ctag__h5533,
rg_addr[11:5],
rg_addr[4:3],
rg_addr[2:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" CSet 0x%0x: (state, tag):", rg_addr[11:5]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" (");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
ram_state_and_ctag_cset$DOB[22])
$write("CTAG_CLEAN");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
!ram_state_and_ctag_cset$DOB[22])
$write("CTAG_EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
ram_state_and_ctag_cset$DOB[22])
$write(", 0x%0x", ram_state_and_ctag_cset$DOB[21:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
!ram_state_and_ctag_cset$DOB[22])
$write(", --");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(")");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" (");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
ram_state_and_ctag_cset$DOB[45])
$write("CTAG_CLEAN");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
!ram_state_and_ctag_cset$DOB[45])
$write("CTAG_EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
ram_state_and_ctag_cset$DOB[45])
$write(", 0x%0x", ram_state_and_ctag_cset$DOB[44:23]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
!ram_state_and_ctag_cset$DOB[45])
$write(", --");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(")");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" CSet 0x%0x, Word64 0x%0x: ",
rg_addr[11:5],
rg_addr[4:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" 0x%0x", ram_word64_set$DOB[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" 0x%0x", ram_word64_set$DOB[127:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" TLB result: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("VM_Xlate_Result { ", "outcome: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("VM_XLATE_OK");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "pa: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'hA, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp && dmem_not_imem &&
!soc_map$m_is_mem_addr &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" => IO_REQ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d162)
$display(" ASSERTION ERROR: fn_test_cache_hit_or_miss: multiple hits in set at [%0d] and [%0d]",
$signed(32'd1),
1'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d361)
begin
v__h19635 = $stime;
#0;
end
v__h19629 = v__h19635 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d361)
if (dmem_not_imem)
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h19629,
"D_MMU_Cache",
rg_addr,
word64__h5847,
64'd0);
else
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h19629,
"I_MMU_Cache",
rg_addr,
word64__h5847,
64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d369)
$display(" AMO LR: reserving PA 0x%0h", rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d361)
$display(" Read-hit: addr 0x%0h word64 0x%0h",
rg_addr,
word64__h5847);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d372)
$display(" Read Miss: -> CACHE_START_REFILL.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d378)
$display(" AMO LR: cache refill: cancelling LR/SC reservation for PA 0x%0h",
rg_lrsc_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d535)
$display(" ST: cancelling LR/SC reservation for PA", rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 &&
rg_lrsc_valid &&
!rg_lrsc_pa_8_EQ_rg_addr_9___d99 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" AMO SC: fail: reserved addr 0x%0h, this address 0x%0h",
rg_lrsc_pa,
rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 &&
!rg_lrsc_valid &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" AMO SC: fail due to invalid LR/SC reservation");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_57_OR_soc_map_m_is_mem_addr__ETC___d547)
$display(" AMO SC result = %0d", lrsc_result__h20012);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d550)
$display(" Write-Cache-Hit: pa 0x%0h word64 0x%0h",
rg_addr,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d550)
$write(" New Word64_Set:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d550)
$write(" CSet 0x%0x, Word64 0x%0x: ",
rg_addr[11:5],
rg_addr[4:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d550)
$write(" 0x%0x",
IF_NOT_ram_state_and_ctag_cset_b_read__05_BIT__ETC___d448);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d550)
$write(" 0x%0x",
IF_ram_state_and_ctag_cset_b_read__05_BIT_45_1_ETC___d447);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d550)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_4_EQ_2_6_41_OR_NOT_rg_amo_funct7_7_B_ETC___d552)
$display(" Write-Cache-Miss: pa 0x%0h word64 0x%0h",
rg_addr,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d558)
$display(" Write-Cache-Hit/Miss: eaddr 0x%0h word64 0x%0h",
rg_addr,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d558)
$display(" => rl_write_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d562)
begin
v__h23351 = $stime;
#0;
end
v__h23345 = v__h23351 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d562)
if (dmem_not_imem)
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h23345,
"D_MMU_Cache",
rg_addr,
64'd1,
64'd0);
else
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h23345,
"I_MMU_Cache",
rg_addr,
64'd1,
64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d562)
$display(" AMO SC: Fail response for addr 0x%0h", rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
NOT_ram_state_and_ctag_cset_b_read__05_BIT_22__ETC___d370)
$display(" AMO Miss: -> CACHE_START_REFILL.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d570)
$display(" AMO: addr 0x%0h amo_f7 0x%0h f3 %0d rs2_val 0x%0h",
rg_addr,
rg_amo_funct7,
rg_f3,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d570)
$display(" PA 0x%0h ", rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d570)
$display(" Cache word64 0x%0h, load-result 0x%0h",
word64__h5847,
word64__h5847);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d570)
$display(" 0x%0h op 0x%0h -> 0x%0h",
word64__h5847,
word64__h5847,
new_st_val__h23573);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d570)
$write(" New Word64_Set:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d570)
$write(" CSet 0x%0x, Word64 0x%0x: ",
rg_addr[11:5],
rg_addr[4:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d570)
$write(" 0x%0x",
IF_NOT_ram_state_and_ctag_cset_b_read__05_BIT__ETC___d525);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d570)
$write(" 0x%0x",
IF_ram_state_and_ctag_cset_b_read__05_BIT_45_1_ETC___d524);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_4_EQ_0_5_40_AND_NOT_rg_op_4_EQ_2_6_4_ETC___d570)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
ram_state_and_ctag_cset_b_read__05_BIT_22_06_A_ETC___d572)
$display(" AMO_op: cancelling LR/SC reservation for PA",
rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h26669 = $stime;
#0;
end
v__h26663 = v__h26669 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_start_cache_refill: ",
v__h26663,
"D_MMU_Cache");
else
$display("%0d: %s.rl_start_cache_refill: ",
v__h26663,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", cline_fabric_addr__h26722);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 8'd3);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 3'b011);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" Victim way %0d; => CACHE_REFILL", tmp__h26885[0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
begin
v__h27408 = $stime;
#0;
end
v__h27402 = v__h27408 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
if (dmem_not_imem)
$display("%0d: %s.rl_cache_refill_rsps_loop:",
v__h27402,
"D_MMU_Cache");
else
$display("%0d: %s.rl_cache_refill_rsps_loop:",
v__h27402,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600 &&
master_xactor_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600 &&
!master_xactor_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h27649 = $stime;
#0;
end
v__h27643 = v__h27649 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d",
v__h27643,
"D_MMU_Cache",
access_exc_code__h2374);
else
$display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d",
v__h27643,
"I_MMU_Cache",
access_exc_code__h2374);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[1:0] == 2'd3 &&
(master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
rg_error_during_refill) &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" => MODULE_EXCEPTION_RSP");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[1:0] == 2'd3 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
!rg_error_during_refill &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" => CACHE_REREQ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$display(" Updating Cache word64_set 0x%0h, word64_in_cline %0d) old => new",
rg_word64_set_in_cache,
rg_word64_set_in_cache[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write(" CSet 0x%0x, Word64 0x%0x: ",
rg_addr[11:5],
rg_word64_set_in_cache[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write(" 0x%0x", ram_word64_set$DOB[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write(" 0x%0x", ram_word64_set$DOB[127:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write(" CSet 0x%0x, Word64 0x%0x: ",
rg_addr[11:5],
rg_word64_set_in_cache[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write(" 0x%0x",
rg_victim_way ?
ram_word64_set$DOB[63:0] :
master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write(" 0x%0x",
rg_victim_way ?
master_xactor_f_rd_data$D_OUT[66:3] :
ram_word64_set$DOB[127:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__0_ULE_2_99___d600)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_rereq && NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]",
rg_addr[11:5],
rg_addr[11:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h30045 = $stime;
#0;
end
v__h30039 = v__h30045 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h",
v__h30039,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h",
v__h30039,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", fabric_addr__h32167);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", value__h32296);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h30395 = $stime;
#0;
end
v__h30389 = v__h30395 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h30389,
"D_MMU_Cache",
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h30389,
"I_MMU_Cache",
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
master_xactor_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
!master_xactor_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h31495 = $stime;
#0;
end
v__h31489 = v__h31495 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h31489,
"D_MMU_Cache",
rg_addr,
ld_val__h30504);
else
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h31489,
"I_MMU_Cache",
rg_addr,
ld_val__h30504);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h31602 = $stime;
#0;
end
v__h31596 = v__h31602 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT",
v__h31596,
"D_MMU_Cache");
else
$display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT",
v__h31596,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_maintain_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h31707 = $stime;
#0;
end
v__h31701 = v__h31707 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_maintain_io_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h31701,
"D_MMU_Cache",
rg_addr,
rg_ld_val);
else
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h31701,
"I_MMU_Cache",
rg_addr,
rg_ld_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h31787 = $stime;
#0;
end
v__h31781 = v__h31787 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h31781,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
else
$display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h31781,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" => rl_ST_AMO_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h31997 = $stime;
#0;
end
v__h31991 = v__h31997 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h31991,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
else
$display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h31991,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" FAIL due to I/O address.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" => rl_ST_AMO_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h32115 = $stime;
#0;
end
v__h32109 = v__h32115 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h",
v__h32109,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h",
v__h32109,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", fabric_addr__h32167);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", value__h32296);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h32409 = $stime;
#0;
end
v__h32403 = v__h32409 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h32403,
"D_MMU_Cache",
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h32403,
"I_MMU_Cache",
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
master_xactor_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
!master_xactor_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h32584 = $stime;
#0;
end
v__h32578 = v__h32584 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h32578,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
else
$display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h32578,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h34843 = $stime;
#0;
end
v__h34837 = v__h34843 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h34837,
"D_MMU_Cache",
rg_addr,
new_ld_val__h32710);
else
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h34837,
"I_MMU_Cache",
rg_addr,
new_ld_val__h32710);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" => rl_ST_AMO_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h32680 = $stime;
#0;
end
v__h32674 = v__h32680 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT",
v__h32674,
"D_MMU_Cache");
else
$display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT",
v__h32674,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h35450 = $stime;
#0;
end
v__h35444 = v__h35450 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
if (dmem_not_imem)
$write("%0d: %s.rl_discard_write_rsp: pending %0d ",
v__h35444,
"D_MMU_Cache",
$unsigned(b__h26623));
else
$write("%0d: %s.rl_discard_write_rsp: pending %0d ",
v__h35444,
"I_MMU_Cache",
$unsigned(b__h26623));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", master_xactor_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", master_xactor_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
begin
v__h35411 = $stime;
#0;
end
v__h35405 = v__h35411 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
if (dmem_not_imem)
$display("%0d: %s.rl_discard_write_rsp: fabric response error: exit",
v__h35405,
"D_MMU_Cache");
else
$display("%0d: %s.rl_discard_write_rsp: fabric response error: exit",
v__h35405,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("'h%h", master_xactor_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("'h%h", master_xactor_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_reset)
begin
v__h3625 = $stime;
#0;
end
v__h3619 = v__h3625 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_reset)
if (dmem_not_imem)
$display("%0d: %s: cache size %0d KB, associativity %0d, line size %0d bytes (= %0d XLEN words)",
v__h3619,
"D_MMU_Cache",
$signed(32'd8),
$signed(32'd2),
$signed(32'd32),
$signed(32'd8));
else
$display("%0d: %s: cache size %0d KB, associativity %0d, line size %0d bytes (= %0d XLEN words)",
v__h3619,
"I_MMU_Cache",
$signed(32'd8),
$signed(32'd2),
$signed(32'd32),
$signed(32'd8));
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42)
begin
v__h35798 = $stime;
#0;
end
v__h35792 = v__h35798 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write("%0d: %m.req: op:", v__h35792);
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42 && req_op == 2'd0)
$write("CACHE_LD");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42 && req_op == 2'd1)
$write("CACHE_ST");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
req_op != 2'd0 &&
req_op != 2'd1)
$write("CACHE_AMO");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" f3:%0d addr:0x%0h st_value:0x%0h",
req_f3,
req_addr,
req_st_value,
"\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" priv:");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
req_priv == 2'b0)
$write("U");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
req_priv == 2'b01)
$write("S");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
req_priv == 2'b11)
$write("M");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42 &&
req_priv != 2'b0 &&
req_priv != 2'b01 &&
req_priv != 2'b11)
$write("RESERVED");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
req_sstatus_SUM,
req_mstatus_MXR,
req_satp,
"\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" amo_funct7 = 0x%0h", req_amo_funct7);
if (RST_N != `BSV_RESET_VALUE)
if (EN_req &&
req_f3_BITS_1_TO_0_36_EQ_0b0_37_OR_req_f3_BITS_ETC___d966 &&
NOT_cfg_verbosity_read__0_ULE_1_1___d42)
$display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]",
req_addr[11:5],
req_addr[11:3]);
end
// synopsys translate_on
endmodule // mkMMU_Cache
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2_2_V
`define SKY130_FD_SC_LP__AND2_2_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2_2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2_2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2_2_V
|
`default_nettype none
`include "core.h"
module decode_function(
//Input
input wire [31:0] iINSTLUCTION,
//Info
output wire oINF_ERROR,
//
output wire oDECODE_SOURCE0_ACTIVE,
output wire oDECODE_SOURCE1_ACTIVE,
output wire oDECODE_SOURCE0_SYSREG,
output wire oDECODE_SOURCE1_SYSREG,
output wire oDECODE_SOURCE0_SYSREG_RENAME,
output wire oDECODE_SOURCE1_SYSREG_RENAME,
output wire oDECODE_ADV_ACTIVE,
output wire oDECODE_DESTINATION_SYSREG,
output wire oDECODE_DEST_RENAME,
output wire oDECODE_WRITEBACK,
output wire oDECODE_FLAGS_WRITEBACK,
output wire oDECODE_FRONT_COMMIT_WAIT,
output wire [4:0] oDECODE_CMD,
output wire [3:0] oDECODE_CC_AFE,
output wire [4:0] oDECODE_SOURCE0,
output wire [31:0] oDECODE_SOURCE1,
output wire [5:0] oDECODE_ADV_DATA,
output wire oDECODE_SOURCE0_FLAGS,
output wire oDECODE_SOURCE1_IMM,
output wire [4:0] oDECODE_DESTINATION,
output wire oDECODE_EX_SYS_REG,
output wire oDECODE_EX_SYS_LDST,
output wire oDECODE_EX_LOGIC,
output wire oDECODE_EX_SHIFT,
output wire oDECODE_EX_ADDER,
output wire oDECODE_EX_MUL,
output wire oDECODE_EX_SDIV,
output wire oDECODE_EX_UDIV,
output wire oDECODE_EX_LDST,
output wire oDECODE_EX_BRANCH
);
function [81:0] f_decode;
input [31:0] f_decode_inst;
begin
case(f_decode_inst[30 : 21])
/*******************
Integer
*******************/
`OC_ADD :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,//++
/* Displacement Data -> ADV Enable */ 1'b0,//++
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_ADD,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{f_decode_inst[15]}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_ADD,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
end
`OC_SUB :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_SUB,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{f_decode_inst[15]}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_SUB,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
end
`OC_MULL :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_MUL_MULL,
/* Execute Module */ `EXE_SELECT_MUL
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{f_decode_inst[15]}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_MUL_MULL,
/* Execute Module */ `EXE_SELECT_MUL
};
end
end
`OC_MULH :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_MUL_MULH,
/* Execute Module */ `EXE_SELECT_MUL
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{f_decode_inst[15]}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_MUL_MULH,
/* Execute Module */ `EXE_SELECT_MUL
};
end
end
`OC_UDIV :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_DIV_UDIV,
/* Execute Module */ `EXE_SELECT_UDIV
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_DIV_UDIV,
/* Execute Module */ `EXE_SELECT_UDIV
};
end
end
`OC_UMOD :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_DIV_UMOD,
/* Execute Module */ `EXE_SELECT_UDIV
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_DIV_UMOD,
/* Execute Module */ `EXE_SELECT_UDIV
};
end
end
`OC_CMP :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_ADDER_SUB,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{f_decode_inst[15]}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_ADDER_SUB,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
end
`OC_DIV :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_DIV_DIV,
/* Execute Module */ `EXE_SELECT_SDIV
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{f_decode_inst[15]}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_DIV_DIV,
/* Execute Module */ `EXE_SELECT_SDIV
};
end
end
`OC_MOD :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_DIV_MOD,
/* Execute Module */ `EXE_SELECT_SDIV
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_DIV_MOD,
/* Execute Module */ `EXE_SELECT_SDIV
};
end
end
`OC_NEG :
begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[4:0],
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_NEG,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
`OC_UMULL :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_MUL_UMULL,
/* Execute Module */ `EXE_SELECT_MUL
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_MUL_UMULL,
/* Execute Module */ `EXE_SELECT_MUL
};
end
end
`OC_UMULH :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_MUL_UMULH,
/* Execute Module */ `EXE_SELECT_MUL
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_MUL_UMULH,
/* Execute Module */ `EXE_SELECT_MUL
};
end
end
`OC_IC :
begin
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[4:0],
/* Source1 */ 32'h1,
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_COUT,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
`OC_ADDC :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_COUT,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{f_decode_inst[15]}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_COUT,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
end
`OC_INC :
begin
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[4:0],
/* Source1 */ 32'h1,
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_ADD,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
`OC_DEC :
begin
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[4:0],
/* Source1 */ 32'h1,
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_SUB,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
`OC_MAX :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_MAX,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{f_decode_inst[15]}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_MAX,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
end
`OC_MIN :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_MIN,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{f_decode_inst[15]}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_MIN,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
end
`OC_UMAX :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_UMAX,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{f_decode_inst[15]}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_UMAX,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
end
`OC_UMIN :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_UMIN,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{f_decode_inst[15]}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_UMIN,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
end
`OC_SEXT8 :
begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_SEXT8,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
`OC_SEXT16 :
begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_SEXT16,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
/*******************
Floating
*******************/
/*******************
Shift
*******************/
`OC_SHL :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SHIFT_LOGICL,
/* Execute Module */ `EXE_SELECT_SHIFT
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SHIFT_LOGICL,
/* Execute Module */ `EXE_SELECT_SHIFT
};
end
end
`OC_SHR :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SHIFT_LOGICR,
/* Execute Module */ `EXE_SELECT_SHIFT
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SHIFT_LOGICR,
/* Execute Module */ `EXE_SELECT_SHIFT
};
end
end
`OC_SAR :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SHIFT_ALITHMETICR,
/* Execute Module */ `EXE_SELECT_SHIFT
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SHIFT_ALITHMETICR,
/* Execute Module */ `EXE_SELECT_SHIFT
};
end
end
`OC_ROL :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SHIFT_ROTATEL,
/* Execute Module */ `EXE_SELECT_SHIFT
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SHIFT_ROTATEL,
/* Execute Module */ `EXE_SELECT_SHIFT
};
end
end
`OC_ROR :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SHIFT_ROTATER,
/* Execute Module */ `EXE_SELECT_SHIFT
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SHIFT_ROTATER,
/* Execute Module */ `EXE_SELECT_SHIFT
};
end
end
/*******************
Logic
*******************/
`OC_AND :
begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_AND,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
`OC_OR :
begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_OR,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
`OC_XOR :
begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_XOR,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
`OC_NOT :
begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[4:0],
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_NOT,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
`OC_NAND :
begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_NAND,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
`OC_NOR :
begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_NOR,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
`OC_XNOR :
begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_XNOR,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
`OC_TEST :
begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b1,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LOGIC_TEST,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
`OC_WL16 :
begin //I16
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{16{1'b0}}, f_decode_inst[20:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_WBL,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
`OC_WH16 :
begin //I16
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{16{1'b0}}, f_decode_inst[20:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_WBH,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
`OC_CLRB :
begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_CLB,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
`OC_SETB :
begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_STB,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
`OC_CLR :
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_CLW,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
`OC_SET : //okasi
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {32{1'b1}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_STW,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
`OC_REVB :
begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[4:0],
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_BITREV,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
`OC_REV8 :
begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[4:0],
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_BYTEREV,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
`OC_GETB :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_GETBIT,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_GETBIT,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
end
`OC_GET8 :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_GETBYTE,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{21{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_GETBYTE,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
end
`OC_LIL :
begin //I16
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{16{1'b0}}, f_decode_inst[20:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_LIL,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
`OC_LIH :
begin //I16
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {f_decode_inst[20:10], f_decode_inst[4:0], {16{1'b0}}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_LIH,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
`OC_ULIL :
begin //I16
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{16{1'b0}}, f_decode_inst[20:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_ULIL,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
/*******************
Load/Store
*******************/
`OC_LD8 :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ {5{1'b0}},
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]}, //Rs
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_LD8,
/* Execute Module */ `EXE_SELECT_LDST
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ {5{1'b0}},
/* Source1 */ {{21{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0]}, //Rs
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_LD8,
/* Execute Module */ `EXE_SELECT_LDST
};
end
end
`OC_LD16 :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ {5{1'b0}},
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]}, //Rs
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_LD16,
/* Execute Module */ `EXE_SELECT_LDST
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ {5{1'b0}},
/* Source1 */ {{20{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0], 1'b0}, //Rs
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_LD16,
/* Execute Module */ `EXE_SELECT_LDST
};
end
end
`OC_LD32 :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ {5{1'b0}},
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]}, //Rs
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_LD32,
/* Execute Module */ `EXE_SELECT_LDST
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ {5{1'b0}},
/* Source1 */ {{19{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0], 2'b00}, //Rs
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_LD32,
/* Execute Module */ `EXE_SELECT_LDST
};
end
end
`OC_ST8 :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5], //Rd
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]}, //Rs
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_ST8,
/* Execute Module */ `EXE_SELECT_LDST
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5], //Rd
/* Source1 */ {{21{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0]}, //Rs
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_ST8,
/* Execute Module */ `EXE_SELECT_LDST
};
end
end
`OC_ST16 :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5], //Rd
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]}, //Rs
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_ST16,
/* Execute Module */ `EXE_SELECT_LDST
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5], //Rd
/* Source1 */ {{20{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0], 1'b0}, //Rs
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_ST16,
/* Execute Module */ `EXE_SELECT_LDST
};
end
end
`OC_ST32 :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5], //Rd
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]}, //Rs
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_ST32,
/* Execute Module */ `EXE_SELECT_LDST
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5], //Rd
/* Source1 */ {{19{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0], 2'b00}, //Rs
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_ST32,
/* Execute Module */ `EXE_SELECT_LDST
};
end
end
`OC_PUSH :
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5], //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
`OC_PUSHPC :
begin //C
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_PCR, //PC
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PPUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
`OC_POP :
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ 5'h00,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
`OC_LDD8 :
begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ {5{1'b0}},
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]}, //Rs
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ f_decode_inst[15:10],
/* Displacement Data -> ADV Enable */ 1'b1,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_LDD8,
/* Execute Module */ `EXE_SELECT_LDST
};
end
`OC_LDD16 :
begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ {5{1'b0}},
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]}, //Rs
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ f_decode_inst[15:10],
/* Displacement Data -> ADV Enable */ 1'b1,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_LDD16,
/* Execute Module */ `EXE_SELECT_LDST
};
end
`OC_LDD32 :
begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ {5{1'b0}},
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]}, //Rs
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ f_decode_inst[15:10],
/* Displacement Data -> ADV Enable */ 1'b1,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_LDD32,
/* Execute Module */ `EXE_SELECT_LDST
};
end
`OC_STD8 :
begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5], //Rd
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]}, //Rs
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ f_decode_inst[15:10],
/* Displacement Data -> ADV Enable */ 1'b1,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_STD8,
/* Execute Module */ `EXE_SELECT_LDST
};
end
`OC_STD16 :
begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5], //Rd
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]}, //Rs
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ f_decode_inst[15:10],
/* Displacement Data -> ADV Enable */ 1'b1,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_STD16,
/* Execute Module */ `EXE_SELECT_LDST
};
end
`OC_STD32 :
begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5], //Rd
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]}, //Rs
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ f_decode_inst[15:10],
/* Displacement Data -> ADV Enable */ 1'b1,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_STD32,
/* Execute Module */ `EXE_SELECT_LDST
};
end
/*******************
Branch
*******************/
`OC_BUR :
begin
if(!f_decode_inst[20])begin //JO1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],// /* Source0 */ `SYSREG_PC, //PC
/* Source1 */ {{27{1'b0}}, f_decode_inst[9:5]}, //Rd
/* Source0 Use Flags*/ 1'b1,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1, //Flag
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,//1'b0,// /* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PCR,
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_BRANCH_BUR,
/* Execute Module */ `EXE_SELECT_BRANCH
};
end
else begin //JI16
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],// /* Source0 */ `SYSREG_PC, //PC
/* Source1 */ {{14{1'b0}}, f_decode_inst[15:0], 2'h0}, //Rd
/* Source0 Use Flags*/ 1'b1,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1, //Flag
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,//1'b0,// /* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PCR,
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_BRANCH_BUR,
/* Execute Module */ `EXE_SELECT_BRANCH
};
end
end
`OC_BR :
begin
if(!f_decode_inst[20])begin //JO1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],// /* Source0 */ `SYSREG_PC, //PC
/* Source1 */ {{27{1'b0}}, f_decode_inst[9:5]}, //Rd
/* Source0 Use Flags*/ 1'b1,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1, //Flag
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,//1'b0,// /* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PCR,
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_BRANCH_BR,
/* Execute Module */ `EXE_SELECT_BRANCH
};
end
else begin //JI16
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],// /* Source0 */ `SYSREG_PC, //PC
/* Source1 */ {{14{f_decode_inst[15]}}, f_decode_inst[15:0], 2'h0}, //{{16{1'b0}}, f_decode_inst[15:0]}, //Rd
/* Source0 Use Flags*/ 1'b1,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1, //Flag
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,//1'b0,// /* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PCR,
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_BRANCH_BR,
/* Execute Module */ `EXE_SELECT_BRANCH
};
end
end
`OC_B :
begin
if(!f_decode_inst[20])begin //JO1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ {5{1'b0}}, //none
/* Source1 */ {{27{1'b0}}, f_decode_inst[9:5]}, //Rd
/* Source0 Use Flags*/ 1'b1,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,//1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,//1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PCR,
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_BRANCH_B,
/* Execute Module */ `EXE_SELECT_BRANCH
};
end
else begin //JI16
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ {5{1'b0}}, //none
/* Source1 */ {{14{1'b0}}, f_decode_inst[15:0], 2'b0}, //Rd
/* Source0 Use Flags*/ 1'b1,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,//1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,//1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PCR,
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_BRANCH_B,
/* Execute Module */ `EXE_SELECT_BRANCH
};
end
end
`OC_IB :
begin
if(!f_decode_inst[20])begin //JO1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ {5{1'b0}}, //none
/* Source1 */ {{27{1'b0}}, f_decode_inst[9:5]}, //Rd
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PCR,
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_BRANCH_INTB,
/* Execute Module */ `EXE_SELECT_BRANCH
};
end
else begin //JI16
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ {5{1'b0}}, //none
/* Source1 */ {{14{1'b0}}, f_decode_inst[15:0], 2'h0}, //Rd
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PCR,
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_BRANCH_INTB,
/* Execute Module */ `EXE_SELECT_BRANCH
};
end
end
`OC_BURN :
begin
if(!f_decode_inst[20])begin //JO1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],// /* Source0 */ `SYSREG_PC, //PC
/* Source1 */ {{27{1'b0}}, f_decode_inst[9:5]}, //Rd
/* Source0 Use Flags*/ 1'b1,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1, //Flag
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,//1'b0,// /* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PCR,
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_BRANCH_BUR,
/* Execute Module */ `EXE_SELECT_BRANCH
};
end
else begin //JI16
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],// /* Source0 */ `SYSREG_PC, //PC
/* Source1 */ {{14{1'b0}}, f_decode_inst[15:0], 2'h0}, //Rd
/* Source0 Use Flags*/ 1'b1,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1, //Flag
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,//1'b0,// /* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PCR,
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_BRANCH_BUR,
/* Execute Module */ `EXE_SELECT_BRANCH
};
end
end
`OC_BRN :
begin
if(!f_decode_inst[20])begin //JO1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],// /* Source0 */ `SYSREG_PC, //PC
/* Source1 */ {{27{1'b0}}, f_decode_inst[9:5]}, //Rd
/* Source0 Use Flags*/ 1'b1,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1, //Flag
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,//1'b0,// /* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PCR,
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_BRANCH_BR,
/* Execute Module */ `EXE_SELECT_BRANCH
};
end
else begin //JI16
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],// /* Source0 */ `SYSREG_PC, //PC
/* Source1 */ {{14{f_decode_inst[15]}}, f_decode_inst[15:0], 2'h0}, //{{16{1'b0}}, f_decode_inst[15:0]}, //Rd
/* Source0 Use Flags*/ 1'b1,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1, //Flag
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,//1'b0,// /* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PCR,
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_BRANCH_BR,
/* Execute Module */ `EXE_SELECT_BRANCH
};
end
end
`OC_BN :
begin
if(!f_decode_inst[20])begin //JO1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ {5{1'b0}}, //none
/* Source1 */ {{27{1'b0}}, f_decode_inst[9:5]}, //Rd
/* Source0 Use Flags*/ 1'b1,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,//1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,//1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PCR,
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_BRANCH_B,
/* Execute Module */ `EXE_SELECT_BRANCH
};
end
else begin //JI16
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ {5{1'b0}}, //none
/* Source1 */ {{14{1'b0}}, f_decode_inst[15:0], 2'b0}, //Rd
/* Source0 Use Flags*/ 1'b1,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,//1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,//1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PCR,
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_BRANCH_B,
/* Execute Module */ `EXE_SELECT_BRANCH
};
end
end
/*******************
System Read
*******************/
`OC_SRSPR :
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_SPR,
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_LDST_READ_SPR,
/* Execute Module */ `EXE_SELECT_SYS_LDST
};
end
`OC_SRPDTR :
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_PDTR,
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRPIDR :
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_CPUIDR,
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRCIDR :
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_COREIDR,
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_MODER :
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_PSR,
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_SR1_CMOD_R,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRIEIR :
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_PSR,
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_SR1_IM_R,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRTISR :
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_TISR,
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRKPDTR :
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_KPDTR,
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRMMUR :
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_PSR,
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_SR1_MMUMOD_R,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRIOSR :
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_IOSR,
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRTIDR :
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_TIDR,
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRPPSR:
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_PPSR,
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRPPCR:
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_PPCR,
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRPPDTR:
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_PPDTR,
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRPTIDR:
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_PTIDR,
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRPSR:
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_PSR,
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRFRCR:
begin //C
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ 5'h0,
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_FRCR2FRCXR,
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRFRCLR:
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_FRCLR,
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRFRCHR:
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_FRCHR,
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRPFLAGR:
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_PFLAGR,
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
/*******************
System Write
*******************/
`OC_SRSPW :
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_SPR,
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_LDST_WRITE_SPR,
/* Execute Module */ `EXE_SELECT_SYS_LDST
};
end
`OC_SRPDTW :
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PDTR,
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_LDST
};
end
`OC_SRIEIW :
begin
if(!f_decode_inst[20])begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_PSR,
/* Source1 */ {{27{1'b0}}, f_decode_inst[9:5]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PSR,
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_REG_SR1_IM_W,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_PSR,
/* Source1 */ {{21{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PSR,
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_REG_SR1_IM_W,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
end
`OC_SRTISW :
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_TISR,
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRKPDTW :
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_KPDTR,
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRMMUW :
begin
if(!f_decode_inst[20])begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_PSR,
/* Source1 */ {{27{1'b0}}, f_decode_inst[9:5]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PSR,
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_REG_SR1_MMUMOD_W,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_PSR,
/* Source1 */ {{21{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PSR,
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_REG_SR1_MMUMOD_W,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
end
`OC_SRPPSW :
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PPSR,
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRPPCW :
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PPCR,
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRPPDTW :
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PPDTR,
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRPTIDW :
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PTIDR,
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRIDTW:
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_IDTR,
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRPSW:
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PSR,
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRFRCW:
begin //C
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ 5'h0,
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_FRCR,
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRFRCLR:
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_FRCLR,
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRFRCHR:
begin //O1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_FRCHR,
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
`OC_SRSPWADD :
begin //CI16
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_SPR,
/* Source1 */ {{14{f_decode_inst[15]}}, f_decode_inst[15:0], 2'h0},//{{16{1'b0}}, f_decode_inst[15:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_SPR,
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_LDST_ADD_SPR,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
/*******************
Other
*******************/
`OC_NOP :
begin //C
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ {5{1'b0}},
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_ADDER_ADD,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
`OC_HALT :
begin //C
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ {5{1'b0}},
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_BRANCH_HALT,
/* Execute Module */ `EXE_SELECT_BRANCH
};
end
`OC_MOVE :
begin
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_BUFFER1,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
`OC_MOVEPC :
begin
if(!f_decode_inst[20])begin //O2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_PCR,
/* Source1 */ {{27{1'b0}}, f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_ADD,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
else begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ `SYSREG_PCR,
/* Source1 */ {{19{f_decode_inst[15]}}, f_decode_inst[15:10], f_decode_inst[4:0], 2'b0},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ f_decode_inst[9:5],
/* Write Back Enable */ 1'b1,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_ADD,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
end
/*******************
OS Support
*******************/
`OC_SWI :
begin //I11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ {5{1'b0}}, //none
/* Source1 */ {{21{1'b0}}, f_decode_inst[15:10], f_decode_inst[4:0]},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ `SYSREG_PCR,
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_BRANCH_SWI,
/* Execute Module */ `EXE_SELECT_BRANCH
};
end
`OC_IDTS :
begin //C
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ f_decode_inst[19:16],
/* Source0 */ f_decode_inst[9:5],
/* Source1 */ {32{1'b0}},
/* Source0 Use Flags*/ 1'b0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Displacement Data -> ADV */ 6'h0,
/* Displacement Data -> ADV Enable */ 1'b0,
/* Destination */ {5{1'b0}},
/* Write Back Enable */ 1'b0,
/* Make Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_BRANCH_IDTS,
/* Execute Module */ `EXE_SELECT_BRANCH
};
end
//Error
default :
begin
f_decode = {1'b1, {81{1'b0}}};
/*
$display("Instruction Error : Decoder > Not Match Instruction(TIME:%t, Line0 Valid0:%d, Line1 Valid:%d)", $stime, iPREVIOUS_0_INST_VALID, iPREVIOUS_1_INST_VALID);
*/
end
endcase
end
endfunction
assign {
oINF_ERROR,
oDECODE_FRONT_COMMIT_WAIT,
oDECODE_CC_AFE,
oDECODE_SOURCE0,
oDECODE_SOURCE1,
oDECODE_SOURCE0_FLAGS,
oDECODE_SOURCE1_IMM,
oDECODE_SOURCE0_ACTIVE,
oDECODE_SOURCE1_ACTIVE,
oDECODE_SOURCE0_SYSREG,
oDECODE_SOURCE1_SYSREG,
oDECODE_SOURCE0_SYSREG_RENAME,
oDECODE_SOURCE1_SYSREG_RENAME,
oDECODE_ADV_DATA,
oDECODE_ADV_ACTIVE,
oDECODE_DESTINATION,
oDECODE_WRITEBACK,
oDECODE_FLAGS_WRITEBACK,
oDECODE_DESTINATION_SYSREG,
oDECODE_DEST_RENAME,
oDECODE_CMD,
oDECODE_EX_SYS_REG,
oDECODE_EX_SYS_LDST,
oDECODE_EX_LOGIC,
oDECODE_EX_SHIFT,
oDECODE_EX_ADDER,
oDECODE_EX_SDIV,
oDECODE_EX_UDIV,
oDECODE_EX_MUL,
oDECODE_EX_LDST,
oDECODE_EX_BRANCH
} = f_decode(iINSTLUCTION);
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EBUFN_2_V
`define SKY130_FD_SC_MS__EBUFN_2_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__ebufn_2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__ebufn_2 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__EBUFN_2_V
|
/* ****************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: execute to control stage signal passing
Generate valid signal when stage is done
Copyright (C) 2012 Authors
Author(s): Julius Baxter <[email protected]>
Stefan Kristiansson <[email protected]>
***************************************************************************** */
`include "mor1kx-defines.v"
module mor1kx_execute_ctrl_cappuccino
#(
parameter OPTION_OPERAND_WIDTH = 32,
parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}},
`OR1K_RESET_VECTOR,8'd0},
parameter OPTION_RF_ADDR_WIDTH = 5,
parameter FEATURE_FPU = "NONE", // ENABLED|NONE
parameter FEATURE_MULTIPLIER = "THREESTAGE"
)
(
input clk,
input rst,
input padv_i,
input padv_ctrl_i,
input execute_except_ibus_err_i,
input execute_except_itlb_miss_i,
input execute_except_ipagefault_i,
input execute_except_illegal_i,
input execute_except_ibus_align_i,
input execute_except_syscall_i,
input lsu_except_dbus_i,
input lsu_except_align_i,
input lsu_except_dtlb_miss_i,
input lsu_except_dpagefault_i,
input execute_except_trap_i,
input pipeline_flush_i,
input op_mul_i,
input op_lsu_load_i,
input op_lsu_store_i,
input op_lsu_atomic_i,
input [1:0] lsu_length_i,
input lsu_zext_i,
input op_msync_i,
input op_mfspr_i,
input op_mtspr_i,
input alu_valid_i,
input lsu_valid_i,
input msync_stall_i,
input op_jr_i,
input op_jal_i,
input op_rfe_i,
input [OPTION_OPERAND_WIDTH-1:0] alu_result_i,
input [OPTION_OPERAND_WIDTH-1:0] adder_result_i,
input [OPTION_OPERAND_WIDTH-1:0] rfb_i,
input [OPTION_OPERAND_WIDTH-1:0] execute_jal_result_i,
input flag_set_i,
input flag_clear_i,
input carry_set_i,
input carry_clear_i,
input overflow_set_i,
input overflow_clear_i,
input [`OR1K_FPCSR_WIDTH-1:0] fpcsr_i,
input fpcsr_set_i,
input [OPTION_OPERAND_WIDTH-1:0] pc_execute_i,
input execute_rf_wb_i,
output reg ctrl_rf_wb_o,
output reg wb_rf_wb_o,
// address of destination register from execute stage
input [OPTION_RF_ADDR_WIDTH-1:0] execute_rfd_adr_i,
output reg [OPTION_RF_ADDR_WIDTH-1:0] ctrl_rfd_adr_o,
output reg [OPTION_RF_ADDR_WIDTH-1:0] wb_rfd_adr_o,
input execute_bubble_i,
// Input from control stage for mfspr/mtspr ack
input ctrl_mfspr_ack_i,
input ctrl_mtspr_ack_i,
output reg [OPTION_OPERAND_WIDTH-1:0] ctrl_alu_result_o,
output reg [OPTION_OPERAND_WIDTH-1:0] ctrl_lsu_adr_o,
output reg [OPTION_OPERAND_WIDTH-1:0] ctrl_rfb_o,
output reg ctrl_flag_set_o,
output reg ctrl_flag_clear_o,
output reg ctrl_carry_set_o,
output reg ctrl_carry_clear_o,
output reg ctrl_overflow_set_o,
output reg ctrl_overflow_clear_o,
output reg [`OR1K_FPCSR_WIDTH-1:0] ctrl_fpcsr_o,
output reg ctrl_fpcsr_set_o,
output reg [OPTION_OPERAND_WIDTH-1:0] pc_ctrl_o,
output reg ctrl_op_mul_o,
output reg ctrl_op_lsu_load_o,
output reg ctrl_op_lsu_store_o,
output reg ctrl_op_lsu_atomic_o,
output reg [1:0] ctrl_lsu_length_o,
output reg ctrl_lsu_zext_o,
output reg ctrl_op_msync_o,
output reg ctrl_op_mfspr_o,
output reg ctrl_op_mtspr_o,
output reg ctrl_op_rfe_o,
output reg ctrl_except_ibus_err_o,
output reg ctrl_except_itlb_miss_o,
output reg ctrl_except_ipagefault_o,
output reg ctrl_except_ibus_align_o,
output reg ctrl_except_illegal_o,
output reg ctrl_except_syscall_o,
output reg ctrl_except_dbus_o,
output reg ctrl_except_dtlb_miss_o,
output reg ctrl_except_dpagefault_o,
output reg ctrl_except_align_o,
output reg ctrl_except_trap_o,
output execute_valid_o,
output ctrl_valid_o
);
wire ctrl_stall;
wire execute_stall;
// LSU or MTSPR/MFSPR can stall from ctrl stage
assign ctrl_stall = (ctrl_op_lsu_load_o | ctrl_op_lsu_store_o) &
!lsu_valid_i |
ctrl_op_msync_o & msync_stall_i |
ctrl_op_mfspr_o & !ctrl_mfspr_ack_i |
ctrl_op_mtspr_o & !ctrl_mtspr_ack_i;
assign ctrl_valid_o = !ctrl_stall;
// Execute stage can be stalled from ctrl stage and by ALU
assign execute_stall = ctrl_stall | !alu_valid_i;
assign execute_valid_o = !execute_stall;
always @(posedge clk `OR_ASYNC_RST)
if (rst) begin
ctrl_except_ibus_err_o <= 0;
ctrl_except_itlb_miss_o <= 0;
ctrl_except_ipagefault_o <= 0;
ctrl_except_ibus_align_o <= 0;
ctrl_except_illegal_o <= 0;
ctrl_except_syscall_o <= 0;
ctrl_except_trap_o <= 0;
ctrl_except_dbus_o <= 0;
ctrl_except_align_o <= 0;
end
else if (pipeline_flush_i) begin
ctrl_except_ibus_err_o <= 0;
ctrl_except_itlb_miss_o <= 0;
ctrl_except_ipagefault_o <= 0;
ctrl_except_ibus_align_o <= 0;
ctrl_except_illegal_o <= 0;
ctrl_except_syscall_o <= 0;
ctrl_except_trap_o <= 0;
ctrl_except_dbus_o <= 0;
ctrl_except_align_o <= 0;
end
else begin
if (padv_i) begin
ctrl_except_ibus_err_o <= execute_except_ibus_err_i;
ctrl_except_itlb_miss_o <= execute_except_itlb_miss_i;
ctrl_except_ipagefault_o <= execute_except_ipagefault_i;
ctrl_except_ibus_align_o <= execute_except_ibus_align_i;
ctrl_except_illegal_o <= execute_except_illegal_i;
ctrl_except_syscall_o <= execute_except_syscall_i;
ctrl_except_trap_o <= execute_except_trap_i;
end
ctrl_except_dbus_o <= lsu_except_dbus_i;
ctrl_except_align_o <= lsu_except_align_i;
ctrl_except_dtlb_miss_o <= lsu_except_dtlb_miss_i;
ctrl_except_dpagefault_o <= lsu_except_dpagefault_i;
end
always @(posedge clk)
if (padv_i)
if (op_jal_i)
ctrl_alu_result_o <= execute_jal_result_i;
else
ctrl_alu_result_o <= alu_result_i;
always @(posedge clk)
if (padv_i & (op_lsu_store_i | op_lsu_load_i))
ctrl_lsu_adr_o <= adder_result_i;
always @(posedge clk)
if (padv_i)
ctrl_rfb_o <= rfb_i;
always @(posedge clk `OR_ASYNC_RST)
if (rst) begin
ctrl_flag_set_o <= 0;
ctrl_flag_clear_o <= 0;
ctrl_carry_set_o <= 0;
ctrl_carry_clear_o <= 0;
ctrl_overflow_set_o <= 0;
ctrl_overflow_clear_o <= 0;
end
else if (padv_i) begin
ctrl_flag_set_o <= flag_set_i;
ctrl_flag_clear_o <= flag_clear_i;
ctrl_carry_set_o <= carry_set_i;
ctrl_carry_clear_o <= carry_clear_i;
ctrl_overflow_set_o <= overflow_set_i;
ctrl_overflow_clear_o <= overflow_clear_i;
end
// pc_ctrl should not advance when a nop bubble moves from execute to
// ctrl/mem stage
always @(posedge clk `OR_ASYNC_RST)
if (rst)
pc_ctrl_o <= OPTION_RESET_PC;
else if (padv_i & !execute_bubble_i)
pc_ctrl_o <= pc_execute_i;
//
// The pipeline flush comes when the instruction that has caused
// an exception or the instruction that has been interrupted is in
// ctrl stage, so the padv_execute signal has to have higher prioity
// than the pipeline flush in order to not accidently kill a valid
// instruction coming in from execute stage.
//
generate
if (FEATURE_MULTIPLIER=="PIPELINED") begin
always @(posedge clk `OR_ASYNC_RST)
if (rst)
ctrl_op_mul_o <= 0;
else if (padv_i)
ctrl_op_mul_o <= op_mul_i;
else if (pipeline_flush_i)
ctrl_op_mul_o <= 0;
end else begin
always @(posedge clk)
ctrl_op_mul_o <= 0;
end
endgenerate
// FPU related
generate
/* verilator lint_off WIDTH */
if (FEATURE_FPU!="NONE") begin : fpu_execute_ctrl_ena
/* verilator lint_on WIDTH */
always @(posedge clk `OR_ASYNC_RST) begin
if (rst) begin
ctrl_fpcsr_o <= {`OR1K_FPCSR_WIDTH{1'b0}};
ctrl_fpcsr_set_o <= 0;
end else if (pipeline_flush_i) begin
ctrl_fpcsr_o <= {`OR1K_FPCSR_WIDTH{1'b0}};
ctrl_fpcsr_set_o <= 0;
end else if (padv_i) begin
ctrl_fpcsr_o <= fpcsr_i;
ctrl_fpcsr_set_o <= fpcsr_set_i;
end
end // @clk
end
else begin : fpu_execute_ctrl_none
always @(posedge clk `OR_ASYNC_RST) begin
if (rst) begin
ctrl_fpcsr_o <= {`OR1K_FPCSR_WIDTH{1'b0}};
ctrl_fpcsr_set_o <= 0;
end
end // @clk
end
endgenerate // FPU related
always @(posedge clk `OR_ASYNC_RST)
if (rst) begin
ctrl_op_mfspr_o <= 0;
ctrl_op_mtspr_o <= 0;
end else if (padv_i) begin
ctrl_op_mfspr_o <= op_mfspr_i;
ctrl_op_mtspr_o <= op_mtspr_i;
end else if (pipeline_flush_i) begin
ctrl_op_mfspr_o <= 0;
ctrl_op_mtspr_o <= 0;
end
always @(posedge clk `OR_ASYNC_RST)
if (rst)
ctrl_op_rfe_o <= 0;
else if (padv_i)
ctrl_op_rfe_o <= op_rfe_i;
else if (pipeline_flush_i)
ctrl_op_rfe_o <= 0;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
ctrl_op_msync_o <= 0;
else if (padv_i)
ctrl_op_msync_o <= op_msync_i;
else if (pipeline_flush_i)
ctrl_op_msync_o <= 0;
always @(posedge clk `OR_ASYNC_RST)
if (rst) begin
ctrl_op_lsu_load_o <= 0;
ctrl_op_lsu_store_o <= 0;
ctrl_op_lsu_atomic_o <= 0;
end else if (ctrl_except_align_o | ctrl_except_dbus_o |
ctrl_except_dtlb_miss_o | ctrl_except_dpagefault_o) begin
ctrl_op_lsu_load_o <= 0;
ctrl_op_lsu_store_o <= 0;
ctrl_op_lsu_atomic_o <= 0;
end else if (padv_i) begin
ctrl_op_lsu_load_o <= op_lsu_load_i;
ctrl_op_lsu_store_o <= op_lsu_store_i;
ctrl_op_lsu_atomic_o <= op_lsu_atomic_i;
end else if (pipeline_flush_i) begin
ctrl_op_lsu_load_o <= 0;
ctrl_op_lsu_store_o <= 0;
ctrl_op_lsu_atomic_o <= 0;
end
always @(posedge clk)
if (padv_i) begin
ctrl_lsu_length_o <= lsu_length_i;
ctrl_lsu_zext_o <= lsu_zext_i;
end
always @(posedge clk `OR_ASYNC_RST)
if (rst)
ctrl_rf_wb_o <= 0;
else if (padv_i)
ctrl_rf_wb_o <= execute_rf_wb_i;
else if (ctrl_op_mfspr_o & ctrl_mfspr_ack_i |
ctrl_op_lsu_load_o & lsu_valid_i)
// Deassert the write enable when the "bus" access is done, to avoid:
// 1) Writing multiple times to RF
// 2) Signaling a need to bypass from control stage, when it really
// should be a bypass from wb stage.
ctrl_rf_wb_o <= 0;
else if (pipeline_flush_i)
ctrl_rf_wb_o <= 0;
always @(posedge clk)
if (padv_i)
ctrl_rfd_adr_o <= execute_rfd_adr_i;
// load and mfpsr can stall from ctrl stage, so we have to hold off the
// write back on them
always @(posedge clk `OR_ASYNC_RST)
if (rst)
wb_rf_wb_o <= 0;
else if (pipeline_flush_i)
wb_rf_wb_o <= 0;
else if (ctrl_op_mfspr_o)
wb_rf_wb_o <= ctrl_rf_wb_o & ctrl_mfspr_ack_i;
else if (ctrl_op_lsu_load_o)
wb_rf_wb_o <= ctrl_rf_wb_o & lsu_valid_i;
else
wb_rf_wb_o <= ctrl_rf_wb_o & padv_ctrl_i;
always @(posedge clk)
wb_rfd_adr_o <= ctrl_rfd_adr_o;
endmodule // mor1kx_execute_ctrl_cappuccino
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module dpram(wclk,wdata,waddr,wen,rclk,rdata,raddr);
parameter depth = 4;
parameter width = 16;
parameter size = 16;
input wclk;
input [width-1:0] wdata;
input [depth-1:0] waddr;
input wen;
input rclk;
output reg [width-1:0] rdata;
input [depth-1:0] raddr;
reg [width-1:0] ram [0:size-1];
always @(posedge wclk)
if(wen)
ram[waddr] <= #1 wdata;
always @(posedge rclk)
rdata <= #1 ram[raddr];
endmodule // dpram
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [1:0] in = crc[1:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[1:0]),
// Inputs
.in (in[1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {62'h0, out};
// What checksum will we end up with
`define EXPECTED_SUM 64'hbb2d9709592f64bd
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [1:0] in;
output reg [1:0] out;
always @* begin
// bug99: Internal Error: ../V3Ast.cpp:495: New node already linked?
case (in[1:0])
2'd0, 2'd1, 2'd2, 2'd3: begin
out = in;
end
endcase
end
endmodule
|
// This top level module chooses between the original Altera-ST JTAG Interface
// component in ACDS version 8.1 and before, and the new one with the PLI
// Simulation mode turned on, which adds a wrapper over the original component.
`timescale 1 ns / 1 ns
module altera_avalon_st_jtag_interface (
clk,
reset_n,
source_ready,
source_data,
source_valid,
sink_data,
sink_valid,
sink_ready,
resetrequest,
debug_reset,
mgmt_valid,
mgmt_channel,
mgmt_data
);
input clk;
input reset_n;
output [7:0] source_data;
input source_ready;
output source_valid;
input [7:0] sink_data;
input sink_valid;
output sink_ready;
output resetrequest;
output debug_reset;
output mgmt_valid;
output mgmt_data;
parameter PURPOSE = 0; // for discovery of services behind this JTAG Phy - 0
// for JTAG Phy, 1 for Packets to Master
parameter UPSTREAM_FIFO_SIZE = 0;
parameter DOWNSTREAM_FIFO_SIZE = 0;
parameter MGMT_CHANNEL_WIDTH = -1;
parameter USE_PLI = 0; // set to 1 enable PLI Simulation Mode
parameter PLI_PORT = 50000; // PLI Simulation Port
output [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel;
wire clk;
wire resetrequest;
wire [7:0] source_data;
wire source_ready;
wire source_valid;
wire [7:0] sink_data;
wire sink_valid;
wire sink_ready;
generate
if (USE_PLI == 0)
begin : normal
altera_jtag_dc_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_dc_streaming (
.clk(clk),
.reset_n(reset_n),
.source_data(source_data),
.source_valid(source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(sink_ready),
.resetrequest(resetrequest),
.debug_reset(debug_reset),
.mgmt_valid(mgmt_valid),
.mgmt_channel(mgmt_channel),
.mgmt_data(mgmt_data)
);
end
else
begin : pli_mode
altera_pli_streaming #(.PURPOSE(PURPOSE), .PLI_PORT(PLI_PORT)) pli_streaming (
.clk(clk),
.reset_n(reset_n),
.source_data(source_data),
.source_valid(source_valid),
.source_ready(source_ready),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(sink_ready),
.resetrequest(resetrequest)
);
end
endgenerate
endmodule
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_mac_pcs.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_mac_pcs.v,v $
//
// $Revision: #1 $
// $Date: 2010/04/12 $
// Check in by : $Author: max $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet
//
// Description :
//
// Top level module for Triple Speed Ethernet MAC + PCS
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_mac_pcs /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
clk, // Avalon slave - clock
read, // Avalon slave - read
write, // Avalon slave - write
address, // Avalon slave - address
writedata, // Avalon slave - writedata
readdata, // Avalon slave - readdata
waitrequest, // Avalon slave - waitrequest
reset, // Avalon slave - reset
reset_rx_clk,
reset_tx_clk,
reset_ff_rx_clk,
reset_ff_tx_clk,
ff_rx_clk, // AtlanticII source - clk
ff_rx_data, // AtlanticII source - data
ff_rx_mod, // Will not exists in SoPC Model as the 8-bit version is used
ff_rx_sop, // AtlanticII source - startofpacket
ff_rx_eop, // AtlanticII source - endofpacket
rx_err, // AtlanticII source - error
rx_err_stat, // AtlanticII source - component_specific_signal(eop)
rx_frm_type, // AtlanticII source - component_specific_signal(data)
ff_rx_rdy, // AtlanticII source - ready
ff_rx_dval, // AtlanticII source - valid
ff_rx_dsav, // Will not exists in SoPC Model (leave unconnected)
ff_tx_clk, // AtlanticII sink - clk
ff_tx_data, // AtlanticII sink - data
ff_tx_mod, // Will not exists in SoPC Model as the 8-bit version is used
ff_tx_sop, // AtlanticII sink - startofpacket
ff_tx_eop, // AtlanticII sink - endofpacket
ff_tx_err, // AtlanticII sink - error
ff_tx_wren, // AtlanticII sink - valid
ff_tx_crc_fwd, // AtlanticII sink - component_specific_signal(eop)
ff_tx_rdy, // AtlanticII sink - ready
ff_tx_septy, // Will not exists in SoPC Model (leave unconnected)
tx_ff_uflow, // Will not exists in SoPC Model (leave unconnected)
ff_rx_a_full,
ff_rx_a_empty,
ff_tx_a_full,
ff_tx_a_empty,
xoff_gen,
xon_gen,
magic_sleep_n,
magic_wakeup,
mdc,
mdio_in,
mdio_out,
mdio_oen,
tbi_rx_clk,
tbi_tx_clk,
tbi_rx_d,
tbi_tx_d,
sd_loopback,
powerdown,
led_col,
led_an,
led_char_err,
led_disp_err,
led_crs,
led_link
);
parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1; // ENA_HASH Enable Hash Table
parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
parameter EG_FIFO = 256 ; // Egress FIFO Depth
parameter EG_ADDR = 8 ; // Egress FIFO Depth
parameter ING_FIFO = 256 ; // Ingress FIFO Depth
parameter ING_ADDR = 8 ; // Egress FIFO Depth
parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3; // ALTERA Core Version
parameter CUST_VERSION = 1 ; // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 0; // Enable the RGMII / MII Interface
parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
parameter ENABLE_MIN_FIFO = 1; // Enable minimun FIFO (Reduced functionality)
parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
parameter RAM_TYPE = "AUTO"; // Specify the RAM type
parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
parameter PHY_IDENTIFIER = 32'h 00000000;
parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
input clk; // 25MHz Host Interface Clock
input read; // Register Read Strobe
input write; // Register Write Strobe
input [7:0] address; // Register Address
input [31:0] writedata; // Write Data for Host Bus
output [31:0] readdata; // Read Data to Host Bus
output waitrequest; // Interface Busy
input reset; // Asynchronous Reset
input reset_rx_clk; // Asynchronous Reset - rx_clk Domain
input reset_tx_clk; // Asynchronous Reset - tx_clk Domain
input reset_ff_rx_clk; // Asynchronous Reset - ff_rx_clk Domain
input reset_ff_tx_clk; // Asynchronous Reset - ff_tx_clk Domain
input ff_rx_clk; // Transmit Local Clock
output [ENABLE_ENA-1:0] ff_rx_data; // Data Out
output [1:0] ff_rx_mod; // Data Modulo
output ff_rx_sop; // Start of Packet
output ff_rx_eop; // End of Packet
output [5:0] rx_err; // Errored Packet Indication
output [17:0] rx_err_stat; // Packet Length and Status Word
output [3:0] rx_frm_type; // Unicast Frame Indication
input ff_rx_rdy; // PHY Application Ready
output ff_rx_dval; // Data Valid Strobe
output ff_rx_dsav; // Data Available
input ff_tx_clk; // Transmit Local Clock
input [ENABLE_ENA-1:0] ff_tx_data; // Data Out
input [1:0] ff_tx_mod; // Data Modulo
input ff_tx_sop; // Start of Packet
input ff_tx_eop; // End of Packet
input ff_tx_err; // Errored Packet
input ff_tx_wren; // Write Enable
input ff_tx_crc_fwd; // Forward Current Frame with CRC from Application
output ff_tx_rdy; // FIFO Ready
output ff_tx_septy; // FIFO has space for at least one section
output tx_ff_uflow; // TX FIFO underflow occured (Synchronous with tx_clk)
output ff_rx_a_full; // Receive FIFO Almost Full
output ff_rx_a_empty; // Receive FIFO Almost Empty
output ff_tx_a_full; // Transmit FIFO Almost Full
output ff_tx_a_empty; // Transmit FIFO Almost Empty
input xoff_gen; // Xoff Pause frame generate
input xon_gen; // Xon Pause frame generate
input magic_sleep_n; // Enable Sleep Mode
output magic_wakeup; // Wake Up Request
output mdc; // 2.5MHz Inteface
input mdio_in; // MDIO Input
output mdio_out; // MDIO Output
output mdio_oen; // MDIO Output Enable
input tbi_rx_clk; // 125MHz Recoved Clock
input tbi_tx_clk; // 125MHz Transmit Clock
input [9:0] tbi_rx_d; // Non Aligned 10-Bit Characters
output [9:0] tbi_tx_d; // Transmit TBI Interface
output sd_loopback; // SERDES Loopback Enable
output powerdown; // Powerdown Enable
output led_crs; // Carrier Sense
output led_link; // Valid Link
output led_col; // Collision Indication
output led_an; // Auto-Negotiation Status
output led_char_err; // Character Error
output led_disp_err; // Disparity Error
wire [31:0] reg_data_out;
wire reg_busy;
wire [ENABLE_ENA-1:0] ff_rx_data;
wire [1:0] ff_rx_mod;
wire ff_rx_sop;
wire ff_rx_eop;
wire ff_rx_dval;
wire ff_rx_dsav;
wire ff_tx_rdy;
wire ff_tx_septy;
wire tx_ff_uflow;
wire magic_wakeup;
wire ff_rx_a_full;
wire ff_rx_a_empty;
wire ff_tx_a_full;
wire ff_tx_a_empty;
wire mdc;
wire mdio_out;
wire mdio_oen;
wire [9:0] tbi_tx_d;
wire sd_loopback;
wire powerdown;
wire led_crs;
wire led_link;
wire led_col;
wire led_an;
wire led_char_err;
wire led_disp_err;
wire rx_clk;
wire tx_clk;
wire rx_clkena;
wire tx_clkena;
wire [7:0] gm_rx_d; // GMII Receive Data
wire gm_rx_dv; // GMII Receive Frame Enable
wire gm_rx_err; // GMII Receive Frame Error
wire [7:0] gm_tx_d; // GMII Transmit Data
wire gm_tx_en; // GMII Transmit Frame Enable
wire gm_tx_err; // GMII Transmit Frame Error
wire [3:0] m_rx_d; // MII Receive Data
wire m_rx_dv; // MII Receive Frame Enable
wire m_rx_err; // MII Receive Drame Error
wire [3:0] m_tx_d; // MII Transmit Data
wire m_tx_en; // MII Transmit Frame Enable
wire m_tx_err; // MII Transmit Frame Error
wire m_rx_crs; // Carrier Sense
wire m_rx_col; // Collition
wire set_1000; // Gigabit Mode Enable
wire set_10; // 10Mbps Mode Enable
wire pcs_en;
wire [31:0]readdata_mac;
wire waitrequest_mac;
wire [31:0]readdata_pcs;
wire waitrequest_pcs;
wire write_pcs;
wire read_pcs;
wire write_mac;
wire read_mac;
wire [5:0] rx_err;
wire [17:0] rx_err_stat;
wire [3:0] rx_frm_type;
// Reset Lines
// -----------
wire reset_rx_clk_int; // Asynchronous Reset - rx_clk Domain
wire reset_tx_clk_int; // Asynchronous Reset - tx_clk Domain
wire reset_ff_rx_clk_int; // Asynchronous Reset - ff_rx_clk Domain
wire reset_ff_tx_clk_int; // Asynchronous Reset - ff_tx_clk Domain
wire reset_reg_clk_int; // Asynchronous Reset - reg_clk Domain
// This is done because the PCS address space is from 0x80 to 0x9F
// ---------------------------------------------------------------
assign pcs_en = address[7] & !address[6] & !address[5];
assign write_pcs = pcs_en? write : 1'b0;
assign read_pcs = pcs_en? read : 1'b0;
assign write_mac = pcs_en? 1'b0 : write;
assign read_mac = pcs_en? 1'b0 : read;
assign readdata = pcs_en? readdata_pcs : readdata_mac;
assign waitrequest = pcs_en? waitrequest_pcs : waitrequest_mac;
assign readdata_pcs[31:16] = {16{1'b0}};
// Programmable Reset Options
// --------------------------
generate if (USE_SYNC_RESET == 1)
begin
assign reset_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset_rx_clk : !reset_rx_clk ;
assign reset_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset_tx_clk : !reset_tx_clk ;
assign reset_ff_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset_ff_rx_clk : !reset_ff_rx_clk ;
assign reset_ff_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset_ff_tx_clk : !reset_ff_tx_clk ;
assign reset_reg_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
end
else
begin
assign reset_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_ff_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_ff_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_reg_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
end
endgenerate
// --------------------------
altera_tse_top_gen_host top_gen_host_inst(
.reset_ff_rx_clk(reset_ff_rx_clk_int),
.reset_ff_tx_clk(reset_ff_tx_clk_int),
.reset_reg_clk(reset_reg_clk_int),
.reset_rx_clk(reset_rx_clk_int),
.reset_tx_clk(reset_tx_clk_int),
.rx_clk(rx_clk),
.tx_clk(tx_clk),
.rx_clkena(rx_clkena),
.tx_clkena(tx_clkena),
.gm_rx_dv(gm_rx_dv),
.gm_rx_d(gm_rx_d),
.gm_rx_err(gm_rx_err),
.m_rx_en(m_rx_dv),
.m_rx_d(m_rx_d),
.m_rx_err(m_rx_err),
.m_rx_col(m_rx_col),
.m_rx_crs(m_rx_crs),
.set_1000(set_1000),
.set_10(set_10),
.ff_rx_clk(ff_rx_clk),
.ff_rx_rdy(ff_rx_rdy),
.ff_tx_clk(ff_tx_clk),
.ff_tx_wren(ff_tx_wren),
.ff_tx_data(ff_tx_data),
.ff_tx_mod(ff_tx_mod),
.ff_tx_sop(ff_tx_sop),
.ff_tx_eop(ff_tx_eop),
.ff_tx_err(ff_tx_err),
.ff_tx_crc_fwd(ff_tx_crc_fwd),
.reg_clk(clk),
.reg_addr(address),
.reg_data_in(writedata),
.reg_rd(read_mac),
.reg_wr(write_mac),
.mdio_in(mdio_in),
.gm_tx_en(gm_tx_en),
.gm_tx_d(gm_tx_d),
.gm_tx_err(gm_tx_err),
.m_tx_en(m_tx_en),
.m_tx_d(m_tx_d),
.m_tx_err(m_tx_err),
.eth_mode(),
.ena_10(),
.ff_rx_dval(ff_rx_dval),
.ff_rx_data(ff_rx_data),
.ff_rx_mod(ff_rx_mod),
.ff_rx_sop(ff_rx_sop),
.ff_rx_eop(ff_rx_eop),
.ff_rx_dsav(ff_rx_dsav),
.rx_err(rx_err),
.rx_err_stat(rx_err_stat),
.rx_frm_type(rx_frm_type),
.ff_tx_rdy(ff_tx_rdy),
.ff_tx_septy(ff_tx_septy),
.tx_ff_uflow(tx_ff_uflow),
.rx_a_full(ff_rx_a_full),
.rx_a_empty(ff_rx_a_empty),
.tx_a_full(ff_tx_a_full),
.tx_a_empty(ff_tx_a_empty),
.xoff_gen(xoff_gen),
.xon_gen(xon_gen),
.reg_data_out(readdata_mac),
.reg_busy(waitrequest_mac),
.reg_sleepN(magic_sleep_n),
.reg_wakeup(magic_wakeup),
.mdc(mdc),
.mdio_out(mdio_out),
.mdio_oen(mdio_oen));
defparam
top_gen_host_inst.EG_FIFO = EG_FIFO,
top_gen_host_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
top_gen_host_inst.CORE_VERSION = CORE_VERSION,
top_gen_host_inst.CRC32GENDELAY = CRC32GENDELAY,
top_gen_host_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
top_gen_host_inst.EG_ADDR = EG_ADDR,
top_gen_host_inst.ENA_HASH = ENA_HASH,
top_gen_host_inst.STAT_CNT_ENA = STAT_CNT_ENA,
top_gen_host_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
top_gen_host_inst.ING_FIFO = ING_FIFO,
top_gen_host_inst.ENABLE_ENA = ENABLE_ENA,
top_gen_host_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
top_gen_host_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
top_gen_host_inst.ENABLE_MDIO = ENABLE_MDIO,
top_gen_host_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
top_gen_host_inst.ENABLE_MIN_FIFO = ENABLE_MIN_FIFO,
top_gen_host_inst.ENABLE_PADDING = !ENABLE_MACLITE,
top_gen_host_inst.ENABLE_LGTH_CHECK = !ENABLE_MACLITE,
top_gen_host_inst.GBIT_ONLY = !ENABLE_MACLITE | MACLITE_GIGE,
top_gen_host_inst.MBIT_ONLY = !ENABLE_MACLITE | !MACLITE_GIGE,
top_gen_host_inst.REDUCED_CONTROL = ENABLE_MACLITE,
top_gen_host_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
top_gen_host_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
top_gen_host_inst.ING_ADDR = ING_ADDR,
top_gen_host_inst.CRC32DWIDTH = CRC32DWIDTH,
top_gen_host_inst.CUST_VERSION = CUST_VERSION,
top_gen_host_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
top_gen_host_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
top_gen_host_inst.INSERT_TA = INSERT_TA,
top_gen_host_inst.RAM_TYPE = RAM_TYPE,
top_gen_host_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
top_gen_host_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
top_gen_host_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
top_gen_host_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
top_gen_host_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
altera_tse_top_1000_base_x top_1000_base_x_inst(
.reset_rx_clk(reset_rx_clk_int),
.reset_tx_clk(reset_tx_clk_int),
.reset_reg_clk(reset_reg_clk_int),
.rx_clk(rx_clk),
.tx_clk(tx_clk),
.rx_clkena(rx_clkena),
.tx_clkena(tx_clkena),
.ref_clk(1'b0),
.gmii_rx_dv(gm_rx_dv),
.gmii_rx_d(gm_rx_d),
.gmii_rx_err(gm_rx_err),
.gmii_tx_en(gm_tx_en),
.gmii_tx_d(gm_tx_d),
.gmii_tx_err(gm_tx_err),
.mii_rx_dv(m_rx_dv),
.mii_rx_d(m_rx_d),
.mii_rx_err(m_rx_err),
.mii_tx_en(m_tx_en),
.mii_tx_d(m_tx_d),
.mii_tx_err(m_tx_err),
.mii_col(m_rx_col),
.mii_crs(m_rx_crs),
.tbi_rx_clk(tbi_rx_clk),
.tbi_tx_clk(tbi_tx_clk),
.tbi_rx_d(tbi_rx_d),
.tbi_tx_d(tbi_tx_d),
.sd_loopback(sd_loopback),
.reg_clk(clk),
.reg_rd(read_pcs),
.reg_wr(write_pcs),
.reg_addr(address[4:0]),
.reg_data_in(writedata[15:0]),
.reg_data_out(readdata_pcs[15:0]),
.reg_busy(waitrequest_pcs),
.powerdown(powerdown),
.set_10(set_10),
.set_100(),
.set_1000(set_1000),
.hd_ena(),
.led_col(led_col),
.led_an(led_an),
.led_char_err(led_char_err),
.led_disp_err(led_disp_err),
.led_crs(led_crs),
.led_link(led_link));
defparam
top_1000_base_x_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
top_1000_base_x_inst.DEV_VERSION = DEV_VERSION,
top_1000_base_x_inst.ENABLE_SGMII = ENABLE_SGMII;
endmodule
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Generic source synchronous SDR output
*/
module ssio_sdr_out #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Width of register in bits
parameter WIDTH = 1
)
(
input wire clk,
input wire [WIDTH-1:0] input_d,
output wire output_clk,
output wire [WIDTH-1:0] output_q
);
oddr #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(1)
)
clk_oddr_inst (
.clk(clk),
.d1(1'b0),
.d2(1'b1),
.q(output_clk)
);
(* IOB = "TRUE" *)
reg [WIDTH-1:0] output_q_reg = {WIDTH{1'b0}};
assign output_q = output_q_reg;
always @(posedge clk) begin
output_q_reg <= input_d;
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Manually created global mem, to avoid qsys hex generation bug
// qsys will always generate a .hex file to initialize the
// altsyncram - EVEN if you specify not to init the ram,
// for big ram's, this causes qsys to hang
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module bram_512x33M (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter DEPTH = 33554432;
parameter NWORDS_A = 33554432;
parameter ADDR_WIDTH = 25; // this should be $clog( DEPTH ), but qsys dies;
output [512: 0] readdata;
// ADDR_WIDTH
input [ 24: 0] address;
input [ 63: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [511: 0] writedata;
reg [511: 0] readdata;
wire [511: 0] readdata_ram;
wire wren;
always @(posedge clk)
begin
if (clken)
readdata <= readdata_ram;
end
assign wren = chipselect & write;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata_ram),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = "UNUSED",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = DEPTH,
the_altsyncram.numwords_a = NWORDS_A,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 512,
the_altsyncram.width_byteena_a = 64,
the_altsyncram.widthad_a = ADDR_WIDTH;
//////////////// END SIMULATION-ONLY CONTENTS
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_BLACKBOX_V
`define SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_BLACKBOX_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_pwrgood_pp$P (
UDP_OUT,
UDP_IN ,
VPWR
);
output UDP_OUT;
input UDP_IN ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_BLACKBOX_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_p_dst_data_stream_2_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_p_dst_data_stream_2_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_p_dst_data_stream_2_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_p_dst_data_stream_2_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFBBN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__SDFBBN_BEHAVIORAL_PP_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dfb_setdom_notify_pg/sky130_fd_sc_hs__u_dfb_setdom_notify_pg.v"
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`celldefine
module sky130_fd_sc_hs__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_N_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
not not2 (CLK , CLK_N_delayed );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_dfb_setdom_notify_pg u_dfb_setdom_notify_pg0 (buf_Q , SET, RESET, CLK, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFBBN_BEHAVIORAL_PP_V |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [15:0] m_din;
// We expect all these blocks should split;
// blocks that don't split should go in t_alw_nosplit.v
reg [15:0] a_split_1, a_split_2;
always @ (/*AS*/m_din) begin
a_split_1 = m_din;
a_split_2 = m_din;
end
reg [15:0] d_split_1, d_split_2;
always @ (posedge clk) begin
d_split_1 <= m_din;
d_split_2 <= d_split_1;
d_split_1 <= ~m_din;
end
reg [15:0] h_split_1;
reg [15:0] h_split_2;
always @ (posedge clk) begin
// $write(" cyc = %x m_din = %x\n", cyc, m_din);
if (cyc > 2) begin
if (m_din == 16'h0) begin
h_split_1 <= 16'h0;
h_split_2 <= 16'h0;
end
else begin
h_split_1 <= m_din;
h_split_2 <= ~m_din;
end
end
else begin
h_split_1 <= 16'h0;
h_split_2 <= 16'h0;
end
end
// (The checker block is an exception, it won't split.)
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==1) begin
m_din <= 16'hfeed;
end
if (cyc==3) begin
end
if (cyc==4) begin
m_din <= 16'he11e;
//$write(" A %x %x\n", a_split_1, a_split_2);
if (!(a_split_1==16'hfeed && a_split_2==16'hfeed)) $stop;
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop;
end
if (cyc==5) begin
m_din <= 16'he22e;
if (!(a_split_1==16'he11e && a_split_2==16'he11e)) $stop;
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop;
end
if (cyc==6) begin
m_din <= 16'he33e;
if (!(a_split_1==16'he22e && a_split_2==16'he22e)) $stop;
if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop;
if (!(h_split_1==16'he11e && h_split_2==16'h1ee1)) $stop;
end
if (cyc==7) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end // always @ (posedge clk)
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// NPCG_Toggle_MNC_getFT for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPCG_Toggle_MNC_getFT
// Module Name: NPCG_Toggle_MNC_getFT
// File Name: NPCG_Toggle_MNC_getFT.v
//
// Version: v1.0.0
//
// Description: Get feature execution FSM
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPCG_Toggle_MNC_N_init
#
(
parameter NumberOfWays = 4
)
(
iSystemClock ,
iReset ,
iOpcode ,
iTargetID ,
iSourceID ,
iCMDValid ,
oCMDReady ,
iWaySelect ,
oStart ,
oLastStep ,
iPM_Ready ,
iPM_LastStep ,
oPM_PCommand ,
oPM_PCommandOption ,
oPM_TargetWay ,
oPM_NumOfData ,
oPM_CASelect ,
oPM_CAData
);
input iSystemClock ;
input iReset ;
input [5:0] iOpcode ;
input [4:0] iTargetID ;
input [4:0] iSourceID ;
input iCMDValid ;
output oCMDReady ;
input [NumberOfWays - 1:0] iWaySelect ;
output oStart ;
output oLastStep ;
input [7:0] iPM_Ready ;
input [7:0] iPM_LastStep ;
output [7:0] oPM_PCommand ;
output [2:0] oPM_PCommandOption ;
output [NumberOfWays - 1:0] oPM_TargetWay ;
output [15:0] oPM_NumOfData ;
output oPM_CASelect ;
output [7:0] oPM_CAData ;
// FSM Parameters/Wires/Regs
localparam N_i_FSM_BIT = 6; // NAND initialization
localparam N_i_RESET = 6'b00_0001;
localparam N_i_READY = 6'b00_0010;
localparam N_i_00001 = 6'b00_0100; // capture, CAL start
localparam N_i_00002 = 6'b00_1000; // CA data
localparam N_i_00003 = 6'b01_0000; // Timer start ready, Timer Loop
localparam N_i_00004 = 6'b10_0000; // wait for request done
reg [N_i_FSM_BIT-1:0] r_N_i_cur_state ;
reg [N_i_FSM_BIT-1:0] r_N_i_nxt_state ;
// Internal Wires/Regs
reg [4:0] rSourceID ;
reg rCMDReady ;
reg [NumberOfWays - 1:0] rWaySelect ;
wire wLastStep ;
reg [7:0] rPM_PCommand ;
reg [2:0] rPM_PCommandOption ;
reg [15:0] rPM_NumOfData ;
reg rPM_CASelect ;
reg [7:0] rPM_CAData ;
wire wPCGStart ;
wire wCapture ;
wire wPMReady ;
wire wCALReady ;
wire wCALStart ;
wire wCALDone ;
wire wTMReady ;
wire wTMStart ;
wire wTMDone ;
reg [3:0] rTM_counter ;
wire wTM_LoopDone ;
// Control Signals
// Flow Contorl
assign wPCGStart = (iOpcode[5:0] == 6'b101100) & (iTargetID[4:0] == 5'b00101) & iCMDValid;
assign wCapture = (r_N_i_cur_state[N_i_FSM_BIT-1:0] == N_i_READY);
assign wPMReady = (iPM_Ready[5:0] == 6'b111111);
assign wCALReady = wPMReady;
assign wCALStart = wCALReady & rPM_PCommand[3];
assign wCALDone = iPM_LastStep[3];
assign wTMReady = wPMReady;
assign wTMStart = wTMReady & rPM_PCommand[0];
assign wTMDone = iPM_LastStep[0];
assign wTM_LoopDone = (rTM_counter[3:0] == 4'd10);
assign wLastStep = wTMDone & wTM_LoopDone & (r_N_i_cur_state[N_i_FSM_BIT-1:0] == N_i_00004);
// FSM: read STatus
// update current state to next state
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
r_N_i_cur_state <= N_i_RESET;
end else begin
r_N_i_cur_state <= r_N_i_nxt_state;
end
end
// deside next state
always @ ( * ) begin
case (r_N_i_cur_state)
N_i_RESET: begin
r_N_i_nxt_state <= N_i_READY;
end
N_i_READY: begin
r_N_i_nxt_state <= (wPCGStart)? N_i_00001:N_i_READY;
end
N_i_00001: begin
r_N_i_nxt_state <= (wCALStart)? N_i_00002:N_i_00001;
end
N_i_00002: begin
r_N_i_nxt_state <= N_i_00003;
end
N_i_00003: begin
r_N_i_nxt_state <= (wTM_LoopDone)? N_i_00004:N_i_00003;
end
N_i_00004: begin
r_N_i_nxt_state <= (wLastStep)? N_i_READY:N_i_00004;
end
default:
r_N_i_nxt_state <= N_i_READY;
endcase
end
// state behaviour
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
rSourceID[4:0] <= 0;
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= 0;
rPM_PCommand[7:0] <= 0;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 0;
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
rTM_counter[3:0] <= 0;
end else begin
case (r_N_i_nxt_state)
N_i_RESET: begin
rSourceID[4:0] <= 0;
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= 0;
rPM_PCommand[7:0] <= 0;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 0;
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
rTM_counter[3:0] <= 0;
end
N_i_READY: begin
rSourceID[4:0] <= 0;
rCMDReady <= 1;
rWaySelect[NumberOfWays - 1:0] <= 0;
rPM_PCommand[7:0] <= 0;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 0;
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
rTM_counter[3:0] <= 0;
end
N_i_00001: begin
rSourceID[4:0] <= (wCapture)? iSourceID[4:0]:rSourceID[4:0];
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= (wCapture)? iWaySelect[NumberOfWays - 1:0]:rWaySelect[NumberOfWays - 1:0];
rPM_PCommand[7:0] <= 8'b0000_1000;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 15'h0000;
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
rTM_counter[3:0] <= 0;
end
N_i_00002: begin
rSourceID[4:0] <= rSourceID[4:0];
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= rWaySelect[NumberOfWays - 1:0];
rPM_PCommand[7:0] <= 0;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 0;
rPM_CASelect <= 1'b0;
rPM_CAData[7:0] <= 8'hFF;
rTM_counter[3:0] <= 4'b0001;
end
N_i_00003: begin
rSourceID[4:0] <= rSourceID[4:0];
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= rWaySelect[NumberOfWays - 1:0];
rPM_PCommand[7:0] <= 8'b0000_0001;
rPM_PCommandOption[2:0] <= 3'b001; // CE on
rPM_NumOfData[15:0] <= 16'd50000; // real condition
//rPM_NumOfData[15:0] <= 16'd5; // test condition
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
rTM_counter[3:0] <= (wTMDone)? (rTM_counter[3:0] + 1'b1):(rTM_counter[3:0]);
end
N_i_00004: begin
rSourceID[4:0] <= rSourceID[4:0];
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= rWaySelect[NumberOfWays - 1:0];
rPM_PCommand[7:0] <= 8'b0000_0000;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 0;
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
rTM_counter[3:0] <= rTM_counter[3:0];
end
endcase
end
end
// Output
assign oCMDReady = rCMDReady;
assign oStart = wPCGStart;
assign oLastStep = wLastStep;
assign oPM_PCommand[7:0] = rPM_PCommand[7:0];
assign oPM_PCommandOption[2:0] = rPM_PCommandOption[2:0];
assign oPM_TargetWay[NumberOfWays - 1:0] = rWaySelect[NumberOfWays - 1:0];
assign oPM_NumOfData[15:0] = rPM_NumOfData[15:0];
assign oPM_CASelect = rPM_CASelect;
assign oPM_CAData[7:0] = rPM_CAData[7:0];
endmodule
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// A clock divider circuit.
// Division is based on the parameters, where
// Division is upper - lower + 1
// Duty cycle is :
// let half = 1 << (width-1)
// (upper - half) / upper - lower + 1
// E.g., (2,1,3) is a divide by 3 duty cycle 2/3
// (2,0,3) is a divide by 4 duty cycle 2/4
// (1,0,1) is a divide by 2, duty cycle 1/2
// (3,1,5) is a divide by 5 duty cycle 2/5
// (3,2,6) is a divide by 5 duty cycle 3/5
// The offset allow edges for seperate modules to be determined
// relative to each other. a clock divider with offset 1 occurs one
// (fast) clock later than a clock with offset 0.
module ClockDiv(CLK_IN, RST_N, PREEDGE, CLK_OUT);
parameter width = 2 ; // must be sufficient to hold upper
parameter lower = 1 ; //
parameter upper = 3 ;
parameter offset = 0; // offset for relative edges.
// (0 <= offset <= (upper - lower)
input CLK_IN; // input clock
input RST_N;
output PREEDGE; // output signal announcing an upcoming edge
output CLK_OUT; // output clock
reg [ width -1 : 0 ] cntr ;
reg PREEDGE ;
// Wire constants for the parameters
wire [width-1:0] upper_w ;
wire [width-1:0] lower_w ;
assign CLK_OUT = cntr[width-1] ;
assign upper_w = upper ;
assign lower_w = lower ;
// The clock is about to tick when counter is about to set its msb
// Note some simulators do not allow 0 width expressions
wire [width-1:0] nexttick = ~ ( 'b01 << (width-1) ) ;
// Combinational block to generate next edge signal
always@( cntr or nexttick )
begin
#0
// The nonblocking assignment use to delay the update of the edge ready signal
// Since this read by other always blocks trigger by the output CLK of this module
PREEDGE <= `BSV_ASSIGNMENT_DELAY (cntr == nexttick) ;
end
always@( posedge CLK_IN or negedge RST_N )
begin
// The use of blocking assignment within this block insures
// that the clock generated from cntr[MSB] occurs before any
// LHS of nonblocking assigments also from CLK_IN occur.
// Basically, this insures that CLK_OUT and CLK_IN occur within
// the same phase of the execution cycle, before any state
// updates occur. see
// http://www.sunburst-design.com/papers/CummingsSNUG2002Boston_NBAwithDelays.pdf
if ( RST_N == 0 )
cntr = upper - offset ;
else
begin
if ( cntr < upper_w )
cntr = cntr + 1 ;
else
cntr = lower_w ;
end // else: !if( RST_N == 0 )
end // always@ ( posedge CLK_IN or negedge RST_N )
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
#0 ;
cntr = (upper - offset) ;
PREEDGE = 0 ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule // ClockDiv
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream frame length adjuster
*/
module axis_frame_length_adjust #
(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Status
*/
output wire status_valid,
input wire status_ready,
output wire status_frame_pad,
output wire status_frame_truncate,
output wire [15:0] status_frame_length,
output wire [15:0] status_frame_original_length,
/*
* Configuration
*/
input wire [15:0] length_min,
input wire [15:0] length_max
);
// bus word width
localparam DATA_WORD_WIDTH = DATA_WIDTH / KEEP_WIDTH;
// bus width assertions
initial begin
if (DATA_WORD_WIDTH * KEEP_WIDTH != DATA_WIDTH) begin
$error("Error: data width not evenly divisble (instance %m)");
$finish;
end
end
// state register
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_TRANSFER = 3'd1,
STATE_PAD = 3'd2,
STATE_TRUNCATE = 3'd3;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_last_word;
reg [15:0] frame_ptr_reg = 16'd0, frame_ptr_next;
reg [DATA_WIDTH-1:0] s_axis_tdata_masked;
// frame length counters
reg [15:0] short_counter_reg = 16'd0, short_counter_next = 16'd0;
reg [15:0] long_counter_reg = 16'd0, long_counter_next = 16'd0;
reg [DATA_WIDTH-1:0] last_word_data_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] last_word_keep_reg = {KEEP_WIDTH{1'b0}};
reg [ID_WIDTH-1:0] last_word_id_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] last_word_dest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] last_word_user_reg = {USER_WIDTH{1'b0}};
reg status_valid_reg = 1'b0, status_valid_next;
reg status_frame_pad_reg = 1'b0, status_frame_pad_next;
reg status_frame_truncate_reg = 1'b0, status_frame_truncate_next;
reg [15:0] status_frame_length_reg = 16'd0, status_frame_length_next;
reg [15:0] status_frame_original_length_reg = 16'd0, status_frame_original_length_next;
// internal datapath
reg [DATA_WIDTH-1:0] m_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_axis_tkeep_int;
reg m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int;
reg [ID_WIDTH-1:0] m_axis_tid_int;
reg [DEST_WIDTH-1:0] m_axis_tdest_int;
reg [USER_WIDTH-1:0] m_axis_tuser_int;
wire m_axis_tready_int_early;
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
assign s_axis_tready = s_axis_tready_reg;
assign status_valid = status_valid_reg;
assign status_frame_pad = status_frame_pad_reg;
assign status_frame_truncate = status_frame_truncate_reg;
assign status_frame_length = status_frame_length_reg;
assign status_frame_original_length = status_frame_original_length_reg;
integer i, word_cnt;
always @* begin
state_next = STATE_IDLE;
store_last_word = 1'b0;
frame_ptr_next = frame_ptr_reg;
short_counter_next = short_counter_reg;
long_counter_next = long_counter_reg;
m_axis_tdata_int = {DATA_WIDTH{1'b0}};
m_axis_tkeep_int = {KEEP_WIDTH{1'b0}};
m_axis_tvalid_int = 1'b0;
m_axis_tlast_int = 1'b0;
m_axis_tid_int = {ID_WIDTH{1'b0}};
m_axis_tdest_int = {DEST_WIDTH{1'b0}};
m_axis_tuser_int = {USER_WIDTH{1'b0}};
s_axis_tready_next = 1'b0;
status_valid_next = status_valid_reg && !status_ready;
status_frame_pad_next = status_frame_pad_reg;
status_frame_truncate_next = status_frame_truncate_reg;
status_frame_length_next = status_frame_length_reg;
status_frame_original_length_next = status_frame_original_length_reg;
if (KEEP_ENABLE) begin
for (i = 0; i < KEEP_WIDTH; i = i + 1) begin
s_axis_tdata_masked[i*DATA_WORD_WIDTH +: DATA_WORD_WIDTH] = s_axis_tkeep[i] ? s_axis_tdata[i*DATA_WORD_WIDTH +: DATA_WORD_WIDTH] : {DATA_WORD_WIDTH{1'b0}};
end
end else begin
s_axis_tdata_masked = s_axis_tdata;
end
case (state_reg)
STATE_IDLE: begin
// idle state
// accept data next cycle if output register ready next cycle
s_axis_tready_next = m_axis_tready_int_early && (!status_valid_reg || status_ready);
m_axis_tdata_int = s_axis_tdata_masked;
m_axis_tkeep_int = s_axis_tkeep;
m_axis_tvalid_int = s_axis_tvalid;
m_axis_tlast_int = s_axis_tlast;
m_axis_tid_int = s_axis_tid;
m_axis_tdest_int = s_axis_tdest;
m_axis_tuser_int = s_axis_tuser;
short_counter_next = length_min;
long_counter_next = length_max;
if (s_axis_tready && s_axis_tvalid) begin
// transfer through
word_cnt = 0;
for (i = 0; i <= KEEP_WIDTH; i = i + 1) begin
//bit_cnt = bit_cnt + monitor_axis_tkeep[i];
if (s_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) word_cnt = i;
end
frame_ptr_next = frame_ptr_reg+KEEP_WIDTH;
if (short_counter_reg > KEEP_WIDTH) begin
short_counter_next = short_counter_reg - KEEP_WIDTH;
end else begin
short_counter_next = 16'd0;
end
if (long_counter_reg > KEEP_WIDTH) begin
long_counter_next = long_counter_reg - KEEP_WIDTH;
end else begin
long_counter_next = 16'd0;
end
if (long_counter_reg <= word_cnt) begin
m_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-long_counter_reg);
if (s_axis_tlast) begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b0;
status_frame_truncate_next = word_cnt > long_counter_reg;
status_frame_length_next = length_max;
status_frame_original_length_next = frame_ptr_reg+word_cnt;
s_axis_tready_next = m_axis_tready_int_early && status_ready;
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end else begin
m_axis_tvalid_int = 1'b0;
store_last_word = 1'b1;
state_next = STATE_TRUNCATE;
end
end else begin
if (s_axis_tlast) begin
status_frame_original_length_next = frame_ptr_reg+word_cnt;
if (short_counter_reg > word_cnt) begin
if (short_counter_reg > KEEP_WIDTH) begin
frame_ptr_next = frame_ptr_reg + KEEP_WIDTH;
s_axis_tready_next = 1'b0;
m_axis_tkeep_int = {KEEP_WIDTH{1'b1}};
m_axis_tlast_int = 1'b0;
store_last_word = 1'b1;
state_next = STATE_PAD;
end else begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b1;
status_frame_truncate_next = 1'b0;
status_frame_length_next = length_min;
s_axis_tready_next = m_axis_tready_int_early && status_ready;
m_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-(length_min - frame_ptr_reg));
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end
end else begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b0;
status_frame_truncate_next = 1'b0;
status_frame_length_next = frame_ptr_reg+word_cnt;
status_frame_original_length_next = frame_ptr_reg+word_cnt;
s_axis_tready_next = m_axis_tready_int_early && status_ready;
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_TRANSFER;
end
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_TRANSFER: begin
// transfer data
// accept data next cycle if output register ready next cycle
s_axis_tready_next = m_axis_tready_int_early;
m_axis_tdata_int = s_axis_tdata_masked;
m_axis_tkeep_int = s_axis_tkeep;
m_axis_tvalid_int = s_axis_tvalid;
m_axis_tlast_int = s_axis_tlast;
m_axis_tid_int = s_axis_tid;
m_axis_tdest_int = s_axis_tdest;
m_axis_tuser_int = s_axis_tuser;
if (s_axis_tready && s_axis_tvalid) begin
// transfer through
word_cnt = 1;
for (i = 1; i <= KEEP_WIDTH; i = i + 1) begin
//bit_cnt = bit_cnt + monitor_axis_tkeep[i];
if (s_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) word_cnt = i;
end
frame_ptr_next = frame_ptr_reg+KEEP_WIDTH;
if (short_counter_reg > KEEP_WIDTH) begin
short_counter_next = short_counter_reg - KEEP_WIDTH;
end else begin
short_counter_next = 16'd0;
end
if (long_counter_reg > KEEP_WIDTH) begin
long_counter_next = long_counter_reg - KEEP_WIDTH;
end else begin
long_counter_next = 16'd0;
end
if (long_counter_reg <= word_cnt) begin
m_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-long_counter_reg);
if (s_axis_tlast) begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b0;
status_frame_truncate_next = word_cnt > long_counter_reg;
status_frame_length_next = length_max;
status_frame_original_length_next = frame_ptr_reg+word_cnt;
s_axis_tready_next = m_axis_tready_int_early && status_ready;
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end else begin
m_axis_tvalid_int = 1'b0;
store_last_word = 1'b1;
state_next = STATE_TRUNCATE;
end
end else begin
if (s_axis_tlast) begin
status_frame_original_length_next = frame_ptr_reg+word_cnt;
if (short_counter_reg > word_cnt) begin
if (short_counter_reg > KEEP_WIDTH) begin
frame_ptr_next = frame_ptr_reg + KEEP_WIDTH;
s_axis_tready_next = 1'b0;
m_axis_tkeep_int = {KEEP_WIDTH{1'b1}};
m_axis_tlast_int = 1'b0;
store_last_word = 1'b1;
state_next = STATE_PAD;
end else begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b1;
status_frame_truncate_next = 1'b0;
status_frame_length_next = length_min;
s_axis_tready_next = m_axis_tready_int_early && status_ready;
m_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-short_counter_reg);
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end
end else begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b0;
status_frame_truncate_next = 1'b0;
status_frame_length_next = frame_ptr_reg+word_cnt;
status_frame_original_length_next = frame_ptr_reg+word_cnt;
s_axis_tready_next = m_axis_tready_int_early && status_ready;
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_TRANSFER;
end
end
end else begin
state_next = STATE_TRANSFER;
end
end
STATE_PAD: begin
// pad to minimum length
s_axis_tready_next = 1'b0;
m_axis_tdata_int = {DATA_WIDTH{1'b0}};
m_axis_tkeep_int = {KEEP_WIDTH{1'b1}};
m_axis_tvalid_int = 1'b1;
m_axis_tlast_int = 1'b0;
m_axis_tid_int = last_word_id_reg;
m_axis_tdest_int = last_word_dest_reg;
m_axis_tuser_int = last_word_user_reg;
if (m_axis_tready_int_reg) begin
frame_ptr_next = frame_ptr_reg + KEEP_WIDTH;
if (short_counter_reg > KEEP_WIDTH) begin
short_counter_next = short_counter_reg - KEEP_WIDTH;
end else begin
short_counter_next = 16'd0;
end
if (long_counter_reg > KEEP_WIDTH) begin
long_counter_next = long_counter_reg - KEEP_WIDTH;
end else begin
long_counter_next = 16'd0;
end
if (short_counter_reg <= KEEP_WIDTH) begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b1;
status_frame_truncate_next = 1'b0;
status_frame_length_next = length_min;
s_axis_tready_next = m_axis_tready_int_early && status_ready;
m_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-short_counter_reg);
m_axis_tlast_int = 1'b1;
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end else begin
state_next = STATE_PAD;
end
end else begin
state_next = STATE_PAD;
end
end
STATE_TRUNCATE: begin
// drop after maximum length
s_axis_tready_next = m_axis_tready_int_early;
m_axis_tdata_int = last_word_data_reg;
m_axis_tkeep_int = last_word_keep_reg;
m_axis_tvalid_int = s_axis_tvalid && s_axis_tlast;
m_axis_tlast_int = s_axis_tlast;
m_axis_tid_int = last_word_id_reg;
m_axis_tdest_int = last_word_dest_reg;
m_axis_tuser_int = s_axis_tuser;
if (s_axis_tready && s_axis_tvalid) begin
word_cnt = 0;
for (i = 0; i <= KEEP_WIDTH; i = i + 1) begin
//bit_cnt = bit_cnt + monitor_axis_tkeep[i];
if (s_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) word_cnt = i;
end
frame_ptr_next = frame_ptr_reg+KEEP_WIDTH;
if (s_axis_tlast) begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b0;
status_frame_truncate_next = 1'b1;
status_frame_length_next = length_max;
status_frame_original_length_next = frame_ptr_reg+word_cnt;
s_axis_tready_next = m_axis_tready_int_early && status_ready;
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end else begin
state_next = STATE_TRUNCATE;
end
end else begin
state_next = STATE_TRUNCATE;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 16'd0;
short_counter_reg <= 16'd0;
long_counter_reg <= 16'd0;
s_axis_tready_reg <= 1'b0;
status_valid_reg <= 1'b0;
end else begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
short_counter_reg <= short_counter_next;
long_counter_reg <= long_counter_next;
s_axis_tready_reg <= s_axis_tready_next;
status_valid_reg <= status_valid_next;
end
status_frame_pad_reg <= status_frame_pad_next;
status_frame_truncate_reg <= status_frame_truncate_next;
status_frame_length_reg <= status_frame_length_next;
status_frame_original_length_reg <= status_frame_original_length_next;
if (store_last_word) begin
last_word_data_reg <= m_axis_tdata_int;
last_word_keep_reg <= m_axis_tkeep_int;
last_word_id_reg <= m_axis_tid_int;
last_word_dest_reg <= m_axis_tdest_int;
last_word_user_reg <= m_axis_tuser_int;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis_tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis_tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end else begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tkeep_reg <= m_axis_tkeep_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tid_reg <= m_axis_tid_int;
m_axis_tdest_reg <= m_axis_tdest_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tid_reg <= temp_m_axis_tid_reg;
m_axis_tdest_reg <= temp_m_axis_tdest_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tkeep_reg <= m_axis_tkeep_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tid_reg <= m_axis_tid_int;
temp_m_axis_tdest_reg <= m_axis_tdest_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
end
endmodule
`resetall
|
/*
* Programing Notes:
1, there are four SPRs in uartlite, access using mtspr/mfspr instructions
2, the four register are:
control register
ctrl[0]: tx_start
ctrl[1]: rx_disenable
ctrl[2]: tx_interrupt_ebable - currently not in use
ctrl[3]: rx_interrupt_enable - currently not in use
ctrl[4]: interrupt status clear
Reset Status: 8'h00
bit[0]/[4] are auto-cleared when writing true-"1" into it.
status register - READ ONLY
sta[0]: transmitter status which 1 means transmitter is busy, 0 means transmitter is idle
sta[1]: receiver status which 1 means receiver is busy, 0 means receiver is idle
sta[2]: interrupt status which 1 mean interrupt status, 0 means normal status
sta[3]: transmitter interrupt status which means transmitter interrupt
sta[4]: receiver interrupt status which means receiver interrupt
receive data register
transmit data register
* Note:
1, there is no flow control, after received a byte, if second byte is coming, first byte is covered
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module dsu_uartlite(
clk, rst,
txd, rxd,
spr_dat_i,
reg_txdata, reg_txdata_we,
reg_ctrl, reg_ctrl_we,
reg_sta, reg_sta_we,
reg_rxdata, reg_rxdata_we,
sram_ce,
sram_we,
sram_addr,
sram_wdata,
download_enable
);
//
input clk;
input rst;
// uart inout
input rxd;
output txd;
// spr access interface
input [7:0] spr_dat_i;
input reg_txdata_we;
input reg_ctrl_we;
input reg_rxdata_we;
input reg_sta_we;
output [7:0] reg_txdata;
output [7:0] reg_ctrl;
output [7:0] reg_sta;
output [7:0] reg_rxdata;
// sram interface
output sram_ce;
output sram_we;
output [63:0] sram_wdata;
output [`IOCM_Word_BW-1:0] sram_addr;
// backdoor control
input download_enable;
//
// four internal SPRs for uartlite
//
reg [7:0] reg_ctrl;
reg [7:0] reg_sta;
reg [7:0] reg_txdata;
reg [7:0] reg_rxdata;
//
wire tx_start;
wire rx_enable;
reg tx_busy_d;
reg interrupt_tx;
reg interrupt_rx;
//
//
//
wire txd;
wire rxd;
wire [7:0] rx_data;
wire [7:0] rx_data_to_sram;
wire rx_data_rdy;
wire tx_busy;
wire rx_idle;
wire interrupt;
//
// SPR: control register
//
// [TBV]: coding style of auto-cleared
always@(posedge clk or `dsu_RST_EVENT rst) begin
if(rst==`dsu_RST_VALUE)
reg_ctrl <= 8'h00;
else if(reg_ctrl[0]) // the tx_enable bit (ctrl[0]) will auto cleared after write 1
reg_ctrl[0] <= 1'b0;
else if(reg_ctrl_we)
reg_ctrl <= spr_dat_i;
else if(reg_ctrl[4]) // the int_clear bit (ctrl[4]) will auto cleared after write 1
reg_ctrl[4] <= 1'b0;
end
assign tx_start = reg_ctrl[0];
assign rx_enable = !reg_ctrl[1];
assign int_clear = reg_ctrl[4];
//
// SPR: status register
//
// tx interrupt detect
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
tx_busy_d <= 1'b0;
else
tx_busy_d <= tx_busy;
//when detect the negedge of tx_busy that means transmitter is finished
//if the tx_interrupt enable then generate interrupt of transmitter.
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
interrupt_tx <= 1'b0;
else if(!tx_busy && tx_busy_d)
interrupt_tx <= 1'b1;
else if(int_clear)
interrupt_tx <= 1'b0;
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
interrupt_rx <= 1'b0;
else if(rx_data_rdy && rx_enable)
interrupt_rx <= 1'b1;
else if(int_clear)
interrupt_rx <= 1'b0;
assign interrupt = interrupt_rx || interrupt_tx;
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
reg_sta <= 8'h00;
else if(reg_sta_we)
reg_sta <= spr_dat_i;
else
reg_sta <= {3'b000, interrupt_rx, interrupt_tx, interrupt, !rx_idle, tx_busy};
//
// SPR: receive data register
//
always@(posedge clk or `dsu_RST_EVENT rst) begin
if(rst==`dsu_RST_VALUE)
reg_rxdata <= 8'h00;
else if(rx_data_rdy && rx_enable )
reg_rxdata <= rx_data;
end
//
// SPR: transmit data register
//
always@(posedge clk or `dsu_RST_EVENT rst) begin
if(rst==`dsu_RST_VALUE)
reg_txdata <= 8'h00;
else if(reg_txdata_we)
reg_txdata <= spr_dat_i;
end
//
// transmitter and receiver
//
dsu_Tx tx(
.clk(clk),
.rst(rst),
.TxD_start(tx_start),
.TxD_data(reg_txdata),
.TxD(txd),
.TxD_busy(tx_busy)
);
dsu_Rx rx(
.clk(clk),
.rst(rst),
.RxD(rxd),
.RxD_data_ready(rx_data_rdy),
.RxD_data(rx_data),
.RxD_endofpacket(),
.RxD_idle(rx_idle)
);
//
// back door mode: burn sram using received data
//
assign rx_data_to_sram = download_enable ? rx_data : 8'h00;
dsu_sram_ctrl sram_ctrl(
.clk(clk),
.rst(rst),
.rxd(rx_data_to_sram),
.rxd_ready(rx_data_rdy && download_enable),
.sram_ce(sram_ce),
.sram_we(sram_we),
.sram_addr(sram_addr),
.sram_wdata(sram_wdata),
.download_enable(download_enable)
);
endmodule |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_bram_v6.v
// Version : 1.7
//--
//-- Description: BlockRAM module for Virtex6 PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_bram_v6
#(
parameter DOB_REG = 0,// 1 use the output register 0 don't use the output register
parameter WIDTH = 0 // supported WIDTH's are: 4, 9, 18, 36 (uses RAMB36) and 72 (uses RAMB36SDP)
)
(
input user_clk_i,// user clock
input reset_i, // bram reset
input wen_i, // write enable
input [12:0] waddr_i, // write address
input [WIDTH - 1:0] wdata_i, // write data
input ren_i, // read enable
input rce_i, // output register clock enable
input [12:0] raddr_i, // read address
output [WIDTH - 1:0] rdata_o // read data
);
// map the address bits
localparam ADDR_MSB = ((WIDTH == 4) ? 12 :
(WIDTH == 9) ? 11 :
(WIDTH == 18) ? 10 :
(WIDTH == 36) ? 9 :
8
);
// set the width of the tied off low address bits
localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 :
(WIDTH == 9) ? 3 :
(WIDTH == 18) ? 4 :
(WIDTH == 36) ? 5 :
0 // for WIDTH 72 use RAMB36SDP
);
// map the data bits
localparam D_MSB = ((WIDTH == 4) ? 3 :
(WIDTH == 9) ? 7 :
(WIDTH == 18) ? 15 :
(WIDTH == 36) ? 31 :
63
);
// map the data parity bits
localparam DP_LSB = D_MSB + 1;
localparam DP_MSB = ((WIDTH == 4) ? 4 :
(WIDTH == 9) ? 8 :
(WIDTH == 18) ? 17 :
(WIDTH == 36) ? 35 :
71
);
localparam DPW = DP_MSB - DP_LSB + 1;
localparam WRITE_MODE = "NO_CHANGE";
//synthesis translate_off
initial begin
//$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d",
// $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB);
case (WIDTH)
4,9,18,36,72:;
default:
begin
$display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH);
$finish;
end
endcase // case (WIDTH)
end
//synthesis translate_on
generate
if (WIDTH == 72) begin : use_ramb36sdp
// use RAMB36SDP if the width is 72
RAMB36SDP #(
.DO_REG (DOB_REG)
)
ramb36sdp(
.WRCLK (user_clk_i),
.SSR (1'b0),
.WRADDR (waddr_i[ADDR_MSB:0]),
.DI (wdata_i[D_MSB:0]),
.DIP (wdata_i[DP_MSB:DP_LSB]),
.WREN (wen_i),
.WE ({8{wen_i}}),
.DBITERR (),
.ECCPARITY (),
.SBITERR (),
.RDCLK (user_clk_i),
.RDADDR (raddr_i[ADDR_MSB:0]),
.DO (rdata_o[D_MSB:0]),
.DOP (rdata_o[DP_MSB:DP_LSB]),
.RDEN (ren_i),
.REGCE (rce_i)
);
// use RAMB36's if the width is 4, 9, 18, or 36
end else if (WIDTH == 36) begin : use_ramb36
RAMB36 #(
.DOA_REG (0),
.DOB_REG (DOB_REG),
.READ_WIDTH_A (0),
.READ_WIDTH_B (WIDTH),
.WRITE_WIDTH_A (WIDTH),
.WRITE_WIDTH_B (0),
.WRITE_MODE_A (WRITE_MODE)
)
ramb36(
.CLKA (user_clk_i),
.SSRA (1'b0),
.REGCEA (1'b0),
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.DOA (),
.DOPA (),
.ADDRA ({1'b1, waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DIA (wdata_i[D_MSB:0]),
.DIPA (wdata_i[DP_MSB:DP_LSB]),
.ENA (wen_i),
.WEA ({4{wen_i}}),
.CLKB (user_clk_i),
.SSRB (1'b0),
.WEB (4'b0),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB (),
.DIB (32'b0),
.DIPB ( 4'b0),
.ADDRB ({1'b1, raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DOB (rdata_o[D_MSB:0]),
.DOPB (rdata_o[DP_MSB:DP_LSB]),
.ENB (ren_i),
.REGCEB (rce_i)
);
end else if (WIDTH < 36 && WIDTH > 4) begin : use_ramb36
wire [31 - D_MSB - 1 : 0] dob_unused;
wire [ 4 - DPW - 1 : 0] dopb_unused;
RAMB36 #(
.DOA_REG (0),
.DOB_REG (DOB_REG),
.READ_WIDTH_A (0),
.READ_WIDTH_B (WIDTH),
.WRITE_WIDTH_A (WIDTH),
.WRITE_WIDTH_B (0),
.WRITE_MODE_A (WRITE_MODE)
)
ramb36(
.CLKA (user_clk_i),
.SSRA (1'b0),
.REGCEA (1'b0),
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.DOA (),
.DOPA (),
.ADDRA ({1'b1, waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DIA ({{31 - D_MSB{1'b0}},wdata_i[D_MSB:0]}),
.DIPA ({{ 4 - DPW {1'b0}},wdata_i[DP_MSB:DP_LSB]}),
.ENA (wen_i),
.WEA ({4{wen_i}}),
.CLKB (user_clk_i),
.SSRB (1'b0),
.WEB (4'b0),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB (),
.DIB (32'b0),
.DIPB ( 4'b0),
.ADDRB ({1'b1, raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DOB ({dob_unused, rdata_o[D_MSB:0]}),
.DOPB ({dopb_unused, rdata_o[DP_MSB:DP_LSB]}),
.ENB (ren_i),
.REGCEB (rce_i)
);
end else if (WIDTH == 4) begin : use_ramb36
wire [31 - D_MSB - 1 : 0] dob_unused;
RAMB36 #(
.DOB_REG (DOB_REG),
.READ_WIDTH_A (0),
.READ_WIDTH_B (WIDTH),
.WRITE_WIDTH_A (WIDTH),
.WRITE_WIDTH_B (0),
.WRITE_MODE_A (WRITE_MODE)
)
ramb36(
.CLKA (user_clk_i),
.SSRA (1'b0),
.REGCEA (1'b0),
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.DOA (),
.DOPA (),
.ADDRA ({1'b1, waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DIA ({{31 - D_MSB{1'b0}},wdata_i[D_MSB:0]}),
//.DIPA (wdata_i[DP_MSB:DP_LSB]),
.DIPA (4'h0),
.ENA (wen_i),
.WEA ({4{wen_i}}),
.CLKB (user_clk_i),
.SSRB (1'b0),
.WEB (4'b0),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB (),
.ADDRB ({1'b1, raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DIB (0),
.DIPB (0),
.DOB ({dob_unused,rdata_o[D_MSB:0]}),
//.DOPB (rdata_o[DP_MSB:DP_LSB]),
.ENB (ren_i),
.REGCEB (rce_i)
);
end // block: use_ramb36
endgenerate
endmodule // pcie_bram_v6
|
/*
Anthony De Caria - May 22, 2014
This module creates a Shift Register with a seperate enable signal.
This specific module creates an output that is 16-bits wide.
This module uses asyncronous D Flip Flops.
It also can allow data to be inputed into the flip flops before shifting.
*/
module ShiftRegisterWEnableFourteenAsyncMuxedInput(clk, resetn, enable, select, d, q);
//Define the inputs and outputs
input clk;
input resetn;
input enable;
input select;
input [13:0] d;
output [13:0] q;
wire [13:1]muxOut;
mux2to1_1bit One_mux(.data1x(d[1]), .data0x(q[0]), .sel(select), .result(muxOut[1]) );
mux2to1_1bit Two_mux(.data1x(d[2]), .data0x(q[1]), .sel(select), .result(muxOut[2]) );
mux2to1_1bit Three_mux(.data1x(d[3]), .data0x(q[2]), .sel(select), .result(muxOut[3]) );
mux2to1_1bit Four_mux(.data1x(d[4]), .data0x(q[3]), .sel(select), .result(muxOut[4]) );
mux2to1_1bit Five_mux(.data1x(d[5]), .data0x(q[4]), .sel(select), .result(muxOut[5]) );
mux2to1_1bit Six_mux(.data1x(d[6]), .data0x(q[5]), .sel(select), .result(muxOut[6]) );
mux2to1_1bit Seven_mux(.data1x(d[7]), .data0x(q[6]), .sel(select), .result(muxOut[7]) );
mux2to1_1bit Eight_mux(.data1x(d[8]), .data0x(q[7]), .sel(select), .result(muxOut[8]) );
mux2to1_1bit Nine_mux(.data1x(d[9]), .data0x(q[8]), .sel(select), .result(muxOut[9]) );
mux2to1_1bit Ten_mux(.data1x(d[10]), .data0x(q[9]), .sel(select), .result(muxOut[10]) );
mux2to1_1bit Eleven_mux(.data1x(d[11]), .data0x(q[10]), .sel(select), .result(muxOut[11]) );
mux2to1_1bit Twelve_mux(.data1x(d[12]), .data0x(q[11]), .sel(select), .result(muxOut[12]) );
mux2to1_1bit Thirteen_mux(.data1x(d[13]), .data0x(q[12]), .sel(select), .result(muxOut[13]) );
D_FF_with_Enable Zero(.clk(clk), .resetn(resetn), .enable(enable), .d(d[0]), .q(q[0]) );
D_FF_with_Enable One(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[1]), .q(q[1]) );
D_FF_with_Enable Two(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[2]), .q(q[2]) );
D_FF_with_Enable Three(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[3]), .q(q[3]) );
D_FF_with_Enable Four(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[4]), .q(q[4]) );
D_FF_with_Enable Five(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[5]), .q(q[5]) );
D_FF_with_Enable Six(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[6]), .q(q[6]) );
D_FF_with_Enable Seven(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[7]), .q(q[7]) );
D_FF_with_Enable Eight(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[8]), .q(q[8]) );
D_FF_with_Enable Nine(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[9]), .q(q[9]) );
D_FF_with_Enable Ten(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[10]), .q(q[10]) );
D_FF_with_Enable Eleven(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[11]), .q(q[11]) );
D_FF_with_Enable Twelve(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[12]), .q(q[12]) );
D_FF_with_Enable Thirteen(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[13]), .q(q[13]) );
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_clock_module.v
//
// *Module Description:
// Basic clock module implementation.
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_clock_module (
// OUTPUTs
aclk, // ACLK
aclk_en, // ACLK enable
cpu_en_s, // Enable CPU code execution (synchronous)
cpu_mclk, // Main system CPU only clock
dma_mclk, // Main system DMA and/or CPU clock
dbg_clk, // Debug unit clock
dbg_en_s, // Debug interface enable (synchronous)
dbg_rst, // Debug unit reset
dco_enable, // Fast oscillator enable
dco_wkup, // Fast oscillator wake-up (asynchronous)
lfxt_enable, // Low frequency oscillator enable
lfxt_wkup, // Low frequency oscillator wake-up (asynchronous)
per_dout, // Peripheral data output
por, // Power-on reset
puc_pnd_set, // PUC pending set for the serial debug interface
puc_rst, // Main system reset
smclk, // SMCLK
smclk_en, // SMCLK enable
// INPUTs
cpu_en, // Enable CPU code execution (asynchronous)
cpuoff, // Turns off the CPU
dbg_cpu_reset, // Reset CPU from debug interface
dbg_en, // Debug interface enable (asynchronous)
dco_clk, // Fast oscillator (fast clock)
lfxt_clk, // Low frequency oscillator (typ 32kHz)
mclk_dma_enable, // DMA Sub-System Clock enable
mclk_dma_wkup, // DMA Sub-System Clock wake-up (asynchronous)
mclk_enable, // Main System Clock enable
mclk_wkup, // Main System Clock wake-up (asynchronous)
oscoff, // Turns off LFXT1 clock input
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write enable (high active)
reset_n, // Reset Pin (low active, asynchronous)
scan_enable, // Scan enable (active during scan shifting)
scan_mode, // Scan mode
scg0, // System clock generator 1. Turns off the DCO
scg1, // System clock generator 1. Turns off the SMCLK
wdt_reset // Watchdog-timer reset
);
// OUTPUTs
//=========
output aclk; // ACLK
output aclk_en; // ACLK enable
output cpu_en_s; // Enable CPU code execution (synchronous)
output cpu_mclk; // Main system CPU only clock
output dma_mclk; // Main system DMA and/or CPU clock
output dbg_clk; // Debug unit clock
output dbg_en_s; // Debug unit enable (synchronous)
output dbg_rst; // Debug unit reset
output dco_enable; // Fast oscillator enable
output dco_wkup; // Fast oscillator wake-up (asynchronous)
output lfxt_enable; // Low frequency oscillator enable
output lfxt_wkup; // Low frequency oscillator wake-up (asynchronous)
output [15:0] per_dout; // Peripheral data output
output por; // Power-on reset
output puc_pnd_set; // PUC pending set for the serial debug interface
output puc_rst; // Main system reset
output smclk; // SMCLK
output smclk_en; // SMCLK enable
// INPUTs
//=========
input cpu_en; // Enable CPU code execution (asynchronous)
input cpuoff; // Turns off the CPU
input dbg_cpu_reset; // Reset CPU from debug interface
input dbg_en; // Debug interface enable (asynchronous)
input dco_clk; // Fast oscillator (fast clock)
input lfxt_clk; // Low frequency oscillator (typ 32kHz)
input mclk_dma_enable; // DMA Sub-System Clock enable
input mclk_dma_wkup; // DMA Sub-System Clock wake-up (asynchronous)
input mclk_enable; // Main System Clock enable
input mclk_wkup; // Main System Clock wake-up (asynchronous)
input oscoff; // Turns off LFXT1 clock input
input [13:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input reset_n; // Reset Pin (low active, asynchronous)
input scan_enable; // Scan enable (active during scan shifting)
input scan_mode; // Scan mode
input scg0; // System clock generator 1. Turns off the DCO
input scg1; // System clock generator 1. Turns off the SMCLK
input wdt_reset; // Watchdog-timer reset
//=============================================================================
// 1) WIRES & PARAMETER DECLARATION
//=============================================================================
// Register base address (must be aligned to decoder bit width)
parameter [14:0] BASE_ADDR = 15'h0050;
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 4;
// Register addresses offset
parameter [DEC_WD-1:0] BCSCTL1 = 'h7,
BCSCTL2 = 'h8;
// Register one-hot decoder utilities
parameter DEC_SZ = (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] BCSCTL1_D = (BASE_REG << BCSCTL1),
BCSCTL2_D = (BASE_REG << BCSCTL2);
// Local wire declarations
wire nodiv_mclk;
wire nodiv_smclk;
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {1'b0, per_addr[DEC_WD-2:0]};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (BCSCTL1_D & {DEC_SZ{(reg_addr==(BCSCTL1 >>1))}}) |
(BCSCTL2_D & {DEC_SZ{(reg_addr==(BCSCTL2 >>1))}});
// Read/Write probes
wire reg_lo_write = per_we[0] & reg_sel;
wire reg_hi_write = per_we[1] & reg_sel;
wire reg_read = ~|per_we & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}};
wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// BCSCTL1 Register
//--------------
reg [7:0] bcsctl1;
wire bcsctl1_wr = BCSCTL1[0] ? reg_hi_wr[BCSCTL1] : reg_lo_wr[BCSCTL1];
wire [7:0] bcsctl1_nxt = BCSCTL1[0] ? per_din[15:8] : per_din[7:0];
`ifdef ASIC_CLOCKING
`ifdef ACLK_DIVIDER
wire [7:0] divax_mask = 8'h30;
`else
wire [7:0] divax_mask = 8'h00;
`endif
`ifdef DMA_IF_EN
`ifdef CPUOFF_EN
wire [7:0] dma_cpuoff_mask = 8'h01;
`else
wire [7:0] dma_cpuoff_mask = 8'h00;
`endif
`ifdef OSCOFF_EN
wire [7:0] dma_oscoff_mask = 8'h02;
`else
wire [7:0] dma_oscoff_mask = 8'h00;
`endif
`ifdef SCG0_EN
wire [7:0] dma_scg0_mask = 8'h04;
`else
wire [7:0] dma_scg0_mask = 8'h00;
`endif
`ifdef SCG1_EN
wire [7:0] dma_scg1_mask = 8'h08;
`else
wire [7:0] dma_scg1_mask = 8'h00;
`endif
`else
wire [7:0] dma_cpuoff_mask = 8'h00;
wire [7:0] dma_scg0_mask = 8'h00;
wire [7:0] dma_scg1_mask = 8'h00;
wire [7:0] dma_oscoff_mask = 8'h00;
`endif
`else
wire [7:0] divax_mask = 8'h30;
wire [7:0] dma_cpuoff_mask = 8'h00;
wire [7:0] dma_scg0_mask = 8'h00;
`ifdef DMA_IF_EN
wire [7:0] dma_oscoff_mask = 8'h02;
wire [7:0] dma_scg1_mask = 8'h08;
`else
wire [7:0] dma_oscoff_mask = 8'h00;
wire [7:0] dma_scg1_mask = 8'h00;
`endif
`endif
always @ (posedge dma_mclk or posedge puc_rst)
if (puc_rst) bcsctl1 <= 8'h00;
else if (bcsctl1_wr) bcsctl1 <= bcsctl1_nxt & (divax_mask |
dma_cpuoff_mask | dma_oscoff_mask |
dma_scg0_mask | dma_scg1_mask ); // Mask unused bits
// BCSCTL2 Register
//--------------
reg [7:0] bcsctl2;
wire bcsctl2_wr = BCSCTL2[0] ? reg_hi_wr[BCSCTL2] : reg_lo_wr[BCSCTL2];
wire [7:0] bcsctl2_nxt = BCSCTL2[0] ? per_din[15:8] : per_din[7:0];
`ifdef MCLK_MUX
wire [7:0] selmx_mask = 8'h80;
`else
wire [7:0] selmx_mask = 8'h00;
`endif
`ifdef MCLK_DIVIDER
wire [7:0] divmx_mask = 8'h30;
`else
wire [7:0] divmx_mask = 8'h00;
`endif
`ifdef ASIC_CLOCKING
`ifdef SMCLK_MUX
wire [7:0] sels_mask = 8'h08;
`else
wire [7:0] sels_mask = 8'h00;
`endif
`ifdef SMCLK_DIVIDER
wire [7:0] divsx_mask = 8'h06;
`else
wire [7:0] divsx_mask = 8'h00;
`endif
`else
wire [7:0] sels_mask = 8'h08;
wire [7:0] divsx_mask = 8'h06;
`endif
always @ (posedge dma_mclk or posedge puc_rst)
if (puc_rst) bcsctl2 <= 8'h00;
else if (bcsctl2_wr) bcsctl2 <= bcsctl2_nxt & ( sels_mask | divsx_mask |
selmx_mask | divmx_mask); // Mask unused bits
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] bcsctl1_rd = {8'h00, (bcsctl1 & {8{reg_rd[BCSCTL1]}})} << (8 & {4{BCSCTL1[0]}});
wire [15:0] bcsctl2_rd = {8'h00, (bcsctl2 & {8{reg_rd[BCSCTL2]}})} << (8 & {4{BCSCTL2[0]}});
wire [15:0] per_dout = bcsctl1_rd |
bcsctl2_rd;
//=============================================================================
// 5) DCO_CLK / LFXT_CLK INTERFACES (WAKEUP, ENABLE, ...)
//=============================================================================
`ifdef ASIC_CLOCKING
wire cpuoff_and_mclk_enable;
wire cpuoff_and_mclk_dma_enable;
wire cpuoff_and_mclk_dma_wkup;
`ifdef CPUOFF_EN
omsp_and_gate and_cpuoff_mclk_en (.y(cpuoff_and_mclk_enable), .a(cpuoff), .b(mclk_enable));
`ifdef DMA_IF_EN
omsp_and_gate and_cpuoff_mclk_dma_en (.y(cpuoff_and_mclk_dma_enable), .a(bcsctl1[`DMA_CPUOFF]), .b(mclk_dma_enable));
omsp_and_gate and_cpuoff_mclk_dma_wkup (.y(cpuoff_and_mclk_dma_wkup), .a(bcsctl1[`DMA_CPUOFF]), .b(mclk_dma_wkup));
`else
assign cpuoff_and_mclk_dma_enable = 1'b0;
assign cpuoff_and_mclk_dma_wkup = 1'b0;
`endif
`else
assign cpuoff_and_mclk_enable = 1'b0;
assign cpuoff_and_mclk_dma_enable = 1'b0;
assign cpuoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_cpuoff = cpuoff;
`endif
wire scg0_and_mclk_dma_enable;
wire scg0_and_mclk_dma_wkup;
`ifdef DMA_IF_EN
`ifdef SCG0_EN
omsp_and_gate and_scg0_mclk_dma_en (.y(scg0_and_mclk_dma_enable), .a(bcsctl1[`DMA_SCG0]), .b(mclk_dma_enable));
omsp_and_gate and_scg0_mclk_dma_wkup (.y(scg0_and_mclk_dma_wkup), .a(bcsctl1[`DMA_SCG0]), .b(mclk_dma_wkup));
`else
assign scg0_and_mclk_dma_enable = 1'b0;
assign scg0_and_mclk_dma_wkup = 1'b0;
wire UNUSED_scg0_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
assign scg0_and_mclk_dma_enable = 1'b0;
assign scg0_and_mclk_dma_wkup = 1'b0;
`endif
wire scg1_and_mclk_dma_enable;
wire scg1_and_mclk_dma_wkup;
`ifdef DMA_IF_EN
`ifdef SCG1_EN
omsp_and_gate and_scg1_mclk_dma_en (.y(scg1_and_mclk_dma_enable), .a(bcsctl1[`DMA_SCG1]), .b(mclk_dma_enable));
omsp_and_gate and_scg1_mclk_dma_wkup (.y(scg1_and_mclk_dma_wkup), .a(bcsctl1[`DMA_SCG1]), .b(mclk_dma_wkup));
`else
assign scg1_and_mclk_dma_enable = 1'b0;
assign scg1_and_mclk_dma_wkup = 1'b0;
wire UNUSED_scg1_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
assign scg1_and_mclk_dma_enable = 1'b0;
assign scg1_and_mclk_dma_wkup = 1'b0;
`endif
wire oscoff_and_mclk_dma_enable;
wire oscoff_and_mclk_dma_wkup;
`ifdef DMA_IF_EN
`ifdef OSCOFF_EN
omsp_and_gate and_oscoff_mclk_dma_en (.y(oscoff_and_mclk_dma_enable), .a(bcsctl1[`DMA_OSCOFF]), .b(mclk_dma_enable));
omsp_and_gate and_oscoff_mclk_dma_wkup (.y(oscoff_and_mclk_dma_wkup), .a(bcsctl1[`DMA_OSCOFF]), .b(mclk_dma_wkup));
`else
assign oscoff_and_mclk_dma_enable = 1'b0;
assign oscoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_oscoff_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
assign oscoff_and_mclk_dma_enable = 1'b0;
assign oscoff_and_mclk_dma_wkup = 1'b0;
wire UNUSED_mclk_dma_wkup = mclk_dma_wkup;
`endif
`else
wire UNUSED_cpuoff = cpuoff;
wire UNUSED_mclk_enable = mclk_enable;
wire UNUSED_mclk_dma_wkup = mclk_dma_wkup;
`endif
//-----------------------------------------------------------
// 5.1) HIGH SPEED SYSTEM CLOCK GENERATOR (DCO_CLK)
//-----------------------------------------------------------
// Note1: switching off the DCO osillator is only
// supported in ASIC mode with SCG0 low power mode
//
// Note2: unlike the original MSP430 specification,
// we allow to switch off the DCO even
// if it is selected by MCLK or SMCLK.
wire por_a;
wire dco_wkup;
wire cpu_en_wkup;
`ifdef SCG0_EN
// The DCO oscillator is synchronously disabled if:
// - the cpu pin is disabled (in that case, wait for mclk_enable==0)
// - the debug interface is disabled
// - SCG0 is set (in that case, wait for the mclk_enable==0 if selected by SELMx)
//
// Note that we make extensive use of the AND gate module in order
// to prevent glitch propagation on the wakeup logic cone.
wire cpu_enabled_with_dco;
wire dco_not_enabled_by_dbg;
wire dco_disable_by_scg0;
wire dco_disable_by_cpu_en;
wire dco_enable_nxt;
omsp_and_gate and_dco_dis1 (.y(cpu_enabled_with_dco), .a(~bcsctl2[`SELMx]), .b(cpuoff_and_mclk_enable));
omsp_and_gate and_dco_dis2 (.y(dco_not_enabled_by_dbg), .a(~dbg_en_s), .b(~(cpu_enabled_with_dco | scg0_and_mclk_dma_enable)));
omsp_and_gate and_dco_dis3 (.y(dco_disable_by_scg0), .a(scg0), .b(dco_not_enabled_by_dbg));
omsp_and_gate and_dco_dis4 (.y(dco_disable_by_cpu_en), .a(~cpu_en_s), .b(~mclk_enable));
omsp_and_gate and_dco_dis5 (.y(dco_enable_nxt), .a(~dco_disable_by_scg0), .b(~dco_disable_by_cpu_en));
// Register to prevent glitch propagation
reg dco_disable;
wire dco_wkup_set_scan_observe;
always @(posedge nodiv_mclk or posedge por)
if (por) dco_disable <= 1'b1;
else dco_disable <= ~dco_enable_nxt | dco_wkup_set_scan_observe;
// Optional scan repair
wire dco_clk_n;
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_dco_clk_n (
.scan_mode (scan_mode),
.data_in_scan ( dco_clk),
.data_in_func (~dco_clk),
.data_out ( dco_clk_n)
);
`else
assign dco_clk_n = ~dco_clk;
`endif
// Note that a synchronizer is required if the MCLK mux is included
`ifdef MCLK_MUX
omsp_sync_cell sync_cell_dco_disable (
.data_out (dco_enable),
.data_in (~dco_disable),
.clk (dco_clk_n),
.rst (por)
);
`else
// Optional scan repair
wire nodiv_mclk_n;
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_nodiv_mclk_n (
.scan_mode (scan_mode),
.data_in_scan ( nodiv_mclk),
.data_in_func (~nodiv_mclk),
.data_out ( nodiv_mclk_n)
);
`else
assign nodiv_mclk_n = ~nodiv_mclk;
`endif
// Re-time DCO enable with MCLK falling edge
reg dco_enable;
always @(posedge nodiv_mclk_n or posedge por)
if (por) dco_enable <= 1'b0;
else dco_enable <= ~dco_disable;
`endif
// The DCO oscillator will get an asynchronous wakeup if:
// - the MCLK generates a wakeup (only if the MCLK mux selects dco_clk)
// - if the DCO wants to be synchronously enabled (i.e dco_enable_nxt=1)
wire dco_mclk_wkup;
wire dco_en_wkup;
omsp_and_gate and_dco_mclk_wkup (.y(dco_mclk_wkup), .a(mclk_wkup), .b(~bcsctl2[`SELMx]));
omsp_and_gate and_dco_en_wkup (.y(dco_en_wkup), .a(~dco_enable), .b(dco_enable_nxt));
wire dco_wkup_set = dco_mclk_wkup | scg0_and_mclk_dma_wkup | dco_en_wkup | cpu_en_wkup;
// Scan MUX for the asynchronous SET
wire dco_wkup_set_scan;
omsp_scan_mux scan_mux_dco_wkup (
.scan_mode (scan_mode),
.data_in_scan (por_a),
.data_in_func (dco_wkup_set | por),
.data_out (dco_wkup_set_scan)
);
// Scan MUX to increase coverage
omsp_scan_mux scan_mux_dco_wkup_observe (
.scan_mode (scan_mode),
.data_in_scan (dco_wkup_set),
.data_in_func (1'b0),
.data_out (dco_wkup_set_scan_observe)
);
// The wakeup is asynchronously set, synchronously released
wire dco_wkup_n;
omsp_sync_cell sync_cell_dco_wkup (
.data_out (dco_wkup_n),
.data_in (1'b1),
.clk (dco_clk_n),
.rst (dco_wkup_set_scan)
);
omsp_and_gate and_dco_wkup (.y(dco_wkup), .a(~dco_wkup_n), .b(cpu_en));
`else
assign dco_enable = 1'b1;
assign dco_wkup = 1'b1;
wire UNUSED_scg0 = scg0;
wire UNUSED_cpu_en_wkup1 = cpu_en_wkup;
`endif
//-----------------------------------------------------------
// 5.2) LOW FREQUENCY CRYSTAL CLOCK GENERATOR (LFXT_CLK)
//-----------------------------------------------------------
// ASIC MODE
//------------------------------------------------
// Note: unlike the original MSP430 specification,
// we allow to switch off the LFXT even
// if it is selected by MCLK or SMCLK.
`ifdef ASIC_CLOCKING
`ifdef OSCOFF_EN
// The LFXT is synchronously disabled if:
// - the cpu pin is disabled (in that case, wait for mclk_enable==0)
// - the debug interface is disabled
// - OSCOFF is set (in that case, wait for the mclk_enable==0 if selected by SELMx)
wire cpu_enabled_with_lfxt;
wire lfxt_not_enabled_by_dbg;
wire lfxt_disable_by_oscoff;
wire lfxt_disable_by_cpu_en;
wire lfxt_enable_nxt;
omsp_and_gate and_lfxt_dis1 (.y(cpu_enabled_with_lfxt), .a(bcsctl2[`SELMx]), .b(cpuoff_and_mclk_enable));
omsp_and_gate and_lfxt_dis2 (.y(lfxt_not_enabled_by_dbg), .a(~dbg_en_s), .b(~(cpu_enabled_with_lfxt | oscoff_and_mclk_dma_enable)));
omsp_and_gate and_lfxt_dis3 (.y(lfxt_disable_by_oscoff), .a(oscoff), .b(lfxt_not_enabled_by_dbg));
omsp_and_gate and_lfxt_dis4 (.y(lfxt_disable_by_cpu_en), .a(~cpu_en_s), .b(~mclk_enable));
omsp_and_gate and_lfxt_dis5 (.y(lfxt_enable_nxt), .a(~lfxt_disable_by_oscoff), .b(~lfxt_disable_by_cpu_en));
// Register to prevent glitch propagation
reg lfxt_disable;
wire lfxt_wkup_set_scan_observe;
always @(posedge nodiv_mclk or posedge por)
if (por) lfxt_disable <= 1'b1;
else lfxt_disable <= ~lfxt_enable_nxt | lfxt_wkup_set_scan_observe;
// Optional scan repair
wire lfxt_clk_n;
`ifdef SCAN_REPAIR_INV_CLOCKS
omsp_scan_mux scan_mux_repair_lfxt_clk_n (
.scan_mode (scan_mode),
.data_in_scan ( lfxt_clk),
.data_in_func (~lfxt_clk),
.data_out ( lfxt_clk_n)
);
`else
assign lfxt_clk_n = ~lfxt_clk;
`endif
// Synchronize the OSCOFF control signal to the LFXT clock domain
omsp_sync_cell sync_cell_lfxt_disable (
.data_out (lfxt_enable),
.data_in (~lfxt_disable),
.clk (lfxt_clk_n),
.rst (por)
);
// The LFXT will get an asynchronous wakeup if:
// - the MCLK generates a wakeup (only if the MCLK mux selects lfxt_clk)
// - if the LFXT wants to be synchronously enabled (i.e lfxt_enable_nxt=1)
wire lfxt_mclk_wkup;
wire lfxt_en_wkup;
omsp_and_gate and_lfxt_mclk_wkup (.y(lfxt_mclk_wkup), .a(mclk_wkup), .b(bcsctl2[`SELMx]));
omsp_and_gate and_lfxt_en_wkup (.y(lfxt_en_wkup), .a(~lfxt_enable), .b(lfxt_enable_nxt));
wire lfxt_wkup_set = lfxt_mclk_wkup | oscoff_and_mclk_dma_wkup | lfxt_en_wkup | cpu_en_wkup;
// Scan MUX for the asynchronous SET
wire lfxt_wkup_set_scan;
omsp_scan_mux scan_mux_lfxt_wkup (
.scan_mode (scan_mode),
.data_in_scan (por_a),
.data_in_func (lfxt_wkup_set | por),
.data_out (lfxt_wkup_set_scan)
);
// Scan MUX to increase coverage
omsp_scan_mux scan_mux_lfxt_wkup_observe (
.scan_mode (scan_mode),
.data_in_scan (lfxt_wkup_set),
.data_in_func (1'b0),
.data_out (lfxt_wkup_set_scan_observe)
);
// The wakeup is asynchronously set, synchronously released
wire lfxt_wkup_n;
omsp_sync_cell sync_cell_lfxt_wkup (
.data_out (lfxt_wkup_n),
.data_in (1'b1),
.clk (lfxt_clk_n),
.rst (lfxt_wkup_set_scan)
);
omsp_and_gate and_lfxt_wkup (.y(lfxt_wkup), .a(~lfxt_wkup_n), .b(cpu_en));
`else
assign lfxt_enable = 1'b1;
assign lfxt_wkup = 1'b0;
wire UNUSED_oscoff = oscoff;
wire UNUSED_cpuoff_and_mclk_enable = cpuoff_and_mclk_enable;
wire UNUSED_cpu_en_wkup2 = cpu_en_wkup;
`endif
// FPGA MODE
//---------------------------------------
// Synchronize LFXT_CLK & edge detection
`else
wire lfxt_clk_s;
omsp_sync_cell sync_cell_lfxt_clk (
.data_out (lfxt_clk_s),
.data_in (lfxt_clk),
.clk (nodiv_mclk),
.rst (por)
);
reg lfxt_clk_dly;
always @ (posedge nodiv_mclk or posedge por)
if (por) lfxt_clk_dly <= 1'b0;
else lfxt_clk_dly <= lfxt_clk_s;
wire lfxt_clk_en = (lfxt_clk_s & ~lfxt_clk_dly) & (~oscoff | (mclk_dma_enable & bcsctl1[`DMA_OSCOFF]));
assign lfxt_enable = 1'b1;
assign lfxt_wkup = 1'b0;
`endif
//=============================================================================
// 6) CLOCK GENERATION
//=============================================================================
//-----------------------------------------------------------
// 6.1) GLOBAL CPU ENABLE
//----------------------------------------------------------
// ACLK and SMCLK are directly switched-off
// with the cpu_en pin (after synchronization).
// MCLK will be switched off once the CPU reaches
// its IDLE state (through the mclk_enable signal)
// Synchronize CPU_EN signal to the MCLK domain
//----------------------------------------------
`ifdef SYNC_CPU_EN
omsp_sync_cell sync_cell_cpu_en (
.data_out (cpu_en_s),
.data_in (cpu_en),
.clk (nodiv_mclk),
.rst (por)
);
omsp_and_gate and_cpu_en_wkup (.y(cpu_en_wkup), .a(cpu_en), .b(~cpu_en_s));
`else
assign cpu_en_s = cpu_en;
assign cpu_en_wkup = 1'b0;
`endif
// Synchronize CPU_EN signal to the ACLK domain
//----------------------------------------------
`ifdef LFXT_DOMAIN
wire cpu_en_aux_s;
omsp_sync_cell sync_cell_cpu_aux_en (
.data_out (cpu_en_aux_s),
.data_in (cpu_en),
.clk (lfxt_clk),
.rst (por)
);
`else
wire cpu_en_aux_s = cpu_en_s;
`endif
// Synchronize CPU_EN signal to the SMCLK domain
//----------------------------------------------
// Note: the synchronizer is only required if there is a SMCLK_MUX
`ifdef ASIC_CLOCKING
`ifdef SMCLK_MUX
wire cpu_en_sm_s;
omsp_sync_cell sync_cell_cpu_sm_en (
.data_out (cpu_en_sm_s),
.data_in (cpu_en),
.clk (nodiv_smclk),
.rst (por)
);
`else
wire cpu_en_sm_s = cpu_en_s;
`endif
`endif
//-----------------------------------------------------------
// 6.2) MCLK GENERATION
//-----------------------------------------------------------
// Clock MUX
//----------------------------
`ifdef MCLK_MUX
omsp_clock_mux clock_mux_mclk (
.clk_out (nodiv_mclk),
.clk_in0 (dco_clk),
.clk_in1 (lfxt_clk),
.reset (por),
.scan_mode (scan_mode),
.select_in (bcsctl2[`SELMx])
);
`else
assign nodiv_mclk = dco_clk;
`endif
// Wakeup synchronizer
//----------------------------
wire cpuoff_and_mclk_dma_wkup_s;
wire mclk_wkup_s;
`ifdef CPUOFF_EN
`ifdef DMA_IF_EN
omsp_sync_cell sync_cell_mclk_dma_wkup (
.data_out (cpuoff_and_mclk_dma_wkup_s),
.data_in (cpuoff_and_mclk_dma_wkup),
.clk (nodiv_mclk),
.rst (puc_rst)
);
`else
assign cpuoff_and_mclk_dma_wkup_s = 1'b0;
`endif
omsp_sync_cell sync_cell_mclk_wkup (
.data_out (mclk_wkup_s),
.data_in (mclk_wkup),
.clk (nodiv_mclk),
.rst (puc_rst)
);
`else
assign cpuoff_and_mclk_dma_wkup_s = 1'b0;
assign mclk_wkup_s = 1'b0;
wire UNUSED_mclk_wkup = mclk_wkup;
`endif
// Clock Divider
//----------------------------
// No need for extra synchronizer as bcsctl2
// comes from the same clock domain.
`ifdef CPUOFF_EN
wire mclk_active = mclk_enable | mclk_wkup_s | (dbg_en_s & cpu_en_s);
wire mclk_dma_active = cpuoff_and_mclk_dma_enable | cpuoff_and_mclk_dma_wkup_s | mclk_active;
`else
wire mclk_active = 1'b1;
wire mclk_dma_active = 1'b1;
`endif
`ifdef MCLK_DIVIDER
reg [2:0] mclk_div;
always @ (posedge nodiv_mclk or posedge puc_rst)
if (puc_rst) mclk_div <= 3'h0;
else if ((bcsctl2[`DIVMx]!=2'b00)) mclk_div <= mclk_div+3'h1;
wire mclk_div_sel = (bcsctl2[`DIVMx]==2'b00) ? 1'b1 :
(bcsctl2[`DIVMx]==2'b01) ? mclk_div[0] :
(bcsctl2[`DIVMx]==2'b10) ? &mclk_div[1:0] :
&mclk_div[2:0] ;
wire mclk_div_en = mclk_active & mclk_div_sel;
wire mclk_dma_div_en = mclk_dma_active & mclk_div_sel;
`else
wire mclk_div_en = mclk_active;
wire mclk_dma_div_en = mclk_dma_active;
`endif
// Generate main system clock
//----------------------------
`ifdef MCLK_CGATE
omsp_clock_gate clock_gate_mclk (
.gclk (cpu_mclk),
.clk (nodiv_mclk),
.enable (mclk_div_en),
.scan_enable (scan_enable)
);
`ifdef DMA_IF_EN
omsp_clock_gate clock_gate_dma_mclk (
.gclk (dma_mclk),
.clk (nodiv_mclk),
.enable (mclk_dma_div_en),
.scan_enable (scan_enable)
);
`else
assign dma_mclk = cpu_mclk;
`endif
`else
assign cpu_mclk = nodiv_mclk;
assign dma_mclk = nodiv_mclk;
`endif
//-----------------------------------------------------------
// 6.3) ACLK GENERATION
//-----------------------------------------------------------
// ASIC MODE
//----------------------------
`ifdef ASIC_CLOCKING
`ifdef ACLK_DIVIDER
`ifdef LFXT_DOMAIN
wire nodiv_aclk = lfxt_clk;
// Synchronizers
//------------------------------------------------------
// Local Reset synchronizer
wire puc_lfxt_noscan_n;
wire puc_lfxt_rst;
omsp_sync_cell sync_cell_puc_lfxt (
.data_out (puc_lfxt_noscan_n),
.data_in (1'b1),
.clk (nodiv_aclk),
.rst (puc_rst)
);
omsp_scan_mux scan_mux_puc_lfxt (
.scan_mode (scan_mode),
.data_in_scan (por_a),
.data_in_func (~puc_lfxt_noscan_n),
.data_out (puc_lfxt_rst)
);
// If the OSCOFF mode is enabled synchronize OSCOFF signal
wire oscoff_s;
`ifdef OSCOFF_EN
omsp_sync_cell sync_cell_oscoff (
.data_out (oscoff_s),
.data_in (oscoff),
.clk (nodiv_aclk),
.rst (puc_lfxt_rst)
);
`else
assign oscoff_s = 1'b0;
`endif
// Local synchronizer for the bcsctl1.DIVAx configuration
// (note that we can live with a full bus synchronizer as
// it won't hurt if we get a wrong DIVAx value for a single clock cycle)
reg [1:0] divax_s;
reg [1:0] divax_ss;
always @ (posedge nodiv_aclk or posedge puc_lfxt_rst)
if (puc_lfxt_rst)
begin
divax_s <= 2'h0;
divax_ss <= 2'h0;
end
else
begin
divax_s <= bcsctl1[`DIVAx];
divax_ss <= divax_s;
end
`else
wire puc_lfxt_rst = puc_rst;
wire nodiv_aclk = dco_clk;
wire [1:0] divax_ss = bcsctl1[`DIVAx];
wire oscoff_s = oscoff;
`endif
// Wakeup synchronizer
//----------------------------
wire oscoff_and_mclk_dma_enable_s;
`ifdef OSCOFF_EN
`ifdef DMA_IF_EN
omsp_sync_cell sync_cell_aclk_dma_wkup (
.data_out (oscoff_and_mclk_dma_enable_s),
.data_in (oscoff_and_mclk_dma_wkup | oscoff_and_mclk_dma_enable),
.clk (nodiv_aclk),
.rst (puc_lfxt_rst)
);
`else
assign oscoff_and_mclk_dma_enable_s = 1'b0;
`endif
`else
assign oscoff_and_mclk_dma_enable_s = 1'b0;
`endif
// Clock Divider
//----------------------------
wire aclk_active = cpu_en_aux_s & (~oscoff_s | oscoff_and_mclk_dma_enable_s);
reg [2:0] aclk_div;
always @ (posedge nodiv_aclk or posedge puc_lfxt_rst)
if (puc_lfxt_rst) aclk_div <= 3'h0;
else if ((divax_ss!=2'b00)) aclk_div <= aclk_div+3'h1;
wire aclk_div_sel = ((divax_ss==2'b00) ? 1'b1 :
(divax_ss==2'b01) ? aclk_div[0] :
(divax_ss==2'b10) ? &aclk_div[1:0] :
&aclk_div[2:0]);
wire aclk_div_en = aclk_active & aclk_div_sel;
// Clock gate
omsp_clock_gate clock_gate_aclk (
.gclk (aclk),
.clk (nodiv_aclk),
.enable (aclk_div_en),
.scan_enable (scan_enable)
);
`else
`ifdef LFXT_DOMAIN
assign aclk = lfxt_clk;
`else
assign aclk = dco_clk;
`endif
wire UNUSED_cpu_en_aux_s = cpu_en_aux_s;
`endif
`ifdef LFXT_DOMAIN
`else
wire UNUSED_lfxt_clk = lfxt_clk;
`endif
assign aclk_en = 1'b1;
// FPGA MODE
//----------------------------
`else
reg aclk_en;
reg [2:0] aclk_div;
wire aclk_en_nxt = lfxt_clk_en & ((bcsctl1[`DIVAx]==2'b00) ? 1'b1 :
(bcsctl1[`DIVAx]==2'b01) ? aclk_div[0] :
(bcsctl1[`DIVAx]==2'b10) ? &aclk_div[1:0] :
&aclk_div[2:0]);
always @ (posedge nodiv_mclk or posedge puc_rst)
if (puc_rst) aclk_div <= 3'h0;
else if ((bcsctl1[`DIVAx]!=2'b00) & lfxt_clk_en) aclk_div <= aclk_div+3'h1;
always @ (posedge nodiv_mclk or posedge puc_rst)
if (puc_rst) aclk_en <= 1'b0;
else aclk_en <= aclk_en_nxt & cpu_en_s;
assign aclk = nodiv_mclk;
wire UNUSED_scan_enable = scan_enable;
wire UNUSED_scan_mode = scan_mode;
`endif
//-----------------------------------------------------------
// 6.4) SMCLK GENERATION
//-----------------------------------------------------------
// Clock MUX
//----------------------------
`ifdef SMCLK_MUX
omsp_clock_mux clock_mux_smclk (
.clk_out (nodiv_smclk),
.clk_in0 (dco_clk),
.clk_in1 (lfxt_clk),
.reset (por),
.scan_mode (scan_mode),
.select_in (bcsctl2[`SELS])
);
`else
assign nodiv_smclk = dco_clk;
`endif
// ASIC MODE
//----------------------------
`ifdef ASIC_CLOCKING
`ifdef SMCLK_MUX
// SMCLK_MUX Synchronizers
//------------------------------------------------------
// When the SMCLK MUX is enabled, the reset and DIVSx
// and SCG1 signals must be synchronized, otherwise not.
// Local Reset synchronizer
wire puc_sm_noscan_n;
wire puc_sm_rst;
omsp_sync_cell sync_cell_puc_sm (
.data_out (puc_sm_noscan_n),
.data_in (1'b1),
.clk (nodiv_smclk),
.rst (puc_rst)
);
omsp_scan_mux scan_mux_puc_sm (
.scan_mode (scan_mode),
.data_in_scan (por_a),
.data_in_func (~puc_sm_noscan_n),
.data_out (puc_sm_rst)
);
// SCG1 synchronizer
wire scg1_s;
`ifdef SCG1_EN
omsp_sync_cell sync_cell_scg1 (
.data_out (scg1_s),
.data_in (scg1),
.clk (nodiv_smclk),
.rst (puc_sm_rst)
);
`else
assign scg1_s = 1'b0;
wire UNUSED_scg1 = scg1;
wire UNUSED_puc_sm_rst = puc_sm_rst;
`endif
`ifdef SMCLK_DIVIDER
// Local synchronizer for the bcsctl2.DIVSx configuration
// (note that we can live with a full bus synchronizer as
// it won't hurt if we get a wrong DIVSx value for a single clock cycle)
reg [1:0] divsx_s;
reg [1:0] divsx_ss;
always @ (posedge nodiv_smclk or posedge puc_sm_rst)
if (puc_sm_rst)
begin
divsx_s <= 2'h0;
divsx_ss <= 2'h0;
end
else
begin
divsx_s <= bcsctl2[`DIVSx];
divsx_ss <= divsx_s;
end
`endif
`else
wire puc_sm_rst = puc_rst;
wire [1:0] divsx_ss = bcsctl2[`DIVSx];
wire scg1_s = scg1;
`endif
// Wakeup synchronizer
//----------------------------
wire scg1_and_mclk_dma_enable_s;
`ifdef SCG1_EN
`ifdef DMA_IF_EN
`ifdef SMCLK_MUX
omsp_sync_cell sync_cell_smclk_dma_wkup (
.data_out (scg1_and_mclk_dma_enable_s),
.data_in (scg1_and_mclk_dma_wkup | scg1_and_mclk_dma_enable),
.clk (nodiv_smclk),
.rst (puc_sm_rst)
);
`else
wire scg1_and_mclk_dma_wkup_s;
omsp_sync_cell sync_cell_smclk_dma_wkup (
.data_out (scg1_and_mclk_dma_wkup_s),
.data_in (scg1_and_mclk_dma_wkup),
.clk (nodiv_smclk),
.rst (puc_sm_rst)
);
assign scg1_and_mclk_dma_enable_s = scg1_and_mclk_dma_wkup_s | scg1_and_mclk_dma_enable;
`endif
`else
assign scg1_and_mclk_dma_enable_s = 1'b0;
`endif
`else
assign scg1_and_mclk_dma_enable_s = 1'b0;
`endif
// Clock Divider
//----------------------------
`ifdef SCG1_EN
wire smclk_active = cpu_en_sm_s & (~scg1_s | scg1_and_mclk_dma_enable_s);
`else
wire smclk_active = cpu_en_sm_s;
`endif
`ifdef SMCLK_DIVIDER
reg [2:0] smclk_div;
always @ (posedge nodiv_smclk or posedge puc_sm_rst)
if (puc_sm_rst) smclk_div <= 3'h0;
else if ((divsx_ss!=2'b00)) smclk_div <= smclk_div+3'h1;
wire smclk_div_sel = ((divsx_ss==2'b00) ? 1'b1 :
(divsx_ss==2'b01) ? smclk_div[0] :
(divsx_ss==2'b10) ? &smclk_div[1:0] :
&smclk_div[2:0]);
wire smclk_div_en = smclk_active & smclk_div_sel;
`else
wire smclk_div_en = smclk_active;
`endif
// Generate sub-system clock
//----------------------------
`ifdef SMCLK_CGATE
omsp_clock_gate clock_gate_smclk (
.gclk (smclk),
.clk (nodiv_smclk),
.enable (smclk_div_en),
.scan_enable (scan_enable)
);
`else
assign smclk = nodiv_smclk;
`endif
assign smclk_en = 1'b1;
// FPGA MODE
//----------------------------
`else
reg smclk_en;
reg [2:0] smclk_div;
wire smclk_in = (scg1 & ~(mclk_dma_enable & bcsctl1[`DMA_SCG1])) ? 1'b0 :
bcsctl2[`SELS] ? lfxt_clk_en : 1'b1;
wire smclk_en_nxt = smclk_in & ((bcsctl2[`DIVSx]==2'b00) ? 1'b1 :
(bcsctl2[`DIVSx]==2'b01) ? smclk_div[0] :
(bcsctl2[`DIVSx]==2'b10) ? &smclk_div[1:0] :
&smclk_div[2:0]);
always @ (posedge nodiv_mclk or posedge puc_rst)
if (puc_rst) smclk_en <= 1'b0;
else smclk_en <= smclk_en_nxt & cpu_en_s;
always @ (posedge nodiv_mclk or posedge puc_rst)
if (puc_rst) smclk_div <= 3'h0;
else if ((bcsctl2[`DIVSx]!=2'b00) & smclk_in) smclk_div <= smclk_div+3'h1;
wire smclk = nodiv_mclk;
`endif
//-----------------------------------------------------------
// 6.5) DEBUG INTERFACE CLOCK GENERATION (DBG_CLK)
//-----------------------------------------------------------
// Synchronize DBG_EN signal to MCLK domain
//------------------------------------------
`ifdef DBG_EN
`ifdef SYNC_DBG_EN
wire dbg_en_n_s;
omsp_sync_cell sync_cell_dbg_en (
.data_out (dbg_en_n_s),
.data_in (~dbg_en),
.clk (cpu_mclk),
.rst (por)
);
assign dbg_en_s = ~dbg_en_n_s;
wire dbg_rst_nxt = dbg_en_n_s;
`else
assign dbg_en_s = dbg_en;
wire dbg_rst_nxt = ~dbg_en;
`endif
`else
assign dbg_en_s = 1'b0;
wire dbg_rst_nxt = 1'b0;
wire UNUSED_dbg_en = dbg_en;
`endif
// Serial Debug Interface Clock gate
//------------------------------------------------
`ifdef DBG_EN
`ifdef ASIC_CLOCKING
omsp_clock_gate clock_gate_dbg_clk (
.gclk (dbg_clk),
.clk (cpu_mclk),
.enable (dbg_en_s),
.scan_enable (scan_enable)
);
`else
assign dbg_clk = dco_clk;
`endif
`else
assign dbg_clk = 1'b0;
`endif
//=============================================================================
// 7) RESET GENERATION
//=============================================================================
//
// Whenever the reset pin (reset_n) is deasserted, the internal resets of the
// openMSP430 will be released in the following order:
// 1- POR
// 2- DBG_RST (if the sdi interface is enabled, i.e. dbg_en=1)
// 3- PUC
//
// Note: releasing the DBG_RST before PUC is particularly important in order
// to allow the sdi interface to halt the cpu immediately after a PUC.
//
// Generate synchronized POR to MCLK domain
//------------------------------------------
// Asynchronous reset source
assign por_a = !reset_n;
wire por_noscan;
// Reset Synchronizer
omsp_sync_reset sync_reset_por (
.rst_s (por_noscan),
.clk (nodiv_mclk),
.rst_a (por_a)
);
// Scan Reset Mux
`ifdef ASIC
omsp_scan_mux scan_mux_por (
.scan_mode (scan_mode),
.data_in_scan (por_a),
.data_in_func (por_noscan),
.data_out (por)
);
`else
assign por = por_noscan;
`endif
// Generate synchronized reset for the SDI
//------------------------------------------
`ifdef DBG_EN
// Reset Generation
reg dbg_rst_noscan;
always @ (posedge cpu_mclk or posedge por)
if (por) dbg_rst_noscan <= 1'b1;
else dbg_rst_noscan <= dbg_rst_nxt;
// Scan Reset Mux
`ifdef ASIC
omsp_scan_mux scan_mux_dbg_rst (
.scan_mode (scan_mode),
.data_in_scan (por_a),
.data_in_func (dbg_rst_noscan),
.data_out (dbg_rst)
);
`else
assign dbg_rst = dbg_rst_noscan;
`endif
`else
wire dbg_rst_noscan = 1'b1;
assign dbg_rst = 1'b1;
`endif
// Generate main system reset (PUC_RST)
//--------------------------------------
wire puc_noscan_n;
wire puc_a_scan;
// Asynchronous PUC reset
wire puc_a = por | wdt_reset;
// Synchronous PUC reset
wire puc_s = dbg_cpu_reset | // With the debug interface command
(dbg_en_s & dbg_rst_noscan & ~puc_noscan_n); // Sequencing making sure PUC is released
// after DBG_RST if the debug interface is
// enabled at power-on-reset time
// Scan Reset Mux
`ifdef ASIC
omsp_scan_mux scan_mux_puc_rst_a (
.scan_mode (scan_mode),
.data_in_scan (por_a),
.data_in_func (puc_a),
.data_out (puc_a_scan)
);
`else
assign puc_a_scan = puc_a;
`endif
// Reset Synchronizer
// (required because of the asynchronous watchdog reset)
omsp_sync_cell sync_cell_puc (
.data_out (puc_noscan_n),
.data_in (~puc_s),
.clk (cpu_mclk),
.rst (puc_a_scan)
);
// Scan Reset Mux
`ifdef ASIC
omsp_scan_mux scan_mux_puc_rst (
.scan_mode (scan_mode),
.data_in_scan (por_a),
.data_in_func (~puc_noscan_n),
.data_out (puc_rst)
);
`else
assign puc_rst = ~puc_noscan_n;
`endif
// PUC pending set the serial debug interface
assign puc_pnd_set = ~puc_noscan_n;
endmodule // omsp_clock_module
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rxr_engine_classic.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The RXR Engine (Classic) takes a single stream of TLP
// packets and provides the request packets on the RXR Interface.
// This Engine is capable of operating at "line rate".
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh"
`include "tlp.vh"
module rxr_engine_classic
#(parameter C_VENDOR = "ALTERA",
parameter C_PCI_DATA_WIDTH = 128,
parameter C_RX_PIPELINE_DEPTH=10)
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RXR_RST,
// Interface: RX Classic
input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
input RX_TLP_VALID,
input RX_TLP_START_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_START_OFFSET,
input RX_TLP_END_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_END_OFFSET,
input [`SIG_BARDECODE_W-1:0] RX_TLP_BAR_DECODE,
// Interface: RXR
output [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
output RXR_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE,
output RXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
output RXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
output [`SIG_FBE_W-1:0] RXR_META_FDWBE,
output [`SIG_LBE_W-1:0] RXR_META_LDWBE,
output [`SIG_TC_W-1:0] RXR_META_TC,
output [`SIG_ATTR_W-1:0] RXR_META_ATTR,
output [`SIG_TAG_W-1:0] RXR_META_TAG,
output [`SIG_TYPE_W-1:0] RXR_META_TYPE,
output [`SIG_ADDR_W-1:0] RXR_META_ADDR,
output [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
output [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
output [`SIG_LEN_W-1:0] RXR_META_LENGTH,
output RXR_META_EP,
// Interface: RX Shift Register
input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_EOP,
input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_END_OFFSET,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_SOP,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_VALID
);
/*AUTOWIRE*/
///*AUTOOUTPUT*/
// End of automatics
localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);
localparam C_RX_INPUT_STAGES = 1;
localparam C_RX_OUTPUT_STAGES = 1; // Must always be at least one
localparam C_RX_COMPUTATION_STAGES = 1;
localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES;
// Cycle index in the SOP register when enable is raised
// Computation can begin when the last DW of the header is recieved.
localparam C_RX_COMPUTATION_CYCLE = C_RX_COMPUTATION_STAGES + (`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
// The computation cycle must be at least one cycle before the address is enabled
localparam C_RX_DATA_CYCLE = C_RX_COMPUTATION_CYCLE;
localparam C_RX_ADDRDW0_CYCLE = (`TLP_REQADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_ADDRDW1_CYCLE = (`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW0_CYCLE = (`TLP_REQMETADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW1_CYCLE = (`TLP_REQMETADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_ADDRDW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQADDRDW0_I%C_PCI_DATA_WIDTH);
localparam C_RX_ADDRDW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQADDRDW1_I%C_PCI_DATA_WIDTH);
localparam C_RX_ADDRDW1_RESET_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES +
C_PCI_DATA_WIDTH*(C_RX_ADDRDW1_CYCLE - C_RX_METADW0_CYCLE) +
`TLP_4DWHBIT_I;
localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQMETADW0_I%C_PCI_DATA_WIDTH);
localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQMETADW1_I%C_PCI_DATA_WIDTH);
localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
localparam C_MAX_ABLANK_WIDTH = 32;
localparam C_MAX_START_OFFSET = (`TLP_MAXHDR_W + C_MAX_ABLANK_WIDTH)/32;
localparam C_STD_START_DELAY = (64/C_PCI_DATA_WIDTH);
wire [63:0] wAddrFmt;
wire [63:0] wMetadata;
wire [`TLP_TYPE_W-1:0] wType;
wire [`TLP_LEN_W-1:0] wLength;
wire wAddrDW0Bit2;
wire wAddrDW1Bit2;
wire wAddrHiReset;
wire [31:0] wAddrMux[(`TLP_REQADDR_W / 32)-1:0];
wire [63:0] wAddr;
wire w4DWH;
wire wHasPayload;
wire [2:0] wHdrLength;
wire [2:0] wHdrLengthM1;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wEndMask;
wire _wEndFlag;
wire wEndFlag;
wire [C_OFFSET_WIDTH-1:0] wEndOffset;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wStartMask;
wire [3:0] wStartFlags;
wire wStartFlag;
wire _wStartFlag;
wire [clog2s(C_MAX_START_OFFSET)-1:0] wStartOffset;
wire wInsertBlank;
wire wRotateAddressField;
wire [C_PCI_DATA_WIDTH-1:0] wRxrData;
wire [`SIG_ADDR_W-1:0] wRxrMetaAddr;
wire [63:0] wRxrMetadata;
wire wRxrDataValid;
wire wRxrDataReady; // Pinned High
wire wRxrDataEndFlag;
wire [C_OFFSET_WIDTH-1:0] wRxrDataEndOffset;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataWordEnable;
wire wRxrDataStartFlag;
wire [C_OFFSET_WIDTH-1:0] wRxrDataStartOffset;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrSop;
reg rValid,_rValid;
reg rRST;
assign DONE_RXR_RST = ~rRST;
assign wAddrHiReset = ~RX_SR_DATA[C_RX_ADDRDW1_RESET_INDEX];
// Select Addr[31:0] from one of the two possible locations in the TLP based
// on header length (1 bit)
assign wRotateAddressField = w4DWH;
assign wAddrFmt = {wAddrMux[~wRotateAddressField],wAddrMux[wRotateAddressField]};
assign wAddrMux[0] = wAddr[31:0];
assign wAddrMux[1] = wAddr[63:32];
// Calculate the header length (start offset), and header length minus 1 (end offset)
assign wHdrLength = {w4DWH,~w4DWH,~w4DWH};
assign wHdrLengthM1 = {1'b0,1'b1,w4DWH};
// Determine if the TLP has an inserted blank before the payload
assign wInsertBlank = ((w4DWH & wAddrDW1Bit2) | (~w4DWH & ~wAddrDW0Bit2)) & (C_VENDOR == "ALTERA");
assign wStartOffset = (wHdrLength + {2'd0,wInsertBlank}); // Start offset in dwords
assign wEndOffset = wHdrLengthM1 + wInsertBlank + wLength;//RX_SR_END_OFFSET[(C_TOTAL_STAGES-1)*`SIG_OFFSET_W +: C_OFFSET_WIDTH];
// Inputs
// Technically an input, but the trellis protocol specifies it must be held high at all times
assign wRxrDataReady = 1;
// Outputs
assign RXR_DATA = RX_SR_DATA[(C_TOTAL_STAGES)*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
assign RXR_DATA_VALID = wRxrDataValid;
assign RXR_DATA_END_FLAG = wRxrDataEndFlag;
assign RXR_DATA_END_OFFSET = wRxrDataEndOffset;
assign RXR_DATA_START_FLAG = wRxrDataStartFlag;
assign RXR_DATA_START_OFFSET = wRxrDataStartOffset;
assign RXR_META_BAR_DECODED = 0;
assign RXR_META_LENGTH = wRxrMetadata[`TLP_LEN_R];
assign RXR_META_TC = wRxrMetadata[`TLP_TC_R];
assign RXR_META_ATTR = {wRxrMetadata[`TLP_ATTR1_R], wRxrMetadata[`TLP_ATTR0_R]};
assign RXR_META_TYPE = tlp_to_trellis_type({wRxrMetadata[`TLP_FMT_R],wRxrMetadata[`TLP_TYPE_R]});
assign RXR_META_ADDR = wRxrMetaAddr;
assign RXR_META_REQUESTER_ID = wRxrMetadata[`TLP_REQREQID_R];
assign RXR_META_TAG = wRxrMetadata[`TLP_REQTAG_R];
assign RXR_META_FDWBE = wRxrMetadata[`TLP_REQFBE_R];
assign RXR_META_LDWBE = wRxrMetadata[`TLP_REQLBE_R];
assign RXR_META_EP = wRxrMetadata[`TLP_EP_R];
assign _wEndFlag = RX_SR_EOP[C_RX_INPUT_STAGES];
assign wEndFlag = RX_SR_EOP[C_RX_INPUT_STAGES+1];
assign _wStartFlag = wStartFlags != 0;
generate
if(C_PCI_DATA_WIDTH == 32) begin
assign wStartFlags[3] = 0;
assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 3] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Any remaining cases
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 2] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I]; // 3DWH, No Blank
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 2] & ~wMetadata[`TLP_PAYBIT_I]; // No Payload
end else if(C_PCI_DATA_WIDTH == 64) begin
assign wStartFlags[3] = 0;
assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 2] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Any remaining cases
if(C_VENDOR == "ALTERA") begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I] & RX_SR_DATA[C_RX_ADDRDW0_INDEX + 2]; // 3DWH, No Blank
end else begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I]; // 3DWH, No Blank
end
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 1] & ~wMetadata[`TLP_PAYBIT_I]; // No Payload
end else if (C_PCI_DATA_WIDTH == 128) begin
assign wStartFlags[3] = 0;
assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Is this correct?
if(C_VENDOR == "ALTERA") begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES] & RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_4DWHBIT_I] & RX_SR_DATA[C_RX_ADDRDW0_INDEX + 2]; // 3DWH, No Blank
end else begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES] & RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_4DWHBIT_I];
end
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I]; // No Payload
end else begin // 256
assign wStartFlags[3] = 0;
assign wStartFlags[2] = 0;
assign wStartFlags[1] = 0;
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
end // else: !if(C_PCI_DATA_WIDTH == 128)
endgenerate
always @(*) begin
_rValid = rValid;
if(_wStartFlag) begin
_rValid = 1'b1;
end else if (wEndFlag) begin
_rValid = 1'b0;
end
end
always @(posedge CLK) begin
if(rRST) begin
rValid <= 1'b0;
end else begin
rValid <= _rValid;
end
end
always @(posedge CLK) begin
rRST <= RST_BUS | RST_LOGIC;
end
assign wStartMask = {C_PCI_DATA_WIDTH/32{1'b1}} << ({C_OFFSET_WIDTH{wStartFlag}}& wStartOffset[C_OFFSET_WIDTH-1:0]);
offset_to_mask
#(// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (C_PCI_DATA_WIDTH/32)
/*AUTOINSTPARAM*/)
o2m_ef
(
// Outputs
.MASK (wEndMask),
// Inputs
.OFFSET_ENABLE (wEndFlag),
.OFFSET (wEndOffset[C_OFFSET_WIDTH-1:0])
/*AUTOINST*/);
generate
if(C_RX_OUTPUT_STAGES == 0) begin
assign RXR_DATA_WORD_ENABLE = {wEndMask & wStartMask} & {C_PCI_DATA_WIDTH/32{~rValid | ~wMetadata[`TLP_PAYBIT_I]}};
end else begin
register
#(
// Parameters
.C_WIDTH (C_PCI_DATA_WIDTH/32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
dw_enable
(// Outputs
.RD_DATA (wRxrDataWordEnable),
// Inputs
.RST_IN (~rValid | ~wMetadata[`TLP_PAYBIT_I]),
.WR_DATA (wEndMask & wStartMask),
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
pipeline
#(
// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES-1),
.C_WIDTH (C_PCI_DATA_WIDTH/32),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
dw_pipeline
(// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA (RXR_DATA_WORD_ENABLE),
.RD_DATA_VALID (),
// Inputs
.WR_DATA (wRxrDataWordEnable),
.WR_DATA_VALID (1),
.RD_DATA_READY (1'b1),
.RST_IN (rRST),
/*AUTOINST*/
// Inputs
.CLK (CLK));
end
endgenerate
register
#(
// Parameters
.C_WIDTH (32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata_DW0_register
(
// Outputs
.RD_DATA (wMetadata[31:0]),
// Inputs
.WR_DATA (RX_SR_DATA[C_RX_METADW0_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW0_CYCLE]),
.RST_IN (rRST),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
meta_DW1_register
(// Outputs
.RD_DATA (wMetadata[63:32]),
// Inputs
.WR_DATA (RX_SR_DATA[C_RX_METADW1_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW1_CYCLE]),
.RST_IN (rRST),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
addr_DW0_register
(// Outputs
.RD_DATA (wAddr[31:0]),
// Inputs
.WR_DATA (RX_SR_DATA[C_RX_ADDRDW0_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_ADDRDW0_CYCLE]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
addr_DW1_register
(// Outputs
.RD_DATA (wAddr[63:32]),
// Inputs
.WR_DATA (RX_SR_DATA[C_RX_ADDRDW1_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_ADDRDW1_CYCLE]),
.RST_IN (wAddrHiReset & wRxSrSop[C_RX_ADDRDW1_CYCLE]),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (2),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata_4DWH_register
(// Outputs
.RD_DATA ({wHasPayload,w4DWH}),
// Inputs
.WR_DATA (RX_SR_DATA[`TLP_FMT_I + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES +: 2]),
.WR_EN (wRxSrSop[`TLP_4DWHBIT_I/C_PCI_DATA_WIDTH + C_RX_INPUT_STAGES]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (`TLP_TYPE_W),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata_type_register
(// Outputs
.RD_DATA (wType),
// Inputs
.WR_DATA (RX_SR_DATA[(`TLP_TYPE_I/* + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES*/) +: `TLP_TYPE_W]),
.WR_EN (wRxSrSop[`TLP_TYPE_I/C_PCI_DATA_WIDTH/* + C_RX_INPUT_STAGES*/]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (`TLP_LEN_W),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata_length_register
(// Outputs
.RD_DATA (wLength),
// Inputs
.WR_DATA (RX_SR_DATA[(`TLP_LEN_I + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES) +: `TLP_LEN_W]),
.WR_EN (wRxSrSop[`TLP_LEN_I/C_PCI_DATA_WIDTH + C_RX_INPUT_STAGES]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
addr_DW0_bit_2_register
(// Outputs
.RD_DATA (wAddrDW0Bit2),
// Inputs
.RST_IN (0),
.WR_DATA (RX_SR_DATA[(`TLP_REQADDRDW0_I%C_PCI_DATA_WIDTH) + 2 + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES]),
.WR_EN (wRxSrSop[(`TLP_REQADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES]),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
addr_DW1_bit_2_register
(// Outputs
.RD_DATA (wAddrDW1Bit2),
// Inputs
.WR_DATA (RX_SR_DATA[(`TLP_REQADDRDW1_I%C_PCI_DATA_WIDTH) + 2 + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES]),
.WR_EN (wRxSrSop[(`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
start_flag_register
(// Outputs
.RD_DATA (wStartFlag),
// Inputs
.WR_DATA (_wStartFlag),
.WR_EN (1),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
pipeline
#(// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES),
.C_WIDTH (`TLP_MAXHDR_W + 2*(1 + C_OFFSET_WIDTH)),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_pipeline
(// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA ({wRxrMetadata,wRxrMetaAddr,wRxrDataStartFlag,wRxrDataStartOffset,wRxrDataEndFlag,wRxrDataEndOffset}),
.RD_DATA_VALID (wRxrDataValid),
// Inputs
.WR_DATA ({wMetadata, wAddrFmt, wStartFlag,wStartOffset[C_OFFSET_WIDTH-1:0],wEndFlag,wEndOffset[C_OFFSET_WIDTH-1:0]}),
.WR_DATA_VALID (rValid & RX_SR_VALID[C_TOTAL_STAGES-C_RX_OUTPUT_STAGES]),
.RD_DATA_READY (1'b1),
.RST_IN (rRST),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// Start Flag Shift Register. Data enables are derived from the
// taps on this shift register.
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
sop_shiftreg_inst
(// Outputs
.RD_DATA (wRxSrSop),
// Inputs
.WR_DATA (RX_TLP_START_FLAG & RX_TLP_VALID & (RX_SR_DATA[`TLP_TYPE_R] == `TLP_TYPE_REQ)),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common")
// End:
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : BUFGCTRL.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 06272013 723696 - dynamic register change
// 02062014 771896 - specify block update
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFGCTRL #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter integer INIT_OUT = 0,
parameter [0:0] IS_CE0_INVERTED = 1'b0,
parameter [0:0] IS_CE1_INVERTED = 1'b0,
parameter [0:0] IS_I0_INVERTED = 1'b0,
parameter [0:0] IS_I1_INVERTED = 1'b0,
parameter [0:0] IS_IGNORE0_INVERTED = 1'b0,
parameter [0:0] IS_IGNORE1_INVERTED = 1'b0,
parameter [0:0] IS_S0_INVERTED = 1'b0,
parameter [0:0] IS_S1_INVERTED = 1'b0,
parameter PRESELECT_I0 = "FALSE",
parameter PRESELECT_I1 = "FALSE"
)(
output O,
input CE0,
input CE1,
input I0,
input I1,
input IGNORE0,
input IGNORE1,
input S0,
input S1
);
// define constants
localparam MODULE_NAME = "BUFGCTRL";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam INIT_OUT_0 = 0;
localparam INIT_OUT_1 = 1;
localparam PRESELECT_I0_FALSE = 0;
localparam PRESELECT_I0_TRUE = 1;
localparam PRESELECT_I1_FALSE = 0;
localparam PRESELECT_I1_TRUE = 1;
`ifndef XIL_DR
localparam [0:0] INIT_OUT_REG = INIT_OUT;
localparam [0:0] IS_CE0_INVERTED_REG = IS_CE0_INVERTED;
localparam [0:0] IS_CE1_INVERTED_REG = IS_CE1_INVERTED;
localparam [0:0] IS_I0_INVERTED_REG = IS_I0_INVERTED;
localparam [0:0] IS_I1_INVERTED_REG = IS_I1_INVERTED;
localparam [0:0] IS_IGNORE0_INVERTED_REG = IS_IGNORE0_INVERTED;
localparam [0:0] IS_IGNORE1_INVERTED_REG = IS_IGNORE1_INVERTED;
localparam [0:0] IS_S0_INVERTED_REG = IS_S0_INVERTED;
localparam [0:0] IS_S1_INVERTED_REG = IS_S1_INVERTED;
localparam [40:1] PRESELECT_I0_REG = PRESELECT_I0;
localparam [40:1] PRESELECT_I1_REG = PRESELECT_I1;
`endif
wire INIT_OUT_BIN;
wire IS_CE0_INVERTED_BIN;
wire IS_CE1_INVERTED_BIN;
wire IS_I0_INVERTED_BIN;
wire IS_I1_INVERTED_BIN;
wire IS_IGNORE0_INVERTED_BIN;
wire IS_IGNORE1_INVERTED_BIN;
wire IS_S0_INVERTED_BIN;
wire IS_S1_INVERTED_BIN;
wire PRESELECT_I0_BIN;
wire PRESELECT_I1_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "BUFGCTRL_dr.v"
`endif
reg O_out;
wire O_delay;
wire CE0_in;
wire CE1_in;
wire I0_in;
wire I1_in;
wire IGNORE0_in;
wire IGNORE1_in;
wire S0_in;
wire S1_in;
wire CE0_delay;
wire CE1_delay;
wire I0_delay;
wire I1_delay;
wire IGNORE0_delay;
wire IGNORE1_delay;
wire S0_delay;
wire S1_delay;
reg q0, q1;
reg q0_enable, q1_enable;
reg task_input_ce0, task_input_ce1, task_input_i0;
reg task_input_i1, task_input_ignore0, task_input_ignore1;
reg task_input_gsr, task_input_s0, task_input_s1;
wire I0t, I1t;
assign #(out_delay) O = O_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) I0_delay = I0;
assign #(inclk_delay) I1_delay = I1;
assign #(in_delay) CE0_delay = CE0;
assign #(in_delay) CE1_delay = CE1;
assign #(in_delay) S0_delay = S0;
assign #(in_delay) S1_delay = S1;
`endif // `ifndef XIL_TIMING
// inputs with no timing checks
assign #(in_delay) IGNORE0_delay = IGNORE0;
assign #(in_delay) IGNORE1_delay = IGNORE1;
assign O_delay = O_out;
assign CE0_in = (CE0 !== 1'bz) && (CE0_delay ^ IS_CE0_INVERTED_BIN); // rv 0
assign CE1_in = (CE1 !== 1'bz) && (CE1_delay ^ IS_CE1_INVERTED_BIN); // rv 0
assign I0_in = I0_delay ^ IS_I0_INVERTED_BIN;
assign I1_in = I1_delay ^ IS_I1_INVERTED_BIN;
assign IGNORE0_in = (IGNORE0 !== 1'bz) && (IGNORE0_delay ^ IS_IGNORE0_INVERTED_BIN); // rv 0
assign IGNORE1_in = (IGNORE1 !== 1'bz) && (IGNORE1_delay ^ IS_IGNORE1_INVERTED_BIN); // rv 0
assign S0_in = (S0 !== 1'bz) && (S0_delay ^ IS_S0_INVERTED_BIN); // rv 0
assign S1_in = (S1 !== 1'bz) && (S1_delay ^ IS_S1_INVERTED_BIN); // rv 0
initial begin
#1;
trig_attr = ~trig_attr;
end
assign INIT_OUT_BIN =
(INIT_OUT_REG == 0) ? INIT_OUT_0 :
(INIT_OUT_REG == 1) ? INIT_OUT_1 :
INIT_OUT_0;
assign IS_CE0_INVERTED_BIN = IS_CE0_INVERTED_REG;
assign IS_CE1_INVERTED_BIN = IS_CE1_INVERTED_REG;
assign IS_I0_INVERTED_BIN = IS_I0_INVERTED_REG;
assign IS_I1_INVERTED_BIN = IS_I1_INVERTED_REG;
assign IS_IGNORE0_INVERTED_BIN = IS_IGNORE0_INVERTED_REG;
assign IS_IGNORE1_INVERTED_BIN = IS_IGNORE1_INVERTED_REG;
assign IS_S0_INVERTED_BIN = IS_S0_INVERTED_REG;
assign IS_S1_INVERTED_BIN = IS_S1_INVERTED_REG;
assign PRESELECT_I0_BIN =
(PRESELECT_I0_REG == "FALSE") ? PRESELECT_I0_FALSE :
(PRESELECT_I0_REG == "TRUE") ? PRESELECT_I0_TRUE :
PRESELECT_I0_FALSE;
assign PRESELECT_I1_BIN =
(PRESELECT_I1_REG == "FALSE") ? PRESELECT_I1_FALSE :
(PRESELECT_I1_REG == "TRUE") ? PRESELECT_I1_TRUE :
PRESELECT_I1_FALSE;
always @ (trig_attr) begin
#1;
if ((INIT_OUT_REG != 0) &&
(INIT_OUT_REG != 1)) begin
$display("Attribute Syntax Error : The attribute INIT_OUT on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, INIT_OUT_REG);
attr_err = 1'b1;
end
if ((IS_CE0_INVERTED_REG != 1'b0) && (IS_CE0_INVERTED_REG != 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_CE0_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CE0_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_CE1_INVERTED_REG != 1'b0) && (IS_CE1_INVERTED_REG != 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_CE1_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CE1_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_I0_INVERTED_REG != 1'b0) && (IS_I0_INVERTED_REG != 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_I0_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_I0_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_I1_INVERTED_REG != 1'b0) && (IS_I1_INVERTED_REG != 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_I1_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_I1_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_IGNORE0_INVERTED_REG != 1'b0) && (IS_IGNORE0_INVERTED_REG != 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_IGNORE0_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_IGNORE0_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_IGNORE1_INVERTED_REG != 1'b0) && (IS_IGNORE1_INVERTED_REG != 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_IGNORE1_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_IGNORE1_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_S0_INVERTED_REG != 1'b0) && (IS_S0_INVERTED_REG != 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_S0_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_S0_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_S1_INVERTED_REG != 1'b0) && (IS_S1_INVERTED_REG != 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_S1_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_S1_INVERTED_REG);
attr_err = 1'b1;
end
if ((PRESELECT_I0_REG != "FALSE") &&
(PRESELECT_I0_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PRESELECT_I0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PRESELECT_I0_REG);
attr_err = 1'b1;
end
if ((PRESELECT_I1_REG != "FALSE") &&
(PRESELECT_I1_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute PRESELECT_I1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PRESELECT_I1_REG);
attr_err = 1'b1;
end
// *** both preselects can not be 1 simultaneously.
if ((PRESELECT_I0_REG == "TRUE") && (PRESELECT_I1_REG == "TRUE")) begin
$display("Attribute Syntax Error : The attributes PRESELECT_I0 and PRESELECT_I1 on BUFGCTRL instance %m should not be set to TRUE simultaneously.");
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
// *** Start here
assign I0t = INIT_OUT_BIN ^ I0_in;
assign I1t = INIT_OUT_BIN ^ I1_in;
// *** Input enable for i1
always @(IGNORE1_in or I1t or S1_in or glblGSR or q0 or PRESELECT_I1_BIN) begin
if (glblGSR == 1)
q1_enable <= PRESELECT_I1_BIN;
else if (glblGSR == 0) begin
if ((I1t == 0) && (IGNORE1_in == 0))
q1_enable <= q1_enable;
else if ((I1t == 1) || (IGNORE1_in == 1))
q1_enable <= (~q0 && S1_in);
end
end
// *** Output q1 for i1
always @(q1_enable or CE1_in or I1t or IGNORE1_in or glblGSR or PRESELECT_I1_BIN) begin
if (glblGSR == 1)
q1 <= PRESELECT_I1_BIN;
else if (glblGSR == 0) begin
if ((I1t == 1)&& (IGNORE1_in == 0))
q1 <= q1;
else if ((I1t == 0) || (IGNORE1_in == 1))
q1 <= (CE1_in && q1_enable);
end
end
// *** input enable for i0
always @(IGNORE0_in or I0t or S0_in or glblGSR or q1 or PRESELECT_I0_BIN) begin
if (glblGSR == 1)
q0_enable <= PRESELECT_I0_BIN;
else if (glblGSR == 0) begin
if ((I0t == 0) && (IGNORE0_in == 0))
q0_enable <= q0_enable;
else if ((I0t == 1) || (IGNORE0_in == 1))
q0_enable <= (~q1 && S0_in);
end
end
// *** Output q0 for i0
always @(q0_enable or CE0_in or I0t or IGNORE0_in or glblGSR or PRESELECT_I0_BIN) begin
if (glblGSR == 1)
q0 <= PRESELECT_I0_BIN;
else if (glblGSR == 0) begin
if ((I0t == 1) && (IGNORE0_in == 0))
q0 <= q0;
else if ((I0t == 0) || (IGNORE0_in == 1))
q0 <= (CE0_in && q0_enable);
end
end
always @(q0 or q1 or I0t or I1t) begin
case ({q1, q0})
2'b01: O_out = I0_in;
2'b10: O_out = I1_in;
2'b00: O_out = INIT_OUT_BIN;
2'b11: begin
q0 = 1'bx;
q1 = 1'bx;
q0_enable = 1'bx;
q1_enable = 1'bx;
O_out = 1'bx;
end
endcase
end
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (negedge I0, 0:0:0, notifier);
$period (negedge I1, 0:0:0, notifier);
$period (posedge I0, 0:0:0, notifier);
$period (posedge I1, 0:0:0, notifier);
$setuphold (negedge I0, negedge CE0, 0:0:0, 0:0:0, notifier,,, I0_delay, CE0_delay);
$setuphold (negedge I0, negedge S0, 0:0:0, 0:0:0, notifier,,, I0_delay, S0_delay);
$setuphold (negedge I0, posedge CE0, 0:0:0, 0:0:0, notifier,,, I0_delay, CE0_delay);
$setuphold (negedge I0, posedge S0, 0:0:0, 0:0:0, notifier,,, I0_delay, S0_delay);
$setuphold (negedge I1, negedge CE1, 0:0:0, 0:0:0, notifier,,, I1_delay, CE1_delay);
$setuphold (negedge I1, negedge S1, 0:0:0, 0:0:0, notifier,,, I1_delay, S1_delay);
$setuphold (negedge I1, posedge CE1, 0:0:0, 0:0:0, notifier,,, I1_delay, CE1_delay);
$setuphold (negedge I1, posedge S1, 0:0:0, 0:0:0, notifier,,, I1_delay, S1_delay);
$setuphold (posedge I0, negedge CE0, 0:0:0, 0:0:0, notifier,,, I0_delay, CE0_delay);
$setuphold (posedge I0, negedge S0, 0:0:0, 0:0:0, notifier,,, I0_delay, S0_delay);
$setuphold (posedge I0, posedge CE0, 0:0:0, 0:0:0, notifier,,, I0_delay, CE0_delay);
$setuphold (posedge I0, posedge S0, 0:0:0, 0:0:0, notifier,,, I0_delay, S0_delay);
$setuphold (posedge I1, negedge CE1, 0:0:0, 0:0:0, notifier,,, I1_delay, CE1_delay);
$setuphold (posedge I1, negedge S1, 0:0:0, 0:0:0, notifier,,, I1_delay, S1_delay);
$setuphold (posedge I1, posedge CE1, 0:0:0, 0:0:0, notifier,,, I1_delay, CE1_delay);
$setuphold (posedge I1, posedge S1, 0:0:0, 0:0:0, notifier,,, I1_delay, S1_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_rfifo.v (Modified from uart_fifo.v) ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver FIFO ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_rfifo.v.rca $
//
// Revision: 1.1.1.1 Tue Jun 7 09:39:01 2011 copew1
// first stab at merging s0903a branch.
//
// Revision: 1.1 Fri Jun 3 12:44:13 2011 tractp1
// UART in test bench to send/receive ASCII bytes with FPGA UART and
// command processing task in firmware
// Revision 1.3 2003/06/11 16:37:47 gorban
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
//
// Revision 1.2 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15 2001/12/18 09:01:07 mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/24 08:48:10 mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:48 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_rfifo (clk,
wb_rst_i, data_in, data_out,
// Control signals
push, // push strobe, active high
pop, // pop strobe, active high
// status signals
overrun,
count,
error_bit,
fifo_reset,
reset_status
);
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
output error_bit;
wire [fifo_width-1:0] data_out;
wire [7:0] data8_out;
// flags FIFO
reg [2:0] fifo[fifo_depth-1:0];
// FIFO pointers
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
raminfr #(fifo_pointer_w,8,fifo_depth) rfifo
(.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in[fifo_width-1:fifo_width-8]),
.dpo(data8_out)
);
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
begin
top <= #1 0;
bottom <= #1 1'b0;
count <= #1 0;
fifo[0] <= #1 0;
fifo[1] <= #1 0;
fifo[2] <= #1 0;
fifo[3] <= #1 0;
fifo[4] <= #1 0;
fifo[5] <= #1 0;
fifo[6] <= #1 0;
fifo[7] <= #1 0;
fifo[8] <= #1 0;
fifo[9] <= #1 0;
fifo[10] <= #1 0;
fifo[11] <= #1 0;
fifo[12] <= #1 0;
fifo[13] <= #1 0;
fifo[14] <= #1 0;
fifo[15] <= #1 0;
end
else
if (fifo_reset) begin
top <= #1 0;
bottom <= #1 1'b0;
count <= #1 0;
fifo[0] <= #1 0;
fifo[1] <= #1 0;
fifo[2] <= #1 0;
fifo[3] <= #1 0;
fifo[4] <= #1 0;
fifo[5] <= #1 0;
fifo[6] <= #1 0;
fifo[7] <= #1 0;
fifo[8] <= #1 0;
fifo[9] <= #1 0;
fifo[10] <= #1 0;
fifo[11] <= #1 0;
fifo[12] <= #1 0;
fifo[13] <= #1 0;
fifo[14] <= #1 0;
fifo[15] <= #1 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= #1 top_plus_1;
fifo[top] <= #1 data_in[2:0];
count <= #1 count + 1'b1;
end
2'b01 : if(count>0)
begin
fifo[bottom] <= #1 0;
bottom <= #1 bottom + 1'b1;
count <= #1 count - 1'b1;
end
2'b11 : begin
bottom <= #1 bottom + 1'b1;
top <= #1 top_plus_1;
fifo[top] <= #1 data_in[2:0];
end
default: ;
endcase
end
end // always
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
overrun <= #1 1'b0;
else
if(fifo_reset | reset_status)
overrun <= #1 1'b0;
else
if(push & ~pop & (count==fifo_depth))
overrun <= #1 1'b1;
end // always
// please note though that data_out is only valid one clock after pop signal
assign data_out = {data8_out,fifo[bottom]};
// Additional logic for detection of error conditions (parity and framing) inside the FIFO
// for the Line Status Register bit 7
wire [2:0] word0 = fifo[0];
wire [2:0] word1 = fifo[1];
wire [2:0] word2 = fifo[2];
wire [2:0] word3 = fifo[3];
wire [2:0] word4 = fifo[4];
wire [2:0] word5 = fifo[5];
wire [2:0] word6 = fifo[6];
wire [2:0] word7 = fifo[7];
wire [2:0] word8 = fifo[8];
wire [2:0] word9 = fifo[9];
wire [2:0] word10 = fifo[10];
wire [2:0] word11 = fifo[11];
wire [2:0] word12 = fifo[12];
wire [2:0] word13 = fifo[13];
wire [2:0] word14 = fifo[14];
wire [2:0] word15 = fifo[15];
// a 1 is returned if any of the error bits in the fifo is 1
assign error_bit = |(word0[2:0] | word1[2:0] | word2[2:0] | word3[2:0] |
word4[2:0] | word5[2:0] | word6[2:0] | word7[2:0] |
word8[2:0] | word9[2:0] | word10[2:0] | word11[2:0] |
word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] );
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Two-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common two-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// two-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Double-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage 2-port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - fix Avant! ////
//// - xilinx rams need external tri-state logic ////
//// - add additional RAMs (VS etc) ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2004/06/08 18:15:48 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.3 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.2 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.7 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_tpram_32x32(
// Generic synchronous two-port RAM interface
clk_a, rst_a, ce_a, we_a, oe_a, addr_a, di_a, do_a,
clk_b, rst_b, ce_b, we_b, oe_b, addr_b, di_b, do_b
);
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 32;
//
// Generic synchronous two-port RAM interface
//
input clk_a; // Clock
input rst_a; // Reset
input ce_a; // Chip enable input
input we_a; // Write enable input
input oe_a; // Output enable input
input [aw-1:0] addr_a; // address bus inputs
input [dw-1:0] di_a; // input data bus
output [dw-1:0] do_a; // output data bus
input clk_b; // Clock
input rst_b; // Reset
input ce_b; // Chip enable input
input we_b; // Write enable input
input oe_b; // Output enable input
input [aw-1:0] addr_b; // address bus inputs
input [dw-1:0] di_b; // input data bus
output [dw-1:0] do_b; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_ARTISAN_SDP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Double-Port RAM (ra2sh)
//
`ifdef UNUSED
art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(
`else
art_hsdp_32x32 artisan_sdp(
`endif
.qa(do_a),
.clka(clk_a),
.cena(~ce_a),
.wena(~we_a),
.aa(addr_a),
.da(di_a),
.oena(~oe_a),
.qb(do_b),
.clkb(clk_b),
.cenb(~ce_b),
.wenb(~we_b),
.ab(addr_b),
.db(di_b),
.oenb(~oe_b)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_STP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 2-port R/W RAM
//
virage_stp virage_stp(
.QA(do_a),
.QB(do_b),
.ADRA(addr_a),
.DA(di_a),
.WEA(we_a),
.OEA(oe_a),
.MEA(ce_a),
.CLKA(clk_a),
.ADRB(adr_b),
.DB(di_b),
.WEB(we_b),
.OEB(oe_b),
.MEB(ce_b),
.CLKB(clk_b)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16_S16 ramb4_s16_s16_0(
.CLKA(clk_a),
.RSTA(rst_a),
.ADDRA(addr_a),
.DIA(di_a[15:0]),
.ENA(ce_a),
.WEA(we_a),
.DOA(do_a[15:0]),
.CLKB(clk_b),
.RSTB(rst_b),
.ADDRB(addr_b),
.DIB(di_b[15:0]),
.ENB(ce_b),
.WEB(we_b),
.DOB(do_b[15:0])
);
//
// Block 1
//
RAMB4_S16_S16 ramb4_s16_s16_1(
.CLKA(clk_a),
.RSTA(rst_a),
.ADDRA(addr_a),
.DIA(di_a[31:16]),
.ENA(ce_a),
.WEA(we_a),
.DOA(do_a[31:16]),
.CLKB(clk_b),
.RSTB(rst_b),
.ADDRB(addr_b),
.DIB(di_b[31:16]),
.ENB(ce_b),
.WEB(we_b),
.DOB(do_b[31:16])
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S36_S36 ramb16_s36_s36(
.CLKA(clk_a),
.SSRA(rst_a),
.ADDRA({4'b0000,addr_a}),
.DIA(di_a),
.DIPA(4'h0),
.ENA(ce_a),
.WEA(we_a),
.DOA(do_a),
.DOPA(),
.CLKB(clk_b),
.SSRB(rst_b),
.ADDRB({4'b0000,addr_b}),
.DIB(di_b),
.DIPB(4'h0),
.ENB(ce_b),
.WEB(we_b),
.DOB(do_b),
.DOPB()
);
`else
`ifdef OR1200_ALTERA_LPM_XXX
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
altqpram altqpram_component (
.wraddress_a (addr_a),
.inclocken_a (ce_a),
.wraddress_b (addr_b),
.wren_a (we_a),
.inclocken_b (ce_b),
.wren_b (we_b),
.inaclr_a (rst_a),
.inaclr_b (rst_b),
.inclock_a (clk_a),
.inclock_b (clk_b),
.data_a (di_a),
.data_b (di_b),
.q_a (do_a),
.q_b (do_b)
);
defparam altqpram_component.operation_mode = "BIDIR_DUAL_PORT",
altqpram_component.width_write_a = dw,
altqpram_component.widthad_write_a = aw,
altqpram_component.numwords_write_a = dw,
altqpram_component.width_read_a = dw,
altqpram_component.widthad_read_a = aw,
altqpram_component.numwords_read_a = dw,
altqpram_component.width_write_b = dw,
altqpram_component.widthad_write_b = aw,
altqpram_component.numwords_write_b = dw,
altqpram_component.width_read_b = dw,
altqpram_component.widthad_read_b = aw,
altqpram_component.numwords_read_b = dw,
altqpram_component.indata_reg_a = "INCLOCK_A",
altqpram_component.wrcontrol_wraddress_reg_a = "INCLOCK_A",
altqpram_component.outdata_reg_a = "INCLOCK_A",
altqpram_component.indata_reg_b = "INCLOCK_B",
altqpram_component.wrcontrol_wraddress_reg_b = "INCLOCK_B",
altqpram_component.outdata_reg_b = "INCLOCK_B",
altqpram_component.indata_aclr_a = "INACLR_A",
altqpram_component.wraddress_aclr_a = "INACLR_A",
altqpram_component.wrcontrol_aclr_a = "INACLR_A",
altqpram_component.outdata_aclr_a = "INACLR_A",
altqpram_component.indata_aclr_b = "NONE",
altqpram_component.wraddress_aclr_b = "NONE",
altqpram_component.wrcontrol_aclr_b = "NONE",
altqpram_component.outdata_aclr_b = "INACLR_B",
altqpram_component.lpm_hint = "USE_ESB=ON";
//examplar attribute altqpram_component NOOPT TRUE
`else
//
// Generic two-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_a_reg; // RAM read address register
reg [aw-1:0] addr_b_reg; // RAM read address register
//
// Data output drivers
//
assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};
assign do_b = (oe_b) ? mem[addr_b_reg] : {dw{1'b0}};
//
// RAM write
//
always @(posedge clk_a)
if (ce_a && we_a)
mem[addr_a] <= #1 di_a;
//
// RAM write
//
always @(posedge clk_b)
if (ce_b && we_b)
mem[addr_b] <= #1 di_b;
//
// RAM read address register
//
always @(posedge clk_a or posedge rst_a)
if (rst_a)
addr_a_reg <= #1 {aw{1'b0}};
else if (ce_a)
addr_a_reg <= #1 addr_a;
//
// RAM read address register
//
always @(posedge clk_b or posedge rst_b)
if (rst_b)
addr_b_reg <= #1 {aw{1'b0}};
else if (ce_b)
addr_b_reg <= #1 addr_b;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRAGE_STP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SDP
endmodule
|
// Local Variables:
// verilog-library-directories:("." "../../../" "../../src")
// End:
module gpu_interface_tb (/*AUTOARG*/) ;
localparam WG_ID_WIDTH = 15;
localparam NUMBER_WG_ID = 2**WG_ID_WIDTH;
localparam WF_COUNT_WIDTH = 4;
localparam MAX_WF_PER_WG = 2**WF_COUNT_WIDTH;
localparam WG_SLOT_ID_WIDTH = 6;
localparam NUMBER_WF_SLOTS = 40;
localparam CU_ID_WIDTH = 3;
localparam NUMBER_CU = 8;
localparam VGPR_ID_WIDTH = 8;
localparam NUMBER_VGPR_SLOTS = 2**VGPR_ID_WIDTH;
localparam SGPR_ID_WIDTH = 8;
localparam NUMBER_SGPR_SLOTS = 2**SGPR_ID_WIDTH;
localparam LDS_ID_WIDTH = 8;
localparam NUMBER_LDS_SLOTS = 2**LDS_ID_WIDTH;
localparam GDS_ID_WIDTH = 8;
localparam NUMBER_GDS_SLOTS = 2**GDS_ID_WIDTH;
localparam MEM_ADDR_WIDTH = 32;
localparam WAVE_ITEM_WIDTH = 6;
localparam NUMBER_ITENS_WF = 64;
localparam TAG_WIDTH = 15;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [NUMBER_CU-1:0] cu2dispatch_wf_done; // From cus of cu_simulator.v
wire [NUMBER_CU*TAG_WIDTH-1:0] cu2dispatch_wf_tag_done;// From cus of cu_simulator.v
wire [15:0] dispatch2cu_lds_base_dispatch;// From DUT of gpu_interface.v
wire [8:0] dispatch2cu_sgpr_base_dispatch;// From DUT of gpu_interface.v
wire [MEM_ADDR_WIDTH-1:0] dispatch2cu_start_pc_dispatch;// From DUT of gpu_interface.v
wire [9:0] dispatch2cu_vgpr_base_dispatch;// From DUT of gpu_interface.v
wire [NUMBER_CU-1:0] dispatch2cu_wf_dispatch;// From DUT of gpu_interface.v
wire [WAVE_ITEM_WIDTH-1:0] dispatch2cu_wf_size_dispatch;// From DUT of gpu_interface.v
wire [TAG_WIDTH-1:0] dispatch2cu_wf_tag_dispatch;// From DUT of gpu_interface.v
wire [WF_COUNT_WIDTH-1:0] dispatch2cu_wg_wf_count;// From DUT of gpu_interface.v
wire gpu_interface_alloc_available;// From DUT of gpu_interface.v
wire [CU_ID_WIDTH-1:0] gpu_interface_cu_id; // From DUT of gpu_interface.v
wire gpu_interface_dealloc_available;// From DUT of gpu_interface.v
wire [WG_ID_WIDTH-1:0] gpu_interface_dealloc_wg_id;// From DUT of gpu_interface.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg [CU_ID_WIDTH-1:0] allocator_cu_id_out; // To DUT of gpu_interface.v
reg [GDS_ID_WIDTH-1:0] allocator_gds_start_out;// To DUT of gpu_interface.v
reg [LDS_ID_WIDTH-1:0] allocator_lds_start_out;// To DUT of gpu_interface.v
reg [SGPR_ID_WIDTH-1:0] allocator_sgpr_start_out;// To DUT of gpu_interface.v
reg [VGPR_ID_WIDTH-1:0] allocator_vgpr_start_out;// To DUT of gpu_interface.v
reg [WF_COUNT_WIDTH-1:0] allocator_wf_count; // To DUT of gpu_interface.v
reg [WG_ID_WIDTH-1:0] allocator_wg_id_out; // To DUT of gpu_interface.v
reg clk; // To DUT of gpu_interface.v, ...
reg dis_controller_wg_alloc_valid;// To DUT of gpu_interface.v
reg dis_controller_wg_dealloc_valid;// To DUT of gpu_interface.v
reg [SGPR_ID_WIDTH:0] inflight_wg_buffer_gpu_sgpr_size_per_wf;// To DUT of gpu_interface.v
reg inflight_wg_buffer_gpu_valid;// To DUT of gpu_interface.v
reg [VGPR_ID_WIDTH:0] inflight_wg_buffer_gpu_vgpr_size_per_wf;// To DUT of gpu_interface.v
reg [WAVE_ITEM_WIDTH-1:0] inflight_wg_buffer_gpu_wf_size;// To DUT of gpu_interface.v
reg [MEM_ADDR_WIDTH-1:0] inflight_wg_buffer_start_pc;// To DUT of gpu_interface.v
reg rst; // To DUT of gpu_interface.v, ...
// End of automatics
gpu_interface
#(/*AUTOINSTPARAM*/
// Parameters
.WG_ID_WIDTH (WG_ID_WIDTH),
.WF_COUNT_WIDTH (WF_COUNT_WIDTH),
.WG_SLOT_ID_WIDTH (WG_SLOT_ID_WIDTH),
.NUMBER_WF_SLOTS (NUMBER_WF_SLOTS),
.NUMBER_CU (NUMBER_CU),
.CU_ID_WIDTH (CU_ID_WIDTH),
.VGPR_ID_WIDTH (VGPR_ID_WIDTH),
.SGPR_ID_WIDTH (SGPR_ID_WIDTH),
.LDS_ID_WIDTH (LDS_ID_WIDTH),
.GDS_ID_WIDTH (GDS_ID_WIDTH),
.TAG_WIDTH (TAG_WIDTH),
.MEM_ADDR_WIDTH (MEM_ADDR_WIDTH),
.WAVE_ITEM_WIDTH (WAVE_ITEM_WIDTH))
DUT
(/*AUTOINST*/
// Outputs
.gpu_interface_alloc_available (gpu_interface_alloc_available),
.gpu_interface_dealloc_available (gpu_interface_dealloc_available),
.gpu_interface_cu_id (gpu_interface_cu_id[CU_ID_WIDTH-1:0]),
.gpu_interface_dealloc_wg_id (gpu_interface_dealloc_wg_id[WG_ID_WIDTH-1:0]),
.dispatch2cu_wf_dispatch (dispatch2cu_wf_dispatch[NUMBER_CU-1:0]),
.dispatch2cu_wg_wf_count (dispatch2cu_wg_wf_count[WF_COUNT_WIDTH-1:0]),
.dispatch2cu_wf_size_dispatch (dispatch2cu_wf_size_dispatch[WAVE_ITEM_WIDTH-1:0]),
.dispatch2cu_sgpr_base_dispatch (dispatch2cu_sgpr_base_dispatch[8:0]),
.dispatch2cu_vgpr_base_dispatch (dispatch2cu_vgpr_base_dispatch[9:0]),
.dispatch2cu_wf_tag_dispatch (dispatch2cu_wf_tag_dispatch[TAG_WIDTH-1:0]),
.dispatch2cu_lds_base_dispatch (dispatch2cu_lds_base_dispatch[15:0]),
.dispatch2cu_start_pc_dispatch (dispatch2cu_start_pc_dispatch[MEM_ADDR_WIDTH-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.inflight_wg_buffer_gpu_valid (inflight_wg_buffer_gpu_valid),
.inflight_wg_buffer_gpu_wf_size (inflight_wg_buffer_gpu_wf_size[WAVE_ITEM_WIDTH-1:0]),
.inflight_wg_buffer_start_pc (inflight_wg_buffer_start_pc[MEM_ADDR_WIDTH-1:0]),
.inflight_wg_buffer_gpu_vgpr_size_per_wf(inflight_wg_buffer_gpu_vgpr_size_per_wf[VGPR_ID_WIDTH:0]),
.inflight_wg_buffer_gpu_sgpr_size_per_wf(inflight_wg_buffer_gpu_sgpr_size_per_wf[SGPR_ID_WIDTH:0]),
.allocator_wg_id_out (allocator_wg_id_out[WG_ID_WIDTH-1:0]),
.allocator_cu_id_out (allocator_cu_id_out[CU_ID_WIDTH-1:0]),
.allocator_wf_count (allocator_wf_count[WF_COUNT_WIDTH-1:0]),
.allocator_vgpr_start_out (allocator_vgpr_start_out[VGPR_ID_WIDTH-1:0]),
.allocator_sgpr_start_out (allocator_sgpr_start_out[SGPR_ID_WIDTH-1:0]),
.allocator_lds_start_out (allocator_lds_start_out[LDS_ID_WIDTH-1:0]),
.allocator_gds_start_out (allocator_gds_start_out[GDS_ID_WIDTH-1:0]),
.dis_controller_wg_alloc_valid (dis_controller_wg_alloc_valid),
.dis_controller_wg_dealloc_valid (dis_controller_wg_dealloc_valid),
.cu2dispatch_wf_done (cu2dispatch_wf_done[NUMBER_CU-1:0]),
.cu2dispatch_wf_tag_done (cu2dispatch_wf_tag_done[NUMBER_CU*TAG_WIDTH-1:0]));
// Clk block
initial begin
clk = 1'b0;
forever begin
#5 clk = ! clk;
end
end
// rst block
initial begin
// Reset the design
rst = 1'b1;
@(posedge clk);
@(posedge clk);
@(posedge clk);
rst = 1'b0;
end
// allocated wg info - wg_id, sizes, starts, wf_count, pc_start
localparam NUM_WG_DISPATCHED = 10;
// running wf
localparam MAX_WF = 200;
integer wf_to_be_dispatched;
wire all_wf_dispatched;
assign all_wf_dispatched = (wf_to_be_dispatched==0);
// dispatched wf info - tag only
task dealloc_wg;
begin
while(!gpu_interface_alloc_available) @(posedge clk);
dis_controller_wg_dealloc_valid = 1'b1;
@(posedge clk);
dis_controller_wg_dealloc_valid = 1'b0;
@(posedge clk);
@(posedge clk);
end
endtask // repeat
// dispatcher controller
task alloc_wg;
input [CU_ID_WIDTH-1 :0] cu_id;
input [WG_ID_WIDTH-1:0] wg_id;
input [WF_COUNT_WIDTH-1:0] wf_count;
input [VGPR_ID_WIDTH-1 :0] vgpr_start;
input [VGPR_ID_WIDTH :0] vgpr_size_per_wf;
input [SGPR_ID_WIDTH-1 :0] sgpr_start;
input [SGPR_ID_WIDTH :0] sgpr_size_per_wf;
input [LDS_ID_WIDTH-1 :0] lds_start;
input [GDS_ID_WIDTH-1 :0] gds_start;
input [WAVE_ITEM_WIDTH-1:0] wf_size;
input [MEM_ADDR_WIDTH-1:0] start_pc;
begin
while(!gpu_interface_alloc_available) @(posedge clk);
dis_controller_wg_alloc_valid = 1'b1;
allocator_wg_id_out = wg_id;
allocator_cu_id_out = cu_id;
allocator_vgpr_start_out = vgpr_start;
allocator_sgpr_start_out = sgpr_start;
allocator_lds_start_out = lds_start;
allocator_gds_start_out = gds_start;
allocator_wf_count = wf_count;
@(posedge clk);
dis_controller_wg_alloc_valid = 1'b0;
repeat(2) @(posedge clk);
inflight_wg_buffer_gpu_valid = 1'b1;
inflight_wg_buffer_gpu_vgpr_size_per_wf = vgpr_size_per_wf;
inflight_wg_buffer_gpu_sgpr_size_per_wf = sgpr_size_per_wf;
inflight_wg_buffer_gpu_wf_size = wf_size;
inflight_wg_buffer_start_pc = start_pc;
@(posedge clk);
inflight_wg_buffer_gpu_valid = 1'b0;
end
endtask //
initial begin : ALLOCATION_BLOCK
integer random_delay;
integer i;
reg [WF_COUNT_WIDTH-1:0] alloc_wf_count;
reg [VGPR_ID_WIDTH-1 :0] alloc_vgpr_start;
reg [VGPR_ID_WIDTH :0] alloc_vgpr_size_per_wf;
reg [SGPR_ID_WIDTH-1 :0] alloc_sgpr_start;
reg [SGPR_ID_WIDTH :0] alloc_sgpr_size_per_wf;
dis_controller_wg_alloc_valid = 1'b0;
inflight_wg_buffer_gpu_valid = 1'b0;
dis_controller_wg_dealloc_valid = 1'b0;
wf_to_be_dispatched = NUM_WG_DISPATCHED;
@(posedge clk);
@(negedge rst);
@(posedge clk);
for (i = 0; i < NUM_WG_DISPATCHED; i = i+1) begin
repeat({$random}%20) @(posedge clk);
if(gpu_interface_dealloc_available) begin
dealloc_wg;
end
alloc_wf_count = ({$random}%(MAX_WF_PER_WG-1))+1;
alloc_vgpr_size_per_wf = {$random}%(NUMBER_VGPR_SLOTS/alloc_wf_count);
alloc_vgpr_start = {$random}%(NUMBER_VGPR_SLOTS-(alloc_vgpr_size_per_wf*
alloc_wf_count));
alloc_sgpr_size_per_wf = {$random}%(NUMBER_SGPR_SLOTS/alloc_wf_count);
alloc_sgpr_start = {$random}%(NUMBER_SGPR_SLOTS-(alloc_sgpr_size_per_wf*
alloc_wf_count));
alloc_wg({$random}%NUMBER_CU,
{$random}%NUMBER_WG_ID,
alloc_wf_count,
alloc_vgpr_start,
alloc_vgpr_size_per_wf,
alloc_sgpr_start,
alloc_sgpr_size_per_wf,
{$random}%NUMBER_LDS_SLOTS,
{$random}%NUMBER_GDS_SLOTS,
{$random}%(NUMBER_ITENS_WF-1)+1,
{$random});
wf_to_be_dispatched = wf_to_be_dispatched - 1;
end // for (i = 0; i < NUM_WG_DISPATCHED; i = i+1)
// Dealloc other wg
forever begin
if(gpu_interface_dealloc_available) begin
dealloc_wg;
end
else begin
@(posedge clk);
end
end
end // block: ALLOCATION_BLOCK
cu_simulator
#(/*AUTOINSTPARAM*/
// Parameters
.CU_ID_WIDTH (CU_ID_WIDTH),
.NUMBER_CU (NUMBER_CU),
.TAG_WIDTH (TAG_WIDTH),
.WAVE_ITEM_WIDTH (WAVE_ITEM_WIDTH),
.WF_COUNT_WIDTH (WF_COUNT_WIDTH),
.MEM_ADDR_WIDTH (MEM_ADDR_WIDTH),
.MAX_WF (MAX_WF))
cus
(/*AUTOINST*/
// Outputs
.cu2dispatch_wf_done (cu2dispatch_wf_done[NUMBER_CU-1:0]),
.cu2dispatch_wf_tag_done (cu2dispatch_wf_tag_done[NUMBER_CU*TAG_WIDTH-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.all_wf_dispatched (all_wf_dispatched),
.dispatch2cu_wf_dispatch (dispatch2cu_wf_dispatch[NUMBER_CU-1:0]),
.dispatch2cu_lds_base_dispatch (dispatch2cu_lds_base_dispatch[15:0]),
.dispatch2cu_sgpr_base_dispatch (dispatch2cu_sgpr_base_dispatch[8:0]),
.dispatch2cu_start_pc_dispatch (dispatch2cu_start_pc_dispatch[MEM_ADDR_WIDTH-1:0]),
.dispatch2cu_vgpr_base_dispatch (dispatch2cu_vgpr_base_dispatch[9:0]),
.dispatch2cu_wf_size_dispatch (dispatch2cu_wf_size_dispatch[WAVE_ITEM_WIDTH-1:0]),
.dispatch2cu_wf_tag_dispatch (dispatch2cu_wf_tag_dispatch[TAG_WIDTH-1:0]),
.dispatch2cu_wg_wf_count (dispatch2cu_wg_wf_count[WF_COUNT_WIDTH-1:0]));
dispatcher_checker
#(/*AUTOINSTPARAM*/
// Parameters
.WG_ID_WIDTH (WG_ID_WIDTH),
.NUMBER_WG_ID (NUMBER_WG_ID),
.WF_COUNT_WIDTH (WF_COUNT_WIDTH),
.MAX_WF_PER_WG (MAX_WF_PER_WG),
.WG_SLOT_ID_WIDTH (WG_SLOT_ID_WIDTH),
.NUMBER_WF_SLOTS (NUMBER_WF_SLOTS),
.CU_ID_WIDTH (CU_ID_WIDTH),
.NUMBER_CU (NUMBER_CU),
.VGPR_ID_WIDTH (VGPR_ID_WIDTH),
.NUMBER_VGPR_SLOTS (NUMBER_VGPR_SLOTS),
.SGPR_ID_WIDTH (SGPR_ID_WIDTH),
.NUMBER_SGPR_SLOTS (NUMBER_SGPR_SLOTS),
.LDS_ID_WIDTH (LDS_ID_WIDTH),
.NUMBER_LDS_SLOTS (NUMBER_LDS_SLOTS),
.GDS_ID_WIDTH (GDS_ID_WIDTH),
.NUMBER_GDS_SLOTS (NUMBER_GDS_SLOTS),
.MEM_ADDR_WIDTH (MEM_ADDR_WIDTH),
.WAVE_ITEM_WIDTH (WAVE_ITEM_WIDTH),
.NUMBER_ITENS_WF (NUMBER_ITENS_WF),
.TAG_WIDTH (TAG_WIDTH),
.MAX_WF (MAX_WF))
dis_checker
(
// Inputs
.clk (clk),
.rst (rst),
.dispatch2cu_wf_dispatch (dispatch2cu_wf_dispatch[NUMBER_CU-1:0]),
.dispatch2cu_lds_base_dispatch (dispatch2cu_lds_base_dispatch[15:0]),
.dispatch2cu_sgpr_base_dispatch (dispatch2cu_sgpr_base_dispatch[8:0]),
.dispatch2cu_start_pc_dispatch (dispatch2cu_start_pc_dispatch[MEM_ADDR_WIDTH-1:0]),
.dispatch2cu_vgpr_base_dispatch (dispatch2cu_vgpr_base_dispatch[9:0]),
.dispatch2cu_wf_size_dispatch (dispatch2cu_wf_size_dispatch[WAVE_ITEM_WIDTH-1:0]),
.dispatch2cu_wf_tag_dispatch (dispatch2cu_wf_tag_dispatch[TAG_WIDTH-1:0]),
.dispatch2cu_wg_wf_count (dispatch2cu_wg_wf_count[WF_COUNT_WIDTH-1:0]),
.alloc_valid (dis_controller_wg_alloc_valid),
.inflight_buffer_valid (inflight_wg_buffer_gpu_valid),
.cu_id (allocator_cu_id_out),
.wg_id (allocator_wg_id_out),
.wf_count (allocator_wf_count),
.vgpr_start (allocator_vgpr_start_out),
.vgpr_size_per_wf (inflight_wg_buffer_gpu_vgpr_size_per_wf),
.sgpr_start (allocator_sgpr_start_out),
.sgpr_size_per_wf (inflight_wg_buffer_gpu_sgpr_size_per_wf),
.lds_start (allocator_lds_start_out),
.gds_start (allocator_gds_start_out),
.wf_size (inflight_wg_buffer_gpu_wf_size),
.start_pc (inflight_wg_buffer_start_pc));
endmodule // gpu_interface_tb
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [2:0] in = (crc[1:0]==0 ? 3'd0
: crc[1:0]==0 ? 3'd1
: crc[1:0]==0 ? 3'd2 : 3'd4);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[2:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h704ca23e2a83e1c5
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
// Replace this module with the device under test.
//
// Change the code in the t module to apply values to the inputs and
// merge the output values into the result vector.
input clk;
input [2:0] in;
output reg [31:0] out;
localparam ST_0 = 0;
localparam ST_1 = 1;
localparam ST_2 = 2;
always @(posedge clk) begin
case (1'b1) // synopsys parallel_case
in[ST_0]: out <= 32'h1234;
in[ST_1]: out <= 32'h4356;
in[ST_2]: out <= 32'h9874;
default: out <= 32'h1;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__INV_TB_V
`define SKY130_FD_SC_HVL__INV_TB_V
/**
* inv: Inverter.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__inv.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hvl__inv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__INV_TB_V
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module strobe_gen
( input clock,
input reset,
input enable,
input [7:0] rate, // Rate should be 1 LESS THAN your desired divide ratio
input strobe_in,
output wire strobe );
// parameter width = 8;
reg [7:0] counter;
assign strobe = ~|counter && enable && strobe_in;
always @(posedge clock)
if(reset | ~enable)
counter <= #1 8'd0;
else if(strobe_in)
if(counter == 0)
counter <= #1 rate;
else
counter <= #1 counter - 8'd1;
endmodule // strobe_gen
|
`default_nettype none
module CPU(clk,rst,start,
ReadData,MemAck,WriteData,MemAddr,MemEnable,MemWrite);
input clk,rst,start,MemAck;
input [255:0] ReadData;
output MemEnable,MemWrite;
output [255:0] WriteData;
output [31:0] MemAddr;
wire [31:0] InstrAddr,NextPC,NextPC_IF,Instr;
Adder Add_PC(
.data0 (InstrAddr),
.data1 (4),
.res (NextPC_IF)
);
wire MemStall;
PC PC(
.clk (clk),
.rst (rst),
.start (start),
.pc_i (NextPC),
.pc_o (InstrAddr),
.Stall (Stall|MemStall),
.Enable (1)
);
wire [31:0] BranchNextPC;
wire [27:0] Jaddr;
MUX32 mux1(NextPC_IF,Baddr,Branch&eq,BranchNextPC);
ShiftLeftTwo26 ShlJ(Instr_ID[25:0],Jaddr);
MUX32 mux2(BranchNextPC,{NextPC_IF[31:28],Jaddr},Jump,NextPC);//acceptable
Instruction_Memory InstrMem(
.addr (InstrAddr),
.instr (Instr)
);
wire Stall, MUXSel;
Hazard_Detection_unit HD(Instr_ID, Control_EX[8:8], Instr_EX[20:16], Stall, MUXSel);
wire [31:0] Instr_ID,NextPC_ID;
Pipeline_Registers IF_ID(
.clk (clk),
.Flush (Jump||(Branch&eq)),
.Stall (Stall|MemStall),
.Control_i (),
.Control (),
.Instr_i (Instr),
.Instr (Instr_ID),
.data0_i (),
.data0 (),
.data1_i (),
.data1 (),
.data2_i (NextPC_IF),
.data2 (NextPC_ID),
.RegAddr_i (),
.RegAddr ()
);
wire RegWrite,RegDst,ALUSrc,Branch,Jump,MemWrite_ID,MemRead,MemtoReg;
wire [1:0] ALUOp;
wire [31:0] RSdata,RTdata,RDdata,ALURes_WB,Control_WB,Imm;
wire [4:0] RegAddr_WB;
Control Control(
.Op (Instr_ID[31:26]),
.RegWrite (RegWrite),
.RegDst (RegDst),
.ALUSrc (ALUSrc),
.ALUOp (ALUOp),
.Branch (Branch),
.Jump (Jump),
.MemWrite (MemWrite_ID),
.MemRead (MemRead),
.MemtoReg (MemtoReg)
);
Registers Registers(
.clk (clk),
.RegWrite (Control_WB[0:0]),
.RSaddr (Instr_ID[25:21]),
.RTaddr (Instr_ID[20:16]),
.RDaddr (RegAddr_WB),
.RSdata (RSdata),
.RTdata (RTdata),
.RDdata (RDdata)
);
wire eq;
Comparator cmp(
.data0(RSdata),
.data1(RTdata),
.res(eq)
);
wire [31:0] Offset,Baddr;
Signed_Extend Sign_extend(Instr_ID[15:0],Imm);
ShiftLeftTwo32 ShlB(Imm,Offset);
Adder ADD(NextPC_ID,Offset,Baddr);
wire [31:0] Control_ID;
MUX32 mux8({22'b0,MemtoReg,MemRead,MemWrite_ID,Jump,Branch,ALUOp,ALUSrc,RegDst,RegWrite},0,MUXSel,Control_ID);
wire [31:0] Instr_EX,Control_EX,RSdata_EX,RTdata_EX,Imm_EX;
Pipeline_Registers ID_EX(
.clk (clk),
.Flush (0),
.Stall (MemStall),
.Control_i (Control_ID),
.Control (Control_EX),
.Instr_i (Instr_ID),
.Instr (Instr_EX),
.data0_i (RSdata),
.data0 (RSdata_EX),
.data1_i (RTdata),
.data1 (RTdata_EX),
.data2_i (Imm),
.data2 (Imm_EX),
.RegAddr_i (),
.RegAddr ()
);
wire [2:0] ALUCtrl;
wire [31:0] ALUdata0,ALUdata1,ALURes,RTdata_FW;
ALU ALU(
.data0 (ALUdata0),
.data1 (ALUdata1),
.ALUCtrl (ALUCtrl),
.res (ALURes)
);
ALU_Control ALU_Control(
.func (Instr_EX[5:0]),
.ALUOp (Control_EX[4:3]),
.ALUCtrl (ALUCtrl)
);
wire [4:0] RegAddr;
wire [1:0] Ci_m6, Ci_m7;
Forwarding_unit FW(
.data0_i (Instr_EX[25:21]),
.data1_i (Instr_EX[20:16]),
.data2_i (RegAddr_MEM),
.data3_i (Control_MEM[0:0]),
.data4_i (RegAddr_WB),
.data5_i (Control_WB[0:0]),
.data0_o (Ci_m6),
.data1_o (Ci_m7)
);
TriMUX mux6(RSdata_EX,RDdata,ALURes_MEM,Ci_m6,ALUdata0);
TriMUX mux7(RTdata_EX,RDdata,ALURes_MEM,Ci_m7,RTdata_FW);
MUX5 mux3(Instr_EX[15:11],Instr_EX[20:16],Control_EX[1:1],RegAddr);
MUX32 mux4(RTdata_FW,Imm_EX,Control_EX[2:2],ALUdata1);
wire [31:0] Control_MEM,ALURes_MEM,RTdata_MEM;
wire [4:0] RegAddr_MEM;
Pipeline_Registers EX_MEM(
.clk (clk),
.Flush (0),
.Stall (MemStall),
.Control_i (Control_EX),
.Control (Control_MEM),
.Instr_i (),
.Instr (),
.data0_i (ALURes),
.data0 (ALURes_MEM),
.data1_i (RTdata_FW),
.data1 (RTdata_MEM),
.data2_i (),
.data2 (),
.RegAddr_i (RegAddr),
.RegAddr (RegAddr_MEM)
);
wire [31:0] MemData,MemData_WB;
dcache_top dcache
(
.clk_i(clk),
.rst_i(rst),
.mem_data_i(ReadData),
.mem_ack_i(MemAck),
.mem_data_o(WriteData),
.mem_addr_o(MemAddr),
.mem_enable_o(MemEnable),
.mem_write_o(MemWrite),
.p1_data_i(RTdata_MEM),
.p1_addr_i(ALURes_MEM),
.p1_MemRead_i(Control_MEM[8]),
.p1_MemWrite_i(Control_MEM[7]),
.p1_data_o(MemData),
.p1_stall_o(MemStall)
);
Pipeline_Registers MEM_WB(
.clk (clk),
.Flush (0),
.Stall (MemStall),
.Control_i (Control_MEM),
.Control (Control_WB),
.Instr_i (),
.Instr (),
.data0_i (ALURes_MEM),
.data0 (ALURes_WB),
.data1_i (MemData),
.data1 (MemData_WB),
.data2_i (),
.data2 (),
.RegAddr_i (RegAddr_MEM),
.RegAddr (RegAddr_WB)
);
MUX32 mux5(ALURes_WB,MemData_WB,Control_WB[9:9],RDdata);
integer i;
parameter nop=32'b00000000000000000000000000100000; // add r0,r0,r0
initial begin
for(i=0;i<32;i=i+1)
Registers.register[i]=0;
//CPU.Registers.register[1]=1;
Control.Jump=0;
Control.Branch=0;
cmp.res=0;
HD.stall=0;
HD.MUXsel=0;
IF_ID.Instr=nop;
ID_EX.Instr=nop;
ID_EX.Control=0;
EX_MEM.Control=0;
MEM_WB.Control=0;
end
endmodule
|
/*
*
* Copyright (c) 2011-2013 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
/*
* When tx_ready is high, uart_transmitter is ready to send a new byte. Drive
* rx_new_byte high for one cycle, and the byte to transmit on rx_byte for one
* cycle.
*/
module uart_receiver # (
parameter comm_clk_frequency = 100000000,
parameter baud_rate = 115200
) (
input clk,
// UART interface
input uart_rx,
// Data received
output reg tx_new_byte = 1'b0,
output reg [7:0] tx_byte = 8'd0
);
localparam [15:0] baud_delay = (comm_clk_frequency / baud_rate) - 1;
//-----------------------------------------------------------------------------
// UART Filtering
//-----------------------------------------------------------------------------
wire rx;
uart_filter uart_fitler_blk (
.clk (clk),
.uart_rx (uart_rx),
.tx_rx (rx)
);
//-----------------------------------------------------------------------------
// UART Decoding
//-----------------------------------------------------------------------------
reg old_rx = 1'b1, idle = 1'b1;
reg [15:0] delay_cnt = 16'd0;
reg [8:0] incoming = 9'd0;
always @ (posedge clk)
begin
old_rx <= rx;
tx_new_byte <= 1'b0;
delay_cnt <= delay_cnt + 16'd1;
if (delay_cnt == baud_delay)
delay_cnt <= 0;
if (idle && old_rx && !rx) // Start bit (falling edge)
begin
idle <= 1'b0;
incoming <= 9'd511;
delay_cnt <= 16'd0; // Synchronize timer to falling edge
end
else if (!idle && (delay_cnt == (baud_delay >> 1)))
begin
incoming <= {rx, incoming[8:1]}; // LSB first
if (incoming == 9'd511 && rx) // False start bit
idle <= 1'b1;
if (!incoming[0]) // Expecting stop bit
begin
idle <= 1'b1;
if (rx)
begin
tx_new_byte <= 1'b1;
tx_byte <= incoming[8:1];
end
end
end
end
endmodule
/*
* Provides metastability protection, and some minimal noise filtering.
* Noise is filtered with a 3-way majority vote. This removes any random single
* 'clk' cycle errors.
*/
module uart_filter (
input clk,
input uart_rx,
output reg tx_rx = 1'b0
);
//-----------------------------------------------------------------------------
// Metastability Protection
//-----------------------------------------------------------------------------
reg rx, meta;
always @ (posedge clk)
{rx, meta} <= {meta, uart_rx};
//-----------------------------------------------------------------------------
// Noise Filtering
//-----------------------------------------------------------------------------
wire sample0 = rx;
reg sample1, sample2;
always @ (posedge clk)
begin
{sample2, sample1} <= {sample1, sample0};
if ((sample2 & sample1) | (sample1 & sample0) | (sample2 & sample0))
tx_rx <= 1'b1;
else
tx_rx <= 1'b0;
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2018 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file upd77c25_datram.v when simulating
// the core, upd77c25_datram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module upd77c25_datram(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
input clkb;
input [0 : 0] web;
input [10 : 0] addrb;
input [7 : 0] dinb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(2048),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(2048),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: StackRAM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module StackRAM (
address,
byteena,
clock,
data,
wren,
q);
input [9:0] address;
input [1:0] byteena;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (address),
.byteena_a (byteena),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "2"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC "byteena[1..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL StackRAM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL StackRAM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL StackRAM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL StackRAM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL StackRAM_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL StackRAM_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_asinpi_s5 (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_arcsinpi_s5 inst (
.en (enable),
.areset(1'b0),
.clk(clock),
.a(dataa),
.q(sub_wire0));
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:46:09 02/22/2015
// Design Name:
// Module Name: SpecialAdd
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SpecialAdd(
input [31:0] cin_Special,
input [31:0] zin_Special,
input reset,
input clock,
output reg idle_Special = 1'b0,
output reg [7:0] difference_Special,
output reg [35:0] cout_Special,
output reg [35:0] zout_Special,
output reg [31:0] sout_Special
);
wire z_sign;
wire [7:0] z_exponent;
wire [26:0] z_mantissa;
wire c_sign;
wire [7:0] c_exponent;
wire [26:0] c_mantissa;
assign c_sign = cin_Special[31];
assign c_exponent = {cin_Special[30:23] - 127};
assign c_mantissa = {cin_Special[22:0],3'd0};
assign z_sign = {zin_Special[31]};
assign z_exponent = {zin_Special[30:23] - 127};
assign z_mantissa = {zin_Special[22:0],3'd0};
parameter no_idle = 1'b0,
put_idle = 1'b1;
always @ (posedge clock)
begin
if (reset == 1'b1) begin
idle_Special <= 1'b0;
end
else begin
if ($signed(z_exponent) > $signed(c_exponent)) begin
difference_Special <= z_exponent - c_exponent;
end
else if ($signed(z_exponent) <= $signed(c_exponent)) begin
difference_Special <= c_exponent - z_exponent;
end
// Most of the special cases will never occur except the case where one input is zero.
// The HCORDIC module will not receive NaN and inf at input stage.
//if c is NaN or z is NaN return NaN
if ((c_exponent == 128 && c_mantissa != 0) || (z_exponent == 128 && z_mantissa != 0)) begin
sout_Special[31] <= 1;
sout_Special[30:23] <= 255;
sout_Special[22] <= 1;
sout_Special[21:0] <= 0;
zout_Special <= zin_Special;
cout_Special <= cin_Special;
idle_Special <= put_idle;
//if c is inf return inf
end else if (c_exponent == 128) begin
sout_Special[31] <= c_sign;
sout_Special[30:23] <= 255;
sout_Special[22:0] <= 0;
zout_Special <= zin_Special;
cout_Special <= cin_Special;
idle_Special <= put_idle;
//if z is inf return inf
end else if (z_exponent == 128) begin
sout_Special[31] <= z_sign;
sout_Special[30:23] <= 255;
sout_Special[22:0] <= 0;
zout_Special <= zin_Special;
cout_Special <= cin_Special;
idle_Special <= put_idle;
//if c is zero return z
end else if ((($signed(c_exponent) == -127) && (c_mantissa == 0)) && (($signed(z_exponent) == -127) && (z_mantissa == 0))) begin
sout_Special[31] <= c_sign & z_sign;
sout_Special[30:23] <= z_exponent[7:0] + 127;
sout_Special[22:0] <= z_mantissa[26:3];
zout_Special <= zin_Special;
cout_Special <= cin_Special;
idle_Special <= put_idle;
//if c is zero return z
end else if (($signed(c_exponent) == -127) && (c_mantissa == 0)) begin
sout_Special[31] <= z_sign;
sout_Special[30:23] <= z_exponent[7:0] + 127;
sout_Special[22:0] <= z_mantissa[26:3];
zout_Special <= zin_Special;
cout_Special <= cin_Special;
idle_Special <= put_idle;
//if z is zero return c
end else if (($signed(z_exponent) == -127) && (z_mantissa == 0)) begin
sout_Special[31] <= c_sign;
sout_Special[30:23] <= c_exponent[7:0] + 127;
sout_Special[22:0] <= c_mantissa[26:3];
zout_Special <= zin_Special;
cout_Special <= cin_Special;
idle_Special <= put_idle;
end else begin
sout_Special <= 0;
//Denormalised Number
if ($signed(c_exponent) == -127) begin
cout_Special[34:27] <= -126;
cout_Special[35] <= c_sign;
cout_Special[26:0] <= c_mantissa;
end else begin
cout_Special[34:27] <= c_exponent + 127;
cout_Special[35] <= c_sign;
cout_Special[26] <= 1;
cout_Special[25:0] <= c_mantissa[25:0];
idle_Special <= no_idle;
end
//Denormalised Number
if ($signed(z_exponent) == -127) begin
zout_Special[35] <= z_sign;
zout_Special[34:27] <= -126;
zout_Special[26:0] <= z_mantissa;
end else begin
zout_Special[35] <= z_sign;
zout_Special[34:27] <= z_exponent + 127;
zout_Special[25:0] <= z_mantissa[25:0];
zout_Special[26] <= 1;
idle_Special <= no_idle;
end
end
end
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This module converts a singed or an unsigned long integer into a floating point number.
module acl_fp_convert_from_long(clock, resetn, dataa, result, enable, valid_in, valid_out, stall_in, stall_out);
parameter UNSIGNED = 0;
parameter HIGH_CAPACITY = 1;
parameter ROUNDING_MODE = 0;
// 0 - round to nearest even
// 1 - round to nearest with ties away from zero
// 2 - round towards zero (truncation)
// 3 - round up
// 4 - round down
input clock, resetn;
input [63:0] dataa;
output [31:0] result;
input enable, valid_in, stall_in;
output valid_out, stall_out;
reg c1_valid;
wire c1_stall;
wire c1_enable;
reg c2_valid;
wire c2_stall;
wire c2_enable;
reg c3_valid;
wire c3_stall;
wire c3_enable;
reg c4_valid;
wire c4_stall;
wire c4_enable;
reg c5_valid;
wire c5_stall;
wire c5_enable;
// Cycle 1 - convert the number to an appropriately signed value and determine the sign of the resulting number.
reg [63:0] c1_value_to_convert;
reg c1_sign;
assign c1_enable = (HIGH_CAPACITY == 1) ? (~c1_valid | ~c1_stall) : enable;
assign stall_out = c1_valid & c1_stall;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c1_valid <= 1'b0;
c1_sign <= 1'bx;
c1_value_to_convert <= 64'dx;
end
else if (c1_enable)
begin
c1_valid <= valid_in;
if (UNSIGNED == 1)
begin
c1_sign <= 1'b0;
c1_value_to_convert <= dataa;
end
else
begin
c1_sign <= dataa[63];
// Convert the value to be positive prior to conversion
c1_value_to_convert <= (dataa ^ {64{dataa[63]}}) + {1'b0, dataa[63]};
end
end
end
// Cycle 2 - initial shifting to determine the magnitude of the number
reg [63:0] c2_value_to_convert;
reg [7:0] c2_exponent;
reg c2_sign, c2_done;
assign c2_enable = (HIGH_CAPACITY == 1) ? (~c2_valid | ~c2_stall) : enable;
assign c1_stall = c2_valid & c2_stall;
wire top_bits_0 = ~(|c1_value_to_convert[63:32]);
wire top_bits_half_0 = ~(|c1_value_to_convert[63:48]);
wire bottom_bits_0 = ~(|c1_value_to_convert[31:0]);
wire bottom_bits_half_0 = ~(|c1_value_to_convert[31:16]);
reg [1:0] c2_shift_value;
always@(*)
begin
c2_shift_value[1] = top_bits_0;
c2_shift_value[0] = top_bits_0 & bottom_bits_half_0 | ~top_bits_0 & top_bits_half_0;
end
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c2_valid <= 1'b0;
c2_value_to_convert <= 64'dx;
c2_exponent <= 8'dx;
c2_sign <= 1'bx;
c2_done <= 1'bx;
end
else if (c2_enable)
begin
c2_valid <= c1_valid;
c2_sign <= c1_sign;
c2_done <= top_bits_0 & bottom_bits_0;
if (top_bits_0 & bottom_bits_0)
begin
c2_exponent <= 8'd0;
c2_value_to_convert <= c1_value_to_convert;
end
else
begin
c2_exponent <= 8'd190 - {1'b0, c2_shift_value, 4'd0}; // = 8'd190 - 8'd32;
case(c2_shift_value)
2'b11: c2_value_to_convert <= {c1_value_to_convert[15:0], 48'd0};
2'b10: c2_value_to_convert <= {c1_value_to_convert[31:0], 32'd0};
2'b01: c2_value_to_convert <= {c1_value_to_convert[47:0], 16'd0};
2'b00: c2_value_to_convert <= c1_value_to_convert;
endcase
end
end
end
// Cycle 3 - second stage of shifting
reg [63:0] c3_value_to_convert;
reg [7:0] c3_exponent;
reg c3_sign, c3_done;
assign c3_enable = (HIGH_CAPACITY == 1) ? (~c3_valid | ~c3_stall) : enable;
assign c2_stall = c3_valid & c3_stall;
wire top_12bits_0 = ~(|c2_value_to_convert[63:52]);
wire top_8bits_0 = ~(|c2_value_to_convert[63:56]);
wire top_4bits_0 = ~(|c2_value_to_convert[63:60]);
reg [1:0] c3_exp_adjust;
always@(*)
begin
if (top_12bits_0 & ~c2_done)
c3_exp_adjust = 2'd3;
else if (top_8bits_0 & ~c2_done)
c3_exp_adjust = 2'd2;
else if (top_4bits_0 & ~c2_done)
c3_exp_adjust = 2'd1;
else
c3_exp_adjust = 2'd0;
end
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c3_valid <= 1'b0;
c3_value_to_convert <= 64'dx;
c3_exponent <= 8'dx;
c3_sign <= 1'bx;
c3_done <= 1'bx;
end
else if (c3_enable)
begin
c3_valid <= c2_valid;
c3_sign <= c2_sign;
c3_done <= c2_done;
c3_exponent <= c2_exponent - {1'b0, c3_exp_adjust, 2'd0};
case (c3_exp_adjust)
2'b11: c3_value_to_convert <= {c2_value_to_convert[51:0], 12'd0};
2'b10: c3_value_to_convert <= {c2_value_to_convert[55:0], 8'd0};
2'b01: c3_value_to_convert <= {c2_value_to_convert[59:0], 4'd0};
2'b00: c3_value_to_convert <= c2_value_to_convert;
endcase
end
end
// Cycle 4 - Last stage of shifting
reg [63:0] c4_value_to_convert;
reg [7:0] c4_exponent;
reg c4_sign;
assign c4_enable = (HIGH_CAPACITY == 1) ? (~c4_valid | ~c4_stall) : enable;
assign c3_stall = c4_valid & c4_stall;
wire top_3bits_0 = ~(|c3_value_to_convert[63:61]);
wire top_2bits_0 = ~(|c3_value_to_convert[63:62]);
wire top_1bits_0 = ~(c3_value_to_convert[63]);
reg [1:0] c4_exp_adjust;
always@(*)
begin
if (top_3bits_0 & ~c3_done)
c4_exp_adjust = 2'd3;
else if (top_2bits_0 & ~c3_done)
c4_exp_adjust = 2'd2;
else if (top_1bits_0 & ~c3_done)
c4_exp_adjust = 2'd1;
else
c4_exp_adjust = 2'd0;
end
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c4_valid <= 1'b0;
c4_value_to_convert <= 64'dx;
c4_exponent <= 8'dx;
c4_sign <= 1'bx;
end
else if (c4_enable)
begin
c4_valid <= c3_valid;
c4_sign <= c3_sign;
c4_exponent <= c3_exponent - {1'b0, c4_exp_adjust};
case (c4_exp_adjust)
2'b11: c4_value_to_convert <= {c3_value_to_convert[60:0], 3'd0};
2'b10: c4_value_to_convert <= {c3_value_to_convert[61:0], 2'd0};
2'b01: c4_value_to_convert <= {c3_value_to_convert[62:0], 1'd0};
2'b00: c4_value_to_convert <= c3_value_to_convert;
endcase
end
end
// Cycle 5 - Rounding stage
reg [22:0] c5_mantissa;
reg [7:0] c5_exponent;
reg c5_sign;
assign c5_enable = (HIGH_CAPACITY == 1) ? (~c5_valid | ~c5_stall) : enable;
assign c4_stall = c5_valid & c5_stall;
wire [3:0] c5_bottom_4 = {c4_value_to_convert[40:38], |c4_value_to_convert[37:0]};
reg [24:0] c5_temp_mantissa;
// 1 - round to nearest with ties away from zero
// 2 - round towards zero (truncation)
// 3 - round up
// 4 - round down
always@(*)
begin
case (ROUNDING_MODE)
4: // 4 - round down (towards -infinity)
begin
if (UNSIGNED == 1)
begin
c5_temp_mantissa <= {1'b0, c4_value_to_convert[63:40]};
end
else
begin
if (|c5_bottom_4[2:0] & c4_sign)
c5_temp_mantissa <= {1'b0, c4_value_to_convert[63:40]} + 1'b1;
else
c5_temp_mantissa <= {1'b0, c4_value_to_convert[63:40]};
end
end
3: // 3 - round up (towards +infinity)
begin
if (UNSIGNED == 1)
begin
if (|c5_bottom_4[2:0])
c5_temp_mantissa <= {1'b0, c4_value_to_convert[63:40]} + 1'b1;
else
c5_temp_mantissa <= {1'b0, c4_value_to_convert[63:40]};
end
else
begin
if (|c5_bottom_4[2:0] & ~c4_sign)
c5_temp_mantissa <= {1'b0, c4_value_to_convert[63:40]} + 1'b1;
else
c5_temp_mantissa <= {1'b0, c4_value_to_convert[63:40]};
end
end
2: // 2 - round towards zero (truncation)
begin
c5_temp_mantissa <= {1'b0, c4_value_to_convert[63:40]};
end
1: // 1 - round to nearest with ties away from zero
begin
if (c5_bottom_4[2])
c5_temp_mantissa <= {1'b0, c4_value_to_convert[63:40]} + 1'b1;
else
c5_temp_mantissa <= {1'b0, c4_value_to_convert[63:40]};
end
default: // 0 and default are round to nearest-even.
begin
if ((&c5_bottom_4[3:2]) || (c5_bottom_4[2] & |c5_bottom_4[1:0]))
c5_temp_mantissa <= {1'b0, c4_value_to_convert[63:40]} + 1'b1;
else
c5_temp_mantissa <= {1'b0, c4_value_to_convert[63:40]};
end
endcase
end
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c5_valid <= 1'b0;
c5_mantissa <= 32'dx;
c5_exponent <= 8'dx;
c5_sign <= 1'bx;
end
else if (c5_enable)
begin
c5_valid <= c4_valid;
c5_sign <= c4_sign;
c5_exponent <= c4_exponent + c5_temp_mantissa[24];
c5_mantissa <= c5_temp_mantissa[24] ? c5_temp_mantissa[23:1] : c5_temp_mantissa[22:0];
end
end
assign c5_stall = stall_in;
assign result = {c5_sign, c5_exponent, c5_mantissa};
assign valid_out = c5_valid;
endmodule
|
`define bsg_nor3_macro(bits) \
if (harden_p && (width_p==bits)) \
begin: macro \
bsg_rp_tsmc_40_NR3D1BWP_b``bits nor3_gate (.i0(a_i),.i1(b_i),.i2(c_i),.o); \
end
module bsg_nor3 #(parameter `BSG_INV_PARAM(width_p)
, parameter harden_p=0
)
(input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, input [width_p-1:0] c_i
, output [width_p-1:0] o
);
`bsg_nor3_macro(34) else
`bsg_nor3_macro(33) else
`bsg_nor3_macro(32) else
`bsg_nor3_macro(31) else
`bsg_nor3_macro(30) else
`bsg_nor3_macro(29) else
`bsg_nor3_macro(28) else
`bsg_nor3_macro(27) else
`bsg_nor3_macro(26) else
`bsg_nor3_macro(25) else
`bsg_nor3_macro(24) else
`bsg_nor3_macro(23) else
`bsg_nor3_macro(22) else
`bsg_nor3_macro(21) else
`bsg_nor3_macro(20) else
`bsg_nor3_macro(19) else
`bsg_nor3_macro(18) else
`bsg_nor3_macro(17) else
`bsg_nor3_macro(16) else
`bsg_nor3_macro(15) else
`bsg_nor3_macro(14) else
`bsg_nor3_macro(13) else
`bsg_nor3_macro(12) else
`bsg_nor3_macro(11) else
`bsg_nor3_macro(10) else
`bsg_nor3_macro(9) else
`bsg_nor3_macro(8) else
`bsg_nor3_macro(7) else
`bsg_nor3_macro(6) else
`bsg_nor3_macro(5) else
`bsg_nor3_macro(4) else
`bsg_nor3_macro(3) else
`bsg_nor3_macro(2) else
`bsg_nor3_macro(1) else
begin :notmacro
initial assert(harden_p==0) else $error("## %m wanted to harden but no macro");
assign o = ~(a_i | b_i | c_i);
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_nor3)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3_4_V
`define SKY130_FD_SC_HS__OR3_4_V
/**
* or3: 3-input OR.
*
* Verilog wrapper for or3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3_4_V
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-1-2017
*/
module jt12_kon(
input rst,
input clk,
input clk_en /* synthesis direct_enable */,
input [3:0] keyon_op,
input [2:0] keyon_ch,
input [1:0] next_op,
input [2:0] next_ch,
input up_keyon,
input csm,
// input flag_A,
input overflow_A,
output reg keyon_I
);
parameter num_ch=6;
wire csr_out;
generate
if(num_ch==6) begin
// capture overflow signal so it lasts long enough
reg overflow2;
reg [4:0] overflow_cycle;
always @(posedge clk) if( clk_en ) begin
if(overflow_A) begin
overflow2 <= 1'b1;
overflow_cycle <= { next_op, next_ch };
end else begin
if(overflow_cycle == {next_op, next_ch}) overflow2<=1'b0;
end
end
always @(posedge clk) if( clk_en )
keyon_I <= (csm&&next_ch==3'd2&&overflow2) || csr_out;
reg up_keyon_reg;
reg [3:0] tkeyon_op;
reg [2:0] tkeyon_ch;
wire key_upnow;
assign key_upnow = up_keyon_reg && (tkeyon_ch==next_ch) && (next_op == 2'd3);
always @(posedge clk) if( clk_en ) begin
if (rst)
up_keyon_reg <= 1'b0;
if (up_keyon) begin
up_keyon_reg <= 1'b1;
tkeyon_op <= keyon_op;
tkeyon_ch <= keyon_ch; end
else if (key_upnow)
up_keyon_reg <= 1'b0;
end
wire middle1;
wire middle2;
wire middle3;
wire din = key_upnow ? tkeyon_op[3] : csr_out;
wire mid_din2 = key_upnow ? tkeyon_op[1] : middle1;
wire mid_din3 = key_upnow ? tkeyon_op[2] : middle2;
wire mid_din4 = key_upnow ? tkeyon_op[0] : middle3;
jt12_sh_rst #(.width(1),.stages(6),.rstval(1'b0)) u_konch0(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( din ),
.drop ( middle1 )
);
jt12_sh_rst #(.width(1),.stages(6),.rstval(1'b0)) u_konch1(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( mid_din2 ),
.drop ( middle2 )
);
jt12_sh_rst #(.width(1),.stages(6),.rstval(1'b0)) u_konch2(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( mid_din3 ),
.drop ( middle3 )
);
jt12_sh_rst #(.width(1),.stages(6),.rstval(1'b0)) u_konch3(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( mid_din4 ),
.drop ( csr_out )
);
end
else begin // 3 channels
reg din;
reg [3:0] next_op_hot;
always @(*) begin
case( next_op )
2'd0: next_op_hot = 4'b0001; // S1
2'd1: next_op_hot = 4'b0100; // S3
2'd2: next_op_hot = 4'b0010; // S2
2'd3: next_op_hot = 4'b1000; // S4
endcase
din = keyon_ch[1:0]==next_ch[1:0] && up_keyon ? |(keyon_op&next_op_hot) : csr_out;
end
always @(posedge clk) if( clk_en )
keyon_I <= csr_out; // No CSM for YM2203
jt12_sh_rst #(.width(1),.stages(12),.rstval(1'b0)) u_konch1(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( din ),
.drop ( csr_out )
);
end
endgenerate
endmodule
|
// lpddr2_cntrlr_0002.v
// This file was auto-generated from alt_mem_if_lpddr2_emif_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module lpddr2_cntrlr_0002 (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire afi_clk, // afi_clk.clk
output wire afi_half_clk, // afi_half_clk.clk
output wire afi_reset_n, // afi_reset.reset_n
output wire afi_reset_export_n, // afi_reset_export.reset_n
output wire [9:0] mem_ca, // memory.mem_ca
output wire [0:0] mem_ck, // .mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [3:0] mem_dm, // .mem_dm
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire avl_ready_0, // avl_0.waitrequest_n
input wire avl_burstbegin_0, // .beginbursttransfer
input wire [26:0] avl_addr_0, // .address
output wire avl_rdata_valid_0, // .readdatavalid
output wire [31:0] avl_rdata_0, // .readdata
input wire [31:0] avl_wdata_0, // .writedata
input wire [3:0] avl_be_0, // .byteenable
input wire avl_read_req_0, // .read
input wire avl_write_req_0, // .write
input wire [2:0] avl_size_0, // .burstcount
input wire mp_cmd_clk_0_clk, // mp_cmd_clk_0.clk
input wire mp_cmd_reset_n_0_reset_n, // mp_cmd_reset_n_0.reset_n
input wire mp_rfifo_clk_0_clk, // mp_rfifo_clk_0.clk
input wire mp_rfifo_reset_n_0_reset_n, // mp_rfifo_reset_n_0.reset_n
input wire mp_wfifo_clk_0_clk, // mp_wfifo_clk_0.clk
input wire mp_wfifo_reset_n_0_reset_n, // mp_wfifo_reset_n_0.reset_n
output wire local_init_done, // status.local_init_done
output wire local_cal_success, // .local_cal_success
output wire local_cal_fail, // .local_cal_fail
input wire oct_rzqin, // oct.rzqin
output wire pll_mem_clk, // pll_sharing.pll_mem_clk
output wire pll_write_clk, // .pll_write_clk
output wire pll_locked, // .pll_locked
output wire pll_write_clk_pre_phy_clk, // .pll_write_clk_pre_phy_clk
output wire pll_addr_cmd_clk, // .pll_addr_cmd_clk
output wire pll_avl_clk, // .pll_avl_clk
output wire pll_config_clk, // .pll_config_clk
output wire pll_mem_phy_clk, // .pll_mem_phy_clk
output wire afi_phy_clk, // .afi_phy_clk
output wire pll_avl_phy_clk // .pll_avl_phy_clk
);
wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire p0_avl_clk_clk; // p0:avl_clk -> s0:avl_clk
wire p0_avl_reset_reset; // p0:avl_reset_n -> s0:avl_reset_n
wire p0_scc_clk_clk; // p0:scc_clk -> s0:scc_clk
wire p0_scc_reset_reset; // p0:scc_reset_n -> s0:reset_n_scc_clk
wire [31:0] s0_scc_scc_dq_ena; // s0:scc_dq_ena -> p0:scc_dq_ena
wire [0:0] s0_scc_scc_upd; // s0:scc_upd -> p0:scc_upd
wire [3:0] s0_scc_scc_dqs_io_ena; // s0:scc_dqs_io_ena -> p0:scc_dqs_io_ena
wire [3:0] s0_scc_scc_dm_ena; // s0:scc_dm_ena -> p0:scc_dm_ena
wire [3:0] p0_scc_capture_strobe_tracking; // p0:capture_strobe_tracking -> s0:capture_strobe_tracking
wire [3:0] s0_scc_scc_dqs_ena; // s0:scc_dqs_ena -> p0:scc_dqs_ena
wire [0:0] s0_scc_scc_data; // s0:scc_data -> p0:scc_data
wire [0:0] s0_tracking_afi_seq_busy; // s0:afi_seq_busy -> c0:afi_seq_busy
wire [31:0] s0_avl_readdata; // p0:avl_readdata -> s0:avl_readdata
wire s0_avl_waitrequest; // p0:avl_waitrequest -> s0:avl_waitrequest
wire [15:0] s0_avl_address; // s0:avl_address -> p0:avl_address
wire s0_avl_read; // s0:avl_read -> p0:avl_read
wire s0_avl_write; // s0:avl_write -> p0:avl_write
wire [31:0] s0_avl_writedata; // s0:avl_writedata -> p0:avl_writedata
wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
wire c0_afi_afi_init_req; // c0:afi_init_req -> s0:afi_init_req
wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [0:0] c0_afi_afi_ctl_refresh_done; // c0:afi_ctl_refresh_done -> s0:afi_ctl_refresh_done
wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire c0_afi_afi_cal_req; // c0:afi_cal_req -> s0:afi_cal_req
wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [0:0] c0_afi_afi_ctl_long_idle; // c0:afi_ctl_long_idle -> s0:afi_ctl_long_idle
wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd
wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig
wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth
wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi
wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl
wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc
wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat
wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr
wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat
wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk
wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n
wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail
wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess
wire [15:0] oct0_oct_sharing_parallelterminationcontrol; // oct0:parallelterminationcontrol -> p0:parallelterminationcontrol
wire [15:0] oct0_oct_sharing_seriesterminationcontrol; // oct0:seriesterminationcontrol -> p0:seriesterminationcontrol
wire p0_dll_clk_clk; // p0:dll_clk -> dll0:clk
wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll0:dll_pll_locked
wire [6:0] dll0_dll_sharing_dll_delayctrl; // dll0:dll_delayctrl -> p0:dll_delayctrl
lpddr2_cntrlr_pll0 pll0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.afi_clk (afi_clk), // afi_clk.clk
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.pll_mem_clk (pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_write_clk), // .pll_write_clk
.pll_locked (pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_avl_phy_clk) // .pll_avl_phy_clk
);
lpddr2_cntrlr_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.afi_reset_export_n (afi_reset_export_n), // afi_reset_export.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_clk (afi_clk), // afi_clk.clk
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.avl_clk (p0_avl_clk_clk), // avl_clk.clk
.avl_reset_n (p0_avl_reset_reset), // avl_reset.reset_n
.scc_clk (p0_scc_clk_clk), // scc_clk.clk
.scc_reset_n (p0_scc_reset_reset), // scc_reset.reset_n
.avl_address (s0_avl_address), // avl.address
.avl_write (s0_avl_write), // .write
.avl_writedata (s0_avl_writedata), // .writedata
.avl_read (s0_avl_read), // .read
.avl_readdata (s0_avl_readdata), // .readdata
.avl_waitrequest (s0_avl_waitrequest), // .waitrequest
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.scc_data (s0_scc_scc_data), // scc.scc_data
.scc_dqs_ena (s0_scc_scc_dqs_ena), // .scc_dqs_ena
.scc_dqs_io_ena (s0_scc_scc_dqs_io_ena), // .scc_dqs_io_ena
.scc_dq_ena (s0_scc_scc_dq_ena), // .scc_dq_ena
.scc_dm_ena (s0_scc_scc_dm_ena), // .scc_dm_ena
.capture_strobe_tracking (p0_scc_capture_strobe_tracking), // .capture_strobe_tracking
.scc_upd (s0_scc_scc_upd), // .scc_upd
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
.pll_mem_clk (pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_write_clk), // .pll_write_clk
.pll_locked (pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_avl_phy_clk), // .pll_avl_phy_clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll0_dll_sharing_dll_delayctrl), // .dll_delayctrl
.seriesterminationcontrol (oct0_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct0_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
.mem_ca (mem_ca), // memory.mem_ca
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.csr_soft_reset_req (1'b0), // (terminated)
.io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intbadout (12'b000000000000), // (terminated)
.io_intcasndout (4'b0000), // (terminated)
.io_intckdout (4'b0000), // (terminated)
.io_intckedout (8'b00000000), // (terminated)
.io_intckndout (4'b0000), // (terminated)
.io_intcsndout (8'b00000000), // (terminated)
.io_intdmdout (20'b00000000000000000000), // (terminated)
.io_intdqdin (), // (terminated)
.io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqsbdout (20'b00000000000000000000), // (terminated)
.io_intdqsboe (10'b0000000000), // (terminated)
.io_intdqsdout (20'b00000000000000000000), // (terminated)
.io_intdqslogicdqsena (10'b0000000000), // (terminated)
.io_intdqslogicfiforeset (5'b00000), // (terminated)
.io_intdqslogicincrdataen (10'b0000000000), // (terminated)
.io_intdqslogicincwrptr (10'b0000000000), // (terminated)
.io_intdqslogicoct (10'b0000000000), // (terminated)
.io_intdqslogicrdatavalid (), // (terminated)
.io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated)
.io_intdqsoe (10'b0000000000), // (terminated)
.io_intodtdout (8'b00000000), // (terminated)
.io_intrasndout (4'b0000), // (terminated)
.io_intresetndout (4'b0000), // (terminated)
.io_intwendout (4'b0000), // (terminated)
.io_intafirlat (), // (terminated)
.io_intafiwlat () // (terminated)
);
lpddr2_cntrlr_s0 s0 (
.avl_clk (p0_avl_clk_clk), // avl_clk.clk
.avl_reset_n (p0_avl_reset_reset), // avl_reset.reset_n
.scc_clk (p0_scc_clk_clk), // scc_clk.clk
.reset_n_scc_clk (p0_scc_reset_reset), // scc_reset.reset_n
.scc_data (s0_scc_scc_data), // scc.scc_data
.scc_dqs_ena (s0_scc_scc_dqs_ena), // .scc_dqs_ena
.scc_dqs_io_ena (s0_scc_scc_dqs_io_ena), // .scc_dqs_io_ena
.scc_dq_ena (s0_scc_scc_dq_ena), // .scc_dq_ena
.scc_dm_ena (s0_scc_scc_dm_ena), // .scc_dm_ena
.capture_strobe_tracking (p0_scc_capture_strobe_tracking), // .capture_strobe_tracking
.scc_upd (s0_scc_scc_upd), // .scc_upd
.afi_init_req (c0_afi_afi_init_req), // afi_init_cal_req.afi_init_req
.afi_cal_req (c0_afi_afi_cal_req), // .afi_cal_req
.avl_address (s0_avl_address), // avl.address
.avl_write (s0_avl_write), // .write
.avl_writedata (s0_avl_writedata), // .writedata
.avl_read (s0_avl_read), // .read
.avl_readdata (s0_avl_readdata), // .readdata
.avl_waitrequest (s0_avl_waitrequest), // .waitrequest
.afi_seq_busy (s0_tracking_afi_seq_busy), // tracking.afi_seq_busy
.afi_ctl_refresh_done (c0_afi_afi_ctl_refresh_done), // .afi_ctl_refresh_done
.afi_ctl_long_idle (c0_afi_afi_ctl_long_idle) // .afi_ctl_long_idle
);
altera_mem_if_hard_memory_controller_top_cyclonev #(
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_CLK_PAIR_COUNT (1),
.CSR_ADDR_WIDTH (10),
.CSR_DATA_WIDTH (8),
.CSR_BE_WIDTH (1),
.AVL_ADDR_WIDTH (26),
.AVL_DATA_WIDTH (64),
.AVL_SIZE_WIDTH (3),
.AVL_DATA_WIDTH_PORT_0 (32),
.AVL_ADDR_WIDTH_PORT_0 (27),
.AVL_NUM_SYMBOLS_PORT_0 (4),
.LSB_WFIFO_PORT_0 (0),
.MSB_WFIFO_PORT_0 (0),
.LSB_RFIFO_PORT_0 (0),
.MSB_RFIFO_PORT_0 (0),
.AVL_DATA_WIDTH_PORT_1 (1),
.AVL_ADDR_WIDTH_PORT_1 (1),
.AVL_NUM_SYMBOLS_PORT_1 (1),
.LSB_WFIFO_PORT_1 (5),
.MSB_WFIFO_PORT_1 (5),
.LSB_RFIFO_PORT_1 (5),
.MSB_RFIFO_PORT_1 (5),
.AVL_DATA_WIDTH_PORT_2 (1),
.AVL_ADDR_WIDTH_PORT_2 (1),
.AVL_NUM_SYMBOLS_PORT_2 (1),
.LSB_WFIFO_PORT_2 (5),
.MSB_WFIFO_PORT_2 (5),
.LSB_RFIFO_PORT_2 (5),
.MSB_RFIFO_PORT_2 (5),
.AVL_DATA_WIDTH_PORT_3 (1),
.AVL_ADDR_WIDTH_PORT_3 (1),
.AVL_NUM_SYMBOLS_PORT_3 (1),
.LSB_WFIFO_PORT_3 (5),
.MSB_WFIFO_PORT_3 (5),
.LSB_RFIFO_PORT_3 (5),
.MSB_RFIFO_PORT_3 (5),
.AVL_DATA_WIDTH_PORT_4 (1),
.AVL_ADDR_WIDTH_PORT_4 (1),
.AVL_NUM_SYMBOLS_PORT_4 (1),
.LSB_WFIFO_PORT_4 (5),
.MSB_WFIFO_PORT_4 (5),
.LSB_RFIFO_PORT_4 (5),
.MSB_RFIFO_PORT_4 (5),
.AVL_DATA_WIDTH_PORT_5 (1),
.AVL_ADDR_WIDTH_PORT_5 (1),
.AVL_NUM_SYMBOLS_PORT_5 (1),
.LSB_WFIFO_PORT_5 (5),
.MSB_WFIFO_PORT_5 (5),
.LSB_RFIFO_PORT_5 (5),
.MSB_RFIFO_PORT_5 (5),
.ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"),
.ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"),
.ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"),
.ENUM_CAL_REQ ("DISABLED"),
.ENUM_CFG_BURST_LENGTH ("BL_8"),
.ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_32"),
.ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"),
.ENUM_CFG_TYPE ("LPDDR2"),
.ENUM_CLOCK_OFF_0 ("DISABLED"),
.ENUM_CLOCK_OFF_1 ("DISABLED"),
.ENUM_CLOCK_OFF_2 ("DISABLED"),
.ENUM_CLOCK_OFF_3 ("DISABLED"),
.ENUM_CLOCK_OFF_4 ("DISABLED"),
.ENUM_CLOCK_OFF_5 ("DISABLED"),
.ENUM_CLR_INTR ("NO_CLR_INTR"),
.ENUM_CMD_PORT_IN_USE_0 ("TRUE"),
.ENUM_CMD_PORT_IN_USE_1 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_2 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_3 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_4 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_5 ("FALSE"),
.ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT0_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT0_TYPE ("BI_DIRECTION"),
.ENUM_CPORT0_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT1_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_TYPE ("DISABLE"),
.ENUM_CPORT1_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT2_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_TYPE ("DISABLE"),
.ENUM_CPORT2_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT3_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_TYPE ("DISABLE"),
.ENUM_CPORT3_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT4_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_TYPE ("DISABLE"),
.ENUM_CPORT4_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT5_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_TYPE ("DISABLE"),
.ENUM_CPORT5_WFIFO_MAP ("FIFO_0"),
.ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"),
.ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"),
.ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"),
.ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"),
.ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"),
.ENUM_CTRL_WIDTH ("DATA_WIDTH_64_BIT"),
.ENUM_DELAY_BONDING ("BONDING_LATENCY_0"),
.ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"),
.ENUM_DISABLE_MERGING ("MERGING_ENABLED"),
.ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"),
.ENUM_ENABLE_ATPG ("DISABLED"),
.ENUM_ENABLE_BONDING_0 ("DISABLED"),
.ENUM_ENABLE_BONDING_1 ("DISABLED"),
.ENUM_ENABLE_BONDING_2 ("DISABLED"),
.ENUM_ENABLE_BONDING_3 ("DISABLED"),
.ENUM_ENABLE_BONDING_4 ("DISABLED"),
.ENUM_ENABLE_BONDING_5 ("DISABLED"),
.ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"),
.ENUM_ENABLE_DQS_TRACKING ("ENABLED"),
.ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"),
.ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"),
.ENUM_ENABLE_INTR ("DISABLED"),
.ENUM_ENABLE_NO_DM ("DISABLED"),
.ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"),
.ENUM_GANGED_ARF ("DISABLED"),
.ENUM_GEN_DBE ("GEN_DBE_DISABLED"),
.ENUM_GEN_SBE ("GEN_SBE_DISABLED"),
.ENUM_INC_SYNC ("FIFO_SET_2"),
.ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"),
.ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"),
.ENUM_MASK_DBE_INTR ("DISABLED"),
.ENUM_MASK_SBE_INTR ("DISABLED"),
.ENUM_MEM_IF_AL ("AL_0"),
.ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"),
.ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"),
.ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"),
.ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"),
.ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"),
.ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"),
.ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_4"),
.ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_32"),
.ENUM_MEM_IF_MEMTYPE ("LPDDR2_SDRAM"),
.ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_14"),
.ENUM_MEM_IF_SPEEDBIN ("DDR3_1066_6_6_6"),
.ENUM_MEM_IF_TCCD ("TCCD_2"),
.ENUM_MEM_IF_TCL ("TCL_7"),
.ENUM_MEM_IF_TCWL ("TCWL_4"),
.ENUM_MEM_IF_TFAW ("TFAW_16"),
.ENUM_MEM_IF_TRAS ("TRAS_23"),
.ENUM_MEM_IF_TRC ("TRC_29"),
.ENUM_MEM_IF_TRCD ("TRCD_6"),
.ENUM_MEM_IF_TRP ("TRP_6"),
.ENUM_MEM_IF_TRRD ("TRRD_4"),
.ENUM_MEM_IF_TRTP ("TRTP_3"),
.ENUM_MEM_IF_TWR ("TWR_5"),
.ENUM_MEM_IF_TWTR ("TWTR_2"),
.ENUM_MMR_CFG_MEM_BL ("MP_BL_8"),
.ENUM_OUTPUT_REGD ("DISABLED"),
.ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"),
.ENUM_PORT0_WIDTH ("PORT_32_BIT"),
.ENUM_PORT1_WIDTH ("PORT_32_BIT"),
.ENUM_PORT2_WIDTH ("PORT_32_BIT"),
.ENUM_PORT3_WIDTH ("PORT_32_BIT"),
.ENUM_PORT4_WIDTH ("PORT_32_BIT"),
.ENUM_PORT5_WIDTH ("PORT_32_BIT"),
.ENUM_PRIORITY_0_0 ("WEIGHT_0"),
.ENUM_PRIORITY_0_1 ("WEIGHT_0"),
.ENUM_PRIORITY_0_2 ("WEIGHT_0"),
.ENUM_PRIORITY_0_3 ("WEIGHT_0"),
.ENUM_PRIORITY_0_4 ("WEIGHT_0"),
.ENUM_PRIORITY_0_5 ("WEIGHT_0"),
.ENUM_PRIORITY_1_0 ("WEIGHT_0"),
.ENUM_PRIORITY_1_1 ("WEIGHT_0"),
.ENUM_PRIORITY_1_2 ("WEIGHT_0"),
.ENUM_PRIORITY_1_3 ("WEIGHT_0"),
.ENUM_PRIORITY_1_4 ("WEIGHT_0"),
.ENUM_PRIORITY_1_5 ("WEIGHT_0"),
.ENUM_PRIORITY_2_0 ("WEIGHT_0"),
.ENUM_PRIORITY_2_1 ("WEIGHT_0"),
.ENUM_PRIORITY_2_2 ("WEIGHT_0"),
.ENUM_PRIORITY_2_3 ("WEIGHT_0"),
.ENUM_PRIORITY_2_4 ("WEIGHT_0"),
.ENUM_PRIORITY_2_5 ("WEIGHT_0"),
.ENUM_PRIORITY_3_0 ("WEIGHT_0"),
.ENUM_PRIORITY_3_1 ("WEIGHT_0"),
.ENUM_PRIORITY_3_2 ("WEIGHT_0"),
.ENUM_PRIORITY_3_3 ("WEIGHT_0"),
.ENUM_PRIORITY_3_4 ("WEIGHT_0"),
.ENUM_PRIORITY_3_5 ("WEIGHT_0"),
.ENUM_PRIORITY_4_0 ("WEIGHT_0"),
.ENUM_PRIORITY_4_1 ("WEIGHT_0"),
.ENUM_PRIORITY_4_2 ("WEIGHT_0"),
.ENUM_PRIORITY_4_3 ("WEIGHT_0"),
.ENUM_PRIORITY_4_4 ("WEIGHT_0"),
.ENUM_PRIORITY_4_5 ("WEIGHT_0"),
.ENUM_PRIORITY_5_0 ("WEIGHT_0"),
.ENUM_PRIORITY_5_1 ("WEIGHT_0"),
.ENUM_PRIORITY_5_2 ("WEIGHT_0"),
.ENUM_PRIORITY_5_3 ("WEIGHT_0"),
.ENUM_PRIORITY_5_4 ("WEIGHT_0"),
.ENUM_PRIORITY_5_5 ("WEIGHT_0"),
.ENUM_PRIORITY_6_0 ("WEIGHT_0"),
.ENUM_PRIORITY_6_1 ("WEIGHT_0"),
.ENUM_PRIORITY_6_2 ("WEIGHT_0"),
.ENUM_PRIORITY_6_3 ("WEIGHT_0"),
.ENUM_PRIORITY_6_4 ("WEIGHT_0"),
.ENUM_PRIORITY_6_5 ("WEIGHT_0"),
.ENUM_PRIORITY_7_0 ("WEIGHT_0"),
.ENUM_PRIORITY_7_1 ("WEIGHT_0"),
.ENUM_PRIORITY_7_2 ("WEIGHT_0"),
.ENUM_PRIORITY_7_3 ("WEIGHT_0"),
.ENUM_PRIORITY_7_4 ("WEIGHT_0"),
.ENUM_PRIORITY_7_5 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_RD_DWIDTH_0 ("DWIDTH_32"),
.ENUM_RD_DWIDTH_1 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_2 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_3 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_4 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_5 ("DWIDTH_0"),
.ENUM_RD_FIFO_IN_USE_0 ("TRUE"),
.ENUM_RD_FIFO_IN_USE_1 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_2 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_3 ("FALSE"),
.ENUM_RD_PORT_INFO_0 ("USE_0"),
.ENUM_RD_PORT_INFO_1 ("USE_NO"),
.ENUM_RD_PORT_INFO_2 ("USE_NO"),
.ENUM_RD_PORT_INFO_3 ("USE_NO"),
.ENUM_RD_PORT_INFO_4 ("USE_NO"),
.ENUM_RD_PORT_INFO_5 ("USE_NO"),
.ENUM_READ_ODT_CHIP ("ODT_DISABLED"),
.ENUM_REORDER_DATA ("DATA_REORDERING"),
.ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"),
.ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"),
.ENUM_TEST_MODE ("NORMAL_MODE"),
.ENUM_THLD_JAR1_0 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_1 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_2 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_3 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_4 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_5 ("THRESHOLD_32"),
.ENUM_THLD_JAR2_0 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_1 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_2 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_3 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_4 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_5 ("THRESHOLD_16"),
.ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"),
.ENUM_USER_ECC_EN ("DISABLE"),
.ENUM_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WR_DWIDTH_0 ("DWIDTH_32"),
.ENUM_WR_DWIDTH_1 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_2 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_3 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_4 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_5 ("DWIDTH_0"),
.ENUM_WR_FIFO_IN_USE_0 ("TRUE"),
.ENUM_WR_FIFO_IN_USE_1 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_2 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_3 ("FALSE"),
.ENUM_WR_PORT_INFO_0 ("USE_0"),
.ENUM_WR_PORT_INFO_1 ("USE_NO"),
.ENUM_WR_PORT_INFO_2 ("USE_NO"),
.ENUM_WR_PORT_INFO_3 ("USE_NO"),
.ENUM_WR_PORT_INFO_4 ("USE_NO"),
.ENUM_WR_PORT_INFO_5 ("USE_NO"),
.ENUM_WRITE_ODT_CHIP ("ODT_DISABLED"),
.INTG_MEM_AUTO_PD_CYCLES (0),
.INTG_CYC_TO_RLD_JARS_0 (1),
.INTG_CYC_TO_RLD_JARS_1 (1),
.INTG_CYC_TO_RLD_JARS_2 (1),
.INTG_CYC_TO_RLD_JARS_3 (1),
.INTG_CYC_TO_RLD_JARS_4 (1),
.INTG_CYC_TO_RLD_JARS_5 (1),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0),
.INTG_EXTRA_CTL_CLK_ARF_PERIOD (0),
.INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PDN_PERIOD (0),
.INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0),
.INTG_EXTRA_CTL_CLK_RD_TO_WR (4),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (4),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (4),
.INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0),
.INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_WR_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_WR_TO_RD (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3),
.INTG_EXTRA_CTL_CLK_WR_TO_WR (0),
.INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0),
.INTG_MEM_IF_TREFI (1248),
.INTG_MEM_IF_TRFC (20),
.INTG_RCFG_SUM_WT_PRIORITY_0 (0),
.INTG_RCFG_SUM_WT_PRIORITY_1 (0),
.INTG_RCFG_SUM_WT_PRIORITY_2 (0),
.INTG_RCFG_SUM_WT_PRIORITY_3 (0),
.INTG_RCFG_SUM_WT_PRIORITY_4 (0),
.INTG_RCFG_SUM_WT_PRIORITY_5 (0),
.INTG_RCFG_SUM_WT_PRIORITY_6 (0),
.INTG_RCFG_SUM_WT_PRIORITY_7 (0),
.INTG_SUM_WT_PRIORITY_0 (0),
.INTG_SUM_WT_PRIORITY_1 (0),
.INTG_SUM_WT_PRIORITY_2 (0),
.INTG_SUM_WT_PRIORITY_3 (0),
.INTG_SUM_WT_PRIORITY_4 (0),
.INTG_SUM_WT_PRIORITY_5 (0),
.INTG_SUM_WT_PRIORITY_6 (0),
.INTG_SUM_WT_PRIORITY_7 (0),
.INTG_POWER_SAVING_EXIT_CYCLES (5),
.INTG_MEM_CLK_ENTRY_CYCLES (10),
.ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"),
.ENUM_ENABLE_BURST_TERMINATE ("DISABLED"),
.AFI_RATE_RATIO (1),
.AFI_ADDR_WIDTH (20),
.AFI_BANKADDR_WIDTH (0),
.AFI_CONTROL_WIDTH (2),
.AFI_CS_WIDTH (1),
.AFI_DM_WIDTH (8),
.AFI_DQ_WIDTH (64),
.AFI_ODT_WIDTH (0),
.AFI_WRITE_DQS_WIDTH (4),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6),
.HARD_PHY (1)
) c0 (
.afi_clk (afi_clk), // afi_clk.clk
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.mp_cmd_clk_0 (mp_cmd_clk_0_clk), // mp_cmd_clk_0.clk
.mp_cmd_reset_n_0 (mp_cmd_reset_n_0_reset_n), // mp_cmd_reset_n_0.reset_n
.mp_rfifo_clk_0 (mp_rfifo_clk_0_clk), // mp_rfifo_clk_0.clk
.mp_rfifo_reset_n_0 (mp_rfifo_reset_n_0_reset_n), // mp_rfifo_reset_n_0.reset_n
.mp_wfifo_clk_0 (mp_wfifo_clk_0_clk), // mp_wfifo_clk_0.clk
.mp_wfifo_reset_n_0 (mp_wfifo_reset_n_0_reset_n), // mp_wfifo_reset_n_0.reset_n
.avl_ready_0 (avl_ready_0), // avl_0.waitrequest_n
.avl_burstbegin_0 (avl_burstbegin_0), // .beginbursttransfer
.avl_addr_0 (avl_addr_0), // .address
.avl_rdata_valid_0 (avl_rdata_valid_0), // .readdatavalid
.avl_rdata_0 (avl_rdata_0), // .readdata
.avl_wdata_0 (avl_wdata_0), // .writedata
.avl_be_0 (avl_be_0), // .byteenable
.avl_read_req_0 (avl_read_req_0), // .read
.avl_write_req_0 (avl_write_req_0), // .write
.avl_size_0 (avl_size_0), // .burstcount
.local_init_done (local_init_done), // status.local_init_done
.local_cal_success (local_cal_success), // .local_cal_success
.local_cal_fail (local_cal_fail), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (c0_afi_afi_init_req), // .afi_init_req
.afi_cal_req (c0_afi_afi_cal_req), // .afi_cal_req
.afi_seq_busy (s0_tracking_afi_seq_busy), // .afi_seq_busy
.afi_ctl_refresh_done (c0_afi_afi_ctl_refresh_done), // .afi_ctl_refresh_done
.afi_ctl_long_idle (c0_afi_afi_ctl_long_idle), // .afi_ctl_long_idle
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.mp_cmd_clk_1 (1'b0), // (terminated)
.mp_cmd_reset_n_1 (1'b1), // (terminated)
.mp_cmd_clk_2 (1'b0), // (terminated)
.mp_cmd_reset_n_2 (1'b1), // (terminated)
.mp_cmd_clk_3 (1'b0), // (terminated)
.mp_cmd_reset_n_3 (1'b1), // (terminated)
.mp_cmd_clk_4 (1'b0), // (terminated)
.mp_cmd_reset_n_4 (1'b1), // (terminated)
.mp_cmd_clk_5 (1'b0), // (terminated)
.mp_cmd_reset_n_5 (1'b1), // (terminated)
.mp_rfifo_clk_1 (1'b0), // (terminated)
.mp_rfifo_reset_n_1 (1'b1), // (terminated)
.mp_wfifo_clk_1 (1'b0), // (terminated)
.mp_wfifo_reset_n_1 (1'b1), // (terminated)
.mp_rfifo_clk_2 (1'b0), // (terminated)
.mp_rfifo_reset_n_2 (1'b1), // (terminated)
.mp_wfifo_clk_2 (1'b0), // (terminated)
.mp_wfifo_reset_n_2 (1'b1), // (terminated)
.mp_rfifo_clk_3 (1'b0), // (terminated)
.mp_rfifo_reset_n_3 (1'b1), // (terminated)
.mp_wfifo_clk_3 (1'b0), // (terminated)
.mp_wfifo_reset_n_3 (1'b1), // (terminated)
.csr_clk (1'b0), // (terminated)
.csr_reset_n (1'b1), // (terminated)
.avl_ready_1 (), // (terminated)
.avl_burstbegin_1 (1'b0), // (terminated)
.avl_addr_1 (1'b0), // (terminated)
.avl_rdata_valid_1 (), // (terminated)
.avl_rdata_1 (), // (terminated)
.avl_wdata_1 (1'b0), // (terminated)
.avl_be_1 (1'b0), // (terminated)
.avl_read_req_1 (1'b0), // (terminated)
.avl_write_req_1 (1'b0), // (terminated)
.avl_size_1 (3'b000), // (terminated)
.avl_ready_2 (), // (terminated)
.avl_burstbegin_2 (1'b0), // (terminated)
.avl_addr_2 (1'b0), // (terminated)
.avl_rdata_valid_2 (), // (terminated)
.avl_rdata_2 (), // (terminated)
.avl_wdata_2 (1'b0), // (terminated)
.avl_be_2 (1'b0), // (terminated)
.avl_read_req_2 (1'b0), // (terminated)
.avl_write_req_2 (1'b0), // (terminated)
.avl_size_2 (3'b000), // (terminated)
.avl_ready_3 (), // (terminated)
.avl_burstbegin_3 (1'b0), // (terminated)
.avl_addr_3 (1'b0), // (terminated)
.avl_rdata_valid_3 (), // (terminated)
.avl_rdata_3 (), // (terminated)
.avl_wdata_3 (1'b0), // (terminated)
.avl_be_3 (1'b0), // (terminated)
.avl_read_req_3 (1'b0), // (terminated)
.avl_write_req_3 (1'b0), // (terminated)
.avl_size_3 (3'b000), // (terminated)
.avl_ready_4 (), // (terminated)
.avl_burstbegin_4 (1'b0), // (terminated)
.avl_addr_4 (1'b0), // (terminated)
.avl_rdata_valid_4 (), // (terminated)
.avl_rdata_4 (), // (terminated)
.avl_wdata_4 (1'b0), // (terminated)
.avl_be_4 (1'b0), // (terminated)
.avl_read_req_4 (1'b0), // (terminated)
.avl_write_req_4 (1'b0), // (terminated)
.avl_size_4 (3'b000), // (terminated)
.avl_ready_5 (), // (terminated)
.avl_burstbegin_5 (1'b0), // (terminated)
.avl_addr_5 (1'b0), // (terminated)
.avl_rdata_valid_5 (), // (terminated)
.avl_rdata_5 (), // (terminated)
.avl_wdata_5 (1'b0), // (terminated)
.avl_be_5 (1'b0), // (terminated)
.avl_read_req_5 (1'b0), // (terminated)
.avl_write_req_5 (1'b0), // (terminated)
.avl_size_5 (3'b000), // (terminated)
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (10'b0000000000), // (terminated)
.csr_be (1'b0), // (terminated)
.csr_wdata (8'b00000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_deep_powerdn_req (1'b0), // (terminated)
.local_deep_powerdn_chip (1'b0), // (terminated)
.local_deep_powerdn_ack (), // (terminated)
.local_powerdn_ack (), // (terminated)
.local_priority (1'b0), // (terminated)
.bonding_in_1 (4'b0000), // (terminated)
.bonding_in_2 (6'b000000), // (terminated)
.bonding_in_3 (6'b000000), // (terminated)
.bonding_out_1 (), // (terminated)
.bonding_out_2 (), // (terminated)
.bonding_out_3 () // (terminated)
);
altera_mem_if_oct_cyclonev #(
.OCT_TERM_CONTROL_WIDTH (16)
) oct0 (
.oct_rzqin (oct_rzqin), // oct.rzqin
.seriesterminationcontrol (oct0_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct0_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
);
altera_mem_if_dll_cyclonev #(
.DLL_DELAY_CTRL_WIDTH (7),
.DLL_OFFSET_CTRL_WIDTH (6),
.DELAY_BUFFER_MODE ("HIGH"),
.DELAY_CHAIN_LENGTH (8),
.DLL_INPUT_FREQUENCY_PS_STR ("3125 ps")
) dll0 (
.clk (p0_dll_clk_clk), // clk.clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll0_dll_sharing_dll_delayctrl) // .dll_delayctrl
);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : gtx_drp_chanalign_fix_3752_v6.v
// Version : 2.3
//--
//-- Description: Virtex6 Workaround for deadlock due lane-lane skew Bug
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns / 1ps
module GTX_DRP_CHANALIGN_FIX_3752_V6
#(
parameter TCQ = 1,
parameter C_SIMULATION = 0 // Set to 1 for simulation
)
(
output reg dwe,
output reg [15:0] din, //THIS IS THE INPUT TO THE DRP
output reg den,
output reg [7:0] daddr,
output reg [3:0] drpstate,
input write_ts1,
input write_fts,
input [15:0] dout, //THIS IS THE OUTPUT OF THE DRP
input drdy,
input Reset_n,
input drp_clk
);
reg [7:0] next_daddr;
reg [3:0] next_drpstate;
reg write_ts1_gated;
reg write_fts_gated;
localparam DRP_IDLE_FTS = 1;
localparam DRP_IDLE_TS1 = 2;
localparam DRP_RESET = 3;
localparam DRP_WRITE_FTS = 6;
localparam DRP_WRITE_DONE_FTS = 7;
localparam DRP_WRITE_TS1 = 8;
localparam DRP_WRITE_DONE_TS1 = 9;
localparam DRP_COM = 10'b0110111100;
localparam DRP_FTS = 10'b0100111100;
localparam DRP_TS1 = 10'b0001001010;
always @(posedge drp_clk) begin
if ( ~Reset_n ) begin
daddr <= #(TCQ) 8'h8;
drpstate <= #(TCQ) DRP_RESET;
write_ts1_gated <= #(TCQ) 0;
write_fts_gated <= #(TCQ) 0;
end else begin
daddr <= #(TCQ) next_daddr;
drpstate <= #(TCQ) next_drpstate;
write_ts1_gated <= #(TCQ) write_ts1;
write_fts_gated <= #(TCQ) write_fts;
end
end
always @(*) begin
// DEFAULT CONDITIONS
next_drpstate=drpstate;
next_daddr=daddr;
den=0;
din=0;
dwe=0;
case(drpstate)
// RESET CONDITION, WE NEED TO READ THE TOP 6 BITS OF THE DRP REGISTER WHEN WE GET THE WRITE FTS TRIGGER
DRP_RESET : begin
next_drpstate= DRP_WRITE_TS1;
next_daddr=8'h8;
end
// WRITE FTS SEQUENCE
DRP_WRITE_FTS : begin
den=1;
dwe=1;
if(daddr==8'h8)
din=16'hFD3C;
else if(daddr==8'h9)
din=16'hC53C;
else if(daddr==8'hA)
din=16'hFDBC;
else if(daddr==8'hB)
din=16'h853C;
next_drpstate=DRP_WRITE_DONE_FTS;
end
// WAIT FOR FTS SEQUENCE WRITE TO FINISH, ONCE WE FINISH ALL WRITES GO TO FTS IDLE
DRP_WRITE_DONE_FTS : begin
if(drdy) begin
if(daddr==8'hB) begin
next_drpstate=DRP_IDLE_FTS;
next_daddr=8'h8;
end else begin
next_drpstate=DRP_WRITE_FTS;
next_daddr=daddr+1'b1;
end
end
end
// FTS IDLE: WAIT HERE UNTIL WE NEED TO WRITE TS1
DRP_IDLE_FTS : begin
if(write_ts1_gated) begin
next_drpstate=DRP_WRITE_TS1;
next_daddr=8'h8;
end
end
// WRITE TS1 SEQUENCE
DRP_WRITE_TS1 : begin
den=1;
dwe=1;
if(daddr==8'h8)
din=16'hFC4A;
else if(daddr==8'h9)
din=16'hDC4A; //CHANGE
else if(daddr==8'hA)
din=16'hC04A; //CHANGE
else if(daddr==8'hB)
din=16'h85BC;
next_drpstate=DRP_WRITE_DONE_TS1;
end
// WAIT FOR TS1 SEQUENCE WRITE TO FINISH, ONCE WE FINISH ALL WRITES GO TO TS1 IDLE
DRP_WRITE_DONE_TS1 : begin
if(drdy) begin
if(daddr==8'hB) begin
next_drpstate=DRP_IDLE_TS1;
next_daddr=8'h8;
end else begin
next_drpstate=DRP_WRITE_TS1;
next_daddr=daddr+1'b1;
end
end
end
// TS1 IDLE: WAIT HERE UNTIL WE NEED TO WRITE FTS
DRP_IDLE_TS1 : begin
if(write_fts_gated) begin
next_drpstate=DRP_WRITE_FTS;
next_daddr=8'h8;
end
end
endcase
end
endmodule
|
(** * Stlc: The Simply Typed Lambda-Calculus *)
Require Export Types.
(* ###################################################################### *)
(** * The Simply Typed Lambda-Calculus *)
(** The simply typed lambda-calculus (STLC) is a tiny core calculus
embodying the key concept of _functional abstraction_, which shows
up in pretty much every real-world programming language in some
form (functions, procedures, methods, etc.).
We will follow exactly the same pattern as in the previous
chapter when formalizing this calculus (syntax, small-step
semantics, typing rules) and its main properties (progress and
preservation). The new technical challenges (which will take some
work to deal with) all arise from the mechanisms of _variable
binding_ and _substitution_. *)
(* ###################################################################### *)
(** ** Overview *)
(** The STLC is built on some collection of _base types_ -- booleans,
numbers, strings, etc. The exact choice of base types doesn't
matter -- the construction of the language and its theoretical
properties work out pretty much the same -- so for the sake of
brevity let's take just [Bool] for the moment. At the end of the
chapter we'll see how to add more base types, and in later
chapters we'll enrich the pure STLC with other useful constructs
like pairs, records, subtyping, and mutable state.
Starting from the booleans, we add three things:
- variables
- function abstractions
- application
This gives us the following collection of abstract syntax
constructors (written out here in informal BNF notation -- we'll
formalize it below).
*)
(** Informal concrete syntax:
t ::= x variable
| \x:T1.t2 abstraction
| t1 t2 application
| true constant true
| false constant false
| if t1 then t2 else t3 conditional
*)
(** The [\] symbol (backslash, in ascii) in a function abstraction
[\x:T1.t2] is generally written as a greek letter "lambda" (hence
the name of the calculus). The variable [x] is called the
_parameter_ to the function; the term [t1] is its _body_. The
annotation [:T] specifies the type of arguments that the function
can be applied to. *)
(** Some examples:
- [\x:Bool. x]
The identity function for booleans.
- [(\x:Bool. x) true]
The identity function for booleans, applied to the boolean [true].
- [\x:Bool. if x then false else true]
The boolean "not" function.
- [\x:Bool. true]
The constant function that takes every (boolean) argument to
[true]. *)
(**
- [\x:Bool. \y:Bool. x]
A two-argument function that takes two booleans and returns
the first one. (Note that, as in Coq, a two-argument function
is really a one-argument function whose body is also a
one-argument function.)
- [(\x:Bool. \y:Bool. x) false true]
A two-argument function that takes two booleans and returns
the first one, applied to the booleans [false] and [true].
Note that, as in Coq, application associates to the left --
i.e., this expression is parsed as [((\x:Bool. \y:Bool. x)
false) true].
- [\f:Bool->Bool. f (f true)]
A higher-order function that takes a _function_ [f] (from
booleans to booleans) as an argument, applies [f] to [true],
and applies [f] again to the result.
- [(\f:Bool->Bool. f (f true)) (\x:Bool. false)]
The same higher-order function, applied to the constantly
[false] function. *)
(** As the last several examples show, the STLC is a language of
_higher-order_ functions: we can write down functions that take
other functions as arguments and/or return other functions as
results.
Another point to note is that the STLC doesn't provide any
primitive syntax for defining _named_ functions -- all functions
are "anonymous." We'll see in chapter [MoreStlc] that it is easy
to add named functions to what we've got -- indeed, the
fundamental naming and binding mechanisms are exactly the same.
The _types_ of the STLC include [Bool], which classifies the
boolean constants [true] and [false] as well as more complex
computations that yield booleans, plus _arrow types_ that classify
functions. *)
(**
T ::= Bool
| T1 -> T2
For example:
- [\x:Bool. false] has type [Bool->Bool]
- [\x:Bool. x] has type [Bool->Bool]
- [(\x:Bool. x) true] has type [Bool]
- [\x:Bool. \y:Bool. x] has type [Bool->Bool->Bool] (i.e. [Bool -> (Bool->Bool)])
- [(\x:Bool. \y:Bool. x) false] has type [Bool->Bool]
- [(\x:Bool. \y:Bool. x) false true] has type [Bool]
*)
(* ###################################################################### *)
(** ** Syntax *)
Module STLC.
(* ################################### *)
(** *** Types *)
Inductive ty : Type :=
| TBool : ty
| TArrow : ty -> ty -> ty.
(* ################################### *)
(** *** Terms *)
Inductive tm : Type :=
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp"
| Case_aux c "tabs" | Case_aux c "ttrue"
| Case_aux c "tfalse" | Case_aux c "tif" ].
(** Note that an abstraction [\x:T.t] (formally, [tabs x T t]) is
always annotated with the type [T] of its parameter, in contrast
to Coq (and other functional languages like ML, Haskell, etc.),
which use _type inference_ to fill in missing annotations. We're
not considering type inference here, to keep things simple. *)
(** Some examples... *)
Definition x := (Id 0).
Definition y := (Id 1).
Definition z := (Id 2).
Hint Unfold x.
Hint Unfold y.
Hint Unfold z.
(** [idB = \x:Bool. x] *)
Notation idB :=
(tabs x TBool (tvar x)).
(** [idBB = \x:Bool->Bool. x] *)
Notation idBB :=
(tabs x (TArrow TBool TBool) (tvar x)).
(** [idBBBB = \x:(Bool->Bool) -> (Bool->Bool). x] *)
Notation idBBBB :=
(tabs x (TArrow (TArrow TBool TBool)
(TArrow TBool TBool))
(tvar x)).
(** [k = \x:Bool. \y:Bool. x] *)
Notation k := (tabs x TBool (tabs y TBool (tvar x))).
(** [notB = \x:Bool. if x then false else true] *)
Notation notB := (tabs x TBool (tif (tvar x) tfalse ttrue)).
(** (We write these as [Notation]s rather than [Definition]s to make
things easier for [auto].) *)
(* ###################################################################### *)
(** ** Operational Semantics *)
(** To define the small-step semantics of STLC terms, we begin -- as
always -- by defining the set of values. Next, we define the
critical notions of _free variables_ and _substitution_, which are
used in the reduction rule for application expressions. And
finally we give the small-step relation itself. *)
(* ################################### *)
(** *** Values *)
(** To define the values of the STLC, we have a few cases to consider.
First, for the boolean part of the language, the situation is
clear: [true] and [false] are the only values. An [if]
expression is never a value. *)
(** Second, an application is clearly not a value: It represents a
function being invoked on some argument, which clearly still has
work left to do. *)
(** Third, for abstractions, we have a choice:
- We can say that [\x:T.t1] is a value only when [t1] is a
value -- i.e., only if the function's body has been
reduced (as much as it can be without knowing what argument it
is going to be applied to).
- Or we can say that [\x:T.t1] is always a value, no matter
whether [t1] is one or not -- in other words, we can say that
reduction stops at abstractions.
Coq, in its built-in functional programming langauge, makes the
first choice -- for example,
Eval simpl in (fun x:bool => 3 + 4)
yields [fun x:bool => 7].
Most real-world functional programming languages make the second
choice -- reduction of a function's body only begins when the
function is actually applied to an argument. We also make the
second choice here. *)
(** Finally, having made the choice not to reduce under abstractions,
we don't need to worry about whether variables are values, since
we'll always be reducing programs "from the outside in," and that
means the [step] relation will always be working with closed
terms (ones with no free variables). *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_true :
value ttrue
| v_false :
value tfalse.
Hint Constructors value.
(* ###################################################################### *)
(** *** Free Variables and Substitution *)
(** Now we come to the heart of the STLC: the operation of
substituting one term for a variable in another term.
This operation will be used below to define the operational
semantics of function application, where we will need to
substitute the argument term for the function parameter in the
function's body. For example, we reduce
(\x:Bool. if x then true else x) false
to
if false then true else false
]]
by substituting [false] for the parameter [x] in the body of the
function.
In general, we need to be able to substitute some given
term [s] for occurrences of some variable [x] in another term [t].
In informal discussions, this is usually written [ [x:=s]t ] and
pronounced "substitute [x] with [s] in [t]." *)
(** Here are some examples:
- [[x:=true] (if x then x else false)] yields [if true then true else false]
- [[x:=true] x] yields [true]
- [[x:=true] (if x then x else y)] yields [if true then true else y]
- [[x:=true] y] yields [y]
- [[x:=true] false] yields [false] (vacuous substitution)
- [[x:=true] (\y:Bool. if y then x else false)] yields [\y:Bool. if y then true else false]
- [[x:=true] (\y:Bool. x)] yields [\y:Bool. true]
- [[x:=true] (\y:Bool. y)] yields [\y:Bool. y]
- [[x:=true] (\x:Bool. x)] yields [\x:Bool. x]
The last example is very important: substituting [x] with [true] in
[\x:Bool. x] does _not_ yield [\x:Bool. true]! The reason for
this is that the [x] in the body of [\x:Bool. x] is _bound_ by the
abstraction: it is a new, local name that just happens to be
spelled the same as some global name [x]. *)
(** Here is the definition, informally...
[x:=s]x = s
[x:=s]y = y if x <> y
[x:=s](\x:T11.t12) = \x:T11. t12
[x:=s](\y:T11.t12) = \y:T11. [x:=s]t12 if x <> y
[x:=s](t1 t2) = ([x:=s]t1) ([x:=s]t2)
[x:=s]true = true
[x:=s]false = false
[x:=s](if t1 then t2 else t3) =
if [x:=s]t1 then [x:=s]t2 else [x:=s]t3
]]
... and formally: *)
Reserved Notation "'[' x ':=' s ']' t" (at level 20).
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar x' =>
if eq_id_dec x x' then s else t
| tabs x' T t1 =>
tabs x' T (if eq_id_dec x x' then t1 else ([x:=s] t1))
| tapp t1 t2 =>
tapp ([x:=s] t1) ([x:=s] t2)
| ttrue =>
ttrue
| tfalse =>
tfalse
| tif t1 t2 t3 =>
tif ([x:=s] t1) ([x:=s] t2) ([x:=s] t3)
end
where "'[' x ':=' s ']' t" := (subst x s t).
(** _Technical note_: Substitution becomes trickier to define if we
consider the case where [s], the term being substituted for a
variable in some other term, may itself contain free variables.
Since we are only interested here in defining the [step] relation
on closed terms (i.e., terms like [\x:Bool. x], that do not mention
variables are not bound by some enclosing lambda), we can skip
this extra complexity here, but it must be dealt with when
formalizing richer languages. *)
(** *** *)
(** **** Exercise: 3 stars (substi) *)
(** The definition that we gave above uses Coq's [Fixpoint] facility
to define substitution as a _function_. Suppose, instead, we
wanted to define substitution as an inductive _relation_ [substi].
We've begun the definition by providing the [Inductive] header and
one of the constructors; your job is to fill in the rest of the
constructors. *)
Inductive substi (s:tm) (x:id) : tm -> tm -> Prop :=
| s_var1 :
substi s x (tvar x) s
(* FILL IN HERE *)
.
Hint Constructors substi.
Theorem substi_correct : forall s x t t',
[x:=s]t = t' <-> substi s x t t'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################### *)
(** *** Reduction *)
(** The small-step reduction relation for STLC now follows the same
pattern as the ones we have seen before. Intuitively, to reduce a
function application, we first reduce its left-hand side until it
becomes a literal function; then we reduce its right-hand
side (the argument) until it is also a value; and finally we
substitute the argument for the bound variable in the body of the
function. This last rule, written informally as
(\x:T.t12) v2 ==> [x:=v2]t12
is traditionally called "beta-reduction". *)
(**
value v2
---------------------------- (ST_AppAbs)
(\x:T.t12) v2 ==> [x:=v2]t12
t1 ==> t1'
---------------- (ST_App1)
t1 t2 ==> t1' t2
value v1
t2 ==> t2'
---------------- (ST_App2)
v1 t2 ==> v1 t2'
*)
(** ... plus the usual rules for booleans:
-------------------------------- (ST_IfTrue)
(if true then t1 else t2) ==> t1
--------------------------------- (ST_IfFalse)
(if false then t1 else t2) ==> t2
t1 ==> t1'
---------------------------------------------------- (ST_If)
(if t1 then t2 else t3) ==> (if t1' then t2 else t3)
*)
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
tapp t1 t2 ==> tapp t1' t2
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
tapp v1 t2 ==> tapp v1 t2'
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1"
| Case_aux c "ST_App2" | Case_aux c "ST_IfTrue"
| Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
Hint Constructors step.
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
(* ##################################### *)
(** *** Examples *)
(** Example:
((\x:Bool->Bool. x) (\x:Bool. x)) ==>* (\x:Bool. x)
i.e.
(idBB idB) ==>* idB
*)
Lemma step_example1 :
(tapp idBB idB) ==>* idB.
Proof.
eapply multi_step.
apply ST_AppAbs.
apply v_abs.
simpl.
apply multi_refl. Qed.
(** Example:
((\x:Bool->Bool. x) ((\x:Bool->Bool. x) (\x:Bool. x)))
==>* (\x:Bool. x)
i.e.
(idBB (idBB idB)) ==>* idB.
*)
Lemma step_example2 :
(tapp idBB (tapp idBB idB)) ==>* idB.
Proof.
eapply multi_step.
apply ST_App2. auto.
apply ST_AppAbs. auto.
eapply multi_step.
apply ST_AppAbs. simpl. auto.
simpl. apply multi_refl. Qed.
(** Example:
((\x:Bool->Bool. x) (\x:Bool. if x then false
else true)) true)
==>* false
i.e.
((idBB notB) ttrue) ==>* tfalse.
*)
Lemma step_example3 :
tapp (tapp idBB notB) ttrue ==>* tfalse.
Proof.
eapply multi_step.
apply ST_App1. apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_IfTrue. apply multi_refl. Qed.
(** Example:
((\x:Bool->Bool. x) ((\x:Bool. if x then false
else true) true))
==>* false
i.e.
(idBB (notB ttrue)) ==>* tfalse.
*)
Lemma step_example4 :
tapp idBB (tapp notB ttrue) ==>* tfalse.
Proof.
eapply multi_step.
apply ST_App2. auto.
apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_App2. auto.
apply ST_IfTrue.
eapply multi_step.
apply ST_AppAbs. auto. simpl.
apply multi_refl. Qed.
(** A more automatic proof *)
Lemma step_example1' :
(tapp idBB idB) ==>* idB.
Proof. normalize. Qed.
(** Again, we can use the [normalize] tactic from above to simplify
the proof. *)
Lemma step_example2' :
(tapp idBB (tapp idBB idB)) ==>* idB.
Proof.
normalize.
Qed.
Lemma step_example3' :
tapp (tapp idBB notB) ttrue ==>* tfalse.
Proof. normalize. Qed.
Lemma step_example4' :
tapp idBB (tapp notB ttrue) ==>* tfalse.
Proof. normalize. Qed.
(** **** Exercise: 2 stars (step_example3) *)
(** Try to do this one both with and without [normalize]. *)
Lemma step_example5 :
(tapp (tapp idBBBB idBB) idB)
==>* idB.
Proof.
(* FILL IN HERE *) Admitted.
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** ** Typing *)
(* ################################### *)
(** *** Contexts *)
(** _Question_: What is the type of the term "[x y]"?
_Answer_: It depends on the types of [x] and [y]!
I.e., in order to assign a type to a term, we need to know
what assumptions we should make about the types of its free
variables.
This leads us to a three-place "typing judgment", informally
written [Gamma |- t : T], where [Gamma] is a
"typing context" -- a mapping from variables to their types. *)
(** We hide the definition of partial maps in a module since it is
actually defined in [SfLib]. *)
Module PartialMap.
Definition partial_map (A:Type) := id -> option A.
Definition empty {A:Type} : partial_map A := (fun _ => None).
(** Informally, we'll write [Gamma, x:T] for "extend the partial
function [Gamma] to also map [x] to [T]." Formally, we use the
function [extend] to add a binding to a partial map. *)
Definition extend {A:Type} (Gamma : partial_map A) (x:id) (T : A) :=
fun x' => if eq_id_dec x x' then Some T else Gamma x'.
Lemma extend_eq : forall A (ctxt: partial_map A) x T,
(extend ctxt x T) x = Some T.
Proof.
intros. unfold extend. rewrite eq_id. auto.
Qed.
Lemma extend_neq : forall A (ctxt: partial_map A) x1 T x2,
x2 <> x1 ->
(extend ctxt x2 T) x1 = ctxt x1.
Proof.
intros. unfold extend. rewrite neq_id; auto.
Qed.
End PartialMap.
Definition context := partial_map ty.
(* ################################### *)
(** *** Typing Relation *)
(**
Gamma x = T
-------------- (T_Var)
Gamma |- x \in T
Gamma , x:T11 |- t12 \in T12
---------------------------- (T_Abs)
Gamma |- \x:T11.t12 \in T11->T12
Gamma |- t1 \in T11->T12
Gamma |- t2 \in T11
---------------------- (T_App)
Gamma |- t1 t2 \in T12
-------------------- (T_True)
Gamma |- true \in Bool
--------------------- (T_False)
Gamma |- false \in Bool
Gamma |- t1 \in Bool Gamma |- t2 \in T Gamma |- t3 \in T
-------------------------------------------------------- (T_If)
Gamma |- if t1 then t2 else t3 \in T
We can read the three-place relation [Gamma |- t \in T] as:
"to the term [t] we can assign the type [T] using as types for
the free variables of [t] the ones specified in the context
[Gamma]." *)
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- tvar x \in T
| T_Abs : forall Gamma x T11 T12 t12,
extend Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
| T_App : forall T11 T12 Gamma t1 t2,
Gamma |- t1 \in TArrow T11 T12 ->
Gamma |- t2 \in T11 ->
Gamma |- tapp t1 t2 \in T12
| T_True : forall Gamma,
Gamma |- ttrue \in TBool
| T_False : forall Gamma,
Gamma |- tfalse \in TBool
| T_If : forall t1 t2 t3 T Gamma,
Gamma |- t1 \in TBool ->
Gamma |- t2 \in T ->
Gamma |- t3 \in T ->
Gamma |- tif t1 t2 t3 \in T
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs"
| Case_aux c "T_App" | Case_aux c "T_True"
| Case_aux c "T_False" | Case_aux c "T_If" ].
Hint Constructors has_type.
(* ################################### *)
(** *** Examples *)
Example typing_example_1 :
empty |- tabs x TBool (tvar x) \in TArrow TBool TBool.
Proof.
apply T_Abs. apply T_Var. reflexivity. Qed.
(** Note that since we added the [has_type] constructors to the hints
database, auto can actually solve this one immediately. *)
Example typing_example_1' :
empty |- tabs x TBool (tvar x) \in TArrow TBool TBool.
Proof. auto. Qed.
(** Another example:
empty |- \x:A. \y:A->A. y (y x))
\in A -> (A->A) -> A.
*)
Example typing_example_2 :
empty |-
(tabs x TBool
(tabs y (TArrow TBool TBool)
(tapp (tvar y) (tapp (tvar y) (tvar x))))) \in
(TArrow TBool (TArrow (TArrow TBool TBool) TBool)).
Proof with auto using extend_eq.
apply T_Abs.
apply T_Abs.
eapply T_App. apply T_Var...
eapply T_App. apply T_Var...
apply T_Var...
Qed.
(** **** Exercise: 2 stars, optional (typing_example_2_full) *)
(** Prove the same result without using [auto], [eauto], or
[eapply]. *)
Example typing_example_2_full :
empty |-
(tabs x TBool
(tabs y (TArrow TBool TBool)
(tapp (tvar y) (tapp (tvar y) (tvar x))))) \in
(TArrow TBool (TArrow (TArrow TBool TBool) TBool)).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (typing_example_3) *)
(** Formally prove the following typing derivation holds: *)
(**
empty |- \x:Bool->B. \y:Bool->Bool. \z:Bool.
y (x z)
\in T.
*)
Example typing_example_3 :
exists T,
empty |-
(tabs x (TArrow TBool TBool)
(tabs y (TArrow TBool TBool)
(tabs z TBool
(tapp (tvar y) (tapp (tvar x) (tvar z)))))) \in
T.
Proof with auto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** We can also show that terms are _not_ typable. For example, let's
formally check that there is no typing derivation assigning a type
to the term [\x:Bool. \y:Bool, x y] -- i.e.,
~ exists T,
empty |- \x:Bool. \y:Bool, x y : T.
*)
Example typing_nonexample_1 :
~ exists T,
empty |-
(tabs x TBool
(tabs y TBool
(tapp (tvar x) (tvar y)))) \in
T.
Proof.
intros Hc. inversion Hc.
(* The [clear] tactic is useful here for tidying away bits of
the context that we're not going to need again. *)
inversion H. subst. clear H.
inversion H5. subst. clear H5.
inversion H4. subst. clear H4.
inversion H2. subst. clear H2.
inversion H5. subst. clear H5.
(* rewrite extend_neq in H1. rewrite extend_eq in H1. *)
inversion H1. Qed.
(** **** Exercise: 3 stars, optional (typing_nonexample_3) *)
(** Another nonexample:
~ (exists S, exists T,
empty |- \x:S. x x : T).
*)
Example typing_nonexample_3 :
~ (exists S, exists T,
empty |-
(tabs x S
(tapp (tvar x) (tvar x))) \in
T).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End STLC.
(* $Date: 2013-07-18 09:59:22 -0400 (Thu, 18 Jul 2013) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4B_4_V
`define SKY130_FD_SC_HS__OR4B_4_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or4b_4 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or4b_4 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4B_4_V
|
/******************************************************************************
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
*****************************************************************************
*
* Filename: BLK_MEM_GEN_v8_2.v
*
* Description:
* This file is the Verilog behvarial model for the
* Block Memory Generator Core.
*
*****************************************************************************
* Author: Xilinx
*
* History: Jan 11, 2006 Initial revision
* Jun 11, 2007 Added independent register stages for
* Port A and Port B (IP1_Jm/v2.5)
* Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)
* Mar 13, 2008 Behavioral model optimizations
* April 07, 2009 : Added support for Spartan-6 and Virtex-6
* features, including the following:
* (i) error injection, detection and/or correction
* (ii) reset priority
* (iii) special reset behavior
*
*****************************************************************************/
`timescale 1ps/1ps
module STATE_LOGIC_v8_2 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4, I3, I2, I1, I0}];
end
endmodule
module beh_vlog_muxf7_v8_2 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
O = I1;
else
O = I0;
endmodule
module beh_vlog_ff_clr_v8_2 (Q, C, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q<= 1'b0;
else
Q<= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_pre_v8_2 (Q, C, D, PRE);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, D, PRE;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (PRE)
Q <= 1'b1;
else
Q <= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_ce_clr_v8_2 (Q, C, CE, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CE, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q <= 1'b0;
else if (CE)
Q <= #FLOP_DELAY D;
endmodule
module write_netlist_v8_2
#(
parameter C_AXI_TYPE = 0
)
(
S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c
);
input S_ACLK;
input S_ARESETN;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input S_AXI_BREADY;
input w_last_c;
input bready_timeout_c;
output aw_ready_r;
output S_AXI_WREADY;
output S_AXI_BVALID;
output S_AXI_WR_EN;
output addr_en_c;
output incr_addr_c;
output bvalid_c;
//-------------------------------------------------------------------------
//AXI LITE
//-------------------------------------------------------------------------
generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm
wire w_ready_r_7;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSignal_bvalid_c;
wire NlwRenamedSignal_incr_addr_c;
wire present_state_FSM_FFd3_13;
wire present_state_FSM_FFd2_14;
wire present_state_FSM_FFd1_15;
wire present_state_FSM_FFd4_16;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd4_In1_21;
wire [0:0] Mmux_aw_ready_c ;
begin
assign
S_AXI_WREADY = w_ready_r_7,
S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,
S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,
incr_addr_c = NlwRenamedSignal_incr_addr_c,
bvalid_c = NlwRenamedSignal_bvalid_c;
assign NlwRenamedSignal_incr_addr_c = 1'b0;
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
aw_ready_r_2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
w_ready_r (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_7)
);
beh_vlog_ff_pre_v8_2 #(
.INIT (1'b1))
present_state_FSM_FFd4 (
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_16)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd3 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_13)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_15)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000055554440))
present_state_FSM_FFd3_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000088880800))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_AWVALID),
.I1 ( S_AXI_WVALID),
.I2 ( bready_timeout_c),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000AAAA2000))
Mmux_addr_en_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_WVALID),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( addr_en_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hF5F07570F5F05500))
Mmux_w_ready_c_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( w_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd3_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd1_15),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( present_state_FSM_FFd3_13),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSignal_bvalid_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h2F0F27072F0F2200))
present_state_FSM_FFd4_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( present_state_FSM_FFd4_In1_21)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000F8))
present_state_FSM_FFd4_In2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_In1_21),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h7535753575305500))
Mmux_aw_ready_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_WVALID),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 ( present_state_FSM_FFd2_14),
.O ( Mmux_aw_ready_c[0])
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000F8))
Mmux_aw_ready_c_0_2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( Mmux_aw_ready_c[0]),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( aw_ready_c)
);
end
end
endgenerate
//---------------------------------------------------------------------
// AXI FULL
//---------------------------------------------------------------------
generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm
wire w_ready_r_8;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSig_OI_bvalid_c;
wire present_state_FSM_FFd1_16;
wire present_state_FSM_FFd4_17;
wire present_state_FSM_FFd3_18;
wire present_state_FSM_FFd2_19;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd2_In1_24;
wire present_state_FSM_FFd4_In1_25;
wire N2;
wire N4;
begin
assign
S_AXI_WREADY = w_ready_r_8,
bvalid_c = NlwRenamedSig_OI_bvalid_c,
S_AXI_BVALID = 1'b0;
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
aw_ready_r_2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
w_ready_r
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_8)
);
beh_vlog_ff_pre_v8_2 #(
.INIT (1'b1))
present_state_FSM_FFd4
(
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_17)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd3
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_18)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_19)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd1
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_16)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000005540))
present_state_FSM_FFd3_In1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd4_17),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hBF3FBB33AF0FAA00))
Mmux_aw_ready_c_0_2
(
.I0 ( S_AXI_BREADY),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd1_16),
.I4 ( present_state_FSM_FFd4_17),
.I5 ( NlwRenamedSig_OI_bvalid_c),
.O ( aw_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hAAAAAAAA20000000))
Mmux_addr_en_c_0_1
(
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( S_AXI_WVALID),
.I4 ( w_last_c),
.I5 ( present_state_FSM_FFd4_17),
.O ( addr_en_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_19),
.I2 ( present_state_FSM_FFd3_18),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( S_AXI_WR_EN)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000002220))
Mmux_incr_addr_c_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( incr_addr_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000008880))
Mmux_aw_ready_c_0_11
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSig_OI_bvalid_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000000000D5C0))
present_state_FSM_FFd2_In1
(
.I0 ( w_last_c),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In1_24)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hFFFFAAAA08AAAAAA))
present_state_FSM_FFd2_In2
(
.I0 ( present_state_FSM_FFd2_19),
.I1 ( S_AXI_AWVALID),
.I2 ( bready_timeout_c),
.I3 ( w_last_c),
.I4 ( S_AXI_WVALID),
.I5 ( present_state_FSM_FFd2_In1_24),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00C0004000C00000))
present_state_FSM_FFd4_In1
(
.I0 ( S_AXI_AWVALID),
.I1 ( w_last_c),
.I2 ( S_AXI_WVALID),
.I3 ( bready_timeout_c),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( present_state_FSM_FFd4_In1_25)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000FFFF88F8))
present_state_FSM_FFd4_In2
(
.I0 ( present_state_FSM_FFd1_16),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( S_AXI_AWVALID),
.I4 ( present_state_FSM_FFd4_In1_25),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000007))
Mmux_w_ready_c_0_SW0
(
.I0 ( w_last_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N2)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hFABAFABAFAAAF000))
Mmux_w_ready_c_0_Q
(
.I0 ( N2),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd4_17),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( w_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000008))
Mmux_aw_ready_c_0_11_SW0
(
.I0 ( bready_timeout_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N4)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1
(
.I0 ( w_last_c),
.I1 ( N4),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 ( present_state_FSM_FFd1_16),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
end
end
endgenerate
endmodule
module read_netlist_v8_2 #(
parameter C_AXI_TYPE = 1,
parameter C_ADDRB_WIDTH = 12
) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);
input S_AXI_R_LAST_INT;
input S_ACLK;
input S_ARESETN;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_INCR_ADDR;
output S_AXI_ADDR_EN;
output S_AXI_SINGLE_TRANS;
output S_AXI_MUX_SEL;
output S_AXI_R_LAST;
output S_AXI_ARREADY;
output S_AXI_RLAST;
output S_AXI_RVALID;
output S_AXI_RD_EN;
input [7:0] S_AXI_ARLEN;
wire present_state_FSM_FFd1_13 ;
wire present_state_FSM_FFd2_14 ;
wire gaxi_full_sm_outstanding_read_r_15 ;
wire gaxi_full_sm_ar_ready_r_16 ;
wire gaxi_full_sm_r_last_r_17 ;
wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ;
wire gaxi_full_sm_r_valid_c ;
wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ;
wire gaxi_full_sm_ar_ready_c ;
wire gaxi_full_sm_outstanding_read_c ;
wire NlwRenamedSig_OI_S_AXI_R_LAST ;
wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ;
wire present_state_FSM_FFd2_In ;
wire present_state_FSM_FFd1_In ;
wire Mmux_S_AXI_R_LAST13 ;
wire N01 ;
wire N2 ;
wire Mmux_gaxi_full_sm_ar_ready_c11 ;
wire N4 ;
wire N8 ;
wire N9 ;
wire N10 ;
wire N11 ;
wire N12 ;
wire N13 ;
assign
S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,
S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,
S_AXI_RLAST = gaxi_full_sm_r_last_r_17,
S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
gaxi_full_sm_outstanding_read_r (
.C (S_ACLK),
.CLR(S_ARESETN),
.D(gaxi_full_sm_outstanding_read_c),
.Q(gaxi_full_sm_outstanding_read_r_15)
);
beh_vlog_ff_ce_clr_v8_2 #(
.INIT (1'b0))
gaxi_full_sm_r_valid_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (gaxi_full_sm_r_valid_c),
.Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
gaxi_full_sm_ar_ready_r (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (gaxi_full_sm_ar_ready_c),
.Q (gaxi_full_sm_ar_ready_r_16)
);
beh_vlog_ff_ce_clr_v8_2 #(
.INIT(1'b0))
gaxi_full_sm_r_last_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (NlwRenamedSig_OI_S_AXI_R_LAST),
.Q (gaxi_full_sm_r_last_r_17)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (present_state_FSM_FFd1_In),
.Q (present_state_FSM_FFd1_13)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000000000000B))
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (
.I0 ( S_AXI_RREADY),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000008))
Mmux_S_AXI_SINGLE_TRANS11 (
.I0 (S_AXI_ARVALID),
.I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_SINGLE_TRANS)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000004))
Mmux_S_AXI_ADDR_EN11 (
.I0 (present_state_FSM_FFd1_13),
.I1 (S_AXI_ARVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_ADDR_EN)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hECEE2022EEEE2022))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_ARVALID),
.I1 ( present_state_FSM_FFd1_13),
.I2 ( S_AXI_RREADY),
.I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000044440444))
Mmux_S_AXI_R_LAST131 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_RREADY),
.I5 (1'b0),
.O ( Mmux_S_AXI_R_LAST13)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h4000FFFF40004000))
Mmux_S_AXI_INCR_ADDR11 (
.I0 ( S_AXI_R_LAST_INT),
.I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( Mmux_S_AXI_R_LAST13),
.O ( S_AXI_INCR_ADDR)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000FE))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (
.I0 ( S_AXI_ARLEN[2]),
.I1 ( S_AXI_ARLEN[1]),
.I2 ( S_AXI_ARLEN[0]),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N01)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000001))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (
.I0 ( S_AXI_ARLEN[7]),
.I1 ( S_AXI_ARLEN[6]),
.I2 ( S_AXI_ARLEN[5]),
.I3 ( S_AXI_ARLEN[4]),
.I4 ( S_AXI_ARLEN[3]),
.I5 ( N01),
.O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000007))
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 ( 1'b0),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N2)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0020000002200200))
Mmux_gaxi_full_sm_outstanding_read_c1 (
.I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd1_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( gaxi_full_sm_outstanding_read_r_15),
.I5 ( N2),
.O ( gaxi_full_sm_outstanding_read_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000004555))
Mmux_gaxi_full_sm_ar_ready_c12 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( Mmux_gaxi_full_sm_ar_ready_c11)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000EF))
Mmux_S_AXI_R_LAST11_SW0 (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N4)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hFCAAFC0A00AA000A))
Mmux_S_AXI_R_LAST11 (
.I0 ( S_AXI_ARVALID),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( N4),
.I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.O ( gaxi_full_sm_r_valid_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000AAAAAA08))
S_AXI_MUX_SEL1 (
.I0 (present_state_FSM_FFd1_13),
.I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (S_AXI_RREADY),
.I3 (present_state_FSM_FFd2_14),
.I4 (gaxi_full_sm_outstanding_read_r_15),
.I5 (1'b0),
.O (S_AXI_MUX_SEL)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hF3F3F755A2A2A200))
Mmux_S_AXI_RD_EN11 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 ( S_AXI_RREADY),
.I3 ( gaxi_full_sm_outstanding_read_r_15),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( S_AXI_ARVALID),
.O ( S_AXI_RD_EN)
);
beh_vlog_muxf7_v8_2 present_state_FSM_FFd1_In3 (
.I0 ( N8),
.I1 ( N9),
.S ( present_state_FSM_FFd1_13),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000005410F4F0))
present_state_FSM_FFd1_In3_F (
.I0 ( S_AXI_RREADY),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( S_AXI_ARVALID),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( 1'b0),
.O ( N8)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000072FF7272))
present_state_FSM_FFd1_In3_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N9)
);
beh_vlog_muxf7_v8_2 Mmux_gaxi_full_sm_ar_ready_c14 (
.I0 ( N10),
.I1 ( N11),
.S ( present_state_FSM_FFd1_13),
.O ( gaxi_full_sm_ar_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000FFFF88A8))
Mmux_gaxi_full_sm_ar_ready_c14_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( Mmux_gaxi_full_sm_ar_ready_c11),
.I5 ( 1'b0),
.O ( N10)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000008D008D8D))
Mmux_gaxi_full_sm_ar_ready_c14_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N11)
);
beh_vlog_muxf7_v8_2 Mmux_S_AXI_R_LAST1 (
.I0 ( N12),
.I1 ( N13),
.S ( present_state_FSM_FFd1_13),
.O ( NlwRenamedSig_OI_S_AXI_R_LAST)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000088088888))
Mmux_S_AXI_R_LAST1_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N12)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000E400E4E4))
Mmux_S_AXI_R_LAST1_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( S_AXI_R_LAST_INT),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N13)
);
endmodule
module blk_mem_axi_write_wrapper_beh_v8_2
# (
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface
parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;
parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
parameter C_WRITE_DEPTH_A = 0,
parameter C_AXI_AWADDR_WIDTH = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_WDATA_WIDTH = 32,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
// AXI OUTSTANDING WRITES
parameter C_AXI_OS_WR = 2
)
(
// AXI Global Signals
input S_ACLK,
input S_ARESETN,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,
input [8-1:0] S_AXI_AWLEN,
input [2:0] S_AXI_AWSIZE,
input [1:0] S_AXI_AWBURST,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input S_AXI_WVALID,
output S_AXI_WREADY,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,
output S_AXI_BVALID,
input S_AXI_BREADY,
// Signals for BMG interface
output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,
output S_AXI_WR_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:
((C_AXI_WDATA_WIDTH==16)?1:
((C_AXI_WDATA_WIDTH==32)?2:
((C_AXI_WDATA_WIDTH==64)?3:
((C_AXI_WDATA_WIDTH==128)?4:
((C_AXI_WDATA_WIDTH==256)?5:0))))));
wire bvalid_c ;
reg bready_timeout_c = 0;
wire [1:0] bvalid_rd_cnt_c;
reg bvalid_r = 0;
reg [2:0] bvalid_count_r = 0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;
reg [1:0] bvalid_wr_cnt_r = 0;
reg [1:0] bvalid_rd_cnt_r = 0;
wire w_last_c ;
wire addr_en_c ;
wire incr_addr_c ;
wire aw_ready_r ;
wire dec_alen_c ;
reg bvalid_d1_c = 0;
reg [7:0] awlen_cntr_r = 0;
reg [7:0] awlen_int = 0;
reg [1:0] awburst_int = 0;
integer total_bytes = 0;
integer wrap_boundary = 0;
integer wrap_base_addr = 0;
integer num_of_bytes_c = 0;
integer num_of_bytes_r = 0;
// Array to store BIDs
reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;
wire S_AXI_BVALID_axi_wr_fsm;
//-------------------------------------
//AXI WRITE FSM COMPONENT INSTANTIATION
//-------------------------------------
write_netlist_v8_2 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm
(
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
.S_AXI_AWVALID(S_AXI_AWVALID),
.aw_ready_r(aw_ready_r),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_WR_EN(S_AXI_WR_EN),
.w_last_c(w_last_c),
.bready_timeout_c(bready_timeout_c),
.addr_en_c(addr_en_c),
.incr_addr_c(incr_addr_c),
.bvalid_c(bvalid_c),
.S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm)
);
//Wrap Address boundary calculation
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);
total_bytes = (num_of_bytes_r)*(awlen_int+1);
wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);
wrap_boundary = wrap_base_addr+total_bytes;
end
//-------------------------------------------------------------------------
// BMG address generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awaddr_reg <= 0;
num_of_bytes_r <= 0;
awburst_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);
end else if (incr_addr_c == 1'b1) begin
if (awburst_int == 2'b10) begin
if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin
awaddr_reg <= wrap_base_addr;
end else begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end
end
end
assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);
//-------------------------------------------------------------------------
// AXI wlast generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awlen_cntr_r <= 0;
awlen_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
end else if (dec_alen_c == 1'b1) begin
awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;
end
end
end
assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;
assign dec_alen_c = (incr_addr_c | w_last_c);
//-------------------------------------------------------------------------
// Generation of bvalid counter for outstanding transactions
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_count_r <= 0;
end else begin
// bvalid_count_r generation
if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;
end else if (bvalid_c == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;
end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;
end
end
end
//-------------------------------------------------------------------------
// Generation of bvalid when BID is used
//-------------------------------------------------------------------------
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
bvalid_d1_c <= 0;
end else begin
// Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
//external bvalid signal generation
if (bvalid_d1_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of bvalid when BID is not used
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
end else begin
//external bvalid signal generation
if (bvalid_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of Bready timeout
//-------------------------------------------------------------------------
always @(bvalid_count_r) begin
// bready_timeout_c generation
if(bvalid_count_r == C_AXI_OS_WR-1) begin
bready_timeout_c <= 1'b1;
end else begin
bready_timeout_c <= 1'b0;
end
end
//-------------------------------------------------------------------------
// Generation of BID
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_wr_cnt_r <= 0;
bvalid_rd_cnt_r <= 0;
end else begin
// STORE AWID IN AN ARRAY
if(bvalid_c == 1'b1) begin
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;
end
// generate BID FROM AWID ARRAY
bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;
S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];
end
end
assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;
//-------------------------------------------------------------------------
// Storing AWID for generation of BID
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if(S_ARESETN == 1'b1) begin
axi_bid_array[0] = 0;
axi_bid_array[1] = 0;
axi_bid_array[2] = 0;
axi_bid_array[3] = 0;
end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin
axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;
end
end
end
endgenerate
assign S_AXI_BVALID = bvalid_r;
assign S_AXI_AWREADY = aw_ready_r;
endmodule
module blk_mem_axi_read_wrapper_beh_v8_2
# (
//// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_WRITE_WIDTH_A = 4,
parameter C_WRITE_DEPTH_A = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_PIPELINE_STAGES = 0,
parameter C_AXI_ARADDR_WIDTH = 12,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_ADDRB_WIDTH = 12
)
(
//// AXI Global Signals
input S_ACLK,
input S_ARESETN,
//// AXI Full/Lite Slave Read (Read side)
input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,
input [7:0] S_AXI_ARLEN,
input [2:0] S_AXI_ARSIZE,
input [1:0] S_AXI_ARBURST,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output S_AXI_RLAST,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,
//// AXI Full/Lite Read Address Signals to BRAM
output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,
output S_AXI_RD_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:
((C_WRITE_WIDTH_A==16)?1:
((C_WRITE_WIDTH_A==32)?2:
((C_WRITE_WIDTH_A==64)?3:
((C_WRITE_WIDTH_A==128)?4:
((C_WRITE_WIDTH_A==256)?5:0))))));
reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;
wire addr_en_c;
wire rd_en_c;
wire incr_addr_c;
wire single_trans_c;
wire dec_alen_c;
wire mux_sel_c;
wire r_last_c;
wire r_last_int_c;
wire [C_ADDRB_WIDTH-1 : 0] araddr_out;
reg [7:0] arlen_int_r=0;
reg [7:0] arlen_cntr=8'h01;
reg [1:0] arburst_int_c=0;
reg [1:0] arburst_int_r=0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;
integer num_of_bytes_c = 0;
integer total_bytes = 0;
integer num_of_bytes_r = 0;
integer wrap_base_addr_r = 0;
integer wrap_boundary_r = 0;
reg [7:0] arlen_int_c=0;
integer total_bytes_c = 0;
integer wrap_base_addr_c = 0;
integer wrap_boundary_c = 0;
assign dec_alen_c = incr_addr_c | r_last_int_c;
read_netlist_v8_2
#(.C_AXI_TYPE (1),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_read_fsm (
.S_AXI_INCR_ADDR(incr_addr_c),
.S_AXI_ADDR_EN(addr_en_c),
.S_AXI_SINGLE_TRANS(single_trans_c),
.S_AXI_MUX_SEL(mux_sel_c),
.S_AXI_R_LAST(r_last_c),
.S_AXI_R_LAST_INT(r_last_int_c),
//// AXI Global Signals
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
//// AXI Full/Lite Slave Read (Read side)
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
//// AXI Full/Lite Read Address Signals to BRAM
.S_AXI_RD_EN(rd_en_c)
);
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);
total_bytes = (num_of_bytes_r)*(arlen_int_r+1);
wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);
wrap_boundary_r = wrap_base_addr_r+total_bytes;
//////// combinatorial from interface
arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);
total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);
wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);
wrap_boundary_c = wrap_base_addr_c+total_bytes_c;
arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);
end
////-------------------------------------------------------------------------
//// BMG address generation
////-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
araddr_reg <= 0;
arburst_int_r <= 0;
num_of_bytes_r <= 0;
end else begin
if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
if (arburst_int_c == 2'b10) begin
if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin
araddr_reg <= wrap_base_addr_c;
end else begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (addr_en_c == 1'b1) begin
araddr_reg <= S_AXI_ARADDR;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
end else if (incr_addr_c == 1'b1) begin
if (arburst_int_r == 2'b10) begin
if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin
araddr_reg <= wrap_base_addr_r;
end else begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end
end
end
assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);
////-----------------------------------------------------------------------
//// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
////-----------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
arlen_cntr <= 8'h01;
arlen_int_r <= 0;
end else begin
if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= S_AXI_ARLEN - 1'b1;
end else if (addr_en_c == 1'b1) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
end else if (dec_alen_c == 1'b1) begin
arlen_cntr <= arlen_cntr - 1'b1 ;
end
else begin
arlen_cntr <= arlen_cntr;
end
end
end
assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;
////------------------------------------------------------------------------
//// AXI FULL FSM
//// Mux Selection of ARADDR
//// ARADDR is driven out from the read fsm based on the mux_sel_c
//// Based on mux_sel either ARADDR is given out or the latched ARADDR is
//// given out to BRAM
////------------------------------------------------------------------------
assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;
////------------------------------------------------------------------------
//// Assign output signals - AXI FULL FSM
////------------------------------------------------------------------------
assign S_AXI_RD_EN = rd_en_c;
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
S_AXI_RID <= 0;
ar_id_r <= 0;
end else begin
if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin
ar_id_r <= S_AXI_ARID;
end else if (rd_en_c == 1'b1) begin
S_AXI_RID <= ar_id_r;
end
end
end
end
endgenerate
endmodule
module blk_mem_axi_regs_fwd_v8_2
#(parameter C_DATA_WIDTH = 8
)(
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1 ) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
//*****************************************************************************
// Output Register Stage module
//
// This module builds the output register stages of the memory. This module is
// instantiated in the main memory module (BLK_MEM_GEN_v8_2) which is
// declared/implemented further down in this file.
//*****************************************************************************
module BLK_MEM_GEN_v8_2_output_stage
#(parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RST = 0,
parameter C_RSTRAM = 0,
parameter C_RST_PRIORITY = "CE",
parameter C_INIT_VAL = "0",
parameter C_HAS_EN = 0,
parameter C_HAS_REGCE = 0,
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_MEM_OUTPUT_REGS = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter NUM_STAGES = 1,
parameter C_EN_ECC_PIPE = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input RST,
input EN,
input REGCE,
input [C_DATA_WIDTH-1:0] DIN_I,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN_I,
input DBITERR_IN_I,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I,
input ECCPIPECE,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RST : Determines the presence of the RST port
// C_RSTRAM : Determines if special reset behavior is used
// C_RST_PRIORITY : Determines the priority between CE and SR
// C_INIT_VAL : Initialization value
// C_HAS_EN : Determines the presence of the EN port
// C_HAS_REGCE : Determines the presence of the REGCE port
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// NUM_STAGES : Determines the number of output stages
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// RST : Reset input to reset memory outputs to a user-defined
// reset state
// EN : Enable all read and write operations
// REGCE : Register Clock Enable to control each pipeline output
// register stages
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
// Fix for CR-509792
localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;
// Declare the pipeline registers
// (includes mem output reg, mux pipeline stages, and mux output reg)
reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;
reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;
reg [REG_STAGES-1:0] sbiterr_regs;
reg [REG_STAGES-1:0] dbiterr_regs;
reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;
reg [C_DATA_WIDTH-1:0] init_val ;
//*********************************************
// Wire off optional inputs based on parameters
//*********************************************
wire en_i;
wire regce_i;
wire rst_i;
// Internal signals
reg [C_DATA_WIDTH-1:0] DIN;
reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN;
reg SBITERR_IN;
reg DBITERR_IN;
// Internal enable for output registers is tied to user EN or '1' depending
// on parameters
assign en_i = (C_HAS_EN==0 || EN);
// Internal register enable for output registers is tied to user REGCE, EN or
// '1' depending on parameters
// For V4 ECC, REGCE is always 1
// Virtex-4 ECC Not Yet Supported
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
//Internal SRR is tied to user RST or '0' depending on parameters
assign rst_i = (C_HAS_RST==1) && RST;
//****************************************************
// Power on: load up the output registers and latches
//****************************************************
initial begin
if (!($sscanf(init_str, "%h", init_val))) begin
init_val = 0;
end
DOUT = init_val;
RDADDRECC = 0;
SBITERR = 1'b0;
DBITERR = 1'b0;
DIN = {(C_DATA_WIDTH){1'b0}};
RDADDRECC_IN = 0;
SBITERR_IN = 0;
DBITERR_IN = 0;
// This will be one wider than need, but 0 is an error
out_regs = {(REG_STAGES+1){init_val}};
rdaddrecc_regs = 0;
sbiterr_regs = {(REG_STAGES+1){1'b0}};
dbiterr_regs = {(REG_STAGES+1){1'b0}};
end
//***********************************************
// NUM_STAGES = 0 (No output registers. RAM only)
//***********************************************
generate if (NUM_STAGES == 0) begin : zero_stages
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg
always @* begin
DIN = DIN_I;
SBITERR_IN = SBITERR_IN_I;
DBITERR_IN = DBITERR_IN_I;
RDADDRECC_IN = RDADDRECC_IN_I;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg
always @(posedge CLK) begin
if(ECCPIPECE == 1) begin
DIN <= #FLOP_DELAY DIN_I;
SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;
DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;
RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;
end
end
end
endgenerate
//***********************************************
// NUM_STAGES = 1
// (Mem Output Reg only or Mux Output Reg only)
//***********************************************
// Possible valid combinations:
// Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
// +-----------------------------------------+
// | C_RSTRAM_* | Reset Behavior |
// +----------------+------------------------+
// | 0 | Normal Behavior |
// +----------------+------------------------+
// | 1 | Special Behavior |
// +----------------+------------------------+
//
// Normal = REGCE gates reset, as in the case of all families except S3ADSP.
// Special = EN gates reset, as in the case of S3ADSP.
generate if (NUM_STAGES == 1 &&
(C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) ||
C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))
begin : one_stages_norm
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end //end Priority conditions
end //end RST Type conditions
end //end one_stages_norm generate statement
endgenerate
// Special Reset Behavior for S3ADSP
generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp"))
begin : one_stage_splbhv
always @(posedge CLK) begin
if (en_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
end else if (regce_i && !rst_i) begin
DOUT <= #FLOP_DELAY DIN;
end //Output signal assignments
end //end CLK
end //end one_stage_splbhv generate statement
endgenerate
//************************************************************
// NUM_STAGES > 1
// Mem Output Reg + Mux Output Reg
// or
// Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
// or
// Mux Pipeline Stages (>0) + Mux Output Reg
//*************************************************************
generate if (NUM_STAGES > 1) begin : multi_stage
//Asynchronous Reset
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end //end Priority conditions
// Shift the data through the output stages
if (en_i) begin
out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;
rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;
sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;
dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;
end
end //end CLK
end //end multi_stage generate statement
endgenerate
endmodule
module BLK_MEM_GEN_v8_2_softecc_output_reg_stage
#(parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
//*****************************************************************************
// Main Memory module
//
// This module is the top-level behavioral model and this implements the RAM
//*****************************************************************************
module BLK_MEM_GEN_v8_2_mem_module
#(parameter C_CORENAME = "blk_mem_gen_v8_2",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter FLOP_DELAY = 100,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input CLKA,
input RSTA,
input ENA,
input REGCEA,
input [C_WEA_WIDTH-1:0] WEA,
input [C_ADDRA_WIDTH-1:0] ADDRA,
input [C_WRITE_WIDTH_A-1:0] DINA,
output [C_READ_WIDTH_A-1:0] DOUTA,
input CLKB,
input RSTB,
input ENB,
input REGCEB,
input [C_WEB_WIDTH-1:0] WEB,
input [C_ADDRB_WIDTH-1:0] ADDRB,
input [C_WRITE_WIDTH_B-1:0] DINB,
output [C_READ_WIDTH_B-1:0] DOUTB,
input INJECTSBITERR,
input INJECTDBITERR,
input ECCPIPECE,
input SLEEP,
output SBITERR,
output DBITERR,
output [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_2" and it is
// only used by this module to print warning messages. It is neither passed
// down from blk_mem_gen_v8_2_xst.v nor present in the instantiation template
// coregen generates
//***************************************************************************
// constants for the core behavior
//***************************************************************************
// file handles for logging
//--------------------------------------------------
localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range
localparam COLLFILE = 32'h8000_0001; //stdout for coll detection
localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors
// other constants
//--------------------------------------------------
localparam COLL_DELAY = 100; // 100 ps
// locally derived parameters to determine memory shape
//-----------------------------------------------------
localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0)))));
localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?
C_WRITE_WIDTH_A : C_READ_WIDTH_A;
localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?
C_WRITE_WIDTH_B : C_READ_WIDTH_B;
localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?
MIN_WIDTH_A : MIN_WIDTH_B;
localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?
C_WRITE_DEPTH_A : C_READ_DEPTH_A;
localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?
C_WRITE_DEPTH_B : C_READ_DEPTH_B;
localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?
MAX_DEPTH_A : MAX_DEPTH_B;
// locally derived parameters to assist memory access
//----------------------------------------------------
// Calculate the width ratios of each port with respect to the narrowest
// port
localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;
localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH;
localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;
localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH;
// To modify the LSBs of the 'wider' data to the actual
// address value
//----------------------------------------------------
localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A;
localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A;
localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B;
localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B;
// If byte writes aren't being used, make sure BYTE_SIZE is not
// wider than the memory elements to avoid compilation warnings
localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;
// The memory
reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1];
reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1];
reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;
// ECC error arrays
reg sbiterr_arr [0:MAX_DEPTH-1];
reg dbiterr_arr [0:MAX_DEPTH-1];
reg softecc_sbiterr_arr [0:MAX_DEPTH-1];
reg softecc_dbiterr_arr [0:MAX_DEPTH-1];
// Memory output 'latches'
reg [C_READ_WIDTH_A-1:0] memory_out_a;
reg [C_READ_WIDTH_B-1:0] memory_out_b;
// ECC error inputs and outputs from output_stage module:
reg sbiterr_in;
wire sbiterr_sdp;
reg dbiterr_in;
wire dbiterr_sdp;
wire [C_READ_WIDTH_B-1:0] dout_i;
wire dbiterr_i;
wire sbiterr_i;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp;
// Reset values
reg [C_READ_WIDTH_A-1:0] inita_val;
reg [C_READ_WIDTH_B-1:0] initb_val;
// Collision detect
reg is_collision;
reg is_collision_a, is_collision_delay_a;
reg is_collision_b, is_collision_delay_b;
// Temporary variables for initialization
//---------------------------------------
integer status;
integer initfile;
integer meminitfile;
// data input buffer
reg [C_WRITE_WIDTH_A-1:0] mif_data;
reg [C_WRITE_WIDTH_A-1:0] mem_data;
// string values in hex
reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL;
reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL;
reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA;
// initialization filename
reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME;
reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE;
//Constants used to calculate the effective address widths for each of the
//four ports.
integer cnt = 1;
integer write_addr_a_width, read_addr_a_width;
integer write_addr_b_width, read_addr_b_width;
localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY))))))))))))))))));
// Internal configuration parameters
//---------------------------------------------
localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);
localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4);
localparam HAS_A_WRITE = (!IS_ROM);
localparam HAS_B_WRITE = (C_MEM_TYPE==2);
localparam HAS_A_READ = (C_MEM_TYPE!=1);
localparam HAS_B_READ = (!SINGLE_PORT);
localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE);
// Calculate the mux pipeline register stages for Port A and Port B
//------------------------------------------------------------------
localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?
C_MUX_PIPELINE_STAGES : 0;
localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?
C_MUX_PIPELINE_STAGES : 0;
// Calculate total number of register stages in the core
// -----------------------------------------------------
localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);
localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);
wire ena_i;
wire enb_i;
wire reseta_i;
wire resetb_i;
wire [C_WEA_WIDTH-1:0] wea_i;
wire [C_WEB_WIDTH-1:0] web_i;
wire rea_i;
wire reb_i;
wire rsta_outp_stage;
wire rstb_outp_stage;
// ECC SBITERR/DBITERR Outputs
// The ECC Behavior is modeled by the behavioral models only for Virtex-6.
// For Virtex-5, these outputs will be tied to 0.
assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;
assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;
assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;
// This effectively wires off optional inputs
assign ena_i = (C_HAS_ENA==0) || ENA;
assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;
assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;
assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;
assign rea_i = (HAS_A_READ) ? ena_i : 'b0;
assign reb_i = (HAS_B_READ) ? enb_i : 'b0;
// These signals reset the memory latches
assign reseta_i =
((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||
(C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));
assign resetb_i =
((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||
(C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));
// Tasks to access the memory
//---------------------------
//**************
// write_a
//**************
task write_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg [C_WEA_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_A-1:0] data,
input inj_sbiterr,
input inj_dbiterr);
reg [C_WRITE_WIDTH_A-1:0] current_contents;
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_A_DIV);
if (address >= C_WRITE_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEA) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_A + i];
end
end
// Apply incoming bytes
if (C_WEA_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Insert double bit errors:
if (C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
current_contents[0] = !(current_contents[0]);
current_contents[1] = !(current_contents[1]);
end
end
// Insert softecc double bit errors:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];
doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];
doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];
current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];
end
end
// Write data to memory
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_A] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_A + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
// Store the address at which error is injected:
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
sbiterr_arr[addr] = 1;
end else begin
sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
dbiterr_arr[addr] = 1;
end else begin
dbiterr_arr[addr] = 0;
end
end
// Store the address at which softecc error is injected:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
softecc_sbiterr_arr[addr] = 1;
end else begin
softecc_sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
softecc_dbiterr_arr[addr] = 1;
end else begin
softecc_dbiterr_arr[addr] = 0;
end
end
end
end
endtask
//**************
// write_b
//**************
task write_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg [C_WEB_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_B-1:0] data);
reg [C_WRITE_WIDTH_B-1:0] current_contents;
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_B_DIV);
if (address >= C_WRITE_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEB) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_B + i];
end
end
// Apply incoming bytes
if (C_WEB_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Write data to memory
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_B] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_B + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
end
end
endtask
//**************
// read_a
//**************
task read_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_a <= #FLOP_DELAY inita_val;
end else begin
// Shift the address by the ratio
address = (addr/READ_ADDR_A_DIV);
if (address >= C_READ_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Read",
C_CORENAME, addr);
end
memory_out_a <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_A==1) begin
memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin
memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];
end
end //end READ_WIDTH_RATIO_A==1 loop
end //end valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// read_b
//**************
task read_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_b <= #FLOP_DELAY initb_val;
sbiterr_in <= #FLOP_DELAY 1'b0;
dbiterr_in <= #FLOP_DELAY 1'b0;
rdaddrecc_in <= #FLOP_DELAY 0;
end else begin
// Shift the address
address = (addr/READ_ADDR_B_DIV);
if (address >= C_READ_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Read",
C_CORENAME, addr);
end
memory_out_b <= #FLOP_DELAY 'bX;
sbiterr_in <= #FLOP_DELAY 1'bX;
dbiterr_in <= #FLOP_DELAY 1'bX;
rdaddrecc_in <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_B==1) begin
memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin
memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];
end
end
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else if (C_USE_SOFTECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (softecc_sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (softecc_dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else begin
rdaddrecc_in <= #FLOP_DELAY 0;
dbiterr_in <= #FLOP_DELAY 1'b0;
sbiterr_in <= #FLOP_DELAY 1'b0;
end //end SOFTECC Loop
end //end Valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// reset_a
//**************
task reset_a (input reg reset);
begin
if (reset) memory_out_a <= #FLOP_DELAY inita_val;
end
endtask
//**************
// reset_b
//**************
task reset_b (input reg reset);
begin
if (reset) memory_out_b <= #FLOP_DELAY initb_val;
end
endtask
//**************
// init_memory
//**************
task init_memory;
integer i, j, addr_step;
integer status;
reg [C_WRITE_WIDTH_A-1:0] default_data;
begin
default_data = 0;
//Display output message indicating that the behavioral model is being
//initialized
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data...");
// Convert the default to hex
if (C_USE_DEFAULT_DATA) begin
if (default_data_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME);
$finish;
end else begin
status = $sscanf(default_data_str, "%h", default_data);
if (status == 0) begin
$fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read",
"from C_DEFAULT_DATA: %0s"},
C_CORENAME, C_DEFAULT_DATA);
$finish;
end
end
end
// Step by WRITE_ADDR_A_DIV through the memory via the
// Port A write interface to hit every location once
addr_step = WRITE_ADDR_A_DIV;
// 'write' to every location with default (or 0)
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);
end
// Get specialized data from the MIF file
if (C_LOAD_INIT_FILE) begin
if (init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!",
C_CORENAME);
$finish;
end else begin
initfile = $fopen(init_file_str, "r");
if (initfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE_NAME: %0s!"},
C_CORENAME, init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
status = $fscanf(initfile, "%b", mif_data);
if (status > 0) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);
end
end
$fclose(initfile);
end //initfile
end //init_file_str
end //C_LOAD_INIT_FILE
if (C_USE_BRAM_BLOCK) begin
// Get specialized data from the MIF file
if (C_INIT_FILE != "NONE") begin
if (mem_init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!",
C_CORENAME);
$finish;
end else begin
meminitfile = $fopen(mem_init_file_str, "r");
if (meminitfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE: %0s!"},
C_CORENAME, mem_init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
$readmemh(mem_init_file_str, memory );
for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin
end
$fclose(meminitfile);
end //meminitfile
end //mem_init_file_str
end //C_INIT_FILE
end //C_USE_BRAM_BLOCK
//Display output message indicating that the behavioral model is done
//initializing
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE)
$display(" Block Memory Generator data initialization complete.");
end
endtask
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//*******************
// collision_check
//*******************
function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,
input integer iswrite_a,
input reg [C_ADDRB_WIDTH-1:0] addr_b,
input integer iswrite_b);
reg c_aw_bw, c_aw_br, c_ar_bw;
integer scaled_addra_to_waddrb_width;
integer scaled_addrb_to_waddrb_width;
integer scaled_addra_to_waddra_width;
integer scaled_addrb_to_waddra_width;
integer scaled_addra_to_raddrb_width;
integer scaled_addrb_to_raddrb_width;
integer scaled_addra_to_raddra_width;
integer scaled_addrb_to_raddra_width;
begin
c_aw_bw = 0;
c_aw_br = 0;
c_ar_bw = 0;
//If write_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_b_width. Once both are scaled to
//write_addr_b_width, compare.
scaled_addra_to_waddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_b_width));
scaled_addrb_to_waddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_b_width));
//If write_addr_a_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_a_width. Once both are scaled to
//write_addr_a_width, compare.
scaled_addra_to_waddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_a_width));
scaled_addrb_to_waddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_a_width));
//If read_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_b_width. Once both are scaled to
//read_addr_b_width, compare.
scaled_addra_to_raddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_b_width));
scaled_addrb_to_raddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_b_width));
//If read_addr_a_width is smaller, scale both addresses to that width for
//comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_a_width. Once both are scaled to
//read_addr_a_width, compare.
scaled_addra_to_raddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_a_width));
scaled_addrb_to_raddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_a_width));
//Look for a write-write collision. In order for a write-write
//collision to exist, both ports must have a write transaction.
if (iswrite_a && iswrite_b) begin
if (write_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end //width
end //iswrite_a and iswrite_b
//If the B port is reading (which means it is enabled - so could be
//a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
//to asymmetric write/read ports.
if (iswrite_a) begin
if (write_addr_a_width > read_addr_b_width) begin
if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end //width
end //iswrite_a
//If the A port is reading (which means it is enabled - so could be
// a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
// to asymmetric write/read ports.
if (iswrite_b) begin
if (read_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end else begin
if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end //width
end //iswrite_b
collision_check = c_aw_bw | c_aw_br | c_ar_bw;
end
endfunction
//*******************************
// power on values
//*******************************
initial begin
// Load up the memory
init_memory;
// Load up the output registers and latches
if ($sscanf(inita_str, "%h", inita_val)) begin
memory_out_a = inita_val;
end else begin
memory_out_a = 0;
end
if ($sscanf(initb_str, "%h", initb_val)) begin
memory_out_b = initb_val;
end else begin
memory_out_b = 0;
end
sbiterr_in = 1'b0;
dbiterr_in = 1'b0;
rdaddrecc_in = 0;
// Determine the effective address widths for each of the 4 ports
write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);
write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);
$display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.");
end
//***************************************************************************
// These are the main blocks which schedule read and write operations
// Note that the reset priority feature at the latch stage is only supported
// for Spartan-6. For other families, the default priority at the latch stage
// is "CE"
//***************************************************************************
// Synchronous clocks: schedule port operations with respect to
// both write operating modes
generate
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_wf_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_rf_wf
always @(posedge CLKA) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_wf_rf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_rf_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_wf_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_rf_nc
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_nc_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_nc_rf
always @(posedge CLKA) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_nc_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK) begin: com_clk_sched_default
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
endgenerate
// Asynchronous clocks: port operation is independent
generate
if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
end
end
endgenerate
generate
if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf
always @(posedge CLKB) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
endgenerate
//***************************************************************
// Instantiate the variable depth output register stage module
//***************************************************************
// Port A
assign rsta_outp_stage = RSTA & (~SLEEP);
BLK_MEM_GEN_v8_2_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTA),
.C_RSTRAM (C_RSTRAM_A),
.C_RST_PRIORITY (C_RST_PRIORITY_A),
.C_INIT_VAL (C_INITA_VAL),
.C_HAS_EN (C_HAS_ENA),
.C_HAS_REGCE (C_HAS_REGCEA),
.C_DATA_WIDTH (C_READ_WIDTH_A),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_A),
.C_EN_ECC_PIPE (0),
.FLOP_DELAY (FLOP_DELAY))
reg_a
(.CLK (CLKA),
.RST (rsta_outp_stage),//(RSTA),
.EN (ENA),
.REGCE (REGCEA),
.DIN_I (memory_out_a),
.DOUT (DOUTA),
.SBITERR_IN_I (1'b0),
.DBITERR_IN_I (1'b0),
.SBITERR (),
.DBITERR (),
.RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),
.ECCPIPECE (1'b0),
.RDADDRECC ()
);
assign rstb_outp_stage = RSTB & (~SLEEP);
// Port B
BLK_MEM_GEN_v8_2_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTB),
.C_RSTRAM (C_RSTRAM_B),
.C_RST_PRIORITY (C_RST_PRIORITY_B),
.C_INIT_VAL (C_INITB_VAL),
.C_HAS_EN (C_HAS_ENB),
.C_HAS_REGCE (C_HAS_REGCEB),
.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_B),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.FLOP_DELAY (FLOP_DELAY))
reg_b
(.CLK (CLKB),
.RST (rstb_outp_stage),//(RSTB),
.EN (ENB),
.REGCE (REGCEB),
.DIN_I (memory_out_b),
.DOUT (dout_i),
.SBITERR_IN_I (sbiterr_in),
.DBITERR_IN_I (dbiterr_in),
.SBITERR (sbiterr_i),
.DBITERR (dbiterr_i),
.RDADDRECC_IN_I (rdaddrecc_in),
.ECCPIPECE (ECCPIPECE),
.RDADDRECC (rdaddrecc_i)
);
//***************************************************************
// Instantiate the Input and Output register stages
//***************************************************************
BLK_MEM_GEN_v8_2_softecc_output_reg_stage
#(.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.FLOP_DELAY (FLOP_DELAY))
has_softecc_output_reg_stage
(.CLK (CLKB),
.DIN (dout_i),
.DOUT (DOUTB),
.SBITERR_IN (sbiterr_i),
.DBITERR_IN (dbiterr_i),
.SBITERR (sbiterr_sdp),
.DBITERR (dbiterr_sdp),
.RDADDRECC_IN (rdaddrecc_i),
.RDADDRECC (rdaddrecc_sdp)
);
//****************************************************
// Synchronous collision checks
//****************************************************
// CR 780544 : To make verilog model's collison warnings in consistant with
// vhdl model, the non-blocking assignments are replaced with blocking
// assignments.
generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision = 0;
end
end else begin
is_collision = 0;
end
// If the write port is in READ_FIRST mode, there is no collision
if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
is_collision = 0;
end
if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
is_collision = 0;
end
// Only flag if one of the accesses is a write
if (is_collision && (wea_i || web_i)) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n",
wea_i ? "write" : "read", ADDRA,
web_i ? "write" : "read", ADDRB);
end
end
//****************************************************
// Asynchronous collision checks
//****************************************************
end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
// Delay A and B addresses in order to mimic setup/hold times
wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;
wire [0:0] #COLL_DELAY wea_delay = wea_i;
wire #COLL_DELAY ena_delay = ena_i;
wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;
wire [0:0] #COLL_DELAY web_delay = web_i;
wire #COLL_DELAY enb_delay = enb_i;
// Do the checks w/rt A
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_a = 0;
end
end else begin
is_collision_a = 0;
end
if (ena_i && enb_delay) begin
if(wea_i || web_delay) begin
is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,
web_delay);
end else begin
is_collision_delay_a = 0;
end
end else begin
is_collision_delay_a = 0;
end
// Only flag if B access is a write
if (is_collision_a && web_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, ADDRB);
end else if (is_collision_delay_a && web_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, addrb_delay);
end
end
// Do the checks w/rt B
always @(posedge CLKB) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_b = 0;
end
end else begin
is_collision_b = 0;
end
if (ena_delay && enb_i) begin
if (wea_delay || web_i) begin
is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,
web_i);
end else begin
is_collision_delay_b = 0;
end
end else begin
is_collision_delay_b = 0;
end
// Only flag if A access is a write
if (is_collision_b && wea_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
ADDRA, web_i ? "write" : "read", ADDRB);
end else if (is_collision_delay_b && wea_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
addra_delay, web_i ? "write" : "read", ADDRB);
end
end
end
endgenerate
endmodule
//*****************************************************************************
// Top module wraps Input register and Memory module
//
// This module is the top-level behavioral model and this implements the memory
// module and the input registers
//*****************************************************************************
module blk_mem_gen_v8_2
#(parameter C_CORENAME = "blk_mem_gen_v8_2",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_ELABORATION_DIR = "",
parameter C_INTERFACE_TYPE = 0,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_CTRL_ECC_ALGO = "NONE",
parameter C_ENABLE_32BIT_ADDRESS = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
//parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_SLEEP_PIN = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0,
parameter C_COUNT_36K_BRAM = "",
parameter C_COUNT_18K_BRAM = "",
parameter C_EST_POWER_SUMMARY = ""
)
(input clka,
input rsta,
input ena,
input regcea,
input [C_WEA_WIDTH-1:0] wea,
input [C_ADDRA_WIDTH-1:0] addra,
input [C_WRITE_WIDTH_A-1:0] dina,
output [C_READ_WIDTH_A-1:0] douta,
input clkb,
input rstb,
input enb,
input regceb,
input [C_WEB_WIDTH-1:0] web,
input [C_ADDRB_WIDTH-1:0] addrb,
input [C_WRITE_WIDTH_B-1:0] dinb,
output [C_READ_WIDTH_B-1:0] doutb,
input injectsbiterr,
input injectdbiterr,
output sbiterr,
output dbiterr,
output [C_ADDRB_WIDTH-1:0] rdaddrecc,
input eccpipece,
input sleep,
//AXI BMG Input and Output Port Declarations
//AXI Global Signals
input s_aclk,
input s_aresetn,
//AXI Full/lite slave write (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awvalid,
output s_axi_awready,
input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,
input [C_WEA_WIDTH-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
//AXI Full/lite slave read (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
input s_axi_rready,
//AXI Full/lite sideband signals
input s_axi_injectsbiterr,
input s_axi_injectdbiterr,
output s_axi_sbiterr,
output s_axi_dbiterr,
output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_HAS_SOFTECC_INPUT_REGS_A :
// C_HAS_SOFTECC_OUTPUT_REGS_B :
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
wire SBITERR;
wire DBITERR;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire S_AXI_BVALID;
wire S_AXI_ARREADY;
wire S_AXI_RLAST;
wire S_AXI_RVALID;
wire S_AXI_SBITERR;
wire S_AXI_DBITERR;
wire [C_WEA_WIDTH-1:0] WEA = wea;
wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;
wire [C_WRITE_WIDTH_A-1:0] DINA = dina;
wire [C_READ_WIDTH_A-1:0] DOUTA;
wire [C_WEB_WIDTH-1:0] WEB = web;
wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;
wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;
wire [C_READ_WIDTH_B-1:0] DOUTB;
wire [C_ADDRB_WIDTH-1:0] RDADDRECC;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;
wire [31:0] S_AXI_AWADDR = s_axi_awaddr;
wire [7:0] S_AXI_AWLEN = s_axi_awlen;
wire [2:0] S_AXI_AWSIZE = s_axi_awsize;
wire [1:0] S_AXI_AWBURST = s_axi_awburst;
wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;
wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [1:0] S_AXI_BRESP;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;
wire [31:0] S_AXI_ARADDR = s_axi_araddr;
wire [7:0] S_AXI_ARLEN = s_axi_arlen;
wire [2:0] S_AXI_ARSIZE = s_axi_arsize;
wire [1:0] S_AXI_ARBURST = s_axi_arburst;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;
// Added to fix the simulation warning #CR731605
wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;
wire ECCPIPECE;
wire SLEEP;
assign CLKA = clka;
assign RSTA = rsta;
assign ENA = ena;
assign REGCEA = regcea;
assign CLKB = clkb;
assign RSTB = rstb;
assign ENB = enb;
assign REGCEB = regceb;
assign INJECTSBITERR = injectsbiterr;
assign INJECTDBITERR = injectdbiterr;
assign ECCPIPECE = eccpipece;
assign SLEEP = sleep;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;
assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;
assign s_axi_sbiterr = S_AXI_SBITERR;
assign s_axi_dbiterr = S_AXI_DBITERR;
assign doutb = DOUTB;
assign douta = DOUTA;
assign rdaddrecc = RDADDRECC;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_rdaddrecc = S_AXI_RDADDRECC;
localparam FLOP_DELAY = 100; // 100 ps
reg injectsbiterr_in;
reg injectdbiterr_in;
reg rsta_in;
reg ena_in;
reg regcea_in;
reg [C_WEA_WIDTH-1:0] wea_in;
reg [C_ADDRA_WIDTH-1:0] addra_in;
reg [C_WRITE_WIDTH_A-1:0] dina_in;
wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;
wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;
wire s_axi_wr_en_c;
wire s_axi_rd_en_c;
wire s_aresetn_a_c;
wire [7:0] s_axi_arlen_c ;
wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;
wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;
wire [1:0] s_axi_rresp_c;
wire s_axi_rlast_c;
wire s_axi_rvalid_c;
wire s_axi_rready_c;
wire regceb_c;
localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;
wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;
wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//**************
// log2int
//**************
function integer log2int (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
cnt= data_value;
for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin
width = width + 1;
end //loop
log2int = width;
end //log2int
endfunction
//**************************************************************************
// FUNCTION : divroundup
// Returns the ceiling value of the division
// Data_value - the quantity to be divided, dividend
// Divisor - the value to divide the data_value by
//**************************************************************************
function integer divroundup (input integer data_value,input integer divisor);
integer div;
begin
div = data_value/divisor;
if ((data_value % divisor) != 0) begin
div = div+1;
end //if
divroundup = div;
end //if
endfunction
localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);
localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;
//Data Width Number of LSB address bits to be discarded
//1 to 16 1
//17 to 32 2
//33 to 64 3
//65 to 128 4
//129 to 256 5
//257 to 512 6
//513 to 1024 7
// The following two constants determine this.
localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);
localparam C_AXI_OS_WR = 2;
//***********************************************
// INPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage
always @* begin
injectsbiterr_in = INJECTSBITERR;
injectdbiterr_in = INJECTDBITERR;
rsta_in = RSTA;
ena_in = ENA;
regcea_in = REGCEA;
wea_in = WEA;
addra_in = ADDRA;
dina_in = DINA;
end //end always
end //end no_softecc_input_reg_stage
endgenerate
generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage
always @(posedge CLKA) begin
injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;
injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;
rsta_in <= #FLOP_DELAY RSTA;
ena_in <= #FLOP_DELAY ENA;
regcea_in <= #FLOP_DELAY REGCEA;
wea_in <= #FLOP_DELAY WEA;
addra_in <= #FLOP_DELAY ADDRA;
dina_in <= #FLOP_DELAY DINA;
end //end always
end //end input_reg_stages generate statement
endgenerate
generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module
BLK_MEM_GEN_v8_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_ALGORITHM (C_ALGORITHM),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_2_inst
(.CLKA (CLKA),
.RSTA (rsta_in),
.ENA (ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB),
.ENB (ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module
localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);
localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);
localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
// localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);
// localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);
localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;
localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;
// Data Width Number of LSB address bits to be discarded
// 1 to 16 1
// 17 to 32 2
// 33 to 64 3
// 65 to 128 4
// 129 to 256 5
// 257 to 512 6
// 513 to 1024 7
// The following two constants determine this.
localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;
localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;
wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;
wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;
wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;
assign msb_zero_i = 0;
assign lsb_zero_i = 0;
assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};
BLK_MEM_GEN_v8_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_2_inst
(.CLKA (CLKA),
.RSTA (rsta_in),
.ENA (ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB),
.ENB (ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (rdaddrecc_i)
);
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RLAST = s_axi_rlast_c;
assign S_AXI_RVALID = s_axi_rvalid_c;
assign S_AXI_RID = s_axi_rid_c;
assign S_AXI_RRESP = s_axi_rresp_c;
assign s_axi_rready_c = S_AXI_RREADY;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb
assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb
assign regceb_c = REGCEB;
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd
blk_mem_axi_regs_fwd_v8_2
#(.C_DATA_WIDTH (C_AXI_PAYLOAD))
axi_regs_inst (
.ACLK (S_ACLK),
.ARESET (s_aresetn_a_c),
.S_VALID (s_axi_rvalid_c),
.S_READY (s_axi_rready_c),
.S_PAYLOAD_DATA (s_axi_payload_c),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY),
.M_PAYLOAD_DATA (m_axi_payload_c)
);
end
endgenerate
generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module
assign s_aresetn_a_c = !S_ARESETN;
assign S_AXI_BRESP = 2'b00;
assign s_axi_rresp_c = 2'b00;
assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;
blk_mem_axi_write_wrapper_beh_v8_2
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),
.C_AXI_OS_WR (C_AXI_OS_WR))
axi_wr_fsm (
// AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
// AXI Full/Lite Slave Write interface
.S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_BID (S_AXI_BID),
// Signals for BRAM interfac(
.S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),
.S_AXI_WR_EN (s_axi_wr_en_c)
);
blk_mem_axi_read_wrapper_beh_v8_2
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_PIPELINE_STAGES (1),
.C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_rd_sm(
//AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
//AXI Full/Lite Read Side
.S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_ARLEN (s_axi_arlen_c),
.S_AXI_ARSIZE (S_AXI_ARSIZE),
.S_AXI_ARBURST (S_AXI_ARBURST),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RLAST (s_axi_rlast_c),
.S_AXI_RVALID (s_axi_rvalid_c),
.S_AXI_RREADY (s_axi_rready_c),
.S_AXI_ARID (S_AXI_ARID),
.S_AXI_RID (s_axi_rid_c),
//AXI Full/Lite Read FSM Outputs
.S_AXI_ARADDR_OUT (s_axi_araddr_out_c),
.S_AXI_RD_EN (s_axi_rd_en_c)
);
BLK_MEM_GEN_v8_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (1),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (1),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (1),
.C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_BYTE_WEB (1),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (0),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (0),
.C_HAS_MUX_OUTPUT_REGS_B (0),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (0),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_2_inst
(.CLKA (S_ACLK),
.RSTA (s_aresetn_a_c),
.ENA (s_axi_wr_en_c),
.REGCEA (regcea_in),
.WEA (S_AXI_WSTRB),
.ADDRA (s_axi_awaddr_out_c),
.DINA (S_AXI_WDATA),
.DOUTA (DOUTA),
.CLKB (S_ACLK),
.RSTB (s_aresetn_a_c),
.ENB (s_axi_rd_en_c),
.REGCEB (regceb_c),
.WEB (WEB_parameterized),
.ADDRB (s_axi_araddr_out_c),
.DINB (DINB),
.DOUTB (s_axi_rdata_c),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.ECCPIPECE (1'b0),
.SLEEP (1'b0),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
endmodule
|
module top(
input REFERENCECLK,
output PLLOUTCORE,
output PLLOUTGLOBAL,
input EXTFEEDBACK,
input [7:0] DYNAMICDELAY,
output LOCK,
input BYPASS,
input RESETB,
input LATCHINPUTVALUE,
//Test Pins
output SDO,
input SDI,
input SCLK
);
SB_PLL40_CORE #(
.FEEDBACK_PATH("DELAY"),
// .FEEDBACK_PATH("SIMPLE"),
// .FEEDBACK_PATH("PHASE_AND_DELAY"),
// .FEEDBACK_PATH("EXTERNAL"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
// .DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC"),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
// .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"),
.PLLOUT_SELECT("GENCLK"),
// .PLLOUT_SELECT("GENCLK_HALF"),
// .PLLOUT_SELECT("SHIFTREG_90deg"),
// .PLLOUT_SELECT("SHIFTREG_0deg"),
.SHIFTREG_DIV_MODE(1'b0),
.FDA_FEEDBACK(4'b1111),
.FDA_RELATIVE(4'b1111),
.DIVR(4'b0000),
.DIVF(7'b0000000),
.DIVQ(3'b001),
.FILTER_RANGE(3'b000),
.ENABLE_ICEGATE(1'b0),
.TEST_MODE(1'b0)
) uut (
.REFERENCECLK (REFERENCECLK ),
.PLLOUTCORE (PLLOUTCORE ),
.PLLOUTGLOBAL (PLLOUTGLOBAL ),
.EXTFEEDBACK (EXTFEEDBACK ),
.DYNAMICDELAY (DYNAMICDELAY ),
.LOCK (LOCK ),
.BYPASS (BYPASS ),
.RESETB (RESETB ),
.LATCHINPUTVALUE(LATCHINPUTVALUE),
.SDO (SDO ),
.SDI (SDI ),
.SCLK (SCLK )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRBP_SYMBOL_V
`define SKY130_FD_SC_HVL__DFRBP_SYMBOL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRBP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3B_4_V
`define SKY130_FD_SC_LP__OR3B_4_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3b_4 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3b_4 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3B_4_V
|
// This is a simple example.
// You can make a your own template file and set its path to settings.
// (Preferences > Package Settings > Verilog Gadget > Settings - User)
//
// "templates": [
// [ "Default", "Packages/Verilog Gadget/template/verilog_template_default.v" ],
// [ "FSM", "D:/template/verilog_fsm_template.v" ]
// ]
module LUT_CASE_32bits #(parameter W=32,N=3)
(
//Input Signals
input wire [N-1:0] address,
//Output Signals
output reg [W-1:0] data_out
);
always @(*) begin
case (address)
4'd0 : begin
data_out =32'h3f490fdb;
end
4'd1 : begin
data_out =32'h3eed6338;
end
4'd2 : begin
data_out =32'h3e7adbb0;
end
4'd3 : begin
data_out =32'h3dfeadd5;
end
4'd4 : begin
data_out =32'h3d7faade;
end
4'd5 : begin
data_out =32'h3cffeaae;
end
4'd6 : begin
data_out =32'h3c7ffaab;
end
4'd7 : begin
data_out =32'h3bfffeab;
end
4'd8 : begin
data_out =32'h3b7fffab;
end
4'd9 : begin
data_out =32'h3affffeb;
end
4'd10 : begin
data_out =32'h3a7ffffb;
end
4'd11 : begin
data_out =32'h39ffffff;
end
4'd12 : begin
data_out =32'h39800000;
end
4'd13 : begin
data_out =32'h39000000;
end
4'd14 : begin
data_out =32'h38800000;
end
4'd15 : begin
data_out =32'h38000000;
end
default: begin
data_out =32'h3f490fdb;
end
endcase
end
endmodule // template
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/14.0/ip/merlin/altera_irq_bridge/altera_irq_bridge.v#1 $
// $Revision: #1 $
// $Date: 2014/02/16 $
// $Author: swbranch $
// -------------------------------------------------------
// Altera IRQ Bridge
//
// Parameters
// IRQ_WIDTH : $IRQ_WIDTH
//
// -------------------------------------------------------
//------------------------------------------
// Message Supression Used
// QIS Warnings
// 15610 - Warning: Design contains x input pin(s) that do not drive logic
//------------------------------------------
`timescale 1 ns / 1 ns
module altera_irq_bridge
#(
parameter IRQ_WIDTH = 32
)
(
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset,
input [IRQ_WIDTH - 1:0] receiver_irq,
output sender31_irq,
output sender30_irq,
output sender29_irq,
output sender28_irq,
output sender27_irq,
output sender26_irq,
output sender25_irq,
output sender24_irq,
output sender23_irq,
output sender22_irq,
output sender21_irq,
output sender20_irq,
output sender19_irq,
output sender18_irq,
output sender17_irq,
output sender16_irq,
output sender15_irq,
output sender14_irq,
output sender13_irq,
output sender12_irq,
output sender11_irq,
output sender10_irq,
output sender9_irq,
output sender8_irq,
output sender7_irq,
output sender6_irq,
output sender5_irq,
output sender4_irq,
output sender3_irq,
output sender2_irq,
output sender1_irq,
output sender0_irq
);
wire [31:0] receiver_temp_irq;
assign receiver_temp_irq = {{(32 - IRQ_WIDTH){1'b0}}, receiver_irq}; //to align a non-32bit receiver interface with 32 interfaces of the receiver
assign sender0_irq = receiver_temp_irq[0];
assign sender1_irq = receiver_temp_irq[1];
assign sender2_irq = receiver_temp_irq[2];
assign sender3_irq = receiver_temp_irq[3];
assign sender4_irq = receiver_temp_irq[4];
assign sender5_irq = receiver_temp_irq[5];
assign sender6_irq = receiver_temp_irq[6];
assign sender7_irq = receiver_temp_irq[7];
assign sender8_irq = receiver_temp_irq[8];
assign sender9_irq = receiver_temp_irq[9];
assign sender10_irq = receiver_temp_irq[10];
assign sender11_irq = receiver_temp_irq[11];
assign sender12_irq = receiver_temp_irq[12];
assign sender13_irq = receiver_temp_irq[13];
assign sender14_irq = receiver_temp_irq[14];
assign sender15_irq = receiver_temp_irq[15];
assign sender16_irq = receiver_temp_irq[16];
assign sender17_irq = receiver_temp_irq[17];
assign sender18_irq = receiver_temp_irq[18];
assign sender19_irq = receiver_temp_irq[19];
assign sender20_irq = receiver_temp_irq[20];
assign sender21_irq = receiver_temp_irq[21];
assign sender22_irq = receiver_temp_irq[22];
assign sender23_irq = receiver_temp_irq[23];
assign sender24_irq = receiver_temp_irq[24];
assign sender25_irq = receiver_temp_irq[25];
assign sender26_irq = receiver_temp_irq[26];
assign sender27_irq = receiver_temp_irq[27];
assign sender28_irq = receiver_temp_irq[28];
assign sender29_irq = receiver_temp_irq[29];
assign sender30_irq = receiver_temp_irq[30];
assign sender31_irq = receiver_temp_irq[31];
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`ifdef WRITEMEM_BIN
`define READMEMX $readmemb
`define WRITEMEMX $writememb
`else
`define READMEMX $readmemh
`define WRITEMEMX $writememh
`endif
module t;
// verilator lint_off LITENDIAN
reg [5:0] binary_string [2:15];
reg [5:0] binary_nostart [2:15];
reg [5:0] binary_start [0:15];
reg [175:0] hex [0:15];
reg [(32*6)-1:0] hex_align [0:15];
string fns;
`ifdef WRITEMEM_READ_BACK
reg [5:0] binary_string_tmp [2:15];
reg [5:0] binary_nostart_tmp [2:15];
reg [5:0] binary_start_tmp [0:15];
reg [175:0] hex_tmp [0:15];
reg [(32*6)-1:0] hex_align_tmp [0:15];
string fns_tmp;
`endif
// verilator lint_on LITENDIAN
integer i;
initial begin
begin
// Initialize memories to zero,
// avoid differences between 2-state and 4-state.
for (i=0; i<16; i=i+1) begin
binary_start[i] = 6'h0;
hex[i] = 176'h0;
hex_align[i] = {32*6{1'b0}};
`ifdef WRITEMEM_READ_BACK
binary_start_tmp[i] = 6'h0;
hex_tmp[i] = 176'h0;
hex_align_tmp[i] = {32*6{1'b0}};
`endif
end
for (i=2; i<16; i=i+1) begin
binary_string[i] = 6'h0;
binary_nostart[i] = 6'h0;
`ifdef WRITEMEM_READ_BACK
binary_string_tmp[i] = 6'h0;
binary_nostart_tmp[i] = 6'h0;
`endif
end
end
begin
`ifdef WRITEMEM_READ_BACK
$readmemb("t/t_sys_readmem_b.mem", binary_nostart_tmp);
// Do a round-trip $writememh(b) and $readmemh(b) cycle.
// This covers $writememh and ensures we can read our
// own memh output file.
// If WRITEMEM_BIN is also defined, use $writememb and
// $readmemb, otherwise use $writememh and $readmemh.
`ifdef TEST_VERBOSE
$display("-Writing %s", `OUT_TMP1);
`endif
`WRITEMEMX(`OUT_TMP1, binary_nostart_tmp);
`READMEMX(`OUT_TMP1, binary_nostart);
`else
$readmemb("t/t_sys_readmem_b.mem", binary_nostart);
`endif
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_nostart[i]);
`endif
if (binary_nostart['h2] != 6'h02) $stop;
if (binary_nostart['h3] != 6'h03) $stop;
if (binary_nostart['h4] != 6'h04) $stop;
if (binary_nostart['h5] != 6'h05) $stop;
if (binary_nostart['h6] != 6'h06) $stop;
if (binary_nostart['h7] != 6'h07) $stop;
if (binary_nostart['h8] != 6'h10) $stop;
if (binary_nostart['hc] != 6'h14) $stop;
if (binary_nostart['hd] != 6'h15) $stop;
end
begin
binary_start['h0c] = 6'h3f; // Not in read range
//
`ifdef WRITEMEM_READ_BACK
$readmemb("t/t_sys_readmem_b_8.mem", binary_start_tmp, 4, 4+7);
`ifdef TEST_VERBOSE
$display("-Writing %s", `OUT_TMP2);
`endif
`WRITEMEMX(`OUT_TMP2, binary_start_tmp, 4, 4+7);
`READMEMX(`OUT_TMP2, binary_start, 4, 4+7);
`else
$readmemb("t/t_sys_readmem_b_8.mem", binary_start, 4, 4+7); // 4-11
`endif
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_start[i]);
`endif
if (binary_start['h04] != 6'h10) $stop;
if (binary_start['h05] != 6'h11) $stop;
if (binary_start['h06] != 6'h12) $stop;
if (binary_start['h07] != 6'h13) $stop;
if (binary_start['h08] != 6'h14) $stop;
if (binary_start['h09] != 6'h15) $stop;
if (binary_start['h0a] != 6'h16) $stop;
if (binary_start['h0b] != 6'h17) $stop;
//
if (binary_start['h0c] != 6'h3f) $stop;
end
begin
// The 'hex' array is a non-exact multiple of word size
// (possible corner case)
`ifdef WRITEMEM_READ_BACK
$readmemh("t/t_sys_readmem_h.mem", hex_tmp, 0);
`ifdef TEST_VERBOSE
$display("-Writing %s", `OUT_TMP3);
`endif
`WRITEMEMX(`OUT_TMP3, hex_tmp, 0);
`READMEMX(`OUT_TMP3, hex, 0);
`else
$readmemh("t/t_sys_readmem_h.mem", hex, 0);
`endif
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, hex[i]);
`endif
if (hex['h04] != 176'h400437654321276543211765432107654321abcdef10) $stop;
if (hex['h0a] != 176'h400a37654321276543211765432107654321abcdef11) $stop;
if (hex['h0b] != 176'h400b37654321276543211765432107654321abcdef12) $stop;
if (hex['h0c] != 176'h400c37654321276543211765432107654321abcdef13) $stop;
end
begin
// The 'hex align' array is similar to 'hex', but it is an
// exact multiple of word size -- another possible corner case.
`ifdef WRITEMEM_READ_BACK
$readmemh("t/t_sys_readmem_align_h.mem", hex_align_tmp, 0);
`ifdef TEST_VERBOSE
$display("-Writing %s", `OUT_TMP4);
`endif
`WRITEMEMX(`OUT_TMP4, hex_align_tmp, 0);
`READMEMX(`OUT_TMP4, hex_align, 0);
`else
$readmemh("t/t_sys_readmem_align_h.mem", hex_align, 0);
`endif
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, hex_align[i]);
`endif
if (hex_align['h04] != 192'h77554004_37654321_27654321_17654321_07654321_abcdef10) $stop;
if (hex_align['h0a] != 192'h7755400a_37654321_27654321_17654321_07654321_abcdef11) $stop;
if (hex_align['h0b] != 192'h7755400b_37654321_27654321_17654321_07654321_abcdef12) $stop;
if (hex_align['h0c] != 192'h7755400c_37654321_27654321_17654321_07654321_abcdef13) $stop;
end
begin
fns = "t/t_sys_readmem_b.mem";
`ifdef WRITEMEM_READ_BACK
fns_tmp = `OUT_TMP5;
$readmemb(fns, binary_string_tmp);
`ifdef TEST_VERBOSE
$display("-Writing %s", `OUT_TMP5);
`endif
`WRITEMEMX(fns_tmp, binary_string_tmp);
`READMEMX(fns_tmp, binary_string);
`else
$readmemb(fns, binary_string);
`endif
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_string[i]);
`endif
if (binary_string['h2] != 6'h02) $stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed May 24 17:28:31 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_vga_buffer_1_0 -prefix
// system_vga_buffer_1_0_ system_vga_buffer_1_0_stub.v
// Design : system_vga_buffer_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_buffer,Vivado 2016.4" *)
module system_vga_buffer_1_0(clk_w, clk_r, wen, x_addr_w, y_addr_w, x_addr_r,
y_addr_r, data_w, data_r)
/* synthesis syn_black_box black_box_pad_pin="clk_w,clk_r,wen,x_addr_w[9:0],y_addr_w[9:0],x_addr_r[9:0],y_addr_r[9:0],data_w[23:0],data_r[23:0]" */;
input clk_w;
input clk_r;
input wen;
input [9:0]x_addr_w;
input [9:0]y_addr_w;
input [9:0]x_addr_r;
input [9:0]y_addr_r;
input [23:0]data_w;
output [23:0]data_r;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9361_tx (
// dac interface
dac_clk,
dac_valid,
dac_data,
dac_r1_mode,
adc_data,
// delay interface
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_locked,
// master/slave
dac_sync_in,
dac_sync_out,
// dma interface
dac_enable_i0,
dac_valid_i0,
dac_data_i0,
dac_enable_q0,
dac_valid_q0,
dac_data_q0,
dac_enable_i1,
dac_valid_i1,
dac_data_i1,
dac_enable_q1,
dac_valid_q1,
dac_data_q1,
dac_dovf,
dac_dunf,
// gpio
up_dac_gpio_in,
up_dac_gpio_out,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter DP_DISABLE = 0;
parameter PCORE_ID = 0;
// dac interface
input dac_clk;
output dac_valid;
output [47:0] dac_data;
output dac_r1_mode;
input [47:0] adc_data;
// delay interface
output [ 7:0] up_dld;
output [39:0] up_dwdata;
input [39:0] up_drdata;
input delay_clk;
output delay_rst;
input delay_locked;
// master/slave
input dac_sync_in;
output dac_sync_out;
// dma interface
output dac_enable_i0;
output dac_valid_i0;
input [15:0] dac_data_i0;
output dac_enable_q0;
output dac_valid_q0;
input [15:0] dac_data_q0;
output dac_enable_i1;
output dac_valid_i1;
input [15:0] dac_data_i1;
output dac_enable_q1;
output dac_valid_q1;
input [15:0] dac_data_q1;
input dac_dovf;
input dac_dunf;
// gpio
input [31:0] up_dac_gpio_in;
output [31:0] up_dac_gpio_out;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg dac_data_sync = 'd0;
reg [ 7:0] dac_rate_cnt = 'd0;
reg dac_valid = 'd0;
reg dac_valid_i0 = 'd0;
reg dac_valid_q0 = 'd0;
reg dac_valid_i1 = 'd0;
reg dac_valid_q1 = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal clock and resets
wire dac_rst;
// internal signals
wire dac_data_sync_s;
wire dac_dds_format_s;
wire [ 7:0] dac_datarate_s;
wire [47:0] dac_data_int_s;
wire [31:0] up_rdata_s[0:5];
wire up_rack_s[0:5];
wire up_wack_s[0:5];
// master/slave
assign dac_data_sync_s = (PCORE_ID == 0) ? dac_sync_out : dac_sync_in;
always @(posedge dac_clk) begin
dac_data_sync <= dac_data_sync_s;
end
// rate counters and data sync signals
always @(posedge dac_clk) begin
if ((dac_data_sync == 1'b1) || (dac_rate_cnt == 8'd0)) begin
dac_rate_cnt <= dac_datarate_s;
end else begin
dac_rate_cnt <= dac_rate_cnt - 1'b1;
end
end
// dma interface
always @(posedge dac_clk) begin
dac_valid <= (dac_rate_cnt == 8'd0) ? 1'b1 : 1'b0;
dac_valid_i0 <= dac_valid;
dac_valid_q0 <= dac_valid;
dac_valid_i1 <= dac_valid & ~dac_r1_mode;
dac_valid_q1 <= dac_valid & ~dac_r1_mode;
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] |
up_rack_s[3] | up_rack_s[4] | up_rack_s[5];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] |
up_wack_s[3] | up_wack_s[4] | up_wack_s[5];
end
end
// dac channel
axi_ad9361_tx_channel #(
.CHID (0),
.IQSEL (0),
.DP_DISABLE (DP_DISABLE))
i_tx_channel_0 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid),
.dma_data (dac_data_i0),
.adc_data (adc_data[11:0]),
.dac_data (dac_data[11:0]),
.dac_data_out (dac_data_int_s[11:0]),
.dac_data_in (dac_data_int_s[23:12]),
.dac_enable (dac_enable_i0),
.dac_data_sync (dac_data_sync),
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// dac channel
axi_ad9361_tx_channel #(
.CHID (1),
.IQSEL (1),
.DP_DISABLE (DP_DISABLE))
i_tx_channel_1 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid),
.dma_data (dac_data_q0),
.adc_data (adc_data[23:12]),
.dac_data (dac_data[23:12]),
.dac_data_out (dac_data_int_s[23:12]),
.dac_data_in (dac_data_int_s[11:0]),
.dac_enable (dac_enable_q0),
.dac_data_sync (dac_data_sync),
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// dac channel
axi_ad9361_tx_channel #(
.CHID (2),
.IQSEL (0),
.DP_DISABLE (DP_DISABLE))
i_tx_channel_2 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid),
.dma_data (dac_data_i1),
.adc_data (adc_data[35:24]),
.dac_data (dac_data[35:24]),
.dac_data_out (dac_data_int_s[35:24]),
.dac_data_in (dac_data_int_s[47:36]),
.dac_enable (dac_enable_i1),
.dac_data_sync (dac_data_sync),
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// dac channel
axi_ad9361_tx_channel #(
.CHID (3),
.IQSEL (1),
.DP_DISABLE (DP_DISABLE))
i_tx_channel_3 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid),
.dma_data (dac_data_q1),
.adc_data (adc_data[47:36]),
.dac_data (dac_data[47:36]),
.dac_data_out (dac_data_int_s[47:36]),
.dac_data_in (dac_data_int_s[35:24]),
.dac_enable (dac_enable_q1),
.dac_data_sync (dac_data_sync),
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[3]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[3]),
.up_rack (up_rack_s[3]));
// dac common processor interface
up_dac_common #(.PCORE_ID (PCORE_ID)) i_up_dac_common (
.mmcm_rst (),
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_sync (dac_sync_out),
.dac_frame (),
.dac_par_type (),
.dac_par_enb (),
.dac_r1_mode (dac_r1_mode),
.dac_datafmt (dac_dds_format_s),
.dac_datarate (dac_datarate_s),
.dac_status (1'b1),
.dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd1),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.dac_usr_chanmax (8'd3),
.up_dac_gpio_in (up_dac_gpio_in),
.up_dac_gpio_out (up_dac_gpio_out),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[4]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[4]),
.up_rack (up_rack_s[4]));
// dac delay control
up_delay_cntrl #(.IO_WIDTH(8), .IO_BASEADDR(6'h12)) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked),
.up_dld (up_dld),
.up_dwdata (up_dwdata),
.up_drdata (up_drdata),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[5]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[5]),
.up_rack (up_rack_s[5]));
endmodule
// ***************************************************************************
// ***************************************************************************
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 13.1
// \ \ Application : xaw2verilog
// / / Filename : main_pll.v
// /___/ /\ Timestamp : 06/02/2011 17:02:40
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -st /home/teknohog/dcmtest/ipcore_dir/./main_pll.xaw /home/teknohog/dcmtest/ipcore_dir/./main_pll
//Design Name: main_pll
//Device: xc3s500e-4fg320
//
// Module main_pll
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
`timescale 1ns / 1ps
module main_pll(CE_IN,
CLKIN_IN,
CLR_IN,
PRE_IN,
CLKIN_IBUFG_OUT,
CLK0_OUT,
CLK180_OUT,
DDR_CLK0_OUT,
LOCKED_OUT);
input CE_IN;
input CLKIN_IN;
input CLR_IN;
input PRE_IN;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
output CLK180_OUT;
output DDR_CLK0_OUT;
output LOCKED_OUT;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire CLK180_BUF;
wire C0_IN;
wire C1_IN;
wire GND_BIT;
wire VCC_BIT;
assign GND_BIT = 0;
assign VCC_BIT = 1;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = C0_IN;
assign CLK180_OUT = C1_IN;
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(C0_IN));
BUFG CLK180_BUFG_INST (.I(CLK180_BUF),
.O(C1_IN));
DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_SP_INST (.CLKFB(C0_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(CLK180_BUF),
.CLK270(),
.LOCKED(LOCKED_OUT),
.PSDONE(),
.STATUS());
OFDDRCPE OFDDRCPE_INST (.CE(CE_IN),
.CLR(CLR_IN),
.C0(C0_IN),
.C1(C1_IN),
.D0(VCC_BIT),
.D1(GND_BIT),
.PRE(PRE_IN),
.Q(DDR_CLK0_OUT));
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//===----------------------------------------------------------------------===//
//
// Parameterized FIFO with input and output registers and ACL pipeline
// protocol ports.
//
//===----------------------------------------------------------------------===//
module acl_mlab_fifo (
clock,
resetn,
data_in,
data_out,
valid_in,
valid_out,
stall_in,
stall_out,
usedw,
empty,
full,
almost_full);
function integer my_local_log;
input [31:0] value;
for (my_local_log=0; value>0; my_local_log=my_local_log+1)
value = value>>1;
endfunction
parameter DATA_WIDTH = 32;
parameter DEPTH = 256;
parameter NUM_BITS_USED_WORDS = DEPTH == 1 ? 1 : my_local_log(DEPTH-1);
parameter ALMOST_FULL_VALUE = 0;
input clock, stall_in, valid_in, resetn;
output stall_out, valid_out;
input [DATA_WIDTH-1:0] data_in;
output [DATA_WIDTH-1:0] data_out;
output [NUM_BITS_USED_WORDS-1:0] usedw;
output empty, full, almost_full;
// add a register stage prior to the acl_fifo.
//reg [DATA_WIDTH-1:0] data_input /* synthesis preserve */;
//reg valid_input /* synthesis preserve */;
//always@(posedge clock or negedge resetn)
//begin
// if (~resetn)
// begin
// data_input <= {DATA_WIDTH{1'bx}};
// valid_input <= 1'b0;
// end
// else if (~valid_input | ~full)
// begin
// valid_input <= valid_in;
// data_input <= data_in;
// end
//end
scfifo scfifo_component (
.clock (clock),
.data (data_in),
.rdreq ((~stall_in) & (~empty)),
.sclr (),
.wrreq (valid_in & (~full)),
.empty (empty),
.full (full),
.q (data_out),
.aclr (~resetn),
.almost_empty (),
.almost_full (almost_full),
.usedw (usedw));
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Stratix V",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB",
scfifo_component.lpm_numwords = DEPTH,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = DATA_WIDTH,
scfifo_component.lpm_widthu = NUM_BITS_USED_WORDS,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON",
scfifo_component.almost_full_value = ALMOST_FULL_VALUE;
assign stall_out = full;
assign valid_out = ~empty;
endmodule
|
module BarrelShifter(input [31:0] Rs,Rm,IR,input SR29_IN,output SR29_OUT,output [31:0] Out);
/*
Data processing immediate IR[27:25] == 000 & IR[4] = 0/ IR[6:5] Shiftype / IR[11:7] Shift Amount/ Shift val Rm
Data register shift IR[27:25] == 000 / IR[6:5] Shiftype / Rs Shift Amount/ Shift val Rm
Data processing immediate IR[27:25] == 001 / ROR Shiftype / IR[11:7] Shift Amount / Shift val IR[7:0]
Load/Store immediate IR[27:25] == 010
Load/Store register offset IR[27:25] == 011
branch and branch with link IR[27:25] == 101
*/
reg [31:0] shiftVal,shiftAmount;
reg [1:0] shiftType;
always@(IR or Rm or Rs or SR29_IN)
begin
case(IR[27:25])
3'b000:
begin
if(!IR[4])//Immediate Rs
begin
$display("Immediate Rm");
shiftVal = Rm;
shiftAmount = IR[11:7];
shiftType = IR[6:5];
end
else
begin
$display("Registe rm"); // Registe rs
shiftVal = Rm;
shiftAmount = Rs[5:0];
shiftType = IR[6:5];
end
end
3'b001:
begin//Imediate IR[7:0]
$display("Imediate IR[7:0]");
shiftVal = IR[7:0];
shiftAmount = IR[11:8]*2;
shiftType = 2'b11;
end
3'b010:
begin//Imediate IR[7:0]
$display("Load/Store-Immediate Rm");
_Out = {IR[11],IR[11],IR[11],IR[11],IR[11],
IR[11],IR[11],IR[11],IR[11],IR[11],
IR[11],IR[11],IR[11],IR[11],IR[11],
IR[11],IR[11],IR[11],IR[11],IR[11],
IR[11:0]};
end
3'b011:
begin//Imediate IR[7:0]
$display("Load/Store-offsett/index Rm");
shiftVal = Rm;
shiftAmount = IR[11:7];
shiftType = IR[6:5];
end
3'b101:
begin//branch
$display("Branch");
_Out = 4*{IR[23],IR[23],IR[23],IR[23],IR[23],IR[23],IR[23],IR[23],IR[23],IR[23:0]};
end
endcase
end
reg [32:0] temp,temp2;
reg [31:0] _Out;
reg _SR29_OUT;
integer i=0;
assign Out = _Out;
assign SR29_OUT = _SR29_OUT;
always@(*)
begin
case(shiftType)
2'b00:
begin
$display("LSL");
if(shiftAmount==32)
_Out = 0 ;
else if (shiftAmount>=33)
{_SR29_OUT,_Out} = 0 ;
else begin
temp = {SR29_IN,shiftVal };
temp2 = 0;
for(i = 0; i <= 32 - shiftAmount[4:0] ;i = i + 1) begin
temp2[32-i] = temp[32-i-shiftAmount[4:0] ] ;
end
{_SR29_OUT,_Out} = temp2;
end
end
2'b01:
begin
$display("LSR");
if(shiftAmount==32)
_Out = 0 ;
else if (shiftAmount>=33)
{_SR29_OUT,_Out} = 0 ;
else begin
temp = {shiftVal,SR29_IN};
temp2 = 0;
for(i = 0; i <= 32-shiftAmount[4:0] ;i = i + 1) begin
temp2[i] = temp[i+shiftAmount[4:0] ] ;
end
{_Out,_SR29_OUT} = temp2;
end
end
2'b10:
begin
$display("ASR");
if(shiftAmount==32)
begin
_Out = {shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31]};
end
else if (shiftAmount>=33)
begin
{_SR29_OUT,_Out} = {shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31]};
end
else begin
temp = {shiftVal,SR29_IN };
//Lazy to encode in loop
temp2 = {shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],shiftVal[31],
shiftVal[31],shiftVal[31]};
for(i = 0; i <= 32-shiftAmount[4:0] ;i = i + 1) begin
temp2[i] = temp[i+shiftAmount[4:0] ] ;
end
{_Out,_SR29_OUT} = temp2;
end
end
2'b11:
begin
$display("ROR");
temp = {shiftVal,SR29_IN};
temp2 = temp;
for(i = 0; i <= 32 ;i = i + 1) begin
temp2[i] = temp[(i+shiftAmount[4:0])%33] ;
$display("[%3d]=[%3d]",i,(i+shiftAmount[4:0])%33);
end
{_Out,_SR29_OUT} = temp2;
end
endcase
end
endmodule
|
`timescale 1 ns / 1 ps
module hapara_axis_id_generator_v1_0_S00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
input wire Finish,
output wire En,
// output wire [C_S_AXI_DATA_WIDTH - 1 : 0] orgX,
// output wire [C_S_AXI_DATA_WIDTH - 1 : 0] orgY,
// output wire [C_S_AXI_DATA_WIDTH - 1 : 0] lengthX,
// output wire [C_S_AXI_DATA_WIDTH - 1 : 0] lengthY,
output wire [C_S_AXI_DATA_WIDTH - 1 : 0] org,
output wire [C_S_AXI_DATA_WIDTH - 1 : 0] len,
output wire [C_S_AXI_DATA_WIDTH - 1 : 0] numOfSlv,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 1;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 4
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 || curr_state == counting)
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
// slv_reg3 <= 0;
end
else begin
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 0
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h1:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 1
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h2:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 2
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
// 2'h3:
// for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
// if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 3
// slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
// end
default : begin
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
// slv_reg3 <= slv_reg3;
end
endcase
end
end
end
//logic for writing slv_reg3;
always @(posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN || curr_state == reset || curr_state == counting) begin
slv_reg3 <= 0;
end
else if (curr_state == finish) begin
slv_reg3 <= 1;
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0 : reg_data_out <= slv_reg0;
2'h1 : reg_data_out <= slv_reg1;
2'h2 : reg_data_out <= slv_reg2;
2'h3 : reg_data_out <= slv_reg3;
default : reg_data_out <= 0;
endcase
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
// Add user logic here
// X: vertical
// Y: horizontal
// slv_reg0: orgX, orgY
// slv_reg1: lenX, lenY
// slv_reg2: num of slaves
// slv_reg3: isFinish?
// reg [C_S_AXI_DATA_WIDTH - 1 : 0] reg_orgX; //slv_reg0
// reg [C_S_AXI_DATA_WIDTH - 1 : 0] reg_orgY; //slv_reg1
// reg [C_S_AXI_DATA_WIDTH - 1 : 0] reg_lengthX; //slv_reg2
// reg [C_S_AXI_DATA_WIDTH - 1 : 0] reg_lengthY; //slv_reg3
reg [C_S_AXI_DATA_WIDTH - 1 : 0] reg_org;
reg [C_S_AXI_DATA_WIDTH - 1 : 0] reg_len;
reg [C_S_AXI_DATA_WIDTH - 1 : 0] reg_numOfSlv;
localparam LENGTH = C_S_AXI_DATA_WIDTH / 2;
localparam reset = 3'b001;
localparam counting = 3'b010;
localparam finish = 3'b100;
reg [2 : 0] next_state;
reg [2 : 0] curr_state;
// logic for reg_*
always @(posedge S_AXI_ACLK or negedge S_AXI_ARESETN) begin
if (!S_AXI_ARESETN) begin
reg_org <= 0;
reg_len <= 0;
reg_numOfSlv <= 0;
end
else begin
if (curr_state == reset) begin
reg_org <= slv_reg0;
reg_len <= slv_reg1;
reg_numOfSlv <= slv_reg2;
end
else begin
reg_org <= reg_org;
reg_len <= reg_len;
reg_numOfSlv <= reg_numOfSlv;
end
end
end
// logic for curr_state;
always @(posedge S_AXI_ACLK or negedge S_AXI_ARESETN) begin
if (!S_AXI_ARESETN) begin
// reset
curr_state <= reset;
end
else begin
curr_state <= next_state;
end
end
wire data_ready;
assign data_ready =
(slv_reg1[C_S_AXI_DATA_WIDTH - 1 : LENGTH] != {LENGTH{1'b0}}) &&
(slv_reg1[LENGTH - 1 : 0] != {LENGTH{1'b0}});
always @(curr_state or data_ready or Finish) begin
case(curr_state)
reset:
if (data_ready) begin
next_state = counting;
end
else begin
next_state = reset;
end
counting:
if (Finish) begin
next_state = finish;
end
else begin
next_state = counting;
end
finish:
if (data_ready) begin
next_state = reset;
end
else begin
next_state = finish;
end
default :
next_state = 3'bxxx;
endcase
end
assign En = curr_state == counting;
// assign orgX = reg_orgX;
// assign orgY = reg_orgY;
// assign lengthX = reg_lengthX;
// assign lengthY = reg_lengthY;
assign org = reg_org;
assign len = reg_len;
assign numOfSlv = reg_numOfSlv;
// User logic ends
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_wrlvl.v
// /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $
// \ \ / \ Date Created: Mon Jun 23 2008
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Memory initialization and overall master state control during
// initialization and calibration. Specifically, the following functions
// are performed:
// 1. Memory initialization (initial AR, mode register programming, etc.)
// 2. Initiating write leveling
// 3. Generate training pattern writes for read leveling. Generate
// memory readback for read leveling.
// This module has a DFI interface for providing control/address and write
// data to the rest of the PHY datapath during initialization/calibration.
// Once initialization is complete, control is passed to the MC.
// NOTES:
// 1. Multiple CS (multi-rank) not supported
// 2. DDR2 not supported
// 3. ODT not supported
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_wrlvl.v,v 1.3 2011/06/24 14:49:00 mgeorge Exp $
**$Date: 2011/06/24 14:49:00 $
**$Author: mgeorge $
**$Revision: 1.3 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_wrlvl.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_wrlvl #
(
parameter TCQ = 100,
parameter DQS_CNT_WIDTH = 3,
parameter DQ_WIDTH = 64,
parameter DQS_WIDTH = 2,
parameter DRAM_WIDTH = 8,
parameter RANKS = 1,
parameter nCK_PER_CLK = 4,
parameter CLK_PERIOD = 4,
parameter SIM_CAL_OPTION = "NONE"
)
(
input clk,
input rst,
input phy_ctl_ready,
input wr_level_start,
input wl_sm_start,
input wrlvl_final,
input wrlvl_byte_redo,
input [DQS_CNT_WIDTH:0] wrcal_cnt,
input early1_data,
input early2_data,
input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt,
input oclkdelay_calib_done,
input [(DQ_WIDTH)-1:0] rd_data_rise0,
output reg wrlvl_byte_done,
output reg dqs_po_dec_done /* synthesis syn_maxfan = 2 */,
output phy_ctl_rdy_dly,
output reg wr_level_done /* synthesis syn_maxfan = 2 */,
// to phy_init for cs logic
output wrlvl_rank_done,
output done_dqs_tap_inc,
output [DQS_CNT_WIDTH:0] po_stg2_wl_cnt,
// Fine delay line used only during write leveling
// Inc/dec Phaser_Out fine delay line
output reg dqs_po_stg2_f_incdec,
// Enable Phaser_Out fine delay inc/dec
output reg dqs_po_en_stg2_f,
// Coarse delay line used during write leveling
// only if 64 taps of fine delay line were not
// sufficient to detect a 0->1 transition
// Inc Phaser_Out coarse delay line
output reg dqs_wl_po_stg2_c_incdec,
// Enable Phaser_Out coarse delay inc/dec
output reg dqs_wl_po_en_stg2_c,
// Read Phaser_Out delay value
input [8:0] po_counter_read_val,
// output reg dqs_wl_po_stg2_load,
// output reg [8:0] dqs_wl_po_stg2_reg_l,
// CK edge undetected
output reg wrlvl_err,
output reg [3*DQS_WIDTH-1:0] wl_po_coarse_cnt,
output reg [6*DQS_WIDTH-1:0] wl_po_fine_cnt,
// Debug ports
output [5:0] dbg_wl_tap_cnt,
output dbg_wl_edge_detect_valid,
output [(DQS_WIDTH)-1:0] dbg_rd_data_edge_detect,
output [DQS_CNT_WIDTH:0] dbg_dqs_count,
output [4:0] dbg_wl_state,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output [255:0] dbg_phy_wrlvl
);
localparam WL_IDLE = 5'h0;
localparam WL_INIT = 5'h1;
localparam WL_INIT_FINE_INC = 5'h2;
localparam WL_INIT_FINE_INC_WAIT1= 5'h3;
localparam WL_INIT_FINE_INC_WAIT = 5'h4;
localparam WL_INIT_FINE_DEC = 5'h5;
localparam WL_INIT_FINE_DEC_WAIT = 5'h6;
localparam WL_FINE_INC = 5'h7;
localparam WL_WAIT = 5'h8;
localparam WL_EDGE_CHECK = 5'h9;
localparam WL_DQS_CHECK = 5'hA;
localparam WL_DQS_CNT = 5'hB;
localparam WL_2RANK_TAP_DEC = 5'hC;
localparam WL_2RANK_DQS_CNT = 5'hD;
localparam WL_FINE_DEC = 5'hE;
localparam WL_FINE_DEC_WAIT = 5'hF;
localparam WL_CORSE_INC = 5'h10;
localparam WL_CORSE_INC_WAIT = 5'h11;
localparam WL_CORSE_INC_WAIT1 = 5'h12;
localparam WL_CORSE_INC_WAIT2 = 5'h13;
localparam WL_CORSE_DEC = 5'h14;
localparam WL_CORSE_DEC_WAIT = 5'h15;
localparam WL_CORSE_DEC_WAIT1 = 5'h16;
localparam WL_FINE_INC_WAIT = 5'h17;
localparam WL_2RANK_FINAL_TAP = 5'h18;
localparam WL_INIT_FINE_DEC_WAIT1= 5'h19;
localparam WL_FINE_DEC_WAIT1 = 5'h1A;
localparam WL_CORSE_INC_WAIT_TMP = 5'h1B;
localparam COARSE_TAPS = 7;
localparam FAST_CAL_FINE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 45 : 48;
localparam FAST_CAL_COARSE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 1 : 2;
localparam REDO_COARSE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 2 : 5;
integer i, j, k, l, p, q, r, s, t, m, n, u, v, w, x,y;
reg phy_ctl_ready_r1;
reg phy_ctl_ready_r2;
reg phy_ctl_ready_r3;
reg phy_ctl_ready_r4;
reg phy_ctl_ready_r5;
reg phy_ctl_ready_r6;
(* max_fanout = 50 *) reg [DQS_CNT_WIDTH:0] dqs_count_r;
reg [1:0] rank_cnt_r;
reg [DQS_WIDTH-1:0] rd_data_rise_wl_r;
reg [DQS_WIDTH-1:0] rd_data_previous_r;
reg [DQS_WIDTH-1:0] rd_data_edge_detect_r;
reg wr_level_done_r;
reg wrlvl_rank_done_r;
reg wr_level_start_r;
reg [4:0] wl_state_r, wl_state_r1;
reg inhibit_edge_detect_r;
reg wl_edge_detect_valid_r;
reg [5:0] wl_tap_count_r;
reg [5:0] fine_dec_cnt;
reg [5:0] fine_inc[0:DQS_WIDTH-1]; // DQS_WIDTH number of counters 6-bit each
reg [2:0] corse_dec[0:DQS_WIDTH-1];
reg [2:0] corse_inc[0:DQS_WIDTH-1];
reg dq_cnt_inc;
reg [3:0] stable_cnt;
reg flag_ck_negedge;
//reg past_negedge;
reg flag_init;
reg [2:0] corse_cnt[0:DQS_WIDTH-1];
reg [3*DQS_WIDTH-1:0] corse_cnt_dbg;
reg [2:0] wl_corse_cnt[0:RANKS-1][0:DQS_WIDTH-1];
//reg [3*DQS_WIDTH-1:0] coarse_tap_inc;
reg [2:0] final_coarse_tap[0:DQS_WIDTH-1];
reg [5:0] add_smallest[0:DQS_WIDTH-1];
reg [5:0] add_largest[0:DQS_WIDTH-1];
//reg [6*DQS_WIDTH-1:0] fine_tap_inc;
//reg [6*DQS_WIDTH-1:0] fine_tap_dec;
reg wr_level_done_r1;
reg wr_level_done_r2;
reg wr_level_done_r3;
reg wr_level_done_r4;
reg wr_level_done_r5;
reg [5:0] wl_dqs_tap_count_r[0:RANKS-1][0:DQS_WIDTH-1];
reg [5:0] smallest[0:DQS_WIDTH-1];
reg [5:0] largest[0:DQS_WIDTH-1];
reg [5:0] final_val[0:DQS_WIDTH-1];
reg [5:0] po_dec_cnt[0:DQS_WIDTH-1];
reg done_dqs_dec;
reg [8:0] po_rdval_cnt;
reg po_cnt_dec;
reg po_dec_done;
reg dual_rnk_dec;
wire [DQS_CNT_WIDTH+2:0] dqs_count_w;
reg [5:0] fast_cal_fine_cnt;
reg [2:0] fast_cal_coarse_cnt;
reg wrlvl_byte_redo_r;
reg [2:0] wrlvl_redo_corse_inc;
reg wrlvl_final_r;
reg final_corse_dec;
wire [DQS_CNT_WIDTH+2:0] oclk_count_w;
reg wrlvl_tap_done_r ;
reg [3:0] wait_cnt;
reg [3:0] incdec_wait_cnt;
// Debug ports
assign dbg_wl_edge_detect_valid = wl_edge_detect_valid_r;
assign dbg_rd_data_edge_detect = rd_data_edge_detect_r;
assign dbg_wl_tap_cnt = wl_tap_count_r;
assign dbg_dqs_count = dqs_count_r;
assign dbg_wl_state = wl_state_r;
assign dbg_wrlvl_fine_tap_cnt = wl_po_fine_cnt;
assign dbg_wrlvl_coarse_tap_cnt = wl_po_coarse_cnt;
always @(*) begin
for (v = 0; v < DQS_WIDTH; v = v + 1)
corse_cnt_dbg[3*v+:3] = corse_cnt[v];
end
assign dbg_phy_wrlvl[0+:27] = corse_cnt_dbg;
assign dbg_phy_wrlvl[27+:5] = wl_state_r;
assign dbg_phy_wrlvl[32+:4] = dqs_count_r;
assign dbg_phy_wrlvl[36+:9] = rd_data_rise_wl_r;
assign dbg_phy_wrlvl[45+:9] = rd_data_previous_r;
assign dbg_phy_wrlvl[54+:4] = stable_cnt;
assign dbg_phy_wrlvl[58] = 'd0;
assign dbg_phy_wrlvl[59] = flag_ck_negedge;
assign dbg_phy_wrlvl [60] = wl_edge_detect_valid_r;
assign dbg_phy_wrlvl [61+:6] = wl_tap_count_r;
assign dbg_phy_wrlvl [67+:9] = rd_data_edge_detect_r;
assign dbg_phy_wrlvl [76+:54] = wl_po_fine_cnt;
assign dbg_phy_wrlvl [130+:27] = wl_po_coarse_cnt;
//**************************************************************************
// DQS count to hard PHY during write leveling using Phaser_OUT Stage2 delay
//**************************************************************************
assign po_stg2_wl_cnt = dqs_count_r;
assign wrlvl_rank_done = wrlvl_rank_done_r;
assign done_dqs_tap_inc = done_dqs_dec;
assign phy_ctl_rdy_dly = phy_ctl_ready_r6;
always @(posedge clk) begin
phy_ctl_ready_r1 <= #TCQ phy_ctl_ready;
phy_ctl_ready_r2 <= #TCQ phy_ctl_ready_r1;
phy_ctl_ready_r3 <= #TCQ phy_ctl_ready_r2;
phy_ctl_ready_r4 <= #TCQ phy_ctl_ready_r3;
phy_ctl_ready_r5 <= #TCQ phy_ctl_ready_r4;
phy_ctl_ready_r6 <= #TCQ phy_ctl_ready_r5;
wrlvl_byte_redo_r <= #TCQ wrlvl_byte_redo;
wrlvl_final_r <= #TCQ wrlvl_final;
if ((wrlvl_byte_redo && ~wrlvl_byte_redo_r) ||
(wrlvl_final && ~wrlvl_final_r))
wr_level_done <= #TCQ 1'b0;
else
wr_level_done <= #TCQ done_dqs_dec;
end
// Status signal that will be asserted once the first
// pass of write leveling is done.
always @(posedge clk) begin
if(rst) begin
wrlvl_tap_done_r <= #TCQ 1'b0 ;
end else begin
if(wrlvl_tap_done_r == 1'b0) begin
if(oclkdelay_calib_done) begin
wrlvl_tap_done_r <= #TCQ 1'b1 ;
end
end
end
end
always @(posedge clk) begin
if (rst || po_cnt_dec)
wait_cnt <= #TCQ 'd8;
else if (phy_ctl_ready_r6 && (wait_cnt > 'd0))
wait_cnt <= #TCQ wait_cnt - 1;
end
always @(posedge clk) begin
if (rst) begin
po_rdval_cnt <= #TCQ 'd0;
end else if (phy_ctl_ready_r5 && ~phy_ctl_ready_r6) begin
po_rdval_cnt <= #TCQ po_counter_read_val;
end else if (po_rdval_cnt > 'd0) begin
if (po_cnt_dec)
po_rdval_cnt <= #TCQ po_rdval_cnt - 1;
else
po_rdval_cnt <= #TCQ po_rdval_cnt;
end else if (po_rdval_cnt == 'd0) begin
po_rdval_cnt <= #TCQ po_rdval_cnt;
end
end
always @(posedge clk) begin
if (rst || (po_rdval_cnt == 'd0))
po_cnt_dec <= #TCQ 1'b0;
else if (phy_ctl_ready_r6 && (po_rdval_cnt > 'd0) && (wait_cnt == 'd1))
po_cnt_dec <= #TCQ 1'b1;
else
po_cnt_dec <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst)
po_dec_done <= #TCQ 1'b0;
else if (((po_cnt_dec == 'd1) && (po_rdval_cnt == 'd1)) ||
(phy_ctl_ready_r6 && (po_rdval_cnt == 'd0))) begin
po_dec_done <= #TCQ 1'b1;
end
end
always @(posedge clk) begin
dqs_po_dec_done <= #TCQ po_dec_done;
wr_level_done_r1 <= #TCQ wr_level_done_r;
wr_level_done_r2 <= #TCQ wr_level_done_r1;
wr_level_done_r3 <= #TCQ wr_level_done_r2;
wr_level_done_r4 <= #TCQ wr_level_done_r3;
wr_level_done_r5 <= #TCQ wr_level_done_r4;
for (l = 0; l < DQS_WIDTH; l = l + 1) begin
wl_po_coarse_cnt[3*l+:3] <= #TCQ final_coarse_tap[l];
if ((RANKS == 1) || ~oclkdelay_calib_done)
wl_po_fine_cnt[6*l+:6] <= #TCQ smallest[l];
else
wl_po_fine_cnt[6*l+:6] <= #TCQ final_val[l];
end
end
generate
if (RANKS == 2) begin: dual_rank
always @(posedge clk) begin
if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r) ||
(wrlvl_final && ~wrlvl_final_r))
done_dqs_dec <= #TCQ 1'b0;
else if ((SIM_CAL_OPTION == "FAST_CAL") || ~oclkdelay_calib_done)
done_dqs_dec <= #TCQ wr_level_done_r;
else if (wr_level_done_r5 && (wl_state_r == WL_IDLE))
done_dqs_dec <= #TCQ 1'b1;
end
end else begin: single_rank
always @(posedge clk) begin
if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r) ||
(wrlvl_final && ~wrlvl_final_r))
done_dqs_dec <= #TCQ 1'b0;
else if (~oclkdelay_calib_done)
done_dqs_dec <= #TCQ wr_level_done_r;
else if (wr_level_done_r3 && ~wr_level_done_r4)
done_dqs_dec <= #TCQ 1'b1;
end
end
endgenerate
always @(posedge clk)
if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r))
wrlvl_byte_done <= #TCQ 1'b0;
else if (wrlvl_byte_redo && wr_level_done_r3 && ~wr_level_done_r4)
wrlvl_byte_done <= #TCQ 1'b1;
// Storing DQS tap values at the end of each DQS write leveling
always @(posedge clk) begin
if (rst) begin
for (k = 0; k < RANKS; k = k + 1) begin: rst_wl_dqs_tap_count_loop
for (n = 0; n < DQS_WIDTH; n = n + 1) begin
wl_corse_cnt[k][n] <= #TCQ 'b0;
wl_dqs_tap_count_r[k][n] <= #TCQ 'b0;
end
end
end else if ((wl_state_r == WL_DQS_CNT) | (wl_state_r == WL_WAIT) |
(wl_state_r == WL_FINE_DEC_WAIT1) |
(wl_state_r == WL_2RANK_TAP_DEC)) begin
wl_dqs_tap_count_r[rank_cnt_r][dqs_count_r] <= #TCQ wl_tap_count_r;
wl_corse_cnt[rank_cnt_r][dqs_count_r] <= #TCQ corse_cnt[dqs_count_r];
end else if ((SIM_CAL_OPTION == "FAST_CAL") & (wl_state_r == WL_DQS_CHECK)) begin
for (p = 0; p < RANKS; p = p +1) begin: dqs_tap_rank_cnt
for(q = 0; q < DQS_WIDTH; q = q +1) begin: dqs_tap_dqs_cnt
wl_dqs_tap_count_r[p][q] <= #TCQ wl_tap_count_r;
wl_corse_cnt[p][q] <= #TCQ corse_cnt[0];
end
end
end
end
// Convert coarse delay to fine taps in case of unequal number of coarse
// taps between ranks. Assuming a difference of 1 coarse tap counts
// between ranks. A common fine and coarse tap value must be used for both ranks
// because Phaser_Out has only one rank register.
// Coarse tap1 = period(ps)*93/360 = 34 fine taps
// Other coarse taps = period(ps)*103/360 = 38 fine taps
generate
genvar cnt;
if (RANKS == 2) begin // Dual rank
for(cnt = 0; cnt < DQS_WIDTH; cnt = cnt +1) begin: coarse_dqs_cnt
always @(posedge clk) begin
if (rst) begin
//coarse_tap_inc[3*cnt+:3] <= #TCQ 'b0;
add_smallest[cnt] <= #TCQ 'd0;
add_largest[cnt] <= #TCQ 'd0;
final_coarse_tap[cnt] <= #TCQ 'd0;
end else if (wr_level_done_r1 & ~wr_level_done_r2) begin
if (~oclkdelay_calib_done) begin
for(y = 0 ; y < DQS_WIDTH; y = y+1) begin
final_coarse_tap[y] <= #TCQ wl_corse_cnt[0][y];
add_smallest[y] <= #TCQ 'd0;
add_largest[y] <= #TCQ 'd0;
end
end else
if (wl_corse_cnt[0][cnt] == wl_corse_cnt[1][cnt]) begin
// Both ranks have use the same number of coarse delay taps.
// No conversion of coarse tap to fine taps required.
//coarse_tap_inc[3*cnt+:3] <= #TCQ wl_corse_cnt[1][3*cnt+:3];
final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt];
add_smallest[cnt] <= #TCQ 'd0;
add_largest[cnt] <= #TCQ 'd0;
end else if (wl_corse_cnt[0][cnt] < wl_corse_cnt[1][cnt]) begin
// Rank 0 uses fewer coarse delay taps than rank1.
// conversion of coarse tap to fine taps required for rank1.
// The final coarse count will the smaller value.
//coarse_tap_inc[3*cnt+:3] <= #TCQ wl_corse_cnt[1][3*cnt+:3] - 1;
final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt] - 1;
if (|wl_corse_cnt[0][cnt])
// Coarse tap 2 or higher being converted to fine taps
// This will be added to 'largest' value in final_val
// computation
add_largest[cnt] <= #TCQ 'd38;
else
// Coarse tap 1 being converted to fine taps
// This will be added to 'largest' value in final_val
// computation
add_largest[cnt] <= #TCQ 'd34;
end else if (wl_corse_cnt[0][cnt] > wl_corse_cnt[1][cnt]) begin
// This may be an unlikely scenario in a real system.
// Rank 0 uses more coarse delay taps than rank1.
// conversion of coarse tap to fine taps required.
//coarse_tap_inc[3*cnt+:3] <= #TCQ 'd0;
final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt];
if (|wl_corse_cnt[1][cnt])
// Coarse tap 2 or higher being converted to fine taps
// This will be added to 'smallest' value in final_val
// computation
add_smallest[cnt] <= #TCQ 'd38;
else
// Coarse tap 1 being converted to fine taps
// This will be added to 'smallest' value in
// final_val computation
add_smallest[cnt] <= #TCQ 'd34;
end
end
end
end
end else begin
// Single rank
always @(posedge clk) begin
//coarse_tap_inc <= #TCQ 'd0;
for(w = 0; w < DQS_WIDTH; w = w + 1) begin
final_coarse_tap[w] <= #TCQ wl_corse_cnt[0][w];
add_smallest[w] <= #TCQ 'd0;
add_largest[w] <= #TCQ 'd0;
end
end
end
endgenerate
// Determine delay value for DQS in multirank system
// Assuming delay value is the smallest for rank 0 DQS
// and largest delay value for rank 4 DQS
// Set to smallest + ((largest-smallest)/2)
always @(posedge clk) begin
if (rst) begin
for(x = 0; x < DQS_WIDTH; x = x +1) begin
smallest[x] <= #TCQ 'b0;
largest[x] <= #TCQ 'b0;
end
end else if ((wl_state_r == WL_DQS_CNT) & wrlvl_byte_redo) begin
smallest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r];
largest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r];
end else if ((wl_state_r == WL_DQS_CNT) |
(wl_state_r == WL_2RANK_TAP_DEC)) begin
smallest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r];
largest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[RANKS-1][dqs_count_r];
end else if (((SIM_CAL_OPTION == "FAST_CAL") |
(~oclkdelay_calib_done & ~wrlvl_byte_redo)) &
wr_level_done_r1 & ~wr_level_done_r2) begin
for(i = 0; i < DQS_WIDTH; i = i +1) begin: smallest_dqs
smallest[i] <= #TCQ wl_dqs_tap_count_r[0][i];
largest[i] <= #TCQ wl_dqs_tap_count_r[0][i];
end
end
end
// final_val to be used for all DQSs in all ranks
genvar wr_i;
generate
for (wr_i = 0; wr_i < DQS_WIDTH; wr_i = wr_i +1) begin: gen_final_tap
always @(posedge clk) begin
if (rst)
final_val[wr_i] <= #TCQ 'b0;
else if (wr_level_done_r2 && ~wr_level_done_r3) begin
if (~oclkdelay_calib_done)
final_val[wr_i] <= #TCQ (smallest[wr_i] + add_smallest[wr_i]);
else if ((smallest[wr_i] + add_smallest[wr_i]) <
(largest[wr_i] + add_largest[wr_i]))
final_val[wr_i] <= #TCQ ((smallest[wr_i] + add_smallest[wr_i]) +
(((largest[wr_i] + add_largest[wr_i]) -
(smallest[wr_i] + add_smallest[wr_i]))/2));
else if ((smallest[wr_i] + add_smallest[wr_i]) >
(largest[wr_i] + add_largest[wr_i]))
final_val[wr_i] <= #TCQ ((largest[wr_i] + add_largest[wr_i]) +
(((smallest[wr_i] + add_smallest[wr_i]) -
(largest[wr_i] + add_largest[wr_i]))/2));
else if ((smallest[wr_i] + add_smallest[wr_i]) ==
(largest[wr_i] + add_largest[wr_i]))
final_val[wr_i] <= #TCQ (largest[wr_i] + add_largest[wr_i]);
end
end
end
endgenerate
// // fine tap inc/dec value for all DQSs in all ranks
// genvar dqs_i;
// generate
// for (dqs_i = 0; dqs_i < DQS_WIDTH; dqs_i = dqs_i +1) begin: gen_fine_tap
// always @(posedge clk) begin
// if (rst)
// fine_tap_inc[6*dqs_i+:6] <= #TCQ 'd0;
// //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0;
// else if (wr_level_done_r3 && ~wr_level_done_r4) begin
// fine_tap_inc[6*dqs_i+:6] <= #TCQ final_val[6*dqs_i+:6];
// //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0;
// end
// end
// endgenerate
// Inc/Dec Phaser_Out stage 2 fine delay line
always @(posedge clk) begin
if (rst) begin
// Fine delay line used only during write leveling
dqs_po_stg2_f_incdec <= #TCQ 1'b0;
dqs_po_en_stg2_f <= #TCQ 1'b0;
// Dec Phaser_Out fine delay (1)before write leveling,
// (2)if no 0 to 1 transition detected with 63 fine delay taps, or
// (3)dual rank case where fine taps for the first rank need to be 0
end else if (po_cnt_dec || (wl_state_r == WL_INIT_FINE_DEC) ||
(wl_state_r == WL_FINE_DEC)) begin
dqs_po_stg2_f_incdec <= #TCQ 1'b0;
dqs_po_en_stg2_f <= #TCQ 1'b1;
// Inc Phaser_Out fine delay during write leveling
end else if ((wl_state_r == WL_INIT_FINE_INC) ||
(wl_state_r == WL_FINE_INC)) begin
dqs_po_stg2_f_incdec <= #TCQ 1'b1;
dqs_po_en_stg2_f <= #TCQ 1'b1;
end else begin
dqs_po_stg2_f_incdec <= #TCQ 1'b0;
dqs_po_en_stg2_f <= #TCQ 1'b0;
end
end
// Inc Phaser_Out stage 2 Coarse delay line
always @(posedge clk) begin
if (rst) begin
// Coarse delay line used during write leveling
// only if no 0->1 transition undetected with 64
// fine delay line taps
dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0;
dqs_wl_po_en_stg2_c <= #TCQ 1'b0;
end else if (wl_state_r == WL_CORSE_INC) begin
// Inc Phaser_Out coarse delay during write leveling
dqs_wl_po_stg2_c_incdec <= #TCQ 1'b1;
dqs_wl_po_en_stg2_c <= #TCQ 1'b1;
end else begin
dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0;
dqs_wl_po_en_stg2_c <= #TCQ 1'b0;
end
end
// only storing the rise data for checking. The data comming back during
// write leveling will be a static value. Just checking for rise data is
// enough.
genvar rd_i;
generate
for(rd_i = 0; rd_i < DQS_WIDTH; rd_i = rd_i +1)begin: gen_rd
always @(posedge clk)
rd_data_rise_wl_r[rd_i] <=
#TCQ |rd_data_rise0[(rd_i*DRAM_WIDTH)+DRAM_WIDTH-1:rd_i*DRAM_WIDTH];
end
endgenerate
// storing the previous data for checking later.
always @(posedge clk)begin
if ((wl_state_r == WL_INIT) || //(wl_state_r == WL_INIT_FINE_INC_WAIT) ||
//(wl_state_r == WL_INIT_FINE_INC_WAIT1) ||
((wl_state_r1 == WL_INIT_FINE_INC_WAIT) & (wl_state_r == WL_INIT_FINE_INC)) ||
(wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT1) || (wl_state_r == WL_FINE_DEC_WAIT) ||
(wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) || (wl_state_r == WL_CORSE_INC_WAIT_TMP) ||
(wl_state_r == WL_CORSE_INC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT2) ||
((wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r)))
rd_data_previous_r <= #TCQ rd_data_rise_wl_r;
end
// changed stable count from 3 to 7 because of fine tap resolution
always @(posedge clk)begin
if (rst | (wl_state_r == WL_DQS_CNT) |
(wl_state_r == WL_2RANK_TAP_DEC) |
(wl_state_r == WL_FINE_DEC) |
(rd_data_previous_r[dqs_count_r] != rd_data_rise_wl_r[dqs_count_r]) |
(wl_state_r1 == WL_INIT_FINE_DEC))
stable_cnt <= #TCQ 'd0;
else if ((wl_tap_count_r > 6'd0) &
(((wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r)) |
((wl_state_r1 == WL_INIT_FINE_INC_WAIT) & (wl_state_r == WL_INIT_FINE_INC)))) begin
if ((rd_data_previous_r[dqs_count_r] == rd_data_rise_wl_r[dqs_count_r])
& (stable_cnt < 'd14))
stable_cnt <= #TCQ stable_cnt + 1;
end
end
// Signal to ensure that flag_ck_negedge does not incorrectly assert
// when DQS is very close to CK rising edge
//always @(posedge clk) begin
// if (rst | (wl_state_r == WL_DQS_CNT) |
// (wl_state_r == WL_DQS_CHECK) | wr_level_done_r)
// past_negedge <= #TCQ 1'b0;
// else if (~flag_ck_negedge && ~rd_data_previous_r[dqs_count_r] &&
// (stable_cnt == 'd0) && ((wl_state_r == WL_CORSE_INC_WAIT1) |
// (wl_state_r == WL_CORSE_INC_WAIT2)))
// past_negedge <= #TCQ 1'b1;
//end
// Flag to indicate negedge of CK detected and ignore 0->1 transitions
// in this region
always @(posedge clk)begin
if (rst | (wl_state_r == WL_DQS_CNT) |
(wl_state_r == WL_DQS_CHECK) | wr_level_done_r |
(wl_state_r1 == WL_INIT_FINE_DEC))
flag_ck_negedge <= #TCQ 1'd0;
else if ((rd_data_previous_r[dqs_count_r] && ((stable_cnt > 'd0) |
(wl_state_r == WL_FINE_DEC) | (wl_state_r == WL_FINE_DEC_WAIT) | (wl_state_r == WL_FINE_DEC_WAIT1))) |
(wl_state_r == WL_CORSE_INC))
flag_ck_negedge <= #TCQ 1'd1;
else if (~rd_data_previous_r[dqs_count_r] && (stable_cnt == 'd14))
//&& flag_ck_negedge)
flag_ck_negedge <= #TCQ 1'd0;
end
// Flag to inhibit rd_data_edge_detect_r before stable DQ
always @(posedge clk) begin
if (rst)
flag_init <= #TCQ 1'b1;
else if ((wl_state_r == WL_WAIT) && ((wl_state_r1 == WL_INIT_FINE_INC_WAIT) ||
(wl_state_r1 == WL_INIT_FINE_DEC_WAIT)))
flag_init <= #TCQ 1'b0;
end
//checking for transition from 0 to 1
always @(posedge clk)begin
if (rst | flag_ck_negedge | flag_init | (wl_tap_count_r < 'd1) |
inhibit_edge_detect_r)
rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}};
else if (rd_data_edge_detect_r[dqs_count_r] == 1'b1) begin
if ((wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT) || (wl_state_r == WL_FINE_DEC_WAIT1) ||
(wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) || (wl_state_r == WL_CORSE_INC_WAIT_TMP) ||
(wl_state_r == WL_CORSE_INC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT2))
rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}};
else
rd_data_edge_detect_r <= #TCQ rd_data_edge_detect_r;
end else if (rd_data_previous_r[dqs_count_r] && (stable_cnt < 'd14))
rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}};
else
rd_data_edge_detect_r <= #TCQ (~rd_data_previous_r & rd_data_rise_wl_r);
end
// registring the write level start signal
always@(posedge clk) begin
wr_level_start_r <= #TCQ wr_level_start;
end
// Assign dqs_count_r to dqs_count_w to perform the shift operation
// instead of multiply operation
assign dqs_count_w = {2'b00, dqs_count_r};
assign oclk_count_w = {2'b00, oclkdelay_calib_cnt};
always @(posedge clk) begin
if (rst)
incdec_wait_cnt <= #TCQ 'd0;
else if ((wl_state_r == WL_FINE_DEC_WAIT1) ||
(wl_state_r == WL_INIT_FINE_DEC_WAIT1) ||
(wl_state_r == WL_CORSE_INC_WAIT_TMP))
incdec_wait_cnt <= #TCQ incdec_wait_cnt + 1;
else
incdec_wait_cnt <= #TCQ 'd0;
end
// state machine to initiate the write leveling sequence
// The state machine operates on one byte at a time.
// It will increment the delays to the DQS OSERDES
// and sample the DQ from the memory. When it detects
// a transition from 1 to 0 then the write leveling is considered
// done.
always @(posedge clk) begin
if(rst)begin
wrlvl_err <= #TCQ 1'b0;
wr_level_done_r <= #TCQ 1'b0;
wrlvl_rank_done_r <= #TCQ 1'b0;
dqs_count_r <= #TCQ {DQS_CNT_WIDTH+1{1'b0}};
dq_cnt_inc <= #TCQ 1'b1;
rank_cnt_r <= #TCQ 2'b00;
wl_state_r <= #TCQ WL_IDLE;
wl_state_r1 <= #TCQ WL_IDLE;
inhibit_edge_detect_r <= #TCQ 1'b1;
wl_edge_detect_valid_r <= #TCQ 1'b0;
wl_tap_count_r <= #TCQ 6'd0;
fine_dec_cnt <= #TCQ 6'd0;
for (r = 0; r < DQS_WIDTH; r = r + 1) begin
fine_inc[r] <= #TCQ 6'b0;
corse_dec[r] <= #TCQ 3'b0;
corse_inc[r] <= #TCQ 3'b0;
corse_cnt[r] <= #TCQ 3'b0;
end
dual_rnk_dec <= #TCQ 1'b0;
fast_cal_fine_cnt <= #TCQ FAST_CAL_FINE;
fast_cal_coarse_cnt <= #TCQ FAST_CAL_COARSE;
final_corse_dec <= #TCQ 1'b0;
//zero_tran_r <= #TCQ 1'b0;
wrlvl_redo_corse_inc <= #TCQ 'd0;
end else begin
wl_state_r1 <= #TCQ wl_state_r;
case (wl_state_r)
WL_IDLE: begin
wrlvl_rank_done_r <= #TCQ 1'd0;
inhibit_edge_detect_r <= #TCQ 1'b1;
if (wrlvl_byte_redo && ~wrlvl_byte_redo_r) begin
wr_level_done_r <= #TCQ 1'b0;
dqs_count_r <= #TCQ wrcal_cnt;
corse_cnt[wrcal_cnt] <= #TCQ final_coarse_tap[wrcal_cnt];
wl_tap_count_r <= #TCQ smallest[wrcal_cnt];
if (early1_data &&
(((final_coarse_tap[wrcal_cnt] < 'd6) && (CLK_PERIOD/nCK_PER_CLK <= 2500)) ||
((final_coarse_tap[wrcal_cnt] < 'd3) && (CLK_PERIOD/nCK_PER_CLK > 2500))))
wrlvl_redo_corse_inc <= #TCQ REDO_COARSE;
else if (early2_data && (final_coarse_tap[wrcal_cnt] < 'd2))
wrlvl_redo_corse_inc <= #TCQ 3'd6;
else begin
wl_state_r <= #TCQ WL_IDLE;
wrlvl_err <= #TCQ 1'b1;
end
end else if (wrlvl_final && ~wrlvl_final_r) begin
wr_level_done_r <= #TCQ 1'b0;
dqs_count_r <= #TCQ 'd0;
end
// verilint STARC-2.2.3.3 off
if(!wr_level_done_r & wr_level_start_r & wl_sm_start) begin
if (SIM_CAL_OPTION == "FAST_CAL")
wl_state_r <= #TCQ WL_FINE_INC;
else
wl_state_r <= #TCQ WL_INIT;
end
end
// verilint STARC-2.2.3.3 on
WL_INIT: begin
wl_edge_detect_valid_r <= #TCQ 1'b0;
inhibit_edge_detect_r <= #TCQ 1'b1;
wrlvl_rank_done_r <= #TCQ 1'd0;
//zero_tran_r <= #TCQ 1'b0;
if (wrlvl_final)
corse_cnt[dqs_count_w ] <= #TCQ final_coarse_tap[dqs_count_w ];
if (wrlvl_byte_redo) begin
if (|wl_tap_count_r) begin
wl_state_r <= #TCQ WL_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
end else if ((corse_cnt[dqs_count_w] + wrlvl_redo_corse_inc) <= 'd7)
wl_state_r <= #TCQ WL_CORSE_INC;
else begin
wl_state_r <= #TCQ WL_IDLE;
wrlvl_err <= #TCQ 1'b1;
end
end else if(wl_sm_start)
wl_state_r <= #TCQ WL_INIT_FINE_INC;
end
// Initially Phaser_Out fine delay taps incremented
// until stable_cnt=14. A stable_cnt of 14 indicates
// that rd_data_rise_wl_r=rd_data_previous_r for 14 fine
// tap increments. This is done to inhibit false 0->1
// edge detection when DQS is initially aligned to the
// negedge of CK
WL_INIT_FINE_INC: begin
wl_state_r <= #TCQ WL_INIT_FINE_INC_WAIT1;
wl_tap_count_r <= #TCQ wl_tap_count_r + 1'b1;
final_corse_dec <= #TCQ 1'b0;
end
WL_INIT_FINE_INC_WAIT1: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_INIT_FINE_INC_WAIT;
end
// Case1: stable value of rd_data_previous_r=0 then
// proceed to 0->1 edge detection.
// Case2: stable value of rd_data_previous_r=1 then
// decrement fine taps to '0' and proceed to 0->1
// edge detection. Need to decrement in this case to
// make sure a valid 0->1 transition was not left
// undetected.
WL_INIT_FINE_INC_WAIT: begin
if (wl_sm_start) begin
if (stable_cnt < 'd14)
wl_state_r <= #TCQ WL_INIT_FINE_INC;
else if (~rd_data_previous_r[dqs_count_r]) begin
wl_state_r <= #TCQ WL_WAIT;
inhibit_edge_detect_r <= #TCQ 1'b0;
end else begin
wl_state_r <= #TCQ WL_INIT_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
end
end
end
// Case2: stable value of rd_data_previous_r=1 then
// decrement fine taps to '0' and proceed to 0->1
// edge detection. Need to decrement in this case to
// make sure a valid 0->1 transition was not left
// undetected.
WL_INIT_FINE_DEC: begin
wl_tap_count_r <= #TCQ 'd0;
wl_state_r <= #TCQ WL_INIT_FINE_DEC_WAIT1;
if (fine_dec_cnt > 6'd0)
fine_dec_cnt <= #TCQ fine_dec_cnt - 1;
else
fine_dec_cnt <= #TCQ fine_dec_cnt;
end
WL_INIT_FINE_DEC_WAIT1: begin
if (incdec_wait_cnt == 'd8)
wl_state_r <= #TCQ WL_INIT_FINE_DEC_WAIT;
end
WL_INIT_FINE_DEC_WAIT: begin
if (fine_dec_cnt > 6'd0) begin
wl_state_r <= #TCQ WL_INIT_FINE_DEC;
inhibit_edge_detect_r <= #TCQ 1'b1;
end else begin
wl_state_r <= #TCQ WL_WAIT;
inhibit_edge_detect_r <= #TCQ 1'b0;
end
end
// Inc DQS Phaser_Out Stage2 Fine Delay line
WL_FINE_INC: begin
wl_edge_detect_valid_r <= #TCQ 1'b0;
if (SIM_CAL_OPTION == "FAST_CAL") begin
wl_state_r <= #TCQ WL_FINE_INC_WAIT;
if (fast_cal_fine_cnt > 'd0)
fast_cal_fine_cnt <= #TCQ fast_cal_fine_cnt - 1;
else
fast_cal_fine_cnt <= #TCQ fast_cal_fine_cnt;
end else if (wr_level_done_r5) begin
wl_tap_count_r <= #TCQ 'd0;
wl_state_r <= #TCQ WL_FINE_INC_WAIT;
if (|fine_inc[dqs_count_w])
fine_inc[dqs_count_w] <= #TCQ fine_inc[dqs_count_w] - 1;
end else begin
wl_state_r <= #TCQ WL_WAIT;
wl_tap_count_r <= #TCQ wl_tap_count_r + 1'b1;
end
end
WL_FINE_INC_WAIT: begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
if (fast_cal_fine_cnt > 'd0)
wl_state_r <= #TCQ WL_FINE_INC;
else if (fast_cal_coarse_cnt > 'd0)
wl_state_r <= #TCQ WL_CORSE_INC;
else
wl_state_r <= #TCQ WL_DQS_CNT;
end else if (|fine_inc[dqs_count_w])
wl_state_r <= #TCQ WL_FINE_INC;
else if (dqs_count_r == (DQS_WIDTH-1))
wl_state_r <= #TCQ WL_IDLE;
else begin
wl_state_r <= #TCQ WL_2RANK_FINAL_TAP;
dqs_count_r <= #TCQ dqs_count_r + 1;
end
end
WL_FINE_DEC: begin
wl_edge_detect_valid_r <= #TCQ 1'b0;
wl_tap_count_r <= #TCQ 'd0;
wl_state_r <= #TCQ WL_FINE_DEC_WAIT1;
if (fine_dec_cnt > 6'd0)
fine_dec_cnt <= #TCQ fine_dec_cnt - 1;
else
fine_dec_cnt <= #TCQ fine_dec_cnt;
end
WL_FINE_DEC_WAIT1: begin
if (incdec_wait_cnt == 'd8)
wl_state_r <= #TCQ WL_FINE_DEC_WAIT;
end
WL_FINE_DEC_WAIT: begin
if (fine_dec_cnt > 6'd0)
wl_state_r <= #TCQ WL_FINE_DEC;
//else if (zero_tran_r)
// wl_state_r <= #TCQ WL_DQS_CNT;
else if (dual_rnk_dec) begin
if (|corse_dec[dqs_count_r])
wl_state_r <= #TCQ WL_CORSE_DEC;
else
wl_state_r <= #TCQ WL_2RANK_DQS_CNT;
end else if (wrlvl_byte_redo) begin
if ((corse_cnt[dqs_count_w] + wrlvl_redo_corse_inc) <= 'd7)
wl_state_r <= #TCQ WL_CORSE_INC;
else begin
wl_state_r <= #TCQ WL_IDLE;
wrlvl_err <= #TCQ 1'b1;
end
end else
wl_state_r <= #TCQ WL_CORSE_INC;
end
WL_CORSE_DEC: begin
wl_state_r <= #TCQ WL_CORSE_DEC_WAIT;
dual_rnk_dec <= #TCQ 1'b0;
if (|corse_dec[dqs_count_r])
corse_dec[dqs_count_r] <= #TCQ corse_dec[dqs_count_r] - 1;
else
corse_dec[dqs_count_r] <= #TCQ corse_dec[dqs_count_r];
end
WL_CORSE_DEC_WAIT: begin
if (wl_sm_start) begin
//if (|corse_dec[dqs_count_r])
// wl_state_r <= #TCQ WL_CORSE_DEC;
if (|corse_dec[dqs_count_r])
wl_state_r <= #TCQ WL_CORSE_DEC_WAIT1;
else
wl_state_r <= #TCQ WL_2RANK_DQS_CNT;
end
end
WL_CORSE_DEC_WAIT1: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_CORSE_DEC;
end
WL_CORSE_INC: begin
wl_state_r <= #TCQ WL_CORSE_INC_WAIT_TMP;
if (SIM_CAL_OPTION == "FAST_CAL") begin
if (fast_cal_coarse_cnt > 'd0)
fast_cal_coarse_cnt <= #TCQ fast_cal_coarse_cnt - 1;
else
fast_cal_coarse_cnt <= #TCQ fast_cal_coarse_cnt;
end else if (wrlvl_byte_redo) begin
corse_cnt[dqs_count_w] <= #TCQ corse_cnt[dqs_count_w] + 1;
if (|wrlvl_redo_corse_inc)
wrlvl_redo_corse_inc <= #TCQ wrlvl_redo_corse_inc - 1;
end else if (~wr_level_done_r5)
corse_cnt[dqs_count_r] <= #TCQ corse_cnt[dqs_count_r] + 1;
else if (|corse_inc[dqs_count_w])
corse_inc[dqs_count_w] <= #TCQ corse_inc[dqs_count_w] - 1;
end
WL_CORSE_INC_WAIT_TMP: begin
if (incdec_wait_cnt == 'd8)
wl_state_r <= #TCQ WL_CORSE_INC_WAIT;
end
WL_CORSE_INC_WAIT: begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
if (fast_cal_coarse_cnt > 'd0)
wl_state_r <= #TCQ WL_CORSE_INC;
else
wl_state_r <= #TCQ WL_DQS_CNT;
end else if (wrlvl_byte_redo) begin
if (|wrlvl_redo_corse_inc)
wl_state_r <= #TCQ WL_CORSE_INC;
else begin
wl_state_r <= #TCQ WL_INIT_FINE_INC;
inhibit_edge_detect_r <= #TCQ 1'b1;
end
end else if (~wr_level_done_r5 && wl_sm_start)
wl_state_r <= #TCQ WL_CORSE_INC_WAIT1;
else if (wr_level_done_r5) begin
if (|corse_inc[dqs_count_r])
wl_state_r <= #TCQ WL_CORSE_INC;
else if (|fine_inc[dqs_count_w])
wl_state_r <= #TCQ WL_FINE_INC;
else if (dqs_count_r == (DQS_WIDTH-1))
wl_state_r <= #TCQ WL_IDLE;
else begin
wl_state_r <= #TCQ WL_2RANK_FINAL_TAP;
dqs_count_r <= #TCQ dqs_count_r + 1;
end
end
end
WL_CORSE_INC_WAIT1: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_CORSE_INC_WAIT2;
end
WL_CORSE_INC_WAIT2: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_WAIT;
end
WL_WAIT: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_EDGE_CHECK;
end
WL_EDGE_CHECK: begin // Look for the edge
if (wl_edge_detect_valid_r == 1'b0) begin
wl_state_r <= #TCQ WL_WAIT;
wl_edge_detect_valid_r <= #TCQ 1'b1;
end
// 0->1 transition detected with DQS
else if(rd_data_edge_detect_r[dqs_count_r] &&
wl_edge_detect_valid_r)
begin
wl_tap_count_r <= #TCQ wl_tap_count_r;
if ((SIM_CAL_OPTION == "FAST_CAL") || (RANKS < 2) ||
~oclkdelay_calib_done)
wl_state_r <= #TCQ WL_DQS_CNT;
else
wl_state_r <= #TCQ WL_2RANK_TAP_DEC;
end
// For initial writes check only upto 56 taps. Reserving the
// remaining taps for OCLK calibration.
else if((~wrlvl_tap_done_r) && (wl_tap_count_r > 6'd55)) begin
if (corse_cnt[dqs_count_r] < COARSE_TAPS) begin
wl_state_r <= #TCQ WL_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
end else begin
wrlvl_err <= #TCQ 1'b1;
wl_state_r <= #TCQ WL_IDLE;
end
end else begin
if (wl_tap_count_r < 6'd56) //for reuse wrlvl for complex ocal
wl_state_r <= #TCQ WL_FINE_INC;
else if (corse_cnt[dqs_count_r] < COARSE_TAPS) begin
wl_state_r <= #TCQ WL_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
end else begin
wrlvl_err <= #TCQ 1'b1;
wl_state_r <= #TCQ WL_IDLE;
end
end
end
WL_2RANK_TAP_DEC: begin
wl_state_r <= #TCQ WL_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
for (m = 0; m < DQS_WIDTH; m = m + 1)
corse_dec[m] <= #TCQ corse_cnt[m];
wl_edge_detect_valid_r <= #TCQ 1'b0;
dual_rnk_dec <= #TCQ 1'b1;
end
WL_DQS_CNT: begin
if ((SIM_CAL_OPTION == "FAST_CAL") ||
(dqs_count_r == (DQS_WIDTH-1)) ||
wrlvl_byte_redo) begin
dqs_count_r <= #TCQ dqs_count_r;
dq_cnt_inc <= #TCQ 1'b0;
end else begin
dqs_count_r <= #TCQ dqs_count_r + 1'b1;
dq_cnt_inc <= #TCQ 1'b1;
end
wl_state_r <= #TCQ WL_DQS_CHECK;
wl_edge_detect_valid_r <= #TCQ 1'b0;
end
WL_2RANK_DQS_CNT: begin
if ((SIM_CAL_OPTION == "FAST_CAL") ||
(dqs_count_r == (DQS_WIDTH-1))) begin
dqs_count_r <= #TCQ dqs_count_r;
dq_cnt_inc <= #TCQ 1'b0;
end else begin
dqs_count_r <= #TCQ dqs_count_r + 1'b1;
dq_cnt_inc <= #TCQ 1'b1;
end
wl_state_r <= #TCQ WL_DQS_CHECK;
wl_edge_detect_valid_r <= #TCQ 1'b0;
dual_rnk_dec <= #TCQ 1'b0;
end
WL_DQS_CHECK: begin // check if all DQS have been calibrated
wl_tap_count_r <= #TCQ 'd0;
if (dq_cnt_inc == 1'b0)begin
wrlvl_rank_done_r <= #TCQ 1'd1;
for (t = 0; t < DQS_WIDTH; t = t + 1)
corse_cnt[t] <= #TCQ 3'b0;
if ((SIM_CAL_OPTION == "FAST_CAL") || (RANKS < 2) || ~oclkdelay_calib_done) begin
wl_state_r <= #TCQ WL_IDLE;
if (wrlvl_byte_redo)
dqs_count_r <= #TCQ dqs_count_r;
else
dqs_count_r <= #TCQ 'd0;
end else if (rank_cnt_r == RANKS-1) begin
dqs_count_r <= #TCQ dqs_count_r;
if (RANKS > 1)
wl_state_r <= #TCQ WL_2RANK_FINAL_TAP;
else
wl_state_r <= #TCQ WL_IDLE;
end else begin
wl_state_r <= #TCQ WL_INIT;
dqs_count_r <= #TCQ 'd0;
end
if ((SIM_CAL_OPTION == "FAST_CAL") ||
(rank_cnt_r == RANKS-1)) begin
wr_level_done_r <= #TCQ 1'd1;
rank_cnt_r <= #TCQ 2'b00;
end else begin
wr_level_done_r <= #TCQ 1'd0;
rank_cnt_r <= #TCQ rank_cnt_r + 1'b1;
end
end else
wl_state_r <= #TCQ WL_INIT;
end
WL_2RANK_FINAL_TAP: begin
if (wr_level_done_r4 && ~wr_level_done_r5) begin
for(u = 0; u < DQS_WIDTH; u = u + 1) begin
corse_inc[u] <= #TCQ final_coarse_tap[u];
fine_inc[u] <= #TCQ final_val[u];
end
dqs_count_r <= #TCQ 'd0;
end else if (wr_level_done_r5) begin
if (|corse_inc[dqs_count_r])
wl_state_r <= #TCQ WL_CORSE_INC;
else if (|fine_inc[dqs_count_w])
wl_state_r <= #TCQ WL_FINE_INC;
end
end
endcase
end
end // always @ (posedge clk)
endmodule
|
module SigmaDeltaFast_tb ();
parameter WIDTH = 4;
parameter OUTLEN = (1 << WIDTH);
// UUT Signals
reg clk; ///< System Clock
reg rst; ///< Reset, active high & synchronous
reg en; ///< Enable (use to clock at slower rate)
reg signed [WIDTH-1:0] in;
wire [OUTLEN-1:0] sdOut; ///< Sigma-delta output
// Testbench Signals
wire sdOutComp; ///< Sigma-delta value for comparison
wire [15:0] out; ///< Sinc^3 filtered version of sdOut
reg [OUTLEN-1:0] shiftReg;
integer i;
integer enCount;
always #1 clk = ~clk;
// Strobe every OUTLEN cycles
always @(posedge clk) begin
if (enCount == 0) begin
enCount = OUTLEN-1;
en = 1'b1;
shiftReg = sdOut;
end
else begin
enCount = enCount - 1;
en = 1'b0;
shiftReg = shiftReg >> 1;
end
end
initial begin
shiftReg = 32'hAAAA_AAAA;
enCount = 'd0;
clk = 1'b0;
rst = 1'b1;
en = 1'b0;
in = 'd0;
@(posedge clk) rst = 1'b1;
@(posedge clk) rst = 1'b1;
@(posedge clk) rst = 1'b0;
#10000 in = (2**(WIDTH-1))-1;
#10000 in = -(2**(WIDTH-1));
#10000 in = (2**(WIDTH-2));
#10000 in = -(2**(WIDTH-2));
#10000 in = 0;
for (i=0; i<2**18; i=i+1) begin
@(posedge en) in = $rtoi((2.0**(WIDTH-1)-1)*$sin(3.141259*2.0*($itor(i)/2.0**15 + $itor(i)**2/2.0**22)));
end
#10000 $stop();
end
SigmaDeltaFast #(
.WIDTH(WIDTH),
.OUTLEN(OUTLEN)
)
uut (
.clk(clk), ///< System clock
.rst(rst), ///< Reset, synchronous active high
.en(en), ///< Enable to run the modulator
.in(in), ///< [WIDTH-1:0] Input to modulator
.sdOut(sdOut) ///< [OUTLEN-1:0] Sigma delta stream, LSB=first sample, MSB=last sample
);
SigmaDelta1stOrder #(
.WIDTH(WIDTH)
)
comparison (
.clk(clk),
.rst(rst),
.en(1'b1),
.in(in), ///< [WIDTH-1:0]
.sdOut(sdOutComp)
);
Sinc3Filter #(
.OSR(32) // Output width is 3*ceil(log2(OSR))+1
)
filterOut (
.clk(clk),
.en(1'b1), ///< Enable (use to clock at slower rate)
.in(shiftReg[0]),
.out(out) ///< [3*$clog2(OSR):0]
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [89:0] in;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [89:0] out; // From test of Test.v
wire [44:0] line0;
wire [44:0] line1;
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[89:0]),
.line0 (line0[44:0]),
.line1 (line1[44:0]),
// Inputs
.clk (clk),
.in (in[89:0]));
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d in=%x out=%x\n",$time, cyc, in, out);
`endif
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF;
end
else if (cyc==10) begin
if (in==out) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
$write("*-* Failed!! *-*\n");
$finish;
end
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
line0, line1, out,
// Inputs
clk, in
);
input clk;
input [89:0] in;
output reg [44:0] line0;
output reg [44:0] line1;
output reg [89:0] out;
assign {line0,line1} = in;
always @(posedge clk) begin
out <= {line0,line1};
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:33:36 01/02/2014
// Design Name:
// Module Name: qmults
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module qmults#(
//Parameterized values
parameter Q = 15,
parameter N = 32
)
(
input [N-1:0] i_multiplicand,
input [N-1:0] i_multiplier,
input i_start,
input i_clk,
output [N-1:0] o_result_out,
output o_complete,
output o_overflow
);
reg [2*N-2:0] reg_working_result; // a place to accumulate our result
reg [2*N-2:0] reg_multiplier_temp; // a working copy of the multiplier
reg [N-1:0] reg_multiplicand_temp; // a working copy of the umultiplicand
reg [N-1:0] reg_count; // This is obviously a lot bigger than it needs to be, as we only need
// count to N, but computing that number of bits requires a
// logarithm (base 2), and I don't know how to do that in a
// way that will work for every possibility
reg reg_done; // Computation completed flag
reg reg_sign; // The result's sign bit
reg reg_overflow; // Overflow flag
initial reg_done = 1'b1; // Initial state is to not be doing anything
initial reg_overflow = 1'b0; // And there should be no woverflow present
initial reg_sign = 1'b0; // And the sign should be positive
assign o_result_out[N-2:0] = reg_working_result[N-2+Q:Q]; // The multiplication results
assign o_result_out[N-1] = reg_sign; // The sign of the result
assign o_complete = reg_done; // "Done" flag
assign o_overflow = reg_overflow; // Overflow flag
always @( posedge i_clk ) begin
if( reg_done && i_start ) begin // This is our startup condition
reg_done <= 1'b0; // We're not done
reg_count <= 0; // Reset the count
reg_working_result <= 0; // Clear out the result register
reg_multiplier_temp <= 0; // Clear out the multiplier register
reg_multiplicand_temp <= 0; // Clear out the multiplicand register
reg_overflow <= 1'b0; // Clear the overflow register
reg_multiplicand_temp <= i_multiplicand[N-2:0]; // Load the multiplicand in its working register and lose the sign bit
reg_multiplier_temp <= i_multiplier[N-2:0]; // Load the multiplier into its working register and lose the sign bit
reg_sign <= i_multiplicand[N-1] ^ i_multiplier[N-1]; // Set the sign bit
end
else if (!reg_done) begin
if (reg_multiplicand_temp[reg_count] == 1'b1) // if the appropriate multiplicand bit is 1
reg_working_result <= reg_working_result + reg_multiplier_temp; // then add the temp multiplier
reg_multiplier_temp <= reg_multiplier_temp << 1; // Do a left-shift on the multiplier
reg_count <= reg_count + 1; // Increment the count
//stop condition
if(reg_count == N) begin
reg_done <= 1'b1; // If we're done, it's time to tell the calling process
if (reg_working_result[2*N-2:N-1+Q] > 0) // Check for an overflow
reg_overflow <= 1'b1;
// else
// reg_count <= reg_count + 1; // Increment the count
end
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_wrcal.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Write calibration logic to align DQS to correct CK edge
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_wrcal.v,v 1.1 2011/06/02 08:35:09 mishra Exp $
**$Date: 2011/06/02 08:35:09 $
**$Author:
**$Revision:
**$Source:
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_wrcal #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter CLK_PERIOD = 2500,
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly
parameter SIM_CAL_OPTION = "NONE" // Skip various calibration steps
)
(
input clk,
input rst,
// Calibration status, control signals
input wrcal_start,
input wrcal_rd_wait,
input wrcal_sanity_chk,
input dqsfound_retry_done,
input phy_rddata_en,
output dqsfound_retry,
output wrcal_read_req,
output reg wrcal_act_req,
output reg wrcal_done,
output reg wrcal_pat_err,
output reg wrcal_prech_req,
output reg temp_wrcal_done,
output reg wrcal_sanity_chk_done,
input prech_done,
// Captured data in resync clock domain
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Write level values of Phaser_Out coarse and fine
// delay taps required to load Phaser_Out register
input [3*DQS_WIDTH-1:0] wl_po_coarse_cnt,
input [6*DQS_WIDTH-1:0] wl_po_fine_cnt,
input wrlvl_byte_done,
output reg wrlvl_byte_redo,
output reg early1_data,
output reg early2_data,
// DQ IDELAY
output reg idelay_ld,
output reg wrcal_pat_resume, // to phy_init for write
output reg [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt,
output phy_if_reset,
// Debug Port
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output [99:0] dbg_phy_wrcal
);
// Length of calibration sequence (in # of words)
//localparam CAL_PAT_LEN = 8;
// Read data shift register length
localparam RD_SHIFT_LEN = 1; //(nCK_PER_CLK == 4) ? 1 : 2;
// # of reads for reliable read capture
localparam NUM_READS = 2;
// # of cycles to wait after changing RDEN count value
localparam RDEN_WAIT_CNT = 12;
localparam COARSE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 3 : 6;
localparam FINE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 22 : 44;
localparam CAL2_IDLE = 4'h0;
localparam CAL2_READ_WAIT = 4'h1;
localparam CAL2_NEXT_DQS = 4'h2;
localparam CAL2_WRLVL_WAIT = 4'h3;
localparam CAL2_IFIFO_RESET = 4'h4;
localparam CAL2_DQ_IDEL_DEC = 4'h5;
localparam CAL2_DONE = 4'h6;
localparam CAL2_SANITY_WAIT = 4'h7;
localparam CAL2_ERR = 4'h8;
integer i,j,k,l,m,p,q,d;
reg [2:0] po_coarse_tap_cnt [0:DQS_WIDTH-1];
reg [3*DQS_WIDTH-1:0] po_coarse_tap_cnt_w;
reg [5:0] po_fine_tap_cnt [0:DQS_WIDTH-1];
reg [6*DQS_WIDTH-1:0] po_fine_tap_cnt_w;
reg [DQS_CNT_WIDTH:0] wrcal_dqs_cnt_r/* synthesis syn_maxfan = 10 */;
reg [4:0] not_empty_wait_cnt;
reg [3:0] tap_inc_wait_cnt;
reg cal2_done_r;
reg cal2_done_r1;
reg cal2_prech_req_r;
reg [3:0] cal2_state_r;
reg [3:0] cal2_state_r1;
reg [2:0] wl_po_coarse_cnt_w [0:DQS_WIDTH-1];
reg [5:0] wl_po_fine_cnt_w [0:DQS_WIDTH-1];
reg cal2_if_reset;
reg wrcal_pat_resume_r;
reg wrcal_pat_resume_r1;
reg wrcal_pat_resume_r2;
reg wrcal_pat_resume_r3;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r;
reg pat_data_match_r;
reg pat1_data_match_r;
reg pat1_data_match_r1;
reg pat2_data_match_r;
reg pat_data_match_valid_r;
wire [RD_SHIFT_LEN-1:0] pat_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_fall1 [3:0];
reg [DRAM_WIDTH-1:0] pat_match_fall0_r;
reg pat_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall1_r;
reg pat_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall2_r;
reg pat_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall3_r;
reg pat_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise0_r;
reg pat_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise1_r;
reg pat_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise2_r;
reg pat_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise3_r;
reg pat_match_rise3_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise0_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise1_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall0_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall1_r;
reg [DRAM_WIDTH-1:0] pat2_match_rise0_r;
reg [DRAM_WIDTH-1:0] pat2_match_rise1_r;
reg [DRAM_WIDTH-1:0] pat2_match_fall0_r;
reg [DRAM_WIDTH-1:0] pat2_match_fall1_r;
reg pat1_match_rise0_and_r;
reg pat1_match_rise1_and_r;
reg pat1_match_fall0_and_r;
reg pat1_match_fall1_and_r;
reg pat2_match_rise0_and_r;
reg pat2_match_rise1_and_r;
reg pat2_match_fall0_and_r;
reg pat2_match_fall1_and_r;
reg early1_data_match_r;
reg early1_data_match_r1;
reg [DRAM_WIDTH-1:0] early1_match_fall0_r;
reg early1_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall1_r;
reg early1_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall2_r;
reg early1_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall3_r;
reg early1_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise0_r;
reg early1_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise1_r;
reg early1_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise2_r;
reg early1_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise3_r;
reg early1_match_rise3_and_r;
reg early2_data_match_r;
reg [DRAM_WIDTH-1:0] early2_match_fall0_r;
reg early2_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall1_r;
reg early2_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall2_r;
reg early2_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall3_r;
reg early2_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise0_r;
reg early2_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise1_r;
reg early2_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise2_r;
reg early2_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise3_r;
reg early2_match_rise3_and_r;
wire [RD_SHIFT_LEN-1:0] pat_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_rise1 [3:0];
wire [DQ_WIDTH-1:0] rd_data_rise0;
wire [DQ_WIDTH-1:0] rd_data_fall0;
wire [DQ_WIDTH-1:0] rd_data_rise1;
wire [DQ_WIDTH-1:0] rd_data_fall1;
wire [DQ_WIDTH-1:0] rd_data_rise2;
wire [DQ_WIDTH-1:0] rd_data_fall2;
wire [DQ_WIDTH-1:0] rd_data_rise3;
wire [DQ_WIDTH-1:0] rd_data_fall3;
reg [DQS_CNT_WIDTH:0] rd_mux_sel_r;
reg rd_active_posedge_r;
reg rd_active_r;
reg rd_active_r1;
reg rd_active_r2;
reg rd_active_r3;
reg rd_active_r4;
reg rd_active_r5;
reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0];
reg wrlvl_byte_done_r;
reg idelay_ld_done;
reg pat1_detect;
reg early1_detect;
reg wrcal_sanity_chk_r;
reg wrcal_sanity_chk_err;
//***************************************************************************
// Debug
//***************************************************************************
always @(*) begin
for (d = 0; d < DQS_WIDTH; d = d + 1) begin
po_fine_tap_cnt_w[(6*d)+:6] = po_fine_tap_cnt[d];
po_coarse_tap_cnt_w[(3*d)+:3] = po_coarse_tap_cnt[d];
end
end
assign dbg_final_po_fine_tap_cnt = po_fine_tap_cnt_w;
assign dbg_final_po_coarse_tap_cnt = po_coarse_tap_cnt_w;
assign dbg_phy_wrcal[0] = pat_data_match_r;
assign dbg_phy_wrcal[4:1] = cal2_state_r1[3:0];
assign dbg_phy_wrcal[5] = wrcal_sanity_chk_err;
assign dbg_phy_wrcal[6] = wrcal_start;
assign dbg_phy_wrcal[7] = wrcal_done;
assign dbg_phy_wrcal[8] = pat_data_match_valid_r;
assign dbg_phy_wrcal[13+:DQS_CNT_WIDTH]= wrcal_dqs_cnt_r;
assign dbg_phy_wrcal[17+:5] = not_empty_wait_cnt;
assign dbg_phy_wrcal[22] = early1_data;
assign dbg_phy_wrcal[23] = early2_data;
assign dbg_phy_wrcal[24+:8] = mux_rd_rise0_r;
assign dbg_phy_wrcal[32+:8] = mux_rd_fall0_r;
assign dbg_phy_wrcal[40+:8] = mux_rd_rise1_r;
assign dbg_phy_wrcal[48+:8] = mux_rd_fall1_r;
assign dbg_phy_wrcal[56+:8] = mux_rd_rise2_r;
assign dbg_phy_wrcal[64+:8] = mux_rd_fall2_r;
assign dbg_phy_wrcal[72+:8] = mux_rd_rise3_r;
assign dbg_phy_wrcal[80+:8] = mux_rd_fall3_r;
assign dbg_phy_wrcal[88] = early1_data_match_r;
assign dbg_phy_wrcal[89] = early2_data_match_r;
assign dbg_phy_wrcal[90] = wrcal_sanity_chk_r & pat_data_match_valid_r;
assign dbg_phy_wrcal[91] = wrcal_sanity_chk_r;
assign dbg_phy_wrcal[92] = wrcal_sanity_chk_done;
assign dqsfound_retry = 1'b0;
assign wrcal_read_req = 1'b0;
assign phy_if_reset = cal2_if_reset;
//**************************************************************************
// DQS count to hard PHY during write calibration using Phaser_OUT Stage2
// coarse delay
//**************************************************************************
always @(posedge clk) begin
po_stg2_wrcal_cnt <= #TCQ wrcal_dqs_cnt_r;
wrlvl_byte_done_r <= #TCQ wrlvl_byte_done;
wrcal_sanity_chk_r <= #TCQ wrcal_sanity_chk;
end
//***************************************************************************
// Data mux to route appropriate byte to calibration logic - i.e. calibration
// is done sequentially, one byte (or DQS group) at a time
//***************************************************************************
generate
if (nCK_PER_CLK == 4) begin: gen_rd_data_div4
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
end else if (nCK_PER_CLK == 2) begin: gen_rd_data_div2
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
end
endgenerate
//**************************************************************************
// Final Phaser OUT coarse and fine delay taps after write calibration
// Sum of taps used during write leveling taps and write calibration
//**************************************************************************
always @(*) begin
for (m = 0; m < DQS_WIDTH; m = m + 1) begin
wl_po_coarse_cnt_w[m] = wl_po_coarse_cnt[3*m+:3];
wl_po_fine_cnt_w[m] = wl_po_fine_cnt[6*m+:6];
end
end
always @(posedge clk) begin
if (rst) begin
for (p = 0; p < DQS_WIDTH; p = p + 1) begin
po_coarse_tap_cnt[p] <= #TCQ {3{1'b0}};
po_fine_tap_cnt[p] <= #TCQ {6{1'b0}};
end
end else if (cal2_done_r && ~cal2_done_r1) begin
for (q = 0; q < DQS_WIDTH; q = q + 1) begin
po_coarse_tap_cnt[q] <= #TCQ wl_po_coarse_cnt_w[i];
po_fine_tap_cnt[q] <= #TCQ wl_po_fine_cnt_w[i];
end
end
end
always @(posedge clk) begin
rd_mux_sel_r <= #TCQ wrcal_dqs_cnt_r;
end
// Register outputs for improved timing.
// NOTE: Will need to change when per-bit DQ deskew is supported.
// Currenly all bits in DQS group are checked in aggregate
generate
genvar mux_i;
if (nCK_PER_CLK == 4) begin: gen_mux_rd_div4
for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
always @(posedge clk) begin
mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
end
end
end else if (nCK_PER_CLK == 2) begin: gen_mux_rd_div2
for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
always @(posedge clk) begin
mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
end
end
end
endgenerate
//***************************************************************************
// generate request to PHY_INIT logic to issue precharged. Required when
// calibration can take a long time (during which there are only constant
// reads present on this bus). In this case need to issue perioidic
// precharges to avoid tRAS violation. This signal must meet the following
// requirements: (1) only transition from 0->1 when prech is first needed,
// (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted
//***************************************************************************
always @(posedge clk)
if (rst)
wrcal_prech_req <= #TCQ 1'b0;
else
// Combine requests from all stages here
wrcal_prech_req <= #TCQ cal2_prech_req_r;
//***************************************************************************
// Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES
// NOTE: Written using discrete flops, but SRL can be used if the matching
// logic does the comparison sequentially, rather than parallel
//***************************************************************************
generate
genvar rd_i;
if (nCK_PER_CLK == 4) begin: gen_sr_div4
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];
sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];
sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];
sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];
sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i];
sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i];
sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i];
sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i];
end
end
end else if (nCK_PER_CLK == 2) begin: gen_sr_div2
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];
sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];
sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];
sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];
end
end
end
endgenerate
//***************************************************************************
// Write calibration:
// During write leveling DQS is aligned to the nearest CK edge that may not
// be the correct CK edge. Write calibration is required to align the DQS to
// the correct CK edge that clocks the write command.
// The Phaser_Out coarse delay line is adjusted if required to add a memory
// clock cycle of delay in order to read back the expected pattern.
//***************************************************************************
always @(posedge clk) begin
rd_active_r <= #TCQ phy_rddata_en;
rd_active_r1 <= #TCQ rd_active_r;
rd_active_r2 <= #TCQ rd_active_r1;
rd_active_r3 <= #TCQ rd_active_r2;
rd_active_r4 <= #TCQ rd_active_r3;
rd_active_r5 <= #TCQ rd_active_r4;
end
//*****************************************************************
// Expected data pattern when properly received by read capture
// logic:
// Based on pattern of ({rise,fall}) =
// 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6
// Each nibble will look like:
// bit3: 1, 0, 1, 0, 0, 1, 1, 0
// bit2: 1, 0, 0, 1, 1, 0, 0, 1
// bit1: 1, 0, 1, 0, 0, 1, 0, 1
// bit0: 1, 0, 0, 1, 1, 0, 1, 0
// Change the hard-coded pattern below accordingly as RD_SHIFT_LEN
// and the actual training pattern contents change
//*****************************************************************
generate
if (nCK_PER_CLK == 4) begin: gen_pat_div4
// FF00AA5555AA9966
assign pat_rise0[3] = 1'b1;
assign pat_fall0[3] = 1'b0;
assign pat_rise1[3] = 1'b1;
assign pat_fall1[3] = 1'b0;
assign pat_rise2[3] = 1'b0;
assign pat_fall2[3] = 1'b1;
assign pat_rise3[3] = 1'b1;
assign pat_fall3[3] = 1'b0;
assign pat_rise0[2] = 1'b1;
assign pat_fall0[2] = 1'b0;
assign pat_rise1[2] = 1'b0;
assign pat_fall1[2] = 1'b1;
assign pat_rise2[2] = 1'b1;
assign pat_fall2[2] = 1'b0;
assign pat_rise3[2] = 1'b0;
assign pat_fall3[2] = 1'b1;
assign pat_rise0[1] = 1'b1;
assign pat_fall0[1] = 1'b0;
assign pat_rise1[1] = 1'b1;
assign pat_fall1[1] = 1'b0;
assign pat_rise2[1] = 1'b0;
assign pat_fall2[1] = 1'b1;
assign pat_rise3[1] = 1'b0;
assign pat_fall3[1] = 1'b1;
assign pat_rise0[0] = 1'b1;
assign pat_fall0[0] = 1'b0;
assign pat_rise1[0] = 1'b0;
assign pat_fall1[0] = 1'b1;
assign pat_rise2[0] = 1'b1;
assign pat_fall2[0] = 1'b0;
assign pat_rise3[0] = 1'b1;
assign pat_fall3[0] = 1'b0;
// Pattern to distinguish between early write and incorrect read
// BB11EE4444EEDD88
assign early_rise0[3] = 1'b1;
assign early_fall0[3] = 1'b0;
assign early_rise1[3] = 1'b1;
assign early_fall1[3] = 1'b0;
assign early_rise2[3] = 1'b0;
assign early_fall2[3] = 1'b1;
assign early_rise3[3] = 1'b1;
assign early_fall3[3] = 1'b1;
assign early_rise0[2] = 1'b0;
assign early_fall0[2] = 1'b0;
assign early_rise1[2] = 1'b1;
assign early_fall1[2] = 1'b1;
assign early_rise2[2] = 1'b1;
assign early_fall2[2] = 1'b1;
assign early_rise3[2] = 1'b1;
assign early_fall3[2] = 1'b0;
assign early_rise0[1] = 1'b1;
assign early_fall0[1] = 1'b0;
assign early_rise1[1] = 1'b1;
assign early_fall1[1] = 1'b0;
assign early_rise2[1] = 1'b0;
assign early_fall2[1] = 1'b1;
assign early_rise3[1] = 1'b0;
assign early_fall3[1] = 1'b0;
assign early_rise0[0] = 1'b1;
assign early_fall0[0] = 1'b1;
assign early_rise1[0] = 1'b0;
assign early_fall1[0] = 1'b0;
assign early_rise2[0] = 1'b0;
assign early_fall2[0] = 1'b0;
assign early_rise3[0] = 1'b1;
assign early_fall3[0] = 1'b0;
end else if (nCK_PER_CLK == 2) begin: gen_pat_div2
// First cycle pattern FF00AA55
assign pat1_rise0[3] = 1'b1;
assign pat1_fall0[3] = 1'b0;
assign pat1_rise1[3] = 1'b1;
assign pat1_fall1[3] = 1'b0;
assign pat1_rise0[2] = 1'b1;
assign pat1_fall0[2] = 1'b0;
assign pat1_rise1[2] = 1'b0;
assign pat1_fall1[2] = 1'b1;
assign pat1_rise0[1] = 1'b1;
assign pat1_fall0[1] = 1'b0;
assign pat1_rise1[1] = 1'b1;
assign pat1_fall1[1] = 1'b0;
assign pat1_rise0[0] = 1'b1;
assign pat1_fall0[0] = 1'b0;
assign pat1_rise1[0] = 1'b0;
assign pat1_fall1[0] = 1'b1;
// Second cycle pattern 55AA9966
assign pat2_rise0[3] = 1'b0;
assign pat2_fall0[3] = 1'b1;
assign pat2_rise1[3] = 1'b1;
assign pat2_fall1[3] = 1'b0;
assign pat2_rise0[2] = 1'b1;
assign pat2_fall0[2] = 1'b0;
assign pat2_rise1[2] = 1'b0;
assign pat2_fall1[2] = 1'b1;
assign pat2_rise0[1] = 1'b0;
assign pat2_fall0[1] = 1'b1;
assign pat2_rise1[1] = 1'b0;
assign pat2_fall1[1] = 1'b1;
assign pat2_rise0[0] = 1'b1;
assign pat2_fall0[0] = 1'b0;
assign pat2_rise1[0] = 1'b1;
assign pat2_fall1[0] = 1'b0;
//Pattern to distinguish between early write and incorrect read
// First cycle pattern AA5555AA
assign early1_rise0[3] = 2'b1;
assign early1_fall0[3] = 2'b0;
assign early1_rise1[3] = 2'b0;
assign early1_fall1[3] = 2'b1;
assign early1_rise0[2] = 2'b0;
assign early1_fall0[2] = 2'b1;
assign early1_rise1[2] = 2'b1;
assign early1_fall1[2] = 2'b0;
assign early1_rise0[1] = 2'b1;
assign early1_fall0[1] = 2'b0;
assign early1_rise1[1] = 2'b0;
assign early1_fall1[1] = 2'b1;
assign early1_rise0[0] = 2'b0;
assign early1_fall0[0] = 2'b1;
assign early1_rise1[0] = 2'b1;
assign early1_fall1[0] = 2'b0;
// Second cycle pattern 9966BB11
assign early2_rise0[3] = 2'b1;
assign early2_fall0[3] = 2'b0;
assign early2_rise1[3] = 2'b1;
assign early2_fall1[3] = 2'b0;
assign early2_rise0[2] = 2'b0;
assign early2_fall0[2] = 2'b1;
assign early2_rise1[2] = 2'b0;
assign early2_fall1[2] = 2'b0;
assign early2_rise0[1] = 2'b0;
assign early2_fall0[1] = 2'b1;
assign early2_rise1[1] = 2'b1;
assign early2_fall1[1] = 2'b0;
assign early2_rise0[0] = 2'b1;
assign early2_fall0[0] = 2'b0;
assign early2_rise1[0] = 2'b1;
assign early2_fall1[0] = 2'b1;
end
endgenerate
// Each bit of each byte is compared to expected pattern.
// This was done to prevent (and "drastically decrease") the chance that
// invalid data clocked in when the DQ bus is tri-state (along with a
// combination of the correct data) will resemble the expected data
// pattern. A better fix for this is to change the training pattern and/or
// make the pattern longer.
generate
genvar pt_i;
if (nCK_PER_CLK == 4) begin: gen_pat_match_div4
for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise0[pt_i%4])
pat_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall0[pt_i%4])
pat_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise1[pt_i%4])
pat_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall1[pt_i%4])
pat_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == pat_rise2[pt_i%4])
pat_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat_fall2[pt_i%4])
pat_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == pat_rise3[pt_i%4])
pat_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == pat_fall3[pt_i%4])
pat_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise1[pt_i%4])
early1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall1[pt_i%4])
early1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise2[pt_i%4])
early1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall2[pt_i%4])
early1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == pat_rise3[pt_i%4])
early1_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat_fall3[pt_i%4])
early1_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == early_rise0[pt_i%4])
early1_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == early_fall0[pt_i%4])
early1_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise2[pt_i%4])
early2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall2[pt_i%4])
early2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise3[pt_i%4])
early2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall3[pt_i%4])
early2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == early_rise0[pt_i%4])
early2_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == early_fall0[pt_i%4])
early2_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == early_rise1[pt_i%4])
early2_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == early_fall1[pt_i%4])
early2_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
pat_match_rise0_and_r <= #TCQ &pat_match_rise0_r;
pat_match_fall0_and_r <= #TCQ &pat_match_fall0_r;
pat_match_rise1_and_r <= #TCQ &pat_match_rise1_r;
pat_match_fall1_and_r <= #TCQ &pat_match_fall1_r;
pat_match_rise2_and_r <= #TCQ &pat_match_rise2_r;
pat_match_fall2_and_r <= #TCQ &pat_match_fall2_r;
pat_match_rise3_and_r <= #TCQ &pat_match_rise3_r;
pat_match_fall3_and_r <= #TCQ &pat_match_fall3_r;
pat_data_match_r <= #TCQ (pat_match_rise0_and_r &&
pat_match_fall0_and_r &&
pat_match_rise1_and_r &&
pat_match_fall1_and_r &&
pat_match_rise2_and_r &&
pat_match_fall2_and_r &&
pat_match_rise3_and_r &&
pat_match_fall3_and_r);
pat_data_match_valid_r <= #TCQ rd_active_r3;
end
always @(posedge clk) begin
early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r;
early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r;
early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r;
early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r;
early1_match_rise2_and_r <= #TCQ &early1_match_rise2_r;
early1_match_fall2_and_r <= #TCQ &early1_match_fall2_r;
early1_match_rise3_and_r <= #TCQ &early1_match_rise3_r;
early1_match_fall3_and_r <= #TCQ &early1_match_fall3_r;
early1_data_match_r <= #TCQ (early1_match_rise0_and_r &&
early1_match_fall0_and_r &&
early1_match_rise1_and_r &&
early1_match_fall1_and_r &&
early1_match_rise2_and_r &&
early1_match_fall2_and_r &&
early1_match_rise3_and_r &&
early1_match_fall3_and_r);
end
always @(posedge clk) begin
early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r;
early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r;
early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r;
early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r;
early2_match_rise2_and_r <= #TCQ &early2_match_rise2_r;
early2_match_fall2_and_r <= #TCQ &early2_match_fall2_r;
early2_match_rise3_and_r <= #TCQ &early2_match_rise3_r;
early2_match_fall3_and_r <= #TCQ &early2_match_fall3_r;
early2_data_match_r <= #TCQ (early2_match_rise0_and_r &&
early2_match_fall0_and_r &&
early2_match_rise1_and_r &&
early2_match_fall1_and_r &&
early2_match_rise2_and_r &&
early2_match_fall2_and_r &&
early2_match_rise3_and_r &&
early2_match_fall3_and_r);
end
end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2
for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4])
pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4])
pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4])
pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4])
pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat2_rise0[pt_i%4])
pat2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat2_fall0[pt_i%4])
pat2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat2_rise1[pt_i%4])
pat2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat2_fall1[pt_i%4])
pat2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == early1_rise0[pt_i%4])
early1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == early1_fall0[pt_i%4])
early1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == early1_rise1[pt_i%4])
early1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == early1_fall1[pt_i%4])
early1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
// early2 in this case does not mean 2 cycles early but
// the second cycle of read data in 2:1 mode
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == early2_rise0[pt_i%4])
early2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == early2_fall0[pt_i%4])
early2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == early2_rise1[pt_i%4])
early2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == early2_fall1[pt_i%4])
early2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r;
pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r;
pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r;
pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r;
pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r &&
pat1_match_fall0_and_r &&
pat1_match_rise1_and_r &&
pat1_match_fall1_and_r);
pat1_data_match_r1 <= #TCQ pat1_data_match_r;
pat2_match_rise0_and_r <= #TCQ &pat2_match_rise0_r && rd_active_r3;
pat2_match_fall0_and_r <= #TCQ &pat2_match_fall0_r && rd_active_r3;
pat2_match_rise1_and_r <= #TCQ &pat2_match_rise1_r && rd_active_r3;
pat2_match_fall1_and_r <= #TCQ &pat2_match_fall1_r && rd_active_r3;
pat2_data_match_r <= #TCQ (pat2_match_rise0_and_r &&
pat2_match_fall0_and_r &&
pat2_match_rise1_and_r &&
pat2_match_fall1_and_r);
// For 2:1 mode, read valid is asserted for 2 clock cycles -
// here we generate a "match valid" pulse that is only 1 clock
// cycle wide that is simulatenous when the match calculation
// is complete
pat_data_match_valid_r <= #TCQ rd_active_r4 & ~rd_active_r5;
end
always @(posedge clk) begin
early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r;
early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r;
early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r;
early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r;
early1_data_match_r <= #TCQ (early1_match_rise0_and_r &&
early1_match_fall0_and_r &&
early1_match_rise1_and_r &&
early1_match_fall1_and_r);
early1_data_match_r1 <= #TCQ early1_data_match_r;
early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r && rd_active_r3;
early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r && rd_active_r3;
early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r && rd_active_r3;
early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r && rd_active_r3;
early2_data_match_r <= #TCQ (early2_match_rise0_and_r &&
early2_match_fall0_and_r &&
early2_match_rise1_and_r &&
early2_match_fall1_and_r);
end
end
endgenerate
// Need to delay it by 3 cycles in order to wait for Phaser_Out
// coarse delay to take effect before issuing a write command
always @(posedge clk) begin
wrcal_pat_resume_r1 <= #TCQ wrcal_pat_resume_r;
wrcal_pat_resume_r2 <= #TCQ wrcal_pat_resume_r1;
wrcal_pat_resume <= #TCQ wrcal_pat_resume_r2;
end
always @(posedge clk) begin
if (rst)
tap_inc_wait_cnt <= #TCQ 'd0;
else if ((cal2_state_r == CAL2_DQ_IDEL_DEC) ||
(cal2_state_r == CAL2_IFIFO_RESET) ||
(cal2_state_r == CAL2_SANITY_WAIT))
tap_inc_wait_cnt <= #TCQ tap_inc_wait_cnt + 1;
else
tap_inc_wait_cnt <= #TCQ 'd0;
end
always @(posedge clk) begin
if (rst)
not_empty_wait_cnt <= #TCQ 'd0;
else if ((cal2_state_r == CAL2_READ_WAIT) && wrcal_rd_wait)
not_empty_wait_cnt <= #TCQ not_empty_wait_cnt + 1;
else
not_empty_wait_cnt <= #TCQ 'd0;
end
always @(posedge clk)
cal2_state_r1 <= #TCQ cal2_state_r;
//*****************************************************************
// Write Calibration state machine
//*****************************************************************
// when calibrating, check to see if the expected pattern is received.
// Otherwise delay DQS to align to correct CK edge.
// NOTES:
// 1. An error condition can occur due to two reasons:
// a. If the matching logic does not receive the expected data
// pattern. However, the error may be "recoverable" because
// the write calibration is still in progress. If an error is
// found the write calibration logic delays DQS by an additional
// clock cycle and restarts the pattern detection process.
// By design, if the write path timing is incorrect, the correct
// data pattern will never be detected.
// b. Valid data not found even after incrementing Phaser_Out
// coarse delay line.
always @(posedge clk) begin
if (rst) begin
wrcal_dqs_cnt_r <= #TCQ 'b0;
cal2_done_r <= #TCQ 1'b0;
cal2_prech_req_r <= #TCQ 1'b0;
cal2_state_r <= #TCQ CAL2_IDLE;
wrcal_pat_err <= #TCQ 1'b0;
wrcal_pat_resume_r <= #TCQ 1'b0;
wrcal_act_req <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
temp_wrcal_done <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b0;
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b0;
idelay_ld <= #TCQ 1'b0;
idelay_ld_done <= #TCQ 1'b0;
pat1_detect <= #TCQ 1'b0;
early1_detect <= #TCQ 1'b0;
wrcal_sanity_chk_done <= #TCQ 1'b0;
wrcal_sanity_chk_err <= #TCQ 1'b0;
end else begin
cal2_prech_req_r <= #TCQ 1'b0;
case (cal2_state_r)
CAL2_IDLE: begin
wrcal_pat_err <= #TCQ 1'b0;
if (wrcal_start) begin
cal2_if_reset <= #TCQ 1'b0;
if (SIM_CAL_OPTION == "SKIP_CAL")
// If skip write calibration, then proceed to end.
cal2_state_r <= #TCQ CAL2_DONE;
else
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end
end
// General wait state to wait for read data to be output by the
// IN_FIFO
CAL2_READ_WAIT: begin
wrcal_pat_resume_r <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
// Wait until read data is received, and pattern matching
// calculation is complete. NOTE: Need to add a timeout here
// in case for some reason data is never received (or rather
// the PHASER_IN and IN_FIFO think they never receives data)
if (pat_data_match_valid_r && (nCK_PER_CLK == 4)) begin
if (pat_data_match_r)
// If found data match, then move on to next DQS group
cal2_state_r <= #TCQ CAL2_NEXT_DQS;
else begin
if (wrcal_sanity_chk_r)
cal2_state_r <= #TCQ CAL2_ERR;
// If writes are one or two cycles early then redo
// write leveling for the byte
else if (early1_data_match_r) begin
early1_data <= #TCQ 1'b1;
early2_data <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
end else if (early2_data_match_r) begin
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b1;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
// Read late due to incorrect MPR idelay value
// Decrement Idelay to '0'for the current byte
end else if (~idelay_ld_done) begin
cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC;
idelay_ld <= #TCQ 1'b1;
end else
cal2_state_r <= #TCQ CAL2_ERR;
end
end else if (pat_data_match_valid_r && (nCK_PER_CLK == 2)) begin
if ((pat1_data_match_r1 && pat2_data_match_r) ||
(pat1_detect && pat2_data_match_r))
// If found data match, then move on to next DQS group
cal2_state_r <= #TCQ CAL2_NEXT_DQS;
else if (pat1_data_match_r1 && ~pat2_data_match_r) begin
cal2_state_r <= #TCQ CAL2_READ_WAIT;
pat1_detect <= #TCQ 1'b1;
end else begin
// If writes are one or two cycles early then redo
// write leveling for the byte
if (wrcal_sanity_chk_r)
cal2_state_r <= #TCQ CAL2_ERR;
else if ((early1_data_match_r1 && early2_data_match_r) ||
(early1_detect && early2_data_match_r)) begin
early1_data <= #TCQ 1'b1;
early2_data <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
end else if (early1_data_match_r1 && ~early2_data_match_r) begin
early1_detect <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
// Read late due to incorrect MPR idelay value
// Decrement Idelay to '0'for the current byte
end else if (~idelay_ld_done) begin
cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC;
idelay_ld <= #TCQ 1'b1;
end else
cal2_state_r <= #TCQ CAL2_ERR;
end
end else if (not_empty_wait_cnt == 'd31)
cal2_state_r <= #TCQ CAL2_ERR;
end
CAL2_WRLVL_WAIT: begin
early1_detect <= #TCQ 1'b0;
if (wrlvl_byte_done && ~wrlvl_byte_done_r)
wrlvl_byte_redo <= #TCQ 1'b0;
if (wrlvl_byte_done) begin
if (rd_active_r1 && ~rd_active_r) begin
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
cal2_if_reset <= #TCQ 1'b1;
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b0;
end
end
end
CAL2_DQ_IDEL_DEC: begin
if (tap_inc_wait_cnt == 'd4) begin
idelay_ld <= #TCQ 1'b0;
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
cal2_if_reset <= #TCQ 1'b1;
idelay_ld_done <= #TCQ 1'b1;
end
end
CAL2_IFIFO_RESET: begin
if (tap_inc_wait_cnt == 'd15) begin
cal2_if_reset <= #TCQ 1'b0;
if (wrcal_sanity_chk_r)
cal2_state_r <= #TCQ CAL2_DONE;
else if (idelay_ld_done) begin
wrcal_pat_resume_r <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end else
cal2_state_r <= #TCQ CAL2_IDLE;
end
end
// Final processing for current DQS group. Move on to next group
CAL2_NEXT_DQS: begin
// At this point, we've just found the correct pattern for the
// current DQS group.
// Request bank/row precharge, and wait for its completion. Always
// precharge after each DQS group to avoid tRAS(max) violation
//verilint STARC-2.2.3.3 off
if (wrcal_sanity_chk_r && (wrcal_dqs_cnt_r != DQS_WIDTH-1)) begin
cal2_prech_req_r <= #TCQ 1'b0;
wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1;
cal2_state_r <= #TCQ CAL2_SANITY_WAIT;
end else
cal2_prech_req_r <= #TCQ 1'b1;
idelay_ld_done <= #TCQ 1'b0;
pat1_detect <= #TCQ 1'b0;
if (prech_done)
if (((DQS_WIDTH == 1) || (SIM_CAL_OPTION == "FAST_CAL")) ||
(wrcal_dqs_cnt_r == DQS_WIDTH-1)) begin
// If either FAST_CAL is enabled and first DQS group is
// finished, or if the last DQS group was just finished,
// then end of write calibration
if (wrcal_sanity_chk_r) begin
cal2_if_reset <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
end else
cal2_state_r <= #TCQ CAL2_DONE;
end else begin
// Continue to next DQS group
wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end
end
//verilint STARC-2.2.3.3 on
CAL2_SANITY_WAIT: begin
if (tap_inc_wait_cnt == 'd15) begin
cal2_state_r <= #TCQ CAL2_READ_WAIT;
wrcal_pat_resume_r <= #TCQ 1'b1;
end
end
// Finished with read enable calibration
CAL2_DONE: begin
if (wrcal_sanity_chk && ~wrcal_sanity_chk_r) begin
cal2_done_r <= #TCQ 1'b0;
wrcal_dqs_cnt_r <= #TCQ 'd0;
cal2_state_r <= #TCQ CAL2_IDLE;
end else
cal2_done_r <= #TCQ 1'b1;
cal2_prech_req_r <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
if (wrcal_sanity_chk_r)
wrcal_sanity_chk_done <= #TCQ 1'b1;
end
// Assert error signal indicating that writes timing is incorrect
CAL2_ERR: begin
wrcal_pat_resume_r <= #TCQ 1'b0;
if (wrcal_sanity_chk_r)
wrcal_sanity_chk_err <= #TCQ 1'b1;
else
wrcal_pat_err <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_ERR;
end
endcase
end
end
// Delay assertion of wrcal_done for write calibration by a few cycles after
// we've reached CAL2_DONE
always @(posedge clk)
if (rst)
cal2_done_r1 <= #TCQ 1'b0;
else
cal2_done_r1 <= #TCQ cal2_done_r;
always @(posedge clk)
if (rst || (wrcal_sanity_chk && ~wrcal_sanity_chk_r))
wrcal_done <= #TCQ 1'b0;
else if (cal2_done_r)
wrcal_done <= #TCQ 1'b1;
endmodule
|
module convert_30to15_fifo(
input wire rst, // reset
input wire clk, // clock input
input wire clkx2, // 2x clock input
input wire [29:0] datain, // input data for 2:1 serialisation
output wire [14:0] dataout); // 5-bit data out
////////////////////////////////////////////////////
// Here we instantiate a 16x10 Dual Port RAM
// and fill first it with data aligned to
// clk domain
////////////////////////////////////////////////////
wire [3:0] wa; // RAM read address
reg [3:0] wa_d; // RAM read address
wire [3:0] ra; // RAM read address
reg [3:0] ra_d; // RAM read address
wire [29:0] dataint; // RAM output
parameter ADDR0 = 4'b0000;
parameter ADDR1 = 4'b0001;
parameter ADDR2 = 4'b0010;
parameter ADDR3 = 4'b0011;
parameter ADDR4 = 4'b0100;
parameter ADDR5 = 4'b0101;
parameter ADDR6 = 4'b0110;
parameter ADDR7 = 4'b0111;
parameter ADDR8 = 4'b1000;
parameter ADDR9 = 4'b1001;
parameter ADDR10 = 4'b1010;
parameter ADDR11 = 4'b1011;
parameter ADDR12 = 4'b1100;
parameter ADDR13 = 4'b1101;
parameter ADDR14 = 4'b1110;
parameter ADDR15 = 4'b1111;
always@(wa) begin
case (wa)
ADDR0 : wa_d = ADDR1 ;
ADDR1 : wa_d = ADDR2 ;
ADDR2 : wa_d = ADDR3 ;
ADDR3 : wa_d = ADDR4 ;
ADDR4 : wa_d = ADDR5 ;
ADDR5 : wa_d = ADDR6 ;
ADDR6 : wa_d = ADDR7 ;
ADDR7 : wa_d = ADDR8 ;
ADDR8 : wa_d = ADDR9 ;
ADDR9 : wa_d = ADDR10;
ADDR10 : wa_d = ADDR11;
ADDR11 : wa_d = ADDR12;
ADDR12 : wa_d = ADDR13;
ADDR13 : wa_d = ADDR14;
ADDR14 : wa_d = ADDR15;
default : wa_d = ADDR0;
endcase
end
FDC fdc_wa0 (.C(clk), .D(wa_d[0]), .CLR(rst), .Q(wa[0]));
FDC fdc_wa1 (.C(clk), .D(wa_d[1]), .CLR(rst), .Q(wa[1]));
FDC fdc_wa2 (.C(clk), .D(wa_d[2]), .CLR(rst), .Q(wa[2]));
FDC fdc_wa3 (.C(clk), .D(wa_d[3]), .CLR(rst), .Q(wa[3]));
//Dual Port fifo to bridge data from clk to clkx2
DRAM16XN #(.data_width(30))
fifo_u (
.DATA_IN(datain),
.ADDRESS(wa),
.ADDRESS_DP(ra),
.WRITE_EN(1'b1),
.CLK(clk),
.O_DATA_OUT(),
.O_DATA_OUT_DP(dataint));
/////////////////////////////////////////////////////////////////
// Here starts clk2x domain for fifo read out
// FIFO read is set to be once every 2 cycles of clk2x in order
// to keep up pace with the fifo write speed
// Also FIFO read reset is delayed a bit in order to avoid
// underflow.
/////////////////////////////////////////////////////////////////
always@(ra) begin
case (ra)
ADDR0 : ra_d = ADDR1 ;
ADDR1 : ra_d = ADDR2 ;
ADDR2 : ra_d = ADDR3 ;
ADDR3 : ra_d = ADDR4 ;
ADDR4 : ra_d = ADDR5 ;
ADDR5 : ra_d = ADDR6 ;
ADDR6 : ra_d = ADDR7 ;
ADDR7 : ra_d = ADDR8 ;
ADDR8 : ra_d = ADDR9 ;
ADDR9 : ra_d = ADDR10;
ADDR10 : ra_d = ADDR11;
ADDR11 : ra_d = ADDR12;
ADDR12 : ra_d = ADDR13;
ADDR13 : ra_d = ADDR14;
ADDR14 : ra_d = ADDR15;
default : ra_d = ADDR0;
endcase
end
wire rstsync, rstsync_q, rstp;
(* ASYNC_REG = "TRUE" *) FDP fdp_rst (.C(clkx2), .D(rst), .PRE(rst), .Q(rstsync));
FD fd_rstsync (.C(clkx2), .D(rstsync), .Q(rstsync_q));
FD fd_rstp (.C(clkx2), .D(rstsync_q), .Q(rstp));
wire sync;
FDR sync_gen (.Q (sync), .C (clkx2), .R(rstp), .D(~sync));
FDRE fdc_ra0 (.C(clkx2), .D(ra_d[0]), .R(rstp), .CE(sync), .Q(ra[0]));
FDRE fdc_ra1 (.C(clkx2), .D(ra_d[1]), .R(rstp), .CE(sync), .Q(ra[1]));
FDRE fdc_ra2 (.C(clkx2), .D(ra_d[2]), .R(rstp), .CE(sync), .Q(ra[2]));
FDRE fdc_ra3 (.C(clkx2), .D(ra_d[3]), .R(rstp), .CE(sync), .Q(ra[3]));
wire [29:0] db;
FDE fd_db0 (.C(clkx2), .D(dataint[0]), .CE(sync), .Q(db[0]));
FDE fd_db1 (.C(clkx2), .D(dataint[1]), .CE(sync), .Q(db[1]));
FDE fd_db2 (.C(clkx2), .D(dataint[2]), .CE(sync), .Q(db[2]));
FDE fd_db3 (.C(clkx2), .D(dataint[3]), .CE(sync), .Q(db[3]));
FDE fd_db4 (.C(clkx2), .D(dataint[4]), .CE(sync), .Q(db[4]));
FDE fd_db5 (.C(clkx2), .D(dataint[5]), .CE(sync), .Q(db[5]));
FDE fd_db6 (.C(clkx2), .D(dataint[6]), .CE(sync), .Q(db[6]));
FDE fd_db7 (.C(clkx2), .D(dataint[7]), .CE(sync), .Q(db[7]));
FDE fd_db8 (.C(clkx2), .D(dataint[8]), .CE(sync), .Q(db[8]));
FDE fd_db9 (.C(clkx2), .D(dataint[9]), .CE(sync), .Q(db[9]));
FDE fd_db10 (.C(clkx2), .D(dataint[10]), .CE(sync), .Q(db[10]));
FDE fd_db11 (.C(clkx2), .D(dataint[11]), .CE(sync), .Q(db[11]));
FDE fd_db12 (.C(clkx2), .D(dataint[12]), .CE(sync), .Q(db[12]));
FDE fd_db13 (.C(clkx2), .D(dataint[13]), .CE(sync), .Q(db[13]));
FDE fd_db14 (.C(clkx2), .D(dataint[14]), .CE(sync), .Q(db[14]));
FDE fd_db15 (.C(clkx2), .D(dataint[15]), .CE(sync), .Q(db[15]));
FDE fd_db16 (.C(clkx2), .D(dataint[16]), .CE(sync), .Q(db[16]));
FDE fd_db17 (.C(clkx2), .D(dataint[17]), .CE(sync), .Q(db[17]));
FDE fd_db18 (.C(clkx2), .D(dataint[18]), .CE(sync), .Q(db[18]));
FDE fd_db19 (.C(clkx2), .D(dataint[19]), .CE(sync), .Q(db[19]));
FDE fd_db20 (.C(clkx2), .D(dataint[20]), .CE(sync), .Q(db[20]));
FDE fd_db21 (.C(clkx2), .D(dataint[21]), .CE(sync), .Q(db[21]));
FDE fd_db22 (.C(clkx2), .D(dataint[22]), .CE(sync), .Q(db[22]));
FDE fd_db23 (.C(clkx2), .D(dataint[23]), .CE(sync), .Q(db[23]));
FDE fd_db24 (.C(clkx2), .D(dataint[24]), .CE(sync), .Q(db[24]));
FDE fd_db25 (.C(clkx2), .D(dataint[25]), .CE(sync), .Q(db[25]));
FDE fd_db26 (.C(clkx2), .D(dataint[26]), .CE(sync), .Q(db[26]));
FDE fd_db27 (.C(clkx2), .D(dataint[27]), .CE(sync), .Q(db[27]));
FDE fd_db28 (.C(clkx2), .D(dataint[28]), .CE(sync), .Q(db[28]));
FDE fd_db29 (.C(clkx2), .D(dataint[29]), .CE(sync), .Q(db[29]));
wire [14:0] mux;
assign mux = (~sync) ? db[14:0] : db[29:15];
FD fd_out0 (.C(clkx2), .D(mux[0]), .Q(dataout[0]));
FD fd_out1 (.C(clkx2), .D(mux[1]), .Q(dataout[1]));
FD fd_out2 (.C(clkx2), .D(mux[2]), .Q(dataout[2]));
FD fd_out3 (.C(clkx2), .D(mux[3]), .Q(dataout[3]));
FD fd_out4 (.C(clkx2), .D(mux[4]), .Q(dataout[4]));
FD fd_out5 (.C(clkx2), .D(mux[5]), .Q(dataout[5]));
FD fd_out6 (.C(clkx2), .D(mux[6]), .Q(dataout[6]));
FD fd_out7 (.C(clkx2), .D(mux[7]), .Q(dataout[7]));
FD fd_out8 (.C(clkx2), .D(mux[8]), .Q(dataout[8]));
FD fd_out9 (.C(clkx2), .D(mux[9]), .Q(dataout[9]));
FD fd_out10 (.C(clkx2), .D(mux[10]), .Q(dataout[10]));
FD fd_out11 (.C(clkx2), .D(mux[11]), .Q(dataout[11]));
FD fd_out12 (.C(clkx2), .D(mux[12]), .Q(dataout[12]));
FD fd_out13 (.C(clkx2), .D(mux[13]), .Q(dataout[13]));
FD fd_out14 (.C(clkx2), .D(mux[14]), .Q(dataout[14]));
endmodule
|
//Jun.28.2004
//Jun.30.2004 jump bug fix
//Jul.11.2004 target special zero
//Jan.20.2005 apply @*
`include "define.h"
//`define ALTERA
module decoder(clock,sync_reset,MWriteD1,RegWriteD2,A_Right_SELD1,RF_inputD2,
RF_input_addr,M_signD1,M_signD2,M_access_modeD1,M_access_modeD2,
ALU_FuncD2,Shift_FuncD2,source_addrD1,target_addrD1,IMMD2,
source_addrD2,target_addrD2,Shift_amountD2,PC_commandD1,IMMD1,IRD1,takenD3,takenD2,beqQ,bneQ,blezQ,bgtzQ,
DAddress,PC,memory_indata,MOUT,IMM,branchQQ,jumpQ,int_req,clear_int,int_address,
A_Left_SELD1,RRegSelD1,MWriteD2,NOP_Signal,mul_alu_selD2,mul_div_funcD2,
pause_out,control_state,Shift_Amount_selD2,uread_port,int_stateD1,bgezQ,bltzQ,write_busy);
input clock,sync_reset;
input takenD3,takenD2;
output MWriteD1,RegWriteD2;
output [1:0] A_Right_SELD1;
output [1:0] RF_inputD2;
output M_signD1,M_signD2;
output [1:0] M_access_modeD1,M_access_modeD2;
output [3:0] ALU_FuncD2;
output [1:0] Shift_FuncD2;
output [25:0] IMMD2,IMMD1;
output [4:0] source_addrD2,target_addrD2;
output [4:0] source_addrD1,target_addrD1,Shift_amountD2;
output [4:0] RF_input_addr;
output [2:0] PC_commandD1;
output [31:0] IRD1;
output beqQ,bneQ,blezQ,bgtzQ;
output bgezQ,bltzQ;
input [7:0] uread_port;
output int_stateD1;
input write_busy;//Apr.2.2005
input [25:0] DAddress,PC;
input [25:0] int_address;
input [31:0] memory_indata;
output [31:0] MOUT;
output [25:0] IMM;
output branchQQ,jumpQ;
input int_req;
output clear_int;
output A_Left_SELD1;
output [1:0] RRegSelD1;
output MWriteD2;
output NOP_Signal;
output [1:0] mul_alu_selD2;
output [3:0] mul_div_funcD2;
input pause_out;
output [7:0] control_state;
output Shift_Amount_selD2;
//For Debug Use
localparam [4:0] zero_=0,
at_=1,
v0_=2,
v1_=3,
a0_=4,
a1_=5,
a2_=6,
a3_=7,
t0_=8, t1_=9,t2_=10,t3_=11,t4_=12,t5_=13,t6_=14,t7_=15,
s0_=16,s1_=17,s2_=18,s3_=19,s4_=20,s5_=21,s6_=22,s7_=23,t8_=24,t9_=25,
k0_=26,k1_=27,gp_=28,sp_=29,s8_=30,ra_=31;
//regsiters
reg [31:0] IRD1;
reg [31:0] IRD2;
reg [1:0] RF_input_addr_selD1;
reg [4:0] RF_input_addr;
reg [1:0] Shift_FuncD1,Shift_FuncD2;
reg [3:0] ALU_FuncD2;
reg [1:0] A_Right_SELD1;
reg [1:0] RF_inputD2,RF_inputD1;
reg [1:0] M_access_modeD1,M_access_modeD2;
reg M_signD1,M_signD2;
reg MWriteD1,RegWriteD2,RegWriteD1,MWriteD2;
reg [2:0] PC_commandD1;
reg beqQ,bneQ,blezQ,bgtzQ;
reg bltzQ,bgezQ;//Jul.11.2004
reg branchQ,branchQQ,jumpQ;
reg [7:0] control_state;
reg sync_resetD1;
reg [31:0] memory_indataD2;
reg A_Left_SELD1;
reg [1:0] RRegSelD1;
reg takenD4,takenD5;
reg nop_bit;
reg [1:0] mul_alu_selD2;
reg mul_div_funcD1;
reg div_mode_ff;
reg [3:0] mul_div_funcD2;
reg excuting_flag;
reg excuting_flagD,excuting_flagDD;
reg Shift_Amount_selD2;
reg int_seqD1;
//wires
wire [31:0] IR;
wire [5:0] opecode=IR[31:26];
wire [5:0] opecodeD1=IRD1[31:26];
wire [5:0] opefuncD1=IRD1[5:0];
wire [5:0] opefunc=IR[5:0];
wire [4:0] destination_addrD1;//Apr.8.2005
wire NOP_Signal;
wire finish_operation;
assign int_stateD1=control_state==5;
assign IMMD2=IRD2[25:0];
assign IMMD1=IRD1[25:0];
assign source_addrD2=IRD2[25:21];
assign target_addrD2=IRD2[20:16];
assign source_addrD1=IRD1[25:21];
assign target_addrD1=IRD1[20:16];
assign destination_addrD1=IRD1[15:11];
assign Shift_amountD2=IRD2[10:6];
assign IMM=IR[25:0];
`ifdef Veritak //Disassenblar
reg [30*8:1] inst;
wire [5:0] op=IR[31:26];
wire [25:0] bra=PC+{{10{IR[15]}},IR[15:0]}*4;//+4;
wire [4:0] rs=IR[25:21];
wire [4:0] rt=IR[20:16];
wire [4:0] rd=IR[15:11];
wire [4:0] sh=IR[10:6];
reg [5*8:1] reg_name="abcd";
reg [30*8:1] instD1,instD2;
function [4*8:1] get_reg_name;
input [4:0] field;
begin
case (field)
0: get_reg_name="$z0";
1: get_reg_name="$at";
2: get_reg_name="$v0";
3: get_reg_name="$v1";
4: get_reg_name="$a0";
5: get_reg_name="$a1";
6: get_reg_name="$a2";
7: get_reg_name="$a3";
8,9,10,11,12,13,14,15:
$sprintf(get_reg_name,"$t%1d",field-8);
16,17,18,19,20,21,22,23,24,25: $sprintf(get_reg_name,"$s%1d",field-16);
26:get_reg_name="$k0";
27:get_reg_name="$k1";
28:get_reg_name="$gp";
29:get_reg_name="$sp";
30:get_reg_name="$s8";
31:get_reg_name="$ra";
endcase
end
endfunction
always @(posedge clock) begin
instD1<=inst;
instD2<=instD1;
end
always @*begin:sprintf //Jan.20.2005 @ (IR,op,bra,rs,rt,rd,sh) begin :sprintf
reg [4*8:1] rdn;//Mar.15.2005 =get_reg_name(rd);//
reg [4*8:1] rsn;//Mar.15.2005=get_reg_name(rs);
reg [4*8:1] rtn;//Mar.15.2005 =get_reg_name(rt);
rdn=get_reg_name(rd);
rsn=get_reg_name(rs);
rtn=get_reg_name(rt);
case (op)
0:
case (IR[5:0])
0: if (rd==0 && rt==0 && rs==0 ) $sprintf(inst,"nop");
else $sprintf(inst,"sll %s,%s,%2d\n",rdn,rtn,sh);
2:
$sprintf(inst," srl %s,%s,%2d\n",rdn,rtn,sh);
3:
$sprintf(inst," sra %s,%s,%2d\n",rdn,rtn,sh);
4:
$sprintf(inst," sllv %s,%s,%s\n",rdn,rtn,rsn);
6:
$sprintf(inst," srlv %s,%s,%s\n",rdn,rtn,rsn);
7:
$sprintf(inst," srav %s,%s,%s\n",rdn,rtn,rsn);
8:
$sprintf(inst," jr %s\n",rsn);
9:
$sprintf(inst," jalr %s\n",rsn);
12:
$sprintf(inst," syscall\n");
13:
$sprintf(inst," break");
16:
$sprintf(inst," mfhi %s\n",rdn);
17:
$sprintf(inst," mthi %s\n",rsn);
18:
$sprintf(inst," mflo %s\n",rdn);
19:
$sprintf(inst," mtlo %s\n",rsn);
24:
$sprintf(inst," mult %s,%s\n",rsn,rtn);
25:
$sprintf(inst," multu %s,%s\n",rsn,rtn);
26:
$sprintf(inst," div %s,%s\n",rsn,rtn);
27:
$sprintf(inst," divu %s,%s\n",rsn,rtn);
32:
$sprintf(inst," add %s,%s,%s",rdn,rsn,rtn);
33:
if(rt==0)
$sprintf(inst," move %s,%s\n",rdn,rsn);
else
$sprintf(inst," addu %s,%s,%s\n",rdn,rsn,rtn);
34:
$sprintf(inst," sub %s,%s,%s\n",rdn,rsn,rtn);
35:
$sprintf(inst," subu %s,%s,%s\n",rdn,rsn,rtn);
36:
$sprintf(inst," and %s,%s,%s\n",rdn,rsn,rtn);
37:
if(rt==0)
$sprintf(inst," move %s,%s\n",rdn,rsn);
else
$sprintf(inst," or %s,%s,%s\n",rdn,rsn,rtn);
38:
$sprintf(inst," xor %s,%s,%s\n",rdn,rsn,rtn);
39:
$sprintf(inst," nor %s,%s,%s\n",rdn,rsn,rtn);
42:
$sprintf(inst," slt %s,%s,%s\n",rdn,rsn,rtn);
43:
$sprintf(inst," sltu %s,%s,%s\n",rdn,rsn,rtn);
default:
$sprintf(inst,"Unknown Func. %08h\n",IR);
endcase
1:
case (IR[20:16])
0:
$sprintf(inst," bltz %s,$%08h\n",rsn,bra);
1:
$sprintf(inst," bgez %s,$%08h\n",rsn,bra);
16:
$sprintf(inst," bltzal %s,$%08h\n",rsn,bra);
17:
$sprintf(inst," bgezal %s,$%08h\n",rsn,bra);
default:
$sprintf(inst,"Unknown1 %08h\n",IR);
endcase
2:
$sprintf(inst," j $%08h\n",((IR*4)&32'h0ffffffc)+(PC&32'hf0000000));
3:
$sprintf(inst," jal $%08h\n",((IR*4)&32'h0ffffffc)+(PC&32'hf0000000));
4:
if(rs==0 && rt==0)
$sprintf(inst," bra $%08h\n",bra);
else
$sprintf(inst," beq %s,%s,$%08h\n",rsn,rtn,bra);
5:
$sprintf(inst," bne %s,%s,$%08h\n",rsn,rtn,bra);
6:
$sprintf(inst," blez %s,$%08h\n",rsn,bra);
7:
$sprintf(inst," bgtz %s,$%08h\n",rsn,bra);
8:
$sprintf(inst," addi %s,%s,#$%04h\n",rtn,rsn,IR[15:0]);
9:
if(rs==0)
$sprintf(inst," li %s,#$%08h\n",rtn,IR[15:0]);
else
$sprintf(inst," addiu %s,%s,#$%04h\n",rtn,rsn,IR[15:0]);
10:
$sprintf(inst," slti %s,%s,#$%04h\n",rtn,rsn,IR[15:0]);
11:
$sprintf(inst," sltiu %s,%s,#$%04h\n",rtn,rsn,IR[15:0]);
12:
$sprintf(inst," andi %s,%s,#$%04h\n",rtn,rsn,IR[15:0]);
13:
if(rs==0)
$sprintf(inst," li %s,#$%08h\n",rtn,IR[15:0]);
else
$sprintf(inst," ori %s,%s,#$%04h\n",rtn,rsn,IR[15:0]);
14:
$sprintf(inst," xori %s,%s,#$%04h\n",rtn,rsn,IR[15:0]);
15://load upper immediate
$sprintf(inst," lui %s,#$%04h",rtn,IR[15:0]);
16, 17, 18, 19: begin
if(rs>=16)
$sprintf(inst," cop%d $%08h\n",op&3,IR[25:0]);
else
case(rsn)
0:
$sprintf(inst," mfc%d %s,%s\n",op&3,rtn,rdn);
2:
$sprintf(inst," cfc%d %s,%s\n",op&3,rtn,rdn);
4:
$sprintf(inst," mtc%d %s,%s\n",op&3,rtn,rdn);
6:
$sprintf(inst," ctc%d %s,%s\n",op&3,rtn,rdn);
8, 12:
if(rt&1)
$sprintf(inst," bc%dt %d,%08h\n",op&3,rs*32+rt,bra);
else
$sprintf(inst," bc%df %d,%08h\n",op&3,rs*32+rt,bra);
default:
$sprintf(inst,"Unknown16 %08h\n",IR);
endcase
end
32:
$sprintf(inst," lb %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
33:
$sprintf(inst," lh %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
34:
$sprintf(inst," lwl %s,$%04h(%s)\n",IR[15:0],rsn);
35:
$sprintf(inst," lw %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
36:
$sprintf(inst," lbu %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
37:
$sprintf(inst," lhu %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
38:
$sprintf(inst," lwr %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
40:
$sprintf(inst," sb %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
41:
$sprintf(inst," sh %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
42:
$sprintf(inst," swl %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
43:
$sprintf(inst," sw %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
46:
$sprintf(inst," swr %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
48, 49, 50, 51:
$sprintf(inst," lwc%d %s,$%04h(%s)\n",op&3,rtn,IR[15:0],rsn);
56, 57, 58, 59:
$sprintf(inst," swc%d %s,$%04h(%s)\n",op&3,rtn,IR[15:0],rsn);
default:
$sprintf(inst,"UnknownOp %08h\n",IR);
endcase
end
`endif
//
always @ (posedge clock) sync_resetD1 <=sync_reset;
//IRD1
always @ (posedge clock) begin
if (sync_resetD1) IRD1 <=32'h00;
else if ((control_state[5:0]==6'b00_0000 && int_req) ) IRD1<=int_address>>2;
else if (opecode==6'b000_001) IRD1<={IR[31:21],5'b00000,IR[15:0]};//Jul.11.2004 target ªSpecial zero
else IRD1 <=IR;
end
//IRD2
always @ (posedge clock) begin
IRD2 <=IRD1;
end
//RF_input_addr [4:0]
always @ (posedge clock) begin
case (RF_input_addr_selD1)
`RF_Ert_sel: RF_input_addr <=target_addrD1;
`RF_Erd_sel: RF_input_addr <=destination_addrD1;
`RF_R15_SEL: RF_input_addr <=`Last_Reg;
`RF_INTR_SEL:RF_input_addr <=`Intr_Reg;
default : RF_input_addr <=target_addrD1;
endcase
end
//int_seqD1
always @(posedge clock) begin
if (sync_reset) int_seqD1<=0;
else int_seqD1<=control_state[5:0]==6'b00_0000 && int_req;
end
// [1:0] Shift_FuncD1,Shift_FuncD2;
always @ (posedge clock) begin
Shift_FuncD2<=Shift_FuncD1;
end
// [3:0] ALU_FuncD1,ALU_FuncD2;
always @ (posedge clock) begin
M_access_modeD2<=M_access_modeD1;
end
//M_signD1,M_signD2;
always @ (posedge clock) begin
M_signD2<=M_signD1;
end
//takenD4
always @ (posedge clock) begin
if (sync_resetD1) takenD4<=1'b0;
else if (NOP_Signal) takenD4<=1'b0;//TRY
else takenD4<=takenD3;
end
//takenD5
always @ (posedge clock) begin
if (sync_resetD1) takenD5<=1'b0;
else takenD5<=takenD4;
end
//RegWriteD2,RegWriteD1;
always @ (posedge clock) begin
if (sync_resetD1) begin
RegWriteD2<=1'b0;
end else if (takenD4 ||takenD5 || NOP_Signal ) RegWriteD2<=1'b0;//NOP
else RegWriteD2<=RegWriteD1;
end
//Combination logics
//RegWrite;
always @ (posedge clock) begin
if (sync_resetD1) RegWriteD1<=1'b0;
else if (control_state[5:0]==6'b00_0000 && int_req) RegWriteD1<=1'b1;
else case (opecode)
`loadbyte_signed : RegWriteD1<=1'b1;
`loadbyte_unsigned : RegWriteD1<=1'b1;
`loadword_signed : RegWriteD1<=1'b1;
`loadword_unsigned : RegWriteD1<=1'b1;
`loadlong : RegWriteD1<=1'b1;
`jump_and_link_im: RegWriteD1<=1'b1;
`andi : RegWriteD1<=1'b1;
`addi : RegWriteD1<=1'b1 ;
`addiu : RegWriteD1<=1'b1;
`ori : RegWriteD1<=1'b1;
`xori : RegWriteD1<=1'b1;
`lui : RegWriteD1<=1'b1;
`comp_im_signed : RegWriteD1<=1'b1;
`comp_im_unsigned : RegWriteD1<=1'b1;
6'b00_0000:
case (opefunc)
`divs: RegWriteD1<=1'b0;
`divu: RegWriteD1<=1'b0;
`muls: RegWriteD1<=1'b0;
`mulu: RegWriteD1<=1'b0;
default: RegWriteD1<=1'b1;
endcase
default: RegWriteD1<=1'b0;
endcase
end
//
always @ (posedge clock) begin
if (sync_resetD1) mul_div_funcD1<=1'b0;
else if (control_state[5:0]==6'b00_0000 && int_req) mul_div_funcD1<=1'b0;
else case (opecode)
6'b00_0000:
case (opefunc)
`divs: begin
mul_div_funcD1<=1'b1;
div_mode_ff<=1'b1;
end
`divu: begin
mul_div_funcD1<=1'b1;
div_mode_ff<=1'b1;
end
`muls: begin
mul_div_funcD1<=1'b1;
div_mode_ff<=1'b0;
end
`mulu: begin
mul_div_funcD1<=1'b1;
div_mode_ff<=1'b0;
end
default: mul_div_funcD1<=1'b0;
endcase
default: mul_div_funcD1<=1'b0;
endcase
end
//mu_div_func
//mul_alu_selD2/excuting_flag
always @ (posedge clock) begin
if (sync_resetD1) begin
mul_div_funcD2 <=`mult_nothing;
mul_alu_selD2<=2'b00;
end else if ( mul_div_funcD2 [3] ) mul_div_funcD2[3]<=1'b0;////
else if( !NOP_Signal) //
case (opecodeD1)
6'b00_0000:
case (opefuncD1)
`divs: begin
mul_div_funcD2<=`mult_signed_divide;
end
`divu: begin
mul_div_funcD2<=`mult_divide;
end
`muls: begin
mul_div_funcD2<=`mult_signed_mult;
end
`mulu: begin
mul_div_funcD2<=`mult_mult;
end
`mfhi : begin
if (!pause_out)mul_div_funcD2<=`mult_read_hi;
mul_alu_selD2<=`MUL_hi_SEL;
end
`mflo : begin
if(!pause_out) mul_div_funcD2<=`mult_read_lo;
mul_alu_selD2<=`MUL_lo_SEL;
end
default: begin
mul_div_funcD2 <=`mult_read_lo;
mul_alu_selD2<=2'b00;
end
endcase
default: mul_alu_selD2<=2'b00;
endcase
end
always @ (posedge clock) begin
if (sync_resetD1) excuting_flagD<=1'b0;
else excuting_flagD<=excuting_flag;
end
always @ (posedge clock) begin
if (sync_resetD1) excuting_flagDD<=1'b0;
else excuting_flagDD<=excuting_flagD;
end
assign finish_operation=excuting_flag && !pause_out;
//MWrite
always @ (posedge clock) begin
if (sync_resetD1) MWriteD1<=1'b0;
else case (opecode)
`storebyte: MWriteD1<=1'b1;
`storeword: MWriteD1<=1'b1;
`storelong: MWriteD1<=1'b1;
default: MWriteD1<=1'b0;
endcase
end
always @ (posedge clock) begin
if (sync_resetD1) MWriteD2<=1'b0;
else if ( NOP_Signal ) MWriteD2<=1'b0;
else MWriteD2<=MWriteD1;//taken NOP
end
//M_sign
always @ (posedge clock) begin
if (sync_resetD1) M_signD1<=`M_unsigned;
else case (opecode)
`loadbyte_signed : M_signD1<=`M_signed;
`loadbyte_unsigned : M_signD1<=`M_unsigned;
`loadword_signed : M_signD1<=`M_signed;
`loadword_unsigned : M_signD1<=`M_unsigned;
`loadlong : M_signD1<=`M_unsigned;
`storebyte: M_signD1<=`M_unsigned;
`storeword: M_signD1<=`M_unsigned;
`storelong: M_signD1<=`M_unsigned;
default: M_signD1<=`M_unsigned;
endcase
end
// [1:0] M_access_mode
always @ (posedge clock) begin
if (sync_resetD1) M_access_modeD1<=`LONG_ACCESS;
else case (opecode)
`loadbyte_signed : M_access_modeD1<=`BYTE_ACCESS;
`loadbyte_unsigned : M_access_modeD1<=`BYTE_ACCESS;
`loadword_signed : M_access_modeD1<=`WORD_ACCESS;
`loadword_unsigned : M_access_modeD1<=`WORD_ACCESS;
`loadlong : M_access_modeD1<=`LONG_ACCESS;
`storebyte: M_access_modeD1<=`BYTE_ACCESS;
`storeword: M_access_modeD1<=`WORD_ACCESS;
`storelong: M_access_modeD1<=`LONG_ACCESS;
default: M_access_modeD1<=`LONG_ACCESS;
endcase
end
// [2:0] RF_input Shift_Amount_sel
always @ (posedge clock) begin
if (sync_resetD1) begin
RF_inputD2 <=`RF_ALU_sel;
Shift_Amount_selD2<=`SHIFT_AMOUNT_IMM_SEL;
end
else if ((int_seqD1) || NOP_Signal ) RF_inputD2<=`RF_PC_SEL;//Jul.7.2004
else
case (opecodeD1)
`lui :RF_inputD2 <=`SHIFT16_SEL;
`jump_and_link_im: RF_inputD2<=`RF_PC_SEL;
6'b00_0000:
case (opefuncD1)
`jump_and_link_register : RF_inputD2<=`RF_PC_SEL;
`lsl : begin
RF_inputD2<=`RF_Shifter_sel ;
Shift_Amount_selD2<=`SHIFT_AMOUNT_IMM_SEL;
end
`sllv : begin
RF_inputD2<=`RF_Shifter_sel ;
Shift_Amount_selD2<=`SHIFT_AMOUNT_REG_SEL;
end
`asr : begin
RF_inputD2<=`RF_Shifter_sel ;
Shift_Amount_selD2<=`SHIFT_AMOUNT_IMM_SEL;
end
`srav : begin
RF_inputD2<=`RF_Shifter_sel ;
Shift_Amount_selD2<=`SHIFT_AMOUNT_REG_SEL;
end
`lsr : begin
RF_inputD2<=`RF_Shifter_sel;
Shift_Amount_selD2<=`SHIFT_AMOUNT_IMM_SEL;
end
`srlv : begin
RF_inputD2<=`RF_Shifter_sel;
Shift_Amount_selD2<=`SHIFT_AMOUNT_REG_SEL;
end
`mfhi : RF_inputD2<=`RF_PC_SEL;
`mflo : RF_inputD2<=`RF_PC_SEL;
default : begin
RF_inputD2<=`RF_ALU_sel;
Shift_Amount_selD2<=`SHIFT_AMOUNT_IMM_SEL;
end
endcase
default: begin
RF_inputD2<=`RF_ALU_sel;
Shift_Amount_selD2<=`SHIFT_AMOUNT_IMM_SEL;
end
endcase
end
//[1:0] A_Right_SEL
always @ (posedge clock) begin
casex (opecode)
`storebyte: A_Right_SELD1<=`A_RIGHT_ERT;
`storeword: A_Right_SELD1<=`A_RIGHT_ERT;
`storelong: A_Right_SELD1<=`A_RIGHT_ERT;
`andi : A_Right_SELD1<=`Imm_unsigned ;
`addi : A_Right_SELD1<=`Imm_signed ;
`addiu : A_Right_SELD1<=`Imm_signed;
`ori : A_Right_SELD1<=`Imm_unsigned;
`xori : A_Right_SELD1<=`Imm_unsigned;
`beq : A_Right_SELD1<=`A_RIGHT_ERT;
`bgtz : A_Right_SELD1<=`A_RIGHT_ERT;
`blez : A_Right_SELD1<=`A_RIGHT_ERT;
`bne : A_Right_SELD1<=`A_RIGHT_ERT;
`comp_im_signed : A_Right_SELD1<=`Imm_signed;
`comp_im_unsigned : A_Right_SELD1<=`Imm_signed;
//6'b00_0000:
6'b00_000?://Jul.11.2004 target select
case (opefunc)
default : A_Right_SELD1<=`A_RIGHT_ERT;
endcase
default: A_Right_SELD1<=`Imm_signed;
endcase
end
//Interim A_Left_SELD1RRegSelD1
always @ (posedge clock) begin
case (opecode)
default: A_Left_SELD1<=0;//always Left_latch
endcase
end
always @ (posedge clock) begin
if ((control_state[5:0]==6'b00__0000 && int_req) ) RRegSelD1<=`NREG_SEL;//Jul.13.2004
else case (opecode)
`loadbyte_signed : RRegSelD1<=`MOUT_SEL;
`loadbyte_unsigned : RRegSelD1<=`MOUT_SEL;
`loadword_signed : RRegSelD1<=`MOUT_SEL;
`loadword_unsigned : RRegSelD1<=`MOUT_SEL;
`loadlong : RRegSelD1<=`MOUT_SEL;
default: RRegSelD1<=`NREG_SEL;//Interim MULSEL
endcase
end
// [3:0] ALU_Func[1:0] ;
always @ (posedge clock) begin
case (opecodeD1)
`andi : ALU_FuncD2<=`ALU_AND;
`addi : ALU_FuncD2<=`ALU_ADD ;
`addiu : ALU_FuncD2<=`ALU_ADD;
`ori : ALU_FuncD2<=`ALU_OR;
`xori : ALU_FuncD2<=`ALU_XOR;
`comp_im_signed : ALU_FuncD2<=`ALU_LESS_THAN_SIGNED;
`comp_im_unsigned : ALU_FuncD2<=`ALU_LESS_THAN_UNSIGNED;
6'b00_0000:
case (opefuncD1)
`add : ALU_FuncD2<=`ALU_ADD ;
`addu : ALU_FuncD2<=`ALU_ADD ;
`sub : ALU_FuncD2<=`ALU_SUBTRACT;
`subu : ALU_FuncD2<=`ALU_SUBTRACT;
`and : ALU_FuncD2<=`ALU_AND;
`nor : ALU_FuncD2<=`ALU_NOR;
`or : ALU_FuncD2<=`ALU_OR;
`xor : ALU_FuncD2<=`ALU_XOR;
`comp_signed : ALU_FuncD2<=`ALU_LESS_THAN_SIGNED;
`comp_unsigned : ALU_FuncD2<=`ALU_LESS_THAN_UNSIGNED;
default : ALU_FuncD2<=`ALU_NOTHING;//Jul.6.2004 ALU_NOTHING;
endcase
default: ALU_FuncD2<=`ALU_NOTHING;//Jul.6.2004 ALU_NOTHING;
endcase
end
// [1:0] Shift_Func;
always @ (posedge clock) begin
case (opecode)
6'b00_0000:
case (opefunc)
`lsl : Shift_FuncD1<=`SHIFT_LEFT;
`sllv : Shift_FuncD1<=`SHIFT_LEFT;
`asr : Shift_FuncD1<=`SHIFT_RIGHT_SIGNED;
`srav : Shift_FuncD1<=`SHIFT_RIGHT_SIGNED;
`lsr : Shift_FuncD1<=`SHIFT_RIGHT_UNSIGNED;
`srlv : Shift_FuncD1<=`SHIFT_RIGHT_UNSIGNED;
default : Shift_FuncD1<=`SHIFT_LEFT;//Jul.5.2004 `SHIFT_NOTHING;
endcase
default: Shift_FuncD1<=`SHIFT_LEFT;//Jul.5.2004`SHIFT_NOTHING;
endcase
end
//RF_input_addr_sel
always @ (posedge clock) begin
if ((control_state[5:0]==6'b00__0000 && int_req) ) RF_input_addr_selD1<=`RF_INTR_SEL;
else
case (opecode)
`andi : RF_input_addr_selD1<=`RF_Ert_sel;
`addi : RF_input_addr_selD1<=`RF_Ert_sel;
`ori : RF_input_addr_selD1<=`RF_Ert_sel;
`xori : RF_input_addr_selD1<=`RF_Ert_sel;
`jump_and_link_im: RF_input_addr_selD1<=`RF_R15_SEL;
`lui : RF_input_addr_selD1<=`RF_Ert_sel;
`comp_im_signed : RF_input_addr_selD1<=`RF_Ert_sel;
`comp_im_unsigned: RF_input_addr_selD1<=`RF_Ert_sel;
6'b00_0000:
case (opefunc)
`jump_and_link_register: RF_input_addr_selD1<=`RF_R15_SEL;
default : RF_input_addr_selD1<=`RF_Erd_sel;
endcase
default: RF_input_addr_selD1<=`RF_Ert_sel;
endcase
end
//PC_command decoder
// always @ (posedge clock) begin
always @(opecode,control_state,int_req,opefunc,NOP_Signal,takenD3,takenD4) begin//Jul.2.2004
if (takenD3 || takenD4) PC_commandD1<=`PC_INC;//
else case (opecode)
6'b00_0000:
case (opefunc)
`jmp_register : PC_commandD1<=`PC_REG;
default: PC_commandD1<=`PC_INC;
endcase
default : PC_commandD1<=`PC_INC;
endcase
end
//unsuppurted command detector Jul.11.2004
always @(posedge clock) begin
case (opecode)
6'b000_001://Jul.11.2004 simple decode
case (IR[20:16])
`bltzal :begin
$display("unsupported command");
$stop;
end
`bgezal : begin
$display("unsupported command");
$stop;
end
`bltzall:begin
$display("unsupported command");
$stop;
end
`bltzl:begin
$display("unsupported command");
$stop;
end
`bgezall:begin
$display("unsupported command");
$stop;
end
`bgezl: begin
$display("unsupported command");
$stop;
end
endcase
endcase
end
always @ (posedge clock) begin
if ((control_state[5:0]==6'b00_0000 && int_req) ) begin
jumpQ<=1'b1;
branchQ<=1'b0;////Jun.30.2004
end else if (takenD3) begin
jumpQ<=1'b0;//inhibit jump at delayed slot2
branchQ<=1'b0;//TRY Jun.30.2004
end else
case (opecode)
`jump: begin
jumpQ<=1'b1;
branchQ<=1'b0;//Jun.30.2004
end
`jump_and_link_im: begin
jumpQ<=1'b1;
branchQ<=1'b0;//Jun.30.2004
end
`beq : begin
jumpQ<=1'b0;//Jun.30.2004
branchQ<=1'b1;
end
`bgtz : begin
jumpQ<=1'b0;//Jun.30.2004
branchQ<=1'b1;
end
`blez : begin
jumpQ<=1'b0;//Jun.30.2004
branchQ<=1'b1;
end
`bne : begin
jumpQ<=1'b0;//Jun.30.2004
branchQ<=1'b1;
end
6'b000_001://Jul.11.2004 simple decode
begin
jumpQ<=1'b0;
branchQ<=1'b1;
end
default : begin
jumpQ<=1'b0;
branchQ<=1'b0;
end
endcase
end
always @ (posedge clock) begin
if (NOP_Signal) branchQQ<=1'b0;
else branchQQ<=branchQ;
end
//For Critical Path
always @(posedge clock) begin
if (sync_resetD1) beqQ<=0;
else if ((control_state[5:0]==6'b00_0000 && int_req) ) beqQ<=1'b0;
else if (opecode==`beq) beqQ<=1'b1;
else beqQ<=1'b0;
end
//Jul.11.2004 bltz
always @(posedge clock) begin
if (sync_resetD1) bltzQ<=0;
else if ((control_state[5:0]==6'b00_0000 && int_req) ) bltzQ<=1'b0;
else if (opecode==6'b000_001 && IR[20:16]==`bltz) bltzQ<=1'b1;//Jul.13.2004
else bltzQ<=1'b0;
end
//Jul.11.2004 bgez
always @(posedge clock) begin
if (sync_resetD1) bgezQ<=0;
else if ((control_state[5:0]==6'b00_0000 && int_req) ) bgezQ<=1'b0;
else if (opecode==6'b000_0001 && IR[20:16]==`bgez) bgezQ<=1'b1;//Jul.13.2004
else bgezQ<=1'b0;
end
always @(posedge clock) begin
if (sync_resetD1) bgtzQ<=0;
else if ((control_state[5:0]==6'b00_0000 && int_req) ) bgtzQ<=1'b0;
else if (opecode==`bgtz) bgtzQ<=1'b1;
else bgtzQ<=1'b0;
end
always @(posedge clock) begin
if (sync_resetD1) blezQ<=0;
else if ((control_state[5:0]==6'b00_0000 && int_req) ) blezQ<=1'b0;
else if (opecode==`blez) blezQ<=1'b1;
else blezQ<=1'b0;
end
always @(posedge clock) begin
if (sync_resetD1) bneQ<=0;
else if ((control_state[5:0]==6'b00_0000 && int_req) ) bneQ<=1'b0;
else if (opecode==`bne) bneQ<=1'b1;
else bneQ<=1'b0;
end
//
always @(posedge clock) begin
if (sync_resetD1) begin
excuting_flag<=1'b0;//
end else
begin
if (!pause_out && excuting_flagDD) excuting_flag<=1'b0;
else case (opecode)
6'b00_0000:
case (opefunc)
`divs: excuting_flag<=1'b1;
`divu: excuting_flag<=1'b1;
`muls: excuting_flag<=1'b1;
`mulu: excuting_flag<=1'b1;
endcase
endcase
end
end
always @(posedge clock) begin
if (sync_resetD1) begin
control_state<=6'b00_0000;
end else
begin
casex (control_state[5:0])
6'b00_0000:
begin
if(int_req) control_state<=6'b000_101;//
else
case (opecode)
`jump: control_state<=6'b100_000;
`jump_and_link_im: control_state<=6'b100_000;
`beq : control_state<=6'b110_000;
`bgtz : control_state<=6'b110_000;
`blez : control_state<=6'b110_000;
`bne : control_state<=6'b110_000;
6'b000_001: control_state<=6'b110_000;//Jul.11.2004 Special Branch
6'b00_0000:
case (opefunc)
`jump_and_link_register: control_state<=6'b101_000;
`jmp_register : control_state<=6'b101_000;
`mfhi: if (excuting_flag) control_state<=8'b00_000_010;
`mflo: if (excuting_flag) control_state<=8'b00_000_010;
default: control_state<=6'b00_0000;//for safety
endcase
endcase
end
6'b???_101: control_state<=6'b000_000;//interrupt_nop state
6'b100_000: control_state<=6'b000_000;//fixed_jump state
6'b101_000: control_state<=6'b001_100;//jump&link state
6'b001_100: control_state<=6'b000_000;//NOP2 state
6'b110_000: control_state<=6'b000_100;//delayed branch
6'b000_100: `ifdef RAM4K//Priotiry Area
if (takenD3) control_state<=6'b001_100;//NOP1 state
else case (opecode)
`jump: control_state<=6'b100_000;
`jump_and_link_im: control_state<=6'b100_000;
`beq : control_state<=6'b110_000;
`bgtz : control_state<=6'b110_000;
`blez : control_state<=6'b110_000;
`bne : control_state<=6'b110_000;
6'b000_001: control_state<=6'b110_000;//Jul.11.2004 Special Branch
6'b00_0000:
case (opefunc)
`jump_and_link_register: control_state<=6'b101_000;
`jmp_register : control_state<=6'b101_000;
`mfhi: if (excuting_flag) control_state<=8'b00_000_010;
`mflo: if (excuting_flag) control_state<=8'b00_000_010;
default: control_state<=6'b00_0000;//for safety
endcase
endcase
`else//Priority Speed
case (opecode)
`jump: if (takenD3) control_state<=6'b001_100;//NOP1 state
else control_state<=6'b100_000;
`jump_and_link_im: if (takenD3) control_state<=6'b001_100;//NOP1 state
else control_state<=6'b100_000;
`beq : if (takenD3) control_state<=6'b001_100;//NOP1 state
else control_state<=6'b110_000;
`bgtz : if (takenD3) control_state<=6'b001_100;//NOP1 state
else control_state<=6'b110_000;
`blez : if (takenD3) control_state<=6'b001_100;//NOP1 state
else control_state<=6'b110_000;
`bne : if (takenD3) control_state<=6'b001_100;//NOP1 state
else control_state<=6'b110_000;
6'b000_001: if (takenD3) control_state<=6'b001_100;//NOP1 state
else control_state<=6'b110_000;//Jul.11.2004 Special Branch
6'b00_0000:
case (opefunc)
`jump_and_link_register: if (takenD3) control_state<=6'b001_100;//NOP1 state
else control_state<=6'b101_000;
`jmp_register : if (takenD3) control_state<=6'b001_100;//NOP1 state
else control_state<=6'b101_000;
`mfhi: if (excuting_flag) begin
if (takenD3) control_state<=6'b001_100;//NOP1 state
else control_state<=8'b00_000_010;
end else if (takenD3) control_state<=6'b001_100;//NOP1 state
`mflo: if (excuting_flag) begin
if (takenD3) control_state<=6'b001_100;//NOP1 state
else control_state<=8'b00_000_010;
end else if (takenD3) control_state<=6'b001_100;//NOP1 state
default: if (takenD3) control_state<=6'b001_100;//NOP1 state
else control_state<=6'b00_0000;//for safety
endcase
default : if (takenD3) control_state<=6'b001_100;//NOP1 state
endcase
`endif
6'b???_010: case (control_state[7:6])
2'b00: control_state<=8'b01_000_010;
2'b01: if (!pause_out) control_state<=8'b11_000_010;//mul/div
2'b11: control_state<=8'b10_000_010;
2'b10: control_state<=8'b00_000_110;//NOP
default: control_state<=8'h00;
endcase
6'b???_110: control_state<=8'h01;//Jul.12.2004 PCC=save_pc;
6'b???_001: control_state<=8'h00; //Jul.12.2004 MUL IDLE avoid interrupt
default: control_state<=8'h00;//for safety
endcase
end
end
assign clear_int=control_state[2:0]==3'b101;//Jul.12.2004 interrupt_nop_state
always @(posedge clock) begin
if (sync_reset) nop_bit<=1'b0;
else if (6'b000_100==control_state[5:0] && !takenD3) nop_bit<=1'b0;//Not taken
else nop_bit<=control_state[2];
end
assign NOP_Signal=nop_bit | control_state[1];//Jul.7.2004 int_bit mul_bit
ram_module_altera
`ifdef RAM4K
ram(.clock(clock),.sync_reset(sync_reset),.IR(IR),.MOUT(MOUT),
.Paddr(PC[11:0]),.Daddr(DAddress[11:0]),.wren(MWriteD2),
.datain(memory_indata),.access_mode(M_access_modeD2),
.M_signed(M_signD2),.uread_port(uread_port),.write_busy(write_busy));
`endif
`ifdef RAM16K
ram(.clock(clock),.sync_reset(sync_reset),.IR(IR),.MOUT(MOUT),
.Paddr(PC[13:0]),.Daddr(DAddress[13:0]),.wren(MWriteD2),
.datain(memory_indata),.access_mode(M_access_modeD2),
.M_signed(M_signD2),.uread_port(uread_port),.write_busy(write_busy));
`endif
`ifdef RAM32K
ram(.clock(clock),.sync_reset(sync_reset),.IR(IR),.MOUT(MOUT),
.Paddr(PC[14:0]),.Daddr(DAddress[14:0]),.wren(MWriteD2),
.datain(memory_indata),.access_mode(M_access_modeD2),
.M_signed(M_signD2),.uread_port(uread_port),.write_busy(write_busy));
`endif
endmodule
|
module AL_MAP_SEQ (
output reg q,
input ce,
input clk,
input sr,
input d
);
parameter DFFMODE = "FF"; //FF,LATCH
parameter REGSET = "RESET"; //RESET/SET
parameter SRMUX = "SR"; //SR/INV
parameter SRMODE = "SYNC"; //SYNC/ASYNC
wire srmux;
generate
case (SRMUX)
"SR": assign srmux = sr;
"INV": assign srmux = ~sr;
default: assign srmux = sr;
endcase
endgenerate
wire regset;
generate
case (REGSET)
"RESET": assign regset = 1'b0;
"SET": assign regset = 1'b1;
default: assign regset = 1'b0;
endcase
endgenerate
initial q = regset;
generate
if (DFFMODE == "FF")
begin
if (SRMODE == "ASYNC")
begin
always @(posedge clk, posedge srmux)
if (srmux)
q <= regset;
else if (ce)
q <= d;
end
else
begin
always @(posedge clk)
if (srmux)
q <= regset;
else if (ce)
q <= d;
end
end
else
begin
// DFFMODE == "LATCH"
if (SRMODE == "ASYNC")
begin
always @*
if (srmux)
q <= regset;
else if (~clk & ce)
q <= d;
end
else
begin
always @*
if (~clk) begin
if (srmux)
q <= regset;
else if (ce)
q <= d;
end
end
end
endgenerate
endmodule
module AL_MAP_LUT1 (
output o,
input a
);
parameter [1:0] INIT = 2'h0;
parameter EQN = "(A)";
assign o = a ? INIT[1] : INIT[0];
endmodule
module AL_MAP_LUT2 (
output o,
input a,
input b
);
parameter [3:0] INIT = 4'h0;
parameter EQN = "(A)";
wire [1:0] s1 = b ? INIT[ 3:2] : INIT[1:0];
assign o = a ? s1[1] : s1[0];
endmodule
module AL_MAP_LUT3 (
output o,
input a,
input b,
input c
);
parameter [7:0] INIT = 8'h0;
parameter EQN = "(A)";
wire [3:0] s2 = c ? INIT[ 7:4] : INIT[3:0];
wire [1:0] s1 = b ? s2[ 3:2] : s2[1:0];
assign o = a ? s1[1] : s1[0];
endmodule
module AL_MAP_LUT4 (
output o,
input a,
input b,
input c,
input d
);
parameter [15:0] INIT = 16'h0;
parameter EQN = "(A)";
wire [7:0] s3 = d ? INIT[15:8] : INIT[7:0];
wire [3:0] s2 = c ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = b ? s2[ 3:2] : s2[1:0];
assign o = a ? s1[1] : s1[0];
endmodule
module AL_MAP_LUT5 (
output o,
input a,
input b,
input c,
input d,
input e
);
parameter [31:0] INIT = 32'h0;
parameter EQN = "(A)";
assign o = INIT >> {e, d, c, b, a};
endmodule
module AL_MAP_LUT6 (
output o,
input a,
input b,
input c,
input d,
input e,
input f
);
parameter [63:0] INIT = 64'h0;
parameter EQN = "(A)";
assign o = INIT >> {f, e, d, c, b, a};
endmodule
module AL_MAP_ALU2B (
input cin,
input a0, b0, c0, d0,
input a1, b1, c1, d1,
output s0, s1, cout
);
parameter [15:0] INIT0 = 16'h0000;
parameter [15:0] INIT1 = 16'h0000;
parameter FUNC0 = "NO";
parameter FUNC1 = "NO";
endmodule
module AL_MAP_ADDER (
input a,
input b,
input c,
output [1:0] o
);
parameter ALUTYPE = "ADD";
generate
case (ALUTYPE)
"ADD": assign o = a + b + c;
"SUB": assign o = a - b - c;
"A_LE_B": assign o = a - b - c;
"ADD_CARRY": assign o = { a, 1'b0 };
"SUB_CARRY": assign o = { ~a, 1'b0 };
"A_LE_B_CARRY": assign o = { a, 1'b0 };
default: assign o = a + b + c;
endcase
endgenerate
endmodule
|
//sata_transport_layer.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`include "sata_defines.v"
module sata_transport_layer (
input rst, //reset
input clk,
input phy_ready,
//Transport Layer Control/Status
output transport_layer_ready,
input sync_escape,
output reg d2h_reg_stb,
output reg dma_activate_stb,
output reg d2h_data_stb,
output reg dma_setup_stb,
output reg pio_setup_stb,
output reg set_device_bits_stb,
output reg remote_abort,
output xmit_error,
output read_crc_error,
input send_command_stb,
input send_control_stb,
input send_data_stb,
//PIO
output reg pio_response,
output reg pio_direction,
output reg [15:0] pio_transfer_count,
output reg [7:0] pio_e_status,
//Host to Device Registers
input [7:0] h2d_command,
input [15:0] h2d_features,
input [7:0] h2d_control,
input [3:0] h2d_port_mult,
input [7:0] h2d_device,
input [47:0] h2d_lba,
input [15:0] h2d_sector_count,
//Device to Host Registers
output reg [7:0] d2h_fis,
output reg d2h_interrupt,
output reg d2h_notification,
output reg [3:0] d2h_port_mult,
output reg [7:0] d2h_device,
output reg [47:0] d2h_lba,
output reg [15:0] d2h_sector_count,
output reg [7:0] d2h_status,
output reg [7:0] d2h_error,
//DMA Specific Control
//Data Control
input cl_if_ready,
output reg cl_if_activate,
input [23:0] cl_if_size,
output cl_if_strobe,
input [31:0] cl_if_data,
input [1:0] cl_of_ready,
output reg [1:0] cl_of_activate,
output cl_of_strobe,
output [31:0] cl_of_data,
input [23:0] cl_of_size,
//Link Layer Interface
input link_layer_ready,
output ll_sync_escape,
output ll_write_start,
input ll_write_strobe,
input ll_write_finished,
output [31:0] ll_write_data,
output [23:0] ll_write_size,
output ll_write_hold,
output ll_write_abort,
input ll_xmit_error,
input ll_read_start,
output ll_read_ready,
input [31:0] ll_read_data,
input ll_read_strobe,
input ll_read_finished,
input ll_read_crc_ok,
input ll_remote_abort,
output [3:0] lax_state
);
//Parameters
parameter IDLE = 4'h0;
parameter READ_FIS = 4'h1;
parameter WAIT_FOR_END = 4'h2;
parameter CHECK_FIS_TYPE = 4'h1;
parameter WRITE_H2D_REG = 4'h2;
parameter RETRY = 4'h3;
parameter READ_D2H_REG = 4'h4;
parameter READ_PIO_SETUP = 4'h5;
parameter READ_SET_DEVICE_BITS = 4'h6;
parameter DMA_ACTIVATE = 4'h7;
parameter SEND_DATA = 4'h8;
parameter READ_DATA = 4'h9;
//Registers/Wires
reg [3:0] fis_id_state;
reg [7:0] current_fis;
reg [3:0] state;
reg detect_fis;
wire processing_fis;
//data direction
wire data_direction;
//Detect FIS from the device
wire detect_d2h_reg;
wire detect_dma_activate;
wire detect_dma_setup;
wire detect_d2h_data;
wire detect_pio_setup;
wire detect_set_device_bits;
//control data signals
wire [31:0] register_fis [5:0];
reg [7:0] register_fis_ptr;
reg cmd_bit;
reg reg_write_start;
wire [31:0] reg_write_data;
wire [23:0] reg_write_size;
reg reg_write_ready;
wire reg_write_hold;
wire reg_write_abort;
wire reg_write_strobe;
//read register
wire reg_read;
wire reg_write;
reg [7:0] reg_read_count;
wire reg_read_stb;
//data state machine signals
reg data_write_start;
wire data_write_strobe;
wire data_read_strobe;
wire [23:0] data_write_size;
wire [31:0] data_write_data;
wire data_write_hold;
wire data_write_abort;
reg data_read_ready;
reg send_data_fis_id;
reg ll_write_finished_en;
//Asnchronous Logic
assign lax_state = state;
assign transport_layer_ready = (state == IDLE) && link_layer_ready;
assign ll_sync_escape = sync_escape;
assign xmit_error = ll_xmit_error;
//Attach Control/Data Signals to link layer depending on the conditions
//Write Control
assign ll_write_start = (reg_write) ? reg_write_start : data_write_start;
assign ll_write_data = (reg_write) ? register_fis[register_fis_ptr] : data_write_data;
assign ll_write_size = (reg_write) ? reg_write_size : data_write_size;
assign ll_write_hold = (reg_write) ? 1'b0 : data_write_hold;
assign ll_write_abort = (reg_write) ? 1'b0 : data_write_abort;
assign cl_if_strobe = (reg_write) ? 1'b0 : (!send_data_fis_id && data_write_strobe);
//Read Control
assign ll_read_ready = (reg_read) ? 1'b1 : data_read_ready;
assign cl_of_strobe = (reg_read) ? 1'b0 : ((state == READ_DATA) && data_read_strobe);
assign cl_of_data = ll_read_data;
//Data Register Write Control Signals
assign data_write_data = (send_data_fis_id) ? {24'h000, `FIS_DATA} : cl_if_data;
//the first DWORD is the FIS ID
assign data_write_size = cl_if_size + 24'h1;
//Add 1 to the size so that there is room for the FIS ID
assign data_write_strobe = ll_write_strobe;
assign data_read_strobe = ll_read_strobe;
assign data_write_hold = 1'b0;
//There should never be a hold on the data becuase the CL will set it up
assign data_write_abort = 1'b0;
assign read_crc_error = !ll_read_crc_ok;
//H2D Register Write control signals
assign reg_write_strobe = ll_write_strobe;
assign reg_write_size = `FIS_H2D_REG_SIZE;
assign reg_write_hold = 1'b0;
assign reg_write_abort = 1'b0;
assign reg_write = (state == WRITE_H2D_REG) || (send_command_stb || send_control_stb);
//D2H Register Read control signals
assign reg_read = (state == READ_D2H_REG) || detect_d2h_reg ||
(state == READ_PIO_SETUP) || detect_pio_setup ||
(state == READ_SET_DEVICE_BITS) || detect_set_device_bits;
assign reg_read_stb = ll_read_strobe;
//Data Read control signals
//Detect Signals
assign processing_fis = (state == READ_FIS);
assign detect_d2h_reg = detect_fis ? (ll_read_data[7:0] == `FIS_D2H_REG) : (current_fis == `FIS_D2H_REG );
assign detect_dma_activate = detect_fis ? (ll_read_data[7:0] == `FIS_DMA_ACT) : (current_fis == `FIS_DMA_ACT );
assign detect_d2h_data = detect_fis ? (ll_read_data[7:0] == `FIS_DATA) : (current_fis == `FIS_DATA );
assign detect_dma_setup = detect_fis ? (ll_read_data[7:0] == `FIS_DMA_SETUP) : (current_fis == `FIS_DMA_SETUP );
assign detect_pio_setup = detect_fis ? (ll_read_data[7:0] == `FIS_PIO_SETUP) : (current_fis == `FIS_PIO_SETUP );
assign detect_set_device_bits = detect_fis ? (ll_read_data[7:0] == `FIS_SET_DEV_BITS) : (current_fis == `FIS_SET_DEV_BITS );
assign register_fis[0] = {h2d_features[7:0], h2d_command, cmd_bit, 3'b000, h2d_port_mult, `FIS_H2D_REG};
assign register_fis[1] = {h2d_device, h2d_lba[23:0]};
assign register_fis[2] = {h2d_features[15:8], h2d_lba[47:24]};
assign register_fis[3] = {h2d_control, 8'h00, h2d_sector_count};
assign register_fis[4] = {32'h00000000};
//Synchronous Logic
//FIS ID State machine
always @ (posedge clk) begin
if (rst) begin
fis_id_state <= IDLE;
detect_fis <= 0;
current_fis <= 0;
d2h_fis <= 0;
end
else begin
//in order to set all the detect_* high when the actual fis is detected send this strobe
if(ll_read_finished) begin
current_fis <= 0;
fis_id_state <= IDLE;
end
else begin
case (fis_id_state)
IDLE: begin
current_fis <= 0;
detect_fis <= 0;
if (ll_read_start) begin
detect_fis <= 1;
fis_id_state <= READ_FIS;
end
end
READ_FIS: begin
if (ll_read_strobe) begin
detect_fis <= 0;
current_fis <= ll_read_data[7:0];
d2h_fis <= ll_read_data[7:0];
fis_id_state <= WAIT_FOR_END;
end
end
WAIT_FOR_END: begin
if (ll_read_finished) begin
current_fis <= 0;
fis_id_state <= IDLE;
end
end
default: begin
fis_id_state <= IDLE;
end
endcase
end
end
end
//main DATA state machine
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
cl_of_activate <= 0;
cl_if_activate <= 0;
data_read_ready <= 0;
//Data Send
send_data_fis_id <= 0;
//H2D Register
register_fis_ptr <= 0;
reg_write_start <= 0;
//D2H Register
reg_read_count <= 0;
//Device Status
d2h_interrupt <= 0;
d2h_notification <= 0;
d2h_port_mult <= 0;
d2h_lba <= 0;
d2h_sector_count <= 0;
d2h_status <= 0;
d2h_error <= 0;
d2h_reg_stb <= 0;
d2h_data_stb <= 0;
pio_setup_stb <= 0;
set_device_bits_stb <= 0;
dma_activate_stb <= 0;
dma_setup_stb <= 0;
remote_abort <= 0;
cmd_bit <= 0;
//PIO
pio_transfer_count <= 0;
pio_e_status <= 0;
pio_direction <= 0;
pio_response <= 0;
data_write_start <= 0;
ll_write_finished_en <= 0;
end
else begin
//Strobed signals
if (phy_ready) begin
//only deassert a link layer strobe when Phy is ready and not sending aligns
data_write_start <= 0;
reg_write_start <= 0;
end
d2h_reg_stb <= 0;
d2h_data_stb <= 0;
pio_setup_stb <= 0;
set_device_bits_stb <= 0;
dma_activate_stb <= 0;
dma_setup_stb <= 0;
remote_abort <= 0;
d2h_device <= 0;
//Always attempt to get a free buffer
if ((cl_of_activate == 0) && (cl_of_ready > 0)) begin
if (cl_of_ready[0]) begin
cl_of_activate[0] <= 1;
end
else begin
cl_of_activate[1] <= 1;
end
data_read_ready <= 1;
end
else if (cl_of_activate == 0) begin
//XXX: NO BUFFER AVAILABLE!!!! Can't accept new data from the Hard Drive
data_read_ready <= 0;
end
//Always attempt to get the incomming buffer
if (cl_if_ready && !cl_if_activate) begin
cl_if_activate <= 1;
end
if (ll_write_finished) begin
ll_write_finished_en <= 1;
end
case (state)
IDLE: begin
register_fis_ptr <= 0;
reg_read_count <= 0;
cmd_bit <= 0;
ll_write_finished_en <= 0;
//Detect a FIS
if(ll_read_start) begin
//detect the start of a frame
state <= CHECK_FIS_TYPE;
//Clear Errors when a new transaction starts
end
//Send Register
if (send_command_stb || send_control_stb) begin
//Clear Errors when a new transaction starts
if (send_command_stb) begin
cmd_bit <= 1;
end
else if (send_control_stb) begin
cmd_bit <= 0;
end
reg_write_start <= 1;
state <= WRITE_H2D_REG;
end
//Send Data
else if (send_data_stb) begin
//Clear Errors when a new transaction starts
data_write_start <= 1;
send_data_fis_id <= 1;
state <= SEND_DATA;
end
end
CHECK_FIS_TYPE: begin
if (detect_dma_setup) begin
//XXX: Future work!
reg_read_count <= reg_read_count + 8'h1;
state <= IDLE;
end
else if (detect_dma_activate) begin
//hard drive is ready to receive data
state <= DMA_ACTIVATE;
reg_read_count <= reg_read_count + 8'h1;
//state <= IDLE;
end
else if (detect_d2h_data) begin
//incomming data, because the out FIFO is directly connected to the output during a read
state <= READ_DATA;
end
else if (detect_d2h_reg) begin
//store the error, status interrupt from this read
d2h_status <= ll_read_data[23:16];
d2h_error <= ll_read_data[31:24];
d2h_interrupt <= ll_read_data[14];
d2h_port_mult <= ll_read_data[11:8];
state <= READ_D2H_REG;
reg_read_count <= reg_read_count + 8'h1;
end
else if (detect_pio_setup) begin
//store the error, status, direction interrupt from this read
pio_response <= 1;
d2h_status <= ll_read_data[23:16];
d2h_error <= ll_read_data[31:24];
d2h_interrupt <= ll_read_data[14];
pio_direction <= ll_read_data[13];
d2h_port_mult <= ll_read_data[11:8];
state <= READ_PIO_SETUP;
reg_read_count <= reg_read_count + 8'h1;
end
else if (detect_set_device_bits) begin
//store the error, a subset of the status bit and the interrupt
state <= IDLE;
d2h_status[6:4] <= ll_read_data[22:20];
d2h_status[2:0] <= ll_read_data[18:16];
d2h_error <= ll_read_data[31:24];
d2h_notification <= ll_read_data[15];
d2h_interrupt <= ll_read_data[14];
d2h_port_mult <= ll_read_data[11:8];
state <= READ_SET_DEVICE_BITS;
end
else if (ll_read_finished) begin
//unrecognized FIS
state <= IDLE;
end
end
WRITE_H2D_REG: begin
if (register_fis_ptr < `FIS_H2D_REG_SIZE) begin
if (reg_write_strobe) begin
register_fis_ptr <= register_fis_ptr + 8'h1;
end
end
if (ll_write_finished_en) begin
if (ll_xmit_error) begin
state <= RETRY;
end
else begin
state <= IDLE;
end
end
end
RETRY: begin
if (link_layer_ready) begin
ll_write_finished_en <= 0;
reg_write_start <= 1;
register_fis_ptr <= 0;
state <= WRITE_H2D_REG;
end
end
READ_D2H_REG: begin
case (reg_read_count)
1: begin
d2h_device <= ll_read_data[31:24];
d2h_lba[23:0] <= ll_read_data[23:0];
end
2: begin
d2h_lba[47:24] <= ll_read_data[23:0];
end
3: begin
d2h_sector_count <= ll_read_data[15:0];
end
4: begin
end
default: begin
end
endcase
if (reg_read_stb) begin
reg_read_count <= reg_read_count + 8'h1;
end
if (ll_read_finished) begin
d2h_reg_stb <= 1;
state <= IDLE;
end
end
READ_PIO_SETUP: begin
case (reg_read_count)
1: begin
d2h_device <= ll_read_data[31:24];
d2h_lba[23:0] <= ll_read_data[23:0];
end
2: begin
d2h_lba[47:24] <= ll_read_data[23:0];
end
3: begin
d2h_sector_count <= ll_read_data[15:0];
pio_e_status <= ll_read_data[31:24];
end
4: begin
pio_transfer_count <= ll_read_data[15:0];
end
default: begin
end
endcase
if (reg_read_stb) begin
reg_read_count <= reg_read_count + 8'h1;
end
if (ll_read_finished) begin
pio_setup_stb <= 1;
state <= IDLE;
end
end
READ_SET_DEVICE_BITS: begin
state <= IDLE;
set_device_bits_stb <= 1;
end
DMA_ACTIVATE: begin
state <= IDLE;
dma_activate_stb <= 1;
end
SEND_DATA: begin
if (ll_write_strobe && send_data_fis_id) begin
send_data_fis_id <= 0;
end
if (ll_write_finished_en) begin
cl_if_activate <= 0;
state <= IDLE;
if (pio_response) begin
//write the end status to the status pin
d2h_status <= pio_e_status;
end
end
end
READ_DATA: begin
//NOTE: the data_read_ready will automatically 'flow control' the data from the link layer
//so we don't have to check it here
//NOTE: We don't have to keep track of the count because the lower level will give a max of 2048 DWORDS
if (ll_read_finished) begin
//deactivate FIFO
d2h_data_stb <= 1;
cl_of_activate <= 0;
state <= IDLE;
if (pio_response) begin
//write the end status to the status pin
d2h_status <= pio_e_status;
end
end
end
default: begin
state <= IDLE;
end
endcase
if (sync_escape) begin
state <= IDLE;
end
end
end
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: completer_pkt_gen
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Completer Packet Generator module. This block creates the header
// info for completer packets- it also passes along the data source and
// address info for the TRN state machine block to request the data from
// the egress data presenter.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module completer_pkt_gen(
input clk,
input rst,
//interface from RX Engine
input [6:0] bar_hit, //denotes which base address was hit
input comp_req, //gets asserted when the rx engine recevies a MemRd request
input [31:0] MEM_addr, //needed to fetch data from egress_data_presenter
input [15:0] MEM_req_id,//needed for completion header
input [15:0] comp_id, //needed for completion header
input [7:0] MEM_tag, //neede for completion header
//interface to completion header fifo
output reg comp_fifo_wren,
output reg [63:0] comp_fifo_data
);
//State machine states
localparam IDLE = 4'h0;
localparam HEAD1 = 4'h1;
localparam HEAD2 = 4'h2;
//parameters used to define fixed header fields
localparam rsvd = 1'b0;
localparam fmt = 2'b10; //always with data
localparam CplD = 5'b01010; //completer
localparam TC = 3'b000;
localparam TD = 1'b0;
localparam EP = 1'b0;
localparam ATTR = 2'b00;
localparam Length = 10'b0000000001; //length is always one DWORD
localparam ByteCount = 12'b000000000100; //BC is always one DWORD
localparam BCM = 1'b0;
reg [3:0] state;
reg [6:0] bar_hit_reg;
reg [26:0] MEM_addr_reg;
reg [15:0] MEM_req_id_reg;
reg [15:0] comp_id_reg;
reg [7:0] MEM_tag_reg;
reg rst_reg;
always@(posedge clk) rst_reg <= rst;
//if there is a memory read request then latch the header information
//needed to create the completion TLP header
always@(posedge clk)begin
if(comp_req)begin
bar_hit_reg <= bar_hit;
MEM_addr_reg[26:0] <= MEM_addr[26:0];
MEM_req_id_reg <= MEM_req_id;
comp_id_reg <= comp_id;
MEM_tag_reg <= MEM_tag;
end
end
// State machine
// Builds headers for completion TLP headers
// Writes them into a FIFO
always @ (posedge clk) begin
if (rst_reg) begin
comp_fifo_data <= 0;
comp_fifo_wren <= 1'b0;
state <= IDLE;
end else begin
case (state)
IDLE : begin
comp_fifo_data <= 0;
comp_fifo_wren <= 1'b0;
if(comp_req)
state<= HEAD1;
else
state<= IDLE;
end
HEAD1 : begin //create first 64-bit completion TLP header
//NOTE: bar_hit_reg[6:0],MEM_addr_reg[26:2] are not part of completion TLP
//header but are used by tx_trn_sm module to fetch data from the
//egress_data_presenter
comp_fifo_data <= {bar_hit_reg[6:0],MEM_addr_reg[26:2],
rsvd,fmt,CplD,rsvd,TC,rsvd,rsvd,rsvd,rsvd,
TD,EP,ATTR,rsvd,rsvd,Length};
comp_fifo_wren <= 1'b1; //write to comp header fifo
state <= HEAD2;
end
HEAD2 : begin //create second 64-bit completion TLP header
comp_fifo_data <= {comp_id_reg[15:0],3'b000, BCM,ByteCount,
MEM_req_id_reg[15:0],MEM_tag_reg[7:0],rsvd,
MEM_addr_reg[6:0]};
comp_fifo_wren <= 1'b1; //write to comp header fifo
state <= IDLE;
end
default : begin
comp_fifo_data <= 0;
comp_fifo_wren <= 1'b0;
state <= IDLE;
end
endcase
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// The code as shown makes a really big file name with Verilator.
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Todd Strader.
`define LONG_NAME_MOD modlongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie
`define LONG_NAME_SUB sublongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie
`define LONG_NAME_VAR varlongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie
module t ();
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
logic `LONG_NAME_VAR;
`LONG_NAME_MOD
`LONG_NAME_SUB
();
endmodule
module `LONG_NAME_MOD ();
// Force Verilator to make a new class
logic a1 /* verilator public */;
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
module altera_up_video_dma_to_memory (
// Inputs
clk,
reset,
stream_data,
stream_startofpacket,
stream_endofpacket,
stream_empty,
stream_valid,
master_waitrequest,
// Bidirectional
// Outputs
stream_ready,
master_write,
master_writedata,
inc_address,
reset_address
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Frame's datawidth
parameter EW = 0; // Frame's empty width
parameter MDW = 15; // Avalon master's datawidth
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_data;
input stream_startofpacket;
input stream_endofpacket;
input [EW: 0] stream_empty;
input stream_valid;
input master_waitrequest;
// Bidirectional
// Outputs
output stream_ready;
output master_write;
output [MDW:0] master_writedata;
output inc_address;
output reset_address;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [DW: 0] temp_data;
reg temp_valid;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
always @(posedge clk)
begin
if (reset & ~master_waitrequest)
begin
temp_data <= 'h0;
temp_valid <= 1'b0;
end
else if (stream_ready)
begin
temp_data <= stream_data;
temp_valid <= stream_valid;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_ready = ~reset & (~temp_valid | ~master_waitrequest);
assign master_write = temp_valid;
assign master_writedata = temp_data;
assign inc_address = stream_ready & stream_valid;
assign reset_address = inc_address & stream_startofpacket;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: IIT Roorkee
// Engineers: Rohith Asrk, Nitin Sethi, Sri Vathsa, Shashwat Kumar
//
// Create Date: 12:37:36 05/01/2017
// Design Name: main
// Module Name: main_test
// Project Name: FPGA Implementation of Image Watermarking
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: main
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module main_test;
// Inputs
reg clk;
// Outputs
wire [7:0] IM_Data_out;
reg [7:0] Data1, Data2, Data3, Data4;
// Instantiate the Unit Under Test (UUT)
main uut (
.clk(clk),
.Data1(Data1),
.Data2(Data2),
.Data3(Data3),
.Data4(Data4),
.IM_Data_out(IM_Data_out)
);
initial begin
// Initialize Inputs
clk = 0;
// Wait 100 ns for global reset to finish
#100
Data1 = 8'b10000000;
Data2 = 8'b00001000;
Data3 = 8'b00100000;
Data4 = 8'b00000010;
#100
Data1 = 8'b11000000;
Data2 = 8'b00001100;
Data3 = 8'b00110000;
Data4 = 8'b00000011;
#100
Data1 = 8'b01101010;
Data2 = 8'b01110010;
Data3 = 8'b01101011;
Data4 = 8'b10101010;
// Add stimulus here
end
always begin
#5 clk=~clk;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:32:01 03/03/2015
// Design Name:
// Module Name: seven_segment
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// Decode 4 bits into seven-segment representation
module seven_segment_decoder(value, dp, segments);
input [3:0] value;
input dp;
output reg [7:0] segments;
// Decode 4-bit hex or bcd digit to lit segments.
// The segments are controlled by the cathode (negative electrode)
// so they are active low, meaning 0 is on and 1 is off.
//
// Segment legend:
//
// _a_
// f|_g_|b
// e|_d_|c .dp
//
always @(value, dp) begin
case (value)
// Segment columns: abcdefg
4'h1 : segments = 7'b1001111;
4'h2 : segments = 7'b0010010;
4'h3 : segments = 7'b0000110;
4'h4 : segments = 7'b1001100;
4'h5 : segments = 7'b0100100;
4'h6 : segments = 7'b0100000;
4'h7 : segments = 7'b0001111;
4'h8 : segments = 7'b0000000;
4'h9 : segments = 7'b0000100;
4'hA : segments = 7'b0001000;
4'hB : segments = 7'b1100000; // lower case
4'hC : segments = 7'b0110001;
4'hD : segments = 7'b1000010; // lower case
4'hE : segments = 7'b0110000;
4'hF : segments = 7'b0111000;
4'h0 : segments = 7'b0000001;
default : segments = 7'b1111111;
endcase
segments[7] = ~dp;
end
endmodule
// Display a value on a multiplexed seven segment display
module seven_segment_mux(clk, value, dp, segments, anodes);
// Refresh the seven segment display too fast, and it will ghost; too slow, and it will flicker.
// See http://en.wikipedia.org/wiki/Flicker_fusion_threshold for more information.
// I have found that a refresh rate of around 14
// Calculates the number of bits required for a given value
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2 = 0; value > 0; clog2 = clog2 + 1)
value = value >> 1;
end
endfunction
// Number of digits in the display
parameter WIDTH = 3;
input clk;
input [4*WIDTH-1:0] value;
input [WIDTH-1:0] dp;
output [7:0] segments;
output [WIDTH-1:0] anodes;
reg [clog2(WIDTH)-1:0] active = 0;
// Decode the 4 bits containing the current digit
seven_segment_decoder decoder(.value(value[active*4 +: 4]), .dp(dp[active]), .segments(segments));
// Anodes are driven by a PNP transistor which inverts its input, so they're active low
// and we have to invert the output another time to get the correct digit to light up.
assign anodes = ~(1 << active);
// Cycle through multiplexed digits on each clock pulse.
always @(posedge clk) active <= (active < WIDTH) ? (active + 1) : 0;
endmodule |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_pipe_misc_v6.v
// Version : 2.4
//--
//-- Description: Misc PIPE module for Virtex6 PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_pipe_misc_v6 #
(
parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
)
(
input wire pipe_tx_rcvr_det_i ,
input wire pipe_tx_reset_i ,
input wire pipe_tx_rate_i ,
input wire pipe_tx_deemph_i ,
input wire [2:0] pipe_tx_margin_i ,
input wire pipe_tx_swing_i ,
output wire pipe_tx_rcvr_det_o ,
output wire pipe_tx_reset_o ,
output wire pipe_tx_rate_o ,
output wire pipe_tx_deemph_o ,
output wire [2:0] pipe_tx_margin_o ,
output wire pipe_tx_swing_o ,
input wire pipe_clk ,
input wire rst_n
);
//******************************************************************//
// Reality check. //
//******************************************************************//
localparam TCQ = 1; // clock to out delay model
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
reg pipe_tx_rcvr_det_qq ;
reg pipe_tx_reset_qq ;
reg pipe_tx_rate_qq ;
reg pipe_tx_deemph_qq ;
reg [2:0] pipe_tx_margin_qq ;
reg pipe_tx_swing_qq ;
generate
if (PIPE_PIPELINE_STAGES == 0) begin
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i;
assign pipe_tx_reset_o = pipe_tx_reset_i;
assign pipe_tx_rate_o = pipe_tx_rate_i;
assign pipe_tx_deemph_o = pipe_tx_deemph_i;
assign pipe_tx_margin_o = pipe_tx_margin_i;
assign pipe_tx_swing_o = pipe_tx_swing_i;
end else if (PIPE_PIPELINE_STAGES == 1) begin
always @(posedge pipe_clk) begin
if (rst_n) begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
end else begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_q;
assign pipe_tx_reset_o = pipe_tx_reset_q;
assign pipe_tx_rate_o = pipe_tx_rate_q;
assign pipe_tx_deemph_o = pipe_tx_deemph_q;
assign pipe_tx_margin_o = pipe_tx_margin_q;
assign pipe_tx_swing_o = pipe_tx_swing_q;
end else if (PIPE_PIPELINE_STAGES == 2) begin
always @(posedge pipe_clk) begin
if (rst_n) begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
pipe_tx_rcvr_det_qq <= #TCQ 0;
pipe_tx_reset_qq <= #TCQ 1'b1;
pipe_tx_rate_qq <= #TCQ 0;
pipe_tx_deemph_qq <= #TCQ 1'b1;
pipe_tx_margin_qq <= #TCQ 0;
pipe_tx_swing_qq <= #TCQ 0;
end else begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
pipe_tx_rcvr_det_qq <= #TCQ pipe_tx_rcvr_det_q;
pipe_tx_reset_qq <= #TCQ pipe_tx_reset_q;
pipe_tx_rate_qq <= #TCQ pipe_tx_rate_q;
pipe_tx_deemph_qq <= #TCQ pipe_tx_deemph_q;
pipe_tx_margin_qq <= #TCQ pipe_tx_margin_q;
pipe_tx_swing_qq <= #TCQ pipe_tx_swing_q;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_qq;
assign pipe_tx_reset_o = pipe_tx_reset_qq;
assign pipe_tx_rate_o = pipe_tx_rate_qq;
assign pipe_tx_deemph_o = pipe_tx_deemph_qq;
assign pipe_tx_margin_o = pipe_tx_margin_qq;
assign pipe_tx_swing_o = pipe_tx_swing_qq;
end
endgenerate
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_sextend(clock, resetn,
i_datain, i_datain_valid, o_datain_stall,
o_dataout, i_dataout_stall, o_dataout_valid);
parameter DATAIN_WIDTH = 32;
parameter DATAOUT_WIDTH = 64;
input clock, resetn;
input [DATAIN_WIDTH-1:0] i_datain;
input i_datain_valid;
output o_datain_stall;
output [DATAOUT_WIDTH-1:0] o_dataout;
input i_dataout_stall;
output o_dataout_valid;
assign o_dataout = {{DATAOUT_WIDTH{i_datain[DATAIN_WIDTH-1]}}, i_datain[DATAIN_WIDTH-1:0]};
assign o_datain_stall = i_dataout_stall;
assign o_dataout_valid = i_datain_valid;
endmodule
|
module lut(clk,f, state);
/* This module contains the framework for an eighty-state look-up table.
It takes a seed value followed by an arbitrary list of 79 corner values in
ascending order and uses if-else conditionals, selecting
if(val<val0), state0, if(val<val1), state1, ..., else state_80.
State changes are made on clock edges.
*/
input clk;
input [13:0] f;
output reg [6:0] state;
//Note that this file should not be included in the project because it is not
//a fully-defined Verilog entity, but a snippet of code. It should
//remain in the working directory, however.
//Load corner frequencies.
`include "cornerFreq.v"
always @(posedge clk) begin
//For now, limit to the 4 states that will be used in the initial 1-board tests.
if(f<fc[0]) state=7'b1010000; //Lowest frequency - hold state for all frequencies lower.
else if(f<fc[1]) state=7'b1001111;
else if(f<fc[2]) state=7'b1001110;
else if(f<fc[3]) state=7'b1001101;
else if(f<fc[4]) state=7'b1001100;
else if(f<fc[5]) state=7'b1001011;
else if(f<fc[6]) state=7'b1001010;
else if(f<fc[7]) state=7'b1001001;
else if(f<fc[8]) state=7'b1001000;
else if(f<fc[9]) state=7'b1000111;
else if(f<fc[10]) state=7'b1000110;
else if(f<fc[11]) state=7'b1000101;
else if(f<fc[12]) state=7'b1000100;
else if(f<fc[13]) state=7'b1000011;
else if(f<fc[14]) state=7'b1000010;
else if(f<fc[15]) state=7'b1000001;
else if(f<fc[16]) state=7'b1000000;
else if(f<fc[17]) state=7'b111111;
else if(f<fc[18]) state=7'b111110;
else if(f<fc[19]) state=7'b111101;
else if(f<fc[20]) state=7'b111100;
else if(f<fc[21]) state=7'b111011;
else if(f<fc[22]) state=7'b111010;
else if(f<fc[23]) state=7'b111001;
else if(f<fc[24]) state=7'b111000;
else if(f<fc[25]) state=7'b110111;
else if(f<fc[26]) state=7'b110110;
else if(f<fc[27]) state=7'b110101;
else if(f<fc[28]) state=7'b110100;
else if(f<fc[29]) state=7'b110011;
else if(f<fc[30]) state=7'b110010;
else if(f<fc[31]) state=7'b110001;
else if(f<fc[32]) state=7'b110000;
else if(f<fc[33]) state=7'b101111;
else if(f<fc[34]) state=7'b101110;
else if(f<fc[35]) state=7'b101101;
else if(f<fc[36]) state=7'b101100;
else if(f<fc[37]) state=7'b101011;
else if(f<fc[38]) state=7'b101010;
else if(f<fc[39]) state=7'b101001;
else if(f<fc[40]) state=7'b101000;
else if(f<fc[41]) state=7'b100111;
else if(f<fc[42]) state=7'b100110;
else if(f<fc[43]) state=7'b100101;
else if(f<fc[44]) state=7'b100100;
else if(f<fc[45]) state=7'b100011;
else if(f<fc[46]) state=7'b100010;
else if(f<fc[47]) state=7'b100001;
else if(f<fc[48]) state=7'b100000;
else if(f<fc[49]) state=7'b11111;
else if(f<fc[50]) state=7'b11110;
else if(f<fc[51]) state=7'b11101;
else if(f<fc[52]) state=7'b11100;
else if(f<fc[53]) state=7'b11011;
else if(f<fc[54]) state=7'b11010;
else if(f<fc[55]) state=7'b11001;
else if(f<fc[56]) state=7'b11000;
else if(f<fc[57]) state=7'b10111;
else if(f<fc[58]) state=7'b10110;
else if(f<fc[59]) state=7'b10101;
else if(f<fc[60]) state=7'b10100;
else if(f<fc[61]) state=7'b10011;
else if(f<fc[62]) state=7'b10010;
else if(f<fc[63]) state=7'b10001;
else if(f<fc[64]) state=7'b10000;
else if(f<fc[65]) state=7'b1111;
else if(f<fc[66]) state=7'b1110;
else if(f<fc[67]) state=7'b1101;
else if(f<fc[68]) state=7'b1100;
else if(f<fc[69]) state=7'b1011;
else if(f<fc[70]) state=7'b1010;
else if(f<fc[71]) state=7'b1001;
else if(f<fc[72]) state=7'b1000;
else if(f<fc[73]) state=7'b111;
else if(f<fc[74]) state=7'b110;
else if(f<fc[75]) state=7'b101;
else if(f<fc[76]) state=7'b100;
else if(f<fc[77]) state=7'b11;
else if(f<fc[78]) state=7'b10;
else if(f<fc[79]) state=7'b1;
else state=7'b0; //Highest frequency - baseload for all frequencies higher.
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// NPCG_Toggle_SCC_PI_reset for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPCG_Toggle_SCC_PI_reset
// Module Name: NPCG_Toggle_SCC_PI_reset
// File Name: NPCG_Toggle_SCC_PI_reset.v
//
// Version: v1.0.0
//
// Description: NFC phy input module reset
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPCG_Toggle_SCC_PI_reset
#
(
parameter NumberOfWays = 4
)
(
iSystemClock,
iReset ,
iOpcode ,
iTargetID ,
iSourceID ,
iCMDValid ,
oCMDReady ,
oStart ,
oLastStep ,
iPM_Ready ,
iPM_LastStep,
oPM_PCommand
);
input iSystemClock ;
input iReset ;
input [5:0] iOpcode ;
input [4:0] iTargetID ;
input [4:0] iSourceID ;
input iCMDValid ;
output oCMDReady ;
output oStart ;
output oLastStep ;
input [7:0] iPM_Ready ;
input [7:0] iPM_LastStep ;
output [7:0] oPM_PCommand ;
wire wModuleTriggered;
localparam State_Idle = 3'b000;
localparam State_PIResetIssue = 3'b001;
localparam State_PIWait = 3'b011;
reg [2:0] rCurState ;
reg [2:0] rNextState ;
wire wPIResetTrig;
always @ (posedge iSystemClock)
if (iReset)
rCurState <= State_Idle;
else
rCurState <= rNextState;
always @ (*)
case (rCurState)
State_Idle:
rNextState <= (wModuleTriggered)?State_PIResetIssue:State_Idle;
State_PIResetIssue:
rNextState <= (iPM_Ready)?State_PIWait:State_PIResetIssue;
State_PIWait:
rNextState <= (oLastStep)?State_Idle:State_PIWait;
default:
rNextState <= State_Idle;
endcase
assign wModuleTriggered = (iCMDValid && iTargetID == 5'b00101 && iOpcode == 6'b110010);
assign oCMDReady = (rCurState == State_Idle);
assign wPIResetTrig = (rCurState == State_PIResetIssue);
assign oStart = wModuleTriggered;
assign oLastStep = (rCurState == State_PIWait) & iPM_LastStep[4];
assign oPM_PCommand[7:0] = {1'b0, 1'b0, 1'b0, wPIResetTrig, 1'b0, 1'b0, 1'b0, 1'b0};
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file eimram.v when simulating
// the core, eimram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module eimram(
clka,
ena,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input ena;
input [1 : 0] wea;
input [14 : 0] addra;
input [15 : 0] dina;
input clkb;
input [14 : 0] addrb;
output [15 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(15),
.C_ADDRB_WIDTH(15),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(32768),
.C_READ_DEPTH_B(32768),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(1),
.C_USE_BYTE_WEB(1),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(2),
.C_WEB_WIDTH(2),
.C_WRITE_DEPTH_A(32768),
.C_WRITE_DEPTH_B(32768),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// SPDX-License-Identifier: CC0-1.0
/* verilator lint_off LITENDIAN */
module some_module (
input wrclk
);
logic [ 1 : 0 ] some_state;
logic [1:0] some_other_state;
always @(posedge wrclk) begin
case (some_state)
2'b11:
if (some_other_state == 0)
some_state <= 2'b00;
default:
$display ("This is a display statement");
endcase
if (wrclk)
some_other_state <= 0;
end
endmodule
`define BROKEN
module t1(
input [-12:-9] i_clks,
input i_clk0,
input i_clk1
);
some_module
some_module
(
`ifdef BROKEN
.wrclk (i_clks[-12])
`else
.wrclk (i_clk1)
`endif
);
endmodule
module t2(
input [2:0] i_clks,
input i_clk0,
input i_clk1,
input i_clk2,
input i_data
);
logic [-12:-9] the_clks;
logic data_q;
assign the_clks[-12] = i_clk1;
assign the_clks[-11] = i_clk2;
assign the_clks[-10] = i_clk1;
assign the_clks[-9] = i_clk0;
always @(posedge i_clk0) begin
data_q <= i_data;
end
t1 t1
(
.i_clks (the_clks),
.i_clk0 (i_clk0),
.i_clk1 (i_clk1)
);
endmodule
module t(
input clk0 /*verilator clocker*/,
input clk1 /*verilator clocker*/,
input clk2 /*verilator clocker*/,
input data_in
);
logic [2:0] clks;
assign clks = {1'b0, clk1, clk0};
t2
t2
(
.i_clks (clks),
.i_clk0 (clk0),
.i_clk1 (clk1),
.i_clk2 (clk2),
.i_data (data_in)
);
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FILL_PP_SYMBOL_V
`define SKY130_FD_SC_MS__FILL_PP_SYMBOL_V
/**
* fill: Fill cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__fill (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FILL_PP_SYMBOL_V
|
/**
* bsg_cache_non_blocking.v
*
* Non-blocking cache.
*
* @author tommy
*
* For design doc, follow this link.
* https://docs.google.com/document/d/1hf4WgCuf4CGjPMZXH5AplK7k9wtcAN2uw2moZhroryU/edit
*/
`include "bsg_defines.v"
module bsg_cache_non_blocking
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(id_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(sets_p)
, parameter `BSG_INV_PARAM(ways_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(miss_fifo_els_p)
, parameter cache_pkt_width_lp=`bsg_cache_non_blocking_pkt_width(id_width_p,addr_width_p,data_width_p)
, parameter dma_pkt_width_lp=`bsg_cache_non_blocking_dma_pkt_width(addr_width_p)
)
(
input clk_i
, input reset_i
, input v_i
, input [cache_pkt_width_lp-1:0] cache_pkt_i
, output logic ready_o
, output logic v_o
, output logic [id_width_p-1:0] id_o
, output logic [data_width_p-1:0] data_o
, input yumi_i
, output logic [dma_pkt_width_lp-1:0] dma_pkt_o
, output logic dma_pkt_v_o
, input dma_pkt_yumi_i
, input [data_width_p-1:0] dma_data_i
, input dma_data_v_i
, output logic dma_data_ready_o
, output logic [data_width_p-1:0] dma_data_o
, output logic dma_data_v_o
, input dma_data_yumi_i
);
// localparam
//
localparam lg_ways_lp = `BSG_SAFE_CLOG2(ways_p);
localparam lg_sets_lp = `BSG_SAFE_CLOG2(sets_p);
localparam lg_block_size_in_words_lp = `BSG_SAFE_CLOG2(block_size_in_words_p);
localparam byte_sel_width_lp = `BSG_SAFE_CLOG2(data_width_p>>3);
localparam tag_width_lp = (addr_width_p-lg_sets_lp-lg_block_size_in_words_lp-byte_sel_width_lp);
// declare structs
//
`declare_bsg_cache_non_blocking_data_mem_pkt_s(ways_p,sets_p,block_size_in_words_p,data_width_p);
`declare_bsg_cache_non_blocking_stat_mem_pkt_s(ways_p,sets_p);
`declare_bsg_cache_non_blocking_tag_mem_pkt_s(ways_p,sets_p,data_width_p,tag_width_lp);
`declare_bsg_cache_non_blocking_miss_fifo_entry_s(id_width_p,addr_width_p,data_width_p);
`declare_bsg_cache_non_blocking_dma_cmd_s(ways_p,sets_p,tag_width_lp);
// stall signal
// When the pipeline is stalled, DMA can still operate, and move data in and
// output of data_mem. TL stage is not able to access data_mem, but it can
// still enqueue missed requests into miss_fifo. MHU cannot dequeue or invalidate
// an entry from miss FIFO.
wire stall = v_o & ~yumi_i;
// cache pkt
//
`declare_bsg_cache_non_blocking_pkt_s(id_width_p,addr_width_p,data_width_p);
bsg_cache_non_blocking_pkt_s cache_pkt;
assign cache_pkt = cache_pkt_i;
// decode
//
bsg_cache_non_blocking_decode_s decode;
bsg_cache_non_blocking_decode decode0 (
.opcode_i(cache_pkt.opcode)
,.decode_o(decode)
);
// TL stage
//
bsg_cache_non_blocking_data_mem_pkt_s tl_data_mem_pkt_lo;
logic tl_data_mem_pkt_v_lo;
logic tl_data_mem_pkt_ready_li;
logic tl_block_loading;
bsg_cache_non_blocking_stat_mem_pkt_s tl_stat_mem_pkt_lo;
logic tl_stat_mem_pkt_v_lo;
logic tl_stat_mem_pkt_ready_li;
bsg_cache_non_blocking_miss_fifo_entry_s tl_miss_fifo_entry_lo;
logic tl_miss_fifo_v_lo;
logic tl_miss_fifo_ready_li;
logic mgmt_v_lo;
logic [ways_p-1:0] valid_tl_lo;
logic [ways_p-1:0] lock_tl_lo;
logic [ways_p-1:0][tag_width_lp-1:0] tag_tl_lo;
bsg_cache_non_blocking_decode_s decode_tl_lo;
logic [addr_width_p-1:0] addr_tl_lo;
logic [id_width_p-1:0] id_tl_lo;
logic [data_width_p-1:0] data_tl_lo;
logic [lg_ways_lp-1:0] tag_hit_way_lo;
logic tag_hit_found_lo;
logic mgmt_yumi_li;
bsg_cache_non_blocking_tag_mem_pkt_s mhu_tag_mem_pkt_lo;
logic mhu_tag_mem_pkt_v_lo;
logic mhu_idle;
logic mhu_recover;
logic [lg_ways_lp-1:0] curr_mhu_way_id;
logic [lg_sets_lp-1:0] curr_mhu_index;
logic curr_mhu_v;
logic [lg_ways_lp-1:0] curr_dma_way_id;
logic [lg_sets_lp-1:0] curr_dma_index;
logic curr_dma_v;
bsg_cache_non_blocking_tl_stage #(
.id_width_p(id_width_p)
,.addr_width_p(addr_width_p)
,.data_width_p(data_width_p)
,.ways_p(ways_p)
,.sets_p(sets_p)
,.block_size_in_words_p(block_size_in_words_p)
) tl0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(v_i)
,.id_i(cache_pkt.id)
,.addr_i(cache_pkt.addr)
,.data_i(cache_pkt.data)
,.mask_i(cache_pkt.mask)
,.decode_i(decode)
,.ready_o(ready_o)
,.data_mem_pkt_v_o(tl_data_mem_pkt_v_lo)
,.data_mem_pkt_o(tl_data_mem_pkt_lo)
,.data_mem_pkt_ready_i(tl_data_mem_pkt_ready_li)
,.block_loading_o(tl_block_loading)
,.stat_mem_pkt_v_o(tl_stat_mem_pkt_v_lo)
,.stat_mem_pkt_o(tl_stat_mem_pkt_lo)
,.stat_mem_pkt_ready_i(tl_stat_mem_pkt_ready_li)
,.miss_fifo_v_o(tl_miss_fifo_v_lo)
,.miss_fifo_entry_o(tl_miss_fifo_entry_lo)
,.miss_fifo_ready_i(tl_miss_fifo_ready_li)
,.mgmt_v_o(mgmt_v_lo)
,.valid_tl_o(valid_tl_lo)
,.lock_tl_o(lock_tl_lo)
,.tag_tl_o(tag_tl_lo)
,.decode_tl_o(decode_tl_lo)
,.addr_tl_o(addr_tl_lo)
,.id_tl_o(id_tl_lo)
,.data_tl_o(data_tl_lo)
,.tag_hit_way_o(tag_hit_way_lo)
,.tag_hit_found_o(tag_hit_found_lo)
,.mgmt_yumi_i(mgmt_yumi_li)
,.mhu_tag_mem_pkt_v_i(mhu_tag_mem_pkt_v_lo)
,.mhu_tag_mem_pkt_i(mhu_tag_mem_pkt_lo)
,.mhu_idle_i(mhu_idle)
,.recover_i(mhu_recover)
,.curr_dma_way_id_i(curr_dma_way_id)
,.curr_dma_index_i(curr_dma_index)
,.curr_dma_v_i(curr_dma_v)
,.curr_mhu_way_id_i(curr_mhu_way_id)
,.curr_mhu_index_i(curr_mhu_index)
,.curr_mhu_v_i(curr_mhu_v)
);
// miss FIFO
//
bsg_cache_non_blocking_miss_fifo_entry_s miss_fifo_data_li;
logic miss_fifo_v_li;
logic miss_fifo_ready_lo;
bsg_cache_non_blocking_miss_fifo_entry_s miss_fifo_data_lo;
logic miss_fifo_v_lo;
logic miss_fifo_yumi_li;
logic miss_fifo_scan_not_dq_li;
bsg_cache_non_blocking_miss_fifo_op_e miss_fifo_yumi_op_li;
logic miss_fifo_rollback_li;
logic miss_fifo_empty_lo;
bsg_cache_non_blocking_miss_fifo #(
.width_p($bits(bsg_cache_non_blocking_miss_fifo_entry_s))
,.els_p(miss_fifo_els_p)
) miss_fifo0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(miss_fifo_v_li)
,.data_i(miss_fifo_data_li)
,.ready_o(miss_fifo_ready_lo)
,.v_o(miss_fifo_v_lo)
,.data_o(miss_fifo_data_lo)
,.yumi_i(miss_fifo_yumi_li)
,.yumi_op_i(miss_fifo_yumi_op_li)
,.scan_not_dq_i(miss_fifo_scan_not_dq_li)
,.rollback_i(miss_fifo_rollback_li)
,.empty_o(miss_fifo_empty_lo)
);
assign miss_fifo_v_li = tl_miss_fifo_v_lo;
assign miss_fifo_data_li = tl_miss_fifo_entry_lo;
assign tl_miss_fifo_ready_li = miss_fifo_ready_lo;
// data_mem
//
bsg_cache_non_blocking_data_mem_pkt_s data_mem_pkt_li;
logic data_mem_v_li;
logic [data_width_p-1:0] data_mem_data_lo;
bsg_cache_non_blocking_data_mem #(
.data_width_p(data_width_p)
,.ways_p(ways_p)
,.sets_p(sets_p)
,.block_size_in_words_p(block_size_in_words_p)
) data_mem0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(data_mem_v_li)
,.data_mem_pkt_i(data_mem_pkt_li)
,.data_o(data_mem_data_lo)
);
// DMA read data buffer
// When the DMA engine reads the data_mem for eviction, the output
// is buffered here, in case dma_data_o is stalled.
logic dma_read_en;
logic dma_read_en_r;
logic [data_width_p-1:0] dma_read_data_r;
bsg_dff_reset #(
.width_p(1)
) dma_read_en_dff (
.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(dma_read_en)
,.data_o(dma_read_en_r)
);
bsg_dff_en_bypass #(
.width_p(data_width_p)
) dma_read_buffer (
.clk_i(clk_i)
,.en_i(dma_read_en_r)
,.data_i(data_mem_data_lo)
,.data_o(dma_read_data_r)
);
// Load data buffer
// When the TL stage or MHU does load, the output is buffered here.
logic load_read_en;
logic load_read_en_r;
logic [data_width_p-1:0] load_read_data_r;
bsg_dff_reset #(
.width_p(1)
) load_read_en_eff (
.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(load_read_en)
,.data_o(load_read_en_r)
);
bsg_dff_en_bypass #(
.width_p(data_width_p)
) load_read_buffer (
.clk_i(clk_i)
,.en_i(load_read_en_r)
,.data_i(data_mem_data_lo)
,.data_o(load_read_data_r)
);
// stat_mem
//
bsg_cache_non_blocking_stat_mem_pkt_s stat_mem_pkt_li;
logic stat_mem_v_li;
logic [ways_p-1:0] dirty_lo;
logic [ways_p-2:0] lru_bits_lo;
bsg_cache_non_blocking_stat_mem #(
.ways_p(ways_p)
,.sets_p(sets_p)
) stat_mem0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(stat_mem_v_li)
,.stat_mem_pkt_i(stat_mem_pkt_li)
,.dirty_o(dirty_lo)
,.lru_bits_o(lru_bits_lo)
);
// MHU
//
bsg_cache_non_blocking_data_mem_pkt_s mhu_data_mem_pkt_lo;
logic [id_width_p-1:0] mhu_data_mem_pkt_id_lo;
logic mhu_data_mem_pkt_v_lo;
logic mhu_data_mem_pkt_yumi_li;
bsg_cache_non_blocking_stat_mem_pkt_s mhu_stat_mem_pkt_lo;
logic mhu_stat_mem_pkt_v_lo;
bsg_cache_non_blocking_dma_cmd_s dma_cmd_lo;
logic dma_cmd_v_lo;
bsg_cache_non_blocking_dma_cmd_s dma_cmd_return_li;
logic dma_done_li;
logic dma_pending_li;
logic dma_ack_lo;
logic mgmt_data_v_lo;
logic [data_width_p-1:0] mgmt_data_lo;
logic [id_width_p-1:0] mgmt_id_lo;
logic mgmt_data_yumi_li;
bsg_cache_non_blocking_mhu #(
.id_width_p(id_width_p)
,.addr_width_p(addr_width_p)
,.data_width_p(data_width_p)
,.ways_p(ways_p)
,.sets_p(sets_p)
,.block_size_in_words_p(block_size_in_words_p)
) mhu0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.mgmt_v_i(mgmt_v_lo)
,.mgmt_yumi_o(mgmt_yumi_li)
,.mgmt_data_v_o(mgmt_data_v_lo)
,.mgmt_data_o(mgmt_data_lo)
,.mgmt_id_o(mgmt_id_lo)
,.mgmt_data_yumi_i(mgmt_data_yumi_li)
,.decode_tl_i(decode_tl_lo)
,.addr_tl_i(addr_tl_lo)
,.id_tl_i(id_tl_lo)
,.idle_o(mhu_idle)
,.recover_o(mhu_recover)
,.tl_block_loading_i(tl_block_loading)
,.data_mem_pkt_v_o(mhu_data_mem_pkt_v_lo)
,.data_mem_pkt_o(mhu_data_mem_pkt_lo)
,.data_mem_pkt_yumi_i(mhu_data_mem_pkt_yumi_li)
,.data_mem_pkt_id_o(mhu_data_mem_pkt_id_lo)
,.stat_mem_pkt_v_o(mhu_stat_mem_pkt_v_lo)
,.stat_mem_pkt_o(mhu_stat_mem_pkt_lo)
,.dirty_i(dirty_lo)
,.lru_bits_i(lru_bits_lo)
,.tag_mem_pkt_v_o(mhu_tag_mem_pkt_v_lo)
,.tag_mem_pkt_o(mhu_tag_mem_pkt_lo)
,.valid_tl_i(valid_tl_lo)
,.lock_tl_i(lock_tl_lo)
,.tag_tl_i(tag_tl_lo)
,.tag_hit_way_i(tag_hit_way_lo)
,.tag_hit_found_i(tag_hit_found_lo)
,.curr_mhu_way_id_o(curr_mhu_way_id)
,.curr_mhu_index_o(curr_mhu_index)
,.curr_mhu_v_o(curr_mhu_v)
,.miss_fifo_v_i(miss_fifo_v_lo)
,.miss_fifo_entry_i(miss_fifo_data_lo)
,.miss_fifo_yumi_o(miss_fifo_yumi_li)
,.miss_fifo_yumi_op_o(miss_fifo_yumi_op_li)
,.miss_fifo_scan_not_dq_o(miss_fifo_scan_not_dq_li)
,.miss_fifo_rollback_o(miss_fifo_rollback_li)
,.miss_fifo_empty_i(miss_fifo_empty_lo)
,.dma_cmd_o(dma_cmd_lo)
,.dma_cmd_v_o(dma_cmd_v_lo)
,.dma_cmd_return_i(dma_cmd_return_li)
,.dma_done_i(dma_done_li)
,.dma_pending_i(dma_pending_li)
,.dma_ack_o(dma_ack_lo)
);
// DMA engine
//
logic dma_data_mem_pkt_v_lo;
bsg_cache_non_blocking_data_mem_pkt_s dma_data_mem_pkt_lo;
bsg_cache_non_blocking_dma #(
.addr_width_p(addr_width_p)
,.data_width_p(data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.sets_p(sets_p)
,.ways_p(ways_p)
) dma0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.dma_cmd_i(dma_cmd_lo)
,.dma_cmd_v_i(dma_cmd_v_lo)
,.dma_cmd_return_o(dma_cmd_return_li)
,.done_o(dma_done_li)
,.pending_o(dma_pending_li)
,.ack_i(dma_ack_lo)
,.curr_dma_way_id_o(curr_dma_way_id)
,.curr_dma_index_o(curr_dma_index)
,.curr_dma_v_o(curr_dma_v)
,.data_mem_pkt_v_o(dma_data_mem_pkt_v_lo)
,.data_mem_pkt_o(dma_data_mem_pkt_lo)
,.data_mem_data_i(dma_read_data_r)
,.dma_pkt_o(dma_pkt_o)
,.dma_pkt_v_o(dma_pkt_v_o)
,.dma_pkt_yumi_i(dma_pkt_yumi_i)
,.dma_data_i(dma_data_i)
,.dma_data_v_i(dma_data_v_i)
,.dma_data_ready_o(dma_data_ready_o)
,.dma_data_o(dma_data_o)
,.dma_data_v_o(dma_data_v_o)
,.dma_data_yumi_i(dma_data_yumi_i)
);
/// ///
/// CTRL LOGIC ///
/// ///
// data_mem ctrl logic
//
// Access priority in descending order.
// 1) DMA engine
// 2) MHU
// 3) TL stage (hit). When neither DMA nor MHU is accessing the data_mem,
// ready signal to TL stage goes high.
always_comb begin
data_mem_v_li = 1'b0;
data_mem_pkt_li = dma_data_mem_pkt_lo;
mhu_data_mem_pkt_yumi_li = 1'b0;
tl_data_mem_pkt_ready_li = 1'b0;
dma_read_en = 1'b0;
load_read_en = 1'b0;
if (dma_data_mem_pkt_v_lo) begin
data_mem_pkt_li = dma_data_mem_pkt_lo;
data_mem_v_li = 1'b1;
dma_read_en = ~dma_data_mem_pkt_lo.write_not_read;
end
else if (mhu_data_mem_pkt_v_lo) begin
data_mem_pkt_li = mhu_data_mem_pkt_lo;
data_mem_v_li = ~stall;
mhu_data_mem_pkt_yumi_li = ~stall;
load_read_en = ~mhu_data_mem_pkt_lo.write_not_read & ~stall;
end
else begin
data_mem_pkt_li = tl_data_mem_pkt_lo;
data_mem_v_li = tl_data_mem_pkt_v_lo & ~stall;
tl_data_mem_pkt_ready_li = ~stall;
load_read_en = ~tl_data_mem_pkt_lo.write_not_read & tl_data_mem_pkt_v_lo & ~stall;
end
end
// stat_mem ctrl logic
//
// MHU has higher priority over TL stage.
// MHU accesses tag_mem and stat_mem together.
always_comb begin
stat_mem_v_li = 1'b0;
stat_mem_pkt_li = mhu_stat_mem_pkt_lo;
tl_stat_mem_pkt_ready_li = 1'b0;
if (mhu_stat_mem_pkt_v_lo) begin
stat_mem_v_li = 1'b1;
stat_mem_pkt_li = mhu_stat_mem_pkt_lo;
end
else begin
tl_stat_mem_pkt_ready_li = ~stall;
stat_mem_pkt_li = tl_stat_mem_pkt_lo;
stat_mem_v_li = tl_stat_mem_pkt_v_lo & ~stall;
end
end
// Output Logic
//
// Output valid signal lasts for only one cycle. The consumer needs to be
// ready to accept the data whenever it becomes ready.
// When the pipeline is stalled, these register values stay the same.
// But the pipeline can only stall, when the output is valid.
logic [data_width_p-1:0] mgmt_data_r, mgmt_data_n;
logic [id_width_p-1:0] out_id_r, out_id_n;
logic mgmt_data_v_r, mgmt_data_v_n;
logic store_v_r, store_v_n;
logic load_v_r, load_v_n;
always_comb begin
if (stall) begin
out_id_n = out_id_r;
mgmt_data_n = mgmt_data_r;
store_v_n = store_v_r;
load_v_n = load_v_r;
mgmt_data_v_n = mgmt_data_v_r;
mgmt_data_yumi_li = 1'b0;
end
else begin
out_id_n = out_id_r;
mgmt_data_n = mgmt_data_r;
store_v_n = 1'b0;
load_v_n = 1'b0;
mgmt_data_v_n = 1'b0;
mgmt_data_yumi_li = 1'b0;
if (mgmt_data_v_lo) begin
mgmt_data_n = mgmt_data_lo;
out_id_n = mgmt_id_lo;
mgmt_data_v_n = mgmt_data_v_lo;
mgmt_data_yumi_li = mgmt_data_v_lo;
end
else if (mhu_data_mem_pkt_yumi_li) begin
out_id_n = mhu_data_mem_pkt_id_lo;
store_v_n = mhu_data_mem_pkt_lo.write_not_read;
load_v_n = ~mhu_data_mem_pkt_lo.write_not_read;
end
else if (tl_data_mem_pkt_ready_li & tl_data_mem_pkt_v_lo) begin
out_id_n = id_tl_lo;
store_v_n = tl_data_mem_pkt_lo.write_not_read;
load_v_n = ~tl_data_mem_pkt_lo.write_not_read;
end
end
if (mgmt_data_v_r)
data_o = mgmt_data_r;
else if (load_v_r)
data_o = load_read_data_r;
else
data_o = '0;
id_o = out_id_r;
v_o = mgmt_data_v_r | store_v_r | load_v_r;
end
// synopsys sync_set_reset "reset_i"
always_ff @ (posedge clk_i) begin
if (reset_i) begin
mgmt_data_r <= '0;
out_id_r <= '0;
mgmt_data_v_r <= 1'b0;
store_v_r <= 1'b0;
load_v_r <= 1'b0;
end
else begin
mgmt_data_r <= mgmt_data_n;
out_id_r <= out_id_n;
mgmt_data_v_r <= mgmt_data_v_n;
store_v_r <= store_v_n;
load_v_r <= load_v_n;
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache_non_blocking)
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