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//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level bank machine block. A structural block instantiating the configured
// individual bank machines, and a common block that computes various items shared
// by all bank machines.
`timescale 1ps/1ps
module mig_7series_v2_3_bank_mach #
(
parameter TCQ = 100,
parameter EVEN_CWL_2T_MODE = "OFF",
parameter ADDR_CMD_MODE = "1T",
parameter BANK_WIDTH = 3,
parameter BM_CNT_WIDTH = 2,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CS_WIDTH = 4,
parameter CL = 5,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter LOW_IDLE_CNT = 1,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nCS_PER_RANK = 1,
parameter nOP_WAIT = 0,
parameter nRAS = 20,
parameter nRCD = 5,
parameter nRFC = 44,
parameter nRTP = 4,
parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal
parameter nRP = 10,
parameter nSLOTS = 2,
parameter nWR = 6,
parameter nXSDLL = 512,
parameter ORDERING = "NORM",
parameter RANK_BM_BV_WIDTH = 16,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter ROW_WIDTH = 16,
parameter RTT_NOM = "40",
parameter RTT_WR = "120",
parameter STARVE_LIMIT = 2,
parameter SLOT_0_CONFIG = 8'b0000_0101,
parameter SLOT_1_CONFIG = 8'b0000_1010,
parameter tZQCS = 64
)
(/*AUTOARG*/
// Outputs
output accept, // From bank_common0 of bank_common.v
output accept_ns, // From bank_common0 of bank_common.v
output [BM_CNT_WIDTH-1:0] bank_mach_next, // From bank_common0 of bank_common.v
output [ROW_WIDTH-1:0] col_a, // From arb_mux0 of arb_mux.v
output [BANK_WIDTH-1:0] col_ba, // From arb_mux0 of arb_mux.v
output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_mux0 of arb_mux.v
output col_periodic_rd, // From arb_mux0 of arb_mux.v
output [RANK_WIDTH-1:0] col_ra, // From arb_mux0 of arb_mux.v
output col_rmw, // From arb_mux0 of arb_mux.v
output col_rd_wr,
output [ROW_WIDTH-1:0] col_row, // From arb_mux0 of arb_mux.v
output col_size, // From arb_mux0 of arb_mux.v
output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_mux0 of arb_mux.v
output wire [nCK_PER_CLK-1:0] mc_ras_n,
output wire [nCK_PER_CLK-1:0] mc_cas_n,
output wire [nCK_PER_CLK-1:0] mc_we_n,
output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
output wire [1:0] mc_odt,
output wire [nCK_PER_CLK-1:0] mc_cke,
output wire [3:0] mc_aux_out0,
output wire [3:0] mc_aux_out1,
output [2:0] mc_cmd,
output [5:0] mc_data_offset,
output [5:0] mc_data_offset_1,
output [5:0] mc_data_offset_2,
output [1:0] mc_cas_slot,
output insert_maint_r1, // From arb_mux0 of arb_mux.v
output maint_wip_r, // From bank_common0 of bank_common.v
output wire [nBANK_MACHS-1:0] sending_row,
output wire [nBANK_MACHS-1:0] sending_col,
output wire sent_col,
output wire sent_col_r,
output periodic_rd_ack_r,
output wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r,
output wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r,
output wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r,
output wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r,
output idle,
// Inputs
input [BANK_WIDTH-1:0] bank, // To bank0 of bank_cntrl.v
input [6*RANKS-1:0] calib_rddata_offset,
input [6*RANKS-1:0] calib_rddata_offset_1,
input [6*RANKS-1:0] calib_rddata_offset_2,
input clk, // To bank0 of bank_cntrl.v, ...
input [2:0] cmd, // To bank0 of bank_cntrl.v, ...
input [COL_WIDTH-1:0] col, // To bank0 of bank_cntrl.v
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr,// To bank0 of bank_cntrl.v
input init_calib_complete, // To bank_common0 of bank_common.v
input phy_rddata_valid, // To bank0 of bank_cntrl.v
input dq_busy_data, // To bank0 of bank_cntrl.v
input hi_priority, // To bank0 of bank_cntrl.v, ...
input [RANKS-1:0] inhbt_act_faw_r, // To bank0 of bank_cntrl.v
input [RANKS-1:0] inhbt_rd, // To bank0 of bank_cntrl.v
input [RANKS-1:0] inhbt_wr, // To bank0 of bank_cntrl.v
input [RANK_WIDTH-1:0] maint_rank_r, // To bank0 of bank_cntrl.v, ...
input maint_req_r, // To bank0 of bank_cntrl.v, ...
input maint_zq_r, // To bank0 of bank_cntrl.v, ...
input maint_sre_r, // To bank0 of bank_cntrl.v, ...
input maint_srx_r, // To bank0 of bank_cntrl.v, ...
input periodic_rd_r, // To bank_common0 of bank_common.v
input [RANK_WIDTH-1:0] periodic_rd_rank_r, // To bank0 of bank_cntrl.v
input phy_mc_ctl_full,
input phy_mc_cmd_full,
input phy_mc_data_full,
input [RANK_WIDTH-1:0] rank, // To bank0 of bank_cntrl.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr, // To bank0 of bank_cntrl.v
input rd_rmw, // To bank0 of bank_cntrl.v
input [ROW_WIDTH-1:0] row, // To bank0 of bank_cntrl.v
input rst, // To bank0 of bank_cntrl.v, ...
input size, // To bank0 of bank_cntrl.v
input [7:0] slot_0_present, // To bank_common0 of bank_common.v, ...
input [7:0] slot_1_present, // To bank_common0 of bank_common.v, ...
input use_addr
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam RANK_VECT_INDX = (nBANK_MACHS *RANK_WIDTH) - 1;
localparam BANK_VECT_INDX = (nBANK_MACHS * BANK_WIDTH) - 1;
localparam ROW_VECT_INDX = (nBANK_MACHS * ROW_WIDTH) - 1;
localparam DATA_BUF_ADDR_VECT_INDX = (nBANK_MACHS * DATA_BUF_ADDR_WIDTH) - 1;
localparam nRAS_CLKS = (nCK_PER_CLK == 1) ? nRAS : (nCK_PER_CLK == 2) ? ((nRAS/2) + (nRAS % 2)) : ((nRAS/4) + ((nRAS%4) ? 1 : 0));
localparam nWTP = CWL + ((BURST_MODE == "4") ? 2 : 4) + nWR;
// Unless 2T mode, add one to nWTP_CLKS for 2:1 mode. This accounts for loss of
// one DRAM CK due to column command to row command fixed offset. In 2T mode,
// Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T
// mode, in which case we add 1 if the remainder exceeds the fixed offset.
localparam nWTP_CLKS = (nCK_PER_CLK == 1)
? nWTP :
(nCK_PER_CLK == 2)
? (nWTP/2) + ((ADDR_CMD_MODE == "2T") ? nWTP%2 : 1) :
(nWTP/4) + ((ADDR_CMD_MODE == "2T") ? (nWTP%4 > 2 ? 2 : 1) : 2);
localparam RAS_TIMER_WIDTH = clogb2(((nRAS_CLKS > nWTP_CLKS)
? nRAS_CLKS
: nWTP_CLKS) - 1);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire accept_internal_r; // From bank_common0 of bank_common.v
wire accept_req; // From bank_common0 of bank_common.v
wire adv_order_q; // From bank_common0 of bank_common.v
wire [BM_CNT_WIDTH-1:0] idle_cnt; // From bank_common0 of bank_common.v
wire insert_maint_r; // From bank_common0 of bank_common.v
wire low_idle_cnt_r; // From bank_common0 of bank_common.v
wire maint_idle; // From bank_common0 of bank_common.v
wire [BM_CNT_WIDTH-1:0] order_cnt; // From bank_common0 of bank_common.v
wire periodic_rd_insert; // From bank_common0 of bank_common.v
wire [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // From bank_common0 of bank_common.v
wire sent_row; // From arb_mux0 of arb_mux.v
wire was_priority; // From bank_common0 of bank_common.v
wire was_wr; // From bank_common0 of bank_common.v
// End of automatics
wire [RANK_WIDTH-1:0] rnk_config;
wire rnk_config_strobe;
wire rnk_config_kill_rts_col;
wire rnk_config_valid_r;
wire [nBANK_MACHS-1:0] rts_row;
wire [nBANK_MACHS-1:0] rts_col;
wire [nBANK_MACHS-1:0] rts_pre;
wire [nBANK_MACHS-1:0] col_rdy_wr;
wire [nBANK_MACHS-1:0] rtc;
wire [nBANK_MACHS-1:0] sending_pre;
wire [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r;
wire [nBANK_MACHS-1:0] req_size_r;
wire [RANK_VECT_INDX:0] req_rank_r;
wire [BANK_VECT_INDX:0] req_bank_r;
wire [ROW_VECT_INDX:0] req_row_r;
wire [ROW_VECT_INDX:0] col_addr;
wire [nBANK_MACHS-1:0] req_periodic_rd_r;
wire [nBANK_MACHS-1:0] req_wr_r;
wire [nBANK_MACHS-1:0] rd_wr_r;
wire [nBANK_MACHS-1:0] req_ras;
wire [nBANK_MACHS-1:0] req_cas;
wire [ROW_VECT_INDX:0] row_addr;
wire [nBANK_MACHS-1:0] row_cmd_wr;
wire [nBANK_MACHS-1:0] demand_priority;
wire [nBANK_MACHS-1:0] demand_act_priority;
wire [nBANK_MACHS-1:0] idle_ns;
wire [nBANK_MACHS-1:0] rb_hit_busy_r;
wire [nBANK_MACHS-1:0] bm_end;
wire [nBANK_MACHS-1:0] passing_open_bank;
wire [nBANK_MACHS-1:0] ordered_r;
wire [nBANK_MACHS-1:0] ordered_issued;
wire [nBANK_MACHS-1:0] rb_hit_busy_ns;
wire [nBANK_MACHS-1:0] maint_hit;
wire [nBANK_MACHS-1:0] idle_r;
wire [nBANK_MACHS-1:0] head_r;
wire [nBANK_MACHS-1:0] start_rcd;
wire [nBANK_MACHS-1:0] end_rtp;
wire [nBANK_MACHS-1:0] op_exit_req;
wire [nBANK_MACHS-1:0] op_exit_grant;
wire [nBANK_MACHS-1:0] start_pre_wait;
wire [(RAS_TIMER_WIDTH*nBANK_MACHS)-1:0] ras_timer_ns;
genvar ID;
generate for (ID=0; ID<nBANK_MACHS; ID=ID+1) begin:bank_cntrl
mig_7series_v2_3_bank_cntrl #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.ECC (ECC),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nOP_WAIT (nOP_WAIT),
.nRAS_CLKS (nRAS_CLKS),
.nRCD (nRCD),
.nRTP (nRTP),
.nRP (nRP),
.nWTP_CLKS (nWTP_CLKS),
.ORDERING (ORDERING),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.RAS_TIMER_WIDTH (RAS_TIMER_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.STARVE_LIMIT (STARVE_LIMIT))
bank0
(.demand_priority (demand_priority[ID]),
.demand_priority_in ({2{demand_priority}}),
.demand_act_priority (demand_act_priority[ID]),
.demand_act_priority_in ({2{demand_act_priority}}),
.rts_row (rts_row[ID]),
.rts_col (rts_col[ID]),
.rts_pre (rts_pre[ID]),
.col_rdy_wr (col_rdy_wr[ID]),
.rtc (rtc[ID]),
.sending_row (sending_row[ID]),
.sending_pre (sending_pre[ID]),
.sending_col (sending_col[ID]),
.req_data_buf_addr_r (req_data_buf_addr_r[(ID*DATA_BUF_ADDR_WIDTH)+:DATA_BUF_ADDR_WIDTH]),
.req_size_r (req_size_r[ID]),
.req_rank_r (req_rank_r[(ID*RANK_WIDTH)+:RANK_WIDTH]),
.req_bank_r (req_bank_r[(ID*BANK_WIDTH)+:BANK_WIDTH]),
.req_row_r (req_row_r[(ID*ROW_WIDTH)+:ROW_WIDTH]),
.col_addr (col_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]),
.req_wr_r (req_wr_r[ID]),
.rd_wr_r (rd_wr_r[ID]),
.req_periodic_rd_r (req_periodic_rd_r[ID]),
.req_ras (req_ras[ID]),
.req_cas (req_cas[ID]),
.row_addr (row_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]),
.row_cmd_wr (row_cmd_wr[ID]),
.act_this_rank_r (act_this_rank_r[(ID*RANKS)+:RANKS]),
.wr_this_rank_r (wr_this_rank_r[(ID*RANKS)+:RANKS]),
.rd_this_rank_r (rd_this_rank_r[(ID*RANKS)+:RANKS]),
.idle_ns (idle_ns[ID]),
.rb_hit_busy_r (rb_hit_busy_r[ID]),
.bm_end (bm_end[ID]),
.bm_end_in ({2{bm_end}}),
.passing_open_bank (passing_open_bank[ID]),
.passing_open_bank_in ({2{passing_open_bank}}),
.ordered_r (ordered_r[ID]),
.ordered_issued (ordered_issued[ID]),
.rb_hit_busy_ns (rb_hit_busy_ns[ID]),
.rb_hit_busy_ns_in ({2{rb_hit_busy_ns}}),
.maint_hit (maint_hit[ID]),
.req_rank_r_in ({2{req_rank_r}}),
.idle_r (idle_r[ID]),
.head_r (head_r[ID]),
.start_rcd (start_rcd[ID]),
.start_rcd_in ({2{start_rcd}}),
.end_rtp (end_rtp[ID]),
.op_exit_req (op_exit_req[ID]),
.op_exit_grant (op_exit_grant[ID]),
.start_pre_wait (start_pre_wait[ID]),
.ras_timer_ns (ras_timer_ns[(ID*RAS_TIMER_WIDTH)+:RAS_TIMER_WIDTH]),
.ras_timer_ns_in ({2{ras_timer_ns}}),
.rank_busy_r (rank_busy_r[ID*RANKS+:RANKS]),
/*AUTOINST*/
// Inputs
.accept_internal_r (accept_internal_r),
.accept_req (accept_req),
.adv_order_q (adv_order_q),
.bank (bank[BANK_WIDTH-1:0]),
.clk (clk),
.cmd (cmd[2:0]),
.col (col[COL_WIDTH-1:0]),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.phy_rddata_valid (phy_rddata_valid),
.dq_busy_data (dq_busy_data),
.hi_priority (hi_priority),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.inhbt_rd (inhbt_rd[RANKS-1:0]),
.inhbt_wr (inhbt_wr[RANKS-1:0]),
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.rnk_config_valid_r (rnk_config_valid_r),
.low_idle_cnt_r (low_idle_cnt_r),
.maint_idle (maint_idle),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.periodic_rd_ack_r (periodic_rd_ack_r),
.periodic_rd_insert (periodic_rd_insert),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.phy_mc_cmd_full (phy_mc_cmd_full),
.phy_mc_ctl_full (phy_mc_ctl_full),
.phy_mc_data_full (phy_mc_data_full),
.rank (rank[RANK_WIDTH-1:0]),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.rd_rmw (rd_rmw),
.row (row[ROW_WIDTH-1:0]),
.rst (rst),
.sent_col (sent_col),
.sent_row (sent_row),
.size (size),
.use_addr (use_addr),
.was_priority (was_priority),
.was_wr (was_wr));
end
endgenerate
mig_7series_v2_3_bank_common #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.LOW_IDLE_CNT (LOW_IDLE_CNT),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nOP_WAIT (nOP_WAIT),
.nRFC (nRFC),
.nXSDLL (nXSDLL),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.CWL (CWL),
.tZQCS (tZQCS))
bank_common0
(.op_exit_grant (op_exit_grant[nBANK_MACHS-1:0]),
/*AUTOINST*/
// Outputs
.accept_internal_r (accept_internal_r),
.accept_ns (accept_ns),
.accept (accept),
.periodic_rd_insert (periodic_rd_insert),
.periodic_rd_ack_r (periodic_rd_ack_r),
.accept_req (accept_req),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.idle (idle),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.adv_order_q (adv_order_q),
.bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]),
.low_idle_cnt_r (low_idle_cnt_r),
.was_wr (was_wr),
.was_priority (was_priority),
.maint_wip_r (maint_wip_r),
.maint_idle (maint_idle),
.insert_maint_r (insert_maint_r),
// Inputs
.clk (clk),
.rst (rst),
.idle_ns (idle_ns[nBANK_MACHS-1:0]),
.init_calib_complete (init_calib_complete),
.periodic_rd_r (periodic_rd_r),
.use_addr (use_addr),
.rb_hit_busy_r (rb_hit_busy_r[nBANK_MACHS-1:0]),
.idle_r (idle_r[nBANK_MACHS-1:0]),
.ordered_r (ordered_r[nBANK_MACHS-1:0]),
.ordered_issued (ordered_issued[nBANK_MACHS-1:0]),
.head_r (head_r[nBANK_MACHS-1:0]),
.end_rtp (end_rtp[nBANK_MACHS-1:0]),
.passing_open_bank (passing_open_bank[nBANK_MACHS-1:0]),
.op_exit_req (op_exit_req[nBANK_MACHS-1:0]),
.start_pre_wait (start_pre_wait[nBANK_MACHS-1:0]),
.cmd (cmd[2:0]),
.hi_priority (hi_priority),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_hit (maint_hit[nBANK_MACHS-1:0]),
.bm_end (bm_end[nBANK_MACHS-1:0]),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]));
mig_7series_v2_3_arb_mux #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_VECT_INDX (BANK_VECT_INDX),
.BANK_WIDTH (BANK_WIDTH),
.BURST_MODE (BURST_MODE),
.CS_WIDTH (CS_WIDTH),
.CL (CL),
.CWL (CWL),
.DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.ECC (ECC),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCS_PER_RANK (nCS_PER_RANK),
.nRAS (nRAS),
.nRCD (nRCD),
.CKE_ODT_AUX (CKE_ODT_AUX),
.nSLOTS (nSLOTS),
.nWR (nWR),
.RANKS (RANKS),
.RANK_VECT_INDX (RANK_VECT_INDX),
.RANK_WIDTH (RANK_WIDTH),
.ROW_VECT_INDX (ROW_VECT_INDX),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG))
arb_mux0
(.rts_col (rts_col[nBANK_MACHS-1:0]), // AUTOs wants to make this an input.
/*AUTOINST*/
// Outputs
.col_a (col_a[ROW_WIDTH-1:0]),
.col_ba (col_ba[BANK_WIDTH-1:0]),
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.col_periodic_rd (col_periodic_rd),
.col_ra (col_ra[RANK_WIDTH-1:0]),
.col_rmw (col_rmw),
.col_rd_wr (col_rd_wr),
.col_row (col_row[ROW_WIDTH-1:0]),
.col_size (col_size),
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.mc_bank (mc_bank),
.mc_address (mc_address),
.mc_ras_n (mc_ras_n),
.mc_cas_n (mc_cas_n),
.mc_we_n (mc_we_n),
.mc_cs_n (mc_cs_n),
.mc_odt (mc_odt),
.mc_cke (mc_cke),
.mc_aux_out0 (mc_aux_out0),
.mc_aux_out1 (mc_aux_out1),
.mc_cmd (mc_cmd),
.mc_data_offset (mc_data_offset),
.mc_data_offset_1 (mc_data_offset_1),
.mc_data_offset_2 (mc_data_offset_2),
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
.rnk_config_valid_r (rnk_config_valid_r),
.mc_cas_slot (mc_cas_slot),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.sending_pre (sending_pre[nBANK_MACHS-1:0]),
.sent_col (sent_col),
.sent_col_r (sent_col_r),
.sent_row (sent_row),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.insert_maint_r1 (insert_maint_r1),
// Inputs
.init_calib_complete (init_calib_complete),
.calib_rddata_offset (calib_rddata_offset),
.calib_rddata_offset_1 (calib_rddata_offset_1),
.calib_rddata_offset_2 (calib_rddata_offset_2),
.col_addr (col_addr[ROW_VECT_INDX:0]),
.col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0]),
.insert_maint_r (insert_maint_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]),
.req_bank_r (req_bank_r[BANK_VECT_INDX:0]),
.req_cas (req_cas[nBANK_MACHS-1:0]),
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]),
.req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]),
.req_rank_r (req_rank_r[RANK_VECT_INDX:0]),
.req_ras (req_ras[nBANK_MACHS-1:0]),
.req_row_r (req_row_r[ROW_VECT_INDX:0]),
.req_size_r (req_size_r[nBANK_MACHS-1:0]),
.req_wr_r (req_wr_r[nBANK_MACHS-1:0]),
.row_addr (row_addr[ROW_VECT_INDX:0]),
.row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]),
.rts_row (rts_row[nBANK_MACHS-1:0]),
.rtc (rtc[nBANK_MACHS-1:0]),
.rts_pre (rts_pre[nBANK_MACHS-1:0]),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.clk (clk),
.rst (rst));
endmodule // bank_mach
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Down-Sizer
// Down-Sizer for generic SI- and MI-side data widths. This module instantiates
// Address, Write Data, Write Response and Read Data Down-Sizer modules, each one taking care
// of the channel specific tasks.
// The Address Down-Sizer can handle both AR and AW channels.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// downsizer
// a_downsizer
// axic_fifo
// fifo_gen
// fifo_coregen
// w_downsizer
// b_downsizer
// r_downsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_8_axi_downsizer #
(
parameter C_FAMILY = "none",
// FPGA Family.
parameter integer C_AXI_PROTOCOL = 0,
// Protocol of SI and MI (0=AXI4, 1=AXI3).
parameter integer C_S_AXI_ID_WIDTH = 1,
// Width of all ID signals on SI side of converter.
// Range: 1 - 32.
parameter integer C_SUPPORTS_ID = 0,
// Indicates whether SI-side ID needs to be stored and compared.
// 0 = No, SI is single-threaded, propagate all transactions.
// 1 = Yes, stall any transaction with ID different than outstanding transactions.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI.
// Range (AXI4, AXI3): 12 - 64.
parameter integer C_S_AXI_DATA_WIDTH = 64,
// Width of s_axi_wdata and s_axi_rdata.
// Range: 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_DATA_WIDTH = 32,
// Width of m_axi_wdata and m_axi_rdata.
// Assume always smaller than C_S_AXI_DATA_WIDTH.
// Range: 32, 64, 128, 256, 512.
// S_DATA_WIDTH = M_DATA_WIDTH not allowed.
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
parameter integer C_MAX_SPLIT_BEATS = 256
// Max burst length after transaction splitting.
// Range: 0 (no splitting), 1 (convert to singles), 16, 256.
)
(
// Global Signals
input wire aresetn,
input wire aclk,
// Slave Interface Write Address Ports
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [8-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [2-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [8-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [2-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [8-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [2-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_M_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_M_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [2-1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [8-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [2-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_M_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire m_axi_rvalid,
output wire m_axi_rready
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
// Log2.
function integer log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
log2 = acc;
end
endfunction
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Log2 of number of 32bit word on SI-side.
localparam integer C_S_AXI_BYTES_LOG = log2(C_S_AXI_DATA_WIDTH/8);
// Log2 of number of 32bit word on MI-side.
localparam integer C_M_AXI_BYTES_LOG = log2(C_M_AXI_DATA_WIDTH/8);
// Log2 of Up-Sizing ratio for data.
localparam integer C_RATIO = C_S_AXI_DATA_WIDTH / C_M_AXI_DATA_WIDTH;
localparam integer C_RATIO_LOG = log2(C_RATIO);
localparam integer P_AXI_ADDR_WIDTH = (C_AXI_ADDR_WIDTH < 13) ? 13 : C_AXI_ADDR_WIDTH;
wire [P_AXI_ADDR_WIDTH-1:0] s_axi_awaddr_i;
wire [P_AXI_ADDR_WIDTH-1:0] s_axi_araddr_i;
wire [P_AXI_ADDR_WIDTH-1:0] m_axi_awaddr_i;
wire [P_AXI_ADDR_WIDTH-1:0] m_axi_araddr_i;
assign s_axi_awaddr_i = s_axi_awaddr;
assign s_axi_araddr_i = s_axi_araddr;
assign m_axi_awaddr = m_axi_awaddr_i[0 +: C_AXI_ADDR_WIDTH] ;
assign m_axi_araddr = m_axi_araddr_i[0 +: C_AXI_ADDR_WIDTH];
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
localparam integer P_MAX_SPLIT_BEATS = (C_MAX_SPLIT_BEATS >= 16) ? C_MAX_SPLIT_BEATS :
(C_AXI_PROTOCOL == P_AXI4) ? 256 : 16;
localparam integer P_MAX_SPLIT_BEATS_LOG = log2(P_MAX_SPLIT_BEATS);
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
generate
if (C_AXI_SUPPORTS_WRITE == 1) begin : USE_WRITE
// Write Channel Signals for Commands Queue Interface.
wire wr_cmd_valid;
wire wr_cmd_split;
wire wr_cmd_mirror;
wire wr_cmd_fix;
wire [C_S_AXI_BYTES_LOG-1:0] wr_cmd_first_word;
wire [C_S_AXI_BYTES_LOG-1:0] wr_cmd_offset;
wire [C_S_AXI_BYTES_LOG-1:0] wr_cmd_mask;
wire [C_M_AXI_BYTES_LOG:0] wr_cmd_step;
wire [3-1:0] wr_cmd_size;
wire [8-1:0] wr_cmd_length;
wire wr_cmd_ready;
wire wr_cmd_b_valid;
wire wr_cmd_b_split;
wire [8-1:0] wr_cmd_b_repeat ;
wire wr_cmd_b_ready;
wire [C_S_AXI_ID_WIDTH-1:0] wr_cmd_b_id;
wire [8-1:0] s_axi_awlen_i;
wire [2-1:0] s_axi_awlock_i;
assign s_axi_awlen_i = (C_AXI_PROTOCOL == P_AXI3) ? {4'b0000, s_axi_awlen[3:0]}: s_axi_awlen;
assign s_axi_awlock_i = (C_AXI_PROTOCOL == P_AXI3) ? s_axi_awlock : {1'b0, s_axi_awlock[0]};
// Write Address Channel.
axi_dwidth_converter_v2_1_8_a_downsizer #
(
.C_FAMILY (C_FAMILY),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_SUPPORTS_ID (C_SUPPORTS_ID),
.C_AXI_ADDR_WIDTH (P_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_AXI_CHANNEL (0),
.C_MAX_SPLIT_BEATS (P_MAX_SPLIT_BEATS),
.C_MAX_SPLIT_BEATS_LOG (P_MAX_SPLIT_BEATS_LOG),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO_LOG (C_RATIO_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (!aresetn),
.ACLK (aclk),
// Command Interface (W)
.cmd_valid (wr_cmd_valid),
.cmd_split (wr_cmd_split),
.cmd_mirror (wr_cmd_mirror),
.cmd_fix (wr_cmd_fix),
.cmd_first_word (wr_cmd_first_word),
.cmd_offset (wr_cmd_offset),
.cmd_mask (wr_cmd_mask),
.cmd_step (wr_cmd_step),
.cmd_size (wr_cmd_size),
.cmd_length (wr_cmd_length),
.cmd_ready (wr_cmd_ready),
// Command Interface (B)
.cmd_b_valid (wr_cmd_b_valid),
.cmd_b_split (wr_cmd_b_split),
.cmd_b_repeat (wr_cmd_b_repeat),
.cmd_b_ready (wr_cmd_b_ready),
.cmd_id (wr_cmd_b_id),
// Slave Interface Write Address Ports
.S_AXI_AID (s_axi_awid),
.S_AXI_AADDR (s_axi_awaddr_i),
.S_AXI_ALEN (s_axi_awlen_i),
.S_AXI_ASIZE (s_axi_awsize),
.S_AXI_ABURST (s_axi_awburst),
.S_AXI_ALOCK (s_axi_awlock_i),
.S_AXI_ACACHE (s_axi_awcache),
.S_AXI_APROT (s_axi_awprot),
.S_AXI_AREGION (s_axi_awregion),
.S_AXI_AQOS (s_axi_awqos),
.S_AXI_AVALID (s_axi_awvalid),
.S_AXI_AREADY (s_axi_awready),
// Master Interface Write Address Port
.M_AXI_AADDR (m_axi_awaddr_i),
.M_AXI_ALEN (m_axi_awlen),
.M_AXI_ASIZE (m_axi_awsize),
.M_AXI_ABURST (m_axi_awburst),
.M_AXI_ALOCK (m_axi_awlock),
.M_AXI_ACACHE (m_axi_awcache),
.M_AXI_APROT (m_axi_awprot),
.M_AXI_AREGION (m_axi_awregion),
.M_AXI_AQOS (m_axi_awqos),
.M_AXI_AVALID (m_axi_awvalid),
.M_AXI_AREADY (m_axi_awready)
);
// Write Data channel.
axi_dwidth_converter_v2_1_8_w_downsizer #
(
.C_FAMILY (C_FAMILY),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO_LOG (C_RATIO_LOG)
) write_data_inst
(
// Global Signals
.ARESET (!aresetn),
.ACLK (aclk),
// Command Interface
.cmd_valid (wr_cmd_valid),
.cmd_mirror (wr_cmd_mirror),
.cmd_fix (wr_cmd_fix),
.cmd_first_word (wr_cmd_first_word),
.cmd_offset (wr_cmd_offset),
.cmd_mask (wr_cmd_mask),
.cmd_step (wr_cmd_step),
.cmd_size (wr_cmd_size),
.cmd_length (wr_cmd_length),
.cmd_ready (wr_cmd_ready),
// Slave Interface Write Data Ports
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WVALID (s_axi_wvalid),
.S_AXI_WREADY (s_axi_wready),
// Master Interface Write Data Ports
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WLAST (m_axi_wlast),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready)
);
// Write Response channel.
if ( P_MAX_SPLIT_BEATS > 0 ) begin : USE_SPLIT
axi_dwidth_converter_v2_1_8_b_downsizer #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH)
) write_resp_inst
(
// Global Signals
.ARESET (!aresetn),
.ACLK (aclk),
// Command Interface
.cmd_valid (wr_cmd_b_valid),
.cmd_split (wr_cmd_b_split),
.cmd_repeat (wr_cmd_b_repeat),
.cmd_ready (wr_cmd_b_ready),
.cmd_id (wr_cmd_b_id),
// Slave Interface Write Response Ports
.S_AXI_BID (s_axi_bid),
.S_AXI_BRESP (s_axi_bresp),
.S_AXI_BVALID (s_axi_bvalid),
.S_AXI_BREADY (s_axi_bready),
// Master Interface Write Response Ports
.M_AXI_BRESP (m_axi_bresp),
.M_AXI_BVALID (m_axi_bvalid),
.M_AXI_BREADY (m_axi_bready)
);
end else begin : NO_SPLIT
assign s_axi_bid = wr_cmd_b_id;
assign s_axi_bresp = m_axi_bresp;
assign s_axi_bvalid = m_axi_bvalid;
assign m_axi_bready = s_axi_bready;
end
end else begin : NO_WRITE
// Slave Interface Write Address Ports
assign s_axi_awready = 1'b0;
// Slave Interface Write Data Ports
assign s_axi_wready = 1'b0;
// Slave Interface Write Response Ports
assign s_axi_bid = {C_S_AXI_ID_WIDTH{1'b0}};
assign s_axi_bresp = 2'b0;
assign s_axi_bvalid = 1'b0;
// Master Interface Write Address Port
assign m_axi_awaddr_i = {P_AXI_ADDR_WIDTH{1'b0}};
assign m_axi_awlen = 8'b0;
assign m_axi_awsize = 3'b0;
assign m_axi_awburst = 2'b0;
assign m_axi_awlock = 2'b0;
assign m_axi_awcache = 4'b0;
assign m_axi_awprot = 3'b0;
assign m_axi_awregion = 4'b0;
assign m_axi_awqos = 4'b0;
assign m_axi_awvalid = 1'b0;
// Master Interface Write Data Ports
assign m_axi_wdata = {C_M_AXI_DATA_WIDTH{1'b0}};
assign m_axi_wstrb = {C_M_AXI_DATA_WIDTH/8{1'b0}};
assign m_axi_wlast = 1'b0;
// assign m_axi_wuser = {C_AXI_WUSER_WIDTH{1'b0}};
assign m_axi_wvalid = 1'b0;
// Master Interface Write Response Ports
assign m_axi_bready = 1'b0;
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
generate
if (C_AXI_SUPPORTS_READ == 1) begin : USE_READ
// Read Channel Signals for Commands Queue Interface.
wire rd_cmd_valid;
wire rd_cmd_split;
wire rd_cmd_mirror;
wire rd_cmd_fix;
wire [C_S_AXI_BYTES_LOG-1:0] rd_cmd_first_word;
wire [C_S_AXI_BYTES_LOG-1:0] rd_cmd_offset;
wire [C_S_AXI_BYTES_LOG-1:0] rd_cmd_mask;
wire [C_M_AXI_BYTES_LOG:0] rd_cmd_step;
wire [3-1:0] rd_cmd_size;
wire [8-1:0] rd_cmd_length;
wire rd_cmd_ready;
wire [C_S_AXI_ID_WIDTH-1:0] rd_cmd_id;
wire [8-1:0] s_axi_arlen_i;
wire [2-1:0] s_axi_arlock_i;
assign s_axi_arlen_i = (C_AXI_PROTOCOL == P_AXI3) ? {4'b0000, s_axi_arlen[3:0]}: s_axi_arlen;
assign s_axi_arlock_i = (C_AXI_PROTOCOL == P_AXI3) ? s_axi_arlock : {1'b0, s_axi_arlock[0]};
// Write Address Channel.
axi_dwidth_converter_v2_1_8_a_downsizer #
(
.C_FAMILY (C_FAMILY),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_SUPPORTS_ID (C_SUPPORTS_ID),
.C_AXI_ADDR_WIDTH (P_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_AXI_CHANNEL (1),
.C_MAX_SPLIT_BEATS (P_MAX_SPLIT_BEATS),
.C_MAX_SPLIT_BEATS_LOG (P_MAX_SPLIT_BEATS_LOG),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO_LOG (C_RATIO_LOG)
) read_addr_inst
(
// Global Signals
.ARESET (!aresetn),
.ACLK (aclk),
// Command Interface (R)
.cmd_valid (rd_cmd_valid),
.cmd_split (rd_cmd_split),
.cmd_mirror (rd_cmd_mirror),
.cmd_fix (rd_cmd_fix),
.cmd_first_word (rd_cmd_first_word),
.cmd_offset (rd_cmd_offset),
.cmd_mask (rd_cmd_mask),
.cmd_step (rd_cmd_step),
.cmd_size (rd_cmd_size),
.cmd_length (rd_cmd_length),
.cmd_ready (rd_cmd_ready),
.cmd_id (rd_cmd_id),
// Command Interface (B)
.cmd_b_valid (),
.cmd_b_split (),
.cmd_b_repeat (),
.cmd_b_ready (1'b0),
// Slave Interface Write Address Ports
.S_AXI_AID (s_axi_arid),
.S_AXI_AADDR (s_axi_araddr_i),
.S_AXI_ALEN (s_axi_arlen_i),
.S_AXI_ASIZE (s_axi_arsize),
.S_AXI_ABURST (s_axi_arburst),
.S_AXI_ALOCK (s_axi_arlock_i),
.S_AXI_ACACHE (s_axi_arcache),
.S_AXI_APROT (s_axi_arprot),
.S_AXI_AREGION (s_axi_arregion),
.S_AXI_AQOS (s_axi_arqos),
.S_AXI_AVALID (s_axi_arvalid),
.S_AXI_AREADY (s_axi_arready),
// Master Interface Write Address Port
.M_AXI_AADDR (m_axi_araddr_i),
.M_AXI_ALEN (m_axi_arlen),
.M_AXI_ASIZE (m_axi_arsize),
.M_AXI_ABURST (m_axi_arburst),
.M_AXI_ALOCK (m_axi_arlock),
.M_AXI_ACACHE (m_axi_arcache),
.M_AXI_APROT (m_axi_arprot),
.M_AXI_AREGION (m_axi_arregion),
.M_AXI_AQOS (m_axi_arqos),
.M_AXI_AVALID (m_axi_arvalid),
.M_AXI_AREADY (m_axi_arready)
);
// Read Data channel.
axi_dwidth_converter_v2_1_8_r_downsizer #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO_LOG (C_RATIO_LOG)
) read_data_inst
(
// Global Signals
.ARESET (!aresetn),
.ACLK (aclk),
// Command Interface
.cmd_valid (rd_cmd_valid),
.cmd_split (rd_cmd_split),
.cmd_mirror (rd_cmd_mirror),
.cmd_fix (rd_cmd_fix),
.cmd_first_word (rd_cmd_first_word),
.cmd_offset (rd_cmd_offset),
.cmd_mask (rd_cmd_mask),
.cmd_step (rd_cmd_step),
.cmd_size (rd_cmd_size),
.cmd_length (rd_cmd_length),
.cmd_ready (rd_cmd_ready),
.cmd_id (rd_cmd_id),
// Slave Interface Read Data Ports
.S_AXI_RID (s_axi_rid),
.S_AXI_RDATA (s_axi_rdata),
.S_AXI_RRESP (s_axi_rresp),
.S_AXI_RLAST (s_axi_rlast),
.S_AXI_RVALID (s_axi_rvalid),
.S_AXI_RREADY (s_axi_rready),
// Master Interface Read Data Ports
.M_AXI_RDATA (m_axi_rdata),
.M_AXI_RRESP (m_axi_rresp),
.M_AXI_RLAST (m_axi_rlast),
.M_AXI_RVALID (m_axi_rvalid),
.M_AXI_RREADY (m_axi_rready)
);
end else begin : NO_READ
// Slave Interface Read Address Ports
assign s_axi_arready = 1'b0;
// Slave Interface Read Data Ports
assign s_axi_rid = {C_S_AXI_ID_WIDTH{1'b0}};
assign s_axi_rdata = {C_S_AXI_DATA_WIDTH{1'b0}};
assign s_axi_rresp = 2'b0;
assign s_axi_rlast = 1'b0;
// assign s_axi_ruser = {C_AXI_RUSER_WIDTH{1'b0}};
assign s_axi_rvalid = 1'b0;
// Master Interface Read Address Port
assign m_axi_araddr_i = {P_AXI_ADDR_WIDTH{1'b0}};
assign m_axi_arlen = 8'b0;
assign m_axi_arsize = 3'b0;
assign m_axi_arburst = 2'b0;
assign m_axi_arlock = 2'b0;
assign m_axi_arcache = 4'b0;
assign m_axi_arprot = 3'b0;
assign m_axi_arregion = 4'b0;
assign m_axi_arqos = 4'b0;
assign m_axi_arvalid = 1'b0;
// Master Interface Read Data Ports
assign m_axi_rready = 1'b0;
end
endgenerate
endmodule
|
// MBT 7/24/2014
//
// This is a launch/synchronization complex.
// The launch flop prevents combinational glitching.
// The two sync flops reduce probability of metastability.
// See MBT's note on async design and CDC.
//
// The three flops should be don't touched in synopsys
// and abutted in physical design to reduce chances of metastability.
//
// Use of reset is optional; it can be used to hold a known value during reset
// if for instance, the value is coming off chip.
//
// the code is structured this way because synopsys's
// support for hierarchical placement groups appears
// not to work for parameterized modules.
// so we must have a non-parameterized module
// in order to abut the three registers, which
// have two different clocks.
//
`define bsg_launch_sync_sync_unit_hard(EDGE,bits) \
\
module bsg_launch_sync_sync_``EDGE``_``bits``_unit \
(input iclk_i \
,input iclk_reset_i \
,input oclk_i \
,input [bits-1:0] iclk_data_i \
,output [bits-1:0] iclk_data_o \
,output [bits-1:0] oclk_data_o \
); \
\
genvar i; \
\
logic [bits-1:0] bsg_SYNC_LNCH_r; \
logic [bits-1:0] bsg_SYNC_2_r; \
\
assign iclk_data_o = bsg_SYNC_LNCH_r; \
assign oclk_data_o = bsg_SYNC_2_r; \
\
always_ff @(EDGE iclk_i) \
begin \
if (iclk_reset_i) \
bsg_SYNC_LNCH_r <= {bits{1'b0}}; \
else \
bsg_SYNC_LNCH_r <= iclk_data_i; \
end \
\
for (i = 0; i < bits; i = i + 1) \
begin : blss_unit \
SDFFYQ2D_X2N_A7P5PP96PTS_C16 hard_sync_int \
(.D (bsg_SYNC_LNCH_r[i]) \
,.CK (oclk_i) \
,.SI (1'b0) \
,.SE (1'b0) \
,.Q (bsg_SYNC_2_r[i]) \
); \
end \
\
endmodule
`BSG_ABSTRACT_MODULE(bsg_launch_sync_sync)
// bsg_launch_sync_sync_posedge_1_unit
`bsg_launch_sync_sync_unit_hard(posedge,1)
`bsg_launch_sync_sync_unit_hard(posedge,2)
`bsg_launch_sync_sync_unit_hard(posedge,3)
`bsg_launch_sync_sync_unit_hard(posedge,4)
`bsg_launch_sync_sync_unit_hard(posedge,5)
`bsg_launch_sync_sync_unit_hard(posedge,6)
`bsg_launch_sync_sync_unit_hard(posedge,7)
`bsg_launch_sync_sync_unit_hard(posedge,8)
// bsg_launch_sync_sync_negedge_1_unit
`bsg_launch_sync_sync_unit_hard(negedge,1)
`bsg_launch_sync_sync_unit_hard(negedge,2)
`bsg_launch_sync_sync_unit_hard(negedge,3)
`bsg_launch_sync_sync_unit_hard(negedge,4)
`bsg_launch_sync_sync_unit_hard(negedge,5)
`bsg_launch_sync_sync_unit_hard(negedge,6)
`bsg_launch_sync_sync_unit_hard(negedge,7)
`bsg_launch_sync_sync_unit_hard(negedge,8)
// warning: if you make this != 8, you need
// to modify other parts of this code
`define blss_max_block 8
// handle trailer bits
`define blss_if_clause(EDGE,num) if ((width_p % `blss_max_block) == num) begin: z \
bsg_launch_sync_sync_``EDGE``_``num``_unit blss \
(.iclk_i \
,.iclk_reset_i \
,.oclk_i \
,.iclk_data_i(iclk_data_i[width_p-1-:num]) \
,.iclk_data_o(iclk_data_o[width_p-1-:num]) \
,.oclk_data_o(oclk_data_o[width_p-1-:num]) \
); end
module bsg_launch_sync_sync #(parameter `BSG_INV_PARAM(width_p)
, parameter use_negedge_for_launch_p = 0)
(input iclk_i
, input iclk_reset_i
, input oclk_i
, input [width_p-1:0] iclk_data_i
, output [width_p-1:0] iclk_data_o // after launch flop
, output [width_p-1:0] oclk_data_o // after sync flops
);
genvar i;
// synopsys translate_off
initial assert (iclk_reset_i !== 'z)
else
begin
$error("%m iclk_reset should be connected");
$finish();
end
// synopsys translate_on
if (use_negedge_for_launch_p)
begin: n
for (i = 0; i < (width_p/`blss_max_block); i = i + 1)
begin : maxb
bsg_launch_sync_sync_negedge_8_unit blss
(.iclk_i
,.iclk_reset_i
,.oclk_i
,.iclk_data_i(iclk_data_i[i*`blss_max_block+:`blss_max_block])
,.iclk_data_o(iclk_data_o[i*`blss_max_block+:`blss_max_block])
,.oclk_data_o(oclk_data_o[i*`blss_max_block+:`blss_max_block])
);
end
`blss_if_clause(negedge,1) else
`blss_if_clause(negedge,2) else
`blss_if_clause(negedge,3) else
`blss_if_clause(negedge,4) else
`blss_if_clause(negedge,5) else
`blss_if_clause(negedge,6) else
`blss_if_clause(negedge,7)
end
else
begin: p
for (i = 0; i < (width_p/`blss_max_block); i = i + 1)
begin : maxb
bsg_launch_sync_sync_posedge_8_unit blss
(.iclk_i
,.iclk_reset_i
,.oclk_i
,.iclk_data_i(iclk_data_i[i*`blss_max_block+:`blss_max_block])
,.iclk_data_o(iclk_data_o[i*`blss_max_block+:`blss_max_block])
,.oclk_data_o(oclk_data_o[i*`blss_max_block+:`blss_max_block])
);
end
`blss_if_clause(posedge,1) else
`blss_if_clause(posedge,2) else
`blss_if_clause(posedge,3) else
`blss_if_clause(posedge,4) else
`blss_if_clause(posedge,5) else
`blss_if_clause(posedge,6) else
`blss_if_clause(posedge,7)
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_launch_sync_sync)
|
/*
* <file> <desc>
*
* <fulldesc>
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017 [email protected]
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
*/
`timescale 1ns/1ns
module mmio (
input clk_i,
input reset_i,
input [5:0] addr_i, // 32-bit addresses, so only 6 bits needed to span 256 bytes of mem
input write_i,
input read_i,
input [31:0] data_i,
output reg [31:0] data_o,
output [79:0] keys
);
// Wire definitions ===========================================================================
// Registers ==================================================================================
reg [79:0] keys_r = 80'hffffffffffffffff;
// Assignments ================================================================================
assign keys = keys_r;
// Module connections =========================================================================
// Simulation branches and control ============================================================
// Other logic ================================================================================
always @(negedge clk_i)
if( !reset_i ) begin
if( write_i ) begin
case(addr_i)
0: keys_r[31:0] <= data_i;
1: keys_r[63:32] <= data_i;
2: keys_r[79:64] <= data_i[15:0];
endcase
end
if( read_i ) begin
case(addr_i)
0: data_o <= keys_r[31:0];
1: data_o <= keys_r[63:32];
2: data_o <= {16'hff,keys_r[79:64]};
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EDFXTP_TB_V
`define SKY130_FD_SC_HD__EDFXTP_TB_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__edfxtp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 DE = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 DE = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 DE = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 DE = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__edfxtp dut (.D(D), .DE(DE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EDFXTP_TB_V
|
//=================================================
//
// Hsiang-Yi Chung
// March 2016
//
// This Module is for averaging samples from an ADC.
// It performs averaging on 8 samples at a time.
//
//=================================================
module Average_Filter(
input [11:0] in,
input clk,
input reset_n,
output reg out_ready,
output reg [11:0] out1,
output reg [11:0] out2
);
localparam s0 = 3'b000;
localparam s1 = 3'b001;
localparam s2 = 3'b010;
localparam s3 = 3'b011;
localparam s4 = 3'b100;
localparam s5 = 3'b101;
localparam s6 = 3'b110;
localparam s7 = 3'b111;
reg [2:0] nextState, state;
reg [11:0] sample_array1 [7:0];
reg [11:0] sample_array2 [7:0];
reg [7:0] counter1, counter2;
reg inc_count1, inc_count2, reset_count1, reset_count2, compute_avg,
update_array1, update_array2;
reg [14:0] temp;
initial begin
counter1 = 0;
counter2 = 0;
state = 0;
end
always @ (posedge clk) begin
if(!reset_n) begin
state <= s0;
end
else begin
state <= nextState;
end
end
always @ (posedge clk) begin
if(inc_count1) begin
counter1 <= counter1 + 1;
end
if(inc_count2) begin
counter2 <= counter2 + 1;
end
if(reset_count1) begin
counter1 <= 0;
end
if(reset_count2) begin
counter2 <= 0;
end
if(compute_avg) begin
temp = sample_array1[0] + sample_array1[1] + sample_array1[2] + sample_array1[3] + sample_array1[4] +
sample_array1[5] + sample_array1[6] + sample_array1[7];
out1 = temp >> 3;
temp = sample_array2[0] + sample_array2[1] + sample_array2[2] + sample_array2[3] + sample_array2[4] +
sample_array2[5] + sample_array2[6] + sample_array2[7];
out2 = temp >> 3;
end
if(update_array1) begin
sample_array1[counter1[2:0]] <= in;
end
if(update_array2) begin
sample_array2[counter2[2:0]] <= in;
end
end
always @ * begin
inc_count1 = 0; inc_count2 = 0; reset_count1 = 0; reset_count2 = 0; out_ready = 0; compute_avg = 0;
update_array1 = 0; update_array2 = 0;
case(state)
s0: begin
update_array1 = 1;
nextState = s1;
end
s1: begin
if(counter1 == 7) begin
reset_count1 = 1;
nextState = s2;
end else begin
inc_count1 = 1;
nextState = s0;
end
end
s2: begin
update_array2 = 1;
nextState = s3;
end
s3: begin
if(counter2 == 7) begin
reset_count2 = 1;
nextState = s4;
end else begin
inc_count2 = 1;
nextState = s2;
end
end
s4: begin
update_array1 = 1;
compute_avg = 1;
nextState = s5;
end
s5: begin
inc_count1 = 1;
out_ready = 1;
nextState = s0;
end
endcase
end
endmodule
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module foo;
reg [2:0] cond;
reg test;
initial begin
cond = 0;
test = cond ? 1'b1 : 1'b0;
if (test !== 1'b0) begin
$display("FAILED -- cond=%b, test=%b", cond, test);
$finish;
end
cond = 1;
test = cond ? 1'b1 : 1'b0;
if (test !== 1) begin
$display("FAILED -- cond=%b, test=%b", cond, test);
$finish;
end
cond = 2;
test = cond ? 1'b1 : 1'b0;
if (test !== 1) begin
$display("FAILED -- cond=%b, test=%b", cond, test);
$finish;
end
$display("PASSED");
end // initial begin
endmodule
|
/**
* bsg_fpu_classify.v
*
* in the spirit of RISC-V FCLASS instruction.
*
* o[0] = neg infty.
* o[1] = neg normal number
* o[2] = neg subnormal number
* o[3] = neg zero
* o[4] = pos zero
* o[5] = pos subnormal number
* o[6] = pos normal number
* o[7] = pos infty
* o[8] = sig nan
* o[9] = quite nan
*/
`include "bsg_defines.v"
module bsg_fpu_classify
#(parameter `BSG_INV_PARAM(e_p)
, parameter `BSG_INV_PARAM(m_p)
, parameter width_lp=(e_p+m_p+1)
, parameter out_width_lp=width_lp
)
(
input [width_lp-1:0] a_i
, output [out_width_lp-1:0] class_o
);
logic zero;
logic nan;
logic sig_nan;
logic infty;
logic denormal;
logic sign;
bsg_fpu_preprocess #(
.e_p(e_p)
,.m_p(m_p)
) prep (
.a_i(a_i)
,.zero_o(zero)
,.nan_o(nan)
,.sig_nan_o(sig_nan)
,.infty_o(infty)
,.exp_zero_o()
,.man_zero_o()
,.denormal_o(denormal)
,.sign_o(sign)
,.exp_o()
,.man_o()
);
assign class_o[0] = sign & infty;
assign class_o[1] = sign & (~infty) & (~denormal) & (~nan) & (~zero);
assign class_o[2] = sign & denormal;
assign class_o[3] = sign & zero;
assign class_o[4] = ~sign & zero;
assign class_o[5] = ~sign & denormal;
assign class_o[6] = ~sign & (~infty) & (~denormal) & (~nan) & (~zero);
assign class_o[7] = ~sign & infty;
assign class_o[8] = sig_nan;
assign class_o[9] = nan & ~sig_nan;
assign class_o[out_width_lp-1:10] = '0;
endmodule
`BSG_ABSTRACT_MODULE(bsg_fpu_classify)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/17/2016 05:20:59 PM
// Design Name:
// Module Name: Priority_Codec_64
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Priority_Codec_64(
input wire [54:0] Data_Dec_i,
output reg [5:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
Data_Bin_o=6'b000000;
if(~Data_Dec_i[54]) begin Data_Bin_o = 6'b000000;//0
end else if(~Data_Dec_i[53]) begin Data_Bin_o = 6'b000001;//1
end else if(~Data_Dec_i[52]) begin Data_Bin_o = 6'b000010;//2
end else if(~Data_Dec_i[51]) begin Data_Bin_o = 6'b000011;//3
end else if(~Data_Dec_i[50]) begin Data_Bin_o = 6'b000100;//4
end else if(~Data_Dec_i[49]) begin Data_Bin_o = 6'b000101;//5
end else if(~Data_Dec_i[48]) begin Data_Bin_o = 6'b000110;//6
end else if(~Data_Dec_i[47]) begin Data_Bin_o = 6'b000111;//7
end else if(~Data_Dec_i[46]) begin Data_Bin_o = 6'b001000;//8
end else if(~Data_Dec_i[45]) begin Data_Bin_o = 6'b001001;//9
end else if(~Data_Dec_i[44]) begin Data_Bin_o = 6'b001010;//10
end else if(~Data_Dec_i[43]) begin Data_Bin_o = 6'b001011;//11
end else if(~Data_Dec_i[42]) begin Data_Bin_o = 6'b001100;//12
end else if(~Data_Dec_i[41]) begin Data_Bin_o = 6'b001101;//13
end else if(~Data_Dec_i[40]) begin Data_Bin_o = 6'b001110;//14
end else if(~Data_Dec_i[39]) begin Data_Bin_o = 6'b001111;//15
end else if(~Data_Dec_i[38]) begin Data_Bin_o = 6'b010000;//16
end else if(~Data_Dec_i[37]) begin Data_Bin_o = 6'b010001;//17
end else if(~Data_Dec_i[36]) begin Data_Bin_o = 6'b010010;//18
end else if(~Data_Dec_i[35]) begin Data_Bin_o = 6'b010011;//19
end else if(~Data_Dec_i[34]) begin Data_Bin_o = 6'b010100;//20
end else if(~Data_Dec_i[33]) begin Data_Bin_o = 6'b010101;//21
end else if(~Data_Dec_i[32]) begin Data_Bin_o = 6'b010110;//22
end else if(~Data_Dec_i[31]) begin Data_Bin_o = 6'b010111;//23
end else if(~Data_Dec_i[30]) begin Data_Bin_o = 6'b011000;//24
end else if(~Data_Dec_i[29]) begin Data_Bin_o = 6'b010101;//25
end else if(~Data_Dec_i[28]) begin Data_Bin_o = 6'b010110;//26
end else if(~Data_Dec_i[27]) begin Data_Bin_o = 6'b010111;//27
end else if(~Data_Dec_i[26]) begin Data_Bin_o = 6'b011000;//28
end else if(~Data_Dec_i[25]) begin Data_Bin_o = 6'b011001;//29
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 6'b011010;//30
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 6'b011011;//31
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 6'b011100;//32
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 6'b011101;//33
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 6'b011110;//34
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 6'b011111;//35
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 6'b100000;//36
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 6'b100001;//37
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 6'b100010;//38
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 6'b100011;//39
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 6'b100100;//40
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 6'b100101;//41
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 6'b100110;//42
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 6'b100111;//43
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 6'b101000;//44
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 6'b101001;//45
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 6'b101010;//46
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 6'b101011;//47
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 6'b101100;//48
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 6'b101101;//49
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 6'b101110;//50
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 6'b101111;//51
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 6'b110000;//52
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 6'b110001;//53
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 6'b110010;//54
end else begin Data_Bin_o = 6'b000000;//zero value
end
end
endmodule |
/*
* Copyright 2013-2021 Robert Newgard
*
* This file is part of fcs.
*
* fcs is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* fcs is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with fcs. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
`include "fcs32_16.v"
`include "fcs32_brev.v"
module uut_16_top
(
output wire [31:0] res_o,
output wire [31:0] exp_o,
output wire [31:0] obs_o,
output wire val_o,
input wire [15:0] data_i,
input wire sof_i,
input wire eof_i,
input wire pclk_i
);
/* -----------------------------------------------------------
parameters
------------------------------------------------------------*/
localparam LO = 1'b0;
localparam HI = 1'b1;
localparam [31:0] ZEROS = {32{LO}};
localparam [31:0] ONES = {32{HI}};
/* -----------------------------------------------------------
net declarations
------------------------------------------------------------*/
reg [15:0] data_z1;
reg sof_z1;
reg [15:0] data_z2;
reg sof_z2;
reg val_z3;
reg [31:0] exp_z3;
reg [31:0] fcs_z3;
reg val_z4;
reg [31:0] exp_z4;
reg [31:0] fcs_z4;
reg val_z5;
reg [31:0] exp_z5;
reg [31:0] fcs_z5;
/* -----------------------------------------------------------
input assignments
------------------------------------------------------------*/
/* -----------------------------------------------------------
Pipeline
------------------------------------------------------------*/
always @ (posedge pclk_i) begin
data_z1[15:0] <= data_i[15:0];
sof_z1 <= sof_i;
data_z2[15:0] <= data_z1[15:0];
sof_z2 <= sof_z1;
val_z3 <= eof_i;
if (eof_i == HI) begin
exp_z3[31:0] <= {data_z1[15:0], data_i[15:0]};
end
if (sof_z2 == HI) begin
fcs_z3[31:0] <= fcs32_16(data_z2[15:0], ONES[31:0]);
end else begin
fcs_z3[31:0] <= fcs32_16(data_z2[15:0], fcs_z3[31:0]);
end
val_z4 <= val_z3;
exp_z4[31:0] <= exp_z3[31:0];
fcs_z4[31:0] <= fcs32_brev(fcs_z3[31:0]);
val_z5 <= val_z4;
exp_z5[31:0] <= exp_z4[31:0];
fcs_z5[31:0] <= fcs_z4[31:0];
end
/* -----------------------------------------------------------
output assignments
------------------------------------------------------------*/
always @ (*) begin
val_o = val_z5;
res_o[31:0] = fcs_z3[31:0];
exp_o[31:0] = exp_z5[31:0];
obs_o[31:0] = fcs_z5[31:0];
end
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.3.1 (lin64) Build 1056140 Thu Oct 30 16:30:39 MDT 2014
// Date : Thu Jul 2 14:31:27 2015
// Host : parallella running 64-bit Ubuntu 14.04.2 LTS
// Command : write_verilog -force -mode synth_stub
// /home/aolofsson/Work_all/oh/elink/scripts/xilinx/temp/temp.srcs/sources_1/ip/fifo_async_104x16/fifo_async_104x16_stub.v
// Design : fifo_async_104x16
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2014.3.1" *)
module fifo_async_104x16(wr_clk, wr_rst, rd_clk, rd_rst, din, wr_en, rd_en, dout, full, almost_full, empty, valid, prog_full)
/* synthesis syn_black_box black_box_pad_pin="wr_clk,wr_rst,rd_clk,rd_rst,din[103:0],wr_en,rd_en,dout[103:0],full,almost_full,empty,valid,prog_full" */;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [103:0]din;
input wr_en;
input rd_en;
output [103:0]dout;
output full;
output almost_full;
output empty;
output valid;
output prog_full;
endmodule
|
/*
* Copyright (c) 2015-2016 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* System fabric
*/
`include "common.vh"
`include "ocp_const.vh"
/*
* Fabric
*/
module fabric(
clk,
nrst,
/* OCP interface: instructions (master) */
i_I_MAddr, i_I_MCmd, i_I_MData, i_I_MByteEn, o_I_SCmdAccept, o_I_SData, o_I_SResp,
/* OCP interface: data (master) */
i_D_MAddr, i_D_MCmd, i_D_MData, i_D_MByteEn, o_D_SCmdAccept, o_D_SData, o_D_SResp,
/* OCP interface: Port 0 (slave) */
o_P0_MAddr, o_P0_MCmd, o_P0_MData, o_P0_MByteEn, i_P0_SCmdAccept, i_P0_SData, i_P0_SResp,
/* OCP interface: Port 1 (slave) */
o_P1_MAddr, o_P1_MCmd, o_P1_MData, o_P1_MByteEn, i_P1_SCmdAccept, i_P1_SData, i_P1_SResp,
/* OCP interface: Port 2 (slave) */
o_P2_MAddr, o_P2_MCmd, o_P2_MData, o_P2_MByteEn, i_P2_SCmdAccept, i_P2_SData, i_P2_SResp,
/* OCP interface: Port 3 (slave) */
o_P3_MAddr, o_P3_MCmd, o_P3_MData, o_P3_MByteEn, i_P3_SCmdAccept, i_P3_SData, i_P3_SResp,
/* OCP interface: Port 4 (slave) */
o_P4_MAddr, o_P4_MCmd, o_P4_MData, o_P4_MByteEn, i_P4_SCmdAccept, i_P4_SData, i_P4_SResp
);
localparam NPORTS = 5;
input wire clk;
input wire nrst;
/* OCP interface: instructions (master) */
input wire [`ADDR_WIDTH-1:0] i_I_MAddr;
input wire [2:0] i_I_MCmd;
input wire [`DATA_WIDTH-1:0] i_I_MData;
input wire [`BEN_WIDTH-1:0] i_I_MByteEn;
output wire o_I_SCmdAccept;
output wire [`DATA_WIDTH-1:0] o_I_SData;
output wire [1:0] o_I_SResp;
/* OCP interface: data (master) */
input wire [`ADDR_WIDTH-1:0] i_D_MAddr;
input wire [2:0] i_D_MCmd;
input wire [`DATA_WIDTH-1:0] i_D_MData;
input wire [`BEN_WIDTH-1:0] i_D_MByteEn;
output wire o_D_SCmdAccept;
output wire [`DATA_WIDTH-1:0] o_D_SData;
output wire [1:0] o_D_SResp;
/* OCP interface: Port 0 (slave) */
output wire [`ADDR_WIDTH-1:0] o_P0_MAddr;
output wire [2:0] o_P0_MCmd;
output wire [`DATA_WIDTH-1:0] o_P0_MData;
output wire [`BEN_WIDTH-1:0] o_P0_MByteEn;
input wire i_P0_SCmdAccept;
input wire [`DATA_WIDTH-1:0] i_P0_SData;
input wire [1:0] i_P0_SResp;
/* OCP interface: Port 1 (slave) */
output wire [`ADDR_WIDTH-1:0] o_P1_MAddr;
output wire [2:0] o_P1_MCmd;
output wire [`DATA_WIDTH-1:0] o_P1_MData;
output wire [`BEN_WIDTH-1:0] o_P1_MByteEn;
input wire i_P1_SCmdAccept;
input wire [`DATA_WIDTH-1:0] i_P1_SData;
input wire [1:0] i_P1_SResp;
/* OCP interface: Port 2 (slave) */
output wire [`ADDR_WIDTH-1:0] o_P2_MAddr;
output wire [2:0] o_P2_MCmd;
output wire [`DATA_WIDTH-1:0] o_P2_MData;
output wire [`BEN_WIDTH-1:0] o_P2_MByteEn;
input wire i_P2_SCmdAccept;
input wire [`DATA_WIDTH-1:0] i_P2_SData;
input wire [1:0] i_P2_SResp;
/* OCP interface: Port 3 (slave) */
output wire [`ADDR_WIDTH-1:0] o_P3_MAddr;
output wire [2:0] o_P3_MCmd;
output wire [`DATA_WIDTH-1:0] o_P3_MData;
output wire [`BEN_WIDTH-1:0] o_P3_MByteEn;
input wire i_P3_SCmdAccept;
input wire [`DATA_WIDTH-1:0] i_P3_SData;
input wire [1:0] i_P3_SResp;
/* OCP interface: Port 4 (slave) */
output wire [`ADDR_WIDTH-1:0] o_P4_MAddr;
output wire [2:0] o_P4_MCmd;
output wire [`DATA_WIDTH-1:0] o_P4_MData;
output wire [`BEN_WIDTH-1:0] o_P4_MByteEn;
input wire i_P4_SCmdAccept;
input wire [`DATA_WIDTH-1:0] i_P4_SData;
input wire [1:0] i_P4_SResp;
/** Internal interconnect **/
wire I_P_SCmdAccept[0:NPORTS-1];
wire [`DATA_WIDTH-1:0] I_P_SData[0:NPORTS-1];
wire [1:0] I_P_SResp[0:NPORTS-1];
wire D_P_SCmdAccept[0:NPORTS-1];
wire [`DATA_WIDTH-1:0] D_P_SData[0:NPORTS-1];
wire [1:0] D_P_SResp[0:NPORTS-1];
wire [`ADDR_WIDTH-1:0] o_P_MAddr[0:NPORTS-1];
wire [2:0] o_P_MCmd[0:NPORTS-1];
wire [`DATA_WIDTH-1:0] o_P_MData[0:NPORTS-1];
wire [`BEN_WIDTH-1:0] o_P_MByteEn[0:NPORTS-1];
wire i_P_SCmdAccept[0:NPORTS-1];
wire [`DATA_WIDTH-1:0] i_P_SData[0:NPORTS-1];
wire [1:0] i_P_SResp[0:NPORTS-1];
assign o_P0_MAddr = o_P_MAddr[0];
assign o_P0_MCmd = o_P_MCmd[0];
assign o_P0_MData = o_P_MData[0];
assign o_P0_MByteEn = o_P_MByteEn[0];
assign i_P_SCmdAccept[0] = i_P0_SCmdAccept;
assign i_P_SData[0] = i_P0_SData;
assign i_P_SResp[0] = i_P0_SResp;
assign o_P1_MAddr = o_P_MAddr[1];
assign o_P1_MCmd = o_P_MCmd[1];
assign o_P1_MData = o_P_MData[1];
assign o_P1_MByteEn = o_P_MByteEn[1];
assign i_P_SCmdAccept[1] = i_P1_SCmdAccept;
assign i_P_SData[1] = i_P1_SData;
assign i_P_SResp[1] = i_P1_SResp;
assign o_P2_MAddr = o_P_MAddr[2];
assign o_P2_MCmd = o_P_MCmd[2];
assign o_P2_MData = o_P_MData[2];
assign o_P2_MByteEn = o_P_MByteEn[2];
assign i_P_SCmdAccept[2] = i_P2_SCmdAccept;
assign i_P_SData[2] = i_P2_SData;
assign i_P_SResp[2] = i_P2_SResp;
assign o_P3_MAddr = o_P_MAddr[3];
assign o_P3_MCmd = o_P_MCmd[3];
assign o_P3_MData = o_P_MData[3];
assign o_P3_MByteEn = o_P_MByteEn[3];
assign i_P_SCmdAccept[3] = i_P3_SCmdAccept;
assign i_P_SData[3] = i_P3_SData;
assign i_P_SResp[3] = i_P3_SResp;
assign o_P4_MAddr = o_P_MAddr[4];
assign o_P4_MCmd = o_P_MCmd[4];
assign o_P4_MData = o_P_MData[4];
assign o_P4_MByteEn = o_P_MByteEn[4];
assign i_P_SCmdAccept[4] = i_P4_SCmdAccept;
assign i_P_SData[4] = i_P4_SData;
assign i_P_SResp[4] = i_P4_SResp;
assign o_I_SCmdAccept = I_P_SCmdAccept[0] & I_P_SCmdAccept[1] & I_P_SCmdAccept[2] &
I_P_SCmdAccept[3] & I_P_SCmdAccept[4];
assign o_I_SData = I_P_SData[0] | I_P_SData[1] | I_P_SData[2] | I_P_SData[3] | I_P_SData[4];
assign o_I_SResp = I_P_SResp[0] | I_P_SResp[1] | I_P_SResp[2] | I_P_SResp[3] | I_P_SResp[4];
assign o_D_SCmdAccept = D_P_SCmdAccept[0] & D_P_SCmdAccept[1] & D_P_SCmdAccept[2] &
D_P_SCmdAccept[3] & D_P_SCmdAccept[4];
assign o_D_SData = D_P_SData[0] | D_P_SData[1] | D_P_SData[2] | D_P_SData[3] | D_P_SData[4];
assign o_D_SResp = D_P_SResp[0] | D_P_SResp[1] | D_P_SResp[2] | D_P_SResp[3] | D_P_SResp[4];
/* Ports FSMs */
genvar i;
generate
for (i=0; i<NPORTS; i=i+1)
begin : ports_inst
fabric_port #(.PORT(i)) port(
.clk(clk),
.nrst(nrst),
.i_I_MAddr(i_I_MAddr),
.i_I_MCmd(i_I_MCmd),
.i_I_MData(i_I_MData),
.i_I_MByteEn(i_I_MByteEn),
.o_I_SCmdAccept(I_P_SCmdAccept[i]),
.o_I_SData(I_P_SData[i]),
.o_I_SResp(I_P_SResp[i]),
.i_D_MAddr(i_D_MAddr),
.i_D_MCmd(i_D_MCmd),
.i_D_MData(i_D_MData),
.i_D_MByteEn(i_D_MByteEn),
.o_D_SCmdAccept(D_P_SCmdAccept[i]),
.o_D_SData(D_P_SData[i]),
.o_D_SResp(D_P_SResp[i]),
.o_P_MAddr(o_P_MAddr[i]),
.o_P_MCmd(o_P_MCmd[i]),
.o_P_MData(o_P_MData[i]),
.o_P_MByteEn(o_P_MByteEn[i]),
.i_P_SCmdAccept(i_P_SCmdAccept[i]),
.i_P_SData(i_P_SData[i]),
.i_P_SResp(i_P_SResp[i])
);
end
endgenerate
endmodule /* fabric */
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_pipe_rate.v
// Version : 3.2
//------------------------------------------------------------------------------
// Filename : pipe_rate.v
// Description : PIPE Rate Module for 7 Series Transceiver
// Version : 20.1
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Rate Module --------------------------------------------------
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PCIeGen2x8If128_pipe_rate #
(
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
parameter TXDATA_WAIT_MAX = 4'd15 // TXDATA wait max
)
(
//---------- Input -------------------------------------
input RATE_CLK,
input RATE_RST_N,
input RATE_RST_IDLE,
input RATE_ACTIVE_LANE,
input [ 1:0] RATE_RATE_IN,
input RATE_CPLLLOCK,
input RATE_QPLLLOCK,
input RATE_MMCM_LOCK,
input RATE_DRP_DONE,
input RATE_RXPMARESETDONE,
input RATE_TXRESETDONE,
input RATE_RXRESETDONE,
input RATE_TXRATEDONE,
input RATE_RXRATEDONE,
input RATE_PHYSTATUS,
input RATE_RESETOVRD_DONE,
input RATE_TXSYNC_DONE,
input RATE_RXSYNC_DONE,
//---------- Output ------------------------------------
output RATE_CPLLPD,
output RATE_QPLLPD,
output RATE_CPLLRESET,
output RATE_QPLLRESET,
output RATE_TXPMARESET,
output RATE_RXPMARESET,
output RATE_DRP_START,
output [ 1:0] RATE_SYSCLKSEL,
output RATE_PCLK_SEL,
output RATE_GEN3,
output RATE_DRP_X16X20_MODE,
output RATE_DRP_X16,
output [ 2:0] RATE_RATE_OUT,
output RATE_RESETOVRD_START,
output RATE_TXSYNC_START,
output RATE_DONE,
output RATE_RXSYNC_START,
output RATE_RXSYNC,
output RATE_IDLE,
output [ 4:0] RATE_FSM
);
//---------- Input FF or Buffer ------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg cplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg cplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_done_reg2;
//---------- Internal Signals --------------------------
wire pll_lock;
wire [ 2:0] rate;
reg [ 3:0] txdata_wait_cnt = 4'd0;
reg txratedone = 1'd0;
reg rxratedone = 1'd0;
reg phystatus = 1'd0;
reg ratedone = 1'd0;
reg gen3_exit = 1'd0;
//---------- Output FF or Buffer -----------------------
reg cpllpd = 1'd0;
reg qpllpd = 1'd0;
reg cpllreset = 1'd0;
reg qpllreset = 1'd0;
reg txpmareset = 1'd0;
reg rxpmareset = 1'd0;
reg [ 1:0] sysclksel = (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
reg gen3 = 1'd0;
reg pclk_sel = 1'd0;
reg [ 2:0] rate_out = 3'd0;
reg drp_start = 1'd0;
reg drp_x16x20_mode = 1'd0;
reg drp_x16 = 1'd0;
reg [4:0] fsm = 0;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 0;
localparam FSM_PLL_PU = 1; // Gen 3 only
localparam FSM_PLL_PURESET = 2; // Gen 3 only
localparam FSM_PLL_LOCK = 3; // Gen 3 or reset only
localparam FSM_DRP_X16_GEN3_START = 4;
localparam FSM_DRP_X16_GEN3_DONE = 5;
localparam FSM_PMARESET_HOLD = 6; // Gen 3 or reset only
localparam FSM_PLL_SEL = 7; // Gen 3 or reset only
localparam FSM_MMCM_LOCK = 8; // Gen 3 or reset only
localparam FSM_DRP_START = 9; // Gen 3 or reset only
localparam FSM_DRP_DONE = 10; // Gen 3 or reset only
localparam FSM_PMARESET_RELEASE = 11; // Gen 3 only
localparam FSM_PMARESET_DONE = 12; // Gen 3 only
localparam FSM_TXDATA_WAIT = 13;
localparam FSM_PCLK_SEL = 14;
localparam FSM_DRP_X16_START = 15;
localparam FSM_DRP_X16_DONE = 16;
localparam FSM_RATE_SEL = 17;
localparam FSM_RXPMARESETDONE = 18;
localparam FSM_DRP_X20_START = 19;
localparam FSM_DRP_X20_DONE = 20;
localparam FSM_RATE_DONE = 21;
localparam FSM_RESETOVRD_START = 22; // PCIe use mode 1.0 only
localparam FSM_RESETOVRD_DONE = 23; // PCIe use mode 1.0 only
localparam FSM_PLL_PDRESET = 24;
localparam FSM_PLL_PD = 25;
localparam FSM_TXSYNC_START = 26;
localparam FSM_TXSYNC_DONE = 27;
localparam FSM_DONE = 28; // Must sync value to pipe_user.v
localparam FSM_RXSYNC_START = 29; // Gen 3 only
localparam FSM_RXSYNC_DONE = 30; // Gen 3 only
//---------- Input FF ----------------------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
//---------- 1st Stage FF --------------------------
rst_idle_reg1 <= 1'd0;
rate_in_reg1 <= 2'd0;
cplllock_reg1 <= 1'd0;
qplllock_reg1 <= 1'd0;
mmcm_lock_reg1 <= 1'd0;
drp_done_reg1 <= 1'd0;
rxpmaresetdone_reg1 <= 1'd0;
txresetdone_reg1 <= 1'd0;
rxresetdone_reg1 <= 1'd0;
txratedone_reg1 <= 1'd0;
rxratedone_reg1 <= 1'd0;
phystatus_reg1 <= 1'd0;
resetovrd_done_reg1 <= 1'd0;
txsync_done_reg1 <= 1'd0;
rxsync_done_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
rst_idle_reg2 <= 1'd0;
rate_in_reg2 <= 2'd0;
cplllock_reg2 <= 1'd0;
qplllock_reg2 <= 1'd0;
mmcm_lock_reg2 <= 1'd0;
drp_done_reg2 <= 1'd0;
rxpmaresetdone_reg2 <= 1'd0;
txresetdone_reg2 <= 1'd0;
rxresetdone_reg2 <= 1'd0;
txratedone_reg2 <= 1'd0;
rxratedone_reg2 <= 1'd0;
phystatus_reg2 <= 1'd0;
resetovrd_done_reg2 <= 1'd0;
txsync_done_reg2 <= 1'd0;
rxsync_done_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
rst_idle_reg1 <= RATE_RST_IDLE;
rate_in_reg1 <= RATE_RATE_IN;
cplllock_reg1 <= RATE_CPLLLOCK;
qplllock_reg1 <= RATE_QPLLLOCK;
mmcm_lock_reg1 <= RATE_MMCM_LOCK;
drp_done_reg1 <= RATE_DRP_DONE;
rxpmaresetdone_reg1 <= RATE_RXPMARESETDONE;
txresetdone_reg1 <= RATE_TXRESETDONE;
rxresetdone_reg1 <= RATE_RXRESETDONE;
txratedone_reg1 <= RATE_TXRATEDONE;
rxratedone_reg1 <= RATE_RXRATEDONE;
phystatus_reg1 <= RATE_PHYSTATUS;
resetovrd_done_reg1 <= RATE_RESETOVRD_DONE;
txsync_done_reg1 <= RATE_TXSYNC_DONE;
rxsync_done_reg1 <= RATE_RXSYNC_DONE;
//---------- 2nd Stage FF --------------------------
rst_idle_reg2 <= rst_idle_reg1;
rate_in_reg2 <= rate_in_reg1;
cplllock_reg2 <= cplllock_reg1;
qplllock_reg2 <= qplllock_reg1;
mmcm_lock_reg2 <= mmcm_lock_reg1;
drp_done_reg2 <= drp_done_reg1;
rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
txresetdone_reg2 <= txresetdone_reg1;
rxresetdone_reg2 <= rxresetdone_reg1;
txratedone_reg2 <= txratedone_reg1;
rxratedone_reg2 <= rxratedone_reg1;
phystatus_reg2 <= phystatus_reg1;
resetovrd_done_reg2 <= resetovrd_done_reg1;
txsync_done_reg2 <= txsync_done_reg1;
rxsync_done_reg2 <= rxsync_done_reg1;
end
end
//---------- Select CPLL or QPLL Lock ------------------------------------------
// Gen1 : Wait for QPLL lock if QPLL is used for Gen1/Gen2, else wait for CPLL lock
// Gen2 : Wait for QPLL lock if QPLL is used for Gen1/Gen2, else wait for CPLL lock
// Gen3 : Wait for QPLL lock
//------------------------------------------------------------------------------
assign pll_lock = (rate_in_reg2 == 2'd2) || (PCIE_PLL_SEL == "QPLL") ? qplllock_reg2 : cplllock_reg2;
//---------- Select Rate -------------------------------------------------------
// Gen1 : Div 4 using [TX/RX]OUT_DIV = 4 if QPLL is used for Gen1/Gen2, else div 2 using [TX/RX]OUT_DIV = 2
// Gen2 : Div 2 using [TX/RX]RATE = 3'd2 if QPLL is used for Gen1/Gen2, else div 1 using [TX/RX]RATE = 3'd1
// Gen3 : Div 1 using [TX/RX]OUT_DIV = 1
//------------------------------------------------------------------------------
assign rate = (rate_in_reg2 == 2'd1) && (PCIE_PLL_SEL == "QPLL") ? 3'd2 :
(rate_in_reg2 == 2'd1) && (PCIE_PLL_SEL == "CPLL") ? 3'd1 : 3'd0;
//---------- TXDATA Wait Counter -----------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
txdata_wait_cnt <= 4'd0;
else
//---------- Increment Wait Counter ----------------
if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt < TXDATA_WAIT_MAX))
txdata_wait_cnt <= txdata_wait_cnt + 4'd1;
//---------- Hold Wait Counter ---------------------
else if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt == TXDATA_WAIT_MAX))
txdata_wait_cnt <= txdata_wait_cnt;
//---------- Reset Wait Counter --------------------
else
txdata_wait_cnt <= 4'd0;
end
//---------- Latch TXRATEDONE, RXRATEDONE, and PHYSTATUS -----------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
txratedone <= 1'd0;
rxratedone <= 1'd0;
phystatus <= 1'd0;
ratedone <= 1'd0;
end
else
begin
if (fsm == FSM_RATE_DONE)
begin
//---------- Latch TXRATEDONE ------------------
if (txratedone_reg2)
txratedone <= 1'd1;
else
txratedone <= txratedone;
//---------- Latch RXRATEDONE ------------------
if (rxratedone_reg2)
rxratedone <= 1'd1;
else
rxratedone <= rxratedone;
//---------- Latch PHYSTATUS -------------------
if (phystatus_reg2)
phystatus <= 1'd1;
else
phystatus <= phystatus;
//---------- Latch Rate Done -------------------
if (rxratedone && txratedone && phystatus)
ratedone <= 1'd1;
else
ratedone <= ratedone;
end
else
begin
txratedone <= 1'd0;
rxratedone <= 1'd0;
phystatus <= 1'd0;
ratedone <= 1'd0;
end
end
end
//---------- PIPE Rate FSM -----------------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
fsm <= FSM_PLL_LOCK;
gen3_exit <= 1'd0;
cpllpd <= 1'd0;
qpllpd <= 1'd0;
cpllreset <= 1'd0;
qpllreset <= 1'd0;
txpmareset <= 1'd0;
rxpmareset <= 1'd0;
sysclksel <= (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
pclk_sel <= 1'd0;
gen3 <= 1'd0;
rate_out <= 3'd0;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
//---------- Detect Rate Change ----------------
if (rate_in_reg2 != rate_in_reg1)
begin
fsm <= ((rate_in_reg2 == 2'd2) || (rate_in_reg1 == 2'd2)) ? FSM_PLL_PU : FSM_TXDATA_WAIT;
gen3_exit <= (rate_in_reg2 == 2'd2);
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
end
//---------- Power-up PLL --------------------------
FSM_PLL_PU :
begin
fsm <= FSM_PLL_PURESET;
gen3_exit <= gen3_exit;
cpllpd <= (PCIE_PLL_SEL == "QPLL");
qpllpd <= 1'd0;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Release PLL Resets --------------------
FSM_PLL_PURESET :
begin
fsm <= FSM_PLL_LOCK;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= (PCIE_PLL_SEL == "QPLL");
qpllreset <= 1'd0;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for PLL Lock ---------------------
FSM_PLL_LOCK :
begin
fsm <= (pll_lock ? ((!rst_idle_reg2 || (rate_in_reg2 == 2'd1)) ? FSM_PMARESET_HOLD : FSM_DRP_X16_GEN3_START) : FSM_PLL_LOCK);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP x16 -------------------------
FSM_DRP_X16_GEN3_START :
begin
fsm <= (!drp_done_reg2) ? FSM_DRP_X16_GEN3_DONE : FSM_DRP_X16_GEN3_START;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Wait for DRP x16 Done -----------------
FSM_DRP_X16_GEN3_DONE :
begin
fsm <= drp_done_reg2 ? FSM_PMARESET_HOLD : FSM_DRP_X16_GEN3_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Hold both PMA in Reset ----------------
// Gen1 : Release PMA Reset
// Gen2 : Release PMA Reset
// Gen3 : Hold PMA Reset
//--------------------------------------------------
FSM_PMARESET_HOLD :
begin
fsm <= FSM_PLL_SEL;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= ((rate_in_reg2 == 2'd2) || gen3_exit);
rxpmareset <= ((rate_in_reg2 == 2'd2) || gen3_exit);
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Select PLL ----------------------------
// Gen1 : QPLL if PCIE_PLL_SEL = QPLL, else CPLL
// Gen2 : QPLL if PCIE_PLL_SEL = QPLL, else CPLL
// Gen3 : QPLL
//--------------------------------------------------
FSM_PLL_SEL :
begin
fsm <= FSM_MMCM_LOCK;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= ((rate_in_reg2 == 2'd2) || (PCIE_PLL_SEL == "QPLL")) ? 2'd1 : 2'd0;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Check for MMCM Lock -------------------
FSM_MMCM_LOCK :
begin
fsm <= (mmcm_lock_reg2 && !rxpmaresetdone_reg2 ? FSM_DRP_START : FSM_MMCM_LOCK);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP -----------------------------
FSM_DRP_START:
begin
fsm <= (!drp_done_reg2 ? FSM_DRP_DONE : FSM_DRP_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= ((rate_in_reg2 == 2'd1) || (rate_in_reg2 == 2'd2));
gen3 <= (rate_in_reg2 == 2'd2);
rate_out <= (((rate_in_reg2 == 2'd2) || gen3_exit) ? rate : rate_out);
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for DRP Done ---------------------
FSM_DRP_DONE :
begin
fsm <= ((drp_done_reg2 && pll_lock) ? (rst_idle_reg2 ? FSM_PMARESET_RELEASE : FSM_IDLE): FSM_DRP_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Release PMA Resets --------------------
FSM_PMARESET_RELEASE :
begin
fsm <= FSM_PMARESET_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= 1'd0;
rxpmareset <= 1'd0;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for both TX/RX PMA Reset Dones and PHYSTATUS Deassertion
FSM_PMARESET_DONE :
begin
fsm <= (((rxresetdone_reg2 && txresetdone_reg2 && !phystatus_reg2) || !RATE_ACTIVE_LANE) ? FSM_TXDATA_WAIT : FSM_PMARESET_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for TXDATA to TX[P/N] Latency ----
FSM_TXDATA_WAIT :
begin
fsm <= (txdata_wait_cnt == TXDATA_WAIT_MAX) ? FSM_PCLK_SEL : FSM_TXDATA_WAIT;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Select PCLK Frequency -----------------
// Gen1 : PCLK = 125 MHz
// Gen2 : PCLK = 250 MHz
// Gen3 : PCLK = 250 MHz
//--------------------------------------------------
FSM_PCLK_SEL :
begin
fsm <= ((PCIE_GT_DEVICE == "GTH") && ((rate_in_reg2 == 2'd1) || ((!gen3_exit) && (rate_in_reg2 == 2'd0)))) ? FSM_DRP_X16_START : FSM_RATE_SEL;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= ((rate_in_reg2 == 2'd1) || (rate_in_reg2 == 2'd2));
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP x16 -------------------------
FSM_DRP_X16_START :
begin
fsm <= (!drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Wait for DRP x16 Done -----------------
FSM_DRP_X16_DONE :
begin
fsm <= drp_done_reg2 ? FSM_RATE_SEL : FSM_DRP_X16_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Select Rate ---------------------------
FSM_RATE_SEL :
begin
fsm <= ((PCIE_GT_DEVICE == "GTH") && ((rate_in_reg2 == 2'd1) || ((!gen3_exit) && (rate_in_reg2 == 2'd0)))) ? FSM_RXPMARESETDONE : FSM_RATE_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate; // Update [TX/RX]RATE
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for RXPMARESETDONE De-assertion --
FSM_RXPMARESETDONE :
begin
fsm <= (!rxpmaresetdone_reg2) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP x20 -------------------------
FSM_DRP_X20_START :
begin
fsm <= (!drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd0;
end
//---------- Wait for DRP x20 Done -----------------
FSM_DRP_X20_DONE :
begin
fsm <= drp_done_reg2 ? FSM_RATE_DONE : FSM_DRP_X20_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd0;
end
//---------- Wait for Rate Change Done -------------
FSM_RATE_DONE :
begin
if (ratedone || (rate_in_reg2 == 2'd2) || (gen3_exit) || !RATE_ACTIVE_LANE)
if ((PCIE_USE_MODE == "1.0") && (rate_in_reg2 != 2'd2) && (!gen3_exit))
fsm <= FSM_RESETOVRD_START;
else
fsm <= FSM_PLL_PDRESET;
else
fsm <= FSM_RATE_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Reset Override Start ------------------
FSM_RESETOVRD_START:
begin
fsm <= (!resetovrd_done_reg2 ? FSM_RESETOVRD_DONE : FSM_RESETOVRD_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Reset Override Done -------------------
FSM_RESETOVRD_DONE :
begin
fsm <= (resetovrd_done_reg2 ? FSM_PLL_PDRESET : FSM_RESETOVRD_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Hold PLL Not Used in Reset ------------
FSM_PLL_PDRESET :
begin
fsm <= FSM_PLL_PD;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= (PCIE_PLL_SEL == "QPLL") ? 1'd1 : (rate_in_reg2 == 2'd2);
qpllreset <= (PCIE_PLL_SEL == "QPLL") ? 1'd0 : (rate_in_reg2 != 2'd2);
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Power-Down PLL Not Used ---------------
FSM_PLL_PD :
begin
fsm <= (((rate_in_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? FSM_TXSYNC_START : FSM_DONE);
gen3_exit <= gen3_exit;
cpllpd <= (PCIE_PLL_SEL == "QPLL") ? 1'd1 : (rate_in_reg2 == 2'd2);
qpllpd <= (PCIE_PLL_SEL == "QPLL") ? 1'd0 : (rate_in_reg2 != 2'd2);
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start TX Sync -------------------------
FSM_TXSYNC_START:
begin
fsm <= (!txsync_done_reg2 ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for TX Sync Done -----------------
FSM_TXSYNC_DONE:
begin
fsm <= (txsync_done_reg2 ? FSM_DONE : FSM_TXSYNC_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Rate Change Done ----------------------
FSM_DONE :
begin
fsm <= (((rate_in_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE") && (PCIE_ASYNC_EN == "TRUE")) ? FSM_RXSYNC_START : FSM_IDLE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start RX Sync -------------------------
FSM_RXSYNC_START:
begin
fsm <= (!rxsync_done_reg2 ? FSM_RXSYNC_DONE : FSM_RXSYNC_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for RX Sync Done -----------------
FSM_RXSYNC_DONE:
begin
fsm <= (rxsync_done_reg2 ? FSM_IDLE : FSM_RXSYNC_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
gen3_exit <= 1'd0;
cpllpd <= 1'd0;
qpllpd <= 1'd0;
cpllreset <= 1'd0;
qpllreset <= 1'd0;
txpmareset <= 1'd0;
rxpmareset <= 1'd0;
sysclksel <= (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
pclk_sel <= 1'd0;
gen3 <= 1'd0;
rate_out <= 3'd0;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
endcase
end
end
//---------- PIPE Rate Output --------------------------------------------------
assign RATE_CPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllpd);
assign RATE_QPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllpd);
assign RATE_CPLLRESET = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllreset);
assign RATE_QPLLRESET = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllreset);
assign RATE_TXPMARESET = txpmareset;
assign RATE_RXPMARESET = rxpmareset;
assign RATE_SYSCLKSEL = sysclksel;
//assign RATE_DRP_START = (fsm == FSM_DRP_START) || (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
assign RATE_DRP_START = drp_start;
//assign RATE_DRP_X16X20_MODE = (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_GEN3_DONE) ||
// (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE) ||
// (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE);
assign RATE_DRP_X16X20_MODE = drp_x16x20_mode;
//assign RATE_DRP_X16 = (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_GEN3_DONE) ||
// (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
assign RATE_DRP_X16 = drp_x16;
assign RATE_PCLK_SEL = pclk_sel;
assign RATE_GEN3 = gen3;
assign RATE_RATE_OUT = rate_out;
assign RATE_RESETOVRD_START = (fsm == FSM_RESETOVRD_START);
assign RATE_TXSYNC_START = (fsm == FSM_TXSYNC_START);
assign RATE_DONE = (fsm == FSM_DONE);
assign RATE_RXSYNC_START = (fsm == FSM_RXSYNC_START);
assign RATE_RXSYNC = ((fsm == FSM_RXSYNC_START) || (fsm == FSM_RXSYNC_DONE));
assign RATE_IDLE = (fsm == FSM_IDLE);
assign RATE_FSM = fsm;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21BA_BEHAVIORAL_V
`define SKY130_FD_SC_MS__O21BA_BEHAVIORAL_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o21ba (
X ,
A1 ,
A2 ,
B1_N
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire nor1_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X, B1_N, nor0_out );
buf buf0 (X , nor1_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21BA_BEHAVIORAL_V |
//////////////////////////////////////////////////////////////////////////////////
// d_KES_PE_ELU_sMINodr.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: d_KES_PE_ELU_sMINodr
// File Name: d_KES_PE_ELU_sMINodr.v
//
// Version: v1.1.1-256B_T14
//
// Description:
// - Processing Element: Error Locator Update module, minimum order + 1 (semi-)
// - for binary version of inversion-less Berlekamp-Massey algorithm (iBM.b)
// - for data area
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.1.1
// - minor modification for releasing
//
// * v1.1.0
// - change state machine: divide states
// - insert additional registers
// - improve frequency characteristic
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`include "d_KES_parameters.vh"
`timescale 1ns / 1ps
module d_KES_PE_ELU_sMINodr // error locate update module: minimum order + 1 (semi-)
(
input wire i_clk,
input wire i_RESET_KES,
input wire i_stop_dec,
input wire i_EXECUTE_PE_ELU,
input wire [`D_KES_GF_ORDER-1:0] i_v_2i_Xm1,
input wire [`D_KES_GF_ORDER-1:0] i_k_2i_Xm1,
input wire [`D_KES_GF_ORDER-1:0] i_d_2i,
input wire [`D_KES_GF_ORDER-1:0] i_delta_2im2,
input wire i_condition_2i,
output reg [`D_KES_GF_ORDER-1:0] o_v_2i_X,
output reg o_v_2i_X_deg_chk_bit,
output reg [`D_KES_GF_ORDER-1:0] o_k_2i_X
);
parameter [11:0] D_KES_VALUE_ZERO = 12'b0000_0000_0000;
parameter [11:0] D_KES_VALUE_ONE = 12'b0000_0000_0001;
// FSM parameters
parameter PE_ELU_RST = 2'b01; // reset
parameter PE_ELU_OUT = 2'b10; // output buffer update
// variable declaration
reg [1:0] r_cur_state;
reg [1:0] r_nxt_state;
wire [`D_KES_GF_ORDER-1:0] w_v_2ip2_X_term_A;
wire [`D_KES_GF_ORDER-1:0] w_v_2ip2_X_term_B;
wire [`D_KES_GF_ORDER-1:0] w_v_2ip2_X;
wire [`D_KES_GF_ORDER-1:0] w_k_2ip2_X;
// update current state to next state
always @ (posedge i_clk)
begin
if ((i_RESET_KES) || (i_stop_dec)) begin
r_cur_state <= PE_ELU_RST;
end else begin
r_cur_state <= r_nxt_state;
end
end
// decide next state
always @ ( * )
begin
case (r_cur_state)
PE_ELU_RST: begin
r_nxt_state <= (i_EXECUTE_PE_ELU)? (PE_ELU_OUT):(PE_ELU_RST);
end
PE_ELU_OUT: begin
r_nxt_state <= PE_ELU_RST;
end
default: begin
r_nxt_state <= PE_ELU_RST;
end
endcase
end
// state behaviour
always @ (posedge i_clk)
begin
if ((i_RESET_KES) || (i_stop_dec)) begin // initializing
o_v_2i_X[`D_KES_GF_ORDER-1:0] <= D_KES_VALUE_ZERO[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= 0;
o_k_2i_X[`D_KES_GF_ORDER-1:0] <= D_KES_VALUE_ZERO[`D_KES_GF_ORDER-1:0];
end
else begin
case (r_nxt_state)
PE_ELU_RST: begin // hold original data
o_v_2i_X[`D_KES_GF_ORDER-1:0] <= o_v_2i_X[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= o_v_2i_X_deg_chk_bit;
o_k_2i_X[`D_KES_GF_ORDER-1:0] <= o_k_2i_X[`D_KES_GF_ORDER-1:0];
end
PE_ELU_OUT: begin // output update only
o_v_2i_X[`D_KES_GF_ORDER-1:0] <= w_v_2ip2_X[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= |(w_v_2ip2_X[`D_KES_GF_ORDER-1:0]);
o_k_2i_X[`D_KES_GF_ORDER-1:0] <= w_k_2ip2_X[`D_KES_GF_ORDER-1:0];
end
default: begin
o_v_2i_X[`D_KES_GF_ORDER-1:0] <= o_v_2i_X[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= o_v_2i_X_deg_chk_bit;
o_k_2i_X[`D_KES_GF_ORDER-1:0] <= o_k_2i_X[`D_KES_GF_ORDER-1:0];
end
endcase
end
end
d_parallel_FFM_gate_GF12 d_delta_2im2_FFM_v_2i_X (
.i_poly_form_A (i_delta_2im2[`D_KES_GF_ORDER-1:0]),
.i_poly_form_B (o_v_2i_X[`D_KES_GF_ORDER-1:0]),
.o_poly_form_result(w_v_2ip2_X_term_A[`D_KES_GF_ORDER-1:0]));
d_parallel_FFM_gate_GF12 d_d_2i_FFM_k_2i_Xm1 (
.i_poly_form_A (i_d_2i[`D_KES_GF_ORDER-1:0]),
.i_poly_form_B (i_k_2i_Xm1[`D_KES_GF_ORDER-1:0]),
.o_poly_form_result(w_v_2ip2_X_term_B[`D_KES_GF_ORDER-1:0]));
assign w_v_2ip2_X[`D_KES_GF_ORDER-1:0] = w_v_2ip2_X_term_A[`D_KES_GF_ORDER-1:0] ^ w_v_2ip2_X_term_B[`D_KES_GF_ORDER-1:0];
assign w_k_2ip2_X[`D_KES_GF_ORDER-1:0] = (i_condition_2i)? (i_v_2i_Xm1[`D_KES_GF_ORDER-1:0]):(D_KES_VALUE_ZERO[`D_KES_GF_ORDER-1:0]);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFBBP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__SDFBBP_FUNCTIONAL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dfb_setdom_pg/sky130_fd_sc_hs__u_dfb_setdom_pg.v"
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`celldefine
module sky130_fd_sc_hs__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D, SCD, SCE );
sky130_fd_sc_hs__u_dfb_setdom_pg `UNIT_DELAY u_dfb_setdom_pg0 (buf_Q , SET, RESET, CLK, mux_out, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFBBP_FUNCTIONAL_V |
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 9
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xbar_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [31:0] [63:32]" *)
input wire [63 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8]" *)
input wire [15 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3]" *)
input wire [5 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2]" *)
input wire [3 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4]" *)
input wire [7 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3]" *)
input wire [5 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4]" *)
input wire [7 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [63:0] [127:64]" *)
input wire [127 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [7:0] [15:8]" *)
input wire [15 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1]" *)
input wire [1 : 0] s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2]" *)
output wire [3 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1]" *)
input wire [1 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [31:0] [63:32]" *)
input wire [63 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8]" *)
input wire [15 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3]" *)
input wire [5 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2]" *)
input wire [3 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4]" *)
input wire [7 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3]" *)
input wire [5 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4]" *)
input wire [7 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [63:0] [127:64]" *)
output wire [127 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2]" *)
output wire [3 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1]" *)
input wire [1 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID" *)
output wire [0 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID" *)
output wire [0 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY" *)
input wire [0 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST" *)
output wire [0 : 0] m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID" *)
output wire [0 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY" *)
input wire [0 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID" *)
input wire [0 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID" *)
input wire [0 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY" *)
output wire [0 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID" *)
output wire [0 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID" *)
output wire [0 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY" *)
input wire [0 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID" *)
input wire [0 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST" *)
input wire [0 : 0] m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID" *)
input wire [0 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY" *)
output wire [0 : 0] m_axi_rready;
axi_crossbar_v2_1_9_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(2),
.C_NUM_MASTER_SLOTS(1),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_PROTOCOL(0),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(64'H0000000000000000),
.C_M_AXI_ADDR_WIDTH(32'H0000001d),
.C_S_AXI_BASE_ID(64'H0000000100000000),
.C_S_AXI_THREAD_ID_WIDTH(64'H0000000000000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(32'H00000002),
.C_M_AXI_READ_CONNECTIVITY(32'H00000001),
.C_R_REGISTER(0),
.C_S_AXI_SINGLE_THREAD(64'H0000000000000000),
.C_S_AXI_WRITE_ACCEPTANCE(64'H0000000200000002),
.C_S_AXI_READ_ACCEPTANCE(64'H0000000200000002),
.C_M_AXI_WRITE_ISSUING(32'H00000008),
.C_M_AXI_READ_ISSUING(32'H00000008),
.C_S_AXI_ARB_PRIORITY(64'H0000000000000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(2'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(2'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(2'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(2'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
//bug844
module device(
input clk,
output logic [7:0] Q, out0,
output logic pass, fail
input [7:0] D, in0,in1 );
enum logic [2:0] {IDLE, START, RUN, PASS, FAIL } state, next_state;
logic ready, next_ready;
logic next_pass, next_fail;
always_ff @(posedge clk, negedge rstn)
if (!rstn) begin
state <= IDLE;
/*AUTORESET*/
end
else begin
state <= next_state;
ready <= next_ready;
pass <= next_pass;
fail <= next_fail;
end
always @* begin
if (!ready) begin
/*AUTORESET*/
end
else begin
out0 = sel ? in1 : in0;
end
end
always_comb begin
next_state = state;
/*AUTORESET*/
case (state)
IDLE : begin
// stuff ...
end
/* Other states */
PASS: begin
next_state = IDLE;
// stuff ...
next_pass = 1'b1;
next_ready = 1'b1;
end
FAIL: begin
next_state = IDLE;
// stuff ...
next_fail = 1'b1;
end
endcase
end
always_latch begin
if (!rstn) begin
/*AUTORESET*/
end
else if (clk) begin
Q <= D;
end
end
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module aestest (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
ap_ce,
inptext_V_read,
key_V_read,
ap_return
);
parameter ap_ST_fsm_pp0_stage0 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
input ap_ce;
input [127:0] inptext_V_read;
input [127:0] key_V_read;
output [127:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_pp0_stage0;
wire ap_enable_reg_pp0_iter0;
wire ap_block_pp0_stage0_flag00000000;
reg ap_enable_reg_pp0_iter1;
reg ap_enable_reg_pp0_iter2;
reg ap_enable_reg_pp0_iter3;
reg ap_enable_reg_pp0_iter4;
reg ap_enable_reg_pp0_iter5;
reg ap_enable_reg_pp0_iter6;
reg ap_enable_reg_pp0_iter7;
reg ap_enable_reg_pp0_iter8;
reg ap_enable_reg_pp0_iter9;
reg ap_enable_reg_pp0_iter10;
reg ap_idle_pp0;
reg ap_block_state1_pp0_stage0_iter0;
wire ap_block_state2_pp0_stage0_iter1;
wire ap_block_state3_pp0_stage0_iter2;
wire ap_block_state4_pp0_stage0_iter3;
wire ap_block_state5_pp0_stage0_iter4;
wire ap_block_state6_pp0_stage0_iter5;
wire ap_block_state7_pp0_stage0_iter6;
wire ap_block_state8_pp0_stage0_iter7;
wire ap_block_state9_pp0_stage0_iter8;
wire ap_block_state10_pp0_stage0_iter9;
wire ap_block_state11_pp0_stage0_iter10;
reg ap_block_pp0_stage0_flag00011001;
wire [7:0] sboxes_address0;
reg sboxes_ce0;
wire [7:0] sboxes_q0;
wire [7:0] sboxes_address1;
reg sboxes_ce1;
wire [7:0] sboxes_q1;
wire [7:0] sboxes_address2;
reg sboxes_ce2;
wire [7:0] sboxes_q2;
wire [7:0] sboxes_address3;
reg sboxes_ce3;
wire [7:0] sboxes_q3;
wire [7:0] sboxes_address4;
reg sboxes_ce4;
wire [7:0] sboxes_q4;
wire [7:0] sboxes_address5;
reg sboxes_ce5;
wire [7:0] sboxes_q5;
wire [7:0] sboxes_address6;
reg sboxes_ce6;
wire [7:0] sboxes_q6;
wire [7:0] sboxes_address7;
reg sboxes_ce7;
wire [7:0] sboxes_q7;
wire [7:0] sboxes_address8;
reg sboxes_ce8;
wire [7:0] sboxes_q8;
wire [7:0] sboxes_address9;
reg sboxes_ce9;
wire [7:0] sboxes_q9;
wire [7:0] sboxes_address10;
reg sboxes_ce10;
wire [7:0] sboxes_q10;
wire [7:0] sboxes_address11;
reg sboxes_ce11;
wire [7:0] sboxes_q11;
wire [7:0] sboxes_address12;
reg sboxes_ce12;
wire [7:0] sboxes_q12;
wire [7:0] sboxes_address13;
reg sboxes_ce13;
wire [7:0] sboxes_q13;
wire [7:0] sboxes_address14;
reg sboxes_ce14;
wire [7:0] sboxes_q14;
wire [7:0] sboxes_address15;
reg sboxes_ce15;
wire [7:0] sboxes_q15;
wire [7:0] sboxes_address16;
reg sboxes_ce16;
wire [7:0] sboxes_q16;
wire [7:0] sboxes_address17;
reg sboxes_ce17;
wire [7:0] sboxes_q17;
wire [7:0] sboxes_address18;
reg sboxes_ce18;
wire [7:0] sboxes_q18;
wire [7:0] sboxes_address19;
reg sboxes_ce19;
wire [7:0] sboxes_q19;
wire [7:0] sboxes_address20;
reg sboxes_ce20;
wire [7:0] sboxes_q20;
wire [7:0] sboxes_address21;
reg sboxes_ce21;
wire [7:0] sboxes_q21;
wire [7:0] sboxes_address22;
reg sboxes_ce22;
wire [7:0] sboxes_q22;
wire [7:0] sboxes_address23;
reg sboxes_ce23;
wire [7:0] sboxes_q23;
wire [7:0] sboxes_address24;
reg sboxes_ce24;
wire [7:0] sboxes_q24;
wire [7:0] sboxes_address25;
reg sboxes_ce25;
wire [7:0] sboxes_q25;
wire [7:0] sboxes_address26;
reg sboxes_ce26;
wire [7:0] sboxes_q26;
wire [7:0] sboxes_address27;
reg sboxes_ce27;
wire [7:0] sboxes_q27;
wire [7:0] sboxes_address28;
reg sboxes_ce28;
wire [7:0] sboxes_q28;
wire [7:0] sboxes_address29;
reg sboxes_ce29;
wire [7:0] sboxes_q29;
wire [7:0] sboxes_address30;
reg sboxes_ce30;
wire [7:0] sboxes_q30;
wire [7:0] sboxes_address31;
reg sboxes_ce31;
wire [7:0] sboxes_q31;
wire [7:0] sboxes_address32;
reg sboxes_ce32;
wire [7:0] sboxes_q32;
wire [7:0] sboxes_address33;
reg sboxes_ce33;
wire [7:0] sboxes_q33;
wire [7:0] sboxes_address34;
reg sboxes_ce34;
wire [7:0] sboxes_q34;
wire [7:0] sboxes_address35;
reg sboxes_ce35;
wire [7:0] sboxes_q35;
wire [7:0] sboxes_address36;
reg sboxes_ce36;
wire [7:0] sboxes_q36;
wire [7:0] sboxes_address37;
reg sboxes_ce37;
wire [7:0] sboxes_q37;
wire [7:0] sboxes_address38;
reg sboxes_ce38;
wire [7:0] sboxes_q38;
wire [7:0] sboxes_address39;
reg sboxes_ce39;
wire [7:0] sboxes_q39;
wire [7:0] sboxes_address40;
reg sboxes_ce40;
wire [7:0] sboxes_q40;
wire [7:0] sboxes_address41;
reg sboxes_ce41;
wire [7:0] sboxes_q41;
wire [7:0] sboxes_address42;
reg sboxes_ce42;
wire [7:0] sboxes_q42;
wire [7:0] sboxes_address43;
reg sboxes_ce43;
wire [7:0] sboxes_q43;
wire [7:0] sboxes_address44;
reg sboxes_ce44;
wire [7:0] sboxes_q44;
wire [7:0] sboxes_address45;
reg sboxes_ce45;
wire [7:0] sboxes_q45;
wire [7:0] sboxes_address46;
reg sboxes_ce46;
wire [7:0] sboxes_q46;
wire [7:0] sboxes_address47;
reg sboxes_ce47;
wire [7:0] sboxes_q47;
wire [7:0] sboxes_address48;
reg sboxes_ce48;
wire [7:0] sboxes_q48;
wire [7:0] sboxes_address49;
reg sboxes_ce49;
wire [7:0] sboxes_q49;
wire [7:0] sboxes_address50;
reg sboxes_ce50;
wire [7:0] sboxes_q50;
wire [7:0] sboxes_address51;
reg sboxes_ce51;
wire [7:0] sboxes_q51;
wire [7:0] sboxes_address52;
reg sboxes_ce52;
wire [7:0] sboxes_q52;
wire [7:0] sboxes_address53;
reg sboxes_ce53;
wire [7:0] sboxes_q53;
wire [7:0] sboxes_address54;
reg sboxes_ce54;
wire [7:0] sboxes_q54;
wire [7:0] sboxes_address55;
reg sboxes_ce55;
wire [7:0] sboxes_q55;
wire [7:0] sboxes_address56;
reg sboxes_ce56;
wire [7:0] sboxes_q56;
wire [7:0] sboxes_address57;
reg sboxes_ce57;
wire [7:0] sboxes_q57;
wire [7:0] sboxes_address58;
reg sboxes_ce58;
wire [7:0] sboxes_q58;
wire [7:0] sboxes_address59;
reg sboxes_ce59;
wire [7:0] sboxes_q59;
wire [7:0] sboxes_address60;
reg sboxes_ce60;
wire [7:0] sboxes_q60;
wire [7:0] sboxes_address61;
reg sboxes_ce61;
wire [7:0] sboxes_q61;
wire [7:0] sboxes_address62;
reg sboxes_ce62;
wire [7:0] sboxes_q62;
wire [7:0] sboxes_address63;
reg sboxes_ce63;
wire [7:0] sboxes_q63;
wire [7:0] sboxes_address64;
reg sboxes_ce64;
wire [7:0] sboxes_q64;
wire [7:0] sboxes_address65;
reg sboxes_ce65;
wire [7:0] sboxes_q65;
wire [7:0] sboxes_address66;
reg sboxes_ce66;
wire [7:0] sboxes_q66;
wire [7:0] sboxes_address67;
reg sboxes_ce67;
wire [7:0] sboxes_q67;
wire [7:0] sboxes_address68;
reg sboxes_ce68;
wire [7:0] sboxes_q68;
wire [7:0] sboxes_address69;
reg sboxes_ce69;
wire [7:0] sboxes_q69;
wire [7:0] sboxes_address70;
reg sboxes_ce70;
wire [7:0] sboxes_q70;
wire [7:0] sboxes_address71;
reg sboxes_ce71;
wire [7:0] sboxes_q71;
wire [7:0] sboxes_address72;
reg sboxes_ce72;
wire [7:0] sboxes_q72;
wire [7:0] sboxes_address73;
reg sboxes_ce73;
wire [7:0] sboxes_q73;
wire [7:0] sboxes_address74;
reg sboxes_ce74;
wire [7:0] sboxes_q74;
wire [7:0] sboxes_address75;
reg sboxes_ce75;
wire [7:0] sboxes_q75;
wire [7:0] sboxes_address76;
reg sboxes_ce76;
wire [7:0] sboxes_q76;
wire [7:0] sboxes_address77;
reg sboxes_ce77;
wire [7:0] sboxes_q77;
wire [7:0] sboxes_address78;
reg sboxes_ce78;
wire [7:0] sboxes_q78;
wire [7:0] sboxes_address79;
reg sboxes_ce79;
wire [7:0] sboxes_q79;
wire [7:0] sboxes_address80;
reg sboxes_ce80;
wire [7:0] sboxes_q80;
wire [7:0] sboxes_address81;
reg sboxes_ce81;
wire [7:0] sboxes_q81;
wire [7:0] sboxes_address82;
reg sboxes_ce82;
wire [7:0] sboxes_q82;
wire [7:0] sboxes_address83;
reg sboxes_ce83;
wire [7:0] sboxes_q83;
wire [7:0] sboxes_address84;
reg sboxes_ce84;
wire [7:0] sboxes_q84;
wire [7:0] sboxes_address85;
reg sboxes_ce85;
wire [7:0] sboxes_q85;
wire [7:0] sboxes_address86;
reg sboxes_ce86;
wire [7:0] sboxes_q86;
wire [7:0] sboxes_address87;
reg sboxes_ce87;
wire [7:0] sboxes_q87;
wire [7:0] sboxes_address88;
reg sboxes_ce88;
wire [7:0] sboxes_q88;
wire [7:0] sboxes_address89;
reg sboxes_ce89;
wire [7:0] sboxes_q89;
wire [7:0] sboxes_address90;
reg sboxes_ce90;
wire [7:0] sboxes_q90;
wire [7:0] sboxes_address91;
reg sboxes_ce91;
wire [7:0] sboxes_q91;
wire [7:0] sboxes_address92;
reg sboxes_ce92;
wire [7:0] sboxes_q92;
wire [7:0] sboxes_address93;
reg sboxes_ce93;
wire [7:0] sboxes_q93;
wire [7:0] sboxes_address94;
reg sboxes_ce94;
wire [7:0] sboxes_q94;
wire [7:0] sboxes_address95;
reg sboxes_ce95;
wire [7:0] sboxes_q95;
wire [7:0] sboxes_address96;
reg sboxes_ce96;
wire [7:0] sboxes_q96;
wire [7:0] sboxes_address97;
reg sboxes_ce97;
wire [7:0] sboxes_q97;
wire [7:0] sboxes_address98;
reg sboxes_ce98;
wire [7:0] sboxes_q98;
wire [7:0] sboxes_address99;
reg sboxes_ce99;
wire [7:0] sboxes_q99;
wire [7:0] sboxes_address100;
reg sboxes_ce100;
wire [7:0] sboxes_q100;
wire [7:0] sboxes_address101;
reg sboxes_ce101;
wire [7:0] sboxes_q101;
wire [7:0] sboxes_address102;
reg sboxes_ce102;
wire [7:0] sboxes_q102;
wire [7:0] sboxes_address103;
reg sboxes_ce103;
wire [7:0] sboxes_q103;
wire [7:0] sboxes_address104;
reg sboxes_ce104;
wire [7:0] sboxes_q104;
wire [7:0] sboxes_address105;
reg sboxes_ce105;
wire [7:0] sboxes_q105;
wire [7:0] sboxes_address106;
reg sboxes_ce106;
wire [7:0] sboxes_q106;
wire [7:0] sboxes_address107;
reg sboxes_ce107;
wire [7:0] sboxes_q107;
wire [7:0] sboxes_address108;
reg sboxes_ce108;
wire [7:0] sboxes_q108;
wire [7:0] sboxes_address109;
reg sboxes_ce109;
wire [7:0] sboxes_q109;
wire [7:0] sboxes_address110;
reg sboxes_ce110;
wire [7:0] sboxes_q110;
wire [7:0] sboxes_address111;
reg sboxes_ce111;
wire [7:0] sboxes_q111;
wire [7:0] sboxes_address112;
reg sboxes_ce112;
wire [7:0] sboxes_q112;
wire [7:0] sboxes_address113;
reg sboxes_ce113;
wire [7:0] sboxes_q113;
wire [7:0] sboxes_address114;
reg sboxes_ce114;
wire [7:0] sboxes_q114;
wire [7:0] sboxes_address115;
reg sboxes_ce115;
wire [7:0] sboxes_q115;
wire [7:0] sboxes_address116;
reg sboxes_ce116;
wire [7:0] sboxes_q116;
wire [7:0] sboxes_address117;
reg sboxes_ce117;
wire [7:0] sboxes_q117;
wire [7:0] sboxes_address118;
reg sboxes_ce118;
wire [7:0] sboxes_q118;
wire [7:0] sboxes_address119;
reg sboxes_ce119;
wire [7:0] sboxes_q119;
wire [7:0] sboxes_address120;
reg sboxes_ce120;
wire [7:0] sboxes_q120;
wire [7:0] sboxes_address121;
reg sboxes_ce121;
wire [7:0] sboxes_q121;
wire [7:0] sboxes_address122;
reg sboxes_ce122;
wire [7:0] sboxes_q122;
wire [7:0] sboxes_address123;
reg sboxes_ce123;
wire [7:0] sboxes_q123;
wire [7:0] sboxes_address124;
reg sboxes_ce124;
wire [7:0] sboxes_q124;
wire [7:0] sboxes_address125;
reg sboxes_ce125;
wire [7:0] sboxes_q125;
wire [7:0] sboxes_address126;
reg sboxes_ce126;
wire [7:0] sboxes_q126;
wire [7:0] sboxes_address127;
reg sboxes_ce127;
wire [7:0] sboxes_q127;
wire [7:0] sboxes_address128;
reg sboxes_ce128;
wire [7:0] sboxes_q128;
wire [7:0] sboxes_address129;
reg sboxes_ce129;
wire [7:0] sboxes_q129;
wire [7:0] sboxes_address130;
reg sboxes_ce130;
wire [7:0] sboxes_q130;
wire [7:0] sboxes_address131;
reg sboxes_ce131;
wire [7:0] sboxes_q131;
wire [7:0] sboxes_address132;
reg sboxes_ce132;
wire [7:0] sboxes_q132;
wire [7:0] sboxes_address133;
reg sboxes_ce133;
wire [7:0] sboxes_q133;
wire [7:0] sboxes_address134;
reg sboxes_ce134;
wire [7:0] sboxes_q134;
wire [7:0] sboxes_address135;
reg sboxes_ce135;
wire [7:0] sboxes_q135;
wire [7:0] sboxes_address136;
reg sboxes_ce136;
wire [7:0] sboxes_q136;
wire [7:0] sboxes_address137;
reg sboxes_ce137;
wire [7:0] sboxes_q137;
wire [7:0] sboxes_address138;
reg sboxes_ce138;
wire [7:0] sboxes_q138;
wire [7:0] sboxes_address139;
reg sboxes_ce139;
wire [7:0] sboxes_q139;
wire [7:0] sboxes_address140;
reg sboxes_ce140;
wire [7:0] sboxes_q140;
wire [7:0] sboxes_address141;
reg sboxes_ce141;
wire [7:0] sboxes_q141;
wire [7:0] sboxes_address142;
reg sboxes_ce142;
wire [7:0] sboxes_q142;
wire [7:0] sboxes_address143;
reg sboxes_ce143;
wire [7:0] sboxes_q143;
wire [7:0] sboxes_address144;
reg sboxes_ce144;
wire [7:0] sboxes_q144;
wire [7:0] sboxes_address145;
reg sboxes_ce145;
wire [7:0] sboxes_q145;
wire [7:0] sboxes_address146;
reg sboxes_ce146;
wire [7:0] sboxes_q146;
wire [7:0] sboxes_address147;
reg sboxes_ce147;
wire [7:0] sboxes_q147;
wire [7:0] sboxes_address148;
reg sboxes_ce148;
wire [7:0] sboxes_q148;
wire [7:0] sboxes_address149;
reg sboxes_ce149;
wire [7:0] sboxes_q149;
wire [7:0] sboxes_address150;
reg sboxes_ce150;
wire [7:0] sboxes_q150;
wire [7:0] sboxes_address151;
reg sboxes_ce151;
wire [7:0] sboxes_q151;
wire [7:0] sboxes_address152;
reg sboxes_ce152;
wire [7:0] sboxes_q152;
wire [7:0] sboxes_address153;
reg sboxes_ce153;
wire [7:0] sboxes_q153;
wire [7:0] sboxes_address154;
reg sboxes_ce154;
wire [7:0] sboxes_q154;
wire [7:0] sboxes_address155;
reg sboxes_ce155;
wire [7:0] sboxes_q155;
wire [7:0] sboxes_address156;
reg sboxes_ce156;
wire [7:0] sboxes_q156;
wire [7:0] sboxes_address157;
reg sboxes_ce157;
wire [7:0] sboxes_q157;
wire [7:0] sboxes_address158;
reg sboxes_ce158;
wire [7:0] sboxes_q158;
wire [7:0] sboxes_address159;
reg sboxes_ce159;
wire [7:0] sboxes_q159;
wire [7:0] sboxes_address160;
reg sboxes_ce160;
wire [7:0] sboxes_q160;
wire [7:0] sboxes_address161;
reg sboxes_ce161;
wire [7:0] sboxes_q161;
wire [7:0] sboxes_address162;
reg sboxes_ce162;
wire [7:0] sboxes_q162;
wire [7:0] sboxes_address163;
reg sboxes_ce163;
wire [7:0] sboxes_q163;
wire [7:0] sboxes_address164;
reg sboxes_ce164;
wire [7:0] sboxes_q164;
wire [7:0] sboxes_address165;
reg sboxes_ce165;
wire [7:0] sboxes_q165;
wire [7:0] sboxes_address166;
reg sboxes_ce166;
wire [7:0] sboxes_q166;
wire [7:0] sboxes_address167;
reg sboxes_ce167;
wire [7:0] sboxes_q167;
wire [7:0] sboxes_address168;
reg sboxes_ce168;
wire [7:0] sboxes_q168;
wire [7:0] sboxes_address169;
reg sboxes_ce169;
wire [7:0] sboxes_q169;
wire [7:0] sboxes_address170;
reg sboxes_ce170;
wire [7:0] sboxes_q170;
wire [7:0] sboxes_address171;
reg sboxes_ce171;
wire [7:0] sboxes_q171;
wire [7:0] sboxes_address172;
reg sboxes_ce172;
wire [7:0] sboxes_q172;
wire [7:0] sboxes_address173;
reg sboxes_ce173;
wire [7:0] sboxes_q173;
wire [7:0] sboxes_address174;
reg sboxes_ce174;
wire [7:0] sboxes_q174;
wire [7:0] sboxes_address175;
reg sboxes_ce175;
wire [7:0] sboxes_q175;
wire [7:0] sboxes_address176;
reg sboxes_ce176;
wire [7:0] sboxes_q176;
wire [7:0] sboxes_address177;
reg sboxes_ce177;
wire [7:0] sboxes_q177;
wire [7:0] sboxes_address178;
reg sboxes_ce178;
wire [7:0] sboxes_q178;
wire [7:0] sboxes_address179;
reg sboxes_ce179;
wire [7:0] sboxes_q179;
wire [7:0] sboxes_address180;
reg sboxes_ce180;
wire [7:0] sboxes_q180;
wire [7:0] sboxes_address181;
reg sboxes_ce181;
wire [7:0] sboxes_q181;
wire [7:0] sboxes_address182;
reg sboxes_ce182;
wire [7:0] sboxes_q182;
wire [7:0] sboxes_address183;
reg sboxes_ce183;
wire [7:0] sboxes_q183;
wire [7:0] sboxes_address184;
reg sboxes_ce184;
wire [7:0] sboxes_q184;
wire [7:0] sboxes_address185;
reg sboxes_ce185;
wire [7:0] sboxes_q185;
wire [7:0] sboxes_address186;
reg sboxes_ce186;
wire [7:0] sboxes_q186;
wire [7:0] sboxes_address187;
reg sboxes_ce187;
wire [7:0] sboxes_q187;
wire [7:0] sboxes_address188;
reg sboxes_ce188;
wire [7:0] sboxes_q188;
wire [7:0] sboxes_address189;
reg sboxes_ce189;
wire [7:0] sboxes_q189;
wire [7:0] sboxes_address190;
reg sboxes_ce190;
wire [7:0] sboxes_q190;
wire [7:0] sboxes_address191;
reg sboxes_ce191;
wire [7:0] sboxes_q191;
wire [7:0] sboxes_address192;
reg sboxes_ce192;
wire [7:0] sboxes_q192;
wire [7:0] sboxes_address193;
reg sboxes_ce193;
wire [7:0] sboxes_q193;
wire [7:0] sboxes_address194;
reg sboxes_ce194;
wire [7:0] sboxes_q194;
wire [7:0] sboxes_address195;
reg sboxes_ce195;
wire [7:0] sboxes_q195;
wire [7:0] sboxes_address196;
reg sboxes_ce196;
wire [7:0] sboxes_q196;
wire [7:0] sboxes_address197;
reg sboxes_ce197;
wire [7:0] sboxes_q197;
wire [7:0] sboxes_address198;
reg sboxes_ce198;
wire [7:0] sboxes_q198;
wire [7:0] sboxes_address199;
reg sboxes_ce199;
wire [7:0] sboxes_q199;
wire [7:0] p_Result_1_fu_2331_p4;
reg [7:0] p_Result_1_reg_12421;
wire [7:0] p_Result_1_1_fu_2351_p4;
reg [7:0] p_Result_1_1_reg_12426;
wire [7:0] p_Result_1_2_fu_2371_p4;
reg [7:0] p_Result_1_2_reg_12431;
wire [7:0] p_Result_1_3_fu_2391_p4;
reg [7:0] p_Result_1_3_reg_12436;
wire [7:0] p_Result_1_4_fu_2411_p4;
reg [7:0] p_Result_1_4_reg_12441;
reg [7:0] ap_reg_pp0_iter1_p_Result_1_4_reg_12441;
wire [7:0] p_Result_1_5_fu_2431_p4;
reg [7:0] p_Result_1_5_reg_12447;
reg [7:0] ap_reg_pp0_iter1_p_Result_1_5_reg_12447;
wire [7:0] p_Result_1_6_fu_2451_p4;
reg [7:0] p_Result_1_6_reg_12453;
reg [7:0] ap_reg_pp0_iter1_p_Result_1_6_reg_12453;
wire [7:0] p_Result_1_7_fu_2471_p4;
reg [7:0] p_Result_1_7_reg_12459;
reg [7:0] ap_reg_pp0_iter1_p_Result_1_7_reg_12459;
wire [7:0] p_Result_1_8_fu_2491_p4;
reg [7:0] p_Result_1_8_reg_12465;
wire [7:0] p_Result_1_9_fu_2511_p4;
reg [7:0] p_Result_1_9_reg_12470;
wire [7:0] p_Result_1_s_fu_2531_p4;
reg [7:0] p_Result_1_s_reg_12475;
wire [7:0] p_Result_1_10_fu_2551_p4;
reg [7:0] p_Result_1_10_reg_12480;
wire [7:0] p_Result_1_11_fu_2571_p4;
reg [7:0] p_Result_1_11_reg_12485;
reg [7:0] ap_reg_pp0_iter1_p_Result_1_11_reg_12485;
reg [7:0] ap_reg_pp0_iter2_p_Result_1_11_reg_12485;
reg [7:0] ap_reg_pp0_iter3_p_Result_1_11_reg_12485;
wire [7:0] p_Result_1_12_fu_2591_p4;
reg [7:0] p_Result_1_12_reg_12492;
reg [7:0] ap_reg_pp0_iter1_p_Result_1_12_reg_12492;
reg [7:0] ap_reg_pp0_iter2_p_Result_1_12_reg_12492;
reg [7:0] ap_reg_pp0_iter3_p_Result_1_12_reg_12492;
wire [7:0] p_Result_1_13_fu_2611_p4;
reg [7:0] p_Result_1_13_reg_12499;
reg [7:0] ap_reg_pp0_iter1_p_Result_1_13_reg_12499;
reg [7:0] ap_reg_pp0_iter2_p_Result_1_13_reg_12499;
reg [7:0] ap_reg_pp0_iter3_p_Result_1_13_reg_12499;
wire [7:0] tmp_100_fu_2625_p1;
reg [7:0] tmp_100_reg_12506;
reg [7:0] ap_reg_pp0_iter1_tmp_100_reg_12506;
reg [7:0] ap_reg_pp0_iter2_tmp_100_reg_12506;
reg [7:0] ap_reg_pp0_iter3_tmp_100_reg_12506;
wire [7:0] tmp_65_fu_3422_p2;
reg [7:0] tmp_65_reg_12613;
wire [7:0] tmp_66_fu_3428_p2;
reg [7:0] tmp_66_reg_12618;
wire [7:0] tmp_67_fu_3433_p2;
reg [7:0] tmp_67_reg_12623;
wire [7:0] tmp_68_fu_3438_p2;
reg [7:0] tmp_68_reg_12628;
wire [7:0] tmp_73_fu_3463_p2;
reg [7:0] tmp_73_reg_12633;
reg [7:0] ap_reg_pp0_iter2_tmp_73_reg_12633;
wire [7:0] tmp_74_fu_3468_p2;
reg [7:0] tmp_74_reg_12639;
reg [7:0] ap_reg_pp0_iter2_tmp_74_reg_12639;
wire [7:0] tmp_75_fu_3473_p2;
reg [7:0] tmp_75_reg_12645;
reg [7:0] ap_reg_pp0_iter2_tmp_75_reg_12645;
wire [7:0] tmp_76_fu_3478_p2;
reg [7:0] tmp_76_reg_12651;
reg [7:0] ap_reg_pp0_iter2_tmp_76_reg_12651;
wire [7:0] tmp_65_1_fu_4465_p2;
reg [7:0] tmp_65_1_reg_12757;
wire [7:0] tmp_66_1_fu_4470_p2;
reg [7:0] tmp_66_1_reg_12762;
wire [7:0] tmp_67_1_fu_4475_p2;
reg [7:0] tmp_67_1_reg_12767;
wire [7:0] tmp_68_1_fu_4480_p2;
reg [7:0] tmp_68_1_reg_12772;
wire [7:0] tmp_69_1_fu_4485_p2;
reg [7:0] tmp_69_1_reg_12777;
reg [7:0] ap_reg_pp0_iter3_tmp_69_1_reg_12777;
wire [7:0] tmp_70_1_fu_4490_p2;
reg [7:0] tmp_70_1_reg_12783;
reg [7:0] ap_reg_pp0_iter3_tmp_70_1_reg_12783;
wire [7:0] tmp_71_1_fu_4495_p2;
reg [7:0] tmp_71_1_reg_12789;
reg [7:0] ap_reg_pp0_iter3_tmp_71_1_reg_12789;
wire [7:0] tmp_72_1_fu_4500_p2;
reg [7:0] tmp_72_1_reg_12795;
reg [7:0] ap_reg_pp0_iter3_tmp_72_1_reg_12795;
wire [7:0] tmp_77_1_fu_4505_p2;
reg [7:0] tmp_77_1_reg_12801;
wire [7:0] tmp_78_1_fu_4510_p2;
reg [7:0] tmp_78_1_reg_12806;
wire [7:0] tmp_79_1_fu_4515_p2;
reg [7:0] tmp_79_1_reg_12811;
wire [7:0] tmp_80_1_fu_4520_p2;
reg [7:0] tmp_80_1_reg_12816;
wire [7:0] tmp_65_2_fu_5506_p2;
reg [7:0] tmp_65_2_reg_12921;
wire [7:0] tmp_66_2_fu_5512_p2;
reg [7:0] tmp_66_2_reg_12926;
wire [7:0] tmp_67_2_fu_5517_p2;
reg [7:0] tmp_67_2_reg_12931;
wire [7:0] tmp_68_2_fu_5522_p2;
reg [7:0] tmp_68_2_reg_12936;
wire [7:0] tmp_73_2_fu_5527_p2;
reg [7:0] tmp_73_2_reg_12941;
reg [7:0] ap_reg_pp0_iter4_tmp_73_2_reg_12941;
wire [7:0] tmp_74_2_fu_5532_p2;
reg [7:0] tmp_74_2_reg_12947;
reg [7:0] ap_reg_pp0_iter4_tmp_74_2_reg_12947;
wire [7:0] tmp_75_2_fu_5537_p2;
reg [7:0] tmp_75_2_reg_12953;
reg [7:0] ap_reg_pp0_iter4_tmp_75_2_reg_12953;
wire [7:0] tmp_76_2_fu_5542_p2;
reg [7:0] tmp_76_2_reg_12959;
reg [7:0] ap_reg_pp0_iter4_tmp_76_2_reg_12959;
wire [7:0] tmp_65_3_fu_6549_p2;
reg [7:0] tmp_65_3_reg_13065;
wire [7:0] tmp_66_3_fu_6554_p2;
reg [7:0] tmp_66_3_reg_13070;
wire [7:0] tmp_67_3_fu_6559_p2;
reg [7:0] tmp_67_3_reg_13075;
wire [7:0] tmp_68_3_fu_6564_p2;
reg [7:0] tmp_68_3_reg_13080;
wire [7:0] tmp_69_3_fu_6569_p2;
reg [7:0] tmp_69_3_reg_13085;
reg [7:0] ap_reg_pp0_iter5_tmp_69_3_reg_13085;
wire [7:0] tmp_70_3_fu_6574_p2;
reg [7:0] tmp_70_3_reg_13091;
reg [7:0] ap_reg_pp0_iter5_tmp_70_3_reg_13091;
wire [7:0] tmp_71_3_fu_6579_p2;
reg [7:0] tmp_71_3_reg_13097;
reg [7:0] ap_reg_pp0_iter5_tmp_71_3_reg_13097;
wire [7:0] tmp_72_3_fu_6584_p2;
reg [7:0] tmp_72_3_reg_13103;
reg [7:0] ap_reg_pp0_iter5_tmp_72_3_reg_13103;
wire [7:0] tmp_77_3_fu_6589_p2;
reg [7:0] tmp_77_3_reg_13109;
reg [7:0] ap_reg_pp0_iter5_tmp_77_3_reg_13109;
reg [7:0] ap_reg_pp0_iter6_tmp_77_3_reg_13109;
reg [7:0] ap_reg_pp0_iter7_tmp_77_3_reg_13109;
wire [7:0] tmp_78_3_fu_6594_p2;
reg [7:0] tmp_78_3_reg_13116;
reg [7:0] ap_reg_pp0_iter5_tmp_78_3_reg_13116;
reg [7:0] ap_reg_pp0_iter6_tmp_78_3_reg_13116;
reg [7:0] ap_reg_pp0_iter7_tmp_78_3_reg_13116;
wire [7:0] tmp_79_3_fu_6599_p2;
reg [7:0] tmp_79_3_reg_13123;
reg [7:0] ap_reg_pp0_iter5_tmp_79_3_reg_13123;
reg [7:0] ap_reg_pp0_iter6_tmp_79_3_reg_13123;
reg [7:0] ap_reg_pp0_iter7_tmp_79_3_reg_13123;
wire [7:0] tmp_80_3_fu_6604_p2;
reg [7:0] tmp_80_3_reg_13130;
reg [7:0] ap_reg_pp0_iter5_tmp_80_3_reg_13130;
reg [7:0] ap_reg_pp0_iter6_tmp_80_3_reg_13130;
reg [7:0] ap_reg_pp0_iter7_tmp_80_3_reg_13130;
wire [7:0] tmp_65_4_fu_7590_p2;
reg [7:0] tmp_65_4_reg_13237;
wire [7:0] tmp_66_4_fu_7596_p2;
reg [7:0] tmp_66_4_reg_13242;
wire [7:0] tmp_67_4_fu_7601_p2;
reg [7:0] tmp_67_4_reg_13247;
wire [7:0] tmp_68_4_fu_7606_p2;
reg [7:0] tmp_68_4_reg_13252;
wire [7:0] tmp_73_4_fu_7611_p2;
reg [7:0] tmp_73_4_reg_13257;
reg [7:0] ap_reg_pp0_iter6_tmp_73_4_reg_13257;
wire [7:0] tmp_74_4_fu_7616_p2;
reg [7:0] tmp_74_4_reg_13263;
reg [7:0] ap_reg_pp0_iter6_tmp_74_4_reg_13263;
wire [7:0] tmp_75_4_fu_7621_p2;
reg [7:0] tmp_75_4_reg_13269;
reg [7:0] ap_reg_pp0_iter6_tmp_75_4_reg_13269;
wire [7:0] tmp_76_4_fu_7626_p2;
reg [7:0] tmp_76_4_reg_13275;
reg [7:0] ap_reg_pp0_iter6_tmp_76_4_reg_13275;
wire [7:0] tmp_65_5_fu_8633_p2;
reg [7:0] tmp_65_5_reg_13381;
wire [7:0] tmp_66_5_fu_8638_p2;
reg [7:0] tmp_66_5_reg_13386;
wire [7:0] tmp_67_5_fu_8643_p2;
reg [7:0] tmp_67_5_reg_13391;
wire [7:0] tmp_68_5_fu_8648_p2;
reg [7:0] tmp_68_5_reg_13396;
wire [7:0] tmp_69_5_fu_8653_p2;
reg [7:0] tmp_69_5_reg_13401;
reg [7:0] ap_reg_pp0_iter7_tmp_69_5_reg_13401;
wire [7:0] tmp_70_5_fu_8658_p2;
reg [7:0] tmp_70_5_reg_13407;
reg [7:0] ap_reg_pp0_iter7_tmp_70_5_reg_13407;
wire [7:0] tmp_71_5_fu_8663_p2;
reg [7:0] tmp_71_5_reg_13413;
reg [7:0] ap_reg_pp0_iter7_tmp_71_5_reg_13413;
wire [7:0] tmp_72_5_fu_8668_p2;
reg [7:0] tmp_72_5_reg_13419;
reg [7:0] ap_reg_pp0_iter7_tmp_72_5_reg_13419;
wire [7:0] tmp_77_5_fu_8673_p2;
reg [7:0] tmp_77_5_reg_13425;
wire [7:0] tmp_78_5_fu_8678_p2;
reg [7:0] tmp_78_5_reg_13430;
wire [7:0] tmp_79_5_fu_8683_p2;
reg [7:0] tmp_79_5_reg_13435;
wire [7:0] tmp_80_5_fu_8688_p2;
reg [7:0] tmp_80_5_reg_13440;
wire [7:0] tmp_65_6_fu_9674_p2;
reg [7:0] tmp_65_6_reg_13545;
wire [7:0] tmp_66_6_fu_9680_p2;
reg [7:0] tmp_66_6_reg_13550;
wire [7:0] tmp_67_6_fu_9685_p2;
reg [7:0] tmp_67_6_reg_13555;
wire [7:0] tmp_68_6_fu_9690_p2;
reg [7:0] tmp_68_6_reg_13560;
wire [7:0] tmp_73_6_fu_9695_p2;
reg [7:0] tmp_73_6_reg_13565;
reg [7:0] ap_reg_pp0_iter8_tmp_73_6_reg_13565;
wire [7:0] tmp_74_6_fu_9700_p2;
reg [7:0] tmp_74_6_reg_13571;
reg [7:0] ap_reg_pp0_iter8_tmp_74_6_reg_13571;
wire [7:0] tmp_75_6_fu_9705_p2;
reg [7:0] tmp_75_6_reg_13577;
reg [7:0] ap_reg_pp0_iter8_tmp_75_6_reg_13577;
wire [7:0] tmp_76_6_fu_9710_p2;
reg [7:0] tmp_76_6_reg_13583;
reg [7:0] ap_reg_pp0_iter8_tmp_76_6_reg_13583;
wire [7:0] tmp_65_7_fu_10717_p2;
reg [7:0] tmp_65_7_reg_13689;
wire [7:0] tmp_66_7_fu_10722_p2;
reg [7:0] tmp_66_7_reg_13694;
wire [7:0] tmp_67_7_fu_10727_p2;
reg [7:0] tmp_67_7_reg_13699;
wire [7:0] tmp_68_7_fu_10732_p2;
reg [7:0] tmp_68_7_reg_13704;
wire [7:0] tmp_69_7_fu_10737_p2;
reg [7:0] tmp_69_7_reg_13709;
reg [7:0] ap_reg_pp0_iter9_tmp_69_7_reg_13709;
wire [7:0] tmp_70_7_fu_10742_p2;
reg [7:0] tmp_70_7_reg_13715;
reg [7:0] ap_reg_pp0_iter9_tmp_70_7_reg_13715;
wire [7:0] tmp_71_7_fu_10747_p2;
reg [7:0] tmp_71_7_reg_13721;
reg [7:0] ap_reg_pp0_iter9_tmp_71_7_reg_13721;
wire [7:0] tmp_72_7_fu_10752_p2;
reg [7:0] tmp_72_7_reg_13727;
reg [7:0] ap_reg_pp0_iter9_tmp_72_7_reg_13727;
wire [7:0] tmp_77_7_fu_10757_p2;
reg [7:0] tmp_77_7_reg_13733;
reg [7:0] ap_reg_pp0_iter9_tmp_77_7_reg_13733;
wire [7:0] tmp_78_7_fu_10762_p2;
reg [7:0] tmp_78_7_reg_13739;
reg [7:0] ap_reg_pp0_iter9_tmp_78_7_reg_13739;
wire [7:0] tmp_79_7_fu_10767_p2;
reg [7:0] tmp_79_7_reg_13745;
reg [7:0] ap_reg_pp0_iter9_tmp_79_7_reg_13745;
wire [7:0] tmp_80_7_fu_10772_p2;
reg [7:0] tmp_80_7_reg_13751;
reg [7:0] ap_reg_pp0_iter9_tmp_80_7_reg_13751;
wire [7:0] tmp_65_8_fu_11758_p2;
reg [7:0] tmp_65_8_reg_13857;
wire [7:0] tmp_66_8_fu_11764_p2;
reg [7:0] tmp_66_8_reg_13862;
wire [7:0] tmp_67_8_fu_11769_p2;
reg [7:0] tmp_67_8_reg_13867;
wire [7:0] tmp_68_8_fu_11774_p2;
reg [7:0] tmp_68_8_reg_13872;
wire [7:0] tmp_73_8_fu_11779_p2;
reg [7:0] tmp_73_8_reg_13877;
wire [7:0] tmp_74_8_fu_11784_p2;
reg [7:0] tmp_74_8_reg_13882;
wire [7:0] tmp_75_8_fu_11789_p2;
reg [7:0] tmp_75_8_reg_13887;
wire [7:0] tmp_76_8_fu_11794_p2;
reg [7:0] tmp_76_8_reg_13892;
reg ap_block_pp0_stage0_flag00011011;
wire [63:0] tmp_35_fu_2725_p1;
wire [63:0] tmp_35_0_1_fu_2730_p1;
wire [63:0] tmp_35_0_2_fu_2735_p1;
wire [63:0] tmp_35_0_3_fu_2740_p1;
wire [63:0] tmp_35_0_4_fu_2745_p1;
wire [63:0] tmp_35_0_5_fu_2750_p1;
wire [63:0] tmp_35_0_6_fu_2755_p1;
wire [63:0] tmp_35_0_7_fu_2760_p1;
wire [63:0] tmp_35_0_8_fu_2765_p1;
wire [63:0] tmp_35_0_9_fu_2770_p1;
wire [63:0] tmp_35_0_s_fu_2775_p1;
wire [63:0] tmp_35_0_10_fu_2780_p1;
wire [63:0] tmp_35_0_11_fu_2785_p1;
wire [63:0] tmp_35_0_12_fu_2790_p1;
wire [63:0] tmp_35_0_13_fu_2795_p1;
wire [63:0] tmp_35_0_14_fu_2800_p1;
wire [63:0] tmp_60_fu_2805_p1;
wire [63:0] tmp_61_fu_2810_p1;
wire [63:0] tmp_62_fu_2815_p1;
wire [63:0] tmp_63_fu_2820_p1;
wire [63:0] tmp_35_1_fu_3767_p1;
wire [63:0] tmp_35_1_1_fu_3772_p1;
wire [63:0] tmp_35_1_2_fu_3777_p1;
wire [63:0] tmp_35_1_3_fu_3782_p1;
wire [63:0] tmp_35_1_4_fu_3787_p1;
wire [63:0] tmp_35_1_5_fu_3792_p1;
wire [63:0] tmp_35_1_6_fu_3797_p1;
wire [63:0] tmp_35_1_7_fu_3802_p1;
wire [63:0] tmp_35_1_8_fu_3807_p1;
wire [63:0] tmp_35_1_9_fu_3812_p1;
wire [63:0] tmp_35_1_s_fu_3817_p1;
wire [63:0] tmp_35_1_10_fu_3822_p1;
wire [63:0] tmp_35_1_11_fu_3827_p1;
wire [63:0] tmp_35_1_12_fu_3832_p1;
wire [63:0] tmp_35_1_13_fu_3837_p1;
wire [63:0] tmp_35_1_14_fu_3842_p1;
wire [63:0] tmp_60_1_fu_3847_p1;
wire [63:0] tmp_61_1_fu_3852_p1;
wire [63:0] tmp_62_1_fu_3857_p1;
wire [63:0] tmp_63_1_fu_3862_p1;
wire [63:0] tmp_35_2_fu_4809_p1;
wire [63:0] tmp_35_2_1_fu_4814_p1;
wire [63:0] tmp_35_2_2_fu_4819_p1;
wire [63:0] tmp_35_2_3_fu_4824_p1;
wire [63:0] tmp_35_2_4_fu_4829_p1;
wire [63:0] tmp_35_2_5_fu_4834_p1;
wire [63:0] tmp_35_2_6_fu_4839_p1;
wire [63:0] tmp_35_2_7_fu_4844_p1;
wire [63:0] tmp_35_2_8_fu_4849_p1;
wire [63:0] tmp_35_2_9_fu_4854_p1;
wire [63:0] tmp_35_2_s_fu_4859_p1;
wire [63:0] tmp_35_2_10_fu_4864_p1;
wire [63:0] tmp_35_2_11_fu_4869_p1;
wire [63:0] tmp_35_2_12_fu_4874_p1;
wire [63:0] tmp_35_2_13_fu_4879_p1;
wire [63:0] tmp_35_2_14_fu_4884_p1;
wire [63:0] tmp_60_2_fu_4889_p1;
wire [63:0] tmp_61_2_fu_4894_p1;
wire [63:0] tmp_62_2_fu_4899_p1;
wire [63:0] tmp_63_2_fu_4904_p1;
wire [63:0] tmp_35_3_fu_5851_p1;
wire [63:0] tmp_35_3_1_fu_5856_p1;
wire [63:0] tmp_35_3_2_fu_5861_p1;
wire [63:0] tmp_35_3_3_fu_5866_p1;
wire [63:0] tmp_35_3_4_fu_5871_p1;
wire [63:0] tmp_35_3_5_fu_5876_p1;
wire [63:0] tmp_35_3_6_fu_5881_p1;
wire [63:0] tmp_35_3_7_fu_5886_p1;
wire [63:0] tmp_35_3_8_fu_5891_p1;
wire [63:0] tmp_35_3_9_fu_5896_p1;
wire [63:0] tmp_35_3_s_fu_5901_p1;
wire [63:0] tmp_35_3_10_fu_5906_p1;
wire [63:0] tmp_35_3_11_fu_5911_p1;
wire [63:0] tmp_35_3_12_fu_5916_p1;
wire [63:0] tmp_35_3_13_fu_5921_p1;
wire [63:0] tmp_35_3_14_fu_5926_p1;
wire [63:0] tmp_60_3_fu_5931_p1;
wire [63:0] tmp_61_3_fu_5936_p1;
wire [63:0] tmp_62_3_fu_5941_p1;
wire [63:0] tmp_63_3_fu_5946_p1;
wire [63:0] tmp_35_4_fu_6893_p1;
wire [63:0] tmp_35_4_1_fu_6898_p1;
wire [63:0] tmp_35_4_2_fu_6903_p1;
wire [63:0] tmp_35_4_3_fu_6908_p1;
wire [63:0] tmp_35_4_4_fu_6913_p1;
wire [63:0] tmp_35_4_5_fu_6918_p1;
wire [63:0] tmp_35_4_6_fu_6923_p1;
wire [63:0] tmp_35_4_7_fu_6928_p1;
wire [63:0] tmp_35_4_8_fu_6933_p1;
wire [63:0] tmp_35_4_9_fu_6938_p1;
wire [63:0] tmp_35_4_s_fu_6943_p1;
wire [63:0] tmp_35_4_10_fu_6948_p1;
wire [63:0] tmp_35_4_11_fu_6953_p1;
wire [63:0] tmp_35_4_12_fu_6958_p1;
wire [63:0] tmp_35_4_13_fu_6963_p1;
wire [63:0] tmp_35_4_14_fu_6968_p1;
wire [63:0] tmp_60_4_fu_6973_p1;
wire [63:0] tmp_61_4_fu_6978_p1;
wire [63:0] tmp_62_4_fu_6983_p1;
wire [63:0] tmp_63_4_fu_6988_p1;
wire [63:0] tmp_35_5_fu_7935_p1;
wire [63:0] tmp_35_5_1_fu_7940_p1;
wire [63:0] tmp_35_5_2_fu_7945_p1;
wire [63:0] tmp_35_5_3_fu_7950_p1;
wire [63:0] tmp_35_5_4_fu_7955_p1;
wire [63:0] tmp_35_5_5_fu_7960_p1;
wire [63:0] tmp_35_5_6_fu_7965_p1;
wire [63:0] tmp_35_5_7_fu_7970_p1;
wire [63:0] tmp_35_5_8_fu_7975_p1;
wire [63:0] tmp_35_5_9_fu_7980_p1;
wire [63:0] tmp_35_5_s_fu_7985_p1;
wire [63:0] tmp_35_5_10_fu_7990_p1;
wire [63:0] tmp_35_5_11_fu_7995_p1;
wire [63:0] tmp_35_5_12_fu_8000_p1;
wire [63:0] tmp_35_5_13_fu_8005_p1;
wire [63:0] tmp_35_5_14_fu_8010_p1;
wire [63:0] tmp_60_5_fu_8015_p1;
wire [63:0] tmp_61_5_fu_8020_p1;
wire [63:0] tmp_62_5_fu_8025_p1;
wire [63:0] tmp_63_5_fu_8030_p1;
wire [63:0] tmp_35_6_fu_8977_p1;
wire [63:0] tmp_35_6_1_fu_8982_p1;
wire [63:0] tmp_35_6_2_fu_8987_p1;
wire [63:0] tmp_35_6_3_fu_8992_p1;
wire [63:0] tmp_35_6_4_fu_8997_p1;
wire [63:0] tmp_35_6_5_fu_9002_p1;
wire [63:0] tmp_35_6_6_fu_9007_p1;
wire [63:0] tmp_35_6_7_fu_9012_p1;
wire [63:0] tmp_35_6_8_fu_9017_p1;
wire [63:0] tmp_35_6_9_fu_9022_p1;
wire [63:0] tmp_35_6_s_fu_9027_p1;
wire [63:0] tmp_35_6_10_fu_9032_p1;
wire [63:0] tmp_35_6_11_fu_9037_p1;
wire [63:0] tmp_35_6_12_fu_9042_p1;
wire [63:0] tmp_35_6_13_fu_9047_p1;
wire [63:0] tmp_35_6_14_fu_9052_p1;
wire [63:0] tmp_60_6_fu_9057_p1;
wire [63:0] tmp_61_6_fu_9062_p1;
wire [63:0] tmp_62_6_fu_9067_p1;
wire [63:0] tmp_63_6_fu_9072_p1;
wire [63:0] tmp_35_7_fu_10019_p1;
wire [63:0] tmp_35_7_1_fu_10024_p1;
wire [63:0] tmp_35_7_2_fu_10029_p1;
wire [63:0] tmp_35_7_3_fu_10034_p1;
wire [63:0] tmp_35_7_4_fu_10039_p1;
wire [63:0] tmp_35_7_5_fu_10044_p1;
wire [63:0] tmp_35_7_6_fu_10049_p1;
wire [63:0] tmp_35_7_7_fu_10054_p1;
wire [63:0] tmp_35_7_8_fu_10059_p1;
wire [63:0] tmp_35_7_9_fu_10064_p1;
wire [63:0] tmp_35_7_s_fu_10069_p1;
wire [63:0] tmp_35_7_10_fu_10074_p1;
wire [63:0] tmp_35_7_11_fu_10079_p1;
wire [63:0] tmp_35_7_12_fu_10084_p1;
wire [63:0] tmp_35_7_13_fu_10089_p1;
wire [63:0] tmp_35_7_14_fu_10094_p1;
wire [63:0] tmp_60_7_fu_10099_p1;
wire [63:0] tmp_61_7_fu_10104_p1;
wire [63:0] tmp_62_7_fu_10109_p1;
wire [63:0] tmp_63_7_fu_10114_p1;
wire [63:0] tmp_35_8_fu_11061_p1;
wire [63:0] tmp_35_8_1_fu_11066_p1;
wire [63:0] tmp_35_8_2_fu_11071_p1;
wire [63:0] tmp_35_8_3_fu_11076_p1;
wire [63:0] tmp_35_8_4_fu_11081_p1;
wire [63:0] tmp_35_8_5_fu_11086_p1;
wire [63:0] tmp_35_8_6_fu_11091_p1;
wire [63:0] tmp_35_8_7_fu_11096_p1;
wire [63:0] tmp_35_8_8_fu_11101_p1;
wire [63:0] tmp_35_8_9_fu_11106_p1;
wire [63:0] tmp_35_8_s_fu_11111_p1;
wire [63:0] tmp_35_8_10_fu_11116_p1;
wire [63:0] tmp_35_8_11_fu_11121_p1;
wire [63:0] tmp_35_8_12_fu_11126_p1;
wire [63:0] tmp_35_8_13_fu_11131_p1;
wire [63:0] tmp_35_8_14_fu_11136_p1;
wire [63:0] tmp_60_8_fu_11141_p1;
wire [63:0] tmp_61_8_fu_11146_p1;
wire [63:0] tmp_62_8_fu_11151_p1;
wire [63:0] tmp_63_8_fu_11156_p1;
wire [63:0] tmp_33_fu_12103_p1;
wire [63:0] tmp_33_1_fu_12108_p1;
wire [63:0] tmp_33_2_fu_12113_p1;
wire [63:0] tmp_33_3_fu_12118_p1;
wire [63:0] tmp_33_4_fu_12123_p1;
wire [63:0] tmp_33_5_fu_12128_p1;
wire [63:0] tmp_33_6_fu_12133_p1;
wire [63:0] tmp_33_7_fu_12138_p1;
wire [63:0] tmp_33_8_fu_12143_p1;
wire [63:0] tmp_33_9_fu_12148_p1;
wire [63:0] tmp_33_s_fu_12153_p1;
wire [63:0] tmp_33_10_fu_12158_p1;
wire [63:0] tmp_33_11_fu_12163_p1;
wire [63:0] tmp_33_12_fu_12168_p1;
wire [63:0] tmp_33_13_fu_12173_p1;
wire [63:0] tmp_33_14_fu_12178_p1;
wire [63:0] tmp_s_fu_12183_p1;
wire [63:0] tmp_1_fu_12188_p1;
wire [63:0] tmp_2_fu_12193_p1;
wire [63:0] tmp_3_fu_12198_p1;
wire [7:0] p_Result_s_fu_2321_p4;
wire [7:0] p_Result_s_39_fu_2341_p4;
wire [7:0] p_Result_2_fu_2361_p4;
wire [7:0] p_Result_3_fu_2381_p4;
wire [7:0] p_Result_4_fu_2401_p4;
wire [7:0] p_Result_5_fu_2421_p4;
wire [7:0] p_Result_6_fu_2441_p4;
wire [7:0] p_Result_7_fu_2461_p4;
wire [7:0] p_Result_8_fu_2481_p4;
wire [7:0] p_Result_9_fu_2501_p4;
wire [7:0] p_Result_10_fu_2521_p4;
wire [7:0] p_Result_11_fu_2541_p4;
wire [7:0] p_Result_12_fu_2561_p4;
wire [7:0] p_Result_13_fu_2581_p4;
wire [7:0] p_Result_14_fu_2601_p4;
wire [7:0] tmp_99_fu_2621_p1;
wire [7:0] tmp_10_fu_2629_p2;
wire [7:0] tmp_10_1_fu_2635_p2;
wire [7:0] tmp_10_2_fu_2641_p2;
wire [7:0] tmp_10_3_fu_2647_p2;
wire [7:0] tmp_10_4_fu_2653_p2;
wire [7:0] tmp_10_5_fu_2659_p2;
wire [7:0] tmp_10_6_fu_2665_p2;
wire [7:0] tmp_10_7_fu_2671_p2;
wire [7:0] tmp_10_8_fu_2677_p2;
wire [7:0] tmp_10_9_fu_2683_p2;
wire [7:0] tmp_10_s_fu_2689_p2;
wire [7:0] tmp_10_10_fu_2695_p2;
wire [7:0] tmp_10_11_fu_2701_p2;
wire [7:0] tmp_10_12_fu_2707_p2;
wire [7:0] tmp_10_13_fu_2713_p2;
wire [7:0] tmp_10_14_fu_2719_p2;
wire [7:0] x_assign_fu_2825_p2;
wire [7:0] tmp_47_fu_2831_p2;
wire [7:0] tmp_101_fu_2843_p2;
wire [0:0] tmp_102_fu_2849_p3;
wire [7:0] rv_1_fu_2857_p2;
wire [7:0] x_assign_1_fu_2871_p2;
wire [7:0] tmp_103_fu_2877_p2;
wire [0:0] tmp_104_fu_2883_p3;
wire [7:0] rv_4_fu_2891_p2;
wire [7:0] x_assign_2_fu_2905_p2;
wire [7:0] tmp_105_fu_2911_p2;
wire [0:0] tmp_106_fu_2917_p3;
wire [7:0] rv_7_fu_2925_p2;
wire [7:0] x_assign_3_fu_2939_p2;
wire [7:0] tmp_107_fu_2945_p2;
wire [0:0] tmp_108_fu_2951_p3;
wire [7:0] rv_s_fu_2959_p2;
wire [7:0] x_assign_0_1_fu_2973_p2;
wire [7:0] tmp_47_0_1_fu_2979_p2;
wire [7:0] tmp_109_fu_2991_p2;
wire [0:0] tmp_110_fu_2997_p3;
wire [7:0] rv_1_0_1_fu_3005_p2;
wire [7:0] x_assign_1_0_1_fu_3019_p2;
wire [7:0] tmp_111_fu_3025_p2;
wire [0:0] tmp_112_fu_3031_p3;
wire [7:0] rv_4_0_1_fu_3039_p2;
wire [7:0] x_assign_2_0_1_fu_3053_p2;
wire [7:0] tmp_113_fu_3059_p2;
wire [0:0] tmp_114_fu_3065_p3;
wire [7:0] rv_7_0_1_fu_3073_p2;
wire [7:0] x_assign_3_0_1_fu_3087_p2;
wire [7:0] tmp_115_fu_3093_p2;
wire [0:0] tmp_116_fu_3099_p3;
wire [7:0] rv_10_0_1_fu_3107_p2;
wire [7:0] x_assign_0_2_fu_3121_p2;
wire [7:0] tmp_47_0_2_fu_3127_p2;
wire [7:0] tmp_117_fu_3139_p2;
wire [0:0] tmp_118_fu_3145_p3;
wire [7:0] rv_1_0_2_fu_3153_p2;
wire [7:0] x_assign_1_0_2_fu_3167_p2;
wire [7:0] tmp_119_fu_3173_p2;
wire [0:0] tmp_120_fu_3179_p3;
wire [7:0] rv_4_0_2_fu_3187_p2;
wire [7:0] x_assign_2_0_2_fu_3201_p2;
wire [7:0] tmp_121_fu_3207_p2;
wire [0:0] tmp_122_fu_3213_p3;
wire [7:0] rv_7_0_2_fu_3221_p2;
wire [7:0] x_assign_3_0_2_fu_3235_p2;
wire [7:0] tmp_123_fu_3241_p2;
wire [0:0] tmp_124_fu_3247_p3;
wire [7:0] rv_10_0_2_fu_3255_p2;
wire [7:0] x_assign_0_3_fu_3269_p2;
wire [7:0] tmp_47_0_3_fu_3275_p2;
wire [7:0] tmp_125_fu_3287_p2;
wire [0:0] tmp_126_fu_3293_p3;
wire [7:0] rv_1_0_3_fu_3301_p2;
wire [7:0] x_assign_1_0_3_fu_3315_p2;
wire [7:0] tmp_127_fu_3321_p2;
wire [0:0] tmp_128_fu_3327_p3;
wire [7:0] rv_4_0_3_fu_3335_p2;
wire [7:0] x_assign_2_0_3_fu_3349_p2;
wire [7:0] tmp_129_fu_3355_p2;
wire [0:0] tmp_130_fu_3361_p3;
wire [7:0] rv_7_0_3_fu_3369_p2;
wire [7:0] x_assign_3_0_3_fu_3383_p2;
wire [7:0] tmp_131_fu_3389_p2;
wire [0:0] tmp_132_fu_3395_p3;
wire [7:0] rv_10_0_3_fu_3403_p2;
wire [7:0] tmp_fu_3417_p2;
wire [7:0] tmp_69_fu_3443_p2;
wire [7:0] tmp_70_fu_3448_p2;
wire [7:0] tmp_71_fu_3453_p2;
wire [7:0] tmp_72_fu_3458_p2;
wire [7:0] rv_2_fu_2863_p3;
wire [7:0] e_fu_2837_p2;
wire [7:0] tmp2_fu_3509_p2;
wire [7:0] tmp1_fu_3503_p2;
wire [7:0] rv_5_fu_2897_p3;
wire [7:0] tmp4_fu_3527_p2;
wire [7:0] tmp3_fu_3521_p2;
wire [7:0] rv_8_fu_2931_p3;
wire [7:0] tmp6_fu_3545_p2;
wire [7:0] tmp5_fu_3539_p2;
wire [7:0] tmp7_fu_3557_p2;
wire [7:0] rv_3_fu_2965_p3;
wire [7:0] rv_2_0_1_fu_3011_p3;
wire [7:0] e_0_1_fu_2985_p2;
wire [7:0] tmp9_fu_3575_p2;
wire [7:0] tmp8_fu_3569_p2;
wire [7:0] rv_5_0_1_fu_3045_p3;
wire [7:0] tmp11_fu_3593_p2;
wire [7:0] tmp10_fu_3587_p2;
wire [7:0] rv_8_0_1_fu_3079_p3;
wire [7:0] tmp13_fu_3611_p2;
wire [7:0] tmp12_fu_3605_p2;
wire [7:0] tmp14_fu_3623_p2;
wire [7:0] rv_11_0_1_fu_3113_p3;
wire [7:0] rv_2_0_2_fu_3159_p3;
wire [7:0] e_0_2_fu_3133_p2;
wire [7:0] tmp16_fu_3641_p2;
wire [7:0] tmp15_fu_3635_p2;
wire [7:0] rv_5_0_2_fu_3193_p3;
wire [7:0] tmp18_fu_3659_p2;
wire [7:0] tmp17_fu_3653_p2;
wire [7:0] rv_8_0_2_fu_3227_p3;
wire [7:0] tmp20_fu_3677_p2;
wire [7:0] tmp19_fu_3671_p2;
wire [7:0] tmp21_fu_3689_p2;
wire [7:0] rv_11_0_2_fu_3261_p3;
wire [7:0] rv_2_0_3_fu_3307_p3;
wire [7:0] e_0_3_fu_3281_p2;
wire [7:0] tmp_77_fu_3483_p2;
wire [7:0] tmp23_fu_3707_p2;
wire [7:0] tmp22_fu_3701_p2;
wire [7:0] rv_5_0_3_fu_3341_p3;
wire [7:0] tmp_78_fu_3488_p2;
wire [7:0] tmp25_fu_3725_p2;
wire [7:0] tmp24_fu_3719_p2;
wire [7:0] rv_8_0_3_fu_3375_p3;
wire [7:0] tmp_79_fu_3493_p2;
wire [7:0] tmp27_fu_3743_p2;
wire [7:0] tmp26_fu_3737_p2;
wire [7:0] tmp_80_fu_3498_p2;
wire [7:0] tmp28_fu_3755_p2;
wire [7:0] rv_11_0_3_fu_3409_p3;
wire [7:0] tmp_85_fu_3515_p2;
wire [7:0] tmp_85_0_1_fu_3533_p2;
wire [7:0] tmp_85_0_2_fu_3551_p2;
wire [7:0] tmp_85_0_3_fu_3563_p2;
wire [7:0] tmp_85_0_4_fu_3581_p2;
wire [7:0] tmp_85_0_5_fu_3599_p2;
wire [7:0] tmp_85_0_6_fu_3617_p2;
wire [7:0] tmp_85_0_7_fu_3629_p2;
wire [7:0] tmp_85_0_8_fu_3647_p2;
wire [7:0] tmp_85_0_9_fu_3665_p2;
wire [7:0] tmp_85_0_s_fu_3683_p2;
wire [7:0] tmp_85_0_10_fu_3695_p2;
wire [7:0] tmp_85_0_11_fu_3713_p2;
wire [7:0] tmp_85_0_12_fu_3731_p2;
wire [7:0] tmp_85_0_13_fu_3749_p2;
wire [7:0] tmp_85_0_14_fu_3761_p2;
wire [7:0] x_assign_s_fu_3867_p2;
wire [7:0] tmp_47_1_fu_3873_p2;
wire [7:0] tmp_133_fu_3885_p2;
wire [0:0] tmp_134_fu_3891_p3;
wire [7:0] rv_1_1_fu_3899_p2;
wire [7:0] x_assign_1_1_fu_3913_p2;
wire [7:0] tmp_135_fu_3919_p2;
wire [0:0] tmp_136_fu_3925_p3;
wire [7:0] rv_4_1_fu_3933_p2;
wire [7:0] x_assign_2_1_fu_3947_p2;
wire [7:0] tmp_137_fu_3953_p2;
wire [0:0] tmp_138_fu_3959_p3;
wire [7:0] rv_7_1_fu_3967_p2;
wire [7:0] x_assign_3_1_fu_3981_p2;
wire [7:0] tmp_139_fu_3987_p2;
wire [0:0] tmp_140_fu_3993_p3;
wire [7:0] rv_10_1_fu_4001_p2;
wire [7:0] x_assign_171_1_fu_4015_p2;
wire [7:0] tmp_47_1_1_fu_4021_p2;
wire [7:0] tmp_141_fu_4033_p2;
wire [0:0] tmp_142_fu_4039_p3;
wire [7:0] rv_1_1_1_fu_4047_p2;
wire [7:0] x_assign_1_1_1_fu_4061_p2;
wire [7:0] tmp_143_fu_4067_p2;
wire [0:0] tmp_144_fu_4073_p3;
wire [7:0] rv_4_1_1_fu_4081_p2;
wire [7:0] x_assign_2_1_1_fu_4095_p2;
wire [7:0] tmp_145_fu_4101_p2;
wire [0:0] tmp_146_fu_4107_p3;
wire [7:0] rv_7_1_1_fu_4115_p2;
wire [7:0] x_assign_3_1_1_fu_4129_p2;
wire [7:0] tmp_147_fu_4135_p2;
wire [0:0] tmp_148_fu_4141_p3;
wire [7:0] rv_10_1_1_fu_4149_p2;
wire [7:0] x_assign_171_2_fu_4163_p2;
wire [7:0] tmp_47_1_2_fu_4169_p2;
wire [7:0] tmp_149_fu_4181_p2;
wire [0:0] tmp_150_fu_4187_p3;
wire [7:0] rv_1_1_2_fu_4195_p2;
wire [7:0] x_assign_1_1_2_fu_4209_p2;
wire [7:0] tmp_151_fu_4215_p2;
wire [0:0] tmp_152_fu_4221_p3;
wire [7:0] rv_4_1_2_fu_4229_p2;
wire [7:0] x_assign_2_1_2_fu_4243_p2;
wire [7:0] tmp_153_fu_4249_p2;
wire [0:0] tmp_154_fu_4255_p3;
wire [7:0] rv_7_1_2_fu_4263_p2;
wire [7:0] x_assign_3_1_2_fu_4277_p2;
wire [7:0] tmp_155_fu_4283_p2;
wire [0:0] tmp_156_fu_4289_p3;
wire [7:0] rv_10_1_2_fu_4297_p2;
wire [7:0] x_assign_171_3_fu_4311_p2;
wire [7:0] tmp_47_1_3_fu_4317_p2;
wire [7:0] tmp_157_fu_4329_p2;
wire [0:0] tmp_158_fu_4335_p3;
wire [7:0] rv_1_1_3_fu_4343_p2;
wire [7:0] x_assign_1_1_3_fu_4357_p2;
wire [7:0] tmp_159_fu_4363_p2;
wire [0:0] tmp_160_fu_4369_p3;
wire [7:0] rv_4_1_3_fu_4377_p2;
wire [7:0] x_assign_2_1_3_fu_4391_p2;
wire [7:0] tmp_161_fu_4397_p2;
wire [0:0] tmp_162_fu_4403_p3;
wire [7:0] rv_7_1_3_fu_4411_p2;
wire [7:0] x_assign_3_1_3_fu_4425_p2;
wire [7:0] tmp_163_fu_4431_p2;
wire [0:0] tmp_164_fu_4437_p3;
wire [7:0] rv_10_1_3_fu_4445_p2;
wire [7:0] tmp_64_1_fu_4459_p2;
wire [7:0] rv_2_1_fu_3905_p3;
wire [7:0] e_1_fu_3879_p2;
wire [7:0] tmp30_fu_4531_p2;
wire [7:0] tmp29_fu_4525_p2;
wire [7:0] rv_5_1_fu_3939_p3;
wire [7:0] tmp32_fu_4549_p2;
wire [7:0] tmp31_fu_4543_p2;
wire [7:0] rv_8_1_fu_3973_p3;
wire [7:0] tmp34_fu_4567_p2;
wire [7:0] tmp33_fu_4561_p2;
wire [7:0] tmp35_fu_4579_p2;
wire [7:0] rv_11_1_fu_4007_p3;
wire [7:0] rv_2_1_1_fu_4053_p3;
wire [7:0] e_1_1_fu_4027_p2;
wire [7:0] tmp37_fu_4597_p2;
wire [7:0] tmp36_fu_4591_p2;
wire [7:0] rv_5_1_1_fu_4087_p3;
wire [7:0] tmp39_fu_4615_p2;
wire [7:0] tmp38_fu_4609_p2;
wire [7:0] rv_8_1_1_fu_4121_p3;
wire [7:0] tmp41_fu_4633_p2;
wire [7:0] tmp40_fu_4627_p2;
wire [7:0] tmp42_fu_4645_p2;
wire [7:0] rv_11_1_1_fu_4155_p3;
wire [7:0] rv_2_1_2_fu_4201_p3;
wire [7:0] tmp45_fu_4663_p2;
wire [7:0] e_1_2_fu_4175_p2;
wire [7:0] tmp44_fu_4668_p2;
wire [7:0] tmp43_fu_4657_p2;
wire [7:0] tmp48_fu_4686_p2;
wire [7:0] rv_5_1_2_fu_4235_p3;
wire [7:0] tmp47_fu_4691_p2;
wire [7:0] tmp46_fu_4680_p2;
wire [7:0] tmp51_fu_4709_p2;
wire [7:0] rv_8_1_2_fu_4269_p3;
wire [7:0] tmp50_fu_4714_p2;
wire [7:0] tmp49_fu_4703_p2;
wire [7:0] rv_11_1_2_fu_4303_p3;
wire [7:0] tmp53_fu_4732_p2;
wire [7:0] tmp52_fu_4726_p2;
wire [7:0] rv_2_1_3_fu_4349_p3;
wire [7:0] e_1_3_fu_4323_p2;
wire [7:0] tmp55_fu_4749_p2;
wire [7:0] tmp54_fu_4743_p2;
wire [7:0] rv_5_1_3_fu_4383_p3;
wire [7:0] tmp57_fu_4767_p2;
wire [7:0] tmp56_fu_4761_p2;
wire [7:0] rv_8_1_3_fu_4417_p3;
wire [7:0] tmp59_fu_4785_p2;
wire [7:0] tmp58_fu_4779_p2;
wire [7:0] tmp60_fu_4797_p2;
wire [7:0] rv_11_1_3_fu_4451_p3;
wire [7:0] tmp_85_1_fu_4537_p2;
wire [7:0] tmp_85_1_1_fu_4555_p2;
wire [7:0] tmp_85_1_2_fu_4573_p2;
wire [7:0] tmp_85_1_3_fu_4585_p2;
wire [7:0] tmp_85_1_4_fu_4603_p2;
wire [7:0] tmp_85_1_5_fu_4621_p2;
wire [7:0] tmp_85_1_6_fu_4639_p2;
wire [7:0] tmp_85_1_7_fu_4651_p2;
wire [7:0] tmp_85_1_8_fu_4674_p2;
wire [7:0] tmp_85_1_9_fu_4697_p2;
wire [7:0] tmp_85_1_s_fu_4720_p2;
wire [7:0] tmp_85_1_10_fu_4737_p2;
wire [7:0] tmp_85_1_11_fu_4755_p2;
wire [7:0] tmp_85_1_12_fu_4773_p2;
wire [7:0] tmp_85_1_13_fu_4791_p2;
wire [7:0] tmp_85_1_14_fu_4803_p2;
wire [7:0] x_assign_9_fu_4909_p2;
wire [7:0] tmp_47_2_fu_4915_p2;
wire [7:0] tmp_165_fu_4927_p2;
wire [0:0] tmp_166_fu_4933_p3;
wire [7:0] rv_1_2_fu_4941_p2;
wire [7:0] x_assign_1_2_fu_4955_p2;
wire [7:0] tmp_167_fu_4961_p2;
wire [0:0] tmp_168_fu_4967_p3;
wire [7:0] rv_4_2_fu_4975_p2;
wire [7:0] x_assign_2_2_fu_4989_p2;
wire [7:0] tmp_169_fu_4995_p2;
wire [0:0] tmp_170_fu_5001_p3;
wire [7:0] rv_7_2_fu_5009_p2;
wire [7:0] x_assign_3_2_fu_5023_p2;
wire [7:0] tmp_171_fu_5029_p2;
wire [0:0] tmp_172_fu_5035_p3;
wire [7:0] rv_10_2_fu_5043_p2;
wire [7:0] x_assign_273_1_fu_5057_p2;
wire [7:0] tmp_47_2_1_fu_5063_p2;
wire [7:0] tmp_173_fu_5075_p2;
wire [0:0] tmp_174_fu_5081_p3;
wire [7:0] rv_1_2_1_fu_5089_p2;
wire [7:0] x_assign_1_2_1_fu_5103_p2;
wire [7:0] tmp_175_fu_5109_p2;
wire [0:0] tmp_176_fu_5115_p3;
wire [7:0] rv_4_2_1_fu_5123_p2;
wire [7:0] x_assign_2_2_1_fu_5137_p2;
wire [7:0] tmp_177_fu_5143_p2;
wire [0:0] tmp_178_fu_5149_p3;
wire [7:0] rv_7_2_1_fu_5157_p2;
wire [7:0] x_assign_3_2_1_fu_5171_p2;
wire [7:0] tmp_179_fu_5177_p2;
wire [0:0] tmp_180_fu_5183_p3;
wire [7:0] rv_10_2_1_fu_5191_p2;
wire [7:0] x_assign_273_2_fu_5205_p2;
wire [7:0] tmp_47_2_2_fu_5211_p2;
wire [7:0] tmp_181_fu_5223_p2;
wire [0:0] tmp_182_fu_5229_p3;
wire [7:0] rv_1_2_2_fu_5237_p2;
wire [7:0] x_assign_1_2_2_fu_5251_p2;
wire [7:0] tmp_183_fu_5257_p2;
wire [0:0] tmp_184_fu_5263_p3;
wire [7:0] rv_4_2_2_fu_5271_p2;
wire [7:0] x_assign_2_2_2_fu_5285_p2;
wire [7:0] tmp_185_fu_5291_p2;
wire [0:0] tmp_186_fu_5297_p3;
wire [7:0] rv_7_2_2_fu_5305_p2;
wire [7:0] x_assign_3_2_2_fu_5319_p2;
wire [7:0] tmp_187_fu_5325_p2;
wire [0:0] tmp_188_fu_5331_p3;
wire [7:0] rv_10_2_2_fu_5339_p2;
wire [7:0] x_assign_273_3_fu_5353_p2;
wire [7:0] tmp_47_2_3_fu_5359_p2;
wire [7:0] tmp_189_fu_5371_p2;
wire [0:0] tmp_190_fu_5377_p3;
wire [7:0] rv_1_2_3_fu_5385_p2;
wire [7:0] x_assign_1_2_3_fu_5399_p2;
wire [7:0] tmp_191_fu_5405_p2;
wire [0:0] tmp_192_fu_5411_p3;
wire [7:0] rv_4_2_3_fu_5419_p2;
wire [7:0] x_assign_2_2_3_fu_5433_p2;
wire [7:0] tmp_193_fu_5439_p2;
wire [0:0] tmp_194_fu_5445_p3;
wire [7:0] rv_7_2_3_fu_5453_p2;
wire [7:0] x_assign_3_2_3_fu_5467_p2;
wire [7:0] tmp_195_fu_5473_p2;
wire [0:0] tmp_196_fu_5479_p3;
wire [7:0] rv_10_2_3_fu_5487_p2;
wire [7:0] tmp61_fu_5501_p2;
wire [7:0] rv_2_2_fu_4947_p3;
wire [7:0] e_2_fu_4921_p2;
wire [7:0] tmp63_fu_5573_p2;
wire [7:0] tmp62_fu_5567_p2;
wire [7:0] rv_5_2_fu_4981_p3;
wire [7:0] tmp65_fu_5591_p2;
wire [7:0] tmp64_fu_5585_p2;
wire [7:0] rv_8_2_fu_5015_p3;
wire [7:0] tmp67_fu_5609_p2;
wire [7:0] tmp66_fu_5603_p2;
wire [7:0] tmp68_fu_5621_p2;
wire [7:0] rv_11_2_fu_5049_p3;
wire [7:0] rv_2_2_1_fu_5095_p3;
wire [7:0] tmp71_fu_5639_p2;
wire [7:0] e_2_1_fu_5069_p2;
wire [7:0] tmp70_fu_5644_p2;
wire [7:0] tmp69_fu_5633_p2;
wire [7:0] tmp74_fu_5662_p2;
wire [7:0] rv_5_2_1_fu_5129_p3;
wire [7:0] tmp73_fu_5667_p2;
wire [7:0] tmp72_fu_5656_p2;
wire [7:0] tmp77_fu_5685_p2;
wire [7:0] rv_8_2_1_fu_5163_p3;
wire [7:0] tmp76_fu_5690_p2;
wire [7:0] tmp75_fu_5679_p2;
wire [7:0] rv_11_2_1_fu_5197_p3;
wire [7:0] tmp79_fu_5708_p2;
wire [7:0] tmp78_fu_5702_p2;
wire [7:0] rv_2_2_2_fu_5243_p3;
wire [7:0] e_2_2_fu_5217_p2;
wire [7:0] tmp81_fu_5725_p2;
wire [7:0] tmp80_fu_5719_p2;
wire [7:0] rv_5_2_2_fu_5277_p3;
wire [7:0] tmp83_fu_5743_p2;
wire [7:0] tmp82_fu_5737_p2;
wire [7:0] rv_8_2_2_fu_5311_p3;
wire [7:0] tmp85_fu_5761_p2;
wire [7:0] tmp84_fu_5755_p2;
wire [7:0] tmp86_fu_5773_p2;
wire [7:0] rv_11_2_2_fu_5345_p3;
wire [7:0] rv_2_2_3_fu_5391_p3;
wire [7:0] e_2_3_fu_5365_p2;
wire [7:0] tmp_77_2_fu_5547_p2;
wire [7:0] tmp88_fu_5791_p2;
wire [7:0] tmp87_fu_5785_p2;
wire [7:0] rv_5_2_3_fu_5425_p3;
wire [7:0] tmp_78_2_fu_5552_p2;
wire [7:0] tmp90_fu_5809_p2;
wire [7:0] tmp89_fu_5803_p2;
wire [7:0] rv_8_2_3_fu_5459_p3;
wire [7:0] tmp_79_2_fu_5557_p2;
wire [7:0] tmp92_fu_5827_p2;
wire [7:0] tmp91_fu_5821_p2;
wire [7:0] tmp_80_2_fu_5562_p2;
wire [7:0] tmp93_fu_5839_p2;
wire [7:0] rv_11_2_3_fu_5493_p3;
wire [7:0] tmp_85_2_fu_5579_p2;
wire [7:0] tmp_85_2_1_fu_5597_p2;
wire [7:0] tmp_85_2_2_fu_5615_p2;
wire [7:0] tmp_85_2_3_fu_5627_p2;
wire [7:0] tmp_85_2_4_fu_5650_p2;
wire [7:0] tmp_85_2_5_fu_5673_p2;
wire [7:0] tmp_85_2_6_fu_5696_p2;
wire [7:0] tmp_85_2_7_fu_5713_p2;
wire [7:0] tmp_85_2_8_fu_5731_p2;
wire [7:0] tmp_85_2_9_fu_5749_p2;
wire [7:0] tmp_85_2_s_fu_5767_p2;
wire [7:0] tmp_85_2_10_fu_5779_p2;
wire [7:0] tmp_85_2_11_fu_5797_p2;
wire [7:0] tmp_85_2_12_fu_5815_p2;
wire [7:0] tmp_85_2_13_fu_5833_p2;
wire [7:0] tmp_85_2_14_fu_5845_p2;
wire [7:0] x_assign_10_fu_5951_p2;
wire [7:0] tmp_47_3_fu_5957_p2;
wire [7:0] tmp_197_fu_5969_p2;
wire [0:0] tmp_198_fu_5975_p3;
wire [7:0] rv_1_3_fu_5983_p2;
wire [7:0] x_assign_1_3_fu_5997_p2;
wire [7:0] tmp_199_fu_6003_p2;
wire [0:0] tmp_200_fu_6009_p3;
wire [7:0] rv_4_3_fu_6017_p2;
wire [7:0] x_assign_2_3_fu_6031_p2;
wire [7:0] tmp_201_fu_6037_p2;
wire [0:0] tmp_202_fu_6043_p3;
wire [7:0] rv_7_3_fu_6051_p2;
wire [7:0] x_assign_3_3_fu_6065_p2;
wire [7:0] tmp_203_fu_6071_p2;
wire [0:0] tmp_204_fu_6077_p3;
wire [7:0] rv_10_3_fu_6085_p2;
wire [7:0] x_assign_375_1_fu_6099_p2;
wire [7:0] tmp_47_3_1_fu_6105_p2;
wire [7:0] tmp_205_fu_6117_p2;
wire [0:0] tmp_206_fu_6123_p3;
wire [7:0] rv_1_3_1_fu_6131_p2;
wire [7:0] x_assign_1_3_1_fu_6145_p2;
wire [7:0] tmp_207_fu_6151_p2;
wire [0:0] tmp_208_fu_6157_p3;
wire [7:0] rv_4_3_1_fu_6165_p2;
wire [7:0] x_assign_2_3_1_fu_6179_p2;
wire [7:0] tmp_209_fu_6185_p2;
wire [0:0] tmp_210_fu_6191_p3;
wire [7:0] rv_7_3_1_fu_6199_p2;
wire [7:0] x_assign_3_3_1_fu_6213_p2;
wire [7:0] tmp_211_fu_6219_p2;
wire [0:0] tmp_212_fu_6225_p3;
wire [7:0] rv_10_3_1_fu_6233_p2;
wire [7:0] x_assign_375_2_fu_6247_p2;
wire [7:0] tmp_47_3_2_fu_6253_p2;
wire [7:0] tmp_213_fu_6265_p2;
wire [0:0] tmp_214_fu_6271_p3;
wire [7:0] rv_1_3_2_fu_6279_p2;
wire [7:0] x_assign_1_3_2_fu_6293_p2;
wire [7:0] tmp_215_fu_6299_p2;
wire [0:0] tmp_216_fu_6305_p3;
wire [7:0] rv_4_3_2_fu_6313_p2;
wire [7:0] x_assign_2_3_2_fu_6327_p2;
wire [7:0] tmp_217_fu_6333_p2;
wire [0:0] tmp_218_fu_6339_p3;
wire [7:0] rv_7_3_2_fu_6347_p2;
wire [7:0] x_assign_3_3_2_fu_6361_p2;
wire [7:0] tmp_219_fu_6367_p2;
wire [0:0] tmp_220_fu_6373_p3;
wire [7:0] rv_10_3_2_fu_6381_p2;
wire [7:0] x_assign_375_3_fu_6395_p2;
wire [7:0] tmp_47_3_3_fu_6401_p2;
wire [7:0] tmp_221_fu_6413_p2;
wire [0:0] tmp_222_fu_6419_p3;
wire [7:0] rv_1_3_3_fu_6427_p2;
wire [7:0] x_assign_1_3_3_fu_6441_p2;
wire [7:0] tmp_223_fu_6447_p2;
wire [0:0] tmp_224_fu_6453_p3;
wire [7:0] rv_4_3_3_fu_6461_p2;
wire [7:0] x_assign_2_3_3_fu_6475_p2;
wire [7:0] tmp_225_fu_6481_p2;
wire [0:0] tmp_226_fu_6487_p3;
wire [7:0] rv_7_3_3_fu_6495_p2;
wire [7:0] x_assign_3_3_3_fu_6509_p2;
wire [7:0] tmp_227_fu_6515_p2;
wire [0:0] tmp_228_fu_6521_p3;
wire [7:0] rv_10_3_3_fu_6529_p2;
wire [7:0] tmp_64_3_fu_6543_p2;
wire [7:0] rv_2_3_fu_5989_p3;
wire [7:0] e_3_fu_5963_p2;
wire [7:0] tmp95_fu_6615_p2;
wire [7:0] tmp94_fu_6609_p2;
wire [7:0] rv_5_3_fu_6023_p3;
wire [7:0] tmp97_fu_6633_p2;
wire [7:0] tmp96_fu_6627_p2;
wire [7:0] rv_8_3_fu_6057_p3;
wire [7:0] tmp99_fu_6651_p2;
wire [7:0] tmp98_fu_6645_p2;
wire [7:0] tmp100_fu_6663_p2;
wire [7:0] rv_11_3_fu_6091_p3;
wire [7:0] rv_2_3_1_fu_6137_p3;
wire [7:0] e_3_1_fu_6111_p2;
wire [7:0] tmp102_fu_6681_p2;
wire [7:0] tmp101_fu_6675_p2;
wire [7:0] rv_5_3_1_fu_6171_p3;
wire [7:0] tmp104_fu_6699_p2;
wire [7:0] tmp103_fu_6693_p2;
wire [7:0] rv_8_3_1_fu_6205_p3;
wire [7:0] tmp106_fu_6717_p2;
wire [7:0] tmp105_fu_6711_p2;
wire [7:0] tmp107_fu_6729_p2;
wire [7:0] rv_11_3_1_fu_6239_p3;
wire [7:0] rv_2_3_2_fu_6285_p3;
wire [7:0] tmp110_fu_6747_p2;
wire [7:0] e_3_2_fu_6259_p2;
wire [7:0] tmp109_fu_6752_p2;
wire [7:0] tmp108_fu_6741_p2;
wire [7:0] tmp113_fu_6770_p2;
wire [7:0] rv_5_3_2_fu_6319_p3;
wire [7:0] tmp112_fu_6775_p2;
wire [7:0] tmp111_fu_6764_p2;
wire [7:0] tmp116_fu_6793_p2;
wire [7:0] rv_8_3_2_fu_6353_p3;
wire [7:0] tmp115_fu_6798_p2;
wire [7:0] tmp114_fu_6787_p2;
wire [7:0] rv_11_3_2_fu_6387_p3;
wire [7:0] tmp118_fu_6816_p2;
wire [7:0] tmp117_fu_6810_p2;
wire [7:0] rv_2_3_3_fu_6433_p3;
wire [7:0] e_3_3_fu_6407_p2;
wire [7:0] tmp120_fu_6833_p2;
wire [7:0] tmp119_fu_6827_p2;
wire [7:0] rv_5_3_3_fu_6467_p3;
wire [7:0] tmp122_fu_6851_p2;
wire [7:0] tmp121_fu_6845_p2;
wire [7:0] rv_8_3_3_fu_6501_p3;
wire [7:0] tmp124_fu_6869_p2;
wire [7:0] tmp123_fu_6863_p2;
wire [7:0] tmp125_fu_6881_p2;
wire [7:0] rv_11_3_3_fu_6535_p3;
wire [7:0] tmp_85_3_fu_6621_p2;
wire [7:0] tmp_85_3_1_fu_6639_p2;
wire [7:0] tmp_85_3_2_fu_6657_p2;
wire [7:0] tmp_85_3_3_fu_6669_p2;
wire [7:0] tmp_85_3_4_fu_6687_p2;
wire [7:0] tmp_85_3_5_fu_6705_p2;
wire [7:0] tmp_85_3_6_fu_6723_p2;
wire [7:0] tmp_85_3_7_fu_6735_p2;
wire [7:0] tmp_85_3_8_fu_6758_p2;
wire [7:0] tmp_85_3_9_fu_6781_p2;
wire [7:0] tmp_85_3_s_fu_6804_p2;
wire [7:0] tmp_85_3_10_fu_6821_p2;
wire [7:0] tmp_85_3_11_fu_6839_p2;
wire [7:0] tmp_85_3_12_fu_6857_p2;
wire [7:0] tmp_85_3_13_fu_6875_p2;
wire [7:0] tmp_85_3_14_fu_6887_p2;
wire [7:0] x_assign_4_fu_6993_p2;
wire [7:0] tmp_47_4_fu_6999_p2;
wire [7:0] tmp_229_fu_7011_p2;
wire [0:0] tmp_230_fu_7017_p3;
wire [7:0] rv_1_4_fu_7025_p2;
wire [7:0] x_assign_1_4_fu_7039_p2;
wire [7:0] tmp_231_fu_7045_p2;
wire [0:0] tmp_232_fu_7051_p3;
wire [7:0] rv_4_4_fu_7059_p2;
wire [7:0] x_assign_2_4_fu_7073_p2;
wire [7:0] tmp_233_fu_7079_p2;
wire [0:0] tmp_234_fu_7085_p3;
wire [7:0] rv_7_4_fu_7093_p2;
wire [7:0] x_assign_3_4_fu_7107_p2;
wire [7:0] tmp_235_fu_7113_p2;
wire [0:0] tmp_236_fu_7119_p3;
wire [7:0] rv_10_4_fu_7127_p2;
wire [7:0] x_assign_4_1_fu_7141_p2;
wire [7:0] tmp_47_4_1_fu_7147_p2;
wire [7:0] tmp_237_fu_7159_p2;
wire [0:0] tmp_238_fu_7165_p3;
wire [7:0] rv_1_4_1_fu_7173_p2;
wire [7:0] x_assign_1_4_1_fu_7187_p2;
wire [7:0] tmp_239_fu_7193_p2;
wire [0:0] tmp_240_fu_7199_p3;
wire [7:0] rv_4_4_1_fu_7207_p2;
wire [7:0] x_assign_2_4_1_fu_7221_p2;
wire [7:0] tmp_241_fu_7227_p2;
wire [0:0] tmp_242_fu_7233_p3;
wire [7:0] rv_7_4_1_fu_7241_p2;
wire [7:0] x_assign_3_4_1_fu_7255_p2;
wire [7:0] tmp_243_fu_7261_p2;
wire [0:0] tmp_244_fu_7267_p3;
wire [7:0] rv_10_4_1_fu_7275_p2;
wire [7:0] x_assign_4_2_fu_7289_p2;
wire [7:0] tmp_47_4_2_fu_7295_p2;
wire [7:0] tmp_245_fu_7307_p2;
wire [0:0] tmp_246_fu_7313_p3;
wire [7:0] rv_1_4_2_fu_7321_p2;
wire [7:0] x_assign_1_4_2_fu_7335_p2;
wire [7:0] tmp_247_fu_7341_p2;
wire [0:0] tmp_248_fu_7347_p3;
wire [7:0] rv_4_4_2_fu_7355_p2;
wire [7:0] x_assign_2_4_2_fu_7369_p2;
wire [7:0] tmp_249_fu_7375_p2;
wire [0:0] tmp_250_fu_7381_p3;
wire [7:0] rv_7_4_2_fu_7389_p2;
wire [7:0] x_assign_3_4_2_fu_7403_p2;
wire [7:0] tmp_251_fu_7409_p2;
wire [0:0] tmp_252_fu_7415_p3;
wire [7:0] rv_10_4_2_fu_7423_p2;
wire [7:0] x_assign_4_3_fu_7437_p2;
wire [7:0] tmp_47_4_3_fu_7443_p2;
wire [7:0] tmp_253_fu_7455_p2;
wire [0:0] tmp_254_fu_7461_p3;
wire [7:0] rv_1_4_3_fu_7469_p2;
wire [7:0] x_assign_1_4_3_fu_7483_p2;
wire [7:0] tmp_255_fu_7489_p2;
wire [0:0] tmp_256_fu_7495_p3;
wire [7:0] rv_4_4_3_fu_7503_p2;
wire [7:0] x_assign_2_4_3_fu_7517_p2;
wire [7:0] tmp_257_fu_7523_p2;
wire [0:0] tmp_258_fu_7529_p3;
wire [7:0] rv_7_4_3_fu_7537_p2;
wire [7:0] x_assign_3_4_3_fu_7551_p2;
wire [7:0] tmp_259_fu_7557_p2;
wire [0:0] tmp_260_fu_7563_p3;
wire [7:0] rv_10_4_3_fu_7571_p2;
wire [7:0] tmp126_fu_7585_p2;
wire [7:0] rv_2_4_fu_7031_p3;
wire [7:0] e_4_fu_7005_p2;
wire [7:0] tmp128_fu_7657_p2;
wire [7:0] tmp127_fu_7651_p2;
wire [7:0] rv_5_4_fu_7065_p3;
wire [7:0] tmp130_fu_7675_p2;
wire [7:0] tmp129_fu_7669_p2;
wire [7:0] rv_8_4_fu_7099_p3;
wire [7:0] tmp132_fu_7693_p2;
wire [7:0] tmp131_fu_7687_p2;
wire [7:0] tmp133_fu_7705_p2;
wire [7:0] rv_11_4_fu_7133_p3;
wire [7:0] rv_2_4_1_fu_7179_p3;
wire [7:0] tmp136_fu_7723_p2;
wire [7:0] e_4_1_fu_7153_p2;
wire [7:0] tmp135_fu_7728_p2;
wire [7:0] tmp134_fu_7717_p2;
wire [7:0] tmp139_fu_7746_p2;
wire [7:0] rv_5_4_1_fu_7213_p3;
wire [7:0] tmp138_fu_7751_p2;
wire [7:0] tmp137_fu_7740_p2;
wire [7:0] tmp142_fu_7769_p2;
wire [7:0] rv_8_4_1_fu_7247_p3;
wire [7:0] tmp141_fu_7774_p2;
wire [7:0] tmp140_fu_7763_p2;
wire [7:0] rv_11_4_1_fu_7281_p3;
wire [7:0] tmp144_fu_7792_p2;
wire [7:0] tmp143_fu_7786_p2;
wire [7:0] rv_2_4_2_fu_7327_p3;
wire [7:0] e_4_2_fu_7301_p2;
wire [7:0] tmp146_fu_7809_p2;
wire [7:0] tmp145_fu_7803_p2;
wire [7:0] rv_5_4_2_fu_7361_p3;
wire [7:0] tmp148_fu_7827_p2;
wire [7:0] tmp147_fu_7821_p2;
wire [7:0] rv_8_4_2_fu_7395_p3;
wire [7:0] tmp150_fu_7845_p2;
wire [7:0] tmp149_fu_7839_p2;
wire [7:0] tmp151_fu_7857_p2;
wire [7:0] rv_11_4_2_fu_7429_p3;
wire [7:0] rv_2_4_3_fu_7475_p3;
wire [7:0] e_4_3_fu_7449_p2;
wire [7:0] tmp_77_4_fu_7631_p2;
wire [7:0] tmp153_fu_7875_p2;
wire [7:0] tmp152_fu_7869_p2;
wire [7:0] rv_5_4_3_fu_7509_p3;
wire [7:0] tmp_78_4_fu_7636_p2;
wire [7:0] tmp155_fu_7893_p2;
wire [7:0] tmp154_fu_7887_p2;
wire [7:0] rv_8_4_3_fu_7543_p3;
wire [7:0] tmp_79_4_fu_7641_p2;
wire [7:0] tmp157_fu_7911_p2;
wire [7:0] tmp156_fu_7905_p2;
wire [7:0] tmp_80_4_fu_7646_p2;
wire [7:0] tmp158_fu_7923_p2;
wire [7:0] rv_11_4_3_fu_7577_p3;
wire [7:0] tmp_85_4_fu_7663_p2;
wire [7:0] tmp_85_4_1_fu_7681_p2;
wire [7:0] tmp_85_4_2_fu_7699_p2;
wire [7:0] tmp_85_4_3_fu_7711_p2;
wire [7:0] tmp_85_4_4_fu_7734_p2;
wire [7:0] tmp_85_4_5_fu_7757_p2;
wire [7:0] tmp_85_4_6_fu_7780_p2;
wire [7:0] tmp_85_4_7_fu_7797_p2;
wire [7:0] tmp_85_4_8_fu_7815_p2;
wire [7:0] tmp_85_4_9_fu_7833_p2;
wire [7:0] tmp_85_4_s_fu_7851_p2;
wire [7:0] tmp_85_4_10_fu_7863_p2;
wire [7:0] tmp_85_4_11_fu_7881_p2;
wire [7:0] tmp_85_4_12_fu_7899_p2;
wire [7:0] tmp_85_4_13_fu_7917_p2;
wire [7:0] tmp_85_4_14_fu_7929_p2;
wire [7:0] x_assign_5_fu_8035_p2;
wire [7:0] tmp_47_5_fu_8041_p2;
wire [7:0] tmp_261_fu_8053_p2;
wire [0:0] tmp_262_fu_8059_p3;
wire [7:0] rv_1_5_fu_8067_p2;
wire [7:0] x_assign_1_5_fu_8081_p2;
wire [7:0] tmp_263_fu_8087_p2;
wire [0:0] tmp_264_fu_8093_p3;
wire [7:0] rv_4_5_fu_8101_p2;
wire [7:0] x_assign_2_5_fu_8115_p2;
wire [7:0] tmp_265_fu_8121_p2;
wire [0:0] tmp_266_fu_8127_p3;
wire [7:0] rv_7_5_fu_8135_p2;
wire [7:0] x_assign_3_5_fu_8149_p2;
wire [7:0] tmp_267_fu_8155_p2;
wire [0:0] tmp_268_fu_8161_p3;
wire [7:0] rv_10_5_fu_8169_p2;
wire [7:0] x_assign_5_1_fu_8183_p2;
wire [7:0] tmp_47_5_1_fu_8189_p2;
wire [7:0] tmp_269_fu_8201_p2;
wire [0:0] tmp_270_fu_8207_p3;
wire [7:0] rv_1_5_1_fu_8215_p2;
wire [7:0] x_assign_1_5_1_fu_8229_p2;
wire [7:0] tmp_271_fu_8235_p2;
wire [0:0] tmp_272_fu_8241_p3;
wire [7:0] rv_4_5_1_fu_8249_p2;
wire [7:0] x_assign_2_5_1_fu_8263_p2;
wire [7:0] tmp_273_fu_8269_p2;
wire [0:0] tmp_274_fu_8275_p3;
wire [7:0] rv_7_5_1_fu_8283_p2;
wire [7:0] x_assign_3_5_1_fu_8297_p2;
wire [7:0] tmp_275_fu_8303_p2;
wire [0:0] tmp_276_fu_8309_p3;
wire [7:0] rv_10_5_1_fu_8317_p2;
wire [7:0] x_assign_5_2_fu_8331_p2;
wire [7:0] tmp_47_5_2_fu_8337_p2;
wire [7:0] tmp_277_fu_8349_p2;
wire [0:0] tmp_278_fu_8355_p3;
wire [7:0] rv_1_5_2_fu_8363_p2;
wire [7:0] x_assign_1_5_2_fu_8377_p2;
wire [7:0] tmp_279_fu_8383_p2;
wire [0:0] tmp_280_fu_8389_p3;
wire [7:0] rv_4_5_2_fu_8397_p2;
wire [7:0] x_assign_2_5_2_fu_8411_p2;
wire [7:0] tmp_281_fu_8417_p2;
wire [0:0] tmp_282_fu_8423_p3;
wire [7:0] rv_7_5_2_fu_8431_p2;
wire [7:0] x_assign_3_5_2_fu_8445_p2;
wire [7:0] tmp_283_fu_8451_p2;
wire [0:0] tmp_284_fu_8457_p3;
wire [7:0] rv_10_5_2_fu_8465_p2;
wire [7:0] x_assign_5_3_fu_8479_p2;
wire [7:0] tmp_47_5_3_fu_8485_p2;
wire [7:0] tmp_285_fu_8497_p2;
wire [0:0] tmp_286_fu_8503_p3;
wire [7:0] rv_1_5_3_fu_8511_p2;
wire [7:0] x_assign_1_5_3_fu_8525_p2;
wire [7:0] tmp_287_fu_8531_p2;
wire [0:0] tmp_288_fu_8537_p3;
wire [7:0] rv_4_5_3_fu_8545_p2;
wire [7:0] x_assign_2_5_3_fu_8559_p2;
wire [7:0] tmp_289_fu_8565_p2;
wire [0:0] tmp_290_fu_8571_p3;
wire [7:0] rv_7_5_3_fu_8579_p2;
wire [7:0] x_assign_3_5_3_fu_8593_p2;
wire [7:0] tmp_291_fu_8599_p2;
wire [0:0] tmp_292_fu_8605_p3;
wire [7:0] rv_10_5_3_fu_8613_p2;
wire [7:0] tmp_64_5_fu_8627_p2;
wire [7:0] rv_2_5_fu_8073_p3;
wire [7:0] e_5_fu_8047_p2;
wire [7:0] tmp160_fu_8699_p2;
wire [7:0] tmp159_fu_8693_p2;
wire [7:0] rv_5_5_fu_8107_p3;
wire [7:0] tmp162_fu_8717_p2;
wire [7:0] tmp161_fu_8711_p2;
wire [7:0] rv_8_5_fu_8141_p3;
wire [7:0] tmp164_fu_8735_p2;
wire [7:0] tmp163_fu_8729_p2;
wire [7:0] tmp165_fu_8747_p2;
wire [7:0] rv_11_5_fu_8175_p3;
wire [7:0] rv_2_5_1_fu_8221_p3;
wire [7:0] e_5_1_fu_8195_p2;
wire [7:0] tmp167_fu_8765_p2;
wire [7:0] tmp166_fu_8759_p2;
wire [7:0] rv_5_5_1_fu_8255_p3;
wire [7:0] tmp169_fu_8783_p2;
wire [7:0] tmp168_fu_8777_p2;
wire [7:0] rv_8_5_1_fu_8289_p3;
wire [7:0] tmp171_fu_8801_p2;
wire [7:0] tmp170_fu_8795_p2;
wire [7:0] tmp172_fu_8813_p2;
wire [7:0] rv_11_5_1_fu_8323_p3;
wire [7:0] rv_2_5_2_fu_8369_p3;
wire [7:0] tmp175_fu_8831_p2;
wire [7:0] e_5_2_fu_8343_p2;
wire [7:0] tmp174_fu_8836_p2;
wire [7:0] tmp173_fu_8825_p2;
wire [7:0] tmp178_fu_8854_p2;
wire [7:0] rv_5_5_2_fu_8403_p3;
wire [7:0] tmp177_fu_8859_p2;
wire [7:0] tmp176_fu_8848_p2;
wire [7:0] tmp181_fu_8877_p2;
wire [7:0] rv_8_5_2_fu_8437_p3;
wire [7:0] tmp180_fu_8882_p2;
wire [7:0] tmp179_fu_8871_p2;
wire [7:0] rv_11_5_2_fu_8471_p3;
wire [7:0] tmp183_fu_8900_p2;
wire [7:0] tmp182_fu_8894_p2;
wire [7:0] rv_2_5_3_fu_8517_p3;
wire [7:0] e_5_3_fu_8491_p2;
wire [7:0] tmp185_fu_8917_p2;
wire [7:0] tmp184_fu_8911_p2;
wire [7:0] rv_5_5_3_fu_8551_p3;
wire [7:0] tmp187_fu_8935_p2;
wire [7:0] tmp186_fu_8929_p2;
wire [7:0] rv_8_5_3_fu_8585_p3;
wire [7:0] tmp189_fu_8953_p2;
wire [7:0] tmp188_fu_8947_p2;
wire [7:0] tmp190_fu_8965_p2;
wire [7:0] rv_11_5_3_fu_8619_p3;
wire [7:0] tmp_85_5_fu_8705_p2;
wire [7:0] tmp_85_5_1_fu_8723_p2;
wire [7:0] tmp_85_5_2_fu_8741_p2;
wire [7:0] tmp_85_5_3_fu_8753_p2;
wire [7:0] tmp_85_5_4_fu_8771_p2;
wire [7:0] tmp_85_5_5_fu_8789_p2;
wire [7:0] tmp_85_5_6_fu_8807_p2;
wire [7:0] tmp_85_5_7_fu_8819_p2;
wire [7:0] tmp_85_5_8_fu_8842_p2;
wire [7:0] tmp_85_5_9_fu_8865_p2;
wire [7:0] tmp_85_5_s_fu_8888_p2;
wire [7:0] tmp_85_5_10_fu_8905_p2;
wire [7:0] tmp_85_5_11_fu_8923_p2;
wire [7:0] tmp_85_5_12_fu_8941_p2;
wire [7:0] tmp_85_5_13_fu_8959_p2;
wire [7:0] tmp_85_5_14_fu_8971_p2;
wire [7:0] x_assign_6_fu_9077_p2;
wire [7:0] tmp_47_6_fu_9083_p2;
wire [7:0] tmp_293_fu_9095_p2;
wire [0:0] tmp_294_fu_9101_p3;
wire [7:0] rv_1_6_fu_9109_p2;
wire [7:0] x_assign_1_6_fu_9123_p2;
wire [7:0] tmp_295_fu_9129_p2;
wire [0:0] tmp_296_fu_9135_p3;
wire [7:0] rv_4_6_fu_9143_p2;
wire [7:0] x_assign_2_6_fu_9157_p2;
wire [7:0] tmp_297_fu_9163_p2;
wire [0:0] tmp_298_fu_9169_p3;
wire [7:0] rv_7_6_fu_9177_p2;
wire [7:0] x_assign_3_6_fu_9191_p2;
wire [7:0] tmp_299_fu_9197_p2;
wire [0:0] tmp_300_fu_9203_p3;
wire [7:0] rv_10_6_fu_9211_p2;
wire [7:0] x_assign_6_1_fu_9225_p2;
wire [7:0] tmp_47_6_1_fu_9231_p2;
wire [7:0] tmp_301_fu_9243_p2;
wire [0:0] tmp_302_fu_9249_p3;
wire [7:0] rv_1_6_1_fu_9257_p2;
wire [7:0] x_assign_1_6_1_fu_9271_p2;
wire [7:0] tmp_303_fu_9277_p2;
wire [0:0] tmp_304_fu_9283_p3;
wire [7:0] rv_4_6_1_fu_9291_p2;
wire [7:0] x_assign_2_6_1_fu_9305_p2;
wire [7:0] tmp_305_fu_9311_p2;
wire [0:0] tmp_306_fu_9317_p3;
wire [7:0] rv_7_6_1_fu_9325_p2;
wire [7:0] x_assign_3_6_1_fu_9339_p2;
wire [7:0] tmp_307_fu_9345_p2;
wire [0:0] tmp_308_fu_9351_p3;
wire [7:0] rv_10_6_1_fu_9359_p2;
wire [7:0] x_assign_6_2_fu_9373_p2;
wire [7:0] tmp_47_6_2_fu_9379_p2;
wire [7:0] tmp_309_fu_9391_p2;
wire [0:0] tmp_310_fu_9397_p3;
wire [7:0] rv_1_6_2_fu_9405_p2;
wire [7:0] x_assign_1_6_2_fu_9419_p2;
wire [7:0] tmp_311_fu_9425_p2;
wire [0:0] tmp_312_fu_9431_p3;
wire [7:0] rv_4_6_2_fu_9439_p2;
wire [7:0] x_assign_2_6_2_fu_9453_p2;
wire [7:0] tmp_313_fu_9459_p2;
wire [0:0] tmp_314_fu_9465_p3;
wire [7:0] rv_7_6_2_fu_9473_p2;
wire [7:0] x_assign_3_6_2_fu_9487_p2;
wire [7:0] tmp_315_fu_9493_p2;
wire [0:0] tmp_316_fu_9499_p3;
wire [7:0] rv_10_6_2_fu_9507_p2;
wire [7:0] x_assign_6_3_fu_9521_p2;
wire [7:0] tmp_47_6_3_fu_9527_p2;
wire [7:0] tmp_317_fu_9539_p2;
wire [0:0] tmp_318_fu_9545_p3;
wire [7:0] rv_1_6_3_fu_9553_p2;
wire [7:0] x_assign_1_6_3_fu_9567_p2;
wire [7:0] tmp_319_fu_9573_p2;
wire [0:0] tmp_320_fu_9579_p3;
wire [7:0] rv_4_6_3_fu_9587_p2;
wire [7:0] x_assign_2_6_3_fu_9601_p2;
wire [7:0] tmp_321_fu_9607_p2;
wire [0:0] tmp_322_fu_9613_p3;
wire [7:0] rv_7_6_3_fu_9621_p2;
wire [7:0] x_assign_3_6_3_fu_9635_p2;
wire [7:0] tmp_323_fu_9641_p2;
wire [0:0] tmp_324_fu_9647_p3;
wire [7:0] rv_10_6_3_fu_9655_p2;
wire [7:0] tmp191_fu_9669_p2;
wire [7:0] rv_2_6_fu_9115_p3;
wire [7:0] e_6_fu_9089_p2;
wire [7:0] tmp193_fu_9741_p2;
wire [7:0] tmp192_fu_9735_p2;
wire [7:0] rv_5_6_fu_9149_p3;
wire [7:0] tmp195_fu_9759_p2;
wire [7:0] tmp194_fu_9753_p2;
wire [7:0] rv_8_6_fu_9183_p3;
wire [7:0] tmp197_fu_9777_p2;
wire [7:0] tmp196_fu_9771_p2;
wire [7:0] tmp198_fu_9789_p2;
wire [7:0] rv_11_6_fu_9217_p3;
wire [7:0] rv_2_6_1_fu_9263_p3;
wire [7:0] tmp201_fu_9807_p2;
wire [7:0] e_6_1_fu_9237_p2;
wire [7:0] tmp200_fu_9812_p2;
wire [7:0] tmp199_fu_9801_p2;
wire [7:0] tmp204_fu_9830_p2;
wire [7:0] rv_5_6_1_fu_9297_p3;
wire [7:0] tmp203_fu_9835_p2;
wire [7:0] tmp202_fu_9824_p2;
wire [7:0] tmp207_fu_9853_p2;
wire [7:0] rv_8_6_1_fu_9331_p3;
wire [7:0] tmp206_fu_9858_p2;
wire [7:0] tmp205_fu_9847_p2;
wire [7:0] rv_11_6_1_fu_9365_p3;
wire [7:0] tmp209_fu_9876_p2;
wire [7:0] tmp208_fu_9870_p2;
wire [7:0] rv_2_6_2_fu_9411_p3;
wire [7:0] e_6_2_fu_9385_p2;
wire [7:0] tmp211_fu_9893_p2;
wire [7:0] tmp210_fu_9887_p2;
wire [7:0] rv_5_6_2_fu_9445_p3;
wire [7:0] tmp213_fu_9911_p2;
wire [7:0] tmp212_fu_9905_p2;
wire [7:0] rv_8_6_2_fu_9479_p3;
wire [7:0] tmp215_fu_9929_p2;
wire [7:0] tmp214_fu_9923_p2;
wire [7:0] tmp216_fu_9941_p2;
wire [7:0] rv_11_6_2_fu_9513_p3;
wire [7:0] rv_2_6_3_fu_9559_p3;
wire [7:0] e_6_3_fu_9533_p2;
wire [7:0] tmp_77_6_fu_9715_p2;
wire [7:0] tmp218_fu_9959_p2;
wire [7:0] tmp217_fu_9953_p2;
wire [7:0] rv_5_6_3_fu_9593_p3;
wire [7:0] tmp_78_6_fu_9720_p2;
wire [7:0] tmp220_fu_9977_p2;
wire [7:0] tmp219_fu_9971_p2;
wire [7:0] rv_8_6_3_fu_9627_p3;
wire [7:0] tmp_79_6_fu_9725_p2;
wire [7:0] tmp222_fu_9995_p2;
wire [7:0] tmp221_fu_9989_p2;
wire [7:0] tmp_80_6_fu_9730_p2;
wire [7:0] tmp223_fu_10007_p2;
wire [7:0] rv_11_6_3_fu_9661_p3;
wire [7:0] tmp_85_6_fu_9747_p2;
wire [7:0] tmp_85_6_1_fu_9765_p2;
wire [7:0] tmp_85_6_2_fu_9783_p2;
wire [7:0] tmp_85_6_3_fu_9795_p2;
wire [7:0] tmp_85_6_4_fu_9818_p2;
wire [7:0] tmp_85_6_5_fu_9841_p2;
wire [7:0] tmp_85_6_6_fu_9864_p2;
wire [7:0] tmp_85_6_7_fu_9881_p2;
wire [7:0] tmp_85_6_8_fu_9899_p2;
wire [7:0] tmp_85_6_9_fu_9917_p2;
wire [7:0] tmp_85_6_s_fu_9935_p2;
wire [7:0] tmp_85_6_10_fu_9947_p2;
wire [7:0] tmp_85_6_11_fu_9965_p2;
wire [7:0] tmp_85_6_12_fu_9983_p2;
wire [7:0] tmp_85_6_13_fu_10001_p2;
wire [7:0] tmp_85_6_14_fu_10013_p2;
wire [7:0] x_assign_7_fu_10119_p2;
wire [7:0] tmp_47_7_fu_10125_p2;
wire [7:0] tmp_325_fu_10137_p2;
wire [0:0] tmp_326_fu_10143_p3;
wire [7:0] rv_1_7_fu_10151_p2;
wire [7:0] x_assign_1_7_fu_10165_p2;
wire [7:0] tmp_327_fu_10171_p2;
wire [0:0] tmp_328_fu_10177_p3;
wire [7:0] rv_4_7_fu_10185_p2;
wire [7:0] x_assign_2_7_fu_10199_p2;
wire [7:0] tmp_329_fu_10205_p2;
wire [0:0] tmp_330_fu_10211_p3;
wire [7:0] rv_7_7_fu_10219_p2;
wire [7:0] x_assign_3_7_fu_10233_p2;
wire [7:0] tmp_331_fu_10239_p2;
wire [0:0] tmp_332_fu_10245_p3;
wire [7:0] rv_10_7_fu_10253_p2;
wire [7:0] x_assign_7_1_fu_10267_p2;
wire [7:0] tmp_47_7_1_fu_10273_p2;
wire [7:0] tmp_333_fu_10285_p2;
wire [0:0] tmp_334_fu_10291_p3;
wire [7:0] rv_1_7_1_fu_10299_p2;
wire [7:0] x_assign_1_7_1_fu_10313_p2;
wire [7:0] tmp_335_fu_10319_p2;
wire [0:0] tmp_336_fu_10325_p3;
wire [7:0] rv_4_7_1_fu_10333_p2;
wire [7:0] x_assign_2_7_1_fu_10347_p2;
wire [7:0] tmp_337_fu_10353_p2;
wire [0:0] tmp_338_fu_10359_p3;
wire [7:0] rv_7_7_1_fu_10367_p2;
wire [7:0] x_assign_3_7_1_fu_10381_p2;
wire [7:0] tmp_339_fu_10387_p2;
wire [0:0] tmp_340_fu_10393_p3;
wire [7:0] rv_10_7_1_fu_10401_p2;
wire [7:0] x_assign_7_2_fu_10415_p2;
wire [7:0] tmp_47_7_2_fu_10421_p2;
wire [7:0] tmp_341_fu_10433_p2;
wire [0:0] tmp_342_fu_10439_p3;
wire [7:0] rv_1_7_2_fu_10447_p2;
wire [7:0] x_assign_1_7_2_fu_10461_p2;
wire [7:0] tmp_343_fu_10467_p2;
wire [0:0] tmp_344_fu_10473_p3;
wire [7:0] rv_4_7_2_fu_10481_p2;
wire [7:0] x_assign_2_7_2_fu_10495_p2;
wire [7:0] tmp_345_fu_10501_p2;
wire [0:0] tmp_346_fu_10507_p3;
wire [7:0] rv_7_7_2_fu_10515_p2;
wire [7:0] x_assign_3_7_2_fu_10529_p2;
wire [7:0] tmp_347_fu_10535_p2;
wire [0:0] tmp_348_fu_10541_p3;
wire [7:0] rv_10_7_2_fu_10549_p2;
wire [7:0] x_assign_7_3_fu_10563_p2;
wire [7:0] tmp_47_7_3_fu_10569_p2;
wire [7:0] tmp_349_fu_10581_p2;
wire [0:0] tmp_350_fu_10587_p3;
wire [7:0] rv_1_7_3_fu_10595_p2;
wire [7:0] x_assign_1_7_3_fu_10609_p2;
wire [7:0] tmp_351_fu_10615_p2;
wire [0:0] tmp_352_fu_10621_p3;
wire [7:0] rv_4_7_3_fu_10629_p2;
wire [7:0] x_assign_2_7_3_fu_10643_p2;
wire [7:0] tmp_353_fu_10649_p2;
wire [0:0] tmp_354_fu_10655_p3;
wire [7:0] rv_7_7_3_fu_10663_p2;
wire [7:0] x_assign_3_7_3_fu_10677_p2;
wire [7:0] tmp_355_fu_10683_p2;
wire [0:0] tmp_356_fu_10689_p3;
wire [7:0] rv_10_7_3_fu_10697_p2;
wire [7:0] tmp_64_7_fu_10711_p2;
wire [7:0] rv_2_7_fu_10157_p3;
wire [7:0] e_7_fu_10131_p2;
wire [7:0] tmp225_fu_10783_p2;
wire [7:0] tmp224_fu_10777_p2;
wire [7:0] rv_5_7_fu_10191_p3;
wire [7:0] tmp227_fu_10801_p2;
wire [7:0] tmp226_fu_10795_p2;
wire [7:0] rv_8_7_fu_10225_p3;
wire [7:0] tmp229_fu_10819_p2;
wire [7:0] tmp228_fu_10813_p2;
wire [7:0] tmp230_fu_10831_p2;
wire [7:0] rv_11_7_fu_10259_p3;
wire [7:0] rv_2_7_1_fu_10305_p3;
wire [7:0] e_7_1_fu_10279_p2;
wire [7:0] tmp232_fu_10849_p2;
wire [7:0] tmp231_fu_10843_p2;
wire [7:0] rv_5_7_1_fu_10339_p3;
wire [7:0] tmp234_fu_10867_p2;
wire [7:0] tmp233_fu_10861_p2;
wire [7:0] rv_8_7_1_fu_10373_p3;
wire [7:0] tmp236_fu_10885_p2;
wire [7:0] tmp235_fu_10879_p2;
wire [7:0] tmp237_fu_10897_p2;
wire [7:0] rv_11_7_1_fu_10407_p3;
wire [7:0] rv_2_7_2_fu_10453_p3;
wire [7:0] tmp240_fu_10915_p2;
wire [7:0] e_7_2_fu_10427_p2;
wire [7:0] tmp239_fu_10920_p2;
wire [7:0] tmp238_fu_10909_p2;
wire [7:0] tmp243_fu_10938_p2;
wire [7:0] rv_5_7_2_fu_10487_p3;
wire [7:0] tmp242_fu_10943_p2;
wire [7:0] tmp241_fu_10932_p2;
wire [7:0] tmp246_fu_10961_p2;
wire [7:0] rv_8_7_2_fu_10521_p3;
wire [7:0] tmp245_fu_10966_p2;
wire [7:0] tmp244_fu_10955_p2;
wire [7:0] rv_11_7_2_fu_10555_p3;
wire [7:0] tmp248_fu_10984_p2;
wire [7:0] tmp247_fu_10978_p2;
wire [7:0] rv_2_7_3_fu_10601_p3;
wire [7:0] e_7_3_fu_10575_p2;
wire [7:0] tmp250_fu_11001_p2;
wire [7:0] tmp249_fu_10995_p2;
wire [7:0] rv_5_7_3_fu_10635_p3;
wire [7:0] tmp252_fu_11019_p2;
wire [7:0] tmp251_fu_11013_p2;
wire [7:0] rv_8_7_3_fu_10669_p3;
wire [7:0] tmp254_fu_11037_p2;
wire [7:0] tmp253_fu_11031_p2;
wire [7:0] tmp255_fu_11049_p2;
wire [7:0] rv_11_7_3_fu_10703_p3;
wire [7:0] tmp_85_7_fu_10789_p2;
wire [7:0] tmp_85_7_1_fu_10807_p2;
wire [7:0] tmp_85_7_2_fu_10825_p2;
wire [7:0] tmp_85_7_3_fu_10837_p2;
wire [7:0] tmp_85_7_4_fu_10855_p2;
wire [7:0] tmp_85_7_5_fu_10873_p2;
wire [7:0] tmp_85_7_6_fu_10891_p2;
wire [7:0] tmp_85_7_7_fu_10903_p2;
wire [7:0] tmp_85_7_8_fu_10926_p2;
wire [7:0] tmp_85_7_9_fu_10949_p2;
wire [7:0] tmp_85_7_s_fu_10972_p2;
wire [7:0] tmp_85_7_10_fu_10989_p2;
wire [7:0] tmp_85_7_11_fu_11007_p2;
wire [7:0] tmp_85_7_12_fu_11025_p2;
wire [7:0] tmp_85_7_13_fu_11043_p2;
wire [7:0] tmp_85_7_14_fu_11055_p2;
wire [7:0] x_assign_8_fu_11161_p2;
wire [7:0] tmp_47_8_fu_11167_p2;
wire [7:0] tmp_357_fu_11179_p2;
wire [0:0] tmp_358_fu_11185_p3;
wire [7:0] rv_1_8_fu_11193_p2;
wire [7:0] x_assign_1_8_fu_11207_p2;
wire [7:0] tmp_359_fu_11213_p2;
wire [0:0] tmp_360_fu_11219_p3;
wire [7:0] rv_4_8_fu_11227_p2;
wire [7:0] x_assign_2_8_fu_11241_p2;
wire [7:0] tmp_361_fu_11247_p2;
wire [0:0] tmp_362_fu_11253_p3;
wire [7:0] rv_7_8_fu_11261_p2;
wire [7:0] x_assign_3_8_fu_11275_p2;
wire [7:0] tmp_363_fu_11281_p2;
wire [0:0] tmp_364_fu_11287_p3;
wire [7:0] rv_10_8_fu_11295_p2;
wire [7:0] x_assign_8_1_fu_11309_p2;
wire [7:0] tmp_47_8_1_fu_11315_p2;
wire [7:0] tmp_365_fu_11327_p2;
wire [0:0] tmp_366_fu_11333_p3;
wire [7:0] rv_1_8_1_fu_11341_p2;
wire [7:0] x_assign_1_8_1_fu_11355_p2;
wire [7:0] tmp_367_fu_11361_p2;
wire [0:0] tmp_368_fu_11367_p3;
wire [7:0] rv_4_8_1_fu_11375_p2;
wire [7:0] x_assign_2_8_1_fu_11389_p2;
wire [7:0] tmp_369_fu_11395_p2;
wire [0:0] tmp_370_fu_11401_p3;
wire [7:0] rv_7_8_1_fu_11409_p2;
wire [7:0] x_assign_3_8_1_fu_11423_p2;
wire [7:0] tmp_371_fu_11429_p2;
wire [0:0] tmp_372_fu_11435_p3;
wire [7:0] rv_10_8_1_fu_11443_p2;
wire [7:0] x_assign_8_2_fu_11457_p2;
wire [7:0] tmp_47_8_2_fu_11463_p2;
wire [7:0] tmp_373_fu_11475_p2;
wire [0:0] tmp_374_fu_11481_p3;
wire [7:0] rv_1_8_2_fu_11489_p2;
wire [7:0] x_assign_1_8_2_fu_11503_p2;
wire [7:0] tmp_375_fu_11509_p2;
wire [0:0] tmp_376_fu_11515_p3;
wire [7:0] rv_4_8_2_fu_11523_p2;
wire [7:0] x_assign_2_8_2_fu_11537_p2;
wire [7:0] tmp_377_fu_11543_p2;
wire [0:0] tmp_378_fu_11549_p3;
wire [7:0] rv_7_8_2_fu_11557_p2;
wire [7:0] x_assign_3_8_2_fu_11571_p2;
wire [7:0] tmp_379_fu_11577_p2;
wire [0:0] tmp_380_fu_11583_p3;
wire [7:0] rv_10_8_2_fu_11591_p2;
wire [7:0] x_assign_8_3_fu_11605_p2;
wire [7:0] tmp_47_8_3_fu_11611_p2;
wire [7:0] tmp_381_fu_11623_p2;
wire [0:0] tmp_382_fu_11629_p3;
wire [7:0] rv_1_8_3_fu_11637_p2;
wire [7:0] x_assign_1_8_3_fu_11651_p2;
wire [7:0] tmp_383_fu_11657_p2;
wire [0:0] tmp_384_fu_11663_p3;
wire [7:0] rv_4_8_3_fu_11671_p2;
wire [7:0] x_assign_2_8_3_fu_11685_p2;
wire [7:0] tmp_385_fu_11691_p2;
wire [0:0] tmp_386_fu_11697_p3;
wire [7:0] rv_7_8_3_fu_11705_p2;
wire [7:0] x_assign_3_8_3_fu_11719_p2;
wire [7:0] tmp_387_fu_11725_p2;
wire [0:0] tmp_388_fu_11731_p3;
wire [7:0] rv_10_8_3_fu_11739_p2;
wire [7:0] tmp256_fu_11753_p2;
wire [7:0] rv_2_8_fu_11199_p3;
wire [7:0] e_8_fu_11173_p2;
wire [7:0] tmp258_fu_11825_p2;
wire [7:0] tmp257_fu_11819_p2;
wire [7:0] rv_5_8_fu_11233_p3;
wire [7:0] tmp260_fu_11843_p2;
wire [7:0] tmp259_fu_11837_p2;
wire [7:0] rv_8_8_fu_11267_p3;
wire [7:0] tmp262_fu_11861_p2;
wire [7:0] tmp261_fu_11855_p2;
wire [7:0] tmp263_fu_11873_p2;
wire [7:0] rv_11_8_fu_11301_p3;
wire [7:0] rv_2_8_1_fu_11347_p3;
wire [7:0] tmp266_fu_11891_p2;
wire [7:0] e_8_1_fu_11321_p2;
wire [7:0] tmp265_fu_11896_p2;
wire [7:0] tmp264_fu_11885_p2;
wire [7:0] tmp269_fu_11914_p2;
wire [7:0] rv_5_8_1_fu_11381_p3;
wire [7:0] tmp268_fu_11919_p2;
wire [7:0] tmp267_fu_11908_p2;
wire [7:0] tmp272_fu_11937_p2;
wire [7:0] rv_8_8_1_fu_11415_p3;
wire [7:0] tmp271_fu_11942_p2;
wire [7:0] tmp270_fu_11931_p2;
wire [7:0] rv_11_8_1_fu_11449_p3;
wire [7:0] tmp274_fu_11960_p2;
wire [7:0] tmp273_fu_11954_p2;
wire [7:0] rv_2_8_2_fu_11495_p3;
wire [7:0] e_8_2_fu_11469_p2;
wire [7:0] tmp276_fu_11977_p2;
wire [7:0] tmp275_fu_11971_p2;
wire [7:0] rv_5_8_2_fu_11529_p3;
wire [7:0] tmp278_fu_11995_p2;
wire [7:0] tmp277_fu_11989_p2;
wire [7:0] rv_8_8_2_fu_11563_p3;
wire [7:0] tmp280_fu_12013_p2;
wire [7:0] tmp279_fu_12007_p2;
wire [7:0] tmp281_fu_12025_p2;
wire [7:0] rv_11_8_2_fu_11597_p3;
wire [7:0] rv_2_8_3_fu_11643_p3;
wire [7:0] e_8_3_fu_11617_p2;
wire [7:0] tmp_77_8_fu_11799_p2;
wire [7:0] tmp283_fu_12043_p2;
wire [7:0] tmp282_fu_12037_p2;
wire [7:0] rv_5_8_3_fu_11677_p3;
wire [7:0] tmp_78_8_fu_11804_p2;
wire [7:0] tmp285_fu_12061_p2;
wire [7:0] tmp284_fu_12055_p2;
wire [7:0] rv_8_8_3_fu_11711_p3;
wire [7:0] tmp_79_8_fu_11809_p2;
wire [7:0] tmp287_fu_12079_p2;
wire [7:0] tmp286_fu_12073_p2;
wire [7:0] tmp_80_8_fu_11814_p2;
wire [7:0] tmp288_fu_12091_p2;
wire [7:0] rv_11_8_3_fu_11745_p3;
wire [7:0] tmp_85_8_fu_11831_p2;
wire [7:0] tmp_85_8_1_fu_11849_p2;
wire [7:0] tmp_85_8_2_fu_11867_p2;
wire [7:0] tmp_85_8_3_fu_11879_p2;
wire [7:0] tmp_85_8_4_fu_11902_p2;
wire [7:0] tmp_85_8_5_fu_11925_p2;
wire [7:0] tmp_85_8_6_fu_11948_p2;
wire [7:0] tmp_85_8_7_fu_11965_p2;
wire [7:0] tmp_85_8_8_fu_11983_p2;
wire [7:0] tmp_85_8_9_fu_12001_p2;
wire [7:0] tmp_85_8_s_fu_12019_p2;
wire [7:0] tmp_85_8_10_fu_12031_p2;
wire [7:0] tmp_85_8_11_fu_12049_p2;
wire [7:0] tmp_85_8_12_fu_12067_p2;
wire [7:0] tmp_85_8_13_fu_12085_p2;
wire [7:0] tmp_85_8_14_fu_12097_p2;
wire [7:0] tmp_4_fu_12203_p2;
wire [7:0] tmp289_fu_12229_p2;
wire [7:0] tmp290_fu_12240_p2;
wire [7:0] tmp291_fu_12251_p2;
wire [7:0] tmp292_fu_12262_p2;
wire [7:0] tmp_9_fu_12209_p2;
wire [7:0] tmp_11_fu_12214_p2;
wire [7:0] tmp_12_fu_12219_p2;
wire [7:0] tmp_13_fu_12224_p2;
wire [7:0] tmp293_fu_12297_p2;
wire [7:0] tmp294_fu_12308_p2;
wire [7:0] tmp295_fu_12319_p2;
wire [7:0] tmp296_fu_12330_p2;
wire [7:0] tmp297_fu_12341_p2;
wire [7:0] tmp298_fu_12352_p2;
wire [7:0] tmp299_fu_12363_p2;
wire [7:0] tmp300_fu_12374_p2;
wire [7:0] tmp_38_fu_12234_p2;
wire [7:0] tmp_38_1_fu_12245_p2;
wire [7:0] tmp_38_2_fu_12256_p2;
wire [7:0] tmp_38_3_fu_12267_p2;
wire [7:0] tmp_38_4_fu_12273_p2;
wire [7:0] tmp_38_5_fu_12279_p2;
wire [7:0] tmp_38_6_fu_12285_p2;
wire [7:0] tmp_38_7_fu_12291_p2;
wire [7:0] tmp_38_8_fu_12302_p2;
wire [7:0] tmp_38_9_fu_12313_p2;
wire [7:0] tmp_38_s_fu_12324_p2;
wire [7:0] tmp_38_10_fu_12335_p2;
wire [7:0] tmp_38_11_fu_12346_p2;
wire [7:0] tmp_38_12_fu_12357_p2;
wire [7:0] tmp_38_13_fu_12368_p2;
wire [7:0] tmp_38_14_fu_12379_p2;
reg [0:0] ap_NS_fsm;
reg ap_idle_pp0_0to9;
reg ap_reset_idle_pp0;
reg ap_reset_start_pp0;
wire ap_enable_pp0;
// power-on initialization
initial begin
#0 ap_CS_fsm = 1'd1;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_enable_reg_pp0_iter2 = 1'b0;
#0 ap_enable_reg_pp0_iter3 = 1'b0;
#0 ap_enable_reg_pp0_iter4 = 1'b0;
#0 ap_enable_reg_pp0_iter5 = 1'b0;
#0 ap_enable_reg_pp0_iter6 = 1'b0;
#0 ap_enable_reg_pp0_iter7 = 1'b0;
#0 ap_enable_reg_pp0_iter8 = 1'b0;
#0 ap_enable_reg_pp0_iter9 = 1'b0;
#0 ap_enable_reg_pp0_iter10 = 1'b0;
end
aestest_sboxes #(
.DataWidth( 8 ),
.AddressRange( 256 ),
.AddressWidth( 8 ))
sboxes_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(sboxes_address0),
.ce0(sboxes_ce0),
.q0(sboxes_q0),
.address1(sboxes_address1),
.ce1(sboxes_ce1),
.q1(sboxes_q1),
.address2(sboxes_address2),
.ce2(sboxes_ce2),
.q2(sboxes_q2),
.address3(sboxes_address3),
.ce3(sboxes_ce3),
.q3(sboxes_q3),
.address4(sboxes_address4),
.ce4(sboxes_ce4),
.q4(sboxes_q4),
.address5(sboxes_address5),
.ce5(sboxes_ce5),
.q5(sboxes_q5),
.address6(sboxes_address6),
.ce6(sboxes_ce6),
.q6(sboxes_q6),
.address7(sboxes_address7),
.ce7(sboxes_ce7),
.q7(sboxes_q7),
.address8(sboxes_address8),
.ce8(sboxes_ce8),
.q8(sboxes_q8),
.address9(sboxes_address9),
.ce9(sboxes_ce9),
.q9(sboxes_q9),
.address10(sboxes_address10),
.ce10(sboxes_ce10),
.q10(sboxes_q10),
.address11(sboxes_address11),
.ce11(sboxes_ce11),
.q11(sboxes_q11),
.address12(sboxes_address12),
.ce12(sboxes_ce12),
.q12(sboxes_q12),
.address13(sboxes_address13),
.ce13(sboxes_ce13),
.q13(sboxes_q13),
.address14(sboxes_address14),
.ce14(sboxes_ce14),
.q14(sboxes_q14),
.address15(sboxes_address15),
.ce15(sboxes_ce15),
.q15(sboxes_q15),
.address16(sboxes_address16),
.ce16(sboxes_ce16),
.q16(sboxes_q16),
.address17(sboxes_address17),
.ce17(sboxes_ce17),
.q17(sboxes_q17),
.address18(sboxes_address18),
.ce18(sboxes_ce18),
.q18(sboxes_q18),
.address19(sboxes_address19),
.ce19(sboxes_ce19),
.q19(sboxes_q19),
.address20(sboxes_address20),
.ce20(sboxes_ce20),
.q20(sboxes_q20),
.address21(sboxes_address21),
.ce21(sboxes_ce21),
.q21(sboxes_q21),
.address22(sboxes_address22),
.ce22(sboxes_ce22),
.q22(sboxes_q22),
.address23(sboxes_address23),
.ce23(sboxes_ce23),
.q23(sboxes_q23),
.address24(sboxes_address24),
.ce24(sboxes_ce24),
.q24(sboxes_q24),
.address25(sboxes_address25),
.ce25(sboxes_ce25),
.q25(sboxes_q25),
.address26(sboxes_address26),
.ce26(sboxes_ce26),
.q26(sboxes_q26),
.address27(sboxes_address27),
.ce27(sboxes_ce27),
.q27(sboxes_q27),
.address28(sboxes_address28),
.ce28(sboxes_ce28),
.q28(sboxes_q28),
.address29(sboxes_address29),
.ce29(sboxes_ce29),
.q29(sboxes_q29),
.address30(sboxes_address30),
.ce30(sboxes_ce30),
.q30(sboxes_q30),
.address31(sboxes_address31),
.ce31(sboxes_ce31),
.q31(sboxes_q31),
.address32(sboxes_address32),
.ce32(sboxes_ce32),
.q32(sboxes_q32),
.address33(sboxes_address33),
.ce33(sboxes_ce33),
.q33(sboxes_q33),
.address34(sboxes_address34),
.ce34(sboxes_ce34),
.q34(sboxes_q34),
.address35(sboxes_address35),
.ce35(sboxes_ce35),
.q35(sboxes_q35),
.address36(sboxes_address36),
.ce36(sboxes_ce36),
.q36(sboxes_q36),
.address37(sboxes_address37),
.ce37(sboxes_ce37),
.q37(sboxes_q37),
.address38(sboxes_address38),
.ce38(sboxes_ce38),
.q38(sboxes_q38),
.address39(sboxes_address39),
.ce39(sboxes_ce39),
.q39(sboxes_q39),
.address40(sboxes_address40),
.ce40(sboxes_ce40),
.q40(sboxes_q40),
.address41(sboxes_address41),
.ce41(sboxes_ce41),
.q41(sboxes_q41),
.address42(sboxes_address42),
.ce42(sboxes_ce42),
.q42(sboxes_q42),
.address43(sboxes_address43),
.ce43(sboxes_ce43),
.q43(sboxes_q43),
.address44(sboxes_address44),
.ce44(sboxes_ce44),
.q44(sboxes_q44),
.address45(sboxes_address45),
.ce45(sboxes_ce45),
.q45(sboxes_q45),
.address46(sboxes_address46),
.ce46(sboxes_ce46),
.q46(sboxes_q46),
.address47(sboxes_address47),
.ce47(sboxes_ce47),
.q47(sboxes_q47),
.address48(sboxes_address48),
.ce48(sboxes_ce48),
.q48(sboxes_q48),
.address49(sboxes_address49),
.ce49(sboxes_ce49),
.q49(sboxes_q49),
.address50(sboxes_address50),
.ce50(sboxes_ce50),
.q50(sboxes_q50),
.address51(sboxes_address51),
.ce51(sboxes_ce51),
.q51(sboxes_q51),
.address52(sboxes_address52),
.ce52(sboxes_ce52),
.q52(sboxes_q52),
.address53(sboxes_address53),
.ce53(sboxes_ce53),
.q53(sboxes_q53),
.address54(sboxes_address54),
.ce54(sboxes_ce54),
.q54(sboxes_q54),
.address55(sboxes_address55),
.ce55(sboxes_ce55),
.q55(sboxes_q55),
.address56(sboxes_address56),
.ce56(sboxes_ce56),
.q56(sboxes_q56),
.address57(sboxes_address57),
.ce57(sboxes_ce57),
.q57(sboxes_q57),
.address58(sboxes_address58),
.ce58(sboxes_ce58),
.q58(sboxes_q58),
.address59(sboxes_address59),
.ce59(sboxes_ce59),
.q59(sboxes_q59),
.address60(sboxes_address60),
.ce60(sboxes_ce60),
.q60(sboxes_q60),
.address61(sboxes_address61),
.ce61(sboxes_ce61),
.q61(sboxes_q61),
.address62(sboxes_address62),
.ce62(sboxes_ce62),
.q62(sboxes_q62),
.address63(sboxes_address63),
.ce63(sboxes_ce63),
.q63(sboxes_q63),
.address64(sboxes_address64),
.ce64(sboxes_ce64),
.q64(sboxes_q64),
.address65(sboxes_address65),
.ce65(sboxes_ce65),
.q65(sboxes_q65),
.address66(sboxes_address66),
.ce66(sboxes_ce66),
.q66(sboxes_q66),
.address67(sboxes_address67),
.ce67(sboxes_ce67),
.q67(sboxes_q67),
.address68(sboxes_address68),
.ce68(sboxes_ce68),
.q68(sboxes_q68),
.address69(sboxes_address69),
.ce69(sboxes_ce69),
.q69(sboxes_q69),
.address70(sboxes_address70),
.ce70(sboxes_ce70),
.q70(sboxes_q70),
.address71(sboxes_address71),
.ce71(sboxes_ce71),
.q71(sboxes_q71),
.address72(sboxes_address72),
.ce72(sboxes_ce72),
.q72(sboxes_q72),
.address73(sboxes_address73),
.ce73(sboxes_ce73),
.q73(sboxes_q73),
.address74(sboxes_address74),
.ce74(sboxes_ce74),
.q74(sboxes_q74),
.address75(sboxes_address75),
.ce75(sboxes_ce75),
.q75(sboxes_q75),
.address76(sboxes_address76),
.ce76(sboxes_ce76),
.q76(sboxes_q76),
.address77(sboxes_address77),
.ce77(sboxes_ce77),
.q77(sboxes_q77),
.address78(sboxes_address78),
.ce78(sboxes_ce78),
.q78(sboxes_q78),
.address79(sboxes_address79),
.ce79(sboxes_ce79),
.q79(sboxes_q79),
.address80(sboxes_address80),
.ce80(sboxes_ce80),
.q80(sboxes_q80),
.address81(sboxes_address81),
.ce81(sboxes_ce81),
.q81(sboxes_q81),
.address82(sboxes_address82),
.ce82(sboxes_ce82),
.q82(sboxes_q82),
.address83(sboxes_address83),
.ce83(sboxes_ce83),
.q83(sboxes_q83),
.address84(sboxes_address84),
.ce84(sboxes_ce84),
.q84(sboxes_q84),
.address85(sboxes_address85),
.ce85(sboxes_ce85),
.q85(sboxes_q85),
.address86(sboxes_address86),
.ce86(sboxes_ce86),
.q86(sboxes_q86),
.address87(sboxes_address87),
.ce87(sboxes_ce87),
.q87(sboxes_q87),
.address88(sboxes_address88),
.ce88(sboxes_ce88),
.q88(sboxes_q88),
.address89(sboxes_address89),
.ce89(sboxes_ce89),
.q89(sboxes_q89),
.address90(sboxes_address90),
.ce90(sboxes_ce90),
.q90(sboxes_q90),
.address91(sboxes_address91),
.ce91(sboxes_ce91),
.q91(sboxes_q91),
.address92(sboxes_address92),
.ce92(sboxes_ce92),
.q92(sboxes_q92),
.address93(sboxes_address93),
.ce93(sboxes_ce93),
.q93(sboxes_q93),
.address94(sboxes_address94),
.ce94(sboxes_ce94),
.q94(sboxes_q94),
.address95(sboxes_address95),
.ce95(sboxes_ce95),
.q95(sboxes_q95),
.address96(sboxes_address96),
.ce96(sboxes_ce96),
.q96(sboxes_q96),
.address97(sboxes_address97),
.ce97(sboxes_ce97),
.q97(sboxes_q97),
.address98(sboxes_address98),
.ce98(sboxes_ce98),
.q98(sboxes_q98),
.address99(sboxes_address99),
.ce99(sboxes_ce99),
.q99(sboxes_q99),
.address100(sboxes_address100),
.ce100(sboxes_ce100),
.q100(sboxes_q100),
.address101(sboxes_address101),
.ce101(sboxes_ce101),
.q101(sboxes_q101),
.address102(sboxes_address102),
.ce102(sboxes_ce102),
.q102(sboxes_q102),
.address103(sboxes_address103),
.ce103(sboxes_ce103),
.q103(sboxes_q103),
.address104(sboxes_address104),
.ce104(sboxes_ce104),
.q104(sboxes_q104),
.address105(sboxes_address105),
.ce105(sboxes_ce105),
.q105(sboxes_q105),
.address106(sboxes_address106),
.ce106(sboxes_ce106),
.q106(sboxes_q106),
.address107(sboxes_address107),
.ce107(sboxes_ce107),
.q107(sboxes_q107),
.address108(sboxes_address108),
.ce108(sboxes_ce108),
.q108(sboxes_q108),
.address109(sboxes_address109),
.ce109(sboxes_ce109),
.q109(sboxes_q109),
.address110(sboxes_address110),
.ce110(sboxes_ce110),
.q110(sboxes_q110),
.address111(sboxes_address111),
.ce111(sboxes_ce111),
.q111(sboxes_q111),
.address112(sboxes_address112),
.ce112(sboxes_ce112),
.q112(sboxes_q112),
.address113(sboxes_address113),
.ce113(sboxes_ce113),
.q113(sboxes_q113),
.address114(sboxes_address114),
.ce114(sboxes_ce114),
.q114(sboxes_q114),
.address115(sboxes_address115),
.ce115(sboxes_ce115),
.q115(sboxes_q115),
.address116(sboxes_address116),
.ce116(sboxes_ce116),
.q116(sboxes_q116),
.address117(sboxes_address117),
.ce117(sboxes_ce117),
.q117(sboxes_q117),
.address118(sboxes_address118),
.ce118(sboxes_ce118),
.q118(sboxes_q118),
.address119(sboxes_address119),
.ce119(sboxes_ce119),
.q119(sboxes_q119),
.address120(sboxes_address120),
.ce120(sboxes_ce120),
.q120(sboxes_q120),
.address121(sboxes_address121),
.ce121(sboxes_ce121),
.q121(sboxes_q121),
.address122(sboxes_address122),
.ce122(sboxes_ce122),
.q122(sboxes_q122),
.address123(sboxes_address123),
.ce123(sboxes_ce123),
.q123(sboxes_q123),
.address124(sboxes_address124),
.ce124(sboxes_ce124),
.q124(sboxes_q124),
.address125(sboxes_address125),
.ce125(sboxes_ce125),
.q125(sboxes_q125),
.address126(sboxes_address126),
.ce126(sboxes_ce126),
.q126(sboxes_q126),
.address127(sboxes_address127),
.ce127(sboxes_ce127),
.q127(sboxes_q127),
.address128(sboxes_address128),
.ce128(sboxes_ce128),
.q128(sboxes_q128),
.address129(sboxes_address129),
.ce129(sboxes_ce129),
.q129(sboxes_q129),
.address130(sboxes_address130),
.ce130(sboxes_ce130),
.q130(sboxes_q130),
.address131(sboxes_address131),
.ce131(sboxes_ce131),
.q131(sboxes_q131),
.address132(sboxes_address132),
.ce132(sboxes_ce132),
.q132(sboxes_q132),
.address133(sboxes_address133),
.ce133(sboxes_ce133),
.q133(sboxes_q133),
.address134(sboxes_address134),
.ce134(sboxes_ce134),
.q134(sboxes_q134),
.address135(sboxes_address135),
.ce135(sboxes_ce135),
.q135(sboxes_q135),
.address136(sboxes_address136),
.ce136(sboxes_ce136),
.q136(sboxes_q136),
.address137(sboxes_address137),
.ce137(sboxes_ce137),
.q137(sboxes_q137),
.address138(sboxes_address138),
.ce138(sboxes_ce138),
.q138(sboxes_q138),
.address139(sboxes_address139),
.ce139(sboxes_ce139),
.q139(sboxes_q139),
.address140(sboxes_address140),
.ce140(sboxes_ce140),
.q140(sboxes_q140),
.address141(sboxes_address141),
.ce141(sboxes_ce141),
.q141(sboxes_q141),
.address142(sboxes_address142),
.ce142(sboxes_ce142),
.q142(sboxes_q142),
.address143(sboxes_address143),
.ce143(sboxes_ce143),
.q143(sboxes_q143),
.address144(sboxes_address144),
.ce144(sboxes_ce144),
.q144(sboxes_q144),
.address145(sboxes_address145),
.ce145(sboxes_ce145),
.q145(sboxes_q145),
.address146(sboxes_address146),
.ce146(sboxes_ce146),
.q146(sboxes_q146),
.address147(sboxes_address147),
.ce147(sboxes_ce147),
.q147(sboxes_q147),
.address148(sboxes_address148),
.ce148(sboxes_ce148),
.q148(sboxes_q148),
.address149(sboxes_address149),
.ce149(sboxes_ce149),
.q149(sboxes_q149),
.address150(sboxes_address150),
.ce150(sboxes_ce150),
.q150(sboxes_q150),
.address151(sboxes_address151),
.ce151(sboxes_ce151),
.q151(sboxes_q151),
.address152(sboxes_address152),
.ce152(sboxes_ce152),
.q152(sboxes_q152),
.address153(sboxes_address153),
.ce153(sboxes_ce153),
.q153(sboxes_q153),
.address154(sboxes_address154),
.ce154(sboxes_ce154),
.q154(sboxes_q154),
.address155(sboxes_address155),
.ce155(sboxes_ce155),
.q155(sboxes_q155),
.address156(sboxes_address156),
.ce156(sboxes_ce156),
.q156(sboxes_q156),
.address157(sboxes_address157),
.ce157(sboxes_ce157),
.q157(sboxes_q157),
.address158(sboxes_address158),
.ce158(sboxes_ce158),
.q158(sboxes_q158),
.address159(sboxes_address159),
.ce159(sboxes_ce159),
.q159(sboxes_q159),
.address160(sboxes_address160),
.ce160(sboxes_ce160),
.q160(sboxes_q160),
.address161(sboxes_address161),
.ce161(sboxes_ce161),
.q161(sboxes_q161),
.address162(sboxes_address162),
.ce162(sboxes_ce162),
.q162(sboxes_q162),
.address163(sboxes_address163),
.ce163(sboxes_ce163),
.q163(sboxes_q163),
.address164(sboxes_address164),
.ce164(sboxes_ce164),
.q164(sboxes_q164),
.address165(sboxes_address165),
.ce165(sboxes_ce165),
.q165(sboxes_q165),
.address166(sboxes_address166),
.ce166(sboxes_ce166),
.q166(sboxes_q166),
.address167(sboxes_address167),
.ce167(sboxes_ce167),
.q167(sboxes_q167),
.address168(sboxes_address168),
.ce168(sboxes_ce168),
.q168(sboxes_q168),
.address169(sboxes_address169),
.ce169(sboxes_ce169),
.q169(sboxes_q169),
.address170(sboxes_address170),
.ce170(sboxes_ce170),
.q170(sboxes_q170),
.address171(sboxes_address171),
.ce171(sboxes_ce171),
.q171(sboxes_q171),
.address172(sboxes_address172),
.ce172(sboxes_ce172),
.q172(sboxes_q172),
.address173(sboxes_address173),
.ce173(sboxes_ce173),
.q173(sboxes_q173),
.address174(sboxes_address174),
.ce174(sboxes_ce174),
.q174(sboxes_q174),
.address175(sboxes_address175),
.ce175(sboxes_ce175),
.q175(sboxes_q175),
.address176(sboxes_address176),
.ce176(sboxes_ce176),
.q176(sboxes_q176),
.address177(sboxes_address177),
.ce177(sboxes_ce177),
.q177(sboxes_q177),
.address178(sboxes_address178),
.ce178(sboxes_ce178),
.q178(sboxes_q178),
.address179(sboxes_address179),
.ce179(sboxes_ce179),
.q179(sboxes_q179),
.address180(sboxes_address180),
.ce180(sboxes_ce180),
.q180(sboxes_q180),
.address181(sboxes_address181),
.ce181(sboxes_ce181),
.q181(sboxes_q181),
.address182(sboxes_address182),
.ce182(sboxes_ce182),
.q182(sboxes_q182),
.address183(sboxes_address183),
.ce183(sboxes_ce183),
.q183(sboxes_q183),
.address184(sboxes_address184),
.ce184(sboxes_ce184),
.q184(sboxes_q184),
.address185(sboxes_address185),
.ce185(sboxes_ce185),
.q185(sboxes_q185),
.address186(sboxes_address186),
.ce186(sboxes_ce186),
.q186(sboxes_q186),
.address187(sboxes_address187),
.ce187(sboxes_ce187),
.q187(sboxes_q187),
.address188(sboxes_address188),
.ce188(sboxes_ce188),
.q188(sboxes_q188),
.address189(sboxes_address189),
.ce189(sboxes_ce189),
.q189(sboxes_q189),
.address190(sboxes_address190),
.ce190(sboxes_ce190),
.q190(sboxes_q190),
.address191(sboxes_address191),
.ce191(sboxes_ce191),
.q191(sboxes_q191),
.address192(sboxes_address192),
.ce192(sboxes_ce192),
.q192(sboxes_q192),
.address193(sboxes_address193),
.ce193(sboxes_ce193),
.q193(sboxes_q193),
.address194(sboxes_address194),
.ce194(sboxes_ce194),
.q194(sboxes_q194),
.address195(sboxes_address195),
.ce195(sboxes_ce195),
.q195(sboxes_q195),
.address196(sboxes_address196),
.ce196(sboxes_ce196),
.q196(sboxes_q196),
.address197(sboxes_address197),
.ce197(sboxes_ce197),
.q197(sboxes_q197),
.address198(sboxes_address198),
.ce198(sboxes_ce198),
.q198(sboxes_q198),
.address199(sboxes_address199),
.ce199(sboxes_ce199),
.q199(sboxes_q199)
);
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_pp0_stage0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter1 <= ap_start;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter10 <= 1'b0;
end else begin
if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter2 <= 1'b0;
end else begin
if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter3 <= 1'b0;
end else begin
if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter4 <= 1'b0;
end else begin
if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter5 <= 1'b0;
end else begin
if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter6 <= 1'b0;
end else begin
if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter7 <= 1'b0;
end else begin
if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter8 <= 1'b0;
end else begin
if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter9 <= 1'b0;
end else begin
if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
end
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
ap_reg_pp0_iter1_p_Result_1_11_reg_12485 <= p_Result_1_11_reg_12485;
ap_reg_pp0_iter1_p_Result_1_12_reg_12492 <= p_Result_1_12_reg_12492;
ap_reg_pp0_iter1_p_Result_1_13_reg_12499 <= p_Result_1_13_reg_12499;
ap_reg_pp0_iter1_p_Result_1_4_reg_12441 <= p_Result_1_4_reg_12441;
ap_reg_pp0_iter1_p_Result_1_5_reg_12447 <= p_Result_1_5_reg_12447;
ap_reg_pp0_iter1_p_Result_1_6_reg_12453 <= p_Result_1_6_reg_12453;
ap_reg_pp0_iter1_p_Result_1_7_reg_12459 <= p_Result_1_7_reg_12459;
ap_reg_pp0_iter1_tmp_100_reg_12506 <= tmp_100_reg_12506;
p_Result_1_10_reg_12480 <= {{key_V_read[39:32]}};
p_Result_1_11_reg_12485 <= {{key_V_read[31:24]}};
p_Result_1_12_reg_12492 <= {{key_V_read[23:16]}};
p_Result_1_13_reg_12499 <= {{key_V_read[15:8]}};
p_Result_1_1_reg_12426 <= {{key_V_read[119:112]}};
p_Result_1_2_reg_12431 <= {{key_V_read[111:104]}};
p_Result_1_3_reg_12436 <= {{key_V_read[103:96]}};
p_Result_1_4_reg_12441 <= {{key_V_read[95:88]}};
p_Result_1_5_reg_12447 <= {{key_V_read[87:80]}};
p_Result_1_6_reg_12453 <= {{key_V_read[79:72]}};
p_Result_1_7_reg_12459 <= {{key_V_read[71:64]}};
p_Result_1_8_reg_12465 <= {{key_V_read[63:56]}};
p_Result_1_9_reg_12470 <= {{key_V_read[55:48]}};
p_Result_1_reg_12421 <= {{key_V_read[127:120]}};
p_Result_1_s_reg_12475 <= {{key_V_read[47:40]}};
tmp_100_reg_12506 <= tmp_100_fu_2625_p1;
tmp_65_reg_12613 <= tmp_65_fu_3422_p2;
tmp_66_reg_12618 <= tmp_66_fu_3428_p2;
tmp_67_reg_12623 <= tmp_67_fu_3433_p2;
tmp_68_reg_12628 <= tmp_68_fu_3438_p2;
tmp_73_reg_12633 <= tmp_73_fu_3463_p2;
tmp_74_reg_12639 <= tmp_74_fu_3468_p2;
tmp_75_reg_12645 <= tmp_75_fu_3473_p2;
tmp_76_reg_12651 <= tmp_76_fu_3478_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
ap_reg_pp0_iter2_p_Result_1_11_reg_12485 <= ap_reg_pp0_iter1_p_Result_1_11_reg_12485;
ap_reg_pp0_iter2_p_Result_1_12_reg_12492 <= ap_reg_pp0_iter1_p_Result_1_12_reg_12492;
ap_reg_pp0_iter2_p_Result_1_13_reg_12499 <= ap_reg_pp0_iter1_p_Result_1_13_reg_12499;
ap_reg_pp0_iter2_tmp_100_reg_12506 <= ap_reg_pp0_iter1_tmp_100_reg_12506;
ap_reg_pp0_iter2_tmp_73_reg_12633 <= tmp_73_reg_12633;
ap_reg_pp0_iter2_tmp_74_reg_12639 <= tmp_74_reg_12639;
ap_reg_pp0_iter2_tmp_75_reg_12645 <= tmp_75_reg_12645;
ap_reg_pp0_iter2_tmp_76_reg_12651 <= tmp_76_reg_12651;
ap_reg_pp0_iter3_p_Result_1_11_reg_12485 <= ap_reg_pp0_iter2_p_Result_1_11_reg_12485;
ap_reg_pp0_iter3_p_Result_1_12_reg_12492 <= ap_reg_pp0_iter2_p_Result_1_12_reg_12492;
ap_reg_pp0_iter3_p_Result_1_13_reg_12499 <= ap_reg_pp0_iter2_p_Result_1_13_reg_12499;
ap_reg_pp0_iter3_tmp_100_reg_12506 <= ap_reg_pp0_iter2_tmp_100_reg_12506;
ap_reg_pp0_iter3_tmp_69_1_reg_12777 <= tmp_69_1_reg_12777;
ap_reg_pp0_iter3_tmp_70_1_reg_12783 <= tmp_70_1_reg_12783;
ap_reg_pp0_iter3_tmp_71_1_reg_12789 <= tmp_71_1_reg_12789;
ap_reg_pp0_iter3_tmp_72_1_reg_12795 <= tmp_72_1_reg_12795;
ap_reg_pp0_iter4_tmp_73_2_reg_12941 <= tmp_73_2_reg_12941;
ap_reg_pp0_iter4_tmp_74_2_reg_12947 <= tmp_74_2_reg_12947;
ap_reg_pp0_iter4_tmp_75_2_reg_12953 <= tmp_75_2_reg_12953;
ap_reg_pp0_iter4_tmp_76_2_reg_12959 <= tmp_76_2_reg_12959;
ap_reg_pp0_iter5_tmp_69_3_reg_13085 <= tmp_69_3_reg_13085;
ap_reg_pp0_iter5_tmp_70_3_reg_13091 <= tmp_70_3_reg_13091;
ap_reg_pp0_iter5_tmp_71_3_reg_13097 <= tmp_71_3_reg_13097;
ap_reg_pp0_iter5_tmp_72_3_reg_13103 <= tmp_72_3_reg_13103;
ap_reg_pp0_iter5_tmp_77_3_reg_13109 <= tmp_77_3_reg_13109;
ap_reg_pp0_iter5_tmp_78_3_reg_13116 <= tmp_78_3_reg_13116;
ap_reg_pp0_iter5_tmp_79_3_reg_13123 <= tmp_79_3_reg_13123;
ap_reg_pp0_iter5_tmp_80_3_reg_13130 <= tmp_80_3_reg_13130;
ap_reg_pp0_iter6_tmp_73_4_reg_13257 <= tmp_73_4_reg_13257;
ap_reg_pp0_iter6_tmp_74_4_reg_13263 <= tmp_74_4_reg_13263;
ap_reg_pp0_iter6_tmp_75_4_reg_13269 <= tmp_75_4_reg_13269;
ap_reg_pp0_iter6_tmp_76_4_reg_13275 <= tmp_76_4_reg_13275;
ap_reg_pp0_iter6_tmp_77_3_reg_13109 <= ap_reg_pp0_iter5_tmp_77_3_reg_13109;
ap_reg_pp0_iter6_tmp_78_3_reg_13116 <= ap_reg_pp0_iter5_tmp_78_3_reg_13116;
ap_reg_pp0_iter6_tmp_79_3_reg_13123 <= ap_reg_pp0_iter5_tmp_79_3_reg_13123;
ap_reg_pp0_iter6_tmp_80_3_reg_13130 <= ap_reg_pp0_iter5_tmp_80_3_reg_13130;
ap_reg_pp0_iter7_tmp_69_5_reg_13401 <= tmp_69_5_reg_13401;
ap_reg_pp0_iter7_tmp_70_5_reg_13407 <= tmp_70_5_reg_13407;
ap_reg_pp0_iter7_tmp_71_5_reg_13413 <= tmp_71_5_reg_13413;
ap_reg_pp0_iter7_tmp_72_5_reg_13419 <= tmp_72_5_reg_13419;
ap_reg_pp0_iter7_tmp_77_3_reg_13109 <= ap_reg_pp0_iter6_tmp_77_3_reg_13109;
ap_reg_pp0_iter7_tmp_78_3_reg_13116 <= ap_reg_pp0_iter6_tmp_78_3_reg_13116;
ap_reg_pp0_iter7_tmp_79_3_reg_13123 <= ap_reg_pp0_iter6_tmp_79_3_reg_13123;
ap_reg_pp0_iter7_tmp_80_3_reg_13130 <= ap_reg_pp0_iter6_tmp_80_3_reg_13130;
ap_reg_pp0_iter8_tmp_73_6_reg_13565 <= tmp_73_6_reg_13565;
ap_reg_pp0_iter8_tmp_74_6_reg_13571 <= tmp_74_6_reg_13571;
ap_reg_pp0_iter8_tmp_75_6_reg_13577 <= tmp_75_6_reg_13577;
ap_reg_pp0_iter8_tmp_76_6_reg_13583 <= tmp_76_6_reg_13583;
ap_reg_pp0_iter9_tmp_69_7_reg_13709 <= tmp_69_7_reg_13709;
ap_reg_pp0_iter9_tmp_70_7_reg_13715 <= tmp_70_7_reg_13715;
ap_reg_pp0_iter9_tmp_71_7_reg_13721 <= tmp_71_7_reg_13721;
ap_reg_pp0_iter9_tmp_72_7_reg_13727 <= tmp_72_7_reg_13727;
ap_reg_pp0_iter9_tmp_77_7_reg_13733 <= tmp_77_7_reg_13733;
ap_reg_pp0_iter9_tmp_78_7_reg_13739 <= tmp_78_7_reg_13739;
ap_reg_pp0_iter9_tmp_79_7_reg_13745 <= tmp_79_7_reg_13745;
ap_reg_pp0_iter9_tmp_80_7_reg_13751 <= tmp_80_7_reg_13751;
tmp_65_1_reg_12757 <= tmp_65_1_fu_4465_p2;
tmp_65_2_reg_12921 <= tmp_65_2_fu_5506_p2;
tmp_65_3_reg_13065 <= tmp_65_3_fu_6549_p2;
tmp_65_4_reg_13237 <= tmp_65_4_fu_7590_p2;
tmp_65_5_reg_13381 <= tmp_65_5_fu_8633_p2;
tmp_65_6_reg_13545 <= tmp_65_6_fu_9674_p2;
tmp_65_7_reg_13689 <= tmp_65_7_fu_10717_p2;
tmp_65_8_reg_13857 <= tmp_65_8_fu_11758_p2;
tmp_66_1_reg_12762 <= tmp_66_1_fu_4470_p2;
tmp_66_2_reg_12926 <= tmp_66_2_fu_5512_p2;
tmp_66_3_reg_13070 <= tmp_66_3_fu_6554_p2;
tmp_66_4_reg_13242 <= tmp_66_4_fu_7596_p2;
tmp_66_5_reg_13386 <= tmp_66_5_fu_8638_p2;
tmp_66_6_reg_13550 <= tmp_66_6_fu_9680_p2;
tmp_66_7_reg_13694 <= tmp_66_7_fu_10722_p2;
tmp_66_8_reg_13862 <= tmp_66_8_fu_11764_p2;
tmp_67_1_reg_12767 <= tmp_67_1_fu_4475_p2;
tmp_67_2_reg_12931 <= tmp_67_2_fu_5517_p2;
tmp_67_3_reg_13075 <= tmp_67_3_fu_6559_p2;
tmp_67_4_reg_13247 <= tmp_67_4_fu_7601_p2;
tmp_67_5_reg_13391 <= tmp_67_5_fu_8643_p2;
tmp_67_6_reg_13555 <= tmp_67_6_fu_9685_p2;
tmp_67_7_reg_13699 <= tmp_67_7_fu_10727_p2;
tmp_67_8_reg_13867 <= tmp_67_8_fu_11769_p2;
tmp_68_1_reg_12772 <= tmp_68_1_fu_4480_p2;
tmp_68_2_reg_12936 <= tmp_68_2_fu_5522_p2;
tmp_68_3_reg_13080 <= tmp_68_3_fu_6564_p2;
tmp_68_4_reg_13252 <= tmp_68_4_fu_7606_p2;
tmp_68_5_reg_13396 <= tmp_68_5_fu_8648_p2;
tmp_68_6_reg_13560 <= tmp_68_6_fu_9690_p2;
tmp_68_7_reg_13704 <= tmp_68_7_fu_10732_p2;
tmp_68_8_reg_13872 <= tmp_68_8_fu_11774_p2;
tmp_69_1_reg_12777 <= tmp_69_1_fu_4485_p2;
tmp_69_3_reg_13085 <= tmp_69_3_fu_6569_p2;
tmp_69_5_reg_13401 <= tmp_69_5_fu_8653_p2;
tmp_69_7_reg_13709 <= tmp_69_7_fu_10737_p2;
tmp_70_1_reg_12783 <= tmp_70_1_fu_4490_p2;
tmp_70_3_reg_13091 <= tmp_70_3_fu_6574_p2;
tmp_70_5_reg_13407 <= tmp_70_5_fu_8658_p2;
tmp_70_7_reg_13715 <= tmp_70_7_fu_10742_p2;
tmp_71_1_reg_12789 <= tmp_71_1_fu_4495_p2;
tmp_71_3_reg_13097 <= tmp_71_3_fu_6579_p2;
tmp_71_5_reg_13413 <= tmp_71_5_fu_8663_p2;
tmp_71_7_reg_13721 <= tmp_71_7_fu_10747_p2;
tmp_72_1_reg_12795 <= tmp_72_1_fu_4500_p2;
tmp_72_3_reg_13103 <= tmp_72_3_fu_6584_p2;
tmp_72_5_reg_13419 <= tmp_72_5_fu_8668_p2;
tmp_72_7_reg_13727 <= tmp_72_7_fu_10752_p2;
tmp_73_2_reg_12941 <= tmp_73_2_fu_5527_p2;
tmp_73_4_reg_13257 <= tmp_73_4_fu_7611_p2;
tmp_73_6_reg_13565 <= tmp_73_6_fu_9695_p2;
tmp_73_8_reg_13877 <= tmp_73_8_fu_11779_p2;
tmp_74_2_reg_12947 <= tmp_74_2_fu_5532_p2;
tmp_74_4_reg_13263 <= tmp_74_4_fu_7616_p2;
tmp_74_6_reg_13571 <= tmp_74_6_fu_9700_p2;
tmp_74_8_reg_13882 <= tmp_74_8_fu_11784_p2;
tmp_75_2_reg_12953 <= tmp_75_2_fu_5537_p2;
tmp_75_4_reg_13269 <= tmp_75_4_fu_7621_p2;
tmp_75_6_reg_13577 <= tmp_75_6_fu_9705_p2;
tmp_75_8_reg_13887 <= tmp_75_8_fu_11789_p2;
tmp_76_2_reg_12959 <= tmp_76_2_fu_5542_p2;
tmp_76_4_reg_13275 <= tmp_76_4_fu_7626_p2;
tmp_76_6_reg_13583 <= tmp_76_6_fu_9710_p2;
tmp_76_8_reg_13892 <= tmp_76_8_fu_11794_p2;
tmp_77_1_reg_12801 <= tmp_77_1_fu_4505_p2;
tmp_77_3_reg_13109 <= tmp_77_3_fu_6589_p2;
tmp_77_5_reg_13425 <= tmp_77_5_fu_8673_p2;
tmp_77_7_reg_13733 <= tmp_77_7_fu_10757_p2;
tmp_78_1_reg_12806 <= tmp_78_1_fu_4510_p2;
tmp_78_3_reg_13116 <= tmp_78_3_fu_6594_p2;
tmp_78_5_reg_13430 <= tmp_78_5_fu_8678_p2;
tmp_78_7_reg_13739 <= tmp_78_7_fu_10762_p2;
tmp_79_1_reg_12811 <= tmp_79_1_fu_4515_p2;
tmp_79_3_reg_13123 <= tmp_79_3_fu_6599_p2;
tmp_79_5_reg_13435 <= tmp_79_5_fu_8683_p2;
tmp_79_7_reg_13745 <= tmp_79_7_fu_10767_p2;
tmp_80_1_reg_12816 <= tmp_80_1_fu_4520_p2;
tmp_80_3_reg_13130 <= tmp_80_3_fu_6604_p2;
tmp_80_5_reg_13440 <= tmp_80_5_fu_8688_p2;
tmp_80_7_reg_13751 <= tmp_80_7_fu_10772_p2;
end
end
always @ (*) begin
if ((((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00000000 == 1'b0)) | ((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter10)))) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_idle_pp0))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter1) & (1'b0 == ap_enable_reg_pp0_iter2) & (1'b0 == ap_enable_reg_pp0_iter3) & (1'b0 == ap_enable_reg_pp0_iter4) & (1'b0 == ap_enable_reg_pp0_iter5) & (1'b0 == ap_enable_reg_pp0_iter6) & (1'b0 == ap_enable_reg_pp0_iter7) & (1'b0 == ap_enable_reg_pp0_iter8) & (1'b0 == ap_enable_reg_pp0_iter9) & (1'b0 == ap_enable_reg_pp0_iter10))) begin
ap_idle_pp0 = 1'b1;
end else begin
ap_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter1) & (1'b0 == ap_enable_reg_pp0_iter2) & (1'b0 == ap_enable_reg_pp0_iter3) & (1'b0 == ap_enable_reg_pp0_iter4) & (1'b0 == ap_enable_reg_pp0_iter5) & (1'b0 == ap_enable_reg_pp0_iter6) & (1'b0 == ap_enable_reg_pp0_iter7) & (1'b0 == ap_enable_reg_pp0_iter8) & (1'b0 == ap_enable_reg_pp0_iter9))) begin
ap_idle_pp0_0to9 = 1'b1;
end else begin
ap_idle_pp0_0to9 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_idle_pp0_0to9))) begin
ap_reset_idle_pp0 = 1'b1;
end else begin
ap_reset_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_idle_pp0_0to9) & (1'b1 == ap_start))) begin
ap_reset_start_pp0 = 1'b1;
end else begin
ap_reset_start_pp0 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce0 = 1'b1;
end else begin
sboxes_ce0 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce1 = 1'b1;
end else begin
sboxes_ce1 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce10 = 1'b1;
end else begin
sboxes_ce10 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce100 = 1'b1;
end else begin
sboxes_ce100 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce101 = 1'b1;
end else begin
sboxes_ce101 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce102 = 1'b1;
end else begin
sboxes_ce102 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce103 = 1'b1;
end else begin
sboxes_ce103 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce104 = 1'b1;
end else begin
sboxes_ce104 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce105 = 1'b1;
end else begin
sboxes_ce105 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce106 = 1'b1;
end else begin
sboxes_ce106 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce107 = 1'b1;
end else begin
sboxes_ce107 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce108 = 1'b1;
end else begin
sboxes_ce108 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce109 = 1'b1;
end else begin
sboxes_ce109 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce11 = 1'b1;
end else begin
sboxes_ce11 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce110 = 1'b1;
end else begin
sboxes_ce110 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce111 = 1'b1;
end else begin
sboxes_ce111 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce112 = 1'b1;
end else begin
sboxes_ce112 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce113 = 1'b1;
end else begin
sboxes_ce113 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce114 = 1'b1;
end else begin
sboxes_ce114 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce115 = 1'b1;
end else begin
sboxes_ce115 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce116 = 1'b1;
end else begin
sboxes_ce116 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce117 = 1'b1;
end else begin
sboxes_ce117 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce118 = 1'b1;
end else begin
sboxes_ce118 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce119 = 1'b1;
end else begin
sboxes_ce119 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce12 = 1'b1;
end else begin
sboxes_ce12 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce120 = 1'b1;
end else begin
sboxes_ce120 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce121 = 1'b1;
end else begin
sboxes_ce121 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce122 = 1'b1;
end else begin
sboxes_ce122 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce123 = 1'b1;
end else begin
sboxes_ce123 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce124 = 1'b1;
end else begin
sboxes_ce124 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce125 = 1'b1;
end else begin
sboxes_ce125 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce126 = 1'b1;
end else begin
sboxes_ce126 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce127 = 1'b1;
end else begin
sboxes_ce127 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce128 = 1'b1;
end else begin
sboxes_ce128 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce129 = 1'b1;
end else begin
sboxes_ce129 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce13 = 1'b1;
end else begin
sboxes_ce13 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce130 = 1'b1;
end else begin
sboxes_ce130 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce131 = 1'b1;
end else begin
sboxes_ce131 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce132 = 1'b1;
end else begin
sboxes_ce132 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce133 = 1'b1;
end else begin
sboxes_ce133 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce134 = 1'b1;
end else begin
sboxes_ce134 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce135 = 1'b1;
end else begin
sboxes_ce135 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce136 = 1'b1;
end else begin
sboxes_ce136 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce137 = 1'b1;
end else begin
sboxes_ce137 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce138 = 1'b1;
end else begin
sboxes_ce138 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce139 = 1'b1;
end else begin
sboxes_ce139 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce14 = 1'b1;
end else begin
sboxes_ce14 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce140 = 1'b1;
end else begin
sboxes_ce140 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce141 = 1'b1;
end else begin
sboxes_ce141 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce142 = 1'b1;
end else begin
sboxes_ce142 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce143 = 1'b1;
end else begin
sboxes_ce143 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce144 = 1'b1;
end else begin
sboxes_ce144 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce145 = 1'b1;
end else begin
sboxes_ce145 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce146 = 1'b1;
end else begin
sboxes_ce146 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce147 = 1'b1;
end else begin
sboxes_ce147 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce148 = 1'b1;
end else begin
sboxes_ce148 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce149 = 1'b1;
end else begin
sboxes_ce149 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce15 = 1'b1;
end else begin
sboxes_ce15 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce150 = 1'b1;
end else begin
sboxes_ce150 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce151 = 1'b1;
end else begin
sboxes_ce151 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce152 = 1'b1;
end else begin
sboxes_ce152 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce153 = 1'b1;
end else begin
sboxes_ce153 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce154 = 1'b1;
end else begin
sboxes_ce154 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce155 = 1'b1;
end else begin
sboxes_ce155 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce156 = 1'b1;
end else begin
sboxes_ce156 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce157 = 1'b1;
end else begin
sboxes_ce157 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce158 = 1'b1;
end else begin
sboxes_ce158 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce159 = 1'b1;
end else begin
sboxes_ce159 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce16 = 1'b1;
end else begin
sboxes_ce16 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce160 = 1'b1;
end else begin
sboxes_ce160 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce161 = 1'b1;
end else begin
sboxes_ce161 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce162 = 1'b1;
end else begin
sboxes_ce162 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce163 = 1'b1;
end else begin
sboxes_ce163 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce164 = 1'b1;
end else begin
sboxes_ce164 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce165 = 1'b1;
end else begin
sboxes_ce165 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce166 = 1'b1;
end else begin
sboxes_ce166 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce167 = 1'b1;
end else begin
sboxes_ce167 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce168 = 1'b1;
end else begin
sboxes_ce168 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce169 = 1'b1;
end else begin
sboxes_ce169 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce17 = 1'b1;
end else begin
sboxes_ce17 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce170 = 1'b1;
end else begin
sboxes_ce170 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce171 = 1'b1;
end else begin
sboxes_ce171 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce172 = 1'b1;
end else begin
sboxes_ce172 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce173 = 1'b1;
end else begin
sboxes_ce173 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce174 = 1'b1;
end else begin
sboxes_ce174 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce175 = 1'b1;
end else begin
sboxes_ce175 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce176 = 1'b1;
end else begin
sboxes_ce176 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce177 = 1'b1;
end else begin
sboxes_ce177 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce178 = 1'b1;
end else begin
sboxes_ce178 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce179 = 1'b1;
end else begin
sboxes_ce179 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce18 = 1'b1;
end else begin
sboxes_ce18 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce180 = 1'b1;
end else begin
sboxes_ce180 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce181 = 1'b1;
end else begin
sboxes_ce181 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce182 = 1'b1;
end else begin
sboxes_ce182 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce183 = 1'b1;
end else begin
sboxes_ce183 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce184 = 1'b1;
end else begin
sboxes_ce184 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce185 = 1'b1;
end else begin
sboxes_ce185 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce186 = 1'b1;
end else begin
sboxes_ce186 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce187 = 1'b1;
end else begin
sboxes_ce187 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce188 = 1'b1;
end else begin
sboxes_ce188 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce189 = 1'b1;
end else begin
sboxes_ce189 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce19 = 1'b1;
end else begin
sboxes_ce19 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce190 = 1'b1;
end else begin
sboxes_ce190 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce191 = 1'b1;
end else begin
sboxes_ce191 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce192 = 1'b1;
end else begin
sboxes_ce192 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce193 = 1'b1;
end else begin
sboxes_ce193 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce194 = 1'b1;
end else begin
sboxes_ce194 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce195 = 1'b1;
end else begin
sboxes_ce195 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce196 = 1'b1;
end else begin
sboxes_ce196 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce197 = 1'b1;
end else begin
sboxes_ce197 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce198 = 1'b1;
end else begin
sboxes_ce198 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce199 = 1'b1;
end else begin
sboxes_ce199 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce2 = 1'b1;
end else begin
sboxes_ce2 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce20 = 1'b1;
end else begin
sboxes_ce20 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce21 = 1'b1;
end else begin
sboxes_ce21 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce22 = 1'b1;
end else begin
sboxes_ce22 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce23 = 1'b1;
end else begin
sboxes_ce23 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce24 = 1'b1;
end else begin
sboxes_ce24 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce25 = 1'b1;
end else begin
sboxes_ce25 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce26 = 1'b1;
end else begin
sboxes_ce26 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce27 = 1'b1;
end else begin
sboxes_ce27 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce28 = 1'b1;
end else begin
sboxes_ce28 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce29 = 1'b1;
end else begin
sboxes_ce29 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce3 = 1'b1;
end else begin
sboxes_ce3 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce30 = 1'b1;
end else begin
sboxes_ce30 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce31 = 1'b1;
end else begin
sboxes_ce31 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce32 = 1'b1;
end else begin
sboxes_ce32 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce33 = 1'b1;
end else begin
sboxes_ce33 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce34 = 1'b1;
end else begin
sboxes_ce34 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce35 = 1'b1;
end else begin
sboxes_ce35 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce36 = 1'b1;
end else begin
sboxes_ce36 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce37 = 1'b1;
end else begin
sboxes_ce37 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce38 = 1'b1;
end else begin
sboxes_ce38 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce39 = 1'b1;
end else begin
sboxes_ce39 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce4 = 1'b1;
end else begin
sboxes_ce4 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce40 = 1'b1;
end else begin
sboxes_ce40 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce41 = 1'b1;
end else begin
sboxes_ce41 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce42 = 1'b1;
end else begin
sboxes_ce42 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce43 = 1'b1;
end else begin
sboxes_ce43 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce44 = 1'b1;
end else begin
sboxes_ce44 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce45 = 1'b1;
end else begin
sboxes_ce45 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce46 = 1'b1;
end else begin
sboxes_ce46 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce47 = 1'b1;
end else begin
sboxes_ce47 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce48 = 1'b1;
end else begin
sboxes_ce48 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce49 = 1'b1;
end else begin
sboxes_ce49 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce5 = 1'b1;
end else begin
sboxes_ce5 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce50 = 1'b1;
end else begin
sboxes_ce50 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce51 = 1'b1;
end else begin
sboxes_ce51 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce52 = 1'b1;
end else begin
sboxes_ce52 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce53 = 1'b1;
end else begin
sboxes_ce53 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce54 = 1'b1;
end else begin
sboxes_ce54 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce55 = 1'b1;
end else begin
sboxes_ce55 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce56 = 1'b1;
end else begin
sboxes_ce56 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce57 = 1'b1;
end else begin
sboxes_ce57 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce58 = 1'b1;
end else begin
sboxes_ce58 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce59 = 1'b1;
end else begin
sboxes_ce59 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce6 = 1'b1;
end else begin
sboxes_ce6 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce60 = 1'b1;
end else begin
sboxes_ce60 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce61 = 1'b1;
end else begin
sboxes_ce61 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce62 = 1'b1;
end else begin
sboxes_ce62 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce63 = 1'b1;
end else begin
sboxes_ce63 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce64 = 1'b1;
end else begin
sboxes_ce64 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce65 = 1'b1;
end else begin
sboxes_ce65 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce66 = 1'b1;
end else begin
sboxes_ce66 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce67 = 1'b1;
end else begin
sboxes_ce67 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce68 = 1'b1;
end else begin
sboxes_ce68 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce69 = 1'b1;
end else begin
sboxes_ce69 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce7 = 1'b1;
end else begin
sboxes_ce7 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce70 = 1'b1;
end else begin
sboxes_ce70 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce71 = 1'b1;
end else begin
sboxes_ce71 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce72 = 1'b1;
end else begin
sboxes_ce72 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce73 = 1'b1;
end else begin
sboxes_ce73 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce74 = 1'b1;
end else begin
sboxes_ce74 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce75 = 1'b1;
end else begin
sboxes_ce75 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce76 = 1'b1;
end else begin
sboxes_ce76 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce77 = 1'b1;
end else begin
sboxes_ce77 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce78 = 1'b1;
end else begin
sboxes_ce78 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce79 = 1'b1;
end else begin
sboxes_ce79 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce8 = 1'b1;
end else begin
sboxes_ce8 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce80 = 1'b1;
end else begin
sboxes_ce80 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce81 = 1'b1;
end else begin
sboxes_ce81 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce82 = 1'b1;
end else begin
sboxes_ce82 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce83 = 1'b1;
end else begin
sboxes_ce83 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce84 = 1'b1;
end else begin
sboxes_ce84 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce85 = 1'b1;
end else begin
sboxes_ce85 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce86 = 1'b1;
end else begin
sboxes_ce86 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce87 = 1'b1;
end else begin
sboxes_ce87 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce88 = 1'b1;
end else begin
sboxes_ce88 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce89 = 1'b1;
end else begin
sboxes_ce89 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce9 = 1'b1;
end else begin
sboxes_ce9 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce90 = 1'b1;
end else begin
sboxes_ce90 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce91 = 1'b1;
end else begin
sboxes_ce91 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce92 = 1'b1;
end else begin
sboxes_ce92 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce93 = 1'b1;
end else begin
sboxes_ce93 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce94 = 1'b1;
end else begin
sboxes_ce94 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce95 = 1'b1;
end else begin
sboxes_ce95 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce96 = 1'b1;
end else begin
sboxes_ce96 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce97 = 1'b1;
end else begin
sboxes_ce97 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce98 = 1'b1;
end else begin
sboxes_ce98 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce99 = 1'b1;
end else begin
sboxes_ce99 = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_pp0_stage0 : begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0];
assign ap_block_pp0_stage0_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage0_flag00011001 = ((1'b0 == ap_start) & (1'b1 == ap_start));
end
always @ (*) begin
ap_block_pp0_stage0_flag00011011 = (((1'b0 == ap_start) & (1'b1 == ap_start)) | (ap_ce == 1'b0));
end
assign ap_block_state10_pp0_stage0_iter9 = ~(1'b1 == 1'b1);
assign ap_block_state11_pp0_stage0_iter10 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state1_pp0_stage0_iter0 = (1'b0 == ap_start);
end
assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state3_pp0_stage0_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state4_pp0_stage0_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state5_pp0_stage0_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state6_pp0_stage0_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state7_pp0_stage0_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state8_pp0_stage0_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state9_pp0_stage0_iter8 = ~(1'b1 == 1'b1);
assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
assign ap_enable_reg_pp0_iter0 = ap_start;
assign ap_return = {{{{{{{{{{{{{{{{tmp_38_fu_12234_p2}, {tmp_38_1_fu_12245_p2}}, {tmp_38_2_fu_12256_p2}}, {tmp_38_3_fu_12267_p2}}, {tmp_38_4_fu_12273_p2}}, {tmp_38_5_fu_12279_p2}}, {tmp_38_6_fu_12285_p2}}, {tmp_38_7_fu_12291_p2}}, {tmp_38_8_fu_12302_p2}}, {tmp_38_9_fu_12313_p2}}, {tmp_38_s_fu_12324_p2}}, {tmp_38_10_fu_12335_p2}}, {tmp_38_11_fu_12346_p2}}, {tmp_38_12_fu_12357_p2}}, {tmp_38_13_fu_12368_p2}}, {tmp_38_14_fu_12379_p2}};
assign e_0_1_fu_2985_p2 = (sboxes_q3 ^ tmp_47_0_1_fu_2979_p2);
assign e_0_2_fu_3133_p2 = (sboxes_q7 ^ tmp_47_0_2_fu_3127_p2);
assign e_0_3_fu_3281_p2 = (sboxes_q11 ^ tmp_47_0_3_fu_3275_p2);
assign e_1_1_fu_4027_p2 = (sboxes_q23 ^ tmp_47_1_1_fu_4021_p2);
assign e_1_2_fu_4175_p2 = (sboxes_q27 ^ tmp_47_1_2_fu_4169_p2);
assign e_1_3_fu_4323_p2 = (sboxes_q31 ^ tmp_47_1_3_fu_4317_p2);
assign e_1_fu_3879_p2 = (sboxes_q35 ^ tmp_47_1_fu_3873_p2);
assign e_2_1_fu_5069_p2 = (sboxes_q43 ^ tmp_47_2_1_fu_5063_p2);
assign e_2_2_fu_5217_p2 = (sboxes_q47 ^ tmp_47_2_2_fu_5211_p2);
assign e_2_3_fu_5365_p2 = (sboxes_q51 ^ tmp_47_2_3_fu_5359_p2);
assign e_2_fu_4921_p2 = (sboxes_q55 ^ tmp_47_2_fu_4915_p2);
assign e_3_1_fu_6111_p2 = (sboxes_q63 ^ tmp_47_3_1_fu_6105_p2);
assign e_3_2_fu_6259_p2 = (sboxes_q67 ^ tmp_47_3_2_fu_6253_p2);
assign e_3_3_fu_6407_p2 = (sboxes_q71 ^ tmp_47_3_3_fu_6401_p2);
assign e_3_fu_5963_p2 = (sboxes_q75 ^ tmp_47_3_fu_5957_p2);
assign e_4_1_fu_7153_p2 = (sboxes_q83 ^ tmp_47_4_1_fu_7147_p2);
assign e_4_2_fu_7301_p2 = (sboxes_q87 ^ tmp_47_4_2_fu_7295_p2);
assign e_4_3_fu_7449_p2 = (sboxes_q91 ^ tmp_47_4_3_fu_7443_p2);
assign e_4_fu_7005_p2 = (sboxes_q95 ^ tmp_47_4_fu_6999_p2);
assign e_5_1_fu_8195_p2 = (sboxes_q103 ^ tmp_47_5_1_fu_8189_p2);
assign e_5_2_fu_8343_p2 = (sboxes_q107 ^ tmp_47_5_2_fu_8337_p2);
assign e_5_3_fu_8491_p2 = (sboxes_q111 ^ tmp_47_5_3_fu_8485_p2);
assign e_5_fu_8047_p2 = (sboxes_q115 ^ tmp_47_5_fu_8041_p2);
assign e_6_1_fu_9237_p2 = (sboxes_q123 ^ tmp_47_6_1_fu_9231_p2);
assign e_6_2_fu_9385_p2 = (sboxes_q127 ^ tmp_47_6_2_fu_9379_p2);
assign e_6_3_fu_9533_p2 = (sboxes_q131 ^ tmp_47_6_3_fu_9527_p2);
assign e_6_fu_9089_p2 = (sboxes_q135 ^ tmp_47_6_fu_9083_p2);
assign e_7_1_fu_10279_p2 = (sboxes_q143 ^ tmp_47_7_1_fu_10273_p2);
assign e_7_2_fu_10427_p2 = (sboxes_q147 ^ tmp_47_7_2_fu_10421_p2);
assign e_7_3_fu_10575_p2 = (sboxes_q151 ^ tmp_47_7_3_fu_10569_p2);
assign e_7_fu_10131_p2 = (sboxes_q155 ^ tmp_47_7_fu_10125_p2);
assign e_8_1_fu_11321_p2 = (sboxes_q163 ^ tmp_47_8_1_fu_11315_p2);
assign e_8_2_fu_11469_p2 = (sboxes_q167 ^ tmp_47_8_2_fu_11463_p2);
assign e_8_3_fu_11617_p2 = (sboxes_q171 ^ tmp_47_8_3_fu_11611_p2);
assign e_8_fu_11173_p2 = (sboxes_q175 ^ tmp_47_8_fu_11167_p2);
assign e_fu_2837_p2 = (sboxes_q15 ^ tmp_47_fu_2831_p2);
assign p_Result_10_fu_2521_p4 = {{inptext_V_read[47:40]}};
assign p_Result_11_fu_2541_p4 = {{inptext_V_read[39:32]}};
assign p_Result_12_fu_2561_p4 = {{inptext_V_read[31:24]}};
assign p_Result_13_fu_2581_p4 = {{inptext_V_read[23:16]}};
assign p_Result_14_fu_2601_p4 = {{inptext_V_read[15:8]}};
assign p_Result_1_10_fu_2551_p4 = {{key_V_read[39:32]}};
assign p_Result_1_11_fu_2571_p4 = {{key_V_read[31:24]}};
assign p_Result_1_12_fu_2591_p4 = {{key_V_read[23:16]}};
assign p_Result_1_13_fu_2611_p4 = {{key_V_read[15:8]}};
assign p_Result_1_1_fu_2351_p4 = {{key_V_read[119:112]}};
assign p_Result_1_2_fu_2371_p4 = {{key_V_read[111:104]}};
assign p_Result_1_3_fu_2391_p4 = {{key_V_read[103:96]}};
assign p_Result_1_4_fu_2411_p4 = {{key_V_read[95:88]}};
assign p_Result_1_5_fu_2431_p4 = {{key_V_read[87:80]}};
assign p_Result_1_6_fu_2451_p4 = {{key_V_read[79:72]}};
assign p_Result_1_7_fu_2471_p4 = {{key_V_read[71:64]}};
assign p_Result_1_8_fu_2491_p4 = {{key_V_read[63:56]}};
assign p_Result_1_9_fu_2511_p4 = {{key_V_read[55:48]}};
assign p_Result_1_fu_2331_p4 = {{key_V_read[127:120]}};
assign p_Result_1_s_fu_2531_p4 = {{key_V_read[47:40]}};
assign p_Result_2_fu_2361_p4 = {{inptext_V_read[111:104]}};
assign p_Result_3_fu_2381_p4 = {{inptext_V_read[103:96]}};
assign p_Result_4_fu_2401_p4 = {{inptext_V_read[95:88]}};
assign p_Result_5_fu_2421_p4 = {{inptext_V_read[87:80]}};
assign p_Result_6_fu_2441_p4 = {{inptext_V_read[79:72]}};
assign p_Result_7_fu_2461_p4 = {{inptext_V_read[71:64]}};
assign p_Result_8_fu_2481_p4 = {{inptext_V_read[63:56]}};
assign p_Result_9_fu_2501_p4 = {{inptext_V_read[55:48]}};
assign p_Result_s_39_fu_2341_p4 = {{inptext_V_read[119:112]}};
assign p_Result_s_fu_2321_p4 = {{inptext_V_read[127:120]}};
assign rv_10_0_1_fu_3107_p2 = (tmp_115_fu_3093_p2 ^ 8'd27);
assign rv_10_0_2_fu_3255_p2 = (tmp_123_fu_3241_p2 ^ 8'd27);
assign rv_10_0_3_fu_3403_p2 = (tmp_131_fu_3389_p2 ^ 8'd27);
assign rv_10_1_1_fu_4149_p2 = (tmp_147_fu_4135_p2 ^ 8'd27);
assign rv_10_1_2_fu_4297_p2 = (tmp_155_fu_4283_p2 ^ 8'd27);
assign rv_10_1_3_fu_4445_p2 = (tmp_163_fu_4431_p2 ^ 8'd27);
assign rv_10_1_fu_4001_p2 = (tmp_139_fu_3987_p2 ^ 8'd27);
assign rv_10_2_1_fu_5191_p2 = (tmp_179_fu_5177_p2 ^ 8'd27);
assign rv_10_2_2_fu_5339_p2 = (tmp_187_fu_5325_p2 ^ 8'd27);
assign rv_10_2_3_fu_5487_p2 = (tmp_195_fu_5473_p2 ^ 8'd27);
assign rv_10_2_fu_5043_p2 = (tmp_171_fu_5029_p2 ^ 8'd27);
assign rv_10_3_1_fu_6233_p2 = (tmp_211_fu_6219_p2 ^ 8'd27);
assign rv_10_3_2_fu_6381_p2 = (tmp_219_fu_6367_p2 ^ 8'd27);
assign rv_10_3_3_fu_6529_p2 = (tmp_227_fu_6515_p2 ^ 8'd27);
assign rv_10_3_fu_6085_p2 = (tmp_203_fu_6071_p2 ^ 8'd27);
assign rv_10_4_1_fu_7275_p2 = (tmp_243_fu_7261_p2 ^ 8'd27);
assign rv_10_4_2_fu_7423_p2 = (tmp_251_fu_7409_p2 ^ 8'd27);
assign rv_10_4_3_fu_7571_p2 = (tmp_259_fu_7557_p2 ^ 8'd27);
assign rv_10_4_fu_7127_p2 = (tmp_235_fu_7113_p2 ^ 8'd27);
assign rv_10_5_1_fu_8317_p2 = (tmp_275_fu_8303_p2 ^ 8'd27);
assign rv_10_5_2_fu_8465_p2 = (tmp_283_fu_8451_p2 ^ 8'd27);
assign rv_10_5_3_fu_8613_p2 = (tmp_291_fu_8599_p2 ^ 8'd27);
assign rv_10_5_fu_8169_p2 = (tmp_267_fu_8155_p2 ^ 8'd27);
assign rv_10_6_1_fu_9359_p2 = (tmp_307_fu_9345_p2 ^ 8'd27);
assign rv_10_6_2_fu_9507_p2 = (tmp_315_fu_9493_p2 ^ 8'd27);
assign rv_10_6_3_fu_9655_p2 = (tmp_323_fu_9641_p2 ^ 8'd27);
assign rv_10_6_fu_9211_p2 = (tmp_299_fu_9197_p2 ^ 8'd27);
assign rv_10_7_1_fu_10401_p2 = (tmp_339_fu_10387_p2 ^ 8'd27);
assign rv_10_7_2_fu_10549_p2 = (tmp_347_fu_10535_p2 ^ 8'd27);
assign rv_10_7_3_fu_10697_p2 = (tmp_355_fu_10683_p2 ^ 8'd27);
assign rv_10_7_fu_10253_p2 = (tmp_331_fu_10239_p2 ^ 8'd27);
assign rv_10_8_1_fu_11443_p2 = (tmp_371_fu_11429_p2 ^ 8'd27);
assign rv_10_8_2_fu_11591_p2 = (tmp_379_fu_11577_p2 ^ 8'd27);
assign rv_10_8_3_fu_11739_p2 = (tmp_387_fu_11725_p2 ^ 8'd27);
assign rv_10_8_fu_11295_p2 = (tmp_363_fu_11281_p2 ^ 8'd27);
assign rv_11_0_1_fu_3113_p3 = ((tmp_116_fu_3099_p3[0:0] === 1'b1) ? rv_10_0_1_fu_3107_p2 : tmp_115_fu_3093_p2);
assign rv_11_0_2_fu_3261_p3 = ((tmp_124_fu_3247_p3[0:0] === 1'b1) ? rv_10_0_2_fu_3255_p2 : tmp_123_fu_3241_p2);
assign rv_11_0_3_fu_3409_p3 = ((tmp_132_fu_3395_p3[0:0] === 1'b1) ? rv_10_0_3_fu_3403_p2 : tmp_131_fu_3389_p2);
assign rv_11_1_1_fu_4155_p3 = ((tmp_148_fu_4141_p3[0:0] === 1'b1) ? rv_10_1_1_fu_4149_p2 : tmp_147_fu_4135_p2);
assign rv_11_1_2_fu_4303_p3 = ((tmp_156_fu_4289_p3[0:0] === 1'b1) ? rv_10_1_2_fu_4297_p2 : tmp_155_fu_4283_p2);
assign rv_11_1_3_fu_4451_p3 = ((tmp_164_fu_4437_p3[0:0] === 1'b1) ? rv_10_1_3_fu_4445_p2 : tmp_163_fu_4431_p2);
assign rv_11_1_fu_4007_p3 = ((tmp_140_fu_3993_p3[0:0] === 1'b1) ? rv_10_1_fu_4001_p2 : tmp_139_fu_3987_p2);
assign rv_11_2_1_fu_5197_p3 = ((tmp_180_fu_5183_p3[0:0] === 1'b1) ? rv_10_2_1_fu_5191_p2 : tmp_179_fu_5177_p2);
assign rv_11_2_2_fu_5345_p3 = ((tmp_188_fu_5331_p3[0:0] === 1'b1) ? rv_10_2_2_fu_5339_p2 : tmp_187_fu_5325_p2);
assign rv_11_2_3_fu_5493_p3 = ((tmp_196_fu_5479_p3[0:0] === 1'b1) ? rv_10_2_3_fu_5487_p2 : tmp_195_fu_5473_p2);
assign rv_11_2_fu_5049_p3 = ((tmp_172_fu_5035_p3[0:0] === 1'b1) ? rv_10_2_fu_5043_p2 : tmp_171_fu_5029_p2);
assign rv_11_3_1_fu_6239_p3 = ((tmp_212_fu_6225_p3[0:0] === 1'b1) ? rv_10_3_1_fu_6233_p2 : tmp_211_fu_6219_p2);
assign rv_11_3_2_fu_6387_p3 = ((tmp_220_fu_6373_p3[0:0] === 1'b1) ? rv_10_3_2_fu_6381_p2 : tmp_219_fu_6367_p2);
assign rv_11_3_3_fu_6535_p3 = ((tmp_228_fu_6521_p3[0:0] === 1'b1) ? rv_10_3_3_fu_6529_p2 : tmp_227_fu_6515_p2);
assign rv_11_3_fu_6091_p3 = ((tmp_204_fu_6077_p3[0:0] === 1'b1) ? rv_10_3_fu_6085_p2 : tmp_203_fu_6071_p2);
assign rv_11_4_1_fu_7281_p3 = ((tmp_244_fu_7267_p3[0:0] === 1'b1) ? rv_10_4_1_fu_7275_p2 : tmp_243_fu_7261_p2);
assign rv_11_4_2_fu_7429_p3 = ((tmp_252_fu_7415_p3[0:0] === 1'b1) ? rv_10_4_2_fu_7423_p2 : tmp_251_fu_7409_p2);
assign rv_11_4_3_fu_7577_p3 = ((tmp_260_fu_7563_p3[0:0] === 1'b1) ? rv_10_4_3_fu_7571_p2 : tmp_259_fu_7557_p2);
assign rv_11_4_fu_7133_p3 = ((tmp_236_fu_7119_p3[0:0] === 1'b1) ? rv_10_4_fu_7127_p2 : tmp_235_fu_7113_p2);
assign rv_11_5_1_fu_8323_p3 = ((tmp_276_fu_8309_p3[0:0] === 1'b1) ? rv_10_5_1_fu_8317_p2 : tmp_275_fu_8303_p2);
assign rv_11_5_2_fu_8471_p3 = ((tmp_284_fu_8457_p3[0:0] === 1'b1) ? rv_10_5_2_fu_8465_p2 : tmp_283_fu_8451_p2);
assign rv_11_5_3_fu_8619_p3 = ((tmp_292_fu_8605_p3[0:0] === 1'b1) ? rv_10_5_3_fu_8613_p2 : tmp_291_fu_8599_p2);
assign rv_11_5_fu_8175_p3 = ((tmp_268_fu_8161_p3[0:0] === 1'b1) ? rv_10_5_fu_8169_p2 : tmp_267_fu_8155_p2);
assign rv_11_6_1_fu_9365_p3 = ((tmp_308_fu_9351_p3[0:0] === 1'b1) ? rv_10_6_1_fu_9359_p2 : tmp_307_fu_9345_p2);
assign rv_11_6_2_fu_9513_p3 = ((tmp_316_fu_9499_p3[0:0] === 1'b1) ? rv_10_6_2_fu_9507_p2 : tmp_315_fu_9493_p2);
assign rv_11_6_3_fu_9661_p3 = ((tmp_324_fu_9647_p3[0:0] === 1'b1) ? rv_10_6_3_fu_9655_p2 : tmp_323_fu_9641_p2);
assign rv_11_6_fu_9217_p3 = ((tmp_300_fu_9203_p3[0:0] === 1'b1) ? rv_10_6_fu_9211_p2 : tmp_299_fu_9197_p2);
assign rv_11_7_1_fu_10407_p3 = ((tmp_340_fu_10393_p3[0:0] === 1'b1) ? rv_10_7_1_fu_10401_p2 : tmp_339_fu_10387_p2);
assign rv_11_7_2_fu_10555_p3 = ((tmp_348_fu_10541_p3[0:0] === 1'b1) ? rv_10_7_2_fu_10549_p2 : tmp_347_fu_10535_p2);
assign rv_11_7_3_fu_10703_p3 = ((tmp_356_fu_10689_p3[0:0] === 1'b1) ? rv_10_7_3_fu_10697_p2 : tmp_355_fu_10683_p2);
assign rv_11_7_fu_10259_p3 = ((tmp_332_fu_10245_p3[0:0] === 1'b1) ? rv_10_7_fu_10253_p2 : tmp_331_fu_10239_p2);
assign rv_11_8_1_fu_11449_p3 = ((tmp_372_fu_11435_p3[0:0] === 1'b1) ? rv_10_8_1_fu_11443_p2 : tmp_371_fu_11429_p2);
assign rv_11_8_2_fu_11597_p3 = ((tmp_380_fu_11583_p3[0:0] === 1'b1) ? rv_10_8_2_fu_11591_p2 : tmp_379_fu_11577_p2);
assign rv_11_8_3_fu_11745_p3 = ((tmp_388_fu_11731_p3[0:0] === 1'b1) ? rv_10_8_3_fu_11739_p2 : tmp_387_fu_11725_p2);
assign rv_11_8_fu_11301_p3 = ((tmp_364_fu_11287_p3[0:0] === 1'b1) ? rv_10_8_fu_11295_p2 : tmp_363_fu_11281_p2);
assign rv_1_0_1_fu_3005_p2 = (tmp_109_fu_2991_p2 ^ 8'd27);
assign rv_1_0_2_fu_3153_p2 = (tmp_117_fu_3139_p2 ^ 8'd27);
assign rv_1_0_3_fu_3301_p2 = (tmp_125_fu_3287_p2 ^ 8'd27);
assign rv_1_1_1_fu_4047_p2 = (tmp_141_fu_4033_p2 ^ 8'd27);
assign rv_1_1_2_fu_4195_p2 = (tmp_149_fu_4181_p2 ^ 8'd27);
assign rv_1_1_3_fu_4343_p2 = (tmp_157_fu_4329_p2 ^ 8'd27);
assign rv_1_1_fu_3899_p2 = (tmp_133_fu_3885_p2 ^ 8'd27);
assign rv_1_2_1_fu_5089_p2 = (tmp_173_fu_5075_p2 ^ 8'd27);
assign rv_1_2_2_fu_5237_p2 = (tmp_181_fu_5223_p2 ^ 8'd27);
assign rv_1_2_3_fu_5385_p2 = (tmp_189_fu_5371_p2 ^ 8'd27);
assign rv_1_2_fu_4941_p2 = (tmp_165_fu_4927_p2 ^ 8'd27);
assign rv_1_3_1_fu_6131_p2 = (tmp_205_fu_6117_p2 ^ 8'd27);
assign rv_1_3_2_fu_6279_p2 = (tmp_213_fu_6265_p2 ^ 8'd27);
assign rv_1_3_3_fu_6427_p2 = (tmp_221_fu_6413_p2 ^ 8'd27);
assign rv_1_3_fu_5983_p2 = (tmp_197_fu_5969_p2 ^ 8'd27);
assign rv_1_4_1_fu_7173_p2 = (tmp_237_fu_7159_p2 ^ 8'd27);
assign rv_1_4_2_fu_7321_p2 = (tmp_245_fu_7307_p2 ^ 8'd27);
assign rv_1_4_3_fu_7469_p2 = (tmp_253_fu_7455_p2 ^ 8'd27);
assign rv_1_4_fu_7025_p2 = (tmp_229_fu_7011_p2 ^ 8'd27);
assign rv_1_5_1_fu_8215_p2 = (tmp_269_fu_8201_p2 ^ 8'd27);
assign rv_1_5_2_fu_8363_p2 = (tmp_277_fu_8349_p2 ^ 8'd27);
assign rv_1_5_3_fu_8511_p2 = (tmp_285_fu_8497_p2 ^ 8'd27);
assign rv_1_5_fu_8067_p2 = (tmp_261_fu_8053_p2 ^ 8'd27);
assign rv_1_6_1_fu_9257_p2 = (tmp_301_fu_9243_p2 ^ 8'd27);
assign rv_1_6_2_fu_9405_p2 = (tmp_309_fu_9391_p2 ^ 8'd27);
assign rv_1_6_3_fu_9553_p2 = (tmp_317_fu_9539_p2 ^ 8'd27);
assign rv_1_6_fu_9109_p2 = (tmp_293_fu_9095_p2 ^ 8'd27);
assign rv_1_7_1_fu_10299_p2 = (tmp_333_fu_10285_p2 ^ 8'd27);
assign rv_1_7_2_fu_10447_p2 = (tmp_341_fu_10433_p2 ^ 8'd27);
assign rv_1_7_3_fu_10595_p2 = (tmp_349_fu_10581_p2 ^ 8'd27);
assign rv_1_7_fu_10151_p2 = (tmp_325_fu_10137_p2 ^ 8'd27);
assign rv_1_8_1_fu_11341_p2 = (tmp_365_fu_11327_p2 ^ 8'd27);
assign rv_1_8_2_fu_11489_p2 = (tmp_373_fu_11475_p2 ^ 8'd27);
assign rv_1_8_3_fu_11637_p2 = (tmp_381_fu_11623_p2 ^ 8'd27);
assign rv_1_8_fu_11193_p2 = (tmp_357_fu_11179_p2 ^ 8'd27);
assign rv_1_fu_2857_p2 = (tmp_101_fu_2843_p2 ^ 8'd27);
assign rv_2_0_1_fu_3011_p3 = ((tmp_110_fu_2997_p3[0:0] === 1'b1) ? rv_1_0_1_fu_3005_p2 : tmp_109_fu_2991_p2);
assign rv_2_0_2_fu_3159_p3 = ((tmp_118_fu_3145_p3[0:0] === 1'b1) ? rv_1_0_2_fu_3153_p2 : tmp_117_fu_3139_p2);
assign rv_2_0_3_fu_3307_p3 = ((tmp_126_fu_3293_p3[0:0] === 1'b1) ? rv_1_0_3_fu_3301_p2 : tmp_125_fu_3287_p2);
assign rv_2_1_1_fu_4053_p3 = ((tmp_142_fu_4039_p3[0:0] === 1'b1) ? rv_1_1_1_fu_4047_p2 : tmp_141_fu_4033_p2);
assign rv_2_1_2_fu_4201_p3 = ((tmp_150_fu_4187_p3[0:0] === 1'b1) ? rv_1_1_2_fu_4195_p2 : tmp_149_fu_4181_p2);
assign rv_2_1_3_fu_4349_p3 = ((tmp_158_fu_4335_p3[0:0] === 1'b1) ? rv_1_1_3_fu_4343_p2 : tmp_157_fu_4329_p2);
assign rv_2_1_fu_3905_p3 = ((tmp_134_fu_3891_p3[0:0] === 1'b1) ? rv_1_1_fu_3899_p2 : tmp_133_fu_3885_p2);
assign rv_2_2_1_fu_5095_p3 = ((tmp_174_fu_5081_p3[0:0] === 1'b1) ? rv_1_2_1_fu_5089_p2 : tmp_173_fu_5075_p2);
assign rv_2_2_2_fu_5243_p3 = ((tmp_182_fu_5229_p3[0:0] === 1'b1) ? rv_1_2_2_fu_5237_p2 : tmp_181_fu_5223_p2);
assign rv_2_2_3_fu_5391_p3 = ((tmp_190_fu_5377_p3[0:0] === 1'b1) ? rv_1_2_3_fu_5385_p2 : tmp_189_fu_5371_p2);
assign rv_2_2_fu_4947_p3 = ((tmp_166_fu_4933_p3[0:0] === 1'b1) ? rv_1_2_fu_4941_p2 : tmp_165_fu_4927_p2);
assign rv_2_3_1_fu_6137_p3 = ((tmp_206_fu_6123_p3[0:0] === 1'b1) ? rv_1_3_1_fu_6131_p2 : tmp_205_fu_6117_p2);
assign rv_2_3_2_fu_6285_p3 = ((tmp_214_fu_6271_p3[0:0] === 1'b1) ? rv_1_3_2_fu_6279_p2 : tmp_213_fu_6265_p2);
assign rv_2_3_3_fu_6433_p3 = ((tmp_222_fu_6419_p3[0:0] === 1'b1) ? rv_1_3_3_fu_6427_p2 : tmp_221_fu_6413_p2);
assign rv_2_3_fu_5989_p3 = ((tmp_198_fu_5975_p3[0:0] === 1'b1) ? rv_1_3_fu_5983_p2 : tmp_197_fu_5969_p2);
assign rv_2_4_1_fu_7179_p3 = ((tmp_238_fu_7165_p3[0:0] === 1'b1) ? rv_1_4_1_fu_7173_p2 : tmp_237_fu_7159_p2);
assign rv_2_4_2_fu_7327_p3 = ((tmp_246_fu_7313_p3[0:0] === 1'b1) ? rv_1_4_2_fu_7321_p2 : tmp_245_fu_7307_p2);
assign rv_2_4_3_fu_7475_p3 = ((tmp_254_fu_7461_p3[0:0] === 1'b1) ? rv_1_4_3_fu_7469_p2 : tmp_253_fu_7455_p2);
assign rv_2_4_fu_7031_p3 = ((tmp_230_fu_7017_p3[0:0] === 1'b1) ? rv_1_4_fu_7025_p2 : tmp_229_fu_7011_p2);
assign rv_2_5_1_fu_8221_p3 = ((tmp_270_fu_8207_p3[0:0] === 1'b1) ? rv_1_5_1_fu_8215_p2 : tmp_269_fu_8201_p2);
assign rv_2_5_2_fu_8369_p3 = ((tmp_278_fu_8355_p3[0:0] === 1'b1) ? rv_1_5_2_fu_8363_p2 : tmp_277_fu_8349_p2);
assign rv_2_5_3_fu_8517_p3 = ((tmp_286_fu_8503_p3[0:0] === 1'b1) ? rv_1_5_3_fu_8511_p2 : tmp_285_fu_8497_p2);
assign rv_2_5_fu_8073_p3 = ((tmp_262_fu_8059_p3[0:0] === 1'b1) ? rv_1_5_fu_8067_p2 : tmp_261_fu_8053_p2);
assign rv_2_6_1_fu_9263_p3 = ((tmp_302_fu_9249_p3[0:0] === 1'b1) ? rv_1_6_1_fu_9257_p2 : tmp_301_fu_9243_p2);
assign rv_2_6_2_fu_9411_p3 = ((tmp_310_fu_9397_p3[0:0] === 1'b1) ? rv_1_6_2_fu_9405_p2 : tmp_309_fu_9391_p2);
assign rv_2_6_3_fu_9559_p3 = ((tmp_318_fu_9545_p3[0:0] === 1'b1) ? rv_1_6_3_fu_9553_p2 : tmp_317_fu_9539_p2);
assign rv_2_6_fu_9115_p3 = ((tmp_294_fu_9101_p3[0:0] === 1'b1) ? rv_1_6_fu_9109_p2 : tmp_293_fu_9095_p2);
assign rv_2_7_1_fu_10305_p3 = ((tmp_334_fu_10291_p3[0:0] === 1'b1) ? rv_1_7_1_fu_10299_p2 : tmp_333_fu_10285_p2);
assign rv_2_7_2_fu_10453_p3 = ((tmp_342_fu_10439_p3[0:0] === 1'b1) ? rv_1_7_2_fu_10447_p2 : tmp_341_fu_10433_p2);
assign rv_2_7_3_fu_10601_p3 = ((tmp_350_fu_10587_p3[0:0] === 1'b1) ? rv_1_7_3_fu_10595_p2 : tmp_349_fu_10581_p2);
assign rv_2_7_fu_10157_p3 = ((tmp_326_fu_10143_p3[0:0] === 1'b1) ? rv_1_7_fu_10151_p2 : tmp_325_fu_10137_p2);
assign rv_2_8_1_fu_11347_p3 = ((tmp_366_fu_11333_p3[0:0] === 1'b1) ? rv_1_8_1_fu_11341_p2 : tmp_365_fu_11327_p2);
assign rv_2_8_2_fu_11495_p3 = ((tmp_374_fu_11481_p3[0:0] === 1'b1) ? rv_1_8_2_fu_11489_p2 : tmp_373_fu_11475_p2);
assign rv_2_8_3_fu_11643_p3 = ((tmp_382_fu_11629_p3[0:0] === 1'b1) ? rv_1_8_3_fu_11637_p2 : tmp_381_fu_11623_p2);
assign rv_2_8_fu_11199_p3 = ((tmp_358_fu_11185_p3[0:0] === 1'b1) ? rv_1_8_fu_11193_p2 : tmp_357_fu_11179_p2);
assign rv_2_fu_2863_p3 = ((tmp_102_fu_2849_p3[0:0] === 1'b1) ? rv_1_fu_2857_p2 : tmp_101_fu_2843_p2);
assign rv_3_fu_2965_p3 = ((tmp_108_fu_2951_p3[0:0] === 1'b1) ? rv_s_fu_2959_p2 : tmp_107_fu_2945_p2);
assign rv_4_0_1_fu_3039_p2 = (tmp_111_fu_3025_p2 ^ 8'd27);
assign rv_4_0_2_fu_3187_p2 = (tmp_119_fu_3173_p2 ^ 8'd27);
assign rv_4_0_3_fu_3335_p2 = (tmp_127_fu_3321_p2 ^ 8'd27);
assign rv_4_1_1_fu_4081_p2 = (tmp_143_fu_4067_p2 ^ 8'd27);
assign rv_4_1_2_fu_4229_p2 = (tmp_151_fu_4215_p2 ^ 8'd27);
assign rv_4_1_3_fu_4377_p2 = (tmp_159_fu_4363_p2 ^ 8'd27);
assign rv_4_1_fu_3933_p2 = (tmp_135_fu_3919_p2 ^ 8'd27);
assign rv_4_2_1_fu_5123_p2 = (tmp_175_fu_5109_p2 ^ 8'd27);
assign rv_4_2_2_fu_5271_p2 = (tmp_183_fu_5257_p2 ^ 8'd27);
assign rv_4_2_3_fu_5419_p2 = (tmp_191_fu_5405_p2 ^ 8'd27);
assign rv_4_2_fu_4975_p2 = (tmp_167_fu_4961_p2 ^ 8'd27);
assign rv_4_3_1_fu_6165_p2 = (tmp_207_fu_6151_p2 ^ 8'd27);
assign rv_4_3_2_fu_6313_p2 = (tmp_215_fu_6299_p2 ^ 8'd27);
assign rv_4_3_3_fu_6461_p2 = (tmp_223_fu_6447_p2 ^ 8'd27);
assign rv_4_3_fu_6017_p2 = (tmp_199_fu_6003_p2 ^ 8'd27);
assign rv_4_4_1_fu_7207_p2 = (tmp_239_fu_7193_p2 ^ 8'd27);
assign rv_4_4_2_fu_7355_p2 = (tmp_247_fu_7341_p2 ^ 8'd27);
assign rv_4_4_3_fu_7503_p2 = (tmp_255_fu_7489_p2 ^ 8'd27);
assign rv_4_4_fu_7059_p2 = (tmp_231_fu_7045_p2 ^ 8'd27);
assign rv_4_5_1_fu_8249_p2 = (tmp_271_fu_8235_p2 ^ 8'd27);
assign rv_4_5_2_fu_8397_p2 = (tmp_279_fu_8383_p2 ^ 8'd27);
assign rv_4_5_3_fu_8545_p2 = (tmp_287_fu_8531_p2 ^ 8'd27);
assign rv_4_5_fu_8101_p2 = (tmp_263_fu_8087_p2 ^ 8'd27);
assign rv_4_6_1_fu_9291_p2 = (tmp_303_fu_9277_p2 ^ 8'd27);
assign rv_4_6_2_fu_9439_p2 = (tmp_311_fu_9425_p2 ^ 8'd27);
assign rv_4_6_3_fu_9587_p2 = (tmp_319_fu_9573_p2 ^ 8'd27);
assign rv_4_6_fu_9143_p2 = (tmp_295_fu_9129_p2 ^ 8'd27);
assign rv_4_7_1_fu_10333_p2 = (tmp_335_fu_10319_p2 ^ 8'd27);
assign rv_4_7_2_fu_10481_p2 = (tmp_343_fu_10467_p2 ^ 8'd27);
assign rv_4_7_3_fu_10629_p2 = (tmp_351_fu_10615_p2 ^ 8'd27);
assign rv_4_7_fu_10185_p2 = (tmp_327_fu_10171_p2 ^ 8'd27);
assign rv_4_8_1_fu_11375_p2 = (tmp_367_fu_11361_p2 ^ 8'd27);
assign rv_4_8_2_fu_11523_p2 = (tmp_375_fu_11509_p2 ^ 8'd27);
assign rv_4_8_3_fu_11671_p2 = (tmp_383_fu_11657_p2 ^ 8'd27);
assign rv_4_8_fu_11227_p2 = (tmp_359_fu_11213_p2 ^ 8'd27);
assign rv_4_fu_2891_p2 = (tmp_103_fu_2877_p2 ^ 8'd27);
assign rv_5_0_1_fu_3045_p3 = ((tmp_112_fu_3031_p3[0:0] === 1'b1) ? rv_4_0_1_fu_3039_p2 : tmp_111_fu_3025_p2);
assign rv_5_0_2_fu_3193_p3 = ((tmp_120_fu_3179_p3[0:0] === 1'b1) ? rv_4_0_2_fu_3187_p2 : tmp_119_fu_3173_p2);
assign rv_5_0_3_fu_3341_p3 = ((tmp_128_fu_3327_p3[0:0] === 1'b1) ? rv_4_0_3_fu_3335_p2 : tmp_127_fu_3321_p2);
assign rv_5_1_1_fu_4087_p3 = ((tmp_144_fu_4073_p3[0:0] === 1'b1) ? rv_4_1_1_fu_4081_p2 : tmp_143_fu_4067_p2);
assign rv_5_1_2_fu_4235_p3 = ((tmp_152_fu_4221_p3[0:0] === 1'b1) ? rv_4_1_2_fu_4229_p2 : tmp_151_fu_4215_p2);
assign rv_5_1_3_fu_4383_p3 = ((tmp_160_fu_4369_p3[0:0] === 1'b1) ? rv_4_1_3_fu_4377_p2 : tmp_159_fu_4363_p2);
assign rv_5_1_fu_3939_p3 = ((tmp_136_fu_3925_p3[0:0] === 1'b1) ? rv_4_1_fu_3933_p2 : tmp_135_fu_3919_p2);
assign rv_5_2_1_fu_5129_p3 = ((tmp_176_fu_5115_p3[0:0] === 1'b1) ? rv_4_2_1_fu_5123_p2 : tmp_175_fu_5109_p2);
assign rv_5_2_2_fu_5277_p3 = ((tmp_184_fu_5263_p3[0:0] === 1'b1) ? rv_4_2_2_fu_5271_p2 : tmp_183_fu_5257_p2);
assign rv_5_2_3_fu_5425_p3 = ((tmp_192_fu_5411_p3[0:0] === 1'b1) ? rv_4_2_3_fu_5419_p2 : tmp_191_fu_5405_p2);
assign rv_5_2_fu_4981_p3 = ((tmp_168_fu_4967_p3[0:0] === 1'b1) ? rv_4_2_fu_4975_p2 : tmp_167_fu_4961_p2);
assign rv_5_3_1_fu_6171_p3 = ((tmp_208_fu_6157_p3[0:0] === 1'b1) ? rv_4_3_1_fu_6165_p2 : tmp_207_fu_6151_p2);
assign rv_5_3_2_fu_6319_p3 = ((tmp_216_fu_6305_p3[0:0] === 1'b1) ? rv_4_3_2_fu_6313_p2 : tmp_215_fu_6299_p2);
assign rv_5_3_3_fu_6467_p3 = ((tmp_224_fu_6453_p3[0:0] === 1'b1) ? rv_4_3_3_fu_6461_p2 : tmp_223_fu_6447_p2);
assign rv_5_3_fu_6023_p3 = ((tmp_200_fu_6009_p3[0:0] === 1'b1) ? rv_4_3_fu_6017_p2 : tmp_199_fu_6003_p2);
assign rv_5_4_1_fu_7213_p3 = ((tmp_240_fu_7199_p3[0:0] === 1'b1) ? rv_4_4_1_fu_7207_p2 : tmp_239_fu_7193_p2);
assign rv_5_4_2_fu_7361_p3 = ((tmp_248_fu_7347_p3[0:0] === 1'b1) ? rv_4_4_2_fu_7355_p2 : tmp_247_fu_7341_p2);
assign rv_5_4_3_fu_7509_p3 = ((tmp_256_fu_7495_p3[0:0] === 1'b1) ? rv_4_4_3_fu_7503_p2 : tmp_255_fu_7489_p2);
assign rv_5_4_fu_7065_p3 = ((tmp_232_fu_7051_p3[0:0] === 1'b1) ? rv_4_4_fu_7059_p2 : tmp_231_fu_7045_p2);
assign rv_5_5_1_fu_8255_p3 = ((tmp_272_fu_8241_p3[0:0] === 1'b1) ? rv_4_5_1_fu_8249_p2 : tmp_271_fu_8235_p2);
assign rv_5_5_2_fu_8403_p3 = ((tmp_280_fu_8389_p3[0:0] === 1'b1) ? rv_4_5_2_fu_8397_p2 : tmp_279_fu_8383_p2);
assign rv_5_5_3_fu_8551_p3 = ((tmp_288_fu_8537_p3[0:0] === 1'b1) ? rv_4_5_3_fu_8545_p2 : tmp_287_fu_8531_p2);
assign rv_5_5_fu_8107_p3 = ((tmp_264_fu_8093_p3[0:0] === 1'b1) ? rv_4_5_fu_8101_p2 : tmp_263_fu_8087_p2);
assign rv_5_6_1_fu_9297_p3 = ((tmp_304_fu_9283_p3[0:0] === 1'b1) ? rv_4_6_1_fu_9291_p2 : tmp_303_fu_9277_p2);
assign rv_5_6_2_fu_9445_p3 = ((tmp_312_fu_9431_p3[0:0] === 1'b1) ? rv_4_6_2_fu_9439_p2 : tmp_311_fu_9425_p2);
assign rv_5_6_3_fu_9593_p3 = ((tmp_320_fu_9579_p3[0:0] === 1'b1) ? rv_4_6_3_fu_9587_p2 : tmp_319_fu_9573_p2);
assign rv_5_6_fu_9149_p3 = ((tmp_296_fu_9135_p3[0:0] === 1'b1) ? rv_4_6_fu_9143_p2 : tmp_295_fu_9129_p2);
assign rv_5_7_1_fu_10339_p3 = ((tmp_336_fu_10325_p3[0:0] === 1'b1) ? rv_4_7_1_fu_10333_p2 : tmp_335_fu_10319_p2);
assign rv_5_7_2_fu_10487_p3 = ((tmp_344_fu_10473_p3[0:0] === 1'b1) ? rv_4_7_2_fu_10481_p2 : tmp_343_fu_10467_p2);
assign rv_5_7_3_fu_10635_p3 = ((tmp_352_fu_10621_p3[0:0] === 1'b1) ? rv_4_7_3_fu_10629_p2 : tmp_351_fu_10615_p2);
assign rv_5_7_fu_10191_p3 = ((tmp_328_fu_10177_p3[0:0] === 1'b1) ? rv_4_7_fu_10185_p2 : tmp_327_fu_10171_p2);
assign rv_5_8_1_fu_11381_p3 = ((tmp_368_fu_11367_p3[0:0] === 1'b1) ? rv_4_8_1_fu_11375_p2 : tmp_367_fu_11361_p2);
assign rv_5_8_2_fu_11529_p3 = ((tmp_376_fu_11515_p3[0:0] === 1'b1) ? rv_4_8_2_fu_11523_p2 : tmp_375_fu_11509_p2);
assign rv_5_8_3_fu_11677_p3 = ((tmp_384_fu_11663_p3[0:0] === 1'b1) ? rv_4_8_3_fu_11671_p2 : tmp_383_fu_11657_p2);
assign rv_5_8_fu_11233_p3 = ((tmp_360_fu_11219_p3[0:0] === 1'b1) ? rv_4_8_fu_11227_p2 : tmp_359_fu_11213_p2);
assign rv_5_fu_2897_p3 = ((tmp_104_fu_2883_p3[0:0] === 1'b1) ? rv_4_fu_2891_p2 : tmp_103_fu_2877_p2);
assign rv_7_0_1_fu_3073_p2 = (tmp_113_fu_3059_p2 ^ 8'd27);
assign rv_7_0_2_fu_3221_p2 = (tmp_121_fu_3207_p2 ^ 8'd27);
assign rv_7_0_3_fu_3369_p2 = (tmp_129_fu_3355_p2 ^ 8'd27);
assign rv_7_1_1_fu_4115_p2 = (tmp_145_fu_4101_p2 ^ 8'd27);
assign rv_7_1_2_fu_4263_p2 = (tmp_153_fu_4249_p2 ^ 8'd27);
assign rv_7_1_3_fu_4411_p2 = (tmp_161_fu_4397_p2 ^ 8'd27);
assign rv_7_1_fu_3967_p2 = (tmp_137_fu_3953_p2 ^ 8'd27);
assign rv_7_2_1_fu_5157_p2 = (tmp_177_fu_5143_p2 ^ 8'd27);
assign rv_7_2_2_fu_5305_p2 = (tmp_185_fu_5291_p2 ^ 8'd27);
assign rv_7_2_3_fu_5453_p2 = (tmp_193_fu_5439_p2 ^ 8'd27);
assign rv_7_2_fu_5009_p2 = (tmp_169_fu_4995_p2 ^ 8'd27);
assign rv_7_3_1_fu_6199_p2 = (tmp_209_fu_6185_p2 ^ 8'd27);
assign rv_7_3_2_fu_6347_p2 = (tmp_217_fu_6333_p2 ^ 8'd27);
assign rv_7_3_3_fu_6495_p2 = (tmp_225_fu_6481_p2 ^ 8'd27);
assign rv_7_3_fu_6051_p2 = (tmp_201_fu_6037_p2 ^ 8'd27);
assign rv_7_4_1_fu_7241_p2 = (tmp_241_fu_7227_p2 ^ 8'd27);
assign rv_7_4_2_fu_7389_p2 = (tmp_249_fu_7375_p2 ^ 8'd27);
assign rv_7_4_3_fu_7537_p2 = (tmp_257_fu_7523_p2 ^ 8'd27);
assign rv_7_4_fu_7093_p2 = (tmp_233_fu_7079_p2 ^ 8'd27);
assign rv_7_5_1_fu_8283_p2 = (tmp_273_fu_8269_p2 ^ 8'd27);
assign rv_7_5_2_fu_8431_p2 = (tmp_281_fu_8417_p2 ^ 8'd27);
assign rv_7_5_3_fu_8579_p2 = (tmp_289_fu_8565_p2 ^ 8'd27);
assign rv_7_5_fu_8135_p2 = (tmp_265_fu_8121_p2 ^ 8'd27);
assign rv_7_6_1_fu_9325_p2 = (tmp_305_fu_9311_p2 ^ 8'd27);
assign rv_7_6_2_fu_9473_p2 = (tmp_313_fu_9459_p2 ^ 8'd27);
assign rv_7_6_3_fu_9621_p2 = (tmp_321_fu_9607_p2 ^ 8'd27);
assign rv_7_6_fu_9177_p2 = (tmp_297_fu_9163_p2 ^ 8'd27);
assign rv_7_7_1_fu_10367_p2 = (tmp_337_fu_10353_p2 ^ 8'd27);
assign rv_7_7_2_fu_10515_p2 = (tmp_345_fu_10501_p2 ^ 8'd27);
assign rv_7_7_3_fu_10663_p2 = (tmp_353_fu_10649_p2 ^ 8'd27);
assign rv_7_7_fu_10219_p2 = (tmp_329_fu_10205_p2 ^ 8'd27);
assign rv_7_8_1_fu_11409_p2 = (tmp_369_fu_11395_p2 ^ 8'd27);
assign rv_7_8_2_fu_11557_p2 = (tmp_377_fu_11543_p2 ^ 8'd27);
assign rv_7_8_3_fu_11705_p2 = (tmp_385_fu_11691_p2 ^ 8'd27);
assign rv_7_8_fu_11261_p2 = (tmp_361_fu_11247_p2 ^ 8'd27);
assign rv_7_fu_2925_p2 = (tmp_105_fu_2911_p2 ^ 8'd27);
assign rv_8_0_1_fu_3079_p3 = ((tmp_114_fu_3065_p3[0:0] === 1'b1) ? rv_7_0_1_fu_3073_p2 : tmp_113_fu_3059_p2);
assign rv_8_0_2_fu_3227_p3 = ((tmp_122_fu_3213_p3[0:0] === 1'b1) ? rv_7_0_2_fu_3221_p2 : tmp_121_fu_3207_p2);
assign rv_8_0_3_fu_3375_p3 = ((tmp_130_fu_3361_p3[0:0] === 1'b1) ? rv_7_0_3_fu_3369_p2 : tmp_129_fu_3355_p2);
assign rv_8_1_1_fu_4121_p3 = ((tmp_146_fu_4107_p3[0:0] === 1'b1) ? rv_7_1_1_fu_4115_p2 : tmp_145_fu_4101_p2);
assign rv_8_1_2_fu_4269_p3 = ((tmp_154_fu_4255_p3[0:0] === 1'b1) ? rv_7_1_2_fu_4263_p2 : tmp_153_fu_4249_p2);
assign rv_8_1_3_fu_4417_p3 = ((tmp_162_fu_4403_p3[0:0] === 1'b1) ? rv_7_1_3_fu_4411_p2 : tmp_161_fu_4397_p2);
assign rv_8_1_fu_3973_p3 = ((tmp_138_fu_3959_p3[0:0] === 1'b1) ? rv_7_1_fu_3967_p2 : tmp_137_fu_3953_p2);
assign rv_8_2_1_fu_5163_p3 = ((tmp_178_fu_5149_p3[0:0] === 1'b1) ? rv_7_2_1_fu_5157_p2 : tmp_177_fu_5143_p2);
assign rv_8_2_2_fu_5311_p3 = ((tmp_186_fu_5297_p3[0:0] === 1'b1) ? rv_7_2_2_fu_5305_p2 : tmp_185_fu_5291_p2);
assign rv_8_2_3_fu_5459_p3 = ((tmp_194_fu_5445_p3[0:0] === 1'b1) ? rv_7_2_3_fu_5453_p2 : tmp_193_fu_5439_p2);
assign rv_8_2_fu_5015_p3 = ((tmp_170_fu_5001_p3[0:0] === 1'b1) ? rv_7_2_fu_5009_p2 : tmp_169_fu_4995_p2);
assign rv_8_3_1_fu_6205_p3 = ((tmp_210_fu_6191_p3[0:0] === 1'b1) ? rv_7_3_1_fu_6199_p2 : tmp_209_fu_6185_p2);
assign rv_8_3_2_fu_6353_p3 = ((tmp_218_fu_6339_p3[0:0] === 1'b1) ? rv_7_3_2_fu_6347_p2 : tmp_217_fu_6333_p2);
assign rv_8_3_3_fu_6501_p3 = ((tmp_226_fu_6487_p3[0:0] === 1'b1) ? rv_7_3_3_fu_6495_p2 : tmp_225_fu_6481_p2);
assign rv_8_3_fu_6057_p3 = ((tmp_202_fu_6043_p3[0:0] === 1'b1) ? rv_7_3_fu_6051_p2 : tmp_201_fu_6037_p2);
assign rv_8_4_1_fu_7247_p3 = ((tmp_242_fu_7233_p3[0:0] === 1'b1) ? rv_7_4_1_fu_7241_p2 : tmp_241_fu_7227_p2);
assign rv_8_4_2_fu_7395_p3 = ((tmp_250_fu_7381_p3[0:0] === 1'b1) ? rv_7_4_2_fu_7389_p2 : tmp_249_fu_7375_p2);
assign rv_8_4_3_fu_7543_p3 = ((tmp_258_fu_7529_p3[0:0] === 1'b1) ? rv_7_4_3_fu_7537_p2 : tmp_257_fu_7523_p2);
assign rv_8_4_fu_7099_p3 = ((tmp_234_fu_7085_p3[0:0] === 1'b1) ? rv_7_4_fu_7093_p2 : tmp_233_fu_7079_p2);
assign rv_8_5_1_fu_8289_p3 = ((tmp_274_fu_8275_p3[0:0] === 1'b1) ? rv_7_5_1_fu_8283_p2 : tmp_273_fu_8269_p2);
assign rv_8_5_2_fu_8437_p3 = ((tmp_282_fu_8423_p3[0:0] === 1'b1) ? rv_7_5_2_fu_8431_p2 : tmp_281_fu_8417_p2);
assign rv_8_5_3_fu_8585_p3 = ((tmp_290_fu_8571_p3[0:0] === 1'b1) ? rv_7_5_3_fu_8579_p2 : tmp_289_fu_8565_p2);
assign rv_8_5_fu_8141_p3 = ((tmp_266_fu_8127_p3[0:0] === 1'b1) ? rv_7_5_fu_8135_p2 : tmp_265_fu_8121_p2);
assign rv_8_6_1_fu_9331_p3 = ((tmp_306_fu_9317_p3[0:0] === 1'b1) ? rv_7_6_1_fu_9325_p2 : tmp_305_fu_9311_p2);
assign rv_8_6_2_fu_9479_p3 = ((tmp_314_fu_9465_p3[0:0] === 1'b1) ? rv_7_6_2_fu_9473_p2 : tmp_313_fu_9459_p2);
assign rv_8_6_3_fu_9627_p3 = ((tmp_322_fu_9613_p3[0:0] === 1'b1) ? rv_7_6_3_fu_9621_p2 : tmp_321_fu_9607_p2);
assign rv_8_6_fu_9183_p3 = ((tmp_298_fu_9169_p3[0:0] === 1'b1) ? rv_7_6_fu_9177_p2 : tmp_297_fu_9163_p2);
assign rv_8_7_1_fu_10373_p3 = ((tmp_338_fu_10359_p3[0:0] === 1'b1) ? rv_7_7_1_fu_10367_p2 : tmp_337_fu_10353_p2);
assign rv_8_7_2_fu_10521_p3 = ((tmp_346_fu_10507_p3[0:0] === 1'b1) ? rv_7_7_2_fu_10515_p2 : tmp_345_fu_10501_p2);
assign rv_8_7_3_fu_10669_p3 = ((tmp_354_fu_10655_p3[0:0] === 1'b1) ? rv_7_7_3_fu_10663_p2 : tmp_353_fu_10649_p2);
assign rv_8_7_fu_10225_p3 = ((tmp_330_fu_10211_p3[0:0] === 1'b1) ? rv_7_7_fu_10219_p2 : tmp_329_fu_10205_p2);
assign rv_8_8_1_fu_11415_p3 = ((tmp_370_fu_11401_p3[0:0] === 1'b1) ? rv_7_8_1_fu_11409_p2 : tmp_369_fu_11395_p2);
assign rv_8_8_2_fu_11563_p3 = ((tmp_378_fu_11549_p3[0:0] === 1'b1) ? rv_7_8_2_fu_11557_p2 : tmp_377_fu_11543_p2);
assign rv_8_8_3_fu_11711_p3 = ((tmp_386_fu_11697_p3[0:0] === 1'b1) ? rv_7_8_3_fu_11705_p2 : tmp_385_fu_11691_p2);
assign rv_8_8_fu_11267_p3 = ((tmp_362_fu_11253_p3[0:0] === 1'b1) ? rv_7_8_fu_11261_p2 : tmp_361_fu_11247_p2);
assign rv_8_fu_2931_p3 = ((tmp_106_fu_2917_p3[0:0] === 1'b1) ? rv_7_fu_2925_p2 : tmp_105_fu_2911_p2);
assign rv_s_fu_2959_p2 = (tmp_107_fu_2945_p2 ^ 8'd27);
assign sboxes_address0 = tmp_35_fu_2725_p1;
assign sboxes_address1 = tmp_35_0_1_fu_2730_p1;
assign sboxes_address10 = tmp_35_0_s_fu_2775_p1;
assign sboxes_address100 = tmp_35_5_fu_7935_p1;
assign sboxes_address101 = tmp_35_5_1_fu_7940_p1;
assign sboxes_address102 = tmp_35_5_2_fu_7945_p1;
assign sboxes_address103 = tmp_35_5_3_fu_7950_p1;
assign sboxes_address104 = tmp_35_5_4_fu_7955_p1;
assign sboxes_address105 = tmp_35_5_5_fu_7960_p1;
assign sboxes_address106 = tmp_35_5_6_fu_7965_p1;
assign sboxes_address107 = tmp_35_5_7_fu_7970_p1;
assign sboxes_address108 = tmp_35_5_8_fu_7975_p1;
assign sboxes_address109 = tmp_35_5_9_fu_7980_p1;
assign sboxes_address11 = tmp_35_0_10_fu_2780_p1;
assign sboxes_address110 = tmp_35_5_s_fu_7985_p1;
assign sboxes_address111 = tmp_35_5_10_fu_7990_p1;
assign sboxes_address112 = tmp_35_5_11_fu_7995_p1;
assign sboxes_address113 = tmp_35_5_12_fu_8000_p1;
assign sboxes_address114 = tmp_35_5_13_fu_8005_p1;
assign sboxes_address115 = tmp_35_5_14_fu_8010_p1;
assign sboxes_address116 = tmp_60_5_fu_8015_p1;
assign sboxes_address117 = tmp_61_5_fu_8020_p1;
assign sboxes_address118 = tmp_62_5_fu_8025_p1;
assign sboxes_address119 = tmp_63_5_fu_8030_p1;
assign sboxes_address12 = tmp_35_0_11_fu_2785_p1;
assign sboxes_address120 = tmp_35_6_fu_8977_p1;
assign sboxes_address121 = tmp_35_6_1_fu_8982_p1;
assign sboxes_address122 = tmp_35_6_2_fu_8987_p1;
assign sboxes_address123 = tmp_35_6_3_fu_8992_p1;
assign sboxes_address124 = tmp_35_6_4_fu_8997_p1;
assign sboxes_address125 = tmp_35_6_5_fu_9002_p1;
assign sboxes_address126 = tmp_35_6_6_fu_9007_p1;
assign sboxes_address127 = tmp_35_6_7_fu_9012_p1;
assign sboxes_address128 = tmp_35_6_8_fu_9017_p1;
assign sboxes_address129 = tmp_35_6_9_fu_9022_p1;
assign sboxes_address13 = tmp_35_0_12_fu_2790_p1;
assign sboxes_address130 = tmp_35_6_s_fu_9027_p1;
assign sboxes_address131 = tmp_35_6_10_fu_9032_p1;
assign sboxes_address132 = tmp_35_6_11_fu_9037_p1;
assign sboxes_address133 = tmp_35_6_12_fu_9042_p1;
assign sboxes_address134 = tmp_35_6_13_fu_9047_p1;
assign sboxes_address135 = tmp_35_6_14_fu_9052_p1;
assign sboxes_address136 = tmp_60_6_fu_9057_p1;
assign sboxes_address137 = tmp_61_6_fu_9062_p1;
assign sboxes_address138 = tmp_62_6_fu_9067_p1;
assign sboxes_address139 = tmp_63_6_fu_9072_p1;
assign sboxes_address14 = tmp_35_0_13_fu_2795_p1;
assign sboxes_address140 = tmp_35_7_fu_10019_p1;
assign sboxes_address141 = tmp_35_7_1_fu_10024_p1;
assign sboxes_address142 = tmp_35_7_2_fu_10029_p1;
assign sboxes_address143 = tmp_35_7_3_fu_10034_p1;
assign sboxes_address144 = tmp_35_7_4_fu_10039_p1;
assign sboxes_address145 = tmp_35_7_5_fu_10044_p1;
assign sboxes_address146 = tmp_35_7_6_fu_10049_p1;
assign sboxes_address147 = tmp_35_7_7_fu_10054_p1;
assign sboxes_address148 = tmp_35_7_8_fu_10059_p1;
assign sboxes_address149 = tmp_35_7_9_fu_10064_p1;
assign sboxes_address15 = tmp_35_0_14_fu_2800_p1;
assign sboxes_address150 = tmp_35_7_s_fu_10069_p1;
assign sboxes_address151 = tmp_35_7_10_fu_10074_p1;
assign sboxes_address152 = tmp_35_7_11_fu_10079_p1;
assign sboxes_address153 = tmp_35_7_12_fu_10084_p1;
assign sboxes_address154 = tmp_35_7_13_fu_10089_p1;
assign sboxes_address155 = tmp_35_7_14_fu_10094_p1;
assign sboxes_address156 = tmp_60_7_fu_10099_p1;
assign sboxes_address157 = tmp_61_7_fu_10104_p1;
assign sboxes_address158 = tmp_62_7_fu_10109_p1;
assign sboxes_address159 = tmp_63_7_fu_10114_p1;
assign sboxes_address16 = tmp_60_fu_2805_p1;
assign sboxes_address160 = tmp_35_8_fu_11061_p1;
assign sboxes_address161 = tmp_35_8_1_fu_11066_p1;
assign sboxes_address162 = tmp_35_8_2_fu_11071_p1;
assign sboxes_address163 = tmp_35_8_3_fu_11076_p1;
assign sboxes_address164 = tmp_35_8_4_fu_11081_p1;
assign sboxes_address165 = tmp_35_8_5_fu_11086_p1;
assign sboxes_address166 = tmp_35_8_6_fu_11091_p1;
assign sboxes_address167 = tmp_35_8_7_fu_11096_p1;
assign sboxes_address168 = tmp_35_8_8_fu_11101_p1;
assign sboxes_address169 = tmp_35_8_9_fu_11106_p1;
assign sboxes_address17 = tmp_61_fu_2810_p1;
assign sboxes_address170 = tmp_35_8_s_fu_11111_p1;
assign sboxes_address171 = tmp_35_8_10_fu_11116_p1;
assign sboxes_address172 = tmp_35_8_11_fu_11121_p1;
assign sboxes_address173 = tmp_35_8_12_fu_11126_p1;
assign sboxes_address174 = tmp_35_8_13_fu_11131_p1;
assign sboxes_address175 = tmp_35_8_14_fu_11136_p1;
assign sboxes_address176 = tmp_60_8_fu_11141_p1;
assign sboxes_address177 = tmp_61_8_fu_11146_p1;
assign sboxes_address178 = tmp_62_8_fu_11151_p1;
assign sboxes_address179 = tmp_63_8_fu_11156_p1;
assign sboxes_address18 = tmp_62_fu_2815_p1;
assign sboxes_address180 = tmp_33_fu_12103_p1;
assign sboxes_address181 = tmp_33_1_fu_12108_p1;
assign sboxes_address182 = tmp_33_2_fu_12113_p1;
assign sboxes_address183 = tmp_33_3_fu_12118_p1;
assign sboxes_address184 = tmp_33_4_fu_12123_p1;
assign sboxes_address185 = tmp_33_5_fu_12128_p1;
assign sboxes_address186 = tmp_33_6_fu_12133_p1;
assign sboxes_address187 = tmp_33_7_fu_12138_p1;
assign sboxes_address188 = tmp_33_8_fu_12143_p1;
assign sboxes_address189 = tmp_33_9_fu_12148_p1;
assign sboxes_address19 = tmp_63_fu_2820_p1;
assign sboxes_address190 = tmp_33_s_fu_12153_p1;
assign sboxes_address191 = tmp_33_10_fu_12158_p1;
assign sboxes_address192 = tmp_33_11_fu_12163_p1;
assign sboxes_address193 = tmp_33_12_fu_12168_p1;
assign sboxes_address194 = tmp_33_13_fu_12173_p1;
assign sboxes_address195 = tmp_33_14_fu_12178_p1;
assign sboxes_address196 = tmp_s_fu_12183_p1;
assign sboxes_address197 = tmp_1_fu_12188_p1;
assign sboxes_address198 = tmp_2_fu_12193_p1;
assign sboxes_address199 = tmp_3_fu_12198_p1;
assign sboxes_address2 = tmp_35_0_2_fu_2735_p1;
assign sboxes_address20 = tmp_35_1_fu_3767_p1;
assign sboxes_address21 = tmp_35_1_1_fu_3772_p1;
assign sboxes_address22 = tmp_35_1_2_fu_3777_p1;
assign sboxes_address23 = tmp_35_1_3_fu_3782_p1;
assign sboxes_address24 = tmp_35_1_4_fu_3787_p1;
assign sboxes_address25 = tmp_35_1_5_fu_3792_p1;
assign sboxes_address26 = tmp_35_1_6_fu_3797_p1;
assign sboxes_address27 = tmp_35_1_7_fu_3802_p1;
assign sboxes_address28 = tmp_35_1_8_fu_3807_p1;
assign sboxes_address29 = tmp_35_1_9_fu_3812_p1;
assign sboxes_address3 = tmp_35_0_3_fu_2740_p1;
assign sboxes_address30 = tmp_35_1_s_fu_3817_p1;
assign sboxes_address31 = tmp_35_1_10_fu_3822_p1;
assign sboxes_address32 = tmp_35_1_11_fu_3827_p1;
assign sboxes_address33 = tmp_35_1_12_fu_3832_p1;
assign sboxes_address34 = tmp_35_1_13_fu_3837_p1;
assign sboxes_address35 = tmp_35_1_14_fu_3842_p1;
assign sboxes_address36 = tmp_60_1_fu_3847_p1;
assign sboxes_address37 = tmp_61_1_fu_3852_p1;
assign sboxes_address38 = tmp_62_1_fu_3857_p1;
assign sboxes_address39 = tmp_63_1_fu_3862_p1;
assign sboxes_address4 = tmp_35_0_4_fu_2745_p1;
assign sboxes_address40 = tmp_35_2_fu_4809_p1;
assign sboxes_address41 = tmp_35_2_1_fu_4814_p1;
assign sboxes_address42 = tmp_35_2_2_fu_4819_p1;
assign sboxes_address43 = tmp_35_2_3_fu_4824_p1;
assign sboxes_address44 = tmp_35_2_4_fu_4829_p1;
assign sboxes_address45 = tmp_35_2_5_fu_4834_p1;
assign sboxes_address46 = tmp_35_2_6_fu_4839_p1;
assign sboxes_address47 = tmp_35_2_7_fu_4844_p1;
assign sboxes_address48 = tmp_35_2_8_fu_4849_p1;
assign sboxes_address49 = tmp_35_2_9_fu_4854_p1;
assign sboxes_address5 = tmp_35_0_5_fu_2750_p1;
assign sboxes_address50 = tmp_35_2_s_fu_4859_p1;
assign sboxes_address51 = tmp_35_2_10_fu_4864_p1;
assign sboxes_address52 = tmp_35_2_11_fu_4869_p1;
assign sboxes_address53 = tmp_35_2_12_fu_4874_p1;
assign sboxes_address54 = tmp_35_2_13_fu_4879_p1;
assign sboxes_address55 = tmp_35_2_14_fu_4884_p1;
assign sboxes_address56 = tmp_60_2_fu_4889_p1;
assign sboxes_address57 = tmp_61_2_fu_4894_p1;
assign sboxes_address58 = tmp_62_2_fu_4899_p1;
assign sboxes_address59 = tmp_63_2_fu_4904_p1;
assign sboxes_address6 = tmp_35_0_6_fu_2755_p1;
assign sboxes_address60 = tmp_35_3_fu_5851_p1;
assign sboxes_address61 = tmp_35_3_1_fu_5856_p1;
assign sboxes_address62 = tmp_35_3_2_fu_5861_p1;
assign sboxes_address63 = tmp_35_3_3_fu_5866_p1;
assign sboxes_address64 = tmp_35_3_4_fu_5871_p1;
assign sboxes_address65 = tmp_35_3_5_fu_5876_p1;
assign sboxes_address66 = tmp_35_3_6_fu_5881_p1;
assign sboxes_address67 = tmp_35_3_7_fu_5886_p1;
assign sboxes_address68 = tmp_35_3_8_fu_5891_p1;
assign sboxes_address69 = tmp_35_3_9_fu_5896_p1;
assign sboxes_address7 = tmp_35_0_7_fu_2760_p1;
assign sboxes_address70 = tmp_35_3_s_fu_5901_p1;
assign sboxes_address71 = tmp_35_3_10_fu_5906_p1;
assign sboxes_address72 = tmp_35_3_11_fu_5911_p1;
assign sboxes_address73 = tmp_35_3_12_fu_5916_p1;
assign sboxes_address74 = tmp_35_3_13_fu_5921_p1;
assign sboxes_address75 = tmp_35_3_14_fu_5926_p1;
assign sboxes_address76 = tmp_60_3_fu_5931_p1;
assign sboxes_address77 = tmp_61_3_fu_5936_p1;
assign sboxes_address78 = tmp_62_3_fu_5941_p1;
assign sboxes_address79 = tmp_63_3_fu_5946_p1;
assign sboxes_address8 = tmp_35_0_8_fu_2765_p1;
assign sboxes_address80 = tmp_35_4_fu_6893_p1;
assign sboxes_address81 = tmp_35_4_1_fu_6898_p1;
assign sboxes_address82 = tmp_35_4_2_fu_6903_p1;
assign sboxes_address83 = tmp_35_4_3_fu_6908_p1;
assign sboxes_address84 = tmp_35_4_4_fu_6913_p1;
assign sboxes_address85 = tmp_35_4_5_fu_6918_p1;
assign sboxes_address86 = tmp_35_4_6_fu_6923_p1;
assign sboxes_address87 = tmp_35_4_7_fu_6928_p1;
assign sboxes_address88 = tmp_35_4_8_fu_6933_p1;
assign sboxes_address89 = tmp_35_4_9_fu_6938_p1;
assign sboxes_address9 = tmp_35_0_9_fu_2770_p1;
assign sboxes_address90 = tmp_35_4_s_fu_6943_p1;
assign sboxes_address91 = tmp_35_4_10_fu_6948_p1;
assign sboxes_address92 = tmp_35_4_11_fu_6953_p1;
assign sboxes_address93 = tmp_35_4_12_fu_6958_p1;
assign sboxes_address94 = tmp_35_4_13_fu_6963_p1;
assign sboxes_address95 = tmp_35_4_14_fu_6968_p1;
assign sboxes_address96 = tmp_60_4_fu_6973_p1;
assign sboxes_address97 = tmp_61_4_fu_6978_p1;
assign sboxes_address98 = tmp_62_4_fu_6983_p1;
assign sboxes_address99 = tmp_63_4_fu_6988_p1;
assign tmp100_fu_6663_p2 = (tmp_47_3_fu_5957_p2 ^ tmp_68_3_fu_6564_p2);
assign tmp101_fu_6675_p2 = (sboxes_q64 ^ rv_2_3_1_fu_6137_p3);
assign tmp102_fu_6681_p2 = (e_3_1_fu_6111_p2 ^ tmp_69_3_fu_6569_p2);
assign tmp103_fu_6693_p2 = (sboxes_q69 ^ e_3_1_fu_6111_p2);
assign tmp104_fu_6699_p2 = (rv_5_3_1_fu_6171_p3 ^ tmp_70_3_fu_6574_p2);
assign tmp105_fu_6711_p2 = (sboxes_q63 ^ x_assign_375_1_fu_6099_p2);
assign tmp106_fu_6717_p2 = (rv_8_3_1_fu_6205_p3 ^ tmp_71_3_fu_6579_p2);
assign tmp107_fu_6729_p2 = (tmp_47_3_1_fu_6105_p2 ^ tmp_72_3_fu_6584_p2);
assign tmp108_fu_6741_p2 = (sboxes_q68 ^ rv_2_3_2_fu_6285_p3);
assign tmp109_fu_6752_p2 = (tmp110_fu_6747_p2 ^ e_3_2_fu_6259_p2);
assign tmp10_fu_3587_p2 = (sboxes_q9 ^ e_0_1_fu_2985_p2);
assign tmp110_fu_6747_p2 = (tmp_69_3_fu_6569_p2 ^ tmp_73_2_reg_12941);
assign tmp111_fu_6764_p2 = (sboxes_q73 ^ e_3_2_fu_6259_p2);
assign tmp112_fu_6775_p2 = (tmp113_fu_6770_p2 ^ rv_5_3_2_fu_6319_p3);
assign tmp113_fu_6770_p2 = (tmp_70_3_fu_6574_p2 ^ tmp_74_2_reg_12947);
assign tmp114_fu_6787_p2 = (sboxes_q67 ^ x_assign_375_2_fu_6247_p2);
assign tmp115_fu_6798_p2 = (tmp116_fu_6793_p2 ^ rv_8_3_2_fu_6353_p3);
assign tmp116_fu_6793_p2 = (tmp_71_3_fu_6579_p2 ^ tmp_75_2_reg_12953);
assign tmp117_fu_6810_p2 = (rv_11_3_2_fu_6387_p3 ^ tmp_47_3_2_fu_6253_p2);
assign tmp118_fu_6816_p2 = (tmp_72_3_fu_6584_p2 ^ tmp_76_2_reg_12959);
assign tmp119_fu_6827_p2 = (sboxes_q72 ^ rv_2_3_3_fu_6433_p3);
assign tmp11_fu_3593_p2 = (rv_5_0_1_fu_3045_p3 ^ tmp_70_fu_3448_p2);
assign tmp120_fu_6833_p2 = (e_3_3_fu_6407_p2 ^ tmp_77_3_fu_6589_p2);
assign tmp121_fu_6845_p2 = (sboxes_q61 ^ e_3_3_fu_6407_p2);
assign tmp122_fu_6851_p2 = (rv_5_3_3_fu_6467_p3 ^ tmp_78_3_fu_6594_p2);
assign tmp123_fu_6863_p2 = (sboxes_q71 ^ x_assign_375_3_fu_6395_p2);
assign tmp124_fu_6869_p2 = (rv_8_3_3_fu_6501_p3 ^ tmp_79_3_fu_6599_p2);
assign tmp125_fu_6881_p2 = (tmp_47_3_3_fu_6401_p2 ^ tmp_80_3_fu_6604_p2);
assign tmp126_fu_7585_p2 = (tmp_65_3_reg_13065 ^ 8'd16);
assign tmp127_fu_7651_p2 = (sboxes_q80 ^ rv_2_4_fu_7031_p3);
assign tmp128_fu_7657_p2 = (e_4_fu_7005_p2 ^ tmp_65_4_fu_7590_p2);
assign tmp129_fu_7669_p2 = (sboxes_q85 ^ e_4_fu_7005_p2);
assign tmp12_fu_3605_p2 = (sboxes_q3 ^ x_assign_0_1_fu_2973_p2);
assign tmp130_fu_7675_p2 = (rv_5_4_fu_7065_p3 ^ tmp_66_4_fu_7596_p2);
assign tmp131_fu_7687_p2 = (sboxes_q95 ^ x_assign_4_fu_6993_p2);
assign tmp132_fu_7693_p2 = (rv_8_4_fu_7099_p3 ^ tmp_67_4_fu_7601_p2);
assign tmp133_fu_7705_p2 = (tmp_47_4_fu_6999_p2 ^ tmp_68_4_fu_7606_p2);
assign tmp134_fu_7717_p2 = (sboxes_q84 ^ rv_2_4_1_fu_7179_p3);
assign tmp135_fu_7728_p2 = (tmp136_fu_7723_p2 ^ e_4_1_fu_7153_p2);
assign tmp136_fu_7723_p2 = (tmp_65_4_fu_7590_p2 ^ tmp_69_3_reg_13085);
assign tmp137_fu_7740_p2 = (sboxes_q89 ^ e_4_1_fu_7153_p2);
assign tmp138_fu_7751_p2 = (tmp139_fu_7746_p2 ^ rv_5_4_1_fu_7213_p3);
assign tmp139_fu_7746_p2 = (tmp_66_4_fu_7596_p2 ^ tmp_70_3_reg_13091);
assign tmp13_fu_3611_p2 = (rv_8_0_1_fu_3079_p3 ^ tmp_71_fu_3453_p2);
assign tmp140_fu_7763_p2 = (sboxes_q83 ^ x_assign_4_1_fu_7141_p2);
assign tmp141_fu_7774_p2 = (tmp142_fu_7769_p2 ^ rv_8_4_1_fu_7247_p3);
assign tmp142_fu_7769_p2 = (tmp_67_4_fu_7601_p2 ^ tmp_71_3_reg_13097);
assign tmp143_fu_7786_p2 = (rv_11_4_1_fu_7281_p3 ^ tmp_47_4_1_fu_7147_p2);
assign tmp144_fu_7792_p2 = (tmp_68_4_fu_7606_p2 ^ tmp_72_3_reg_13103);
assign tmp145_fu_7803_p2 = (sboxes_q88 ^ rv_2_4_2_fu_7327_p3);
assign tmp146_fu_7809_p2 = (e_4_2_fu_7301_p2 ^ tmp_73_4_fu_7611_p2);
assign tmp147_fu_7821_p2 = (sboxes_q93 ^ e_4_2_fu_7301_p2);
assign tmp148_fu_7827_p2 = (rv_5_4_2_fu_7361_p3 ^ tmp_74_4_fu_7616_p2);
assign tmp149_fu_7839_p2 = (sboxes_q87 ^ x_assign_4_2_fu_7289_p2);
assign tmp14_fu_3623_p2 = (tmp_47_0_1_fu_2979_p2 ^ tmp_72_fu_3458_p2);
assign tmp150_fu_7845_p2 = (rv_8_4_2_fu_7395_p3 ^ tmp_75_4_fu_7621_p2);
assign tmp151_fu_7857_p2 = (tmp_47_4_2_fu_7295_p2 ^ tmp_76_4_fu_7626_p2);
assign tmp152_fu_7869_p2 = (sboxes_q92 ^ rv_2_4_3_fu_7475_p3);
assign tmp153_fu_7875_p2 = (e_4_3_fu_7449_p2 ^ tmp_77_4_fu_7631_p2);
assign tmp154_fu_7887_p2 = (sboxes_q81 ^ e_4_3_fu_7449_p2);
assign tmp155_fu_7893_p2 = (rv_5_4_3_fu_7509_p3 ^ tmp_78_4_fu_7636_p2);
assign tmp156_fu_7905_p2 = (sboxes_q91 ^ x_assign_4_3_fu_7437_p2);
assign tmp157_fu_7911_p2 = (rv_8_4_3_fu_7543_p3 ^ tmp_79_4_fu_7641_p2);
assign tmp158_fu_7923_p2 = (tmp_47_4_3_fu_7443_p2 ^ tmp_80_4_fu_7646_p2);
assign tmp159_fu_8693_p2 = (sboxes_q100 ^ rv_2_5_fu_8073_p3);
assign tmp15_fu_3635_p2 = (sboxes_q8 ^ rv_2_0_2_fu_3159_p3);
assign tmp160_fu_8699_p2 = (e_5_fu_8047_p2 ^ tmp_65_5_fu_8633_p2);
assign tmp161_fu_8711_p2 = (sboxes_q105 ^ e_5_fu_8047_p2);
assign tmp162_fu_8717_p2 = (rv_5_5_fu_8107_p3 ^ tmp_66_5_fu_8638_p2);
assign tmp163_fu_8729_p2 = (sboxes_q115 ^ x_assign_5_fu_8035_p2);
assign tmp164_fu_8735_p2 = (rv_8_5_fu_8141_p3 ^ tmp_67_5_fu_8643_p2);
assign tmp165_fu_8747_p2 = (tmp_47_5_fu_8041_p2 ^ tmp_68_5_fu_8648_p2);
assign tmp166_fu_8759_p2 = (sboxes_q104 ^ rv_2_5_1_fu_8221_p3);
assign tmp167_fu_8765_p2 = (e_5_1_fu_8195_p2 ^ tmp_69_5_fu_8653_p2);
assign tmp168_fu_8777_p2 = (sboxes_q109 ^ e_5_1_fu_8195_p2);
assign tmp169_fu_8783_p2 = (rv_5_5_1_fu_8255_p3 ^ tmp_70_5_fu_8658_p2);
assign tmp16_fu_3641_p2 = (e_0_2_fu_3133_p2 ^ tmp_73_fu_3463_p2);
assign tmp170_fu_8795_p2 = (sboxes_q103 ^ x_assign_5_1_fu_8183_p2);
assign tmp171_fu_8801_p2 = (rv_8_5_1_fu_8289_p3 ^ tmp_71_5_fu_8663_p2);
assign tmp172_fu_8813_p2 = (tmp_47_5_1_fu_8189_p2 ^ tmp_72_5_fu_8668_p2);
assign tmp173_fu_8825_p2 = (sboxes_q108 ^ rv_2_5_2_fu_8369_p3);
assign tmp174_fu_8836_p2 = (tmp175_fu_8831_p2 ^ e_5_2_fu_8343_p2);
assign tmp175_fu_8831_p2 = (tmp_69_5_fu_8653_p2 ^ tmp_73_4_reg_13257);
assign tmp176_fu_8848_p2 = (sboxes_q113 ^ e_5_2_fu_8343_p2);
assign tmp177_fu_8859_p2 = (tmp178_fu_8854_p2 ^ rv_5_5_2_fu_8403_p3);
assign tmp178_fu_8854_p2 = (tmp_70_5_fu_8658_p2 ^ tmp_74_4_reg_13263);
assign tmp179_fu_8871_p2 = (sboxes_q107 ^ x_assign_5_2_fu_8331_p2);
assign tmp17_fu_3653_p2 = (sboxes_q13 ^ e_0_2_fu_3133_p2);
assign tmp180_fu_8882_p2 = (tmp181_fu_8877_p2 ^ rv_8_5_2_fu_8437_p3);
assign tmp181_fu_8877_p2 = (tmp_71_5_fu_8663_p2 ^ tmp_75_4_reg_13269);
assign tmp182_fu_8894_p2 = (rv_11_5_2_fu_8471_p3 ^ tmp_47_5_2_fu_8337_p2);
assign tmp183_fu_8900_p2 = (tmp_72_5_fu_8668_p2 ^ tmp_76_4_reg_13275);
assign tmp184_fu_8911_p2 = (sboxes_q112 ^ rv_2_5_3_fu_8517_p3);
assign tmp185_fu_8917_p2 = (e_5_3_fu_8491_p2 ^ tmp_77_5_fu_8673_p2);
assign tmp186_fu_8929_p2 = (sboxes_q101 ^ e_5_3_fu_8491_p2);
assign tmp187_fu_8935_p2 = (rv_5_5_3_fu_8551_p3 ^ tmp_78_5_fu_8678_p2);
assign tmp188_fu_8947_p2 = (sboxes_q111 ^ x_assign_5_3_fu_8479_p2);
assign tmp189_fu_8953_p2 = (rv_8_5_3_fu_8585_p3 ^ tmp_79_5_fu_8683_p2);
assign tmp18_fu_3659_p2 = (rv_5_0_2_fu_3193_p3 ^ tmp_74_fu_3468_p2);
assign tmp190_fu_8965_p2 = (tmp_47_5_3_fu_8485_p2 ^ tmp_80_5_fu_8688_p2);
assign tmp191_fu_9669_p2 = (tmp_65_5_reg_13381 ^ 8'd64);
assign tmp192_fu_9735_p2 = (sboxes_q120 ^ rv_2_6_fu_9115_p3);
assign tmp193_fu_9741_p2 = (e_6_fu_9089_p2 ^ tmp_65_6_fu_9674_p2);
assign tmp194_fu_9753_p2 = (sboxes_q125 ^ e_6_fu_9089_p2);
assign tmp195_fu_9759_p2 = (rv_5_6_fu_9149_p3 ^ tmp_66_6_fu_9680_p2);
assign tmp196_fu_9771_p2 = (sboxes_q135 ^ x_assign_6_fu_9077_p2);
assign tmp197_fu_9777_p2 = (rv_8_6_fu_9183_p3 ^ tmp_67_6_fu_9685_p2);
assign tmp198_fu_9789_p2 = (tmp_47_6_fu_9083_p2 ^ tmp_68_6_fu_9690_p2);
assign tmp199_fu_9801_p2 = (sboxes_q124 ^ rv_2_6_1_fu_9263_p3);
assign tmp19_fu_3671_p2 = (sboxes_q7 ^ x_assign_0_2_fu_3121_p2);
assign tmp1_fu_3503_p2 = (sboxes_q0 ^ rv_2_fu_2863_p3);
assign tmp200_fu_9812_p2 = (tmp201_fu_9807_p2 ^ e_6_1_fu_9237_p2);
assign tmp201_fu_9807_p2 = (tmp_65_6_fu_9674_p2 ^ tmp_69_5_reg_13401);
assign tmp202_fu_9824_p2 = (sboxes_q129 ^ e_6_1_fu_9237_p2);
assign tmp203_fu_9835_p2 = (tmp204_fu_9830_p2 ^ rv_5_6_1_fu_9297_p3);
assign tmp204_fu_9830_p2 = (tmp_66_6_fu_9680_p2 ^ tmp_70_5_reg_13407);
assign tmp205_fu_9847_p2 = (sboxes_q123 ^ x_assign_6_1_fu_9225_p2);
assign tmp206_fu_9858_p2 = (tmp207_fu_9853_p2 ^ rv_8_6_1_fu_9331_p3);
assign tmp207_fu_9853_p2 = (tmp_67_6_fu_9685_p2 ^ tmp_71_5_reg_13413);
assign tmp208_fu_9870_p2 = (rv_11_6_1_fu_9365_p3 ^ tmp_47_6_1_fu_9231_p2);
assign tmp209_fu_9876_p2 = (tmp_68_6_fu_9690_p2 ^ tmp_72_5_reg_13419);
assign tmp20_fu_3677_p2 = (rv_8_0_2_fu_3227_p3 ^ tmp_75_fu_3473_p2);
assign tmp210_fu_9887_p2 = (sboxes_q128 ^ rv_2_6_2_fu_9411_p3);
assign tmp211_fu_9893_p2 = (e_6_2_fu_9385_p2 ^ tmp_73_6_fu_9695_p2);
assign tmp212_fu_9905_p2 = (sboxes_q133 ^ e_6_2_fu_9385_p2);
assign tmp213_fu_9911_p2 = (rv_5_6_2_fu_9445_p3 ^ tmp_74_6_fu_9700_p2);
assign tmp214_fu_9923_p2 = (sboxes_q127 ^ x_assign_6_2_fu_9373_p2);
assign tmp215_fu_9929_p2 = (rv_8_6_2_fu_9479_p3 ^ tmp_75_6_fu_9705_p2);
assign tmp216_fu_9941_p2 = (tmp_47_6_2_fu_9379_p2 ^ tmp_76_6_fu_9710_p2);
assign tmp217_fu_9953_p2 = (sboxes_q132 ^ rv_2_6_3_fu_9559_p3);
assign tmp218_fu_9959_p2 = (e_6_3_fu_9533_p2 ^ tmp_77_6_fu_9715_p2);
assign tmp219_fu_9971_p2 = (sboxes_q121 ^ e_6_3_fu_9533_p2);
assign tmp21_fu_3689_p2 = (tmp_47_0_2_fu_3127_p2 ^ tmp_76_fu_3478_p2);
assign tmp220_fu_9977_p2 = (rv_5_6_3_fu_9593_p3 ^ tmp_78_6_fu_9720_p2);
assign tmp221_fu_9989_p2 = (sboxes_q131 ^ x_assign_6_3_fu_9521_p2);
assign tmp222_fu_9995_p2 = (rv_8_6_3_fu_9627_p3 ^ tmp_79_6_fu_9725_p2);
assign tmp223_fu_10007_p2 = (tmp_47_6_3_fu_9527_p2 ^ tmp_80_6_fu_9730_p2);
assign tmp224_fu_10777_p2 = (sboxes_q140 ^ rv_2_7_fu_10157_p3);
assign tmp225_fu_10783_p2 = (e_7_fu_10131_p2 ^ tmp_65_7_fu_10717_p2);
assign tmp226_fu_10795_p2 = (sboxes_q145 ^ e_7_fu_10131_p2);
assign tmp227_fu_10801_p2 = (rv_5_7_fu_10191_p3 ^ tmp_66_7_fu_10722_p2);
assign tmp228_fu_10813_p2 = (sboxes_q155 ^ x_assign_7_fu_10119_p2);
assign tmp229_fu_10819_p2 = (rv_8_7_fu_10225_p3 ^ tmp_67_7_fu_10727_p2);
assign tmp22_fu_3701_p2 = (sboxes_q12 ^ rv_2_0_3_fu_3307_p3);
assign tmp230_fu_10831_p2 = (tmp_47_7_fu_10125_p2 ^ tmp_68_7_fu_10732_p2);
assign tmp231_fu_10843_p2 = (sboxes_q144 ^ rv_2_7_1_fu_10305_p3);
assign tmp232_fu_10849_p2 = (e_7_1_fu_10279_p2 ^ tmp_69_7_fu_10737_p2);
assign tmp233_fu_10861_p2 = (sboxes_q149 ^ e_7_1_fu_10279_p2);
assign tmp234_fu_10867_p2 = (rv_5_7_1_fu_10339_p3 ^ tmp_70_7_fu_10742_p2);
assign tmp235_fu_10879_p2 = (sboxes_q143 ^ x_assign_7_1_fu_10267_p2);
assign tmp236_fu_10885_p2 = (rv_8_7_1_fu_10373_p3 ^ tmp_71_7_fu_10747_p2);
assign tmp237_fu_10897_p2 = (tmp_47_7_1_fu_10273_p2 ^ tmp_72_7_fu_10752_p2);
assign tmp238_fu_10909_p2 = (sboxes_q148 ^ rv_2_7_2_fu_10453_p3);
assign tmp239_fu_10920_p2 = (tmp240_fu_10915_p2 ^ e_7_2_fu_10427_p2);
assign tmp23_fu_3707_p2 = (e_0_3_fu_3281_p2 ^ tmp_77_fu_3483_p2);
assign tmp240_fu_10915_p2 = (tmp_69_7_fu_10737_p2 ^ tmp_73_6_reg_13565);
assign tmp241_fu_10932_p2 = (sboxes_q153 ^ e_7_2_fu_10427_p2);
assign tmp242_fu_10943_p2 = (tmp243_fu_10938_p2 ^ rv_5_7_2_fu_10487_p3);
assign tmp243_fu_10938_p2 = (tmp_70_7_fu_10742_p2 ^ tmp_74_6_reg_13571);
assign tmp244_fu_10955_p2 = (sboxes_q147 ^ x_assign_7_2_fu_10415_p2);
assign tmp245_fu_10966_p2 = (tmp246_fu_10961_p2 ^ rv_8_7_2_fu_10521_p3);
assign tmp246_fu_10961_p2 = (tmp_71_7_fu_10747_p2 ^ tmp_75_6_reg_13577);
assign tmp247_fu_10978_p2 = (rv_11_7_2_fu_10555_p3 ^ tmp_47_7_2_fu_10421_p2);
assign tmp248_fu_10984_p2 = (tmp_72_7_fu_10752_p2 ^ tmp_76_6_reg_13583);
assign tmp249_fu_10995_p2 = (sboxes_q152 ^ rv_2_7_3_fu_10601_p3);
assign tmp24_fu_3719_p2 = (sboxes_q1 ^ e_0_3_fu_3281_p2);
assign tmp250_fu_11001_p2 = (e_7_3_fu_10575_p2 ^ tmp_77_7_fu_10757_p2);
assign tmp251_fu_11013_p2 = (sboxes_q141 ^ e_7_3_fu_10575_p2);
assign tmp252_fu_11019_p2 = (rv_5_7_3_fu_10635_p3 ^ tmp_78_7_fu_10762_p2);
assign tmp253_fu_11031_p2 = (sboxes_q151 ^ x_assign_7_3_fu_10563_p2);
assign tmp254_fu_11037_p2 = (rv_8_7_3_fu_10669_p3 ^ tmp_79_7_fu_10767_p2);
assign tmp255_fu_11049_p2 = (tmp_47_7_3_fu_10569_p2 ^ tmp_80_7_fu_10772_p2);
assign tmp256_fu_11753_p2 = (tmp_65_7_reg_13689 ^ 8'd27);
assign tmp257_fu_11819_p2 = (sboxes_q160 ^ rv_2_8_fu_11199_p3);
assign tmp258_fu_11825_p2 = (e_8_fu_11173_p2 ^ tmp_65_8_fu_11758_p2);
assign tmp259_fu_11837_p2 = (sboxes_q165 ^ e_8_fu_11173_p2);
assign tmp25_fu_3725_p2 = (rv_5_0_3_fu_3341_p3 ^ tmp_78_fu_3488_p2);
assign tmp260_fu_11843_p2 = (rv_5_8_fu_11233_p3 ^ tmp_66_8_fu_11764_p2);
assign tmp261_fu_11855_p2 = (sboxes_q175 ^ x_assign_8_fu_11161_p2);
assign tmp262_fu_11861_p2 = (rv_8_8_fu_11267_p3 ^ tmp_67_8_fu_11769_p2);
assign tmp263_fu_11873_p2 = (tmp_47_8_fu_11167_p2 ^ tmp_68_8_fu_11774_p2);
assign tmp264_fu_11885_p2 = (sboxes_q164 ^ rv_2_8_1_fu_11347_p3);
assign tmp265_fu_11896_p2 = (tmp266_fu_11891_p2 ^ e_8_1_fu_11321_p2);
assign tmp266_fu_11891_p2 = (tmp_65_8_fu_11758_p2 ^ tmp_69_7_reg_13709);
assign tmp267_fu_11908_p2 = (sboxes_q169 ^ e_8_1_fu_11321_p2);
assign tmp268_fu_11919_p2 = (tmp269_fu_11914_p2 ^ rv_5_8_1_fu_11381_p3);
assign tmp269_fu_11914_p2 = (tmp_66_8_fu_11764_p2 ^ tmp_70_7_reg_13715);
assign tmp26_fu_3737_p2 = (sboxes_q11 ^ x_assign_0_3_fu_3269_p2);
assign tmp270_fu_11931_p2 = (sboxes_q163 ^ x_assign_8_1_fu_11309_p2);
assign tmp271_fu_11942_p2 = (tmp272_fu_11937_p2 ^ rv_8_8_1_fu_11415_p3);
assign tmp272_fu_11937_p2 = (tmp_67_8_fu_11769_p2 ^ tmp_71_7_reg_13721);
assign tmp273_fu_11954_p2 = (rv_11_8_1_fu_11449_p3 ^ tmp_47_8_1_fu_11315_p2);
assign tmp274_fu_11960_p2 = (tmp_68_8_fu_11774_p2 ^ tmp_72_7_reg_13727);
assign tmp275_fu_11971_p2 = (sboxes_q168 ^ rv_2_8_2_fu_11495_p3);
assign tmp276_fu_11977_p2 = (e_8_2_fu_11469_p2 ^ tmp_73_8_fu_11779_p2);
assign tmp277_fu_11989_p2 = (sboxes_q173 ^ e_8_2_fu_11469_p2);
assign tmp278_fu_11995_p2 = (rv_5_8_2_fu_11529_p3 ^ tmp_74_8_fu_11784_p2);
assign tmp279_fu_12007_p2 = (sboxes_q167 ^ x_assign_8_2_fu_11457_p2);
assign tmp27_fu_3743_p2 = (rv_8_0_3_fu_3375_p3 ^ tmp_79_fu_3493_p2);
assign tmp280_fu_12013_p2 = (rv_8_8_2_fu_11563_p3 ^ tmp_75_8_fu_11789_p2);
assign tmp281_fu_12025_p2 = (tmp_47_8_2_fu_11463_p2 ^ tmp_76_8_fu_11794_p2);
assign tmp282_fu_12037_p2 = (sboxes_q172 ^ rv_2_8_3_fu_11643_p3);
assign tmp283_fu_12043_p2 = (e_8_3_fu_11617_p2 ^ tmp_77_8_fu_11799_p2);
assign tmp284_fu_12055_p2 = (sboxes_q161 ^ e_8_3_fu_11617_p2);
assign tmp285_fu_12061_p2 = (rv_5_8_3_fu_11677_p3 ^ tmp_78_8_fu_11804_p2);
assign tmp286_fu_12073_p2 = (sboxes_q171 ^ x_assign_8_3_fu_11605_p2);
assign tmp287_fu_12079_p2 = (rv_8_8_3_fu_11711_p3 ^ tmp_79_8_fu_11809_p2);
assign tmp288_fu_12091_p2 = (tmp_47_8_3_fu_11611_p2 ^ tmp_80_8_fu_11814_p2);
assign tmp289_fu_12229_p2 = (tmp_4_fu_12203_p2 ^ tmp_65_8_reg_13857);
assign tmp28_fu_3755_p2 = (tmp_47_0_3_fu_3275_p2 ^ tmp_80_fu_3498_p2);
assign tmp290_fu_12240_p2 = (sboxes_q185 ^ tmp_66_8_reg_13862);
assign tmp291_fu_12251_p2 = (sboxes_q190 ^ tmp_67_8_reg_13867);
assign tmp292_fu_12262_p2 = (sboxes_q195 ^ tmp_68_8_reg_13872);
assign tmp293_fu_12297_p2 = (tmp_73_8_reg_13877 ^ tmp_9_fu_12209_p2);
assign tmp294_fu_12308_p2 = (tmp_74_8_reg_13882 ^ tmp_11_fu_12214_p2);
assign tmp295_fu_12319_p2 = (tmp_75_8_reg_13887 ^ tmp_12_fu_12219_p2);
assign tmp296_fu_12330_p2 = (tmp_76_8_reg_13892 ^ tmp_13_fu_12224_p2);
assign tmp297_fu_12341_p2 = (tmp_9_fu_12209_p2 ^ ap_reg_pp0_iter9_tmp_77_7_reg_13733);
assign tmp298_fu_12352_p2 = (tmp_11_fu_12214_p2 ^ ap_reg_pp0_iter9_tmp_78_7_reg_13739);
assign tmp299_fu_12363_p2 = (tmp_12_fu_12219_p2 ^ ap_reg_pp0_iter9_tmp_79_7_reg_13745);
assign tmp29_fu_4525_p2 = (sboxes_q20 ^ rv_2_1_fu_3905_p3);
assign tmp2_fu_3509_p2 = (e_fu_2837_p2 ^ tmp_65_fu_3422_p2);
assign tmp300_fu_12374_p2 = (tmp_13_fu_12224_p2 ^ ap_reg_pp0_iter9_tmp_80_7_reg_13751);
assign tmp30_fu_4531_p2 = (e_1_fu_3879_p2 ^ tmp_65_1_fu_4465_p2);
assign tmp31_fu_4543_p2 = (sboxes_q25 ^ e_1_fu_3879_p2);
assign tmp32_fu_4549_p2 = (rv_5_1_fu_3939_p3 ^ tmp_66_1_fu_4470_p2);
assign tmp33_fu_4561_p2 = (sboxes_q35 ^ x_assign_s_fu_3867_p2);
assign tmp34_fu_4567_p2 = (rv_8_1_fu_3973_p3 ^ tmp_67_1_fu_4475_p2);
assign tmp35_fu_4579_p2 = (tmp_47_1_fu_3873_p2 ^ tmp_68_1_fu_4480_p2);
assign tmp36_fu_4591_p2 = (sboxes_q24 ^ rv_2_1_1_fu_4053_p3);
assign tmp37_fu_4597_p2 = (e_1_1_fu_4027_p2 ^ tmp_69_1_fu_4485_p2);
assign tmp38_fu_4609_p2 = (sboxes_q29 ^ e_1_1_fu_4027_p2);
assign tmp39_fu_4615_p2 = (rv_5_1_1_fu_4087_p3 ^ tmp_70_1_fu_4490_p2);
assign tmp3_fu_3521_p2 = (sboxes_q5 ^ e_fu_2837_p2);
assign tmp40_fu_4627_p2 = (sboxes_q23 ^ x_assign_171_1_fu_4015_p2);
assign tmp41_fu_4633_p2 = (rv_8_1_1_fu_4121_p3 ^ tmp_71_1_fu_4495_p2);
assign tmp42_fu_4645_p2 = (tmp_47_1_1_fu_4021_p2 ^ tmp_72_1_fu_4500_p2);
assign tmp43_fu_4657_p2 = (sboxes_q28 ^ rv_2_1_2_fu_4201_p3);
assign tmp44_fu_4668_p2 = (tmp45_fu_4663_p2 ^ e_1_2_fu_4175_p2);
assign tmp45_fu_4663_p2 = (tmp_69_1_fu_4485_p2 ^ tmp_73_reg_12633);
assign tmp46_fu_4680_p2 = (sboxes_q33 ^ e_1_2_fu_4175_p2);
assign tmp47_fu_4691_p2 = (tmp48_fu_4686_p2 ^ rv_5_1_2_fu_4235_p3);
assign tmp48_fu_4686_p2 = (tmp_70_1_fu_4490_p2 ^ tmp_74_reg_12639);
assign tmp49_fu_4703_p2 = (sboxes_q27 ^ x_assign_171_2_fu_4163_p2);
assign tmp4_fu_3527_p2 = (rv_5_fu_2897_p3 ^ tmp_66_fu_3428_p2);
assign tmp50_fu_4714_p2 = (tmp51_fu_4709_p2 ^ rv_8_1_2_fu_4269_p3);
assign tmp51_fu_4709_p2 = (tmp_71_1_fu_4495_p2 ^ tmp_75_reg_12645);
assign tmp52_fu_4726_p2 = (rv_11_1_2_fu_4303_p3 ^ tmp_47_1_2_fu_4169_p2);
assign tmp53_fu_4732_p2 = (tmp_72_1_fu_4500_p2 ^ tmp_76_reg_12651);
assign tmp54_fu_4743_p2 = (sboxes_q32 ^ rv_2_1_3_fu_4349_p3);
assign tmp55_fu_4749_p2 = (e_1_3_fu_4323_p2 ^ tmp_77_1_fu_4505_p2);
assign tmp56_fu_4761_p2 = (sboxes_q21 ^ e_1_3_fu_4323_p2);
assign tmp57_fu_4767_p2 = (rv_5_1_3_fu_4383_p3 ^ tmp_78_1_fu_4510_p2);
assign tmp58_fu_4779_p2 = (sboxes_q31 ^ x_assign_171_3_fu_4311_p2);
assign tmp59_fu_4785_p2 = (rv_8_1_3_fu_4417_p3 ^ tmp_79_1_fu_4515_p2);
assign tmp5_fu_3539_p2 = (sboxes_q15 ^ x_assign_fu_2825_p2);
assign tmp60_fu_4797_p2 = (tmp_47_1_3_fu_4317_p2 ^ tmp_80_1_fu_4520_p2);
assign tmp61_fu_5501_p2 = (tmp_65_1_reg_12757 ^ 8'd4);
assign tmp62_fu_5567_p2 = (sboxes_q40 ^ rv_2_2_fu_4947_p3);
assign tmp63_fu_5573_p2 = (e_2_fu_4921_p2 ^ tmp_65_2_fu_5506_p2);
assign tmp64_fu_5585_p2 = (sboxes_q45 ^ e_2_fu_4921_p2);
assign tmp65_fu_5591_p2 = (rv_5_2_fu_4981_p3 ^ tmp_66_2_fu_5512_p2);
assign tmp66_fu_5603_p2 = (sboxes_q55 ^ x_assign_9_fu_4909_p2);
assign tmp67_fu_5609_p2 = (rv_8_2_fu_5015_p3 ^ tmp_67_2_fu_5517_p2);
assign tmp68_fu_5621_p2 = (tmp_47_2_fu_4915_p2 ^ tmp_68_2_fu_5522_p2);
assign tmp69_fu_5633_p2 = (sboxes_q44 ^ rv_2_2_1_fu_5095_p3);
assign tmp6_fu_3545_p2 = (rv_8_fu_2931_p3 ^ tmp_67_fu_3433_p2);
assign tmp70_fu_5644_p2 = (tmp71_fu_5639_p2 ^ e_2_1_fu_5069_p2);
assign tmp71_fu_5639_p2 = (tmp_65_2_fu_5506_p2 ^ tmp_69_1_reg_12777);
assign tmp72_fu_5656_p2 = (sboxes_q49 ^ e_2_1_fu_5069_p2);
assign tmp73_fu_5667_p2 = (tmp74_fu_5662_p2 ^ rv_5_2_1_fu_5129_p3);
assign tmp74_fu_5662_p2 = (tmp_66_2_fu_5512_p2 ^ tmp_70_1_reg_12783);
assign tmp75_fu_5679_p2 = (sboxes_q43 ^ x_assign_273_1_fu_5057_p2);
assign tmp76_fu_5690_p2 = (tmp77_fu_5685_p2 ^ rv_8_2_1_fu_5163_p3);
assign tmp77_fu_5685_p2 = (tmp_67_2_fu_5517_p2 ^ tmp_71_1_reg_12789);
assign tmp78_fu_5702_p2 = (rv_11_2_1_fu_5197_p3 ^ tmp_47_2_1_fu_5063_p2);
assign tmp79_fu_5708_p2 = (tmp_68_2_fu_5522_p2 ^ tmp_72_1_reg_12795);
assign tmp7_fu_3557_p2 = (tmp_47_fu_2831_p2 ^ tmp_68_fu_3438_p2);
assign tmp80_fu_5719_p2 = (sboxes_q48 ^ rv_2_2_2_fu_5243_p3);
assign tmp81_fu_5725_p2 = (e_2_2_fu_5217_p2 ^ tmp_73_2_fu_5527_p2);
assign tmp82_fu_5737_p2 = (sboxes_q53 ^ e_2_2_fu_5217_p2);
assign tmp83_fu_5743_p2 = (rv_5_2_2_fu_5277_p3 ^ tmp_74_2_fu_5532_p2);
assign tmp84_fu_5755_p2 = (sboxes_q47 ^ x_assign_273_2_fu_5205_p2);
assign tmp85_fu_5761_p2 = (rv_8_2_2_fu_5311_p3 ^ tmp_75_2_fu_5537_p2);
assign tmp86_fu_5773_p2 = (tmp_47_2_2_fu_5211_p2 ^ tmp_76_2_fu_5542_p2);
assign tmp87_fu_5785_p2 = (sboxes_q52 ^ rv_2_2_3_fu_5391_p3);
assign tmp88_fu_5791_p2 = (e_2_3_fu_5365_p2 ^ tmp_77_2_fu_5547_p2);
assign tmp89_fu_5803_p2 = (sboxes_q41 ^ e_2_3_fu_5365_p2);
assign tmp8_fu_3569_p2 = (sboxes_q4 ^ rv_2_0_1_fu_3011_p3);
assign tmp90_fu_5809_p2 = (rv_5_2_3_fu_5425_p3 ^ tmp_78_2_fu_5552_p2);
assign tmp91_fu_5821_p2 = (sboxes_q51 ^ x_assign_273_3_fu_5353_p2);
assign tmp92_fu_5827_p2 = (rv_8_2_3_fu_5459_p3 ^ tmp_79_2_fu_5557_p2);
assign tmp93_fu_5839_p2 = (tmp_47_2_3_fu_5359_p2 ^ tmp_80_2_fu_5562_p2);
assign tmp94_fu_6609_p2 = (sboxes_q60 ^ rv_2_3_fu_5989_p3);
assign tmp95_fu_6615_p2 = (e_3_fu_5963_p2 ^ tmp_65_3_fu_6549_p2);
assign tmp96_fu_6627_p2 = (sboxes_q65 ^ e_3_fu_5963_p2);
assign tmp97_fu_6633_p2 = (rv_5_3_fu_6023_p3 ^ tmp_66_3_fu_6554_p2);
assign tmp98_fu_6645_p2 = (sboxes_q75 ^ x_assign_10_fu_5951_p2);
assign tmp99_fu_6651_p2 = (rv_8_3_fu_6057_p3 ^ tmp_67_3_fu_6559_p2);
assign tmp9_fu_3575_p2 = (e_0_1_fu_2985_p2 ^ tmp_69_fu_3443_p2);
assign tmp_100_fu_2625_p1 = key_V_read[7:0];
assign tmp_101_fu_2843_p2 = x_assign_fu_2825_p2 << 8'd1;
assign tmp_102_fu_2849_p3 = x_assign_fu_2825_p2[32'd7];
assign tmp_103_fu_2877_p2 = x_assign_1_fu_2871_p2 << 8'd1;
assign tmp_104_fu_2883_p3 = x_assign_1_fu_2871_p2[32'd7];
assign tmp_105_fu_2911_p2 = x_assign_2_fu_2905_p2 << 8'd1;
assign tmp_106_fu_2917_p3 = x_assign_2_fu_2905_p2[32'd7];
assign tmp_107_fu_2945_p2 = x_assign_3_fu_2939_p2 << 8'd1;
assign tmp_108_fu_2951_p3 = x_assign_3_fu_2939_p2[32'd7];
assign tmp_109_fu_2991_p2 = x_assign_0_1_fu_2973_p2 << 8'd1;
assign tmp_10_10_fu_2695_p2 = (p_Result_11_fu_2541_p4 ^ p_Result_1_10_fu_2551_p4);
assign tmp_10_11_fu_2701_p2 = (p_Result_12_fu_2561_p4 ^ p_Result_1_11_fu_2571_p4);
assign tmp_10_12_fu_2707_p2 = (p_Result_13_fu_2581_p4 ^ p_Result_1_12_fu_2591_p4);
assign tmp_10_13_fu_2713_p2 = (p_Result_14_fu_2601_p4 ^ p_Result_1_13_fu_2611_p4);
assign tmp_10_14_fu_2719_p2 = (tmp_99_fu_2621_p1 ^ tmp_100_fu_2625_p1);
assign tmp_10_1_fu_2635_p2 = (p_Result_s_39_fu_2341_p4 ^ p_Result_1_1_fu_2351_p4);
assign tmp_10_2_fu_2641_p2 = (p_Result_2_fu_2361_p4 ^ p_Result_1_2_fu_2371_p4);
assign tmp_10_3_fu_2647_p2 = (p_Result_3_fu_2381_p4 ^ p_Result_1_3_fu_2391_p4);
assign tmp_10_4_fu_2653_p2 = (p_Result_4_fu_2401_p4 ^ p_Result_1_4_fu_2411_p4);
assign tmp_10_5_fu_2659_p2 = (p_Result_5_fu_2421_p4 ^ p_Result_1_5_fu_2431_p4);
assign tmp_10_6_fu_2665_p2 = (p_Result_6_fu_2441_p4 ^ p_Result_1_6_fu_2451_p4);
assign tmp_10_7_fu_2671_p2 = (p_Result_7_fu_2461_p4 ^ p_Result_1_7_fu_2471_p4);
assign tmp_10_8_fu_2677_p2 = (p_Result_8_fu_2481_p4 ^ p_Result_1_8_fu_2491_p4);
assign tmp_10_9_fu_2683_p2 = (p_Result_9_fu_2501_p4 ^ p_Result_1_9_fu_2511_p4);
assign tmp_10_fu_2629_p2 = (p_Result_s_fu_2321_p4 ^ p_Result_1_fu_2331_p4);
assign tmp_10_s_fu_2689_p2 = (p_Result_10_fu_2521_p4 ^ p_Result_1_s_fu_2531_p4);
assign tmp_110_fu_2997_p3 = x_assign_0_1_fu_2973_p2[32'd7];
assign tmp_111_fu_3025_p2 = x_assign_1_0_1_fu_3019_p2 << 8'd1;
assign tmp_112_fu_3031_p3 = x_assign_1_0_1_fu_3019_p2[32'd7];
assign tmp_113_fu_3059_p2 = x_assign_2_0_1_fu_3053_p2 << 8'd1;
assign tmp_114_fu_3065_p3 = x_assign_2_0_1_fu_3053_p2[32'd7];
assign tmp_115_fu_3093_p2 = x_assign_3_0_1_fu_3087_p2 << 8'd1;
assign tmp_116_fu_3099_p3 = x_assign_3_0_1_fu_3087_p2[32'd7];
assign tmp_117_fu_3139_p2 = x_assign_0_2_fu_3121_p2 << 8'd1;
assign tmp_118_fu_3145_p3 = x_assign_0_2_fu_3121_p2[32'd7];
assign tmp_119_fu_3173_p2 = x_assign_1_0_2_fu_3167_p2 << 8'd1;
assign tmp_11_fu_12214_p2 = (sboxes_q197 ^ ap_reg_pp0_iter9_tmp_70_7_reg_13715);
assign tmp_120_fu_3179_p3 = x_assign_1_0_2_fu_3167_p2[32'd7];
assign tmp_121_fu_3207_p2 = x_assign_2_0_2_fu_3201_p2 << 8'd1;
assign tmp_122_fu_3213_p3 = x_assign_2_0_2_fu_3201_p2[32'd7];
assign tmp_123_fu_3241_p2 = x_assign_3_0_2_fu_3235_p2 << 8'd1;
assign tmp_124_fu_3247_p3 = x_assign_3_0_2_fu_3235_p2[32'd7];
assign tmp_125_fu_3287_p2 = x_assign_0_3_fu_3269_p2 << 8'd1;
assign tmp_126_fu_3293_p3 = x_assign_0_3_fu_3269_p2[32'd7];
assign tmp_127_fu_3321_p2 = x_assign_1_0_3_fu_3315_p2 << 8'd1;
assign tmp_128_fu_3327_p3 = x_assign_1_0_3_fu_3315_p2[32'd7];
assign tmp_129_fu_3355_p2 = x_assign_2_0_3_fu_3349_p2 << 8'd1;
assign tmp_12_fu_12219_p2 = (sboxes_q198 ^ ap_reg_pp0_iter9_tmp_71_7_reg_13721);
assign tmp_130_fu_3361_p3 = x_assign_2_0_3_fu_3349_p2[32'd7];
assign tmp_131_fu_3389_p2 = x_assign_3_0_3_fu_3383_p2 << 8'd1;
assign tmp_132_fu_3395_p3 = x_assign_3_0_3_fu_3383_p2[32'd7];
assign tmp_133_fu_3885_p2 = x_assign_s_fu_3867_p2 << 8'd1;
assign tmp_134_fu_3891_p3 = x_assign_s_fu_3867_p2[32'd7];
assign tmp_135_fu_3919_p2 = x_assign_1_1_fu_3913_p2 << 8'd1;
assign tmp_136_fu_3925_p3 = x_assign_1_1_fu_3913_p2[32'd7];
assign tmp_137_fu_3953_p2 = x_assign_2_1_fu_3947_p2 << 8'd1;
assign tmp_138_fu_3959_p3 = x_assign_2_1_fu_3947_p2[32'd7];
assign tmp_139_fu_3987_p2 = x_assign_3_1_fu_3981_p2 << 8'd1;
assign tmp_13_fu_12224_p2 = (sboxes_q199 ^ ap_reg_pp0_iter9_tmp_72_7_reg_13727);
assign tmp_140_fu_3993_p3 = x_assign_3_1_fu_3981_p2[32'd7];
assign tmp_141_fu_4033_p2 = x_assign_171_1_fu_4015_p2 << 8'd1;
assign tmp_142_fu_4039_p3 = x_assign_171_1_fu_4015_p2[32'd7];
assign tmp_143_fu_4067_p2 = x_assign_1_1_1_fu_4061_p2 << 8'd1;
assign tmp_144_fu_4073_p3 = x_assign_1_1_1_fu_4061_p2[32'd7];
assign tmp_145_fu_4101_p2 = x_assign_2_1_1_fu_4095_p2 << 8'd1;
assign tmp_146_fu_4107_p3 = x_assign_2_1_1_fu_4095_p2[32'd7];
assign tmp_147_fu_4135_p2 = x_assign_3_1_1_fu_4129_p2 << 8'd1;
assign tmp_148_fu_4141_p3 = x_assign_3_1_1_fu_4129_p2[32'd7];
assign tmp_149_fu_4181_p2 = x_assign_171_2_fu_4163_p2 << 8'd1;
assign tmp_150_fu_4187_p3 = x_assign_171_2_fu_4163_p2[32'd7];
assign tmp_151_fu_4215_p2 = x_assign_1_1_2_fu_4209_p2 << 8'd1;
assign tmp_152_fu_4221_p3 = x_assign_1_1_2_fu_4209_p2[32'd7];
assign tmp_153_fu_4249_p2 = x_assign_2_1_2_fu_4243_p2 << 8'd1;
assign tmp_154_fu_4255_p3 = x_assign_2_1_2_fu_4243_p2[32'd7];
assign tmp_155_fu_4283_p2 = x_assign_3_1_2_fu_4277_p2 << 8'd1;
assign tmp_156_fu_4289_p3 = x_assign_3_1_2_fu_4277_p2[32'd7];
assign tmp_157_fu_4329_p2 = x_assign_171_3_fu_4311_p2 << 8'd1;
assign tmp_158_fu_4335_p3 = x_assign_171_3_fu_4311_p2[32'd7];
assign tmp_159_fu_4363_p2 = x_assign_1_1_3_fu_4357_p2 << 8'd1;
assign tmp_160_fu_4369_p3 = x_assign_1_1_3_fu_4357_p2[32'd7];
assign tmp_161_fu_4397_p2 = x_assign_2_1_3_fu_4391_p2 << 8'd1;
assign tmp_162_fu_4403_p3 = x_assign_2_1_3_fu_4391_p2[32'd7];
assign tmp_163_fu_4431_p2 = x_assign_3_1_3_fu_4425_p2 << 8'd1;
assign tmp_164_fu_4437_p3 = x_assign_3_1_3_fu_4425_p2[32'd7];
assign tmp_165_fu_4927_p2 = x_assign_9_fu_4909_p2 << 8'd1;
assign tmp_166_fu_4933_p3 = x_assign_9_fu_4909_p2[32'd7];
assign tmp_167_fu_4961_p2 = x_assign_1_2_fu_4955_p2 << 8'd1;
assign tmp_168_fu_4967_p3 = x_assign_1_2_fu_4955_p2[32'd7];
assign tmp_169_fu_4995_p2 = x_assign_2_2_fu_4989_p2 << 8'd1;
assign tmp_170_fu_5001_p3 = x_assign_2_2_fu_4989_p2[32'd7];
assign tmp_171_fu_5029_p2 = x_assign_3_2_fu_5023_p2 << 8'd1;
assign tmp_172_fu_5035_p3 = x_assign_3_2_fu_5023_p2[32'd7];
assign tmp_173_fu_5075_p2 = x_assign_273_1_fu_5057_p2 << 8'd1;
assign tmp_174_fu_5081_p3 = x_assign_273_1_fu_5057_p2[32'd7];
assign tmp_175_fu_5109_p2 = x_assign_1_2_1_fu_5103_p2 << 8'd1;
assign tmp_176_fu_5115_p3 = x_assign_1_2_1_fu_5103_p2[32'd7];
assign tmp_177_fu_5143_p2 = x_assign_2_2_1_fu_5137_p2 << 8'd1;
assign tmp_178_fu_5149_p3 = x_assign_2_2_1_fu_5137_p2[32'd7];
assign tmp_179_fu_5177_p2 = x_assign_3_2_1_fu_5171_p2 << 8'd1;
assign tmp_180_fu_5183_p3 = x_assign_3_2_1_fu_5171_p2[32'd7];
assign tmp_181_fu_5223_p2 = x_assign_273_2_fu_5205_p2 << 8'd1;
assign tmp_182_fu_5229_p3 = x_assign_273_2_fu_5205_p2[32'd7];
assign tmp_183_fu_5257_p2 = x_assign_1_2_2_fu_5251_p2 << 8'd1;
assign tmp_184_fu_5263_p3 = x_assign_1_2_2_fu_5251_p2[32'd7];
assign tmp_185_fu_5291_p2 = x_assign_2_2_2_fu_5285_p2 << 8'd1;
assign tmp_186_fu_5297_p3 = x_assign_2_2_2_fu_5285_p2[32'd7];
assign tmp_187_fu_5325_p2 = x_assign_3_2_2_fu_5319_p2 << 8'd1;
assign tmp_188_fu_5331_p3 = x_assign_3_2_2_fu_5319_p2[32'd7];
assign tmp_189_fu_5371_p2 = x_assign_273_3_fu_5353_p2 << 8'd1;
assign tmp_190_fu_5377_p3 = x_assign_273_3_fu_5353_p2[32'd7];
assign tmp_191_fu_5405_p2 = x_assign_1_2_3_fu_5399_p2 << 8'd1;
assign tmp_192_fu_5411_p3 = x_assign_1_2_3_fu_5399_p2[32'd7];
assign tmp_193_fu_5439_p2 = x_assign_2_2_3_fu_5433_p2 << 8'd1;
assign tmp_194_fu_5445_p3 = x_assign_2_2_3_fu_5433_p2[32'd7];
assign tmp_195_fu_5473_p2 = x_assign_3_2_3_fu_5467_p2 << 8'd1;
assign tmp_196_fu_5479_p3 = x_assign_3_2_3_fu_5467_p2[32'd7];
assign tmp_197_fu_5969_p2 = x_assign_10_fu_5951_p2 << 8'd1;
assign tmp_198_fu_5975_p3 = x_assign_10_fu_5951_p2[32'd7];
assign tmp_199_fu_6003_p2 = x_assign_1_3_fu_5997_p2 << 8'd1;
assign tmp_1_fu_12188_p1 = tmp_79_8_fu_11809_p2;
assign tmp_200_fu_6009_p3 = x_assign_1_3_fu_5997_p2[32'd7];
assign tmp_201_fu_6037_p2 = x_assign_2_3_fu_6031_p2 << 8'd1;
assign tmp_202_fu_6043_p3 = x_assign_2_3_fu_6031_p2[32'd7];
assign tmp_203_fu_6071_p2 = x_assign_3_3_fu_6065_p2 << 8'd1;
assign tmp_204_fu_6077_p3 = x_assign_3_3_fu_6065_p2[32'd7];
assign tmp_205_fu_6117_p2 = x_assign_375_1_fu_6099_p2 << 8'd1;
assign tmp_206_fu_6123_p3 = x_assign_375_1_fu_6099_p2[32'd7];
assign tmp_207_fu_6151_p2 = x_assign_1_3_1_fu_6145_p2 << 8'd1;
assign tmp_208_fu_6157_p3 = x_assign_1_3_1_fu_6145_p2[32'd7];
assign tmp_209_fu_6185_p2 = x_assign_2_3_1_fu_6179_p2 << 8'd1;
assign tmp_210_fu_6191_p3 = x_assign_2_3_1_fu_6179_p2[32'd7];
assign tmp_211_fu_6219_p2 = x_assign_3_3_1_fu_6213_p2 << 8'd1;
assign tmp_212_fu_6225_p3 = x_assign_3_3_1_fu_6213_p2[32'd7];
assign tmp_213_fu_6265_p2 = x_assign_375_2_fu_6247_p2 << 8'd1;
assign tmp_214_fu_6271_p3 = x_assign_375_2_fu_6247_p2[32'd7];
assign tmp_215_fu_6299_p2 = x_assign_1_3_2_fu_6293_p2 << 8'd1;
assign tmp_216_fu_6305_p3 = x_assign_1_3_2_fu_6293_p2[32'd7];
assign tmp_217_fu_6333_p2 = x_assign_2_3_2_fu_6327_p2 << 8'd1;
assign tmp_218_fu_6339_p3 = x_assign_2_3_2_fu_6327_p2[32'd7];
assign tmp_219_fu_6367_p2 = x_assign_3_3_2_fu_6361_p2 << 8'd1;
assign tmp_220_fu_6373_p3 = x_assign_3_3_2_fu_6361_p2[32'd7];
assign tmp_221_fu_6413_p2 = x_assign_375_3_fu_6395_p2 << 8'd1;
assign tmp_222_fu_6419_p3 = x_assign_375_3_fu_6395_p2[32'd7];
assign tmp_223_fu_6447_p2 = x_assign_1_3_3_fu_6441_p2 << 8'd1;
assign tmp_224_fu_6453_p3 = x_assign_1_3_3_fu_6441_p2[32'd7];
assign tmp_225_fu_6481_p2 = x_assign_2_3_3_fu_6475_p2 << 8'd1;
assign tmp_226_fu_6487_p3 = x_assign_2_3_3_fu_6475_p2[32'd7];
assign tmp_227_fu_6515_p2 = x_assign_3_3_3_fu_6509_p2 << 8'd1;
assign tmp_228_fu_6521_p3 = x_assign_3_3_3_fu_6509_p2[32'd7];
assign tmp_229_fu_7011_p2 = x_assign_4_fu_6993_p2 << 8'd1;
assign tmp_230_fu_7017_p3 = x_assign_4_fu_6993_p2[32'd7];
assign tmp_231_fu_7045_p2 = x_assign_1_4_fu_7039_p2 << 8'd1;
assign tmp_232_fu_7051_p3 = x_assign_1_4_fu_7039_p2[32'd7];
assign tmp_233_fu_7079_p2 = x_assign_2_4_fu_7073_p2 << 8'd1;
assign tmp_234_fu_7085_p3 = x_assign_2_4_fu_7073_p2[32'd7];
assign tmp_235_fu_7113_p2 = x_assign_3_4_fu_7107_p2 << 8'd1;
assign tmp_236_fu_7119_p3 = x_assign_3_4_fu_7107_p2[32'd7];
assign tmp_237_fu_7159_p2 = x_assign_4_1_fu_7141_p2 << 8'd1;
assign tmp_238_fu_7165_p3 = x_assign_4_1_fu_7141_p2[32'd7];
assign tmp_239_fu_7193_p2 = x_assign_1_4_1_fu_7187_p2 << 8'd1;
assign tmp_240_fu_7199_p3 = x_assign_1_4_1_fu_7187_p2[32'd7];
assign tmp_241_fu_7227_p2 = x_assign_2_4_1_fu_7221_p2 << 8'd1;
assign tmp_242_fu_7233_p3 = x_assign_2_4_1_fu_7221_p2[32'd7];
assign tmp_243_fu_7261_p2 = x_assign_3_4_1_fu_7255_p2 << 8'd1;
assign tmp_244_fu_7267_p3 = x_assign_3_4_1_fu_7255_p2[32'd7];
assign tmp_245_fu_7307_p2 = x_assign_4_2_fu_7289_p2 << 8'd1;
assign tmp_246_fu_7313_p3 = x_assign_4_2_fu_7289_p2[32'd7];
assign tmp_247_fu_7341_p2 = x_assign_1_4_2_fu_7335_p2 << 8'd1;
assign tmp_248_fu_7347_p3 = x_assign_1_4_2_fu_7335_p2[32'd7];
assign tmp_249_fu_7375_p2 = x_assign_2_4_2_fu_7369_p2 << 8'd1;
assign tmp_250_fu_7381_p3 = x_assign_2_4_2_fu_7369_p2[32'd7];
assign tmp_251_fu_7409_p2 = x_assign_3_4_2_fu_7403_p2 << 8'd1;
assign tmp_252_fu_7415_p3 = x_assign_3_4_2_fu_7403_p2[32'd7];
assign tmp_253_fu_7455_p2 = x_assign_4_3_fu_7437_p2 << 8'd1;
assign tmp_254_fu_7461_p3 = x_assign_4_3_fu_7437_p2[32'd7];
assign tmp_255_fu_7489_p2 = x_assign_1_4_3_fu_7483_p2 << 8'd1;
assign tmp_256_fu_7495_p3 = x_assign_1_4_3_fu_7483_p2[32'd7];
assign tmp_257_fu_7523_p2 = x_assign_2_4_3_fu_7517_p2 << 8'd1;
assign tmp_258_fu_7529_p3 = x_assign_2_4_3_fu_7517_p2[32'd7];
assign tmp_259_fu_7557_p2 = x_assign_3_4_3_fu_7551_p2 << 8'd1;
assign tmp_260_fu_7563_p3 = x_assign_3_4_3_fu_7551_p2[32'd7];
assign tmp_261_fu_8053_p2 = x_assign_5_fu_8035_p2 << 8'd1;
assign tmp_262_fu_8059_p3 = x_assign_5_fu_8035_p2[32'd7];
assign tmp_263_fu_8087_p2 = x_assign_1_5_fu_8081_p2 << 8'd1;
assign tmp_264_fu_8093_p3 = x_assign_1_5_fu_8081_p2[32'd7];
assign tmp_265_fu_8121_p2 = x_assign_2_5_fu_8115_p2 << 8'd1;
assign tmp_266_fu_8127_p3 = x_assign_2_5_fu_8115_p2[32'd7];
assign tmp_267_fu_8155_p2 = x_assign_3_5_fu_8149_p2 << 8'd1;
assign tmp_268_fu_8161_p3 = x_assign_3_5_fu_8149_p2[32'd7];
assign tmp_269_fu_8201_p2 = x_assign_5_1_fu_8183_p2 << 8'd1;
assign tmp_270_fu_8207_p3 = x_assign_5_1_fu_8183_p2[32'd7];
assign tmp_271_fu_8235_p2 = x_assign_1_5_1_fu_8229_p2 << 8'd1;
assign tmp_272_fu_8241_p3 = x_assign_1_5_1_fu_8229_p2[32'd7];
assign tmp_273_fu_8269_p2 = x_assign_2_5_1_fu_8263_p2 << 8'd1;
assign tmp_274_fu_8275_p3 = x_assign_2_5_1_fu_8263_p2[32'd7];
assign tmp_275_fu_8303_p2 = x_assign_3_5_1_fu_8297_p2 << 8'd1;
assign tmp_276_fu_8309_p3 = x_assign_3_5_1_fu_8297_p2[32'd7];
assign tmp_277_fu_8349_p2 = x_assign_5_2_fu_8331_p2 << 8'd1;
assign tmp_278_fu_8355_p3 = x_assign_5_2_fu_8331_p2[32'd7];
assign tmp_279_fu_8383_p2 = x_assign_1_5_2_fu_8377_p2 << 8'd1;
assign tmp_280_fu_8389_p3 = x_assign_1_5_2_fu_8377_p2[32'd7];
assign tmp_281_fu_8417_p2 = x_assign_2_5_2_fu_8411_p2 << 8'd1;
assign tmp_282_fu_8423_p3 = x_assign_2_5_2_fu_8411_p2[32'd7];
assign tmp_283_fu_8451_p2 = x_assign_3_5_2_fu_8445_p2 << 8'd1;
assign tmp_284_fu_8457_p3 = x_assign_3_5_2_fu_8445_p2[32'd7];
assign tmp_285_fu_8497_p2 = x_assign_5_3_fu_8479_p2 << 8'd1;
assign tmp_286_fu_8503_p3 = x_assign_5_3_fu_8479_p2[32'd7];
assign tmp_287_fu_8531_p2 = x_assign_1_5_3_fu_8525_p2 << 8'd1;
assign tmp_288_fu_8537_p3 = x_assign_1_5_3_fu_8525_p2[32'd7];
assign tmp_289_fu_8565_p2 = x_assign_2_5_3_fu_8559_p2 << 8'd1;
assign tmp_290_fu_8571_p3 = x_assign_2_5_3_fu_8559_p2[32'd7];
assign tmp_291_fu_8599_p2 = x_assign_3_5_3_fu_8593_p2 << 8'd1;
assign tmp_292_fu_8605_p3 = x_assign_3_5_3_fu_8593_p2[32'd7];
assign tmp_293_fu_9095_p2 = x_assign_6_fu_9077_p2 << 8'd1;
assign tmp_294_fu_9101_p3 = x_assign_6_fu_9077_p2[32'd7];
assign tmp_295_fu_9129_p2 = x_assign_1_6_fu_9123_p2 << 8'd1;
assign tmp_296_fu_9135_p3 = x_assign_1_6_fu_9123_p2[32'd7];
assign tmp_297_fu_9163_p2 = x_assign_2_6_fu_9157_p2 << 8'd1;
assign tmp_298_fu_9169_p3 = x_assign_2_6_fu_9157_p2[32'd7];
assign tmp_299_fu_9197_p2 = x_assign_3_6_fu_9191_p2 << 8'd1;
assign tmp_2_fu_12193_p1 = tmp_80_8_fu_11814_p2;
assign tmp_300_fu_9203_p3 = x_assign_3_6_fu_9191_p2[32'd7];
assign tmp_301_fu_9243_p2 = x_assign_6_1_fu_9225_p2 << 8'd1;
assign tmp_302_fu_9249_p3 = x_assign_6_1_fu_9225_p2[32'd7];
assign tmp_303_fu_9277_p2 = x_assign_1_6_1_fu_9271_p2 << 8'd1;
assign tmp_304_fu_9283_p3 = x_assign_1_6_1_fu_9271_p2[32'd7];
assign tmp_305_fu_9311_p2 = x_assign_2_6_1_fu_9305_p2 << 8'd1;
assign tmp_306_fu_9317_p3 = x_assign_2_6_1_fu_9305_p2[32'd7];
assign tmp_307_fu_9345_p2 = x_assign_3_6_1_fu_9339_p2 << 8'd1;
assign tmp_308_fu_9351_p3 = x_assign_3_6_1_fu_9339_p2[32'd7];
assign tmp_309_fu_9391_p2 = x_assign_6_2_fu_9373_p2 << 8'd1;
assign tmp_310_fu_9397_p3 = x_assign_6_2_fu_9373_p2[32'd7];
assign tmp_311_fu_9425_p2 = x_assign_1_6_2_fu_9419_p2 << 8'd1;
assign tmp_312_fu_9431_p3 = x_assign_1_6_2_fu_9419_p2[32'd7];
assign tmp_313_fu_9459_p2 = x_assign_2_6_2_fu_9453_p2 << 8'd1;
assign tmp_314_fu_9465_p3 = x_assign_2_6_2_fu_9453_p2[32'd7];
assign tmp_315_fu_9493_p2 = x_assign_3_6_2_fu_9487_p2 << 8'd1;
assign tmp_316_fu_9499_p3 = x_assign_3_6_2_fu_9487_p2[32'd7];
assign tmp_317_fu_9539_p2 = x_assign_6_3_fu_9521_p2 << 8'd1;
assign tmp_318_fu_9545_p3 = x_assign_6_3_fu_9521_p2[32'd7];
assign tmp_319_fu_9573_p2 = x_assign_1_6_3_fu_9567_p2 << 8'd1;
assign tmp_320_fu_9579_p3 = x_assign_1_6_3_fu_9567_p2[32'd7];
assign tmp_321_fu_9607_p2 = x_assign_2_6_3_fu_9601_p2 << 8'd1;
assign tmp_322_fu_9613_p3 = x_assign_2_6_3_fu_9601_p2[32'd7];
assign tmp_323_fu_9641_p2 = x_assign_3_6_3_fu_9635_p2 << 8'd1;
assign tmp_324_fu_9647_p3 = x_assign_3_6_3_fu_9635_p2[32'd7];
assign tmp_325_fu_10137_p2 = x_assign_7_fu_10119_p2 << 8'd1;
assign tmp_326_fu_10143_p3 = x_assign_7_fu_10119_p2[32'd7];
assign tmp_327_fu_10171_p2 = x_assign_1_7_fu_10165_p2 << 8'd1;
assign tmp_328_fu_10177_p3 = x_assign_1_7_fu_10165_p2[32'd7];
assign tmp_329_fu_10205_p2 = x_assign_2_7_fu_10199_p2 << 8'd1;
assign tmp_330_fu_10211_p3 = x_assign_2_7_fu_10199_p2[32'd7];
assign tmp_331_fu_10239_p2 = x_assign_3_7_fu_10233_p2 << 8'd1;
assign tmp_332_fu_10245_p3 = x_assign_3_7_fu_10233_p2[32'd7];
assign tmp_333_fu_10285_p2 = x_assign_7_1_fu_10267_p2 << 8'd1;
assign tmp_334_fu_10291_p3 = x_assign_7_1_fu_10267_p2[32'd7];
assign tmp_335_fu_10319_p2 = x_assign_1_7_1_fu_10313_p2 << 8'd1;
assign tmp_336_fu_10325_p3 = x_assign_1_7_1_fu_10313_p2[32'd7];
assign tmp_337_fu_10353_p2 = x_assign_2_7_1_fu_10347_p2 << 8'd1;
assign tmp_338_fu_10359_p3 = x_assign_2_7_1_fu_10347_p2[32'd7];
assign tmp_339_fu_10387_p2 = x_assign_3_7_1_fu_10381_p2 << 8'd1;
assign tmp_33_10_fu_12158_p1 = tmp_85_8_10_fu_12031_p2;
assign tmp_33_11_fu_12163_p1 = tmp_85_8_11_fu_12049_p2;
assign tmp_33_12_fu_12168_p1 = tmp_85_8_12_fu_12067_p2;
assign tmp_33_13_fu_12173_p1 = tmp_85_8_13_fu_12085_p2;
assign tmp_33_14_fu_12178_p1 = tmp_85_8_14_fu_12097_p2;
assign tmp_33_1_fu_12108_p1 = tmp_85_8_1_fu_11849_p2;
assign tmp_33_2_fu_12113_p1 = tmp_85_8_2_fu_11867_p2;
assign tmp_33_3_fu_12118_p1 = tmp_85_8_3_fu_11879_p2;
assign tmp_33_4_fu_12123_p1 = tmp_85_8_4_fu_11902_p2;
assign tmp_33_5_fu_12128_p1 = tmp_85_8_5_fu_11925_p2;
assign tmp_33_6_fu_12133_p1 = tmp_85_8_6_fu_11948_p2;
assign tmp_33_7_fu_12138_p1 = tmp_85_8_7_fu_11965_p2;
assign tmp_33_8_fu_12143_p1 = tmp_85_8_8_fu_11983_p2;
assign tmp_33_9_fu_12148_p1 = tmp_85_8_9_fu_12001_p2;
assign tmp_33_fu_12103_p1 = tmp_85_8_fu_11831_p2;
assign tmp_33_s_fu_12153_p1 = tmp_85_8_s_fu_12019_p2;
assign tmp_340_fu_10393_p3 = x_assign_3_7_1_fu_10381_p2[32'd7];
assign tmp_341_fu_10433_p2 = x_assign_7_2_fu_10415_p2 << 8'd1;
assign tmp_342_fu_10439_p3 = x_assign_7_2_fu_10415_p2[32'd7];
assign tmp_343_fu_10467_p2 = x_assign_1_7_2_fu_10461_p2 << 8'd1;
assign tmp_344_fu_10473_p3 = x_assign_1_7_2_fu_10461_p2[32'd7];
assign tmp_345_fu_10501_p2 = x_assign_2_7_2_fu_10495_p2 << 8'd1;
assign tmp_346_fu_10507_p3 = x_assign_2_7_2_fu_10495_p2[32'd7];
assign tmp_347_fu_10535_p2 = x_assign_3_7_2_fu_10529_p2 << 8'd1;
assign tmp_348_fu_10541_p3 = x_assign_3_7_2_fu_10529_p2[32'd7];
assign tmp_349_fu_10581_p2 = x_assign_7_3_fu_10563_p2 << 8'd1;
assign tmp_350_fu_10587_p3 = x_assign_7_3_fu_10563_p2[32'd7];
assign tmp_351_fu_10615_p2 = x_assign_1_7_3_fu_10609_p2 << 8'd1;
assign tmp_352_fu_10621_p3 = x_assign_1_7_3_fu_10609_p2[32'd7];
assign tmp_353_fu_10649_p2 = x_assign_2_7_3_fu_10643_p2 << 8'd1;
assign tmp_354_fu_10655_p3 = x_assign_2_7_3_fu_10643_p2[32'd7];
assign tmp_355_fu_10683_p2 = x_assign_3_7_3_fu_10677_p2 << 8'd1;
assign tmp_356_fu_10689_p3 = x_assign_3_7_3_fu_10677_p2[32'd7];
assign tmp_357_fu_11179_p2 = x_assign_8_fu_11161_p2 << 8'd1;
assign tmp_358_fu_11185_p3 = x_assign_8_fu_11161_p2[32'd7];
assign tmp_359_fu_11213_p2 = x_assign_1_8_fu_11207_p2 << 8'd1;
assign tmp_35_0_10_fu_2780_p1 = tmp_10_10_fu_2695_p2;
assign tmp_35_0_11_fu_2785_p1 = tmp_10_11_fu_2701_p2;
assign tmp_35_0_12_fu_2790_p1 = tmp_10_12_fu_2707_p2;
assign tmp_35_0_13_fu_2795_p1 = tmp_10_13_fu_2713_p2;
assign tmp_35_0_14_fu_2800_p1 = tmp_10_14_fu_2719_p2;
assign tmp_35_0_1_fu_2730_p1 = tmp_10_1_fu_2635_p2;
assign tmp_35_0_2_fu_2735_p1 = tmp_10_2_fu_2641_p2;
assign tmp_35_0_3_fu_2740_p1 = tmp_10_3_fu_2647_p2;
assign tmp_35_0_4_fu_2745_p1 = tmp_10_4_fu_2653_p2;
assign tmp_35_0_5_fu_2750_p1 = tmp_10_5_fu_2659_p2;
assign tmp_35_0_6_fu_2755_p1 = tmp_10_6_fu_2665_p2;
assign tmp_35_0_7_fu_2760_p1 = tmp_10_7_fu_2671_p2;
assign tmp_35_0_8_fu_2765_p1 = tmp_10_8_fu_2677_p2;
assign tmp_35_0_9_fu_2770_p1 = tmp_10_9_fu_2683_p2;
assign tmp_35_0_s_fu_2775_p1 = tmp_10_s_fu_2689_p2;
assign tmp_35_1_10_fu_3822_p1 = tmp_85_0_10_fu_3695_p2;
assign tmp_35_1_11_fu_3827_p1 = tmp_85_0_11_fu_3713_p2;
assign tmp_35_1_12_fu_3832_p1 = tmp_85_0_12_fu_3731_p2;
assign tmp_35_1_13_fu_3837_p1 = tmp_85_0_13_fu_3749_p2;
assign tmp_35_1_14_fu_3842_p1 = tmp_85_0_14_fu_3761_p2;
assign tmp_35_1_1_fu_3772_p1 = tmp_85_0_1_fu_3533_p2;
assign tmp_35_1_2_fu_3777_p1 = tmp_85_0_2_fu_3551_p2;
assign tmp_35_1_3_fu_3782_p1 = tmp_85_0_3_fu_3563_p2;
assign tmp_35_1_4_fu_3787_p1 = tmp_85_0_4_fu_3581_p2;
assign tmp_35_1_5_fu_3792_p1 = tmp_85_0_5_fu_3599_p2;
assign tmp_35_1_6_fu_3797_p1 = tmp_85_0_6_fu_3617_p2;
assign tmp_35_1_7_fu_3802_p1 = tmp_85_0_7_fu_3629_p2;
assign tmp_35_1_8_fu_3807_p1 = tmp_85_0_8_fu_3647_p2;
assign tmp_35_1_9_fu_3812_p1 = tmp_85_0_9_fu_3665_p2;
assign tmp_35_1_fu_3767_p1 = tmp_85_fu_3515_p2;
assign tmp_35_1_s_fu_3817_p1 = tmp_85_0_s_fu_3683_p2;
assign tmp_35_2_10_fu_4864_p1 = tmp_85_1_10_fu_4737_p2;
assign tmp_35_2_11_fu_4869_p1 = tmp_85_1_11_fu_4755_p2;
assign tmp_35_2_12_fu_4874_p1 = tmp_85_1_12_fu_4773_p2;
assign tmp_35_2_13_fu_4879_p1 = tmp_85_1_13_fu_4791_p2;
assign tmp_35_2_14_fu_4884_p1 = tmp_85_1_14_fu_4803_p2;
assign tmp_35_2_1_fu_4814_p1 = tmp_85_1_1_fu_4555_p2;
assign tmp_35_2_2_fu_4819_p1 = tmp_85_1_2_fu_4573_p2;
assign tmp_35_2_3_fu_4824_p1 = tmp_85_1_3_fu_4585_p2;
assign tmp_35_2_4_fu_4829_p1 = tmp_85_1_4_fu_4603_p2;
assign tmp_35_2_5_fu_4834_p1 = tmp_85_1_5_fu_4621_p2;
assign tmp_35_2_6_fu_4839_p1 = tmp_85_1_6_fu_4639_p2;
assign tmp_35_2_7_fu_4844_p1 = tmp_85_1_7_fu_4651_p2;
assign tmp_35_2_8_fu_4849_p1 = tmp_85_1_8_fu_4674_p2;
assign tmp_35_2_9_fu_4854_p1 = tmp_85_1_9_fu_4697_p2;
assign tmp_35_2_fu_4809_p1 = tmp_85_1_fu_4537_p2;
assign tmp_35_2_s_fu_4859_p1 = tmp_85_1_s_fu_4720_p2;
assign tmp_35_3_10_fu_5906_p1 = tmp_85_2_10_fu_5779_p2;
assign tmp_35_3_11_fu_5911_p1 = tmp_85_2_11_fu_5797_p2;
assign tmp_35_3_12_fu_5916_p1 = tmp_85_2_12_fu_5815_p2;
assign tmp_35_3_13_fu_5921_p1 = tmp_85_2_13_fu_5833_p2;
assign tmp_35_3_14_fu_5926_p1 = tmp_85_2_14_fu_5845_p2;
assign tmp_35_3_1_fu_5856_p1 = tmp_85_2_1_fu_5597_p2;
assign tmp_35_3_2_fu_5861_p1 = tmp_85_2_2_fu_5615_p2;
assign tmp_35_3_3_fu_5866_p1 = tmp_85_2_3_fu_5627_p2;
assign tmp_35_3_4_fu_5871_p1 = tmp_85_2_4_fu_5650_p2;
assign tmp_35_3_5_fu_5876_p1 = tmp_85_2_5_fu_5673_p2;
assign tmp_35_3_6_fu_5881_p1 = tmp_85_2_6_fu_5696_p2;
assign tmp_35_3_7_fu_5886_p1 = tmp_85_2_7_fu_5713_p2;
assign tmp_35_3_8_fu_5891_p1 = tmp_85_2_8_fu_5731_p2;
assign tmp_35_3_9_fu_5896_p1 = tmp_85_2_9_fu_5749_p2;
assign tmp_35_3_fu_5851_p1 = tmp_85_2_fu_5579_p2;
assign tmp_35_3_s_fu_5901_p1 = tmp_85_2_s_fu_5767_p2;
assign tmp_35_4_10_fu_6948_p1 = tmp_85_3_10_fu_6821_p2;
assign tmp_35_4_11_fu_6953_p1 = tmp_85_3_11_fu_6839_p2;
assign tmp_35_4_12_fu_6958_p1 = tmp_85_3_12_fu_6857_p2;
assign tmp_35_4_13_fu_6963_p1 = tmp_85_3_13_fu_6875_p2;
assign tmp_35_4_14_fu_6968_p1 = tmp_85_3_14_fu_6887_p2;
assign tmp_35_4_1_fu_6898_p1 = tmp_85_3_1_fu_6639_p2;
assign tmp_35_4_2_fu_6903_p1 = tmp_85_3_2_fu_6657_p2;
assign tmp_35_4_3_fu_6908_p1 = tmp_85_3_3_fu_6669_p2;
assign tmp_35_4_4_fu_6913_p1 = tmp_85_3_4_fu_6687_p2;
assign tmp_35_4_5_fu_6918_p1 = tmp_85_3_5_fu_6705_p2;
assign tmp_35_4_6_fu_6923_p1 = tmp_85_3_6_fu_6723_p2;
assign tmp_35_4_7_fu_6928_p1 = tmp_85_3_7_fu_6735_p2;
assign tmp_35_4_8_fu_6933_p1 = tmp_85_3_8_fu_6758_p2;
assign tmp_35_4_9_fu_6938_p1 = tmp_85_3_9_fu_6781_p2;
assign tmp_35_4_fu_6893_p1 = tmp_85_3_fu_6621_p2;
assign tmp_35_4_s_fu_6943_p1 = tmp_85_3_s_fu_6804_p2;
assign tmp_35_5_10_fu_7990_p1 = tmp_85_4_10_fu_7863_p2;
assign tmp_35_5_11_fu_7995_p1 = tmp_85_4_11_fu_7881_p2;
assign tmp_35_5_12_fu_8000_p1 = tmp_85_4_12_fu_7899_p2;
assign tmp_35_5_13_fu_8005_p1 = tmp_85_4_13_fu_7917_p2;
assign tmp_35_5_14_fu_8010_p1 = tmp_85_4_14_fu_7929_p2;
assign tmp_35_5_1_fu_7940_p1 = tmp_85_4_1_fu_7681_p2;
assign tmp_35_5_2_fu_7945_p1 = tmp_85_4_2_fu_7699_p2;
assign tmp_35_5_3_fu_7950_p1 = tmp_85_4_3_fu_7711_p2;
assign tmp_35_5_4_fu_7955_p1 = tmp_85_4_4_fu_7734_p2;
assign tmp_35_5_5_fu_7960_p1 = tmp_85_4_5_fu_7757_p2;
assign tmp_35_5_6_fu_7965_p1 = tmp_85_4_6_fu_7780_p2;
assign tmp_35_5_7_fu_7970_p1 = tmp_85_4_7_fu_7797_p2;
assign tmp_35_5_8_fu_7975_p1 = tmp_85_4_8_fu_7815_p2;
assign tmp_35_5_9_fu_7980_p1 = tmp_85_4_9_fu_7833_p2;
assign tmp_35_5_fu_7935_p1 = tmp_85_4_fu_7663_p2;
assign tmp_35_5_s_fu_7985_p1 = tmp_85_4_s_fu_7851_p2;
assign tmp_35_6_10_fu_9032_p1 = tmp_85_5_10_fu_8905_p2;
assign tmp_35_6_11_fu_9037_p1 = tmp_85_5_11_fu_8923_p2;
assign tmp_35_6_12_fu_9042_p1 = tmp_85_5_12_fu_8941_p2;
assign tmp_35_6_13_fu_9047_p1 = tmp_85_5_13_fu_8959_p2;
assign tmp_35_6_14_fu_9052_p1 = tmp_85_5_14_fu_8971_p2;
assign tmp_35_6_1_fu_8982_p1 = tmp_85_5_1_fu_8723_p2;
assign tmp_35_6_2_fu_8987_p1 = tmp_85_5_2_fu_8741_p2;
assign tmp_35_6_3_fu_8992_p1 = tmp_85_5_3_fu_8753_p2;
assign tmp_35_6_4_fu_8997_p1 = tmp_85_5_4_fu_8771_p2;
assign tmp_35_6_5_fu_9002_p1 = tmp_85_5_5_fu_8789_p2;
assign tmp_35_6_6_fu_9007_p1 = tmp_85_5_6_fu_8807_p2;
assign tmp_35_6_7_fu_9012_p1 = tmp_85_5_7_fu_8819_p2;
assign tmp_35_6_8_fu_9017_p1 = tmp_85_5_8_fu_8842_p2;
assign tmp_35_6_9_fu_9022_p1 = tmp_85_5_9_fu_8865_p2;
assign tmp_35_6_fu_8977_p1 = tmp_85_5_fu_8705_p2;
assign tmp_35_6_s_fu_9027_p1 = tmp_85_5_s_fu_8888_p2;
assign tmp_35_7_10_fu_10074_p1 = tmp_85_6_10_fu_9947_p2;
assign tmp_35_7_11_fu_10079_p1 = tmp_85_6_11_fu_9965_p2;
assign tmp_35_7_12_fu_10084_p1 = tmp_85_6_12_fu_9983_p2;
assign tmp_35_7_13_fu_10089_p1 = tmp_85_6_13_fu_10001_p2;
assign tmp_35_7_14_fu_10094_p1 = tmp_85_6_14_fu_10013_p2;
assign tmp_35_7_1_fu_10024_p1 = tmp_85_6_1_fu_9765_p2;
assign tmp_35_7_2_fu_10029_p1 = tmp_85_6_2_fu_9783_p2;
assign tmp_35_7_3_fu_10034_p1 = tmp_85_6_3_fu_9795_p2;
assign tmp_35_7_4_fu_10039_p1 = tmp_85_6_4_fu_9818_p2;
assign tmp_35_7_5_fu_10044_p1 = tmp_85_6_5_fu_9841_p2;
assign tmp_35_7_6_fu_10049_p1 = tmp_85_6_6_fu_9864_p2;
assign tmp_35_7_7_fu_10054_p1 = tmp_85_6_7_fu_9881_p2;
assign tmp_35_7_8_fu_10059_p1 = tmp_85_6_8_fu_9899_p2;
assign tmp_35_7_9_fu_10064_p1 = tmp_85_6_9_fu_9917_p2;
assign tmp_35_7_fu_10019_p1 = tmp_85_6_fu_9747_p2;
assign tmp_35_7_s_fu_10069_p1 = tmp_85_6_s_fu_9935_p2;
assign tmp_35_8_10_fu_11116_p1 = tmp_85_7_10_fu_10989_p2;
assign tmp_35_8_11_fu_11121_p1 = tmp_85_7_11_fu_11007_p2;
assign tmp_35_8_12_fu_11126_p1 = tmp_85_7_12_fu_11025_p2;
assign tmp_35_8_13_fu_11131_p1 = tmp_85_7_13_fu_11043_p2;
assign tmp_35_8_14_fu_11136_p1 = tmp_85_7_14_fu_11055_p2;
assign tmp_35_8_1_fu_11066_p1 = tmp_85_7_1_fu_10807_p2;
assign tmp_35_8_2_fu_11071_p1 = tmp_85_7_2_fu_10825_p2;
assign tmp_35_8_3_fu_11076_p1 = tmp_85_7_3_fu_10837_p2;
assign tmp_35_8_4_fu_11081_p1 = tmp_85_7_4_fu_10855_p2;
assign tmp_35_8_5_fu_11086_p1 = tmp_85_7_5_fu_10873_p2;
assign tmp_35_8_6_fu_11091_p1 = tmp_85_7_6_fu_10891_p2;
assign tmp_35_8_7_fu_11096_p1 = tmp_85_7_7_fu_10903_p2;
assign tmp_35_8_8_fu_11101_p1 = tmp_85_7_8_fu_10926_p2;
assign tmp_35_8_9_fu_11106_p1 = tmp_85_7_9_fu_10949_p2;
assign tmp_35_8_fu_11061_p1 = tmp_85_7_fu_10789_p2;
assign tmp_35_8_s_fu_11111_p1 = tmp_85_7_s_fu_10972_p2;
assign tmp_35_fu_2725_p1 = tmp_10_fu_2629_p2;
assign tmp_360_fu_11219_p3 = x_assign_1_8_fu_11207_p2[32'd7];
assign tmp_361_fu_11247_p2 = x_assign_2_8_fu_11241_p2 << 8'd1;
assign tmp_362_fu_11253_p3 = x_assign_2_8_fu_11241_p2[32'd7];
assign tmp_363_fu_11281_p2 = x_assign_3_8_fu_11275_p2 << 8'd1;
assign tmp_364_fu_11287_p3 = x_assign_3_8_fu_11275_p2[32'd7];
assign tmp_365_fu_11327_p2 = x_assign_8_1_fu_11309_p2 << 8'd1;
assign tmp_366_fu_11333_p3 = x_assign_8_1_fu_11309_p2[32'd7];
assign tmp_367_fu_11361_p2 = x_assign_1_8_1_fu_11355_p2 << 8'd1;
assign tmp_368_fu_11367_p3 = x_assign_1_8_1_fu_11355_p2[32'd7];
assign tmp_369_fu_11395_p2 = x_assign_2_8_1_fu_11389_p2 << 8'd1;
assign tmp_370_fu_11401_p3 = x_assign_2_8_1_fu_11389_p2[32'd7];
assign tmp_371_fu_11429_p2 = x_assign_3_8_1_fu_11423_p2 << 8'd1;
assign tmp_372_fu_11435_p3 = x_assign_3_8_1_fu_11423_p2[32'd7];
assign tmp_373_fu_11475_p2 = x_assign_8_2_fu_11457_p2 << 8'd1;
assign tmp_374_fu_11481_p3 = x_assign_8_2_fu_11457_p2[32'd7];
assign tmp_375_fu_11509_p2 = x_assign_1_8_2_fu_11503_p2 << 8'd1;
assign tmp_376_fu_11515_p3 = x_assign_1_8_2_fu_11503_p2[32'd7];
assign tmp_377_fu_11543_p2 = x_assign_2_8_2_fu_11537_p2 << 8'd1;
assign tmp_378_fu_11549_p3 = x_assign_2_8_2_fu_11537_p2[32'd7];
assign tmp_379_fu_11577_p2 = x_assign_3_8_2_fu_11571_p2 << 8'd1;
assign tmp_380_fu_11583_p3 = x_assign_3_8_2_fu_11571_p2[32'd7];
assign tmp_381_fu_11623_p2 = x_assign_8_3_fu_11605_p2 << 8'd1;
assign tmp_382_fu_11629_p3 = x_assign_8_3_fu_11605_p2[32'd7];
assign tmp_383_fu_11657_p2 = x_assign_1_8_3_fu_11651_p2 << 8'd1;
assign tmp_384_fu_11663_p3 = x_assign_1_8_3_fu_11651_p2[32'd7];
assign tmp_385_fu_11691_p2 = x_assign_2_8_3_fu_11685_p2 << 8'd1;
assign tmp_386_fu_11697_p3 = x_assign_2_8_3_fu_11685_p2[32'd7];
assign tmp_387_fu_11725_p2 = x_assign_3_8_3_fu_11719_p2 << 8'd1;
assign tmp_388_fu_11731_p3 = x_assign_3_8_3_fu_11719_p2[32'd7];
assign tmp_38_10_fu_12335_p2 = (tmp296_fu_12330_p2 ^ sboxes_q187);
assign tmp_38_11_fu_12346_p2 = (tmp297_fu_12341_p2 ^ sboxes_q192);
assign tmp_38_12_fu_12357_p2 = (tmp298_fu_12352_p2 ^ sboxes_q181);
assign tmp_38_13_fu_12368_p2 = (tmp299_fu_12363_p2 ^ sboxes_q186);
assign tmp_38_14_fu_12379_p2 = (tmp300_fu_12374_p2 ^ sboxes_q191);
assign tmp_38_1_fu_12245_p2 = (tmp290_fu_12240_p2 ^ sboxes_q197);
assign tmp_38_2_fu_12256_p2 = (tmp291_fu_12251_p2 ^ sboxes_q198);
assign tmp_38_3_fu_12267_p2 = (tmp292_fu_12262_p2 ^ sboxes_q199);
assign tmp_38_4_fu_12273_p2 = (sboxes_q184 ^ tmp_9_fu_12209_p2);
assign tmp_38_5_fu_12279_p2 = (sboxes_q189 ^ tmp_11_fu_12214_p2);
assign tmp_38_6_fu_12285_p2 = (sboxes_q194 ^ tmp_12_fu_12219_p2);
assign tmp_38_7_fu_12291_p2 = (sboxes_q183 ^ tmp_13_fu_12224_p2);
assign tmp_38_8_fu_12302_p2 = (tmp293_fu_12297_p2 ^ sboxes_q188);
assign tmp_38_9_fu_12313_p2 = (tmp294_fu_12308_p2 ^ sboxes_q193);
assign tmp_38_fu_12234_p2 = (tmp289_fu_12229_p2 ^ sboxes_q180);
assign tmp_38_s_fu_12324_p2 = (tmp295_fu_12319_p2 ^ sboxes_q182);
assign tmp_3_fu_12198_p1 = tmp_77_8_fu_11799_p2;
assign tmp_47_0_1_fu_2979_p2 = (sboxes_q14 ^ x_assign_0_1_fu_2973_p2);
assign tmp_47_0_2_fu_3127_p2 = (sboxes_q2 ^ x_assign_0_2_fu_3121_p2);
assign tmp_47_0_3_fu_3275_p2 = (sboxes_q6 ^ x_assign_0_3_fu_3269_p2);
assign tmp_47_1_1_fu_4021_p2 = (sboxes_q34 ^ x_assign_171_1_fu_4015_p2);
assign tmp_47_1_2_fu_4169_p2 = (sboxes_q22 ^ x_assign_171_2_fu_4163_p2);
assign tmp_47_1_3_fu_4317_p2 = (sboxes_q26 ^ x_assign_171_3_fu_4311_p2);
assign tmp_47_1_fu_3873_p2 = (sboxes_q30 ^ x_assign_s_fu_3867_p2);
assign tmp_47_2_1_fu_5063_p2 = (sboxes_q54 ^ x_assign_273_1_fu_5057_p2);
assign tmp_47_2_2_fu_5211_p2 = (sboxes_q42 ^ x_assign_273_2_fu_5205_p2);
assign tmp_47_2_3_fu_5359_p2 = (sboxes_q46 ^ x_assign_273_3_fu_5353_p2);
assign tmp_47_2_fu_4915_p2 = (sboxes_q50 ^ x_assign_9_fu_4909_p2);
assign tmp_47_3_1_fu_6105_p2 = (sboxes_q74 ^ x_assign_375_1_fu_6099_p2);
assign tmp_47_3_2_fu_6253_p2 = (sboxes_q62 ^ x_assign_375_2_fu_6247_p2);
assign tmp_47_3_3_fu_6401_p2 = (sboxes_q66 ^ x_assign_375_3_fu_6395_p2);
assign tmp_47_3_fu_5957_p2 = (sboxes_q70 ^ x_assign_10_fu_5951_p2);
assign tmp_47_4_1_fu_7147_p2 = (sboxes_q94 ^ x_assign_4_1_fu_7141_p2);
assign tmp_47_4_2_fu_7295_p2 = (sboxes_q82 ^ x_assign_4_2_fu_7289_p2);
assign tmp_47_4_3_fu_7443_p2 = (sboxes_q86 ^ x_assign_4_3_fu_7437_p2);
assign tmp_47_4_fu_6999_p2 = (sboxes_q90 ^ x_assign_4_fu_6993_p2);
assign tmp_47_5_1_fu_8189_p2 = (sboxes_q114 ^ x_assign_5_1_fu_8183_p2);
assign tmp_47_5_2_fu_8337_p2 = (sboxes_q102 ^ x_assign_5_2_fu_8331_p2);
assign tmp_47_5_3_fu_8485_p2 = (sboxes_q106 ^ x_assign_5_3_fu_8479_p2);
assign tmp_47_5_fu_8041_p2 = (sboxes_q110 ^ x_assign_5_fu_8035_p2);
assign tmp_47_6_1_fu_9231_p2 = (sboxes_q134 ^ x_assign_6_1_fu_9225_p2);
assign tmp_47_6_2_fu_9379_p2 = (sboxes_q122 ^ x_assign_6_2_fu_9373_p2);
assign tmp_47_6_3_fu_9527_p2 = (sboxes_q126 ^ x_assign_6_3_fu_9521_p2);
assign tmp_47_6_fu_9083_p2 = (sboxes_q130 ^ x_assign_6_fu_9077_p2);
assign tmp_47_7_1_fu_10273_p2 = (sboxes_q154 ^ x_assign_7_1_fu_10267_p2);
assign tmp_47_7_2_fu_10421_p2 = (sboxes_q142 ^ x_assign_7_2_fu_10415_p2);
assign tmp_47_7_3_fu_10569_p2 = (sboxes_q146 ^ x_assign_7_3_fu_10563_p2);
assign tmp_47_7_fu_10125_p2 = (sboxes_q150 ^ x_assign_7_fu_10119_p2);
assign tmp_47_8_1_fu_11315_p2 = (sboxes_q174 ^ x_assign_8_1_fu_11309_p2);
assign tmp_47_8_2_fu_11463_p2 = (sboxes_q162 ^ x_assign_8_2_fu_11457_p2);
assign tmp_47_8_3_fu_11611_p2 = (sboxes_q166 ^ x_assign_8_3_fu_11605_p2);
assign tmp_47_8_fu_11167_p2 = (sboxes_q170 ^ x_assign_8_fu_11161_p2);
assign tmp_47_fu_2831_p2 = (sboxes_q10 ^ x_assign_fu_2825_p2);
assign tmp_4_fu_12203_p2 = (sboxes_q196 ^ 8'd54);
assign tmp_60_1_fu_3847_p1 = tmp_78_fu_3488_p2;
assign tmp_60_2_fu_4889_p1 = tmp_78_1_fu_4510_p2;
assign tmp_60_3_fu_5931_p1 = tmp_78_2_fu_5552_p2;
assign tmp_60_4_fu_6973_p1 = tmp_78_3_fu_6594_p2;
assign tmp_60_5_fu_8015_p1 = tmp_78_4_fu_7636_p2;
assign tmp_60_6_fu_9057_p1 = tmp_78_5_fu_8678_p2;
assign tmp_60_7_fu_10099_p1 = tmp_78_6_fu_9720_p2;
assign tmp_60_8_fu_11141_p1 = tmp_78_7_fu_10762_p2;
assign tmp_60_fu_2805_p1 = p_Result_1_12_fu_2591_p4;
assign tmp_61_1_fu_3852_p1 = tmp_79_fu_3493_p2;
assign tmp_61_2_fu_4894_p1 = tmp_79_1_fu_4515_p2;
assign tmp_61_3_fu_5936_p1 = tmp_79_2_fu_5557_p2;
assign tmp_61_4_fu_6978_p1 = tmp_79_3_fu_6599_p2;
assign tmp_61_5_fu_8020_p1 = tmp_79_4_fu_7641_p2;
assign tmp_61_6_fu_9062_p1 = tmp_79_5_fu_8683_p2;
assign tmp_61_7_fu_10104_p1 = tmp_79_6_fu_9725_p2;
assign tmp_61_8_fu_11146_p1 = tmp_79_7_fu_10767_p2;
assign tmp_61_fu_2810_p1 = p_Result_1_13_fu_2611_p4;
assign tmp_62_1_fu_3857_p1 = tmp_80_fu_3498_p2;
assign tmp_62_2_fu_4899_p1 = tmp_80_1_fu_4520_p2;
assign tmp_62_3_fu_5941_p1 = tmp_80_2_fu_5562_p2;
assign tmp_62_4_fu_6983_p1 = tmp_80_3_fu_6604_p2;
assign tmp_62_5_fu_8025_p1 = tmp_80_4_fu_7646_p2;
assign tmp_62_6_fu_9067_p1 = tmp_80_5_fu_8688_p2;
assign tmp_62_7_fu_10109_p1 = tmp_80_6_fu_9730_p2;
assign tmp_62_8_fu_11151_p1 = tmp_80_7_fu_10772_p2;
assign tmp_62_fu_2815_p1 = tmp_100_fu_2625_p1;
assign tmp_63_1_fu_3862_p1 = tmp_77_fu_3483_p2;
assign tmp_63_2_fu_4904_p1 = tmp_77_1_fu_4505_p2;
assign tmp_63_3_fu_5946_p1 = tmp_77_2_fu_5547_p2;
assign tmp_63_4_fu_6988_p1 = tmp_77_3_fu_6589_p2;
assign tmp_63_5_fu_8030_p1 = tmp_77_4_fu_7631_p2;
assign tmp_63_6_fu_9072_p1 = tmp_77_5_fu_8673_p2;
assign tmp_63_7_fu_10114_p1 = tmp_77_6_fu_9715_p2;
assign tmp_63_8_fu_11156_p1 = tmp_77_7_fu_10757_p2;
assign tmp_63_fu_2820_p1 = p_Result_1_11_fu_2571_p4;
assign tmp_64_1_fu_4459_p2 = (sboxes_q36 ^ 8'd2);
assign tmp_64_3_fu_6543_p2 = (sboxes_q76 ^ 8'd8);
assign tmp_64_5_fu_8627_p2 = (sboxes_q116 ^ 8'd32);
assign tmp_64_7_fu_10711_p2 = (sboxes_q156 ^ 8'd128);
assign tmp_65_1_fu_4465_p2 = (tmp_64_1_fu_4459_p2 ^ tmp_65_reg_12613);
assign tmp_65_2_fu_5506_p2 = (tmp61_fu_5501_p2 ^ sboxes_q56);
assign tmp_65_3_fu_6549_p2 = (tmp_64_3_fu_6543_p2 ^ tmp_65_2_reg_12921);
assign tmp_65_4_fu_7590_p2 = (tmp126_fu_7585_p2 ^ sboxes_q96);
assign tmp_65_5_fu_8633_p2 = (tmp_64_5_fu_8627_p2 ^ tmp_65_4_reg_13237);
assign tmp_65_6_fu_9674_p2 = (tmp191_fu_9669_p2 ^ sboxes_q136);
assign tmp_65_7_fu_10717_p2 = (tmp_64_7_fu_10711_p2 ^ tmp_65_6_reg_13545);
assign tmp_65_8_fu_11758_p2 = (tmp256_fu_11753_p2 ^ sboxes_q176);
assign tmp_65_fu_3422_p2 = (tmp_fu_3417_p2 ^ sboxes_q16);
assign tmp_66_1_fu_4470_p2 = (sboxes_q37 ^ tmp_66_reg_12618);
assign tmp_66_2_fu_5512_p2 = (sboxes_q57 ^ tmp_66_1_reg_12762);
assign tmp_66_3_fu_6554_p2 = (sboxes_q77 ^ tmp_66_2_reg_12926);
assign tmp_66_4_fu_7596_p2 = (sboxes_q97 ^ tmp_66_3_reg_13070);
assign tmp_66_5_fu_8638_p2 = (sboxes_q117 ^ tmp_66_4_reg_13242);
assign tmp_66_6_fu_9680_p2 = (sboxes_q137 ^ tmp_66_5_reg_13386);
assign tmp_66_7_fu_10722_p2 = (sboxes_q157 ^ tmp_66_6_reg_13550);
assign tmp_66_8_fu_11764_p2 = (sboxes_q177 ^ tmp_66_7_reg_13694);
assign tmp_66_fu_3428_p2 = (sboxes_q17 ^ p_Result_1_1_reg_12426);
assign tmp_67_1_fu_4475_p2 = (sboxes_q38 ^ tmp_67_reg_12623);
assign tmp_67_2_fu_5517_p2 = (sboxes_q58 ^ tmp_67_1_reg_12767);
assign tmp_67_3_fu_6559_p2 = (sboxes_q78 ^ tmp_67_2_reg_12931);
assign tmp_67_4_fu_7601_p2 = (sboxes_q98 ^ tmp_67_3_reg_13075);
assign tmp_67_5_fu_8643_p2 = (sboxes_q118 ^ tmp_67_4_reg_13247);
assign tmp_67_6_fu_9685_p2 = (sboxes_q138 ^ tmp_67_5_reg_13391);
assign tmp_67_7_fu_10727_p2 = (sboxes_q158 ^ tmp_67_6_reg_13555);
assign tmp_67_8_fu_11769_p2 = (sboxes_q178 ^ tmp_67_7_reg_13699);
assign tmp_67_fu_3433_p2 = (sboxes_q18 ^ p_Result_1_2_reg_12431);
assign tmp_68_1_fu_4480_p2 = (sboxes_q39 ^ tmp_68_reg_12628);
assign tmp_68_2_fu_5522_p2 = (sboxes_q59 ^ tmp_68_1_reg_12772);
assign tmp_68_3_fu_6564_p2 = (sboxes_q79 ^ tmp_68_2_reg_12936);
assign tmp_68_4_fu_7606_p2 = (sboxes_q99 ^ tmp_68_3_reg_13080);
assign tmp_68_5_fu_8648_p2 = (sboxes_q119 ^ tmp_68_4_reg_13252);
assign tmp_68_6_fu_9690_p2 = (sboxes_q139 ^ tmp_68_5_reg_13396);
assign tmp_68_7_fu_10732_p2 = (sboxes_q159 ^ tmp_68_6_reg_13560);
assign tmp_68_8_fu_11774_p2 = (sboxes_q179 ^ tmp_68_7_reg_13704);
assign tmp_68_fu_3438_p2 = (sboxes_q19 ^ p_Result_1_3_reg_12436);
assign tmp_69_1_fu_4485_p2 = (ap_reg_pp0_iter1_p_Result_1_4_reg_12441 ^ tmp_64_1_fu_4459_p2);
assign tmp_69_3_fu_6569_p2 = (ap_reg_pp0_iter3_tmp_69_1_reg_12777 ^ tmp_64_3_fu_6543_p2);
assign tmp_69_5_fu_8653_p2 = (ap_reg_pp0_iter5_tmp_69_3_reg_13085 ^ tmp_64_5_fu_8627_p2);
assign tmp_69_7_fu_10737_p2 = (ap_reg_pp0_iter7_tmp_69_5_reg_13401 ^ tmp_64_7_fu_10711_p2);
assign tmp_69_fu_3443_p2 = (p_Result_1_4_reg_12441 ^ tmp_65_fu_3422_p2);
assign tmp_70_1_fu_4490_p2 = (sboxes_q37 ^ ap_reg_pp0_iter1_p_Result_1_5_reg_12447);
assign tmp_70_3_fu_6574_p2 = (sboxes_q77 ^ ap_reg_pp0_iter3_tmp_70_1_reg_12783);
assign tmp_70_5_fu_8658_p2 = (sboxes_q117 ^ ap_reg_pp0_iter5_tmp_70_3_reg_13091);
assign tmp_70_7_fu_10742_p2 = (sboxes_q157 ^ ap_reg_pp0_iter7_tmp_70_5_reg_13407);
assign tmp_70_fu_3448_p2 = (p_Result_1_5_reg_12447 ^ tmp_66_fu_3428_p2);
assign tmp_71_1_fu_4495_p2 = (sboxes_q38 ^ ap_reg_pp0_iter1_p_Result_1_6_reg_12453);
assign tmp_71_3_fu_6579_p2 = (sboxes_q78 ^ ap_reg_pp0_iter3_tmp_71_1_reg_12789);
assign tmp_71_5_fu_8663_p2 = (sboxes_q118 ^ ap_reg_pp0_iter5_tmp_71_3_reg_13097);
assign tmp_71_7_fu_10747_p2 = (sboxes_q158 ^ ap_reg_pp0_iter7_tmp_71_5_reg_13413);
assign tmp_71_fu_3453_p2 = (p_Result_1_6_reg_12453 ^ tmp_67_fu_3433_p2);
assign tmp_72_1_fu_4500_p2 = (sboxes_q39 ^ ap_reg_pp0_iter1_p_Result_1_7_reg_12459);
assign tmp_72_3_fu_6584_p2 = (sboxes_q79 ^ ap_reg_pp0_iter3_tmp_72_1_reg_12795);
assign tmp_72_5_fu_8668_p2 = (sboxes_q119 ^ ap_reg_pp0_iter5_tmp_72_3_reg_13103);
assign tmp_72_7_fu_10752_p2 = (sboxes_q159 ^ ap_reg_pp0_iter7_tmp_72_5_reg_13419);
assign tmp_72_fu_3458_p2 = (p_Result_1_7_reg_12459 ^ tmp_68_fu_3438_p2);
assign tmp_73_2_fu_5527_p2 = (ap_reg_pp0_iter2_tmp_73_reg_12633 ^ tmp_65_2_fu_5506_p2);
assign tmp_73_4_fu_7611_p2 = (ap_reg_pp0_iter4_tmp_73_2_reg_12941 ^ tmp_65_4_fu_7590_p2);
assign tmp_73_6_fu_9695_p2 = (ap_reg_pp0_iter6_tmp_73_4_reg_13257 ^ tmp_65_6_fu_9674_p2);
assign tmp_73_8_fu_11779_p2 = (ap_reg_pp0_iter8_tmp_73_6_reg_13565 ^ tmp_65_8_fu_11758_p2);
assign tmp_73_fu_3463_p2 = (p_Result_1_8_reg_12465 ^ tmp_69_fu_3443_p2);
assign tmp_74_2_fu_5532_p2 = (ap_reg_pp0_iter2_tmp_74_reg_12639 ^ tmp_66_2_fu_5512_p2);
assign tmp_74_4_fu_7616_p2 = (ap_reg_pp0_iter4_tmp_74_2_reg_12947 ^ tmp_66_4_fu_7596_p2);
assign tmp_74_6_fu_9700_p2 = (ap_reg_pp0_iter6_tmp_74_4_reg_13263 ^ tmp_66_6_fu_9680_p2);
assign tmp_74_8_fu_11784_p2 = (ap_reg_pp0_iter8_tmp_74_6_reg_13571 ^ tmp_66_8_fu_11764_p2);
assign tmp_74_fu_3468_p2 = (p_Result_1_9_reg_12470 ^ tmp_70_fu_3448_p2);
assign tmp_75_2_fu_5537_p2 = (ap_reg_pp0_iter2_tmp_75_reg_12645 ^ tmp_67_2_fu_5517_p2);
assign tmp_75_4_fu_7621_p2 = (ap_reg_pp0_iter4_tmp_75_2_reg_12953 ^ tmp_67_4_fu_7601_p2);
assign tmp_75_6_fu_9705_p2 = (ap_reg_pp0_iter6_tmp_75_4_reg_13269 ^ tmp_67_6_fu_9685_p2);
assign tmp_75_8_fu_11789_p2 = (ap_reg_pp0_iter8_tmp_75_6_reg_13577 ^ tmp_67_8_fu_11769_p2);
assign tmp_75_fu_3473_p2 = (p_Result_1_s_reg_12475 ^ tmp_71_fu_3453_p2);
assign tmp_76_2_fu_5542_p2 = (ap_reg_pp0_iter2_tmp_76_reg_12651 ^ tmp_68_2_fu_5522_p2);
assign tmp_76_4_fu_7626_p2 = (ap_reg_pp0_iter4_tmp_76_2_reg_12959 ^ tmp_68_4_fu_7606_p2);
assign tmp_76_6_fu_9710_p2 = (ap_reg_pp0_iter6_tmp_76_4_reg_13275 ^ tmp_68_6_fu_9690_p2);
assign tmp_76_8_fu_11794_p2 = (ap_reg_pp0_iter8_tmp_76_6_reg_13583 ^ tmp_68_8_fu_11774_p2);
assign tmp_76_fu_3478_p2 = (p_Result_1_10_reg_12480 ^ tmp_72_fu_3458_p2);
assign tmp_77_1_fu_4505_p2 = (tmp_69_1_fu_4485_p2 ^ ap_reg_pp0_iter1_p_Result_1_11_reg_12485);
assign tmp_77_2_fu_5547_p2 = (tmp_73_2_fu_5527_p2 ^ tmp_77_1_reg_12801);
assign tmp_77_3_fu_6589_p2 = (tmp_64_3_fu_6543_p2 ^ ap_reg_pp0_iter3_p_Result_1_11_reg_12485);
assign tmp_77_4_fu_7631_p2 = (tmp_73_4_fu_7611_p2 ^ tmp_77_3_reg_13109);
assign tmp_77_5_fu_8673_p2 = (tmp_69_5_fu_8653_p2 ^ ap_reg_pp0_iter5_tmp_77_3_reg_13109);
assign tmp_77_6_fu_9715_p2 = (tmp_73_6_fu_9695_p2 ^ tmp_77_5_reg_13425);
assign tmp_77_7_fu_10757_p2 = (tmp_64_7_fu_10711_p2 ^ ap_reg_pp0_iter7_tmp_77_3_reg_13109);
assign tmp_77_8_fu_11799_p2 = (tmp_73_8_fu_11779_p2 ^ tmp_77_7_reg_13733);
assign tmp_77_fu_3483_p2 = (tmp_73_fu_3463_p2 ^ p_Result_1_11_reg_12485);
assign tmp_78_1_fu_4510_p2 = (tmp_70_1_fu_4490_p2 ^ ap_reg_pp0_iter1_p_Result_1_12_reg_12492);
assign tmp_78_2_fu_5552_p2 = (tmp_74_2_fu_5532_p2 ^ tmp_78_1_reg_12806);
assign tmp_78_3_fu_6594_p2 = (sboxes_q77 ^ ap_reg_pp0_iter3_p_Result_1_12_reg_12492);
assign tmp_78_4_fu_7636_p2 = (tmp_74_4_fu_7616_p2 ^ tmp_78_3_reg_13116);
assign tmp_78_5_fu_8678_p2 = (tmp_70_5_fu_8658_p2 ^ ap_reg_pp0_iter5_tmp_78_3_reg_13116);
assign tmp_78_6_fu_9720_p2 = (tmp_74_6_fu_9700_p2 ^ tmp_78_5_reg_13430);
assign tmp_78_7_fu_10762_p2 = (sboxes_q157 ^ ap_reg_pp0_iter7_tmp_78_3_reg_13116);
assign tmp_78_8_fu_11804_p2 = (tmp_74_8_fu_11784_p2 ^ tmp_78_7_reg_13739);
assign tmp_78_fu_3488_p2 = (tmp_74_fu_3468_p2 ^ p_Result_1_12_reg_12492);
assign tmp_79_1_fu_4515_p2 = (tmp_71_1_fu_4495_p2 ^ ap_reg_pp0_iter1_p_Result_1_13_reg_12499);
assign tmp_79_2_fu_5557_p2 = (tmp_75_2_fu_5537_p2 ^ tmp_79_1_reg_12811);
assign tmp_79_3_fu_6599_p2 = (sboxes_q78 ^ ap_reg_pp0_iter3_p_Result_1_13_reg_12499);
assign tmp_79_4_fu_7641_p2 = (tmp_75_4_fu_7621_p2 ^ tmp_79_3_reg_13123);
assign tmp_79_5_fu_8683_p2 = (tmp_71_5_fu_8663_p2 ^ ap_reg_pp0_iter5_tmp_79_3_reg_13123);
assign tmp_79_6_fu_9725_p2 = (tmp_75_6_fu_9705_p2 ^ tmp_79_5_reg_13435);
assign tmp_79_7_fu_10767_p2 = (sboxes_q158 ^ ap_reg_pp0_iter7_tmp_79_3_reg_13123);
assign tmp_79_8_fu_11809_p2 = (tmp_75_8_fu_11789_p2 ^ tmp_79_7_reg_13745);
assign tmp_79_fu_3493_p2 = (tmp_75_fu_3473_p2 ^ p_Result_1_13_reg_12499);
assign tmp_80_1_fu_4520_p2 = (tmp_72_1_fu_4500_p2 ^ ap_reg_pp0_iter1_tmp_100_reg_12506);
assign tmp_80_2_fu_5562_p2 = (tmp_76_2_fu_5542_p2 ^ tmp_80_1_reg_12816);
assign tmp_80_3_fu_6604_p2 = (sboxes_q79 ^ ap_reg_pp0_iter3_tmp_100_reg_12506);
assign tmp_80_4_fu_7646_p2 = (tmp_76_4_fu_7626_p2 ^ tmp_80_3_reg_13130);
assign tmp_80_5_fu_8688_p2 = (tmp_72_5_fu_8668_p2 ^ ap_reg_pp0_iter5_tmp_80_3_reg_13130);
assign tmp_80_6_fu_9730_p2 = (tmp_76_6_fu_9710_p2 ^ tmp_80_5_reg_13440);
assign tmp_80_7_fu_10772_p2 = (sboxes_q159 ^ ap_reg_pp0_iter7_tmp_80_3_reg_13130);
assign tmp_80_8_fu_11814_p2 = (tmp_76_8_fu_11794_p2 ^ tmp_80_7_reg_13751);
assign tmp_80_fu_3498_p2 = (tmp_76_fu_3478_p2 ^ tmp_100_reg_12506);
assign tmp_85_0_10_fu_3695_p2 = (tmp21_fu_3689_p2 ^ rv_11_0_2_fu_3261_p3);
assign tmp_85_0_11_fu_3713_p2 = (tmp23_fu_3707_p2 ^ tmp22_fu_3701_p2);
assign tmp_85_0_12_fu_3731_p2 = (tmp25_fu_3725_p2 ^ tmp24_fu_3719_p2);
assign tmp_85_0_13_fu_3749_p2 = (tmp27_fu_3743_p2 ^ tmp26_fu_3737_p2);
assign tmp_85_0_14_fu_3761_p2 = (tmp28_fu_3755_p2 ^ rv_11_0_3_fu_3409_p3);
assign tmp_85_0_1_fu_3533_p2 = (tmp4_fu_3527_p2 ^ tmp3_fu_3521_p2);
assign tmp_85_0_2_fu_3551_p2 = (tmp6_fu_3545_p2 ^ tmp5_fu_3539_p2);
assign tmp_85_0_3_fu_3563_p2 = (tmp7_fu_3557_p2 ^ rv_3_fu_2965_p3);
assign tmp_85_0_4_fu_3581_p2 = (tmp9_fu_3575_p2 ^ tmp8_fu_3569_p2);
assign tmp_85_0_5_fu_3599_p2 = (tmp11_fu_3593_p2 ^ tmp10_fu_3587_p2);
assign tmp_85_0_6_fu_3617_p2 = (tmp13_fu_3611_p2 ^ tmp12_fu_3605_p2);
assign tmp_85_0_7_fu_3629_p2 = (tmp14_fu_3623_p2 ^ rv_11_0_1_fu_3113_p3);
assign tmp_85_0_8_fu_3647_p2 = (tmp16_fu_3641_p2 ^ tmp15_fu_3635_p2);
assign tmp_85_0_9_fu_3665_p2 = (tmp18_fu_3659_p2 ^ tmp17_fu_3653_p2);
assign tmp_85_0_s_fu_3683_p2 = (tmp20_fu_3677_p2 ^ tmp19_fu_3671_p2);
assign tmp_85_1_10_fu_4737_p2 = (tmp53_fu_4732_p2 ^ tmp52_fu_4726_p2);
assign tmp_85_1_11_fu_4755_p2 = (tmp55_fu_4749_p2 ^ tmp54_fu_4743_p2);
assign tmp_85_1_12_fu_4773_p2 = (tmp57_fu_4767_p2 ^ tmp56_fu_4761_p2);
assign tmp_85_1_13_fu_4791_p2 = (tmp59_fu_4785_p2 ^ tmp58_fu_4779_p2);
assign tmp_85_1_14_fu_4803_p2 = (tmp60_fu_4797_p2 ^ rv_11_1_3_fu_4451_p3);
assign tmp_85_1_1_fu_4555_p2 = (tmp32_fu_4549_p2 ^ tmp31_fu_4543_p2);
assign tmp_85_1_2_fu_4573_p2 = (tmp34_fu_4567_p2 ^ tmp33_fu_4561_p2);
assign tmp_85_1_3_fu_4585_p2 = (tmp35_fu_4579_p2 ^ rv_11_1_fu_4007_p3);
assign tmp_85_1_4_fu_4603_p2 = (tmp37_fu_4597_p2 ^ tmp36_fu_4591_p2);
assign tmp_85_1_5_fu_4621_p2 = (tmp39_fu_4615_p2 ^ tmp38_fu_4609_p2);
assign tmp_85_1_6_fu_4639_p2 = (tmp41_fu_4633_p2 ^ tmp40_fu_4627_p2);
assign tmp_85_1_7_fu_4651_p2 = (tmp42_fu_4645_p2 ^ rv_11_1_1_fu_4155_p3);
assign tmp_85_1_8_fu_4674_p2 = (tmp44_fu_4668_p2 ^ tmp43_fu_4657_p2);
assign tmp_85_1_9_fu_4697_p2 = (tmp47_fu_4691_p2 ^ tmp46_fu_4680_p2);
assign tmp_85_1_fu_4537_p2 = (tmp30_fu_4531_p2 ^ tmp29_fu_4525_p2);
assign tmp_85_1_s_fu_4720_p2 = (tmp50_fu_4714_p2 ^ tmp49_fu_4703_p2);
assign tmp_85_2_10_fu_5779_p2 = (tmp86_fu_5773_p2 ^ rv_11_2_2_fu_5345_p3);
assign tmp_85_2_11_fu_5797_p2 = (tmp88_fu_5791_p2 ^ tmp87_fu_5785_p2);
assign tmp_85_2_12_fu_5815_p2 = (tmp90_fu_5809_p2 ^ tmp89_fu_5803_p2);
assign tmp_85_2_13_fu_5833_p2 = (tmp92_fu_5827_p2 ^ tmp91_fu_5821_p2);
assign tmp_85_2_14_fu_5845_p2 = (tmp93_fu_5839_p2 ^ rv_11_2_3_fu_5493_p3);
assign tmp_85_2_1_fu_5597_p2 = (tmp65_fu_5591_p2 ^ tmp64_fu_5585_p2);
assign tmp_85_2_2_fu_5615_p2 = (tmp67_fu_5609_p2 ^ tmp66_fu_5603_p2);
assign tmp_85_2_3_fu_5627_p2 = (tmp68_fu_5621_p2 ^ rv_11_2_fu_5049_p3);
assign tmp_85_2_4_fu_5650_p2 = (tmp70_fu_5644_p2 ^ tmp69_fu_5633_p2);
assign tmp_85_2_5_fu_5673_p2 = (tmp73_fu_5667_p2 ^ tmp72_fu_5656_p2);
assign tmp_85_2_6_fu_5696_p2 = (tmp76_fu_5690_p2 ^ tmp75_fu_5679_p2);
assign tmp_85_2_7_fu_5713_p2 = (tmp79_fu_5708_p2 ^ tmp78_fu_5702_p2);
assign tmp_85_2_8_fu_5731_p2 = (tmp81_fu_5725_p2 ^ tmp80_fu_5719_p2);
assign tmp_85_2_9_fu_5749_p2 = (tmp83_fu_5743_p2 ^ tmp82_fu_5737_p2);
assign tmp_85_2_fu_5579_p2 = (tmp63_fu_5573_p2 ^ tmp62_fu_5567_p2);
assign tmp_85_2_s_fu_5767_p2 = (tmp85_fu_5761_p2 ^ tmp84_fu_5755_p2);
assign tmp_85_3_10_fu_6821_p2 = (tmp118_fu_6816_p2 ^ tmp117_fu_6810_p2);
assign tmp_85_3_11_fu_6839_p2 = (tmp120_fu_6833_p2 ^ tmp119_fu_6827_p2);
assign tmp_85_3_12_fu_6857_p2 = (tmp122_fu_6851_p2 ^ tmp121_fu_6845_p2);
assign tmp_85_3_13_fu_6875_p2 = (tmp124_fu_6869_p2 ^ tmp123_fu_6863_p2);
assign tmp_85_3_14_fu_6887_p2 = (tmp125_fu_6881_p2 ^ rv_11_3_3_fu_6535_p3);
assign tmp_85_3_1_fu_6639_p2 = (tmp97_fu_6633_p2 ^ tmp96_fu_6627_p2);
assign tmp_85_3_2_fu_6657_p2 = (tmp99_fu_6651_p2 ^ tmp98_fu_6645_p2);
assign tmp_85_3_3_fu_6669_p2 = (tmp100_fu_6663_p2 ^ rv_11_3_fu_6091_p3);
assign tmp_85_3_4_fu_6687_p2 = (tmp102_fu_6681_p2 ^ tmp101_fu_6675_p2);
assign tmp_85_3_5_fu_6705_p2 = (tmp104_fu_6699_p2 ^ tmp103_fu_6693_p2);
assign tmp_85_3_6_fu_6723_p2 = (tmp106_fu_6717_p2 ^ tmp105_fu_6711_p2);
assign tmp_85_3_7_fu_6735_p2 = (tmp107_fu_6729_p2 ^ rv_11_3_1_fu_6239_p3);
assign tmp_85_3_8_fu_6758_p2 = (tmp109_fu_6752_p2 ^ tmp108_fu_6741_p2);
assign tmp_85_3_9_fu_6781_p2 = (tmp112_fu_6775_p2 ^ tmp111_fu_6764_p2);
assign tmp_85_3_fu_6621_p2 = (tmp95_fu_6615_p2 ^ tmp94_fu_6609_p2);
assign tmp_85_3_s_fu_6804_p2 = (tmp115_fu_6798_p2 ^ tmp114_fu_6787_p2);
assign tmp_85_4_10_fu_7863_p2 = (tmp151_fu_7857_p2 ^ rv_11_4_2_fu_7429_p3);
assign tmp_85_4_11_fu_7881_p2 = (tmp153_fu_7875_p2 ^ tmp152_fu_7869_p2);
assign tmp_85_4_12_fu_7899_p2 = (tmp155_fu_7893_p2 ^ tmp154_fu_7887_p2);
assign tmp_85_4_13_fu_7917_p2 = (tmp157_fu_7911_p2 ^ tmp156_fu_7905_p2);
assign tmp_85_4_14_fu_7929_p2 = (tmp158_fu_7923_p2 ^ rv_11_4_3_fu_7577_p3);
assign tmp_85_4_1_fu_7681_p2 = (tmp130_fu_7675_p2 ^ tmp129_fu_7669_p2);
assign tmp_85_4_2_fu_7699_p2 = (tmp132_fu_7693_p2 ^ tmp131_fu_7687_p2);
assign tmp_85_4_3_fu_7711_p2 = (tmp133_fu_7705_p2 ^ rv_11_4_fu_7133_p3);
assign tmp_85_4_4_fu_7734_p2 = (tmp135_fu_7728_p2 ^ tmp134_fu_7717_p2);
assign tmp_85_4_5_fu_7757_p2 = (tmp138_fu_7751_p2 ^ tmp137_fu_7740_p2);
assign tmp_85_4_6_fu_7780_p2 = (tmp141_fu_7774_p2 ^ tmp140_fu_7763_p2);
assign tmp_85_4_7_fu_7797_p2 = (tmp144_fu_7792_p2 ^ tmp143_fu_7786_p2);
assign tmp_85_4_8_fu_7815_p2 = (tmp146_fu_7809_p2 ^ tmp145_fu_7803_p2);
assign tmp_85_4_9_fu_7833_p2 = (tmp148_fu_7827_p2 ^ tmp147_fu_7821_p2);
assign tmp_85_4_fu_7663_p2 = (tmp128_fu_7657_p2 ^ tmp127_fu_7651_p2);
assign tmp_85_4_s_fu_7851_p2 = (tmp150_fu_7845_p2 ^ tmp149_fu_7839_p2);
assign tmp_85_5_10_fu_8905_p2 = (tmp183_fu_8900_p2 ^ tmp182_fu_8894_p2);
assign tmp_85_5_11_fu_8923_p2 = (tmp185_fu_8917_p2 ^ tmp184_fu_8911_p2);
assign tmp_85_5_12_fu_8941_p2 = (tmp187_fu_8935_p2 ^ tmp186_fu_8929_p2);
assign tmp_85_5_13_fu_8959_p2 = (tmp189_fu_8953_p2 ^ tmp188_fu_8947_p2);
assign tmp_85_5_14_fu_8971_p2 = (tmp190_fu_8965_p2 ^ rv_11_5_3_fu_8619_p3);
assign tmp_85_5_1_fu_8723_p2 = (tmp162_fu_8717_p2 ^ tmp161_fu_8711_p2);
assign tmp_85_5_2_fu_8741_p2 = (tmp164_fu_8735_p2 ^ tmp163_fu_8729_p2);
assign tmp_85_5_3_fu_8753_p2 = (tmp165_fu_8747_p2 ^ rv_11_5_fu_8175_p3);
assign tmp_85_5_4_fu_8771_p2 = (tmp167_fu_8765_p2 ^ tmp166_fu_8759_p2);
assign tmp_85_5_5_fu_8789_p2 = (tmp169_fu_8783_p2 ^ tmp168_fu_8777_p2);
assign tmp_85_5_6_fu_8807_p2 = (tmp171_fu_8801_p2 ^ tmp170_fu_8795_p2);
assign tmp_85_5_7_fu_8819_p2 = (tmp172_fu_8813_p2 ^ rv_11_5_1_fu_8323_p3);
assign tmp_85_5_8_fu_8842_p2 = (tmp174_fu_8836_p2 ^ tmp173_fu_8825_p2);
assign tmp_85_5_9_fu_8865_p2 = (tmp177_fu_8859_p2 ^ tmp176_fu_8848_p2);
assign tmp_85_5_fu_8705_p2 = (tmp160_fu_8699_p2 ^ tmp159_fu_8693_p2);
assign tmp_85_5_s_fu_8888_p2 = (tmp180_fu_8882_p2 ^ tmp179_fu_8871_p2);
assign tmp_85_6_10_fu_9947_p2 = (tmp216_fu_9941_p2 ^ rv_11_6_2_fu_9513_p3);
assign tmp_85_6_11_fu_9965_p2 = (tmp218_fu_9959_p2 ^ tmp217_fu_9953_p2);
assign tmp_85_6_12_fu_9983_p2 = (tmp220_fu_9977_p2 ^ tmp219_fu_9971_p2);
assign tmp_85_6_13_fu_10001_p2 = (tmp222_fu_9995_p2 ^ tmp221_fu_9989_p2);
assign tmp_85_6_14_fu_10013_p2 = (tmp223_fu_10007_p2 ^ rv_11_6_3_fu_9661_p3);
assign tmp_85_6_1_fu_9765_p2 = (tmp195_fu_9759_p2 ^ tmp194_fu_9753_p2);
assign tmp_85_6_2_fu_9783_p2 = (tmp197_fu_9777_p2 ^ tmp196_fu_9771_p2);
assign tmp_85_6_3_fu_9795_p2 = (tmp198_fu_9789_p2 ^ rv_11_6_fu_9217_p3);
assign tmp_85_6_4_fu_9818_p2 = (tmp200_fu_9812_p2 ^ tmp199_fu_9801_p2);
assign tmp_85_6_5_fu_9841_p2 = (tmp203_fu_9835_p2 ^ tmp202_fu_9824_p2);
assign tmp_85_6_6_fu_9864_p2 = (tmp206_fu_9858_p2 ^ tmp205_fu_9847_p2);
assign tmp_85_6_7_fu_9881_p2 = (tmp209_fu_9876_p2 ^ tmp208_fu_9870_p2);
assign tmp_85_6_8_fu_9899_p2 = (tmp211_fu_9893_p2 ^ tmp210_fu_9887_p2);
assign tmp_85_6_9_fu_9917_p2 = (tmp213_fu_9911_p2 ^ tmp212_fu_9905_p2);
assign tmp_85_6_fu_9747_p2 = (tmp193_fu_9741_p2 ^ tmp192_fu_9735_p2);
assign tmp_85_6_s_fu_9935_p2 = (tmp215_fu_9929_p2 ^ tmp214_fu_9923_p2);
assign tmp_85_7_10_fu_10989_p2 = (tmp248_fu_10984_p2 ^ tmp247_fu_10978_p2);
assign tmp_85_7_11_fu_11007_p2 = (tmp250_fu_11001_p2 ^ tmp249_fu_10995_p2);
assign tmp_85_7_12_fu_11025_p2 = (tmp252_fu_11019_p2 ^ tmp251_fu_11013_p2);
assign tmp_85_7_13_fu_11043_p2 = (tmp254_fu_11037_p2 ^ tmp253_fu_11031_p2);
assign tmp_85_7_14_fu_11055_p2 = (tmp255_fu_11049_p2 ^ rv_11_7_3_fu_10703_p3);
assign tmp_85_7_1_fu_10807_p2 = (tmp227_fu_10801_p2 ^ tmp226_fu_10795_p2);
assign tmp_85_7_2_fu_10825_p2 = (tmp229_fu_10819_p2 ^ tmp228_fu_10813_p2);
assign tmp_85_7_3_fu_10837_p2 = (tmp230_fu_10831_p2 ^ rv_11_7_fu_10259_p3);
assign tmp_85_7_4_fu_10855_p2 = (tmp232_fu_10849_p2 ^ tmp231_fu_10843_p2);
assign tmp_85_7_5_fu_10873_p2 = (tmp234_fu_10867_p2 ^ tmp233_fu_10861_p2);
assign tmp_85_7_6_fu_10891_p2 = (tmp236_fu_10885_p2 ^ tmp235_fu_10879_p2);
assign tmp_85_7_7_fu_10903_p2 = (tmp237_fu_10897_p2 ^ rv_11_7_1_fu_10407_p3);
assign tmp_85_7_8_fu_10926_p2 = (tmp239_fu_10920_p2 ^ tmp238_fu_10909_p2);
assign tmp_85_7_9_fu_10949_p2 = (tmp242_fu_10943_p2 ^ tmp241_fu_10932_p2);
assign tmp_85_7_fu_10789_p2 = (tmp225_fu_10783_p2 ^ tmp224_fu_10777_p2);
assign tmp_85_7_s_fu_10972_p2 = (tmp245_fu_10966_p2 ^ tmp244_fu_10955_p2);
assign tmp_85_8_10_fu_12031_p2 = (tmp281_fu_12025_p2 ^ rv_11_8_2_fu_11597_p3);
assign tmp_85_8_11_fu_12049_p2 = (tmp283_fu_12043_p2 ^ tmp282_fu_12037_p2);
assign tmp_85_8_12_fu_12067_p2 = (tmp285_fu_12061_p2 ^ tmp284_fu_12055_p2);
assign tmp_85_8_13_fu_12085_p2 = (tmp287_fu_12079_p2 ^ tmp286_fu_12073_p2);
assign tmp_85_8_14_fu_12097_p2 = (tmp288_fu_12091_p2 ^ rv_11_8_3_fu_11745_p3);
assign tmp_85_8_1_fu_11849_p2 = (tmp260_fu_11843_p2 ^ tmp259_fu_11837_p2);
assign tmp_85_8_2_fu_11867_p2 = (tmp262_fu_11861_p2 ^ tmp261_fu_11855_p2);
assign tmp_85_8_3_fu_11879_p2 = (tmp263_fu_11873_p2 ^ rv_11_8_fu_11301_p3);
assign tmp_85_8_4_fu_11902_p2 = (tmp265_fu_11896_p2 ^ tmp264_fu_11885_p2);
assign tmp_85_8_5_fu_11925_p2 = (tmp268_fu_11919_p2 ^ tmp267_fu_11908_p2);
assign tmp_85_8_6_fu_11948_p2 = (tmp271_fu_11942_p2 ^ tmp270_fu_11931_p2);
assign tmp_85_8_7_fu_11965_p2 = (tmp274_fu_11960_p2 ^ tmp273_fu_11954_p2);
assign tmp_85_8_8_fu_11983_p2 = (tmp276_fu_11977_p2 ^ tmp275_fu_11971_p2);
assign tmp_85_8_9_fu_12001_p2 = (tmp278_fu_11995_p2 ^ tmp277_fu_11989_p2);
assign tmp_85_8_fu_11831_p2 = (tmp258_fu_11825_p2 ^ tmp257_fu_11819_p2);
assign tmp_85_8_s_fu_12019_p2 = (tmp280_fu_12013_p2 ^ tmp279_fu_12007_p2);
assign tmp_85_fu_3515_p2 = (tmp2_fu_3509_p2 ^ tmp1_fu_3503_p2);
assign tmp_99_fu_2621_p1 = inptext_V_read[7:0];
assign tmp_9_fu_12209_p2 = (ap_reg_pp0_iter9_tmp_69_7_reg_13709 ^ tmp_4_fu_12203_p2);
assign tmp_fu_3417_p2 = (p_Result_1_reg_12421 ^ 8'd1);
assign tmp_s_fu_12183_p1 = tmp_78_8_fu_11804_p2;
assign x_assign_0_1_fu_2973_p2 = (sboxes_q9 ^ sboxes_q4);
assign x_assign_0_2_fu_3121_p2 = (sboxes_q13 ^ sboxes_q8);
assign x_assign_0_3_fu_3269_p2 = (sboxes_q1 ^ sboxes_q12);
assign x_assign_10_fu_5951_p2 = (sboxes_q65 ^ sboxes_q60);
assign x_assign_171_1_fu_4015_p2 = (sboxes_q29 ^ sboxes_q24);
assign x_assign_171_2_fu_4163_p2 = (sboxes_q33 ^ sboxes_q28);
assign x_assign_171_3_fu_4311_p2 = (sboxes_q21 ^ sboxes_q32);
assign x_assign_1_0_1_fu_3019_p2 = (sboxes_q14 ^ sboxes_q9);
assign x_assign_1_0_2_fu_3167_p2 = (sboxes_q2 ^ sboxes_q13);
assign x_assign_1_0_3_fu_3315_p2 = (sboxes_q6 ^ sboxes_q1);
assign x_assign_1_1_1_fu_4061_p2 = (sboxes_q34 ^ sboxes_q29);
assign x_assign_1_1_2_fu_4209_p2 = (sboxes_q22 ^ sboxes_q33);
assign x_assign_1_1_3_fu_4357_p2 = (sboxes_q26 ^ sboxes_q21);
assign x_assign_1_1_fu_3913_p2 = (sboxes_q30 ^ sboxes_q25);
assign x_assign_1_2_1_fu_5103_p2 = (sboxes_q54 ^ sboxes_q49);
assign x_assign_1_2_2_fu_5251_p2 = (sboxes_q42 ^ sboxes_q53);
assign x_assign_1_2_3_fu_5399_p2 = (sboxes_q46 ^ sboxes_q41);
assign x_assign_1_2_fu_4955_p2 = (sboxes_q50 ^ sboxes_q45);
assign x_assign_1_3_1_fu_6145_p2 = (sboxes_q74 ^ sboxes_q69);
assign x_assign_1_3_2_fu_6293_p2 = (sboxes_q62 ^ sboxes_q73);
assign x_assign_1_3_3_fu_6441_p2 = (sboxes_q66 ^ sboxes_q61);
assign x_assign_1_3_fu_5997_p2 = (sboxes_q70 ^ sboxes_q65);
assign x_assign_1_4_1_fu_7187_p2 = (sboxes_q94 ^ sboxes_q89);
assign x_assign_1_4_2_fu_7335_p2 = (sboxes_q82 ^ sboxes_q93);
assign x_assign_1_4_3_fu_7483_p2 = (sboxes_q86 ^ sboxes_q81);
assign x_assign_1_4_fu_7039_p2 = (sboxes_q90 ^ sboxes_q85);
assign x_assign_1_5_1_fu_8229_p2 = (sboxes_q114 ^ sboxes_q109);
assign x_assign_1_5_2_fu_8377_p2 = (sboxes_q102 ^ sboxes_q113);
assign x_assign_1_5_3_fu_8525_p2 = (sboxes_q106 ^ sboxes_q101);
assign x_assign_1_5_fu_8081_p2 = (sboxes_q110 ^ sboxes_q105);
assign x_assign_1_6_1_fu_9271_p2 = (sboxes_q134 ^ sboxes_q129);
assign x_assign_1_6_2_fu_9419_p2 = (sboxes_q122 ^ sboxes_q133);
assign x_assign_1_6_3_fu_9567_p2 = (sboxes_q126 ^ sboxes_q121);
assign x_assign_1_6_fu_9123_p2 = (sboxes_q130 ^ sboxes_q125);
assign x_assign_1_7_1_fu_10313_p2 = (sboxes_q154 ^ sboxes_q149);
assign x_assign_1_7_2_fu_10461_p2 = (sboxes_q142 ^ sboxes_q153);
assign x_assign_1_7_3_fu_10609_p2 = (sboxes_q146 ^ sboxes_q141);
assign x_assign_1_7_fu_10165_p2 = (sboxes_q150 ^ sboxes_q145);
assign x_assign_1_8_1_fu_11355_p2 = (sboxes_q174 ^ sboxes_q169);
assign x_assign_1_8_2_fu_11503_p2 = (sboxes_q162 ^ sboxes_q173);
assign x_assign_1_8_3_fu_11651_p2 = (sboxes_q166 ^ sboxes_q161);
assign x_assign_1_8_fu_11207_p2 = (sboxes_q170 ^ sboxes_q165);
assign x_assign_1_fu_2871_p2 = (sboxes_q10 ^ sboxes_q5);
assign x_assign_273_1_fu_5057_p2 = (sboxes_q49 ^ sboxes_q44);
assign x_assign_273_2_fu_5205_p2 = (sboxes_q53 ^ sboxes_q48);
assign x_assign_273_3_fu_5353_p2 = (sboxes_q41 ^ sboxes_q52);
assign x_assign_2_0_1_fu_3053_p2 = (sboxes_q3 ^ sboxes_q14);
assign x_assign_2_0_2_fu_3201_p2 = (sboxes_q7 ^ sboxes_q2);
assign x_assign_2_0_3_fu_3349_p2 = (sboxes_q11 ^ sboxes_q6);
assign x_assign_2_1_1_fu_4095_p2 = (sboxes_q23 ^ sboxes_q34);
assign x_assign_2_1_2_fu_4243_p2 = (sboxes_q27 ^ sboxes_q22);
assign x_assign_2_1_3_fu_4391_p2 = (sboxes_q31 ^ sboxes_q26);
assign x_assign_2_1_fu_3947_p2 = (sboxes_q35 ^ sboxes_q30);
assign x_assign_2_2_1_fu_5137_p2 = (sboxes_q43 ^ sboxes_q54);
assign x_assign_2_2_2_fu_5285_p2 = (sboxes_q47 ^ sboxes_q42);
assign x_assign_2_2_3_fu_5433_p2 = (sboxes_q51 ^ sboxes_q46);
assign x_assign_2_2_fu_4989_p2 = (sboxes_q55 ^ sboxes_q50);
assign x_assign_2_3_1_fu_6179_p2 = (sboxes_q63 ^ sboxes_q74);
assign x_assign_2_3_2_fu_6327_p2 = (sboxes_q67 ^ sboxes_q62);
assign x_assign_2_3_3_fu_6475_p2 = (sboxes_q71 ^ sboxes_q66);
assign x_assign_2_3_fu_6031_p2 = (sboxes_q75 ^ sboxes_q70);
assign x_assign_2_4_1_fu_7221_p2 = (sboxes_q83 ^ sboxes_q94);
assign x_assign_2_4_2_fu_7369_p2 = (sboxes_q87 ^ sboxes_q82);
assign x_assign_2_4_3_fu_7517_p2 = (sboxes_q91 ^ sboxes_q86);
assign x_assign_2_4_fu_7073_p2 = (sboxes_q95 ^ sboxes_q90);
assign x_assign_2_5_1_fu_8263_p2 = (sboxes_q103 ^ sboxes_q114);
assign x_assign_2_5_2_fu_8411_p2 = (sboxes_q107 ^ sboxes_q102);
assign x_assign_2_5_3_fu_8559_p2 = (sboxes_q111 ^ sboxes_q106);
assign x_assign_2_5_fu_8115_p2 = (sboxes_q115 ^ sboxes_q110);
assign x_assign_2_6_1_fu_9305_p2 = (sboxes_q123 ^ sboxes_q134);
assign x_assign_2_6_2_fu_9453_p2 = (sboxes_q127 ^ sboxes_q122);
assign x_assign_2_6_3_fu_9601_p2 = (sboxes_q131 ^ sboxes_q126);
assign x_assign_2_6_fu_9157_p2 = (sboxes_q135 ^ sboxes_q130);
assign x_assign_2_7_1_fu_10347_p2 = (sboxes_q143 ^ sboxes_q154);
assign x_assign_2_7_2_fu_10495_p2 = (sboxes_q147 ^ sboxes_q142);
assign x_assign_2_7_3_fu_10643_p2 = (sboxes_q151 ^ sboxes_q146);
assign x_assign_2_7_fu_10199_p2 = (sboxes_q155 ^ sboxes_q150);
assign x_assign_2_8_1_fu_11389_p2 = (sboxes_q163 ^ sboxes_q174);
assign x_assign_2_8_2_fu_11537_p2 = (sboxes_q167 ^ sboxes_q162);
assign x_assign_2_8_3_fu_11685_p2 = (sboxes_q171 ^ sboxes_q166);
assign x_assign_2_8_fu_11241_p2 = (sboxes_q175 ^ sboxes_q170);
assign x_assign_2_fu_2905_p2 = (sboxes_q15 ^ sboxes_q10);
assign x_assign_375_1_fu_6099_p2 = (sboxes_q69 ^ sboxes_q64);
assign x_assign_375_2_fu_6247_p2 = (sboxes_q73 ^ sboxes_q68);
assign x_assign_375_3_fu_6395_p2 = (sboxes_q61 ^ sboxes_q72);
assign x_assign_3_0_1_fu_3087_p2 = (sboxes_q3 ^ sboxes_q4);
assign x_assign_3_0_2_fu_3235_p2 = (sboxes_q7 ^ sboxes_q8);
assign x_assign_3_0_3_fu_3383_p2 = (sboxes_q11 ^ sboxes_q12);
assign x_assign_3_1_1_fu_4129_p2 = (sboxes_q23 ^ sboxes_q24);
assign x_assign_3_1_2_fu_4277_p2 = (sboxes_q27 ^ sboxes_q28);
assign x_assign_3_1_3_fu_4425_p2 = (sboxes_q31 ^ sboxes_q32);
assign x_assign_3_1_fu_3981_p2 = (sboxes_q35 ^ sboxes_q20);
assign x_assign_3_2_1_fu_5171_p2 = (sboxes_q43 ^ sboxes_q44);
assign x_assign_3_2_2_fu_5319_p2 = (sboxes_q47 ^ sboxes_q48);
assign x_assign_3_2_3_fu_5467_p2 = (sboxes_q51 ^ sboxes_q52);
assign x_assign_3_2_fu_5023_p2 = (sboxes_q55 ^ sboxes_q40);
assign x_assign_3_3_1_fu_6213_p2 = (sboxes_q63 ^ sboxes_q64);
assign x_assign_3_3_2_fu_6361_p2 = (sboxes_q67 ^ sboxes_q68);
assign x_assign_3_3_3_fu_6509_p2 = (sboxes_q71 ^ sboxes_q72);
assign x_assign_3_3_fu_6065_p2 = (sboxes_q75 ^ sboxes_q60);
assign x_assign_3_4_1_fu_7255_p2 = (sboxes_q83 ^ sboxes_q84);
assign x_assign_3_4_2_fu_7403_p2 = (sboxes_q87 ^ sboxes_q88);
assign x_assign_3_4_3_fu_7551_p2 = (sboxes_q91 ^ sboxes_q92);
assign x_assign_3_4_fu_7107_p2 = (sboxes_q95 ^ sboxes_q80);
assign x_assign_3_5_1_fu_8297_p2 = (sboxes_q103 ^ sboxes_q104);
assign x_assign_3_5_2_fu_8445_p2 = (sboxes_q107 ^ sboxes_q108);
assign x_assign_3_5_3_fu_8593_p2 = (sboxes_q111 ^ sboxes_q112);
assign x_assign_3_5_fu_8149_p2 = (sboxes_q115 ^ sboxes_q100);
assign x_assign_3_6_1_fu_9339_p2 = (sboxes_q123 ^ sboxes_q124);
assign x_assign_3_6_2_fu_9487_p2 = (sboxes_q127 ^ sboxes_q128);
assign x_assign_3_6_3_fu_9635_p2 = (sboxes_q131 ^ sboxes_q132);
assign x_assign_3_6_fu_9191_p2 = (sboxes_q135 ^ sboxes_q120);
assign x_assign_3_7_1_fu_10381_p2 = (sboxes_q143 ^ sboxes_q144);
assign x_assign_3_7_2_fu_10529_p2 = (sboxes_q147 ^ sboxes_q148);
assign x_assign_3_7_3_fu_10677_p2 = (sboxes_q151 ^ sboxes_q152);
assign x_assign_3_7_fu_10233_p2 = (sboxes_q155 ^ sboxes_q140);
assign x_assign_3_8_1_fu_11423_p2 = (sboxes_q163 ^ sboxes_q164);
assign x_assign_3_8_2_fu_11571_p2 = (sboxes_q167 ^ sboxes_q168);
assign x_assign_3_8_3_fu_11719_p2 = (sboxes_q171 ^ sboxes_q172);
assign x_assign_3_8_fu_11275_p2 = (sboxes_q175 ^ sboxes_q160);
assign x_assign_3_fu_2939_p2 = (sboxes_q15 ^ sboxes_q0);
assign x_assign_4_1_fu_7141_p2 = (sboxes_q89 ^ sboxes_q84);
assign x_assign_4_2_fu_7289_p2 = (sboxes_q93 ^ sboxes_q88);
assign x_assign_4_3_fu_7437_p2 = (sboxes_q81 ^ sboxes_q92);
assign x_assign_4_fu_6993_p2 = (sboxes_q85 ^ sboxes_q80);
assign x_assign_5_1_fu_8183_p2 = (sboxes_q109 ^ sboxes_q104);
assign x_assign_5_2_fu_8331_p2 = (sboxes_q113 ^ sboxes_q108);
assign x_assign_5_3_fu_8479_p2 = (sboxes_q101 ^ sboxes_q112);
assign x_assign_5_fu_8035_p2 = (sboxes_q105 ^ sboxes_q100);
assign x_assign_6_1_fu_9225_p2 = (sboxes_q129 ^ sboxes_q124);
assign x_assign_6_2_fu_9373_p2 = (sboxes_q133 ^ sboxes_q128);
assign x_assign_6_3_fu_9521_p2 = (sboxes_q121 ^ sboxes_q132);
assign x_assign_6_fu_9077_p2 = (sboxes_q125 ^ sboxes_q120);
assign x_assign_7_1_fu_10267_p2 = (sboxes_q149 ^ sboxes_q144);
assign x_assign_7_2_fu_10415_p2 = (sboxes_q153 ^ sboxes_q148);
assign x_assign_7_3_fu_10563_p2 = (sboxes_q141 ^ sboxes_q152);
assign x_assign_7_fu_10119_p2 = (sboxes_q145 ^ sboxes_q140);
assign x_assign_8_1_fu_11309_p2 = (sboxes_q169 ^ sboxes_q164);
assign x_assign_8_2_fu_11457_p2 = (sboxes_q173 ^ sboxes_q168);
assign x_assign_8_3_fu_11605_p2 = (sboxes_q161 ^ sboxes_q172);
assign x_assign_8_fu_11161_p2 = (sboxes_q165 ^ sboxes_q160);
assign x_assign_9_fu_4909_p2 = (sboxes_q45 ^ sboxes_q40);
assign x_assign_fu_2825_p2 = (sboxes_q5 ^ sboxes_q0);
assign x_assign_s_fu_3867_p2 = (sboxes_q25 ^ sboxes_q20);
endmodule //aestest
|
// Fetch-Issue Pipeline Register
module iss_pipe_reg
(
input wire clk,
input wire reset,
input wire clr,
input wire enable,
// PC related inputs from fetch stage
input wire[31:0] next_pc_iss_pipe_reg_i,
input wire[31:0] instr_iss_pipe_reg_i,
input wire brn_pred_iss_pipe_reg_i,
input wire[31:0] curr_pc_iss_pipe_reg_i,
input wire[31:0] next_pred_pc_iss_pipe_reg_i,
// Register outputs
output wire[31:0] next_pc_iss_pipe_reg_o,
output wire[31:0] instr_iss_pipe_reg_o,
output wire brn_pred_iss_pipe_reg_o,
output wire[31:0] curr_pc_iss_pipe_reg_o,
output wire[31:0] next_pred_pc_iss_pipe_reg_o
);
reg [31:0] next_pc_iss_pipe_reg;
reg [31:0] instr_iss_pipe_reg;
reg brn_pred_iss_pipe_reg;
reg [31:0] curr_pc_iss_pipe_reg;
reg [31:0] next_pred_pc_iss_pipe_reg;
assign next_pc_iss_pipe_reg_o = next_pc_iss_pipe_reg;
assign instr_iss_pipe_reg_o = instr_iss_pipe_reg;
assign brn_pred_iss_pipe_reg_o = brn_pred_iss_pipe_reg;
assign curr_pc_iss_pipe_reg_o = curr_pc_iss_pipe_reg;
assign next_pred_pc_iss_pipe_reg_o = next_pred_pc_iss_pipe_reg;
always @(posedge clk or posedge reset)
if (reset | clr)
begin
next_pc_iss_pipe_reg <= 31'b0;
instr_iss_pipe_reg <= 31'b0;
brn_pred_iss_pipe_reg <= 31'b0;
curr_pc_iss_pipe_reg <= 31'b0;
next_pred_pc_iss_pipe_reg <= 31'b0;
end
else if (~enable)
begin
next_pc_iss_pipe_reg <= next_pc_iss_pipe_reg_i;
instr_iss_pipe_reg <= instr_iss_pipe_reg_i;
brn_pred_iss_pipe_reg <= brn_pred_iss_pipe_reg_i;
curr_pc_iss_pipe_reg <= curr_pc_iss_pipe_reg_i;
next_pred_pc_iss_pipe_reg <= next_pred_pc_iss_pipe_reg_i;
end
endmodule
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_acv_hard_io_pads(
reset_n_addr_cmd_clk,
reset_n_afi_clk,
oct_ctl_rs_value,
oct_ctl_rt_value,
phy_ddio_address,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_odt,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_ck,
phy_ddio_reset_n,
phy_mem_address,
phy_mem_bank,
phy_mem_cs_n,
phy_mem_cke,
phy_mem_odt,
phy_mem_we_n,
phy_mem_ras_n,
phy_mem_cas_n,
phy_mem_reset_n,
pll_afi_clk,
pll_afi_phy_clk,
pll_avl_phy_clk,
pll_avl_clk,
avl_clk,
pll_mem_clk,
pll_mem_phy_clk,
pll_write_clk,
pll_dqs_ena_clk,
pll_addr_cmd_clk,
phy_mem_dq,
phy_mem_dm,
phy_mem_ck,
phy_mem_ck_n,
mem_dqs,
mem_dqs_n,
dll_phy_delayctrl,
scc_clk,
scc_data,
scc_dqs_ena,
scc_dqs_io_ena,
scc_dq_ena,
scc_dm_ena,
scc_upd,
seq_read_latency_counter,
seq_read_increment_vfifo_fr,
seq_read_increment_vfifo_hr,
phy_ddio_dmdout,
phy_ddio_dqdout,
phy_ddio_dqs_oe,
phy_ddio_dqsdout,
phy_ddio_dqsb_oe,
phy_ddio_dqslogic_oct,
phy_ddio_dqslogic_fiforeset,
phy_ddio_dqslogic_aclr_pstamble,
phy_ddio_dqslogic_aclr_fifoctrl,
phy_ddio_dqslogic_incwrptr,
phy_ddio_dqslogic_readlatency,
ddio_phy_dqslogic_rdatavalid,
ddio_phy_dqdin,
phy_ddio_dqslogic_incrdataen,
phy_ddio_dqslogic_dqsena,
phy_ddio_dqoe,
capture_strobe_tracking
);
parameter DEVICE_FAMILY = "";
parameter FAST_SIM_MODEL = 0;
parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = "";
parameter ADC_INVERT_PHASE = "";
parameter IS_HHP_HPS = "";
localparam AFI_ADDRESS_WIDTH = 64;
localparam AFI_BANK_WIDTH = 12;
localparam AFI_CHIP_SELECT_WIDTH = 8;
localparam AFI_CLK_EN_WIDTH = 8;
localparam AFI_ODT_WIDTH = 8;
localparam AFI_DATA_MASK_WIDTH = 20;
localparam AFI_CONTROL_WIDTH = 4;
input reset_n_afi_clk;
input reset_n_addr_cmd_clk;
input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ck;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
output phy_mem_reset_n;
input pll_afi_clk;
input pll_afi_phy_clk;
input pll_avl_phy_clk;
input pll_avl_clk;
input avl_clk;
input pll_mem_clk;
input pll_mem_phy_clk;
input pll_write_clk;
input pll_dqs_ena_clk;
input pll_addr_cmd_clk;
inout [MEM_DQ_WIDTH-1:0] phy_mem_dq;
output [MEM_DM_WIDTH-1:0] phy_mem_dm;
output [MEM_CK_WIDTH-1:0] phy_mem_ck;
output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
input scc_clk;
input scc_data;
input [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_ena;
input [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_io_ena;
input [MEM_DQ_WIDTH - 1:0] scc_dq_ena;
input [MEM_DM_WIDTH - 1:0] scc_dm_ena;
input [4:0] seq_read_latency_counter;
input [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_fr;
input [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_hr;
input scc_upd;
output [MEM_READ_DQS_WIDTH - 1:0] capture_strobe_tracking;
input [24 : 0] phy_ddio_dmdout;
input [179 : 0] phy_ddio_dqdout;
input [9 : 0] phy_ddio_dqs_oe;
input [19 : 0] phy_ddio_dqsdout;
input [9 : 0] phy_ddio_dqsb_oe;
input [9 : 0] phy_ddio_dqslogic_oct;
input [4 : 0] phy_ddio_dqslogic_fiforeset;
input [4 : 0] phy_ddio_dqslogic_aclr_pstamble;
input [4 : 0] phy_ddio_dqslogic_aclr_fifoctrl;
input [9 : 0] phy_ddio_dqslogic_incwrptr;
input [24 : 0] phy_ddio_dqslogic_readlatency;
output [4 : 0] ddio_phy_dqslogic_rdatavalid;
output [179 : 0] ddio_phy_dqdin;
input [9 : 0] phy_ddio_dqslogic_incrdataen;
input [9 : 0] phy_ddio_dqslogic_dqsena;
input [89 : 0] phy_ddio_dqoe;
wire [MEM_DQ_WIDTH-1:0] mem_phy_dq;
wire [DLL_DELAY_CTRL_WIDTH-1:0] read_bidir_dll_phy_delayctrl;
wire [MEM_READ_DQS_WIDTH-1:0] bidir_read_dqs_bus_out;
wire [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_high;
wire [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_low;
wire hr_clk = pll_avl_clk;
wire core_clk = pll_afi_clk;
wire reset_n_core_clk = reset_n_afi_clk;
hps_sdram_p0_acv_hard_addr_cmd_pads uaddr_cmd_pads(
/*
.config_data_in(config_data_in),
.config_clock_in(config_clock_in),
.config_io_ena(config_io_ena),
.config_update(config_update),
*/
.reset_n (reset_n_addr_cmd_clk),
.reset_n_afi_clk (reset_n_afi_clk),
.pll_afi_clk (pll_afi_phy_clk),
.pll_mem_clk (pll_mem_phy_clk),
.pll_hr_clk (hr_clk),
.pll_avl_phy_clk (pll_avl_phy_clk),
.pll_write_clk (pll_write_clk),
.dll_delayctrl_in (dll_phy_delayctrl),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_ddio_ck (phy_ddio_ck),
.phy_ddio_reset_n (phy_ddio_reset_n),
.phy_mem_address (phy_mem_address),
.phy_mem_bank (phy_mem_bank),
.phy_mem_cs_n (phy_mem_cs_n),
.phy_mem_cke (phy_mem_cke),
.phy_mem_odt (phy_mem_odt),
.phy_mem_we_n (phy_mem_we_n),
.phy_mem_ras_n (phy_mem_ras_n),
.phy_mem_cas_n (phy_mem_cas_n),
.phy_mem_reset_n (phy_mem_reset_n),
.phy_mem_ck (phy_mem_ck),
.phy_mem_ck_n (phy_mem_ck_n)
);
defparam uaddr_cmd_pads.DEVICE_FAMILY = DEVICE_FAMILY;
defparam uaddr_cmd_pads.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uaddr_cmd_pads.MEM_BANK_WIDTH = MEM_BANK_WIDTH;
defparam uaddr_cmd_pads.MEM_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_pads.MEM_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH;
defparam uaddr_cmd_pads.MEM_CK_WIDTH = MEM_CK_WIDTH;
defparam uaddr_cmd_pads.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
defparam uaddr_cmd_pads.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_pads.AFI_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH * 4;
defparam uaddr_cmd_pads.AFI_BANK_WIDTH = MEM_BANK_WIDTH * 4;
defparam uaddr_cmd_pads.AFI_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH * 4;
defparam uaddr_cmd_pads.AFI_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH * 4;
defparam uaddr_cmd_pads.AFI_ODT_WIDTH = MEM_ODT_WIDTH * 4;
defparam uaddr_cmd_pads.AFI_CONTROL_WIDTH = MEM_CONTROL_WIDTH * 4;
defparam uaddr_cmd_pads.DLL_WIDTH = DLL_DELAY_CTRL_WIDTH;
defparam uaddr_cmd_pads.ADC_PHASE_SETTING = ADC_PHASE_SETTING;
defparam uaddr_cmd_pads.ADC_INVERT_PHASE = ADC_INVERT_PHASE;
defparam uaddr_cmd_pads.IS_HHP_HPS = IS_HHP_HPS;
localparam NUM_OF_DQDQS = MEM_WRITE_DQS_WIDTH;
localparam DQDQS_DATA_WIDTH = MEM_DQ_WIDTH / NUM_OF_DQDQS;
localparam NATIVE_GROUP_SIZE =
(DQDQS_DATA_WIDTH == 8) ? 9 : DQDQS_DATA_WIDTH;
localparam DQDQS_DM_WIDTH = MEM_DM_WIDTH / MEM_WRITE_DQS_WIDTH;
localparam NUM_OF_DQDQS_WITH_DM = MEM_WRITE_DQS_WIDTH;
generate
genvar i;
for (i=0; i<NUM_OF_DQDQS; i=i+1)
begin: dq_ddio
hps_sdram_p0_altdqdqs ubidir_dq_dqs (
.write_strobe_clock_in (pll_mem_phy_clk),
.reset_n_core_clock_in (reset_n_core_clk),
.core_clock_in (core_clk),
.fr_clock_in (pll_write_clk),
.hr_clock_in (pll_avl_phy_clk),
.parallelterminationcontrol_in(oct_ctl_rt_value),
.seriesterminationcontrol_in(oct_ctl_rs_value),
.strobe_ena_hr_clock_in (hr_clk),
.capture_strobe_tracking (capture_strobe_tracking[i]),
.read_write_data_io (phy_mem_dq[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
.read_data_out (ddio_phy_dqdin[((NATIVE_GROUP_SIZE*i+DQDQS_DATA_WIDTH)*4-1) : (NATIVE_GROUP_SIZE*i*4)]),
.capture_strobe_out(dqs_busout),
.extra_write_data_in (phy_ddio_dmdout[(i + 1) * 4 - 1 : (i * 4)]),
.write_data_in (phy_ddio_dqdout[((NATIVE_GROUP_SIZE*i+DQDQS_DATA_WIDTH)*4-1) : (NATIVE_GROUP_SIZE*i*4)]),
.write_oe_in (phy_ddio_dqoe[((NATIVE_GROUP_SIZE*i+DQDQS_DATA_WIDTH)*2-1) : (NATIVE_GROUP_SIZE*i*2)]),
.strobe_io (mem_dqs[i]),
.strobe_n_io (mem_dqs_n[i]),
.output_strobe_ena(phy_ddio_dqs_oe[(i + 1) * 2 - 1 : (i * 2)]),
.write_strobe(phy_ddio_dqsdout[(i + 1) * 4 - 1 : (i * 4)]),
.oct_ena_in(phy_ddio_dqslogic_oct[(i + 1) * 2 - 1 : (i * 2)]),
.extra_write_data_out (phy_mem_dm[i]),
.config_data_in (scc_data),
.config_dqs_ena (scc_dqs_ena[i]),
.config_io_ena (scc_dq_ena[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
.config_dqs_io_ena (scc_dqs_io_ena[i]),
.config_update (scc_upd),
.config_clock_in (scc_clk),
.config_extra_io_ena (scc_dm_ena[i]),
.lfifo_rdata_en(phy_ddio_dqslogic_incrdataen[(i + 1) * 2 - 1 : (i * 2)]),
.lfifo_rdata_en_full(phy_ddio_dqslogic_dqsena[(i + 1) * 2 - 1 : (i * 2)]),
.lfifo_rd_latency(phy_ddio_dqslogic_readlatency[(i + 1) * 5 - 1 : (i * 5)]),
.lfifo_reset_n (phy_ddio_dqslogic_aclr_fifoctrl[i]),
.lfifo_rdata_valid(ddio_phy_dqslogic_rdatavalid[i]),
.vfifo_qvld(phy_ddio_dqslogic_dqsena[(i + 1) * 2 - 1 : (i * 2)]),
.vfifo_inc_wr_ptr(phy_ddio_dqslogic_incwrptr[(i + 1) * 2 - 1 : (i * 2)]),
.vfifo_reset_n (phy_ddio_dqslogic_aclr_pstamble[i]),
.dll_delayctrl_in (dll_phy_delayctrl),
.rfifo_reset_n(phy_ddio_dqslogic_fiforeset[i])
);
end
endgenerate
generate
genvar j;
for (j = NUM_OF_DQDQS; j < 5; j=j+1)
begin: to_vcc
assign ddio_phy_dqslogic_rdatavalid[j] = 1'b1;
end
endgenerate
endmodule
|
// generated by gen_VerilogEHR.py using VerilogEHR.mako
// Copyright (c) 2019 Massachusetts Institute of Technology
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
module EHR_5 (
CLK,
RST_N,
read_0,
write_0,
EN_write_0,
read_1,
write_1,
EN_write_1,
read_2,
write_2,
EN_write_2,
read_3,
write_3,
EN_write_3,
read_4,
write_4,
EN_write_4
);
parameter DATA_SZ = 1;
parameter RESET_VAL = 0;
input CLK;
input RST_N;
output [DATA_SZ-1:0] read_0;
input [DATA_SZ-1:0] write_0;
input EN_write_0;
output [DATA_SZ-1:0] read_1;
input [DATA_SZ-1:0] write_1;
input EN_write_1;
output [DATA_SZ-1:0] read_2;
input [DATA_SZ-1:0] write_2;
input EN_write_2;
output [DATA_SZ-1:0] read_3;
input [DATA_SZ-1:0] write_3;
input EN_write_3;
output [DATA_SZ-1:0] read_4;
input [DATA_SZ-1:0] write_4;
input EN_write_4;
reg [DATA_SZ-1:0] r;
wire [DATA_SZ-1:0] wire_0;
wire [DATA_SZ-1:0] wire_1;
wire [DATA_SZ-1:0] wire_2;
wire [DATA_SZ-1:0] wire_3;
wire [DATA_SZ-1:0] wire_4;
wire [DATA_SZ-1:0] wire_5;
assign wire_0 = r;
assign wire_1 = EN_write_0 ? write_0 : wire_0;
assign wire_2 = EN_write_1 ? write_1 : wire_1;
assign wire_3 = EN_write_2 ? write_2 : wire_2;
assign wire_4 = EN_write_3 ? write_3 : wire_3;
assign wire_5 = EN_write_4 ? write_4 : wire_4;
assign read_0 = wire_0;
assign read_1 = wire_1;
assign read_2 = wire_2;
assign read_3 = wire_3;
assign read_4 = wire_4;
always @(posedge CLK) begin
if (RST_N == 0) begin
r <= RESET_VAL;
end else begin
r <= wire_5;
end
end
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module contains counter for the width and height of frames for the *
* video clipper core. *
* *
******************************************************************************/
module altera_up_video_clipper_counters (
// Inputs
clk,
reset,
increment_counters,
// Bi-Directional
// Outputs
start_of_outer_frame,
end_of_outer_frame,
start_of_inner_frame,
end_of_inner_frame,
inner_frame_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IMAGE_WIDTH = 640; // Final image width in pixels
parameter IMAGE_HEIGHT = 480; // Final image height in lines
parameter WW = 9; // Final image width address width
parameter HW = 8; // Final image height address width
parameter LEFT_OFFSET = 0;
parameter RIGHT_OFFSET = 0;
parameter TOP_OFFSET = 0;
parameter BOTTOM_OFFSET = 0;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input increment_counters;
// Bi-Directional
// Outputs
output start_of_outer_frame;
output end_of_outer_frame;
output start_of_inner_frame;
output end_of_inner_frame;
output inner_frame_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [WW: 0] width;
reg [HW: 0] height;
reg inner_width_valid;
reg inner_height_valid;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output registers
// Internal registers
always @(posedge clk)
begin
if (reset)
width <= 'h0;
else if (increment_counters & (width == (IMAGE_WIDTH - 1)))
width <= 'h0;
else if (increment_counters)
width <= width + 1;
end
always @(posedge clk)
begin
if (reset)
height <= 'h0;
else if (increment_counters & (width == (IMAGE_WIDTH - 1)))
begin
if (height == (IMAGE_HEIGHT - 1))
height <= 'h0;
else
height <= height + 1;
end
end
always @(posedge clk)
begin
if (reset)
inner_width_valid <= (LEFT_OFFSET == 0);
else if (increment_counters)
begin
if (width == (IMAGE_WIDTH - 1))
inner_width_valid <= (LEFT_OFFSET == 0);
else if (width == (IMAGE_WIDTH - RIGHT_OFFSET - 1))
inner_width_valid <= 1'b0;
else if (width == (LEFT_OFFSET - 1))
inner_width_valid <= 1'b1;
end
end
always @(posedge clk)
begin
if (reset)
inner_height_valid <= (TOP_OFFSET == 0);
else if (increment_counters & (width == (IMAGE_WIDTH - 1)))
begin
if (height == (IMAGE_HEIGHT - 1))
inner_height_valid <= (TOP_OFFSET == 0);
else if (height == (IMAGE_HEIGHT - BOTTOM_OFFSET - 1))
inner_height_valid <= 1'b0;
else if (height == (TOP_OFFSET - 1))
inner_height_valid <= 1'b1;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign start_of_outer_frame = (width == 'h0) & (height == 'h0);
assign end_of_outer_frame = (width == (IMAGE_WIDTH - 1)) &
(height == (IMAGE_HEIGHT - 1));
assign start_of_inner_frame = (width == LEFT_OFFSET) &
(height == TOP_OFFSET);
assign end_of_inner_frame = (width == (IMAGE_WIDTH - RIGHT_OFFSET - 1)) &
(height == (IMAGE_HEIGHT - BOTTOM_OFFSET - 1));
assign inner_frame_valid = inner_width_valid & inner_height_valid;
// Internal assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_fmsw_gp.v
*
* Date : 2012-11
*
* Description : Mimics FMSW switch.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_fmsw_gp(
sw_clk,
rstn,
w_qos_gp0,
r_qos_gp0,
wr_ack_ocm_gp0,
wr_ack_ddr_gp0,
wr_data_gp0,
wr_addr_gp0,
wr_bytes_gp0,
wr_dv_ocm_gp0,
wr_dv_ddr_gp0,
rd_req_ocm_gp0,
rd_req_ddr_gp0,
rd_req_reg_gp0,
rd_addr_gp0,
rd_bytes_gp0,
rd_data_ocm_gp0,
rd_data_ddr_gp0,
rd_data_reg_gp0,
rd_dv_ocm_gp0,
rd_dv_ddr_gp0,
rd_dv_reg_gp0,
w_qos_gp1,
r_qos_gp1,
wr_ack_ocm_gp1,
wr_ack_ddr_gp1,
wr_data_gp1,
wr_addr_gp1,
wr_bytes_gp1,
wr_dv_ocm_gp1,
wr_dv_ddr_gp1,
rd_req_ocm_gp1,
rd_req_ddr_gp1,
rd_req_reg_gp1,
rd_addr_gp1,
rd_bytes_gp1,
rd_data_ocm_gp1,
rd_data_ddr_gp1,
rd_data_reg_gp1,
rd_dv_ocm_gp1,
rd_dv_ddr_gp1,
rd_dv_reg_gp1,
ocm_wr_ack,
ocm_wr_dv,
ocm_rd_req,
ocm_rd_dv,
ddr_wr_ack,
ddr_wr_dv,
ddr_rd_req,
ddr_rd_dv,
reg_rd_req,
reg_rd_dv,
ocm_wr_qos,
ddr_wr_qos,
ocm_rd_qos,
ddr_rd_qos,
reg_rd_qos,
ocm_wr_addr,
ocm_wr_data,
ocm_wr_bytes,
ocm_rd_addr,
ocm_rd_data,
ocm_rd_bytes,
ddr_wr_addr,
ddr_wr_data,
ddr_wr_bytes,
ddr_rd_addr,
ddr_rd_data,
ddr_rd_bytes,
reg_rd_addr,
reg_rd_data,
reg_rd_bytes
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input sw_clk;
input rstn;
input [axi_qos_width-1:0]w_qos_gp0;
input [axi_qos_width-1:0]r_qos_gp0;
input [axi_qos_width-1:0]w_qos_gp1;
input [axi_qos_width-1:0]r_qos_gp1;
output [axi_qos_width-1:0]ocm_wr_qos;
output [axi_qos_width-1:0]ocm_rd_qos;
output [axi_qos_width-1:0]ddr_wr_qos;
output [axi_qos_width-1:0]ddr_rd_qos;
output [axi_qos_width-1:0]reg_rd_qos;
output wr_ack_ocm_gp0;
output wr_ack_ddr_gp0;
input [max_burst_bits-1:0] wr_data_gp0;
input [addr_width-1:0] wr_addr_gp0;
input [max_burst_bytes_width:0] wr_bytes_gp0;
output wr_dv_ocm_gp0;
output wr_dv_ddr_gp0;
input rd_req_ocm_gp0;
input rd_req_ddr_gp0;
input rd_req_reg_gp0;
input [addr_width-1:0] rd_addr_gp0;
input [max_burst_bytes_width:0] rd_bytes_gp0;
output [max_burst_bits-1:0] rd_data_ocm_gp0;
output [max_burst_bits-1:0] rd_data_ddr_gp0;
output [max_burst_bits-1:0] rd_data_reg_gp0;
output rd_dv_ocm_gp0;
output rd_dv_ddr_gp0;
output rd_dv_reg_gp0;
output wr_ack_ocm_gp1;
output wr_ack_ddr_gp1;
input [max_burst_bits-1:0] wr_data_gp1;
input [addr_width-1:0] wr_addr_gp1;
input [max_burst_bytes_width:0] wr_bytes_gp1;
output wr_dv_ocm_gp1;
output wr_dv_ddr_gp1;
input rd_req_ocm_gp1;
input rd_req_ddr_gp1;
input rd_req_reg_gp1;
input [addr_width-1:0] rd_addr_gp1;
input [max_burst_bytes_width:0] rd_bytes_gp1;
output [max_burst_bits-1:0] rd_data_ocm_gp1;
output [max_burst_bits-1:0] rd_data_ddr_gp1;
output [max_burst_bits-1:0] rd_data_reg_gp1;
output rd_dv_ocm_gp1;
output rd_dv_ddr_gp1;
output rd_dv_reg_gp1;
input ocm_wr_ack;
output ocm_wr_dv;
output [addr_width-1:0]ocm_wr_addr;
output [max_burst_bits-1:0]ocm_wr_data;
output [max_burst_bytes_width:0]ocm_wr_bytes;
input ocm_rd_dv;
input [max_burst_bits-1:0] ocm_rd_data;
output ocm_rd_req;
output [addr_width-1:0] ocm_rd_addr;
output [max_burst_bytes_width:0] ocm_rd_bytes;
input ddr_wr_ack;
output ddr_wr_dv;
output [addr_width-1:0]ddr_wr_addr;
output [max_burst_bits-1:0]ddr_wr_data;
output [max_burst_bytes_width:0]ddr_wr_bytes;
input ddr_rd_dv;
input [max_burst_bits-1:0] ddr_rd_data;
output ddr_rd_req;
output [addr_width-1:0] ddr_rd_addr;
output [max_burst_bytes_width:0] ddr_rd_bytes;
input reg_rd_dv;
input [max_burst_bits-1:0] reg_rd_data;
output reg_rd_req;
output [addr_width-1:0] reg_rd_addr;
output [max_burst_bytes_width:0] reg_rd_bytes;
processing_system7_bfm_v2_0_5_arb_wr ocm_gp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_gp0),
.qos2(w_qos_gp1),
.prt_dv1(wr_dv_ocm_gp0),
.prt_dv2(wr_dv_ocm_gp1),
.prt_data1(wr_data_gp0),
.prt_data2(wr_data_gp1),
.prt_addr1(wr_addr_gp0),
.prt_addr2(wr_addr_gp1),
.prt_bytes1(wr_bytes_gp0),
.prt_bytes2(wr_bytes_gp1),
.prt_ack1(wr_ack_ocm_gp0),
.prt_ack2(wr_ack_ocm_gp1),
.prt_req(ocm_wr_dv),
.prt_qos(ocm_wr_qos),
.prt_data(ocm_wr_data),
.prt_addr(ocm_wr_addr),
.prt_bytes(ocm_wr_bytes),
.prt_ack(ocm_wr_ack)
);
processing_system7_bfm_v2_0_5_arb_wr ddr_gp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_gp0),
.qos2(w_qos_gp1),
.prt_dv1(wr_dv_ddr_gp0),
.prt_dv2(wr_dv_ddr_gp1),
.prt_data1(wr_data_gp0),
.prt_data2(wr_data_gp1),
.prt_addr1(wr_addr_gp0),
.prt_addr2(wr_addr_gp1),
.prt_bytes1(wr_bytes_gp0),
.prt_bytes2(wr_bytes_gp1),
.prt_ack1(wr_ack_ddr_gp0),
.prt_ack2(wr_ack_ddr_gp1),
.prt_req(ddr_wr_dv),
.prt_qos(ddr_wr_qos),
.prt_data(ddr_wr_data),
.prt_addr(ddr_wr_addr),
.prt_bytes(ddr_wr_bytes),
.prt_ack(ddr_wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd ocm_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_ocm_gp0),
.prt_req2(rd_req_ocm_gp1),
.prt_data1(rd_data_ocm_gp0),
.prt_data2(rd_data_ocm_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_ocm_gp0),
.prt_dv2(rd_dv_ocm_gp1),
.prt_req(ocm_rd_req),
.prt_qos(ocm_rd_qos),
.prt_data(ocm_rd_data),
.prt_addr(ocm_rd_addr),
.prt_bytes(ocm_rd_bytes),
.prt_dv(ocm_rd_dv)
);
processing_system7_bfm_v2_0_5_arb_rd ddr_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_ddr_gp0),
.prt_req2(rd_req_ddr_gp1),
.prt_data1(rd_data_ddr_gp0),
.prt_data2(rd_data_ddr_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_ddr_gp0),
.prt_dv2(rd_dv_ddr_gp1),
.prt_req(ddr_rd_req),
.prt_qos(ddr_rd_qos),
.prt_data(ddr_rd_data),
.prt_addr(ddr_rd_addr),
.prt_bytes(ddr_rd_bytes),
.prt_dv(ddr_rd_dv)
);
processing_system7_bfm_v2_0_5_arb_rd reg_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_reg_gp0),
.prt_req2(rd_req_reg_gp1),
.prt_data1(rd_data_reg_gp0),
.prt_data2(rd_data_reg_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_reg_gp0),
.prt_dv2(rd_dv_reg_gp1),
.prt_req(reg_rd_req),
.prt_qos(reg_rd_qos),
.prt_data(reg_rd_data),
.prt_addr(reg_rd_addr),
.prt_bytes(reg_rd_bytes),
.prt_dv(reg_rd_dv)
);
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_fmsw_gp.v
*
* Date : 2012-11
*
* Description : Mimics FMSW switch.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_fmsw_gp(
sw_clk,
rstn,
w_qos_gp0,
r_qos_gp0,
wr_ack_ocm_gp0,
wr_ack_ddr_gp0,
wr_data_gp0,
wr_addr_gp0,
wr_bytes_gp0,
wr_dv_ocm_gp0,
wr_dv_ddr_gp0,
rd_req_ocm_gp0,
rd_req_ddr_gp0,
rd_req_reg_gp0,
rd_addr_gp0,
rd_bytes_gp0,
rd_data_ocm_gp0,
rd_data_ddr_gp0,
rd_data_reg_gp0,
rd_dv_ocm_gp0,
rd_dv_ddr_gp0,
rd_dv_reg_gp0,
w_qos_gp1,
r_qos_gp1,
wr_ack_ocm_gp1,
wr_ack_ddr_gp1,
wr_data_gp1,
wr_addr_gp1,
wr_bytes_gp1,
wr_dv_ocm_gp1,
wr_dv_ddr_gp1,
rd_req_ocm_gp1,
rd_req_ddr_gp1,
rd_req_reg_gp1,
rd_addr_gp1,
rd_bytes_gp1,
rd_data_ocm_gp1,
rd_data_ddr_gp1,
rd_data_reg_gp1,
rd_dv_ocm_gp1,
rd_dv_ddr_gp1,
rd_dv_reg_gp1,
ocm_wr_ack,
ocm_wr_dv,
ocm_rd_req,
ocm_rd_dv,
ddr_wr_ack,
ddr_wr_dv,
ddr_rd_req,
ddr_rd_dv,
reg_rd_req,
reg_rd_dv,
ocm_wr_qos,
ddr_wr_qos,
ocm_rd_qos,
ddr_rd_qos,
reg_rd_qos,
ocm_wr_addr,
ocm_wr_data,
ocm_wr_bytes,
ocm_rd_addr,
ocm_rd_data,
ocm_rd_bytes,
ddr_wr_addr,
ddr_wr_data,
ddr_wr_bytes,
ddr_rd_addr,
ddr_rd_data,
ddr_rd_bytes,
reg_rd_addr,
reg_rd_data,
reg_rd_bytes
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input sw_clk;
input rstn;
input [axi_qos_width-1:0]w_qos_gp0;
input [axi_qos_width-1:0]r_qos_gp0;
input [axi_qos_width-1:0]w_qos_gp1;
input [axi_qos_width-1:0]r_qos_gp1;
output [axi_qos_width-1:0]ocm_wr_qos;
output [axi_qos_width-1:0]ocm_rd_qos;
output [axi_qos_width-1:0]ddr_wr_qos;
output [axi_qos_width-1:0]ddr_rd_qos;
output [axi_qos_width-1:0]reg_rd_qos;
output wr_ack_ocm_gp0;
output wr_ack_ddr_gp0;
input [max_burst_bits-1:0] wr_data_gp0;
input [addr_width-1:0] wr_addr_gp0;
input [max_burst_bytes_width:0] wr_bytes_gp0;
output wr_dv_ocm_gp0;
output wr_dv_ddr_gp0;
input rd_req_ocm_gp0;
input rd_req_ddr_gp0;
input rd_req_reg_gp0;
input [addr_width-1:0] rd_addr_gp0;
input [max_burst_bytes_width:0] rd_bytes_gp0;
output [max_burst_bits-1:0] rd_data_ocm_gp0;
output [max_burst_bits-1:0] rd_data_ddr_gp0;
output [max_burst_bits-1:0] rd_data_reg_gp0;
output rd_dv_ocm_gp0;
output rd_dv_ddr_gp0;
output rd_dv_reg_gp0;
output wr_ack_ocm_gp1;
output wr_ack_ddr_gp1;
input [max_burst_bits-1:0] wr_data_gp1;
input [addr_width-1:0] wr_addr_gp1;
input [max_burst_bytes_width:0] wr_bytes_gp1;
output wr_dv_ocm_gp1;
output wr_dv_ddr_gp1;
input rd_req_ocm_gp1;
input rd_req_ddr_gp1;
input rd_req_reg_gp1;
input [addr_width-1:0] rd_addr_gp1;
input [max_burst_bytes_width:0] rd_bytes_gp1;
output [max_burst_bits-1:0] rd_data_ocm_gp1;
output [max_burst_bits-1:0] rd_data_ddr_gp1;
output [max_burst_bits-1:0] rd_data_reg_gp1;
output rd_dv_ocm_gp1;
output rd_dv_ddr_gp1;
output rd_dv_reg_gp1;
input ocm_wr_ack;
output ocm_wr_dv;
output [addr_width-1:0]ocm_wr_addr;
output [max_burst_bits-1:0]ocm_wr_data;
output [max_burst_bytes_width:0]ocm_wr_bytes;
input ocm_rd_dv;
input [max_burst_bits-1:0] ocm_rd_data;
output ocm_rd_req;
output [addr_width-1:0] ocm_rd_addr;
output [max_burst_bytes_width:0] ocm_rd_bytes;
input ddr_wr_ack;
output ddr_wr_dv;
output [addr_width-1:0]ddr_wr_addr;
output [max_burst_bits-1:0]ddr_wr_data;
output [max_burst_bytes_width:0]ddr_wr_bytes;
input ddr_rd_dv;
input [max_burst_bits-1:0] ddr_rd_data;
output ddr_rd_req;
output [addr_width-1:0] ddr_rd_addr;
output [max_burst_bytes_width:0] ddr_rd_bytes;
input reg_rd_dv;
input [max_burst_bits-1:0] reg_rd_data;
output reg_rd_req;
output [addr_width-1:0] reg_rd_addr;
output [max_burst_bytes_width:0] reg_rd_bytes;
processing_system7_bfm_v2_0_5_arb_wr ocm_gp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_gp0),
.qos2(w_qos_gp1),
.prt_dv1(wr_dv_ocm_gp0),
.prt_dv2(wr_dv_ocm_gp1),
.prt_data1(wr_data_gp0),
.prt_data2(wr_data_gp1),
.prt_addr1(wr_addr_gp0),
.prt_addr2(wr_addr_gp1),
.prt_bytes1(wr_bytes_gp0),
.prt_bytes2(wr_bytes_gp1),
.prt_ack1(wr_ack_ocm_gp0),
.prt_ack2(wr_ack_ocm_gp1),
.prt_req(ocm_wr_dv),
.prt_qos(ocm_wr_qos),
.prt_data(ocm_wr_data),
.prt_addr(ocm_wr_addr),
.prt_bytes(ocm_wr_bytes),
.prt_ack(ocm_wr_ack)
);
processing_system7_bfm_v2_0_5_arb_wr ddr_gp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_gp0),
.qos2(w_qos_gp1),
.prt_dv1(wr_dv_ddr_gp0),
.prt_dv2(wr_dv_ddr_gp1),
.prt_data1(wr_data_gp0),
.prt_data2(wr_data_gp1),
.prt_addr1(wr_addr_gp0),
.prt_addr2(wr_addr_gp1),
.prt_bytes1(wr_bytes_gp0),
.prt_bytes2(wr_bytes_gp1),
.prt_ack1(wr_ack_ddr_gp0),
.prt_ack2(wr_ack_ddr_gp1),
.prt_req(ddr_wr_dv),
.prt_qos(ddr_wr_qos),
.prt_data(ddr_wr_data),
.prt_addr(ddr_wr_addr),
.prt_bytes(ddr_wr_bytes),
.prt_ack(ddr_wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd ocm_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_ocm_gp0),
.prt_req2(rd_req_ocm_gp1),
.prt_data1(rd_data_ocm_gp0),
.prt_data2(rd_data_ocm_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_ocm_gp0),
.prt_dv2(rd_dv_ocm_gp1),
.prt_req(ocm_rd_req),
.prt_qos(ocm_rd_qos),
.prt_data(ocm_rd_data),
.prt_addr(ocm_rd_addr),
.prt_bytes(ocm_rd_bytes),
.prt_dv(ocm_rd_dv)
);
processing_system7_bfm_v2_0_5_arb_rd ddr_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_ddr_gp0),
.prt_req2(rd_req_ddr_gp1),
.prt_data1(rd_data_ddr_gp0),
.prt_data2(rd_data_ddr_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_ddr_gp0),
.prt_dv2(rd_dv_ddr_gp1),
.prt_req(ddr_rd_req),
.prt_qos(ddr_rd_qos),
.prt_data(ddr_rd_data),
.prt_addr(ddr_rd_addr),
.prt_bytes(ddr_rd_bytes),
.prt_dv(ddr_rd_dv)
);
processing_system7_bfm_v2_0_5_arb_rd reg_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_reg_gp0),
.prt_req2(rd_req_reg_gp1),
.prt_data1(rd_data_reg_gp0),
.prt_data2(rd_data_reg_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_reg_gp0),
.prt_dv2(rd_dv_reg_gp1),
.prt_req(reg_rd_req),
.prt_qos(reg_rd_qos),
.prt_data(reg_rd_data),
.prt_addr(reg_rd_addr),
.prt_bytes(reg_rd_bytes),
.prt_dv(reg_rd_dv)
);
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_ln1px_s5 (
enable, resetn,
clock,
dataa,
result);
input enable, resetn;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_ln1px_s5 inst ( .clk(clock),
.areset(1'b0),
.en(enable),
.a(dataa),
.q(sub_wire0));
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_b2s_b_channel.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_b_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk,
input wire reset,
// AXI signals
output wire [C_ID_WIDTH-1:0] s_bid,
output wire [1:0] s_bresp,
output wire s_bvalid,
input wire s_bready,
input wire [1:0] m_bresp,
input wire m_bvalid,
output wire m_bready,
// Signals to/from the axi_protocol_converter_v2_1_b2s_aw_channel modules
input wire b_push,
input wire [C_ID_WIDTH-1:0] b_awid,
input wire [7:0] b_awlen,
input wire b_resp_rdy,
output wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// AXI protocol responses:
localparam [1:0] LP_RESP_OKAY = 2'b00;
localparam [1:0] LP_RESP_EXOKAY = 2'b01;
localparam [1:0] LP_RESP_SLVERROR = 2'b10;
localparam [1:0] LP_RESP_DECERR = 2'b11;
// FIFO settings
localparam P_WIDTH = C_ID_WIDTH + 8;
localparam P_DEPTH = 4;
localparam P_AWIDTH = 2;
localparam P_RWIDTH = 2;
localparam P_RDEPTH = 4;
localparam P_RAWIDTH = 2;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
reg bvalid_i;
wire [C_ID_WIDTH-1:0] bid_i;
wire shandshake;
reg shandshake_r;
wire mhandshake;
reg mhandshake_r;
wire b_empty;
wire bresp_full;
wire bresp_empty;
wire [7:0] b_awlen_i;
reg [7:0] bresp_cnt;
reg [1:0] s_bresp_acc;
wire [1:0] s_bresp_acc_r;
reg [1:0] s_bresp_i;
wire need_to_update_bresp;
wire bresp_push;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// assign AXI outputs
assign s_bid = bid_i;
assign s_bresp = s_bresp_acc_r;
assign s_bvalid = bvalid_i;
assign shandshake = s_bvalid & s_bready;
assign mhandshake = m_bvalid & m_bready;
always @(posedge clk) begin
if (reset | shandshake) begin
bvalid_i <= 1'b0;
end else if (~b_empty & ~shandshake_r & ~bresp_empty) begin
bvalid_i <= 1'b1;
end
end
always @(posedge clk) begin
shandshake_r <= shandshake;
mhandshake_r <= mhandshake;
end
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
bid_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( b_push ) ,
.rd_en ( shandshake_r ) ,
.din ( {b_awid, b_awlen} ) ,
.dout ( {bid_i, b_awlen_i}) ,
.a_full ( ) ,
.full ( b_full ) ,
.a_empty ( ) ,
.empty ( b_empty )
);
assign m_bready = ~mhandshake_r & bresp_empty;
/////////////////////////////////////////////////////////////////////////////
// Update if more critical.
assign need_to_update_bresp = ( m_bresp > s_bresp_acc );
// Select accumultated or direct depending on setting.
always @( * ) begin
if ( need_to_update_bresp ) begin
s_bresp_i = m_bresp;
end else begin
s_bresp_i = s_bresp_acc;
end
end
/////////////////////////////////////////////////////////////////////////////
// Accumulate MI-side BRESP.
always @ (posedge clk) begin
if (reset | bresp_push ) begin
s_bresp_acc <= LP_RESP_OKAY;
end else if ( mhandshake ) begin
s_bresp_acc <= s_bresp_i;
end
end
assign bresp_push = ( mhandshake_r ) & (bresp_cnt == b_awlen_i) & ~b_empty;
always @ (posedge clk) begin
if (reset | bresp_push ) begin
bresp_cnt <= 8'h00;
end else if ( mhandshake_r ) begin
bresp_cnt <= bresp_cnt + 1'b1;
end
end
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_RWIDTH),
.C_AWIDTH (P_RAWIDTH),
.C_DEPTH (P_RDEPTH)
)
bresp_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( bresp_push ) ,
.rd_en ( shandshake_r ) ,
.din ( s_bresp_acc ) ,
.dout ( s_bresp_acc_r) ,
.a_full ( ) ,
.full ( bresp_full ) ,
.a_empty ( ) ,
.empty ( bresp_empty )
);
endmodule
`default_nettype wire
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module hshrink(
input [3:0] SHRINK, // Shrink value
input CK, L,
output OUTA, OUTB
);
wire [3:0] nSHRINK;
wire [3:0] U193_REG;
wire [3:0] T196_REG;
wire [3:0] U243_REG;
wire [3:0] U226_REG;
wire [3:0] U193_P;
wire [3:0] T196_P;
wire [3:0] U243_P;
wire [3:0] U226_P;
assign nSHRINK[3:0] = ~SHRINK[3:0];
// Lookup
assign U193_P[0] = ~&{nSHRINK[3:2]};
assign U193_P[1] = ~&{nSHRINK[3:1]};
assign U193_P[2] = ~&{nSHRINK[3], ~&{SHRINK[2:1]}};
assign U193_P[3] = 1'b1;
assign T196_P[0] = ~|{&{SHRINK[2], ~|{SHRINK[1:0], SHRINK[3]}}, ~|{SHRINK[3:2]}};
assign T196_P[1] = ~&{nSHRINK[3:0]};
assign T196_P[2] = ~&{~&{SHRINK[1:0]}, ~|{SHRINK[3:2]}};
assign T196_P[3] = ~&{nSHRINK[3], ~&{SHRINK[2:0]}};
assign U243_P[0] = ~|{nSHRINK[3], ~|{SHRINK[2:1]}};
assign U243_P[1] = ~|{nSHRINK[3:2]};
assign U243_P[2] = ~|{nSHRINK[3:1]};
assign U243_P[3] = SHRINK[3];
assign U226_P[0] = ~&{~&{SHRINK[1:0], nSHRINK[2], SHRINK[3]}, ~&{SHRINK[3:2]}};
assign U226_P[1] = &{SHRINK[3:0]};
assign U226_P[2] = ~|{nSHRINK[3], ~|{SHRINK[2:0]}};
assign U226_P[3] = ~|{~&{SHRINK[3:2]}, ~|{SHRINK[1:0]}};
// Shift registers
FS2 U193(CK, U193_P, 1'b1, ~L, U193_REG);
BD3 T193A(U193_REG[3], T193A_OUT);
FS2 T196(CK, T196_P, T193A_OUT, ~L, T196_REG);
FS2 U243(CK, U243_P, 1'b1, ~L, U243_REG);
BD3 U258A(U243_REG[3], U258A_OUT);
FS2 U226(CK, U226_P, U258A_OUT, ~L, U226_REG);
assign OUTA = T196_REG[3];
assign OUTB = U226_REG[3];
/*always@(*)
begin
case (SHRINK)
4'h0: BITMAP <= 16'b0000000010000000;
4'h1: BITMAP <= 16'b0000100010000000;
4'h2: BITMAP <= 16'b0000100010001000;
4'h3: BITMAP <= 16'b0010100010001000;
4'h4: BITMAP <= 16'b0010100010001010;
4'h5: BITMAP <= 16'b0010101010001010;
4'h6: BITMAP <= 16'b0010101010101010;
4'h7: BITMAP <= 16'b1010101010101010;
4'h8: BITMAP <= 16'b1010101011101010;
4'h9: BITMAP <= 16'b1011101011101010;
4'hA: BITMAP <= 16'b1011101011101011;
4'hB: BITMAP <= 16'b1011101111101011;
4'hC: BITMAP <= 16'b1011101111101111;
4'hD: BITMAP <= 16'b1111101111101111;
4'hE: BITMAP <= 16'b1111101111111111;
4'hF: BITMAP <= 16'b1111111111111111;
endcase
end*/
endmodule
|
// Copyright (c) 2015 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test writing files using std.textio library.
module vhdl_textio_write_test;
reg write;
vhdl_textio_write dut(write);
initial begin
// this test is later verified by vhdl_read_textio
$display("PASSED");
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// A test case for struct signal bit selection.
//
// This test is to check that bit selection of multi-dimensional signal inside
// of a packed struct works. Currently +: and -: blow up with packed structs.
//
// This file ONLY is placed into the Public Domain, for any use, without
// warranty, 2013 by Jie Xu.
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
typedef struct packed {
logic [15:0] channel;
logic [15:0] others;
} buss_t;
buss_t b;
reg [7:0] a;
reg [7:0] c;
reg [7:0] d;
union packed {
logic [31:0] [7:0] idx;
struct packed {
logic [15:0] z, y, x;
logic [25:0] [7:0] r;
} nam;
} gpr;
reg [14:0] gpr_a;
initial begin
b = {16'h8765,16'h4321};
a = b[19:12]; // This works
c = b[8+:8]; // This fails
d = b[11-:8]; // This fails
`checkh(a, 8'h54);
`checkh(c, 8'h43);
`checkh(d, 8'h32);
gpr = 256'h12346789_abcdef12_3456789a_bcdef123_456789ab_cdef1234_56789abc_def12345;
`checkh (gpr[255:255-14], 15'h091a);
gpr_a = gpr.nam.z[15:1];
`checkh (gpr_a, 15'h091a);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
`timescale 1 ns / 1 ns
module tb_monitor;
parameter tck = 10;
reg sys_clk, sys_rst;
reg wb_we_i, wb_stb_i, wb_cyc_i;
reg [31:0] wb_adr_i;
reg [3:0] wb_sel_i;
reg [31:0] wb_dat_i;
wire wb_ack_o;
wire [31:0] wb_dat_o;
reg dat;
monitor dut(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.write_lock(1'b1),
.wb_stb_i(wb_stb_i),
.wb_cyc_i(wb_cyc_i),
.wb_ack_o(wb_ack_o),
.wb_we_i(wb_we_i),
.wb_adr_i(wb_adr_i),
.wb_sel_i(wb_sel_i),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o)
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
task wbwrite;
input [31:0] address;
input [31:0] data;
integer i;
begin
wb_adr_i = address;
wb_dat_i = data;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b1;
i = 0;
while(~wb_ack_o) begin
i = i+1;
waitclock;
end
waitclock;
$display("WB Write: %x=%x acked in %d clocks", address, data, i);
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
task wbread;
input [31:0] address;
integer i;
begin
wb_adr_i = address;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b0;
i = 0;
while(~wb_ack_o) begin
i = i+1;
waitclock;
end
$display("WB Read : %x=%x acked in %d clocks", address, wb_dat_o, i);
waitclock;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
/* clock */
initial sys_clk <= 0;
always #(tck/2) sys_clk <= ~sys_clk;
initial begin
$dumpfile("monitor.vcd");
$dumpvars(-1, dut);
/* Reset / Initialize our logic */
sys_rst = 1'b1;
wb_adr_i = 32'd0;
wb_dat_i = 32'd0;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
wb_sel_i = 4'b1111;
waitclock;
sys_rst = 1'b0;
waitclock;
$display("Reading ROM");
wbread(32'h00000000);
wbread(32'h00000004);
wbread(32'h00000008);
wbread(32'h00000010);
$display("Reading and writing ROM/RAM");
wbread(32'h00000600);
wbwrite(32'h00000000, 32'h12345678);
wbwrite(32'h00000600, 32'h12345678);
wbread(32'h00000000);
wbread(32'h00000600);
$display("Test byte enables");
wbwrite(32'h00000600, 32'h00000000);
wbread(32'h00000600);
wb_sel_i = 4'b0001;
wbwrite(32'h00000600, 32'haa55aa55);
wbread(32'h00000600);
wb_sel_i = 4'b0100;
wbwrite(32'h00000600, 32'haa55aa55);
wbread(32'h00000600);
wb_sel_i = 4'b0010;
wbwrite(32'h00000600, 32'haa55aa55);
wbread(32'h00000600);
wb_sel_i = 4'b1000;
wbwrite(32'h00000600, 32'haa55aa55);
wbread(32'h00000600);
$finish;
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized AND with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_carry_and #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = CIN & S;
end else begin : USE_FPGA
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (1'b0),
.S (S)
);
end
endgenerate
endmodule
|
/*
* Copyright (c) 2000 Guy Hutchison ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module pullupdown;
// declare several bussed wires
wire pull_up_1, pull_down_1;
wire [7:0] pull_up_8, pull_down_8;
reg error;
// assign pullups to each wire
pullup (pull_up_1);
pulldown (pull_down_1);
pullup u8 [7:0] (pull_up_8);
pulldown d8 [7:0] (pull_down_8);
// create tristate drivers for each wire
reg driver_1;
reg [7:0] driver_8;
assign pull_up_1 = driver_1;
assign pull_down_1 = driver_1;
assign pull_up_8 = driver_8;
assign pull_down_8 = driver_8;
initial
begin : test_block
integer i;
// turn off all drivers
driver_1 = 1'bz;
driver_8 = 8'bz;
error = 0;
#1;
// check default values
if ((pull_up_1 !== 1'b1) || (pull_down_1 !== 1'b0) ||
(pull_up_8 !== 8'hFF) || (pull_down_8 !== 8'h00)) begin
$display("driver_8=%b, pull_up_8=%b, pull_down_8=%b",
driver_8, pull_up_8, pull_down_8);
$display("driver_1=%b, pull_up_1=%b, pull_down_1=%b",
driver_1, pull_up_1, pull_down_1);
error = 1;
end
for (i=0; i<256; i=i+1)
begin
driver_1 = ~driver_1;
driver_8 = i;
$display ("Testing drivers with value %h", driver_8);
#1;
check_drivers;
#10;
end
if (error)
$display ("FAILED - pullupdown ");
else $display ("PASSED");
end // block: test_block
task check_drivers;
begin
if ((pull_up_1 !== driver_1) || (pull_down_1 !== driver_1) ||
(pull_up_8 !== driver_8) || (pull_down_8 !== driver_8)) begin
$display("driver_8=%b, pull_up_8=%b, pull_down_8=%b",
driver_8, pull_up_8, pull_down_8);
$display("driver_1=%b, pull_up_1=%b, pull_down_1=%b",
driver_1, pull_up_1, pull_down_1);
error = 1;
end
end
endtask // check_drivers
endmodule // pullupdown
|
/*
** -----------------------------------------------------------------------------**
** huffman333.v
**
** Huffman encoder for JPEG compressorrdy
**
** Copyright (C) 2002-2004 Elphelk, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X333
** X333 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
// 01/22/2004 - extended flush until ready (modified stuffer.v too)
module huffman (pclk, // half frequency, sync to incoming data
clk, // pixel clock
en, // enable (0 resets) sync to pclk
// cwr, // CPU WR global clock
twe, // enable write to a table - now the following will be valid ant negedge clk
ta, // [8:0] table address
tdi, // [15:0] table data in
// readback, // [23:0] readback data
di, // [15:0] specially RLL prepared 16-bit data (to FIFO) (sync to pclk)
ds, // di valid strobe (sync to pclk)
rdy, // receiver (bit stuffer) is ready to accept data
do, // [15:0] output data
dl, // [3:0] data length (4'h0 is 'h16)
dv, // output data valid
flush, // last block done - flush the rest bits
last_block,
test_lbw,
gotLastBlock
);
input pclk;
input clk;
input en;
// input cwr;
input twe;
input [ 8:0] ta;
input [15:0] tdi;
// output [23:0] readback; // readback data
input [15:0] di;
input ds;
input rdy;
output [15:0] do;
output [ 3:0] dl;
output dv;
output flush;
output last_block;
output test_lbw;
output gotLastBlock;
reg test_lbw;
wire [19:0] tables_out;
wire [15:0] hcode; // table output huffman code (1..16 bits)
wire [ 3:0] hlen; // table - code length only 4 LSBs are used
wire [11:0] unused; // SuppressThisWarning Veditor UNUSED
reg [ 7:0] haddr_r; // index in huffman table
wire [ 7:0] haddr_next;
wire [ 8:0] haddr; // index in huffman table (after latches)
wire [15:0] fifo_o;
reg stuffer_was_rdy;
wire tables_re;
wire read_next; // assigned depending on steps (each other cycle for normal codes, each for special 00/F0
reg [5:0] steps;
// first stage registers
reg [5:0] rll; // 2 MSBs - counter to send "f0" codes
// replacing SRL16 with FD as SRL has longer output delay from clock
reg [3:0] rll1;
reg [3:0] rll2;
reg typeDC;
reg typeAC;
reg [11:0] sval; // signed input value
wire [1:0] code_typ0; // valid at steps[0]
reg tbsel_YC0; // valid at steps[0] - 0 -Y table, 1 - CbCr
reg [1:0] code_typ1;
reg [1:0] code_typ2;
reg code_typ3;
reg code_typ4;
reg tbsel_YC1;
reg tbsel_YC2;
reg tbsel_YC3;
reg last_block; //
reg [15:0] out_bits; // bits to send
reg [3:0] out_len; // length of bits to send (4'h0 means 16)
wire fifo_or_full; // fifo output register full read_next
wire will_read;
wire [10:0] var_do;
wire [3:0] var_dl;
wire [3:0] var_dl_late;
//wire dv;
reg dv;
reg dv0;
//reg dv_d; // dv0 delayed
//reg [15:0] out_bits_d; // bits to send (delayed)
//reg [3:0] out_len_d; // length of bits to send (4'h0 means 16) (delayed)
reg flush;
//wire [23:0] readback; // readback data
reg eob;
wire gotDC;
wire gotAC;
wire gotRLL;
wire gotEOB;
wire gotLastBlock;
wire gotLastWord;
wire gotColor;
wire want_read; // as will_read, but w/o fifo status
reg ready_to_flush; // read the last data from fifo
reg en2x; // en sync to clk;
reg [15:0] do;
reg [ 3:0] dl;
wire pre_dv;
wire [15:0] pre_bits;
wire [ 3:0] pre_len;
reg twe_d; // table write enable (twe) delayued by 1 clock
always @ (negedge clk) en2x <= en;
assign gotDC= fifo_o[15] && fifo_o[14];
assign gotAC= fifo_o[15] && !fifo_o[14];
assign gotRLL= !fifo_o[15] && !fifo_o[12];
assign gotEOB= !fifo_o[15] && fifo_o[12];
assign gotLastBlock= fifo_o[15] && fifo_o[14] && fifo_o[12];
assign gotLastWord= !fifo_o[14] && fifo_o[12]; // (AC or RLL) and last bit set
assign gotColor= fifo_o[13];
always @(negedge clk) stuffer_was_rdy <= !en2x || rdy; // stuffer ready shoud be on if !en (move to register?)for now]
wire stuffer_was_rdy_early;
wire want_read_early;
LD i_stuffer_was_rdy_early (.Q(stuffer_was_rdy_early),.G(clk),.D(!en2x || rdy));
LD i_tables_re (.Q(tables_re),.G(clk),.D(en2x && rdy));
assign read_next= en2x && ((!steps[0] && !rll[5]) || eob ) && fifo_or_full; // fifo will never have data after the last block...
assign will_read= stuffer_was_rdy && fifo_or_full && en2x && ((!steps[0] && !rll[5]) || eob ); // fifo will never have data after the last block...
assign want_read= stuffer_was_rdy && ((!steps[0] && !rll[5]) || eob ); // for FIFO
assign want_read_early= stuffer_was_rdy_early && ((!steps[0] && !rll[5]) || eob ); // for FIFO
always @ (negedge clk) if (stuffer_was_rdy) begin
eob <= read_next && gotEOB;// will be 1 only during step[0]
if (!en2x) steps[5:0] <= 'b0;
else steps[5:0] <= { steps[4] && code_typ4, // will be skipped for codes 00/F0
steps[3:0],
(read_next && !(gotRLL && (fifo_o[5:4]==2'b00))) || rll[5] }; // will not start if it was <16, waiting for AC
end
always @ (negedge clk) begin
last_block <= en2x && (last_block?(!flush):(stuffer_was_rdy && will_read && gotLastBlock));
ready_to_flush <= en2x && (ready_to_flush?(!flush):(stuffer_was_rdy && last_block && will_read && gotLastWord));
test_lbw <= en2x && last_block && gotLastWord;
// did not work if flush was just after not ready?
flush <= en2x &&( flush?(!rdy):(rdy && stuffer_was_rdy && ready_to_flush && !(|steps)) );
end
always @ (negedge clk) if (will_read) begin
typeDC <= gotDC;
typeAC <= gotAC;
sval[11:0] <= fifo_o[11:0];
if (gotDC) tbsel_YC0 <= gotColor;
end
always @ (negedge clk) if (stuffer_was_rdy) begin
if (!en2x || (read_next && gotAC) || (steps[0] && typeAC)) rll[5:4] <= 2'b0;
else if (read_next && gotRLL) rll[5:4] <= fifo_o[5:4];
else if (rll[5:4]!=2'b00) rll[5:4] <= rll[5:4]-1;
if (!en2x || (read_next && !gotAC && !gotRLL) || (steps[0] && typeAC)) rll[3:0] <= 4'b0;
else if (read_next && gotRLL) rll[3:0] <= fifo_o[3:0];
end
assign code_typ0={typeDC || (!eob && (rll[5:4]==2'b0)),
typeDC || (!eob && (rll[5:4]!=2'b0))};
assign haddr_next[7:0] = code_typ2[1]?
(code_typ2[0]?{var_dl[3:0],4'hf}: // DC (reusing the spare cells of the AC table)
{rll2[3:0],var_dl[3:0]}): // AC normal code
(code_typ2[0]?8'hf0: //skip 16 zeros code
8'h00); //skip to end of block code
always @ (negedge clk) if (stuffer_was_rdy && steps[2]) begin // may be just if (stuffer_was_rdy)
haddr_r[7:0] <= haddr_next[7:0];
end
LD i_haddr_7 (.Q(haddr[7]),.G(clk),.D((stuffer_was_rdy && steps[2])?haddr_next[7]:haddr_r[7]));
LD i_haddr_6 (.Q(haddr[6]),.G(clk),.D((stuffer_was_rdy && steps[2])?haddr_next[6]:haddr_r[6]));
LD i_haddr_5 (.Q(haddr[5]),.G(clk),.D((stuffer_was_rdy && steps[2])?haddr_next[5]:haddr_r[5]));
LD i_haddr_4 (.Q(haddr[4]),.G(clk),.D((stuffer_was_rdy && steps[2])?haddr_next[4]:haddr_r[4]));
LD i_haddr_3 (.Q(haddr[3]),.G(clk),.D((stuffer_was_rdy && steps[2])?haddr_next[3]:haddr_r[3]));
LD i_haddr_2 (.Q(haddr[2]),.G(clk),.D((stuffer_was_rdy && steps[2])?haddr_next[2]:haddr_r[2]));
LD i_haddr_1 (.Q(haddr[1]),.G(clk),.D((stuffer_was_rdy && steps[2])?haddr_next[1]:haddr_r[1]));
LD i_haddr_0 (.Q(haddr[0]),.G(clk),.D((stuffer_was_rdy && steps[2])?haddr_next[0]:haddr_r[0]));
//
assign pre_dv = steps[4] || (steps[5] && (var_dl_late[3:0]!=4'b0));
assign pre_bits[15:0] = steps[5]?{5'b0,var_do[10:0]}: hcode[15:0];
assign pre_len [ 3:0] = steps[5]? var_dl_late[ 3:0]: hlen [3:0];
always @ (negedge clk) if (stuffer_was_rdy) begin
dv0 <= pre_dv;
out_bits[15:0] <= pre_bits[15:0];
out_len [ 3:0] <= pre_len [ 3:0];
end
always @ (negedge clk) if (!en2x || rdy) begin
dv <= stuffer_was_rdy? pre_dv:dv0;
do[15:0] <= stuffer_was_rdy? pre_bits[15:0]:out_bits[15:0];
dl[ 3:0] <= stuffer_was_rdy? pre_len [ 3:0]:out_len [ 3:0];
end
// "Extract shift registers" in synthesis should be off! FD has lower output delay than SRL16
always @ (negedge clk) if (stuffer_was_rdy) begin
code_typ1[1:0] <= code_typ0[1:0];
code_typ2[1:0] <= code_typ1[1:0];
code_typ3 <= code_typ2[1];
code_typ4 <= code_typ3;
rll1[3:0] <= rll[3:0];
rll2[3:0] <= rll1[3:0];
tbsel_YC1 <= tbsel_YC0;
tbsel_YC2 <= tbsel_YC1;
tbsel_YC3 <= tbsel_YC2;
end
LD i_haddr_8 (.Q(haddr[8]),.G(clk),.D(stuffer_was_rdy?tbsel_YC2:tbsel_YC3));
LD_1 i_hlen3 (.Q( hlen[ 3]),.G(clk),.D(tables_out[19]));
LD_1 i_hlen2 (.Q( hlen[ 2]),.G(clk),.D(tables_out[18]));
LD_1 i_hlen1 (.Q( hlen[ 1]),.G(clk),.D(tables_out[17]));
LD_1 i_hlen0 (.Q( hlen[ 0]),.G(clk),.D(tables_out[16]));
LD_1 i_hcode15(.Q(hcode[15]),.G(clk),.D(tables_out[15]));
LD_1 i_hcode14(.Q(hcode[14]),.G(clk),.D(tables_out[14]));
LD_1 i_hcode13(.Q(hcode[13]),.G(clk),.D(tables_out[13]));
LD_1 i_hcode12(.Q(hcode[12]),.G(clk),.D(tables_out[12]));
LD_1 i_hcode11(.Q(hcode[11]),.G(clk),.D(tables_out[11]));
LD_1 i_hcode10(.Q(hcode[10]),.G(clk),.D(tables_out[10]));
LD_1 i_hcode9 (.Q(hcode[ 9]),.G(clk),.D(tables_out[ 9]));
LD_1 i_hcode8 (.Q(hcode[ 8]),.G(clk),.D(tables_out[ 8]));
LD_1 i_hcode7 (.Q(hcode[ 7]),.G(clk),.D(tables_out[ 7]));
LD_1 i_hcode6 (.Q(hcode[ 6]),.G(clk),.D(tables_out[ 6]));
LD_1 i_hcode5 (.Q(hcode[ 5]),.G(clk),.D(tables_out[ 5]));
LD_1 i_hcode4 (.Q(hcode[ 4]),.G(clk),.D(tables_out[ 4]));
LD_1 i_hcode3 (.Q(hcode[ 3]),.G(clk),.D(tables_out[ 3]));
LD_1 i_hcode2 (.Q(hcode[ 2]),.G(clk),.D(tables_out[ 2]));
LD_1 i_hcode1 (.Q(hcode[ 1]),.G(clk),.D(tables_out[ 1]));
LD_1 i_hcode0 (.Q(hcode[ 0]),.G(clk),.D(tables_out[ 0]));
huff_fifo i_huff_fifo(.pclk(pclk),
.clk(clk),
.en(en), // will reset if ==0 (sync to pclk)
.di(di[15:0]), // data in (sync to pclk)
.ds(ds), // din valid (sync to pclk)
.want_read(want_read),
.want_read_early(want_read_early),
.dav(fifo_or_full), // FIFO output register has data
.q(fifo_o[15:0])); // output data (will add extra buffering if needed)
varlen_encode i_varlen_encode(.clk(clk),
.en(stuffer_was_rdy), //will enable registers. 0 - freese
.start(steps[0]),
.d(sval[11:0]), // 12-bit signed
.l(var_dl[ 3:0]), // [3:0] code length
.l_late(var_dl_late[3:0]),
.q(var_do[10:0])); // [10:0]code
always @ (negedge clk) twe_d <= twe;
RAMB16_S18_S36 i_htab (
.DOA(), // Port A 16-bit Data Output
.DOPA(), // Port A 2-bit Parity Output
.ADDRA({ta[8:0],twe_d}), // Port A 10-bit Address Input
.CLKA(!clk), // Port A Clock
.DIA(tdi[15:0]), // Port A 16-bit Data Input
.DIPA(2'b0), // Port A 2-bit parity Input
.ENA(1'b1), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(twe | twe_d),// Port A Write Enable Input
.DOB({unused[11:0],tables_out[19:0]}), // Port B 32-bit Data Output
.DOPB(), // Port B 4-bit Parity Output
.ADDRB(haddr[8:0]), // Port B 9-bit Address Input
.CLKB(clk), // Port B Clock
.DIB(32'b0), // Port B 32-bit Data Input
.DIPB(4'b0), // Port-B 4-bit parity Input
.ENB(tables_re), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b0) // Port B Write Enable Input
);
endmodule
//used the other edge of the clk2x
module huff_fifo (pclk,
clk,
en, // will reset if ==0 (sync to pclk)
di, // data in (sync to pclk)
ds, // din valid (sync to pclk)
want_read,
want_read_early,
dav, // FIFO output register has data (fifo_or_full)
q); // output data
input pclk,clk,en,ds, want_read, want_read_early; //,got; // will_read;
input [15:0] di;
output dav;
output[15:0] q;
reg [9:0] wa;
reg [9:0] sync_wa; // delayed wa, re-calculated at output clock
reg [9:0] ra_r;
wire [9:0] ra;
wire [15:0] q;
reg load_q; // SuppressThisWarning Veditor VDT_BUG
wire [15:0] fifo_o;
reg ds1; // ds delayed by one pclk to give time to block ram to write data. Not needed likely.
reg synci;
reg [1:0] synco;
reg sync_we; // single clk period pulse for each ds@pclk
reg en2x; // en sync to clk;
reg re_r;
wire re;
reg dav; // output latch has data
reg fifo_dav; // RAM output reg has data
reg dav_and_fifo_dav;
wire ram_dav; // RAM has data inside
reg [9:0] diff_a;
wire next_re;
always @ (posedge pclk) begin // input stage, no overrun detection
if (!en) wa[9:0] <= 10'b0;
else if (ds) wa[9:0] <= wa[9:0]+1;
ds1 <= ds && en;
if (!en) synci <= 1'b0;
else if (ds1) synci <= ~synci;
end
always @ (negedge clk) begin
en2x <= en;
synco[1:0] <= {synco[0],synci};
sync_we <= en2x && (synco[0] != synco[1]);
end
assign ram_dav= sync_we || (diff_a[9:0] != 10'b0);
// assign next_re= ram_dav && (!dav || !fifo_dav || want_read);
assign next_re= ram_dav && (!dav_and_fifo_dav || want_read);
always @ (negedge clk) begin
dav <= en2x && (fifo_dav || (dav && !want_read));
fifo_dav <= en2x && (ram_dav ||(dav && fifo_dav && !want_read));
dav_and_fifo_dav <= en2x && (fifo_dav || (dav && !want_read)) && (ram_dav ||(dav && fifo_dav && !want_read)); // will optimize auto
re_r <= en2x && next_re;
if (!en2x) sync_wa[9:0] <= 10'b0;
else if (sync_we) sync_wa[9:0] <= sync_wa[9:0]+1;
if (!en2x) ra_r [9:0] <= 10'b0;
else if (next_re) ra_r [9:0] <= ra_r[9:0]+1;
if (!en2x) diff_a[9:0] <= 10'b0;
else if (sync_we && !next_re) diff_a[9:0] <= diff_a[9:0]+1;
else if (!sync_we && next_re) diff_a[9:0] <= diff_a[9:0]-1;
end
LD i_re (.Q(re),.G(clk),.D(next_re));
LD i_ra9 (.Q(ra[9]),.G(clk),.D(ra_r[9]));
LD i_ra8 (.Q(ra[8]),.G(clk),.D(ra_r[8]));
LD i_ra7 (.Q(ra[7]),.G(clk),.D(ra_r[7]));
LD i_ra6 (.Q(ra[6]),.G(clk),.D(ra_r[6]));
LD i_ra5 (.Q(ra[5]),.G(clk),.D(ra_r[5]));
LD i_ra4 (.Q(ra[4]),.G(clk),.D(ra_r[4]));
LD i_ra3 (.Q(ra[3]),.G(clk),.D(ra_r[3]));
LD i_ra2 (.Q(ra[2]),.G(clk),.D(ra_r[2]));
LD i_ra1 (.Q(ra[1]),.G(clk),.D(ra_r[1]));
LD i_ra0 (.Q(ra[0]),.G(clk),.D(ra_r[0]));
always @ (posedge clk) begin
load_q <= dav?want_read_early:re_r;
end
LD_1 i_q15 (.Q( q[15]),.G(clk),.D(load_q?fifo_o[15]:q[15]));
LD_1 i_q14 (.Q( q[14]),.G(clk),.D(load_q?fifo_o[14]:q[14]));
LD_1 i_q13 (.Q( q[13]),.G(clk),.D(load_q?fifo_o[13]:q[13]));
LD_1 i_q12 (.Q( q[12]),.G(clk),.D(load_q?fifo_o[12]:q[12]));
LD_1 i_q11 (.Q( q[11]),.G(clk),.D(load_q?fifo_o[11]:q[11]));
LD_1 i_q10 (.Q( q[10]),.G(clk),.D(load_q?fifo_o[10]:q[10]));
LD_1 i_q9 (.Q( q[ 9]),.G(clk),.D(load_q?fifo_o[ 9]:q[ 9]));
LD_1 i_q8 (.Q( q[ 8]),.G(clk),.D(load_q?fifo_o[ 8]:q[ 8]));
LD_1 i_q7 (.Q( q[ 7]),.G(clk),.D(load_q?fifo_o[ 7]:q[ 7]));
LD_1 i_q6 (.Q( q[ 6]),.G(clk),.D(load_q?fifo_o[ 6]:q[ 6]));
LD_1 i_q5 (.Q( q[ 5]),.G(clk),.D(load_q?fifo_o[ 5]:q[ 5]));
LD_1 i_q4 (.Q( q[ 4]),.G(clk),.D(load_q?fifo_o[ 4]:q[ 4]));
LD_1 i_q3 (.Q( q[ 3]),.G(clk),.D(load_q?fifo_o[ 3]:q[ 3]));
LD_1 i_q2 (.Q( q[ 2]),.G(clk),.D(load_q?fifo_o[ 2]:q[ 2]));
LD_1 i_q1 (.Q( q[ 1]),.G(clk),.D(load_q?fifo_o[ 1]:q[ 1]));
LD_1 i_q0 (.Q( q[ 0]),.G(clk),.D(load_q?fifo_o[ 0]:q[ 0]));
/*
RAMB4_S16_S16 i_fifo (.DOB(fifo_o[15:0]),
.ADDRA(wa[7:0]),
.CLKA(pclk),
.DIA(di[15:0]),
.ENA(ds),.RSTA(1'b0),.WEA(1'b1),
.ADDRB(ra[7:0]),
.CLKB(clk),
.DIB(16'b0),.ENB(re),.RSTB(1'b0),.WEB(1'b0));
*/
RAMB16_S18_S18 i_fifo (
.DOA(), // Port A 16-bit Data Output
.DOPA(), // Port A 2-bit Parity Output
.ADDRA(wa[9:0]), // Port A 10-bit Address Input
.CLKA(pclk), // Port A Clock
.DIA(di[15:0]), // Port A 16-bit Data Input
.DIPA(2'b0), // Port A 2-bit parity Input
.ENA(ds), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(1'b1), // Port A Write Enable Input
.DOB(fifo_o[15:0]),// Port B 16-bit Data Output
.DOPB(), // Port B 2-bit Parity Output
.ADDRB(ra[9:0]), // Port B 10-bit Address Input
.CLKB(clk), // Port B Clock
.DIB(16'b0), // Port B 16-bit Data Input
.DIPB(2'b0), // Port-B 2-bit parity Input
.ENB(re), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b0) // Port B Write Enable Input
);
endmodule
// Encoder will work 2 cycles/"normal" word, 1 cycle for codes "00" and "f0",
// only magnitude output is needed ASAP (2 cycles, the value out should be
// valid on the 5-th cycle - it will latency 4 cycles run each other cycle
// I'll make a shortcut - all codes processed in 2 cycles.
module varlen_encode (clk,
en, // will enable registers. 0 - "freese" at once
start, // (not faster than each other cycle)
d, // 12-bit signed
l, // [3:0] code length
l_late,// delayed l (sync to q)
q); // [10:0]code
input clk, en,start;
input [11:0] d;
output [ 3:0] l;
output [ 3:0] l_late;
output [10:0] q;
reg [11:0] d1;
reg [10:0] q,q0;
reg [ 3:0] l,l_late;
reg [2:0] cycles;
wire this0= |d1[ 3:0];
wire this1= |d1[ 7:4];
wire this2= |d1[10:8];
wire [1:0] codel0={|d1[ 3: 2],d1[ 3] || (d1[ 1] & ~d1[ 2])};
wire [1:0] codel1={|d1[ 7: 6],d1[ 7] || (d1[ 5] & ~d1[ 6])};
wire [1:0] codel2={|d1[ 10], (d1[ 9] & ~d1[10])};
wire [3:0] codel= this2? {2'b10,codel2[1:0]} :
(this1? {2'b01,codel1[1:0]} :
(this0? {2'b00,codel0[1:0]} : 4'b1111)); // after +1 will be 0;
always @ (negedge clk) if (en) begin
cycles[2:0] <= {cycles[1:0],start};
end
always @ (negedge clk) if (en && start) begin
d1[ 11] <= d[11];
d1[10:0] <= d[11]?-d[10:0]:d[10:0];
end
always @ (negedge clk) if (en & cycles[0]) begin
q0[10:0] <= d1[11]?~d1[10:0]:d1[10:0];
l <= codel[3:0]+1; // needed only ASAP, valid only 2 cycles after start
end
always @ (negedge clk) if (en & cycles[2]) begin
q[10:0] <= q0[10:0];
l_late[3:0] <= l[3:0];
end
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 08/13/2010
Version 1.2
This block is responsible determine the appropriate burst count based on the
master length register as well as the buffer watermark and eop/early termination
conditions.
Within this block is a burst counter which is used to control when the next burst
is started. This down counter is loaded with whatever burst count is presented
to the fabric and counts down when waitrequest is deasserted. When it reaches 1
it can either start another burst or reach 0. When the counter reaches 0 this is
considered the idle state which can occur if there is not enough data buffered to
start another burst.
During write bursts the address and burst count must be held for all the beats.
This block will register the address and burst count to keep these signals
held constant to the fabric. This block will not begin a burst until enough
data has been buffered to start the burst so it will assert the stall signal
to keep the write master from advancing to the next word (just like waitrequest)
and will filter the write signal accordingly.
Revision History:
1.0 Initial version
1.1 Added sw_stop and stopped so that the write master will not be
stopped in the middle of a burst write transaction.
1.2 Added the sink ready and valid signals to this block and qualified the
eop signal with them.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module write_burst_control (
clk,
reset,
sw_reset,
sw_stop,
length,
eop_enabled,
eop,
ready,
valid,
early_termination,
address_in,
write_in,
max_burst_count,
write_fifo_used,
waitrequest,
short_first_access_enable,
short_last_access_enable,
short_first_and_last_access_enable,
address_out,
write_out,
burst_count,
stall,
reset_taken,
stopped
);
parameter BURST_ENABLE = 1; // set to 0 to hardwire the address and write signals straight out
parameter BURST_COUNT_WIDTH = 3;
parameter WORD_SIZE = 4;
parameter WORD_SIZE_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter LENGTH_WIDTH = 32;
parameter WRITE_FIFO_USED_WIDTH = 5;
parameter BURST_WRAPPING_SUPPORT = 1; // set 1 for on, set 0 for off. This parameter can't be enabled when the master supports programmable bursting.
localparam BURST_OFFSET_WIDTH = (BURST_COUNT_WIDTH == 1)? 1: (BURST_COUNT_WIDTH-1);
input clk;
input reset;
input sw_reset;
input sw_stop;
input [LENGTH_WIDTH-1:0] length;
input eop_enabled;
input eop;
input ready;
input valid;
input early_termination;
input [ADDRESS_WIDTH-1:0] address_in;
input write_in;
input [BURST_COUNT_WIDTH-1:0] max_burst_count; // will be either a hardcoded input or programmable
input [WRITE_FIFO_USED_WIDTH:0] write_fifo_used; // using the fifo full MSB as well
input waitrequest; // this needs to be the waitrequest from the fabric and not the byte enable generator since partial transfers count as burst beats
input short_first_access_enable;
input short_last_access_enable;
input short_first_and_last_access_enable;
output wire [ADDRESS_WIDTH-1:0] address_out;
output wire write_out;
output wire [BURST_COUNT_WIDTH-1:0] burst_count;
output wire stall; // need to issue a stall if there isn't enough data buffered to start a burst
output wire reset_taken; // if a reset occurs in the middle of a burst larger than 1 then the write master needs to know that the burst hasn't completed yet
output wire stopped; // if a stop occurs in the middle of a burst larger than 1 then the write master needs to know that the burst hasn't completed yet
reg [ADDRESS_WIDTH-1:0] address_d1;
reg [BURST_COUNT_WIDTH-1:0] burst_counter; // interal statemachine register
wire idle_state;
wire decrement_burst_counter;
wire ready_during_idle_state; // when there is enough data buffered to start up the burst counter state machine again
wire ready_for_quick_burst; // when there is enough data bufferred to start another burst immediately
wire burst_begin_from_idle_state;
wire burst_begin_quickly; // start another burst immediately after the previous burst completes
wire burst_begin;
wire burst_of_one_enable; // asserted when partial word accesses are occuring or the last early termination word is being written out
wire [BURST_COUNT_WIDTH-1:0] short_length_burst;
wire [BURST_COUNT_WIDTH-1:0] short_packet_burst;
wire short_length_burst_enable;
wire short_early_termination_burst_enable;
wire short_packet_burst_enable;
wire [3:0] mux_select;
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count;
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count_d1;
reg packet_complete;
wire [BURST_OFFSET_WIDTH-1:0] burst_offset;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
packet_complete <= 0;
end
else
begin
if ((packet_complete == 1) & (write_fifo_used == 0))
begin
packet_complete <= 0;
end
else if ((eop == 1) & (ready == 1) & (valid == 1))
begin
packet_complete <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
address_d1 <= 0;
end
else if (burst_begin == 1)
begin
address_d1 <= (burst_begin_quickly == 1)? (address_in + WORD_SIZE) : address_in;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
burst_counter <= 0;
end
else
if ((burst_begin == 1) & (sw_reset == 0) & (sw_stop == 0)) // for reset and stop we need to let the burst complete so the fabric doesn't lock up
begin
burst_counter <= internal_burst_count;
end
else if (decrement_burst_counter == 1)
begin
burst_counter <= burst_counter - 1'b1;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
internal_burst_count_d1 <= 0;
end
else if (burst_begin == 1)
begin
internal_burst_count_d1 <= internal_burst_count;
end
end
// state machine status and control
assign idle_state = (burst_counter == 0); // any time idle_state is set then there is no burst underway
assign decrement_burst_counter = (idle_state == 0) & (waitrequest == 0);
// control for all the various cases that a burst of one beat needs to be posted
assign burst_offset = address_in[BURST_OFFSET_WIDTH+WORD_SIZE_LOG2-1:WORD_SIZE_LOG2];
assign burst_of_one_enable = (short_first_access_enable == 1) | (short_last_access_enable == 1) | (short_first_and_last_access_enable == 1) | (early_termination == 1) |
((BURST_WRAPPING_SUPPORT == 1) & (idle_state == 1) & (burst_offset != 0)) | // need to make sure bursts start on burst boundaries
((BURST_WRAPPING_SUPPORT == 1) & (idle_state == 0) & (burst_offset != (max_burst_count - 1))); // need to make sure bursts start on burst boundaries
assign short_length_burst_enable = ((length >> WORD_SIZE_LOG2) < max_burst_count) & (eop_enabled == 0) & (burst_of_one_enable == 0);
assign short_early_termination_burst_enable = ((length >> WORD_SIZE_LOG2) < max_burst_count) & (eop_enabled == 1) & (burst_of_one_enable == 0); // trim back the burst count regardless if there is enough data buffered for a full burst
assign short_packet_burst_enable = (short_early_termination_burst_enable == 0) & (eop_enabled == 1) & (packet_complete == 1) & (write_fifo_used < max_burst_count) & (burst_of_one_enable == 0);
// various burst amounts that are not the max burst count or 1 that feed the internal_burst_count mux. short_length_burst is used when short_length_burst_enable or short_early_termination_burst_enable is asserted.
assign short_length_burst = (length >> WORD_SIZE_LOG2) & {(BURST_COUNT_WIDTH-1){1'b1}};
assign short_packet_burst = (write_fifo_used & {(BURST_COUNT_WIDTH-1){1'b1}});
// since the write master may not have enough data buffered in the FIFO to start a burst the FIFO fill level must be checked before starting another burst
assign ready_during_idle_state = (burst_of_one_enable == 1) | // burst of one is only enabled when there is data in the write fifo so write_fifo_used doesn't need to be checked in this case
((write_fifo_used >= short_length_burst) & (short_length_burst_enable == 1)) |
((write_fifo_used >= short_length_burst) & (short_early_termination_burst_enable == 1)) |
((write_fifo_used >= short_packet_burst) & (short_packet_burst_enable == 1)) |
(write_fifo_used >= max_burst_count);
// same as ready_during_idle_state only we need to make sure there is more data in the fifo than the burst being posted (since the FIFO is in the middle of being popped)
assign ready_for_quick_burst = (length >= (max_burst_count << WORD_SIZE_LOG2)) & (burst_of_one_enable == 0) & // address and length lags by one clock cycle so this will let the state machine catch up
( ((write_fifo_used > short_length_burst) & (short_length_burst_enable == 1)) |
((write_fifo_used > short_length_burst) & (short_early_termination_burst_enable == 1)) |
((write_fifo_used > short_packet_burst) & (short_packet_burst_enable == 1)) |
(write_fifo_used > max_burst_count) );
// burst begin signals used to start up the burst counter state machine
assign burst_begin_from_idle_state = (write_in == 1) & (idle_state == 1) & (ready_during_idle_state == 1); // start the state machine up again
assign burst_begin_quickly = (write_in == 1) & (burst_counter == 1) & (waitrequest == 0) & (ready_for_quick_burst == 1); // enough data is buffered to start another burst immediately after the current burst
assign burst_begin = (burst_begin_quickly == 1) | (burst_begin_from_idle_state == 1);
assign mux_select = {short_packet_burst_enable, short_early_termination_burst_enable, short_length_burst_enable, burst_of_one_enable};
// one-hot mux that selects the appropriate burst count to present to the fabric
always @ (short_length_burst or short_packet_burst or max_burst_count or mux_select)
begin
case (mux_select)
4'b0001 : internal_burst_count = 1;
4'b0010 : internal_burst_count = short_length_burst;
4'b0100 : internal_burst_count = short_length_burst;
4'b1000 : internal_burst_count = short_packet_burst;
default : internal_burst_count = max_burst_count;
endcase
end
generate
if (BURST_ENABLE == 1)
begin
// outputs that need to be held constant throughout the entire burst transaction
assign address_out = address_d1;
assign burst_count = internal_burst_count_d1;
assign write_out = (idle_state == 0);
assign stall = (idle_state == 1);
assign reset_taken = (sw_reset == 1) & (idle_state == 1); // for bursts of 1 the write master logic will handle the correct reset timing
assign stopped = (sw_stop == 1) & (idle_state == 1); // for bursts of 1 the write master logic will handle the correct stop timing
end
else
begin
assign address_out = address_in;
assign burst_count = 1; // this will be stubbed at the top level
assign write_out = write_in;
assign stall = 0;
assign reset_taken = sw_reset;
assign stopped = sw_stop;
end
endgenerate
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// This module defines the LDEXP function, which multiplies a floating point number by 2^(shift_in).
// The result is a valid floating point number within single-precision range, +/- INF or 0.
// If a denormalized number is supplied as input, the result will be zero (until we add denormalized
// number support).
//
module acl_fp_ldexp(clock, resetn, dataa, datab, enable, result);
input clock, resetn;
input [31:0] dataa;
input [31:0] datab;
input enable;
output [31:0] result;
// Cycle 1: Test inputs and compute resulting exponents.
wire [7:0] exponent_in = dataa[30:23];
wire [22:0] mantissa_in = dataa[22:0];
wire sign_in = dataa[31];
wire [31:0] shift_in = datab;
wire [31:0] intermediate_exp = shift_in + exponent_in;
reg [7:0] exp_stage_1;
reg [22:0] man_stage_1;
reg sign_stage_1;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
exp_stage_1 <= 8'dx;
man_stage_1 <= 23'dx;
sign_stage_1 <= 1'bx;
end
else if (enable)
begin
sign_stage_1 <= sign_in;
if (exponent_in == 8'hff)
begin
// NaN / Inf input, so produce an NaN / Inf output.
man_stage_1 <= mantissa_in;
exp_stage_1 <= exponent_in;
end
else
if (intermediate_exp[31] | (exponent_in == 8'd0))
begin
man_stage_1 <= 23'd0;
exp_stage_1 <= 8'd0;
end
else if ({1'b0, intermediate_exp[30:0]} >= 255)
begin
// infinity
man_stage_1 <= 23'd0;
exp_stage_1 <= 8'hff;
end
else if (intermediate_exp[7:0] == 8'd0)
begin
// zero
man_stage_1 <= 23'd0;
exp_stage_1 <= 8'h00;
end
else
begin
man_stage_1 <= mantissa_in;
exp_stage_1 <= intermediate_exp[7:0];
end
end
end
assign result = {sign_stage_1, exp_stage_1, man_stage_1};
endmodule
|
/****************************************************************************************
*
* File Name: ddr2_model.v
* Version: 5.82
* Model: BUS Functional
*
* Dependencies: ddr2_model_parameters.vh
*
* Description: Micron SDRAM DDR2 (Double Data Rate 2)
*
* Limitation: - doesn't check for average refresh timings
* - positive ck and ck_n edges are used to form internal clock
* - positive dqs and dqs_n edges are used to latch data
* - test mode is not modeled
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set Debug = 0 to disable $display messages
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
* Rev Author Date Changes
* ---------------------------------------------------------------------------------------
* 1.00 JMK 07/29/03 Initial Release
* 1.10 JMK 08/09/03 Timing Parameter updates to tIS, tIH, tDS, tDH
* 2.20 JMK 08/07/03 General cleanup
* 2.30 JMK 11/26/03 Added CL_MIN, CL_MAX, wl_min and wl_max parameters.
* Added AL_MIN and AL_MAX parameters.
* Removed support for OCD.
* 2.40 JMK 01/15/04 Removed verilog 2001 constructs.
* 2.50 JMK 01/29/04 Removed tRP checks during Precharge command.
* 2.60 JMK 04/20/04 Fixed tWTR check.
* 2.70 JMK 04/30/04 Added tRFC maximum check.
* Combined Self Refresh and Power Down always blocks.
* Added Reset Function (CKE LOW Anytime).
* 2.80 JMK 08/19/04 Precharge is treated as NOP when bank is not active.
* Added checks for tRAS, tWR, tRTP to any bank during Pre-All.
* tRFC maximum violation will only display one time.
* 2.90 JMK 11/05/04 Fixed DQS checking during write.
* Fixed false tRFC max assertion during power up and self ref.
* Added warning for 200us CKE low time during initialization.
* Added -3, -3E, and -37V speed grades to ddr2_parameters.v
* 3.00 JMK 04/22/05 Removed ODT off requirement during power down.
* Added tAOND, tAOFD, tANPD, tAXPD, tAONPD, and tAOFPD parameters.
* Added ODT status messages.
* Updated the initialization sequence.
* Disable ODT and CLK pins during self refresh.
* Disable cmd and addr pins during power down and self refresh.
* 3.10 JMK 06/07/05 Disable trpa checking if the part does not have 8 banks.
* Changed tAXPD message from error to a warning.
* Added tDSS checking.
* Removed tDQSL checking during tWPRE and tWPST.
* Fixed a burst order error during writes.
* Renamed parameters file with .vh extension.
* 3.20 JMK 07/18/05 Removed 14 tCK requirement from LMR to READ.
* 3.30 JMK 08/03/05 Added check for interrupting a burst with auto precharge.
* 4.00 JMK 11/21/05 Parameter names all UPPERCASE, signal names all lowercase.
* Clock jitter can be tolerated within specification range.
* Clock frequency is sampled from the CK pin.
* Scaleable up to 64 DQ and 16 DQS bits.
* Read data can be randomly skewed using RANDOM_OUT_DELAY.
* Parameterized read and write DQS, and read DQ.
* Initialization can be bypassed using initialize task.
* 4.10 JMK 11/30/05 Fixed compile errors when `MAX_MEM was defined.
* 4.20 JMK 12/09/05 Fixed memory addressing error when `MAX_MEM was defined.
* 4.30 JMK 02/15/06 Added dummy write to initialization sequence.
* Removed tWPST maximum checking.
* Rising dqs_n edge latches data when enabled in EMR.
* Fixed a sign error in the tJIT(cc) calculation.
* 4.40 JMK 02/16/06 Fixed dummy write when`MAX_MEM was defined.
* 4.50 JMK 02/27/06 Fixed extra tDQSS assertions.
* Fixed tRCD and tWTR checking.
* Errors entering Power Down or Self Refresh will cause reset.
* Ignore dqs_n when disabled in EMR.
* 5.00 JMK 04/24/06 Test stimulus now included from external file (subtest.vh)
* Fixed tRFC max assertion during self refresh.
* Fixed tANPD checking during Power Down.
* Removed dummy write from initialization sequence.
* 5.01 JMK 04/28/06 Fixed Auto Precharge to Load Mode, Refresh and Self Refresh.
* Removed Auto Precharge error message during Power Down Enter.
* 5.10 JMK 07/26/06 Created internal clock using ck and ck_n.
* RDQS can only be enabled in EMR for x8 configurations.
* CAS latency is checked vs frequency when DLL locks.
* tMOD changed from tCK units to ns units.
* Added 50 Ohm setting for Rtt in EMR.
* Improved checking of DQS during writes.
* 5.20 JMK 10/02/06 Fixed DQS checking for interrupting write to write and x16.
* 5.30 JMK 05/25/07 Fixed checking for 0-Z transition on write postamble.
* 5.50 JMK 05/30/08 Renamed ddr2_dimm.v to ddr2_module.v and added SODIMM support.
* Added a register delay to ddr2_module.v when RDIMM is defined.
* Added multi-chip package model support in ddr2_mcp.v
* Added High Temp Self Refresh rate setting in EMRS2[7]
* 5.70 JMK 04/23/09 Updated tRPA definition
* Increased internal width to 72 bit DQ bus
* 5.80 SPH 08/12/09 Fixed tRAS maximum violation (only check if bank still open)
* 5.81 SPH 12/08/09 Only check tIH for cmd_addr if CS# LOW
* 5.82 SPH 04/08/10 Correct debug message for SRT in EMR2
* 5.81 SPH 12/08/09 Only check tIH for cmd_addr if CS# LOW
* 5.81 SPH 12/08/09 Only check tIH for cmd_addr if CS# LOW
****************************************************************************************/
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
`timescale 1ps / 1ps
module ddr2_model_c3 (
ck,
ck_n,
cke,
cs_n,
ras_n,
cas_n,
we_n,
dm_rdqs,
ba,
addr,
dq,
dqs,
dqs_n,
rdqs_n,
odt
);
`include "ddr2_model_parameters_c3.vh"
// text macros
`define DQ_PER_DQS DQ_BITS/DQS_BITS
`define BANKS (1<<BA_BITS)
`define MAX_BITS (BA_BITS+ROW_BITS+COL_BITS-BL_BITS)
`define MAX_SIZE (1<<(BA_BITS+ROW_BITS+COL_BITS-BL_BITS))
`define MEM_SIZE (1<<MEM_BITS)
`define MAX_PIPE 2*(AL_MAX + CL_MAX)
// Declare Ports
input ck;
input ck_n;
input cke;
input cs_n;
input ras_n;
input cas_n;
input we_n;
inout [DM_BITS-1:0] dm_rdqs;
input [BA_BITS-1:0] ba;
input [ADDR_BITS-1:0] addr;
inout [DQ_BITS-1:0] dq;
inout [DQS_BITS-1:0] dqs;
inout [DQS_BITS-1:0] dqs_n;
output [DQS_BITS-1:0] rdqs_n;
input odt;
// clock jitter
real tck_avg;
time tck_sample [TDLLK-1:0];
time tch_sample [TDLLK-1:0];
time tcl_sample [TDLLK-1:0];
time tck_i;
time tch_i;
time tcl_i;
real tch_avg;
real tcl_avg;
time tm_ck_pos;
time tm_ck_neg;
real tjit_per_rtime;
integer tjit_cc_time;
real terr_nper_rtime;
// clock skew
real out_delay;
integer dqsck [DQS_BITS-1:0];
integer dqsck_min;
integer dqsck_max;
integer dqsq_min;
integer dqsq_max;
integer seed;
// Mode Registers
reg burst_order;
reg [BL_BITS:0] burst_length;
integer cas_latency;
integer additive_latency;
reg dll_reset;
reg dll_locked;
reg dll_en;
integer write_recovery;
reg low_power;
reg [1:0] odt_rtt;
reg odt_en;
reg [2:0] ocd;
reg dqs_n_en;
reg rdqs_en;
reg out_en;
integer read_latency;
integer write_latency;
// cmd encoding
parameter
LOAD_MODE = 4'b0000,
REFRESH = 4'b0001,
PRECHARGE = 4'b0010,
ACTIVATE = 4'b0011,
WRITE = 4'b0100,
READ = 4'b0101,
NOP = 4'b0111,
PWR_DOWN = 4'b1000,
SELF_REF = 4'b1001
;
reg [8*9-1:0] cmd_string [9:0];
initial begin
cmd_string[LOAD_MODE] = "Load Mode";
cmd_string[REFRESH ] = "Refresh ";
cmd_string[PRECHARGE] = "Precharge";
cmd_string[ACTIVATE ] = "Activate ";
cmd_string[WRITE ] = "Write ";
cmd_string[READ ] = "Read ";
cmd_string[NOP ] = "No Op ";
cmd_string[PWR_DOWN ] = "Pwr Down ";
cmd_string[SELF_REF ] = "Self Ref ";
end
// command state
reg [`BANKS-1:0] active_bank;
reg [`BANKS-1:0] auto_precharge_bank;
reg [`BANKS-1:0] write_precharge_bank;
reg [`BANKS-1:0] read_precharge_bank;
reg [ROW_BITS-1:0] active_row [`BANKS-1:0];
reg in_power_down;
reg in_self_refresh;
reg [3:0] init_mode_reg;
reg init_done;
integer init_step;
reg er_trfc_max;
reg odt_state;
reg prev_odt;
// cmd timers/counters
integer ref_cntr;
integer ck_cntr;
integer ck_load_mode;
integer ck_write;
integer ck_read;
integer ck_write_ap;
integer ck_power_down;
integer ck_slow_exit_pd;
integer ck_self_refresh;
integer ck_cke;
integer ck_odt;
integer ck_dll_reset;
integer ck_bank_write [`BANKS-1:0];
integer ck_bank_read [`BANKS-1:0];
time tm_refresh;
time tm_precharge;
time tm_precharge_all;
time tm_activate;
time tm_write_end;
time tm_self_refresh;
time tm_odt_en;
time tm_bank_precharge [`BANKS-1:0];
time tm_bank_activate [`BANKS-1:0];
time tm_bank_write_end [`BANKS-1:0];
time tm_bank_read_end [`BANKS-1:0];
// pipelines
reg [`MAX_PIPE:0] al_pipeline;
reg [`MAX_PIPE:0] wr_pipeline;
reg [`MAX_PIPE:0] rd_pipeline;
reg [`MAX_PIPE:0] odt_pipeline;
reg [BA_BITS-1:0] ba_pipeline [`MAX_PIPE:0];
reg [ROW_BITS-1:0] row_pipeline [`MAX_PIPE:0];
reg [COL_BITS-1:0] col_pipeline [`MAX_PIPE:0];
reg prev_cke;
// data state
reg [BL_MAX*DQ_BITS-1:0] memory_data;
reg [BL_MAX*DQ_BITS-1:0] bit_mask;
reg [BL_BITS-1:0] burst_position;
reg [BL_BITS:0] burst_cntr;
reg [DQ_BITS-1:0] dq_temp;
reg [35:0] check_write_postamble;
reg [35:0] check_write_preamble;
reg [35:0] check_write_dqs_high;
reg [35:0] check_write_dqs_low;
reg [17:0] check_dm_tdipw;
reg [71:0] check_dq_tdipw;
// data timers/counters
time tm_cke;
time tm_odt;
time tm_tdqss;
time tm_dm [17:0];
time tm_dqs [17:0];
time tm_dqs_pos [35:0];
time tm_dqss_pos [35:0];
time tm_dqs_neg [35:0];
time tm_dq [71:0];
time tm_cmd_addr [22:0];
reg [8*7-1:0] cmd_addr_string [22:0];
initial begin
cmd_addr_string[ 0] = "CS_N ";
cmd_addr_string[ 1] = "RAS_N ";
cmd_addr_string[ 2] = "CAS_N ";
cmd_addr_string[ 3] = "WE_N ";
cmd_addr_string[ 4] = "BA 0 ";
cmd_addr_string[ 5] = "BA 1 ";
cmd_addr_string[ 6] = "BA 2 ";
cmd_addr_string[ 7] = "ADDR 0";
cmd_addr_string[ 8] = "ADDR 1";
cmd_addr_string[ 9] = "ADDR 2";
cmd_addr_string[10] = "ADDR 3";
cmd_addr_string[11] = "ADDR 4";
cmd_addr_string[12] = "ADDR 5";
cmd_addr_string[13] = "ADDR 6";
cmd_addr_string[14] = "ADDR 7";
cmd_addr_string[15] = "ADDR 8";
cmd_addr_string[16] = "ADDR 9";
cmd_addr_string[17] = "ADDR 10";
cmd_addr_string[18] = "ADDR 11";
cmd_addr_string[19] = "ADDR 12";
cmd_addr_string[20] = "ADDR 13";
cmd_addr_string[21] = "ADDR 14";
cmd_addr_string[22] = "ADDR 15";
end
reg [8*5-1:0] dqs_string [1:0];
initial begin
dqs_string[0] = "DQS ";
dqs_string[1] = "DQS_N";
end
// Memory Storage
`ifdef MAX_MEM
reg [BL_MAX*DQ_BITS-1:0] memory [0:`MAX_SIZE-1];
`else
reg [BL_MAX*DQ_BITS-1:0] memory [0:`MEM_SIZE-1];
reg [`MAX_BITS-1:0] address [0:`MEM_SIZE-1];
reg [MEM_BITS:0] memory_index;
reg [MEM_BITS:0] memory_used;
`endif
// receive
reg ck_in;
reg ck_n_in;
reg cke_in;
reg cs_n_in;
reg ras_n_in;
reg cas_n_in;
reg we_n_in;
reg [17:0] dm_in;
reg [2:0] ba_in;
reg [15:0] addr_in;
reg [71:0] dq_in;
reg [35:0] dqs_in;
reg odt_in;
reg [17:0] dm_in_pos;
reg [17:0] dm_in_neg;
reg [71:0] dq_in_pos;
reg [71:0] dq_in_neg;
reg dq_in_valid;
reg dqs_in_valid;
integer wdqs_cntr;
integer wdq_cntr;
integer wdqs_pos_cntr [35:0];
reg b2b_write;
reg [35:0] prev_dqs_in;
reg diff_ck;
always @(ck ) ck_in <= #BUS_DELAY ck;
always @(ck_n ) ck_n_in <= #BUS_DELAY ck_n;
always @(cke ) cke_in <= #BUS_DELAY cke;
always @(cs_n ) cs_n_in <= #BUS_DELAY cs_n;
always @(ras_n ) ras_n_in <= #BUS_DELAY ras_n;
always @(cas_n ) cas_n_in <= #BUS_DELAY cas_n;
always @(we_n ) we_n_in <= #BUS_DELAY we_n;
always @(dm_rdqs) dm_in <= #BUS_DELAY dm_rdqs;
always @(ba ) ba_in <= #BUS_DELAY ba;
always @(addr ) addr_in <= #BUS_DELAY addr;
always @(dq ) dq_in <= #BUS_DELAY dq;
always @(dqs or dqs_n) dqs_in <= #BUS_DELAY (dqs_n<<18) | dqs;
always @(odt ) odt_in <= #BUS_DELAY odt;
// create internal clock
always @(posedge ck_in) diff_ck <= ck_in;
always @(posedge ck_n_in) diff_ck <= ~ck_n_in;
wire [17:0] dqs_even = dqs_in[17:0];
wire [17:0] dqs_odd = dqs_n_en ? dqs_in[35:18] : ~dqs_in[17:0];
wire [3:0] cmd_n_in = !cs_n_in ? {ras_n_in, cas_n_in, we_n_in} : NOP; //deselect = nop
// transmit
reg dqs_out_en;
reg [DQS_BITS-1:0] dqs_out_en_dly;
reg dqs_out;
reg [DQS_BITS-1:0] dqs_out_dly;
reg dq_out_en;
reg [DQ_BITS-1:0] dq_out_en_dly;
reg [DQ_BITS-1:0] dq_out;
reg [DQ_BITS-1:0] dq_out_dly;
integer rdqsen_cntr;
integer rdqs_cntr;
integer rdqen_cntr;
integer rdq_cntr;
bufif1 buf_dqs [DQS_BITS-1:0] (dqs, dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});
bufif1 buf_dm [DM_BITS-1:0] (dm_rdqs, dqs_out_dly, dqs_out_en_dly & {DM_BITS {out_en}} & {DM_BITS{rdqs_en}});
bufif1 buf_dqs_n [DQS_BITS-1:0] (dqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}});
bufif1 buf_rdqs_n [DQS_BITS-1:0] (rdqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}} & {DQS_BITS{rdqs_en}});
bufif1 buf_dq [DQ_BITS-1:0] (dq, dq_out_dly, dq_out_en_dly & {DQ_BITS {out_en}});
initial begin
if (BL_MAX < 2)
$display("%m ERROR: BL_MAX parameter must be >= 2. \nBL_MAX = %d", BL_MAX);
if ((1<<BO_BITS) > BL_MAX)
$display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter.");
$timeformat (-12, 1, " ps", 1);
reset_task;
seed = RANDOM_SEED;
ck_cntr = 0;
end
// calculate the absolute value of a real number
function real abs_value;
input arg;
real arg;
begin
if (arg < 0.0)
abs_value = -1.0 * arg;
else
abs_value = arg;
end
endfunction
`ifdef MAX_MEM
`else
function get_index;
input [`MAX_BITS-1:0] addr;
begin : index
get_index = 0;
for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
if (address[memory_index] == addr) begin
get_index = 1;
disable index;
end
end
end
endfunction
`endif
task memory_write;
input [BA_BITS-1:0] bank;
input [ROW_BITS-1:0] row;
input [COL_BITS-1:0] col;
input [BL_MAX*DQ_BITS-1:0] data;
reg [`MAX_BITS-1:0] addr;
begin
// chop off the lowest address bits
addr = {bank, row, col}/BL_MAX;
`ifdef MAX_MEM
memory[addr] = data;
`else
if (get_index(addr)) begin
address[memory_index] = addr;
memory[memory_index] = data;
end else if (memory_used == `MEM_SIZE) begin
$display ("%m: at time %t ERROR: Memory overflow. Write to Address %h with Data %h will be lost.\nYou must increase the MEM_BITS parameter or define MAX_MEM.", $time, addr, data);
if (STOP_ON_ERROR) $stop(0);
end else begin
address[memory_used] = addr;
memory[memory_used] = data;
memory_used = memory_used + 1;
end
`endif
end
endtask
task memory_read;
input [BA_BITS-1:0] bank;
input [ROW_BITS-1:0] row;
input [COL_BITS-1:0] col;
output [BL_MAX*DQ_BITS-1:0] data;
reg [`MAX_BITS-1:0] addr;
begin
// chop off the lowest address bits
addr = {bank, row, col}/BL_MAX;
`ifdef MAX_MEM
data = memory[addr];
`else
if (get_index(addr)) begin
data = memory[memory_index];
end else begin
data = {BL_MAX*DQ_BITS{1'bx}};
end
`endif
end
endtask
// Before this task runs, the model must be in a valid state for precharge power down.
// After this task runs, NOP commands must be issued until tRFC has been met
task initialize;
input [ADDR_BITS-1:0] mode_reg0;
input [ADDR_BITS-1:0] mode_reg1;
input [ADDR_BITS-1:0] mode_reg2;
input [ADDR_BITS-1:0] mode_reg3;
begin
if (DEBUG) $display ("%m: at time %t INFO: Performing Initialization Sequence", $time);
cmd_task(1, NOP, 'bx, 'bx);
cmd_task(1, PRECHARGE, 'bx, 1<<AP); // Precharege ALL
cmd_task(1, LOAD_MODE, 3, mode_reg3);
cmd_task(1, LOAD_MODE, 2, mode_reg2);
cmd_task(1, LOAD_MODE, 1, mode_reg1);
cmd_task(1, LOAD_MODE, 0, mode_reg0 | 'h100); // DLL Reset
cmd_task(1, PRECHARGE, 'bx, 1<<AP); // Precharege ALL
cmd_task(1, REFRESH, 'bx, 'bx);
cmd_task(1, REFRESH, 'bx, 'bx);
cmd_task(1, LOAD_MODE, 0, mode_reg0);
cmd_task(1, LOAD_MODE, 1, mode_reg1 | 'h380); // OCD Default
cmd_task(1, LOAD_MODE, 1, mode_reg1);
cmd_task(0, NOP, 'bx, 'bx);
end
endtask
task reset_task;
integer i;
begin
// disable inputs
dq_in_valid = 0;
dqs_in_valid <= 0;
wdqs_cntr = 0;
wdq_cntr = 0;
for (i=0; i<36; i=i+1) begin
wdqs_pos_cntr[i] <= 0;
end
b2b_write <= 0;
// disable outputs
out_en = 0;
dqs_n_en = 0;
rdqs_en = 0;
dq_out_en = 0;
rdq_cntr = 0;
dqs_out_en = 0;
rdqs_cntr = 0;
// disable ODT
odt_en = 0;
odt_state = 0;
// reset bank state
active_bank = {`BANKS{1'b1}};
auto_precharge_bank = 0;
read_precharge_bank = 0;
write_precharge_bank = 0;
// require initialization sequence
init_done = 0;
init_step = 0;
init_mode_reg = 0;
// reset DLL
dll_en = 0;
dll_reset = 0;
dll_locked = 0;
ocd = 0;
// exit power down and self refresh
in_power_down = 0;
in_self_refresh = 0;
// clear pipelines
al_pipeline = 0;
wr_pipeline = 0;
rd_pipeline = 0;
odt_pipeline = 0;
// clear memory
`ifdef MAX_MEM
for (i=0; i<=`MAX_SIZE; i=i+1) begin //erase memory ... one address at a time
memory[i] <= 'bx;
end
`else
memory_used <= 0; //erase memory
`endif
// clear maximum timing checks
tm_refresh <= 'bx;
for (i=0; i<`BANKS; i=i+1) begin
tm_bank_activate[i] <= 'bx;
end
end
endtask
task chk_err;
input samebank;
input [BA_BITS-1:0] bank;
input [3:0] fromcmd;
input [3:0] cmd;
reg err;
begin
// all matching case expressions will be evaluated
casex ({samebank, fromcmd, cmd})
{1'b0, LOAD_MODE, 4'b0xxx } : begin if (ck_cntr - ck_load_mode < TMRD) $display ("%m: at time %t ERROR: tMRD violation during %s", $time, cmd_string[cmd]); end
{1'b0, LOAD_MODE, 4'b100x } : begin if (ck_cntr - ck_load_mode < TMRD) begin $display ("%m: at time %t INFO: Load Mode to Reset condition.", $time); init_done = 0; end end
{1'b0, REFRESH , 4'b0xxx } : begin if ($time - tm_refresh < TRFC_MIN) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]); end
{1'b0, REFRESH , PWR_DOWN } : ; // 1 tCK
{1'b0, REFRESH , SELF_REF } : begin if ($time - tm_refresh < TRFC_MIN) begin $display ("%m: at time %t INFO: Refresh to Reset condition", $time); init_done = 0; end end
{1'b0, PRECHARGE, 4'b000x } : begin if ($time - tm_precharge_all < TRPA) $display ("%m: at time %t ERROR: tRPA violation during %s", $time, cmd_string[cmd]);
if ($time - tm_precharge < TRP) $display ("%m: at time %t ERROR: tRP violation during %s", $time, cmd_string[cmd]); end
{1'b1, PRECHARGE, PRECHARGE} : begin if (DEBUG && ($time - tm_precharge_all < TRPA)) $display ("%m: at time %t INFO: Precharge All interruption during %s", $time, cmd_string[cmd]);
if (DEBUG && ($time - tm_bank_precharge[bank] < TRP)) $display ("%m: at time %t INFO: Precharge bank %d interruption during %s", $time, cmd_string[cmd], bank); end
{1'b1, PRECHARGE, ACTIVATE } : begin if ($time - tm_precharge_all < TRPA) $display ("%m: at time %t ERROR: tRPA violation during %s", $time, cmd_string[cmd]);
if ($time - tm_bank_precharge[bank] < TRP) $display ("%m: at time %t ERROR: tRP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, PRECHARGE, PWR_DOWN } : ; //1 tCK, can be concurrent with auto precharge
{1'b0, PRECHARGE, SELF_REF } : begin if (($time - tm_precharge_all < TRPA) || ($time - tm_precharge < TRP)) begin $display ("%m: at time %t INFO: Precharge to Reset condition", $time); init_done = 0; end end
{1'b0, ACTIVATE , REFRESH } : begin if ($time - tm_activate < TRC) $display ("%m: at time %t ERROR: tRC violation during %s", $time, cmd_string[cmd]); end
{1'b1, ACTIVATE , PRECHARGE} : begin if (($time - tm_bank_activate[bank] > TRAS_MAX) && (active_bank[bank] === 1'b1)) $display ("%m: at time %t ERROR: tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank);
if ($time - tm_bank_activate[bank] < TRAS_MIN) $display ("%m: at time %t ERROR: tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end
{1'b0, ACTIVATE , ACTIVATE } : begin if ($time - tm_activate < TRRD) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC) $display ("%m: at time %t ERROR: tRC violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, ACTIVATE , 4'b010x } : ; // tRCD is checked outside this task
{1'b1, ACTIVATE , PWR_DOWN } : ; // 1 tCK
{1'b1, WRITE , PRECHARGE} : begin if ((ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2) || ($time - tm_bank_write_end[bank] < TWR)) $display ("%m: at time %t ERROR: tWR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, WRITE , READ } : begin if ((ck_load_mode < ck_write) && (ck_cntr - ck_write < write_latency + burst_length/2 + 2 - additive_latency)) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, WRITE , PWR_DOWN } : begin if ((ck_load_mode < ck_write) && (
|write_precharge_bank
|| (ck_cntr - ck_write_ap < 1)
|| (ck_cntr - ck_write < write_latency + burst_length/2 + 2)
|| ($time - tm_write_end < TWTR))) begin $display ("%m: at time %t INFO: Write to Reset condition", $time); init_done = 0; end end
{1'b1, READ , PRECHARGE} : begin if ((ck_cntr - ck_bank_read[bank] < additive_latency + burst_length/2) || ($time - tm_bank_read_end[bank] < TRTP)) $display ("%m: at time %t ERROR: tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, READ , WRITE } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1 - write_latency)) $display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, READ , READ } : begin if (ck_cntr - ck_read < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, READ , PWR_DOWN } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1)) begin $display ("%m: at time %t INFO: Read to Reset condition", $time); init_done = 0; end end
{1'b0, PWR_DOWN , 4'b00xx } : begin if (ck_cntr - ck_power_down < TXP) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end
{1'b0, PWR_DOWN , WRITE } : begin if (ck_cntr - ck_power_down < TXP) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end
{1'b0, PWR_DOWN , READ } : begin if (ck_cntr - ck_slow_exit_pd < TXARDS - additive_latency) $display ("%m: at time %t ERROR: tXARDS violation during %s", $time, cmd_string[cmd]);
else if (ck_cntr - ck_power_down < TXARD) $display ("%m: at time %t ERROR: tXARD violation during %s", $time, cmd_string[cmd]); end
{1'b0, SELF_REF , 4'b00xx } : begin if ($time - tm_self_refresh < TXSNR) $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]); end
{1'b0, SELF_REF , WRITE } : begin if ($time - tm_self_refresh < TXSNR) $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]); end
{1'b0, SELF_REF , READ } : begin if (ck_cntr - ck_self_refresh < TXSRD) $display ("%m: at time %t ERROR: tXSRD violation during %s", $time, cmd_string[cmd]); end
{1'b0, 4'b100x , 4'b100x } : begin if (ck_cntr - ck_cke < TCKE) begin $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); init_done = 0; end end
endcase
end
endtask
task cmd_task;
input cke;
input [2:0] cmd;
input [BA_BITS-1:0] bank;
input [ADDR_BITS-1:0] addr;
reg [`BANKS:0] i;
integer j;
reg [`BANKS:0] tfaw_cntr;
reg [COL_BITS-1:0] col;
begin
// tRFC max check
if (!er_trfc_max && !in_self_refresh) begin
if ($time - tm_refresh > TRFC_MAX) begin
$display ("%m: at time %t ERROR: tRFC maximum violation during %s", $time, cmd_string[cmd]);
er_trfc_max = 1;
end
end
if (cke) begin
if ((cmd < NOP) && ((cmd != PRECHARGE) || !addr[AP])) begin
for (j=0; j<NOP; j=j+1) begin
chk_err(1'b0, bank, j, cmd);
chk_err(1'b1, bank, j, cmd);
end
chk_err(1'b0, bank, PWR_DOWN, cmd);
chk_err(1'b0, bank, SELF_REF, cmd);
end
case (cmd)
LOAD_MODE : begin
if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank);
case (bank)
0 : begin
// Burst Length
burst_length = 1<<addr[2:0];
if ((burst_length >= BL_MIN) && (burst_length <= BL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
end
// Burst Order
burst_order = addr[3];
if (!burst_order) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank);
end else if (burst_order) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order);
end
// CAS Latency
cas_latency = addr[6:4];
read_latency = cas_latency + additive_latency;
write_latency = read_latency - 1;
if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
end
// Test Mode
if (!addr[7]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Test Mode = Normal", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Test Mode = %d", $time, cmd_string[cmd], bank, addr[7]);
end
// DLL Reset
dll_reset = addr[8];
if (!dll_reset) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank);
end else if (dll_reset) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank);
dll_locked = 0;
ck_dll_reset <= ck_cntr;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset);
end
// Write Recovery
write_recovery = addr[11:9] + 1;
if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
end
// Power Down Mode
low_power = addr[12];
if (!low_power) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Fast Exit", $time, cmd_string[cmd], bank);
end else if (low_power) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Slow Exit", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power);
end
end
1 : begin
// DLL Enable
dll_en = !addr[0];
if (!dll_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (dll_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en);
end
// Output Drive Strength
if (!addr[1]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Full", $time, cmd_string[cmd], bank);
end else if (addr[1]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Reduced", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, addr[1]);
end
// ODT Rtt
odt_rtt = {addr[6], addr[2]};
if (odt_rtt == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank);
odt_en = 0;
end else if (odt_rtt == 2'b01) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 75 Ohm", $time, cmd_string[cmd], bank);
odt_en = 1;
tm_odt_en <= $time;
end else if (odt_rtt == 2'b10) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 150 Ohm", $time, cmd_string[cmd], bank);
odt_en = 1;
tm_odt_en <= $time;
end else if (odt_rtt == 2'b11) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 50 Ohm", $time, cmd_string[cmd], bank);
odt_en = 1;
tm_odt_en <= $time;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt);
odt_en = 0;
end
// Additive Latency
additive_latency = addr[5:3];
read_latency = cas_latency + additive_latency;
write_latency = read_latency - 1;
if ((additive_latency >= AL_MIN) && (additive_latency <= AL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency);
end
// OCD Program
ocd = addr[9:7];
if (ocd == 3'b000) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Exit", $time, cmd_string[cmd], bank);
end else if (ocd == 3'b111) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Default", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal OCD Program = %b", $time, cmd_string[cmd], bank, ocd);
end
// DQS_N Enable
dqs_n_en = !addr[10];
if (!dqs_n_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (dqs_n_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DQS_N Enable = %d", $time, cmd_string[cmd], bank, dqs_n_en);
end
// RDQS Enable
rdqs_en = addr[11];
if (!rdqs_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (rdqs_en) begin
`ifdef x8
if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Enabled", $time, cmd_string[cmd], bank);
`else
$display ("%m: at time %t WARNING: %s %d Illegal RDQS Enable. RDQS only exists on a x8 part", $time, cmd_string[cmd], bank);
rdqs_en = 0;
`endif
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal RDQS Enable = %d", $time, cmd_string[cmd], bank, rdqs_en);
end
// Output Enable
out_en = !addr[12];
if (!out_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (out_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Output Enable = %d", $time, cmd_string[cmd], bank, out_en);
end
end
2 : begin
// High Temperature Self Refresh rate
if (!addr[7]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d High Temperature Self Refresh rate = 1X (0C-85C)", $time, cmd_string[cmd], bank);
end else if (addr[7]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d High Temperature Self Refresh rate = 2X (>85C)", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal High Temperature Self Refresh rate = %d", $time, cmd_string[cmd], bank, addr[7]);
end
if ((addr & ~(1<<7)) !== 0) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
3 : begin
if (addr !== 0) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
endcase
init_mode_reg[bank] = 1;
ck_load_mode <= ck_cntr;
end
end
REFRESH : begin
if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]);
er_trfc_max = 0;
ref_cntr = ref_cntr + 1;
tm_refresh <= $time;
end
end
PRECHARGE : begin
if (addr[AP]) begin
// tRPA timing applies when the PRECHARGE (ALL) command is issued, regardless of
// the number of banks already open or closed.
for (i=0; i<`BANKS; i=i+1) begin
for (j=0; j<NOP; j=j+1) begin
chk_err(1'b0, i, j, cmd);
chk_err(1'b1, i, j, cmd);
end
chk_err(1'b0, i, PWR_DOWN, cmd);
chk_err(1'b0, i, SELF_REF, cmd);
end
if (|auto_precharge_bank) begin
$display ("%m: at time %t ERROR: %s All Failure. Auto Precharge is scheduled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]);
active_bank = 0;
tm_precharge_all <= $time;
end
end else begin
// A PRECHARGE command is allowed if there is no open row in that bank (idle state)
// or if the previously open row is already in the process of precharging.
// However, the precharge period will be determined by the last PRECHARGE command issued to the bank.
if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d", $time, cmd_string[cmd], bank);
active_bank[bank] = 1'b0;
tm_bank_precharge[bank] <= $time;
tm_precharge <= $time;
end
end
end
ACTIVATE : begin
if (`BANKS == 8) begin
tfaw_cntr = 0;
for (i=0; i<`BANKS; i=i+1) begin
if ($time - tm_bank_activate[i] < TFAW) begin
tfaw_cntr = tfaw_cntr + 1;
end
end
if (tfaw_cntr > 3) begin
$display ("%m: at time %t ERROR: tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
end
if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (active_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Bank %d must be Precharged.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr >= 1<<ROW_BITS) begin
$display ("%m: at time %t WARNING: row = %h does not exist. Maximum row = %h", $time, addr, (1<<ROW_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d row %h", $time, cmd_string[cmd], bank, addr);
active_bank[bank] = 1'b1;
active_row[bank] = addr;
tm_bank_activate[bank] <= $time;
tm_activate <= $time;
end
end
WRITE : begin
if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!active_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if ((ck_cntr - ck_write < burst_length/2) && (ck_cntr - ck_write)%2) begin
$display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr[AP]) begin
auto_precharge_bank[bank] = 1'b1;
write_precharge_bank[bank] = 1'b1;
end
col = ((addr>>1) & -1*(1<<AP)) | (addr & {AP{1'b1}});
if (col >= 1<<COL_BITS) begin
$display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
wr_pipeline[2*write_latency + 1] = 1;
ba_pipeline[2*write_latency + 1] = bank;
row_pipeline[2*write_latency + 1] = active_row[bank];
col_pipeline[2*write_latency + 1] = col;
ck_bank_write[bank] <= ck_cntr;
ck_write <= ck_cntr;
end
end
READ : begin
if (!dll_locked)
$display ("%m: at time %t WARNING: %s prior to DLL locked. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.", $time, cmd_string[cmd]);
if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!active_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if ((ck_cntr - ck_read < burst_length/2) && (ck_cntr - ck_read)%2) begin
$display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr[AP]) begin
auto_precharge_bank[bank] = 1'b1;
read_precharge_bank[bank] = 1'b1;
end
col = ((addr>>1) & -1*(1<<AP)) | (addr & {AP{1'b1}});
if (col >= 1<<COL_BITS) begin
$display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
rd_pipeline[2*read_latency - 1] = 1;
ba_pipeline[2*read_latency - 1] = bank;
row_pipeline[2*read_latency - 1] = active_row[bank];
col_pipeline[2*read_latency - 1] = col;
ck_bank_read[bank] <= ck_cntr;
ck_read <= ck_cntr;
end
end
NOP: begin
if (in_power_down) begin
if (DEBUG) $display ("%m: at time %t INFO: Power Down Exit", $time);
in_power_down = 0;
if (|active_bank & low_power) begin // slow exit active power down
ck_slow_exit_pd <= ck_cntr;
end
ck_power_down <= ck_cntr;
end
if (in_self_refresh) begin
if ($time - tm_cke < TISXR)
$display ("%m: at time %t ERROR: tISXR violation during Self Refresh Exit", $time);
if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Exit", $time);
in_self_refresh = 0;
ck_dll_reset <= ck_cntr;
ck_self_refresh <= ck_cntr;
tm_self_refresh <= $time;
tm_refresh <= $time;
end
end
endcase
if ((prev_cke !== 1) && (cmd !== NOP)) begin
$display ("%m: at time %t ERROR: NOP or Deselect is required when CKE goes active.", $time);
end
if (!init_done) begin
case (init_step)
0 : begin
if ($time < 200000000)
$display ("%m: at time %t WARNING: 200 us is required before CKE goes active.", $time);
// if (cmd_chk + 200000000 > $time)
// $display("%m: at time %t WARNING: NOP or DESELECT is required for 200 us before CKE is brought high", $time);
init_step = init_step + 1;
end
1 : if (dll_en) init_step = init_step + 1;
2 : begin
if (&init_mode_reg && dll_reset) begin
active_bank = {`BANKS{1'b1}}; // require Precharge All or bank Precharges
ref_cntr = 0; // require refresh
init_step = init_step + 1;
end
end
3 : if (ref_cntr == 2) begin
init_step = init_step + 1;
end
4 : if (!dll_reset) init_step = init_step + 1;
5 : if (ocd == 3'b111) init_step = init_step + 1;
6 : begin
if (ocd == 3'b000) begin
if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time);
init_done = 1;
end
end
endcase
end
end else if (prev_cke) begin
if ((!init_done) && (init_step > 1)) begin
$display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end
case (cmd)
REFRESH : begin
for (j=0; j<NOP; j=j+1) begin
chk_err(1'b0, bank, j, SELF_REF);
end
chk_err(1'b0, bank, PWR_DOWN, SELF_REF);
chk_err(1'b0, bank, SELF_REF, SELF_REF);
if (|active_bank) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. All banks must be Precharged.", $time);
if (STOP_ON_ERROR) $stop(0);
init_done = 0;
end else if (odt_en && odt_state) begin
$display ("%m: at time %t ERROR: ODT must be off prior to entering Self Refresh", $time);
if (STOP_ON_ERROR) $stop(0);
init_done = 0;
end else if (!init_done) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. Initialization sequence is not complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Enter", $time);
in_self_refresh = 1;
dll_locked = 0;
end
end
NOP : begin
// entering slow_exit or precharge power down and tANPD has not been satisfied
if ((low_power || (active_bank == 0)) && (ck_cntr - ck_odt < TANPD))
$display ("%m: at time %t WARNING: tANPD violation during %s. Synchronous or asynchronous change in termination resistance is possible.", $time, cmd_string[PWR_DOWN]);
for (j=0; j<NOP; j=j+1) begin
chk_err(1'b0, bank, j, PWR_DOWN);
end
chk_err(1'b0, bank, PWR_DOWN, PWR_DOWN);
chk_err(1'b0, bank, SELF_REF, PWR_DOWN);
if (!init_done) begin
$display ("%m: at time %t ERROR: Power Down Failure. Initialization sequence is not complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) begin
if (|active_bank) begin
$display ("%m: at time %t INFO: Active Power Down Enter", $time);
end else begin
$display ("%m: at time %t INFO: Precharge Power Down Enter", $time);
end
end
in_power_down = 1;
end
end
default : begin
$display ("%m: at time %t ERROR: NOP, Deselect, or Refresh is required when CKE goes inactive.", $time);
init_done = 0;
end
endcase
if (!init_done) begin
if (DEBUG) $display ("%m: at time %t WARNING: Reset has occurred. Device must be re-initialized.", $time);
reset_task;
end
end
prev_cke = cke;
end
endtask
task data_task;
reg [BA_BITS-1:0] bank;
reg [ROW_BITS-1:0] row;
reg [COL_BITS-1:0] col;
integer i;
integer j;
begin
if (diff_ck) begin
for (i=0; i<36; i=i+1) begin
if (dq_in_valid && dll_locked && ($time - tm_dqs_neg[i] < $rtoi(TDSS*tck_avg)))
$display ("%m: at time %t ERROR: tDSS violation on %s bit %d", $time, dqs_string[i/18], i%18);
if (check_write_dqs_high[i])
$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period.", $time, dqs_string[i/18], i%18);
end
check_write_dqs_high <= 0;
end else begin
for (i=0; i<36; i=i+1) begin
if (dll_locked && dq_in_valid) begin
tm_tdqss = abs_value(1.0*tm_ck_pos - tm_dqss_pos[i]);
if ((tm_tdqss < tck_avg/2.0) && (tm_tdqss > TDQSS*tck_avg))
$display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/18], i%18);
end
if (check_write_dqs_low[i])
$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/18], i%18);
end
check_write_preamble <= 0;
check_write_postamble <= 0;
check_write_dqs_low <= 0;
end
if (wr_pipeline[0] || rd_pipeline[0]) begin
bank = ba_pipeline[0];
row = row_pipeline[0];
col = col_pipeline[0];
burst_cntr = 0;
memory_read(bank, row, col, memory_data);
end
// burst counter
if (burst_cntr < burst_length) begin
burst_position = col ^ burst_cntr;
if (!burst_order) begin
burst_position[BO_BITS-1:0] = col + burst_cntr;
end
burst_cntr = burst_cntr + 1;
end
// write dqs counter
if (wr_pipeline[WDQS_PRE + 1]) begin
wdqs_cntr = WDQS_PRE + burst_length + WDQS_PST - 1;
end
// write dqs
if ((wdqs_cntr == burst_length + WDQS_PST) && (wdq_cntr == 0)) begin //write preamble
check_write_preamble <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
end
if (wdqs_cntr > 1) begin // write data
if ((wdqs_cntr - WDQS_PST)%2) begin
check_write_dqs_high <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
end else begin
check_write_dqs_low <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
end
end
if (wdqs_cntr == WDQS_PST) begin // write postamble
check_write_postamble <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
end
if (wdqs_cntr > 0) begin
wdqs_cntr = wdqs_cntr - 1;
end
// write dq
if (dq_in_valid) begin // write data
bit_mask = 0;
if (diff_ck) begin
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_neg[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
end
memory_data = (dq_in_neg<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
end else begin
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_pos[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
end
memory_data = (dq_in_pos<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
end
dq_temp = memory_data>>(burst_position*DQ_BITS);
if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
if (burst_cntr%BL_MIN == 0) begin
memory_write(bank, row, col, memory_data);
end
end
if (wr_pipeline[1]) begin
wdq_cntr = burst_length;
end
if (wdq_cntr > 0) begin
wdq_cntr = wdq_cntr - 1;
dq_in_valid = 1'b1;
end else begin
dq_in_valid = 1'b0;
dqs_in_valid <= 1'b0;
for (i=0; i<36; i=i+1) begin
wdqs_pos_cntr[i] <= 0;
end
end
if (wr_pipeline[0]) begin
b2b_write <= 1'b0;
end
if (wr_pipeline[2]) begin
if (dqs_in_valid) begin
b2b_write <= 1'b1;
end
dqs_in_valid <= 1'b1;
end
// read dqs enable counter
if (rd_pipeline[RDQSEN_PRE]) begin
rdqsen_cntr = RDQSEN_PRE + burst_length + RDQSEN_PST - 1;
end
if (rdqsen_cntr > 0) begin
rdqsen_cntr = rdqsen_cntr - 1;
dqs_out_en = 1'b1;
end else begin
dqs_out_en = 1'b0;
end
// read dqs counter
if (rd_pipeline[RDQS_PRE]) begin
rdqs_cntr = RDQS_PRE + burst_length + RDQS_PST - 1;
end
// read dqs
if ((rdqs_cntr >= burst_length + RDQS_PST) && (rdq_cntr == 0)) begin //read preamble
dqs_out = 1'b0;
end else if (rdqs_cntr > RDQS_PST) begin // read data
dqs_out = rdqs_cntr - RDQS_PST;
end else if (rdqs_cntr > 0) begin // read postamble
dqs_out = 1'b0;
end else begin
dqs_out = 1'b1;
end
if (rdqs_cntr > 0) begin
rdqs_cntr = rdqs_cntr - 1;
end
// read dq enable counter
if (rd_pipeline[RDQEN_PRE]) begin
rdqen_cntr = RDQEN_PRE + burst_length + RDQEN_PST;
end
if (rdqen_cntr > 0) begin
rdqen_cntr = rdqen_cntr - 1;
dq_out_en = 1'b1;
end else begin
dq_out_en = 1'b0;
end
// read dq
if (rd_pipeline[0]) begin
rdq_cntr = burst_length;
end
if (rdq_cntr > 0) begin // read data
dq_temp = memory_data>>(burst_position*DQ_BITS);
dq_out = dq_temp;
if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
rdq_cntr = rdq_cntr - 1;
end else begin
dq_out = {DQ_BITS{1'b1}};
end
// delay signals prior to output
if (RANDOM_OUT_DELAY && (dqs_out_en || |dqs_out_en_dly || dq_out_en || |dq_out_en_dly)) begin
for (i=0; i<DQS_BITS; i=i+1) begin
// DQSCK requirements
// 1.) less than tDQSCK
// 2.) greater than -tDQSCK
// 3.) cannot change more than tQHS + tDQSQ from previous DQS edge
dqsck_max = TDQSCK;
if (dqsck_max > dqsck[i] + TQHS + TDQSQ) begin
dqsck_max = dqsck[i] + TQHS + TDQSQ;
end
dqsck_min = -1*TDQSCK;
if (dqsck_min < dqsck[i] - TQHS - TDQSQ) begin
dqsck_min = dqsck[i] - TQHS - TDQSQ;
end
// DQSQ requirements
// 1.) less than tAC - DQSCK
// 2.) less than tDQSQ
// 3.) greater than -tAC
// 4.) greater than tQH from previous DQS edge
dqsq_min = -1*TAC;
if (dqsq_min < dqsck[i] - TQHS) begin
dqsq_min = dqsck[i] - TQHS;
end
if (dqsck_min == dqsck_max) begin
dqsck[i] = dqsck_min;
end else begin
dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max);
end
dqsq_max = TAC;
if (dqsq_max > TDQSQ + dqsck[i]) begin
dqsq_max = TDQSQ + dqsck[i];
end
dqs_out_en_dly[i] <= #(tck_avg/2.0 + ($random % TAC)) dqs_out_en;
dqs_out_dly[i] <= #(tck_avg/2.0 + dqsck[i]) dqs_out;
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if (dq_out_en) begin // tLZ2
dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + $dist_uniform(seed, -2*TAC, dqsq_max)) dq_out_en;
end else begin // tHZ
dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + ($random % TAC)) dq_out_en;
end
if (dqsq_min == dqsq_max) begin
dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + dqsq_min) dq_out[i*`DQ_PER_DQS + j];
end else begin
dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j];
end
end
end
end else begin
out_delay = tck_avg/2.0;
dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}};
dqs_out_dly <= #(out_delay) {DQS_BITS{dqs_out }};
dq_out_en_dly <= #(out_delay) {DQ_BITS {dq_out_en }};
dq_out_dly <= #(out_delay) {DQ_BITS {dq_out }};
end
end
endtask
always @(diff_ck) begin : main
integer i;
if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1))
$display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time);
data_task;
if (diff_ck) begin
// check setup of command signals
if ($time > TIS) begin
if ($time - tm_cke < TIS)
$display ("%m: at time %t ERROR: tIS violation on CKE by %t", $time, tm_cke + TIS - $time);
if (cke_in) begin
for (i=0; i<22; i=i+1) begin
if ($time - tm_cmd_addr[i] < TIS)
$display ("%m: at time %t ERROR: tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time);
end
end
end
// update current state
if (!dll_locked && !in_self_refresh && (ck_cntr - ck_dll_reset == TDLLK)) begin
// check CL value against the clock frequency
if (cas_latency*tck_avg < CL_TIME)
$display ("%m: at time %t ERROR: CAS Latency = %d is illegal @tCK(avg) = %f", $time, cas_latency, tck_avg);
// check WR value against the clock frequency
if (write_recovery*tck_avg < TWR)
$display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg);
dll_locked = 1;
end
if (|auto_precharge_bank) begin
for (i=0; i<`BANKS; i=i+1) begin
// Write with Auto Precharge Calculation
// 1. Meet minimum tRAS requirement
// 2. Write Latency PLUS BL/2 cycles PLUS WR after Write command
if (write_precharge_bank[i]
&& ($time - tm_bank_activate[i] >= TRAS_MIN)
&& (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery)) begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
write_precharge_bank[i] = 0;
active_bank[i] = 0;
auto_precharge_bank[i] = 0;
ck_write_ap = ck_cntr;
tm_bank_precharge[i] = $time;
tm_precharge = $time;
end
// Read with Auto Precharge Calculation
// 1. Meet minimum tRAS requirement
// 2. Additive Latency plus BL/2 cycles after Read command
// 3. tRTP after the last 4-bit prefetch
if (read_precharge_bank[i]
&& ($time - tm_bank_activate[i] >= TRAS_MIN)
&& (ck_cntr - ck_bank_read[i] >= additive_latency + burst_length/2)) begin
read_precharge_bank[i] = 0;
// In case the internal precharge is pushed out by tRTP, tRP starts at the point where
// the internal precharge happens (not at the next rising clock edge after this event).
if ($time - tm_bank_read_end[i] < TRTP) begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i);
active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
active_bank[i] = 0;
auto_precharge_bank[i] = 0;
tm_bank_precharge[i] = $time;
tm_precharge = $time;
end
end
end
end
// respond to incoming command
if (cke_in ^ prev_cke) begin
ck_cke <= ck_cntr;
end
cmd_task(cke_in, cmd_n_in, ba_in, addr_in);
if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin
al_pipeline[2*additive_latency] = 1'b1;
end
if (al_pipeline[0]) begin
// check tRCD after additive latency
if ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD) begin
if (rd_pipeline[2*cas_latency - 1]) begin
$display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[READ]);
end else begin
$display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[WRITE]);
end
end
// check tWTR after additive latency
if (rd_pipeline[2*cas_latency - 1]) begin
if ($time - tm_write_end < TWTR)
$display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]);
end
end
if (rd_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]) begin
tm_bank_read_end[ba_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]] <= $time;
end
for (i=0; i<`BANKS; i=i+1) begin
if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin
tm_bank_write_end[i] <= $time;
tm_write_end <= $time;
end
end
// clk pin is disabled during self refresh
if (!in_self_refresh) begin
tjit_cc_time = $time - tm_ck_pos - tck_i;
tck_i = $time - tm_ck_pos;
tck_avg = tck_avg - tck_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tck_avg = tck_avg + tck_i/$itor(TDLLK);
tck_sample[ck_cntr%TDLLK] = tck_i;
tjit_per_rtime = tck_i - tck_avg;
if (dll_locked) begin
// check accumulated error
terr_nper_rtime = 0;
for (i=0; i<50; i=i+1) begin
terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg;
terr_nper_rtime = abs_value(terr_nper_rtime);
case (i)
0 :;
1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER);
2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER);
3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER);
4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER);
5,6,7,8,9 : if (terr_nper_rtime - TERR_N1PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n1per) violation by %f ps.", $time, terr_nper_rtime - TERR_N1PER);
default : if (terr_nper_rtime - TERR_N2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n2per) violation by %f ps.", $time, terr_nper_rtime - TERR_N2PER);
endcase
end
// check tCK min/max/jitter
if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0)
$display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER);
if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0)
$display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC);
if (TCK_MIN - tck_avg >= 1.0)
$display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg);
if (tck_avg - TCK_MAX >= 1.0)
$display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX);
if (tm_ck_pos + TCK_MIN - TJIT_PER > $time)
$display ("%m: at time %t ERROR: tCK(abs) minimum violation by %t", $time, tm_ck_pos + TCK_MIN - TJIT_PER - $time);
if (tm_ck_pos + TCK_MAX + TJIT_PER < $time)
$display ("%m: at time %t ERROR: tCK(abs) maximum violation by %t", $time, $time - tm_ck_pos - TCK_MAX - TJIT_PER);
// check tCL
if (tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY > $time)
$display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY - $time);
if (tm_ck_neg + TCL_MAX*tck_avg + TJIT_DUTY < $time)
$display ("%m: at time %t ERROR: tCL(abs) maximum violation on CLK by %t", $time, $time - tm_ck_neg - TCL_MAX*tck_avg - TJIT_DUTY);
if (tcl_avg < TCL_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_MIN*tck_avg - tcl_avg);
if (tcl_avg > TCL_MAX*tck_avg)
$display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_MAX*tck_avg);
end
// calculate the tch avg jitter
tch_avg = tch_avg - tch_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tch_avg = tch_avg + tch_i/$itor(TDLLK);
tch_sample[ck_cntr%TDLLK] = tch_i;
// update timers/counters
tcl_i <= $time - tm_ck_neg;
end
prev_odt <= odt_in;
// update timers/counters
ck_cntr <= ck_cntr + 1;
tm_ck_pos <= $time;
end else begin
// clk pin is disabled during self refresh
if (!in_self_refresh) begin
if (dll_locked) begin
if (tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY > $time)
$display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY + $time);
if (tm_ck_pos + TCH_MAX*tck_avg + TJIT_DUTY < $time)
$display ("%m: at time %t ERROR: tCH(abs) maximum violation on CLK by %t", $time, $time - tm_ck_pos - TCH_MAX*tck_avg - TJIT_DUTY);
if (tch_avg < TCH_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_MIN*tck_avg - tch_avg);
if (tch_avg > TCH_MAX*tck_avg)
$display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_MAX*tck_avg);
end
// calculate the tcl avg jitter
tcl_avg = tcl_avg - tcl_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tcl_avg = tcl_avg + tcl_i/$itor(TDLLK);
tcl_sample[ck_cntr%TDLLK] = tcl_i;
// update timers/counters
tch_i <= $time - tm_ck_pos;
end
tm_ck_neg <= $time;
end
// on die termination
if (odt_en) begin
// clk pin is disabled during self refresh
if (!in_self_refresh && diff_ck) begin
if ($time - tm_odt < TIS) begin
$display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time);
end
if (prev_odt ^ odt_in) begin
if (!dll_locked)
$display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time);
if (odt_in && ($time - tm_odt_en < TMOD))
$display ("%m: at time %t ERROR: tMOD violation during ODT transition", $time);
if ($time - tm_self_refresh < TXSNR)
$display ("%m: at time %t ERROR: tXSNR violation during ODT transition", $time);
if (in_self_refresh)
$display ("%m: at time %t ERROR: Illegal ODT transition during Self Refresh.", $time);
// async ODT mode applies:
// 1.) during active power down with slow exit
// 2.) during precharge power down
// 3.) if tANPD has not been satisfied
// 4.) until tAXPD has been satisfied
if ((in_power_down && (low_power || (active_bank == 0))) || (ck_cntr - ck_slow_exit_pd < TAXPD)) begin
if (ck_cntr - ck_slow_exit_pd < TAXPD)
$display ("%m: at time %t WARNING: tAXPD violation during ODT transition. Synchronous or asynchronous change in termination resistance is possible.", $time);
if (odt_in) begin
if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAONPD, 1'b1);
odt_state <= #(TAONPD) 1'b1;
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAOFPD, 1'b0);
odt_state <= #(TAOFPD) 1'b0;
end
// sync ODT mode applies:
// 1.) during normal operation
// 2.) during active power down with fast exit
end else begin
if (odt_in) begin
i = TAOND*2;
odt_pipeline[i] = 1'b1;
end else begin
i = TAOFD*2;
odt_pipeline[i] = 1'b1;
end
end
ck_odt <= ck_cntr;
end
end
if (odt_pipeline[0]) begin
odt_state = ~odt_state;
if (DEBUG) $display ("%m: at time %t INFO: Sync On Die Termination = %d", $time, odt_state);
end
end
// shift pipelines
if (|wr_pipeline || |rd_pipeline || |al_pipeline) begin
al_pipeline = al_pipeline>>1;
wr_pipeline = wr_pipeline>>1;
rd_pipeline = rd_pipeline>>1;
for (i=0; i<`MAX_PIPE; i=i+1) begin
ba_pipeline[i] = ba_pipeline[i+1];
row_pipeline[i] = row_pipeline[i+1];
col_pipeline[i] = col_pipeline[i+1];
end
end
if (|odt_pipeline) begin
odt_pipeline = odt_pipeline>>1;
end
end
// receiver(s)
task dqs_even_receiver;
input [4:0] i;
reg [71:0] bit_mask;
begin
bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
if (dqs_even[i]) begin
if (rdqs_en) begin // rdqs disables dm
dm_in_pos[i] = 1'b0;
end else begin
dm_in_pos[i] = dm_in[i];
end
dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask);
end
end
endtask
always @(posedge dqs_even[ 0]) dqs_even_receiver( 0);
always @(posedge dqs_even[ 1]) dqs_even_receiver( 1);
always @(posedge dqs_even[ 2]) dqs_even_receiver( 2);
always @(posedge dqs_even[ 3]) dqs_even_receiver( 3);
always @(posedge dqs_even[ 4]) dqs_even_receiver( 4);
always @(posedge dqs_even[ 5]) dqs_even_receiver( 5);
always @(posedge dqs_even[ 6]) dqs_even_receiver( 6);
always @(posedge dqs_even[ 7]) dqs_even_receiver( 7);
always @(posedge dqs_even[ 8]) dqs_even_receiver( 8);
always @(posedge dqs_even[ 9]) dqs_even_receiver( 9);
always @(posedge dqs_even[10]) dqs_even_receiver(10);
always @(posedge dqs_even[11]) dqs_even_receiver(11);
always @(posedge dqs_even[12]) dqs_even_receiver(12);
always @(posedge dqs_even[13]) dqs_even_receiver(13);
always @(posedge dqs_even[14]) dqs_even_receiver(14);
always @(posedge dqs_even[15]) dqs_even_receiver(15);
always @(posedge dqs_even[16]) dqs_even_receiver(16);
always @(posedge dqs_even[17]) dqs_even_receiver(17);
task dqs_odd_receiver;
input [4:0] i;
reg [71:0] bit_mask;
begin
bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
if (dqs_odd[i]) begin
if (rdqs_en) begin // rdqs disables dm
dm_in_neg[i] = 1'b0;
end else begin
dm_in_neg[i] = dm_in[i];
end
dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask);
end
end
endtask
always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0);
always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1);
always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2);
always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3);
always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4);
always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5);
always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6);
always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7);
always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8);
always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9);
always @(posedge dqs_odd[10]) dqs_odd_receiver(10);
always @(posedge dqs_odd[11]) dqs_odd_receiver(11);
always @(posedge dqs_odd[12]) dqs_odd_receiver(12);
always @(posedge dqs_odd[13]) dqs_odd_receiver(13);
always @(posedge dqs_odd[14]) dqs_odd_receiver(14);
always @(posedge dqs_odd[15]) dqs_odd_receiver(15);
always @(posedge dqs_odd[16]) dqs_odd_receiver(16);
always @(posedge dqs_odd[17]) dqs_odd_receiver(17);
// Processes to check hold and pulse width of control signals
always @(cke_in) begin
if ($time > TIH) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time);
end
if (dll_locked && ($time - tm_cke < $rtoi(TIPW*tck_avg)))
$display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW*tck_avg - $time);
tm_cke = $time;
end
always @(odt_in) begin
if (odt_en && !in_self_refresh) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time);
if (dll_locked && ($time - tm_odt < $rtoi(TIPW*tck_avg)))
$display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW*tck_avg - $time);
end
tm_odt = $time;
end
task cmd_addr_timing_check;
input i;
reg [4:0] i;
begin
if (prev_cke) begin
if ((i == 0) && ($time - tm_ck_pos < TIH)) // Always check tIH for CS#
$display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
if ((i > 0) && (cs_n_in == 1'b0) && ($time - tm_ck_pos < TIH)) // Only check tIH for cmd_addr if CS# low
$display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
if (dll_locked && ($time - tm_cmd_addr[i] < $rtoi(TIPW*tck_avg)))
$display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW*tck_avg - $time);
end
tm_cmd_addr[i] = $time;
end
endtask
always @(cs_n_in ) cmd_addr_timing_check( 0);
always @(ras_n_in ) cmd_addr_timing_check( 1);
always @(cas_n_in ) cmd_addr_timing_check( 2);
always @(we_n_in ) cmd_addr_timing_check( 3);
always @(ba_in [ 0]) cmd_addr_timing_check( 4);
always @(ba_in [ 1]) cmd_addr_timing_check( 5);
always @(ba_in [ 2]) cmd_addr_timing_check( 6);
always @(addr_in[ 0]) cmd_addr_timing_check( 7);
always @(addr_in[ 1]) cmd_addr_timing_check( 8);
always @(addr_in[ 2]) cmd_addr_timing_check( 9);
always @(addr_in[ 3]) cmd_addr_timing_check(10);
always @(addr_in[ 4]) cmd_addr_timing_check(11);
always @(addr_in[ 5]) cmd_addr_timing_check(12);
always @(addr_in[ 6]) cmd_addr_timing_check(13);
always @(addr_in[ 7]) cmd_addr_timing_check(14);
always @(addr_in[ 8]) cmd_addr_timing_check(15);
always @(addr_in[ 9]) cmd_addr_timing_check(16);
always @(addr_in[10]) cmd_addr_timing_check(17);
always @(addr_in[11]) cmd_addr_timing_check(18);
always @(addr_in[12]) cmd_addr_timing_check(19);
always @(addr_in[13]) cmd_addr_timing_check(20);
always @(addr_in[14]) cmd_addr_timing_check(21);
always @(addr_in[15]) cmd_addr_timing_check(22);
// Processes to check setup and hold of data signals
task dm_timing_check;
input i;
reg [4:0] i;
begin
if (dqs_in_valid) begin
if ($time - tm_dqs[i] < TDH)
$display ("%m: at time %t ERROR: tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time);
if (check_dm_tdipw[i]) begin
if (dll_locked && ($time - tm_dm[i] < $rtoi(TDIPW*tck_avg)))
$display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW*tck_avg - $time);
end
end
check_dm_tdipw[i] <= 1'b0;
tm_dm[i] = $time;
end
endtask
always @(dm_in[ 0]) dm_timing_check( 0);
always @(dm_in[ 1]) dm_timing_check( 1);
always @(dm_in[ 2]) dm_timing_check( 2);
always @(dm_in[ 3]) dm_timing_check( 3);
always @(dm_in[ 4]) dm_timing_check( 4);
always @(dm_in[ 5]) dm_timing_check( 5);
always @(dm_in[ 6]) dm_timing_check( 6);
always @(dm_in[ 7]) dm_timing_check( 7);
always @(dm_in[ 8]) dm_timing_check( 8);
always @(dm_in[ 9]) dm_timing_check( 9);
always @(dm_in[10]) dm_timing_check(10);
always @(dm_in[11]) dm_timing_check(11);
always @(dm_in[12]) dm_timing_check(12);
always @(dm_in[13]) dm_timing_check(13);
always @(dm_in[14]) dm_timing_check(14);
always @(dm_in[15]) dm_timing_check(15);
always @(dm_in[16]) dm_timing_check(16);
always @(dm_in[17]) dm_timing_check(17);
task dq_timing_check;
input i;
reg [6:0] i;
begin
if (dqs_in_valid) begin
if ($time - tm_dqs[i/`DQ_PER_DQS] < TDH)
$display ("%m: at time %t ERROR: tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time);
if (check_dq_tdipw[i]) begin
if (dll_locked && ($time - tm_dq[i] < $rtoi(TDIPW*tck_avg)))
$display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW*tck_avg - $time);
end
end
check_dq_tdipw[i] <= 1'b0;
tm_dq[i] = $time;
end
endtask
always @(dq_in[ 0]) dq_timing_check( 0);
always @(dq_in[ 1]) dq_timing_check( 1);
always @(dq_in[ 2]) dq_timing_check( 2);
always @(dq_in[ 3]) dq_timing_check( 3);
always @(dq_in[ 4]) dq_timing_check( 4);
always @(dq_in[ 5]) dq_timing_check( 5);
always @(dq_in[ 6]) dq_timing_check( 6);
always @(dq_in[ 7]) dq_timing_check( 7);
always @(dq_in[ 8]) dq_timing_check( 8);
always @(dq_in[ 9]) dq_timing_check( 9);
always @(dq_in[10]) dq_timing_check(10);
always @(dq_in[11]) dq_timing_check(11);
always @(dq_in[12]) dq_timing_check(12);
always @(dq_in[13]) dq_timing_check(13);
always @(dq_in[14]) dq_timing_check(14);
always @(dq_in[15]) dq_timing_check(15);
always @(dq_in[16]) dq_timing_check(16);
always @(dq_in[17]) dq_timing_check(17);
always @(dq_in[18]) dq_timing_check(18);
always @(dq_in[19]) dq_timing_check(19);
always @(dq_in[20]) dq_timing_check(20);
always @(dq_in[21]) dq_timing_check(21);
always @(dq_in[22]) dq_timing_check(22);
always @(dq_in[23]) dq_timing_check(23);
always @(dq_in[24]) dq_timing_check(24);
always @(dq_in[25]) dq_timing_check(25);
always @(dq_in[26]) dq_timing_check(26);
always @(dq_in[27]) dq_timing_check(27);
always @(dq_in[28]) dq_timing_check(28);
always @(dq_in[29]) dq_timing_check(29);
always @(dq_in[30]) dq_timing_check(30);
always @(dq_in[31]) dq_timing_check(31);
always @(dq_in[32]) dq_timing_check(32);
always @(dq_in[33]) dq_timing_check(33);
always @(dq_in[34]) dq_timing_check(34);
always @(dq_in[35]) dq_timing_check(35);
always @(dq_in[36]) dq_timing_check(36);
always @(dq_in[37]) dq_timing_check(37);
always @(dq_in[38]) dq_timing_check(38);
always @(dq_in[39]) dq_timing_check(39);
always @(dq_in[40]) dq_timing_check(40);
always @(dq_in[41]) dq_timing_check(41);
always @(dq_in[42]) dq_timing_check(42);
always @(dq_in[43]) dq_timing_check(43);
always @(dq_in[44]) dq_timing_check(44);
always @(dq_in[45]) dq_timing_check(45);
always @(dq_in[46]) dq_timing_check(46);
always @(dq_in[47]) dq_timing_check(47);
always @(dq_in[48]) dq_timing_check(48);
always @(dq_in[49]) dq_timing_check(49);
always @(dq_in[50]) dq_timing_check(50);
always @(dq_in[51]) dq_timing_check(51);
always @(dq_in[52]) dq_timing_check(52);
always @(dq_in[53]) dq_timing_check(53);
always @(dq_in[54]) dq_timing_check(54);
always @(dq_in[55]) dq_timing_check(55);
always @(dq_in[56]) dq_timing_check(56);
always @(dq_in[57]) dq_timing_check(57);
always @(dq_in[58]) dq_timing_check(58);
always @(dq_in[59]) dq_timing_check(59);
always @(dq_in[60]) dq_timing_check(60);
always @(dq_in[61]) dq_timing_check(61);
always @(dq_in[62]) dq_timing_check(62);
always @(dq_in[63]) dq_timing_check(63);
always @(dq_in[64]) dq_timing_check(64);
always @(dq_in[65]) dq_timing_check(65);
always @(dq_in[66]) dq_timing_check(66);
always @(dq_in[67]) dq_timing_check(67);
always @(dq_in[68]) dq_timing_check(68);
always @(dq_in[69]) dq_timing_check(69);
always @(dq_in[70]) dq_timing_check(70);
always @(dq_in[71]) dq_timing_check(71);
task dqs_pos_timing_check;
input i;
reg [5:0] i;
reg [3:0] j;
begin
if (dqs_in_valid && ((wdqs_pos_cntr[i] < burst_length/2) || b2b_write) && (dqs_n_en || i<18)) begin
if (dqs_in[i] ^ prev_dqs_in[i]) begin
if (dll_locked) begin
if (check_write_preamble[i]) begin
if ($time - tm_dqs_neg[i] < $rtoi(TWPRE*tck_avg))
$display ("%m: at time %t ERROR: tWPRE violation on &s bit %d", $time, dqs_string[i/18], i%18);
end else if (check_write_postamble[i]) begin
if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg))
$display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/18], i%18);
end else begin
if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg))
$display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/18], i%18);
end
end
if ($time - tm_dm[i%18] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%18] + TDS - $time);
if (!dq_out_en) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time);
check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1;
end
end
if ((wdqs_pos_cntr[i] < burst_length/2) && !b2b_write) begin
wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1;
end else begin
wdqs_pos_cntr[i] <= 1;
end
check_dm_tdipw[i%18] <= 1'b1;
check_write_preamble[i] <= 1'b0;
check_write_postamble[i] <= 1'b0;
check_write_dqs_low[i] <= 1'b0;
tm_dqs[i%18] <= $time;
end else begin
$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/18], i%18);
end
end
tm_dqss_pos[i] <= $time;
tm_dqs_pos[i] = $time;
prev_dqs_in[i] <= dqs_in[i];
end
endtask
always @(posedge dqs_in[ 0]) dqs_pos_timing_check( 0);
always @(posedge dqs_in[ 1]) dqs_pos_timing_check( 1);
always @(posedge dqs_in[ 2]) dqs_pos_timing_check( 2);
always @(posedge dqs_in[ 3]) dqs_pos_timing_check( 3);
always @(posedge dqs_in[ 4]) dqs_pos_timing_check( 4);
always @(posedge dqs_in[ 5]) dqs_pos_timing_check( 5);
always @(posedge dqs_in[ 6]) dqs_pos_timing_check( 6);
always @(posedge dqs_in[ 7]) dqs_pos_timing_check( 7);
always @(posedge dqs_in[ 8]) dqs_pos_timing_check( 8);
always @(posedge dqs_in[ 9]) dqs_pos_timing_check( 9);
always @(posedge dqs_in[10]) dqs_pos_timing_check(10);
always @(posedge dqs_in[11]) dqs_pos_timing_check(11);
always @(posedge dqs_in[12]) dqs_pos_timing_check(12);
always @(posedge dqs_in[13]) dqs_pos_timing_check(13);
always @(posedge dqs_in[14]) dqs_pos_timing_check(14);
always @(posedge dqs_in[15]) dqs_pos_timing_check(15);
always @(posedge dqs_in[16]) dqs_pos_timing_check(16);
always @(posedge dqs_in[17]) dqs_pos_timing_check(17);
always @(negedge dqs_in[18]) dqs_pos_timing_check(18);
always @(negedge dqs_in[19]) dqs_pos_timing_check(19);
always @(negedge dqs_in[20]) dqs_pos_timing_check(20);
always @(negedge dqs_in[21]) dqs_pos_timing_check(21);
always @(negedge dqs_in[22]) dqs_pos_timing_check(22);
always @(negedge dqs_in[23]) dqs_pos_timing_check(23);
always @(negedge dqs_in[24]) dqs_pos_timing_check(24);
always @(negedge dqs_in[25]) dqs_pos_timing_check(25);
always @(negedge dqs_in[26]) dqs_pos_timing_check(26);
always @(negedge dqs_in[27]) dqs_pos_timing_check(27);
always @(negedge dqs_in[28]) dqs_pos_timing_check(28);
always @(negedge dqs_in[29]) dqs_pos_timing_check(29);
always @(negedge dqs_in[30]) dqs_pos_timing_check(30);
always @(negedge dqs_in[31]) dqs_pos_timing_check(31);
always @(negedge dqs_in[32]) dqs_neg_timing_check(32);
always @(negedge dqs_in[33]) dqs_neg_timing_check(33);
always @(negedge dqs_in[34]) dqs_neg_timing_check(34);
always @(negedge dqs_in[35]) dqs_neg_timing_check(35);
task dqs_neg_timing_check;
input i;
reg [5:0] i;
reg [3:0] j;
begin
if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && check_write_dqs_high[i] && (dqs_n_en || i < 18)) begin
if (dqs_in[i] ^ prev_dqs_in[i]) begin
if (dll_locked) begin
if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
$display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/18], i%18);
if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg))
$display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/18], i%18);
end
if ($time - tm_dm[i%18] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%18] + TDS - $time);
if (!dq_out_en) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time);
check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1;
end
end
check_dm_tdipw[i%18] <= 1'b1;
check_write_dqs_high[i] <= 1'b0;
tm_dqs[i%18] <= $time;
end else begin
$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/18], i%18);
end
end
tm_dqs_neg[i] = $time;
prev_dqs_in[i] <= dqs_in[i];
end
endtask
always @(negedge dqs_in[ 0]) dqs_neg_timing_check( 0);
always @(negedge dqs_in[ 1]) dqs_neg_timing_check( 1);
always @(negedge dqs_in[ 2]) dqs_neg_timing_check( 2);
always @(negedge dqs_in[ 3]) dqs_neg_timing_check( 3);
always @(negedge dqs_in[ 4]) dqs_neg_timing_check( 4);
always @(negedge dqs_in[ 5]) dqs_neg_timing_check( 5);
always @(negedge dqs_in[ 6]) dqs_neg_timing_check( 6);
always @(negedge dqs_in[ 7]) dqs_neg_timing_check( 7);
always @(negedge dqs_in[ 8]) dqs_neg_timing_check( 8);
always @(negedge dqs_in[ 9]) dqs_neg_timing_check( 9);
always @(negedge dqs_in[10]) dqs_neg_timing_check(10);
always @(negedge dqs_in[11]) dqs_neg_timing_check(11);
always @(negedge dqs_in[12]) dqs_neg_timing_check(12);
always @(negedge dqs_in[13]) dqs_neg_timing_check(13);
always @(negedge dqs_in[14]) dqs_neg_timing_check(14);
always @(negedge dqs_in[15]) dqs_neg_timing_check(15);
always @(negedge dqs_in[16]) dqs_neg_timing_check(16);
always @(negedge dqs_in[17]) dqs_neg_timing_check(17);
always @(posedge dqs_in[18]) dqs_neg_timing_check(18);
always @(posedge dqs_in[19]) dqs_neg_timing_check(19);
always @(posedge dqs_in[20]) dqs_neg_timing_check(20);
always @(posedge dqs_in[21]) dqs_neg_timing_check(21);
always @(posedge dqs_in[22]) dqs_neg_timing_check(22);
always @(posedge dqs_in[23]) dqs_neg_timing_check(23);
always @(posedge dqs_in[24]) dqs_neg_timing_check(24);
always @(posedge dqs_in[25]) dqs_neg_timing_check(25);
always @(posedge dqs_in[26]) dqs_neg_timing_check(26);
always @(posedge dqs_in[27]) dqs_neg_timing_check(27);
always @(posedge dqs_in[28]) dqs_neg_timing_check(28);
always @(posedge dqs_in[29]) dqs_neg_timing_check(29);
always @(posedge dqs_in[30]) dqs_neg_timing_check(30);
always @(posedge dqs_in[31]) dqs_neg_timing_check(31);
always @(posedge dqs_in[32]) dqs_neg_timing_check(32);
always @(posedge dqs_in[33]) dqs_neg_timing_check(33);
always @(posedge dqs_in[34]) dqs_neg_timing_check(34);
always @(posedge dqs_in[35]) dqs_neg_timing_check(35);
endmodule
|
(* Copyright © 1998-2006
* Henk Barendregt
* Luís Cruz-Filipe
* Herman Geuvers
* Mariusz Giero
* Rik van Ginneken
* Dimitri Hendriks
* Sébastien Hinderer
* Bart Kirkels
* Pierre Letouzey
* Iris Loeb
* Lionel Mamane
* Milad Niqui
* Russell O’Connor
* Randy Pollack
* Nickolay V. Shmyrev
* Bas Spitters
* Dan Synek
* Freek Wiedijk
* Jan Zwanenburg
*
* This work is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This work is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this work; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*)
Require Export TaylorSeries.
Opaque Min Max.
(**
* Exponential and Logarithmic Functions
The main properties of the exponential and logarithmic functions.
** Properties of Exponential
Exponential is strongly extensional and well defined.
*)
Lemma Exp_strext : forall x y : IR, Exp x [#] Exp y -> x [#] y.
Proof.
intros x y H.
exact (un_op_strext_unfolded _ _ _ _ H).
Qed.
Lemma Exp_wd : forall x y : IR, x [=] y -> Exp x [=] Exp y.
Proof.
intros x y H.
unfold Exp in |- *; algebra.
Qed.
Hint Resolve Exp_wd: algebra.
Lemma Exp_zero : Exp [0] [=] [1].
Proof.
unfold Exp in |- *; simpl in |- *.
set (h := (fun n : nat => match n with | O => [1] | S p => [0] end):nat -> IR) in *.
cut (forall n : nat, h n [=] ([1][/] _[//]nring_fac_ap_zero _ n) [*]nexp _ n ([0][-][0])).
intro H.
cut (convergent h).
intro H0.
apply eq_transitive_unfolded with (series_sum h H0).
apply series_sum_wd; algebra.
unfold series_sum in |- *.
apply eq_symmetric_unfolded.
eapply eq_transitive_unfolded.
apply Lim_const.
apply Lim_seq_eq_Lim_subseq with (f := fun n : nat => S n).
auto with arith.
intro n; exists (S n); split; auto with arith.
intro n; simpl in |- *.
induction n as [| n Hrecn]; simpl in |- *; [ algebra | Step_final (OneR[+][0]) ].
apply convergent_wd with (fun n : nat =>
([1][/] _[//]nring_fac_ap_zero IR n) [*]nexp _ n ([0][-][0])).
algebra.
exact (fun_series_conv_imp_conv [0] [0] (leEq_reflexive IR [0]) Exp_ps
(Exp_conv [0] [0] (leEq_reflexive IR [0]) (compact_single_iprop realline [0] I)) [0]
(compact_single_prop [0]) (fun_series_inc_IR realline Exp_ps Exp_conv [0] I)).
simple destruct n; simpl in |- *; intros; rational.
Qed.
(** $e^1=e$#e<sup>1</sup>=e#, where [e] was defined a long time ago.
*)
Lemma Exp_one : Exp [1] [=] E.
Proof.
unfold E, Exp, e_series in |- *; simpl in |- *.
apply series_sum_wd; intro n.
astepr (([1][/] _[//]nring_fac_ap_zero IR n) [*][1]); apply mult_wdr.
astepl (([1][+][--]ZeroR) [^]n).
eapply eq_transitive_unfolded.
2: apply (one_nexp IR n).
apply nexp_wd; rational.
Qed.
Hint Resolve Exp_zero Exp_one: algebra.
(**
The exponential function is its own derivative, and continuous.
*)
Lemma Derivative_Exp : forall H, Derivative realline H Expon Expon.
Proof.
intro H.
unfold Expon, Exp_ps in |- *.
cut (fun_series_convergent_IR realline
(FPowerSeries' [0] (fun n : nat => (fun _ : nat => [1]) (S n)))).
intro H0.
eapply Derivative_wdr.
2: apply Derivative_FPowerSeries1' with (a := fun _ : nat => OneR) (Hg := H0).
FEQ.
simpl in |- *.
apply series_sum_wd; algebra.
fold Exp_ps in |- *; apply Exp_conv.
Qed.
Hint Resolve Derivative_Exp: derivate.
Lemma Continuous_Exp : Continuous realline Expon.
Proof.
apply Derivative_imp_Continuous with I Expon.
apply Derivative_Exp.
Qed.
Hint Resolve Continuous_Exp: continuous.
(**
Negative numbers are projected into the interval [[0,1]].
*)
Lemma One_less_Exp : forall x : IR, [0] [<] x -> [1] [<] Exp x.
Proof.
unfold Exp in |- *; simpl in |- *; intros x H.
unfold series_sum in |- *.
apply less_leEq_trans with ([1][+]x).
astepl (OneR[+][0]); apply plus_resp_less_lft; auto.
apply str_leEq_seq_so_leEq_Lim.
exists 2; intros i Hi.
simpl in |- *.
unfold seq_part_sum in |- *.
induction i as [| i Hreci].
elimtype False; inversion Hi.
clear Hreci.
induction i as [| i Hreci].
elimtype False; inversion Hi; inversion H1.
clear Hreci.
induction i as [| i Hreci].
simpl in |- *.
apply eq_imp_leEq; rational.
eapply leEq_transitive.
apply Hreci; auto with arith.
clear Hreci.
eapply leEq_wdl.
2: apply cm_rht_unit_unfolded.
set (j := S (S i)) in *; clearbody j.
simpl in |- *; apply plus_resp_leEq_lft.
apply less_leEq; apply mult_resp_pos.
apply recip_resp_pos; apply pos_nring_fac.
astepr ((x[+][--][0]) [^]j); apply nexp_resp_pos.
rstepr x; auto.
Qed.
Lemma One_leEq_Exp : forall x : IR, [0] [<=] x -> [1] [<=] Exp x.
Proof.
intros x H.
astepl (Exp [0]).
apply resp_leEq_char; auto.
algebra.
intro H0; astepl OneR.
apply One_less_Exp; auto.
Qed.
Lemma Exp_pos' : forall x : IR, [0] [<] x -> [0] [<] Exp x.
Proof.
intros x H.
apply less_leEq_trans with OneR.
apply pos_one.
apply One_leEq_Exp; apply less_leEq; auto.
Qed.
(**
Exponential is the unique function which evaluates to 1 at 0 and is
its own derivative.
*)
Lemma Exp_unique_lemma : forall H F,
Derivative realline H F F -> forall n, Derivative_n n realline H F F.
Proof.
intros H F H0 n; induction n as [| n Hrecn].
apply Derivative_n_O; Included.
apply Derivative_n_plus with n 1 F; auto.
apply Derivative_n_1; auto.
Qed.
Lemma Exp_bnd : Taylor_bnd (fun n => Expon).
Proof.
apply bnd_imp_Taylor_bnd with Expon.
intros n x Hx Hx'; apply eq_imp_leEq; algebra.
Contin.
Included.
Qed.
Lemma Exp_unique : forall F, Derivative realline I F F -> (forall H1, F [0] H1 [=] [1]) -> Feq realline Expon F.
Proof.
intros F H H0.
cut (forall n : nat, Derivative_n n realline I Expon Expon).
intro derF.
cut (Taylor_bnd (fun n : nat => Expon)); [ intro bndf | apply Exp_bnd ].
cut (forall n : nat, Derivative_n n realline I F F).
intros derG.
apply Taylor_unique_crit with (f := fun _ : nat => Expon) (a := ZeroR) (g := fun n : nat => F)
(bndf := bndf) (derF := derF); auto.
apply bnd_imp_Taylor_bnd with F.
intros; apply eq_imp_leEq; algebra.
apply Derivative_n_imp_Continuous with I 1 F; auto with arith.
intro n.
change (included realline (Dom F)) in |- *.
apply Derivative_n_imp_inc with I 1 F; auto with arith.
intros; astepr OneR.
astepr (Exp [0]).
Opaque Expon.
unfold Exp in |- *; simpl in |- *; algebra.
Transparent Expon.
apply Taylor_Series_conv_to_fun; auto.
apply Exp_unique_lemma; auto.
apply Exp_unique_lemma; apply Derivative_Exp.
Qed.
Opaque Expon.
Lemma Exp_plus_pos : forall z, [0] [<] z -> forall x, Exp (x[+]z) [=] Exp x[*]Exp z.
Proof.
intros z H x.
set (F := ([1][/] _[//]pos_ap_zero _ _ (Exp_pos' _ H)) {**} (Expon[o]FId{+}[-C-]z)) in *.
apply eq_symmetric_unfolded.
rstepr ((Exp (x[+]z) [/] _[//]pos_ap_zero _ _ (Exp_pos' _ H)) [*]Exp z).
apply mult_wdl.
unfold Exp at 1 in |- *.
simpl in |- *.
assert (H0 : Dom F x). repeat split; exists (I, I); apply Exp_domain.
apply eq_transitive_unfolded with (Part F x H0).
2: unfold F, Exp in |- *; simpl in |- *; rational.
apply Feq_imp_eq with realline.
apply Exp_unique.
assert (H1 : Derivative realline I Expon Expon). apply Derivative_Exp.
unfold F in |- *; Derivative_Help.
apply eq_imp_Feq.
apply included_FScalMult; apply included_FMult.
apply included_FComp; Included.
Included.
apply included_FScalMult; apply included_FComp; Included.
intros; simpl in |- *; rational.
apply Derivative_scal.
apply Derivative_comp with realline I; Deriv.
red in |- *; intros a b Hab H2.
exists (a[+]z); exists (b[+]z[+][1]).
cut (a[+]z [<] b[+]z[+][1]).
intro H3.
exists H3; repeat split; simpl in |- *; try rename H4 into X; elim X; try intros H5 H6.
apply plus_resp_leEq; auto.
apply leEq_transitive with (b[+]z).
apply plus_resp_leEq; auto.
apply less_leEq; apply less_plusOne.
apply leEq_less_trans with (b[+]z).
apply plus_resp_leEq; auto.
apply less_plusOne.
intro H1; simpl in |- *.
rational.
split.
Qed.
(** The usual rules for computing the exponential of a sum. *)
Lemma Exp_plus : forall x y : IR, Exp (x[+]y) [=] Exp x[*]Exp y.
Proof.
intros x y.
set (z := Max [1] ([1][-]y)) in *.
cut ([0] [<] z).
intro H.
apply mult_cancel_rht with (Exp z).
apply Greater_imp_ap; apply Exp_pos'; auto.
eapply eq_transitive_unfolded.
apply eq_symmetric_unfolded; apply Exp_plus_pos; auto.
astepl (Exp (x[+] (y[+]z))).
eapply eq_transitive_unfolded.
apply Exp_plus_pos.
2: astepr (Exp x[*] (Exp y[*]Exp z)); apply mult_wdr; apply Exp_plus_pos; auto.
unfold z in |- *.
apply shift_less_plus'; astepl ( [--]y).
apply less_leEq_trans with ([1][-]y).
eapply less_wdr.
apply less_plusOne.
rational.
apply rht_leEq_Max.
apply less_leEq_trans with OneR.
apply pos_one.
unfold z in |- *; apply lft_leEq_Max.
Qed.
Hint Resolve Exp_plus: algebra.
Lemma Exp_plus' : forall x y z : IR, z [=] x[+]y -> Exp z [=] Exp x[*]Exp y.
Proof.
intros x y z H.
Step_final (Exp (x[+]y)).
Qed.
Lemma Exp_inv_char : forall x : IR, Exp x[*]Exp [--]x [=] [1].
Proof.
intro x.
astepr (Exp [0]).
apply eq_symmetric_unfolded; apply Exp_plus'.
algebra.
Qed.
Hint Resolve Exp_inv_char: algebra.
(** The exponential of any number is always positive---and thus apart
from zero.
*)
Lemma Exp_pos : forall x : IR, [0] [<] Exp x.
Proof.
intro x.
cut (Exp x[*]Exp [--]x [=] [1]); [ intro | apply Exp_inv_char ].
cut ( [--][1] [<=] OneR).
intro H0.
cut (Continuous_I H0 Expon).
intro H1.
elim H1; intros Hinc contExp.
elim (contExp _ (pos_half IR)); clear H1 Hinc contExp; intros d H1 H2.
cut ([0] [<] Min d [1]); [ intro H3 | apply less_Min; auto; apply pos_one ].
cut ( [--] (Min d [1]) [<] [0]); [ intro H4 | astepr ( [--]ZeroR); apply inv_resp_less; auto ].
elim (less_cotransitive _ _ _ H4 x); intro H5.
elim (less_cotransitive _ _ _ H3 x); intro H6.
apply Exp_pos'; auto.
apply less_leEq_trans with (Half:IR).
apply pos_half.
apply leEq_wdl with ([1][-] (Half:IR)).
2: unfold Half in |- *; rational.
apply shift_minus_leEq; apply shift_leEq_plus'.
astepl (Exp [0][-]Exp x).
eapply leEq_transitive.
apply leEq_AbsIR.
simpl in |- *; apply H2.
split; apply less_leEq.
astepr ( [--]ZeroR); apply inv_resp_less; apply pos_one.
apply pos_one.
split; apply less_leEq.
apply leEq_less_trans with ( [--] (Min d [1])).
apply inv_resp_leEq; apply Min_leEq_rht.
auto.
apply less_leEq_trans with (Min d [1]).
auto.
apply Min_leEq_rht.
astepl (AbsIR [--]x).
eapply leEq_wdl.
2: apply AbsIR_inv.
simpl in |- *; unfold ABSIR in |- *; apply less_leEq; apply Max_less.
apply less_leEq_trans with (Min d [1]); auto; apply Min_leEq_lft.
apply less_leEq_trans with ( [--][--] (Min d [1])).
apply inv_resp_less; auto.
astepl (Min d [1]); apply Min_leEq_lft.
clear H4 H3 H2 H1 d H0.
apply mult_cancel_less with (Exp [--]x).
apply Exp_pos'.
astepl ( [--]ZeroR); apply inv_resp_less; auto.
astepl ZeroR; astepr OneR; apply pos_one.
apply included_imp_Continuous with realline; [ apply Continuous_Exp | repeat split ].
apply leEq_transitive with ZeroR; [ astepr ( [--]ZeroR) | apply less_leEq; apply pos_one ].
apply inv_resp_leEq; apply less_leEq; apply pos_one.
Qed.
Lemma Exp_ap_zero : forall x : IR, Exp x [#] [0].
Proof.
intro; apply Greater_imp_ap; apply Exp_pos.
Qed.
Lemma pos_E : [0] [<] E.
Proof.
astepr (Exp [1]).
apply Exp_pos.
Qed.
(**
And the rules for the exponential of differences.
*)
Lemma Exp_inv : forall x : IR, Exp [--]x [=] ([1][/] _[//]Exp_ap_zero x).
Proof.
intro x.
apply mult_cancel_lft with (Exp x).
apply Exp_ap_zero.
rstepr OneR; algebra.
Qed.
Hint Resolve Exp_inv: algebra.
Lemma Exp_minus : forall x y : IR, Exp (x[-]y) [=] (Exp x[/] _[//]Exp_ap_zero y).
Proof.
intros x y.
unfold cg_minus in |- *; astepl (Exp x[*]Exp [--]y).
rstepr (Exp x[*] ([1][/] _[//]Exp_ap_zero y)).
algebra.
Qed.
Hint Resolve Exp_minus: algebra.
Lemma Exp_inv' : forall x y : IR, y [=] [--]x -> Exp y [=] ([1][/] _[//]Exp_ap_zero x).
Proof.
intros x y Hxy.
Step_final (Exp [--]x).
Qed.
Lemma Exp_minus' : forall x y z : IR, z [=] x[-]y -> Exp z [=] (Exp x[/] Exp y[//]Exp_ap_zero _).
Proof.
intros x y z H.
Step_final (Exp (x[-]y)).
Qed.
(** Exponential is a monotonous function. *)
Lemma Exp_less_One : forall x : IR, x [<] [0] -> Exp x [<] [1].
Proof.
intros x H.
astepr (Exp x[*]Exp [--]x).
astepl (Exp x[*][1]).
apply mult_resp_less_lft.
apply One_less_Exp; astepl ( [--]ZeroR); apply inv_resp_less; auto.
apply Exp_pos.
Qed.
Lemma Exp_leEq_One : forall x : IR, x [<=] [0] -> Exp x [<=] [1].
Proof.
intros x H.
astepr (Exp x[*]Exp [--]x).
astepl (Exp x[*][1]).
apply mult_resp_leEq_lft.
apply One_leEq_Exp; astepl ( [--]ZeroR); apply inv_resp_leEq; auto.
apply less_leEq; apply Exp_pos.
Qed.
Lemma Exp_resp_less : forall x y : IR, x [<] y -> Exp x [<] Exp y.
Proof.
intros x y H.
apply less_wdr with (Exp (x[+] (y[-]x))).
2: apply Exp_wd; rational.
astepr (Exp x[*]Exp (y[-]x)).
astepl (Exp x[*][1]).
apply mult_resp_less_lft.
apply One_less_Exp.
apply shift_less_minus; astepl x; auto.
apply Exp_pos.
Qed.
Lemma Exp_resp_leEq : forall x y : IR, x [<=] y -> Exp x [<=] Exp y.
Proof.
intros x y; apply resp_leEq_char.
algebra.
intro H; apply Exp_resp_less; auto.
Qed.
(**
** Properties of Logarithm
The logarithm is a continuous function with derivative [[1][/]x].
*)
Lemma Derivative_Log : forall H, Derivative (openl [0]) H Logarithm {1/}FId.
Proof.
intro H.
unfold Logarithm in |- *.
Deriv.
Qed.
Hint Resolve Derivative_Log: derivate.
Lemma Continuous_Log : Continuous (openl [0]) Logarithm.
Proof.
apply Derivative_imp_Continuous with I ( {1/} (Fid IR)).
Deriv.
Qed.
Hint Resolve Continuous_Log: continuous.
(** Logarithm of [[1]]. *)
Lemma Log_one : forall H, Log [1] H [=] [0].
Proof.
intro H; unfold Log in |- *; simpl in |- *.
apply Integral_empty; algebra.
Qed.
Hint Resolve Log_one: algebra.
(** The logarithm is (strongly) extensional. *)
Lemma Log_strext : forall (x y : IR) Hx Hy, Log x Hx [#] Log y Hy -> x [#] y.
Proof.
intros x y Hx Hy H.
unfold Log in H.
exact (pfstrx _ _ _ _ _ _ H).
Qed.
Lemma Log_wd : forall (x y : IR) Hx Hy, x [=] y -> Log x Hx [=] Log y Hy.
Proof.
intros x y Hx Hy H.
unfold Log in |- *; algebra.
Qed.
Hint Resolve Log_wd: algebra.
(** The rule for the logarithm of the product. *)
Lemma Log_mult : forall x y Hx Hy Hxy, Log (x[*]y) Hxy [=] Log x Hx[+]Log y Hy.
Proof.
intros x y Hx Hy Hxy.
set (G := (Logarithm[o]y{**}FId) {-}[-C-] (Log y Hy)) in *.
cut (proper (openl [0])); [ intro H | simpl in |- *; auto ].
cut (Derivative (openl [0]) H G {1/}FId).
intro H0.
cut (Derivative (openl [0]) H Logarithm {1/}FId); [ intro H1 | Deriv ].
elim (FTC2 (openl [0]) {1/}FId log_defn_lemma [1] (pos_one IR) H G H0); intros c Hc.
fold Logarithm in Hc.
elim Hc; intros H2' H2''.
elim H2''; intros H2 H5.
clear Hc H2 H2' H2''.
cut (c [=] [0]).
intro H2.
cut (forall z w t : IR, w[-] (z[-]t) [=] [0] -> z [=] w[+]t).
intro H3.
apply H3; clear H3.
astepr c; clear H2.
cut (Dom (Logarithm{-}G) x); [ intro H2 | repeat split; simpl in |- *; auto ].
eapply eq_transitive_unfolded.
2: apply (H5 x Hx H2 I).
Opaque Logarithm.
simpl in |- *; algebra.
clear H5.
exists (I, I); apply mult_resp_pos; auto.
intros z w t H3.
rstepl (z[-]t[+]t).
apply bin_op_wd_unfolded.
2: algebra.
apply cg_inv_unique_2.
astepr ( [--]ZeroR).
rstepl ( [--] (w[-] (z[-]t))).
apply un_op_wd_unfolded; auto.
cut (Dom (Logarithm{-}G) [1]); [ intro H2 | repeat split; simpl in |- *; auto ].
apply eq_symmetric_unfolded; eapply eq_transitive_unfolded.
2: apply (H5 [1] (pos_one IR) H2 I).
simpl in |- *.
rstepl ([0][-] (Log y Hy[-]Log y Hy)).
algebra.
Transparent Logarithm.
simpl in |- *; apply pos_one.
exists (I, I); simpl in |- *; apply mult_resp_pos; auto; apply pos_one.
unfold G in |- *.
cut (Derivative (openl [0]) H Logarithm {1/}FId);
[ intro H0 | unfold Logarithm in |- *; apply FTC1 ].
Derivative_Help.
apply eq_imp_Feq.
repeat split.
exists (I, I); simpl in |- *.
repeat split.
intros; apply Greater_imp_ap; apply mult_resp_pos; auto.
Included.
intros; simpl in |- *; rational.
apply Derivative_minus.
apply Derivative_comp with (openl [0]) H; Deriv.
clear H0; red in |- *; intros a b Hab H0.
simpl in |- *; exists (y[*]a); exists (y[*]b[+][1]).
cut (y[*]a [<] y[*]b[+][1]).
intro H1; exists H1; split.
intros x0 H2.
elim H2; intros H3 H4; simpl in |- *.
apply less_leEq_trans with (y[*]a).
apply mult_resp_pos; auto.
apply H0; apply compact_inc_lft.
auto.
intros x0 Hx0 H2; elim H2; intros H3 H4; split.
apply mult_resp_leEq_lft; auto.
apply less_leEq; auto.
apply leEq_transitive with (y[*]b).
apply mult_resp_leEq_lft; auto.
apply less_leEq; auto.
apply less_leEq; apply less_plusOne.
apply leEq_less_trans with (y[*]b).
apply mult_resp_leEq_lft; auto.
apply less_leEq; auto.
apply less_plusOne.
Deriv.
Qed.
Hint Resolve Log_mult: algebra.
Lemma Log_mult' : forall x y z Hx Hy Hz, z [=] x[*]y -> Log z Hz [=] Log x Hx[+]Log y Hy.
Proof.
intros.
Step_final (Log (x[*]y) (mult_resp_pos _ _ _ Hx Hy)).
Qed.
Lemma Log_nexp : forall x n Hx Hxn, Log (x[^]n) Hxn [=] (nring n)[*]Log x Hx.
Proof.
induction n.
intros Hx Hn.
simpl.
rstepr ([0]:IR).
apply Log_one.
intros Hx Hn.
assert (X:[0][<]x[^]n).
apply nexp_resp_pos.
assumption.
stepl (Log _ X[+]Log x Hx); [| apply eq_symmetric; apply (Log_mult _ _ X Hx)].
astepr ((nring n [+] [1])[*]Log x Hx).
rstepr (nring n[*]Log x Hx[+]Log x Hx).
apply bin_op_wd_unfolded; try apply eq_reflexive.
apply IHn.
Qed.
Hint Resolve Log_nexp: algebra.
(** A characterization of the domain of the logarithm. *)
Lemma Log_domain : forall x : IR, [0] [<] x -> Dom Logarithm x.
Proof.
intros; auto.
Qed.
Opaque Expon Logarithm.
(** $\log(e^x)=x$#log(e<sup>x</sup>)=x# for all [x], both as a
numerical and as a functional equation.
*)
Lemma Log_Exp_inv : Feq realline (Logarithm[o]Expon) FId.
Proof.
apply Feq_criterium with I (Fconst (S:=IR) [1]) ZeroR.
cut (Derivative realline I Expon Expon); [ intro H | apply Derivative_Exp ].
cut (Derivative (openl [0]) I Logarithm {1/}FId); [ intro H0 | apply Derivative_Log ].
Derivative_Help.
apply eq_imp_Feq.
split; auto.
exists I.
split; auto.
intro; simpl in |- *; apply Greater_imp_ap.
apply less_wdr with (Exp x); [ apply Exp_pos | simpl in |- *; algebra ].
Included.
intros; simpl in |- *; rational.
apply Derivative_comp with (openl [0]) I; Deriv.
red in |- *; intros a b Hab H1.
exists (Exp a); exists (Exp b[+][1]); exists
(leEq_less_trans _ _ _ _ (Exp_resp_leEq _ _ Hab) (less_plusOne _ _)).
split.
red in |- *; intros x H2.
elim H2; intros H3 H4.
simpl in |- *.
apply less_leEq_trans with (Exp a); auto.
apply Exp_pos.
intros x Hx H2; elim H2; intros H3 H4; split.
apply leEq_wdr with (Exp x).
apply Exp_resp_leEq; auto.
simpl in |- *; algebra.
apply less_leEq; apply leEq_less_trans with (Exp b).
apply leEq_wdl with (Exp x).
apply Exp_resp_leEq; auto.
simpl in |- *; algebra.
apply less_plusOne.
Deriv.
split.
intros; simpl in |- *.
astepr (Log [1] (pos_one _)).
unfold Log in |- *; apply pfwdef.
astepr (Exp [0]).
simpl in |- *; algebra.
Qed.
Lemma Log_Exp : forall x H, Log (Exp x) H [=] x.
Proof.
intros x H.
cut (Dom (Logarithm[o]Expon) x).
intro H0.
unfold Log in |- *; simpl in |- *; apply eq_transitive_unfolded with (Part _ _ H0).
simpl in |- *; algebra.
astepr (Part FId x I).
apply Feq_imp_eq with realline.
apply Log_Exp_inv.
split.
exists I.
apply Log_domain.
apply less_wdr with (Exp x); auto.
simpl in |- *; algebra.
Qed.
Transparent Logarithm.
Hint Resolve Log_Exp: algebra.
Lemma Exp_Log_lemma : forall x y Hx Hy, [0] [=] Log y Hy[-]Log x Hx -> y [<=] x.
Proof.
intros x y Hx Hy H; rewrite -> leEq_def; intro H0.
cut ((y[-]x[/] _[//]pos_ap_zero _ _ Hy) [<=] [0]).
intro H1.
apply less_irreflexive_unfolded with (x := x).
apply less_leEq_trans with y; auto.
astepr (x[+][0]); apply shift_leEq_plus'.
rstepl ((y[-]x[/] _[//]pos_ap_zero _ _ Hy) [*]y).
apply shift_mult_leEq with (pos_ap_zero _ _ Hy); auto.
rstepr ZeroR; auto.
astepr (Log y Hy[-]Log x Hx).
unfold Log in |- *; simpl in |- *.
apply leEq_wdr with (Integral (prim_lemma _ _ log_defn_lemma x Hx y Hy)).
2: rstepl (Integral (prim_lemma _ _ log_defn_lemma [1] (pos_one _) x Hx) [+]
Integral (prim_lemma _ _ log_defn_lemma x Hx y Hy) [-]
Integral (prim_lemma _ _ log_defn_lemma [1] (pos_one _) x Hx)).
2: apply cg_minus_wd; algebra.
2: apply eq_symmetric_unfolded; apply Integral_plus_Integral with (Min3_leEq_Max3 [1] y x).
2: apply included_imp_Continuous with (openl [0]);
[ apply log_defn_lemma | intros x0 H1; inversion_clear H1 ].
2: simpl in |- *; apply less_leEq_trans with (Min (Min [1] y) x); auto;
repeat apply less_Min; auto; apply pos_one.
cut (Continuous_I (less_leEq _ _ _ H0) {1/}FId).
intro H1.
apply leEq_wdr with (integral _ _ _ _ H1).
2: apply eq_symmetric_unfolded; apply Integral_integral.
rstepl (([1][/] _[//]pos_ap_zero _ _ Hy) [*] (y[-]x)).
apply lb_integral.
intros x0 H2 Hx0; simpl in |- *.
elim H2; intros H3 H4; apply recip_resp_leEq; auto.
apply less_leEq_trans with x; auto.
apply included_imp_Continuous with (openl [0]); [ apply log_defn_lemma | red in |- *; intros x0 X ].
inversion_clear X; simpl in |- *; apply less_leEq_trans with x; auto.
Qed.
(** The converse expression. *)
Lemma Exp_Log : forall x H, Exp (Log x H) [=] x.
Proof.
intros x H.
set (y := Exp (Log x H)) in *.
cut ([0] [<] y); [ intro H0 | unfold y in |- *; apply Exp_pos ].
cut (Log y H0 [=] Log x H); [ intro H1 | unfold y in |- *; algebra ].
cut ([0] [=] Log y H0[-]Log x H);
[ clear H1; intro H1 | apply eq_symmetric_unfolded; apply x_minus_x; auto ].
apply leEq_imp_eq.
apply Exp_Log_lemma with H H0; auto.
apply Exp_Log_lemma with H0 H.
astepl ( [--]ZeroR); rstepr ( [--] (Log y H0[-]Log x H)); algebra.
Qed.
Hint Resolve Exp_Log: algebra.
(** Exponential and logarithm are injective. *)
Lemma Exp_cancel : forall x y : IR, Exp x [=] Exp y -> x [=] y.
Proof.
intros.
astepl (Log (Exp x) (Exp_pos x)); Step_final (Log (Exp y) (Exp_pos y)).
Qed.
Lemma Log_cancel : forall (x y : IR) Hx Hy, Log x Hx [=] Log y Hy -> x [=] y.
Proof.
intros.
astepl (Exp (Log x Hx)); Step_final (Exp (Log y Hy)).
Qed.
Opaque Logarithm.
(** And the final characterization as inverse functions. *)
Lemma Exp_Log_inv : Feq (openl [0]) (Expon[o]Logarithm) FId.
Proof.
apply eq_imp_Feq.
red in |- *; intros x H.
simpl in H; exists H; apply Exp_domain.
Included.
intros x H Hx Hx'; simpl in |- *.
astepr (Exp (Log x H)).
unfold Log in |- *; simpl in |- *; algebra.
Qed.
Lemma Log_E : forall He, Log E He [=] [1].
Proof.
intro.
Step_final (Log (Exp [1]) (Exp_pos [1])).
Qed.
Hint Resolve Log_E: algebra.
(** Several rules regarding inequalities. *)
Lemma Log_cancel_less : forall x y Hx Hy, Log x Hx [<] Log y Hy -> x [<] y.
Proof.
intros x y Hx Hy H.
astepl (Exp (Log x Hx)).
astepr (Exp (Log y Hy)).
apply Exp_resp_less; auto.
Qed.
Lemma Log_cancel_leEq : forall x y Hx Hy, Log x Hx [<=] Log y Hy -> x [<=] y.
Proof.
intros x y Hx Hy H.
astepl (Exp (Log x Hx)).
astepr (Exp (Log y Hy)).
apply Exp_resp_leEq; auto.
Qed.
Lemma Log_resp_less : forall (x y : IR) Hx Hy, x [<] y -> Log x Hx [<] Log y Hy.
Proof.
intros x y Hx Hy H.
unfold Log in |- *; apply Derivative_imp_resp_less with (openl [0]) I ( {1/} (Fid IR));
simpl in |- *; auto.
apply Derivative_Log.
intro contF.
apply less_wdr with ([1][/] _[//]pos_ap_zero _ _ Hy).
apply recip_resp_pos; auto.
apply glb_charact.
split.
intros z Hz.
elim Hz; intros t H1.
elim H1; intros H2 H3.
elim H3; clear Hz H1 H3; intros H1 H3.
assert (H0 := H3 H1); simpl in H0.
astepr ([1][/] t[//]ext2 (P:=fun _ : IR => True) H1).
elim H2; intros HMin HMax.
apply recip_resp_leEq; auto.
apply less_leEq_trans with (Min x y); auto.
apply less_Min; auto.
apply leEq_wdr with (Max x y); auto.
apply leEq_imp_Max_is_rht; apply less_leEq; auto.
intros e He.
exists ([1][/] _[//]pos_ap_zero _ _ Hy).
exists y.
split.
split; [ apply Min_leEq_rht | apply rht_leEq_Max ].
repeat split.
intro; simpl in |- *; apply pos_ap_zero; auto.
simpl in |- *; algebra.
astepl ZeroR; auto.
Qed.
Lemma Log_resp_leEq : forall (x y : IR) Hx Hy, x [<=] y -> Log x Hx [<=] Log y Hy.
Proof.
intros x y Hx Hy; apply resp_leEq_char' with (P := fun x : IR => [0] [<] x).
algebra.
apply Log_resp_less.
Qed.
Lemma Exp_cancel_less : forall x y, Exp x [<] Exp y -> x [<] y.
Proof.
intros x y H.
astepl (Log (Exp x) (Exp_pos x)).
astepr (Log (Exp y) (Exp_pos y)).
apply Log_resp_less; auto.
Qed.
Lemma Exp_cancel_leEq : forall x y : IR, Exp x [<=] Exp y -> x [<=] y.
Proof.
intros x y H.
astepl (Log (Exp x) (Exp_pos x)).
astepr (Log (Exp y) (Exp_pos y)).
apply Log_resp_leEq; auto.
Qed.
Lemma Log_less_Zero : forall (x : IR) Hx, x [<] [1] -> Log x Hx [<] [0].
Proof.
intros x Hx H.
astepr (Log (Exp [0]) (Exp_pos [0])).
apply Log_resp_less.
astepr OneR; auto.
Qed.
Lemma Log_leEq_Zero : forall (x : IR) Hx, x [<=] [1] -> Log x Hx [<=] [0].
Proof.
intros x Hx H.
astepr (Log (Exp [0]) (Exp_pos [0])).
apply Log_resp_leEq.
astepr OneR; auto.
Qed.
Lemma Zero_less_Log : forall (x : IR) Hx, [1] [<] x -> [0] [<] Log x Hx.
Proof.
intros x Hx H.
astepl (Log (Exp [0]) (Exp_pos [0])).
apply Log_resp_less.
astepl OneR; auto.
Qed.
Lemma Zero_leEq_Log : forall (x : IR) Hx, [1] [<=] x -> [0] [<=] Log x Hx.
Proof.
intros x Hx H.
astepl (Log (Exp [0]) (Exp_pos [0])).
apply Log_resp_leEq.
astepl OneR; auto.
Qed.
(** Finally, rules for logarithm of quotients. *)
Lemma Log_recip_char : forall x Hx Hx' Hx'', Log ([1][/] x[//]Hx) Hx'[+]Log x Hx'' [=] [0].
Proof.
intros x Hx Hx' Hx''.
astepl (Log _ (mult_resp_pos _ _ _ Hx' Hx'')).
astepr (Log _ (pos_one IR)).
apply Log_wd; rational.
Qed.
Lemma Log_recip : forall x Hx Hx' Hx'', Log ([1][/] x[//]Hx) Hx' [=] [--] (Log x Hx'').
Proof.
intros x Hx Hx' Hx''.
apply cg_inv_unique'; apply Log_recip_char.
Qed.
Hint Resolve Log_recip: algebra.
Lemma Log_recip' : forall x y Hx Hx' Hy, y [=] ([1][/] x[//]Hx) -> Log y Hy [=] [--] (Log x Hx').
Proof.
intros x y Hx Hx' Hy H.
Step_final (Log ([1][/] _[//]Hx) (recip_resp_pos _ _ Hx Hx')).
Qed.
Lemma Log_div : forall x y Hx Hy Hy' Hxy, Log (x[/] y[//]Hy') Hxy [=] Log x Hx[-]Log y Hy.
Proof.
intros x y Hx Hy Hy' Hxy.
unfold cg_minus in |- *.
apply eq_transitive_unfolded with (Log _ (mult_resp_pos _ _ _ Hx (recip_resp_pos _ _ Hy' Hy))).
apply Log_wd; rational.
Step_final (Log _ Hx[+]Log _ (recip_resp_pos _ _ Hy' Hy)).
Qed.
Hint Resolve Log_div: algebra.
Lemma Log_div' : forall x y z Hx Hy Hy' Hz,
z [=] (x[/] y[//]Hy') -> Log z Hz [=] Log x Hx[-]Log y Hy.
Proof.
intros x y z Hx Hy Hy' Hz H.
Step_final (Log _ (div_resp_pos _ _ _ Hy' Hy Hx)).
Qed.
Lemma Log_zexp : forall x n Hx Hx0 Hxn, Log ((x[//]Hx0)[^^]n) Hxn [=] (zring n)[*]Log x Hx.
Proof.
intros x [|n|n] Hx Hx0 Hxn.
simpl.
rstepr ([0]:IR).
algebra.
assert (X:[0][<]x[^](nat_of_P n)).
astepr ((x[//]Hx0)[^^]n).
assumption.
change (Log (x[^](nat_of_P n)) Hxn[=]zring (R:=IR) n[*]Log x Hx).
astepl (nring (nat_of_P n)[*]Log x Hx).
apply mult_wdl.
apply eq_symmetric.
rewrite <- inject_nat_convert.
refine (zring_plus_nat IR (nat_of_P n)).
simpl.
change (Log (([1][/]x[//]Hx0)[^](nat_of_P n)) Hxn[=][--](zring n)[*]Log x Hx).
assert (X:[0][<]([1][/]x[//]Hx0)).
apply recip_resp_pos.
assumption.
astepl ((nring (nat_of_P n))[*](Log _ X)).
astepl ((nring (nat_of_P n))[*]([--](Log _ Hx))).
rstepl ([--](nring (nat_of_P n))[*](Log x Hx)).
apply mult_wdl.
apply un_op_wd_unfolded.
rewrite <- inject_nat_convert.
apply eq_symmetric.
refine (zring_plus_nat IR (nat_of_P n)).
Qed.
Hint Resolve Log_zexp: algebra.
Section Log_Series.
Definition Log_series_coef (n:nat) :=
match n with
| O => [0]
| (S n') => ([--][1])[^](S (S n'))[/](nring (S n'))[//]nringS_ap_zero IR n'
end.
Definition Log_ps := FPowerSeries [1] Log_series_coef.
Lemma Log_series_convergent_IR : fun_series_convergent_IR (olor [0] Two) Log_ps.
Proof.
intros a b Hab Hinc.
apply fun_ratio_test_conv.
unfold Log_ps; unfold FPowerSeries; Contin.
exists 1.
pose (c:=Max (AbsIR (a[-][1])) (AbsIR (b[-][1]))).
assert (Z0:c[<][1]).
unfold c.
destruct (Hinc _ (compact_inc_lft _ _ Hab)).
destruct (Hinc _ (compact_inc_rht _ _ Hab)).
apply Max_less; apply AbsIR_less; first [apply shift_minus_less; rstepr (Two:IR)
|apply shift_less_minus; rstepl ([0]:IR)]; assumption.
assert (Z1:[0][<=]c).
unfold c.
eapply leEq_transitive.
apply AbsIR_nonneg.
apply lft_leEq_Max.
exists c.
assumption.
split.
assumption.
intros x [Hx0 Hx1] n Hn Hx Hx'.
destruct n.
elimtype False; auto with *.
unfold Log_ps, FPowerSeries, Log_series_coef.
generalize (nringS_ap_zero IR (S n)).
generalize (nringS_ap_zero IR (n)).
intros Y0 Y1.
stepl ( (nexp IR (S (S n)) (AbsIR (x[-][1])))[/]nring (R:=IR) (S (S n))[//]Y1).
apply shift_div_leEq.
apply nring_pos; auto with *.
stepr ((((nexp IR (S n) (AbsIR (x[-][1]))[*]c)[*](nring (R:=IR) (S (S n))))[/]nring (R:=IR) (S n)[//]Y0)).
apply shift_leEq_div.
apply nring_pos; auto with *.
apply mult_resp_leEq_both.
apply (nexp_resp_nonneg _ (AbsIR (x[-][1])) (S (S n))).
apply AbsIR_nonneg.
apply nring_nonneg; auto with *.
change (nexp IR (S (S n)) (AbsIR (x[-][1])))
with ((nexp IR (S n) (AbsIR (x[-][1])))[*](AbsIR (x[-][1]))).
apply mult_resp_leEq_lft.
apply AbsSmall_imp_AbsIR.
split.
apply shift_zero_leEq_minus'.
rstepr (c[-]([--](x[-][1]))).
apply shift_zero_leEq_minus.
unfold c.
eapply leEq_transitive;[|apply lft_leEq_Max].
eapply leEq_transitive;[|apply inv_leEq_AbsIR].
apply inv_resp_leEq.
apply minus_resp_leEq.
assumption.
unfold c.
eapply leEq_transitive;[|apply rht_leEq_Max].
eapply leEq_transitive;[|apply leEq_AbsIR].
apply minus_resp_leEq.
assumption.
apply (nexp_resp_nonneg _ (AbsIR (x[-][1])) (S n)).
apply AbsIR_nonneg.
apply nring_leEq; auto with *.
rstepl (c[*](nexp IR (S n) (AbsIR (x[-][1]))[/]
nring (R:=IR) (S n)[//]Y0)[*]nring (R:=IR) (S (S n))).
apply mult_wdl.
apply mult_wdr.
stepl (AbsIR ((x[-][1])[^](S n))[/]_[//](AbsIR_resp_ap_zero _ Y0)).
eapply eq_transitive.
apply eq_symmetric.
apply (AbsIR_division ((x[-][1])[^]S n) _ Y0).
stepr (AbsIR (([--][1])[^](S (S n)))[*]AbsIR ((x[-][1])[^]S n[/]nring (R:=IR) (S n)[//]Y0)).
rstepl ([1][*]AbsIR ((x[-][1])[^]S n[/]nring (R:=IR) (S n)[//]Y0)).
apply mult_wdl.
csetoid_rewrite (AbsIR_nexp_op (S (S n)) ([--][1])).
csetoid_replace (AbsIR ([--][1])) ([1]:IR).
apply eq_symmetric.
apply (one_nexp IR (S (S n))).
rstepr ([--][--][1]:IR).
apply AbsIR_eq_inv_x.
apply shift_zero_leEq_minus'.
rstepr ([1]:IR).
apply less_leEq; apply pos_one.
eapply eq_transitive.
apply eq_symmetric; apply AbsIR_resp_mult.
apply AbsIR_wd.
change ((([--][1][^]S (S n)[/]nring (R:=IR) (S n)[//]Y0){**}(FId{-}[-C-][1]){^}S n) x Hx)
with ((([--][1][^]S (S n)[/]nring (R:=IR) (S n)[//]Y0)[*](x[-][1])[^]S n)).
rational.
apply div_wd.
apply (AbsIR_nexp (x[-][1]) (S n)).
apply AbsIR_eq_x.
apply nring_nonneg.
stepl (AbsIR ((x[-][1])[^](S (S n)))[/]_[//](AbsIR_resp_ap_zero _ Y1)).
eapply eq_transitive.
apply eq_symmetric.
apply (AbsIR_division ((x[-][1])[^]S (S n)) _ Y1).
stepr (AbsIR (([--][1][^]S (S (S n))[*]((x[-][1])[^]S (S n)[/]_[//]Y1)))).
eapply eq_transitive;[|apply eq_symmetric; apply AbsIR_resp_mult].
rstepl ([1][*]AbsIR ((x[-][1])[^]S (S n)[/]nring (R:=IR) (S (S n))[//]Y1)).
apply mult_wdl.
csetoid_rewrite (AbsIR_nexp_op (S (S (S n))) [--][1]).
csetoid_replace (AbsIR ([--][1])) ([1]:IR).
apply eq_symmetric.
apply (one_nexp IR).
rstepr ([--][--][1]:IR).
apply AbsIR_eq_inv_x.
apply shift_zero_leEq_minus'.
rstepr ([1]:IR).
apply less_leEq; apply pos_one.
apply AbsIR_wd.
change ((([--][1][^]S (S (S n))[/]nring (R:=IR) (S (S n))[//]Y1){**}(FId{-}[-C-][1]){^}S (S n)) x Hx')
with ((([--][1][^]S (S (S n))[/]nring (R:=IR) (S (S n))[//]Y1)[*](x[-][1])[^]S (S n))).
rational.
apply div_wd.
apply (AbsIR_nexp (x[-][1]) (S (S n))).
apply AbsIR_eq_x.
apply nring_nonneg.
Qed.
Lemma Log_series : forall c : IR,
forall (Hs:fun_series_convergent_IR (olor [0] Two) Log_ps) Hc0 Hc1,
FSeries_Sum Hs c Hc0[=]Log c Hc1.
Proof.
intros c Hs Hc0 Hc1.
Transparent Logarithm.
assert (Z:fun_series_convergent_IR (olor [0] Two) (fun n : nat => Log_ps (S n))).
generalize Log_ps Hs.
intros p Hp; clear - Hp.
intros a b Hab Hinc.
destruct (Hp a b Hab Hinc) as [A B].
exists (fun n => (A (S n))).
intros e He.
destruct (B e He) as [C D].
exists (C).
intros m n Hm Hn x Hx.
assert (D' := (D (S m) (S n))).
stepl (AbsIR (fun_seq_part_sum p (S m) x (contin_imp_inc a b Hab (fun_seq_part_sum p (S m))
(fun_seq_part_sum_cont a b Hab p A (S m)) x Hx)[-] fun_seq_part_sum p (S n) x
(contin_imp_inc a b Hab (fun_seq_part_sum p (S n))
(fun_seq_part_sum_cont a b Hab p A (S n)) x Hx))).
apply D'; auto with *.
apply AbsIR_wd.
set (g:=(fun (y n0 : nat) => Part (p n0) x (contin_imp_inc a b Hab (fun_seq_part_sum p y)
(fun_seq_part_sum_cont a b Hab p A y) x Hx n0))).
set (g':=(fun y n0 : nat => Part (p (S n0)) x
(contin_imp_inc a b Hab (fun_seq_part_sum (fun n1 : nat => p (S n1)) y)
(fun_seq_part_sum_cont a b Hab (fun n1 : nat => p (S n1))
(fun n1 : nat => A (S n1)) y) x Hx n0))).
change (Sum0 (G:=IR) (S m) (g (S m))[-](Sum0 (G:=IR) (S n) (g (S n)))[=]
Sum0 (G:=IR) m (g' m)[-]Sum0 (G:=IR) n (g' n)).
stepr ((g (S m) 0[+]Sum0 (G:=IR) m (g' m))[-](g (S n) 0[+]Sum0 (G:=IR) n (g' n))).
unfold cg_minus.
apply eq_symmetric; apply bin_op_wd_unfolded; try apply un_op_wd_unfolded; apply Sum0_shift;
intros i; unfold g', g; apply pfwdef; apply eq_reflexive.
apply cg_cancel_lft with (g (S n) 0[-](Sum0 (G:=IR) m (g' m)[-]Sum0 (G:=IR) n (g' n))).
rstepr (g (S n) 0).
rstepl (g (S m) 0).
unfold g; apply pfwdef; apply eq_reflexive.
assert (Z0:=insert_series_sum _ _ Z).
set (Hs':=(insert_series_conv (olor [0] Two) (fun n : nat => Log_ps (S n)) Z)) in *.
apply eq_transitive with (FSeries_Sum (J:=olor [0] Two)
(f:=insert_series (fun n : nat => Log_ps (S n))) Hs' c Hc0).
simpl.
apply series_sum_wd.
intros [|n].
simpl; rational.
simpl; rational.
apply eq_transitive with (FSeries_Sum Z c Hc0).
apply Feq_imp_eq with (olor [0] Two).
apply Feq_symmetric.
apply (insert_series_sum _ _ Z).
assumption.
simpl.
unfold series_sum.
apply eq_symmetric.
apply Limits_unique.
simpl.
unfold Log, Logarithm.
simpl.
assert (X:forall n, Continuous_I (Min_leEq_Max [1] c) (([-C-][1]{-}FId){^}n)).
Contin.
apply Cauchy_Lim_prop2_wd with (fun n => Integral (fun_seq_part_sum_cont _ _ _ _ X n)).
assert (A0:Continuous (olor [0] Two) ({1/}FId)).
apply Continuous_recip.
Contin.
intros a b Hab Hinc.
split.
Included.
exists a.
destruct (Hinc _ (compact_inc_lft _ _ Hab)); assumption.
simpl.
intros y _ Hy.
stepr y.
destruct Hy; assumption.
apply eq_symmetric.
apply AbsIR_eq_x.
apply less_leEq; destruct (Hinc _ Hy); assumption.
assert (A1:forall n : nat, Continuous (olor [0] Two) (fun_seq_part_sum (Fnth (R:=IR) ([-C-][1]{-}FId)) n)).
intros n.
split.
repeat constructor.
intros a b Hab Hinc.
Contin.
eapply (limit_of_Integral (olor [0] Two) _ _ A1 A0).
unfold fun_seq_part_sum.
assert (A2:fun_series_convergent_IR (olor [0] Two) (Fnth (R:=IR) ([-C-][1]{-}FId))).
cut (fun_series_convergent_IR (olor [0] Two) (fun n => FId{^}n[o]([-C-][1]{-}FId))).
apply fun_series_convergent_wd_IR.
intros n.
FEQ.
intros x Hx.
assert (W:Dom ([-C-][1]{-}FId) x).
repeat constructor.
exists W.
repeat constructor.
apply FSeries_Sum_comp_conv with (olor [--][1] [1]).
intros a b Hab Hinc.
exists ([1][-]b).
exists ([1][-]a).
assert (W:[1][-]b[<=][1][-]a).
unfold cg_minus.
apply plus_resp_leEq_lft.
apply inv_resp_leEq.
assumption.
exists W.
split.
intros x [Hx0 Hx1].
split.
eapply less_leEq_trans;[|apply Hx0].
apply shift_less_minus.
apply shift_plus_less'.
rstepr (Two:IR).
destruct (Hinc _ (compact_inc_rht _ _ Hab)); assumption.
eapply leEq_less_trans;[apply Hx1|].
apply shift_minus_less.
apply shift_less_plus'.
rstepl ([0]:IR).
destruct (Hinc _ (compact_inc_lft _ _ Hab)); assumption.
intros x Hx [Hx0 Hx1].
split; simpl.
apply shift_leEq_minus'.
apply shift_plus_leEq.
rstepr b.
assumption.
apply shift_leEq_minus'.
apply shift_plus_leEq.
rstepr x.
assumption.
Contin.
apply fun_power_series_conv_IR.
assert (A3:Continuous (olor [0] Two)
(FSeries_Sum (J:=olor [0] Two) (f:=Fnth (R:=IR) ([-C-][1]{-}FId)) A2)).
Contin.
eapply (conv_fun_seq'_wdr_IR);[|apply (FSeries_conv _ _ A2 A1 A3)].
FEQ.
assert (Y:AbsIR ([1][-]x)[<][1]).
destruct X0.
apply AbsIR_less.
apply shift_minus_less.
apply shift_less_plus'.
rstepl ([0]:IR); assumption.
apply shift_less_minus'.
apply shift_plus_less.
rstepr (Two:IR); assumption.
assert (Y0:[1][-]([1][-]x)[#][0]).
rstepl (x).
apply Greater_imp_ap.
destruct X0; assumption.
apply eq_transitive with ([1][/]_[//]Y0).
eapply eq_transitive;[|apply (power_series_sum _ Y Y0 (power_series_conv _ Y))].
simpl.
apply series_sum_wd.
intros n; apply eq_reflexive.
simpl.
rational.
intros x [Hx0 Hx1].
split.
apply less_leEq_trans with (Min [1] c); try assumption.
apply less_Min; try assumption.
apply pos_one.
apply leEq_less_trans with (Max [1] c); try assumption.
destruct Hc0.
apply Max_less; try assumption.
apply one_less_two.
intros n.
induction n.
simpl.
rstepr ([0][*](c[-][1])).
eapply eq_transitive;[|apply (Integral_const _ _ (Min_leEq_Max [1] c) [0] (Continuous_I_const _ _ _ _))].
apply Integral_wd.
FEQ.
auto with *.
simpl.
csetoid_rewrite_rev IHn.
assert (Y:Continuous_I (Min_leEq_Max [1] c) (([-C-][1]{-}FId){^}n)).
Contin.
csetoid_replace ((nexp IR n [--][1][*][--][1][*][--][1][/]nring (R:=IR) n[+][1][//]
nringS_ap_zero IR n)[*](nexp IR n (c[-][1])[*](c[-][1]))) (Integral Y).
assert (Y0:=Continuous_I_plus _ _ _ _ _ (fun_seq_part_sum_cont (Min [1] c) (Max [1] c) (Min_leEq_Max [1] c)
(Fnth (R:=IR) ([-C-][1]{-}FId)) X n) Y).
stepl (Integral Y0).
apply Integral_plus.
apply Integral_wd.
apply eq_imp_Feq; try Included.
intros x Hx; split; constructor.
intros x H Hx Hx'.
simpl.
apply eq_reflexive.
rstepl ((nexp IR n [--][1][/]nring (R:=IR) n[+][1][//]
nringS_ap_zero IR n)[*](nexp IR n (c[-][1])[*](c[-][1]))).
change ((nexp IR n [--][1][/]nring (R:=IR) n[+][1][//]nringS_ap_zero IR n)[*]
(nexp IR n (c[-][1])[*](c[-][1])))
with (([--][1][^]n[/]_[//]nringS_ap_zero IR n)[*](c[-][1])[^](S n)).
pose (G:=(([--][1][/]_[//]nringS_ap_zero IR n){**}([-C-][1]{-}FId){^}(S n))).
assert (X0:Derivative (olor [0] Two) (pos_two IR) G (([-C-][1]{-}FId){^}n)).
unfold G.
Derivative_Help; [|apply Derivative_scal;refine (Derivative_nth _ _ _ _ _ _);Deriv].
FEQ.
repeat constructor.
assert (X1:Continuous (olor [0] Two) (([-C-][1]{-}FId){^}n)).
Contin.
assert (X2:(olor [0] Two [1])).
split.
apply pos_one.
apply one_less_two.
eapply eq_transitive.
2:apply eq_symmetric.
2:apply (fun A => Barrow (olor [0] Two) _ X1 _ _ X0 _ _ A X2 Hc0).
simpl.
rstepr (([--][1][/]nring (R:=IR) n[+][1][//]nringS_ap_zero IR n)[*]
(nexp IR n ([1][-]c)[*]([1][-]c))).
change (([--][1][^]n[/]_[//]nringS_ap_zero IR n)[*] ((c[-][1])[^](S n))[=]
([--][1][/]_[//]nringS_ap_zero IR n)[*] (([1][-]c)[^](S n))).
rstepr (([--][1][/]nring (R:=IR) (S n)[//]nringS_ap_zero IR n)[*] ([--][1][*](c[-][1]))[^]S n).
csetoid_rewrite (mult_nexp IR ([--][1]) (c[-][1]) (S n)).
simpl.
rational.
Qed.
End Log_Series.
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_top.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
////
//// /* Modifications to spi_top.v */
//// /* Copyright (c) 2006 Rice University */
//// /* All Rights Reserved */
//// /* This code is covered by the Rice-WARP license */
//// /* See http://warp.rice.edu/license/ for details */
module spi_top
(
// OPB signals
opb_clk_i, opb_rst_i,
// SPI registers
reg_ctrl, reg_ss, reg_divider, reg_tx, ctrlwrite, busval, go,
// SPI signals
ss_pad_o, sclk_pad_o, mosi_pad_o
);
parameter Tp = 1;
// OPB signals
input opb_clk_i; // master clock input
input opb_rst_i; // synchronous active high reset
// SPI registers
input [13:0] reg_ctrl;
input [7:0] reg_ss;
input [3:0] reg_divider;
input [17:0] reg_tx;
input ctrlwrite;
input busval;
output go;
// SPI signals
output [8-1:0] ss_pad_o; // slave select
output sclk_pad_o; // serial clock
output mosi_pad_o; // master out slave in
// Internal signals
wire [17:0] rx; // Rx register
wire rx_negedge; // miso is sampled on negative edge
wire tx_negedge; // mosi is driven on negative edge
wire [4:0] char_len; // char len
//wire go; // go
wire lsb; // lsb first on line
wire ie; // interrupt enable
wire ass; // automatic slave select
wire spi_divider_sel; // divider register select
wire spi_ctrl_sel; // ctrl register select
wire [3:0] spi_tx_sel; // tx_l register select
wire spi_ss_sel; // ss register select
wire tip; // transfer in progress
wire pos_edge; // recognize posedge of sclk
wire neg_edge; // recognize negedge of sclk
wire last_bit; // marks last character bit
reg ctrlbitgo;
assign rx_negedge = reg_ctrl[9];
assign tx_negedge = reg_ctrl[10];
assign go = ctrlbitgo;
assign char_len = reg_ctrl[6:0];
assign lsb = reg_ctrl[11];
assign ie = reg_ctrl[12];
assign ass = reg_ctrl[13];
always @(posedge opb_clk_i or posedge opb_rst_i)
begin
if (opb_rst_i)
ctrlbitgo <= #Tp 1'b0;
else if(ctrlwrite && !tip)
ctrlbitgo <= #Tp busval;
else if(tip && last_bit && pos_edge)
ctrlbitgo <= #Tp 1'b0;
end
assign ss_pad_o = ~((reg_ss & {8{tip & ass}}) | (reg_ss & {8{!ass}}));
spi_clgen clgen (.clk_in(opb_clk_i), .rst(opb_rst_i), .go(go), .enable(tip), .last_clk(last_bit),
.divider(reg_divider), .clk_out(sclk_pad_o), .pos_edge(pos_edge),
.neg_edge(neg_edge));
spi_shift shift (.clk(opb_clk_i), .rst(opb_rst_i), .len(char_len[5-1:0]),
.lsb(lsb), .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge),
.rx_negedge(rx_negedge), .tx_negedge(tx_negedge),
.tip(tip), .last(last_bit),
.p_in(reg_tx), .p_out(rx),
.s_clk(sclk_pad_o), .s_out(mosi_pad_o));
endmodule
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
(* altera_attribute = "-name GLOBAL_SIGNAL OFF" *)
module hps_sdram_p0_reset(
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
reset_n_afi_clk,
reset_n_addr_cmd_clk,
reset_n_resync_clk,
reset_n_seq_clk,
reset_n_read_capture_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input seq_reset_mem_stable;
input pll_afi_clk;
input pll_addr_cmd_clk;
input pll_dqs_ena_clk;
input seq_clk;
input scc_clk;
input pll_avl_clk;
output reset_n_scc_clk;
output reset_n_avl_clk;
input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input pll_locked;
input global_reset_n;
input soft_reset_n;
output ctl_reset_n;
output ctl_reset_export_n;
output [NUM_AFI_RESET-1:0] reset_n_afi_clk;
output reset_n_addr_cmd_clk;
output reset_n_resync_clk;
output reset_n_seq_clk;
output [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk;
// Apply the synthesis keep attribute on the synchronized reset wires
// so that these names can be constrained using QSF settings to keep
// the resets on local routing.
wire phy_reset_n /* synthesis keep = 1 */;
wire phy_reset_mem_stable_n /* synthesis keep = 1*/;
wire [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture;
assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable;
assign reset_n_read_capture_clk = reset_n_read_capture;
assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n;
hps_sdram_p0_reset_sync ureset_afi_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (reset_n_afi_clk)
);
defparam ureset_afi_clk.RESET_SYNC_STAGES = 15;
defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET;
hps_sdram_p0_reset_sync ureset_ctl_reset_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync ({ctl_reset_n, ctl_reset_export_n})
);
defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 15;
defparam ureset_ctl_reset_clk.NUM_RESET_OUTPUT = 2;
hps_sdram_p0_reset_sync ureset_addr_cmd_clk(
.reset_n (phy_reset_n),
.clk (pll_addr_cmd_clk),
.reset_n_sync (reset_n_addr_cmd_clk)
);
defparam ureset_addr_cmd_clk.RESET_SYNC_STAGES = 15;
defparam ureset_addr_cmd_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_resync_clk(
.reset_n (phy_reset_n),
.clk (pll_dqs_ena_clk),
.reset_n_sync (reset_n_resync_clk)
);
defparam ureset_resync_clk.RESET_SYNC_STAGES = 15;
defparam ureset_resync_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_seq_clk(
.reset_n (phy_reset_n),
.clk (seq_clk),
.reset_n_sync (reset_n_seq_clk)
);
defparam ureset_seq_clk.RESET_SYNC_STAGES = 15;
defparam ureset_seq_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_scc_clk(
.reset_n (phy_reset_n),
.clk (scc_clk),
.reset_n_sync (reset_n_scc_clk)
);
defparam ureset_scc_clk.RESET_SYNC_STAGES = 15;
defparam ureset_scc_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_avl_clk(
.reset_n (phy_reset_n),
.clk (pll_avl_clk),
.reset_n_sync (reset_n_avl_clk)
);
defparam ureset_avl_clk.RESET_SYNC_STAGES = 2;
defparam ureset_avl_clk.NUM_RESET_OUTPUT = 1;
generate
genvar i;
for (i=0; i<MEM_READ_DQS_WIDTH; i=i+1)
begin: read_capture_reset
hps_sdram_p0_reset_sync #(
.RESET_SYNC_STAGES(15),
.NUM_RESET_OUTPUT(1)
)
ureset_read_capture_clk(
.reset_n (phy_reset_mem_stable_n),
.clk (read_capture_clk[i]),
.reset_n_sync (reset_n_read_capture[i])
);
end
endgenerate
endmodule
|
module bram_tb #(
parameter ABITS = 8, DBITS = 8,
parameter INIT_ADDR = 0, INIT_DATA = 0
);
reg clk;
reg [ABITS-1:0] WR_ADDR;
reg [DBITS-1:0] WR_DATA;
reg WR_EN;
reg [ABITS-1:0] RD_ADDR;
wire [DBITS-1:0] RD_DATA;
bram uut (
.clk (clk ),
.WR_ADDR(WR_ADDR),
.WR_DATA(WR_DATA),
.WR_EN (WR_EN ),
.RD_ADDR(RD_ADDR),
.RD_DATA(RD_DATA)
);
reg [63:0] xorshift64_state = 64'd88172645463325252 ^ (ABITS << 24) ^ (DBITS << 16);
task xorshift64_next;
begin
// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
end
endtask
reg [ABITS-1:0] randaddr1;
reg [ABITS-1:0] randaddr2;
reg [ABITS-1:0] randaddr3;
function [31:0] getaddr(input [3:0] n);
begin
case (n)
0: getaddr = 0;
1: getaddr = 2**ABITS-1;
2: getaddr = 'b101 << (ABITS / 3);
3: getaddr = 'b101 << (2*ABITS / 3);
4: getaddr = 'b11011 << (ABITS / 4);
5: getaddr = 'b11011 << (2*ABITS / 4);
6: getaddr = 'b11011 << (3*ABITS / 4);
7: getaddr = randaddr1;
8: getaddr = randaddr2;
9: getaddr = randaddr3;
default: begin
getaddr = 1 << (2*n-16);
if (!getaddr) getaddr = xorshift64_state;
end
endcase
end
endfunction
reg [DBITS-1:0] memory [0:2**ABITS-1];
reg [DBITS-1:0] expected_rd, expected_rd_masked;
event error;
integer i, j;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, bram_tb);
memory[INIT_ADDR] <= INIT_DATA;
xorshift64_next;
xorshift64_next;
xorshift64_next;
xorshift64_next;
randaddr1 = xorshift64_state;
xorshift64_next;
randaddr2 = xorshift64_state;
xorshift64_next;
randaddr3 = xorshift64_state;
xorshift64_next;
clk <= 0;
for (i = 0; i < 512; i = i+1) begin
WR_DATA = xorshift64_state;
xorshift64_next;
WR_ADDR = getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]);
xorshift64_next;
RD_ADDR = i == 0 ? INIT_ADDR : getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
WR_EN = xorshift64_state[55] && ((WR_ADDR & 'hff) != (RD_ADDR & 'hff));
xorshift64_next;
#1; clk <= 1;
#1; clk <= 0;
expected_rd = memory[RD_ADDR];
if (WR_EN) memory[WR_ADDR] = WR_DATA;
for (j = 0; j < DBITS; j = j+1)
expected_rd_masked[j] = expected_rd[j] !== 1'bx ? expected_rd[j] : RD_DATA[j];
$display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x (%x) | %s",
i, WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd,
expected_rd_masked === RD_DATA ? "ok" : "ERROR");
if (expected_rd_masked !== RD_DATA) begin -> error; end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
// bug598
module t (/*AUTOARG*/
// Outputs
val,
// Inputs
clk
);
input clk;
output integer val;
integer dbg_addr = 0;
function func1;
input en;
input [31:0] a;
func1 = en && (a == 1);
endfunction
function func2;
input en;
input [31:0] a;
func2 = en && (a == 2);
endfunction
always @(posedge clk) begin
case( 1'b1 )
// This line is OK:
func1(1'b1, dbg_addr) : val = 1;
// This fails:
// %Error: Internal Error: test.v:23: ../V3Task.cpp:993: Function not underneath a statement
// %Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.
func2(1'b1, dbg_addr) : val = 2;
default : val = 0;
endcase
//
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:03:51 02/23/2015
// Design Name:
// Module Name: HCORDIC_Pipeline
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module HCORDIC_Pipeline(
input [15:0] InstructionPacket,
input clock,
output [31:0] x_out,
output [31:0] y_out,
output [31:0] z_out,
output done
);
wire stall,load,ALU_done,converge;
wire operation_Fetch,operation_iter,operation_FSM,operation_Execute;
wire [1:0] mode_Fetch,mode_iter,mode_FSM,mode_Execute;
wire [31:0] x_input, x_iter, xout_Mux, x_scale, xout_FSM;
wire [31:0] y_input, y_iter, yout_Mux, y_scale, yout_FSM;
wire [31:0] z_input, z_iter, zout_Mux, z_scale, zout_FSM;
wire [31:0] k_iter, kout_Mux, k_scale, kout_FSM;
wire [31:0] thetaout_FSM;
wire [31:0] deltaout_FSM;
wire [31:0] kappaout_FSM;
Fetch v0 (
.InstructionPacket(InstructionPacket),
.clock(clock),
.stall(stall),
.x_input(x_input),
.y_input(y_input),
.z_input(z_input),
.mode(mode_Fetch),
.operation(operation_Fetch),
.load(load)
);
InputMux v1 (
.x_in(x_input),
.y_in(y_input),
.z_in(z_input),
.x_iter(x_iter),
.y_iter(y_iter),
.z_iter(z_iter),
.k_iter(k_iter),
.load(load),
.ALU_done(ALU_done),
.clock(clock),
.mode_in(mode_Fetch),
.operation_in(operation_Fetch),
.mode_iter(mode_iter),
.operation_iter(operation_iter),
.x_out(xout_Mux),
.y_out(yout_Mux),
.z_out(zout_Mux),
.k_out(kout_Mux),
.x_scale(x_scale),
.y_scale(y_scale),
.z_scale(z_scale),
.k_scale(k_scale),
.modeout_Mux(mode_FSM),
.operationout_Mux(operation_FSM),
.converge(converge),
.stall(stall)
);
FSM v3 (
.x_FSM(xout_Mux),
.y_FSM(yout_Mux),
.z_FSM(zout_Mux),
.k_FSM(kout_Mux),
.clock(clock),
.mode_FSM(mode_FSM),
.operation_FSM(operation_FSM),
.modeout_FSM(mode_Execute),
.operationout_FSM(operation_Execute),
.xout_FSM(xout_FSM),
.yout_FSM(yout_FSM),
.zout_FSM(zout_FSM),
.kout_FSM(kout_FSM),
.thetaout_FSM(thetaout_FSM),
.deltaout_FSM(deltaout_FSM),
.kappaout_FSM(kappaout_FSM)
);
ExecutePipeline v4 (
.X_in(xout_FSM),
.Y_in(yout_FSM),
.Z_in(zout_FSM),
.K_in(kout_FSM),
.kappa_in(kappaout_FSM),
.theta_in(thetaout_FSM),
.delta_in(deltaout_FSM),
.clock(clock),
.operation(operation_Execute),
.mode(mode_Execute),
.X_next(x_iter),
.Y_next(y_iter),
.Z_next(z_iter),
.K_next(k_iter),
.mode_out(mode_iter),
.operation_out(operation_iter),
.ALU_done(ALU_done)
);
Descale_pipeline v5 (
.x_scale(x_scale),
.y_scale(y_scale),
.z_scale(z_scale),
.k_in(k_scale),
.clock(clock),
.x_out(x_out),
.y_out(y_out),
.z_out(z_out),
.done(done)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t_case_huge_sub2 (/*AUTOARG*/
// Outputs
outa,
// Inputs
index
);
input [9:0] index;
output [9:0] outa;
// =============================
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [9:0] outa;
// End of automatics
// =============================
// Created from perl
// for $i (0..1023) { printf "\t10'h%03x: begin outa = 10'h%03x; outb = 2'b%02b; outc = 1'b%d; end\n", $i, rand(1024),rand(4),rand(2); };
always @(/*AS*/index) begin
case (index[7:0])
`ifdef VERILATOR // Harder test
8'h00: begin outa = $c("0"); end // Makes whole table non-optimizable
`else
8'h00: begin outa = 10'h0; end
`endif
8'h01: begin outa = 10'h318; end
8'h02: begin outa = 10'h29f; end
8'h03: begin outa = 10'h392; end
8'h04: begin outa = 10'h1ef; end
8'h05: begin outa = 10'h06c; end
8'h06: begin outa = 10'h29f; end
8'h07: begin outa = 10'h29a; end
8'h08: begin outa = 10'h3ce; end
8'h09: begin outa = 10'h37c; end
8'h0a: begin outa = 10'h058; end
8'h0b: begin outa = 10'h3b2; end
8'h0c: begin outa = 10'h36f; end
8'h0d: begin outa = 10'h2c5; end
8'h0e: begin outa = 10'h23a; end
8'h0f: begin outa = 10'h222; end
8'h10: begin outa = 10'h328; end
8'h11: begin outa = 10'h3c3; end
8'h12: begin outa = 10'h12c; end
8'h13: begin outa = 10'h1d0; end
8'h14: begin outa = 10'h3ff; end
8'h15: begin outa = 10'h115; end
8'h16: begin outa = 10'h3ba; end
8'h17: begin outa = 10'h3ba; end
8'h18: begin outa = 10'h10d; end
8'h19: begin outa = 10'h13b; end
8'h1a: begin outa = 10'h0a0; end
8'h1b: begin outa = 10'h264; end
8'h1c: begin outa = 10'h3a2; end
8'h1d: begin outa = 10'h07c; end
8'h1e: begin outa = 10'h291; end
8'h1f: begin outa = 10'h1d1; end
8'h20: begin outa = 10'h354; end
8'h21: begin outa = 10'h0c0; end
8'h22: begin outa = 10'h191; end
8'h23: begin outa = 10'h379; end
8'h24: begin outa = 10'h073; end
8'h25: begin outa = 10'h2fd; end
8'h26: begin outa = 10'h2e0; end
8'h27: begin outa = 10'h337; end
8'h28: begin outa = 10'h2c7; end
8'h29: begin outa = 10'h19e; end
8'h2a: begin outa = 10'h107; end
8'h2b: begin outa = 10'h06a; end
8'h2c: begin outa = 10'h1c7; end
8'h2d: begin outa = 10'h107; end
8'h2e: begin outa = 10'h0cf; end
8'h2f: begin outa = 10'h009; end
8'h30: begin outa = 10'h09d; end
8'h31: begin outa = 10'h28e; end
8'h32: begin outa = 10'h010; end
8'h33: begin outa = 10'h1e0; end
8'h34: begin outa = 10'h079; end
8'h35: begin outa = 10'h13e; end
8'h36: begin outa = 10'h282; end
8'h37: begin outa = 10'h21c; end
8'h38: begin outa = 10'h148; end
8'h39: begin outa = 10'h3c0; end
8'h3a: begin outa = 10'h176; end
8'h3b: begin outa = 10'h3fc; end
8'h3c: begin outa = 10'h295; end
8'h3d: begin outa = 10'h113; end
8'h3e: begin outa = 10'h354; end
8'h3f: begin outa = 10'h0db; end
8'h40: begin outa = 10'h238; end
8'h41: begin outa = 10'h12b; end
8'h42: begin outa = 10'h1dc; end
8'h43: begin outa = 10'h137; end
8'h44: begin outa = 10'h1e2; end
8'h45: begin outa = 10'h3d5; end
8'h46: begin outa = 10'h30c; end
8'h47: begin outa = 10'h298; end
8'h48: begin outa = 10'h080; end
8'h49: begin outa = 10'h35a; end
8'h4a: begin outa = 10'h01b; end
8'h4b: begin outa = 10'h0a3; end
8'h4c: begin outa = 10'h0b3; end
8'h4d: begin outa = 10'h17a; end
8'h4e: begin outa = 10'h3ae; end
8'h4f: begin outa = 10'h078; end
8'h50: begin outa = 10'h322; end
8'h51: begin outa = 10'h213; end
8'h52: begin outa = 10'h11a; end
8'h53: begin outa = 10'h1a7; end
8'h54: begin outa = 10'h35a; end
8'h55: begin outa = 10'h233; end
8'h56: begin outa = 10'h01d; end
8'h57: begin outa = 10'h2d5; end
8'h58: begin outa = 10'h1a0; end
8'h59: begin outa = 10'h3d0; end
8'h5a: begin outa = 10'h181; end
8'h5b: begin outa = 10'h219; end
8'h5c: begin outa = 10'h26a; end
8'h5d: begin outa = 10'h050; end
8'h5e: begin outa = 10'h189; end
8'h5f: begin outa = 10'h1eb; end
8'h60: begin outa = 10'h224; end
8'h61: begin outa = 10'h2fe; end
8'h62: begin outa = 10'h0ae; end
8'h63: begin outa = 10'h1cd; end
8'h64: begin outa = 10'h273; end
8'h65: begin outa = 10'h268; end
8'h66: begin outa = 10'h111; end
8'h67: begin outa = 10'h1f9; end
8'h68: begin outa = 10'h232; end
8'h69: begin outa = 10'h255; end
8'h6a: begin outa = 10'h34c; end
8'h6b: begin outa = 10'h049; end
8'h6c: begin outa = 10'h197; end
8'h6d: begin outa = 10'h0fe; end
8'h6e: begin outa = 10'h253; end
8'h6f: begin outa = 10'h2de; end
8'h70: begin outa = 10'h13b; end
8'h71: begin outa = 10'h040; end
8'h72: begin outa = 10'h0b4; end
8'h73: begin outa = 10'h233; end
8'h74: begin outa = 10'h198; end
8'h75: begin outa = 10'h018; end
8'h76: begin outa = 10'h2f7; end
8'h77: begin outa = 10'h134; end
8'h78: begin outa = 10'h1ca; end
8'h79: begin outa = 10'h286; end
8'h7a: begin outa = 10'h0e6; end
8'h7b: begin outa = 10'h064; end
8'h7c: begin outa = 10'h257; end
8'h7d: begin outa = 10'h31a; end
8'h7e: begin outa = 10'h247; end
8'h7f: begin outa = 10'h299; end
8'h80: begin outa = 10'h02c; end
8'h81: begin outa = 10'h2bb; end
8'h82: begin outa = 10'h180; end
8'h83: begin outa = 10'h245; end
8'h84: begin outa = 10'h0da; end
8'h85: begin outa = 10'h367; end
8'h86: begin outa = 10'h304; end
8'h87: begin outa = 10'h38b; end
8'h88: begin outa = 10'h09f; end
8'h89: begin outa = 10'h1f0; end
8'h8a: begin outa = 10'h281; end
8'h8b: begin outa = 10'h019; end
8'h8c: begin outa = 10'h1f2; end
8'h8d: begin outa = 10'h0b1; end
8'h8e: begin outa = 10'h058; end
8'h8f: begin outa = 10'h39b; end
8'h90: begin outa = 10'h2ec; end
8'h91: begin outa = 10'h250; end
8'h92: begin outa = 10'h3f4; end
8'h93: begin outa = 10'h057; end
8'h94: begin outa = 10'h18f; end
8'h95: begin outa = 10'h105; end
8'h96: begin outa = 10'h1ae; end
8'h97: begin outa = 10'h04e; end
8'h98: begin outa = 10'h240; end
8'h99: begin outa = 10'h3e4; end
8'h9a: begin outa = 10'h3c6; end
8'h9b: begin outa = 10'h109; end
8'h9c: begin outa = 10'h073; end
8'h9d: begin outa = 10'h19f; end
8'h9e: begin outa = 10'h3b8; end
8'h9f: begin outa = 10'h00e; end
8'ha0: begin outa = 10'h1b3; end
8'ha1: begin outa = 10'h2bd; end
8'ha2: begin outa = 10'h324; end
8'ha3: begin outa = 10'h343; end
8'ha4: begin outa = 10'h1c9; end
8'ha5: begin outa = 10'h185; end
8'ha6: begin outa = 10'h37a; end
8'ha7: begin outa = 10'h0e0; end
8'ha8: begin outa = 10'h0a3; end
8'ha9: begin outa = 10'h019; end
8'haa: begin outa = 10'h099; end
8'hab: begin outa = 10'h376; end
8'hac: begin outa = 10'h077; end
8'had: begin outa = 10'h2b1; end
8'hae: begin outa = 10'h27f; end
8'haf: begin outa = 10'h265; end
8'hb0: begin outa = 10'h156; end
8'hb1: begin outa = 10'h1ce; end
8'hb2: begin outa = 10'h008; end
8'hb3: begin outa = 10'h12e; end
8'hb4: begin outa = 10'h199; end
8'hb5: begin outa = 10'h330; end
8'hb6: begin outa = 10'h1ab; end
8'hb7: begin outa = 10'h3bd; end
8'hb8: begin outa = 10'h0ca; end
8'hb9: begin outa = 10'h367; end
8'hba: begin outa = 10'h334; end
8'hbb: begin outa = 10'h040; end
8'hbc: begin outa = 10'h1a7; end
8'hbd: begin outa = 10'h036; end
8'hbe: begin outa = 10'h223; end
8'hbf: begin outa = 10'h075; end
8'hc0: begin outa = 10'h3c4; end
8'hc1: begin outa = 10'h2cc; end
8'hc2: begin outa = 10'h123; end
8'hc3: begin outa = 10'h3fd; end
8'hc4: begin outa = 10'h11e; end
8'hc5: begin outa = 10'h27c; end
8'hc6: begin outa = 10'h1e2; end
8'hc7: begin outa = 10'h377; end
8'hc8: begin outa = 10'h33a; end
8'hc9: begin outa = 10'h32d; end
8'hca: begin outa = 10'h014; end
8'hcb: begin outa = 10'h332; end
8'hcc: begin outa = 10'h359; end
8'hcd: begin outa = 10'h0a4; end
8'hce: begin outa = 10'h348; end
8'hcf: begin outa = 10'h04b; end
8'hd0: begin outa = 10'h147; end
8'hd1: begin outa = 10'h026; end
8'hd2: begin outa = 10'h103; end
8'hd3: begin outa = 10'h106; end
8'hd4: begin outa = 10'h35a; end
8'hd5: begin outa = 10'h254; end
8'hd6: begin outa = 10'h0cd; end
8'hd7: begin outa = 10'h17c; end
8'hd8: begin outa = 10'h37e; end
8'hd9: begin outa = 10'h0a9; end
8'hda: begin outa = 10'h0fe; end
8'hdb: begin outa = 10'h3c0; end
8'hdc: begin outa = 10'h1d9; end
8'hdd: begin outa = 10'h10e; end
8'hde: begin outa = 10'h394; end
8'hdf: begin outa = 10'h316; end
8'he0: begin outa = 10'h05b; end
8'he1: begin outa = 10'h126; end
8'he2: begin outa = 10'h369; end
8'he3: begin outa = 10'h291; end
8'he4: begin outa = 10'h2ca; end
8'he5: begin outa = 10'h25b; end
8'he6: begin outa = 10'h106; end
8'he7: begin outa = 10'h172; end
8'he8: begin outa = 10'h2f7; end
8'he9: begin outa = 10'h2d3; end
8'hea: begin outa = 10'h182; end
8'heb: begin outa = 10'h327; end
8'hec: begin outa = 10'h1d0; end
8'hed: begin outa = 10'h204; end
8'hee: begin outa = 10'h11f; end
8'hef: begin outa = 10'h365; end
8'hf0: begin outa = 10'h2c2; end
8'hf1: begin outa = 10'h2b5; end
8'hf2: begin outa = 10'h1f8; end
8'hf3: begin outa = 10'h2a7; end
8'hf4: begin outa = 10'h1be; end
8'hf5: begin outa = 10'h25e; end
8'hf6: begin outa = 10'h032; end
8'hf7: begin outa = 10'h2ef; end
8'hf8: begin outa = 10'h02f; end
8'hf9: begin outa = 10'h201; end
8'hfa: begin outa = 10'h054; end
8'hfb: begin outa = 10'h013; end
8'hfc: begin outa = 10'h249; end
8'hfd: begin outa = 10'h09a; end
8'hfe: begin outa = 10'h012; end
8'hff: begin outa = 10'h114; end
endcase
end
endmodule
|
(** * Types: Type Systems *)
(* $Date: 2011-06-03 13:58:55 -0400 (Fri, 03 Jun 2011) $ *)
Require Export Smallstep.
(** Our next topic, a large one, is _type systems_ -- static program
analyses that classify expressions according to the "shapes" of
their results. We'll begin with a typed version of a very simple
language with just booleans and numbers, to introduce the basic
ideas of types, typing rules, and the fundamental theorems about
type systems: _type preservation_ and _progress_. Then we'll move
on to the _simply typed lambda-calculus_, which lives at the core
of every modern functional programming language (including
Coq). *)
(* ###################################################################### *)
(** * More Automation *)
(** Before we start, let's spend a little time learning to use
some of Coq's more powerful automation features... *)
(* ###################################################################### *)
(** ** The [auto] and [eauto] Tactics *)
(** The [auto] tactic solves goals that are solvable by any combination of
- [intros],
- [apply] (with a local hypothesis, by default), and
- [reflexivity].
The [eauto] tactic works just like [auto], except that it uses
[eapply] instead of [apply]. *)
(** Using [auto] is always "safe" in the sense that it will never fail
and will never change the proof state: either it completely solves
the current goal, or it does nothing.
Here is a contrived example: *)
Lemma auto_example_1 : forall P Q R S T U : Prop,
(P -> Q) ->
(P -> R) ->
(T -> R) ->
(S -> T -> U) ->
((P->Q) -> (P->S)) ->
T ->
P ->
U.
Proof. auto. Qed.
(** When searching for potential proofs of the current goal, [auto]
and [eauto] consider the hypotheses in the current context
together with a _hint database_ of other lemmas and constructors.
Some of the lemmas and constructors we've already seen -- e.g.,
[conj], [or_introl], and [or_intror] -- are installed in this hint
database by default. *)
Lemma auto_example_2 : forall P Q R : Prop,
Q ->
(Q -> R) ->
P \/ (Q /\ R).
Proof.
auto. Qed.
(** We can extend the hint database just for the purposes of one
application of [auto] or [eauto] by writing [auto using ...].
E.g., if [conj], [or_introl], and [or_intror] had _not_ already
been in the hint database, we could have done this instead: *)
Lemma auto_example_2a : forall P Q R : Prop,
Q ->
(Q -> R) ->
P \/ (Q /\ R).
Proof.
auto using conj, or_introl, or_intror. Qed.
(** Of course, in any given development there will also be some of our
own specific constructors and lemmas that are used very often in
proofs. We can add these to the global hint database by writing
Hint Resolve T.
at the top level, where [T] is a top-level theorem or a
constructor of an inductively defined proposition (i.e., anything
whose type is an implication). As a shorthand, we can write
Hint Constructors c.
to tell Coq to do a [Hint Resolve] for _all_ of the constructors
from the inductive definition of [c].
It is also sometimes necessary to add
Hint Unfold d.
where [d] is a defined symbol, so that [auto] knows to expand
uses of [d] and enable further possibilities for applying
lemmas that it knows about. *)
(** Here are some [Hint]s we will find useful. *)
Hint Constructors multi.
Hint Resolve beq_id_eq beq_id_false_not_eq.
(** Warning: Just as with Coq's other automation facilities, it is
easy to overuse [auto] and [eauto] and wind up with proofs that
are impossible to understand later!
Also, overuse of [eauto] can make proof scripts very slow. Get in
the habit of using [auto] most of the time and [eauto] only when
necessary.
For much more detailed information about using [auto] and [eauto],
see the chapter [UseAuto]. *)
(* ###################################################################### *)
(** ** The [Proof with] Tactic *)
(** If you start a proof by saying [Proof with (tactic)] instead of
just [Proof], then writing [...] instead of [.] after a tactic in
the body of the proof will try to solve all generated subgoals
with [tactic] (and fail if this doesn't work).
One common use of this facility is "[Proof with auto]" (or
[eauto]). We'll see many examples of this later in the file. *)
(* ###################################################################### *)
(** ** The [solve by inversion] Tactic *)
(** Here's another nice automation feature: it often arises that the
context contains a contradictory assumption and we want to use
[inversion] on it to solve the goal. We'd like to be able to say
to Coq, "find a contradictory assumption and invert it" without
giving its name explicitly.
Doing [solve by inversion] will find a hypothesis that can be
inverted to solve the goal, if there is one. The tactics [solve
by inversion 2] and [solve by inversion 3] are slightly fancier
versions which will perform two or three inversions in a row, if
necessary, to solve the goal.
(These tactics are not actually built into Coq -- their
definitions are in [Sflib].)
Caution: Overuse of [solve by inversion] can lead to slow proof
scripts. *)
(* ###################################################################### *)
(** ** The [try solve] Tactic *)
(** If [t] is a tactic, then [try solve [t]] is a tactic that
- if [t] solves the goal, behaves just like [t], or
- if [t] cannot completely solve the goal, does
nothing.
More generally, [try solve [t1 | t2 | ...]] will try to solve the
goal by using [t1], [t2], etc. If none of them succeeds in
completely solving the goal, then [try solve [t1 | t2 | ...]] does
nothing. *)
(* ###################################################################### *)
(** ** The [f_equal] Tactic *)
(** [f_equal] replaces a goal of the form [f x1 x2 ... xn = f y1 y2
... yn], where [f] is some function, with the subgoals [x1 = y1],
[x2 = y2],...,[xn = yn]. It is useful for avoiding explicit
rewriting steps, and often the generated subgoals can be quickly
cleared by [auto]. This tactic is not fundamental, in the sense
that it can always be replaced by a sequence of [assert]s.
However in some cases it can be very handy. *)
(* ###################################################################### *)
(** ** The [normalize] Tactic *)
(** When experimenting with definitions of programming languages in
Coq, we often want to see what a particular concrete term steps
to -- i.e., we want to find proofs for goals of the form [t ==>*
t'], where [t] is a completely concrete term and [t'] is unknown.
These proofs are simple but repetitive to do by hand. Consider for
example reducing an arithmetic expression using the small-step
relation [astep] defined in the previous chapter: *)
Definition amultistep st := multi (astep st).
Notation " t '/' st '==>a*' t' " := (amultistep st t t')
(at level 40, st at level 39).
Example astep_example1 :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
apply multi_step with (APlus (ANum 3) (ANum 12)).
apply AS_Plus2.
apply av_num.
apply AS_Mult.
apply multi_step with (ANum 15).
apply AS_Plus.
apply multi_refl.
Qed.
(** We repeatedly applied [multi_step] until we got to a normal
form. The proofs that the intermediate steps are possible are
simple enough that [auto], with appropriate hints, can solve
them. *)
Hint Constructors astep aval.
Example astep_example1' :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
eapply multi_step. auto. simpl.
eapply multi_step. auto. simpl.
apply multi_refl.
Qed.
(** The following custom [Tactic Notation] definition captures this
pattern. In addition, before each [multi_step] we print out the
current goal, so that the user can follow how the term is being
evaluated. *)
Tactic Notation "print_goal" := match goal with |- ?x => idtac x end.
Tactic Notation "normalize" :=
repeat (print_goal; eapply multi_step ;
[ (eauto 10; fail) | (instantiate; simpl)]);
apply multi_refl.
Example astep_example1'' :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
normalize.
(* At this point in the proof script, the Coq response shows
a trace of how the expression evaluated.
(APlus (ANum 3) (AMult (ANum 3) (ANum 4)) / empty_state ==>a* ANum 15)
(multi (astep empty_state) (APlus (ANum 3) (ANum 12)) (ANum 15))
(multi (astep empty_state) (ANum 15) (ANum 15))
*)
Qed.
(** The [normalize] tactic also provides a simple way to calculate
what the normal form of a term is, by proving a goal with an
existential variable in it. *)
Example astep_example1''' : exists e',
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* e'.
Proof.
eapply ex_intro. normalize.
(* This time the trace will be:
(APlus (ANum 3) (AMult (ANum 3) (ANum 4)) / empty_state ==>a* ??)
(multi (astep empty_state) (APlus (ANum 3) (ANum 12)) ??)
(multi (astep empty_state) (ANum 15) ??)
where ?? is the variable ``guessed'' by eapply.
*)
Qed.
(** **** Exercise: 1 star (normalize_ex) *)
Theorem normalize_ex : exists e',
(AMult (ANum 3) (AMult (ANum 2) (ANum 1))) / empty_state
==>a* e'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (normalize_ex') *)
(** This time prove it by using [apply] instead of [eapply]. *)
Theorem normalize_ex' : exists e',
(AMult (ANum 3) (AMult (ANum 2) (ANum 1))) / empty_state
==>a* e'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** * Typed Arithmetic Expressions *)
(** To motivate the discussion of type systems, let's begin as
usual with an extremely simple toy language. We want it to have
the potential for programs "going wrong" because of runtime type
errors, so we need something a tiny bit more complex than the
language of constants and addition that we used in chapter
[Smallstep]: a single kind of data (just numbers) is too simple,
but just two kinds (numbers and booleans) already gives us enough
material to tell an interesting story.
The language definition is completely routine. The only thing to
notice is that we are _not_ using the [asnum]/[aslist] trick that
we used in chapter [ImpList] to make all the operations total by
forcibly coercing the arguments to [+] (for example) into numbers.
Instead, we simply let terms get stuck if they try to use an
operator with the wrong kind of operands: the [step] relation
doesn't relate them to anything. *)
(* ###################################################################### *)
(** ** Syntax *)
(** Informally:
t ::= true
| false
| if t then t else t
| 0
| succ t
| pred t
| iszero t
Formally:
*)
Inductive tm : Type :=
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm
| tzero : tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tiszero : tm -> tm.
(** _Values_ are [true], [false], and numeric values... *)
Inductive bvalue : tm -> Prop :=
| bv_true : bvalue ttrue
| bv_false : bvalue tfalse.
Inductive nvalue : tm -> Prop :=
| nv_zero : nvalue tzero
| nv_succ : forall t, nvalue t -> nvalue (tsucc t).
Definition value (t:tm) := bvalue t \/ nvalue t.
Hint Constructors bvalue nvalue.
Hint Unfold value.
(* ###################################################################### *)
(** ** Operational Semantics *)
(** Informally:
------------------------------ (ST_IfTrue)
if true then t1 else t2 ==> t1
------------------------------- (ST_IfFalse)
if false then t1 else t2 ==> t2
t1 ==> t1'
------------------------- (ST_If)
if t1 then t2 else t3 ==>
if t1' then t2 else t3
t1 ==> t1'
-------------------- (ST_Succ)
succ t1 ==> succ t1'
------------ (ST_PredZero)
pred 0 ==> 0
numeric value v1
--------------------- (ST_PredSucc)
pred (succ v1) ==> v1
t1 ==> t1'
-------------------- (ST_Pred)
pred t1 ==> pred t1'
----------------- (ST_IszeroZero)
iszero 0 ==> true
numeric value v1
-------------------------- (ST_IszeroSucc)
iszero (succ v1) ==> false
t1 ==> t1'
------------------------ (ST_Iszero)
iszero t1 ==> iszero t1'
Formally:
*)
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
| ST_Succ : forall t1 t1',
t1 ==> t1' ->
(tsucc t1) ==> (tsucc t1')
| ST_PredZero :
(tpred tzero) ==> tzero
| ST_PredSucc : forall t1,
nvalue t1 ->
(tpred (tsucc t1)) ==> t1
| ST_Pred : forall t1 t1',
t1 ==> t1' ->
(tpred t1) ==> (tpred t1')
| ST_IszeroZero :
(tiszero tzero) ==> ttrue
| ST_IszeroSucc : forall t1,
nvalue t1 ->
(tiszero (tsucc t1)) ==> tfalse
| ST_Iszero : forall t1 t1',
t1 ==> t1' ->
(tiszero t1) ==> (tiszero t1')
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If"
| Case_aux c "ST_Succ" | Case_aux c "ST_PredZero"
| Case_aux c "ST_PredSucc" | Case_aux c "ST_Pred"
| Case_aux c "ST_IszeroZero" | Case_aux c "ST_IszeroSucc"
| Case_aux c "ST_Iszero" ].
Hint Constructors step.
(** Notice that the [step] relation doesn't care about whether
expressions make global sense -- it just checks that the operation
in the _next_ reduction step is being applied to the right kinds
of operands. For example, the term [succ true] (i.e., [tsucc
ttrue] in the formal syntax) cannot take a step, but the
almost-as-obviously-nonsensical term
succ (if true then true else true)
can take _one_ step. *)
(* ###################################################################### *)
(** ** Normal Forms and Values *)
(** The first interesting thing about the [step] relation in this
language is that the strong progress theorem from the Smallstep
chapter fails! That is, there are terms that are normal
forms (they can't take a step) but not values (because we have not
included them in our definition of possible "results of
evaluation"). Such terms are _stuck_. *)
Notation step_normal_form := (normal_form step).
Definition stuck (t:tm) : Prop :=
step_normal_form t /\ ~ value t.
Hint Unfold stuck.
(** **** Exercise: 2 stars (some_term_is_stuck) *)
Example some_term_is_stuck :
exists t, stuck t.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** However, although values and normal forms are not the same in this
language, the former set is included in the latter. This is
important because it shows we did not accidentally define things
so that some value could still take a step. *)
(** **** Exercise: 3 stars, optional (value_is_nf) *)
(** Hint: You will reach a point in this proof where you need to
use an induction to reason about a term that is known to be a
numeric value. This induction can be performed either over the
term itself or over the evidence that it is a numeric value. The
proof goes through in either case, but you will find that one way
is quite a bit shorter than the other. For the sake of the
exercise, try to complete the proof both ways. *)
Lemma value_is_nf : forall t,
value t -> step_normal_form t.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (step_deterministic) *)
(** Using [value_is_nf], we can show that the [step] relation is
also deterministic... *)
Theorem step_deterministic:
deterministic step.
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** ** Typing *)
(** The next critical observation about this language is that,
although there are stuck terms, they are all "nonsensical", mixing
booleans and numbers in a way that we don't even _want_ to have a
meaning. We can easily exclude such ill-typed terms by defining a
_typing relation_ that relates terms to the types (either numeric
or boolean) of their final results. *)
Inductive ty : Type :=
| TBool : ty
| TNat : ty.
(** In informal notation, the typing relation is often written
[|- t : T], pronounced "[t] has type [T]." The [|-] symbol is
called a "turnstile". (Below, we're going to see richer typing
relations where an additional "context" argument is written to the
left of the turnstile. Here, the context is always empty.) *)
(**
-------------- (T_True)
|- true : Bool
--------------- (T_False)
|- false : Bool
|- t1 : Bool |- t2 : T |- t3 : T
-------------------------------------- (T_If)
|- if t1 then t2 else t3 : T
---------- (T_Zero)
|- 0 : Nat
|- t1 : Nat
---------------- (T_Succ)
|- succ t1 : Nat
|- t1 : Nat
---------------- (T_Pred)
|- pred t1 : Nat
|- t1 : Nat
------------------- (T_IsZero)
|- iszero t1 : Bool
*)
Inductive has_type : tm -> ty -> Prop :=
| T_True :
has_type ttrue TBool
| T_False :
has_type tfalse TBool
| T_If : forall t1 t2 t3 T,
has_type t1 TBool ->
has_type t2 T ->
has_type t3 T ->
has_type (tif t1 t2 t3) T
| T_Zero :
has_type tzero TNat
| T_Succ : forall t1,
has_type t1 TNat ->
has_type (tsucc t1) TNat
| T_Pred : forall t1,
has_type t1 TNat ->
has_type (tpred t1) TNat
| T_Iszero : forall t1,
has_type t1 TNat ->
has_type (tiszero t1) TBool.
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_True" | Case_aux c "T_False" | Case_aux c "T_If"
| Case_aux c "T_Zero" | Case_aux c "T_Succ" | Case_aux c "T_Pred"
| Case_aux c "T_Iszero" ].
Hint Constructors has_type.
(* ###################################################################### *)
(** *** Examples *)
(** It's important to realize that the typing relation is a
_conservative_ (or _static_) approximation: it does not calculate
the type of the normal form of a term. *)
Example has_type_1 :
has_type (tif tfalse tzero (tsucc tzero)) TNat.
Proof.
apply T_If.
apply T_False.
apply T_Zero.
apply T_Succ.
apply T_Zero.
Qed.
(** (Since we've included all the constructors of the typing relation
in the hint database, the [auto] tactic can actually find this
proof automatically.) *)
Example has_type_not :
~ has_type (tif tfalse tzero ttrue) TBool.
Proof.
intros Contra. solve by inversion 2. Qed.
(** **** Exercise: 1 star (succ_hastype_nat__hastype_nat) *)
Example succ_hastype_nat__hastype_nat : forall t,
has_type (tsucc t) TNat ->
has_type t TNat.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** ** Progress *)
(** The typing relation enjoys two critical properties. The first is
that well-typed normal forms are values (i.e., not stuck). *)
(** **** Exercise: 3 stars, recommended (finish_progress_informal) *)
(** Complete the following proof: *)
(** _Theorem_: If [|- t : T], then either [t] is a value or else
[t ==> t'] for some [t']. *)
(** _Proof_: By induction on a derivation of [|- t : T].
- If the last rule in the derivation is [T_If], then [t = if t1
then t2 else t3], with [|- t1 : Bool], [|- t2 : T] and [|- t3
: T]. By the IH, either [t1] is a value or else [t1] can step
to some [t1'].
- If [t1] is a value, then it is either an [nvalue] or a
[bvalue]. But it cannot be an [nvalue], because we know
[|- t1 : Bool] and there are no rules assigning type
[Bool] to any term that could be an [nvalue]. So [t1]
is a [bvalue] -- i.e., it is either [true] or [false].
If [t1 = true], then [t] steps to [t2] by [ST_IfTrue],
while if [t1 = false], then [t] steps to [t3] by
[ST_IfFalse]. Either way, [t] can step, which is what
we wanted to show.
- If [t1] itself can take a step, then, by [ST_If], so can
[t].
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars (finish_progress) *)
Theorem progress : forall t T,
has_type t T ->
value t \/ exists t', t ==> t'.
Proof with auto.
intros t T HT.
has_type_cases (induction HT) Case...
(* The cases that were obviously values, like T_True and
T_False, were eliminated immediately by auto *)
Case "T_If".
right. inversion IHHT1; clear IHHT1.
SCase "t1 is a value". inversion H; clear H.
SSCase "t1 is a bvalue". inversion H0; clear H0.
SSSCase "t1 is ttrue".
exists t2...
SSSCase "t1 is tfalse".
exists t3...
SSCase "t1 is an nvalue".
solve by inversion 2. (* on H and HT1 *)
SCase "t1 can take a step".
inversion H as [t1' H1].
exists (tif t1' t2 t3)...
(* FILL IN HERE *) Admitted.
(** [] *)
(** This is more interesting than the strong progress theorem that we
saw in the Smallstep chapter, where _all_ normal forms were
values. Here, a term can be stuck, but only if it is ill
typed. *)
(** **** Exercise: 1 star (step_review) *)
(** Quick review. Answer _true_ or _false_. In this language...
- Every well-typed normal form is a value.
- Every value is a normal form.
- The single-step evaluation relation is
a partial function (i.e., it is deterministic).
- The single-step evaluation relation is a _total_ function.
*)
(** [] *)
(* ###################################################################### *)
(** ** Type Preservation *)
(** The second critical property of typing is that, when a well-typed
term takes a step, the result is also a well-typed term.
This theorem is often called the _subject reduction_ property,
because it tells us what happens when the "subject" of the typing
relation is reduced. This terminology comes from thinking of
typing statements as sentences, where the term is the subject and
the type is the predicate. *)
(** **** Exercise: 3 stars, recommended (finish_preservation_informal) *)
(** Complete the following proof: *)
(** _Theorem_: If [|- t : T] and [t ==> t'], then [|- t' : T]. *)
(** _Proof_: By induction on a derivation of [|- t : T].
- If the last rule in the derivation is [T_If], then [t = if t1
then t2 else t3], with [|- t1 : Bool], [|- t2 : T] and [|- t3
: T].
Inspecting the rules for the small-step reduction relation and
remembering that [t] has the form [if ...], we see that the
only ones that could have been used to prove [t ==> t'] are
[ST_IfTrue], [ST_IfFalse], or [ST_If].
- If the last rule was [ST_IfTrue], then [t' = t2]. But we
know that [|- t2 : T], so we are done.
- If the last rule was [ST_IfFalse], then [t' = t3]. But we
know that [|- t3 : T], so we are done.
- If the last rule was [ST_If], then [t' = if t1' then t2
else t3], where [t1 ==> t1']. We know [|- t1 : Bool] so,
by the IH, [|- t1' : Bool]. The [T_If] rule then gives us
[|- if t1' then t2 else t3 : T], as required.
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 2 stars (finish_preservation) *)
Theorem preservation : forall t t' T,
has_type t T ->
t ==> t' ->
has_type t' T.
Proof with auto.
intros t t' T HT HE.
generalize dependent t'.
has_type_cases (induction HT) Case;
(* every case needs to introduce a couple of things *)
intros t' HE;
(* and we can deal with several impossible
cases all at once *)
try (solve by inversion).
Case "T_If". inversion HE; subst.
SCase "ST_IFTrue". assumption.
SCase "ST_IfFalse". assumption.
SCase "ST_If". apply T_If; try assumption.
apply IHHT1; assumption.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (preservation_alternate_proof) *)
(** Now prove the same property again by induction on the
_evaluation_ derivation instead of on the typing derivation.
Begin by carefully reading and thinking about the first few
lines of the above proof to make sure you understand what
each one is doing. The set-up for this proof is similar, but
not exactly the same. *)
Theorem preservation' : forall t t' T,
has_type t T ->
t ==> t' ->
has_type t' T.
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** ** Type Soundness *)
(** Putting progress and preservation together, we can see that a
well-typed term can _never_ reach a stuck state. *)
Definition multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Corollary soundness : forall t t' T,
has_type t T ->
t ==>* t' ->
~(stuck t').
Proof.
intros t t' T HT P. induction P; intros [R S].
destruct (progress x T HT); auto.
apply IHP. apply (preservation x y T HT H).
unfold stuck. split; auto. Qed.
(* ###################################################################### *)
(** ** Additional Exercises *)
(** **** Exercise: 2 stars, recommended (subject_expansion) *)
(** Having seen the subject reduction property, it is reasonable to
wonder whether the opposity property -- subject _expansion_ --
also holds. That is, is it always the case that, if [t ==> t']
and [has_type t' T], then [has_type t T]? If so, prove it. If
not, give a counter-example. (You do not need to prove your
counter-example in Coq, but feel free to do so if you like.)
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 2 stars (variation1) *)
(** Suppose we add the following two new rules to the reduction
relation:
| ST_PredTrue :
(tpred ttrue) ==> (tpred tfalse)
| ST_PredFalse :
(tpred tfalse) ==> (tpred ttrue)
Which of the following properties remain true in the presence
of these rules? For each one, write either "remains true" or
else "becomes false." If a property becomes false, give a
counterexample.
- Determinism of [step]
- Progress
- Preservation
[]
*)
(** **** Exercise: 2 stars (variation2) *)
(** Suppose, instead, that we add this new rule to the typing relation:
| T_IfFunny : forall t2 t3,
has_type t2 TNat ->
has_type (tif ttrue t2 t3) TNat
Which of the following properties remain true in the presence of
this rule? (Answer in the same style as above.)
- Determinism of [step]
- Progress
- Preservation
[]
*)
(** **** Exercise: 2 stars (variation3) *)
(** Suppose, instead, that we add this new rule to the typing relation:
| T_SuccBool : forall t,
has_type t TBool ->
has_type (tsucc t) TBool
Which of the following properties remain true in the presence of
this rule? (Answer in the same style as above.)
- Determinism of [step]
- Progress
- Preservation
[]
*)
(** **** Exercise: 2 stars (variation4) *)
(** Suppose, instead, that we add this new rule to the [step] relation:
| ST_Funny1 : forall t2 t3,
(tif ttrue t2 t3) ==> t3
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 2 stars (variation5) *)
(** Suppose instead that we add this rule:
| ST_Funny2 : forall t1 t2 t2' t3,
t2 ==> t2' ->
(tif t1 t2 t3) ==> (tif t1 t2' t3)
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 2 stars (variation6) *)
(** Suppose instead that we add this rule:
| ST_Funny3 :
(tpred tfalse) ==> (tpred (tpred tfalse))
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 2 stars (variation7) *)
(** Suppose instead that we add this rule:
| T_Funny4 :
has_type tzero TBool
]]
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 2 stars (variation8) *)
(** Suppose instead that we add this rule:
| T_Funny5 :
has_type (tpred tzero) TBool
]]
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 3 stars, optional (more_variations) *)
(** Make up some exercises of your own along the same lines as
the ones above. Try to find ways of selectively breaking
properties -- i.e., ways of changing the definitions that
break just one of the properties and leave the others alone.
[]
*)
(** **** Exercise: 1 star (remove_predzero) *)
(** The evaluation rule [E_PredZero] is a bit counter-intuitive: we
might feel that it makes more sense for the predecessor of zero to
be undefined, rather than being defined to be zero. Can we
achieve this simply by removing the rule from the definition of
[step]? Would doing so create any problems elsewhere?
(* FILL IN HERE *)
[] *)
(** **** Exercise: 4 stars, optional (prog_pres_bigstep) *)
(** Suppose our evaluation relation is defined in the big-step style.
What are the appropriate analogs of the progress and preservation
properties?
(* FILL IN HERE *)
[]
*)
|
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_cpu.v ////
//// ////
//// ////
//// This file is part of the SoC Debug Interface. ////
//// http://www.opencores.org/projects/DebugInterface/ ////
//// ////
//// Author(s): ////
//// Igor Mohor ([email protected]) ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_cpu_defines.v"
// Top module
module dbg_cpu(
// JTAG signals
tck_i,
tdi_i,
tdo_o,
// TAP states
shift_dr_i,
pause_dr_i,
update_dr_i,
cpu_ce_i,
crc_match_i,
crc_en_o,
shift_crc_o,
rst_i,
// CPU
cpu_clk_i,
cpu_addr_o, cpu_data_i, cpu_data_o, cpu_bp_i, cpu_stall_o,
cpu_stb_o,
cpu_we_o, cpu_ack_i, cpu_rst_o
);
// JTAG signals
input tck_i;
input tdi_i;
output tdo_o;
// TAP states
input shift_dr_i;
input pause_dr_i;
input update_dr_i;
input cpu_ce_i;
input crc_match_i;
output crc_en_o;
output shift_crc_o;
input rst_i;
// CPU
input cpu_clk_i;
output [31:0] cpu_addr_o;
output [31:0] cpu_data_o;
input cpu_bp_i;
output cpu_stall_o;
input [31:0] cpu_data_i;
output cpu_stb_o;
output cpu_we_o;
input cpu_ack_i;
output cpu_rst_o;
reg cpu_stb_o;
wire cpu_reg_stall;
reg tdo_o;
reg cpu_ack_q;
reg cpu_ack_csff;
reg cpu_ack_tck;
reg [31:0] cpu_dat_tmp, cpu_data_dsff;
reg [31:0] cpu_addr_dsff;
reg cpu_we_dsff;
reg [`DBG_CPU_DR_LEN -1 :0] dr;
wire enable;
wire cmd_cnt_en;
reg [`DBG_CPU_CMD_CNT_WIDTH -1:0] cmd_cnt;
wire cmd_cnt_end;
reg cmd_cnt_end_q;
reg addr_len_cnt_en;
reg [5:0] addr_len_cnt;
wire addr_len_cnt_end;
reg addr_len_cnt_end_q;
reg crc_cnt_en;
reg [`DBG_CPU_CRC_CNT_WIDTH -1:0] crc_cnt;
wire crc_cnt_end;
reg crc_cnt_end_q;
reg data_cnt_en;
reg [`DBG_CPU_DATA_CNT_WIDTH:0] data_cnt;
reg [`DBG_CPU_DATA_CNT_LIM_WIDTH:0] data_cnt_limit;
wire data_cnt_end;
reg data_cnt_end_q;
reg crc_match_reg;
reg [`DBG_CPU_ACC_TYPE_LEN -1:0] acc_type;
reg [`DBG_CPU_ADR_LEN -1:0] adr;
reg [`DBG_CPU_LEN_LEN -1:0] len;
reg [`DBG_CPU_LEN_LEN:0] len_var;
wire [`DBG_CPU_CTRL_LEN -1:0]ctrl_reg;
reg start_rd_tck;
reg rd_tck_started;
reg start_rd_csff;
reg start_cpu_rd;
reg start_cpu_rd_q;
reg start_wr_tck;
reg start_wr_csff;
reg start_cpu_wr;
reg start_cpu_wr_q;
reg status_cnt_en;
wire status_cnt_end;
wire half, long;
reg half_q, long_q;
reg [`DBG_CPU_STATUS_CNT_WIDTH -1:0] status_cnt;
reg [`DBG_CPU_STATUS_LEN -1:0] status;
reg cpu_overrun, cpu_overrun_csff, cpu_overrun_tck;
reg underrun_tck;
reg busy_cpu;
reg busy_tck;
reg cpu_end;
reg cpu_end_rst;
reg cpu_end_rst_csff;
reg cpu_end_csff;
reg cpu_end_tck, cpu_end_tck_q;
reg busy_csff;
reg latch_data;
reg update_dr_csff, update_dr_cpu;
wire [`DBG_CPU_CTRL_LEN -1:0] cpu_reg_data_i;
wire cpu_reg_we;
reg set_addr, set_addr_csff, set_addr_cpu, set_addr_cpu_q;
wire [31:0] input_data;
wire len_eq_0;
wire crc_cnt_31;
reg fifo_full;
reg [7:0] mem [0:3];
reg cpu_ce_csff;
reg mem_ptr_init;
reg [`DBG_CPU_CMD_LEN -1: 0] curr_cmd;
wire curr_cmd_go;
reg curr_cmd_go_q;
wire curr_cmd_wr_comm;
wire curr_cmd_wr_ctrl;
wire curr_cmd_rd_comm;
wire curr_cmd_rd_ctrl;
wire acc_type_read;
wire acc_type_write;
assign enable = cpu_ce_i & shift_dr_i;
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC
assign curr_cmd_go = (curr_cmd == `DBG_CPU_GO) && cmd_cnt_end;
assign curr_cmd_wr_comm = (curr_cmd == `DBG_CPU_WR_COMM) && cmd_cnt_end;
assign curr_cmd_wr_ctrl = (curr_cmd == `DBG_CPU_WR_CTRL) && cmd_cnt_end;
assign curr_cmd_rd_comm = (curr_cmd == `DBG_CPU_RD_COMM) && cmd_cnt_end;
assign curr_cmd_rd_ctrl = (curr_cmd == `DBG_CPU_RD_CTRL) && cmd_cnt_end;
assign acc_type_read = (acc_type == `DBG_CPU_READ);
assign acc_type_write = (acc_type == `DBG_CPU_WRITE);
// Shift register for shifting in and out the data
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
begin
latch_data <= 1'b0;
dr <= {`DBG_CPU_DR_LEN{1'b0}};
end
else if (curr_cmd_rd_comm && crc_cnt_31) // Latching data (from internal regs)
begin
dr[`DBG_CPU_DR_LEN -1:0] <= {acc_type, adr, len};
end
else if (curr_cmd_rd_ctrl && crc_cnt_31) // Latching data (from control regs)
begin
dr[`DBG_CPU_DR_LEN -1:0] <= {ctrl_reg, {`DBG_CPU_DR_LEN -`DBG_CPU_CTRL_LEN{1'b0}}};
end
else if (acc_type_read && curr_cmd_go && crc_cnt_31) // Latchind first data (from WB)
begin
dr[31:0] <= input_data[31:0];
latch_data <= 1'b1;
end
else if (acc_type_read && curr_cmd_go && crc_cnt_end) // Latching data (from WB)
begin
case (acc_type) // synthesis parallel_case full_case
`DBG_CPU_READ: begin
if(long & (~long_q))
begin
dr[31:0] <= input_data[31:0];
latch_data <= 1'b1;
end
else if (enable)
begin
dr[31:0] <= {dr[30:0], 1'b0};
latch_data <= 1'b0;
end
end
default: begin
end
endcase
end
else if (enable && (!addr_len_cnt_end))
begin
dr <= {dr[`DBG_CPU_DR_LEN -2:0], tdi_i};
end
end
assign cmd_cnt_en = enable & (~cmd_cnt_end);
// Command counter
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
cmd_cnt <= {`DBG_CPU_CMD_CNT_WIDTH{1'b0}};
else if (update_dr_i)
cmd_cnt <= {`DBG_CPU_CMD_CNT_WIDTH{1'b0}};
else if (cmd_cnt_en)
cmd_cnt <= cmd_cnt + 1;
end
// Assigning current command
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
curr_cmd <= {`DBG_CPU_CMD_LEN{1'b0}};
else if (update_dr_i)
curr_cmd <= {`DBG_CPU_CMD_LEN{1'b0}};
else if (cmd_cnt == (`DBG_CPU_CMD_LEN -1))
curr_cmd <= {dr[`DBG_CPU_CMD_LEN-2 :0], tdi_i};
end
// Assigning current command
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
curr_cmd_go_q <= 1'b0;
else
curr_cmd_go_q <= curr_cmd_go;
end
always @ (enable or cmd_cnt_end or addr_len_cnt_end or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_rd_comm or curr_cmd_rd_ctrl or crc_cnt_end)
begin
if (enable && (!addr_len_cnt_end))
begin
if (cmd_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
addr_len_cnt_en = 1'b1;
else if (crc_cnt_end && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
addr_len_cnt_en = 1'b1;
else
addr_len_cnt_en = 1'b0;
end
else
addr_len_cnt_en = 1'b0;
end
// Address/length counter
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
addr_len_cnt <= 6'h0;
else if (update_dr_i)
addr_len_cnt <= 6'h0;
else if (addr_len_cnt_en)
addr_len_cnt <= addr_len_cnt + 1;
end
always @ (enable or data_cnt_end or cmd_cnt_end or curr_cmd_go or acc_type_write or acc_type_read or crc_cnt_end)
begin
if (enable && (!data_cnt_end))
begin
if (cmd_cnt_end && curr_cmd_go && acc_type_write)
data_cnt_en = 1'b1;
else if (crc_cnt_end && curr_cmd_go && acc_type_read)
data_cnt_en = 1'b1;
else
data_cnt_en = 1'b0;
end
else
data_cnt_en = 1'b0;
end
// Data counter
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
data_cnt <= {`DBG_CPU_DATA_CNT_WIDTH+1{1'b0}};
else if (update_dr_i)
data_cnt <= {`DBG_CPU_DATA_CNT_WIDTH+1{1'b0}};
else if (data_cnt_en)
data_cnt <= data_cnt + 1;
end
// Upper limit. Data counter counts until this value is reached.
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
data_cnt_limit <= {`DBG_CPU_DATA_CNT_LIM_WIDTH+1{1'b0}};
else if (update_dr_i)
data_cnt_limit <= len + 1;
end
always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
begin
if (enable && (!crc_cnt_end) && cmd_cnt_end)
begin
if (addr_len_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
crc_cnt_en = 1'b1;
else if (data_cnt_end && curr_cmd_go && acc_type_write)
crc_cnt_en = 1'b1;
else if (cmd_cnt_end && (curr_cmd_go && acc_type_read || curr_cmd_rd_comm || curr_cmd_rd_ctrl))
crc_cnt_en = 1'b1;
else
crc_cnt_en = 1'b0;
end
else
crc_cnt_en = 1'b0;
end
// crc counter
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
crc_cnt <= {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
else if(crc_cnt_en)
crc_cnt <= crc_cnt + 1;
else if (update_dr_i)
crc_cnt <= {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
end
assign cmd_cnt_end = cmd_cnt == `DBG_CPU_CMD_LEN;
assign addr_len_cnt_end = addr_len_cnt == `DBG_CPU_DR_LEN;
assign crc_cnt_end = crc_cnt == `DBG_CPU_CRC_CNT_WIDTH'd32;
assign crc_cnt_31 = crc_cnt == `DBG_CPU_CRC_CNT_WIDTH'd31;
assign data_cnt_end = (data_cnt == {data_cnt_limit, 3'b000});
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
begin
crc_cnt_end_q <= 1'b0;
cmd_cnt_end_q <= 1'b0;
data_cnt_end_q <= 1'b0;
addr_len_cnt_end_q <= 1'b0;
end
else
begin
crc_cnt_end_q <= crc_cnt_end;
cmd_cnt_end_q <= cmd_cnt_end;
data_cnt_end_q <= data_cnt_end;
addr_len_cnt_end_q <= addr_len_cnt_end;
end
end
// Status counter is made of 4 serialy connected registers
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
status_cnt <= {`DBG_CPU_STATUS_CNT_WIDTH{1'b0}};
else if (update_dr_i)
status_cnt <= {`DBG_CPU_STATUS_CNT_WIDTH{1'b0}};
else if (status_cnt_en)
status_cnt <= status_cnt + 1;
end
always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or
curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or
acc_type_read or data_cnt_end or addr_len_cnt_end)
begin
if (enable && (!status_cnt_end))
begin
if (crc_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
status_cnt_en = 1'b1;
else if (crc_cnt_end && curr_cmd_go && acc_type_write)
status_cnt_en = 1'b1;
else if (data_cnt_end && curr_cmd_go && acc_type_read)
status_cnt_en = 1'b1;
else if (addr_len_cnt_end && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
status_cnt_en = 1'b1;
else
status_cnt_en = 1'b0;
end
else
status_cnt_en = 1'b0;
end
assign status_cnt_end = status_cnt == `DBG_CPU_STATUS_LEN;
// Latching acc_type, address and length
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
begin
acc_type <= {`DBG_CPU_ACC_TYPE_LEN{1'b0}};
adr <= {`DBG_CPU_ADR_LEN{1'b0}};
len <= {`DBG_CPU_LEN_LEN{1'b0}};
set_addr <= 1'b0;
end
else if(crc_cnt_end && (!crc_cnt_end_q) && crc_match_i && curr_cmd_wr_comm)
begin
acc_type <= dr[`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1 : `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN];
adr <= dr[`DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1 : `DBG_CPU_LEN_LEN];
len <= dr[`DBG_CPU_LEN_LEN -1:0];
set_addr <= 1'b1;
end
else if(cpu_end_tck) // Writing back the address
begin
adr <= cpu_addr_dsff;
end
else
set_addr <= 1'b0;
end
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
crc_match_reg <= 1'b0;
else if(crc_cnt_end & (~crc_cnt_end_q))
crc_match_reg <= crc_match_i;
end
// Length counter
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
len_var <= {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
else if(update_dr_i)
len_var <= len + 'd1;
else if (start_rd_tck)
begin
if (len_var > 4)
len_var <= len_var - 'd4;
else
len_var <= {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
end
end
assign len_eq_0 = len_var == 'h0;
assign half = data_cnt[3:0] == 4'd15;
assign long = data_cnt[4:0] == 5'd31;
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
begin
half_q <= 1'b0;
long_q <= 1'b0;
end
else
begin
half_q <= half;
long_q <= long;
end
end
// Start cpu write cycle
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
begin
start_wr_tck <= 1'b0;
cpu_dat_tmp <= 32'd0;
end
else if (curr_cmd_go && acc_type_write)
begin
if (long_q)
begin
start_wr_tck <= 1'b1;
cpu_dat_tmp <= dr[31:0];
end
else
begin
start_wr_tck <= 1'b0;
end
end
else
start_wr_tck <= 1'b0;
end
// cpu_data_o in WB clk domain
always @ (posedge cpu_clk_i)
begin
cpu_data_dsff <= cpu_dat_tmp;
end
assign cpu_data_o = cpu_data_dsff;
// Start cpu read cycle
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
start_rd_tck <= 1'b0;
else if (curr_cmd_go && (!curr_cmd_go_q) && acc_type_read) // First read after cmd is entered
start_rd_tck <= 1'b1;
else if ((!start_rd_tck) && curr_cmd_go && acc_type_read && (!len_eq_0) && (!fifo_full) && (!rd_tck_started) && (!cpu_ack_tck))
start_rd_tck <= 1'b1;
else
start_rd_tck <= 1'b0;
end
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
rd_tck_started <= 1'b0;
else if (update_dr_i || cpu_end_tck && (!cpu_end_tck_q))
rd_tck_started <= 1'b0;
else if (start_rd_tck)
rd_tck_started <= 1'b1;
end
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if (rst_i)
begin
start_rd_csff <= 1'b0;
start_cpu_rd <= 1'b0;
start_cpu_rd_q <= 1'b0;
start_wr_csff <= 1'b0;
start_cpu_wr <= 1'b0;
start_cpu_wr_q <= 1'b0;
set_addr_csff <= 1'b0;
set_addr_cpu <= 1'b0;
set_addr_cpu_q <= 1'b0;
cpu_ack_q <= 1'b0;
end
else
begin
start_rd_csff <= start_rd_tck;
start_cpu_rd <= start_rd_csff;
start_cpu_rd_q <= start_cpu_rd;
start_wr_csff <= start_wr_tck;
start_cpu_wr <= start_wr_csff;
start_cpu_wr_q <= start_cpu_wr;
set_addr_csff <= set_addr;
set_addr_cpu <= set_addr_csff;
set_addr_cpu_q <= set_addr_cpu;
cpu_ack_q <= cpu_ack_i;
end
end
// cpu_stb_o
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if (rst_i)
cpu_stb_o <= 1'b0;
else if (cpu_ack_i)
cpu_stb_o <= 1'b0;
else if ((start_cpu_wr && (!start_cpu_wr_q)) || (start_cpu_rd && (!start_cpu_rd_q)))
cpu_stb_o <= 1'b1;
end
assign cpu_stall_o = cpu_stb_o | cpu_reg_stall;
// cpu_addr_o logic
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if (rst_i)
cpu_addr_dsff <= 32'h0;
else if (set_addr_cpu && (!set_addr_cpu_q)) // Setting starting address
cpu_addr_dsff <= adr;
else if (cpu_ack_i && (!cpu_ack_q))
//cpu_addr_dsff <= cpu_addr_dsff + 3'd4;
// Increment by just 1, to allow block reading -- jb 090901
cpu_addr_dsff <= cpu_addr_dsff + 'd1;
end
assign cpu_addr_o = cpu_addr_dsff;
always @ (posedge cpu_clk_i)
begin
cpu_we_dsff <= curr_cmd_go && acc_type_write;
end
assign cpu_we_o = cpu_we_dsff;
// Logic for detecting end of transaction
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if (rst_i)
cpu_end <= 1'b0;
else if (cpu_ack_i && (!cpu_ack_q))
cpu_end <= 1'b1;
else if (cpu_end_rst)
cpu_end <= 1'b0;
end
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
begin
cpu_end_csff <= 1'b0;
cpu_end_tck <= 1'b0;
cpu_end_tck_q <= 1'b0;
end
else
begin
cpu_end_csff <= cpu_end;
cpu_end_tck <= cpu_end_csff;
cpu_end_tck_q <= cpu_end_tck;
end
end
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if (rst_i)
begin
cpu_end_rst_csff <= 1'b0;
cpu_end_rst <= 1'b0;
end
else
begin
cpu_end_rst_csff <= cpu_end_tck;
cpu_end_rst <= cpu_end_rst_csff;
end
end
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if (rst_i)
busy_cpu <= 1'b0;
else if (cpu_end_rst)
busy_cpu <= 1'b0;
else if (cpu_stb_o)
busy_cpu <= 1'b1;
end
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
begin
busy_csff <= 1'b0;
busy_tck <= 1'b0;
update_dr_csff <= 1'b0;
update_dr_cpu <= 1'b0;
end
else
begin
busy_csff <= busy_cpu;
busy_tck <= busy_csff;
update_dr_csff <= update_dr_i;
update_dr_cpu <= update_dr_csff;
end
end
// Detecting overrun when write operation.
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if (rst_i)
cpu_overrun <= 1'b0;
else if(start_cpu_wr && (!start_cpu_wr_q) && cpu_ack_i)
cpu_overrun <= 1'b1;
else if(update_dr_cpu) // error remains active until update_dr arrives
cpu_overrun <= 1'b0;
end
// Detecting underrun when read operation
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
underrun_tck <= 1'b0;
else if(latch_data && (!fifo_full) && (!data_cnt_end))
underrun_tck <= 1'b1;
else if(update_dr_i) // error remains active until update_dr arrives
underrun_tck <= 1'b0;
end
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
begin
cpu_overrun_csff <= 1'b0;
cpu_overrun_tck <= 1'b0;
cpu_ack_csff <= 1'b0;
cpu_ack_tck <= 1'b0;
end
else
begin
cpu_overrun_csff <= cpu_overrun;
cpu_overrun_tck <= cpu_overrun_csff;
cpu_ack_csff <= cpu_ack_i;
cpu_ack_tck <= cpu_ack_csff;
end
end
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if (rst_i)
begin
cpu_ce_csff <= 1'b0;
mem_ptr_init <= 1'b0;
end
else
begin
cpu_ce_csff <= cpu_ce_i;
mem_ptr_init <= ~cpu_ce_csff;
end
end
// Logic for latching data that is read from cpu
always @ (posedge cpu_clk_i)
begin
if (cpu_ack_i && (!cpu_ack_q))
begin
mem[0] <= cpu_data_i[31:24];
mem[1] <= cpu_data_i[23:16];
mem[2] <= cpu_data_i[15:08];
mem[3] <= cpu_data_i[07:00];
end
end
assign input_data = {mem[0], mem[1], mem[2], mem[3]};
// Fifo counter and empty/full detection
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
fifo_full <= 1'h0;
else if (update_dr_i)
fifo_full <= 1'h0;
else if (cpu_end_tck && (!cpu_end_tck_q) && (!latch_data) && (!fifo_full)) // incrementing
fifo_full <= 1'b1;
else if (!(cpu_end_tck && (!cpu_end_tck_q)) && latch_data && (fifo_full)) // decrementing
fifo_full <= 1'h0;
end
// TDO multiplexer
always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or acc_type_read or crc_match_i or data_cnt_end or dr or data_cnt_end_q or crc_match_reg or status_cnt_en or status or addr_len_cnt_end or addr_len_cnt_end_q or curr_cmd_rd_comm or curr_cmd_rd_ctrl)
begin
if (pause_dr_i)
begin
tdo_o = busy_tck;
end
else if (crc_cnt_end && (!crc_cnt_end_q) && (curr_cmd_wr_comm || curr_cmd_wr_ctrl || curr_cmd_go && acc_type_write ))
begin
tdo_o = ~crc_match_i;
end
else if (curr_cmd_go && acc_type_read && crc_cnt_end && (!data_cnt_end))
begin
tdo_o = dr[31];
end
else if (curr_cmd_go && acc_type_read && data_cnt_end && (!data_cnt_end_q))
begin
tdo_o = ~crc_match_reg;
end
else if ((curr_cmd_rd_comm || curr_cmd_rd_ctrl) && addr_len_cnt_end && (!addr_len_cnt_end_q))
begin
tdo_o = ~crc_match_reg;
end
else if ((curr_cmd_rd_comm || curr_cmd_rd_ctrl) && crc_cnt_end && (!addr_len_cnt_end))
begin
tdo_o = dr[`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1];
end
else if (status_cnt_en)
begin
tdo_o = status[3];
end
else
begin
tdo_o = 1'b0;
end
end
// Status register
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
begin
status <= {`DBG_CPU_STATUS_LEN{1'b0}};
end
else if(crc_cnt_end && (!crc_cnt_end_q) && (!(curr_cmd_go && acc_type_read)))
begin
status <= {1'b0, 1'b0, cpu_overrun_tck, crc_match_i};
end
else if (data_cnt_end && (!data_cnt_end_q) && curr_cmd_go && acc_type_read)
begin
status <= {1'b0, 1'b0, underrun_tck, crc_match_reg};
end
else if (addr_len_cnt_end && (!addr_len_cnt_end) && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
begin
status <= {1'b0, 1'b0, 1'b0, crc_match_reg};
end
else if (shift_dr_i && (!status_cnt_end))
begin
status <= {status[`DBG_CPU_STATUS_LEN -2:0], status[`DBG_CPU_STATUS_LEN -1]};
end
end
// Following status is shifted out (MSB first):
// 3. bit: 1 if crc is OK, else 0
// 2. bit: 1'b0
// 1. bit: 0
// 0. bit: 1 if overrun occured during write (data couldn't be written fast enough)
// or underrun occured during read (data couldn't be read fast enough)
// Connecting cpu registers
assign cpu_reg_we = crc_cnt_end && (!crc_cnt_end_q) && crc_match_i && curr_cmd_wr_ctrl;
assign cpu_reg_data_i = dr[`DBG_CPU_DR_LEN -1:`DBG_CPU_DR_LEN -`DBG_CPU_CTRL_LEN];
dbg_cpu_registers i_dbg_cpu_registers
(
.data_i (cpu_reg_data_i),
.we_i (cpu_reg_we),
.tck_i (tck_i),
.bp_i (cpu_bp_i),
.rst_i (rst_i),
.cpu_clk_i (cpu_clk_i),
.ctrl_reg_o (ctrl_reg),
.cpu_stall_o (cpu_reg_stall),
.cpu_rst_o (cpu_rst_o)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Differential Signaling Input Buffer with Differential Outputs
// /___/ /\ Filename : IBUFDS_DIFF_OUT_IBUFDISABLE.v
// \ \ / \ Timestamp : Wed Dec 8 17:04:24 PST 2010
// \___\/\___\
//
// Revision:
// 12/08/10 - Initial version.
// 04/04/11 - CR 604808 fix
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- added attribute USE_IBUFDISABLE
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_DIFF_OUT_IBUFDISABLE (O, OB, I, IB, IBUFDISABLE);
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SIM_DEVICE = "7SERIES";
parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
output O;
output OB;
input I;
input IB;
input IBUFDISABLE;
reg o_out;
reg DQS_BIAS_BINARY = 1'b0;
wire out_val;
wire out_b_val;
initial begin
if ((SIM_DEVICE != "7SERIES") &&
(SIM_DEVICE != "ULTRASCALE")) begin
$display("Attribute Syntax Error : The attribute SIM_DEVICE on IBUFDS_DIFF_OUT_IBUFDISABLE instance %m is set to %s. Legal values for this attribute are 7SERIES or ULTRASCALE.", SIM_DEVICE);
$finish;
end
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on IBUFDS_DIFF_OUT_IBUFDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DQS_BIAS);
$finish;
end
endcase
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFDS_DIFF_OUT_IBUFDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUFDS_DIFF_OUT_IBUFDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
end
always @(I or IB or DQS_BIAS_BINARY) begin
if (I == 1'b1 && IB == 1'b0)
o_out <= I;
else if (I == 1'b0 && IB == 1'b1)
o_out <= I;
else if ((I === 1'bz || I == 1'b0) && (IB === 1'bz || IB == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if (I === 1'bx || IB === 1'bx)
o_out <= 1'bx;
end
generate
case (SIM_DEVICE)
"7SERIES" : begin
assign out_val = 1'b1;
assign out_b_val = 1'b1;
end
"ULTRASCALE" : begin
assign out_val = 1'b0;
assign out_b_val = 1'bx;
end
endcase
endgenerate
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign O = (IBUFDISABLE == 0)? o_out : (IBUFDISABLE == 1)? out_val : 1'bx;
assign OB = (IBUFDISABLE == 0)? ~o_out : (IBUFDISABLE == 1)? out_b_val : 1'bx;
end
"FALSE" : begin
assign O = o_out;
assign OB = ~o_out;
end
endcase
endgenerate
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
(IB => OB) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
|
module top;
reg pass;
enum bit signed [7:0] {a = 1, b = 2, c = 3, d = 4} enum_var;
initial begin
pass = 1'b1;
// Add another test that a negative value is not valid.
// Also an out of range value stays out of range.
enum_var = a;
if (enum_var !== enum_var.first) begin
$display("FAILED: initialization, expected %d, got %d", a, enum_var);
pass = 1'b0;
end
enum_var = enum_var.next;
enum_var = enum_var.prev;
enum_var = enum_var.next();
if (enum_var !== b) begin
$display("FAILED: next(), expected %d, got %d", b, enum_var);
pass = 1'b0;
end
enum_var = enum_var.next(0);
if (enum_var !== b) begin
$display("FAILED: next(0), expected %d, got %d", b, enum_var);
pass = 1'b0;
end
enum_var = enum_var.next(1);
if (enum_var !== c) begin
$display("FAILED: next(1), expected %d, got %d", c, enum_var);
pass = 1'b0;
end
enum_var = enum_var.next(2);
if (enum_var !== a) begin
$display("FAILED: next(2), expected %d, got %d", a, enum_var);
pass = 1'b0;
end
enum_var = enum_var.prev();
if (enum_var !== d) begin
$display("FAILED: prev(), expected %d, got %d", d, enum_var);
pass = 1'b0;
end
enum_var = enum_var.prev(0);
if (enum_var !== d) begin
$display("FAILED: prev(0), expected %d, got %d", d, enum_var);
pass = 1'b0;
end
enum_var = enum_var.prev(1);
if (enum_var !== c) begin
$display("FAILED: prev(1), expected %d, got %d", c, enum_var);
pass = 1'b0;
end
enum_var = enum_var.prev(2);
if (enum_var !== a) begin
$display("FAILED: prev(2), expected %d, got %d", a, enum_var);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB4_S16 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_64x22(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 6;
parameter dw = 22;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
wire [9:0] unconnected;
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_64x22 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_64x22_bist artisan_ssp(
`else
art_hssp_64x22 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_64x22 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_64x22_bist vs_ssp(
`else
vs_hdsp_64x22 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.ADDR({2'b00, addr}),
.DI(di[15:0]),
.EN(ce),
.WE(we),
.DO(doq[15:0])
);
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(rst),
.ADDR({2'b00, addr}),
.DI({unconnected, di[21:16]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[21:16]})
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB4_S16
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O2BB2AI_PP_BLACKBOX_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2AI_PP_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
typedef enum {
E01 = 1,
E03 = 3,
E04 = 4
} my_t;
integer cyc=0;
my_t e;
int arrayfits [e.num]; // Check can use as constant
string all;
// Check constification
initial begin
e = E03;
`checkh(e.first, E01);
`checkh(e.last, E04);
`checkh(e.last(), E04);
`checkh(e.next, E04);
`checkh(e.next(), E04);
`checkh(e.next(1), E04);
//Unsup: `checkh(e.next(2), E01);
`checkh(e.prev, E01);
`checkh(e.prev(1), E01);
//Unsup: `checkh(e.prev(2), E04);
`checkh(e.num, 3);
`checks(e.name, "E03");
//
all = "";
for (my_t e = e.first; e != e.last; e = e.next) begin
all = {all, e.name};
end
e = e.last;
all = {all, e.name};
`checks(all, "E01E03E04");
end
// Check runtime
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
e <= E01;
end
else if (cyc==1) begin
`checks(e.name, "E01");
`checkh(e.next, E03);
`checkh(e.next(1), E03);
//Unsup: `checkh(e.next(2), E04);
`checkh(e.prev, E04);
`checkh(e.prev(1), E04);
//Unsup: `checkh(e.prev(2), E03);
e <= E03;
end
else if (cyc==2) begin
`checks(e.name, "E03");
`checkh(e.next, E04);
`checkh(e.next(1), E04);
//Unsup: `checkh(e.next(2), E01);
`checkh(e.prev, E01);
`checkh(e.prev(1), E01);
//Unsup: `checkh(e.prev(2), E04);
e <= E04;
end
else if (cyc==3) begin
`checks(e.name, "E04");
`checkh(e.next, E01);
`checkh(e.next(1), E01);
//Unsup: `checkh(e.next(2), E03);
`checkh(e.prev, E03);
`checkh(e.prev(1), E03);
//Unsup: `checkh(e.prev(2), E01);
e <= E01;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module ad_gt_common_1 (
// reset and clocks
qpll0_rst,
qpll0_ref_clk_in,
qpll1_rst,
qpll1_ref_clk_in,
qpll_clk,
qpll_ref_clk,
qpll_locked,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter integer ID = 0;
parameter integer GTH_OR_GTX_N = 0;
parameter integer QPLL0_ENABLE = 1;
parameter integer QPLL0_REFCLK_DIV = 2;
parameter [26:0] QPLL0_CFG = 27'h06801C1;
parameter integer QPLL0_FBDIV_RATIO = 1'b1;
parameter [ 9:0] QPLL0_FBDIV = 10'b0000110000;
parameter integer QPLL1_ENABLE = 1;
parameter integer QPLL1_REFCLK_DIV = 2;
parameter [26:0] QPLL1_CFG = 27'h06801C1;
parameter integer QPLL1_FBDIV_RATIO = 1'b1;
parameter [ 9:0] QPLL1_FBDIV = 10'b0000110000;
// reset and clocks
input qpll0_rst;
input qpll0_ref_clk_in;
input qpll1_rst;
input qpll1_ref_clk_in;
output [ 7:0] qpll_clk;
output [ 7:0] qpll_ref_clk;
output [ 7:0] qpll_locked;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
wire up_drp_qpll0_sel_s;
wire up_drp_qpll0_wr_s;
wire [11:0] up_drp_qpll0_addr_s;
wire [15:0] up_drp_qpll0_wdata_s;
wire [15:0] up_drp_qpll0_rdata_s;
wire up_drp_qpll0_ready_s;
wire up_drp_qpll1_sel_s;
wire up_drp_qpll1_wr_s;
wire [11:0] up_drp_qpll1_addr_s;
wire [15:0] up_drp_qpll1_wdata_s;
wire [15:0] up_drp_qpll1_rdata_s;
wire up_drp_qpll1_ready_s;
// replicate to match channels
assign qpll_clk[1] = qpll_clk[0];
assign qpll_ref_clk[1] = qpll_ref_clk[0];
assign qpll_locked[1] = qpll_locked[0];
assign qpll_clk[2] = qpll_clk[0];
assign qpll_ref_clk[2] = qpll_ref_clk[0];
assign qpll_locked[2] = qpll_locked[0];
assign qpll_clk[3] = qpll_clk[0];
assign qpll_ref_clk[3] = qpll_ref_clk[0];
assign qpll_locked[3] = qpll_locked[0];
assign qpll_clk[5] = qpll_clk[4];
assign qpll_ref_clk[5] = qpll_ref_clk[4];
assign qpll_locked[5] = qpll_locked[4];
assign qpll_clk[6] = qpll_clk[4];
assign qpll_ref_clk[6] = qpll_ref_clk[4];
assign qpll_locked[6] = qpll_locked[4];
assign qpll_clk[7] = qpll_clk[4];
assign qpll_ref_clk[7] = qpll_ref_clk[4];
assign qpll_locked[7] = qpll_locked[4];
// instantiations
ad_gt_common #(
.GTH_OR_GTX_N (GTH_OR_GTX_N),
.QPLL_ENABLE (QPLL0_ENABLE),
.QPLL_REFCLK_DIV (QPLL0_REFCLK_DIV),
.QPLL_CFG (QPLL0_CFG),
.QPLL_FBDIV_RATIO (QPLL0_FBDIV_RATIO),
.QPLL_FBDIV (QPLL0_FBDIV))
i_qpll_0 (
.qpll_ref_clk_in (qpll0_ref_clk_in),
.qpll_rst (qpll0_rst),
.qpll_clk (qpll_clk[0]),
.qpll_ref_clk (qpll_ref_clk[0]),
.qpll_locked (qpll_locked[0]),
.up_clk (up_clk),
.up_drp_sel (up_drp_qpll0_sel_s),
.up_drp_addr (up_drp_qpll0_addr_s),
.up_drp_wr (up_drp_qpll0_wr_s),
.up_drp_wdata (up_drp_qpll0_wdata_s),
.up_drp_rdata (up_drp_qpll0_rdata_s),
.up_drp_ready (up_drp_qpll0_ready_s));
ad_gt_common #(
.GTH_OR_GTX_N (GTH_OR_GTX_N),
.QPLL_ENABLE (QPLL1_ENABLE),
.QPLL_REFCLK_DIV (QPLL1_REFCLK_DIV),
.QPLL_CFG (QPLL1_CFG),
.QPLL_FBDIV_RATIO (QPLL1_FBDIV_RATIO),
.QPLL_FBDIV (QPLL1_FBDIV))
i_qpll_1 (
.qpll_ref_clk_in (qpll1_ref_clk_in),
.qpll_rst (qpll1_rst),
.qpll_clk (qpll_clk[4]),
.qpll_ref_clk (qpll_ref_clk[4]),
.qpll_locked (qpll_locked[4]),
.up_clk (up_clk),
.up_drp_sel (up_drp_qpll1_sel_s),
.up_drp_addr (up_drp_qpll1_addr_s),
.up_drp_wr (up_drp_qpll1_wr_s),
.up_drp_wdata (up_drp_qpll1_wdata_s),
.up_drp_rdata (up_drp_qpll1_rdata_s),
.up_drp_ready (up_drp_qpll1_ready_s));
up_gt #(
.GTH_OR_GTX_N (GTH_OR_GTX_N))
i_up (
.up_drp_qpll0_sel (up_drp_qpll0_sel_s),
.up_drp_qpll0_wr (up_drp_qpll0_wr_s),
.up_drp_qpll0_addr (up_drp_qpll0_addr_s),
.up_drp_qpll0_wdata (up_drp_qpll0_wdata_s),
.up_drp_qpll0_rdata (up_drp_qpll0_rdata_s),
.up_drp_qpll0_ready (up_drp_qpll0_ready_s),
.up_drp_qpll1_sel (up_drp_qpll1_sel_s),
.up_drp_qpll1_wr (up_drp_qpll1_wr_s),
.up_drp_qpll1_addr (up_drp_qpll1_addr_s),
.up_drp_qpll1_wdata (up_drp_qpll1_wdata_s),
.up_drp_qpll1_rdata (up_drp_qpll1_rdata_s),
.up_drp_qpll1_ready (up_drp_qpll1_ready_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*****************************************************************
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/byte_group_io.v#4 $
// $Author: $
// $DateTime: $
// $Change: $
// Description:
// This verilog file is a paramertizable I/O termination for
// the single byte lane.
// to create a N byte-lane wide phy.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
//////////////////////////////////////////////////////////////////
*****************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_byte_group_io #(
// bit lane existance
parameter BITLANES = 12'b1111_1111_1111,
parameter BITLANES_OUTONLY = 12'b0000_0000_0000,
parameter PO_DATA_CTL = "FALSE",
parameter OSERDES_DATA_RATE = "DDR",
parameter OSERDES_DATA_WIDTH = 4,
parameter IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter IDELAYE2_IDELAY_VALUE = 00,
parameter IODELAY_GRP = "IODELAY_MIG",
// local usage only, don't pass down
parameter BUS_WIDTH = 12,
parameter SYNTHESIS = "FALSE"
)
(
input [9:0] mem_dq_in,
output [BUS_WIDTH-1:0] mem_dq_out,
output [BUS_WIDTH-1:0] mem_dq_ts,
input mem_dqs_in,
output mem_dqs_out,
output mem_dqs_ts,
output [(4*10)-1:0] iserdes_dout, // 2 extra 12-bit lanes not used
output dqs_to_phaser,
input iserdes_clk,
input iserdes_clkb,
input iserdes_clkdiv,
input phy_clk,
input rst,
input oserdes_rst,
input iserdes_rst,
input [1:0] oserdes_dqs,
input [1:0] oserdes_dqsts,
input [(4*BUS_WIDTH)-1:0] oserdes_dq,
input [1:0] oserdes_dqts,
input oserdes_clk,
input oserdes_clk_delayed,
input oserdes_clkdiv,
input idelay_inc,
input idelay_ce,
input idelay_ld,
input idelayctrl_refclk
);
/// INSTANCES
localparam ISERDES_DQ_DATA_RATE = "DDR";
localparam ISERDES_DQ_DATA_WIDTH = 4;
localparam ISERDES_DQ_DYN_CLKDIV_INV_EN = "FALSE";
localparam ISERDES_DQ_DYN_CLK_INV_EN = "FALSE";
localparam ISERDES_DQ_INIT_Q1 = 1'b0;
localparam ISERDES_DQ_INIT_Q2 = 1'b0;
localparam ISERDES_DQ_INIT_Q3 = 1'b0;
localparam ISERDES_DQ_INIT_Q4 = 1'b0;
localparam ISERDES_DQ_INTERFACE_TYPE = "MEMORY_DDR3";
localparam ISERDES_NUM_CE = 2;
localparam ISERDES_DQ_IOBDELAY = "IFD";
localparam ISERDES_DQ_OFB_USED = "FALSE";
localparam ISERDES_DQ_SERDES_MODE = "MASTER";
localparam ISERDES_DQ_SRVAL_Q1 = 1'b0;
localparam ISERDES_DQ_SRVAL_Q2 = 1'b0;
localparam ISERDES_DQ_SRVAL_Q3 = 1'b0;
localparam ISERDES_DQ_SRVAL_Q4 = 1'b0;
wire [BUS_WIDTH-1:0] data_in_dly;
wire [BUS_WIDTH-1:0] oserdes_dq_buf;
wire [BUS_WIDTH-1:0] oserdes_dqts_buf;
wire oserdes_dqs_buf;
wire oserdes_dqsts_buf;
wire [9:0] data_in;
wire tbyte_out;
assign mem_dq_out = oserdes_dq_buf;
assign mem_dq_ts = oserdes_dqts_buf;
assign data_in = mem_dq_in;
assign mem_dqs_out = oserdes_dqs_buf;
assign mem_dqs_ts = oserdes_dqsts_buf;
assign dqs_to_phaser = mem_dqs_in;
reg iserdes_clk_d;
always @(*)
iserdes_clk_d <= #(025) iserdes_clk;
reg idelay_ld_rst;
reg rst_r1;
reg rst_r2;
reg rst_r3;
reg rst_r4;
always @(posedge phy_clk) begin
rst_r1 <= #1 rst;
rst_r2 <= #1 rst_r1;
rst_r3 <= #1 rst_r2;
rst_r4 <= #1 rst_r3;
end
always @(posedge phy_clk) begin
if (rst)
idelay_ld_rst <= #1 1'b1;
else if (rst_r4)
idelay_ld_rst <= #1 1'b0;
end
genvar i;
generate
for ( i = 0; i != 10 && PO_DATA_CTL == "TRUE" ; i=i+1) begin : input_
if ( BITLANES[i] && !BITLANES_OUTONLY[i]) begin : iserdes_dq_
ISERDESE2 #(
.DATA_RATE ( ISERDES_DQ_DATA_RATE),
.DATA_WIDTH ( ISERDES_DQ_DATA_WIDTH),
.DYN_CLKDIV_INV_EN ( ISERDES_DQ_DYN_CLKDIV_INV_EN),
.DYN_CLK_INV_EN ( ISERDES_DQ_DYN_CLK_INV_EN),
.INIT_Q1 ( ISERDES_DQ_INIT_Q1),
.INIT_Q2 ( ISERDES_DQ_INIT_Q2),
.INIT_Q3 ( ISERDES_DQ_INIT_Q3),
.INIT_Q4 ( ISERDES_DQ_INIT_Q4),
.INTERFACE_TYPE ( ISERDES_DQ_INTERFACE_TYPE),
.NUM_CE ( ISERDES_NUM_CE),
.IOBDELAY ( ISERDES_DQ_IOBDELAY),
.OFB_USED ( ISERDES_DQ_OFB_USED),
.SERDES_MODE ( ISERDES_DQ_SERDES_MODE),
.SRVAL_Q1 ( ISERDES_DQ_SRVAL_Q1),
.SRVAL_Q2 ( ISERDES_DQ_SRVAL_Q2),
.SRVAL_Q3 ( ISERDES_DQ_SRVAL_Q3),
.SRVAL_Q4 ( ISERDES_DQ_SRVAL_Q4)
)
iserdesdq
(
.O (),
.Q1 (iserdes_dout[4*i + 3]),
.Q2 (iserdes_dout[4*i + 2]),
.Q3 (iserdes_dout[4*i + 1]),
.Q4 (iserdes_dout[4*i + 0]),
.Q5 (),
.Q6 (),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.BITSLIP (1'b0),
.CE1 (1'b1),
.CE2 (1'b1),
.CLK (iserdes_clk_d),
.CLKB (!iserdes_clk_d),
.CLKDIVP (iserdes_clkdiv),
.CLKDIV (),
.DDLY (data_in_dly[i]),
.D (data_in[i]), // dedicated route to iob for debugging
// or as needed, select with IOBDELAY
.DYNCLKDIVSEL (1'b0),
.DYNCLKSEL (1'b0),
// NOTE: OCLK is not used in this design, but is required to meet
// a design rule check in map and bitgen. Do not disconnect it.
.OCLK (oserdes_clk),
.OFB (),
.RST (1'b0),
// .RST (iserdes_rst),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0)
);
localparam IDELAYE2_CINVCTRL_SEL = "FALSE";
localparam IDELAYE2_DELAY_SRC = "IDATAIN";
localparam IDELAYE2_HIGH_PERFORMANCE_MODE = "TRUE";
localparam IDELAYE2_PIPE_SEL = "FALSE";
localparam IDELAYE2_ODELAY_TYPE = "FIXED";
localparam IDELAYE2_REFCLK_FREQUENCY = 200.0;
localparam IDELAYE2_SIGNAL_PATTERN = "DATA";
(* IODELAY_GROUP = IODELAY_GRP *)
IDELAYE2 #(
.CINVCTRL_SEL ( IDELAYE2_CINVCTRL_SEL),
.DELAY_SRC ( IDELAYE2_DELAY_SRC),
.HIGH_PERFORMANCE_MODE ( IDELAYE2_HIGH_PERFORMANCE_MODE),
.IDELAY_TYPE ( IDELAYE2_IDELAY_TYPE),
.IDELAY_VALUE ( IDELAYE2_IDELAY_VALUE),
.PIPE_SEL ( IDELAYE2_PIPE_SEL),
.REFCLK_FREQUENCY ( IDELAYE2_REFCLK_FREQUENCY ),
.SIGNAL_PATTERN ( IDELAYE2_SIGNAL_PATTERN)
)
idelaye2
(
.CNTVALUEOUT (),
.DATAOUT (data_in_dly[i]),
.C (phy_clk), // automatically wired by ISE
.CE (idelay_ce),
.CINVCTRL (),
.CNTVALUEIN (5'b00000),
.DATAIN (1'b0),
.IDATAIN (data_in[i]),
.INC (idelay_inc),
.LD (idelay_ld | idelay_ld_rst),
.LDPIPEEN (1'b0),
.REGRST (rst)
);
end // iserdes_dq
else begin
assign iserdes_dout[4*i + 3] = 0;
assign iserdes_dout[4*i + 2] = 0;
assign iserdes_dout[4*i + 1] = 0;
assign iserdes_dout[4*i + 0] = 0;
end
end // input_
endgenerate // iserdes_dq_
localparam OSERDES_DQ_DATA_RATE_OQ = OSERDES_DATA_RATE;
localparam OSERDES_DQ_DATA_RATE_TQ = OSERDES_DQ_DATA_RATE_OQ;
localparam OSERDES_DQ_DATA_WIDTH = OSERDES_DATA_WIDTH;
localparam OSERDES_DQ_INIT_OQ = 1'b1;
localparam OSERDES_DQ_INIT_TQ = 1'b1;
localparam OSERDES_DQ_INTERFACE_TYPE = "DEFAULT";
localparam OSERDES_DQ_ODELAY_USED = 0;
localparam OSERDES_DQ_SERDES_MODE = "MASTER";
localparam OSERDES_DQ_SRVAL_OQ = 1'b1;
localparam OSERDES_DQ_SRVAL_TQ = 1'b1;
// note: obuf used in control path case, no ts input so width irrelevant
localparam OSERDES_DQ_TRISTATE_WIDTH = (OSERDES_DQ_DATA_RATE_OQ == "DDR") ? 4 : 1;
localparam OSERDES_DQS_DATA_RATE_OQ = "DDR";
localparam OSERDES_DQS_DATA_RATE_TQ = "DDR";
localparam OSERDES_DQS_TRISTATE_WIDTH = 4; // this is always ddr
localparam OSERDES_DQS_DATA_WIDTH = 4;
localparam ODDR_CLK_EDGE = "SAME_EDGE";
localparam OSERDES_TBYTE_CTL = "TRUE";
generate
localparam NUM_BITLANES = PO_DATA_CTL == "TRUE" ? 10 : BUS_WIDTH;
if ( PO_DATA_CTL == "TRUE" ) begin : slave_ts
OSERDESE2 #(
.DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ),
.DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ),
.DATA_WIDTH (OSERDES_DQ_DATA_WIDTH),
.INIT_OQ (OSERDES_DQ_INIT_OQ),
.INIT_TQ (OSERDES_DQ_INIT_TQ),
.SERDES_MODE (OSERDES_DQ_SERDES_MODE),
.SRVAL_OQ (OSERDES_DQ_SRVAL_OQ),
.SRVAL_TQ (OSERDES_DQ_SRVAL_TQ),
.TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH),
.TBYTE_CTL ("TRUE"),
.TBYTE_SRC ("TRUE")
)
oserdes_slave_ts
(
.OFB (),
.OQ (),
.SHIFTOUT1 (), // not extended
.SHIFTOUT2 (), // not extended
.TFB (),
.TQ (),
.CLK (oserdes_clk),
.CLKDIV (oserdes_clkdiv),
.D1 (),
.D2 (),
.D3 (),
.D4 (),
.D5 (),
.D6 (),
.OCE (1'b1),
.RST (oserdes_rst),
.SHIFTIN1 (), // not extended
.SHIFTIN2 (), // not extended
.T1 (oserdes_dqts[0]),
.T2 (oserdes_dqts[0]),
.T3 (oserdes_dqts[1]),
.T4 (oserdes_dqts[1]),
.TCE (1'b1),
.TBYTEOUT (tbyte_out),
.TBYTEIN (tbyte_out)
);
end // slave_ts
for (i = 0; i != NUM_BITLANES; i=i+1) begin : output_
if ( BITLANES[i]) begin : oserdes_dq_
if ( PO_DATA_CTL == "TRUE" ) begin : ddr
OSERDESE2 #(
.DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ),
.DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ),
.DATA_WIDTH (OSERDES_DQ_DATA_WIDTH),
.INIT_OQ (OSERDES_DQ_INIT_OQ),
.INIT_TQ (OSERDES_DQ_INIT_TQ),
.SERDES_MODE (OSERDES_DQ_SERDES_MODE),
.SRVAL_OQ (OSERDES_DQ_SRVAL_OQ),
.SRVAL_TQ (OSERDES_DQ_SRVAL_TQ),
.TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH),
.TBYTE_CTL (OSERDES_TBYTE_CTL),
.TBYTE_SRC ("FALSE")
)
oserdes_dq_i
(
.OFB (),
.OQ (oserdes_dq_buf[i]),
.SHIFTOUT1 (), // not extended
.SHIFTOUT2 (), // not extended
.TFB (),
.TQ (oserdes_dqts_buf[i]),
.CLK (oserdes_clk),
.CLKDIV (oserdes_clkdiv),
.D1 (oserdes_dq[4 * i + 0]),
.D2 (oserdes_dq[4 * i + 1]),
.D3 (oserdes_dq[4 * i + 2]),
.D4 (oserdes_dq[4 * i + 3]),
.D5 (),
.D6 (),
.OCE (1'b1),
.RST (oserdes_rst),
.SHIFTIN1 (), // not extended
.SHIFTIN2 (), // not extended
.T1 (/*oserdes_dqts[0]*/),
.T2 (/*oserdes_dqts[0]*/),
.T3 (/*oserdes_dqts[1]*/),
.T4 (/*oserdes_dqts[1]*/),
.TCE (1'b1),
.TBYTEIN (tbyte_out)
);
end
else begin : sdr
OSERDESE2 #(
.DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ),
.DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ),
.DATA_WIDTH (OSERDES_DQ_DATA_WIDTH),
.INIT_OQ (1'b0 /*OSERDES_DQ_INIT_OQ*/),
.INIT_TQ (OSERDES_DQ_INIT_TQ),
.SERDES_MODE (OSERDES_DQ_SERDES_MODE),
.SRVAL_OQ (1'b0 /*OSERDES_DQ_SRVAL_OQ*/),
.SRVAL_TQ (OSERDES_DQ_SRVAL_TQ),
.TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH)
)
oserdes_dq_i
(
.OFB (),
.OQ (oserdes_dq_buf[i]),
.SHIFTOUT1 (), // not extended
.SHIFTOUT2 (), // not extended
.TFB (),
.TQ (),
.CLK (oserdes_clk),
.CLKDIV (oserdes_clkdiv),
.D1 (oserdes_dq[4 * i + 0]),
.D2 (oserdes_dq[4 * i + 1]),
.D3 (oserdes_dq[4 * i + 2]),
.D4 (oserdes_dq[4 * i + 3]),
.D5 (),
.D6 (),
.OCE (1'b1),
.RST (oserdes_rst),
.SHIFTIN1 (), // not extended
.SHIFTIN2 (), // not extended
.T1 (),
.T2 (),
.T3 (),
.T4 (),
.TCE (1'b1)
);
end // ddr
end // oserdes_dq_
end // output_
endgenerate
generate
if ( PO_DATA_CTL == "TRUE" ) begin : dqs_gen
ODDR
#(.DDR_CLK_EDGE (ODDR_CLK_EDGE))
oddr_dqs
(
.Q (oserdes_dqs_buf),
.D1 (oserdes_dqs[0]),
.D2 (oserdes_dqs[1]),
.C (oserdes_clk_delayed),
.R (1'b0),
.S (),
.CE (1'b1)
);
ODDR
#(.DDR_CLK_EDGE (ODDR_CLK_EDGE))
oddr_dqsts
( .Q (oserdes_dqsts_buf),
.D1 (oserdes_dqsts[0]),
.D2 (oserdes_dqsts[0]),
.C (oserdes_clk_delayed),
.R (),
.S (1'b0),
.CE (1'b1)
);
end // sdr rate
else begin:null_dqs
end
endgenerate
endmodule // byte_group_io
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_register_slice:2.1
// IP Revision: 9
(* X_CORE_INFO = "axi_register_slice_v2_1_9_axi_register_slice,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "block_design_m00_regslice_0,axi_register_slice_v2_1_9_axi_register_slice,{}" *)
(* CORE_GENERATION_INFO = "block_design_m00_regslice_0,axi_register_slice_v2_1_9_axi_register_slice,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=2,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=6,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_REG_CONFIG_W=7,C_REG_\
CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=7}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module block_design_m00_regslice_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [5 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [5 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [5 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [5 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_register_slice_v2_1_9_axi_register_slice #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(2),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(6),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_REG_CONFIG_AW(7),
.C_REG_CONFIG_W(7),
.C_REG_CONFIG_B(7),
.C_REG_CONFIG_AR(7),
.C_REG_CONFIG_R(7)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H1),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H1),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_avm_to_ic #(
parameter integer DATA_W = 256,
parameter integer WRITEDATA_W = 256,
parameter integer BURSTCOUNT_W = 6,
parameter integer ADDRESS_W = 32,
parameter integer BYTEENA_W = DATA_W / 8,
parameter integer ID_W = 1,
parameter ADDR_SHIFT=1 // shift the address?
)
(
// AVM interface
input logic avm_read,
input logic avm_write,
input logic [WRITEDATA_W-1:0] avm_writedata,
input logic [BURSTCOUNT_W-1:0] avm_burstcount,
input logic [ADDRESS_W-1:0] avm_address,
input logic [BYTEENA_W-1:0] avm_byteenable,
output logic avm_waitrequest,
output logic avm_readdatavalid,
output logic [WRITEDATA_W-1:0] avm_readdata,
output logic avm_writeack, // not a true Avalon signal
// IC interface
output logic ic_arb_request,
output logic ic_arb_read,
output logic ic_arb_write,
output logic [WRITEDATA_W-1:0] ic_arb_writedata,
output logic [BURSTCOUNT_W-1:0] ic_arb_burstcount,
output logic [ADDRESS_W-$clog2(DATA_W / 8)-1:0] ic_arb_address,
output logic [BYTEENA_W-1:0] ic_arb_byteenable,
output logic [ID_W-1:0] ic_arb_id,
input logic ic_arb_stall,
input logic ic_wrp_ack,
input logic ic_rrp_datavalid,
input logic [WRITEDATA_W-1:0] ic_rrp_data
);
// The logic for ic_arb_request (below) makes a MAJOR ASSUMPTION:
// avm_write will never be deasserted in the MIDDLE of a write burst
// (read bursts are fine since they are single cycle requests)
//
// For proper burst functionality, ic_arb_request must remain asserted
// for the ENTIRE duration of a burst request, otherwise the burst may be
// interrupted and lead to all sorts of chaos. At this time, LSUs do not
// deassert avm_write in the middle of a write burst, so this assumption
// is valid.
//
// If there comes a time when this assumption is no longer valid,
// logic needs to be added to detect when a burst begins/ends.
assign ic_arb_request = avm_read | avm_write;
assign ic_arb_read = avm_read;
assign ic_arb_write = avm_write;
assign ic_arb_writedata = avm_writedata;
assign ic_arb_burstcount = avm_burstcount;
generate
if(ADDR_SHIFT==1)
begin
assign ic_arb_address = avm_address[ADDRESS_W-1:$clog2(DATA_W / 8)];
end
else
begin
assign ic_arb_address = avm_address[ADDRESS_W-$clog2(DATA_W / 8)-1:0];
end
endgenerate
assign ic_arb_byteenable = avm_byteenable;
assign avm_waitrequest = ic_arb_stall;
assign avm_readdatavalid = ic_rrp_datavalid;
assign avm_readdata = ic_rrp_data;
assign avm_writeack = ic_wrp_ack;
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: crossbar.v
//
// Description:
// This module is a M-master to N-slave AXI axi_crossbar_v2_1_10_crossbar switch.
// The interface of this module consists of a vectored slave and master interface
// in which all slots are sized and synchronized to the native width and clock
// of the interconnect.
// The SAMD axi_crossbar_v2_1_10_crossbar supports only AXI4 and AXI3 protocols.
// All width, clock and protocol conversions are done outside this block, as are
// any pipeline registers or data FIFOs.
// This module contains all arbitration, decoders and channel multiplexing logic.
// It also contains the diagnostic registers and control interface.
//
//-----------------------------------------------------------------------------
//
// Structure:
// crossbar
// si_transactor
// addr_decoder
// comparator_static
// mux_enc
// axic_srl_fifo
// arbiter_resp
// splitter
// wdata_router
// axic_reg_srl_fifo
// wdata_mux
// axic_reg_srl_fifo
// mux_enc
// addr_decoder
// comparator_static
// axic_srl_fifo
// axi_register_slice
// addr_arbiter
// mux_enc
// decerr_slave
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_10_crossbar #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_SLAVE_SLOTS = 1,
parameter integer C_NUM_MASTER_SLOTS = 1,
parameter integer C_NUM_ADDR_RANGES = 1,
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_PROTOCOL = 0,
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b1}},
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}},
parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_BASE_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},
parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_HIGH_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}},
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_WRITE = {C_NUM_SLAVE_SLOTS{1'b1}},
parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_READ = {C_NUM_SLAVE_SLOTS{1'b1}},
parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_WRITE = {C_NUM_MASTER_SLOTS{1'b1}},
parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_READ = {C_NUM_MASTER_SLOTS{1'b1}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = {C_NUM_MASTER_SLOTS*32{1'b1}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = {C_NUM_MASTER_SLOTS*32{1'b1}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD = {C_NUM_SLAVE_SLOTS{32'h00000000}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE = {C_NUM_SLAVE_SLOTS{32'h00000001}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE = {C_NUM_SLAVE_SLOTS{32'h00000001}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING = {C_NUM_MASTER_SLOTS{32'h00000001}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING = {C_NUM_MASTER_SLOTS{32'h00000001}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY = {C_NUM_SLAVE_SLOTS{32'h00000000}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE = {C_NUM_MASTER_SLOTS{32'h00000000}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}},
parameter integer C_RANGE_CHECK = 0,
parameter integer C_ADDR_DECODE = 0,
parameter [(C_NUM_MASTER_SLOTS+1)*32-1:0] C_W_ISSUE_WIDTH = {C_NUM_MASTER_SLOTS+1{32'h00000000}},
parameter [(C_NUM_MASTER_SLOTS+1)*32-1:0] C_R_ISSUE_WIDTH = {C_NUM_MASTER_SLOTS+1{32'h00000000}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_W_ACCEPT_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_R_ACCEPT_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}},
parameter integer C_DEBUG = 1
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_AWLEN,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWSIZE,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWBURST,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWLOCK,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWCACHE,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWPROT,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWREGION,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWQOS,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WLAST,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_BRESP,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BVALID,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_ARLEN,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARSIZE,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARBURST,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARLOCK,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARCACHE,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARPROT,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARREGION,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARQOS,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_RRESP,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RLAST,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RVALID,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_AWLEN,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWSIZE,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWBURST,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWLOCK,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWCACHE,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWPROT,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWREGION,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWQOS,
output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWVALID,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WLAST,
output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WVALID,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_BRESP,
input wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BVALID,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_ARLEN,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARSIZE,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARBURST,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARLOCK,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARCACHE,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARPROT,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARREGION,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARQOS,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARVALID,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_RRESP,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RLAST,
input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RVALID,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RREADY
);
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
localparam integer P_WRITE = 0;
localparam integer P_READ = 1;
localparam integer P_NUM_MASTER_SLOTS_LOG = f_ceil_log2(C_NUM_MASTER_SLOTS);
localparam integer P_NUM_SLAVE_SLOTS_LOG = f_ceil_log2((C_NUM_SLAVE_SLOTS>1) ? C_NUM_SLAVE_SLOTS : 2);
localparam integer P_AXI_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 1;
localparam integer P_ST_AWMESG_WIDTH = 2+4+4 + C_AXI_AWUSER_WIDTH;
localparam integer P_AA_AWMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+4 + P_ST_AWMESG_WIDTH;
localparam integer P_ST_ARMESG_WIDTH = 2+4+4 + C_AXI_ARUSER_WIDTH;
localparam integer P_AA_ARMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+4 + P_ST_ARMESG_WIDTH;
localparam integer P_ST_BMESG_WIDTH = 2 + C_AXI_BUSER_WIDTH;
localparam integer P_ST_RMESG_WIDTH = 2 + C_AXI_RUSER_WIDTH + C_AXI_DATA_WIDTH;
localparam integer P_WR_WMESG_WIDTH = C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_WUSER_WIDTH + P_AXI_WID_WIDTH;
localparam [31:0] P_BYPASS = 32'h00000000;
localparam [31:0] P_FWD_REV = 32'h00000001;
localparam [31:0] P_SIMPLE = 32'h00000007;
localparam [(C_NUM_MASTER_SLOTS+1)-1:0] P_M_AXI_SUPPORTS_READ = {1'b1, C_M_AXI_SUPPORTS_READ[0+:C_NUM_MASTER_SLOTS]};
localparam [(C_NUM_MASTER_SLOTS+1)-1:0] P_M_AXI_SUPPORTS_WRITE = {1'b1, C_M_AXI_SUPPORTS_WRITE[0+:C_NUM_MASTER_SLOTS]};
localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_WRITE_CONNECTIVITY = {{32{1'b1}}, C_M_AXI_WRITE_CONNECTIVITY[0+:C_NUM_MASTER_SLOTS*32]};
localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_READ_CONNECTIVITY = {{32{1'b1}}, C_M_AXI_READ_CONNECTIVITY[0+:C_NUM_MASTER_SLOTS*32]};
localparam [C_NUM_SLAVE_SLOTS*32-1:0] P_S_AXI_WRITE_CONNECTIVITY = f_si_write_connectivity(0);
localparam [C_NUM_SLAVE_SLOTS*32-1:0] P_S_AXI_READ_CONNECTIVITY = f_si_read_connectivity(0);
localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_READ_ISSUING = {32'h00000001, C_M_AXI_READ_ISSUING[0+:C_NUM_MASTER_SLOTS*32]};
localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_WRITE_ISSUING = {32'h00000001, C_M_AXI_WRITE_ISSUING[0+:C_NUM_MASTER_SLOTS*32]};
localparam P_DECERR = 2'b11;
//---------------------------------------------------------------------------
// Functions
//---------------------------------------------------------------------------
// Ceiling of log2(x)
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// Isolate thread bits of input S_ID and add to BASE_ID (RNG00) to form MI-side ID value
// only for end-point SI-slots
function [C_AXI_ID_WIDTH-1:0] f_extend_ID
(
input [C_AXI_ID_WIDTH-1:0] s_id,
input integer slot
);
begin
f_extend_ID = C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] | (s_id & (C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] ^ C_S_AXI_HIGH_ID[slot*64+:C_AXI_ID_WIDTH]));
end
endfunction
// Write connectivity array transposed
function [C_NUM_SLAVE_SLOTS*32-1:0] f_si_write_connectivity
(
input integer null_arg
);
integer si_slot;
integer mi_slot;
reg [C_NUM_SLAVE_SLOTS*32-1:0] result;
begin
result = {C_NUM_SLAVE_SLOTS*32{1'b1}};
for (si_slot=0; si_slot<C_NUM_SLAVE_SLOTS; si_slot=si_slot+1) begin
for (mi_slot=0; mi_slot<C_NUM_MASTER_SLOTS; mi_slot=mi_slot+1) begin
result[si_slot*32+mi_slot] = C_M_AXI_WRITE_CONNECTIVITY[mi_slot*32+si_slot];
end
end
f_si_write_connectivity = result;
end
endfunction
// Read connectivity array transposed
function [C_NUM_SLAVE_SLOTS*32-1:0] f_si_read_connectivity
(
input integer null_arg
);
integer si_slot;
integer mi_slot;
reg [C_NUM_SLAVE_SLOTS*32-1:0] result;
begin
result = {C_NUM_SLAVE_SLOTS*32{1'b1}};
for (si_slot=0; si_slot<C_NUM_SLAVE_SLOTS; si_slot=si_slot+1) begin
for (mi_slot=0; mi_slot<C_NUM_MASTER_SLOTS; mi_slot=mi_slot+1) begin
result[si_slot*32+mi_slot] = C_M_AXI_READ_CONNECTIVITY[mi_slot*32+si_slot];
end
end
f_si_read_connectivity = result;
end
endfunction
genvar gen_si_slot;
genvar gen_mi_slot;
wire [C_NUM_SLAVE_SLOTS*P_ST_AWMESG_WIDTH-1:0] si_st_awmesg ;
wire [C_NUM_SLAVE_SLOTS*P_ST_AWMESG_WIDTH-1:0] st_tmp_awmesg ;
wire [C_NUM_SLAVE_SLOTS*P_AA_AWMESG_WIDTH-1:0] tmp_aa_awmesg ;
wire [P_AA_AWMESG_WIDTH-1:0] aa_mi_awmesg ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] st_aa_awid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] st_aa_awaddr ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_awlen ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_awsize ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] st_aa_awlock ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_awprot ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] st_aa_awregion ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_awerror ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_aa_awtarget_hot ;
wire [C_NUM_SLAVE_SLOTS*(P_NUM_MASTER_SLOTS_LOG+1)-1:0] st_aa_awtarget_enc ;
wire [P_NUM_SLAVE_SLOTS_LOG*1-1:0] aa_wm_awgrant_enc ;
wire [(C_NUM_MASTER_SLOTS+1)-1:0] aa_mi_awtarget_hot ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_awvalid_qual ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] st_ss_awvalid ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] st_ss_awready ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_wr_awvalid ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_wr_awready ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_aa_awvalid ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_aa_awready ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] sa_wm_awvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] sa_wm_awready ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_awvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_awready ;
wire aa_sa_awvalid ;
wire aa_sa_awready ;
wire aa_mi_arready ;
wire mi_awvalid_en ;
wire sa_wm_awvalid_en ;
wire sa_wm_awready_mux ;
wire [C_NUM_SLAVE_SLOTS*P_ST_ARMESG_WIDTH-1:0] si_st_armesg ;
wire [C_NUM_SLAVE_SLOTS*P_ST_ARMESG_WIDTH-1:0] st_tmp_armesg ;
wire [C_NUM_SLAVE_SLOTS*P_AA_ARMESG_WIDTH-1:0] tmp_aa_armesg ;
wire [P_AA_ARMESG_WIDTH-1:0] aa_mi_armesg ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] st_aa_arid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] st_aa_araddr ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_arlen ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_arsize ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] st_aa_arlock ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_arprot ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] st_aa_arregion ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_arerror ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_aa_artarget_hot ;
wire [C_NUM_SLAVE_SLOTS*(P_NUM_MASTER_SLOTS_LOG+1)-1:0] st_aa_artarget_enc ;
wire [(C_NUM_MASTER_SLOTS+1)-1:0] aa_mi_artarget_hot ;
wire [P_NUM_SLAVE_SLOTS_LOG*1-1:0] aa_mi_argrant_enc ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_arvalid_qual ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_arvalid ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_arready ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_arvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_arready ;
wire aa_mi_arvalid ;
wire mi_awready_mux ;
wire [C_NUM_SLAVE_SLOTS*P_ST_BMESG_WIDTH-1:0] st_si_bmesg ;
wire [(C_NUM_MASTER_SLOTS+1)*P_ST_BMESG_WIDTH-1:0] st_mr_bmesg ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] st_mr_bid ;
wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] st_mr_bresp ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_BUSER_WIDTH-1:0] st_mr_buser ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_bvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_bready ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_bready ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_bid_target ;
wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_mr_bid_target ;
wire [(C_NUM_MASTER_SLOTS+1)*P_NUM_SLAVE_SLOTS_LOG-1:0] debug_bid_target_i ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] bid_match ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] mi_bid ;
wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] mi_bresp ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_BUSER_WIDTH-1:0] mi_buser ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_bvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_bready ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] bready_carry ;
wire [C_NUM_SLAVE_SLOTS*P_ST_RMESG_WIDTH-1:0] st_si_rmesg ;
wire [(C_NUM_MASTER_SLOTS+1)*P_ST_RMESG_WIDTH-1:0] st_mr_rmesg ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] st_mr_rid ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] st_mr_rdata ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_RUSER_WIDTH-1:0] st_mr_ruser ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_rlast ;
wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] st_mr_rresp ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_rvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_rready ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_rready ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_rid_target ;
wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_mr_rid_target ;
wire [(C_NUM_MASTER_SLOTS+1)*P_NUM_SLAVE_SLOTS_LOG-1:0] debug_rid_target_i ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] rid_match ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] mi_rid ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] mi_rdata ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_RUSER_WIDTH-1:0] mi_ruser ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_rlast ;
wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] mi_rresp ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_rvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_rready ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] rready_carry ;
wire [C_NUM_SLAVE_SLOTS*P_WR_WMESG_WIDTH-1:0] si_wr_wmesg ;
wire [C_NUM_SLAVE_SLOTS*P_WR_WMESG_WIDTH-1:0] wr_wm_wmesg ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] wr_wm_wlast ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] wr_tmp_wvalid ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] wr_tmp_wready ;
wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_wm_wvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_wm_wready ;
wire [(C_NUM_MASTER_SLOTS+1)*P_WR_WMESG_WIDTH-1:0] wm_mr_wmesg ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] wm_mr_wdata ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH/8-1:0] wm_mr_wstrb ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] wm_mr_wid ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_WUSER_WIDTH-1:0] wm_mr_wuser ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] wm_mr_wlast ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] wm_mr_wvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] wm_mr_wready ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] mi_wdata ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH/8-1:0] mi_wstrb ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_WUSER_WIDTH-1:0] mi_wuser ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] mi_wid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_wlast ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_wvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_wready ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] w_cmd_push ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] w_cmd_pop ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] r_cmd_push ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] r_cmd_pop ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_awmaxissuing ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_armaxissuing ;
reg [(C_NUM_MASTER_SLOTS+1)*8-1:0] w_issuing_cnt ;
reg [(C_NUM_MASTER_SLOTS+1)*8-1:0] r_issuing_cnt ;
reg [8-1:0] debug_aw_trans_seq_i ;
reg [8-1:0] debug_ar_trans_seq_i ;
wire [(C_NUM_MASTER_SLOTS+1)*8-1:0] debug_w_trans_seq_i ;
reg [(C_NUM_MASTER_SLOTS+1)*8-1:0] debug_w_beat_cnt_i ;
reg aresetn_d = 1'b0; // Reset delay register
always @(posedge ACLK) begin
if (~ARESETN) begin
aresetn_d <= 1'b0;
end else begin
aresetn_d <= ARESETN;
end
end
wire reset;
assign reset = ~aresetn_d;
generate
for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_slave_slots
if (C_S_AXI_SUPPORTS_READ[gen_si_slot]) begin : gen_si_read
axi_crossbar_v2_1_10_si_transactor # // "ST": SI Transactor (read channel)
(
.C_FAMILY (C_FAMILY),
.C_SI (gen_si_slot),
.C_DIR (P_READ),
.C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES),
.C_NUM_M (C_NUM_MASTER_SLOTS),
.C_NUM_M_LOG (P_NUM_MASTER_SLOTS_LOG),
.C_ACCEPTANCE (C_S_AXI_READ_ACCEPTANCE[gen_si_slot*32+:32]),
.C_ACCEPTANCE_LOG (C_R_ACCEPT_WIDTH[gen_si_slot*32+:32]),
.C_ID_WIDTH (C_AXI_ID_WIDTH),
.C_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH[gen_si_slot*32+:32]),
.C_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AMESG_WIDTH (P_ST_ARMESG_WIDTH),
.C_RMESG_WIDTH (P_ST_RMESG_WIDTH),
.C_BASE_ID (C_S_AXI_BASE_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),
.C_HIGH_ID (C_S_AXI_HIGH_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),
.C_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD[gen_si_slot*32+:32]),
.C_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_HIGH_ADDR (C_M_AXI_HIGH_ADDR),
.C_TARGET_QUAL (P_S_AXI_READ_CONNECTIVITY[gen_si_slot*32+:C_NUM_MASTER_SLOTS]),
.C_M_AXI_SECURE (C_M_AXI_SECURE),
.C_RANGE_CHECK (C_RANGE_CHECK),
.C_ADDR_DECODE (C_ADDR_DECODE),
.C_ERR_MODE (C_M_AXI_ERR_MODE),
.C_DEBUG (C_DEBUG)
)
si_transactor_ar
(
.ACLK (ACLK),
.ARESET (reset),
.S_AID (f_extend_ID(S_AXI_ARID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)),
.S_AADDR (S_AXI_ARADDR[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),
.S_ALEN (S_AXI_ARLEN[gen_si_slot*8+:8]),
.S_ASIZE (S_AXI_ARSIZE[gen_si_slot*3+:3]),
.S_ABURST (S_AXI_ARBURST[gen_si_slot*2+:2]),
.S_ALOCK (S_AXI_ARLOCK[gen_si_slot*2+:2]),
.S_APROT (S_AXI_ARPROT[gen_si_slot*3+:3]),
// .S_AREGION (S_AXI_ARREGION[gen_si_slot*4+:4]),
.S_AMESG (si_st_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH]),
.S_AVALID (S_AXI_ARVALID[gen_si_slot]),
.S_AREADY (S_AXI_ARREADY[gen_si_slot]),
.M_AID (st_aa_arid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.M_AADDR (st_aa_araddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),
.M_ALEN (st_aa_arlen[gen_si_slot*8+:8]),
.M_ASIZE (st_aa_arsize[gen_si_slot*3+:3]),
.M_ALOCK (st_aa_arlock[gen_si_slot*2+:2]),
.M_APROT (st_aa_arprot[gen_si_slot*3+:3]),
.M_AREGION (st_aa_arregion[gen_si_slot*4+:4]),
.M_AMESG (st_tmp_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH]),
.M_ATARGET_HOT (st_aa_artarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
.M_ATARGET_ENC (st_aa_artarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]),
.M_AERROR (st_aa_arerror[gen_si_slot*8+:8]),
.M_AVALID_QUAL (st_aa_arvalid_qual[gen_si_slot]),
.M_AVALID (st_aa_arvalid[gen_si_slot]),
.M_AREADY (st_aa_arready[gen_si_slot]),
.S_RID (S_AXI_RID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.S_RMESG (st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH]),
.S_RLAST (S_AXI_RLAST[gen_si_slot]),
.S_RVALID (S_AXI_RVALID[gen_si_slot]),
.S_RREADY (S_AXI_RREADY[gen_si_slot]),
.M_RID (st_mr_rid),
.M_RLAST (st_mr_rlast),
.M_RMESG (st_mr_rmesg),
.M_RVALID (st_mr_rvalid),
.M_RREADY (st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
.M_RTARGET (st_tmp_rid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
.DEBUG_A_TRANS_SEQ (C_DEBUG ? debug_ar_trans_seq_i : 8'h0)
);
assign si_st_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH] = {
S_AXI_ARUSER[gen_si_slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH],
S_AXI_ARQOS[gen_si_slot*4+:4],
S_AXI_ARCACHE[gen_si_slot*4+:4],
S_AXI_ARBURST[gen_si_slot*2+:2]
};
assign tmp_aa_armesg[gen_si_slot*P_AA_ARMESG_WIDTH+:P_AA_ARMESG_WIDTH] = {
st_tmp_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH],
st_aa_arregion[gen_si_slot*4+:4],
st_aa_arprot[gen_si_slot*3+:3],
st_aa_arlock[gen_si_slot*2+:2],
st_aa_arsize[gen_si_slot*3+:3],
st_aa_arlen[gen_si_slot*8+:8],
st_aa_araddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH],
st_aa_arid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]
};
assign S_AXI_RRESP[gen_si_slot*2+:2] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+:2];
assign S_AXI_RUSER[gen_si_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+2 +: C_AXI_RUSER_WIDTH];
assign S_AXI_RDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+2+C_AXI_RUSER_WIDTH +: C_AXI_DATA_WIDTH];
end else begin : gen_no_si_read
assign S_AXI_ARREADY[gen_si_slot] = 1'b0;
assign st_aa_arvalid[gen_si_slot] = 1'b0;
assign st_aa_arvalid_qual[gen_si_slot] = 1'b1;
assign tmp_aa_armesg[gen_si_slot*P_AA_ARMESG_WIDTH+:P_AA_ARMESG_WIDTH] = 0;
assign S_AXI_RID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;
assign S_AXI_RRESP[gen_si_slot*2+:2] = 0;
assign S_AXI_RUSER[gen_si_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = 0;
assign S_AXI_RDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0;
assign S_AXI_RVALID[gen_si_slot] = 1'b0;
assign S_AXI_RLAST[gen_si_slot] = 1'b0;
assign st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;
assign st_aa_artarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;
end // gen_si_read
if (C_S_AXI_SUPPORTS_WRITE[gen_si_slot]) begin : gen_si_write
axi_crossbar_v2_1_10_si_transactor # // "ST": SI Transactor (write channel)
(
.C_FAMILY (C_FAMILY),
.C_SI (gen_si_slot),
.C_DIR (P_WRITE),
.C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES),
.C_NUM_M (C_NUM_MASTER_SLOTS),
.C_NUM_M_LOG (P_NUM_MASTER_SLOTS_LOG),
.C_ACCEPTANCE (C_S_AXI_WRITE_ACCEPTANCE[gen_si_slot*32+:32]),
.C_ACCEPTANCE_LOG (C_W_ACCEPT_WIDTH[gen_si_slot*32+:32]),
.C_ID_WIDTH (C_AXI_ID_WIDTH),
.C_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH[gen_si_slot*32+:32]),
.C_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AMESG_WIDTH (P_ST_AWMESG_WIDTH),
.C_RMESG_WIDTH (P_ST_BMESG_WIDTH),
.C_BASE_ID (C_S_AXI_BASE_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),
.C_HIGH_ID (C_S_AXI_HIGH_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),
.C_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD[gen_si_slot*32+:32]),
.C_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_HIGH_ADDR (C_M_AXI_HIGH_ADDR),
.C_TARGET_QUAL (P_S_AXI_WRITE_CONNECTIVITY[gen_si_slot*32+:C_NUM_MASTER_SLOTS]),
.C_M_AXI_SECURE (C_M_AXI_SECURE),
.C_RANGE_CHECK (C_RANGE_CHECK),
.C_ADDR_DECODE (C_ADDR_DECODE),
.C_ERR_MODE (C_M_AXI_ERR_MODE),
.C_DEBUG (C_DEBUG)
)
si_transactor_aw
(
.ACLK (ACLK),
.ARESET (reset),
.S_AID (f_extend_ID(S_AXI_AWID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)),
.S_AADDR (S_AXI_AWADDR[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),
.S_ALEN (S_AXI_AWLEN[gen_si_slot*8+:8]),
.S_ASIZE (S_AXI_AWSIZE[gen_si_slot*3+:3]),
.S_ABURST (S_AXI_AWBURST[gen_si_slot*2+:2]),
.S_ALOCK (S_AXI_AWLOCK[gen_si_slot*2+:2]),
.S_APROT (S_AXI_AWPROT[gen_si_slot*3+:3]),
// .S_AREGION (S_AXI_AWREGION[gen_si_slot*4+:4]),
.S_AMESG (si_st_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH]),
.S_AVALID (S_AXI_AWVALID[gen_si_slot]),
.S_AREADY (S_AXI_AWREADY[gen_si_slot]),
.M_AID (st_aa_awid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.M_AADDR (st_aa_awaddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),
.M_ALEN (st_aa_awlen[gen_si_slot*8+:8]),
.M_ASIZE (st_aa_awsize[gen_si_slot*3+:3]),
.M_ALOCK (st_aa_awlock[gen_si_slot*2+:2]),
.M_APROT (st_aa_awprot[gen_si_slot*3+:3]),
.M_AREGION (st_aa_awregion[gen_si_slot*4+:4]),
.M_AMESG (st_tmp_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH]),
.M_ATARGET_HOT (st_aa_awtarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
.M_ATARGET_ENC (st_aa_awtarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]),
.M_AERROR (st_aa_awerror[gen_si_slot*8+:8]),
.M_AVALID_QUAL (st_aa_awvalid_qual[gen_si_slot]),
.M_AVALID (st_ss_awvalid[gen_si_slot]),
.M_AREADY (st_ss_awready[gen_si_slot]),
.S_RID (S_AXI_BID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.S_RMESG (st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH]),
.S_RLAST (),
.S_RVALID (S_AXI_BVALID[gen_si_slot]),
.S_RREADY (S_AXI_BREADY[gen_si_slot]),
.M_RID (st_mr_bid),
.M_RLAST ({(C_NUM_MASTER_SLOTS+1){1'b1}}),
.M_RMESG (st_mr_bmesg),
.M_RVALID (st_mr_bvalid),
.M_RREADY (st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
.M_RTARGET (st_tmp_bid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
.DEBUG_A_TRANS_SEQ (C_DEBUG ? debug_aw_trans_seq_i : 8'h0)
);
// Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order.
assign si_st_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH] = {
S_AXI_AWUSER[gen_si_slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH],
S_AXI_AWQOS[gen_si_slot*4+:4],
S_AXI_AWCACHE[gen_si_slot*4+:4],
S_AXI_AWBURST[gen_si_slot*2+:2]
};
assign tmp_aa_awmesg[gen_si_slot*P_AA_AWMESG_WIDTH+:P_AA_AWMESG_WIDTH] = {
st_tmp_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH],
st_aa_awregion[gen_si_slot*4+:4],
st_aa_awprot[gen_si_slot*3+:3],
st_aa_awlock[gen_si_slot*2+:2],
st_aa_awsize[gen_si_slot*3+:3],
st_aa_awlen[gen_si_slot*8+:8],
st_aa_awaddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH],
st_aa_awid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]
};
assign S_AXI_BRESP[gen_si_slot*2+:2] = st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+:2];
assign S_AXI_BUSER[gen_si_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+2 +: C_AXI_BUSER_WIDTH];
// AW SI-transactor transfer completes upon completion of both W-router address acceptance (command push) and AW arbitration
axi_crossbar_v2_1_10_splitter # // "SS": Splitter from SI-Transactor (write channel)
(
.C_NUM_M (2)
)
splitter_aw_si
(
.ACLK (ACLK),
.ARESET (reset),
.S_VALID (st_ss_awvalid[gen_si_slot]),
.S_READY (st_ss_awready[gen_si_slot]),
.M_VALID ({ss_wr_awvalid[gen_si_slot], ss_aa_awvalid[gen_si_slot]}),
.M_READY ({ss_wr_awready[gen_si_slot], ss_aa_awready[gen_si_slot]})
);
axi_crossbar_v2_1_10_wdata_router # // "WR": Write data Router
(
.C_FAMILY (C_FAMILY),
.C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS+1),
.C_SELECT_WIDTH (P_NUM_MASTER_SLOTS_LOG+1),
.C_WMESG_WIDTH (P_WR_WMESG_WIDTH),
.C_FIFO_DEPTH_LOG (C_W_ACCEPT_WIDTH[gen_si_slot*32+:6])
)
wdata_router_w
(
.ACLK (ACLK),
.ARESET (reset),
// Write transfer input from the current SI-slot
.S_WMESG (si_wr_wmesg[gen_si_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH]),
.S_WLAST (S_AXI_WLAST[gen_si_slot]),
.S_WVALID (S_AXI_WVALID[gen_si_slot]),
.S_WREADY (S_AXI_WREADY[gen_si_slot]),
// Vector of write transfer outputs to each MI-slot's W-mux
.M_WMESG (wr_wm_wmesg[gen_si_slot*(P_WR_WMESG_WIDTH)+:P_WR_WMESG_WIDTH]),
.M_WLAST (wr_wm_wlast[gen_si_slot]),
.M_WVALID (wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
.M_WREADY (wr_tmp_wready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
// AW command push from local SI-slot
.S_ASELECT (st_aa_awtarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]), // Target MI-slot
.S_AVALID (ss_wr_awvalid[gen_si_slot]),
.S_AREADY (ss_wr_awready[gen_si_slot])
);
assign si_wr_wmesg[gen_si_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH] = {
((C_AXI_PROTOCOL == P_AXI3) ? f_extend_ID(S_AXI_WID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) : 1'b0),
S_AXI_WUSER[gen_si_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH],
S_AXI_WSTRB[gen_si_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8],
S_AXI_WDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]
};
end else begin : gen_no_si_write
assign S_AXI_AWREADY[gen_si_slot] = 1'b0;
assign ss_aa_awvalid[gen_si_slot] = 1'b0;
assign st_aa_awvalid_qual[gen_si_slot] = 1'b1;
assign tmp_aa_awmesg[gen_si_slot*P_AA_AWMESG_WIDTH+:P_AA_AWMESG_WIDTH] = 0;
assign S_AXI_BID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;
assign S_AXI_BRESP[gen_si_slot*2+:2] = 0;
assign S_AXI_BUSER[gen_si_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = 0;
assign S_AXI_BVALID[gen_si_slot] = 1'b0;
assign st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;
assign S_AXI_WREADY[gen_si_slot] = 1'b0;
assign wr_wm_wmesg[gen_si_slot*(P_WR_WMESG_WIDTH)+:P_WR_WMESG_WIDTH] = 0;
assign wr_wm_wlast[gen_si_slot] = 1'b0;
assign wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;
assign st_aa_awtarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;
end // gen_si_write
end // gen_slave_slots
for (gen_mi_slot=0; gen_mi_slot<C_NUM_MASTER_SLOTS+1; gen_mi_slot=gen_mi_slot+1) begin : gen_master_slots
if (P_M_AXI_SUPPORTS_READ[gen_mi_slot]) begin : gen_mi_read
if (C_NUM_SLAVE_SLOTS>1) begin : gen_rid_decoder
axi_crossbar_v2_1_10_addr_decoder #
(
.C_FAMILY (C_FAMILY),
.C_NUM_TARGETS (C_NUM_SLAVE_SLOTS),
.C_NUM_TARGETS_LOG (P_NUM_SLAVE_SLOTS_LOG),
.C_NUM_RANGES (1),
.C_ADDR_WIDTH (C_AXI_ID_WIDTH),
.C_TARGET_ENC (C_DEBUG),
.C_TARGET_HOT (1),
.C_REGION_ENC (0),
.C_BASE_ADDR (C_S_AXI_BASE_ID),
.C_HIGH_ADDR (C_S_AXI_HIGH_ID),
.C_TARGET_QUAL (P_M_AXI_READ_CONNECTIVITY[gen_mi_slot*32+:C_NUM_SLAVE_SLOTS]),
.C_RESOLUTION (0)
)
rid_decoder_inst
(
.ADDR (st_mr_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.TARGET_HOT (tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),
.TARGET_ENC (debug_rid_target_i[gen_mi_slot*P_NUM_SLAVE_SLOTS_LOG+:P_NUM_SLAVE_SLOTS_LOG]),
.MATCH (rid_match[gen_mi_slot]),
.REGION ()
);
end else begin : gen_no_rid_decoder
assign tmp_mr_rid_target[gen_mi_slot] = 1'b1; // All response transfers route to solo SI-slot.
assign rid_match[gen_mi_slot] = 1'b1;
end
assign st_mr_rmesg[gen_mi_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH] = {
st_mr_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH],
st_mr_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH],
st_mr_rresp[gen_mi_slot*2+:2]
};
end else begin : gen_no_mi_read
assign tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0;
assign rid_match[gen_mi_slot] = 1'b0;
assign st_mr_rmesg[gen_mi_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH] = 0;
end // gen_mi_read
if (P_M_AXI_SUPPORTS_WRITE[gen_mi_slot]) begin : gen_mi_write
if (C_NUM_SLAVE_SLOTS>1) begin : gen_bid_decoder
axi_crossbar_v2_1_10_addr_decoder #
(
.C_FAMILY (C_FAMILY),
.C_NUM_TARGETS (C_NUM_SLAVE_SLOTS),
.C_NUM_TARGETS_LOG (P_NUM_SLAVE_SLOTS_LOG),
.C_NUM_RANGES (1),
.C_ADDR_WIDTH (C_AXI_ID_WIDTH),
.C_TARGET_ENC (C_DEBUG),
.C_TARGET_HOT (1),
.C_REGION_ENC (0),
.C_BASE_ADDR (C_S_AXI_BASE_ID),
.C_HIGH_ADDR (C_S_AXI_HIGH_ID),
.C_TARGET_QUAL (P_M_AXI_WRITE_CONNECTIVITY[gen_mi_slot*32+:C_NUM_SLAVE_SLOTS]),
.C_RESOLUTION (0)
)
bid_decoder_inst
(
.ADDR (st_mr_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.TARGET_HOT (tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),
.TARGET_ENC (debug_bid_target_i[gen_mi_slot*P_NUM_SLAVE_SLOTS_LOG+:P_NUM_SLAVE_SLOTS_LOG]),
.MATCH (bid_match[gen_mi_slot]),
.REGION ()
);
end else begin : gen_no_bid_decoder
assign tmp_mr_bid_target[gen_mi_slot] = 1'b1; // All response transfers route to solo SI-slot.
assign bid_match[gen_mi_slot] = 1'b1;
end
axi_crossbar_v2_1_10_wdata_mux # // "WM": Write data Mux, per MI-slot (incl error-handler)
(
.C_FAMILY (C_FAMILY),
.C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS),
.C_SELECT_WIDTH (P_NUM_SLAVE_SLOTS_LOG),
.C_WMESG_WIDTH (P_WR_WMESG_WIDTH),
.C_FIFO_DEPTH_LOG (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6])
)
wdata_mux_w
(
.ACLK (ACLK),
.ARESET (reset),
// Vector of write transfer inputs from each SI-slot's W-router
.S_WMESG (wr_wm_wmesg),
.S_WLAST (wr_wm_wlast),
.S_WVALID (tmp_wm_wvalid[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),
.S_WREADY (tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),
// Write transfer output to the current MI-slot
.M_WMESG (wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH]),
.M_WLAST (wm_mr_wlast[gen_mi_slot]),
.M_WVALID (wm_mr_wvalid[gen_mi_slot]),
.M_WREADY (wm_mr_wready[gen_mi_slot]),
// AW command push from AW arbiter output
.S_ASELECT (aa_wm_awgrant_enc), // SI-slot selected by arbiter
.S_AVALID (sa_wm_awvalid[gen_mi_slot]),
.S_AREADY (sa_wm_awready[gen_mi_slot])
);
if (C_DEBUG) begin : gen_debug_w
// DEBUG WRITE BEAT COUNTER
always @(posedge ACLK) begin
if (reset) begin
debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= 0;
end else begin
if (mi_wvalid[gen_mi_slot] & mi_wready[gen_mi_slot]) begin
if (mi_wlast[gen_mi_slot]) begin
debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= 0;
end else begin
debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= debug_w_beat_cnt_i[gen_mi_slot*8+:8] + 1;
end
end
end
end // clocked process
// DEBUG W-CHANNEL TRANSACTION SEQUENCE QUEUE
axi_data_fifo_v2_1_8_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]),
.C_USE_FULL (0)
)
debug_w_seq_fifo
(
.ACLK (ACLK),
.ARESET (reset),
.S_MESG (debug_aw_trans_seq_i),
.S_VALID (sa_wm_awvalid[gen_mi_slot]),
.S_READY (),
.M_MESG (debug_w_trans_seq_i[gen_mi_slot*8+:8]),
.M_VALID (),
.M_READY (mi_wvalid[gen_mi_slot] & mi_wready[gen_mi_slot] & mi_wlast[gen_mi_slot])
);
end // gen_debug_w
assign wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH +: C_AXI_DATA_WIDTH];
assign wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH +: C_AXI_DATA_WIDTH/8];
assign wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8 +: C_AXI_WUSER_WIDTH];
assign wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH+(C_AXI_DATA_WIDTH/8)+C_AXI_WUSER_WIDTH +: P_AXI_WID_WIDTH];
assign st_mr_bmesg[gen_mi_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH] = {
st_mr_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH],
st_mr_bresp[gen_mi_slot*2+:2]
};
end else begin : gen_no_mi_write
assign tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0;
assign bid_match[gen_mi_slot] = 1'b0;
assign wm_mr_wvalid[gen_mi_slot] = 0;
assign wm_mr_wlast[gen_mi_slot] = 0;
assign wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0;
assign wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = 0;
assign wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = 0;
assign wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;
assign st_mr_bmesg[gen_mi_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH] = 0;
assign tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0;
assign sa_wm_awready[gen_mi_slot] = 0;
end // gen_mi_write
for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_trans_si
// Transpose handshakes from W-router (SxM) to W-mux (MxS).
assign tmp_wm_wvalid[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot] = wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot];
assign wr_tmp_wready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot];
// Transpose response enables from ID decoders (MxS) to si_transactors (SxM).
assign st_tmp_bid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot];
assign st_tmp_rid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot];
end // gen_trans_si
assign bready_carry[gen_mi_slot] = st_tmp_bready[gen_mi_slot];
assign rready_carry[gen_mi_slot] = st_tmp_rready[gen_mi_slot];
for (gen_si_slot=1; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_resp_carry_si
assign bready_carry[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = // Generate M_BREADY if ...
bready_carry[(gen_si_slot-1)*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] | // For any SI-slot (OR carry-chain across all SI-slots), ...
st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot]; // The write SI transactor indicates BREADY for that MI-slot.
assign rready_carry[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = // Generate M_RREADY if ...
rready_carry[(gen_si_slot-1)*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] | // For any SI-slot (OR carry-chain across all SI-slots), ...
st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot]; // The write SI transactor indicates RREADY for that MI-slot.
end // gen_resp_carry_si
assign w_cmd_push[gen_mi_slot] = mi_awvalid[gen_mi_slot] && mi_awready[gen_mi_slot] && P_M_AXI_SUPPORTS_WRITE[gen_mi_slot];
assign r_cmd_push[gen_mi_slot] = mi_arvalid[gen_mi_slot] && mi_arready[gen_mi_slot] && P_M_AXI_SUPPORTS_READ[gen_mi_slot];
assign w_cmd_pop[gen_mi_slot] = st_mr_bvalid[gen_mi_slot] && st_mr_bready[gen_mi_slot] && P_M_AXI_SUPPORTS_WRITE[gen_mi_slot];
assign r_cmd_pop[gen_mi_slot] = st_mr_rvalid[gen_mi_slot] && st_mr_rready[gen_mi_slot] && st_mr_rlast[gen_mi_slot] && P_M_AXI_SUPPORTS_READ[gen_mi_slot];
// Disqualify arbitration of SI-slot if targeted MI-slot has reached its issuing limit.
assign mi_awmaxissuing[gen_mi_slot] = (w_issuing_cnt[gen_mi_slot*8 +: (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] ==
P_M_AXI_WRITE_ISSUING[gen_mi_slot*32 +: (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)]) & ~w_cmd_pop[gen_mi_slot];
assign mi_armaxissuing[gen_mi_slot] = (r_issuing_cnt[gen_mi_slot*8 +: (C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] ==
P_M_AXI_READ_ISSUING[gen_mi_slot*32 +: (C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)]) & ~r_cmd_pop[gen_mi_slot];
always @(posedge ACLK) begin
if (reset) begin
w_issuing_cnt[gen_mi_slot*8+:8] <= 0; // Some high-order bits remain constant 0
r_issuing_cnt[gen_mi_slot*8+:8] <= 0; // Some high-order bits remain constant 0
end else begin
if (w_cmd_push[gen_mi_slot] && ~w_cmd_pop[gen_mi_slot]) begin
w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] + 1;
end else if (w_cmd_pop[gen_mi_slot] && ~w_cmd_push[gen_mi_slot] && (|w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)])) begin
w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] - 1;
end
if (r_cmd_push[gen_mi_slot] && ~r_cmd_pop[gen_mi_slot]) begin
r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] + 1;
end else if (r_cmd_pop[gen_mi_slot] && ~r_cmd_push[gen_mi_slot] && (|r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)])) begin
r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] - 1;
end
end
end // Clocked process
// Reg-slice must break combinatorial path from M_BID and M_RID inputs to M_BREADY and M_RREADY outputs.
// (See m_rready_i and m_resp_en combinatorial assignments in si_transactor.)
// Reg-slice incurs +1 latency, but no bubble-cycles.
axi_register_slice_v2_1_9_axi_register_slice # // "MR": MI-side R/B-channel Reg-slice, per MI-slot (pass-through if only 1 SI-slot configured)
(
.C_FAMILY (C_FAMILY),
.C_AXI_PROTOCOL ((C_AXI_PROTOCOL == P_AXI3) ? P_AXI3 : P_AXI4),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (1),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (1),
.C_AXI_ARUSER_WIDTH (1),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_REG_CONFIG_AW (P_BYPASS),
.C_REG_CONFIG_AR (P_BYPASS),
.C_REG_CONFIG_W (P_BYPASS),
.C_REG_CONFIG_R (P_M_AXI_SUPPORTS_READ[gen_mi_slot] ? P_FWD_REV : P_BYPASS),
.C_REG_CONFIG_B (P_M_AXI_SUPPORTS_WRITE[gen_mi_slot] ? P_SIMPLE : P_BYPASS)
)
reg_slice_mi
(
.aresetn (ARESETN),
.aclk (ACLK),
.s_axi_awid ({C_AXI_ID_WIDTH{1'b0}}),
.s_axi_awaddr ({1{1'b0}}),
.s_axi_awlen ({((C_AXI_PROTOCOL == P_AXI3) ? 4 : 8){1'b0}}),
.s_axi_awsize ({3{1'b0}}),
.s_axi_awburst ({2{1'b0}}),
.s_axi_awlock ({((C_AXI_PROTOCOL == P_AXI3) ? 2 : 1){1'b0}}),
.s_axi_awcache ({4{1'b0}}),
.s_axi_awprot ({3{1'b0}}),
.s_axi_awregion ({4{1'b0}}),
.s_axi_awqos ({4{1'b0}}),
.s_axi_awuser ({1{1'b0}}),
.s_axi_awvalid ({1{1'b0}}),
.s_axi_awready (),
.s_axi_wid (wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.s_axi_wdata (wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),
.s_axi_wstrb (wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]),
.s_axi_wlast (wm_mr_wlast[gen_mi_slot]),
.s_axi_wuser (wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]),
.s_axi_wvalid (wm_mr_wvalid[gen_mi_slot]),
.s_axi_wready (wm_mr_wready[gen_mi_slot]),
.s_axi_bid (st_mr_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ),
.s_axi_bresp (st_mr_bresp[gen_mi_slot*2+:2] ),
.s_axi_buser (st_mr_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] ),
.s_axi_bvalid (st_mr_bvalid[gen_mi_slot*1+:1] ),
.s_axi_bready (st_mr_bready[gen_mi_slot*1+:1] ),
.s_axi_arid ({C_AXI_ID_WIDTH{1'b0}}),
.s_axi_araddr ({1{1'b0}}),
.s_axi_arlen ({((C_AXI_PROTOCOL == P_AXI3) ? 4 : 8){1'b0}}),
.s_axi_arsize ({3{1'b0}}),
.s_axi_arburst ({2{1'b0}}),
.s_axi_arlock ({((C_AXI_PROTOCOL == P_AXI3) ? 2 : 1){1'b0}}),
.s_axi_arcache ({4{1'b0}}),
.s_axi_arprot ({3{1'b0}}),
.s_axi_arregion ({4{1'b0}}),
.s_axi_arqos ({4{1'b0}}),
.s_axi_aruser ({1{1'b0}}),
.s_axi_arvalid ({1{1'b0}}),
.s_axi_arready (),
.s_axi_rid (st_mr_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ),
.s_axi_rdata (st_mr_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] ),
.s_axi_rresp (st_mr_rresp[gen_mi_slot*2+:2] ),
.s_axi_rlast (st_mr_rlast[gen_mi_slot*1+:1] ),
.s_axi_ruser (st_mr_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] ),
.s_axi_rvalid (st_mr_rvalid[gen_mi_slot*1+:1] ),
.s_axi_rready (st_mr_rready[gen_mi_slot*1+:1] ),
.m_axi_awid (),
.m_axi_awaddr (),
.m_axi_awlen (),
.m_axi_awsize (),
.m_axi_awburst (),
.m_axi_awlock (),
.m_axi_awcache (),
.m_axi_awprot (),
.m_axi_awregion (),
.m_axi_awqos (),
.m_axi_awuser (),
.m_axi_awvalid (),
.m_axi_awready ({1{1'b0}}),
.m_axi_wid (mi_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.m_axi_wdata (mi_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),
.m_axi_wstrb (mi_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]),
.m_axi_wlast (mi_wlast[gen_mi_slot]),
.m_axi_wuser (mi_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]),
.m_axi_wvalid (mi_wvalid[gen_mi_slot]),
.m_axi_wready (mi_wready[gen_mi_slot]),
.m_axi_bid (mi_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ),
.m_axi_bresp (mi_bresp[gen_mi_slot*2+:2] ),
.m_axi_buser (mi_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] ),
.m_axi_bvalid (mi_bvalid[gen_mi_slot*1+:1] ),
.m_axi_bready (mi_bready[gen_mi_slot*1+:1] ),
.m_axi_arid (),
.m_axi_araddr (),
.m_axi_arlen (),
.m_axi_arsize (),
.m_axi_arburst (),
.m_axi_arlock (),
.m_axi_arcache (),
.m_axi_arprot (),
.m_axi_arregion (),
.m_axi_arqos (),
.m_axi_aruser (),
.m_axi_arvalid (),
.m_axi_arready ({1{1'b0}}),
.m_axi_rid (mi_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ),
.m_axi_rdata (mi_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] ),
.m_axi_rresp (mi_rresp[gen_mi_slot*2+:2] ),
.m_axi_rlast (mi_rlast[gen_mi_slot*1+:1] ),
.m_axi_ruser (mi_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] ),
.m_axi_rvalid (mi_rvalid[gen_mi_slot*1+:1] ),
.m_axi_rready (mi_rready[gen_mi_slot*1+:1] )
);
end // gen_master_slots (Next gen_mi_slot)
// Highest row of *ready_carry contains accumulated OR across all SI-slots, for each MI-slot.
assign st_mr_bready = bready_carry[(C_NUM_SLAVE_SLOTS-1)*(C_NUM_MASTER_SLOTS+1) +: C_NUM_MASTER_SLOTS+1];
assign st_mr_rready = rready_carry[(C_NUM_SLAVE_SLOTS-1)*(C_NUM_MASTER_SLOTS+1) +: C_NUM_MASTER_SLOTS+1];
// Assign MI-side B, R and W channel ports (exclude error handler signals).
assign mi_bid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] = M_AXI_BID;
assign mi_bvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_BVALID;
assign mi_bresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_BRESP;
assign mi_buser[0+:C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH] = M_AXI_BUSER;
assign M_AXI_BREADY = mi_bready[0+:C_NUM_MASTER_SLOTS];
assign mi_rid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] = M_AXI_RID;
assign mi_rlast[0+:C_NUM_MASTER_SLOTS] = M_AXI_RLAST;
assign mi_rvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_RVALID;
assign mi_rresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_RRESP;
assign mi_ruser[0+:C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH] = M_AXI_RUSER;
assign mi_rdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH] = M_AXI_RDATA;
assign M_AXI_RREADY = mi_rready[0+:C_NUM_MASTER_SLOTS];
assign M_AXI_WLAST = mi_wlast[0+:C_NUM_MASTER_SLOTS];
assign M_AXI_WVALID = mi_wvalid[0+:C_NUM_MASTER_SLOTS];
assign M_AXI_WUSER = mi_wuser[0+:C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH];
assign M_AXI_WID = (C_AXI_PROTOCOL == P_AXI3) ? mi_wid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] : 0;
assign M_AXI_WDATA = mi_wdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH];
assign M_AXI_WSTRB = mi_wstrb[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8];
assign mi_wready[0+:C_NUM_MASTER_SLOTS] = M_AXI_WREADY;
axi_crossbar_v2_1_10_addr_arbiter # // "AA": Addr Arbiter (AW channel)
(
.C_FAMILY (C_FAMILY),
.C_NUM_M (C_NUM_MASTER_SLOTS+1),
.C_NUM_S (C_NUM_SLAVE_SLOTS),
.C_NUM_S_LOG (P_NUM_SLAVE_SLOTS_LOG),
.C_MESG_WIDTH (P_AA_AWMESG_WIDTH),
.C_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY)
)
addr_arbiter_aw
(
.ACLK (ACLK),
.ARESET (reset),
// Vector of SI-side AW command request inputs
.S_MESG (tmp_aa_awmesg),
.S_TARGET_HOT (st_aa_awtarget_hot),
.S_VALID (ss_aa_awvalid),
.S_VALID_QUAL (st_aa_awvalid_qual),
.S_READY (ss_aa_awready),
// Granted AW command output
.M_MESG (aa_mi_awmesg),
.M_TARGET_HOT (aa_mi_awtarget_hot), // MI-slot targeted by granted command
.M_GRANT_ENC (aa_wm_awgrant_enc), // SI-slot index of granted command
.M_VALID (aa_sa_awvalid),
.M_READY (aa_sa_awready),
.ISSUING_LIMIT (mi_awmaxissuing)
);
// Broadcast AW transfer payload to all MI-slots
assign M_AXI_AWID = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[0+:C_AXI_ID_WIDTH]}};
assign M_AXI_AWADDR = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+:C_AXI_ADDR_WIDTH]}};
assign M_AXI_AWLEN = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]}};
assign M_AXI_AWSIZE = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +:3]}};
assign M_AXI_AWLOCK = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +:2]}};
assign M_AXI_AWPROT = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +:3]}};
assign M_AXI_AWREGION = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +:4]}};
assign M_AXI_AWBURST = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4 +:2]}};
assign M_AXI_AWCACHE = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2 +:4]}};
assign M_AXI_AWQOS = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4 +:4]}};
assign M_AXI_AWUSER = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4+4 +:C_AXI_AWUSER_WIDTH]}};
axi_crossbar_v2_1_10_addr_arbiter # // "AA": Addr Arbiter (AR channel)
(
.C_FAMILY (C_FAMILY),
.C_NUM_M (C_NUM_MASTER_SLOTS+1),
.C_NUM_S (C_NUM_SLAVE_SLOTS),
.C_NUM_S_LOG (P_NUM_SLAVE_SLOTS_LOG),
.C_MESG_WIDTH (P_AA_ARMESG_WIDTH),
.C_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY)
)
addr_arbiter_ar
(
.ACLK (ACLK),
.ARESET (reset),
// Vector of SI-side AR command request inputs
.S_MESG (tmp_aa_armesg),
.S_TARGET_HOT (st_aa_artarget_hot),
.S_VALID_QUAL (st_aa_arvalid_qual),
.S_VALID (st_aa_arvalid),
.S_READY (st_aa_arready),
// Granted AR command output
.M_MESG (aa_mi_armesg),
.M_TARGET_HOT (aa_mi_artarget_hot), // MI-slot targeted by granted command
.M_GRANT_ENC (aa_mi_argrant_enc),
.M_VALID (aa_mi_arvalid), // SI-slot index of granted command
.M_READY (aa_mi_arready),
.ISSUING_LIMIT (mi_armaxissuing)
);
if (C_DEBUG) begin : gen_debug_trans_seq
// DEBUG WRITE TRANSACTION SEQUENCE COUNTER
always @(posedge ACLK) begin
if (reset) begin
debug_aw_trans_seq_i <= 1;
end else begin
if (aa_sa_awvalid && aa_sa_awready) begin
debug_aw_trans_seq_i <= debug_aw_trans_seq_i + 1;
end
end
end
// DEBUG READ TRANSACTION SEQUENCE COUNTER
always @(posedge ACLK) begin
if (reset) begin
debug_ar_trans_seq_i <= 1;
end else begin
if (aa_mi_arvalid && aa_mi_arready) begin
debug_ar_trans_seq_i <= debug_ar_trans_seq_i + 1;
end
end
end
end // gen_debug_trans_seq
// Broadcast AR transfer payload to all MI-slots
assign M_AXI_ARID = {C_NUM_MASTER_SLOTS{aa_mi_armesg[0+:C_AXI_ID_WIDTH]}};
assign M_AXI_ARADDR = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+:C_AXI_ADDR_WIDTH]}};
assign M_AXI_ARLEN = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]}};
assign M_AXI_ARSIZE = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +:3]}};
assign M_AXI_ARLOCK = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +:2]}};
assign M_AXI_ARPROT = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +:3]}};
assign M_AXI_ARREGION = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +:4]}};
assign M_AXI_ARBURST = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4 +:2]}};
assign M_AXI_ARCACHE = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2 +:4]}};
assign M_AXI_ARQOS = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4 +:4]}};
assign M_AXI_ARUSER = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4+4 +:C_AXI_ARUSER_WIDTH]}};
// AW arbiter command transfer completes upon completion of both M-side AW-channel transfer and W-mux address acceptance (command push).
axi_crossbar_v2_1_10_splitter # // "SA": Splitter for Write Addr Arbiter
(
.C_NUM_M (2)
)
splitter_aw_mi
(
.ACLK (ACLK),
.ARESET (reset),
.S_VALID (aa_sa_awvalid),
.S_READY (aa_sa_awready),
.M_VALID ({mi_awvalid_en, sa_wm_awvalid_en}),
.M_READY ({mi_awready_mux, sa_wm_awready_mux})
);
assign mi_awvalid = aa_mi_awtarget_hot & {C_NUM_MASTER_SLOTS+1{mi_awvalid_en}};
assign mi_awready_mux = |(aa_mi_awtarget_hot & mi_awready);
assign M_AXI_AWVALID = mi_awvalid[0+:C_NUM_MASTER_SLOTS]; // Slot C_NUM_MASTER_SLOTS+1 is the error handler
assign mi_awready[0+:C_NUM_MASTER_SLOTS] = M_AXI_AWREADY;
assign sa_wm_awvalid = aa_mi_awtarget_hot & {C_NUM_MASTER_SLOTS+1{sa_wm_awvalid_en}};
assign sa_wm_awready_mux = |(aa_mi_awtarget_hot & sa_wm_awready);
assign mi_arvalid = aa_mi_artarget_hot & {C_NUM_MASTER_SLOTS+1{aa_mi_arvalid}};
assign aa_mi_arready = |(aa_mi_artarget_hot & mi_arready);
assign M_AXI_ARVALID = mi_arvalid[0+:C_NUM_MASTER_SLOTS]; // Slot C_NUM_MASTER_SLOTS+1 is the error handler
assign mi_arready[0+:C_NUM_MASTER_SLOTS] = M_AXI_ARREADY;
// MI-slot # C_NUM_MASTER_SLOTS is the error handler
if (C_RANGE_CHECK) begin : gen_decerr_slave
axi_crossbar_v2_1_10_decerr_slave #
(
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_RESP (P_DECERR)
)
decerr_slave_inst
(
.S_AXI_ACLK (ACLK),
.S_AXI_ARESET (reset),
.S_AXI_AWID (aa_mi_awmesg[0+:C_AXI_ID_WIDTH]),
.S_AXI_AWVALID (mi_awvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_AWREADY (mi_awready[C_NUM_MASTER_SLOTS]),
.S_AXI_WLAST (mi_wlast[C_NUM_MASTER_SLOTS]),
.S_AXI_WVALID (mi_wvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_WREADY (mi_wready[C_NUM_MASTER_SLOTS]),
.S_AXI_BID (mi_bid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.S_AXI_BRESP (mi_bresp[C_NUM_MASTER_SLOTS*2+:2]),
.S_AXI_BUSER (mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]),
.S_AXI_BVALID (mi_bvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_BREADY (mi_bready[C_NUM_MASTER_SLOTS]),
.S_AXI_ARID (aa_mi_armesg[0+:C_AXI_ID_WIDTH]),
.S_AXI_ARLEN (aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]),
.S_AXI_ARVALID (mi_arvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_ARREADY (mi_arready[C_NUM_MASTER_SLOTS]),
.S_AXI_RID (mi_rid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.S_AXI_RDATA (mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),
.S_AXI_RRESP (mi_rresp[C_NUM_MASTER_SLOTS*2+:2]),
.S_AXI_RUSER (mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]),
.S_AXI_RLAST (mi_rlast[C_NUM_MASTER_SLOTS]),
.S_AXI_RVALID (mi_rvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_RREADY (mi_rready[C_NUM_MASTER_SLOTS])
);
end else begin : gen_no_decerr_slave
assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0;
assign mi_wready[C_NUM_MASTER_SLOTS] = 1'b0;
assign mi_arready[C_NUM_MASTER_SLOTS] = 1'b0;
assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0;
assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0;
assign mi_bid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;
assign mi_bresp[C_NUM_MASTER_SLOTS*2+:2] = 0;
assign mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = 0;
assign mi_bvalid[C_NUM_MASTER_SLOTS] = 1'b0;
assign mi_rid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;
assign mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0;
assign mi_rresp[C_NUM_MASTER_SLOTS*2+:2] = 0;
assign mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = 0;
assign mi_rlast[C_NUM_MASTER_SLOTS] = 1'b0;
assign mi_rvalid[C_NUM_MASTER_SLOTS] = 1'b0;
end // gen_decerr_slave
endgenerate
endmodule
`default_nettype wire
|
module SigmaDeltaPhasedArray #(
parameter NUM_CH = 64, ///< Number of input channels
parameter ADDR_WIDTH = 8, ///< Depth of sample buffers
parameter OUT_WIDTH = 16, ///< Width of output signal
parameter OUT_DELAY = 3 ///< Specified delay between cmdIn/invertBit and dataOut
)
(
input clk,
input rst,
input sample,
input [NUM_CH-1:0] dataIn,
input [NUM_CH*ADDR_WIDTH-1:0] cmdIn, ///< Array of which sample to pull from each channel
input [NUM_CH-1:0] invertBit, ///< 1 to invert channel bit, 0 to not invert
output [OUT_WIDTH-1:0] outData
);
///////////////////////////////////////////////////////////////////////////
// PARAMETER DECLARATIONS
///////////////////////////////////////////////////////////////////////////
initial begin
if ((2**OUT_WIDTH-1) < NUM_CH) begin
$display("Attribute OUT_WIDTH on phaseDelay instance %m is %i. Must be at least %i (log2(NUM_CH+1)).", OUT_WIDTH, $log2(NUM_CH+1));
#1 $finish;
end
end
parameter SUM_DEPTH = $rtoi($ceil($log10(NUM_CH/3.0)/$log10(3.0)));
parameter NUM_SUMS = 3**SUM_DEPTH;
localparam NUM_128BUF = (ADDR_WIDTH > 7) ? (1 << (ADDR_WIDTH-7)) : 1;
localparam MUX_ADDR_WIDTH = (ADDR_WIDTH > 7) ? (ADDR_WIDTH-7) : 1;
///////////////////////////////////////////////////////////////////////////
// SIGNAL DECLARATIONS
///////////////////////////////////////////////////////////////////////////
genvar chIndex;
genvar bufIndex;
integer sumIndex;
integer addr128Index;
integer addrIndex;
integer muxIndex;
reg [NUM_SUMS*2-1:0] sumsReg;
reg [NUM_SUMS*2-1:0] sums;
reg [ADDR_WIDTH-1:0] bufAddr [NUM_CH-1:0];
reg [6:0] buf128Addr [NUM_CH-1:0];
reg [MUX_ADDR_WIDTH-1:0] muxAddr [NUM_CH-1:0];
wire [NUM_128BUF:0] shiftArray [NUM_CH-1:0];
reg [NUM_CH-1:0] invertBitBuf;
reg [NUM_CH-1:0] invertBitD1;
reg [NUM_128BUF-1:0] buf128Out [NUM_CH-1:0];
reg [NUM_CH-1:0] bufOut;
///////////////////////////////////////////////////////////////////////////
// BUFFERS & ADDRESS LOGIC
///////////////////////////////////////////////////////////////////////////
// Split up the inputs & optionally delay them
if (OUT_DELAY > SUM_DEPTH+2) begin
always @(posedge clk) begin
invertBitD1 <= invertBit;
for (addrIndex=0; addrIndex<NUM_CH; addrIndex=addrIndex+1) begin
bufAddr[addrIndex] <= cmdIn[(addrIndex*ADDR_WIDTH)+:ADDR_WIDTH];
end
end
end
else begin
always @(*) begin
invertBitD1 = invertBit;
for (addrIndex=0; addrIndex<NUM_CH; addrIndex=addrIndex+1) begin
bufAddr[addrIndex] = cmdIn[(addrIndex*ADDR_WIDTH)+:ADDR_WIDTH];
end
end
end
if (OUT_DELAY > SUM_DEPTH+1) begin
always @(posedge clk) invertBitBuf <= invertBitD1;
end
else begin
always @(*) invertBitBuf = invertBitD1;
end
// Get the buf128 addresses
always @(*) begin
for (addr128Index=0; addr128Index<NUM_CH; addr128Index=addr128Index+1) begin
buf128Addr[addr128Index] = bufAddr[addr128Index];
end
end
// Generate the 128 sample deep buffers
generate
for (chIndex=0;chIndex<NUM_CH; chIndex=chIndex+1) begin
assign shiftArray[chIndex][0] = dataIn[chIndex];
for (bufIndex=0; bufIndex<NUM_128BUF; bufIndex=bufIndex+1) begin
SigmaDeltaPhasedArray128Buf sampleBuffer (
.clk(clk),
.sample(sample),
.shiftIn(shiftArray[chIndex][bufIndex]),
.addr(buf128Addr[chIndex]), ///< [6:0]
.shiftOut(shiftArray[chIndex][bufIndex+1]),
.dataOut(buf128Out[chIndex][bufIndex])
);
end
end
endgenerate
// Multiplexers to select from the sample buffers
if (NUM_128BUF == 1) begin
if (OUT_DELAY > SUM_DEPTH+1) begin
always @(posedge clk) begin
for (muxIndex=0; muxIndex<NUM_CH; muxIndex=muxIndex+1) begin
bufOut[muxIndex] <= buf128Out[muxIndex][0];
end
end
end
else begin
always @(*) begin
for (muxIndex=0; muxIndex<NUM_CH; muxIndex=muxIndex+1) begin
bufOut[muxIndex] <= buf128Out[muxIndex][0];
end
end
end
end
else begin
if (OUT_DELAY > SUM_DEPTH+1) begin
always @(posedge clk) begin
for (muxIndex=0; muxIndex<NUM_CH; muxIndex=muxIndex+1) begin
bufOut[muxIndex] <= buf128Out[muxIndex][bufAddr[muxIndex][ADDR_WIDTH-1:7]];
end
end
end
else begin
always @(*) begin
for (muxIndex=0; muxIndex<NUM_CH; muxIndex=muxIndex+1) begin
bufOut[muxIndex] <= buf128Out[muxIndex][bufAddr[muxIndex][ADDR_WIDTH-1:7]];
end
end
end
end
///////////////////////////////////////////////////////////////////////////
// SUMMATION
///////////////////////////////////////////////////////////////////////////
// Sum 3 bits
always @(*) begin
sums = 'd0;
for (sumIndex=0; sumIndex<NUM_CH/3; sumIndex=sumIndex+1) begin
sums[sumIndex] = (invertBitBuf[sumIndex+0] ^ bufOut[sumIndex+0])
^ (invertBitBuf[sumIndex+1] ^ bufOut[sumIndex+1])
^ (invertBitBuf[sumIndex+2] ^ bufOut[sumIndex+2]);
sums[sumIndex+1] = (invertBitBuf[sumIndex+0] ^ bufOut[sumIndex+0]) & (invertBitBuf[sumIndex+1] ^ bufOut[sumIndex+1])
| (invertBitBuf[sumIndex+1] ^ bufOut[sumIndex+1]) & (invertBitBuf[sumIndex+2] ^ bufOut[sumIndex+2])
| (invertBitBuf[sumIndex+2] ^ bufOut[sumIndex+2]) & (invertBitBuf[sumIndex+0] ^ bufOut[sumIndex+0]);
end
if (NUM_CH % 3 == 1) begin
sums[(NUM_CH/3)*2-2] = (invertBitBuf[NUM_CH-1] ^ bufOut[NUM_CH-1]);
sums[(NUM_CH/3)*2-1] = 1'b0;
end
else if (NUM_CH % 3 == 2) begin
sums[(NUM_CH/3)*2-2] = (invertBitBuf[NUM_CH-2] ^ bufOut[NUM_CH-2])
^ (invertBitBuf[NUM_CH-1] ^ bufOut[NUM_CH-1]);
sums[(NUM_CH/3)*2-1] = (invertBitBuf[NUM_CH-2] ^ bufOut[NUM_CH-2])
& (invertBitBuf[NUM_CH-1] ^ bufOut[NUM_CH-1]);
end
end
// Register sums if necessary
if (OUT_DELAY > SUM_DEPTH) begin
always @(posedge clk) sumsReg <= sums;
end
else begin
always @(*) sumsReg = sums;
end
// Nested summations
if (SUM_DEPTH >= 1) begin
// At least 4 channels exist - sum them
reg [3:0] sum3 [NUM_SUMS/3-1:0];
integer sum3Index;
if (OUT_DELAY > SUM_DEPTH-1) begin
always @(posedge clk) begin
for (sum3Index=0; sum3Index<NUM_SUMS/3; sum3Index=sum3Index+1) begin
sum3[sum3Index] <= sumsReg[3*sum3Index+:2] + sumsReg[3*sum3Index+1+:2] + sumsReg[3*sum3Index+2+:2];
end
end
always @(*) begin
for (sum3Index=0; sum3Index<NUM_SUMS/3; sum3Index=sum3Index+1) begin
sum3[sum3Index] = sumsReg[3*sum3Index+:2] + sumsReg[3*sum3Index+1+:2] + sumsReg[3*sum3Index+2+:2];
end
end
end
// At least 10 channels exist - sum them
if (SUM_DEPTH >= 2) begin
reg [4:0] sum9 [NUM_SUMS/9-1:0];
integer sum9Index;
if (OUT_DELAY > SUM_DEPTH-2) begin
always @(posedge clk) begin
for (sum9Index=0; sum9Index<NUM_SUMS/9; sum9Index=sum9Index+1) begin
sum9[sum9Index] <= sum3[sum9Index] + sum3[sum9Index+1] + sum3[sum9Index+2];
end
end
end
else begin
always @(*) begin
for (sum9Index=0; sum9Index<NUM_SUMS/9; sum9Index=sum9Index+1) begin
sum9[sum9Index] = sum3[sum9Index] + sum3[sum9Index+1] + sum3[sum9Index+2];
end
end
end
// At least 28 channels exist - sum them
if (SUM_DEPTH >= 3) begin
reg [6:0] sum27 [NUM_SUMS/27-1:0];
integer sum27Index;
if (OUT_DELAY > SUM_DEPTH-3) begin
always @(posedge clk) begin
for (sum27Index=0; sum27Index<NUM_SUMS/27; sum27Index=sum27Index+1) begin
sum27[sum27Index] <= sum9[sum27Index] + sum9[sum27Index+1] + sum9[sum27Index+2];
end
end
end
else begin
always @(*) begin
for (sum27Index=0; sum27Index<NUM_SUMS/27; sum27Index=sum27Index+1) begin
sum27[sum27Index] = sum9[sum27Index] + sum9[sum27Index+1] + sum9[sum27Index+2];
end
end
end
// At least 82 channels exist - sum them
// This supports up to 243 channels
if (SUM_DEPTH >= 4) begin
reg [7:0] sum81;
if (OUT_DELAY >= 1) begin
always @(posedge clk) begin
sum81 <= sum27[0] + sum27[1] + sum27[2];
end
end
else begin
always @(*) begin
sum81 = sum27[0] + sum27[1] + sum27[2];
end
end
assign outData = sum81;
end
else begin
assign outData = sum27[0];
end
end
else begin
assign outData = sum9[0];
end
end
else begin
assign outData = sum3[0];
end
end
else begin
assign outData = sums[1:0];
end
endmodule
///////////////////////////////////////////////////////////////////////////
// BUFFER SUBMODULE
///////////////////////////////////////////////////////////////////////////
module SigmaDeltaPhasedArray128Buf (
input clk,
input sample,
input shiftIn,
input [6:0] addr,
output shiftOut,
output dataOut
);
reg [127:0] shiftReg;
assign dataOut = shiftReg[addr];
assign shiftOut = shiftReg[127];
always @(posedge clk) begin
if (sample) begin
shiftReg <= {shiftReg[126:0], shiftIn};
end
end
endmodule
|
// arWCIS2A4LM.v - Bridge module from WCI-Slave to AXI4-Lite Master
// Copyright (c) 2010 Atomic Rules LLC, ALL RIGHTS RESERVED
//
// 2010-09-12 Module declaration in Verilog
// 2010-09-14 20b, 1MB Address Window on both sides of bridge
// 2011-01-15 Switch to 32b 4GB address
module arWCI2A4LM (
input bridge_Clk,
input bridge_Reset_n,
input [2:0] wciS0_MCmd, // WCI Slave...
input [0:0] wciS0_MAddrSpace, // MAddrSpace[0]: 0=Control ; 1=Configuration
input [3:0] wciS0_MByteEn,
input [31:0] wciS0_MAddr, // 32b 4GB Address Space
input [31:0] wciS0_MData,
output [1:0] wciS0_SResp,
output [31:0] wciS0_SData,
output [0:0] wciS0_SThreadBusy,
output [0:0] wciS0_SFlag,
input [0:0] wciS0_MFlag,
output axiM0_AWVALID, // AXI4-Lite Write-Address channel...
input axiM0_AWREADY,
output [31:0] axiM0_AWADDR, // 32b 4GB Address Space
output [2:0] axiM0_AWPROT,
output axiM0_WVALID, // AXI4-Lite Write-Data channel...
input axiM0_WREADY,
output [31:0] axiM0_WDATA,
output [3:0] axiM0_WSTRB,
input axiM0_BVALID, // AXI4-Lite Write-Response channel...
output axiM0_BREADY,
input [1:0] axiM0_BRESP,
output axiM0_ARVALID, // AXI4-Lite Read-Address channel...
input axiM0_ARREADY,
output [31:0] axiM0_ARADDR, // 32b 4GB Address Space
output [2:0] axiM0_ARPROT, // ARPROT[2]: 0=Data/Configuration ; 1=Instruction/Control
input axiM0_RVALID, // AXI4-Lite Read-Data channel...
output axiM0_RREADY,
input [31:0] axiM0_RDATA,
input [1:0] axiM0_RRESP
);
wire[34:0] axiM0_wrAddr_data = {axiM0_AWPROT, axiM0_AWADDR};
wire[35:0] axiM0_wrData_data = {axiM0_WSTRB, axiM0_WDATA};
wire[1:0] axiM0_wrResp_data_value = {axiM0_BRESP};
wire[34:0] axiM0_rdAddr_data = {axiM0_ARPROT, axiM0_ARADDR};
wire[33:0] axiM0_rdResp_data_value = {axiM0_RRESP, axiM0_RDATA};
// Instance the BSV module...
mkWCI2A4LM bridge(
.wciS0_Clk (bridge_Clk),
.wciS0_MReset_n (bridge_Reset_n),
.wciS0_MCmd (wciS0_MCmd),
.wciS0_MAddrSpace (wciS0_AddrSpace),
.wciS0_MByteEn (wciS0_MByteEn),
.wciS0_MAddr (wciS0_MAddr),
.wciS0_MData (wciS0_MData),
.wciS0_SResp (wciS0_SResp),
.wciS0_SData (wciS0_SData),
.wciS0_SThreadBusy (wciS0_SThreadBusy),
.wciS0_SFlag (wciS0_SFlag),
.wciS0_MFlag (wciS0_MFlag),
.axiM0_wrAddr_data (axiM0_wrAddr_data),
.axiM0_wrAddr_valid (axiM0_AWVALID),
.axiM0_wrAddr_ready_value (axiM0_AWREADY),
.axiM0_wrData_data (axiM0_wrData_data),
.axiM0_wrData_valid (axiM0_WVALID),
.axiM0_wrData_ready_value (axiM0_WREADY),
.axiM0_wrResp_data_value (axiM0_wrResp_data_value),
.axiM0_wrResp_valid_value (axiM0_BVALID),
.axiM0_wrResp_ready (axiM0_BREADY),
.axiM0_rdAddr_data (axiM0_rdAddr_data),
.axiM0_rdAddr_valid (axiM0_ARVALID),
.axiM0_rdAddr_ready_value (axiM0_ARREADY),
.axiM0_rdResp_data_value (axiM0_rdResp_data_value),
.axiM0_rdResp_valid_value (axiM0_RVALID),
.axiM0_rdResp_ready (axiM0_RREADY)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22A_1_V
`define SKY130_FD_SC_HVL__O22A_1_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__o22a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__o22a_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__o22a_1 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22A_1_V
|
/*
* Miller Encoder
*
* By our algorithm, Miller Encoder can operate in the lowest frequency
* to save the power dissipation
*
* This algorithm is also applied to FMo Encoder
*
* If enable Miller Encoder, disable FM0 Encoder and vice versa
*/
`timescale 1us / 1ns
module miller_enc
(
output miller_data,
output mil_complete,
input clk_mil,
input rst_for_new_package,
input clk_blf,
input send_data,
input en_fm0, // if en_fm0 = 0, enable miller encoder
input trext,
input st_enc,
input fg_complete
);
parameter GetData = 2'b00;
parameter DataP = 2'b01;
parameter DataN = 2'b10;
reg [1:0]ps;
reg [1:0]ns;
wire clk_blf_n;
wire en_mil_out;
wire m2o;
wire mp_complete;
wire me_start;
reg [5:0]mp_end;
reg [5:0]mp_cnt;
reg m_cnt;
reg m1o;
reg [1:0]data_select;
reg [1:0]fg_comp_cnt;
assign clk_blf_n = ~clk_blf;
assign en_mil_out = (mp_cnt > 6'h0)? 1'b1 : 1'b0;
assign miller_data = (en_mil_out & ~mil_complete)? m2o : 1'b0;
assign m2o = mp_complete? m1o : clk_blf;
assign mp_complete = (mp_cnt == mp_end)? 1'b1 : 1'b0;
assign me_start = (mp_cnt > mp_end - 6'h2)? 1'b1 : 1'b0;
always@(*) begin
if(~trext) mp_end = 6'h9;
else mp_end = 6'h21;
end
always@(posedge clk_mil or negedge rst_for_new_package) begin
if(~rst_for_new_package) mp_cnt <= 6'h0;
else begin
if(mp_cnt == mp_end) mp_cnt <= mp_cnt;
else if(~en_fm0 & st_enc) mp_cnt <= mp_cnt + 6'h1;
end
end
always@(posedge clk_mil or negedge rst_for_new_package) begin
if(~rst_for_new_package) m_cnt <= 1'b0;
else if(me_start) m_cnt <= m_cnt + 1'b1;
end
always@(posedge clk_mil or negedge rst_for_new_package) begin
if(~rst_for_new_package) ps <= GetData;
else if(st_enc) ps <= ns;
end
always@(*) begin
case(ps)
GetData : if(~en_fm0 & me_start) ns = DataP;
else ns = GetData;
DataP : if(~send_data) ns = DataP;
else begin
if(~m_cnt) ns = DataP;
else ns = DataN;
end
DataN : if(~send_data) ns = DataN;
else begin
if(~m_cnt) ns = DataN;
else ns = DataP;
end
default : ns = GetData;
endcase
end
always@(*) begin
case(ps)
GetData : data_select = 2'h0;
DataP : data_select = 2'h1;
DataN : data_select = 2'h2;
default : data_select = 2'h0;
endcase
end
always@(*) begin
case(data_select)
2'h0 : m1o = 1'b0;
2'h1 : m1o = clk_blf;
2'h2 : m1o = clk_blf_n;
default : m1o = 1'b0;
endcase
end
always@(posedge clk_mil or negedge rst_for_new_package) begin
if(~rst_for_new_package) fg_comp_cnt <= 2'b0;
else begin
if(fg_comp_cnt == 2'b11) fg_comp_cnt <= fg_comp_cnt;
else if(~en_fm0 & fg_complete) fg_comp_cnt <= fg_comp_cnt + 2'b1;
end
end
assign mil_complete = (fg_comp_cnt == 2'b11)? 1'b1 : 1'b0;
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:12.0
// IP Revision: 2
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module fifo_async_103x32 (
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
prog_full
);
input wire rst;
input wire wr_clk;
input wire rd_clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
input wire [102 : 0] din;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
input wire wr_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
input wire rd_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
output wire [102 : 0] dout;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
output wire full;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
output wire empty;
output wire prog_full;
fifo_generator_v12_0 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(5),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(103),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(103),
.C_ENABLE_RLOCS(0),
.C_FAMILY("zynq"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(16),
.C_PROG_FULL_THRESH_NEGATE_VAL(15),
.C_PROG_FULL_TYPE(1),
.C_RD_DATA_COUNT_WIDTH(5),
.C_RD_DEPTH(32),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(5),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_PIPELINE_REG(0),
.C_POWER_SAVING_MODE(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(5),
.C_WR_DEPTH(32),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(5),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(2),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(1),
.C_HAS_AXI_ID(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(1),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(1),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(8),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(1),
.C_AXIS_TKEEP_WIDTH(1),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_PRIM_FIFO_TYPE_WACH("512x36"),
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
.C_PRIM_FIFO_TYPE_RACH("512x36"),
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
.C_PRIM_FIFO_TYPE_AXIS("1kx18"),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) inst (
.backup(1'D0),
.backup_marker(1'D0),
.clk(1'D0),
.rst(rst),
.srst(1'D0),
.wr_clk(wr_clk),
.wr_rst(1'D0),
.rd_clk(rd_clk),
.rd_rst(1'D0),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.prog_empty_thresh(5'B0),
.prog_empty_thresh_assert(5'B0),
.prog_empty_thresh_negate(5'B0),
.prog_full_thresh(5'B0),
.prog_full_thresh_assert(5'B0),
.prog_full_thresh_negate(5'B0),
.int_clk(1'D0),
.injectdbiterr(1'D0),
.injectsbiterr(1'D0),
.sleep(1'D0),
.dout(dout),
.full(full),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(empty),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(prog_full),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.wr_rst_busy(),
.rd_rst_busy(),
.m_aclk(1'D0),
.s_aclk(1'D0),
.s_aresetn(1'D0),
.m_aclk_en(1'D0),
.s_aclk_en(1'D0),
.s_axi_awid(1'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awlock(1'B0),
.s_axi_awcache(4'B0),
.s_axi_awprot(3'B0),
.s_axi_awqos(4'B0),
.s_axi_awregion(4'B0),
.s_axi_awuser(1'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wid(1'B0),
.s_axi_wdata(64'B0),
.s_axi_wstrb(8'B0),
.s_axi_wlast(1'D0),
.s_axi_wuser(1'B0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'D0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'D0),
.m_axi_bid(1'B0),
.m_axi_bresp(2'B0),
.m_axi_buser(1'B0),
.m_axi_bvalid(1'D0),
.m_axi_bready(),
.s_axi_arid(1'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arlock(1'B0),
.s_axi_arcache(4'B0),
.s_axi_arprot(3'B0),
.s_axi_arqos(4'B0),
.s_axi_arregion(4'B0),
.s_axi_aruser(1'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'D0),
.m_axi_rid(1'B0),
.m_axi_rdata(64'B0),
.m_axi_rresp(2'B0),
.m_axi_rlast(1'D0),
.m_axi_ruser(1'B0),
.m_axi_rvalid(1'D0),
.m_axi_rready(),
.s_axis_tvalid(1'D0),
.s_axis_tready(),
.s_axis_tdata(8'B0),
.s_axis_tstrb(1'B0),
.s_axis_tkeep(1'B0),
.s_axis_tlast(1'D0),
.s_axis_tid(1'B0),
.s_axis_tdest(1'B0),
.s_axis_tuser(4'B0),
.m_axis_tvalid(),
.m_axis_tready(1'D0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'D0),
.axi_aw_injectdbiterr(1'D0),
.axi_aw_prog_full_thresh(4'B0),
.axi_aw_prog_empty_thresh(4'B0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'D0),
.axi_w_injectdbiterr(1'D0),
.axi_w_prog_full_thresh(10'B0),
.axi_w_prog_empty_thresh(10'B0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectsbiterr(1'D0),
.axi_b_injectdbiterr(1'D0),
.axi_b_prog_full_thresh(4'B0),
.axi_b_prog_empty_thresh(4'B0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectsbiterr(1'D0),
.axi_ar_injectdbiterr(1'D0),
.axi_ar_prog_full_thresh(4'B0),
.axi_ar_prog_empty_thresh(4'B0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'D0),
.axi_r_injectdbiterr(1'D0),
.axi_r_prog_full_thresh(10'B0),
.axi_r_prog_empty_thresh(10'B0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectsbiterr(1'D0),
.axis_injectdbiterr(1'D0),
.axis_prog_full_thresh(10'B0),
.axis_prog_empty_thresh(10'B0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty()
);
endmodule
|
// $Id: c_clkgate.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// a generic clock gating module
//==============================================================================
module c_clkgate
(clk, active, clk_gated);
input clk;
input active;
output clk_gated;
wire clk_gated;
reg active_q;
always @(clk, active)
begin
if(clk == 0)
active_q <= active;
end
assign clk_gated = clk & active_q;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 14:03:06 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [31:0] Data_MX;
input [31:0] Data_MY;
input [1:0] round_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
Exp_module_Overflow_flag_A, Sgf_operation_Result_17_,
Sgf_operation_EVEN1_S_B_14_, n168, n170, n171, n172, n173, n174, n175,
n176, n177, n178, n179, n180, n181, n182, n183, n184, n185, n186,
n187, n188, n189, n190, n191, n192, n193, n194, n195, n196, n197,
n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, n208,
n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219,
n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, n230,
n231, n232, n233, n234, n235, n236, n238, n239, n240, n241, n242,
n243, n244, n245, n246, n247, n248, n249, n250, n251, n252, n253,
n254, n255, n256, n257, n258, n259, n260, n261, n262, n263, n264,
n265, n267, n268, n269, n270, n271, n272, n273, n274, n285, n286,
n287, n288, n289, n290, n291, n292, n293, n294, n295, n296, n297,
n298, n299, n300, n301, n302, n303, n304, n305, n306, n307, n308,
n309, n310, n311, n312, n313, n314, n316, n318, n319, n320, n321,
n322, n323, n325, n329, n330, n331, n332, n333, n334, n335, n336,
n337, n338, n339, n340, n341, n342, n343, n345, n346, n347, n348,
n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359,
n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, n370,
n371, n372, n373, n374, n375, n376, n377, n378, n379, n380, n381,
DP_OP_154J7_123_2038_n795, DP_OP_154J7_123_2038_n794,
DP_OP_154J7_123_2038_n793, DP_OP_154J7_123_2038_n792,
DP_OP_154J7_123_2038_n782, DP_OP_154J7_123_2038_n781,
DP_OP_154J7_123_2038_n779, DP_OP_154J7_123_2038_n778,
DP_OP_154J7_123_2038_n720, DP_OP_154J7_123_2038_n718,
DP_OP_154J7_123_2038_n715, DP_OP_154J7_123_2038_n699,
DP_OP_154J7_123_2038_n687, DP_OP_154J7_123_2038_n684,
DP_OP_154J7_123_2038_n636, DP_OP_154J7_123_2038_n635,
DP_OP_154J7_123_2038_n634, DP_OP_154J7_123_2038_n632,
DP_OP_154J7_123_2038_n628, DP_OP_154J7_123_2038_n357,
DP_OP_156J7_125_3370_n213, DP_OP_156J7_125_3370_n211,
DP_OP_156J7_125_3370_n210, DP_OP_156J7_125_3370_n207,
DP_OP_156J7_125_3370_n202, DP_OP_156J7_125_3370_n199,
DP_OP_156J7_125_3370_n198, DP_OP_156J7_125_3370_n196,
DP_OP_156J7_125_3370_n195, DP_OP_156J7_125_3370_n194,
DP_OP_156J7_125_3370_n193, DP_OP_156J7_125_3370_n192,
DP_OP_156J7_125_3370_n189, DP_OP_156J7_125_3370_n185,
DP_OP_156J7_125_3370_n99, DP_OP_156J7_125_3370_n93,
DP_OP_156J7_125_3370_n88, DP_OP_156J7_125_3370_n87,
DP_OP_156J7_125_3370_n84, DP_OP_156J7_125_3370_n83,
DP_OP_156J7_125_3370_n81, DP_OP_156J7_125_3370_n75,
DP_OP_156J7_125_3370_n73, DP_OP_156J7_125_3370_n70,
DP_OP_156J7_125_3370_n69, DP_OP_156J7_125_3370_n61,
DP_OP_156J7_125_3370_n13, DP_OP_156J7_125_3370_n12,
DP_OP_156J7_125_3370_n9, DP_OP_156J7_125_3370_n3,
DP_OP_155J7_124_2038_n803, DP_OP_155J7_124_2038_n802,
DP_OP_155J7_124_2038_n801, DP_OP_155J7_124_2038_n798,
DP_OP_155J7_124_2038_n796, DP_OP_155J7_124_2038_n794,
DP_OP_155J7_124_2038_n793, DP_OP_155J7_124_2038_n791,
DP_OP_155J7_124_2038_n789, DP_OP_155J7_124_2038_n788,
DP_OP_155J7_124_2038_n783, DP_OP_155J7_124_2038_n728,
DP_OP_155J7_124_2038_n725, DP_OP_155J7_124_2038_n388,
DP_OP_36J7_126_4699_n22, DP_OP_36J7_126_4699_n21,
DP_OP_36J7_126_4699_n20, DP_OP_36J7_126_4699_n19,
DP_OP_36J7_126_4699_n18, DP_OP_36J7_126_4699_n17,
DP_OP_36J7_126_4699_n16, DP_OP_36J7_126_4699_n15,
DP_OP_36J7_126_4699_n9, DP_OP_36J7_126_4699_n8,
DP_OP_36J7_126_4699_n7, DP_OP_36J7_126_4699_n6,
DP_OP_36J7_126_4699_n5, DP_OP_36J7_126_4699_n4,
DP_OP_36J7_126_4699_n3, DP_OP_36J7_126_4699_n2,
DP_OP_36J7_126_4699_n1, add_x_19_n293, add_x_19_n284, add_x_19_n282,
add_x_19_n279, add_x_19_n276, add_x_19_n275, add_x_19_n273,
add_x_19_n270, add_x_19_n269, add_x_19_n252, add_x_19_n251,
add_x_19_n244, add_x_19_n243, add_x_19_n242, add_x_19_n234,
add_x_19_n233, add_x_19_n229, add_x_19_n228, add_x_19_n227,
add_x_19_n226, add_x_19_n222, add_x_19_n220, add_x_19_n106,
add_x_19_n96, add_x_19_n94, add_x_19_n85, add_x_19_n59, add_x_19_n57,
add_x_19_n51, add_x_19_n47, add_x_19_n39, add_x_19_n26, add_x_19_n25,
add_x_19_n24, add_x_19_n23, add_x_19_n22, add_x_19_n21, add_x_19_n20,
add_x_19_n19, DP_OP_153J7_122_5442_n1508, DP_OP_153J7_122_5442_n1495,
DP_OP_153J7_122_5442_n1475, DP_OP_153J7_122_5442_n1474,
DP_OP_153J7_122_5442_n1470, DP_OP_153J7_122_5442_n1464,
DP_OP_153J7_122_5442_n1459, DP_OP_153J7_122_5442_n1205,
DP_OP_153J7_122_5442_n1201, DP_OP_153J7_122_5442_n1193,
DP_OP_153J7_122_5442_n1192, DP_OP_153J7_122_5442_n1182,
DP_OP_153J7_122_5442_n1181, DP_OP_153J7_122_5442_n1173,
DP_OP_153J7_122_5442_n1148, DP_OP_153J7_122_5442_n1127,
DP_OP_153J7_122_5442_n1120, DP_OP_153J7_122_5442_n1118,
DP_OP_153J7_122_5442_n1117, DP_OP_153J7_122_5442_n1114,
DP_OP_153J7_122_5442_n1113, DP_OP_153J7_122_5442_n1103,
DP_OP_153J7_122_5442_n1102, DP_OP_153J7_122_5442_n1097,
DP_OP_153J7_122_5442_n1096, DP_OP_153J7_122_5442_n1061,
DP_OP_153J7_122_5442_n829, DP_OP_153J7_122_5442_n788,
DP_OP_153J7_122_5442_n778, DP_OP_153J7_122_5442_n451, n391, n392,
n393, n395, n396, n397, n398, n399, n400, n401, n402, n403, n404,
n405, n406, n407, n408, n409, n410, n411, n412, n413, n414, n415,
n416, n417, n418, n419, n420, n421, n422, n423, n424, n425, n426,
n427, n428, n429, n430, n431, n432, n433, n434, n435, n436, n437,
n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, n448,
n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459,
n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470,
n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481,
n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492,
n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, n503,
n504, n505, n506, n507, n508, n509, n510, n511, n512, n513, n514,
n515, n516, n517, n518, n519, n520, n521, n522, n523, n524, n525,
n526, n527, n528, n529, n530, n531, n532, n533, n534, n535, n536,
n537, n538, n539, n540, n541, n542, n543, n544, n545, n546, n547,
n548, n549, n550, n551, n552, n553, n554, n555, n556, n557, n558,
n559, n560, n561, n562, n563, n564, n565, n566, n567, n568, n569,
n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, n580,
n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591,
n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, n602,
n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, n613,
n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, n624,
n625, n626, n627, n628, n629, n630, n631, n632, n633, n634, n635,
n636, n637, n638, n639, n640, n641, n642, n643, n644, n645, n646,
n647, n648, n649, n650, n651, n652, n653, n654, n655, n656, n657,
n658, n659, n660, n661, n662, n663, n664, n665, n666, n667, n668,
n669, n670, n671, n672, n673, n674, n675, n676, n677, n678, n679,
n680, n681, n682, n683, n684, n685, n686, n687, n688, n689, n690,
n691, n692, n693, n694, n695, n696, n697, n698, n699, n700, n701,
n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, n712,
n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723,
n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734,
n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, n745,
n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756,
n757, n758, n759, n760, n761, n762, n763, n764, n765, n766, n767,
n768, n769, n770, n771, n772, n773, n774, n775, n776, n777, n778,
n779, n780, n781, n782, n783, n784, n785, n786, n787, n788, n789,
n790, n791, n792, n793, n794, n795, n796, n797, n798, n799, n800,
n801, n802, n803, n804, n805, n806, n807, n808, n809, n810, n811,
n812, n813, n814, n815, n816, n817, n818, n819, n820, n821, n822,
n823, n824, n825, n826, n827, n828, n829, n830, n831, n832, n833,
n834, n835, n836, n837, n838, n839, n840, n841, n842, n843, n844,
n845, n846, n847, n848, n849, n850, n851, n852, n853, n854, n855,
n856, n857, n858, n859, n860, n861, n862, n863, n864, n865, n866,
n867, n868, n869, n870, n871, n872, n873, n874, n875, n876, n877,
n878, n879, n880, n881, n882, n883, n884, n885, n886, n887, n888,
n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, n899,
n900, n901, n902, n903, n904, n905, n906, n907, n908, n909, n910,
n911, n912, n913, n914, n915, n916, n917, n918, n919, n920, n921,
n922, n923, n924, n925, n926, n927, n928, n929, n930, n931, n932,
n933, n934, n935, n936, n937, n938, n939, n940, n941, n942, n943,
n944, n945, n946, n947, n948, n949, n950, n951, n952, n953, n954,
n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, n965,
n966, n967, n968, n969, n970, n971, n972, n973, n974, n975, n976,
n977, n978, n979, n980, n981, n982, n983, n984, n985, n986, n987,
n988, n989, n990, n991, n992, n993, n994, n995, n996, n997, n998,
n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008,
n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018,
n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028,
n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038,
n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048,
n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058,
n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068,
n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078,
n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088,
n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098,
n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108,
n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118,
n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128,
n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138,
n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148,
n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158,
n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168,
n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178,
n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188,
n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198,
n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208,
n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218,
n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228,
n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238,
n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248,
n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258,
n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268,
n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278,
n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288,
n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298,
n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308,
n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318,
n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328,
n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338,
n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348,
n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358,
n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368,
n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378,
n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388,
n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398,
n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408,
n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418,
n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428,
n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438,
n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448,
n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458,
n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468,
n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478,
n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488,
n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498,
n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508,
n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518,
n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528,
n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538,
n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548,
n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558,
n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568,
n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578,
n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588,
n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598,
n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608,
n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618,
n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628,
n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638,
n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648,
n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658,
n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668,
n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678,
n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688,
n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698,
n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708,
n1709, n1710, n1711, n1712, n1713, n1714, n1716, n1717, n1718, n1719,
n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729,
n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739,
n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749,
n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1760,
n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770,
n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780,
n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790,
n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800,
n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810,
n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820,
n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830,
n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840,
n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850,
n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860,
n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870,
n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880,
n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890,
n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900,
n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910,
n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920,
n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930,
n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940,
n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950,
n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960,
n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970,
n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980,
n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990,
n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000,
n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010,
n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020,
n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030,
n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040,
n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050,
n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060,
n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070,
n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080,
n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090,
n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100,
n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110,
n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120,
n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130,
n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140,
n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150,
n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160,
n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170,
n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180,
n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190,
n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200,
n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210,
n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220,
n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230,
n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240,
n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250,
n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260,
n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270,
n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280,
n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290,
n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300,
n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310,
n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320,
n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330,
n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340,
n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350,
n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360,
n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370,
n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380,
n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390,
n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400,
n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410,
n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420,
n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430,
n2431, n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440,
n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450,
n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460,
n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470,
n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480,
n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490,
n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500,
n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510,
n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520,
n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530,
n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540,
n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550,
n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560,
n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570,
n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580,
n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590,
n2591, n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600,
n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610,
n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620,
n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630,
n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640,
n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650,
n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660,
n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670,
n2671, n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680,
n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690,
n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700,
n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710,
n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720,
n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730,
n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740,
n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750,
n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760,
n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770,
n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780,
n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790,
n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800,
n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810,
n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820,
n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830,
n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840,
n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850,
n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860,
n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870,
n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880,
n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890,
n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900,
n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910,
n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920,
n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930,
n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940,
n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950,
n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960,
n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970,
n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980,
n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990,
n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000,
n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010,
n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020,
n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030,
n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040,
n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050,
n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060,
n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070,
n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080,
n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090,
n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100,
n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110,
n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120,
n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130,
n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140,
n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150,
n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160,
n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170,
n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180,
n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190,
n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200,
n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210,
n3211, n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220,
n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230,
n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240,
n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250,
n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260,
n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270,
n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280,
n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290,
n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300,
n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310,
n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320,
n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330,
n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340,
n3341, n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350,
n3351, n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360,
n3361, n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370,
n3371, n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380,
n3381, n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390,
n3391, n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400,
n3401, n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410,
n3411, n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420,
n3421, n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430,
n3431, n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440,
n3441, n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450,
n3451, n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460,
n3461, n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470,
n3471, n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480,
n3481, n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490,
n3491, n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500,
n3501, n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510,
n3511, n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520,
n3521, n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530,
n3531, n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540,
n3541, n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550,
n3551, n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560,
n3561, n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570,
n3571, n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580,
n3581, n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590,
n3591, n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600,
n3601, n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610,
n3611, n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620,
n3621, n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630,
n3631, n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640,
n3641, n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650,
n3651, n3652, n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660,
n3661, n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670,
n3671, n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680,
n3681, n3682, n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690,
n3691, n3692, n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700,
n3701, n3702, n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710,
n3711, n3712, n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720,
n3721, n3722, n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730,
n3731, n3732, n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740,
n3741, n3742, n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750,
n3751, n3752, n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760,
n3761, n3762, n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770,
n3771, n3772, n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780,
n3781, n3782, n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790,
n3791, n3792, n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800,
n3801, n3802, n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810,
n3811, n3812, n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820,
n3821, n3822, n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830,
n3831, n3832, n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840,
n3841, n3842, n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850,
n3851, n3852, n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860,
n3861, n3862, n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870,
n3871, n3872, n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880,
n3881, n3882, n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890,
n3891, n3892, n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900,
n3901, n3902, n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910,
n3911, n3912, n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920,
n3921, n3922, n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930,
n3931, n3932, n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940,
n3941, n3942, n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950,
n3951, n3952, n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960,
n3961, n3962, n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970,
n3971, n3972, n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980,
n3981, n3982, n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990,
n3991, n3992, n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000,
n4001, n4002, n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010,
n4011, n4012, n4013, n4014, n4015, n4016, n4017, n4018, n4019, n4020,
n4021, n4022, n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030,
n4031, n4032, n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040,
n4041, n4042, n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050,
n4051, n4052, n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060,
n4061, n4062, n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070,
n4071, n4072, n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080,
n4081, n4082, n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090,
n4091, n4092, n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100,
n4101, n4102, n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110,
n4111, n4112, n4113, n4114, n4115, n4116, n4117, n4118, n4119, n4120,
n4121, n4122, n4123, n4124, n4125, n4127, n4128, n4129, n4130, n4131,
n4132, n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140, n4141,
n4142, n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150, n4151,
n4152, n4153, n4154, n4155, n4156, n4157, n4158, n4159, n4160, n4161,
n4162, n4163, n4164, n4165, n4166, n4167, n4168, n4169, n4170, n4171,
n4172, n4173, n4174, n4175, n4176, n4177, n4178, n4179, n4180, n4181,
n4182, n4183, n4184, n4185, n4186, n4187, n4188, n4189, n4190, n4191,
n4192, n4193, n4194, n4195, n4196, n4197, n4198, n4199, n4200, n4201,
n4202, n4203, n4204, n4205, n4206, n4207, n4208, n4209, n4210, n4211,
n4212, n4213, n4214, n4215, n4216, n4217, n4218, n4219, n4220, n4221,
n4222, n4223, n4224, n4225, n4226, n4227, n4228, n4229, n4230, n4231,
n4232, n4233, n4234, n4235, n4236, n4237, n4238, n4239, n4240, n4241,
n4242, n4243;
wire [15:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [31:4] Op_MX;
wire [31:2] Op_MY;
wire [8:0] exp_oper_result;
wire [8:0] S_Oper_A_exp;
wire [23:0] Add_result;
wire [23:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [8:0] Exp_module_Data_S;
wire [22:2] Sgf_operation_EVEN1_Q_left;
wire [16:15] Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B;
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n381), .CK(clk), .RN(
n4216), .Q(Op_MY[31]) );
DFFRXLTS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n311), .CK(clk),
.RN(n4216), .Q(zero_flag), .QN(n4145) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n379), .CK(clk), .RN(n456), .Q(
FS_Module_state_reg[0]), .QN(n4129) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n367), .CK(clk), .RN(
n4227), .QN(n437) );
DFFRX4TS R_189 ( .D(n366), .CK(clk), .RN(n463), .Q(Op_MX[22]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n365), .CK(clk), .RN(
n462), .Q(Op_MX[21]), .QN(n429) );
DFFRX4TS R_324 ( .D(n364), .CK(clk), .RN(n463), .Q(Op_MX[20]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n363), .CK(clk), .RN(
n462), .Q(Op_MX[19]), .QN(n522) );
DFFRX4TS R_487 ( .D(n362), .CK(clk), .RN(n463), .Q(Op_MX[18]), .QN(n520) );
DFFRX4TS R_179 ( .D(n360), .CK(clk), .RN(n461), .Q(Op_MX[16]), .QN(n4172) );
DFFRX4TS R_282 ( .D(n356), .CK(clk), .RN(n4227), .Q(Op_MX[12]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n355), .CK(clk), .RN(
n4148), .Q(Op_MX[11]), .QN(n521) );
DFFRX4TS R_321 ( .D(n354), .CK(clk), .RN(n4148), .Q(Op_MX[10]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n353), .CK(clk), .RN(
n4148), .Q(Op_MX[9]), .QN(n517) );
DFFRX4TS R_315 ( .D(n352), .CK(clk), .RN(n4227), .Q(Op_MX[8]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n351), .CK(clk), .RN(
n4149), .Q(Op_MX[7]), .QN(n435) );
DFFRX4TS R_848 ( .D(n349), .CK(clk), .RN(n4226), .Q(Op_MX[5]), .QN(n428) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n343), .CK(clk), .RN(
n4217), .Q(Op_MX[31]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n334), .CK(clk), .RN(
n4220), .Q(Op_MY[22]), .QN(n4182) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n333), .CK(clk), .RN(
n4224), .Q(Op_MY[21]), .QN(n447) );
DFFRX4TS R_390 ( .D(n331), .CK(clk), .RN(n4150), .Q(Op_MY[19]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n323), .CK(clk), .RN(
n3698), .Q(Op_MY[11]), .QN(n506) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n322), .CK(clk), .RN(
n4226), .Q(Op_MY[10]), .QN(n4184) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n321), .CK(clk), .RN(
n4151), .Q(Op_MY[9]), .QN(n419) );
DFFRX4TS R_334 ( .D(n320), .CK(clk), .RN(n4149), .Q(Op_MY[8]), .QN(n418) );
DFFRX4TS R_461 ( .D(n318), .CK(clk), .RN(n4227), .Q(Op_MY[6]), .QN(n422) );
DFFRX4TS R_328 ( .D(n316), .CK(clk), .RN(n4223), .Q(Op_MY[4]), .QN(n417) );
DFFRX4TS R_175 ( .D(n314), .CK(clk), .RN(n4226), .Q(Op_MY[2]), .QN(n423) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_16_ ( .D(n254), .CK(clk), .RN(
n455), .QN(n439) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n249), .CK(clk), .RN(
n455), .QN(n438) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n239), .CK(clk), .RN(
n486), .Q(P_Sgf[1]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n238), .CK(clk), .RN(
n454), .Q(P_Sgf[0]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n310), .CK(clk),
.RN(n4224), .Q(Sgf_normalized_result[23]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n211), .CK(clk),
.RN(n4221), .Q(Sgf_normalized_result[9]), .QN(n4133) );
DFFSX2TS R_2 ( .D(n4242), .CK(clk), .SN(n455), .Q(n4207) );
DFFRX4TS R_268 ( .D(n325), .CK(clk), .RN(n4150), .Q(
DP_OP_154J7_123_2038_n779) );
DFFRX4TS R_277 ( .D(DP_OP_153J7_122_5442_n1470), .CK(clk), .RN(n4150), .Q(
DP_OP_155J7_124_2038_n791), .QN(n421) );
DFFRX4TS R_276 ( .D(DP_OP_153J7_122_5442_n1459), .CK(clk), .RN(n4150), .Q(
DP_OP_154J7_123_2038_n781), .QN(n4178) );
DFFRX4TS R_298 ( .D(n312), .CK(clk), .RN(n3980), .Q(
DP_OP_155J7_124_2038_n788), .QN(n396) );
DFFRX4TS R_309 ( .D(n345), .CK(clk), .RN(n4217), .Q(
DP_OP_155J7_124_2038_n801), .QN(n431) );
DFFRX4TS R_308 ( .D(n357), .CK(clk), .RN(n4223), .Q(
DP_OP_154J7_123_2038_n792) );
DFFRX4TS R_320 ( .D(n346), .CK(clk), .RN(n4219), .Q(
DP_OP_153J7_122_5442_n1508) );
DFFRX4TS R_356 ( .D(n361), .CK(clk), .RN(n4224), .Q(n4209), .QN(n507) );
DFFRX4TS R_442 ( .D(n329), .CK(clk), .RN(n4223), .Q(
DP_OP_154J7_123_2038_n357) );
DFFRX4TS R_441 ( .D(n4137), .CK(clk), .RN(n4226), .Q(
DP_OP_155J7_124_2038_n793), .QN(n420) );
DFFRX4TS R_458 ( .D(n358), .CK(clk), .RN(n4151), .Q(
DP_OP_153J7_122_5442_n1495) );
DFFRX4TS R_475 ( .D(n347), .CK(clk), .RN(n4217), .Q(
DP_OP_155J7_124_2038_n803) );
DFFRX4TS R_492 ( .D(n350), .CK(clk), .RN(n461), .Q(DP_OP_155J7_124_2038_n794), .QN(n398) );
DFFRX4TS R_595 ( .D(n330), .CK(clk), .RN(n4150), .Q(n4181) );
DFFSX2TS R_864 ( .D(n4215), .CK(clk), .SN(n486), .Q(n4155) );
DFFSX2TS R_867 ( .D(n4213), .CK(clk), .SN(n455), .Q(n4154) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n168),
.CK(clk), .RN(n488), .Q(final_result_ieee[31]), .QN(n4146) );
DFFRXLTS R_297 ( .D(DP_OP_154J7_123_2038_n778), .CK(clk), .RN(n488), .Q(
n4187), .QN(n4162) );
DFFRXLTS R_184 ( .D(n313), .CK(clk), .RN(n4217), .Q(n4144), .QN(n4212) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n209), .CK(clk),
.RN(n4222), .Q(Sgf_normalized_result[7]), .QN(n4143) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n208), .CK(clk),
.RN(n4222), .Q(Sgf_normalized_result[6]), .QN(n4140) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n206), .CK(clk),
.RN(n4222), .Q(Sgf_normalized_result[4]), .QN(n4139) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n207), .CK(clk),
.RN(n4222), .Q(Sgf_normalized_result[5]), .QN(n4134) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n205), .CK(clk),
.RN(n4222), .Q(Sgf_normalized_result[3]), .QN(n4132) );
DFFRX2TS Sel_A_Q_reg_0_ ( .D(n376), .CK(clk), .RN(n4216), .Q(FSM_selector_A),
.QN(n4141) );
DFFRX1TS Sel_B_Q_reg_0_ ( .D(n236), .CK(clk), .RN(n3978), .Q(
FSM_selector_B[0]), .QN(n4127) );
DFFRX2TS FS_Module_state_reg_reg_1_ ( .D(n378), .CK(clk), .RN(n4228), .Q(
FS_Module_state_reg[1]), .QN(n4135) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n200),
.CK(clk), .RN(n4219), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n199),
.CK(clk), .RN(n4226), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n198),
.CK(clk), .RN(n4151), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n197),
.CK(clk), .RN(n4223), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n196),
.CK(clk), .RN(n4224), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n195),
.CK(clk), .RN(n4219), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n194),
.CK(clk), .RN(n4149), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n193),
.CK(clk), .RN(n4227), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n192),
.CK(clk), .RN(n4149), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n191),
.CK(clk), .RN(n4227), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n190),
.CK(clk), .RN(n4219), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n189),
.CK(clk), .RN(n4226), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n188),
.CK(clk), .RN(n4151), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n187),
.CK(clk), .RN(n4223), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n186),
.CK(clk), .RN(n4224), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n185),
.CK(clk), .RN(n4219), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n184),
.CK(clk), .RN(n4226), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n183),
.CK(clk), .RN(n4151), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n182),
.CK(clk), .RN(n4223), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n181),
.CK(clk), .RN(n4224), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n180),
.CK(clk), .RN(n4225), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n179),
.CK(clk), .RN(n4225), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n178),
.CK(clk), .RN(n4225), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n177),
.CK(clk), .RN(n4225), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n176),
.CK(clk), .RN(n4225), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n175),
.CK(clk), .RN(n4225), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n174),
.CK(clk), .RN(n4225), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n173),
.CK(clk), .RN(n4225), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n172),
.CK(clk), .RN(n4225), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n171),
.CK(clk), .RN(n4225), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n170),
.CK(clk), .RN(n4224), .Q(final_result_ieee[30]) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n225), .CK(clk), .RN(n3980), .Q(
Exp_module_Overflow_flag_A) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n226), .CK(clk), .RN(n488),
.Q(exp_oper_result[8]) );
DFFSX4TS DP_OP_154J7_123_2038_R_597 ( .D(n4125), .CK(clk), .SN(n4151), .Q(
DP_OP_154J7_123_2038_n715) );
DFFRX4TS DP_OP_154J7_123_2038_R_598 ( .D(n332), .CK(clk), .RN(n4149), .Q(
DP_OP_154J7_123_2038_n684) );
DFFSX4TS DP_OP_154J7_123_2038_R_459 ( .D(n4124), .CK(clk), .SN(n4148), .Q(
DP_OP_154J7_123_2038_n636) );
DFFSX4TS DP_OP_154J7_123_2038_R_454 ( .D(n4123), .CK(clk), .SN(n462), .Q(
DP_OP_154J7_123_2038_n635) );
DFFSX4TS DP_OP_154J7_123_2038_R_325 ( .D(n4122), .CK(clk), .SN(n463), .Q(
DP_OP_154J7_123_2038_n720) );
DFFSX4TS DP_OP_154J7_123_2038_R_314 ( .D(n4121), .CK(clk), .SN(n4150), .Q(
DP_OP_154J7_123_2038_n628) );
DFFSX4TS DP_OP_154J7_123_2038_R_294 ( .D(n4120), .CK(clk), .SN(n4150), .Q(
DP_OP_154J7_123_2038_n632) );
DFFSX4TS DP_OP_154J7_123_2038_R_190 ( .D(n4119), .CK(clk), .SN(n463), .Q(
DP_OP_154J7_123_2038_n718) );
DFFSX4TS DP_OP_154J7_123_2038_R_180 ( .D(n4118), .CK(clk), .SN(n462), .Q(
DP_OP_154J7_123_2038_n634) );
DFFSX2TS DP_OP_156J7_125_3370_R_1013 ( .D(DP_OP_156J7_125_3370_n93), .CK(clk), .SN(n4153), .Q(n4109) );
DFFSX2TS DP_OP_156J7_125_3370_R_1001 ( .D(DP_OP_156J7_125_3370_n88), .CK(clk), .SN(n4065), .Q(n4105) );
DFFSX2TS DP_OP_156J7_125_3370_R_1000 ( .D(DP_OP_156J7_125_3370_n99), .CK(clk), .SN(n4228), .Q(n4104) );
DFFSX1TS DP_OP_156J7_125_3370_R_656_RW_2 ( .D(DP_OP_156J7_125_3370_n9), .CK(
clk), .SN(n4115), .Q(n4075) );
DFFRXLTS DP_OP_156J7_125_3370_R_949_RW_0 ( .D(DP_OP_156J7_125_3370_n194),
.CK(clk), .RN(n4116), .Q(n4087) );
DFFRXLTS DP_OP_156J7_125_3370_R_964_RW_0 ( .D(DP_OP_156J7_125_3370_n69),
.CK(clk), .RN(n4116), .Q(n4093) );
DFFSX4TS DP_OP_155J7_124_2038_R_322 ( .D(n4073), .CK(clk), .SN(n4148), .Q(
DP_OP_155J7_124_2038_n728) );
DFFSX2TS DP_OP_155J7_124_2038_R_317 ( .D(n4072), .CK(clk), .SN(n4148), .Q(
DP_OP_155J7_124_2038_n388) );
DFFRX4TS DP_OP_155J7_124_2038_R_318 ( .D(n352), .CK(clk), .RN(n4148), .Q(
DP_OP_155J7_124_2038_n796), .QN(n427) );
DFFRX4TS DP_OP_155J7_124_2038_R_319 ( .D(n346), .CK(clk), .RN(n4148), .Q(
DP_OP_155J7_124_2038_n802), .QN(n397) );
DFFSX4TS DP_OP_155J7_124_2038_R_289 ( .D(n4071), .CK(clk), .SN(n4223), .Q(
DP_OP_155J7_124_2038_n725) );
CMPR32X2TS DP_OP_36J7_126_4699_U9 ( .A(DP_OP_36J7_126_4699_n21), .B(
S_Oper_A_exp[1]), .C(DP_OP_36J7_126_4699_n9), .CO(
DP_OP_36J7_126_4699_n8), .S(Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_36J7_126_4699_U7 ( .A(DP_OP_36J7_126_4699_n19), .B(
S_Oper_A_exp[3]), .C(DP_OP_36J7_126_4699_n7), .CO(
DP_OP_36J7_126_4699_n6), .S(Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_36J7_126_4699_U6 ( .A(DP_OP_36J7_126_4699_n18), .B(
S_Oper_A_exp[4]), .C(DP_OP_36J7_126_4699_n6), .CO(
DP_OP_36J7_126_4699_n5), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_36J7_126_4699_U5 ( .A(DP_OP_36J7_126_4699_n17), .B(
S_Oper_A_exp[5]), .C(DP_OP_36J7_126_4699_n5), .CO(
DP_OP_36J7_126_4699_n4), .S(Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_36J7_126_4699_U4 ( .A(DP_OP_36J7_126_4699_n16), .B(
S_Oper_A_exp[6]), .C(DP_OP_36J7_126_4699_n4), .CO(
DP_OP_36J7_126_4699_n3), .S(Exp_module_Data_S[6]) );
DFFSX1TS add_x_19_R_608 ( .D(add_x_19_n222), .CK(clk), .SN(n4069), .QN(n4058) );
DFFSX4TS DP_OP_153J7_122_5442_R_904 ( .D(n3965), .CK(clk), .SN(n3981), .Q(
n3946), .QN(n3991) );
DFFSX2TS DP_OP_153J7_122_5442_R_902 ( .D(n3988), .CK(clk), .SN(n3978), .Q(
DP_OP_153J7_122_5442_n1097) );
DFFSX2TS DP_OP_153J7_122_5442_R_858 ( .D(n3972), .CK(clk), .SN(n4226), .Q(
DP_OP_153J7_122_5442_n1193) );
DFFRX2TS DP_OP_153J7_122_5442_R_484 ( .D(n331), .CK(clk), .RN(n3979), .Q(
DP_OP_153J7_122_5442_n778) );
DFFRX2TS DP_OP_153J7_122_5442_R_483 ( .D(n319), .CK(clk), .RN(n3979), .Q(
DP_OP_153J7_122_5442_n1474) );
DFFRX2TS DP_OP_153J7_122_5442_R_482 ( .D(n3962), .CK(clk), .RN(n3979), .Q(
DP_OP_153J7_122_5442_n451) );
DFFSX4TS DP_OP_153J7_122_5442_R_476 ( .D(n3960), .CK(clk), .SN(n4219), .Q(
DP_OP_153J7_122_5442_n1192), .QN(n3993) );
DFFSX4TS DP_OP_153J7_122_5442_R_900 ( .D(n3959), .CK(clk), .SN(n3979), .Q(
DP_OP_153J7_122_5442_n1096), .QN(n3983) );
DFFSX4TS DP_OP_153J7_122_5442_R_585 ( .D(n3958), .CK(clk), .SN(n3981), .Q(
DP_OP_153J7_122_5442_n1117), .QN(n3982) );
DFFSX4TS DP_OP_153J7_122_5442_R_897 ( .D(n3954), .CK(clk), .SN(n3981), .Q(
DP_OP_153J7_122_5442_n1102) );
DFFSX4TS DP_OP_153J7_122_5442_R_584 ( .D(n3953), .CK(clk), .SN(n3981), .Q(
DP_OP_153J7_122_5442_n1120) );
DFFSX4TS DP_OP_153J7_122_5442_R_586 ( .D(n3949), .CK(clk), .SN(n3981), .Q(
DP_OP_153J7_122_5442_n1118), .QN(n502) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n235), .CK(clk), .RN(n3978), .Q(
FSM_selector_B[1]), .QN(n4130) );
DFFRX4TS DP_OP_153J7_122_5442_R_994 ( .D(n3974), .CK(clk), .RN(n3979), .Q(
n3951) );
DFFSX2TS DP_OP_153J7_122_5442_R_852 ( .D(n3967), .CK(clk), .SN(n4147), .QN(
n3989) );
DFFSX2TS DP_OP_153J7_122_5442_R_489 ( .D(n3963), .CK(clk), .SN(n4223), .QN(
n3994) );
DFFRXLTS R_316 ( .D(n346), .CK(clk), .RN(n4217), .QN(n4180) );
DFFRXLTS R_835 ( .D(n255), .CK(clk), .RN(n445), .Q(n4157) );
DFFSX1TS add_x_19_R_804 ( .D(add_x_19_n227), .CK(clk), .SN(n4069), .Q(n4038)
);
DFFSX1TS add_x_19_R_962 ( .D(add_x_19_n229), .CK(clk), .SN(n4065), .Q(n4059)
);
DFFRXLTS DP_OP_156J7_125_3370_R_1014 ( .D(DP_OP_156J7_125_3370_n13), .CK(clk), .RN(n4116), .Q(n4110) );
DFFRXLTS add_x_19_R_992 ( .D(add_x_19_n220), .CK(clk), .RN(n4068), .Q(n4060)
);
DFFRXLTS DP_OP_156J7_125_3370_R_990_RW_0 ( .D(DP_OP_156J7_125_3370_n81),
.CK(clk), .RN(n4152), .Q(n4100) );
DFFRXLTS DP_OP_156J7_125_3370_R_1016 ( .D(DP_OP_156J7_125_3370_n198), .CK(
clk), .RN(n4116), .Q(n4111) );
DFFRXLTS DP_OP_156J7_125_3370_R_987_RW_0 ( .D(DP_OP_156J7_125_3370_n75),
.CK(clk), .RN(n4152), .Q(n4098) );
DFFRXLTS add_x_19_R_619_RW_1 ( .D(add_x_19_n234), .CK(clk), .RN(n4068), .Q(
n4016) );
DFFRXLTS add_x_19_R_659_RW_2 ( .D(add_x_19_n229), .CK(clk), .RN(n4068), .Q(
n4026) );
DFFRXLTS DP_OP_156J7_125_3370_R_552_RW_1 ( .D(DP_OP_156J7_125_3370_n3), .CK(
clk), .RN(n4116), .Q(n4074) );
DFFRXLTS R_416 ( .D(n263), .CK(clk), .RN(n457), .Q(n4167) );
DFFRXLTS R_613 ( .D(n256), .CK(clk), .RN(n454), .Q(n4160) );
DFFSX1TS DP_OP_156J7_125_3370_R_1019 ( .D(DP_OP_156J7_125_3370_n195), .CK(
clk), .SN(n4115), .Q(n4112) );
DFFRXLTS DP_OP_156J7_125_3370_R_971 ( .D(DP_OP_156J7_125_3370_n199), .CK(clk), .RN(n4116), .Q(n4097) );
DFFSX1TS add_x_19_R_1002 ( .D(Sgf_operation_EVEN1_S_B_14_), .CK(clk), .SN(
n4065), .Q(n4061) );
DFFRXLTS add_x_19_R_641_RW_1 ( .D(add_x_19_n252), .CK(clk), .RN(n4068), .Q(
n4020) );
DFFRXLTS add_x_19_R_875 ( .D(add_x_19_n57), .CK(clk), .RN(n445), .Q(n4045)
);
DFFSX1TS add_x_19_R_714 ( .D(add_x_19_n293), .CK(clk), .SN(n4069), .Q(n4029)
);
DFFRXLTS add_x_19_R_41 ( .D(add_x_19_n51), .CK(clk), .RN(n4229), .Q(n3997)
);
DFFRX1TS DP_OP_153J7_122_5442_R_853 ( .D(n3968), .CK(clk), .RN(n3981), .Q(
n3948) );
DFFSX1TS DP_OP_153J7_122_5442_R_996 ( .D(n3977), .CK(clk), .SN(n3978), .QN(
n510) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n202), .CK(clk),
.RN(n4222), .Q(Sgf_normalized_result[0]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n204), .CK(clk),
.RN(n4222), .Q(Sgf_normalized_result[2]) );
DFFSHQX1TS R_847_IP ( .D(n4186), .CK(clk), .SN(n488), .Q(n3943) );
DFFSHQX2TS R_174_IP ( .D(n3942), .CK(clk), .SN(n489), .Q(n4179) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n201), .CK(clk), .RN(n4222),
.Q(underflow_flag) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n213), .CK(clk),
.RN(n4221), .Q(Sgf_normalized_result[11]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n215), .CK(clk),
.RN(n4221), .Q(Sgf_normalized_result[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n217), .CK(clk),
.RN(n4221), .Q(Sgf_normalized_result[15]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n219), .CK(clk),
.RN(n4221), .Q(Sgf_normalized_result[17]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n221), .CK(clk),
.RN(n4226), .Q(Sgf_normalized_result[19]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n223), .CK(clk),
.RN(n461), .Q(Sgf_normalized_result[21]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n214), .CK(clk),
.RN(n4221), .Q(Sgf_normalized_result[12]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n216), .CK(clk),
.RN(n4221), .Q(Sgf_normalized_result[14]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n218), .CK(clk),
.RN(n4221), .Q(Sgf_normalized_result[16]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n220), .CK(clk),
.RN(n4221), .Q(Sgf_normalized_result[18]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n222), .CK(clk),
.RN(n463), .Q(Sgf_normalized_result[20]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n224), .CK(clk),
.RN(n462), .Q(Sgf_normalized_result[22]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n371), .CK(clk), .RN(
n4216), .Q(Op_MX[27]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n307), .CK(clk), .RN(n4223),
.Q(Add_result[2]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n342), .CK(clk), .RN(
n4220), .Q(Op_MY[30]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n368), .CK(clk), .RN(
n4149), .Q(Op_MX[24]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n227), .CK(clk), .RN(n461),
.Q(exp_oper_result[7]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n228), .CK(clk), .RN(n463),
.Q(exp_oper_result[6]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n229), .CK(clk), .RN(n462),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n231), .CK(clk), .RN(n4150),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n232), .CK(clk), .RN(n4217),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n234), .CK(clk), .RN(n3980),
.Q(exp_oper_result[0]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n339), .CK(clk), .RN(
n4220), .Q(Op_MY[27]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n210), .CK(clk),
.RN(n4222), .Q(Sgf_normalized_result[8]), .QN(n4128) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n212), .CK(clk),
.RN(n4221), .Q(Sgf_normalized_result[10]), .QN(n4142) );
DFFSX1TS DP_OP_156J7_125_3370_R_823 ( .D(DP_OP_156J7_125_3370_n75), .CK(clk),
.SN(n4115), .Q(n4079) );
DFFRX1TS R_479 ( .D(n319), .CK(clk), .RN(n488), .Q(Op_MY[7]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n248), .CK(clk), .RN(
n454), .Q(P_Sgf[10]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_15_ ( .D(n253), .CK(clk), .RN(
n4228), .Q(P_Sgf[15]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n240), .CK(clk), .RN(
n456), .Q(P_Sgf[2]) );
DFFRX1TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n285), .CK(clk), .RN(
n4220), .Q(FSM_add_overflow_flag) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n309), .CK(clk), .RN(n4224),
.Q(Add_result[0]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n203), .CK(clk),
.RN(n4222), .Q(Sgf_normalized_result[1]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n369), .CK(clk), .RN(
n4216), .Q(Op_MX[25]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n370), .CK(clk), .RN(
n4216), .Q(Op_MX[26]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n287), .CK(clk), .RN(n4217),
.Q(Add_result[22]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n288), .CK(clk), .RN(n4217),
.Q(Add_result[21]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n289), .CK(clk), .RN(n4217),
.Q(Add_result[20]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n290), .CK(clk), .RN(n4217),
.Q(Add_result[19]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n291), .CK(clk), .RN(n4218),
.Q(Add_result[18]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n292), .CK(clk), .RN(n4218),
.Q(Add_result[17]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n293), .CK(clk), .RN(n4218),
.Q(Add_result[16]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n294), .CK(clk), .RN(n4218),
.Q(Add_result[15]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n295), .CK(clk), .RN(n4218),
.Q(Add_result[14]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n296), .CK(clk), .RN(n4218),
.Q(Add_result[13]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n297), .CK(clk), .RN(n4218),
.Q(Add_result[12]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n298), .CK(clk), .RN(n4218),
.Q(Add_result[11]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n299), .CK(clk), .RN(n4218),
.Q(Add_result[10]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n300), .CK(clk), .RN(n4218),
.Q(Add_result[9]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n301), .CK(clk), .RN(n4226),
.Q(Add_result[8]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n302), .CK(clk), .RN(n4149),
.Q(Add_result[7]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n303), .CK(clk), .RN(n4227),
.Q(Add_result[6]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n304), .CK(clk), .RN(n4219),
.Q(Add_result[5]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n305), .CK(clk), .RN(n4149),
.Q(Add_result[4]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n306), .CK(clk), .RN(n4227),
.Q(Add_result[3]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n308), .CK(clk), .RN(n4149),
.Q(Add_result[1]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n286), .CK(clk), .RN(n4227),
.Q(Add_result[23]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n233), .CK(clk), .RN(n3978),
.Q(exp_oper_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n230), .CK(clk), .RN(n3978),
.Q(exp_oper_result[4]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n341), .CK(clk), .RN(
n4220), .Q(Op_MY[29]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n337), .CK(clk), .RN(
n4220), .Q(Op_MY[25]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n338), .CK(clk), .RN(
n4220), .Q(Op_MY[26]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n340), .CK(clk), .RN(
n4220), .Q(Op_MY[28]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n336), .CK(clk), .RN(
n4220), .Q(Op_MY[24]) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n377), .CK(clk), .RN(n486), .Q(
FS_Module_state_reg[2]), .QN(n4131) );
DFFSX1TS DP_OP_156J7_125_3370_R_1007 ( .D(DP_OP_156J7_125_3370_n213), .CK(
clk), .SN(n457), .Q(n4108) );
DFFSX1TS DP_OP_156J7_125_3370_R_824_RW_1 ( .D(DP_OP_156J7_125_3370_n70),
.CK(clk), .SN(n457), .Q(n4080) );
DFFRXLTS DP_OP_156J7_125_3370_R_1005 ( .D(DP_OP_156J7_125_3370_n83), .CK(clk), .RN(n4152), .Q(n4106) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n251), .CK(clk), .RN(
n4230), .Q(P_Sgf[13]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n242), .CK(clk), .RN(
n456), .Q(P_Sgf[4]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n250), .CK(clk), .RN(
n4228), .Q(P_Sgf[12]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n241), .CK(clk), .RN(
n456), .Q(P_Sgf[3]) );
DFFRXLTS R_327 ( .D(DP_OP_154J7_123_2038_n782), .CK(clk), .RN(n488), .Q(
n4208), .QN(n4163) );
DFFRXLTS R_335 ( .D(n332), .CK(clk), .RN(n489), .QN(n4183) );
DFFRX1TS R_480 ( .D(n331), .CK(clk), .RN(n4151), .Q(n4211) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_14_ ( .D(n252), .CK(clk), .RN(
n487), .Q(P_Sgf[14]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n247), .CK(clk), .RN(
n456), .Q(P_Sgf[9]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n244), .CK(clk), .RN(
n444), .Q(P_Sgf[6]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n246), .CK(clk), .RN(
n444), .Q(P_Sgf[8]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n245), .CK(clk), .RN(
n444), .Q(P_Sgf[7]) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(n380), .CK(clk), .RN(n4229), .Q(
FS_Module_state_reg[3]), .QN(n4136) );
DFFSX1TS R_5 ( .D(n4233), .CK(clk), .SN(n486), .Q(n4206) );
DFFSX1TS R_8 ( .D(n4232), .CK(clk), .SN(n486), .Q(n4205) );
DFFSX1TS R_11 ( .D(n4234), .CK(clk), .SN(n487), .Q(n4204) );
DFFSX1TS R_14 ( .D(n4238), .CK(clk), .SN(n486), .Q(n4203) );
DFFSX1TS R_17 ( .D(n4237), .CK(clk), .SN(n487), .Q(n4202) );
DFFSX1TS R_20 ( .D(n4235), .CK(clk), .SN(n487), .Q(n4201) );
DFFSX1TS R_23 ( .D(n4240), .CK(clk), .SN(n456), .Q(n4200) );
DFFSX1TS R_26 ( .D(n4239), .CK(clk), .SN(n486), .Q(n4199) );
DFFSX1TS R_29 ( .D(n4236), .CK(clk), .SN(n486), .Q(n4198) );
DFFSX1TS R_32 ( .D(n4231), .CK(clk), .SN(n487), .Q(n4197) );
DFFRXLTS R_34 ( .D(n274), .CK(clk), .RN(n4153), .Q(n4196) );
DFFRXLTS R_61 ( .D(n273), .CK(clk), .RN(n4153), .Q(n4195) );
DFFRXLTS R_64 ( .D(n271), .CK(clk), .RN(n4153), .Q(n4194) );
DFFRXLTS R_67 ( .D(n272), .CK(clk), .RN(n455), .Q(n4193) );
DFFRXLTS R_70 ( .D(n270), .CK(clk), .RN(n4153), .Q(n4192) );
DFFSX1TS R_84 ( .D(n4241), .CK(clk), .SN(n444), .Q(n4191) );
DFFRXLTS R_119 ( .D(n267), .CK(clk), .RN(n4153), .Q(n4190) );
DFFRXLTS R_122 ( .D(n269), .CK(clk), .RN(n444), .Q(n4189) );
DFFRXLTS R_125 ( .D(n268), .CK(clk), .RN(n4230), .Q(n4188) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n335), .CK(clk), .RN(
n4220), .Q(Op_MY[23]), .QN(n4185) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n372), .CK(clk), .RN(
n4216), .Q(Op_MX[28]), .QN(n4177) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n373), .CK(clk), .RN(
n4216), .Q(Op_MX[29]), .QN(n4176) );
DFFRXLTS R_398 ( .D(n258), .CK(clk), .RN(n487), .Q(n4171) );
DFFRXLTS R_407 ( .D(n261), .CK(clk), .RN(n454), .Q(n4170) );
DFFRXLTS R_410 ( .D(n259), .CK(clk), .RN(n486), .Q(n4169) );
DFFRXLTS R_413 ( .D(n260), .CK(clk), .RN(n444), .Q(n4168) );
DFFRXLTS R_419 ( .D(n262), .CK(clk), .RN(n456), .Q(n4166) );
DFFRXLTS R_422 ( .D(n264), .CK(clk), .RN(n454), .Q(n4165) );
DFFRXLTS R_425 ( .D(n265), .CK(clk), .RN(n454), .Q(n4164) );
DFFRXLTS R_427 ( .D(n359), .CK(clk), .RN(n4227), .QN(n4173) );
DFFRXLTS R_474 ( .D(n359), .CK(clk), .RN(n4149), .Q(n4161) );
DFFRXLTS R_596 ( .D(n332), .CK(clk), .RN(n488), .Q(n4210) );
DFFRXLTS R_691 ( .D(n257), .CK(clk), .RN(n4230), .Q(n4159) );
DFFSX1TS R_834 ( .D(Sgf_operation_Result_17_), .CK(clk), .SN(n486), .Q(n4158) );
DFFSX1TS R_849 ( .D(n4156), .CK(clk), .SN(n4224), .Q(n4174) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n375), .CK(clk), .RN(n461), .Q(FSM_selector_C),
.QN(n4138) );
DFFRXLTS DP_OP_154J7_123_2038_R_455 ( .D(n359), .CK(clk), .RN(n462), .Q(
DP_OP_154J7_123_2038_n794) );
DFFRX1TS DP_OP_154J7_123_2038_R_191 ( .D(n366), .CK(clk), .RN(n461), .Q(
DP_OP_154J7_123_2038_n687) );
DFFRXLTS DP_OP_154J7_123_2038_R_181 ( .D(n360), .CK(clk), .RN(n461), .Q(
DP_OP_154J7_123_2038_n795) );
DFFSX1TS DP_OP_156J7_125_3370_R_1020 ( .D(DP_OP_156J7_125_3370_n61), .CK(clk), .SN(n4115), .Q(n4113), .QN(n4117) );
DFFSX1TS DP_OP_156J7_125_3370_R_999 ( .D(DP_OP_156J7_125_3370_n87), .CK(clk),
.SN(n4114), .Q(n4103) );
DFFSX1TS DP_OP_156J7_125_3370_R_998 ( .D(DP_OP_156J7_125_3370_n210), .CK(clk), .SN(n4114), .Q(n4102) );
DFFSX1TS DP_OP_156J7_125_3370_R_997 ( .D(DP_OP_156J7_125_3370_n207), .CK(clk), .SN(n4114), .Q(n4101) );
DFFSX1TS DP_OP_156J7_125_3370_R_989 ( .D(DP_OP_156J7_125_3370_n84), .CK(clk),
.SN(n4114), .Q(n4099) );
DFFRXLTS DP_OP_156J7_125_3370_R_970 ( .D(DP_OP_156J7_125_3370_n202), .CK(clk), .RN(n4115), .Q(n4096) );
DFFSX1TS DP_OP_156J7_125_3370_R_945_RW_1 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15]), .CK(clk), .SN(
n4114), .Q(n4084) );
DFFSX1TS DP_OP_156J7_125_3370_R_830_RW_1 ( .D(DP_OP_156J7_125_3370_n194),
.CK(clk), .SN(n4114), .Q(n4081) );
DFFSX1TS DP_OP_156J7_125_3370_R_733_RW_2 ( .D(DP_OP_156J7_125_3370_n73),
.CK(clk), .SN(n4114), .Q(n4076) );
DFFRXLTS DP_OP_156J7_125_3370_R_969 ( .D(DP_OP_156J7_125_3370_n84), .CK(clk),
.RN(n4116), .Q(n4095) );
DFFSX1TS DP_OP_156J7_125_3370_R_968 ( .D(DP_OP_156J7_125_3370_n83), .CK(clk),
.SN(n4114), .Q(n4094) );
DFFRXLTS DP_OP_156J7_125_3370_R_946_RW_0 ( .D(DP_OP_156J7_125_3370_n196),
.CK(clk), .RN(n4116), .Q(n4085) );
DFFSX1TS DP_OP_156J7_125_3370_R_957 ( .D(DP_OP_156J7_125_3370_n189), .CK(clk), .SN(n4115), .Q(n4092) );
DFFSX1TS DP_OP_156J7_125_3370_R_956 ( .D(DP_OP_156J7_125_3370_n192), .CK(clk), .SN(n4115), .Q(n4091) );
DFFSX1TS DP_OP_156J7_125_3370_R_955 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16]), .CK(clk), .SN(
n4114), .Q(n4090) );
DFFSX1TS DP_OP_156J7_125_3370_R_954 ( .D(DP_OP_156J7_125_3370_n81), .CK(clk),
.SN(n4115), .Q(n4089) );
DFFSX1TS DP_OP_156J7_125_3370_R_951 ( .D(DP_OP_156J7_125_3370_n198), .CK(clk), .SN(n4115), .Q(n4088) );
DFFRXLTS DP_OP_156J7_125_3370_R_947 ( .D(DP_OP_156J7_125_3370_n193), .CK(clk), .RN(n4116), .Q(n4086) );
DFFRXLTS DP_OP_156J7_125_3370_R_910 ( .D(DP_OP_156J7_125_3370_n185), .CK(clk), .RN(n4116), .Q(n4083) );
DFFSX1TS DP_OP_156J7_125_3370_R_907 ( .D(DP_OP_156J7_125_3370_n185), .CK(clk), .SN(n457), .Q(n4082) );
DFFSX1TS DP_OP_156J7_125_3370_R_771 ( .D(DP_OP_156J7_125_3370_n12), .CK(clk),
.SN(n4114), .Q(n4077) );
DFFRX1TS DP_OP_155J7_124_2038_R_323 ( .D(n354), .CK(clk), .RN(n4148), .Q(
DP_OP_155J7_124_2038_n798) );
DFFRXLTS DP_OP_155J7_124_2038_R_290 ( .D(n319), .CK(clk), .RN(n4219), .Q(
DP_OP_155J7_124_2038_n783) );
DFFSX1TS add_x_19_R_1018 ( .D(Sgf_operation_EVEN1_Q_left[6]), .CK(clk), .SN(
n4067), .Q(n4064) );
DFFSX1TS add_x_19_R_1017 ( .D(add_x_19_n243), .CK(clk), .SN(n444), .Q(n4063)
);
DFFSX1TS add_x_19_R_809_RW_2 ( .D(add_x_19_n226), .CK(clk), .SN(n4069), .Q(
n4039) );
DFFSX1TS add_x_19_R_1003 ( .D(Sgf_operation_EVEN1_Q_left[2]), .CK(clk), .SN(
n454), .Q(n4062) );
DFFSX1TS add_x_19_R_725_RW_2 ( .D(add_x_19_n26), .CK(clk), .SN(n4065), .Q(
n4032) );
DFFRX1TS add_x_19_R_884_RW_0 ( .D(Sgf_operation_EVEN1_Q_left[5]), .CK(clk),
.RN(n4068), .Q(n4052) );
DFFRXLTS add_x_19_R_800_RW_0 ( .D(add_x_19_n276), .CK(clk), .RN(n4068), .Q(
n4037) );
DFFRXLTS add_x_19_R_799_RW_0 ( .D(add_x_19_n275), .CK(clk), .RN(n4068), .Q(
n4036) );
DFFSX1TS add_x_19_R_653_RW_1 ( .D(add_x_19_n244), .CK(clk), .SN(n4065), .Q(
n4024) );
DFFSX1TS add_x_19_R_643_RW_1 ( .D(n3235), .CK(clk), .SN(n4065), .Q(n4021) );
DFFSX1TS add_x_19_R_640_RW_1 ( .D(add_x_19_n251), .CK(clk), .SN(n4065), .Q(
n4019) );
DFFSX1TS add_x_19_R_624_RW_1 ( .D(add_x_19_n269), .CK(clk), .SN(n4065), .Q(
n4017) );
DFFSX1TS add_x_19_R_618_RW_1 ( .D(add_x_19_n233), .CK(clk), .SN(n4065), .Q(
n4015) );
DFFRXLTS add_x_19_R_647_RW_2 ( .D(add_x_19_n244), .CK(clk), .RN(n4068), .Q(
n4023) );
DFFRXLTS add_x_19_R_654_RW_1 ( .D(n3945), .CK(clk), .RN(n4067), .Q(n4025) );
DFFRXLTS add_x_19_R_644_RW_1 ( .D(n3309), .CK(clk), .RN(n4068), .Q(n4022) );
DFFRXLTS add_x_19_R_625_RW_1 ( .D(add_x_19_n270), .CK(clk), .RN(n4067), .Q(
n4018) );
DFFRXLTS add_x_19_R_540_RW_1 ( .D(add_x_19_n24), .CK(clk), .RN(n4067), .Q(
n4006) );
DFFSX1TS add_x_19_R_889 ( .D(Sgf_operation_EVEN1_Q_left[8]), .CK(clk), .SN(
n4065), .Q(n4057) );
DFFSX1TS add_x_19_R_888 ( .D(Sgf_operation_EVEN1_Q_left[9]), .CK(clk), .SN(
n4066), .Q(n4056) );
DFFSX1TS add_x_19_R_887 ( .D(Sgf_operation_EVEN1_Q_left[10]), .CK(clk), .SN(
n4066), .Q(n4055) );
DFFSX1TS add_x_19_R_886 ( .D(Sgf_operation_EVEN1_Q_left[11]), .CK(clk), .SN(
n4066), .Q(n4054) );
DFFSX1TS add_x_19_R_885 ( .D(Sgf_operation_EVEN1_Q_left[12]), .CK(clk), .SN(
n4069), .Q(n4053) );
DFFSX1TS add_x_19_R_883 ( .D(add_x_19_n220), .CK(clk), .SN(n4069), .Q(n4051)
);
DFFRXLTS add_x_19_R_881 ( .D(n432), .CK(clk), .RN(n4228), .Q(n4050) );
DFFRX1TS add_x_19_R_880 ( .D(n3320), .CK(clk), .RN(n4228), .Q(n4049) );
DFFRX1TS add_x_19_R_879 ( .D(add_x_19_n94), .CK(clk), .RN(n4152), .Q(n4048)
);
DFFSX1TS add_x_19_R_878 ( .D(add_x_19_n85), .CK(clk), .SN(n4069), .Q(n4047)
);
DFFRX1TS add_x_19_R_876 ( .D(n3269), .CK(clk), .RN(n445), .Q(n4046) );
DFFRX1TS add_x_19_R_874 ( .D(add_x_19_n47), .CK(clk), .RN(n4229), .Q(n4044)
);
DFFRX1TS add_x_19_R_873 ( .D(add_x_19_n39), .CK(clk), .RN(n445), .Q(n4043)
);
DFFRXLTS add_x_19_R_843 ( .D(Sgf_operation_EVEN1_Q_left[3]), .CK(clk), .RN(
n4067), .Q(n4042) );
DFFSX1TS add_x_19_R_838 ( .D(add_x_19_n25), .CK(clk), .SN(n487), .Q(n4041)
);
DFFSX1TS add_x_19_R_837 ( .D(add_x_19_n279), .CK(clk), .SN(n4228), .Q(n4040)
);
DFFSX1TS add_x_19_R_798 ( .D(add_x_19_n284), .CK(clk), .SN(n4066), .Q(n4035)
);
DFFRXLTS add_x_19_R_589_RW_0 ( .D(Sgf_operation_EVEN1_Q_left[7]), .CK(clk),
.RN(n4067), .Q(n4013) );
DFFSX1TS add_x_19_R_573_RW_1 ( .D(add_x_19_n22), .CK(clk), .SN(n4067), .Q(
n4011) );
DFFSX1TS add_x_19_R_571_RW_1 ( .D(add_x_19_n20), .CK(clk), .SN(n4066), .Q(
n4010) );
DFFSX1TS add_x_19_R_567_RW_1 ( .D(add_x_19_n21), .CK(clk), .SN(n4066), .Q(
n4009) );
DFFSX1TS add_x_19_R_565_RW_1 ( .D(add_x_19_n19), .CK(clk), .SN(n4066), .Q(
n4008) );
DFFSX1TS add_x_19_R_563_RW_1 ( .D(add_x_19_n23), .CK(clk), .SN(n4067), .Q(
n4007) );
DFFSX1TS add_x_19_R_738_RW_0 ( .D(add_x_19_n242), .CK(clk), .SN(n4067), .Q(
n4034) );
DFFSX1TS add_x_19_R_724 ( .D(add_x_19_n282), .CK(clk), .SN(n4230), .Q(n4031)
);
DFFSX1TS add_x_19_R_715 ( .D(add_x_19_n273), .CK(clk), .SN(n4069), .Q(n4030)
);
DFFRXLTS add_x_19_R_686 ( .D(Sgf_operation_EVEN1_Q_left[4]), .CK(clk), .RN(
n4068), .Q(n4028) );
DFFSX1TS add_x_19_R_677 ( .D(Sgf_operation_EVEN1_Q_left[4]), .CK(clk), .SN(
n4067), .Q(n4027) );
DFFSX1TS add_x_19_R_577 ( .D(Sgf_operation_EVEN1_Q_left[7]), .CK(clk), .SN(
n4066), .Q(n4012) );
DFFRXLTS add_x_19_R_517 ( .D(Sgf_operation_EVEN1_Q_left[13]), .CK(clk), .RN(
n455), .Q(n4005) );
DFFSX1TS add_x_19_R_465 ( .D(Sgf_operation_EVEN1_Q_left[13]), .CK(clk), .SN(
n4069), .Q(n4004) );
DFFSX1TS add_x_19_R_55 ( .D(Sgf_operation_EVEN1_Q_left[22]), .CK(clk), .SN(
n487), .Q(n4003) );
DFFSX1TS add_x_19_R_53 ( .D(n3255), .CK(clk), .SN(n487), .Q(n4002) );
DFFSX1TS add_x_19_R_51 ( .D(n3337), .CK(clk), .SN(n4228), .Q(n4001) );
DFFRXLTS add_x_19_R_47 ( .D(add_x_19_n106), .CK(clk), .RN(n4229), .Q(n4000)
);
DFFRXLTS add_x_19_R_45 ( .D(add_x_19_n96), .CK(clk), .RN(n4229), .Q(n3999)
);
DFFRXLTS add_x_19_R_43 ( .D(n3944), .CK(clk), .RN(n4229), .Q(n3998) );
DFFRXLTS add_x_19_R_39 ( .D(add_x_19_n59), .CK(clk), .RN(n4229), .Q(n3996)
);
DFFRXLTS add_x_19_R_37 ( .D(n430), .CK(clk), .RN(n4229), .Q(n3995) );
DFFRX2TS DP_OP_153J7_122_5442_R_402 ( .D(n3957), .CK(clk), .RN(n4147), .Q(
DP_OP_153J7_122_5442_n1201), .QN(n3990) );
DFFSX2TS DP_OP_153J7_122_5442_R_401 ( .D(n3950), .CK(clk), .SN(n4147), .Q(
DP_OP_153J7_122_5442_n1205) );
DFFRXLTS DP_OP_153J7_122_5442_R_993 ( .D(n3976), .CK(clk), .RN(n3979), .QN(
n3986) );
DFFRX1TS DP_OP_153J7_122_5442_R_898 ( .D(n3975), .CK(clk), .RN(n3981), .Q(
DP_OP_153J7_122_5442_n1127) );
DFFSX1TS DP_OP_153J7_122_5442_R_859 ( .D(n3973), .CK(clk), .SN(n4151), .Q(
DP_OP_153J7_122_5442_n1173), .QN(n3992) );
DFFSX1TS DP_OP_153J7_122_5442_R_855 ( .D(n3970), .CK(clk), .SN(n4147), .Q(
DP_OP_153J7_122_5442_n1182) );
DFFSX2TS DP_OP_153J7_122_5442_R_901 ( .D(n3969), .CK(clk), .SN(n3980), .Q(
DP_OP_153J7_122_5442_n1103) );
DFFSX1TS DP_OP_153J7_122_5442_R_851 ( .D(n3966), .CK(clk), .SN(n3980), .Q(
DP_OP_153J7_122_5442_n1061) );
DFFRXLTS DP_OP_153J7_122_5442_R_481 ( .D(n3961), .CK(clk), .RN(n3979), .Q(
DP_OP_153J7_122_5442_n829) );
DFFSX2TS DP_OP_153J7_122_5442_R_353 ( .D(n3956), .CK(clk), .SN(n4147), .Q(
DP_OP_153J7_122_5442_n1181), .QN(n3985) );
DFFSX1TS DP_OP_153J7_122_5442_R_336 ( .D(n3955), .CK(clk), .SN(n3979), .Q(
DP_OP_153J7_122_5442_n788) );
DFFRX2TS DP_OP_153J7_122_5442_R_337 ( .D(n320), .CK(clk), .RN(n3979), .Q(
DP_OP_153J7_122_5442_n1475) );
DFFRX2TS DP_OP_153J7_122_5442_R_338 ( .D(n332), .CK(clk), .RN(n3979), .Q(
DP_OP_153J7_122_5442_n1464) );
DFFSX1TS DP_OP_153J7_122_5442_R_590 ( .D(n3952), .CK(clk), .SN(n3981), .Q(
DP_OP_153J7_122_5442_n1113), .QN(n3984) );
DFFSX1TS DP_OP_153J7_122_5442_R_856 ( .D(n3971), .CK(clk), .SN(n4147), .Q(
DP_OP_153J7_122_5442_n1148) );
DFFSX1TS add_x_19_R_727 ( .D(Sgf_operation_EVEN1_Q_left[3]), .CK(clk), .SN(
n4069), .Q(n4033) );
DFFSX1TS add_x_19_R_602 ( .D(n3945), .CK(clk), .SN(n4066), .Q(n4014) );
DFFSX1TS DP_OP_156J7_125_3370_R_1006 ( .D(DP_OP_156J7_125_3370_n211), .CK(
clk), .SN(n457), .Q(n4107) );
DFFRX4TS R_269 ( .D(n313), .CK(clk), .RN(n3980), .Q(
DP_OP_155J7_124_2038_n789) );
DFFSX2TS R_1021 ( .D(n3496), .CK(clk), .SN(n4228), .Q(n411) );
DFFSX2TS R_1022 ( .D(add_x_19_n228), .CK(clk), .SN(n4066), .Q(n410) );
DFFSX2TS R_1023 ( .D(n4214), .CK(clk), .SN(n455), .Q(n409) );
DFFRX2TS R_1024 ( .D(n3496), .CK(clk), .RN(n4230), .Q(n408) );
DFFSX2TS R_1025 ( .D(n3496), .CK(clk), .SN(n454), .Q(n407) );
DFFRX2TS R_1026 ( .D(n416), .CK(clk), .RN(n4229), .Q(n406) );
ADDFHX2TS DP_OP_36J7_126_4699_U3 ( .A(DP_OP_36J7_126_4699_n15), .B(
S_Oper_A_exp[7]), .CI(DP_OP_36J7_126_4699_n3), .CO(
DP_OP_36J7_126_4699_n2), .S(Exp_module_Data_S[7]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n243), .CK(clk), .RN(
n444), .Q(P_Sgf[5]) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n374), .CK(clk), .RN(
n4216), .Q(Op_MX[30]), .QN(n4175) );
DFFRHQX4TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n348), .CK(clk), .RN(
n489), .Q(Op_MX[4]) );
DFFRX1TS DP_OP_154J7_123_2038_R_460 ( .D(n358), .CK(clk), .RN(n4148), .Q(
DP_OP_154J7_123_2038_n793) );
DFFSX2TS DP_OP_153J7_122_5442_R_273 ( .D(n3947), .CK(clk), .SN(n3981), .Q(
DP_OP_153J7_122_5442_n1114) );
DFFRX2TS DP_OP_154J7_123_2038_R_326 ( .D(n364), .CK(clk), .RN(n461), .Q(
DP_OP_154J7_123_2038_n699) );
DFFRX1TS DP_OP_153J7_122_5442_R_995 ( .D(n3964), .CK(clk), .RN(n3981), .QN(
n3987) );
DFFSX1TS DP_OP_156J7_125_3370_R_822 ( .D(DP_OP_156J7_125_3370_n69), .CK(clk),
.SN(n4115), .Q(n4078) );
CMPR32X2TS DP_OP_36J7_126_4699_U10 ( .A(S_Oper_A_exp[0]), .B(n4070), .C(
DP_OP_36J7_126_4699_n22), .CO(DP_OP_36J7_126_4699_n9), .S(
Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_36J7_126_4699_U8 ( .A(DP_OP_36J7_126_4699_n20), .B(
S_Oper_A_exp[2]), .C(DP_OP_36J7_126_4699_n8), .CO(
DP_OP_36J7_126_4699_n7), .S(Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_36J7_126_4699_U2 ( .A(n4070), .B(S_Oper_A_exp[8]), .C(
DP_OP_36J7_126_4699_n2), .CO(DP_OP_36J7_126_4699_n1), .S(
Exp_module_Data_S[8]) );
NAND2X2TS U406 ( .A(DP_OP_156J7_125_3370_n202), .B(DP_OP_156J7_125_3370_n199), .Y(DP_OP_156J7_125_3370_n61) );
NAND2X1TS U407 ( .A(n3307), .B(n3302), .Y(add_x_19_n20) );
NAND2X1TS U408 ( .A(n3323), .B(n3321), .Y(add_x_19_n22) );
NAND2X1TS U409 ( .A(n3305), .B(n3323), .Y(add_x_19_n251) );
NAND2X1TS U410 ( .A(n3238), .B(n3237), .Y(add_x_19_n23) );
NAND2X1TS U411 ( .A(n3336), .B(n3335), .Y(add_x_19_n21) );
NAND2X1TS U412 ( .A(n3273), .B(n3272), .Y(add_x_19_n25) );
XOR2X1TS U413 ( .A(n3331), .B(n3330), .Y(Sgf_operation_Result_17_) );
NAND2X4TS U414 ( .A(n3362), .B(n3361), .Y(DP_OP_156J7_125_3370_n84) );
INVX2TS U415 ( .A(n3936), .Y(n3935) );
INVX2TS U416 ( .A(n3936), .Y(n3933) );
INVX2TS U417 ( .A(n3941), .Y(n3934) );
INVX2TS U418 ( .A(n3496), .Y(n4215) );
CLKINVX6TS U419 ( .A(add_x_19_n244), .Y(add_x_19_n242) );
NAND2X6TS U420 ( .A(DP_OP_156J7_125_3370_n207), .B(DP_OP_156J7_125_3370_n210), .Y(DP_OP_156J7_125_3370_n75) );
NAND2X1TS U421 ( .A(n3252), .B(n3251), .Y(n3272) );
CLKMX2X2TS U422 ( .A(Data_MY[7]), .B(Op_MY[7]), .S0(n3899), .Y(n319) );
INVX2TS U423 ( .A(n3266), .Y(n3323) );
CLKMX2X2TS U424 ( .A(Data_MX[15]), .B(n4161), .S0(n3803), .Y(n359) );
BUFX4TS U425 ( .A(n2885), .Y(n3945) );
CLKMX2X2TS U426 ( .A(Data_MY[20]), .B(n4210), .S0(n3804), .Y(n332) );
NOR2X6TS U427 ( .A(n3306), .B(n3315), .Y(add_x_19_n228) );
OR2X4TS U428 ( .A(n3430), .B(n534), .Y(n3432) );
AOI21X2TS U429 ( .A0(n3550), .A1(n3548), .B0(n3326), .Y(n3331) );
NAND2X1TS U430 ( .A(n3253), .B(n414), .Y(n3332) );
AOI21X1TS U431 ( .A0(n3815), .A1(n3814), .B0(n3817), .Y(n3816) );
XOR2X1TS U432 ( .A(n3526), .B(n3467), .Y(n3468) );
INVX2TS U433 ( .A(n3377), .Y(n3380) );
BUFX3TS U434 ( .A(n3936), .Y(n3940) );
NAND2X1TS U435 ( .A(n3337), .B(n3239), .Y(n3320) );
INVX3TS U436 ( .A(DP_OP_156J7_125_3370_n99), .Y(n3435) );
AND2X2TS U437 ( .A(n3388), .B(n3387), .Y(n3389) );
NAND2X4TS U438 ( .A(n3305), .B(n3304), .Y(add_x_19_n244) );
OAI21X2TS U439 ( .A0(n3382), .A1(n3386), .B0(n3387), .Y(n3231) );
AND3X2TS U440 ( .A(n3796), .B(n3771), .C(n3710), .Y(n3713) );
OR2X2TS U441 ( .A(n3704), .B(n3703), .Y(n3838) );
NOR2X2TS U442 ( .A(n3208), .B(n3386), .Y(n3230) );
NOR2X2TS U443 ( .A(n3325), .B(n3327), .Y(n3314) );
OAI2BB1X1TS U444 ( .A0N(n3794), .A1N(n490), .B0(n3638), .Y(n3639) );
NAND2X2TS U445 ( .A(n3274), .B(n3267), .Y(n3268) );
INVX2TS U446 ( .A(n3790), .Y(n490) );
NAND2X1TS U447 ( .A(n3313), .B(n3312), .Y(n3328) );
NAND2X6TS U448 ( .A(n3141), .B(n3140), .Y(n3385) );
CLKMX2X2TS U449 ( .A(Data_MY[16]), .B(n4208), .S0(n3891), .Y(
DP_OP_154J7_123_2038_n782) );
INVX2TS U450 ( .A(n3063), .Y(n414) );
INVX2TS U451 ( .A(n3325), .Y(n3548) );
OAI2BB1X2TS U452 ( .A0N(n407), .A1N(n3763), .B0(n4203), .Y(n3785) );
NAND2X1TS U453 ( .A(n3175), .B(n3174), .Y(n3178) );
NOR2X4TS U454 ( .A(n3266), .B(n3334), .Y(n3304) );
CLKXOR2X2TS U455 ( .A(n3249), .B(n3248), .Y(n3253) );
NOR2X4TS U456 ( .A(add_x_19_n269), .B(n3236), .Y(n3305) );
OR3X1TS U457 ( .A(underflow_flag), .B(overflow_flag), .C(n3937), .Y(n3936)
);
BUFX3TS U458 ( .A(n3244), .Y(n3251) );
OR2X2TS U459 ( .A(n3459), .B(n3560), .Y(n3496) );
INVX6TS U460 ( .A(n1172), .Y(add_x_19_n51) );
INVX6TS U461 ( .A(n3250), .Y(n3063) );
INVX2TS U462 ( .A(n458), .Y(n459) );
INVX2TS U463 ( .A(n458), .Y(n460) );
BUFX3TS U464 ( .A(n3736), .Y(n3817) );
NOR2X1TS U465 ( .A(n3559), .B(n4135), .Y(n3459) );
NOR2X4TS U466 ( .A(n3210), .B(n3209), .Y(n3386) );
NOR2X4TS U467 ( .A(n2834), .B(n3453), .Y(n3266) );
NAND2X1TS U468 ( .A(n3565), .B(n3815), .Y(n3563) );
CLKBUFX2TS U469 ( .A(n518), .Y(n3944) );
NAND2X1TS U470 ( .A(n3247), .B(n3246), .Y(n3248) );
NOR2X6TS U471 ( .A(n2835), .B(n3402), .Y(n3334) );
NAND2X4TS U472 ( .A(n3035), .B(n3033), .Y(n3030) );
NOR2X6TS U473 ( .A(n2736), .B(n3377), .Y(n3236) );
NOR2X4TS U474 ( .A(n3234), .B(n3233), .Y(add_x_19_n269) );
NAND2X2TS U475 ( .A(n3082), .B(n3132), .Y(n2369) );
OR2X1TS U476 ( .A(n3815), .B(FSM_selector_C), .Y(n3790) );
NAND2X2TS U477 ( .A(n3117), .B(n3131), .Y(n3118) );
NAND2X4TS U478 ( .A(n3026), .B(n3025), .Y(n3033) );
OA21XLTS U479 ( .A0(n2994), .A1(n2993), .B0(n2992), .Y(n504) );
NAND2X1TS U480 ( .A(n3299), .B(n3347), .Y(n3528) );
NAND2X1TS U481 ( .A(n1743), .B(n1742), .Y(n1744) );
INVX1TS U482 ( .A(n3569), .Y(n458) );
INVX2TS U483 ( .A(n3899), .Y(n3900) );
OAI21X2TS U484 ( .A0(n3133), .A1(n3132), .B0(n3131), .Y(n3134) );
AOI21X2TS U485 ( .A0(n2312), .A1(n1740), .B0(n1739), .Y(n1745) );
NAND2X2TS U486 ( .A(n3886), .B(n3885), .Y(n3887) );
INVX2TS U487 ( .A(n3565), .Y(n3736) );
CLKBUFX2TS U488 ( .A(n3939), .Y(n3941) );
OAI21XLTS U489 ( .A0(n3781), .A1(n3597), .B0(n3596), .Y(n3598) );
INVX6TS U490 ( .A(n3261), .Y(n2463) );
OA21XLTS U491 ( .A0(n2832), .A1(n2831), .B0(n2830), .Y(n527) );
NAND2X1TS U492 ( .A(n433), .B(n2321), .Y(n2299) );
NAND2X1TS U493 ( .A(n2454), .B(n2671), .Y(n2455) );
CLKBUFX2TS U494 ( .A(n3282), .Y(n3885) );
INVX3TS U495 ( .A(n2841), .Y(n2842) );
NAND2X1TS U496 ( .A(n2640), .B(n2715), .Y(n2641) );
NAND2X2TS U497 ( .A(n2766), .B(n2784), .Y(n2767) );
NAND2X2TS U498 ( .A(n2307), .B(n2306), .Y(n2308) );
AND2X2TS U499 ( .A(n3800), .B(n3706), .Y(n3939) );
NOR2X2TS U500 ( .A(n3558), .B(n4135), .Y(n3565) );
NAND2X2TS U501 ( .A(n3796), .B(n3712), .Y(n3899) );
NAND2X1TS U502 ( .A(n3399), .B(n3398), .Y(n3417) );
INVX2TS U503 ( .A(n3283), .Y(n3038) );
NAND2X1TS U504 ( .A(n3072), .B(n2771), .Y(n2773) );
INVX1TS U505 ( .A(n2305), .Y(n2307) );
NOR2X1TS U506 ( .A(n3369), .B(n3366), .Y(n3372) );
NOR2X2TS U507 ( .A(FS_Module_state_reg[3]), .B(FS_Module_state_reg[2]), .Y(
n3712) );
NOR2XLTS U508 ( .A(n4043), .B(n3642), .Y(n2971) );
NOR2XLTS U509 ( .A(n3642), .B(n4044), .Y(n3643) );
NOR2X1TS U510 ( .A(n3798), .B(n3710), .Y(n3558) );
OAI21X2TS U511 ( .A0(n3561), .A1(n3560), .B0(FS_Module_state_reg[1]), .Y(
n3815) );
NOR2X2TS U512 ( .A(n4129), .B(FS_Module_state_reg[1]), .Y(n3796) );
NAND2X1TS U513 ( .A(n3069), .B(n3068), .Y(n3368) );
NAND2X1TS U514 ( .A(n3374), .B(n3373), .Y(n3445) );
BUFX3TS U515 ( .A(n3469), .Y(n3693) );
NOR2XLTS U516 ( .A(n3201), .B(n448), .Y(n3218) );
INVX3TS U517 ( .A(n2293), .Y(n3044) );
NAND2X2TS U518 ( .A(n2281), .B(n2419), .Y(n2282) );
NAND2X2TS U519 ( .A(n2290), .B(n2289), .Y(n2291) );
NAND2X6TS U520 ( .A(n403), .B(n433), .Y(n3081) );
NAND2X1TS U521 ( .A(n3049), .B(n3048), .Y(n3050) );
NOR2X4TS U522 ( .A(n2817), .B(n426), .Y(n2819) );
AOI21X1TS U523 ( .A0(n2459), .A1(n2458), .B0(n2376), .Y(n3067) );
NAND2X1TS U524 ( .A(FS_Module_state_reg[2]), .B(n4136), .Y(n3718) );
INVX2TS U525 ( .A(n2287), .Y(n3056) );
AND2X6TS U526 ( .A(n1104), .B(n2311), .Y(n1153) );
INVX2TS U527 ( .A(n2769), .Y(n2720) );
NOR2X4TS U528 ( .A(n3586), .B(n3632), .Y(n3741) );
NAND2X2TS U529 ( .A(n3046), .B(n3019), .Y(n3021) );
INVX3TS U530 ( .A(n2817), .Y(n3078) );
OAI21X1TS U531 ( .A0(n2373), .A1(n2372), .B0(n2371), .Y(n2459) );
NAND2X1TS U532 ( .A(n2285), .B(n2284), .Y(n2372) );
NAND2X1TS U533 ( .A(n2970), .B(n4005), .Y(n3633) );
NAND2X4TS U534 ( .A(n1103), .B(n1102), .Y(n1738) );
NOR2X6TS U535 ( .A(n1173), .B(n1741), .Y(n2311) );
NAND2X2TS U536 ( .A(n1100), .B(n1099), .Y(n2306) );
INVX4TS U537 ( .A(n2671), .Y(n2672) );
NOR2X2TS U538 ( .A(n3703), .B(FS_Module_state_reg[0]), .Y(n3798) );
XOR2X2TS U539 ( .A(n2809), .B(n2808), .Y(n2848) );
NOR2X2TS U540 ( .A(n2970), .B(n4004), .Y(n3632) );
CMPR32X2TS U541 ( .A(n3099), .B(n3098), .C(n3097), .CO(n3162), .S(n3089) );
INVX2TS U542 ( .A(n3879), .Y(n2747) );
NAND2X1TS U543 ( .A(n4131), .B(FS_Module_state_reg[3]), .Y(n3703) );
INVX2TS U544 ( .A(n3882), .Y(n2789) );
INVX3TS U545 ( .A(Sgf_operation_EVEN1_Q_left[9]), .Y(n2746) );
NAND2X1TS U546 ( .A(n2807), .B(n2856), .Y(n2808) );
NOR2X4TS U547 ( .A(n2235), .B(n2234), .Y(n3293) );
XOR2X1TS U548 ( .A(n2909), .B(n2908), .Y(n2969) );
INVX2TS U549 ( .A(n2844), .Y(n1460) );
NAND2X4TS U550 ( .A(n2235), .B(n2234), .Y(n3294) );
NOR2X6TS U551 ( .A(n1046), .B(n1045), .Y(n1741) );
NAND2X1TS U552 ( .A(n2962), .B(n4055), .Y(n3502) );
NAND2X6TS U553 ( .A(n3046), .B(n3049), .Y(n2182) );
XOR2X2TS U554 ( .A(n2692), .B(n2691), .Y(n2763) );
NAND2X2TS U555 ( .A(n2742), .B(n2741), .Y(n2744) );
CLKXOR2X2TS U556 ( .A(n2916), .B(n4074), .Y(n2970) );
CMPR32X2TS U557 ( .A(n3105), .B(n3104), .C(n3103), .CO(n3146), .S(n3090) );
NAND2X1TS U558 ( .A(n1157), .B(n1156), .Y(n1162) );
OR2X2TS U559 ( .A(n2579), .B(n2578), .Y(n3263) );
CLKINVX6TS U560 ( .A(n3019), .Y(n3045) );
NAND2X1TS U561 ( .A(n2697), .B(n2753), .Y(n2698) );
NAND2X4TS U562 ( .A(n1147), .B(n1146), .Y(n3053) );
NOR2X1TS U563 ( .A(n3658), .B(n3663), .Y(n2891) );
NOR2X6TS U564 ( .A(n1145), .B(n1144), .Y(n2997) );
OAI21X1TS U565 ( .A0(n2832), .A1(n2730), .B0(n2729), .Y(n2734) );
CMPR32X2TS U566 ( .A(n1721), .B(n3398), .C(n1720), .CO(n2350), .S(n1717) );
OR2X6TS U567 ( .A(n1133), .B(n1132), .Y(n2838) );
OR2X6TS U568 ( .A(n2174), .B(n2173), .Y(n2851) );
NOR2X1TS U569 ( .A(n3101), .B(n448), .Y(n3159) );
NAND2X1TS U570 ( .A(n1048), .B(n1075), .Y(n1022) );
NAND2X1TS U571 ( .A(n2443), .B(n2644), .Y(n2444) );
OR2X4TS U572 ( .A(n1327), .B(n1326), .Y(n2742) );
NAND2X1TS U573 ( .A(n2611), .B(n2623), .Y(n2612) );
INVX2TS U574 ( .A(n2837), .Y(n1134) );
INVX2TS U575 ( .A(n2741), .Y(n1328) );
OAI21X2TS U576 ( .A0(n1105), .A1(n1034), .B0(n1106), .Y(n1039) );
OAI21X2TS U577 ( .A0(n1050), .A1(n1109), .B0(n1049), .Y(n1064) );
INVX2TS U578 ( .A(n1125), .Y(n735) );
AOI21X2TS U579 ( .A0(n2664), .A1(n2663), .B0(n2662), .Y(n2832) );
OAI21X2TS U580 ( .A0(n2608), .A1(n2622), .B0(n2624), .Y(n2613) );
NAND2X2TS U581 ( .A(n2227), .B(n2236), .Y(n2228) );
OAI2BB1X1TS U582 ( .A0N(n2914), .A1N(n2913), .B0(n2912), .Y(n2915) );
BUFX12TS U583 ( .A(n2190), .Y(n2652) );
CMPR32X2TS U584 ( .A(n1698), .B(n1697), .C(n1696), .CO(n2362), .S(n1728) );
NAND2X1TS U585 ( .A(n2732), .B(n2731), .Y(n2826) );
NOR2X1TS U586 ( .A(n2731), .B(n2732), .Y(n2822) );
NAND2X1TS U587 ( .A(n1094), .B(n1093), .Y(n1163) );
INVX2TS U588 ( .A(n3876), .Y(n2599) );
NOR2X1TS U589 ( .A(n2333), .B(n448), .Y(n3108) );
INVX2TS U590 ( .A(n2635), .Y(n2705) );
NAND2X1TS U591 ( .A(n2907), .B(n4083), .Y(n2912) );
NAND2X1TS U592 ( .A(n1072), .B(n1077), .Y(n1080) );
INVX2TS U593 ( .A(n2649), .Y(n2385) );
NAND2X1TS U594 ( .A(n1072), .B(n1048), .Y(n1050) );
INVX2TS U595 ( .A(n2643), .Y(n2386) );
NOR2X1TS U596 ( .A(n3844), .B(n3811), .Y(n3842) );
AO21X1TS U597 ( .A0(n1505), .A1(n2335), .B0(n2334), .Y(n3107) );
INVX1TS U598 ( .A(n2384), .Y(n2270) );
CLKINVX1TS U599 ( .A(n1035), .Y(n1037) );
NAND2X1TS U600 ( .A(n2947), .B(n2945), .Y(n2944) );
NOR2X1TS U601 ( .A(n2943), .B(n2951), .Y(n2910) );
INVX3TS U602 ( .A(n2627), .Y(n2608) );
OAI21X2TS U603 ( .A0(n1138), .A1(n1135), .B0(n1136), .Y(n1119) );
AOI21X2TS U604 ( .A0(n1078), .A1(n1048), .B0(n1047), .Y(n1049) );
OAI21X2TS U605 ( .A0(n2646), .A1(n2645), .B0(n2644), .Y(n2647) );
INVX2TS U606 ( .A(n2752), .Y(n2694) );
NAND2X2TS U607 ( .A(n2643), .B(n2427), .Y(n2429) );
ADDFHX1TS U608 ( .A(n1727), .B(n1726), .CI(n1725), .CO(n2351), .S(n1730) );
CMPR32X2TS U609 ( .A(n1615), .B(n1614), .C(n1613), .CO(n1665), .S(n1625) );
NAND2X1TS U610 ( .A(n2498), .B(n2497), .Y(n2499) );
XNOR2X1TS U611 ( .A(n1521), .B(n3156), .Y(n3157) );
XOR2X2TS U612 ( .A(n2569), .B(n2585), .Y(n2579) );
XNOR2X1TS U613 ( .A(n1408), .B(n3156), .Y(n3109) );
NAND2X1TS U614 ( .A(n1030), .B(n1029), .Y(n1088) );
NAND2X1TS U615 ( .A(n2679), .B(n2678), .Y(n2726) );
NAND2X1TS U616 ( .A(n2666), .B(n2665), .Y(n2727) );
CMPR32X2TS U617 ( .A(n2867), .B(n2866), .C(n2865), .CO(n3100), .S(n2805) );
NAND2X1TS U618 ( .A(n2448), .B(n2447), .Y(n2659) );
CMPR32X2TS U619 ( .A(n1572), .B(n1571), .C(n1570), .CO(n3373), .S(n3122) );
CLKINVX2TS U620 ( .A(n2695), .Y(n1726) );
INVX2TS U621 ( .A(n2630), .Y(n1671) );
NAND2X1TS U622 ( .A(n2413), .B(n2412), .Y(n2660) );
INVX6TS U623 ( .A(n1113), .Y(n1138) );
ADDFX2TS U624 ( .A(n1694), .B(n1693), .CI(n1692), .CO(n2359), .S(n1725) );
OR2X2TS U625 ( .A(n1322), .B(n1321), .Y(n2633) );
NAND2X1TS U626 ( .A(n2553), .B(n2552), .Y(n3285) );
INVX2TS U627 ( .A(n2642), .Y(n2427) );
CMPR32X2TS U628 ( .A(n1493), .B(n1492), .C(n1491), .CO(n1582), .S(n1461) );
INVX2TS U629 ( .A(n1071), .Y(n1048) );
NAND2X1TS U630 ( .A(n2564), .B(n2584), .Y(n2569) );
INVX2TS U631 ( .A(n2923), .Y(n2938) );
NOR2X2TS U632 ( .A(n2630), .B(n2629), .Y(n2752) );
NOR2X2TS U633 ( .A(n2665), .B(n2666), .Y(n2725) );
NOR2X4TS U634 ( .A(n1105), .B(n1035), .Y(n1072) );
NOR2X6TS U635 ( .A(n2381), .B(n2384), .Y(n2643) );
OAI22X1TS U636 ( .A0(n1603), .A1(n1505), .B0(n1656), .B1(n477), .Y(n1653) );
NAND2X2TS U637 ( .A(n2153), .B(n2152), .Y(n2155) );
NAND2X2TS U638 ( .A(n404), .B(n2185), .Y(n2005) );
NAND2X2TS U639 ( .A(n2470), .B(n2469), .Y(n2472) );
OAI21X2TS U640 ( .A0(n1075), .A1(n1074), .B0(n1073), .Y(n1076) );
ADDFX1TS U641 ( .A(n1659), .B(n1658), .CI(n1657), .CO(n1696), .S(n1652) );
CMPR32X2TS U642 ( .A(n1352), .B(n1351), .C(n1350), .CO(n1436), .S(n1329) );
CMPR32X2TS U643 ( .A(n1312), .B(n1311), .C(n1310), .CO(n1393), .S(n1324) );
CMPR32X2TS U644 ( .A(n1537), .B(n1536), .C(n1535), .CO(n1617), .S(n1570) );
NAND2X1TS U645 ( .A(n2563), .B(n2562), .Y(n2584) );
NOR2X4TS U646 ( .A(n1021), .B(n1020), .Y(n1071) );
NOR2X4TS U647 ( .A(n2409), .B(n2408), .Y(n2642) );
NAND2X1TS U648 ( .A(n2906), .B(n2905), .Y(n2949) );
CMPR32X2TS U649 ( .A(n1509), .B(n1508), .C(n1507), .CO(n3121), .S(n3068) );
NOR2X6TS U650 ( .A(n2225), .B(n2226), .Y(n2381) );
NAND2X2TS U651 ( .A(n1021), .B(n1020), .Y(n1075) );
NOR2X1TS U652 ( .A(n1650), .B(n3216), .Y(n1694) );
INVX3TS U653 ( .A(n2183), .Y(n404) );
NOR2X1TS U654 ( .A(n2340), .B(n2339), .Y(n3112) );
NOR2X4TS U655 ( .A(n996), .B(n997), .Y(n1105) );
INVX2TS U656 ( .A(n2186), .Y(n2058) );
NOR2X4TS U657 ( .A(n2183), .B(n2186), .Y(n2189) );
OAI22X1TS U658 ( .A0(n1684), .A1(n2336), .B0(n1619), .B1(n2337), .Y(n1674)
);
OAI22X2TS U659 ( .A0(n3197), .A1(n1576), .B0(n3196), .B1(n1606), .Y(n1593)
);
XNOR2X2TS U660 ( .A(n1408), .B(n1421), .Y(n1603) );
XNOR2X2TS U661 ( .A(n1521), .B(n1595), .Y(n1562) );
XNOR2X2TS U662 ( .A(n1408), .B(n2341), .Y(n1699) );
XNOR2X1TS U663 ( .A(n3214), .B(n1421), .Y(n1691) );
XNOR2X2TS U664 ( .A(n1348), .B(n1421), .Y(n1569) );
XNOR2X2TS U665 ( .A(n1605), .B(n2341), .Y(n1577) );
AOI21X1TS U666 ( .A0(n515), .A1(n1111), .B0(n1026), .Y(n1043) );
CMPR32X2TS U667 ( .A(n1609), .B(n1608), .C(n1607), .CO(n2629), .S(n2610) );
CMPR32X2TS U668 ( .A(n2328), .B(n2327), .C(n2326), .CO(n2865), .S(n2329) );
OR2X6TS U669 ( .A(n779), .B(n778), .Y(n2494) );
CLKINVX2TS U670 ( .A(n3874), .Y(n2577) );
NOR2X1TS U671 ( .A(n1539), .B(n2339), .Y(n1621) );
NOR2X1TS U672 ( .A(n1682), .B(n2339), .Y(n1704) );
NOR2X6TS U673 ( .A(n930), .B(n931), .Y(n1135) );
NOR2X1TS U674 ( .A(n2919), .B(n4106), .Y(n2897) );
NOR2X1TS U675 ( .A(n1623), .B(n2339), .Y(n1680) );
INVX2TS U676 ( .A(n3156), .Y(n448) );
INVX2TS U677 ( .A(n1127), .Y(n1129) );
NAND2X2TS U678 ( .A(n2128), .B(n2127), .Y(n2636) );
INVX4TS U679 ( .A(n2497), .Y(n2492) );
XNOR2X1TS U680 ( .A(n1681), .B(n1683), .Y(n1619) );
XNOR2X2TS U681 ( .A(n1605), .B(n3156), .Y(n1651) );
CMPR32X2TS U682 ( .A(n2239), .B(n2238), .C(n2237), .CO(n2389), .S(n2267) );
CMPR32X2TS U683 ( .A(n2551), .B(n2550), .C(n2549), .CO(n2535), .S(n2552) );
NAND2X1TS U684 ( .A(n2230), .B(n2229), .Y(n2275) );
NOR2X4TS U685 ( .A(n929), .B(n928), .Y(n1127) );
CLKINVX6TS U686 ( .A(n434), .Y(n451) );
BUFX6TS U687 ( .A(n1449), .Y(n2341) );
INVX2TS U688 ( .A(n1519), .Y(n3016) );
INVX2TS U689 ( .A(n2152), .Y(n1995) );
INVX2TS U690 ( .A(n918), .Y(n919) );
INVX4TS U691 ( .A(n3216), .Y(n3156) );
NAND2X1TS U692 ( .A(n1141), .B(n1140), .Y(n1142) );
NAND2X2TS U693 ( .A(n779), .B(n778), .Y(n2493) );
NAND2X2TS U694 ( .A(n2507), .B(n2506), .Y(n2531) );
XNOR2X2TS U695 ( .A(n2332), .B(n1595), .Y(n1349) );
CLKXOR2X2TS U696 ( .A(n2513), .B(n2512), .Y(n3874) );
ADDFHX2TS U697 ( .A(n1476), .B(n1475), .CI(n1474), .CO(n2581), .S(n2563) );
NAND2X1TS U698 ( .A(n2098), .B(n2097), .Y(n2099) );
NAND2X1TS U699 ( .A(n1497), .B(n1288), .Y(n2284) );
BUFX8TS U700 ( .A(n1186), .Y(n2335) );
XNOR2X2TS U701 ( .A(n1681), .B(n1269), .Y(n1376) );
XNOR2X1TS U702 ( .A(n1538), .B(n1540), .Y(n1377) );
CLKXOR2X2TS U703 ( .A(n1193), .B(n1389), .Y(n1194) );
ADDFX2TS U704 ( .A(n2404), .B(n2403), .CI(n2402), .CO(n2438), .S(n2407) );
ADDFHX2TS U705 ( .A(n1016), .B(n1015), .CI(n1014), .CO(n1052), .S(n1017) );
CMPR32X2TS U706 ( .A(n983), .B(n982), .C(n981), .CO(n1015), .S(n975) );
CMPR32X2TS U707 ( .A(n2264), .B(n2263), .C(n2262), .CO(n2390), .S(n2237) );
NAND2X1TS U708 ( .A(n1389), .B(n1388), .Y(n1390) );
NOR2BX1TS U709 ( .AN(n1551), .B(n1380), .Y(n1415) );
NAND2X1TS U710 ( .A(n736), .B(n765), .Y(n737) );
NAND2X1TS U711 ( .A(n2107), .B(n2106), .Y(n2108) );
NAND2X1TS U712 ( .A(n2116), .B(n2115), .Y(n2117) );
BUFX8TS U713 ( .A(n1258), .Y(n1595) );
NAND2X1TS U714 ( .A(n769), .B(n768), .Y(n770) );
NAND2X1TS U715 ( .A(n2111), .B(n2110), .Y(n2112) );
OAI21X2TS U716 ( .A0(n1335), .A1(n1334), .B0(n1333), .Y(n1336) );
BUFX6TS U717 ( .A(n1224), .Y(n1676) );
ADDFHX2TS U718 ( .A(n857), .B(n856), .CI(n855), .CO(n916), .S(n922) );
OAI22X1TS U719 ( .A0(n2245), .A1(n2398), .B0(n2434), .B1(n2244), .Y(n2403)
);
NOR2X2TS U720 ( .A(n1335), .B(n1332), .Y(n1338) );
NOR2X2TS U721 ( .A(n478), .B(n1009), .Y(n1055) );
OAI22X2TS U722 ( .A0(n1550), .A1(n1713), .B0(n1714), .B1(n1304), .Y(n2506)
);
CMPR32X2TS U723 ( .A(n643), .B(n642), .C(n641), .CO(n805), .S(n672) );
NOR2X1TS U724 ( .A(n1444), .B(n1438), .Y(n1387) );
CMPR32X2TS U725 ( .A(n891), .B(n890), .C(n889), .CO(n942), .S(n897) );
INVX12TS U726 ( .A(n1490), .Y(n2868) );
BUFX6TS U727 ( .A(n1231), .Y(n1499) );
INVX2TS U728 ( .A(n2732), .Y(n2248) );
NAND2X1TS U729 ( .A(n1238), .B(n1235), .Y(n1211) );
NOR2X1TS U730 ( .A(n2114), .B(n2570), .Y(n2080) );
NOR2X1TS U731 ( .A(n1226), .B(n1225), .Y(n1227) );
NAND2X2TS U732 ( .A(n1446), .B(n1445), .Y(n1447) );
NOR2X2TS U733 ( .A(n483), .B(n2211), .Y(n2261) );
AOI21X2TS U734 ( .A0(n1373), .A1(n1273), .B0(n1276), .Y(n1215) );
OAI21X2TS U735 ( .A0(n1208), .A1(n1209), .B0(n1234), .Y(n1212) );
OAI22X1TS U736 ( .A0(n1547), .A1(n1300), .B0(n1381), .B1(n1546), .Y(n1385)
);
NOR2X1TS U737 ( .A(n479), .B(n879), .Y(n941) );
NOR2X2TS U738 ( .A(n2434), .B(n2255), .Y(n2394) );
ADDFX2TS U739 ( .A(n1961), .B(n1960), .CI(n1959), .CO(n1953), .S(n1991) );
OAI21X2TS U740 ( .A0(n2096), .A1(n2107), .B0(n2097), .Y(n2163) );
XNOR2X2TS U741 ( .A(n1716), .B(n1545), .Y(n1412) );
NOR2X1TS U742 ( .A(n479), .B(n980), .Y(n1005) );
ADDFX2TS U743 ( .A(n1911), .B(n1910), .CI(n1909), .CO(n1920), .S(n1954) );
NAND2X6TS U744 ( .A(n1302), .B(n473), .Y(n1550) );
CMPR32X2TS U745 ( .A(n2030), .B(n2029), .C(n2028), .CO(n2194), .S(n2049) );
ADDHX2TS U746 ( .A(n1008), .B(n2987), .CO(n1056), .S(n1006) );
INVX2TS U747 ( .A(n2665), .Y(n2032) );
CLKINVX2TS U748 ( .A(n1094), .Y(n898) );
NAND2X1TS U749 ( .A(n1984), .B(n1983), .Y(n2110) );
NOR2X4TS U750 ( .A(n2077), .B(n2078), .Y(n2114) );
NAND2X1TS U751 ( .A(n3994), .B(DP_OP_153J7_122_5442_n1173), .Y(n1487) );
NAND2X2TS U752 ( .A(n2078), .B(n2077), .Y(n2115) );
INVX2TS U753 ( .A(n1553), .Y(n443) );
NAND2X1TS U754 ( .A(n1359), .B(n1358), .Y(n1362) );
NOR2X1TS U755 ( .A(n478), .B(n865), .Y(n889) );
NOR2X1TS U756 ( .A(n743), .B(n2477), .Y(n698) );
NAND2X1TS U757 ( .A(n1183), .B(n1182), .Y(n1257) );
NAND2X1TS U758 ( .A(n1291), .B(n1365), .Y(n1294) );
AND2X2TS U759 ( .A(n750), .B(n663), .Y(n503) );
OAI21X2TS U760 ( .A0(n1370), .A1(n1371), .B0(n1369), .Y(n1375) );
OAI22X1TS U761 ( .A0(n2021), .A1(n2396), .B0(n453), .B1(n2433), .Y(n2030) );
XNOR2X1TS U762 ( .A(n1410), .B(n1552), .Y(n1382) );
OAI2BB2X1TS U763 ( .B0(n2021), .B1(n2398), .A0N(n1836), .A1N(n1778), .Y(
n2029) );
CMPR32X2TS U764 ( .A(n2020), .B(n2019), .C(n2018), .CO(n2679), .S(n2666) );
NOR2X1TS U765 ( .A(n4184), .B(n521), .Y(n2253) );
CMPR32X2TS U766 ( .A(n952), .B(n951), .C(n950), .CO(n1168), .S(n1156) );
NAND2X1TS U767 ( .A(n2074), .B(n2073), .Y(n2510) );
NOR2X1TS U768 ( .A(n2257), .B(DP_OP_155J7_124_2038_n728), .Y(n2254) );
NAND2X1TS U769 ( .A(n3985), .B(DP_OP_153J7_122_5442_n1182), .Y(n1402) );
INVX2TS U770 ( .A(n830), .Y(n846) );
CLKINVX3TS U771 ( .A(n499), .Y(n473) );
INVX8TS U772 ( .A(n539), .Y(n481) );
INVX4TS U773 ( .A(n840), .Y(n478) );
CLKXOR2X2TS U774 ( .A(DP_OP_153J7_122_5442_n778), .B(
DP_OP_153J7_122_5442_n1474), .Y(n1270) );
INVX6TS U775 ( .A(n840), .Y(n479) );
BUFX6TS U776 ( .A(n2397), .Y(n2245) );
OAI21X1TS U777 ( .A0(n1280), .A1(DP_OP_153J7_122_5442_n451), .B0(n1218), .Y(
n1183) );
AOI21X2TS U778 ( .A0(n1238), .A1(n1237), .B0(n1236), .Y(n1239) );
INVX4TS U779 ( .A(n1280), .Y(n1546) );
NOR2X2TS U780 ( .A(n1372), .B(n1371), .Y(n1374) );
BUFX4TS U781 ( .A(n1010), .Y(n440) );
NAND2X1TS U782 ( .A(n1647), .B(n1364), .Y(n1343) );
CMPR32X2TS U783 ( .A(n1871), .B(n1870), .C(n1869), .CO(n2448), .S(n2413) );
CMPR32X2TS U784 ( .A(Op_MX[21]), .B(n3903), .C(n948), .CO(n979), .S(n951) );
NOR2X1TS U785 ( .A(n420), .B(n2090), .Y(n2145) );
NOR2X1TS U786 ( .A(n4184), .B(DP_OP_155J7_124_2038_n728), .Y(n2206) );
INVX6TS U787 ( .A(n1250), .Y(n1647) );
NAND2X1TS U788 ( .A(n3951), .B(n3987), .Y(n1468) );
CLKINVX2TS U789 ( .A(n691), .Y(n593) );
NOR2X1TS U790 ( .A(n880), .B(DP_OP_154J7_123_2038_n628), .Y(n727) );
NOR2X1TS U791 ( .A(n835), .B(DP_OP_154J7_123_2038_n634), .Y(n728) );
INVX2TS U792 ( .A(n583), .Y(n1009) );
INVX8TS U793 ( .A(n1763), .Y(n2397) );
INVX2TS U794 ( .A(n1809), .Y(n2433) );
NOR2X2TS U795 ( .A(n419), .B(n521), .Y(n2207) );
INVX2TS U796 ( .A(n1795), .Y(n2398) );
OAI21X2TS U797 ( .A0(DP_OP_153J7_122_5442_n778), .A1(
DP_OP_153J7_122_5442_n1474), .B0(n1218), .Y(n1220) );
INVX2TS U798 ( .A(n1209), .Y(n1233) );
OAI21X2TS U799 ( .A0(n2487), .A1(n2520), .B0(n2488), .Y(n2467) );
BUFX16TS U800 ( .A(n2022), .Y(n2215) );
OAI22X1TS U801 ( .A0(n480), .A1(n841), .B0(n450), .B1(n865), .Y(n652) );
NAND2X2TS U802 ( .A(n1273), .B(n401), .Y(n1372) );
ADDFHX2TS U803 ( .A(DP_OP_153J7_122_5442_n1475), .B(
DP_OP_153J7_122_5442_n1464), .CI(DP_OP_153J7_122_5442_n829), .CO(n1192), .S(n1187) );
ADDFHX2TS U804 ( .A(n560), .B(n559), .CI(n558), .CO(n695), .S(n694) );
ADDFX2TS U805 ( .A(n722), .B(n721), .CI(n720), .CO(n964), .S(n908) );
CMPR32X2TS U806 ( .A(n623), .B(n622), .C(n621), .CO(n810), .S(n561) );
NOR2X1TS U807 ( .A(n418), .B(n521), .Y(n2013) );
NOR2X1TS U808 ( .A(n423), .B(n428), .Y(n2038) );
NOR2X1TS U809 ( .A(n420), .B(n397), .Y(n2039) );
CMPR32X2TS U810 ( .A(n2007), .B(n1952), .C(n1951), .CO(n1973), .S(n1974) );
NOR2X1TS U811 ( .A(n419), .B(DP_OP_155J7_124_2038_n728), .Y(n2012) );
NOR2X1TS U812 ( .A(n417), .B(n2090), .Y(n2091) );
NOR2X1TS U813 ( .A(n421), .B(n2090), .Y(n2037) );
INVX2TS U814 ( .A(n1024), .Y(n609) );
INVX2TS U815 ( .A(n1794), .Y(n2211) );
INVX8TS U816 ( .A(n501), .Y(n1545) );
INVX6TS U817 ( .A(n400), .Y(n450) );
INVX2TS U818 ( .A(n556), .Y(n841) );
OR2X2TS U819 ( .A(Op_MX[22]), .B(Op_MX[10]), .Y(n1364) );
INVX2TS U820 ( .A(n1793), .Y(n1978) );
NOR2X1TS U821 ( .A(n827), .B(n858), .Y(n657) );
NAND2X1TS U822 ( .A(n2523), .B(n2522), .Y(n2528) );
INVX2TS U823 ( .A(n2007), .Y(n1940) );
NOR2X2TS U824 ( .A(DP_OP_154J7_123_2038_n715), .B(DP_OP_154J7_123_2038_n718),
.Y(n872) );
NAND2X2TS U825 ( .A(n3983), .B(DP_OP_153J7_122_5442_n1097), .Y(n1416) );
CLKINVX1TS U826 ( .A(n1242), .Y(n1244) );
INVX1TS U827 ( .A(n1466), .Y(n1467) );
NAND2X2TS U828 ( .A(n2071), .B(n2070), .Y(n2514) );
NAND2X4TS U829 ( .A(n1202), .B(n1340), .Y(n1204) );
OA21X2TS U830 ( .A0(n1766), .A1(n1841), .B0(n1765), .Y(n1767) );
NOR2X2TS U831 ( .A(n1950), .B(n1949), .Y(n1975) );
OR2X1TS U832 ( .A(n1766), .B(n1840), .Y(n1768) );
NOR2X2TS U833 ( .A(n662), .B(n987), .Y(n591) );
NAND2X2TS U834 ( .A(n1551), .B(n1205), .Y(n1234) );
NOR2X1TS U835 ( .A(n419), .B(n398), .Y(n1803) );
NOR2X1TS U836 ( .A(n421), .B(n397), .Y(n1815) );
NOR2X1TS U837 ( .A(n4184), .B(n398), .Y(n1821) );
NOR2X1TS U838 ( .A(n423), .B(n397), .Y(n1814) );
NOR2X1TS U839 ( .A(n421), .B(n431), .Y(n1812) );
NOR2X1TS U840 ( .A(n420), .B(n431), .Y(n1852) );
NOR2X1TS U841 ( .A(n447), .B(DP_OP_154J7_123_2038_n720), .Y(n815) );
NOR2X1TS U842 ( .A(n447), .B(n520), .Y(n588) );
NOR2X1TS U843 ( .A(n4178), .B(DP_OP_154J7_123_2038_n634), .Y(n714) );
NOR2X1TS U844 ( .A(DP_OP_155J7_124_2038_n725), .B(n521), .Y(n1891) );
NOR2X1TS U845 ( .A(n880), .B(n4178), .Y(n723) );
NAND2X1TS U846 ( .A(n3993), .B(DP_OP_153J7_122_5442_n1193), .Y(n1248) );
NOR2X1TS U847 ( .A(n2257), .B(n1939), .Y(n1893) );
INVX2TS U848 ( .A(n1856), .Y(n1949) );
NOR2X4TS U849 ( .A(DP_OP_154J7_123_2038_n715), .B(n429), .Y(n816) );
INVX2TS U850 ( .A(n690), .Y(n567) );
NOR2X2TS U851 ( .A(n447), .B(DP_OP_154J7_123_2038_n718), .Y(n904) );
NAND2X1TS U852 ( .A(n1760), .B(n1765), .Y(n1761) );
INVX2TS U853 ( .A(n1796), .Y(n2202) );
INVX2TS U854 ( .A(n1788), .Y(n2027) );
NOR2X2TS U855 ( .A(DP_OP_154J7_123_2038_n715), .B(DP_OP_154J7_123_2038_n720),
.Y(n622) );
INVX2TS U856 ( .A(n1778), .Y(n2244) );
NOR2X2TS U857 ( .A(n835), .B(DP_OP_154J7_123_2038_n635), .Y(n724) );
OAI21X2TS U858 ( .A0(n1242), .A1(n3990), .B0(n1247), .Y(n1249) );
INVX2TS U859 ( .A(n540), .Y(n858) );
INVX6TS U860 ( .A(n399), .Y(n662) );
NAND2X2TS U861 ( .A(Op_MX[20]), .B(Op_MX[8]), .Y(n1274) );
NAND2X2TS U862 ( .A(Op_MX[19]), .B(Op_MX[7]), .Y(n1229) );
NOR2X1TS U863 ( .A(n405), .B(n522), .Y(n814) );
INVX4TS U864 ( .A(n1777), .Y(n1981) );
NOR2X2TS U865 ( .A(n419), .B(n1755), .Y(n1895) );
CLKXOR2X4TS U866 ( .A(DP_OP_153J7_122_5442_n1148), .B(
DP_OP_153J7_122_5442_n1205), .Y(n1552) );
INVX4TS U867 ( .A(n1777), .Y(n1950) );
AND2X4TS U868 ( .A(n1482), .B(n3994), .Y(n1202) );
INVX4TS U869 ( .A(n549), .Y(n947) );
NOR2X1TS U870 ( .A(DP_OP_155J7_124_2038_n725), .B(n517), .Y(n1773) );
NAND2X1TS U871 ( .A(Op_MX[11]), .B(Op_MX[5]), .Y(n1765) );
NOR2X1TS U872 ( .A(n880), .B(n675), .Y(n705) );
INVX6TS U873 ( .A(Op_MY[11]), .Y(n2257) );
NAND2X1TS U874 ( .A(n1833), .B(n1832), .Y(n1834) );
NOR2X4TS U875 ( .A(n502), .B(n1176), .Y(n1190) );
NOR2X2TS U876 ( .A(n396), .B(n428), .Y(n1749) );
NAND2X2TS U877 ( .A(n3982), .B(DP_OP_153J7_122_5442_n1118), .Y(n1178) );
INVX3TS U878 ( .A(n541), .Y(n579) );
BUFX4TS U879 ( .A(DP_OP_153J7_122_5442_n1120), .Y(n1180) );
NOR2X4TS U880 ( .A(n1948), .B(n1846), .Y(n1750) );
NAND2X2TS U881 ( .A(n1785), .B(DP_OP_155J7_124_2038_n388), .Y(n1786) );
NOR2X2TS U882 ( .A(n699), .B(DP_OP_154J7_123_2038_n634), .Y(n703) );
NOR2X2TS U883 ( .A(n396), .B(n1938), .Y(n2523) );
CLKBUFX2TS U884 ( .A(Op_MX[12]), .Y(n3922) );
BUFX3TS U885 ( .A(n4181), .Y(n3901) );
NOR2X2TS U886 ( .A(Op_MX[11]), .B(Op_MX[5]), .Y(n1766) );
INVX8TS U887 ( .A(DP_OP_154J7_123_2038_n357), .Y(n835) );
INVX4TS U888 ( .A(n1784), .Y(n1830) );
INVX6TS U889 ( .A(Op_MX[7]), .Y(n1939) );
OR2X2TS U890 ( .A(DP_OP_155J7_124_2038_n794), .B(n3183), .Y(n1775) );
NOR2X2TS U891 ( .A(n396), .B(n2040), .Y(n1779) );
INVX3TS U892 ( .A(Op_MX[4]), .Y(n1846) );
NAND2X2TS U893 ( .A(n405), .B(DP_OP_154J7_123_2038_n628), .Y(n555) );
BUFX3TS U894 ( .A(n620), .Y(n675) );
BUFX6TS U895 ( .A(DP_OP_154J7_123_2038_n632), .Y(n661) );
INVX6TS U896 ( .A(n552), .Y(n699) );
CLKINVX6TS U897 ( .A(DP_OP_155J7_124_2038_n789), .Y(n1948) );
INVX8TS U898 ( .A(DP_OP_154J7_123_2038_n792), .Y(n681) );
NAND2X2TS U899 ( .A(n3993), .B(DP_OP_153J7_122_5442_n1201), .Y(n1199) );
NAND2X2TS U900 ( .A(n3903), .B(DP_OP_154J7_123_2038_n781), .Y(n543) );
NOR2X6TS U901 ( .A(DP_OP_154J7_123_2038_n684), .B(n535), .Y(n575) );
INVX6TS U902 ( .A(n3183), .Y(n1979) );
OR2X4TS U903 ( .A(n1755), .B(n2040), .Y(n1832) );
BUFX12TS U904 ( .A(Op_MY[22]), .Y(n3806) );
BUFX4TS U905 ( .A(n552), .Y(n535) );
CLKBUFX2TS U906 ( .A(Op_MX[4]), .Y(n3802) );
INVX8TS U907 ( .A(DP_OP_155J7_124_2038_n803), .Y(n2040) );
INVX4TS U908 ( .A(n3943), .Y(n3183) );
INVX2TS U909 ( .A(n409), .Y(n391) );
INVX2TS U910 ( .A(n391), .Y(n392) );
INVX2TS U911 ( .A(n391), .Y(n393) );
INVX2TS U912 ( .A(n2448), .Y(n1864) );
INVX2TS U913 ( .A(n2447), .Y(n1838) );
OAI22X2TS U914 ( .A0(n962), .A1(n987), .B0(n480), .B1(n1009), .Y(n890) );
INVX2TS U915 ( .A(n1797), .Y(n2255) );
INVX4TS U916 ( .A(n566), .Y(n987) );
BUFX3TS U917 ( .A(n834), .Y(n839) );
OAI22X2TS U918 ( .A0(n1547), .A1(n1381), .B0(n1412), .B1(n1546), .Y(n1414)
);
INVX2TS U919 ( .A(n2071), .Y(n1933) );
INVX4TS U920 ( .A(n399), .Y(n827) );
NOR2BX1TS U921 ( .AN(n484), .B(n1596), .Y(n1319) );
NOR2X2TS U922 ( .A(n835), .B(n681), .Y(n704) );
NAND2X1TS U923 ( .A(n2442), .B(n2441), .Y(n2644) );
INVX2TS U924 ( .A(n2581), .Y(n1555) );
BUFX3TS U925 ( .A(n1186), .Y(n477) );
INVX6TS U926 ( .A(n1793), .Y(n453) );
NAND2X4TS U927 ( .A(n2056), .B(n2057), .Y(n2184) );
XNOR2X1TS U928 ( .A(n1418), .B(n1519), .Y(n2323) );
NOR2X1TS U929 ( .A(n447), .B(n522), .Y(n625) );
NAND2X4TS U930 ( .A(n997), .B(n996), .Y(n1033) );
XNOR2X1TS U931 ( .A(n1348), .B(n3156), .Y(n2354) );
NAND2X2TS U932 ( .A(n4184), .B(n506), .Y(n1683) );
ADDFHX2TS U933 ( .A(n1556), .B(n1555), .CI(n1554), .CO(n1600), .S(n1583) );
NAND2X2TS U934 ( .A(n2409), .B(n2408), .Y(n2646) );
INVX2TS U935 ( .A(n3048), .Y(n2180) );
INVX2TS U936 ( .A(n2188), .Y(n2004) );
NAND2X1TS U937 ( .A(n2532), .B(n2531), .Y(n2534) );
OAI21X2TS U938 ( .A0(n1467), .A1(n3946), .B0(n3986), .Y(n1469) );
CLKXOR2X4TS U939 ( .A(n1278), .B(n1277), .Y(n1622) );
NAND2X2TS U940 ( .A(n1992), .B(n1991), .Y(n2135) );
NAND2X1TS U941 ( .A(n1062), .B(n1073), .Y(n1063) );
NAND2X4TS U942 ( .A(n929), .B(n928), .Y(n1128) );
NAND2X2TS U943 ( .A(n673), .B(n672), .Y(n784) );
ADDHX1TS U944 ( .A(n3922), .B(Op_MX[18]), .CO(n557), .S(n556) );
OR2X4TS U945 ( .A(n1441), .B(Op_MY[11]), .Y(n1574) );
XOR2X1TS U946 ( .A(n2930), .B(n2929), .Y(n2931) );
NAND2X2TS U947 ( .A(n2136), .B(n2135), .Y(n2138) );
NOR2XLTS U948 ( .A(n3642), .B(n4046), .Y(n3609) );
ADDFX2TS U949 ( .A(n3113), .B(n3112), .CI(n3111), .CO(n3114), .S(n3424) );
AOI21X2TS U950 ( .A0(n524), .A1(n3257), .B0(n2559), .Y(n2560) );
OR2X1TS U951 ( .A(n749), .B(n748), .Y(n512) );
AOI21X2TS U952 ( .A0(n2771), .A1(n3073), .B0(n2770), .Y(n2772) );
NAND2X1TS U953 ( .A(n2963), .B(n4054), .Y(n3490) );
BUFX3TS U954 ( .A(n3736), .Y(n3788) );
BUFX3TS U955 ( .A(n3469), .Y(n3781) );
NOR2X4TS U956 ( .A(n1103), .B(n1102), .Y(n1173) );
NOR2X6TS U957 ( .A(n1147), .B(n1146), .Y(n3052) );
INVX2TS U958 ( .A(n3658), .Y(n3653) );
NAND2X2TS U959 ( .A(n2076), .B(n2075), .Y(n2571) );
OAI21XLTS U960 ( .A0(n2994), .A1(n1166), .B0(n1165), .Y(n1170) );
INVX6TS U961 ( .A(Op_MX[12]), .Y(n660) );
OAI21X1TS U962 ( .A0(n3781), .A1(n2974), .B0(n2973), .Y(n2975) );
NAND2X1TS U963 ( .A(n3798), .B(FSM_add_overflow_flag), .Y(n3559) );
INVX2TS U964 ( .A(n1173), .Y(n1740) );
NAND2X1TS U965 ( .A(n403), .B(n2320), .Y(n1736) );
OAI21XLTS U966 ( .A0(n3720), .A1(n4021), .B0(n4022), .Y(n3687) );
NAND2X1TS U967 ( .A(n2704), .B(n2636), .Y(n2637) );
NOR2XLTS U968 ( .A(n4136), .B(n4129), .Y(n3706) );
NOR3X2TS U969 ( .A(n4131), .B(FS_Module_state_reg[3]), .C(
FS_Module_state_reg[0]), .Y(n3560) );
NOR2X2TS U970 ( .A(n3253), .B(n414), .Y(n3333) );
OAI21XLTS U971 ( .A0(n4131), .A1(n3716), .B0(FS_Module_state_reg[3]), .Y(
n3709) );
INVX2TS U972 ( .A(n3838), .Y(n3835) );
OAI2BB1X1TS U973 ( .A0N(n407), .A1N(n3754), .B0(n4198), .Y(n3776) );
NOR4X1TS U974 ( .A(Exp_module_Data_S[8]), .B(Exp_module_Data_S[7]), .C(n3897), .D(n3931), .Y(n3898) );
INVX2TS U975 ( .A(n3931), .Y(n3715) );
OR2X6TS U976 ( .A(n3061), .B(n3060), .Y(n533) );
NOR2X1TS U977 ( .A(n4135), .B(FS_Module_state_reg[2]), .Y(n3800) );
INVX2TS U978 ( .A(n3941), .Y(n3937) );
OAI2BB1X2TS U979 ( .A0N(n407), .A1N(n2976), .B0(n4207), .Y(n3771) );
BUFX8TS U980 ( .A(Op_MY[21]), .Y(n3903) );
CLKINVX3TS U981 ( .A(n3900), .Y(n3804) );
NAND2X4TS U982 ( .A(n3234), .B(n3233), .Y(add_x_19_n270) );
OAI211XLTS U983 ( .A0(n3894), .A1(n4145), .B0(n3709), .C0(n3817), .Y(n380)
);
OR2X1TS U984 ( .A(DP_OP_154J7_123_2038_n778), .B(n312), .Y(n3968) );
NOR2XLTS U985 ( .A(n362), .B(n350), .Y(n3963) );
INVX2TS U986 ( .A(n3496), .Y(n4213) );
NOR2X4TS U987 ( .A(n2425), .B(n2424), .Y(n395) );
INVX4TS U988 ( .A(n412), .Y(n416) );
INVX2TS U989 ( .A(n3255), .Y(n2319) );
CLKXOR2X4TS U990 ( .A(n1745), .B(n1744), .Y(n3255) );
AND2X4TS U991 ( .A(n548), .B(n572), .Y(n399) );
CLKXOR2X4TS U992 ( .A(n573), .B(n572), .Y(n400) );
OR2X2TS U993 ( .A(Op_MX[20]), .B(Op_MX[8]), .Y(n401) );
BUFX3TS U994 ( .A(n2954), .Y(n474) );
INVX2TS U995 ( .A(n2968), .Y(n475) );
OA21X2TS U996 ( .A0(n3472), .A1(n2967), .B0(n2966), .Y(n2968) );
OAI22X2TS U997 ( .A0(n881), .A1(n947), .B0(n449), .B1(n980), .Y(n825) );
NOR2X4TS U998 ( .A(n3269), .B(n3268), .Y(n3310) );
CLKMX2X2TS U999 ( .A(n3468), .B(P_Sgf[14]), .S0(n4214), .Y(n252) );
XNOR2X1TS U1000 ( .A(n3531), .B(n3530), .Y(n3532) );
INVX4TS U1001 ( .A(n3402), .Y(n3412) );
NAND2X4TS U1002 ( .A(n412), .B(n3232), .Y(n3269) );
CLKMX2X2TS U1003 ( .A(n3884), .B(n467), .S0(n4214), .Y(n249) );
INVX4TS U1004 ( .A(n3020), .Y(n3047) );
INVX2TS U1005 ( .A(n3240), .Y(n2616) );
AO21X2TS U1006 ( .A0(Sgf_normalized_result[23]), .A1(n3817), .B0(n3816), .Y(
n310) );
CLKMX2X2TS U1007 ( .A(FSM_add_overflow_flag), .B(n3871), .S0(n3861), .Y(n285) );
CLKMX2X2TS U1008 ( .A(n3878), .B(P_Sgf[8]), .S0(n4214), .Y(n246) );
INVX2TS U1009 ( .A(n1072), .Y(n1001) );
INVX2TS U1010 ( .A(n2381), .Y(n2227) );
OAI2BB1X2TS U1011 ( .A0N(n411), .A1N(n3599), .B0(n4201), .Y(n3773) );
INVX4TS U1012 ( .A(n3877), .Y(n2617) );
NAND2X4TS U1013 ( .A(n2226), .B(n2225), .Y(n2383) );
INVX2TS U1014 ( .A(n2375), .Y(n1331) );
NAND2X2TS U1015 ( .A(n2589), .B(n2588), .Y(n2590) );
OR2X2TS U1016 ( .A(n2589), .B(n2588), .Y(n2591) );
INVX2TS U1017 ( .A(n2284), .Y(n1314) );
OAI22X2TS U1018 ( .A0(n1297), .A1(n1497), .B0(n1376), .B1(n425), .Y(n1353)
);
ADDFHX2TS U1019 ( .A(n2026), .B(n2025), .CI(n2024), .CO(n2223), .S(n2011) );
INVX2TS U1020 ( .A(n2502), .Y(n1426) );
XNOR2X2TS U1021 ( .A(n2734), .B(n2733), .Y(n2768) );
NAND2X4TS U1022 ( .A(n4047), .B(n3742), .Y(n3642) );
CLKMX2X2TS U1023 ( .A(n3874), .B(P_Sgf[4]), .S0(n4214), .Y(n242) );
INVX2TS U1024 ( .A(n3632), .Y(n3634) );
INVX2TS U1025 ( .A(n964), .Y(n981) );
INVX2TS U1026 ( .A(n866), .Y(n900) );
INVX2TS U1027 ( .A(n1335), .Y(n1254) );
OAI21X1TS U1028 ( .A0(FS_Module_state_reg[1]), .A1(n3718), .B0(n3717), .Y(
n377) );
INVX2TS U1029 ( .A(n908), .Y(n966) );
INVX3TS U1030 ( .A(n2679), .Y(n2198) );
NAND2X2TS U1031 ( .A(n2931), .B(n4057), .Y(n3511) );
INVX4TS U1032 ( .A(n2666), .Y(n2031) );
CLKMX2X2TS U1033 ( .A(Add_result[7]), .B(n3855), .S0(n3870), .Y(n302) );
CLKMX2X2TS U1034 ( .A(Add_result[9]), .B(n3849), .S0(n3861), .Y(n300) );
CLKMX2X2TS U1035 ( .A(Add_result[10]), .B(n3847), .S0(n3870), .Y(n299) );
INVX2TS U1036 ( .A(n347), .Y(n3701) );
INVX2TS U1037 ( .A(n1093), .Y(n899) );
INVX4TS U1038 ( .A(n3496), .Y(n4214) );
OR2X2TS U1039 ( .A(n2539), .B(n2538), .Y(n2541) );
INVX4TS U1040 ( .A(n3496), .Y(n3892) );
INVX2TS U1041 ( .A(n1156), .Y(n967) );
CLKMX2X2TS U1042 ( .A(Add_result[6]), .B(n3857), .S0(n3861), .Y(n303) );
CLKMX2X2TS U1043 ( .A(Add_result[8]), .B(n3851), .S0(n3861), .Y(n301) );
MX2X1TS U1044 ( .A(Data_MX[11]), .B(Op_MX[11]), .S0(n3805), .Y(n355) );
MX2X1TS U1045 ( .A(Data_MY[28]), .B(Op_MY[28]), .S0(n3804), .Y(n340) );
MX2X1TS U1046 ( .A(Data_MY[26]), .B(Op_MY[26]), .S0(n3804), .Y(n338) );
MX2X1TS U1047 ( .A(Data_MY[27]), .B(Op_MY[27]), .S0(n3803), .Y(n339) );
INVX2TS U1048 ( .A(n2272), .Y(n1900) );
MX2X1TS U1049 ( .A(Data_MY[25]), .B(Op_MY[25]), .S0(n3890), .Y(n337) );
MX2X1TS U1050 ( .A(Data_MY[29]), .B(Op_MY[29]), .S0(n3803), .Y(n341) );
MX2X1TS U1051 ( .A(Data_MY[30]), .B(Op_MY[30]), .S0(n3801), .Y(n342) );
MX2X1TS U1052 ( .A(Data_MY[11]), .B(Op_MY[11]), .S0(n3801), .Y(n323) );
NAND2X2TS U1053 ( .A(n1281), .B(n1547), .Y(n2539) );
NAND2BX1TS U1054 ( .AN(n1551), .B(n1545), .Y(n1281) );
INVX4TS U1055 ( .A(n1545), .Y(n2327) );
INVX4TS U1056 ( .A(n3900), .Y(n3891) );
OR2X2TS U1057 ( .A(n2519), .B(n2518), .Y(n2521) );
INVX2TS U1058 ( .A(n2070), .Y(n1874) );
INVX4TS U1059 ( .A(n3838), .Y(n3861) );
ADDHX2TS U1060 ( .A(n1772), .B(n1771), .CO(n1819), .S(n1782) );
ADDHX2TS U1061 ( .A(n1752), .B(n1751), .CO(n1890), .S(n1828) );
NOR2X4TS U1062 ( .A(n1199), .B(n1242), .Y(n1200) );
INVX2TS U1063 ( .A(n2068), .Y(n1941) );
BUFX6TS U1064 ( .A(n3708), .Y(n4070) );
XNOR2X1TS U1065 ( .A(n1225), .B(n1221), .Y(n1222) );
INVX2TS U1066 ( .A(n1140), .Y(n613) );
CLKINVX1TS U1067 ( .A(n3798), .Y(n3735) );
ADDHX2TS U1068 ( .A(Op_MX[18]), .B(n3901), .CO(n875), .S(n813) );
NOR2X4TS U1069 ( .A(n1948), .B(n397), .Y(n1780) );
CLKMX2X2TS U1070 ( .A(Op_MX[25]), .B(exp_oper_result[2]), .S0(FSM_selector_A), .Y(S_Oper_A_exp[2]) );
NAND2X2TS U1071 ( .A(n3317), .B(n3316), .Y(add_x_19_n19) );
NAND2X4TS U1072 ( .A(n3430), .B(n534), .Y(n3431) );
MX2X2TS U1073 ( .A(n3551), .B(n468), .S0(n4215), .Y(n254) );
MX2X2TS U1074 ( .A(n3532), .B(P_Sgf[15]), .S0(n4215), .Y(n253) );
NAND2X6TS U1075 ( .A(n533), .B(n3434), .Y(n3062) );
NOR2X1TS U1076 ( .A(n3320), .B(n3319), .Y(add_x_19_n85) );
INVX6TS U1077 ( .A(add_x_19_n293), .Y(n3550) );
NAND2X4TS U1078 ( .A(n3440), .B(n3439), .Y(n3443) );
CLKMX2X2TS U1079 ( .A(n3464), .B(P_Sgf[13]), .S0(n4215), .Y(n251) );
NOR2X4TS U1080 ( .A(n3313), .B(n3312), .Y(n3327) );
INVX6TS U1081 ( .A(n3073), .Y(n3074) );
NOR2X4TS U1082 ( .A(n3299), .B(n3347), .Y(n3527) );
NAND2X2TS U1083 ( .A(n2461), .B(n2669), .Y(n2462) );
NAND2X2TS U1084 ( .A(n3298), .B(n3289), .Y(n3524) );
CLKMX2X2TS U1085 ( .A(n3889), .B(P_Sgf[12]), .S0(n4215), .Y(n250) );
AND2X2TS U1086 ( .A(n3888), .B(n3887), .Y(n3889) );
INVX6TS U1087 ( .A(n3081), .Y(n3137) );
OR2X2TS U1088 ( .A(n3886), .B(n3885), .Y(n3888) );
OR2X2TS U1089 ( .A(n3231), .B(n529), .Y(n530) );
INVX4TS U1090 ( .A(n2302), .Y(n402) );
OAI2BB1X1TS U1091 ( .A0N(n470), .A1N(n274), .B0(n3640), .Y(n215) );
INVX6TS U1092 ( .A(n2322), .Y(n403) );
CLKMX2X2TS U1093 ( .A(n3882), .B(P_Sgf[10]), .S0(n4215), .Y(n248) );
OAI21X1TS U1094 ( .A0(n3447), .A1(n3406), .B0(n3405), .Y(n3411) );
NAND2X2TS U1095 ( .A(n2797), .B(n2796), .Y(n2799) );
NAND2X4TS U1096 ( .A(n2845), .B(n2844), .Y(n2847) );
OAI21X1TS U1097 ( .A0(n3447), .A1(n3397), .B0(n3396), .Y(n3401) );
CLKMX2X2TS U1098 ( .A(n3879), .B(P_Sgf[9]), .S0(n4215), .Y(n247) );
OAI21X1TS U1099 ( .A0(n3447), .A1(n3423), .B0(n3422), .Y(n3429) );
OAI21X1TS U1100 ( .A0(n3447), .A1(n3446), .B0(n3445), .Y(n3452) );
OAI21X1TS U1101 ( .A0(n3120), .A1(n3366), .B0(n3368), .Y(n3125) );
BUFX12TS U1102 ( .A(n1034), .Y(n1109) );
CLKMX2X2TS U1103 ( .A(Add_result[23]), .B(n3812), .S0(n3835), .Y(n286) );
NAND2X2TS U1104 ( .A(n2427), .B(n2646), .Y(n2410) );
NAND2X2TS U1105 ( .A(n1037), .B(n1036), .Y(n1038) );
NAND2X4TS U1106 ( .A(n1133), .B(n1132), .Y(n2837) );
NAND2X4TS U1107 ( .A(n2058), .B(n2184), .Y(n2059) );
XOR3X2TS U1108 ( .A(n3226), .B(n3225), .C(n3224), .Y(n3227) );
ADDFHX2TS U1109 ( .A(n1662), .B(n1661), .CI(n1660), .CO(n1732), .S(n1685) );
NAND2X2TS U1110 ( .A(n2270), .B(n2382), .Y(n415) );
OAI2BB1X2TS U1111 ( .A0N(n407), .A1N(n3637), .B0(n4200), .Y(n3794) );
XNOR2X2TS U1112 ( .A(n2975), .B(n3995), .Y(n2976) );
CLKMX2X2TS U1113 ( .A(Add_result[22]), .B(n3819), .S0(n3835), .Y(n287) );
NAND2X1TS U1114 ( .A(n3263), .B(n3262), .Y(n3265) );
OAI21X1TS U1115 ( .A0(n3418), .A1(n3417), .B0(n3416), .Y(n3419) );
OAI21X2TS U1116 ( .A0(n3693), .A1(n3585), .B0(n2968), .Y(n3588) );
INVX6TS U1117 ( .A(n2864), .Y(n2804) );
CLKMX2X2TS U1118 ( .A(n3877), .B(P_Sgf[7]), .S0(n4214), .Y(n245) );
CLKMX2X2TS U1119 ( .A(Add_result[21]), .B(n3821), .S0(n3835), .Y(n288) );
INVX2TS U1120 ( .A(n2645), .Y(n2443) );
CLKMX2X2TS U1121 ( .A(Add_result[20]), .B(n3823), .S0(n3835), .Y(n289) );
INVX3TS U1122 ( .A(n2706), .Y(n2131) );
OR2X2TS U1123 ( .A(n3151), .B(n3150), .Y(n3203) );
CLKMX2X2TS U1124 ( .A(n3876), .B(P_Sgf[6]), .S0(n4214), .Y(n244) );
OR2X2TS U1125 ( .A(n3425), .B(n3424), .Y(n3427) );
INVX2TS U1126 ( .A(n2377), .Y(n1428) );
AND2X2TS U1127 ( .A(n3174), .B(n3176), .Y(n2986) );
NOR2X1TS U1128 ( .A(n3215), .B(n448), .Y(n3217) );
INVX2TS U1129 ( .A(n3256), .Y(n3291) );
NAND2X2TS U1130 ( .A(n785), .B(n784), .Y(n787) );
CLKMX2X2TS U1131 ( .A(Add_result[19]), .B(n3825), .S0(n3835), .Y(n290) );
NOR2X1TS U1132 ( .A(n3152), .B(n448), .Y(n3202) );
CLKMX2X2TS U1133 ( .A(Add_result[18]), .B(n3827), .S0(n3835), .Y(n291) );
CLKMX2X2TS U1134 ( .A(exp_oper_result[8]), .B(Exp_module_Data_S[8]), .S0(
n3893), .Y(n226) );
XNOR2X1TS U1135 ( .A(DP_OP_36J7_126_4699_n1), .B(n3894), .Y(n3895) );
OAI21X1TS U1136 ( .A0(n3693), .A1(n3501), .B0(n3500), .Y(n3505) );
ADDFHX2TS U1137 ( .A(n1454), .B(n1453), .CI(n1452), .CO(n3069), .S(n2377) );
OR2X2TS U1138 ( .A(n3100), .B(n3110), .Y(n523) );
OR2X2TS U1139 ( .A(n3200), .B(n3199), .Y(n3219) );
OAI22X2TS U1140 ( .A0(n1677), .A1(n1624), .B0(n1676), .B1(n1675), .Y(n1678)
);
OAI21X1TS U1141 ( .A0(n3693), .A1(n3475), .B0(n3474), .Y(n3480) );
OAI21X1TS U1142 ( .A0(n3693), .A1(n3470), .B0(n3510), .Y(n3514) );
NAND2X2TS U1143 ( .A(n2769), .B(n2768), .Y(n2816) );
CLKMX2X2TS U1144 ( .A(Add_result[17]), .B(n3829), .S0(n3835), .Y(n292) );
NOR2X1TS U1145 ( .A(n1700), .B(n2339), .Y(n2345) );
CLKMX2X2TS U1146 ( .A(exp_oper_result[7]), .B(Exp_module_Data_S[7]), .S0(
n3893), .Y(n227) );
NOR2X1TS U1147 ( .A(n3778), .B(n4049), .Y(n3743) );
OAI22X2TS U1148 ( .A0(n1505), .A1(n2334), .B0(n477), .B1(n1306), .Y(n1350)
);
NOR2X1TS U1149 ( .A(n3778), .B(n4050), .Y(n3758) );
CLKMX2X2TS U1150 ( .A(exp_oper_result[6]), .B(Exp_module_Data_S[6]), .S0(
n3893), .Y(n228) );
NOR2X1TS U1151 ( .A(n3778), .B(n4048), .Y(n3749) );
CLKMX2X2TS U1152 ( .A(Add_result[16]), .B(n3831), .S0(n3835), .Y(n293) );
OAI21X1TS U1153 ( .A0(n3498), .A1(n3484), .B0(n3502), .Y(n3486) );
ADDHX2TS U1154 ( .A(n1383), .B(n2503), .CO(n1425), .S(n1351) );
CLKMX2X2TS U1155 ( .A(exp_oper_result[5]), .B(Exp_module_Data_S[5]), .S0(
n3893), .Y(n229) );
CLKMX2X2TS U1156 ( .A(Add_result[15]), .B(n3833), .S0(n3870), .Y(n294) );
NAND2BX1TS U1157 ( .AN(n1604), .B(n1595), .Y(n1282) );
NAND2BX1TS U1158 ( .AN(n1499), .B(n1683), .Y(n1432) );
NAND2BX1TS U1159 ( .AN(n1499), .B(n1540), .Y(n1290) );
NAND2BX1TS U1160 ( .AN(n484), .B(n2341), .Y(n1450) );
OAI21X1TS U1161 ( .A0(n1065), .A1(n1086), .B0(n1088), .Y(n1070) );
OAI21X1TS U1162 ( .A0(n2994), .A1(n2993), .B0(n2983), .Y(n2985) );
OAI21X2TS U1163 ( .A0(n738), .A1(n503), .B0(n739), .Y(n774) );
OAI21X1TS U1164 ( .A0(n789), .A1(n796), .B0(n797), .Y(n729) );
NAND2X2TS U1165 ( .A(n1254), .B(n1333), .Y(n1255) );
CLKMX2X2TS U1166 ( .A(Add_result[14]), .B(n3836), .S0(n3870), .Y(n295) );
CLKMX2X2TS U1167 ( .A(exp_oper_result[4]), .B(Exp_module_Data_S[4]), .S0(
n3893), .Y(n230) );
NOR2X1TS U1168 ( .A(n483), .B(n2433), .Y(n2655) );
OAI21X1TS U1169 ( .A0(n3693), .A1(n3539), .B0(n3538), .Y(n3544) );
AO21X1TS U1170 ( .A0(n3519), .A1(n3534), .B0(n3518), .Y(n3521) );
NAND2X2TS U1171 ( .A(n3534), .B(n2960), .Y(n3470) );
ADDFHX2TS U1172 ( .A(n900), .B(n899), .CI(n898), .CO(n961), .S(n896) );
NAND3X1TS U1173 ( .A(n3731), .B(n3730), .C(n3729), .Y(n3734) );
AND2X4TS U1174 ( .A(n1374), .B(n1373), .Y(n531) );
NAND2X2TS U1175 ( .A(n2969), .B(n4053), .Y(n3627) );
CLKMX2X2TS U1176 ( .A(exp_oper_result[0]), .B(Exp_module_Data_S[0]), .S0(
n3893), .Y(n234) );
CLKMX2X2TS U1177 ( .A(exp_oper_result[2]), .B(Exp_module_Data_S[2]), .S0(
n3893), .Y(n232) );
CLKMX2X2TS U1178 ( .A(exp_oper_result[3]), .B(Exp_module_Data_S[3]), .S0(
n3893), .Y(n231) );
OAI21X1TS U1179 ( .A0(n3693), .A1(n3689), .B0(n3690), .Y(n3555) );
XOR2X1TS U1180 ( .A(n3693), .B(n3692), .Y(n3694) );
OAI21X1TS U1181 ( .A0(n3184), .A1(n3950), .B0(n3188), .Y(n3957) );
ADDFHX2TS U1182 ( .A(n632), .B(n631), .CI(n630), .CO(n819), .S(n642) );
ADDHX2TS U1183 ( .A(n829), .B(n828), .CO(n847), .S(n821) );
OAI21X1TS U1184 ( .A0(n2826), .A1(n2825), .B0(n2824), .Y(n2827) );
CLKMX2X2TS U1185 ( .A(Add_result[13]), .B(n3839), .S0(n3861), .Y(n296) );
CLKMX2X2TS U1186 ( .A(exp_oper_result[1]), .B(Exp_module_Data_S[1]), .S0(
n3893), .Y(n233) );
OAI21X1TS U1187 ( .A0(n3185), .A1(n3947), .B0(n3186), .Y(n3180) );
CLKMX2X2TS U1188 ( .A(Add_result[12]), .B(n3841), .S0(n3870), .Y(n297) );
NAND2X4TS U1189 ( .A(n1343), .B(n1366), .Y(n1344) );
NOR2X1TS U1190 ( .A(n3952), .B(n3185), .Y(n3181) );
OAI21X1TS U1191 ( .A0(n3953), .A1(n3958), .B0(n3949), .Y(n3182) );
NOR2X4TS U1192 ( .A(FSM_selector_C), .B(n3563), .Y(n3562) );
OR2X2TS U1193 ( .A(n4138), .B(n3563), .Y(n3564) );
ADDHX2TS U1194 ( .A(n591), .B(n590), .CO(n828), .S(n601) );
NOR3X1TS U1195 ( .A(n260), .B(P_Sgf[1]), .C(P_Sgf[0]), .Y(n3727) );
ADDHX2TS U1196 ( .A(n1811), .B(n1810), .CO(n1861), .S(n1879) );
BUFX16TS U1197 ( .A(n1342), .Y(n1716) );
AND2X2TS U1198 ( .A(n2541), .B(n2540), .Y(n2545) );
AO22X1TS U1199 ( .A0(Sgf_normalized_result[4]), .A1(n3933), .B0(
final_result_ieee[4]), .B1(n3932), .Y(n196) );
AO22X1TS U1200 ( .A0(Sgf_normalized_result[5]), .A1(n3933), .B0(
final_result_ieee[5]), .B1(n3932), .Y(n195) );
AO22X1TS U1201 ( .A0(Sgf_normalized_result[6]), .A1(n3933), .B0(
final_result_ieee[6]), .B1(n3932), .Y(n194) );
AO22X1TS U1202 ( .A0(Sgf_normalized_result[7]), .A1(n3933), .B0(
final_result_ieee[7]), .B1(n3932), .Y(n193) );
INVX4TS U1203 ( .A(n949), .Y(n985) );
AO22X1TS U1204 ( .A0(Sgf_normalized_result[9]), .A1(n3933), .B0(
final_result_ieee[9]), .B1(n3934), .Y(n191) );
AO22X1TS U1205 ( .A0(Sgf_normalized_result[8]), .A1(n3933), .B0(
final_result_ieee[8]), .B1(n3932), .Y(n192) );
ADDFHX2TS U1206 ( .A(n594), .B(n593), .CI(n592), .CO(n633), .S(n648) );
NOR2X1TS U1207 ( .A(n356), .B(n3699), .Y(n3967) );
INVX1TS U1208 ( .A(n350), .Y(n3702) );
OR2X2TS U1209 ( .A(n318), .B(n330), .Y(n3974) );
CLKMX2X2TS U1210 ( .A(n3668), .B(n4164), .S0(n4154), .Y(n265) );
AND2X2TS U1211 ( .A(n330), .B(n318), .Y(n3964) );
NOR2X1TS U1212 ( .A(n359), .B(n347), .Y(n3960) );
OR2X2TS U1213 ( .A(n357), .B(n345), .Y(n3189) );
CLKMX2X2TS U1214 ( .A(n3673), .B(n4166), .S0(n4154), .Y(n262) );
CLKMX2X2TS U1215 ( .A(n3688), .B(n4168), .S0(n4155), .Y(n260) );
NOR2X4TS U1216 ( .A(n3815), .B(n4138), .Y(n3569) );
CLKMX2X2TS U1217 ( .A(Add_result[11]), .B(n3843), .S0(n3861), .Y(n298) );
ADDHX2TS U1218 ( .A(n1805), .B(n1804), .CO(n1810), .S(n1899) );
NOR2X1TS U1219 ( .A(n349), .B(n361), .Y(n3956) );
INVX1TS U1220 ( .A(n349), .Y(n3700) );
NAND2BX1TS U1221 ( .AN(n3553), .B(n3552), .Y(n3554) );
CLKMX2X2TS U1222 ( .A(Data_MX[12]), .B(n3922), .S0(n3805), .Y(n356) );
CLKMX2X2TS U1223 ( .A(Data_MY[6]), .B(Op_MY[6]), .S0(n3899), .Y(n318) );
CLKMX2X2TS U1224 ( .A(Data_MX[10]), .B(Op_MX[10]), .S0(n3890), .Y(n354) );
CLKMX2X2TS U1225 ( .A(Data_MY[0]), .B(DP_OP_155J7_124_2038_n788), .S0(n3805),
.Y(n312) );
CLKMX2X2TS U1226 ( .A(Data_MX[1]), .B(n3920), .S0(n3890), .Y(n345) );
CLKMX2X2TS U1227 ( .A(Data_MY[3]), .B(DP_OP_155J7_124_2038_n791), .S0(n3891),
.Y(DP_OP_153J7_122_5442_n1470) );
CLKMX2X2TS U1228 ( .A(Data_MX[13]), .B(DP_OP_154J7_123_2038_n792), .S0(n3899), .Y(n357) );
CLKMX2X2TS U1229 ( .A(Data_MX[22]), .B(Op_MX[22]), .S0(n3890), .Y(n366) );
CLKMX2X2TS U1230 ( .A(Data_MX[18]), .B(Op_MX[18]), .S0(n3803), .Y(n362) );
CLKMX2X2TS U1231 ( .A(Data_MY[15]), .B(DP_OP_154J7_123_2038_n781), .S0(n3891), .Y(DP_OP_153J7_122_5442_n1459) );
CLKMX2X2TS U1232 ( .A(Data_MX[2]), .B(DP_OP_153J7_122_5442_n1508), .S0(n3801), .Y(n346) );
CLKMX2X2TS U1233 ( .A(Data_MY[8]), .B(Op_MY[8]), .S0(n3890), .Y(n320) );
CLKMX2X2TS U1234 ( .A(n3719), .B(n4171), .S0(n4155), .Y(n258) );
CLKMX2X2TS U1235 ( .A(Data_MX[20]), .B(Op_MX[20]), .S0(n3803), .Y(n364) );
CLKMX2X2TS U1236 ( .A(Data_MX[27]), .B(Op_MX[27]), .S0(n3805), .Y(n371) );
CLKMX2X2TS U1237 ( .A(Data_MY[5]), .B(DP_OP_155J7_124_2038_n793), .S0(n3891),
.Y(n4137) );
CLKMX2X2TS U1238 ( .A(Data_MX[14]), .B(DP_OP_153J7_122_5442_n1495), .S0(
n3801), .Y(n358) );
AND2X2TS U1239 ( .A(n2524), .B(n2528), .Y(n3881) );
CLKMX2X2TS U1240 ( .A(Data_MX[3]), .B(DP_OP_155J7_124_2038_n803), .S0(n3804),
.Y(n347) );
CLKMX2X2TS U1241 ( .A(Data_MY[18]), .B(n3901), .S0(n3801), .Y(n330) );
AND2X2TS U1242 ( .A(n2521), .B(n2520), .Y(n3032) );
CLKMX2X2TS U1243 ( .A(n3656), .B(n4165), .S0(n4154), .Y(n264) );
CLKMX2X2TS U1244 ( .A(Data_MY[19]), .B(n4211), .S0(n3801), .Y(n331) );
CLKMX2X2TS U1245 ( .A(Data_MX[28]), .B(Op_MX[28]), .S0(n3805), .Y(n372) );
CLKMX2X2TS U1246 ( .A(Data_MY[12]), .B(n4187), .S0(n3804), .Y(
DP_OP_154J7_123_2038_n778) );
CLKMX2X2TS U1247 ( .A(Data_MY[1]), .B(n4144), .S0(n3891), .Y(n313) );
CLKMX2X2TS U1248 ( .A(Add_result[3]), .B(n3865), .S0(n3870), .Y(n306) );
CLKMX2X2TS U1249 ( .A(Add_result[1]), .B(n3868), .S0(n3861), .Y(n308) );
CLKMX2X2TS U1250 ( .A(Data_MX[26]), .B(Op_MX[26]), .S0(n3805), .Y(n370) );
OR2X2TS U1251 ( .A(n2120), .B(n2119), .Y(n511) );
CLKMX2X2TS U1252 ( .A(Data_MX[25]), .B(Op_MX[25]), .S0(n3801), .Y(n369) );
OAI21X1TS U1253 ( .A0(n3838), .A1(Sgf_normalized_result[0]), .B0(n3705), .Y(
n309) );
NOR2X1TS U1254 ( .A(n4023), .B(n2893), .Y(n2895) );
CLKMX2X2TS U1255 ( .A(Data_MX[8]), .B(Op_MX[8]), .S0(n3890), .Y(n352) );
OAI21X1TS U1256 ( .A0(n4014), .A1(n2893), .B0(n2892), .Y(n2894) );
CLKMX2X2TS U1257 ( .A(Data_MX[5]), .B(Op_MX[5]), .S0(n3803), .Y(n349) );
CLKMX2X2TS U1258 ( .A(Add_result[2]), .B(n3867), .S0(n3861), .Y(n307) );
CLKMX2X2TS U1259 ( .A(Data_MY[24]), .B(Op_MY[24]), .S0(n3805), .Y(n336) );
INVX2TS U1260 ( .A(n2230), .Y(n1932) );
CLKMX2X2TS U1261 ( .A(Data_MX[4]), .B(n3802), .S0(n3805), .Y(n348) );
CLKMX2X2TS U1262 ( .A(Data_MY[2]), .B(Op_MY[2]), .S0(n3801), .Y(n314) );
OR2X2TS U1263 ( .A(n2230), .B(n2229), .Y(n516) );
ADDHX2TS U1264 ( .A(n568), .B(n567), .CO(n590), .S(n608) );
ADDHX2TS U1265 ( .A(n1875), .B(n1874), .CO(n1804), .S(n1906) );
CLKMX2X2TS U1266 ( .A(Data_MY[4]), .B(Op_MY[4]), .S0(n3801), .Y(n316) );
CLKMX2X2TS U1267 ( .A(Data_MY[14]), .B(n535), .S0(n3891), .Y(n3179) );
ADDFHX2TS U1268 ( .A(n1887), .B(n1886), .CI(n1885), .CO(n2665), .S(n2447) );
AND2X2TS U1269 ( .A(n1143), .B(n1142), .Y(n1144) );
INVX4TS U1270 ( .A(n3900), .Y(n3801) );
INVX4TS U1271 ( .A(n1259), .Y(n1218) );
OAI21X1TS U1272 ( .A0(n3720), .A1(n4024), .B0(n4025), .Y(n3672) );
AND2X2TS U1273 ( .A(n2910), .B(n2913), .Y(n2911) );
AND2X2TS U1274 ( .A(n2008), .B(n2231), .Y(n2176) );
OR2X2TS U1275 ( .A(n2523), .B(n2522), .Y(n2524) );
ADDHX2TS U1276 ( .A(n1750), .B(n1749), .CO(n1849), .S(n1818) );
AO22X1TS U1277 ( .A0(n3900), .A1(Data_MY[31]), .B0(n3899), .B1(Op_MY[31]),
.Y(n381) );
ADDFHX2TS U1278 ( .A(n1803), .B(n1802), .CI(n1801), .CO(n2272), .S(n2230) );
ADDFHX2TS U1279 ( .A(n1829), .B(n1828), .CI(n1827), .CO(n1886), .S(n1869) );
OAI21X1TS U1280 ( .A0(n3720), .A1(n4017), .B0(n4018), .Y(n3721) );
OAI21X1TS U1281 ( .A0(n3720), .A1(n4015), .B0(n4016), .Y(n3674) );
OAI21X1TS U1282 ( .A0(n3720), .A1(n4019), .B0(n4020), .Y(n3679) );
OAI21X1TS U1283 ( .A0(n3720), .A1(n3662), .B0(n3661), .Y(n3667) );
ADDFHX2TS U1284 ( .A(n2254), .B(n2253), .CI(n2252), .CO(n2779), .S(n2732) );
AO22X1TS U1285 ( .A0(n3900), .A1(Data_MX[31]), .B0(n3899), .B1(Op_MX[31]),
.Y(n343) );
OR2X2TS U1286 ( .A(n1141), .B(n1140), .Y(n1143) );
ADDFHX2TS U1287 ( .A(n2014), .B(n2013), .CI(n2012), .CO(n2214), .S(n2019) );
NAND2X2TS U1288 ( .A(n1217), .B(n1216), .Y(n1358) );
CMPR22X2TS U1289 ( .A(n1892), .B(n1891), .CO(n2016), .S(n1889) );
NOR2X1TS U1290 ( .A(n3863), .B(Sgf_normalized_result[2]), .Y(n3864) );
INVX1TS U1291 ( .A(n3663), .Y(n3665) );
ADDHX2TS U1292 ( .A(n619), .B(n618), .CO(n678), .S(n559) );
OAI21X1TS U1293 ( .A0(n3663), .A1(n4051), .B0(n3664), .Y(n2890) );
OR2X2TS U1294 ( .A(n2007), .B(n2006), .Y(n2008) );
ADDHX2TS U1295 ( .A(n1780), .B(n1779), .CO(n1783), .S(n2070) );
ADDFHX2TS U1296 ( .A(n1854), .B(n1853), .CI(n1852), .CO(n2041), .S(n1884) );
AND2X2TS U1297 ( .A(n3712), .B(n2886), .Y(n4243) );
CLKMX2X2TS U1298 ( .A(n3723), .B(n4160), .S0(n4155), .Y(n256) );
OAI21X1TS U1299 ( .A0(FSM_selector_B[0]), .A1(n3345), .B0(n3344), .Y(n3346)
);
OAI21X1TS U1300 ( .A0(n4038), .A1(n3658), .B0(n4051), .Y(n3659) );
NOR2X1TS U1301 ( .A(n3808), .B(n3853), .Y(n3809) );
ADDFHX2TS U1302 ( .A(DP_OP_154J7_123_2038_n699), .B(
DP_OP_154J7_123_2038_n684), .CI(n904), .CO(n952), .S(n905) );
OR2X2TS U1303 ( .A(n2907), .B(n4082), .Y(n2913) );
NOR2X1TS U1304 ( .A(n3808), .B(n4134), .Y(n3810) );
INVX16TS U1305 ( .A(n3806), .Y(n405) );
CLKMX2X2TS U1306 ( .A(n4158), .B(n4157), .S0(n4155), .Y(n255) );
CLKMX2X2TS U1307 ( .A(Op_MX[30]), .B(exp_oper_result[7]), .S0(FSM_selector_A), .Y(S_Oper_A_exp[7]) );
CLKMX2X2TS U1308 ( .A(Op_MX[29]), .B(exp_oper_result[6]), .S0(FSM_selector_A), .Y(S_Oper_A_exp[6]) );
CLKMX2X2TS U1309 ( .A(Op_MX[28]), .B(exp_oper_result[5]), .S0(FSM_selector_A), .Y(S_Oper_A_exp[5]) );
CLKMX2X2TS U1310 ( .A(Op_MX[27]), .B(exp_oper_result[4]), .S0(FSM_selector_A), .Y(S_Oper_A_exp[4]) );
CLKMX2X2TS U1311 ( .A(Op_MX[26]), .B(exp_oper_result[3]), .S0(FSM_selector_A), .Y(S_Oper_A_exp[3]) );
INVX12TS U1312 ( .A(Op_MY[19]), .Y(n624) );
NOR2X1TS U1313 ( .A(n4135), .B(n4129), .Y(n3711) );
OR2X2TS U1314 ( .A(exp_oper_result[8]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
NAND2X2TS U1315 ( .A(n3984), .B(DP_OP_153J7_122_5442_n1114), .Y(n1177) );
OAI2BB1X1TS U1316 ( .A0N(n393), .A1N(n4195), .B0(n3495), .Y(n273) );
OR2X6TS U1317 ( .A(n624), .B(n620), .Y(n570) );
CLKINVX12TS U1318 ( .A(DP_OP_154J7_123_2038_n779), .Y(n620) );
XOR2X1TS U1319 ( .A(n2534), .B(n2533), .Y(n2556) );
AO21X4TS U1320 ( .A0(n2102), .A1(n2104), .B0(n1987), .Y(n2066) );
NOR2X4TS U1321 ( .A(n396), .B(n397), .Y(n2068) );
OR2X8TS U1322 ( .A(n2714), .B(n2713), .Y(n2739) );
ADDFHX2TS U1323 ( .A(n640), .B(n639), .CI(n638), .CO(n925), .S(n673) );
ADDFHX2TS U1324 ( .A(n907), .B(n906), .CI(n905), .CO(n950), .S(n910) );
NOR2X6TS U1325 ( .A(n3903), .B(DP_OP_154J7_123_2038_n781), .Y(n542) );
NOR2X4TS U1326 ( .A(n423), .B(n1979), .Y(n1903) );
NOR2X4TS U1327 ( .A(n2168), .B(n2167), .Y(n2795) );
NOR2X4TS U1328 ( .A(n620), .B(DP_OP_154J7_123_2038_n634), .Y(n679) );
NOR2X2TS U1329 ( .A(n1981), .B(n2027), .Y(n1942) );
NAND2BX1TS U1330 ( .AN(n3491), .B(n3490), .Y(n3492) );
NOR2X2TS U1331 ( .A(n3484), .B(n3491), .Y(n2965) );
ADDFX2TS U1332 ( .A(n2360), .B(n2359), .CI(n2358), .CO(n3094), .S(n2363) );
BUFX8TS U1333 ( .A(Op_MX[9]), .Y(n3921) );
ADDFX2TS U1334 ( .A(n1878), .B(n1877), .CI(n1876), .CO(n2412), .S(n2273) );
ADDFX2TS U1335 ( .A(n2347), .B(n3407), .CI(n2346), .CO(n3088), .S(n2361) );
BUFX3TS U1336 ( .A(n1243), .Y(n1247) );
ADDFHX4TS U1337 ( .A(n2350), .B(n2349), .CI(n2348), .CO(n3086), .S(n2364) );
NAND2X8TS U1338 ( .A(n2868), .B(n1470), .Y(n3017) );
ADDFHX2TS U1339 ( .A(n976), .B(n975), .CI(n974), .CO(n1018), .S(n990) );
CLKMX2X2TS U1340 ( .A(n3895), .B(Exp_module_Overflow_flag_A), .S0(n4213),
.Y(n225) );
NAND2X2TS U1341 ( .A(n2527), .B(n2526), .Y(n2529) );
OAI21X2TS U1342 ( .A0(n3781), .A1(n3752), .B0(n3751), .Y(n3753) );
NAND2X4TS U1343 ( .A(DP_OP_155J7_124_2038_n794), .B(n3183), .Y(n1792) );
ADDFHX4TS U1344 ( .A(n851), .B(n850), .CI(n849), .CO(n913), .S(n857) );
INVX2TS U1345 ( .A(n1482), .Y(n1485) );
XNOR2X4TS U1346 ( .A(n1441), .B(Op_MY[11]), .Y(n1446) );
XNOR2X2TS U1347 ( .A(n2341), .B(n1649), .Y(n1502) );
CLKXOR2X4TS U1348 ( .A(n1195), .B(n1301), .Y(n1189) );
AND2X6TS U1349 ( .A(n624), .B(n620), .Y(n569) );
CMPR22X2TS U1350 ( .A(n946), .B(n945), .CO(n973), .S(n939) );
INVX8TS U1351 ( .A(n500), .Y(n1301) );
ADDFHX4TS U1352 ( .A(n3144), .B(n3143), .CI(n3142), .CO(n3165), .S(n3116) );
ADDFHX2TS U1353 ( .A(n887), .B(n886), .CI(n885), .CO(n957), .S(n894) );
ADDFX2TS U1354 ( .A(n861), .B(n860), .CI(n859), .CO(n885), .S(n864) );
NOR2X6TS U1355 ( .A(n2610), .B(n2609), .Y(n2625) );
NAND2X4TS U1356 ( .A(n659), .B(n661), .Y(n548) );
INVX2TS U1357 ( .A(n756), .Y(n671) );
OAI21X4TS U1358 ( .A0(n783), .A1(n786), .B0(n784), .Y(n920) );
ADDFX2TS U1359 ( .A(n970), .B(n969), .CI(n968), .CO(n1004), .S(n995) );
ADDFHX2TS U1360 ( .A(n903), .B(n902), .CI(n901), .CO(n960), .S(n914) );
ADDFX2TS U1361 ( .A(n563), .B(n562), .CI(n561), .CO(n1029), .S(n1028) );
ADDFHX2TS U1362 ( .A(n941), .B(n940), .CI(n939), .CO(n970), .S(n958) );
INVX12TS U1363 ( .A(n1152), .Y(n2312) );
ADDFHX4TS U1364 ( .A(n917), .B(n916), .CI(n915), .CO(n933), .S(n931) );
ADDFHX4TS U1365 ( .A(n710), .B(n709), .CI(n708), .CO(n866), .S(n811) );
ADDFHX4TS U1366 ( .A(n2747), .B(n2746), .CI(n2745), .CO(n2811), .S(n2713) );
OR2X4TS U1367 ( .A(n754), .B(n753), .Y(n2470) );
ADDFX2TS U1368 ( .A(n658), .B(n657), .CI(n656), .CO(n650), .S(n665) );
CMPR22X2TS U1369 ( .A(n1504), .B(n1503), .CO(n1532), .S(n1510) );
NOR2X2TS U1370 ( .A(n423), .B(n2040), .Y(n1816) );
ADDFHX2TS U1371 ( .A(n2196), .B(n2195), .CI(n2194), .CO(n2239), .S(n2222) );
AOI21X2TS U1372 ( .A0(n2633), .A1(n509), .B0(n1323), .Y(n2691) );
XNOR2X2TS U1373 ( .A(n2634), .B(n509), .Y(n2712) );
AOI21X1TS U1374 ( .A0(n2948), .A1(n2910), .B0(n2914), .Y(n2909) );
AOI21X2TS U1375 ( .A0(n475), .A1(n3750), .B0(n3749), .Y(n3751) );
ADDFHX4TS U1376 ( .A(n1733), .B(n1732), .CI(n1731), .CO(n1735), .S(n1689) );
CMPR22X2TS U1377 ( .A(n1594), .B(n1593), .CO(n1670), .S(n1615) );
NAND2X6TS U1378 ( .A(DP_OP_156J7_125_3370_n211), .B(
DP_OP_156J7_125_3370_n213), .Y(DP_OP_156J7_125_3370_n81) );
NOR2X6TS U1379 ( .A(n3293), .B(n2420), .Y(n2423) );
ADDFHX4TS U1380 ( .A(n2049), .B(n2048), .CI(n2047), .CO(n2204), .S(n2009) );
XNOR2X4TS U1381 ( .A(n2118), .B(n2117), .Y(n2589) );
XOR2X4TS U1382 ( .A(n2709), .B(n2708), .Y(n3879) );
NOR2X4TS U1383 ( .A(DP_OP_155J7_124_2038_n798), .B(n3802), .Y(n1840) );
INVX6TS U1384 ( .A(n1836), .Y(n2022) );
ADDFHX4TS U1385 ( .A(n2221), .B(n2220), .CI(n2219), .CO(n2241), .S(n2205) );
ADDFHX2TS U1386 ( .A(n2036), .B(n2035), .CI(n2034), .CO(n2220), .S(n2051) );
NAND2X4TS U1387 ( .A(n435), .B(n1938), .Y(n1790) );
INVX12TS U1388 ( .A(n1753), .Y(n1789) );
OAI21X4TS U1389 ( .A0(n2294), .A1(n3041), .B0(n2295), .Y(n1638) );
ADDFHX2TS U1390 ( .A(n1612), .B(n1611), .CI(n1610), .CO(n1686), .S(n1631) );
OAI22X2TS U1391 ( .A0(n1434), .A1(n1497), .B0(n1498), .B1(n425), .Y(n1495)
);
ADDFHX2TS U1392 ( .A(n3163), .B(n3162), .CI(n3161), .CO(n3190), .S(n3142) );
ADDFHX2TS U1393 ( .A(n3096), .B(n3095), .CI(n3094), .CO(n3163), .S(n3092) );
XNOR2X2TS U1394 ( .A(n2332), .B(n1421), .Y(n1506) );
ADDFHX2TS U1395 ( .A(n1665), .B(n1664), .CI(n1663), .CO(n1719), .S(n1662) );
ADDFX2TS U1396 ( .A(n1618), .B(n1617), .CI(n1616), .CO(n3394), .S(n3374) );
NAND2X4TS U1397 ( .A(n2174), .B(n2173), .Y(n2850) );
ADDFHX2TS U1398 ( .A(n652), .B(n651), .CI(n650), .CO(n644), .S(n667) );
XNOR2X4TS U1399 ( .A(n2500), .B(n2499), .Y(Sgf_operation_EVEN1_Q_left[8]) );
INVX6TS U1400 ( .A(n580), .Y(n480) );
NAND2X4TS U1401 ( .A(n1545), .B(n1546), .Y(n1547) );
AOI21X2TS U1402 ( .A0(n3288), .A1(n3286), .B0(n2554), .Y(n3256) );
ADDFHX2TS U1403 ( .A(n1314), .B(n1313), .CI(n2285), .CO(n1307), .S(n1322) );
OAI22X2TS U1404 ( .A0(n1289), .A1(n1596), .B0(n484), .B1(n1597), .Y(n1313)
);
NOR2X8TS U1405 ( .A(n3165), .B(n3164), .Y(n3208) );
ADDFHX4TS U1406 ( .A(n2242), .B(n2241), .CI(n2240), .CO(n2388), .S(n2265) );
CLKXOR2X4TS U1407 ( .A(n1561), .B(n1347), .Y(n1348) );
XNOR2X2TS U1408 ( .A(n1348), .B(n2341), .Y(n1655) );
ADDFHX4TS U1409 ( .A(n2001), .B(n2000), .CI(n1999), .CO(n2002), .S(n1994) );
ADDFHX4TS U1410 ( .A(n1931), .B(n1930), .CI(n1929), .CO(n1922), .S(n2000) );
CMPR22X2TS U1411 ( .A(n1873), .B(n1872), .CO(n1878), .S(n2229) );
NOR2X2TS U1412 ( .A(n422), .B(n1755), .Y(n1873) );
NOR2X2TS U1413 ( .A(n417), .B(n1979), .Y(n1813) );
NAND2X4TS U1414 ( .A(n637), .B(n636), .Y(n918) );
ADDFHX2TS U1415 ( .A(n927), .B(n926), .CI(n925), .CO(n928), .S(n637) );
ADDFHX2TS U1416 ( .A(n1730), .B(n1729), .CI(n1728), .CO(n2348), .S(n1733) );
OAI21X4TS U1417 ( .A0(n2688), .A1(n2691), .B0(n2689), .Y(n2743) );
XNOR2X2TS U1418 ( .A(n2332), .B(n2341), .Y(n1602) );
NOR2X4TS U1419 ( .A(n1135), .B(n1114), .Y(n935) );
ADDFHX4TS U1420 ( .A(n992), .B(n991), .CI(n990), .CO(n1002), .S(n993) );
ADDFHX4TS U1421 ( .A(n958), .B(n957), .CI(n956), .CO(n992), .S(n938) );
OAI21X2TS U1422 ( .A0(n1080), .A1(n1109), .B0(n1079), .Y(n1085) );
INVX12TS U1423 ( .A(n988), .Y(n1010) );
XNOR2X4TS U1424 ( .A(n1408), .B(n1595), .Y(n1522) );
ADDFHX2TS U1425 ( .A(n1525), .B(n1524), .CI(n1523), .CO(n1563), .S(n1528) );
ADDFX2TS U1426 ( .A(n1083), .B(n1082), .CI(n1081), .CO(n1084), .S(n1060) );
XNOR2X4TS U1427 ( .A(n1519), .B(n1410), .Y(n1646) );
XNOR2X4TS U1428 ( .A(n1519), .B(n1712), .Y(n1548) );
OAI22X4TS U1429 ( .A0(n1591), .A1(n1550), .B0(n1646), .B1(n1714), .Y(n1645)
);
XNOR2X4TS U1430 ( .A(n3011), .B(n2873), .Y(n3023) );
OR2X8TS U1431 ( .A(n3440), .B(n3439), .Y(n3444) );
NAND2X4TS U1432 ( .A(n2505), .B(n1305), .Y(n2503) );
XNOR2X4TS U1433 ( .A(n1283), .B(n1545), .Y(n1300) );
OR2X8TS U1434 ( .A(n2814), .B(n2813), .Y(n532) );
BUFX12TS U1435 ( .A(n1198), .Y(n1421) );
XNOR2X4TS U1436 ( .A(n1444), .B(n1438), .Y(n1389) );
AOI21X2TS U1437 ( .A0(n2804), .A1(n2803), .B0(n2802), .Y(n2809) );
ADDFHX2TS U1438 ( .A(n1642), .B(n1641), .CI(n1640), .CO(n2696), .S(n2630) );
ADDFHX2TS U1439 ( .A(n2208), .B(n2207), .CI(n2206), .CO(n2252), .S(n2213) );
NAND2X4TS U1440 ( .A(n2269), .B(n2268), .Y(n2382) );
NAND2X4TS U1441 ( .A(n802), .B(n801), .Y(n2684) );
XOR2X4TS U1442 ( .A(n787), .B(n786), .Y(n802) );
AOI21X4TS U1443 ( .A0(n2686), .A1(n2685), .B0(n803), .Y(n1126) );
ADDFHX4TS U1444 ( .A(n2033), .B(n2032), .CI(n2031), .CO(n2221), .S(n2048) );
ADDFHX4TS U1445 ( .A(n2432), .B(n2431), .CI(n2430), .CO(n2442), .S(n2408) );
ADDFHX2TS U1446 ( .A(n2440), .B(n2439), .CI(n2438), .CO(n2653), .S(n2431) );
OAI2BB2X2TS U1447 ( .B0(n2021), .B1(n2433), .A0N(n1836), .A1N(n1776), .Y(
n2201) );
AND2X8TS U1448 ( .A(Op_MX[7]), .B(DP_OP_155J7_124_2038_n801), .Y(n1753) );
ADDFHX2TS U1449 ( .A(n3090), .B(n3089), .CI(n3088), .CO(n3144), .S(n3087) );
OAI22X2TS U1450 ( .A0(n3017), .A1(n2325), .B0(n2868), .B1(n2869), .Y(n3014)
);
NOR2X8TS U1451 ( .A(n2269), .B(n2268), .Y(n2384) );
ADDFHX4TS U1452 ( .A(n2145), .B(n2144), .CI(n2143), .CO(n2258), .S(n2209) );
NAND2X4TS U1453 ( .A(n2834), .B(n3453), .Y(n3321) );
NOR2X4TS U1454 ( .A(n3470), .B(n2967), .Y(n2954) );
NAND2X4TS U1455 ( .A(n3483), .B(n2965), .Y(n2967) );
ADDFHX4TS U1456 ( .A(n1019), .B(n1018), .CI(n1017), .CO(n1051), .S(n1003) );
ADDFHX2TS U1457 ( .A(n725), .B(n724), .CI(n723), .CO(n726), .S(n721) );
ADDFHX4TS U1458 ( .A(n2205), .B(n2204), .CI(n2203), .CO(n2266), .S(n2191) );
ADDFHX4TS U1459 ( .A(n2052), .B(n2051), .CI(n2050), .CO(n2203), .S(n2054) );
ADDFHX4TS U1460 ( .A(n1868), .B(n1867), .CI(n1866), .CO(n2078), .S(n2076) );
NOR2X6TS U1461 ( .A(n1530), .B(n1529), .Y(n3002) );
NAND2X4TS U1462 ( .A(n3004), .B(n3003), .Y(n3006) );
XNOR2X2TS U1463 ( .A(n1622), .B(n1540), .Y(n1430) );
NOR2X4TS U1464 ( .A(n734), .B(n733), .Y(n1125) );
NAND2X4TS U1465 ( .A(Op_MX[16]), .B(Op_MX[4]), .Y(n1400) );
XOR2X4TS U1466 ( .A(n1215), .B(n1214), .Y(n1538) );
AOI21X4TS U1467 ( .A0(n3550), .A1(n3314), .B0(add_x_19_n284), .Y(
add_x_19_n282) );
AOI21X4TS U1468 ( .A0(n921), .A1(n920), .B0(n919), .Y(n1130) );
NAND2X4TS U1469 ( .A(n1637), .B(n1636), .Y(n2295) );
ADDFHX4TS U1470 ( .A(n894), .B(n893), .CI(n892), .CO(n937), .S(n915) );
ADDFHX4TS U1471 ( .A(n864), .B(n863), .CI(n862), .CO(n893), .S(n923) );
ADDFHX2TS U1472 ( .A(n814), .B(n813), .CI(n812), .CO(n868), .S(n808) );
NAND2X2TS U1473 ( .A(n2690), .B(n2689), .Y(n2692) );
NAND2X2TS U1474 ( .A(n1244), .B(n1247), .Y(n1245) );
XNOR2X4TS U1475 ( .A(n1286), .B(n1285), .Y(n2548) );
XNOR2X4TS U1476 ( .A(n1341), .B(n1340), .Y(n1342) );
INVX8TS U1477 ( .A(n1486), .Y(n1340) );
ADDFHX2TS U1478 ( .A(n2261), .B(n2260), .CI(n2259), .CO(n2391), .S(n2250) );
OAI22X2TS U1479 ( .A0(n2243), .A1(n2396), .B0(n2215), .B1(n2433), .Y(n2259)
);
NAND2X6TS U1480 ( .A(n2425), .B(n2424), .Y(n2669) );
NAND2X4TS U1481 ( .A(n4047), .B(n3741), .Y(n3641) );
NOR2X2TS U1482 ( .A(n2969), .B(n4053), .Y(n3586) );
NAND2X6TS U1483 ( .A(n2814), .B(n2813), .Y(n2841) );
ADDFHX4TS U1484 ( .A(Op_MY[9]), .B(n3903), .CI(n1192), .CO(n1438), .S(n1195)
);
CMPR22X2TS U1485 ( .A(n1354), .B(n1353), .CO(n2378), .S(n2375) );
ADDFHX2TS U1486 ( .A(n635), .B(n634), .CI(n633), .CO(n832), .S(n641) );
ADDFHX4TS U1487 ( .A(n2366), .B(n2365), .CI(n2364), .CO(n2367), .S(n1734) );
ADDFHX4TS U1488 ( .A(n2363), .B(n2362), .CI(n2361), .CO(n3091), .S(n2366) );
NAND2X4TS U1489 ( .A(n1734), .B(n1735), .Y(n2320) );
XOR2X4TS U1490 ( .A(n1262), .B(n1261), .Y(n1605) );
NAND2X4TS U1491 ( .A(n1260), .B(n1334), .Y(n1261) );
INVX4TS U1492 ( .A(n3306), .Y(n3307) );
NOR2X6TS U1493 ( .A(n1396), .B(n1395), .Y(n2790) );
NOR2X4TS U1494 ( .A(n2507), .B(n2506), .Y(n2530) );
CMPR22X2TS U1495 ( .A(n1385), .B(n1384), .CO(n2501), .S(n2507) );
NOR2X8TS U1496 ( .A(n3130), .B(n3133), .Y(n3136) );
XNOR2X4TS U1497 ( .A(n1716), .B(Op_MX[11]), .Y(n1345) );
ADDFHX4TS U1498 ( .A(n3379), .B(n3378), .CI(add_x_19_n59), .CO(n3393), .S(
n3438) );
ADDFHX2TS U1499 ( .A(n944), .B(n943), .CI(n942), .CO(n969), .S(n956) );
NOR2X8TS U1500 ( .A(n2675), .B(n2674), .Y(n2817) );
ADDFHX4TS U1501 ( .A(n2011), .B(n2010), .CI(n2009), .CO(n2193), .S(n2053) );
OAI21X4TS U1502 ( .A0(n3327), .A1(n3547), .B0(n3328), .Y(add_x_19_n284) );
ADDFHX2TS U1503 ( .A(n1357), .B(n1356), .CI(n1355), .CO(n1429), .S(n1394) );
ADDFHX4TS U1504 ( .A(n1394), .B(n1393), .CI(n1392), .CO(n1395), .S(n1327) );
NAND2X6TS U1505 ( .A(n2884), .B(n2883), .Y(n3302) );
INVX8TS U1506 ( .A(n3244), .Y(n3128) );
ADDFHX4TS U1507 ( .A(n955), .B(n954), .CI(n953), .CO(n994), .S(n936) );
ADDFHX4TS U1508 ( .A(n961), .B(n960), .CI(n959), .CO(n991), .S(n954) );
NOR2X8TS U1509 ( .A(n999), .B(n998), .Y(n1035) );
ADDFHX4TS U1510 ( .A(n810), .B(n809), .CI(n808), .CO(n1067), .S(n1030) );
NOR2X4TS U1511 ( .A(n1071), .B(n1074), .Y(n1077) );
NOR2X8TS U1512 ( .A(n1637), .B(n1636), .Y(n2294) );
ADDFHX4TS U1513 ( .A(n1687), .B(n1686), .CI(n1685), .CO(n1688), .S(n1637) );
OAI22X4TS U1514 ( .A0(n1434), .A1(n425), .B0(n1376), .B1(n1497), .Y(n1453)
);
OAI22X2TS U1515 ( .A0(n2243), .A1(n2202), .B0(n2022), .B1(n2255), .Y(n2036)
);
INVX12TS U1516 ( .A(n1845), .Y(n2243) );
NAND2X2TS U1517 ( .A(DP_OP_155J7_124_2038_n798), .B(n3802), .Y(n1841) );
OAI21X4TS U1518 ( .A0(n2134), .A1(n2137), .B0(n2135), .Y(n2154) );
AOI21X2TS U1519 ( .A0(n3047), .A1(n3046), .B0(n3045), .Y(n3051) );
AOI21X4TS U1520 ( .A0(n2852), .A1(n2851), .B0(n2175), .Y(n3020) );
AOI21X4TS U1521 ( .A0(n2065), .A1(n2066), .B0(n1990), .Y(n2137) );
OAI21X4TS U1522 ( .A0(n3044), .A1(n3040), .B0(n3041), .Y(n2298) );
NOR2X4TS U1523 ( .A(Op_MX[16]), .B(Op_MX[4]), .Y(n1401) );
XNOR2X4TS U1524 ( .A(n1348), .B(n1595), .Y(n1409) );
NOR2X2TS U1525 ( .A(n3333), .B(n3271), .Y(add_x_19_n275) );
OAI21X2TS U1526 ( .A0(n3271), .A1(n3332), .B0(n3272), .Y(add_x_19_n276) );
NOR2X8TS U1527 ( .A(n3362), .B(n3361), .Y(DP_OP_156J7_125_3370_n83) );
ADDFHX4TS U1528 ( .A(n924), .B(n923), .CI(n922), .CO(n930), .S(n929) );
ADDFHX4TS U1529 ( .A(n869), .B(n868), .CI(n867), .CO(n1093), .S(n1066) );
INVX4TS U1530 ( .A(n3239), .Y(add_x_19_n106) );
XNOR2X4TS U1531 ( .A(n2155), .B(n2154), .Y(n2168) );
NAND2X4TS U1532 ( .A(n3032), .B(n3031), .Y(n3316) );
CLKINVX6TS U1533 ( .A(Sgf_operation_EVEN1_Q_left[13]), .Y(n3059) );
ADDFHX4TS U1534 ( .A(n3438), .B(n3437), .CI(n3436), .CO(
DP_OP_156J7_125_3370_n198), .S(DP_OP_156J7_125_3370_n199) );
NAND2X4TS U1535 ( .A(n3137), .B(n3136), .Y(n3138) );
OAI22X2TS U1536 ( .A0(n1541), .A1(n1676), .B0(n1677), .B1(n1501), .Y(n1535)
);
XNOR2X4TS U1537 ( .A(n1681), .B(n1540), .Y(n1501) );
NOR2X4TS U1538 ( .A(n662), .B(n888), .Y(n605) );
XOR2X4TS U1539 ( .A(n2786), .B(n2767), .Y(n2834) );
NOR2X8TS U1540 ( .A(n1100), .B(n1099), .Y(n2305) );
NOR2X4TS U1541 ( .A(n2817), .B(n2720), .Y(n2722) );
XOR2X4TS U1542 ( .A(n2300), .B(n2315), .Y(DP_OP_156J7_125_3370_n211) );
NAND2X4TS U1543 ( .A(n1117), .B(n1116), .Y(n1118) );
OAI21X4TS U1544 ( .A0(n1130), .A1(n1127), .B0(n1128), .Y(n1113) );
OAI21X4TS U1545 ( .A0(n3000), .A1(n2997), .B0(n2998), .Y(n2287) );
ADDFHX4TS U1546 ( .A(n3360), .B(n3359), .CI(n3358), .CO(n3361), .S(n3440) );
XNOR2X4TS U1547 ( .A(n1085), .B(n1084), .Y(n1100) );
ADDFHX4TS U1548 ( .A(n1053), .B(n1052), .CI(n1051), .CO(n1061), .S(n1020) );
ADDFHX4TS U1549 ( .A(n1004), .B(n1003), .CI(n1002), .CO(n1021), .S(n999) );
XNOR2X4TS U1550 ( .A(n2843), .B(n2815), .Y(n2835) );
NAND2X4TS U1551 ( .A(n532), .B(n2841), .Y(n2815) );
NAND2X2TS U1552 ( .A(n734), .B(n733), .Y(n1124) );
XNOR2X4TS U1553 ( .A(n674), .B(n920), .Y(n734) );
NAND2X2TS U1554 ( .A(n921), .B(n918), .Y(n674) );
NOR2X6TS U1555 ( .A(n3031), .B(n3032), .Y(n3315) );
OAI21X2TS U1556 ( .A0(n1756), .A1(DP_OP_155J7_124_2038_n388), .B0(n1832),
.Y(n1757) );
XNOR2X4TS U1557 ( .A(n2853), .B(n2852), .Y(n3282) );
XNOR2X4TS U1558 ( .A(n3030), .B(n3036), .Y(n3031) );
NAND2X4TS U1559 ( .A(n1755), .B(n2040), .Y(n1833) );
CLKINVX12TS U1560 ( .A(n3921), .Y(n1755) );
XOR2X4TS U1561 ( .A(n2172), .B(n2171), .Y(n2174) );
NAND2BX4TS U1562 ( .AN(n2170), .B(n2169), .Y(n2172) );
NAND2X4TS U1563 ( .A(n2296), .B(n2295), .Y(n2297) );
XOR2X4TS U1564 ( .A(n2318), .B(n2319), .Y(n2300) );
XNOR2X4TS U1565 ( .A(n1119), .B(n1118), .Y(n1147) );
OAI22X2TS U1566 ( .A0(n1547), .A1(n1284), .B0(n1300), .B1(n1546), .Y(n2505)
);
INVX4TS U1567 ( .A(n2737), .Y(n2738) );
OAI21X1TS U1568 ( .A0(n3866), .A1(n4132), .B0(n3807), .Y(n3852) );
NAND2X1TS U1569 ( .A(n519), .B(n3290), .Y(n3292) );
OAI21X1TS U1570 ( .A0(n1043), .A1(n1040), .B0(n1041), .Y(n1091) );
OR2X1TS U1571 ( .A(n1168), .B(n1167), .Y(n2990) );
NAND2X6TS U1572 ( .A(n1153), .B(n2312), .Y(n1154) );
INVX4TS U1573 ( .A(n1790), .Y(n1754) );
INVX2TS U1574 ( .A(n2229), .Y(n1908) );
ADDHX1TS U1575 ( .A(DP_OP_154J7_123_2038_n795), .B(DP_OP_154J7_123_2038_n687), .CO(n583), .S(n566) );
ADDFHX2TS U1576 ( .A(n848), .B(n847), .CI(n846), .CO(n901), .S(n849) );
XOR2X1TS U1577 ( .A(n1280), .B(DP_OP_153J7_122_5442_n451), .Y(n1263) );
NOR2X1TS U1578 ( .A(n2434), .B(n2398), .Y(n2436) );
NOR2X4TS U1579 ( .A(n2003), .B(n2002), .Y(n2170) );
OAI22X1TS U1580 ( .A0(n450), .A1(n888), .B0(n662), .B1(n963), .Y(n611) );
ADDFHX2TS U1581 ( .A(n614), .B(n613), .CI(n1141), .CO(n655), .S(n656) );
ADDFHX2TS U1582 ( .A(n3108), .B(n3107), .CI(n3106), .CO(n3155), .S(n3103) );
AOI21X1TS U1583 ( .A0(n516), .A1(n2277), .B0(n2276), .Y(n2417) );
NAND2X2TS U1584 ( .A(n1465), .B(n1464), .Y(n1473) );
OR2X6TS U1585 ( .A(n1459), .B(n1458), .Y(n2845) );
OAI21X2TS U1586 ( .A0(n2114), .A1(n2571), .B0(n2115), .Y(n2079) );
OAI21X2TS U1587 ( .A0(n743), .A1(n2478), .B0(n744), .Y(n697) );
OAI22X2TS U1588 ( .A0(n1701), .A1(n2337), .B0(n2336), .B1(n2339), .Y(n3111)
);
OAI21X2TS U1589 ( .A0(n2417), .A1(n2416), .B0(n2415), .Y(n2663) );
ADDFHX2TS U1590 ( .A(n1621), .B(n1679), .CI(n1620), .CO(n1673), .S(n1616) );
NAND2X1TS U1591 ( .A(n410), .B(n2891), .Y(n2893) );
AOI21X1TS U1592 ( .A0(n3810), .A1(n3852), .B0(n3809), .Y(n3844) );
NOR2XLTS U1593 ( .A(FSM_selector_B[1]), .B(Op_MY[23]), .Y(n3345) );
NAND2X2TS U1594 ( .A(n757), .B(n756), .Y(n759) );
AO21X1TS U1595 ( .A0(n1677), .A1(n1676), .B0(n1675), .Y(n1724) );
NOR2X1TS U1596 ( .A(n3399), .B(n3398), .Y(n3414) );
NOR2X4TS U1597 ( .A(n2879), .B(n2878), .Y(n3028) );
INVX2TS U1598 ( .A(n3852), .Y(n3860) );
INVX2TS U1599 ( .A(n3844), .Y(n3850) );
MX2X1TS U1600 ( .A(Op_MX[24]), .B(exp_oper_result[1]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[1]) );
NAND2X4TS U1601 ( .A(n3139), .B(n424), .Y(n3140) );
INVX2TS U1602 ( .A(n3138), .Y(n3139) );
INVX4TS U1603 ( .A(n3126), .Y(n3378) );
NAND2X1TS U1604 ( .A(n3070), .B(n3368), .Y(n3071) );
AO21XLTS U1605 ( .A0(n4063), .A1(n410), .B0(n4059), .Y(n3652) );
NOR2X2TS U1606 ( .A(n3525), .B(n3527), .Y(n3301) );
INVX2TS U1607 ( .A(n3305), .Y(n3235) );
INVX2TS U1608 ( .A(n2081), .Y(n2033) );
ADDFX2TS U1609 ( .A(n2218), .B(n2217), .CI(n2216), .CO(n2249), .S(n2219) );
INVX2TS U1610 ( .A(n2084), .Y(n2217) );
INVX2TS U1611 ( .A(n2083), .Y(n2218) );
INVX2TS U1612 ( .A(n2077), .Y(n1839) );
INVX2TS U1613 ( .A(n2210), .Y(n2246) );
ADDFHX2TS U1614 ( .A(n2199), .B(n2198), .CI(n2197), .CO(n2238), .S(n2224) );
INVX2TS U1615 ( .A(n2731), .Y(n2260) );
ADDFX2TS U1616 ( .A(n2251), .B(n2250), .CI(n2249), .CO(n2406), .S(n2242) );
INVX2TS U1617 ( .A(n555), .Y(n838) );
INVX2TS U1618 ( .A(n539), .Y(n989) );
NAND2BX1TS U1619 ( .AN(n827), .B(n507), .Y(n565) );
OR2X2TS U1620 ( .A(n405), .B(DP_OP_154J7_123_2038_n628), .Y(n836) );
ADDHX1TS U1621 ( .A(Op_MX[7]), .B(Op_MX[19]), .CO(n1241), .S(n1205) );
INVX4TS U1622 ( .A(n1769), .Y(n2434) );
INVX2TS U1623 ( .A(n1776), .Y(n2396) );
NAND2X2TS U1624 ( .A(n1552), .B(n1210), .Y(n1235) );
NOR2X4TS U1625 ( .A(n1551), .B(n1205), .Y(n1209) );
XNOR2X2TS U1626 ( .A(n1545), .B(n1187), .Y(n1265) );
NAND2X1TS U1627 ( .A(n1339), .B(n1400), .Y(n1341) );
XNOR2X2TS U1628 ( .A(n2324), .B(n1410), .Y(n1591) );
INVX2TS U1629 ( .A(n1552), .Y(n1592) );
INVX4TS U1630 ( .A(n2327), .Y(n1712) );
INVX2TS U1631 ( .A(n2075), .Y(n1881) );
INVX2TS U1632 ( .A(n2412), .Y(n1880) );
OAI22X1TS U1633 ( .A0(n2021), .A1(n2202), .B0(n453), .B1(n2255), .Y(n1807)
);
INVX2TS U1634 ( .A(n1855), .Y(n2023) );
ADDFX2TS U1635 ( .A(n2392), .B(n2391), .CI(n2390), .CO(n2432), .S(n2405) );
ADDFHX2TS U1636 ( .A(n2407), .B(n2406), .CI(n2405), .CO(n2430), .S(n2387) );
OAI22X1TS U1637 ( .A0(n2021), .A1(n2027), .B0(n453), .B1(n2211), .Y(n1916)
);
ADDFHX2TS U1638 ( .A(n1914), .B(n1913), .CI(n1912), .CO(n1927), .S(n1960) );
INVX2TS U1639 ( .A(n2273), .Y(n1912) );
OAI22X1TS U1640 ( .A0(n481), .A1(n947), .B0(n446), .B1(n980), .Y(n902) );
INVX2TS U1641 ( .A(n845), .Y(n903) );
INVX2TS U1642 ( .A(n1067), .Y(n860) );
ADDFX2TS U1643 ( .A(n878), .B(n877), .CI(n876), .CO(n895), .S(n863) );
OAI22X1TS U1644 ( .A0(n481), .A1(n888), .B0(n446), .B1(n963), .Y(n876) );
INVX2TS U1645 ( .A(n1066), .Y(n877) );
INVX4TS U1646 ( .A(n580), .Y(n881) );
INVX2TS U1647 ( .A(n574), .Y(n980) );
INVX2TS U1648 ( .A(n582), .Y(n963) );
NAND2X1TS U1649 ( .A(Op_MX[22]), .B(Op_MX[10]), .Y(n1366) );
OR2X4TS U1650 ( .A(n1552), .B(n1210), .Y(n1238) );
INVX2TS U1651 ( .A(n1235), .Y(n1236) );
NAND2X4TS U1652 ( .A(DP_OP_153J7_122_5442_n1495), .B(
DP_OP_153J7_122_5442_n1508), .Y(n1243) );
OAI22X1TS U1653 ( .A0(n1267), .A1(n1596), .B0(n1289), .B1(n1597), .Y(n1312)
);
OAI22X1TS U1654 ( .A0(n1349), .A1(n1596), .B0(n1267), .B1(n1597), .Y(n1355)
);
OAI22X1TS U1655 ( .A0(n1505), .A1(n1213), .B0(n2335), .B1(n1378), .Y(n1357)
);
INVX2TS U1656 ( .A(n2076), .Y(n1910) );
NOR2X1TS U1657 ( .A(n417), .B(n2040), .Y(n2043) );
ADDFHX2TS U1658 ( .A(n2093), .B(n2092), .CI(n2091), .CO(n2143), .S(n2088) );
OAI22X1TS U1659 ( .A0(n1550), .A1(n1303), .B0(n1714), .B1(n1382), .Y(n1384)
);
AND2X2TS U1660 ( .A(n1775), .B(n1792), .Y(n1777) );
OAI21X2TS U1661 ( .A0(DP_OP_153J7_122_5442_n1181), .A1(n1400), .B0(
DP_OP_153J7_122_5442_n1182), .Y(n1483) );
NOR2X2TS U1662 ( .A(DP_OP_155J7_124_2038_n725), .B(n398), .Y(n2007) );
INVX2TS U1663 ( .A(n2505), .Y(n1286) );
AOI21X2TS U1664 ( .A0(n2804), .A1(n2694), .B0(n2693), .Y(n2699) );
ADDFHX2TS U1665 ( .A(n914), .B(n913), .CI(n912), .CO(n953), .S(n917) );
OAI22X1TS U1666 ( .A0(n481), .A1(n858), .B0(n446), .B1(n879), .Y(n820) );
ADDFHX2TS U1667 ( .A(n719), .B(n718), .CI(n717), .CO(n720), .S(n711) );
INVX4TS U1668 ( .A(n400), .Y(n449) );
INVX2TS U1669 ( .A(n1292), .Y(n1368) );
AOI21X2TS U1670 ( .A0(n1276), .A1(n401), .B0(n1275), .Y(n1370) );
NOR2X1TS U1671 ( .A(DP_OP_155J7_124_2038_n725), .B(n427), .Y(n1872) );
NAND2X1TS U1672 ( .A(Op_MX[21]), .B(n3921), .Y(n1292) );
INVX2TS U1673 ( .A(n1370), .Y(n1293) );
CLKXOR2X2TS U1674 ( .A(Op_MX[10]), .B(Op_MX[22]), .Y(n1295) );
OR2X2TS U1675 ( .A(Op_MX[21]), .B(n3921), .Y(n1365) );
INVX2TS U1676 ( .A(n1372), .Y(n1291) );
INVX2TS U1677 ( .A(n1373), .Y(n1208) );
INVX2TS U1678 ( .A(n1229), .Y(n1276) );
NOR2X4TS U1679 ( .A(n1246), .B(n1283), .Y(n1332) );
NOR2X2TS U1680 ( .A(n1401), .B(DP_OP_153J7_122_5442_n1181), .Y(n1482) );
NAND2X2TS U1681 ( .A(n1448), .B(n1447), .Y(n1465) );
CLKXOR2X2TS U1682 ( .A(n1446), .B(n1445), .Y(n1440) );
NOR2X2TS U1683 ( .A(n2642), .B(n2645), .Y(n2648) );
INVX2TS U1684 ( .A(n1421), .Y(n2334) );
ADDFHX2TS U1685 ( .A(n2357), .B(n2356), .CI(n2355), .CO(n3095), .S(n2346) );
NOR2X1TS U1686 ( .A(n1705), .B(n448), .Y(n2357) );
INVX2TS U1687 ( .A(n2757), .Y(n2355) );
XNOR2X1TS U1688 ( .A(n1521), .B(n2341), .Y(n2342) );
NOR2X4TS U1689 ( .A(n2442), .B(n2441), .Y(n2645) );
INVX2TS U1690 ( .A(n2646), .Y(n2426) );
ADDFHX2TS U1691 ( .A(n1627), .B(n1626), .CI(n1625), .CO(n1661), .S(n1611) );
NAND2X6TS U1692 ( .A(n1419), .B(n2871), .Y(n2872) );
NAND2X1TS U1693 ( .A(n2758), .B(n2857), .Y(n2759) );
NAND2X2TS U1694 ( .A(n1327), .B(n1326), .Y(n2741) );
NAND2X2TS U1695 ( .A(n1989), .B(n1988), .Y(n2064) );
OR2X4TS U1696 ( .A(n1989), .B(n1988), .Y(n2065) );
NOR2X1TS U1697 ( .A(n417), .B(n431), .Y(n1820) );
AND2X6TS U1698 ( .A(n1180), .B(n3948), .Y(n1280) );
NOR2X1TS U1699 ( .A(n396), .B(n1846), .Y(n1771) );
NOR2X2TS U1700 ( .A(n2040), .B(n1948), .Y(n1772) );
OR2X2TS U1701 ( .A(Op_MX[19]), .B(Op_MX[7]), .Y(n1273) );
INVX2TS U1702 ( .A(n2064), .Y(n1990) );
NOR2X1TS U1703 ( .A(n624), .B(DP_OP_154J7_123_2038_n720), .Y(n553) );
NOR2X1TS U1704 ( .A(n659), .B(n429), .Y(n554) );
NAND2X1TS U1705 ( .A(n1025), .B(n1024), .Y(n1110) );
ADDFHX2TS U1706 ( .A(n649), .B(n648), .CI(n647), .CO(n640), .S(n669) );
INVX8TS U1707 ( .A(n3914), .Y(n880) );
NOR2X1TS U1708 ( .A(DP_OP_153J7_122_5442_n1475), .B(
DP_OP_153J7_122_5442_n1464), .Y(n1221) );
XNOR2X2TS U1709 ( .A(n1500), .B(n1540), .Y(n1541) );
INVX2TS U1710 ( .A(n2850), .Y(n2175) );
NOR2X4TS U1711 ( .A(DP_OP_153J7_122_5442_n1102), .B(
DP_OP_153J7_122_5442_n1096), .Y(n1466) );
ADDFHX2TS U1712 ( .A(n1528), .B(n1527), .CI(n1526), .CO(n1529), .S(n1459) );
ADDFX2TS U1713 ( .A(n1583), .B(n1582), .CI(n1581), .CO(n1610), .S(n1585) );
INVX2TS U1714 ( .A(n3408), .Y(n2352) );
INVX2TS U1715 ( .A(n1078), .Y(n1000) );
NAND2X1TS U1716 ( .A(n3100), .B(n3110), .Y(n3009) );
OAI21X1TS U1717 ( .A0(n2801), .A1(n2854), .B0(n2857), .Y(n2802) );
OAI21X1TS U1718 ( .A0(n4103), .A1(n4104), .B0(n4105), .Y(n2917) );
OR2X4TS U1719 ( .A(n1994), .B(n1993), .Y(n2153) );
NOR2X1TS U1720 ( .A(n2545), .B(n2544), .Y(n3276) );
OR2X6TS U1721 ( .A(n2179), .B(n2178), .Y(n3049) );
NOR2X1TS U1722 ( .A(n405), .B(n429), .Y(n907) );
AOI21X1TS U1723 ( .A0(n1078), .A1(n1077), .B0(n1076), .Y(n1079) );
NAND2X1TS U1724 ( .A(n665), .B(n664), .Y(n739) );
NOR2X4TS U1725 ( .A(n1061), .B(n1060), .Y(n1074) );
NAND2X2TS U1726 ( .A(n1107), .B(n1106), .Y(n1108) );
INVX2TS U1727 ( .A(n1105), .Y(n1107) );
NAND2X4TS U1728 ( .A(n931), .B(n930), .Y(n1136) );
CLKBUFX2TS U1729 ( .A(n1114), .Y(n1115) );
NOR2X2TS U1730 ( .A(n624), .B(n522), .Y(n1120) );
OR2X4TS U1731 ( .A(n637), .B(n636), .Y(n921) );
OR2X2TS U1732 ( .A(n667), .B(n666), .Y(n773) );
INVX2TS U1733 ( .A(n3878), .Y(n2711) );
INVX2TS U1734 ( .A(Sgf_operation_EVEN1_Q_left[8]), .Y(n2710) );
NAND2X1TS U1735 ( .A(n2754), .B(n2694), .Y(n2631) );
NAND2X2TS U1736 ( .A(n2615), .B(n2614), .Y(n3240) );
NOR2X1TS U1737 ( .A(n4178), .B(DP_OP_154J7_123_2038_n636), .Y(n677) );
OR2X2TS U1738 ( .A(n2816), .B(n528), .Y(n426) );
NAND2X1TS U1739 ( .A(n1558), .B(n1519), .Y(n1559) );
NAND2X1TS U1740 ( .A(n1557), .B(n1519), .Y(n1560) );
NAND2X4TS U1741 ( .A(n1573), .B(n508), .Y(n3197) );
BUFX3TS U1742 ( .A(n1573), .Y(n3196) );
AO21XLTS U1743 ( .A0(n3149), .A1(n452), .B0(n3148), .Y(n3204) );
ADDFX2TS U1744 ( .A(n3147), .B(n3146), .CI(n3145), .CO(n3192), .S(n3161) );
NAND2X2TS U1745 ( .A(n1530), .B(n1529), .Y(n3003) );
ADDFHX2TS U1746 ( .A(n3093), .B(n3092), .CI(n3091), .CO(n3143), .S(n3085) );
INVX2TS U1747 ( .A(n2670), .Y(n2454) );
NAND2BX1TS U1748 ( .AN(n1499), .B(n1269), .Y(n1288) );
OAI22X2TS U1749 ( .A0(n1279), .A1(n425), .B0(n1499), .B1(n1497), .Y(n2285)
);
OAI21X2TS U1750 ( .A0(n2864), .A1(n2863), .B0(n2862), .Y(n3011) );
NAND2X1TS U1751 ( .A(n2855), .B(n2861), .Y(n2863) );
AOI21X1TS U1752 ( .A0(n2861), .A1(n2860), .B0(n2859), .Y(n2862) );
OAI21X2TS U1753 ( .A0(n3008), .A1(n494), .B0(n3007), .Y(n493) );
NAND2X2TS U1754 ( .A(n2579), .B(n2578), .Y(n3262) );
OAI21X1TS U1755 ( .A0(n2166), .A1(n2165), .B0(n2164), .Y(n2167) );
INVX2TS U1756 ( .A(n2590), .Y(n2606) );
NAND2X2TS U1757 ( .A(n2851), .B(n2850), .Y(n2853) );
AO21X1TS U1758 ( .A0(n2337), .A1(n2336), .B0(n2339), .Y(n3113) );
XNOR2X2TS U1759 ( .A(n2718), .B(n2740), .Y(n2736) );
NAND2X1TS U1760 ( .A(n2739), .B(n2737), .Y(n2718) );
CMPR22X2TS U1761 ( .A(n551), .B(n550), .CO(n560), .S(n690) );
NOR2X2TS U1762 ( .A(n661), .B(DP_OP_154J7_123_2038_n635), .Y(n550) );
INVX2TS U1763 ( .A(n1115), .Y(n1117) );
OAI21X1TS U1764 ( .A0(n795), .A1(n732), .B0(n731), .Y(n733) );
XNOR2X1TS U1765 ( .A(n3243), .B(n3242), .Y(n3252) );
NAND2X1TS U1766 ( .A(n3241), .B(n3240), .Y(n3242) );
NOR2X2TS U1767 ( .A(n661), .B(n660), .Y(n2883) );
NAND2X1TS U1768 ( .A(n811), .B(n830), .Y(n744) );
INVX8TS U1769 ( .A(n2719), .Y(n3073) );
NAND2X2TS U1770 ( .A(n3072), .B(n2819), .Y(n2821) );
NOR2X1TS U1771 ( .A(n2661), .B(n2658), .Y(n2664) );
OAI21X1TS U1772 ( .A0(n2661), .A1(n2660), .B0(n2659), .Y(n2662) );
NOR2X1TS U1773 ( .A(n2377), .B(n2378), .Y(n3066) );
NAND2X4TS U1774 ( .A(n1689), .B(n1688), .Y(n2321) );
ADDFHX2TS U1775 ( .A(n3354), .B(n3353), .CI(n3352), .CO(n3439), .S(n3061) );
NAND2X2TS U1776 ( .A(n3042), .B(n3041), .Y(n3043) );
XOR2X1TS U1777 ( .A(n2927), .B(n4075), .Y(n2958) );
XOR2X1TS U1778 ( .A(n2942), .B(n2941), .Y(n2961) );
INVX2TS U1779 ( .A(n2748), .Y(n2151) );
NAND2X2TS U1780 ( .A(n2168), .B(n2167), .Y(n2796) );
XOR2X1TS U1781 ( .A(n3260), .B(n3259), .Y(n3311) );
AND2X2TS U1782 ( .A(n2591), .B(n2590), .Y(n3876) );
NAND2X1TS U1783 ( .A(n2707), .B(n2706), .Y(n2708) );
XOR2X1TS U1784 ( .A(n2574), .B(n2573), .Y(n3875) );
XNOR2X1TS U1785 ( .A(n2517), .B(n2516), .Y(n3873) );
INVX2TS U1786 ( .A(n2509), .Y(n2511) );
XOR2X1TS U1787 ( .A(n2529), .B(n2528), .Y(n3872) );
MX2X1TS U1788 ( .A(n472), .B(exp_oper_result[0]), .S0(FSM_selector_A), .Y(
S_Oper_A_exp[0]) );
INVX2TS U1789 ( .A(add_x_19_n59), .Y(n3274) );
MX2X1TS U1790 ( .A(Data_MX[0]), .B(n3183), .S0(n3803), .Y(n3699) );
INVX2TS U1791 ( .A(n2980), .Y(n3127) );
NAND2X2TS U1792 ( .A(n2736), .B(n3377), .Y(n3237) );
NAND2X2TS U1793 ( .A(n3402), .B(n2835), .Y(n3335) );
NAND2X1TS U1794 ( .A(n691), .B(n690), .Y(n2465) );
INVX2TS U1795 ( .A(n2684), .Y(n803) );
OR2X4TS U1796 ( .A(n802), .B(n801), .Y(n2685) );
NOR2X2TS U1797 ( .A(n3252), .B(n3251), .Y(n3271) );
INVX2TS U1798 ( .A(n3347), .Y(n3360) );
INVX2TS U1799 ( .A(n3434), .Y(n3442) );
NAND3BXLTS U1800 ( .AN(DP_OP_155J7_124_2038_n788), .B(n4184), .C(n4185), .Y(
n3910) );
MX2X1TS U1801 ( .A(n3875), .B(P_Sgf[5]), .S0(n4213), .Y(n243) );
NAND2X1TS U1802 ( .A(n3466), .B(n3524), .Y(n3467) );
MX2X1TS U1803 ( .A(n3873), .B(P_Sgf[3]), .S0(n4214), .Y(n241) );
XOR2X1TS U1804 ( .A(n3463), .B(n3887), .Y(n3464) );
NAND2X1TS U1805 ( .A(n3462), .B(n3461), .Y(n3463) );
INVX2TS U1806 ( .A(n3312), .Y(n3364) );
INVX2TS U1807 ( .A(n3866), .Y(n3863) );
MX2X1TS U1808 ( .A(Add_result[4]), .B(n3862), .S0(n3870), .Y(n305) );
MX2X1TS U1809 ( .A(Add_result[5]), .B(n3859), .S0(n3861), .Y(n304) );
MX2X1TS U1810 ( .A(n3872), .B(P_Sgf[2]), .S0(n4213), .Y(n240) );
MX2X1TS U1811 ( .A(Data_MX[24]), .B(Op_MX[24]), .S0(n3899), .Y(n368) );
MX2X1TS U1812 ( .A(n3675), .B(n4167), .S0(n393), .Y(n263) );
NAND2X2TS U1813 ( .A(n3444), .B(n3443), .Y(DP_OP_156J7_125_3370_n13) );
NAND2X4TS U1814 ( .A(n3175), .B(n2986), .Y(n2995) );
CLKXOR2X2TS U1815 ( .A(n3001), .B(n3000), .Y(Sgf_operation_EVEN1_Q_left[13])
);
CLKXOR2X2TS U1816 ( .A(n2486), .B(n2485), .Y(Sgf_operation_EVEN1_Q_left[4])
);
NAND2X1TS U1817 ( .A(n3314), .B(add_x_19_n275), .Y(add_x_19_n273) );
INVX2TS U1818 ( .A(n3315), .Y(n3317) );
XNOR2X2TS U1819 ( .A(n2468), .B(n2467), .Y(Sgf_operation_EVEN1_Q_left[3]) );
NAND2X1TS U1820 ( .A(n2466), .B(n2465), .Y(n2468) );
NAND2X1TS U1821 ( .A(n3310), .B(Sgf_operation_EVEN1_Q_left[22]), .Y(
add_x_19_n39) );
INVX2TS U1822 ( .A(n3310), .Y(add_x_19_n47) );
INVX2TS U1823 ( .A(n3944), .Y(n3232) );
NAND2X1TS U1824 ( .A(n3303), .B(n3318), .Y(add_x_19_n94) );
NAND2X1TS U1825 ( .A(n2494), .B(n2493), .Y(n2495) );
NAND2X1TS U1826 ( .A(add_x_19_n242), .B(n3307), .Y(add_x_19_n233) );
XOR2X1TS U1827 ( .A(n2481), .B(n2480), .Y(Sgf_operation_EVEN1_Q_left[5]) );
NAND2X1TS U1828 ( .A(n3254), .B(n3332), .Y(add_x_19_n26) );
INVX2TS U1829 ( .A(n2487), .Y(n2489) );
INVX2TS U1830 ( .A(n3945), .Y(add_x_19_n243) );
AND2X2TS U1831 ( .A(n2476), .B(n2475), .Y(Sgf_operation_EVEN1_Q_left[6]) );
NAND2X1TS U1832 ( .A(n3433), .B(DP_OP_156J7_125_3370_n84), .Y(
DP_OP_156J7_125_3370_n12) );
INVX2TS U1833 ( .A(DP_OP_156J7_125_3370_n83), .Y(n3433) );
AOI21X1TS U1834 ( .A0(n3230), .A1(n3385), .B0(n530), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16]) );
INVX2TS U1835 ( .A(Sgf_operation_EVEN1_Q_left[22]), .Y(n3454) );
INVX2TS U1836 ( .A(n3453), .Y(n3455) );
INVX2TS U1837 ( .A(DP_OP_156J7_125_3370_n75), .Y(DP_OP_156J7_125_3370_n73)
);
XOR2X1TS U1838 ( .A(n3229), .B(n529), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15]) );
AOI21X1TS U1839 ( .A0(n3385), .A1(n3230), .B0(n3231), .Y(n3229) );
NAND2X1TS U1840 ( .A(n533), .B(n3444), .Y(DP_OP_156J7_125_3370_n87) );
INVX2TS U1841 ( .A(n3033), .Y(n3034) );
AOI21X2TS U1842 ( .A0(n3444), .A1(n3442), .B0(n3441), .Y(
DP_OP_156J7_125_3370_n88) );
INVX2TS U1843 ( .A(n3443), .Y(n3441) );
AOI21X1TS U1844 ( .A0(n3435), .A1(n533), .B0(n3442), .Y(
DP_OP_156J7_125_3370_n93) );
OAI31X1TS U1845 ( .A0(FS_Module_state_reg[1]), .A1(n3735), .A2(n3797), .B0(
n4138), .Y(n375) );
MX2X1TS U1846 ( .A(n3724), .B(n4159), .S0(n392), .Y(n257) );
MX2X1TS U1847 ( .A(Data_MX[6]), .B(DP_OP_155J7_124_2038_n794), .S0(n3890),
.Y(n350) );
MX2X1TS U1848 ( .A(Data_MY[17]), .B(DP_OP_154J7_123_2038_n357), .S0(n3891),
.Y(n329) );
AO21XLTS U1849 ( .A0(n3657), .A1(n4058), .B0(n3652), .Y(n3655) );
MX2X1TS U1850 ( .A(n3722), .B(n4169), .S0(n392), .Y(n259) );
MX2X1TS U1851 ( .A(n3680), .B(n4170), .S0(n393), .Y(n261) );
MX2X1TS U1852 ( .A(Data_MX[30]), .B(Op_MX[30]), .S0(n3804), .Y(n374) );
MX2X1TS U1853 ( .A(Data_MX[29]), .B(Op_MX[29]), .S0(n3890), .Y(n373) );
MX2X1TS U1854 ( .A(Data_MX[17]), .B(n3914), .S0(n3804), .Y(n361) );
MX2X1TS U1855 ( .A(Data_MY[23]), .B(Op_MY[23]), .S0(n3803), .Y(n335) );
MX2X1TS U1856 ( .A(Data_MY[13]), .B(DP_OP_154J7_123_2038_n779), .S0(n3891),
.Y(n325) );
MX2X1TS U1857 ( .A(n3880), .B(P_Sgf[0]), .S0(n4213), .Y(n238) );
MX2X1TS U1858 ( .A(n3881), .B(P_Sgf[1]), .S0(n4214), .Y(n239) );
INVX2TS U1859 ( .A(n3883), .Y(n3884) );
MX2X1TS U1860 ( .A(Data_MY[9]), .B(Op_MY[9]), .S0(n3803), .Y(n321) );
MX2X1TS U1861 ( .A(Data_MY[10]), .B(Op_MY[10]), .S0(n3804), .Y(n322) );
MX2X1TS U1862 ( .A(Data_MY[21]), .B(n3903), .S0(n3890), .Y(n333) );
MX2X1TS U1863 ( .A(Data_MY[22]), .B(n3806), .S0(n3803), .Y(n334) );
BUFX3TS U1864 ( .A(n489), .Y(n4149) );
MX2X1TS U1865 ( .A(Data_MX[7]), .B(Op_MX[7]), .S0(n3891), .Y(n351) );
MX2X1TS U1866 ( .A(Data_MX[9]), .B(n3921), .S0(n3801), .Y(n353) );
MX2X1TS U1867 ( .A(Data_MX[16]), .B(Op_MX[16]), .S0(n3804), .Y(n360) );
MX2X1TS U1868 ( .A(Data_MX[19]), .B(Op_MX[19]), .S0(n3890), .Y(n363) );
MX2X1TS U1869 ( .A(Data_MX[21]), .B(Op_MX[21]), .S0(n3804), .Y(n365) );
BUFX3TS U1870 ( .A(n489), .Y(n4227) );
MX2X1TS U1871 ( .A(Data_MX[23]), .B(n472), .S0(n3899), .Y(n367) );
XNOR2X4TS U1872 ( .A(n2314), .B(n413), .Y(n412) );
AND2X4TS U1873 ( .A(n402), .B(n2313), .Y(n413) );
NAND2X4TS U1874 ( .A(n2749), .B(n2748), .Y(n2750) );
AOI21X4TS U1875 ( .A0(n424), .A1(n433), .B0(n1690), .Y(n1737) );
ADDFX2TS U1876 ( .A(n1580), .B(n1579), .CI(n1578), .CO(n2609), .S(n2582) );
ADDFHX4TS U1877 ( .A(n3024), .B(n3023), .CI(n3022), .CO(n3037), .S(n3007) );
ADDFHX4TS U1878 ( .A(n3883), .B(n2849), .CI(n2848), .CO(n3008), .S(n2875) );
ADDFHX4TS U1879 ( .A(n2046), .B(n2045), .CI(n2044), .CO(n2084), .S(n2082) );
ADDFHX2TS U1880 ( .A(n1654), .B(n1653), .CI(n1652), .CO(n1729), .S(n1666) );
ADDFHX4TS U1881 ( .A(n1633), .B(n1632), .CI(n1631), .CO(n1636), .S(n1635) );
XNOR2X4TS U1882 ( .A(n1391), .B(n1390), .Y(n434) );
ADDFHX2TS U1883 ( .A(n1429), .B(n1428), .CI(n1427), .CO(n1527), .S(n1455) );
ADDFX2TS U1884 ( .A(n3192), .B(n3191), .CI(n3190), .CO(n3210), .S(n3164) );
ADDFX2TS U1885 ( .A(n3207), .B(n3206), .CI(n3205), .CO(n3211), .S(n3191) );
XNOR2X4TS U1886 ( .A(n1649), .B(n1421), .Y(n1378) );
CLKINVX6TS U1887 ( .A(DP_OP_155J7_124_2038_n801), .Y(n1938) );
INVX8TS U1888 ( .A(n882), .Y(n446) );
XNOR2X4TS U1889 ( .A(n3056), .B(n3055), .Y(n432) );
XNOR2X4TS U1890 ( .A(n2271), .B(n415), .Y(n2280) );
BUFX16TS U1891 ( .A(n1418), .Y(n485) );
NAND2BX1TS U1892 ( .AN(n443), .B(n1386), .Y(n1304) );
OAI22X2TS U1893 ( .A0(n1550), .A1(n1382), .B0(n1411), .B1(n1714), .Y(n1413)
);
OAI22X4TS U1894 ( .A0(n1489), .A1(n1547), .B0(n1548), .B1(n1546), .Y(n1543)
);
XOR2X4TS U1895 ( .A(n1488), .B(n1487), .Y(n1519) );
NOR2X8TS U1896 ( .A(n3115), .B(n3116), .Y(n3133) );
ADDFHX2TS U1897 ( .A(n2331), .B(n2330), .CI(n2329), .CO(n2806), .S(n2757) );
ADDFHX2TS U1898 ( .A(n1712), .B(n1711), .CI(n1710), .CO(n2330), .S(n1706) );
ADDFHX2TS U1899 ( .A(n1463), .B(n1462), .CI(n1461), .CO(n1586), .S(n1526) );
ADDFHX2TS U1900 ( .A(n1437), .B(n1436), .CI(n1435), .CO(n1462), .S(n1456) );
ADDFHX2TS U1901 ( .A(n1783), .B(n1782), .CI(n1781), .CO(n2075), .S(n2074) );
INVX2TS U1902 ( .A(n2503), .Y(n2504) );
OAI22X2TS U1903 ( .A0(n2022), .A1(n1980), .B0(n2021), .B1(n1977), .Y(n1966)
);
NAND2X2TS U1904 ( .A(n3284), .B(n3283), .Y(n3461) );
NAND2X2TS U1905 ( .A(n1470), .B(n1574), .Y(n3216) );
AO21X4TS U1906 ( .A0(n2293), .A1(n1639), .B0(n1638), .Y(n424) );
CLKXOR2X4TS U1907 ( .A(n1259), .B(n1270), .Y(n425) );
XNOR2X4TS U1908 ( .A(n2995), .B(n504), .Y(n430) );
OR2X4TS U1909 ( .A(n1689), .B(n1688), .Y(n433) );
INVX2TS U1910 ( .A(n3309), .Y(n3324) );
INVX2TS U1911 ( .A(n3308), .Y(n3309) );
AND2X4TS U1912 ( .A(n3384), .B(n3382), .Y(n436) );
INVX2TS U1913 ( .A(n3900), .Y(n3805) );
CLKBUFX2TS U1914 ( .A(n487), .Y(n4152) );
INVX2TS U1915 ( .A(n2243), .Y(n441) );
INVX2TS U1916 ( .A(n441), .Y(n442) );
AND2X4TS U1917 ( .A(n3989), .B(DP_OP_153J7_122_5442_n1205), .Y(n1551) );
INVX12TS U1918 ( .A(n498), .Y(n3076) );
OAI22X2TS U1919 ( .A0(n2245), .A1(n2027), .B0(n442), .B1(n2211), .Y(n2025)
);
OAI21X2TS U1920 ( .A0(n1844), .A1(n1840), .B0(n1841), .Y(n1762) );
AOI21X4TS U1921 ( .A0(n3465), .A1(n3301), .B0(n3300), .Y(add_x_19_n293) );
OAI21X2TS U1922 ( .A0(n3527), .A1(n3524), .B0(n3528), .Y(n3300) );
OAI21X2TS U1923 ( .A0(n3197), .A1(n3216), .B0(n1575), .Y(n1594) );
CLKINVX6TS U1924 ( .A(n4179), .Y(n552) );
ADDFHX4TS U1925 ( .A(n3393), .B(n3392), .CI(n3391), .CO(
DP_OP_156J7_125_3370_n194), .S(DP_OP_156J7_125_3370_n195) );
BUFX20TS U1926 ( .A(n1386), .Y(n1410) );
ADDFHX2TS U1927 ( .A(n1645), .B(n1712), .CI(n1644), .CO(n1707), .S(n1640) );
ADDFHX2TS U1928 ( .A(n1589), .B(n1588), .CI(n1587), .CO(n1642), .S(n1607) );
XOR2X4TS U1929 ( .A(n485), .B(n1470), .Y(n1490) );
OR2X4TS U1930 ( .A(n2150), .B(n2149), .Y(n2749) );
ADDFHX2TS U1931 ( .A(n1823), .B(n1822), .CI(n1821), .CO(n1871), .S(n1876) );
OR2X6TS U1932 ( .A(n2177), .B(n2176), .Y(n3046) );
NOR2BX2TS U1933 ( .AN(n443), .B(n1714), .Y(n1305) );
INVX2TS U1934 ( .A(rst), .Y(n444) );
INVX2TS U1935 ( .A(rst), .Y(n445) );
INVX4TS U1936 ( .A(n882), .Y(n962) );
NAND2X1TS U1937 ( .A(Op_MY[9]), .B(n3903), .Y(n1216) );
INVX4TS U1938 ( .A(n434), .Y(n452) );
INVX2TS U1939 ( .A(rst), .Y(n454) );
INVX2TS U1940 ( .A(rst), .Y(n455) );
INVX2TS U1941 ( .A(rst), .Y(n456) );
INVX2TS U1942 ( .A(rst), .Y(n457) );
INVX2TS U1943 ( .A(n4243), .Y(n461) );
INVX2TS U1944 ( .A(n4243), .Y(n462) );
INVX2TS U1945 ( .A(n4243), .Y(n463) );
INVX2TS U1946 ( .A(n3564), .Y(n464) );
INVX2TS U1947 ( .A(n3564), .Y(n465) );
INVX2TS U1948 ( .A(n3564), .Y(n466) );
NOR4X1TS U1949 ( .A(P_Sgf[6]), .B(P_Sgf[7]), .C(P_Sgf[8]), .D(P_Sgf[9]), .Y(
n3725) );
CLKINVX3TS U1950 ( .A(n4243), .Y(n489) );
BUFX3TS U1951 ( .A(n489), .Y(n4226) );
INVX2TS U1952 ( .A(n438), .Y(n467) );
INVX2TS U1953 ( .A(n439), .Y(n468) );
NOR2X2TS U1954 ( .A(DP_OP_153J7_122_5442_n1459), .B(
DP_OP_153J7_122_5442_n1470), .Y(n3185) );
NOR2X1TS U1955 ( .A(n3716), .B(n2979), .Y(n379) );
OAI22X2TS U1956 ( .A0(ack_FSM), .A1(n2887), .B0(beg_FSM), .B1(n4216), .Y(
n3716) );
NAND2X4TS U1957 ( .A(n3892), .B(n3931), .Y(n3893) );
INVX2TS U1958 ( .A(n3562), .Y(n469) );
INVX2TS U1959 ( .A(n469), .Y(n470) );
INVX2TS U1960 ( .A(n469), .Y(n471) );
INVX2TS U1961 ( .A(n437), .Y(n472) );
INVX4TS U1962 ( .A(n3900), .Y(n3803) );
INVX4TS U1963 ( .A(n3900), .Y(n3890) );
NOR2X2TS U1964 ( .A(Sgf_normalized_result[0]), .B(Sgf_normalized_result[1]),
.Y(n3866) );
BUFX8TS U1965 ( .A(n1380), .Y(n2871) );
AO21X1TS U1966 ( .A0(n1550), .A1(n1714), .B0(n1713), .Y(n2328) );
INVX4TS U1967 ( .A(n499), .Y(n1714) );
INVX4TS U1968 ( .A(n2968), .Y(n476) );
AOI21X1TS U1969 ( .A0(n476), .A1(n2972), .B0(n2971), .Y(n2973) );
NOR2XLTS U1970 ( .A(n479), .B(n507), .Y(n1083) );
OAI22X1TS U1971 ( .A0(n1010), .A1(n879), .B0(n479), .B1(n858), .Y(n887) );
OAI22X1TS U1972 ( .A0(n440), .A1(n841), .B0(n481), .B1(n865), .Y(n818) );
OAI22X1TS U1973 ( .A0(n481), .A1(n987), .B0(n446), .B1(n1009), .Y(n940) );
OAI22X1TS U1974 ( .A0(n1010), .A1(n888), .B0(n481), .B1(n963), .Y(n886) );
INVX2TS U1975 ( .A(n1787), .Y(n482) );
INVX6TS U1976 ( .A(n1787), .Y(n2021) );
INVX8TS U1977 ( .A(n1769), .Y(n483) );
BUFX4TS U1978 ( .A(n1207), .Y(n484) );
NOR2BX1TS U1979 ( .AN(n484), .B(n3196), .Y(n1556) );
NOR2BX1TS U1980 ( .AN(n484), .B(n477), .Y(n1298) );
CLKBUFX2TS U1981 ( .A(n1207), .Y(n1604) );
XNOR2X2TS U1982 ( .A(n485), .B(n1574), .Y(n1464) );
XOR2X1TS U1983 ( .A(n485), .B(n1441), .Y(n1419) );
NOR2X1TS U1984 ( .A(n485), .B(n1574), .Y(n1471) );
NAND2X2TS U1985 ( .A(n2474), .B(n2473), .Y(n2475) );
XNOR2X2TS U1986 ( .A(n3411), .B(n3410), .Y(n3458) );
NOR4X1TS U1987 ( .A(P_Sgf[13]), .B(P_Sgf[12]), .C(n467), .D(P_Sgf[10]), .Y(
n3726) );
NOR4X1TS U1988 ( .A(Op_MY[9]), .B(Op_MY[8]), .C(DP_OP_154J7_123_2038_n779),
.D(Op_MY[7]), .Y(n3909) );
OAI21X2TS U1989 ( .A0(n4029), .A1(n4030), .B0(n2888), .Y(n3657) );
OAI21X2TS U1990 ( .A0(n4078), .A1(n4079), .B0(n4080), .Y(n2933) );
OAI21X2TS U1991 ( .A0(n1164), .A1(n1163), .B0(n1162), .Y(n2991) );
NOR2X2TS U1992 ( .A(n3284), .B(n3283), .Y(n3460) );
NOR2X2TS U1993 ( .A(n3298), .B(n3289), .Y(n3525) );
NOR3XLTS U1994 ( .A(n3922), .B(Op_MX[7]), .C(Op_MX[24]), .Y(n3923) );
CLKBUFX3TS U1995 ( .A(n445), .Y(n486) );
CLKBUFX3TS U1996 ( .A(n445), .Y(n487) );
BUFX3TS U1997 ( .A(n445), .Y(n4229) );
INVX2TS U1998 ( .A(n4243), .Y(n488) );
INVX2TS U1999 ( .A(n3790), .Y(n491) );
INVX2TS U2000 ( .A(n3790), .Y(n492) );
NAND2X1TS U2001 ( .A(Sgf_normalized_result[3]), .B(Sgf_normalized_result[2]),
.Y(n3807) );
XNOR2X4TS U2002 ( .A(n2847), .B(n2846), .Y(n494) );
XNOR2X4TS U2003 ( .A(n494), .B(n3008), .Y(n2874) );
OAI2BB1X4TS U2004 ( .A0N(n3008), .A1N(n494), .B0(n493), .Y(n3057) );
XNOR2X4TS U2005 ( .A(n495), .B(n1296), .Y(n1681) );
OAI21X4TS U2006 ( .A0(n1294), .A1(n1208), .B0(n496), .Y(n495) );
AOI21X4TS U2007 ( .A0(n1293), .A1(n1365), .B0(n1368), .Y(n496) );
XOR2X4TS U2008 ( .A(n497), .B(n835), .Y(n988) );
OAI21X4TS U2009 ( .A0(n834), .A1(n838), .B0(n836), .Y(n497) );
XOR2X4TS U2010 ( .A(n3175), .B(n3127), .Y(add_x_19_n59) );
OAI21X4TS U2011 ( .A0(n2322), .A1(n2321), .B0(n2320), .Y(n3135) );
NOR2X8TS U2012 ( .A(n1734), .B(n1735), .Y(n2322) );
OAI21X4TS U2013 ( .A0(n2186), .A1(n2185), .B0(n2184), .Y(n2187) );
NAND2X6TS U2014 ( .A(n1925), .B(n1924), .Y(n2185) );
NOR2X8TS U2015 ( .A(n2056), .B(n2057), .Y(n2186) );
OAI21X4TS U2016 ( .A0(n3076), .A1(n395), .B0(n2669), .Y(n2456) );
AO21X4TS U2017 ( .A0(n2423), .A1(n2422), .B0(n2421), .Y(n498) );
XOR2X4TS U2018 ( .A(n1301), .B(n1545), .Y(n499) );
XNOR2X4TS U2019 ( .A(n1178), .B(n1180), .Y(n501) );
XNOR2X4TS U2020 ( .A(n1190), .B(n1177), .Y(n500) );
CLKXOR2X2TS U2021 ( .A(n2717), .B(n2641), .Y(n3234) );
NOR2X4TS U2022 ( .A(DP_OP_155J7_124_2038_n796), .B(DP_OP_155J7_124_2038_n802), .Y(n1831) );
NAND2X4TS U2023 ( .A(n2792), .B(n2791), .Y(n2793) );
XNOR2X4TS U2024 ( .A(n1269), .B(n2338), .Y(n1498) );
OAI22X1TS U2025 ( .A0(n2354), .A1(n3196), .B0(n1695), .B1(n3197), .Y(n2358)
);
OR2X2TS U2026 ( .A(n1716), .B(Op_MX[11]), .Y(n1404) );
CMPR22X2TS U2027 ( .A(n598), .B(n597), .CO(n584), .S(n689) );
OAI22X2TS U2028 ( .A0(n3149), .A1(n1451), .B0(n452), .B1(n1502), .Y(n1492)
);
NOR2X2TS U2029 ( .A(n835), .B(DP_OP_154J7_123_2038_n636), .Y(n715) );
NOR2X2TS U2030 ( .A(DP_OP_154J7_123_2038_n636), .B(n620), .Y(n551) );
NAND2X2TS U2031 ( .A(n3072), .B(n2722), .Y(n2724) );
OAI21X2TS U2032 ( .A0(n1446), .A1(n1445), .B0(n1444), .Y(n1448) );
ADDFHX4TS U2033 ( .A(n3064), .B(n3063), .CI(n416), .CO(n3168), .S(n3170) );
NOR2X2TS U2034 ( .A(n3311), .B(n3261), .Y(n3325) );
NAND2X2TS U2035 ( .A(n3311), .B(n3261), .Y(n3547) );
NOR2X8TS U2036 ( .A(n1375), .B(n531), .Y(n1433) );
NAND2X4TS U2037 ( .A(n2675), .B(n2674), .Y(n3077) );
NOR2X2TS U2038 ( .A(DP_OP_154J7_123_2038_n632), .B(DP_OP_154J7_123_2038_n634), .Y(n618) );
ADDFHX2TS U2039 ( .A(n1544), .B(n1543), .CI(n1542), .CO(n1608), .S(n1578) );
NAND2X8TS U2040 ( .A(n2335), .B(n1194), .Y(n1505) );
OAI22X1TS U2041 ( .A0(n1522), .A1(n1596), .B0(n1409), .B1(n1597), .Y(n1524)
);
OAI22X2TS U2042 ( .A0(n1409), .A1(n1596), .B0(n1349), .B1(n1597), .Y(n1437)
);
XNOR2X2TS U2043 ( .A(n1545), .B(n1552), .Y(n1284) );
XNOR2X2TS U2044 ( .A(n1410), .B(n1647), .Y(n1481) );
XNOR2X2TS U2045 ( .A(n2324), .B(n1712), .Y(n1489) );
CLKXOR2X2TS U2046 ( .A(n1170), .B(n1169), .Y(n505) );
OR2X1TS U2047 ( .A(n485), .B(n1470), .Y(n508) );
AO21X1TS U2048 ( .A0(n2601), .A1(n2602), .B0(n1320), .Y(n509) );
AND2X2TS U2049 ( .A(n2121), .B(n1982), .Y(n513) );
INVX2TS U2050 ( .A(n3269), .Y(n3275) );
OR2X1TS U2051 ( .A(n405), .B(n506), .Y(n514) );
OR2X1TS U2052 ( .A(n1025), .B(n1024), .Y(n515) );
XNOR2X4TS U2053 ( .A(n2309), .B(n2308), .Y(n518) );
OR2X2TS U2054 ( .A(n2556), .B(n2555), .Y(n519) );
NOR2X1TS U2055 ( .A(n396), .B(n1979), .Y(n3880) );
INVX2TS U2056 ( .A(n432), .Y(n3337) );
OR2X4TS U2057 ( .A(n2558), .B(n2557), .Y(n524) );
OR2X1TS U2058 ( .A(n1121), .B(n1120), .Y(n525) );
OR2X1TS U2059 ( .A(n2062), .B(n2061), .Y(n526) );
CLKXOR2X2TS U2060 ( .A(n2782), .B(n2781), .Y(n528) );
BUFX3TS U2061 ( .A(n1846), .Y(n2090) );
AND2X2TS U2062 ( .A(n3228), .B(n3227), .Y(n529) );
INVX2TS U2063 ( .A(add_x_19_n229), .Y(add_x_19_n227) );
CLKXOR2X2TS U2064 ( .A(n3429), .B(n3428), .Y(n534) );
AOI2BB2X1TS U2065 ( .B0(n882), .B1(n507), .A0N(n480), .A1N(n880), .Y(n883)
);
INVX2TS U2066 ( .A(n2082), .Y(n2035) );
INVX2TS U2067 ( .A(n1157), .Y(n965) );
NAND2X4TS U2068 ( .A(DP_OP_154J7_123_2038_n684), .B(n535), .Y(n576) );
OAI2BB2XLTS U2069 ( .B0(n989), .B1(n507), .A0N(n988), .A1N(n507), .Y(n1011)
);
INVX2TS U2070 ( .A(n693), .Y(n603) );
ADDFHX2TS U2071 ( .A(n2401), .B(n2400), .CI(n2399), .CO(n2435), .S(n2393) );
OAI22X1TS U2072 ( .A0(n1010), .A1(n507), .B0(n479), .B1(n3914), .Y(n1054) );
INVX2TS U2073 ( .A(n547), .Y(n879) );
OAI22X1TS U2074 ( .A0(n1695), .A1(n3196), .B0(n1651), .B1(n3197), .Y(n1692)
);
NOR2X2TS U2075 ( .A(n421), .B(n2040), .Y(n1854) );
ADDFHX2TS U2076 ( .A(n1944), .B(n1943), .CI(n1942), .CO(n1947), .S(n1971) );
INVX2TS U2077 ( .A(n557), .Y(n865) );
NOR2X1TS U2078 ( .A(n2273), .B(n2272), .Y(n2416) );
AO21X1TS U2079 ( .A0(n2872), .A1(n2871), .B0(n2870), .Y(n3012) );
NOR2X1TS U2080 ( .A(n2800), .B(n2854), .Y(n2803) );
XNOR2X2TS U2081 ( .A(Op_MY[10]), .B(n3806), .Y(n1359) );
AOI21X2TS U2082 ( .A0(n2897), .A1(n2917), .B0(n2896), .Y(n2923) );
NOR2X1TS U2083 ( .A(n2210), .B(n2209), .Y(n2156) );
INVX2TS U2084 ( .A(n2984), .Y(n2987) );
NOR2X1TS U2085 ( .A(n1028), .B(n1027), .Y(n1040) );
XNOR2X2TS U2086 ( .A(n1500), .B(n1683), .Y(n1684) );
CLKXOR2X2TS U2087 ( .A(n1223), .B(n1222), .Y(n1224) );
OAI21X2TS U2088 ( .A0(n2903), .A1(n2923), .B0(n2902), .Y(n2948) );
ADDFHX2TS U2089 ( .A(n2577), .B(n2576), .CI(n2575), .CO(n2592), .S(n2557) );
NAND2X2TS U2090 ( .A(n670), .B(n669), .Y(n756) );
INVX2TS U2091 ( .A(n1770), .Y(n1980) );
OAI21X1TS U2092 ( .A0(n2166), .A1(n2142), .B0(n2141), .Y(n2148) );
AOI21X2TS U2093 ( .A0(n1092), .A1(n1091), .B0(n1090), .Y(n2994) );
NAND2X2TS U2094 ( .A(n3072), .B(n3078), .Y(n2677) );
NAND2X2TS U2095 ( .A(n3078), .B(n3077), .Y(n3079) );
NOR2X1TS U2096 ( .A(n1981), .B(n1980), .Y(n2123) );
INVX2TS U2097 ( .A(n2795), .Y(n2797) );
OR2X4TS U2098 ( .A(n2130), .B(n2129), .Y(n2707) );
NAND2X4TS U2099 ( .A(n3175), .B(n2980), .Y(n1171) );
NAND2X1TS U2100 ( .A(n694), .B(n693), .Y(n2483) );
XOR2X1TS U2101 ( .A(n3120), .B(n3071), .Y(n3129) );
XOR2X1TS U2102 ( .A(n4070), .B(n2996), .Y(DP_OP_36J7_126_4699_n21) );
NAND2X1TS U2103 ( .A(n3529), .B(n3528), .Y(n3530) );
INVX2TS U2104 ( .A(n2475), .Y(n2471) );
INVX2TS U2105 ( .A(n3320), .Y(n3303) );
NAND2X1TS U2106 ( .A(n3329), .B(n3328), .Y(n3330) );
NAND2X1TS U2107 ( .A(n3589), .B(n408), .Y(n3590) );
NAND2X1TS U2108 ( .A(n3275), .B(n3274), .Y(add_x_19_n57) );
NAND2X1TS U2109 ( .A(n3270), .B(add_x_19_n270), .Y(add_x_19_n24) );
OAI2BB1X1TS U2110 ( .A0N(n393), .A1N(n4196), .B0(n3590), .Y(n274) );
INVX2TS U2111 ( .A(n3179), .Y(n3942) );
INVX12TS U2112 ( .A(n4181), .Y(n659) );
OR2X8TS U2113 ( .A(DP_OP_154J7_123_2038_n632), .B(n659), .Y(n572) );
OAI21X4TS U2114 ( .A0(n569), .A1(n572), .B0(n570), .Y(n541) );
NOR2X4TS U2115 ( .A(n542), .B(n575), .Y(n537) );
OAI21X4TS U2116 ( .A0(n542), .A1(n576), .B0(n543), .Y(n536) );
AOI21X4TS U2117 ( .A0(n541), .A1(n537), .B0(n536), .Y(n834) );
NAND2X2TS U2118 ( .A(n555), .B(n836), .Y(n538) );
XOR2X4TS U2119 ( .A(n834), .B(n538), .Y(n539) );
OAI21X4TS U2120 ( .A0(n579), .A1(n575), .B0(n576), .Y(n546) );
INVX2TS U2121 ( .A(n542), .Y(n544) );
NAND2X2TS U2122 ( .A(n544), .B(n543), .Y(n545) );
XNOR2X4TS U2123 ( .A(n546), .B(n545), .Y(n882) );
ADDHX1TS U2124 ( .A(DP_OP_154J7_123_2038_n792), .B(Op_MX[19]), .CO(n547),
.S(n540) );
INVX2TS U2125 ( .A(n1120), .Y(n568) );
NOR2X1TS U2126 ( .A(n827), .B(n947), .Y(n607) );
NOR2X4TS U2127 ( .A(DP_OP_154J7_123_2038_n635), .B(n620), .Y(n619) );
NOR2X2TS U2128 ( .A(DP_OP_154J7_123_2038_n628), .B(n660), .Y(n617) );
NOR2X2TS U2129 ( .A(n699), .B(DP_OP_154J7_123_2038_n636), .Y(n616) );
NOR2X1TS U2130 ( .A(n4178), .B(n681), .Y(n615) );
INVX2TS U2131 ( .A(n694), .Y(n631) );
ADDHX1TS U2132 ( .A(n554), .B(n553), .CO(n563), .S(n1024) );
NOR2X2TS U2133 ( .A(n659), .B(DP_OP_154J7_123_2038_n718), .Y(n626) );
NOR2X2TS U2134 ( .A(n405), .B(n520), .Y(n623) );
NOR2X1TS U2135 ( .A(n624), .B(n429), .Y(n621) );
INVX2TS U2136 ( .A(n1028), .Y(n630) );
INVX2TS U2137 ( .A(n695), .Y(n823) );
CLKINVX6TS U2138 ( .A(n1029), .Y(n822) );
INVX8TS U2139 ( .A(n4209), .Y(n564) );
INVX12TS U2140 ( .A(n564), .Y(n3914) );
INVX2TS U2141 ( .A(n565), .Y(n829) );
INVX4TS U2142 ( .A(n569), .Y(n571) );
NAND2X4TS U2143 ( .A(n571), .B(n570), .Y(n573) );
ADDHX1TS U2144 ( .A(DP_OP_154J7_123_2038_n794), .B(Op_MX[21]), .CO(n574),
.S(n549) );
OAI22X1TS U2145 ( .A0(n450), .A1(n947), .B0(n827), .B1(n980), .Y(n635) );
INVX2TS U2146 ( .A(n575), .Y(n577) );
NAND2X2TS U2147 ( .A(n577), .B(n576), .Y(n578) );
XOR2X4TS U2148 ( .A(n579), .B(n578), .Y(n580) );
INVX4TS U2149 ( .A(n581), .Y(n888) );
ADDHX1TS U2150 ( .A(DP_OP_154J7_123_2038_n793), .B(DP_OP_154J7_123_2038_n699), .CO(n582), .S(n581) );
OAI22X1TS U2151 ( .A0(n881), .A1(n888), .B0(n449), .B1(n963), .Y(n634) );
NOR2X2TS U2152 ( .A(DP_OP_154J7_123_2038_n632), .B(DP_OP_154J7_123_2038_n636), .Y(n688) );
INVX2TS U2153 ( .A(n688), .Y(n596) );
NOR2X2TS U2154 ( .A(n624), .B(n520), .Y(n1141) );
INVX2TS U2155 ( .A(n1141), .Y(n595) );
NOR2X2TS U2156 ( .A(n4178), .B(n660), .Y(n586) );
NOR2X2TS U2157 ( .A(n699), .B(n681), .Y(n585) );
NOR2X2TS U2158 ( .A(n699), .B(n660), .Y(n598) );
NOR2X2TS U2159 ( .A(n620), .B(n681), .Y(n597) );
NOR2X1TS U2160 ( .A(DP_OP_154J7_123_2038_n715), .B(n522), .Y(n589) );
NOR2X2TS U2161 ( .A(DP_OP_154J7_123_2038_n720), .B(n659), .Y(n600) );
NOR2X2TS U2162 ( .A(DP_OP_154J7_123_2038_n715), .B(n520), .Y(n599) );
INVX2TS U2163 ( .A(n1025), .Y(n592) );
OAI22X1TS U2164 ( .A0(n450), .A1(n987), .B0(n662), .B1(n1009), .Y(n826) );
CMPR32X2TS U2165 ( .A(n586), .B(n585), .C(n584), .CO(n693), .S(n691) );
CMPR32X2TS U2166 ( .A(n589), .B(n588), .C(n587), .CO(n1027), .S(n1025) );
INVX2TS U2167 ( .A(n1027), .Y(n602) );
OAI22X1TS U2168 ( .A0(n480), .A1(n858), .B0(n450), .B1(n879), .Y(n649) );
NOR2X2TS U2169 ( .A(n675), .B(n660), .Y(n2518) );
INVX2TS U2170 ( .A(n2518), .Y(n614) );
NOR2X2TS U2171 ( .A(n659), .B(n522), .Y(n1140) );
CMPR32X2TS U2172 ( .A(n596), .B(n1120), .C(n595), .CO(n594), .S(n654) );
INVX2TS U2173 ( .A(n689), .Y(n606) );
ADDHX1TS U2174 ( .A(n600), .B(n599), .CO(n587), .S(n1121) );
INVX2TS U2175 ( .A(n1121), .Y(n604) );
ADDFHX2TS U2176 ( .A(n603), .B(n602), .CI(n601), .CO(n824), .S(n629) );
OAI22X1TS U2177 ( .A0(n962), .A1(n858), .B0(n480), .B1(n879), .Y(n628) );
CMPR32X2TS U2178 ( .A(n606), .B(n605), .C(n604), .CO(n612), .S(n653) );
ADDFHX2TS U2179 ( .A(n609), .B(n608), .CI(n607), .CO(n632), .S(n610) );
OAI22X1TS U2180 ( .A0(n446), .A1(n841), .B0(n480), .B1(n865), .Y(n646) );
ADDFHX2TS U2181 ( .A(n612), .B(n611), .CI(n610), .CO(n627), .S(n645) );
OAI22X1TS U2182 ( .A0(n449), .A1(n858), .B0(n827), .B1(n879), .Y(n651) );
NOR2X2TS U2183 ( .A(n661), .B(n681), .Y(n2519) );
INVX2TS U2184 ( .A(n2519), .Y(n658) );
CMPR32X2TS U2185 ( .A(n617), .B(n616), .C(n615), .CO(n687), .S(n558) );
NOR2X2TS U2186 ( .A(DP_OP_154J7_123_2038_n628), .B(n681), .Y(n684) );
NOR2X2TS U2187 ( .A(n699), .B(DP_OP_154J7_123_2038_n635), .Y(n683) );
NOR2X1TS U2188 ( .A(n880), .B(DP_OP_154J7_123_2038_n632), .Y(n682) );
NOR2X2TS U2189 ( .A(n835), .B(n660), .Y(n680) );
INVX6TS U2190 ( .A(n696), .Y(n844) );
NOR2X4TS U2191 ( .A(n624), .B(DP_OP_154J7_123_2038_n718), .Y(n817) );
CMPR22X2TS U2192 ( .A(n626), .B(n625), .CO(n812), .S(n562) );
INVX2TS U2193 ( .A(n1030), .Y(n843) );
OAI22X1TS U2194 ( .A0(n446), .A1(n888), .B0(n480), .B1(n963), .Y(n842) );
ADDFHX2TS U2195 ( .A(n629), .B(n628), .CI(n627), .CO(n806), .S(n639) );
OAI22X1TS U2196 ( .A0(n481), .A1(n841), .B0(n446), .B1(n865), .Y(n643) );
NOR2X4TS U2197 ( .A(n673), .B(n672), .Y(n783) );
ADDFHX2TS U2198 ( .A(n646), .B(n645), .CI(n644), .CO(n638), .S(n670) );
OR2X4TS U2199 ( .A(n670), .B(n669), .Y(n757) );
CMPR32X2TS U2200 ( .A(n655), .B(n654), .C(n653), .CO(n647), .S(n666) );
OAI22X1TS U2201 ( .A0(n450), .A1(n841), .B0(n662), .B1(n865), .Y(n664) );
NOR2X2TS U2202 ( .A(n665), .B(n664), .Y(n738) );
NOR2X2TS U2203 ( .A(n659), .B(n520), .Y(n1132) );
INVX2TS U2204 ( .A(n1132), .Y(n749) );
INVX2TS U2205 ( .A(n2883), .Y(n748) );
NAND2X1TS U2206 ( .A(n749), .B(n748), .Y(n750) );
NOR2X1TS U2207 ( .A(n662), .B(n841), .Y(n752) );
INVX2TS U2208 ( .A(n752), .Y(n663) );
NAND2X2TS U2209 ( .A(n667), .B(n666), .Y(n772) );
INVX2TS U2210 ( .A(n772), .Y(n668) );
AO21X4TS U2211 ( .A0(n773), .A1(n774), .B0(n668), .Y(n758) );
AOI21X4TS U2212 ( .A0(n757), .A1(n758), .B0(n671), .Y(n786) );
NOR2X2TS U2213 ( .A(DP_OP_154J7_123_2038_n628), .B(DP_OP_154J7_123_2038_n636), .Y(n707) );
NOR2X2TS U2214 ( .A(n4178), .B(DP_OP_154J7_123_2038_n635), .Y(n706) );
ADDFHX2TS U2215 ( .A(n678), .B(n677), .CI(n676), .CO(n709), .S(n685) );
ADDHX1TS U2216 ( .A(n680), .B(n679), .CO(n702), .S(n676) );
ADDFHX2TS U2217 ( .A(n684), .B(n683), .CI(n682), .CO(n700), .S(n686) );
ADDFX2TS U2218 ( .A(n687), .B(n686), .CI(n685), .CO(n830), .S(n696) );
NOR2X4TS U2219 ( .A(n811), .B(n830), .Y(n743) );
NOR2X4TS U2220 ( .A(n695), .B(n696), .Y(n2477) );
OR2X2TS U2221 ( .A(n691), .B(n690), .Y(n2466) );
NOR2X2TS U2222 ( .A(n689), .B(n688), .Y(n2487) );
NAND2X2TS U2223 ( .A(n2519), .B(n2518), .Y(n2520) );
NAND2X1TS U2224 ( .A(n689), .B(n688), .Y(n2488) );
INVX2TS U2225 ( .A(n2465), .Y(n692) );
AOI21X4TS U2226 ( .A0(n2466), .A1(n2467), .B0(n692), .Y(n2485) );
NOR2X2TS U2227 ( .A(n694), .B(n693), .Y(n2482) );
OAI21X4TS U2228 ( .A0(n2485), .A1(n2482), .B0(n2483), .Y(n742) );
NAND2X2TS U2229 ( .A(n696), .B(n695), .Y(n2478) );
AOI21X4TS U2230 ( .A0(n698), .A1(n742), .B0(n697), .Y(n795) );
NOR2X2TS U2231 ( .A(n880), .B(n699), .Y(n716) );
ADDFHX2TS U2232 ( .A(n702), .B(n701), .CI(n700), .CO(n712), .S(n708) );
NOR2X1TS U2233 ( .A(DP_OP_154J7_123_2038_n628), .B(DP_OP_154J7_123_2038_n635), .Y(n719) );
ADDHX1TS U2234 ( .A(n704), .B(n703), .CO(n718), .S(n701) );
ADDFHX2TS U2235 ( .A(n707), .B(n706), .CI(n705), .CO(n717), .S(n710) );
NOR2X2TS U2236 ( .A(n845), .B(n866), .Y(n766) );
ADDFHX2TS U2237 ( .A(n713), .B(n712), .CI(n711), .CO(n884), .S(n845) );
CMPR32X2TS U2238 ( .A(n716), .B(n715), .C(n714), .CO(n722), .S(n713) );
NOR2X2TS U2239 ( .A(DP_OP_154J7_123_2038_n628), .B(DP_OP_154J7_123_2038_n634), .Y(n725) );
NOR2X2TS U2240 ( .A(n884), .B(n908), .Y(n767) );
NOR2X2TS U2241 ( .A(n766), .B(n767), .Y(n788) );
NOR2X1TS U2242 ( .A(n964), .B(n949), .Y(n762) );
CMPR32X2TS U2243 ( .A(n728), .B(n727), .C(n726), .CO(n977), .S(n949) );
NOR2X2TS U2244 ( .A(n880), .B(n835), .Y(n978) );
NOR2X2TS U2245 ( .A(n977), .B(n978), .Y(n796) );
NOR2X1TS U2246 ( .A(n762), .B(n796), .Y(n730) );
NAND2X1TS U2247 ( .A(n788), .B(n730), .Y(n732) );
NAND2X2TS U2248 ( .A(n845), .B(n866), .Y(n765) );
NAND2X1TS U2249 ( .A(n884), .B(n908), .Y(n768) );
OAI21X2TS U2250 ( .A0(n767), .A1(n765), .B0(n768), .Y(n792) );
NAND2X1TS U2251 ( .A(n964), .B(n949), .Y(n789) );
NAND2X1TS U2252 ( .A(n977), .B(n978), .Y(n797) );
AOI21X1TS U2253 ( .A0(n792), .A1(n730), .B0(n729), .Y(n731) );
NAND2X2TS U2254 ( .A(n735), .B(n1124), .Y(n804) );
INVX2TS U2255 ( .A(n766), .Y(n736) );
XOR2X4TS U2256 ( .A(n795), .B(n737), .Y(n754) );
INVX2TS U2257 ( .A(n738), .Y(n740) );
NAND2X2TS U2258 ( .A(n740), .B(n739), .Y(n741) );
CLKXOR2X2TS U2259 ( .A(n741), .B(n503), .Y(n753) );
INVX4TS U2260 ( .A(n742), .Y(n2480) );
OAI21X2TS U2261 ( .A0(n2480), .A1(n2477), .B0(n2478), .Y(n747) );
INVX2TS U2262 ( .A(n743), .Y(n745) );
NAND2X2TS U2263 ( .A(n745), .B(n744), .Y(n746) );
XNOR2X4TS U2264 ( .A(n747), .B(n746), .Y(n2474) );
NAND2X1TS U2265 ( .A(n512), .B(n750), .Y(n751) );
XNOR2X1TS U2266 ( .A(n752), .B(n751), .Y(n2473) );
NAND2X2TS U2267 ( .A(n754), .B(n753), .Y(n2469) );
INVX2TS U2268 ( .A(n2469), .Y(n755) );
AOI21X4TS U2269 ( .A0(n2470), .A1(n2471), .B0(n755), .Y(n2491) );
XNOR2X4TS U2270 ( .A(n759), .B(n758), .Y(n779) );
INVX2TS U2271 ( .A(n788), .Y(n761) );
INVX2TS U2272 ( .A(n792), .Y(n760) );
OAI21X2TS U2273 ( .A0(n795), .A1(n761), .B0(n760), .Y(n764) );
INVX2TS U2274 ( .A(n762), .Y(n791) );
NAND2X1TS U2275 ( .A(n791), .B(n789), .Y(n763) );
XNOR2X4TS U2276 ( .A(n764), .B(n763), .Y(n778) );
OAI21X2TS U2277 ( .A0(n795), .A1(n766), .B0(n765), .Y(n771) );
INVX2TS U2278 ( .A(n767), .Y(n769) );
XNOR2X4TS U2279 ( .A(n771), .B(n770), .Y(n777) );
NAND2X2TS U2280 ( .A(n773), .B(n772), .Y(n775) );
XNOR2X2TS U2281 ( .A(n775), .B(n774), .Y(n776) );
OR2X4TS U2282 ( .A(n777), .B(n776), .Y(n2498) );
NAND2X2TS U2283 ( .A(n2494), .B(n2498), .Y(n782) );
NAND2X2TS U2284 ( .A(n777), .B(n776), .Y(n2497) );
INVX2TS U2285 ( .A(n2493), .Y(n780) );
AOI21X4TS U2286 ( .A0(n2494), .A1(n2492), .B0(n780), .Y(n781) );
OAI21X4TS U2287 ( .A0(n2491), .A1(n782), .B0(n781), .Y(n2686) );
INVX2TS U2288 ( .A(n783), .Y(n785) );
NAND2X1TS U2289 ( .A(n788), .B(n791), .Y(n794) );
INVX2TS U2290 ( .A(n789), .Y(n790) );
AOI21X1TS U2291 ( .A0(n792), .A1(n791), .B0(n790), .Y(n793) );
OAI21X1TS U2292 ( .A0(n795), .A1(n794), .B0(n793), .Y(n800) );
INVX2TS U2293 ( .A(n796), .Y(n798) );
NAND2X1TS U2294 ( .A(n798), .B(n797), .Y(n799) );
XNOR2X2TS U2295 ( .A(n800), .B(n799), .Y(n801) );
XOR2X4TS U2296 ( .A(n804), .B(n1126), .Y(Sgf_operation_EVEN1_Q_left[11]) );
ADDFHX2TS U2297 ( .A(n807), .B(n806), .CI(n805), .CO(n924), .S(n636) );
OAI22X1TS U2298 ( .A0(n881), .A1(n987), .B0(n449), .B1(n1009), .Y(n861) );
OAI22X1TS U2299 ( .A0(n446), .A1(n947), .B0(n480), .B1(n980), .Y(n859) );
INVX2TS U2300 ( .A(n811), .Y(n878) );
NOR2X2TS U2301 ( .A(n405), .B(DP_OP_154J7_123_2038_n720), .Y(n871) );
NOR2X1TS U2302 ( .A(n447), .B(n429), .Y(n870) );
ADDFHX2TS U2303 ( .A(n817), .B(n816), .CI(n815), .CO(n873), .S(n809) );
ADDFHX2TS U2304 ( .A(n820), .B(n819), .CI(n818), .CO(n862), .S(n927) );
ADDFHX2TS U2305 ( .A(n823), .B(n822), .CI(n821), .CO(n851), .S(n833) );
ADDFHX2TS U2306 ( .A(n826), .B(n825), .CI(n824), .CO(n850), .S(n831) );
OAI22X1TS U2307 ( .A0(n449), .A1(n3914), .B0(n827), .B1(n880), .Y(n848) );
ADDFHX2TS U2308 ( .A(n833), .B(n832), .CI(n831), .CO(n856), .S(n926) );
AND2X2TS U2309 ( .A(n836), .B(n835), .Y(n837) );
OAI21X4TS U2310 ( .A0(n839), .A1(n838), .B0(n837), .Y(n840) );
OAI22X1TS U2311 ( .A0(n440), .A1(n865), .B0(n479), .B1(n841), .Y(n854) );
OAI22X1TS U2312 ( .A0(n1010), .A1(n858), .B0(n481), .B1(n879), .Y(n853) );
ADDFHX4TS U2313 ( .A(n844), .B(n843), .CI(n842), .CO(n852), .S(n807) );
CMPR32X2TS U2314 ( .A(n854), .B(n853), .C(n852), .CO(n912), .S(n855) );
OAI22X1TS U2315 ( .A0(n881), .A1(n3914), .B0(n449), .B1(n880), .Y(n891) );
CMPR32X2TS U2316 ( .A(n872), .B(n871), .C(n870), .CO(n911), .S(n869) );
ADDHX1TS U2317 ( .A(Op_MX[19]), .B(Op_MY[19]), .CO(n906), .S(n874) );
CMPR32X2TS U2318 ( .A(n875), .B(n874), .C(n873), .CO(n909), .S(n867) );
INVX2TS U2319 ( .A(n883), .Y(n946) );
INVX4TS U2320 ( .A(n884), .Y(n945) );
OAI22X1TS U2321 ( .A0(n1010), .A1(n963), .B0(n479), .B1(n888), .Y(n944) );
OAI22X1TS U2322 ( .A0(n1010), .A1(n947), .B0(n481), .B1(n980), .Y(n943) );
ADDFHX2TS U2323 ( .A(n897), .B(n896), .CI(n895), .CO(n955), .S(n892) );
NOR2X2TS U2324 ( .A(n405), .B(DP_OP_154J7_123_2038_n718), .Y(n948) );
CMPR32X2TS U2325 ( .A(n911), .B(n910), .C(n909), .CO(n1157), .S(n1094) );
NOR2X8TS U2326 ( .A(n932), .B(n933), .Y(n1114) );
NAND2X4TS U2327 ( .A(n933), .B(n932), .Y(n1116) );
OAI21X4TS U2328 ( .A0(n1114), .A1(n1136), .B0(n1116), .Y(n934) );
AOI21X4TS U2329 ( .A0(n935), .A1(n1113), .B0(n934), .Y(n1034) );
ADDFHX4TS U2330 ( .A(n938), .B(n937), .CI(n936), .CO(n996), .S(n932) );
OAI22X1TS U2331 ( .A0(n440), .A1(n980), .B0(n479), .B1(n947), .Y(n972) );
INVX2TS U2332 ( .A(n1167), .Y(n986) );
INVX2TS U2333 ( .A(n1168), .Y(n984) );
OAI22X1TS U2334 ( .A0(n440), .A1(n987), .B0(n481), .B1(n1009), .Y(n976) );
OAI22X2TS U2335 ( .A0(n989), .A1(n3914), .B0(n962), .B1(n507), .Y(n983) );
NOR2X2TS U2336 ( .A(n478), .B(n963), .Y(n982) );
ADDFHX2TS U2337 ( .A(n967), .B(n966), .CI(n965), .CO(n974), .S(n959) );
ADDFHX1TS U2338 ( .A(n973), .B(n972), .CI(n971), .CO(n1019), .S(n968) );
INVX2TS U2339 ( .A(n977), .Y(n1007) );
INVX2TS U2340 ( .A(n978), .Y(n1008) );
CMPR32X2TS U2341 ( .A(DP_OP_154J7_123_2038_n687), .B(n3806), .C(n979), .CO(
n2984), .S(n1167) );
ADDFHX4TS U2342 ( .A(n986), .B(n985), .CI(n984), .CO(n1013), .S(n971) );
OAI22X1TS U2343 ( .A0(n1010), .A1(n1009), .B0(n478), .B1(n987), .Y(n1012) );
ADDFHX4TS U2344 ( .A(n995), .B(n994), .CI(n993), .CO(n998), .S(n997) );
NAND2X4TS U2345 ( .A(n999), .B(n998), .Y(n1036) );
OAI21X4TS U2346 ( .A0(n1033), .A1(n1035), .B0(n1036), .Y(n1078) );
OAI21X4TS U2347 ( .A0(n1109), .A1(n1001), .B0(n1000), .Y(n1023) );
ADDFHX1TS U2348 ( .A(n1007), .B(n1006), .CI(n1005), .CO(n1059), .S(n1016) );
ADDFHX2TS U2349 ( .A(n1013), .B(n1012), .CI(n1011), .CO(n1057), .S(n1014) );
XNOR2X4TS U2350 ( .A(n1023), .B(n1022), .Y(n1046) );
NAND2X1TS U2351 ( .A(n1121), .B(n1120), .Y(n1122) );
NAND2X1TS U2352 ( .A(n1122), .B(n1142), .Y(n1111) );
INVX2TS U2353 ( .A(n1110), .Y(n1026) );
NAND2X1TS U2354 ( .A(n1028), .B(n1027), .Y(n1041) );
INVX2TS U2355 ( .A(n1091), .Y(n1065) );
NOR2X2TS U2356 ( .A(n1030), .B(n1029), .Y(n1086) );
INVX2TS U2357 ( .A(n1086), .Y(n1031) );
NAND2X1TS U2358 ( .A(n1031), .B(n1088), .Y(n1032) );
CLKXOR2X2TS U2359 ( .A(n1065), .B(n1032), .Y(n1045) );
BUFX3TS U2360 ( .A(n1033), .Y(n1106) );
XNOR2X4TS U2361 ( .A(n1039), .B(n1038), .Y(n1103) );
INVX2TS U2362 ( .A(n1040), .Y(n1042) );
NAND2X1TS U2363 ( .A(n1042), .B(n1041), .Y(n1044) );
CLKXOR2X2TS U2364 ( .A(n1044), .B(n1043), .Y(n1102) );
NAND2X4TS U2365 ( .A(n1046), .B(n1045), .Y(n1742) );
OAI21X4TS U2366 ( .A0(n1741), .A1(n1738), .B0(n1742), .Y(n2310) );
INVX2TS U2367 ( .A(n1075), .Y(n1047) );
CMPR32X2TS U2368 ( .A(n1056), .B(n1055), .C(n1054), .CO(n1082), .S(n1058) );
CMPR32X2TS U2369 ( .A(n1059), .B(n1058), .C(n1057), .CO(n1081), .S(n1053) );
INVX2TS U2370 ( .A(n1074), .Y(n1062) );
NAND2X2TS U2371 ( .A(n1061), .B(n1060), .Y(n1073) );
XNOR2X4TS U2372 ( .A(n1064), .B(n1063), .Y(n1098) );
NOR2X2TS U2373 ( .A(n1066), .B(n1067), .Y(n1089) );
INVX2TS U2374 ( .A(n1089), .Y(n1068) );
NAND2X1TS U2375 ( .A(n1067), .B(n1066), .Y(n1087) );
NAND2X1TS U2376 ( .A(n1068), .B(n1087), .Y(n1069) );
XNOR2X2TS U2377 ( .A(n1070), .B(n1069), .Y(n1097) );
NOR2X8TS U2378 ( .A(n1098), .B(n1097), .Y(n2302) );
NOR2X1TS U2379 ( .A(n1089), .B(n1086), .Y(n1092) );
OAI21X1TS U2380 ( .A0(n1089), .A1(n1088), .B0(n1087), .Y(n1090) );
NOR2X2TS U2381 ( .A(n1094), .B(n1093), .Y(n1161) );
INVX2TS U2382 ( .A(n1161), .Y(n1095) );
NAND2X1TS U2383 ( .A(n1095), .B(n1163), .Y(n1096) );
CLKXOR2X2TS U2384 ( .A(n2994), .B(n1096), .Y(n1099) );
NOR2X8TS U2385 ( .A(n2302), .B(n2305), .Y(n1104) );
NAND2X4TS U2386 ( .A(n1098), .B(n1097), .Y(n2313) );
OAI21X4TS U2387 ( .A0(n2305), .A1(n2313), .B0(n2306), .Y(n1101) );
AOI21X4TS U2388 ( .A0(n2310), .A1(n1104), .B0(n1101), .Y(n1155) );
XOR2X4TS U2389 ( .A(n1109), .B(n1108), .Y(n1149) );
NAND2X1TS U2390 ( .A(n515), .B(n1110), .Y(n1112) );
XNOR2X2TS U2391 ( .A(n1112), .B(n1111), .Y(n1148) );
NOR2X8TS U2392 ( .A(n1149), .B(n1148), .Y(n2288) );
NAND2X1TS U2393 ( .A(n525), .B(n1122), .Y(n1123) );
CLKXOR2X2TS U2394 ( .A(n1123), .B(n1142), .Y(n1146) );
NOR2X4TS U2395 ( .A(n2288), .B(n3052), .Y(n1151) );
OAI21X4TS U2396 ( .A0(n1126), .A1(n1125), .B0(n1124), .Y(n2839) );
NAND2X4TS U2397 ( .A(n1129), .B(n1128), .Y(n1131) );
XOR2X4TS U2398 ( .A(n1131), .B(n1130), .Y(n1133) );
AOI21X4TS U2399 ( .A0(n2839), .A1(n2838), .B0(n1134), .Y(n3000) );
INVX2TS U2400 ( .A(n1135), .Y(n1137) );
NAND2X4TS U2401 ( .A(n1137), .B(n1136), .Y(n1139) );
XOR2X4TS U2402 ( .A(n1139), .B(n1138), .Y(n1145) );
NAND2X4TS U2403 ( .A(n1145), .B(n1144), .Y(n2998) );
NAND2X4TS U2404 ( .A(n1149), .B(n1148), .Y(n2289) );
OAI21X4TS U2405 ( .A0(n2288), .A1(n3053), .B0(n2289), .Y(n1150) );
AOI21X4TS U2406 ( .A0(n1151), .A1(n2287), .B0(n1150), .Y(n1152) );
NAND2X8TS U2407 ( .A(n1155), .B(n1154), .Y(n3175) );
OAI21X1TS U2408 ( .A0(n2994), .A1(n1161), .B0(n1163), .Y(n1160) );
NOR2X2TS U2409 ( .A(n1157), .B(n1156), .Y(n1164) );
INVX2TS U2410 ( .A(n1164), .Y(n1158) );
NAND2X1TS U2411 ( .A(n1158), .B(n1162), .Y(n1159) );
XNOR2X2TS U2412 ( .A(n1160), .B(n1159), .Y(n2980) );
NOR2X1TS U2413 ( .A(n1161), .B(n1164), .Y(n2981) );
INVX2TS U2414 ( .A(n2981), .Y(n1166) );
INVX2TS U2415 ( .A(n2991), .Y(n1165) );
NAND2X1TS U2416 ( .A(n1168), .B(n1167), .Y(n2988) );
NAND2X1TS U2417 ( .A(n2990), .B(n2988), .Y(n1169) );
XOR2X4TS U2418 ( .A(n1171), .B(n505), .Y(n1172) );
NAND2X4TS U2419 ( .A(n1740), .B(n1738), .Y(n1174) );
XNOR2X4TS U2420 ( .A(n2312), .B(n1174), .Y(n1175) );
INVX6TS U2421 ( .A(n1175), .Y(add_x_19_n96) );
NOR2X8TS U2422 ( .A(DP_OP_153J7_122_5442_n1120), .B(
DP_OP_153J7_122_5442_n1117), .Y(n1176) );
NOR2X1TS U2423 ( .A(n1545), .B(n1187), .Y(n1179) );
XNOR2X4TS U2424 ( .A(n1189), .B(n1179), .Y(n1185) );
AND2X4TS U2425 ( .A(n1466), .B(n3951), .Y(n1181) );
AOI21X4TS U2426 ( .A0(n3991), .A1(n1181), .B0(n510), .Y(n1259) );
NAND2X1TS U2427 ( .A(n1280), .B(DP_OP_153J7_122_5442_n451), .Y(n1182) );
NAND2X2TS U2428 ( .A(n1257), .B(n1265), .Y(n1184) );
XOR2X4TS U2429 ( .A(n1185), .B(n1184), .Y(n1186) );
XOR2X1TS U2430 ( .A(n1301), .B(n1187), .Y(n1188) );
NOR2X2TS U2431 ( .A(n1189), .B(n1188), .Y(n1193) );
OAI21X4TS U2432 ( .A0(n1190), .A1(DP_OP_153J7_122_5442_n1113), .B0(
DP_OP_153J7_122_5442_n1114), .Y(n1191) );
XNOR2X4TS U2433 ( .A(n1191), .B(DP_OP_153J7_122_5442_n1061), .Y(n1386) );
OAI21X4TS U2434 ( .A0(n1195), .A1(n1301), .B0(n1712), .Y(n1197) );
NAND2X2TS U2435 ( .A(n1195), .B(n1301), .Y(n1196) );
NAND2X2TS U2436 ( .A(n1197), .B(n1196), .Y(n1388) );
XNOR2X4TS U2437 ( .A(n1389), .B(n1388), .Y(n1198) );
OAI21X4TS U2438 ( .A0(n1243), .A1(DP_OP_153J7_122_5442_n1192), .B0(
DP_OP_153J7_122_5442_n1193), .Y(n1201) );
NOR2X8TS U2439 ( .A(DP_OP_153J7_122_5442_n1495), .B(
DP_OP_153J7_122_5442_n1508), .Y(n1242) );
NOR2X8TS U2440 ( .A(n1201), .B(n1200), .Y(n1486) );
AOI21X4TS U2441 ( .A0(n1483), .A1(n3994), .B0(n3992), .Y(n1203) );
NAND2X8TS U2442 ( .A(n1204), .B(n1203), .Y(n1373) );
NAND2X2TS U2443 ( .A(n1233), .B(n1234), .Y(n1206) );
XNOR2X2TS U2444 ( .A(n1373), .B(n1206), .Y(n1207) );
XNOR2X1TS U2445 ( .A(n1421), .B(n1604), .Y(n1213) );
XNOR2X4TS U2446 ( .A(n1212), .B(n1211), .Y(n1649) );
NAND2X1TS U2447 ( .A(n401), .B(n1274), .Y(n1214) );
OAI21X2TS U2448 ( .A0(Op_MY[9]), .A1(n3903), .B0(DP_OP_153J7_122_5442_n1475),
.Y(n1217) );
XNOR2X4TS U2449 ( .A(n1359), .B(n1358), .Y(n1540) );
NAND2X1TS U2450 ( .A(DP_OP_153J7_122_5442_n778), .B(
DP_OP_153J7_122_5442_n1474), .Y(n1219) );
NAND2X4TS U2451 ( .A(n1220), .B(n1219), .Y(n1268) );
NAND2X2TS U2452 ( .A(n1268), .B(DP_OP_153J7_122_5442_n788), .Y(n1223) );
CLKXOR2X2TS U2453 ( .A(Op_MY[9]), .B(n3903), .Y(n1225) );
XOR2X1TS U2454 ( .A(DP_OP_153J7_122_5442_n1464), .B(n3903), .Y(n1226) );
XOR2X1TS U2455 ( .A(n1227), .B(n1359), .Y(n1228) );
NAND2X6TS U2456 ( .A(n1676), .B(n1228), .Y(n1677) );
NAND2X1TS U2457 ( .A(n1229), .B(n1273), .Y(n1230) );
XNOR2X2TS U2458 ( .A(n1373), .B(n1230), .Y(n1231) );
XNOR2X1TS U2459 ( .A(n1499), .B(n1540), .Y(n1232) );
OAI22X2TS U2460 ( .A0(n1377), .A1(n1676), .B0(n1677), .B1(n1232), .Y(n2374)
);
INVX2TS U2461 ( .A(n2374), .Y(n1356) );
NAND2X2TS U2462 ( .A(n1238), .B(n1233), .Y(n1240) );
INVX2TS U2463 ( .A(n1234), .Y(n1237) );
OAI21X4TS U2464 ( .A0(n1208), .A1(n1240), .B0(n1239), .Y(n1337) );
INVX4TS U2465 ( .A(n1337), .Y(n1262) );
ADDFHX2TS U2466 ( .A(Op_MX[8]), .B(Op_MX[20]), .CI(n1241), .CO(n1251), .S(
n1210) );
XOR2X4TS U2467 ( .A(n1245), .B(n3990), .Y(n1283) );
NAND2X4TS U2468 ( .A(n1246), .B(n1283), .Y(n1334) );
OAI21X4TS U2469 ( .A0(n1262), .A1(n1332), .B0(n1334), .Y(n1256) );
XOR2X4TS U2470 ( .A(n1249), .B(n1248), .Y(n1250) );
XOR2X4TS U2471 ( .A(n1647), .B(n1295), .Y(n1253) );
ADDFHX2TS U2472 ( .A(n3921), .B(Op_MX[21]), .CI(n1251), .CO(n1252), .S(n1246) );
NOR2X6TS U2473 ( .A(n1253), .B(n1252), .Y(n1335) );
NAND2X2TS U2474 ( .A(n1253), .B(n1252), .Y(n1333) );
XNOR2X4TS U2475 ( .A(n1256), .B(n1255), .Y(n2332) );
XNOR2X2TS U2476 ( .A(n1257), .B(n1265), .Y(n1258) );
CLKXOR2X4TS U2477 ( .A(n1259), .B(n1263), .Y(n1596) );
INVX2TS U2478 ( .A(n1332), .Y(n1260) );
XNOR2X4TS U2479 ( .A(n1605), .B(n1595), .Y(n1267) );
NOR2X1TS U2480 ( .A(n1263), .B(DP_OP_153J7_122_5442_n451), .Y(n1264) );
XOR2X1TS U2481 ( .A(n1265), .B(n1264), .Y(n1266) );
NAND2X4TS U2482 ( .A(n1596), .B(n1266), .Y(n1597) );
XNOR2X2TS U2483 ( .A(n1595), .B(n1649), .Y(n1289) );
XNOR2X4TS U2484 ( .A(n1268), .B(DP_OP_153J7_122_5442_n788), .Y(n1269) );
XNOR2X2TS U2485 ( .A(n1538), .B(n1269), .Y(n1279) );
NOR2X2TS U2486 ( .A(n1270), .B(DP_OP_153J7_122_5442_n778), .Y(n1271) );
XOR2X1TS U2487 ( .A(n1271), .B(DP_OP_153J7_122_5442_n788), .Y(n1272) );
NAND2X4TS U2488 ( .A(n425), .B(n1272), .Y(n1497) );
INVX2TS U2489 ( .A(n2285), .Y(n1311) );
INVX2TS U2490 ( .A(n1274), .Y(n1275) );
AOI21X4TS U2491 ( .A0(n1373), .A1(n1291), .B0(n1293), .Y(n1278) );
NAND2X1TS U2492 ( .A(n1365), .B(n1292), .Y(n1277) );
XNOR2X2TS U2493 ( .A(n1622), .B(n1269), .Y(n1297) );
OAI22X2TS U2494 ( .A0(n1279), .A1(n1497), .B0(n1297), .B1(n425), .Y(n1746)
);
INVX2TS U2495 ( .A(n1746), .Y(n1310) );
OAI22X2TS U2496 ( .A0(n1547), .A1(n1551), .B0(n1284), .B1(n1546), .Y(n2538)
);
INVX2TS U2497 ( .A(n2538), .Y(n1317) );
INVX2TS U2498 ( .A(n2539), .Y(n1316) );
NAND2X1TS U2499 ( .A(n1597), .B(n1282), .Y(n1315) );
INVX2TS U2500 ( .A(n1305), .Y(n1285) );
NOR2BX2TS U2501 ( .AN(n1499), .B(n1676), .Y(n1287) );
INVX2TS U2502 ( .A(n1287), .Y(n1299) );
INVX2TS U2503 ( .A(n1540), .Y(n1675) );
OAI22X1TS U2504 ( .A0(n1677), .A1(n1675), .B0(n1676), .B1(n1290), .Y(n1354)
);
INVX2TS U2505 ( .A(n1295), .Y(n1296) );
CMPR32X2TS U2506 ( .A(n2548), .B(n1299), .C(n1298), .CO(n1330), .S(n1308) );
XNOR2X2TS U2507 ( .A(n1647), .B(n1545), .Y(n1381) );
XOR2X4TS U2508 ( .A(n1301), .B(n1410), .Y(n1302) );
XNOR2X1TS U2509 ( .A(n1410), .B(n1551), .Y(n1303) );
INVX2TS U2510 ( .A(n2507), .Y(n1352) );
INVX2TS U2511 ( .A(n1410), .Y(n1713) );
INVX2TS U2512 ( .A(n2506), .Y(n1383) );
NAND2BX1TS U2513 ( .AN(n1604), .B(n1421), .Y(n1306) );
ADDFHX2TS U2514 ( .A(n1309), .B(n1308), .CI(n1307), .CO(n1392), .S(n1325) );
NOR2X4TS U2515 ( .A(n1325), .B(n1324), .Y(n2688) );
CMPR32X2TS U2516 ( .A(n1317), .B(n1316), .C(n1315), .CO(n1309), .S(n1321) );
NOR2BX1TS U2517 ( .AN(n443), .B(n1546), .Y(n3281) );
INVX2TS U2518 ( .A(n3281), .Y(n1318) );
OR2X2TS U2519 ( .A(n1319), .B(n1318), .Y(n2601) );
NOR2BX1TS U2520 ( .AN(n1499), .B(n425), .Y(n3349) );
INVX2TS U2521 ( .A(n3349), .Y(n2602) );
NAND2X2TS U2522 ( .A(n1319), .B(n1318), .Y(n2600) );
INVX2TS U2523 ( .A(n2600), .Y(n1320) );
NAND2X2TS U2524 ( .A(n1322), .B(n1321), .Y(n2632) );
INVX2TS U2525 ( .A(n2632), .Y(n1323) );
NAND2X2TS U2526 ( .A(n1325), .B(n1324), .Y(n2689) );
AOI21X4TS U2527 ( .A0(n2742), .A1(n2743), .B0(n1328), .Y(n2794) );
CMPR32X2TS U2528 ( .A(n1331), .B(n1330), .C(n1329), .CO(n1457), .S(n1326) );
AOI21X4TS U2529 ( .A0(n1338), .A1(n1337), .B0(n1336), .Y(n1561) );
INVX2TS U2530 ( .A(n1401), .Y(n1339) );
NOR2X4TS U2531 ( .A(n1345), .B(n1344), .Y(n1513) );
INVX2TS U2532 ( .A(n1513), .Y(n1346) );
NAND2X4TS U2533 ( .A(n1345), .B(n1344), .Y(n1515) );
NAND2X2TS U2534 ( .A(n1346), .B(n1515), .Y(n1347) );
INVX2TS U2535 ( .A(n2378), .Y(n1435) );
NOR2X1TS U2536 ( .A(Op_MY[10]), .B(n3806), .Y(n1360) );
XNOR2X1TS U2537 ( .A(n1360), .B(n506), .Y(n1361) );
XOR2X2TS U2538 ( .A(n1362), .B(n1361), .Y(n1363) );
BUFX12TS U2539 ( .A(n1363), .Y(n2336) );
NOR2BX1TS U2540 ( .AN(n1499), .B(n2336), .Y(n1454) );
NAND2X2TS U2541 ( .A(n1365), .B(n1364), .Y(n1371) );
INVX2TS U2542 ( .A(n1366), .Y(n1367) );
AOI21X2TS U2543 ( .A0(n1364), .A1(n1368), .B0(n1367), .Y(n1369) );
XOR2X4TS U2544 ( .A(n1433), .B(Op_MX[11]), .Y(n1500) );
XNOR2X2TS U2545 ( .A(n1500), .B(n1269), .Y(n1434) );
OAI22X1TS U2546 ( .A0(n1377), .A1(n1677), .B0(n1430), .B1(n1676), .Y(n1452)
);
XNOR2X2TS U2547 ( .A(n1605), .B(n1421), .Y(n1422) );
OAI22X2TS U2548 ( .A0(n1505), .A1(n1378), .B0(n1422), .B1(n2335), .Y(n1399)
);
NAND2X4TS U2549 ( .A(DP_OP_153J7_122_5442_n1127), .B(
DP_OP_153J7_122_5442_n1103), .Y(n1379) );
XNOR2X4TS U2550 ( .A(n3991), .B(n1379), .Y(n1441) );
XNOR2X4TS U2551 ( .A(n1441), .B(n1410), .Y(n1380) );
XNOR2X2TS U2552 ( .A(n1410), .B(n1283), .Y(n1411) );
INVX2TS U2553 ( .A(n2501), .Y(n1424) );
ADDFHX2TS U2554 ( .A(Op_MY[10]), .B(n3806), .CI(n1386), .CO(n1445), .S(n1444) );
XNOR2X4TS U2555 ( .A(n1440), .B(n1387), .Y(n1391) );
NOR2BX1TS U2556 ( .AN(n484), .B(n451), .Y(n1397) );
NAND2X4TS U2557 ( .A(n1396), .B(n1395), .Y(n2791) );
OAI21X4TS U2558 ( .A0(n2794), .A1(n2790), .B0(n2791), .Y(n2846) );
ADDFHX2TS U2559 ( .A(n1399), .B(n1398), .CI(n1397), .CO(n1525), .S(n1427) );
OAI21X2TS U2560 ( .A0(n1561), .A1(n1513), .B0(n1515), .Y(n1407) );
OAI21X4TS U2561 ( .A0(n1486), .A1(n1401), .B0(n1400), .Y(n1403) );
XNOR2X4TS U2562 ( .A(n1403), .B(n1402), .Y(n2324) );
NOR2X4TS U2563 ( .A(n2324), .B(n1404), .Y(n1516) );
INVX2TS U2564 ( .A(n1516), .Y(n1405) );
NAND2X2TS U2565 ( .A(n2324), .B(n1404), .Y(n1514) );
NAND2X2TS U2566 ( .A(n1405), .B(n1514), .Y(n1406) );
XNOR2X4TS U2567 ( .A(n1407), .B(n1406), .Y(n1408) );
OAI22X2TS U2568 ( .A0(n1550), .A1(n1411), .B0(n1481), .B1(n1714), .Y(n1478)
);
OAI22X2TS U2569 ( .A0(n1489), .A1(n1546), .B0(n1547), .B1(n1412), .Y(n1477)
);
ADDFHX2TS U2570 ( .A(n1415), .B(n1414), .CI(n1413), .CO(n1475), .S(n2502) );
OAI21X4TS U2571 ( .A0(n3946), .A1(DP_OP_153J7_122_5442_n1102), .B0(
DP_OP_153J7_122_5442_n1103), .Y(n1417) );
XNOR2X4TS U2572 ( .A(n1417), .B(n1416), .Y(n1418) );
XNOR2X1TS U2573 ( .A(n485), .B(n443), .Y(n1420) );
XNOR2X1TS U2574 ( .A(n485), .B(n1552), .Y(n1480) );
OAI22X1TS U2575 ( .A0(n2872), .A1(n1420), .B0(n1480), .B1(n2871), .Y(n1474)
);
INVX2TS U2576 ( .A(n2563), .Y(n1512) );
OAI22X2TS U2577 ( .A0(n1506), .A1(n477), .B0(n1505), .B1(n1422), .Y(n1511)
);
INVX2TS U2578 ( .A(n1418), .Y(n2870) );
NAND2BX1TS U2579 ( .AN(n443), .B(n485), .Y(n1423) );
OAI22X2TS U2580 ( .A0(n2872), .A1(n2870), .B0(n1423), .B1(n2871), .Y(n2562)
);
INVX2TS U2581 ( .A(n2562), .Y(n1504) );
ADDFHX2TS U2582 ( .A(n1426), .B(n1425), .CI(n1424), .CO(n1503), .S(n1398) );
OAI22X1TS U2583 ( .A0(n1430), .A1(n1677), .B0(n1676), .B1(n1501), .Y(n1509)
);
XNOR2X1TS U2584 ( .A(n1538), .B(n1683), .Y(n1494) );
XNOR2X1TS U2585 ( .A(n1499), .B(n1683), .Y(n1431) );
NAND2X6TS U2586 ( .A(n2336), .B(n514), .Y(n2337) );
OAI22X1TS U2587 ( .A0(n1494), .A1(n2336), .B0(n1431), .B1(n2337), .Y(n1508)
);
INVX4TS U2588 ( .A(n1683), .Y(n2339) );
OAI22X1TS U2589 ( .A0(n1432), .A1(n2336), .B0(n2337), .B1(n2339), .Y(n1496)
);
NAND2X6TS U2590 ( .A(n1433), .B(n521), .Y(n2338) );
INVX2TS U2591 ( .A(n3068), .Y(n1463) );
XOR2X1TS U2592 ( .A(n1445), .B(n1438), .Y(n1439) );
NOR2X2TS U2593 ( .A(n1440), .B(n1439), .Y(n1442) );
CLKXOR2X2TS U2594 ( .A(n1442), .B(n1464), .Y(n1443) );
NAND2X6TS U2595 ( .A(n451), .B(n1443), .Y(n3149) );
XNOR2X2TS U2596 ( .A(n1465), .B(n1464), .Y(n1449) );
INVX2TS U2597 ( .A(n2341), .Y(n3148) );
OAI22X2TS U2598 ( .A0(n3149), .A1(n3148), .B0(n452), .B1(n1450), .Y(n1493)
);
XNOR2X1TS U2599 ( .A(n2341), .B(n484), .Y(n1451) );
INVX2TS U2600 ( .A(n3069), .Y(n1491) );
ADDFHX2TS U2601 ( .A(n1457), .B(n1456), .CI(n1455), .CO(n1458), .S(n1396) );
NAND2X4TS U2602 ( .A(n1459), .B(n1458), .Y(n2844) );
AOI21X4TS U2603 ( .A0(n2846), .A1(n2845), .B0(n1460), .Y(n3005) );
XNOR2X4TS U2604 ( .A(n1469), .B(n1468), .Y(n1470) );
XNOR2X1TS U2605 ( .A(n1471), .B(n1470), .Y(n1472) );
XOR2X4TS U2606 ( .A(n1473), .B(n1472), .Y(n1573) );
ADDHX1TS U2607 ( .A(n1478), .B(n1477), .CO(n1580), .S(n1476) );
XNOR2X1TS U2608 ( .A(n485), .B(n1283), .Y(n1479) );
OAI22X1TS U2609 ( .A0(n2872), .A1(n1480), .B0(n1479), .B1(n2871), .Y(n1579)
);
XNOR2X2TS U2610 ( .A(n1410), .B(n1716), .Y(n1549) );
OAI22X2TS U2611 ( .A0(n1550), .A1(n1481), .B0(n1549), .B1(n1714), .Y(n1544)
);
INVX2TS U2612 ( .A(n1483), .Y(n1484) );
OA21X4TS U2613 ( .A0(n1486), .A1(n1485), .B0(n1484), .Y(n1488) );
NOR2BX1TS U2614 ( .AN(n443), .B(n2868), .Y(n1542) );
INVX2TS U2615 ( .A(n2582), .Y(n1554) );
XNOR2X1TS U2616 ( .A(n1622), .B(n1683), .Y(n1534) );
OAI22X1TS U2617 ( .A0(n1494), .A1(n2337), .B0(n1534), .B1(n2336), .Y(n1572)
);
ADDHX1TS U2618 ( .A(n1496), .B(n1495), .CO(n1571), .S(n1507) );
INVX4TS U2619 ( .A(n1269), .Y(n1703) );
OAI22X1TS U2620 ( .A0(n1498), .A1(n1497), .B0(n1703), .B1(n425), .Y(n1537)
);
NOR2BX1TS U2621 ( .AN(n1499), .B(n2339), .Y(n1536) );
INVX2TS U2622 ( .A(n3122), .Y(n1581) );
OAI22X1TS U2623 ( .A0(n3149), .A1(n1502), .B0(n451), .B1(n1577), .Y(n1533)
);
OAI22X1TS U2624 ( .A0(n1569), .A1(n477), .B0(n1506), .B1(n1505), .Y(n1531)
);
INVX2TS U2625 ( .A(n3121), .Y(n1568) );
ADDFHX2TS U2626 ( .A(n1512), .B(n1511), .CI(n1510), .CO(n1567), .S(n1523) );
NOR2X4TS U2627 ( .A(n1513), .B(n1516), .Y(n1557) );
INVX2TS U2628 ( .A(n1557), .Y(n1518) );
OAI21X4TS U2629 ( .A0(n1516), .A1(n1515), .B0(n1514), .Y(n1558) );
INVX2TS U2630 ( .A(n1558), .Y(n1517) );
OAI21X2TS U2631 ( .A0(n1561), .A1(n1518), .B0(n1517), .Y(n1520) );
XNOR2X4TS U2632 ( .A(n1520), .B(n3016), .Y(n1521) );
OAI22X1TS U2633 ( .A0(n1522), .A1(n1597), .B0(n1562), .B1(n1596), .Y(n1566)
);
OAI21X4TS U2634 ( .A0(n3005), .A1(n3002), .B0(n3003), .Y(n2293) );
ADDFHX2TS U2635 ( .A(n1533), .B(n1532), .CI(n1531), .CO(n1630), .S(n1565) );
OAI22X1TS U2636 ( .A0(n1534), .A1(n2337), .B0(n1619), .B1(n2336), .Y(n1618)
);
INVX2TS U2637 ( .A(n1538), .Y(n1539) );
INVX2TS U2638 ( .A(n1703), .Y(n1679) );
XNOR2X2TS U2639 ( .A(n2338), .B(n1540), .Y(n1624) );
OAI22X1TS U2640 ( .A0(n1541), .A1(n1677), .B0(n1676), .B1(n1624), .Y(n1620)
);
INVX2TS U2641 ( .A(n3374), .Y(n1629) );
XNOR2X1TS U2642 ( .A(n485), .B(n1647), .Y(n1590) );
OAI22X1TS U2643 ( .A0(n2872), .A1(n1479), .B0(n1590), .B1(n2871), .Y(n1609)
);
OAI22X2TS U2644 ( .A0(n1548), .A1(n1547), .B0(n2327), .B1(n1546), .Y(n1589)
);
OAI22X2TS U2645 ( .A0(n1591), .A1(n1714), .B0(n1550), .B1(n1549), .Y(n1588)
);
INVX2TS U2646 ( .A(n1551), .Y(n1553) );
OAI22X1TS U2647 ( .A0(n3017), .A1(n1553), .B0(n2868), .B1(n1592), .Y(n1587)
);
INVX2TS U2648 ( .A(n2610), .Y(n1601) );
OAI21X4TS U2649 ( .A0(n1561), .A1(n1560), .B0(n1559), .Y(n3214) );
XNOR2X2TS U2650 ( .A(n3214), .B(n1595), .Y(n1598) );
OAI22X1TS U2651 ( .A0(n1562), .A1(n1597), .B0(n1598), .B1(n1596), .Y(n1599)
);
ADDFHX2TS U2652 ( .A(n1565), .B(n1564), .CI(n1563), .CO(n1632), .S(n1584) );
ADDFHX2TS U2653 ( .A(n1568), .B(n1567), .CI(n1566), .CO(n1612), .S(n1564) );
OAI22X1TS U2654 ( .A0(n1603), .A1(n477), .B0(n1569), .B1(n1505), .Y(n1627)
);
INVX2TS U2655 ( .A(n3373), .Y(n1626) );
NAND2BX1TS U2656 ( .AN(n484), .B(n3156), .Y(n1575) );
XNOR2X1TS U2657 ( .A(n484), .B(n3156), .Y(n1576) );
XNOR2X2TS U2658 ( .A(n1649), .B(n3156), .Y(n1606) );
OAI22X2TS U2659 ( .A0(n3149), .A1(n1577), .B0(n451), .B1(n1602), .Y(n1614)
);
INVX2TS U2660 ( .A(n2609), .Y(n1613) );
ADDFHX4TS U2661 ( .A(n1586), .B(n1585), .CI(n1584), .CO(n1634), .S(n1530) );
NOR2X8TS U2662 ( .A(n1635), .B(n1634), .Y(n3040) );
XNOR2X1TS U2663 ( .A(n1418), .B(n1716), .Y(n1643) );
OAI22X1TS U2664 ( .A0(n2872), .A1(n1590), .B0(n1643), .B1(n2871), .Y(n1641)
);
INVX2TS U2665 ( .A(n1283), .Y(n1648) );
OAI22X1TS U2666 ( .A0(n3017), .A1(n1592), .B0(n2868), .B1(n1648), .Y(n1644)
);
INVX2TS U2667 ( .A(n1595), .Y(n1693) );
OAI22X1TS U2668 ( .A0(n1598), .A1(n1597), .B0(n1693), .B1(n1596), .Y(n1669)
);
ADDFHX2TS U2669 ( .A(n1601), .B(n1600), .CI(n1599), .CO(n1667), .S(n1628) );
OAI22X1TS U2670 ( .A0(n1655), .A1(n452), .B0(n3149), .B1(n1602), .Y(n1654)
);
XNOR2X2TS U2671 ( .A(n1521), .B(n1421), .Y(n1656) );
NOR2BX1TS U2672 ( .AN(n484), .B(n448), .Y(n1659) );
OAI22X1TS U2673 ( .A0(n3197), .A1(n1606), .B0(n1651), .B1(n3196), .Y(n1658)
);
INVX2TS U2674 ( .A(n2629), .Y(n1657) );
INVX2TS U2675 ( .A(n3394), .Y(n1664) );
INVX2TS U2676 ( .A(n1622), .Y(n1623) );
INVX2TS U2677 ( .A(n3395), .Y(n1663) );
ADDFHX1TS U2678 ( .A(n1630), .B(n1629), .CI(n1628), .CO(n1660), .S(n1633) );
NOR2X4TS U2679 ( .A(n3040), .B(n2294), .Y(n1639) );
NAND2X4TS U2680 ( .A(n1635), .B(n1634), .Y(n3041) );
INVX2TS U2681 ( .A(n2696), .Y(n1727) );
XNOR2X1TS U2682 ( .A(n1418), .B(n2324), .Y(n1709) );
OAI22X1TS U2683 ( .A0(n2872), .A1(n1643), .B0(n1709), .B1(n2871), .Y(n1708)
);
OAI22X2TS U2684 ( .A0(n1646), .A1(n1550), .B0(n1714), .B1(n1713), .Y(n1711)
);
OAI22X1TS U2685 ( .A0(n3017), .A1(n1648), .B0(n2868), .B1(n1250), .Y(n1710)
);
INVX2TS U2686 ( .A(n1649), .Y(n1650) );
XNOR2X2TS U2687 ( .A(n2332), .B(n3156), .Y(n1695) );
OAI22X1TS U2688 ( .A0(n1699), .A1(n452), .B0(n1655), .B1(n3149), .Y(n1698)
);
OAI22X1TS U2689 ( .A0(n1656), .A1(n1505), .B0(n1691), .B1(n2335), .Y(n1697)
);
ADDFHX2TS U2690 ( .A(n1668), .B(n1667), .CI(n1666), .CO(n1718), .S(n1687) );
CMPR32X2TS U2691 ( .A(n1671), .B(n1670), .C(n1669), .CO(n1721), .S(n1668) );
CMPR32X2TS U2692 ( .A(n1674), .B(n1673), .C(n1672), .CO(n3398), .S(n3395) );
CMPR32X2TS U2693 ( .A(n1680), .B(n1679), .C(n1678), .CO(n1723), .S(n1672) );
INVX2TS U2694 ( .A(n1681), .Y(n1682) );
XNOR2X2TS U2695 ( .A(n2338), .B(n1683), .Y(n1701) );
OAI22X1TS U2696 ( .A0(n1684), .A1(n2337), .B0(n1701), .B1(n2336), .Y(n1702)
);
INVX2TS U2697 ( .A(n3399), .Y(n1720) );
INVX2TS U2698 ( .A(n2321), .Y(n1690) );
OAI22X1TS U2699 ( .A0(n1691), .A1(n1505), .B0(n2335), .B1(n2334), .Y(n2360)
);
OAI22X1TS U2700 ( .A0(n1699), .A1(n3149), .B0(n2342), .B1(n452), .Y(n2347)
);
INVX2TS U2701 ( .A(n1500), .Y(n1700) );
INVX2TS U2702 ( .A(n3111), .Y(n2344) );
ADDFHX2TS U2703 ( .A(n1704), .B(n1703), .CI(n1702), .CO(n2343), .S(n1722) );
INVX2TS U2704 ( .A(n1605), .Y(n1705) );
ADDFX2TS U2705 ( .A(n1708), .B(n1707), .CI(n1706), .CO(n2756), .S(n2695) );
INVX2TS U2706 ( .A(n2756), .Y(n2356) );
OAI22X1TS U2707 ( .A0(n2872), .A1(n1709), .B0(n2323), .B1(n2871), .Y(n2331)
);
INVX2TS U2708 ( .A(n1716), .Y(n2325) );
OAI22X1TS U2709 ( .A0(n3017), .A1(n1250), .B0(n2868), .B1(n2325), .Y(n2326)
);
ADDFHX2TS U2710 ( .A(n1719), .B(n1718), .CI(n1717), .CO(n2365), .S(n1731) );
INVX2TS U2711 ( .A(n3398), .Y(n2353) );
CMPR32X2TS U2712 ( .A(n1724), .B(n1723), .C(n1722), .CO(n3408), .S(n3399) );
XOR2X4TS U2713 ( .A(n1737), .B(n1736), .Y(n2318) );
INVX2TS U2714 ( .A(n1738), .Y(n1739) );
INVX2TS U2715 ( .A(n1741), .Y(n1743) );
NOR2X1TS U2716 ( .A(n1746), .B(n1287), .Y(n2373) );
INVX2TS U2717 ( .A(n2373), .Y(n1747) );
NAND2X1TS U2718 ( .A(n1746), .B(n1287), .Y(n2371) );
NAND2X1TS U2719 ( .A(n1747), .B(n2371), .Y(n1748) );
XOR2X1TS U2720 ( .A(n1748), .B(n2372), .Y(n2464) );
NOR2X2TS U2721 ( .A(n417), .B(n397), .Y(n1853) );
NOR2X2TS U2722 ( .A(n423), .B(n1846), .Y(n1851) );
NOR2X2TS U2723 ( .A(n1948), .B(n428), .Y(n1850) );
NOR2X4TS U2724 ( .A(n420), .B(n1979), .Y(n1817) );
NOR2X2TS U2725 ( .A(n4184), .B(n427), .Y(n1894) );
NOR2X2TS U2726 ( .A(n4184), .B(n1939), .Y(n1829) );
NOR2X4TS U2727 ( .A(n521), .B(n422), .Y(n1752) );
NOR2X2TS U2728 ( .A(DP_OP_155J7_124_2038_n725), .B(DP_OP_155J7_124_2038_n728), .Y(n1751) );
NOR2X2TS U2729 ( .A(n422), .B(DP_OP_155J7_124_2038_n728), .Y(n1774) );
NOR2X2TS U2730 ( .A(n418), .B(DP_OP_155J7_124_2038_n728), .Y(n1892) );
NOR2X2TS U2731 ( .A(n2257), .B(n398), .Y(n1826) );
NOR2X2TS U2732 ( .A(n418), .B(n517), .Y(n1825) );
NOR2X1TS U2733 ( .A(n419), .B(n427), .Y(n1824) );
OAI21X4TS U2734 ( .A0(n1754), .A1(n1792), .B0(n1789), .Y(n1784) );
INVX8TS U2735 ( .A(n1833), .Y(n1756) );
NOR2X4TS U2736 ( .A(n1831), .B(n1756), .Y(n1758) );
AOI21X4TS U2737 ( .A0(n1784), .A1(n1758), .B0(n1757), .Y(n1844) );
INVX2TS U2738 ( .A(n1766), .Y(n1760) );
XNOR2X4TS U2739 ( .A(n1762), .B(n1761), .Y(n1763) );
INVX2TS U2740 ( .A(n1764), .Y(n1977) );
OAI21X4TS U2741 ( .A0(n1768), .A1(n1844), .B0(n1767), .Y(n1769) );
ADDHX1TS U2742 ( .A(Op_MY[6]), .B(DP_OP_155J7_124_2038_n788), .CO(n1764),
.S(n1770) );
OAI22X1TS U2743 ( .A0(n2397), .A1(n1977), .B0(n483), .B1(n1980), .Y(n1837)
);
CMPR22X2TS U2744 ( .A(n1774), .B(n1773), .CO(n1827), .S(n1877) );
NOR2X2TS U2745 ( .A(n419), .B(n1939), .Y(n1823) );
NOR2X2TS U2746 ( .A(n418), .B(n427), .Y(n1822) );
NOR2X2TS U2747 ( .A(n1950), .B(n2396), .Y(n1811) );
NOR2X4TS U2748 ( .A(n1981), .B(n2244), .Y(n1805) );
NOR2X4TS U2749 ( .A(DP_OP_155J7_124_2038_n725), .B(n1939), .Y(n2061) );
INVX2TS U2750 ( .A(n2061), .Y(n1875) );
INVX2TS U2751 ( .A(n2074), .Y(n1917) );
INVX2TS U2752 ( .A(n1831), .Y(n1785) );
XOR2X4TS U2753 ( .A(n1830), .B(n1786), .Y(n1787) );
NAND2X2TS U2754 ( .A(n1790), .B(n1789), .Y(n1791) );
XOR2X4TS U2755 ( .A(n1792), .B(n1791), .Y(n1793) );
ADDHX1TS U2756 ( .A(Op_MY[8]), .B(Op_MY[2]), .CO(n1794), .S(n1788) );
NOR2X2TS U2757 ( .A(n421), .B(n1979), .Y(n1800) );
NOR2X2TS U2758 ( .A(n423), .B(n431), .Y(n1799) );
NOR2X2TS U2759 ( .A(n1948), .B(n1938), .Y(n1902) );
NOR2X2TS U2760 ( .A(n418), .B(n1939), .Y(n1802) );
NOR2X2TS U2761 ( .A(n418), .B(n398), .Y(n1905) );
NOR2X2TS U2762 ( .A(n422), .B(n427), .Y(n1904) );
ADDHX1TS U2763 ( .A(Op_MY[4]), .B(Op_MY[10]), .CO(n1795), .S(n1778) );
OAI22X1TS U2764 ( .A0(n453), .A1(n2244), .B0(n1981), .B1(n2398), .Y(n1808)
);
ADDHX1TS U2765 ( .A(DP_OP_155J7_124_2038_n791), .B(Op_MY[9]), .CO(n1797),
.S(n1796) );
CMPR32X2TS U2766 ( .A(n1800), .B(n1799), .C(n1798), .CO(n2073), .S(n2071) );
INVX2TS U2767 ( .A(n2073), .Y(n1901) );
ADDFHX2TS U2768 ( .A(n1808), .B(n1807), .CI(n1806), .CO(n1859), .S(n1929) );
ADDHX1TS U2769 ( .A(DP_OP_155J7_124_2038_n793), .B(Op_MY[11]), .CO(n1809),
.S(n1776) );
OAI22X1TS U2770 ( .A0(n453), .A1(n2396), .B0(n1950), .B1(n2433), .Y(n1862)
);
OAI22X1TS U2771 ( .A0(n482), .A1(n2244), .B0(n453), .B1(n2398), .Y(n1860) );
ADDFHX2TS U2772 ( .A(n1814), .B(n1813), .CI(n1812), .CO(n1868), .S(n1781) );
ADDFHX2TS U2773 ( .A(n1817), .B(n1816), .CI(n1815), .CO(n1847), .S(n1867) );
ADDFHX2TS U2774 ( .A(n1820), .B(n1819), .CI(n1818), .CO(n1883), .S(n1866) );
INVX2TS U2775 ( .A(n2078), .Y(n1865) );
ADDFHX2TS U2776 ( .A(n1826), .B(n1825), .CI(n1824), .CO(n1888), .S(n1870) );
OAI21X4TS U2777 ( .A0(n1831), .A1(n1830), .B0(DP_OP_155J7_124_2038_n388),
.Y(n1835) );
XNOR2X4TS U2778 ( .A(n1835), .B(n1834), .Y(n1836) );
OAI22X1TS U2779 ( .A0(n2215), .A1(n2202), .B0(n482), .B1(n2255), .Y(n1863)
);
ADDFHX2TS U2780 ( .A(n1839), .B(n1838), .CI(n1837), .CO(n2052), .S(n1923) );
INVX2TS U2781 ( .A(n1840), .Y(n1842) );
NAND2X2TS U2782 ( .A(n1842), .B(n1841), .Y(n1843) );
XOR2X4TS U2783 ( .A(n1844), .B(n1843), .Y(n1845) );
ADDFHX2TS U2784 ( .A(n1849), .B(n1848), .CI(n1847), .CO(n2045), .S(n1882) );
CMPR22X2TS U2785 ( .A(n1851), .B(n1850), .CO(n2042), .S(n1848) );
ADDHX1TS U2786 ( .A(DP_OP_155J7_124_2038_n789), .B(DP_OP_155J7_124_2038_n783), .CO(n1855), .S(n1856) );
OAI22X1TS U2787 ( .A0(n2397), .A1(n2023), .B0(n483), .B1(n1949), .Y(n2034)
);
ADDFHX2TS U2788 ( .A(n1859), .B(n1858), .CI(n1857), .CO(n2050), .S(n1921) );
ADDFHX2TS U2789 ( .A(n1862), .B(n1861), .CI(n1860), .CO(n2026), .S(n1858) );
ADDFHX2TS U2790 ( .A(n1865), .B(n1864), .CI(n1863), .CO(n2024), .S(n1857) );
OAI22X1TS U2791 ( .A0(n2022), .A1(n2027), .B0(n2021), .B1(n2211), .Y(n1911)
);
INVX2TS U2792 ( .A(n2413), .Y(n1909) );
OAI22X1TS U2793 ( .A0(n2243), .A1(n1949), .B0(n2022), .B1(n2023), .Y(n1928)
);
OAI22X1TS U2794 ( .A0(n1978), .A1(n2202), .B0(n1950), .B1(n2255), .Y(n1914)
);
NOR2X2TS U2795 ( .A(n1950), .B(n2202), .Y(n1907) );
OAI22X1TS U2796 ( .A0(n2245), .A1(n1980), .B0(n2243), .B1(n1977), .Y(n1926)
);
OAI22X1TS U2797 ( .A0(n2243), .A1(n2027), .B0(n2215), .B1(n2211), .Y(n1898)
);
OAI22X1TS U2798 ( .A0(n2397), .A1(n1949), .B0(n2243), .B1(n2023), .Y(n1897)
);
ADDFHX2TS U2799 ( .A(n1881), .B(n1880), .CI(n1879), .CO(n1896), .S(n1931) );
NOR2X1TS U2800 ( .A(n2434), .B(n1977), .Y(n2028) );
ADDFHX2TS U2801 ( .A(n1884), .B(n1883), .CI(n1882), .CO(n2081), .S(n2077) );
ADDFHX2TS U2802 ( .A(n1890), .B(n1889), .CI(n1888), .CO(n2020), .S(n1885) );
NOR2X2TS U2803 ( .A(n2257), .B(n427), .Y(n2014) );
NOR2X1TS U2804 ( .A(n4184), .B(n517), .Y(n2017) );
ADDFHX2TS U2805 ( .A(n1895), .B(n1894), .CI(n1893), .CO(n2015), .S(n1887) );
ADDFHX2TS U2806 ( .A(n1898), .B(n1897), .CI(n1896), .CO(n2047), .S(n1918) );
OAI22X1TS U2807 ( .A0(n2022), .A1(n1949), .B0(n2021), .B1(n2023), .Y(n1937)
);
ADDFHX2TS U2808 ( .A(n1901), .B(n1900), .CI(n1899), .CO(n1806), .S(n1936) );
CMPR22X2TS U2809 ( .A(n1903), .B(n1902), .CO(n1798), .S(n2069) );
INVX2TS U2810 ( .A(n2069), .Y(n1944) );
ADDHX1TS U2811 ( .A(n1905), .B(n1904), .CO(n1801), .S(n2062) );
INVX2TS U2812 ( .A(n2062), .Y(n1943) );
OAI22X2TS U2813 ( .A0(n453), .A1(n2027), .B0(n1981), .B1(n2211), .Y(n1946)
);
ADDFHX2TS U2814 ( .A(n1908), .B(n1907), .CI(n1906), .CO(n1913), .S(n1945) );
OAI22X1TS U2815 ( .A0(n442), .A1(n1980), .B0(n2215), .B1(n1977), .Y(n1961)
);
ADDFHX2TS U2816 ( .A(n1917), .B(n1916), .CI(n1915), .CO(n1930), .S(n1959) );
ADDFHX4TS U2817 ( .A(n1920), .B(n1919), .CI(n1918), .CO(n2010), .S(n1997) );
ADDFHX2TS U2818 ( .A(n1923), .B(n1922), .CI(n1921), .CO(n2055), .S(n1996) );
NOR2X8TS U2819 ( .A(n1925), .B(n1924), .Y(n2183) );
ADDFHX4TS U2820 ( .A(n1928), .B(n1927), .CI(n1926), .CO(n1919), .S(n2001) );
OAI22X1TS U2821 ( .A0(n2021), .A1(n1949), .B0(n453), .B1(n2023), .Y(n1967)
);
ADDFHX2TS U2822 ( .A(n1934), .B(n1933), .CI(n1932), .CO(n1915), .S(n1965) );
ADDFHX2TS U2823 ( .A(n1937), .B(n1936), .CI(n1935), .CO(n1955), .S(n1957) );
INVX2TS U2824 ( .A(n2523), .Y(n1952) );
NOR2X2TS U2825 ( .A(n422), .B(n1939), .Y(n2006) );
INVX2TS U2826 ( .A(n2006), .Y(n1951) );
CMPR32X2TS U2827 ( .A(n2061), .B(n1941), .C(n1940), .CO(n1934), .S(n1972) );
ADDFHX2TS U2828 ( .A(n1947), .B(n1946), .CI(n1945), .CO(n1935), .S(n1963) );
OAI22X1TS U2829 ( .A0(n1978), .A1(n1949), .B0(n1950), .B1(n2023), .Y(n1970)
);
NOR2X2TS U2830 ( .A(n1948), .B(n1979), .Y(n2522) );
INVX2TS U2831 ( .A(n2522), .Y(n1976) );
OAI22X1TS U2832 ( .A0(n482), .A1(n1980), .B0(n453), .B1(n1977), .Y(n1968) );
ADDFHX2TS U2833 ( .A(n1955), .B(n1954), .CI(n1953), .CO(n1998), .S(n1993) );
ADDFHX4TS U2834 ( .A(n1958), .B(n1957), .CI(n1956), .CO(n1999), .S(n1992) );
NOR2X4TS U2835 ( .A(n1992), .B(n1991), .Y(n2134) );
ADDFHX2TS U2836 ( .A(n1964), .B(n1963), .CI(n1962), .CO(n1956), .S(n1989) );
CMPR32X2TS U2837 ( .A(n1967), .B(n1966), .C(n1965), .CO(n1958), .S(n1988) );
ADDFHX2TS U2838 ( .A(n1970), .B(n1969), .CI(n1968), .CO(n1962), .S(n1986) );
CMPR32X2TS U2839 ( .A(n1973), .B(n1972), .C(n1971), .CO(n1964), .S(n1985) );
OR2X4TS U2840 ( .A(n1986), .B(n1985), .Y(n2102) );
ADDFHX2TS U2841 ( .A(n1976), .B(n1975), .CI(n1974), .CO(n1969), .S(n1984) );
OAI22X1TS U2842 ( .A0(n453), .A1(n1980), .B0(n1981), .B1(n1977), .Y(n1983)
);
NOR2X2TS U2843 ( .A(n1984), .B(n1983), .Y(n2109) );
NOR2X2TS U2844 ( .A(n422), .B(n398), .Y(n2173) );
INVX2TS U2845 ( .A(n2173), .Y(n2120) );
INVX2TS U2846 ( .A(n3880), .Y(n2119) );
NAND2X1TS U2847 ( .A(n2120), .B(n2119), .Y(n2121) );
INVX2TS U2848 ( .A(n2123), .Y(n1982) );
OAI21X2TS U2849 ( .A0(n2109), .A1(n513), .B0(n2110), .Y(n2104) );
NAND2X2TS U2850 ( .A(n1986), .B(n1985), .Y(n2101) );
INVX2TS U2851 ( .A(n2101), .Y(n1987) );
NAND2X4TS U2852 ( .A(n1994), .B(n1993), .Y(n2152) );
AOI21X4TS U2853 ( .A0(n2153), .A1(n2154), .B0(n1995), .Y(n2171) );
ADDFHX4TS U2854 ( .A(n1998), .B(n1997), .CI(n1996), .CO(n1924), .S(n2003) );
NAND2X4TS U2855 ( .A(n2003), .B(n2002), .Y(n2169) );
OAI21X4TS U2856 ( .A0(n2171), .A1(n2170), .B0(n2169), .Y(n2188) );
XOR2X4TS U2857 ( .A(n2005), .B(n2004), .Y(n2177) );
NAND2X1TS U2858 ( .A(n2007), .B(n2006), .Y(n2231) );
OAI2BB1X4TS U2859 ( .A0N(n2188), .A1N(n404), .B0(n2185), .Y(n2060) );
NOR2X2TS U2860 ( .A(n2257), .B(n517), .Y(n2208) );
ADDFHX2TS U2861 ( .A(n2017), .B(n2016), .CI(n2015), .CO(n2212), .S(n2018) );
INVX2TS U2862 ( .A(n2678), .Y(n2199) );
NOR2X2TS U2863 ( .A(n483), .B(n2023), .Y(n2200) );
OAI22X1TS U2864 ( .A0(n2397), .A1(n2211), .B0(n483), .B1(n2027), .Y(n2196)
);
OAI22X1TS U2865 ( .A0(n2397), .A1(n2202), .B0(n2243), .B1(n2255), .Y(n2195)
);
ADDFHX2TS U2866 ( .A(n2039), .B(n2038), .CI(n2037), .CO(n2089), .S(n2046) );
NOR2X2TS U2867 ( .A(n420), .B(n2040), .Y(n2093) );
NOR2X2TS U2868 ( .A(n421), .B(n428), .Y(n2092) );
ADDFHX2TS U2869 ( .A(n2043), .B(n2042), .CI(n2041), .CO(n2087), .S(n2044) );
OAI22X1TS U2870 ( .A0(n2243), .A1(n2244), .B0(n2215), .B1(n2398), .Y(n2216)
);
ADDFHX4TS U2871 ( .A(n2055), .B(n2054), .CI(n2053), .CO(n2057), .S(n1925) );
XNOR2X4TS U2872 ( .A(n2060), .B(n2059), .Y(n2179) );
NAND2X1TS U2873 ( .A(n2062), .B(n2061), .Y(n2232) );
NAND2X1TS U2874 ( .A(n526), .B(n2232), .Y(n2063) );
CLKXOR2X2TS U2875 ( .A(n2063), .B(n2231), .Y(n2178) );
NAND2X2TS U2876 ( .A(n2065), .B(n2064), .Y(n2067) );
XNOR2X4TS U2877 ( .A(n2067), .B(n2066), .Y(n2130) );
NOR2X4TS U2878 ( .A(n2076), .B(n2075), .Y(n2570) );
OR2X4TS U2879 ( .A(n2071), .B(n2070), .Y(n2515) );
NOR2X2TS U2880 ( .A(n2069), .B(n2068), .Y(n2525) );
NAND2X1TS U2881 ( .A(n2069), .B(n2068), .Y(n2526) );
OAI21X2TS U2882 ( .A0(n2525), .A1(n2528), .B0(n2526), .Y(n2516) );
INVX2TS U2883 ( .A(n2514), .Y(n2072) );
AOI21X4TS U2884 ( .A0(n2515), .A1(n2516), .B0(n2072), .Y(n2512) );
NOR2X2TS U2885 ( .A(n2074), .B(n2073), .Y(n2509) );
OAI21X4TS U2886 ( .A0(n2512), .A1(n2509), .B0(n2510), .Y(n2113) );
AOI21X4TS U2887 ( .A0(n2080), .A1(n2113), .B0(n2079), .Y(n2166) );
NOR2X2TS U2888 ( .A(n2081), .B(n2082), .Y(n2105) );
NOR2X2TS U2889 ( .A(n2084), .B(n2083), .Y(n2096) );
NOR2X2TS U2890 ( .A(n2105), .B(n2096), .Y(n2157) );
INVX2TS U2891 ( .A(n2157), .Y(n2086) );
NAND2X2TS U2892 ( .A(n2082), .B(n2081), .Y(n2107) );
NAND2X1TS U2893 ( .A(n2084), .B(n2083), .Y(n2097) );
INVX2TS U2894 ( .A(n2163), .Y(n2085) );
OAI21X4TS U2895 ( .A0(n2166), .A1(n2086), .B0(n2085), .Y(n2095) );
ADDFHX4TS U2896 ( .A(n2089), .B(n2088), .CI(n2087), .CO(n2210), .S(n2083) );
NOR2X2TS U2897 ( .A(n417), .B(n428), .Y(n2144) );
INVX2TS U2898 ( .A(n2156), .Y(n2140) );
NAND2X1TS U2899 ( .A(n2210), .B(n2209), .Y(n2160) );
NAND2X1TS U2900 ( .A(n2140), .B(n2160), .Y(n2094) );
XNOR2X4TS U2901 ( .A(n2095), .B(n2094), .Y(n2129) );
OAI21X4TS U2902 ( .A0(n2166), .A1(n2105), .B0(n2107), .Y(n2100) );
INVX2TS U2903 ( .A(n2096), .Y(n2098) );
XNOR2X4TS U2904 ( .A(n2100), .B(n2099), .Y(n2128) );
NAND2X2TS U2905 ( .A(n2102), .B(n2101), .Y(n2103) );
XNOR2X2TS U2906 ( .A(n2104), .B(n2103), .Y(n2127) );
OR2X4TS U2907 ( .A(n2128), .B(n2127), .Y(n2704) );
INVX2TS U2908 ( .A(n2105), .Y(n2106) );
XOR2X4TS U2909 ( .A(n2166), .B(n2108), .Y(n2125) );
INVX2TS U2910 ( .A(n2109), .Y(n2111) );
XOR2X2TS U2911 ( .A(n2112), .B(n513), .Y(n2124) );
OR2X4TS U2912 ( .A(n2125), .B(n2124), .Y(n2605) );
INVX4TS U2913 ( .A(n2113), .Y(n2573) );
OAI21X4TS U2914 ( .A0(n2573), .A1(n2570), .B0(n2571), .Y(n2118) );
INVX2TS U2915 ( .A(n2114), .Y(n2116) );
NAND2X1TS U2916 ( .A(n511), .B(n2121), .Y(n2122) );
XNOR2X1TS U2917 ( .A(n2123), .B(n2122), .Y(n2588) );
NAND2X4TS U2918 ( .A(n2125), .B(n2124), .Y(n2604) );
INVX2TS U2919 ( .A(n2604), .Y(n2126) );
AOI21X4TS U2920 ( .A0(n2605), .A1(n2606), .B0(n2126), .Y(n2635) );
NOR2BX4TS U2921 ( .AN(n2704), .B(n2635), .Y(n2133) );
INVX4TS U2922 ( .A(n2636), .Y(n2703) );
NAND2X2TS U2923 ( .A(n2130), .B(n2129), .Y(n2706) );
AOI21X4TS U2924 ( .A0(n2707), .A1(n2703), .B0(n2131), .Y(n2132) );
OAI2BB1X4TS U2925 ( .A0N(n2707), .A1N(n2133), .B0(n2132), .Y(n2751) );
INVX2TS U2926 ( .A(n2134), .Y(n2136) );
XOR2X4TS U2927 ( .A(n2138), .B(n2137), .Y(n2150) );
NAND2X1TS U2928 ( .A(n2157), .B(n2140), .Y(n2142) );
INVX2TS U2929 ( .A(n2160), .Y(n2139) );
AOI21X1TS U2930 ( .A0(n2140), .A1(n2163), .B0(n2139), .Y(n2141) );
NOR2X2TS U2931 ( .A(n420), .B(n428), .Y(n2256) );
NOR2X2TS U2932 ( .A(n2258), .B(n2256), .Y(n2159) );
INVX2TS U2933 ( .A(n2159), .Y(n2146) );
NAND2X1TS U2934 ( .A(n2258), .B(n2256), .Y(n2158) );
NAND2X1TS U2935 ( .A(n2146), .B(n2158), .Y(n2147) );
XNOR2X4TS U2936 ( .A(n2148), .B(n2147), .Y(n2149) );
NAND2X4TS U2937 ( .A(n2150), .B(n2149), .Y(n2748) );
AOI21X4TS U2938 ( .A0(n2751), .A1(n2749), .B0(n2151), .Y(n2798) );
NOR2X1TS U2939 ( .A(n2156), .B(n2159), .Y(n2162) );
NAND2X1TS U2940 ( .A(n2157), .B(n2162), .Y(n2165) );
OAI21X1TS U2941 ( .A0(n2160), .A1(n2159), .B0(n2158), .Y(n2161) );
AOI21X1TS U2942 ( .A0(n2163), .A1(n2162), .B0(n2161), .Y(n2164) );
OAI21X4TS U2943 ( .A0(n2798), .A1(n2795), .B0(n2796), .Y(n2852) );
NAND2X4TS U2944 ( .A(n2177), .B(n2176), .Y(n3019) );
NAND2X4TS U2945 ( .A(n2179), .B(n2178), .Y(n3048) );
AOI21X4TS U2946 ( .A0(n3049), .A1(n3045), .B0(n2180), .Y(n2181) );
OAI21X4TS U2947 ( .A0(n2182), .A1(n3020), .B0(n2181), .Y(n2422) );
INVX4TS U2948 ( .A(n2422), .Y(n3296) );
AOI21X4TS U2949 ( .A0(n2189), .A1(n2188), .B0(n2187), .Y(n2190) );
ADDFHX4TS U2950 ( .A(n2193), .B(n2192), .CI(n2191), .CO(n2225), .S(n2056) );
OAI22X1TS U2951 ( .A0(n2397), .A1(n2244), .B0(n2243), .B1(n2398), .Y(n2264)
);
ADDHX1TS U2952 ( .A(n2201), .B(n2200), .CO(n2263), .S(n2197) );
OAI22X1TS U2953 ( .A0(n2397), .A1(n2255), .B0(n2434), .B1(n2202), .Y(n2262)
);
INVX2TS U2954 ( .A(n2209), .Y(n2247) );
ADDFHX4TS U2955 ( .A(n2214), .B(n2213), .CI(n2212), .CO(n2731), .S(n2678) );
ADDFHX2TS U2956 ( .A(n2224), .B(n2223), .CI(n2222), .CO(n2240), .S(n2192) );
BUFX3TS U2957 ( .A(n2383), .Y(n2236) );
XOR2X4TS U2958 ( .A(n2652), .B(n2228), .Y(n2235) );
NAND2X1TS U2959 ( .A(n516), .B(n2275), .Y(n2233) );
NAND2X1TS U2960 ( .A(n2232), .B(n2231), .Y(n2277) );
XNOR2X2TS U2961 ( .A(n2233), .B(n2277), .Y(n2234) );
OAI21X4TS U2962 ( .A0(n3296), .A1(n3293), .B0(n3294), .Y(n2283) );
OAI21X4TS U2963 ( .A0(n2652), .A1(n2381), .B0(n2236), .Y(n2271) );
OAI22X1TS U2964 ( .A0(n2245), .A1(n2396), .B0(n442), .B1(n2433), .Y(n2404)
);
CMPR32X2TS U2965 ( .A(n2248), .B(n2247), .C(n2246), .CO(n2402), .S(n2251) );
INVX2TS U2966 ( .A(n2779), .Y(n2395) );
INVX2TS U2967 ( .A(n2256), .Y(n2401) );
NOR2X2TS U2968 ( .A(n2257), .B(n521), .Y(n2778) );
INVX2TS U2969 ( .A(n2778), .Y(n2400) );
INVX2TS U2970 ( .A(n2258), .Y(n2399) );
ADDFHX4TS U2971 ( .A(n2267), .B(n2266), .CI(n2265), .CO(n2268), .S(n2226) );
INVX2TS U2972 ( .A(n2416), .Y(n2274) );
NAND2X1TS U2973 ( .A(n2273), .B(n2272), .Y(n2415) );
NAND2X1TS U2974 ( .A(n2274), .B(n2415), .Y(n2278) );
INVX2TS U2975 ( .A(n2275), .Y(n2276) );
CLKXOR2X2TS U2976 ( .A(n2278), .B(n2417), .Y(n2279) );
NOR2X8TS U2977 ( .A(n2280), .B(n2279), .Y(n2420) );
INVX2TS U2978 ( .A(n2420), .Y(n2281) );
NAND2X4TS U2979 ( .A(n2280), .B(n2279), .Y(n2419) );
XNOR2X4TS U2980 ( .A(n2283), .B(n2282), .Y(n3261) );
OR2X2TS U2981 ( .A(n2285), .B(n2284), .Y(n2286) );
AND2X2TS U2982 ( .A(n2286), .B(n2372), .Y(n3351) );
OAI21X4TS U2983 ( .A0(n3056), .A1(n3052), .B0(n3053), .Y(n2292) );
INVX2TS U2984 ( .A(n2288), .Y(n2290) );
XNOR2X4TS U2985 ( .A(n2292), .B(n2291), .Y(n3239) );
INVX2TS U2986 ( .A(n2294), .Y(n2296) );
XNOR2X4TS U2987 ( .A(n2298), .B(n2297), .Y(n3350) );
XNOR2X4TS U2988 ( .A(n424), .B(n2299), .Y(n3355) );
INVX2TS U2989 ( .A(n2311), .Y(n2301) );
NOR2X4TS U2990 ( .A(n2301), .B(n2302), .Y(n2304) );
OAI2BB1X4TS U2991 ( .A0N(n402), .A1N(n2310), .B0(n2313), .Y(n2303) );
AOI21X4TS U2992 ( .A0(n2312), .A1(n2304), .B0(n2303), .Y(n2309) );
AOI21X4TS U2993 ( .A0(n2312), .A1(n2311), .B0(n2310), .Y(n2314) );
INVX2TS U2994 ( .A(n2318), .Y(n2316) );
OAI2BB1X4TS U2995 ( .A0N(n2316), .A1N(n3255), .B0(n2315), .Y(n2317) );
OAI2BB1X4TS U2996 ( .A0N(n2319), .A1N(n2318), .B0(n2317), .Y(
DP_OP_156J7_125_3370_n210) );
AOI21X4TS U2997 ( .A0(n424), .A1(n3137), .B0(n3135), .Y(n2370) );
OAI22X1TS U2998 ( .A0(n2872), .A1(n2323), .B0(n2870), .B1(n2871), .Y(n2867)
);
INVX2TS U2999 ( .A(n2324), .Y(n2869) );
INVX2TS U3000 ( .A(n3014), .Y(n2866) );
INVX2TS U3001 ( .A(n2805), .Y(n3105) );
INVX2TS U3002 ( .A(n2806), .Y(n3104) );
INVX2TS U3003 ( .A(n2332), .Y(n2333) );
INVX2TS U3004 ( .A(n2338), .Y(n2340) );
INVX2TS U3005 ( .A(n3424), .Y(n3106) );
XNOR2X1TS U3006 ( .A(n3214), .B(n2341), .Y(n3102) );
OAI22X1TS U3007 ( .A0(n2342), .A1(n3149), .B0(n3102), .B1(n452), .Y(n3099)
);
CMPR32X2TS U3008 ( .A(n2345), .B(n2344), .C(n2343), .CO(n3425), .S(n3407) );
INVX2TS U3009 ( .A(n3425), .Y(n3098) );
INVX2TS U3010 ( .A(n3407), .Y(n3097) );
ADDFX2TS U3011 ( .A(n2353), .B(n2352), .CI(n2351), .CO(n3093), .S(n2349) );
OAI22X1TS U3012 ( .A0(n3109), .A1(n3196), .B0(n2354), .B1(n3197), .Y(n3096)
);
NOR2X8TS U3013 ( .A(n2368), .B(n2367), .Y(n3130) );
INVX4TS U3014 ( .A(n3130), .Y(n3082) );
NAND2X4TS U3015 ( .A(n2368), .B(n2367), .Y(n3132) );
XOR2X4TS U3016 ( .A(n2370), .B(n2369), .Y(n3171) );
OR2X2TS U3017 ( .A(n2375), .B(n2374), .Y(n2458) );
NAND2X1TS U3018 ( .A(n2375), .B(n2374), .Y(n2457) );
INVX2TS U3019 ( .A(n2457), .Y(n2376) );
INVX2TS U3020 ( .A(n3066), .Y(n2379) );
NAND2X1TS U3021 ( .A(n2378), .B(n2377), .Y(n3065) );
NAND2X1TS U3022 ( .A(n2379), .B(n3065), .Y(n2380) );
XOR2X1TS U3023 ( .A(n3067), .B(n2380), .Y(n3064) );
OAI21X4TS U3024 ( .A0(n2384), .A1(n2383), .B0(n2382), .Y(n2649) );
OAI21X4TS U3025 ( .A0(n2386), .A1(n2652), .B0(n2385), .Y(n2411) );
ADDFHX4TS U3026 ( .A(n2389), .B(n2388), .CI(n2387), .CO(n2409), .S(n2269) );
CMPR32X2TS U3027 ( .A(n2395), .B(n2394), .C(n2393), .CO(n2440), .S(n2392) );
OAI22X1TS U3028 ( .A0(n2397), .A1(n2433), .B0(n2434), .B1(n2396), .Y(n2437)
);
XNOR2X4TS U3029 ( .A(n2411), .B(n2410), .Y(n2425) );
NOR2X2TS U3030 ( .A(n2413), .B(n2412), .Y(n2658) );
INVX2TS U3031 ( .A(n2658), .Y(n2414) );
NAND2X1TS U3032 ( .A(n2414), .B(n2660), .Y(n2418) );
INVX2TS U3033 ( .A(n2663), .Y(n2446) );
CLKXOR2X2TS U3034 ( .A(n2418), .B(n2446), .Y(n2424) );
OAI21X4TS U3035 ( .A0(n2420), .A1(n3294), .B0(n2419), .Y(n2421) );
AOI21X4TS U3036 ( .A0(n2649), .A1(n2427), .B0(n2426), .Y(n2428) );
OAI21X4TS U3037 ( .A0(n2652), .A1(n2429), .B0(n2428), .Y(n2445) );
CMPR32X2TS U3038 ( .A(n2437), .B(n2436), .C(n2435), .CO(n2654), .S(n2439) );
XNOR2X4TS U3039 ( .A(n2445), .B(n2444), .Y(n2453) );
OAI21X1TS U3040 ( .A0(n2446), .A1(n2658), .B0(n2660), .Y(n2451) );
NOR2X2TS U3041 ( .A(n2447), .B(n2448), .Y(n2661) );
INVX2TS U3042 ( .A(n2661), .Y(n2449) );
NAND2X1TS U3043 ( .A(n2449), .B(n2659), .Y(n2450) );
XNOR2X2TS U3044 ( .A(n2451), .B(n2450), .Y(n2452) );
NOR2X8TS U3045 ( .A(n2453), .B(n2452), .Y(n2670) );
NAND2X4TS U3046 ( .A(n2453), .B(n2452), .Y(n2671) );
XNOR2X4TS U3047 ( .A(n2456), .B(n2455), .Y(n3250) );
NAND2X1TS U3048 ( .A(n2458), .B(n2457), .Y(n2460) );
XNOR2X1TS U3049 ( .A(n2460), .B(n2459), .Y(n3365) );
INVX2TS U3050 ( .A(n395), .Y(n2461) );
XOR2X4TS U3051 ( .A(n3076), .B(n2462), .Y(n3312) );
ADDFHX4TS U3052 ( .A(n2464), .B(n2463), .CI(add_x_19_n96), .CO(n3363), .S(
n3357) );
XNOR2X4TS U3053 ( .A(n2472), .B(n2471), .Y(Sgf_operation_EVEN1_Q_left[7]) );
OR2X2TS U3054 ( .A(n2474), .B(n2473), .Y(n2476) );
INVX2TS U3055 ( .A(n2477), .Y(n2479) );
NAND2X1TS U3056 ( .A(n2479), .B(n2478), .Y(n2481) );
INVX2TS U3057 ( .A(n2482), .Y(n2484) );
NAND2X1TS U3058 ( .A(n2484), .B(n2483), .Y(n2486) );
NAND2X1TS U3059 ( .A(n2489), .B(n2488), .Y(n2490) );
CLKXOR2X2TS U3060 ( .A(n2490), .B(n2520), .Y(Sgf_operation_EVEN1_Q_left[2])
);
INVX4TS U3061 ( .A(n2491), .Y(n2500) );
AOI21X2TS U3062 ( .A0(n2500), .A1(n2498), .B0(n2492), .Y(n2496) );
XOR2X4TS U3063 ( .A(n2496), .B(n2495), .Y(Sgf_operation_EVEN1_Q_left[9]) );
OR2X2TS U3064 ( .A(n2501), .B(n2502), .Y(n2567) );
NAND2X1TS U3065 ( .A(n2502), .B(n2501), .Y(n2565) );
NAND2X1TS U3066 ( .A(n2567), .B(n2565), .Y(n2508) );
NAND2X2TS U3067 ( .A(n2539), .B(n2538), .Y(n2540) );
INVX2TS U3068 ( .A(n2540), .Y(n2547) );
AOI21X1TS U3069 ( .A0(n2505), .A1(n2547), .B0(n2504), .Y(n2533) );
OAI21X2TS U3070 ( .A0(n2530), .A1(n2533), .B0(n2531), .Y(n2568) );
XNOR2X2TS U3071 ( .A(n2508), .B(n2568), .Y(n2558) );
NAND2X1TS U3072 ( .A(n2511), .B(n2510), .Y(n2513) );
INVX2TS U3073 ( .A(Sgf_operation_EVEN1_Q_left[4]), .Y(n2576) );
NAND2X1TS U3074 ( .A(n2515), .B(n2514), .Y(n2517) );
INVX2TS U3075 ( .A(n3873), .Y(n2537) );
INVX2TS U3076 ( .A(Sgf_operation_EVEN1_Q_left[3]), .Y(n2536) );
INVX2TS U3077 ( .A(n3032), .Y(n2543) );
INVX2TS U3078 ( .A(n3881), .Y(n2542) );
OR2X2TS U3079 ( .A(n2543), .B(n2542), .Y(n2551) );
INVX2TS U3080 ( .A(n2525), .Y(n2527) );
INVX2TS U3081 ( .A(n3872), .Y(n2550) );
INVX2TS U3082 ( .A(Sgf_operation_EVEN1_Q_left[2]), .Y(n2549) );
INVX2TS U3083 ( .A(n2530), .Y(n2532) );
ADDFHX4TS U3084 ( .A(n2537), .B(n2536), .CI(n2535), .CO(n2575), .S(n2555) );
NAND2X2TS U3085 ( .A(n524), .B(n519), .Y(n2561) );
XNOR2X1TS U3086 ( .A(n2543), .B(n2542), .Y(n2544) );
INVX2TS U3087 ( .A(n3279), .Y(n2546) );
NAND2X1TS U3088 ( .A(n2545), .B(n2544), .Y(n3277) );
OAI21X1TS U3089 ( .A0(n3276), .A1(n2546), .B0(n3277), .Y(n3288) );
XNOR2X1TS U3090 ( .A(n2548), .B(n2547), .Y(n2553) );
OR2X2TS U3091 ( .A(n2553), .B(n2552), .Y(n3286) );
INVX2TS U3092 ( .A(n3285), .Y(n2554) );
NAND2X2TS U3093 ( .A(n2556), .B(n2555), .Y(n3290) );
INVX2TS U3094 ( .A(n3290), .Y(n3257) );
NAND2X2TS U3095 ( .A(n2558), .B(n2557), .Y(n3258) );
INVX2TS U3096 ( .A(n3258), .Y(n2559) );
OAI21X4TS U3097 ( .A0(n2561), .A1(n3256), .B0(n2560), .Y(n3264) );
NOR2X2TS U3098 ( .A(n2563), .B(n2562), .Y(n2586) );
INVX2TS U3099 ( .A(n2586), .Y(n2564) );
INVX2TS U3100 ( .A(n2565), .Y(n2566) );
AOI21X4TS U3101 ( .A0(n2568), .A1(n2567), .B0(n2566), .Y(n2585) );
INVX2TS U3102 ( .A(n2570), .Y(n2572) );
NAND2X1TS U3103 ( .A(n2572), .B(n2571), .Y(n2574) );
INVX2TS U3104 ( .A(n3875), .Y(n2594) );
INVX2TS U3105 ( .A(Sgf_operation_EVEN1_Q_left[5]), .Y(n2593) );
INVX2TS U3106 ( .A(n3262), .Y(n2580) );
AOI21X4TS U3107 ( .A0(n3264), .A1(n3263), .B0(n2580), .Y(n3249) );
NOR2X4TS U3108 ( .A(n2581), .B(n2582), .Y(n2622) );
INVX2TS U3109 ( .A(n2622), .Y(n2583) );
NAND2X2TS U3110 ( .A(n2582), .B(n2581), .Y(n2624) );
NAND2X1TS U3111 ( .A(n2583), .B(n2624), .Y(n2587) );
OAI21X4TS U3112 ( .A0(n2586), .A1(n2585), .B0(n2584), .Y(n2627) );
CLKXOR2X2TS U3113 ( .A(n2587), .B(n2608), .Y(n2596) );
INVX4TS U3114 ( .A(Sgf_operation_EVEN1_Q_left[6]), .Y(n2598) );
ADDFHX4TS U3115 ( .A(n2594), .B(n2593), .CI(n2592), .CO(n2597), .S(n2578) );
NOR2X4TS U3116 ( .A(n2596), .B(n2595), .Y(n3245) );
NAND2X2TS U3117 ( .A(n2596), .B(n2595), .Y(n3246) );
OAI21X4TS U3118 ( .A0(n3249), .A1(n3245), .B0(n3246), .Y(n3243) );
INVX4TS U3119 ( .A(Sgf_operation_EVEN1_Q_left[7]), .Y(n2621) );
ADDFHX4TS U3120 ( .A(n2599), .B(n2598), .CI(n2597), .CO(n2620), .S(n2595) );
NAND2X2TS U3121 ( .A(n2601), .B(n2600), .Y(n2603) );
XNOR2X1TS U3122 ( .A(n2603), .B(n2602), .Y(n2618) );
NAND2X2TS U3123 ( .A(n2605), .B(n2604), .Y(n2607) );
XNOR2X4TS U3124 ( .A(n2607), .B(n2606), .Y(n3877) );
INVX2TS U3125 ( .A(n2625), .Y(n2611) );
NAND2X2TS U3126 ( .A(n2610), .B(n2609), .Y(n2623) );
XNOR2X2TS U3127 ( .A(n2613), .B(n2612), .Y(n2614) );
OR2X4TS U3128 ( .A(n2615), .B(n2614), .Y(n3241) );
AOI21X4TS U3129 ( .A0(n3243), .A1(n3241), .B0(n2616), .Y(n2717) );
ADDHX1TS U3130 ( .A(n2618), .B(n2617), .CO(n2702), .S(n2619) );
ADDFHX4TS U3131 ( .A(n2621), .B(n2620), .CI(n2619), .CO(n2701), .S(n2615) );
NOR2X2TS U3132 ( .A(n2625), .B(n2622), .Y(n2628) );
OAI21X4TS U3133 ( .A0(n2625), .A1(n2624), .B0(n2623), .Y(n2626) );
AOI21X4TS U3134 ( .A0(n2628), .A1(n2627), .B0(n2626), .Y(n2864) );
NAND2X2TS U3135 ( .A(n2629), .B(n2630), .Y(n2754) );
XNOR2X2TS U3136 ( .A(n2804), .B(n2631), .Y(n2700) );
NAND2X2TS U3137 ( .A(n2633), .B(n2632), .Y(n2634) );
XNOR2X4TS U3138 ( .A(n2705), .B(n2637), .Y(n3878) );
NOR2X4TS U3139 ( .A(n2639), .B(n2638), .Y(n2716) );
INVX2TS U3140 ( .A(n2716), .Y(n2640) );
NAND2X4TS U3141 ( .A(n2639), .B(n2638), .Y(n2715) );
NOR2X8TS U3142 ( .A(n395), .B(n2670), .Y(n3072) );
NAND2X4TS U3143 ( .A(n2648), .B(n2643), .Y(n2651) );
AOI21X4TS U3144 ( .A0(n2649), .A1(n2648), .B0(n2647), .Y(n2650) );
OAI21X4TS U3145 ( .A0(n2652), .A1(n2651), .B0(n2650), .Y(n2657) );
CMPR32X2TS U3146 ( .A(n2655), .B(n2654), .C(n2653), .CO(n2656), .S(n2441) );
XNOR2X4TS U3147 ( .A(n2657), .B(n2656), .Y(n2675) );
INVX2TS U3148 ( .A(n2725), .Y(n2667) );
NAND2X1TS U3149 ( .A(n2667), .B(n2727), .Y(n2668) );
CLKXOR2X2TS U3150 ( .A(n2832), .B(n2668), .Y(n2674) );
NOR2X8TS U3151 ( .A(n2670), .B(n2669), .Y(n2673) );
NOR2X8TS U3152 ( .A(n2673), .B(n2672), .Y(n2719) );
OA21X4TS U3153 ( .A0(n2817), .A1(n2719), .B0(n3077), .Y(n2676) );
OAI21X4TS U3154 ( .A0(n2677), .A1(n3076), .B0(n2676), .Y(n2683) );
OAI21X1TS U3155 ( .A0(n2832), .A1(n2725), .B0(n2727), .Y(n2682) );
NOR2X2TS U3156 ( .A(n2679), .B(n2678), .Y(n2728) );
INVX2TS U3157 ( .A(n2728), .Y(n2680) );
NAND2X1TS U3158 ( .A(n2680), .B(n2726), .Y(n2681) );
XNOR2X2TS U3159 ( .A(n2682), .B(n2681), .Y(n2769) );
XNOR2X4TS U3160 ( .A(n2683), .B(n2720), .Y(n3126) );
BUFX6TS U3161 ( .A(n3126), .Y(n3233) );
NAND2X2TS U3162 ( .A(n2685), .B(n2684), .Y(n2687) );
XNOR2X4TS U3163 ( .A(n2687), .B(n2686), .Y(Sgf_operation_EVEN1_Q_left[10])
);
INVX2TS U3164 ( .A(n2688), .Y(n2690) );
INVX2TS U3165 ( .A(n2754), .Y(n2693) );
NOR2X4TS U3166 ( .A(n2695), .B(n2696), .Y(n2755) );
INVX2TS U3167 ( .A(n2755), .Y(n2697) );
NAND2X2TS U3168 ( .A(n2696), .B(n2695), .Y(n2753) );
XOR2X4TS U3169 ( .A(n2699), .B(n2698), .Y(n2762) );
ADDFHX4TS U3170 ( .A(n2702), .B(n2701), .CI(n2700), .CO(n2761), .S(n2639) );
AOI21X2TS U3171 ( .A0(n2705), .A1(n2704), .B0(n2703), .Y(n2709) );
ADDFHX2TS U3172 ( .A(n2712), .B(n2711), .CI(n2710), .CO(n2745), .S(n2638) );
NAND2X4TS U3173 ( .A(n2714), .B(n2713), .Y(n2737) );
OAI21X4TS U3174 ( .A0(n2717), .A1(n2716), .B0(n2715), .Y(n2740) );
NOR2X2TS U3175 ( .A(n3077), .B(n2720), .Y(n2721) );
AOI21X4TS U3176 ( .A0(n3073), .A1(n2722), .B0(n2721), .Y(n2723) );
OAI21X4TS U3177 ( .A0(n3076), .A1(n2724), .B0(n2723), .Y(n2735) );
NOR2X2TS U3178 ( .A(n2725), .B(n2728), .Y(n2823) );
INVX2TS U3179 ( .A(n2823), .Y(n2730) );
OAI21X2TS U3180 ( .A0(n2728), .A1(n2727), .B0(n2726), .Y(n2829) );
INVX2TS U3181 ( .A(n2829), .Y(n2729) );
INVX2TS U3182 ( .A(n2822), .Y(n2775) );
NAND2X1TS U3183 ( .A(n2775), .B(n2826), .Y(n2733) );
XOR2X4TS U3184 ( .A(n2735), .B(n2768), .Y(n3377) );
OAI21X4TS U3185 ( .A0(n3236), .A1(add_x_19_n270), .B0(n3237), .Y(n3308) );
AOI21X4TS U3186 ( .A0(n2740), .A1(n2739), .B0(n2738), .Y(n2786) );
XNOR2X2TS U3187 ( .A(n2744), .B(n2743), .Y(n2812) );
XNOR2X4TS U3188 ( .A(n2751), .B(n2750), .Y(n3882) );
INVX4TS U3189 ( .A(Sgf_operation_EVEN1_Q_left[10]), .Y(n2788) );
NOR2X4TS U3190 ( .A(n2752), .B(n2755), .Y(n2855) );
OAI21X4TS U3191 ( .A0(n2755), .A1(n2754), .B0(n2753), .Y(n2860) );
AOI21X2TS U3192 ( .A0(n2804), .A1(n2855), .B0(n2860), .Y(n2760) );
NOR2X4TS U3193 ( .A(n2757), .B(n2756), .Y(n2854) );
INVX2TS U3194 ( .A(n2854), .Y(n2758) );
NAND2X2TS U3195 ( .A(n2757), .B(n2756), .Y(n2857) );
XOR2X4TS U3196 ( .A(n2760), .B(n2759), .Y(n2787) );
ADDFHX4TS U3197 ( .A(n2763), .B(n2762), .CI(n2761), .CO(n2764), .S(n2714) );
NOR2X4TS U3198 ( .A(n2765), .B(n2764), .Y(n2785) );
INVX2TS U3199 ( .A(n2785), .Y(n2766) );
NAND2X4TS U3200 ( .A(n2765), .B(n2764), .Y(n2784) );
NOR2X4TS U3201 ( .A(n2817), .B(n2816), .Y(n2771) );
NOR2X2TS U3202 ( .A(n3077), .B(n2816), .Y(n2770) );
OAI21X4TS U3203 ( .A0(n3076), .A1(n2773), .B0(n2772), .Y(n2783) );
NAND2X1TS U3204 ( .A(n2823), .B(n2775), .Y(n2777) );
INVX2TS U3205 ( .A(n2826), .Y(n2774) );
AOI21X1TS U3206 ( .A0(n2829), .A1(n2775), .B0(n2774), .Y(n2776) );
OAI21X1TS U3207 ( .A0(n2832), .A1(n2777), .B0(n2776), .Y(n2782) );
NOR2X2TS U3208 ( .A(n2779), .B(n2778), .Y(n2825) );
INVX2TS U3209 ( .A(n2825), .Y(n2780) );
NAND2X1TS U3210 ( .A(n2779), .B(n2778), .Y(n2824) );
NAND2X1TS U3211 ( .A(n2780), .B(n2824), .Y(n2781) );
XNOR2X4TS U3212 ( .A(n2783), .B(n528), .Y(n3453) );
OAI21X4TS U3213 ( .A0(n2786), .A1(n2785), .B0(n2784), .Y(n2843) );
ADDFHX2TS U3214 ( .A(n2789), .B(n2788), .CI(n2787), .CO(n2877), .S(n2810) );
INVX4TS U3215 ( .A(n2790), .Y(n2792) );
XOR2X4TS U3216 ( .A(n2794), .B(n2793), .Y(n2876) );
XNOR2X4TS U3217 ( .A(n2799), .B(n2798), .Y(n3883) );
INVX6TS U3218 ( .A(Sgf_operation_EVEN1_Q_left[11]), .Y(n2849) );
INVX2TS U3219 ( .A(n2855), .Y(n2800) );
INVX2TS U3220 ( .A(n2860), .Y(n2801) );
NOR2X4TS U3221 ( .A(n2806), .B(n2805), .Y(n2858) );
INVX2TS U3222 ( .A(n2858), .Y(n2807) );
NAND2X2TS U3223 ( .A(n2806), .B(n2805), .Y(n2856) );
ADDFHX4TS U3224 ( .A(n2812), .B(n2811), .CI(n2810), .CO(n2813), .S(n2765) );
NOR2X2TS U3225 ( .A(n3077), .B(n426), .Y(n2818) );
AOI21X4TS U3226 ( .A0(n3073), .A1(n2819), .B0(n2818), .Y(n2820) );
OAI21X4TS U3227 ( .A0(n3076), .A1(n2821), .B0(n2820), .Y(n2833) );
NOR2X1TS U3228 ( .A(n2822), .B(n2825), .Y(n2828) );
NAND2X1TS U3229 ( .A(n2823), .B(n2828), .Y(n2831) );
AOI21X1TS U3230 ( .A0(n2829), .A1(n2828), .B0(n2827), .Y(n2830) );
XNOR2X4TS U3231 ( .A(n2833), .B(n527), .Y(n3402) );
OAI21X4TS U3232 ( .A0(n3321), .A1(n3334), .B0(n3335), .Y(n2836) );
AOI21X4TS U3233 ( .A0(n3308), .A1(n3304), .B0(n2836), .Y(n2885) );
NAND2X4TS U3234 ( .A(n2838), .B(n2837), .Y(n2840) );
XNOR2X4TS U3235 ( .A(n2840), .B(n2839), .Y(Sgf_operation_EVEN1_Q_left[12])
);
AOI21X4TS U3236 ( .A0(n2843), .A1(n532), .B0(n2842), .Y(n3029) );
BUFX3TS U3237 ( .A(n3029), .Y(n2882) );
INVX4TS U3238 ( .A(n3282), .Y(n3024) );
NOR2X2TS U3239 ( .A(n2854), .B(n2858), .Y(n2861) );
OAI21X1TS U3240 ( .A0(n2858), .A1(n2857), .B0(n2856), .Y(n2859) );
OAI22X1TS U3241 ( .A0(n3017), .A1(n2869), .B0(n2868), .B1(n3016), .Y(n3013)
);
NAND2X1TS U3242 ( .A(n523), .B(n3009), .Y(n2873) );
INVX4TS U3243 ( .A(Sgf_operation_EVEN1_Q_left[12]), .Y(n3022) );
XNOR2X4TS U3244 ( .A(n2874), .B(n3007), .Y(n2879) );
ADDFHX4TS U3245 ( .A(n2877), .B(n2876), .CI(n2875), .CO(n2878), .S(n2814) );
INVX4TS U3246 ( .A(n3028), .Y(n2880) );
NAND2X4TS U3247 ( .A(n2879), .B(n2878), .Y(n3027) );
NAND2X4TS U3248 ( .A(n2880), .B(n3027), .Y(n2881) );
XOR2X4TS U3249 ( .A(n2882), .B(n2881), .Y(n2884) );
NOR2X6TS U3250 ( .A(n2884), .B(n2883), .Y(n3306) );
OA21X4TS U3251 ( .A0(n2885), .A1(n3306), .B0(n3302), .Y(add_x_19_n234) );
NAND2X1TS U3252 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]),
.Y(n3795) );
NOR3X1TS U3253 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[0]), .C(
n3795), .Y(ready) );
NOR2XLTS U3254 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[1]), .Y(
n2886) );
CLKBUFX2TS U3255 ( .A(n488), .Y(n3698) );
BUFX3TS U3256 ( .A(n3698), .Y(n4216) );
INVX2TS U3257 ( .A(ready), .Y(n2887) );
NOR2BX2TS U3258 ( .AN(n3560), .B(FS_Module_state_reg[1]), .Y(n3708) );
NOR2BX1TS U3259 ( .AN(n3708), .B(zero_flag), .Y(n2978) );
INVX2TS U3260 ( .A(n3796), .Y(n3704) );
NOR2X2TS U3261 ( .A(n4061), .B(n4062), .Y(n3658) );
XOR2X1TS U3262 ( .A(n4109), .B(n4110), .Y(n2889) );
NOR2X2TS U3263 ( .A(n2889), .B(n4033), .Y(n3663) );
AOI21X1TS U3264 ( .A0(n4035), .A1(n4036), .B0(n4037), .Y(n2888) );
NAND2X1TS U3265 ( .A(n2889), .B(n4042), .Y(n3664) );
AOI21X1TS U3266 ( .A0(n4026), .A1(n2891), .B0(n2890), .Y(n2892) );
AOI21X1TS U3267 ( .A0(n2895), .A1(n3657), .B0(n2894), .Y(n3469) );
NOR2X2TS U3268 ( .A(n4112), .B(n4088), .Y(n2898) );
NOR2X2TS U3269 ( .A(n4096), .B(n4097), .Y(n2934) );
NOR2X2TS U3270 ( .A(n2898), .B(n2934), .Y(n2901) );
NOR2X2TS U3271 ( .A(n4101), .B(n4102), .Y(n2924) );
NOR2X2TS U3272 ( .A(n2924), .B(n4093), .Y(n2932) );
NAND2X1TS U3273 ( .A(n2901), .B(n2932), .Y(n2903) );
NOR2X4TS U3274 ( .A(n4107), .B(n4108), .Y(n2919) );
OAI21X1TS U3275 ( .A0(n2919), .A1(n4099), .B0(n4100), .Y(n2896) );
INVX2TS U3276 ( .A(n2898), .Y(n2940) );
NAND2X1TS U3277 ( .A(n4112), .B(n4111), .Y(n2939) );
INVX2TS U3278 ( .A(n2939), .Y(n2899) );
AO21X2TS U3279 ( .A0(n2940), .A1(n4117), .B0(n2899), .Y(n2900) );
AOI21X1TS U3280 ( .A0(n2901), .A1(n2933), .B0(n2900), .Y(n2902) );
NOR2X2TS U3281 ( .A(n2904), .B(n4081), .Y(n2943) );
CMPR32X2TS U3282 ( .A(n4084), .B(n4085), .C(n4086), .CO(n2905), .S(n2904) );
NOR2X2TS U3283 ( .A(n2906), .B(n2905), .Y(n2951) );
NAND2X2TS U3284 ( .A(n2904), .B(n4087), .Y(n2945) );
OAI21X1TS U3285 ( .A0(n2951), .A1(n2945), .B0(n2949), .Y(n2914) );
CMPR32X2TS U3286 ( .A(n4090), .B(n4091), .C(n4092), .CO(n2907), .S(n2906) );
NAND2X1TS U3287 ( .A(n2913), .B(n2912), .Y(n2908) );
AOI21X1TS U3288 ( .A0(n2948), .A1(n2911), .B0(n2915), .Y(n2916) );
NOR2X1TS U3289 ( .A(n3641), .B(n4043), .Y(n2972) );
INVX2TS U3290 ( .A(n2917), .Y(n2918) );
XOR2X1TS U3291 ( .A(n2918), .B(n4077), .Y(n2955) );
NOR2X2TS U3292 ( .A(n2955), .B(n4028), .Y(n3689) );
OAI21X1TS U3293 ( .A0(n2918), .A1(n4094), .B0(n4095), .Y(n2922) );
INVX2TS U3294 ( .A(n2919), .Y(n2920) );
NAND2X1TS U3295 ( .A(n2920), .B(n4089), .Y(n2921) );
XNOR2X1TS U3296 ( .A(n2922), .B(n2921), .Y(n2956) );
NOR2X2TS U3297 ( .A(n2956), .B(n4052), .Y(n3553) );
NOR2X2TS U3298 ( .A(n3689), .B(n3553), .Y(n3534) );
INVX2TS U3299 ( .A(n2924), .Y(n2926) );
NAND2X1TS U3300 ( .A(n2926), .B(n4098), .Y(n2925) );
XNOR2X1TS U3301 ( .A(n2938), .B(n2925), .Y(n2957) );
NOR2X2TS U3302 ( .A(n2957), .B(n4064), .Y(n3536) );
AOI21X1TS U3303 ( .A0(n2938), .A1(n2926), .B0(n4076), .Y(n2927) );
NOR2X2TS U3304 ( .A(n2958), .B(n4012), .Y(n3540) );
NOR2X2TS U3305 ( .A(n3536), .B(n3540), .Y(n2960) );
AOI21X1TS U3306 ( .A0(n2938), .A1(n2932), .B0(n2933), .Y(n2930) );
INVX2TS U3307 ( .A(n2934), .Y(n2928) );
NAND2X1TS U3308 ( .A(n2928), .B(n4113), .Y(n2929) );
NOR2X2TS U3309 ( .A(n2931), .B(n4057), .Y(n3471) );
NOR2BX1TS U3310 ( .AN(n2932), .B(n2934), .Y(n2937) );
INVX2TS U3311 ( .A(n2933), .Y(n2935) );
OAI21X1TS U3312 ( .A0(n2935), .A1(n2934), .B0(n4113), .Y(n2936) );
AOI21X1TS U3313 ( .A0(n2938), .A1(n2937), .B0(n2936), .Y(n2942) );
NAND2X1TS U3314 ( .A(n2940), .B(n2939), .Y(n2941) );
NOR2X2TS U3315 ( .A(n2961), .B(n4056), .Y(n3476) );
NOR2X2TS U3316 ( .A(n3471), .B(n3476), .Y(n3483) );
INVX2TS U3317 ( .A(n2943), .Y(n2947) );
XNOR2X1TS U3318 ( .A(n2948), .B(n2944), .Y(n2962) );
NOR2X2TS U3319 ( .A(n2962), .B(n4055), .Y(n3484) );
INVX2TS U3320 ( .A(n2945), .Y(n2946) );
AOI21X1TS U3321 ( .A0(n2948), .A1(n2947), .B0(n2946), .Y(n2953) );
INVX2TS U3322 ( .A(n2949), .Y(n2950) );
OR2X2TS U3323 ( .A(n2951), .B(n2950), .Y(n2952) );
CLKXOR2X2TS U3324 ( .A(n2953), .B(n2952), .Y(n2963) );
NOR2X2TS U3325 ( .A(n2963), .B(n4054), .Y(n3491) );
NAND2X1TS U3326 ( .A(n2972), .B(n474), .Y(n2974) );
NAND2X1TS U3327 ( .A(n2955), .B(n4027), .Y(n3690) );
NAND2X1TS U3328 ( .A(n2956), .B(n4052), .Y(n3552) );
OAI21X1TS U3329 ( .A0(n3553), .A1(n3690), .B0(n3552), .Y(n3517) );
NAND2X1TS U3330 ( .A(n2957), .B(n4064), .Y(n3535) );
NAND2X1TS U3331 ( .A(n2958), .B(n4013), .Y(n3541) );
OAI21X1TS U3332 ( .A0(n3540), .A1(n3535), .B0(n3541), .Y(n2959) );
AOI21X1TS U3333 ( .A0(n3517), .A1(n2960), .B0(n2959), .Y(n3472) );
NAND2X1TS U3334 ( .A(n2961), .B(n4056), .Y(n3477) );
OAI21X1TS U3335 ( .A0(n3476), .A1(n3511), .B0(n3477), .Y(n3485) );
OAI21X1TS U3336 ( .A0(n3491), .A1(n3502), .B0(n3490), .Y(n2964) );
AOI21X1TS U3337 ( .A0(n3485), .A1(n2965), .B0(n2964), .Y(n2966) );
OAI21X4TS U3338 ( .A0(n3632), .A1(n3627), .B0(n3633), .Y(n3742) );
NOR3X1TS U3339 ( .A(n3704), .B(n3771), .C(n3718), .Y(n2977) );
AOI211X1TS U3340 ( .A0(n4129), .A1(n4131), .B0(n2978), .C0(n2977), .Y(n2979)
);
NOR2X2TS U3341 ( .A(n3127), .B(n505), .Y(n3174) );
NAND2X1TS U3342 ( .A(n2981), .B(n2990), .Y(n2993) );
INVX2TS U3343 ( .A(n2988), .Y(n2982) );
AOI21X1TS U3344 ( .A0(n2991), .A1(n2990), .B0(n2982), .Y(n2983) );
XNOR2X1TS U3345 ( .A(n2985), .B(n2984), .Y(n3176) );
NAND2X1TS U3346 ( .A(n2988), .B(n2987), .Y(n2989) );
AOI21X1TS U3347 ( .A0(n2991), .A1(n2990), .B0(n2989), .Y(n2992) );
OR2X2TS U3348 ( .A(FSM_selector_B[1]), .B(n4127), .Y(n3344) );
OAI2BB1X1TS U3349 ( .A0N(Op_MY[24]), .A1N(n4130), .B0(n3344), .Y(n2996) );
INVX2TS U3350 ( .A(n2997), .Y(n2999) );
NAND2X2TS U3351 ( .A(n2999), .B(n2998), .Y(n3001) );
INVX2TS U3352 ( .A(n3002), .Y(n3004) );
XOR2X4TS U3353 ( .A(n3006), .B(n3005), .Y(n3058) );
INVX2TS U3354 ( .A(n3009), .Y(n3010) );
AOI21X2TS U3355 ( .A0(n3011), .A1(n523), .B0(n3010), .Y(n3018) );
CMPR32X2TS U3356 ( .A(n3014), .B(n3013), .C(n3012), .CO(n3015), .S(n3110) );
INVX2TS U3357 ( .A(n3015), .Y(n3200) );
NOR2X2TS U3358 ( .A(n3017), .B(n3016), .Y(n3199) );
XNOR2X1TS U3359 ( .A(n3200), .B(n3199), .Y(n3195) );
XOR2X1TS U3360 ( .A(n3018), .B(n3195), .Y(n3039) );
XNOR2X4TS U3361 ( .A(n3021), .B(n3047), .Y(n3283) );
OR2X8TS U3362 ( .A(n3025), .B(n3026), .Y(n3035) );
OAI21X4TS U3363 ( .A0(n3029), .A1(n3028), .B0(n3027), .Y(n3036) );
OAI21X4TS U3364 ( .A0(n3315), .A1(n3302), .B0(n3316), .Y(add_x_19_n229) );
AOI21X4TS U3365 ( .A0(n3036), .A1(n3035), .B0(n3034), .Y(
DP_OP_156J7_125_3370_n99) );
ADDFHX2TS U3366 ( .A(n3039), .B(n3038), .CI(n3037), .CO(n3354), .S(n3026) );
INVX2TS U3367 ( .A(n3040), .Y(n3042) );
XOR2X4TS U3368 ( .A(n3044), .B(n3043), .Y(n3353) );
XOR2X4TS U3369 ( .A(n3051), .B(n3050), .Y(n3289) );
INVX4TS U3370 ( .A(n3289), .Y(n3348) );
INVX2TS U3371 ( .A(n3052), .Y(n3054) );
NAND2X4TS U3372 ( .A(n3054), .B(n3053), .Y(n3055) );
ADDFHX4TS U3373 ( .A(n3059), .B(n3058), .CI(n3057), .CO(n3060), .S(n3025) );
NAND2X4TS U3374 ( .A(n3061), .B(n3060), .Y(n3434) );
XNOR2X4TS U3375 ( .A(n3062), .B(n3435), .Y(Sgf_operation_EVEN1_S_B_14_) );
NAND2X6TS U3376 ( .A(Sgf_operation_EVEN1_S_B_14_), .B(
Sgf_operation_EVEN1_Q_left[2]), .Y(add_x_19_n220) );
OAI21X2TS U3377 ( .A0(n3067), .A1(n3066), .B0(n3065), .Y(n3371) );
INVX2TS U3378 ( .A(n3371), .Y(n3120) );
NOR2X2TS U3379 ( .A(n3068), .B(n3069), .Y(n3366) );
INVX2TS U3380 ( .A(n3366), .Y(n3070) );
INVX4TS U3381 ( .A(n3072), .Y(n3075) );
OAI21X4TS U3382 ( .A0(n3076), .A1(n3075), .B0(n3074), .Y(n3080) );
XNOR2X4TS U3383 ( .A(n3080), .B(n3079), .Y(n3244) );
NOR2X2TS U3384 ( .A(n3081), .B(n3130), .Y(n3084) );
OAI2BB1X4TS U3385 ( .A0N(n3082), .A1N(n3135), .B0(n3132), .Y(n3083) );
AOI21X4TS U3386 ( .A0(n424), .A1(n3084), .B0(n3083), .Y(n3119) );
ADDFHX4TS U3387 ( .A(n3087), .B(n3086), .CI(n3085), .CO(n3115), .S(n2368) );
INVX2TS U3388 ( .A(n3100), .Y(n3160) );
INVX2TS U3389 ( .A(n1348), .Y(n3101) );
OAI22X1TS U3390 ( .A0(n3102), .A1(n3149), .B0(n452), .B1(n3148), .Y(n3158)
);
OAI22X1TS U3391 ( .A0(n3109), .A1(n3197), .B0(n3157), .B1(n3196), .Y(n3154)
);
INVX2TS U3392 ( .A(n3110), .Y(n3151) );
INVX2TS U3393 ( .A(n3114), .Y(n3150) );
XNOR2X1TS U3394 ( .A(n3151), .B(n3150), .Y(n3153) );
INVX2TS U3395 ( .A(n3133), .Y(n3117) );
NAND2X2TS U3396 ( .A(n3116), .B(n3115), .Y(n3131) );
XOR2X4TS U3397 ( .A(n3119), .B(n3118), .Y(n3166) );
NOR2X2TS U3398 ( .A(n3122), .B(n3121), .Y(n3369) );
INVX2TS U3399 ( .A(n3369), .Y(n3123) );
NAND2X1TS U3400 ( .A(n3122), .B(n3121), .Y(n3367) );
NAND2X1TS U3401 ( .A(n3123), .B(n3367), .Y(n3124) );
XNOR2X1TS U3402 ( .A(n3125), .B(n3124), .Y(n3379) );
ADDFHX4TS U3403 ( .A(n3129), .B(n3128), .CI(n518), .CO(n3437), .S(n3167) );
AOI21X4TS U3404 ( .A0(n3135), .A1(n3136), .B0(n3134), .Y(n3141) );
INVX2TS U3405 ( .A(n1408), .Y(n3152) );
ADDFHX1TS U3406 ( .A(n3155), .B(n3154), .CI(n3153), .CO(n3206), .S(n3145) );
XNOR2X1TS U3407 ( .A(n3214), .B(n3156), .Y(n3198) );
OAI22X1TS U3408 ( .A0(n3157), .A1(n3197), .B0(n3198), .B1(n3196), .Y(n3194)
);
CMPR32X2TS U3409 ( .A(n3160), .B(n3159), .C(n3158), .CO(n3193), .S(n3147) );
INVX4TS U3410 ( .A(n3208), .Y(n3384) );
NAND2X4TS U3411 ( .A(n3165), .B(n3164), .Y(n3382) );
XOR2X4TS U3412 ( .A(n3385), .B(n436), .Y(n3436) );
ADDFHX4TS U3413 ( .A(n3168), .B(n3167), .CI(n3166), .CO(
DP_OP_156J7_125_3370_n202), .S(n3172) );
ADDFHX4TS U3414 ( .A(n3171), .B(n3170), .CI(n3169), .CO(n3173), .S(
DP_OP_156J7_125_3370_n207) );
NOR2X8TS U3415 ( .A(n3172), .B(n3173), .Y(DP_OP_156J7_125_3370_n69) );
NAND2X4TS U3416 ( .A(n3173), .B(n3172), .Y(DP_OP_156J7_125_3370_n70) );
NAND2BX4TS U3417 ( .AN(DP_OP_156J7_125_3370_n69), .B(
DP_OP_156J7_125_3370_n70), .Y(DP_OP_156J7_125_3370_n9) );
INVX2TS U3418 ( .A(n3176), .Y(n3177) );
XOR2X4TS U3419 ( .A(n3178), .B(n3177), .Y(Sgf_operation_EVEN1_Q_left[22]) );
XNOR2X1TS U3420 ( .A(n320), .B(n332), .Y(n3955) );
NAND2X1TS U3421 ( .A(DP_OP_154J7_123_2038_n778), .B(n312), .Y(n3953) );
NOR2X1TS U3422 ( .A(n325), .B(n313), .Y(n3958) );
NAND2X1TS U3423 ( .A(n325), .B(n313), .Y(n3949) );
NOR2X1TS U3424 ( .A(n3179), .B(n314), .Y(n3952) );
NAND2X1TS U3425 ( .A(n3179), .B(n314), .Y(n3947) );
NAND2X1TS U3426 ( .A(DP_OP_153J7_122_5442_n1459), .B(
DP_OP_153J7_122_5442_n1470), .Y(n3186) );
AOI21X1TS U3427 ( .A0(n3182), .A1(n3181), .B0(n3180), .Y(n3965) );
NOR2X1TS U3428 ( .A(n4137), .B(n329), .Y(n3959) );
NAND2X1TS U3429 ( .A(DP_OP_154J7_123_2038_n782), .B(n316), .Y(n3969) );
NAND2X1TS U3430 ( .A(n4137), .B(n329), .Y(n3988) );
OAI21X1TS U3431 ( .A0(n3959), .A1(n3969), .B0(n3988), .Y(n3976) );
AOI21X1TS U3432 ( .A0(n3976), .A1(n3974), .B0(n3964), .Y(n3977) );
BUFX3TS U3433 ( .A(n4151), .Y(n4150) );
CLKBUFX2TS U3434 ( .A(n4150), .Y(n3980) );
CLKBUFX2TS U3435 ( .A(DP_OP_155J7_124_2038_n801), .Y(n3920) );
NAND2X1TS U3436 ( .A(n356), .B(n3699), .Y(n3950) );
INVX2TS U3437 ( .A(n3189), .Y(n3184) );
NAND2X1TS U3438 ( .A(n357), .B(n345), .Y(n3188) );
NOR2X1TS U3439 ( .A(DP_OP_154J7_123_2038_n782), .B(n316), .Y(n3954) );
INVX2TS U3440 ( .A(n3954), .Y(n3975) );
CLKBUFX3TS U3441 ( .A(n4150), .Y(n3981) );
INVX2TS U3442 ( .A(n3185), .Y(n3187) );
NAND2X1TS U3443 ( .A(n3187), .B(n3186), .Y(n3966) );
NAND2X1TS U3444 ( .A(n3189), .B(n3188), .Y(n3971) );
ADDHXLTS U3445 ( .A(n319), .B(n331), .CO(n3961), .S(n3962) );
NAND2X1TS U3446 ( .A(n359), .B(n347), .Y(n3972) );
NAND2X1TS U3447 ( .A(n362), .B(n350), .Y(n3973) );
NAND2X1TS U3448 ( .A(n349), .B(n361), .Y(n3970) );
BUFX3TS U3449 ( .A(n489), .Y(n4151) );
BUFX3TS U3450 ( .A(n4151), .Y(n3979) );
CLKBUFX2TS U3451 ( .A(n4219), .Y(n3978) );
CMPR32X2TS U3452 ( .A(n3195), .B(n3194), .C(n3193), .CO(n3213), .S(n3205) );
OAI22X1TS U3453 ( .A0(n3198), .A1(n3197), .B0(n3196), .B1(n448), .Y(n3223)
);
INVX2TS U3454 ( .A(n3199), .Y(n3220) );
INVX2TS U3455 ( .A(n1521), .Y(n3201) );
CMPR32X2TS U3456 ( .A(n3204), .B(n3203), .C(n3202), .CO(n3221), .S(n3207) );
NAND2X2TS U3457 ( .A(n3210), .B(n3209), .Y(n3387) );
CMPR32X2TS U3458 ( .A(n3213), .B(n3212), .C(n3211), .CO(n3228), .S(n3209) );
INVX2TS U3459 ( .A(n3214), .Y(n3215) );
XNOR2X1TS U3460 ( .A(n3217), .B(n3216), .Y(n3226) );
CMPR32X2TS U3461 ( .A(n3220), .B(n3219), .C(n3218), .CO(n3225), .S(n3222) );
CMPR32X2TS U3462 ( .A(n3223), .B(n3222), .C(n3221), .CO(n3224), .S(n3212) );
INVX2TS U3463 ( .A(n3236), .Y(n3238) );
INVX2TS U3464 ( .A(n3245), .Y(n3247) );
INVX2TS U3465 ( .A(n3333), .Y(n3254) );
AOI21X1TS U3466 ( .A0(n3291), .A1(n519), .B0(n3257), .Y(n3260) );
NAND2X1TS U3467 ( .A(n524), .B(n3258), .Y(n3259) );
XNOR2X2TS U3468 ( .A(n3265), .B(n3264), .Y(n3313) );
CLKBUFX3TS U3469 ( .A(n445), .Y(n4228) );
CLKBUFX2TS U3470 ( .A(n455), .Y(n4153) );
BUFX3TS U3471 ( .A(n457), .Y(n4067) );
BUFX3TS U3472 ( .A(n455), .Y(n4068) );
CLKBUFX3TS U3473 ( .A(n456), .Y(n4065) );
CLKBUFX3TS U3474 ( .A(n4229), .Y(n4066) );
INVX2TS U3475 ( .A(add_x_19_n51), .Y(n3267) );
INVX2TS U3476 ( .A(add_x_19_n269), .Y(n3270) );
INVX2TS U3477 ( .A(n3271), .Y(n3273) );
CLKBUFX3TS U3478 ( .A(n457), .Y(n4069) );
INVX2TS U3479 ( .A(n3276), .Y(n3278) );
NAND2X1TS U3480 ( .A(n3278), .B(n3277), .Y(n3280) );
XNOR2X1TS U3481 ( .A(n3280), .B(n3279), .Y(n3284) );
CMPR32X2TS U3482 ( .A(n748), .B(n2119), .C(n3281), .CO(n3279), .S(n3886) );
OAI21X4TS U3483 ( .A0(n3460), .A1(n3887), .B0(n3461), .Y(n3465) );
NAND2X1TS U3484 ( .A(n3286), .B(n3285), .Y(n3287) );
XNOR2X1TS U3485 ( .A(n3288), .B(n3287), .Y(n3298) );
XNOR2X2TS U3486 ( .A(n3292), .B(n3291), .Y(n3299) );
INVX2TS U3487 ( .A(n3293), .Y(n3295) );
NAND2X2TS U3488 ( .A(n3295), .B(n3294), .Y(n3297) );
XOR2X4TS U3489 ( .A(n3297), .B(n3296), .Y(n3347) );
INVX2TS U3490 ( .A(add_x_19_n96), .Y(n3318) );
NAND2X2TS U3491 ( .A(add_x_19_n242), .B(add_x_19_n228), .Y(add_x_19_n222) );
NAND2X1TS U3492 ( .A(n3318), .B(n3255), .Y(n3319) );
INVX2TS U3493 ( .A(n3321), .Y(n3322) );
AOI21X2TS U3494 ( .A0(n3324), .A1(n3323), .B0(n3322), .Y(add_x_19_n252) );
INVX2TS U3495 ( .A(add_x_19_n228), .Y(add_x_19_n226) );
INVX2TS U3496 ( .A(n3547), .Y(n3326) );
INVX2TS U3497 ( .A(n3327), .Y(n3329) );
OAI21X1TS U3498 ( .A0(add_x_19_n282), .A1(n3333), .B0(n3332), .Y(
add_x_19_n279) );
INVX2TS U3499 ( .A(n3334), .Y(n3336) );
NOR3BX1TS U3500 ( .AN(Op_MY[30]), .B(FSM_selector_B[1]), .C(
FSM_selector_B[0]), .Y(n3338) );
XOR2X1TS U3501 ( .A(n4070), .B(n3338), .Y(DP_OP_36J7_126_4699_n15) );
OAI2BB1X1TS U3502 ( .A0N(Op_MY[29]), .A1N(n4130), .B0(n3344), .Y(n3339) );
XOR2X1TS U3503 ( .A(n4070), .B(n3339), .Y(DP_OP_36J7_126_4699_n16) );
OAI2BB1X1TS U3504 ( .A0N(Op_MY[28]), .A1N(n4130), .B0(n3344), .Y(n3340) );
XOR2X1TS U3505 ( .A(n4070), .B(n3340), .Y(DP_OP_36J7_126_4699_n17) );
OAI2BB1X1TS U3506 ( .A0N(Op_MY[27]), .A1N(n4130), .B0(n3344), .Y(n3341) );
XOR2X1TS U3507 ( .A(n4070), .B(n3341), .Y(DP_OP_36J7_126_4699_n18) );
OAI2BB1X1TS U3508 ( .A0N(Op_MY[26]), .A1N(n4130), .B0(n3344), .Y(n3342) );
XOR2X1TS U3509 ( .A(n4070), .B(n3342), .Y(DP_OP_36J7_126_4699_n19) );
OAI2BB1X1TS U3510 ( .A0N(Op_MY[25]), .A1N(n4130), .B0(n3344), .Y(n3343) );
XOR2X1TS U3511 ( .A(n4070), .B(n3343), .Y(DP_OP_36J7_126_4699_n20) );
XOR2X1TS U3512 ( .A(n3708), .B(n3346), .Y(DP_OP_36J7_126_4699_n22) );
INVX2TS U3513 ( .A(n319), .Y(n4071) );
INVX2TS U3514 ( .A(n354), .Y(n4073) );
NAND2X1TS U3515 ( .A(n352), .B(n346), .Y(n4072) );
ADDFHX2TS U3516 ( .A(n3349), .B(n3348), .CI(n432), .CO(n3359), .S(n3352) );
ADDFHX4TS U3517 ( .A(n3351), .B(add_x_19_n106), .CI(n3350), .CO(n3356), .S(
n3358) );
BUFX3TS U3518 ( .A(n457), .Y(n4116) );
CLKBUFX3TS U3519 ( .A(n457), .Y(n4115) );
CLKBUFX3TS U3520 ( .A(n4230), .Y(n4114) );
ADDFHX4TS U3521 ( .A(n3357), .B(n3356), .CI(n3355), .CO(n2315), .S(n3362) );
ADDFHX2TS U3522 ( .A(n3365), .B(n3364), .CI(n3363), .CO(n3169), .S(
DP_OP_156J7_125_3370_n213) );
OAI21X1TS U3523 ( .A0(n3369), .A1(n3368), .B0(n3367), .Y(n3370) );
AOI21X4TS U3524 ( .A0(n3372), .A1(n3371), .B0(n3370), .Y(n3447) );
NOR2X2TS U3525 ( .A(n3374), .B(n3373), .Y(n3446) );
INVX2TS U3526 ( .A(n3446), .Y(n3375) );
NAND2X1TS U3527 ( .A(n3375), .B(n3445), .Y(n3376) );
XOR2X1TS U3528 ( .A(n3447), .B(n3376), .Y(n3381) );
ADDFHX4TS U3529 ( .A(n3381), .B(add_x_19_n51), .CI(n3380), .CO(
DP_OP_156J7_125_3370_n196), .S(n3392) );
INVX2TS U3530 ( .A(n3382), .Y(n3383) );
AOI21X4TS U3531 ( .A0(n3385), .A1(n3384), .B0(n3383), .Y(n3390) );
INVX2TS U3532 ( .A(n3386), .Y(n3388) );
XNOR2X4TS U3533 ( .A(n3390), .B(n3389), .Y(n3391) );
NOR2X2TS U3534 ( .A(n3395), .B(n3394), .Y(n3448) );
NOR2X2TS U3535 ( .A(n3446), .B(n3448), .Y(n3415) );
INVX2TS U3536 ( .A(n3415), .Y(n3397) );
NAND2X1TS U3537 ( .A(n3395), .B(n3394), .Y(n3449) );
OAI21X2TS U3538 ( .A0(n3448), .A1(n3445), .B0(n3449), .Y(n3421) );
INVX2TS U3539 ( .A(n3421), .Y(n3396) );
INVX2TS U3540 ( .A(n3414), .Y(n3404) );
NAND2X1TS U3541 ( .A(n3404), .B(n3417), .Y(n3400) );
XNOR2X1TS U3542 ( .A(n3401), .B(n3400), .Y(n3413) );
NAND2X1TS U3543 ( .A(n3415), .B(n3404), .Y(n3406) );
INVX2TS U3544 ( .A(n3417), .Y(n3403) );
AOI21X1TS U3545 ( .A0(n3421), .A1(n3404), .B0(n3403), .Y(n3405) );
NOR2X2TS U3546 ( .A(n3408), .B(n3407), .Y(n3418) );
INVX2TS U3547 ( .A(n3418), .Y(n3409) );
NAND2X1TS U3548 ( .A(n3408), .B(n3407), .Y(n3416) );
NAND2X1TS U3549 ( .A(n3409), .B(n3416), .Y(n3410) );
ADDFHX4TS U3550 ( .A(n3413), .B(n430), .CI(n3412), .CO(n3457), .S(
DP_OP_156J7_125_3370_n189) );
NOR2X1TS U3551 ( .A(n3414), .B(n3418), .Y(n3420) );
NAND2X1TS U3552 ( .A(n3415), .B(n3420), .Y(n3423) );
AOI21X1TS U3553 ( .A0(n3421), .A1(n3420), .B0(n3419), .Y(n3422) );
NAND2X1TS U3554 ( .A(n3425), .B(n3424), .Y(n3426) );
NAND2X1TS U3555 ( .A(n3427), .B(n3426), .Y(n3428) );
NAND2X4TS U3556 ( .A(n3432), .B(n3431), .Y(DP_OP_156J7_125_3370_n3) );
INVX2TS U3557 ( .A(n3448), .Y(n3450) );
NAND2X1TS U3558 ( .A(n3450), .B(n3449), .Y(n3451) );
XNOR2X1TS U3559 ( .A(n3452), .B(n3451), .Y(n3456) );
CMPR32X2TS U3560 ( .A(n3456), .B(n3455), .C(n3454), .CO(
DP_OP_156J7_125_3370_n192), .S(DP_OP_156J7_125_3370_n193) );
ADDHX4TS U3561 ( .A(n3458), .B(n3457), .CO(n3430), .S(
DP_OP_156J7_125_3370_n185) );
INVX2TS U3562 ( .A(n332), .Y(n4125) );
INVX2TS U3563 ( .A(n359), .Y(n4123) );
INVX2TS U3564 ( .A(DP_OP_154J7_123_2038_n782), .Y(n4121) );
INVX2TS U3565 ( .A(DP_OP_154J7_123_2038_n778), .Y(n4120) );
INVX2TS U3566 ( .A(n358), .Y(n4124) );
INVX2TS U3567 ( .A(n364), .Y(n4122) );
INVX2TS U3568 ( .A(n360), .Y(n4118) );
INVX2TS U3569 ( .A(n366), .Y(n4119) );
INVX2TS U3570 ( .A(n3460), .Y(n3462) );
INVX2TS U3571 ( .A(n3465), .Y(n3526) );
INVX2TS U3572 ( .A(n3525), .Y(n3466) );
INVX2TS U3573 ( .A(n3470), .Y(n3508) );
INVX2TS U3574 ( .A(n3471), .Y(n3512) );
NAND2X1TS U3575 ( .A(n3508), .B(n3512), .Y(n3475) );
INVX2TS U3576 ( .A(n3472), .Y(n3509) );
INVX2TS U3577 ( .A(n3511), .Y(n3473) );
AOI21X1TS U3578 ( .A0(n3509), .A1(n3512), .B0(n3473), .Y(n3474) );
INVX2TS U3579 ( .A(n3476), .Y(n3478) );
NAND2X1TS U3580 ( .A(n3478), .B(n3477), .Y(n3479) );
XNOR2X1TS U3581 ( .A(n3480), .B(n3479), .Y(n3481) );
NAND2X1TS U3582 ( .A(n3481), .B(n408), .Y(n3482) );
OAI2BB1X1TS U3583 ( .A0N(n392), .A1N(n4194), .B0(n3482), .Y(n271) );
INVX2TS U3584 ( .A(n3483), .Y(n3497) );
INVX2TS U3585 ( .A(n3484), .Y(n3503) );
NOR2X1TS U3586 ( .A(n3497), .B(n3484), .Y(n3487) );
NAND2X1TS U3587 ( .A(n3487), .B(n3508), .Y(n3489) );
INVX2TS U3588 ( .A(n3485), .Y(n3498) );
AOI21X1TS U3589 ( .A0(n3509), .A1(n3487), .B0(n3486), .Y(n3488) );
OAI21X1TS U3590 ( .A0(n3693), .A1(n3489), .B0(n3488), .Y(n3493) );
XNOR2X1TS U3591 ( .A(n3493), .B(n3492), .Y(n3494) );
NAND2X1TS U3592 ( .A(n3494), .B(n408), .Y(n3495) );
NAND2X1TS U3593 ( .A(n3508), .B(n3483), .Y(n3501) );
INVX2TS U3594 ( .A(n3498), .Y(n3499) );
AOI21X1TS U3595 ( .A0(n3509), .A1(n3483), .B0(n3499), .Y(n3500) );
NAND2X1TS U3596 ( .A(n3503), .B(n3502), .Y(n3504) );
XNOR2X1TS U3597 ( .A(n3505), .B(n3504), .Y(n3506) );
NAND2X1TS U3598 ( .A(n3506), .B(n408), .Y(n3507) );
OAI2BB1X1TS U3599 ( .A0N(n393), .A1N(n4193), .B0(n3507), .Y(n272) );
INVX2TS U3600 ( .A(n3509), .Y(n3510) );
NAND2X1TS U3601 ( .A(n3512), .B(n3511), .Y(n3513) );
XNOR2X1TS U3602 ( .A(n3514), .B(n3513), .Y(n3515) );
NAND2X1TS U3603 ( .A(n3515), .B(n408), .Y(n3516) );
OAI2BB1X1TS U3604 ( .A0N(n393), .A1N(n4192), .B0(n3516), .Y(n270) );
INVX2TS U3605 ( .A(n3693), .Y(n3519) );
INVX2TS U3606 ( .A(n3517), .Y(n3537) );
INVX2TS U3607 ( .A(n3537), .Y(n3518) );
INVX2TS U3608 ( .A(n3536), .Y(n3533) );
NAND2X1TS U3609 ( .A(n3533), .B(n3535), .Y(n3520) );
XNOR2X1TS U3610 ( .A(n3521), .B(n3520), .Y(n3522) );
NAND2X1TS U3611 ( .A(n3522), .B(n407), .Y(n3523) );
OAI2BB1X1TS U3612 ( .A0N(n393), .A1N(n4188), .B0(n3523), .Y(n268) );
OAI21X1TS U3613 ( .A0(n3526), .A1(n3525), .B0(n3524), .Y(n3531) );
INVX2TS U3614 ( .A(n3527), .Y(n3529) );
NAND2X1TS U3615 ( .A(n3534), .B(n3533), .Y(n3539) );
OA21XLTS U3616 ( .A0(n3537), .A1(n3536), .B0(n3535), .Y(n3538) );
INVX2TS U3617 ( .A(n3540), .Y(n3542) );
NAND2X1TS U3618 ( .A(n3542), .B(n3541), .Y(n3543) );
XNOR2X1TS U3619 ( .A(n3544), .B(n3543), .Y(n3545) );
NAND2X1TS U3620 ( .A(n3545), .B(n407), .Y(n3546) );
OAI2BB1X1TS U3621 ( .A0N(n393), .A1N(n4189), .B0(n3546), .Y(n269) );
NAND2X2TS U3622 ( .A(n3548), .B(n3547), .Y(n3549) );
XNOR2X4TS U3623 ( .A(n3550), .B(n3549), .Y(n3551) );
XNOR2X1TS U3624 ( .A(n3555), .B(n3554), .Y(n3556) );
NAND2X1TS U3625 ( .A(n3556), .B(n411), .Y(n3557) );
OAI2BB1X1TS U3626 ( .A0N(n393), .A1N(n4190), .B0(n3557), .Y(n267) );
INVX2TS U3627 ( .A(n3718), .Y(n3710) );
INVX2TS U3628 ( .A(n3559), .Y(n3561) );
AOI22X1TS U3629 ( .A0(n460), .A1(Add_result[7]), .B0(
Sgf_normalized_result[6]), .B1(n3736), .Y(n3566) );
OAI2BB1X1TS U3630 ( .A0N(n492), .A1N(n268), .B0(n3566), .Y(n3567) );
AOI21X1TS U3631 ( .A0(n466), .A1(Add_result[6]), .B0(n3567), .Y(n3568) );
OAI2BB1X1TS U3632 ( .A0N(n3562), .A1N(n267), .B0(n3568), .Y(n208) );
AOI22X1TS U3633 ( .A0(n3569), .A1(Add_result[8]), .B0(
Sgf_normalized_result[7]), .B1(n3736), .Y(n3570) );
OAI2BB1X1TS U3634 ( .A0N(n490), .A1N(n269), .B0(n3570), .Y(n3571) );
AOI21X1TS U3635 ( .A0(n465), .A1(Add_result[7]), .B0(n3571), .Y(n3572) );
OAI2BB1X1TS U3636 ( .A0N(n3562), .A1N(n268), .B0(n3572), .Y(n209) );
AOI22X1TS U3637 ( .A0(n459), .A1(Add_result[9]), .B0(
Sgf_normalized_result[8]), .B1(n3817), .Y(n3573) );
OAI2BB1X1TS U3638 ( .A0N(n490), .A1N(n270), .B0(n3573), .Y(n3574) );
AOI21X1TS U3639 ( .A0(n466), .A1(Add_result[8]), .B0(n3574), .Y(n3575) );
OAI2BB1X1TS U3640 ( .A0N(n3562), .A1N(n269), .B0(n3575), .Y(n210) );
AOI22X1TS U3641 ( .A0(n460), .A1(Add_result[11]), .B0(
Sgf_normalized_result[10]), .B1(n3817), .Y(n3576) );
OAI2BB1X1TS U3642 ( .A0N(n491), .A1N(n272), .B0(n3576), .Y(n3577) );
AOI21X1TS U3643 ( .A0(n465), .A1(Add_result[10]), .B0(n3577), .Y(n3578) );
OAI2BB1X1TS U3644 ( .A0N(n3562), .A1N(n271), .B0(n3578), .Y(n212) );
AOI22X1TS U3645 ( .A0(n459), .A1(Add_result[12]), .B0(
Sgf_normalized_result[11]), .B1(n3788), .Y(n3579) );
OAI2BB1X1TS U3646 ( .A0N(n492), .A1N(n273), .B0(n3579), .Y(n3580) );
AOI21X1TS U3647 ( .A0(n466), .A1(Add_result[11]), .B0(n3580), .Y(n3581) );
OAI2BB1X1TS U3648 ( .A0N(n3562), .A1N(n272), .B0(n3581), .Y(n213) );
AOI22X1TS U3649 ( .A0(n3569), .A1(Add_result[10]), .B0(
Sgf_normalized_result[9]), .B1(n3736), .Y(n3582) );
OAI2BB1X1TS U3650 ( .A0N(n490), .A1N(n271), .B0(n3582), .Y(n3583) );
AOI21X1TS U3651 ( .A0(n464), .A1(Add_result[9]), .B0(n3583), .Y(n3584) );
OAI2BB1X1TS U3652 ( .A0N(n3562), .A1N(n270), .B0(n3584), .Y(n211) );
INVX2TS U3653 ( .A(n474), .Y(n3585) );
INVX2TS U3654 ( .A(n3586), .Y(n3629) );
NAND2X1TS U3655 ( .A(n3629), .B(n3627), .Y(n3587) );
XNOR2X1TS U3656 ( .A(n3588), .B(n3587), .Y(n3589) );
AOI22X1TS U3657 ( .A0(n459), .A1(Add_result[13]), .B0(
Sgf_normalized_result[12]), .B1(n3788), .Y(n3591) );
OAI2BB1X1TS U3658 ( .A0N(n491), .A1N(n274), .B0(n3591), .Y(n3592) );
AOI21X1TS U3659 ( .A0(n464), .A1(Add_result[12]), .B0(n3592), .Y(n3593) );
OAI2BB1X1TS U3660 ( .A0N(n471), .A1N(n273), .B0(n3593), .Y(n214) );
INVX2TS U3661 ( .A(n3641), .Y(n3595) );
NAND2X1TS U3662 ( .A(n2954), .B(n3595), .Y(n3597) );
INVX2TS U3663 ( .A(n3642), .Y(n3594) );
AOI21X1TS U3664 ( .A0(n475), .A1(n3595), .B0(n3594), .Y(n3596) );
XNOR2X1TS U3665 ( .A(n3598), .B(n406), .Y(n3599) );
NOR2X1TS U3666 ( .A(n3641), .B(n406), .Y(n3601) );
NAND2X1TS U3667 ( .A(n3601), .B(n474), .Y(n3603) );
NOR2X1TS U3668 ( .A(n3642), .B(n406), .Y(n3600) );
AOI21X1TS U3669 ( .A0(n476), .A1(n3601), .B0(n3600), .Y(n3602) );
OAI21X1TS U3670 ( .A0(n3781), .A1(n3603), .B0(n3602), .Y(n3604) );
XNOR2X1TS U3671 ( .A(n3604), .B(n3998), .Y(n3605) );
OAI2BB1X2TS U3672 ( .A0N(n411), .A1N(n3605), .B0(n4204), .Y(n3768) );
AOI22X1TS U3673 ( .A0(n460), .A1(Add_result[20]), .B0(
Sgf_normalized_result[19]), .B1(n3788), .Y(n3606) );
OAI2BB1X1TS U3674 ( .A0N(n3768), .A1N(n491), .B0(n3606), .Y(n3607) );
AOI21X1TS U3675 ( .A0(n465), .A1(Add_result[19]), .B0(n3607), .Y(n3608) );
OAI2BB1X1TS U3676 ( .A0N(n3773), .A1N(n470), .B0(n3608), .Y(n221) );
NOR2X1TS U3677 ( .A(n3641), .B(n4046), .Y(n3610) );
NAND2X1TS U3678 ( .A(n3610), .B(n2954), .Y(n3612) );
AOI21X1TS U3679 ( .A0(n476), .A1(n3610), .B0(n3609), .Y(n3611) );
OAI21X1TS U3680 ( .A0(n3781), .A1(n3612), .B0(n3611), .Y(n3613) );
XNOR2X1TS U3681 ( .A(n3613), .B(n3996), .Y(n3614) );
OAI2BB1X2TS U3682 ( .A0N(n411), .A1N(n3614), .B0(n4206), .Y(n3770) );
AOI22X1TS U3683 ( .A0(n460), .A1(Add_result[21]), .B0(
Sgf_normalized_result[20]), .B1(n3817), .Y(n3615) );
OAI2BB1X1TS U3684 ( .A0N(n3770), .A1N(n490), .B0(n3615), .Y(n3616) );
AOI21X1TS U3685 ( .A0(n466), .A1(Add_result[20]), .B0(n3616), .Y(n3617) );
OAI2BB1X1TS U3686 ( .A0N(n3768), .A1N(n471), .B0(n3617), .Y(n222) );
NOR2X1TS U3687 ( .A(n3641), .B(n4045), .Y(n3619) );
NAND2X1TS U3688 ( .A(n3619), .B(n474), .Y(n3621) );
NOR2X1TS U3689 ( .A(n3642), .B(n4045), .Y(n3618) );
AOI21X1TS U3690 ( .A0(n476), .A1(n3619), .B0(n3618), .Y(n3620) );
OAI21X1TS U3691 ( .A0(n3781), .A1(n3621), .B0(n3620), .Y(n3622) );
XNOR2X1TS U3692 ( .A(n3622), .B(n3997), .Y(n3623) );
OAI2BB1X2TS U3693 ( .A0N(n411), .A1N(n3623), .B0(n4205), .Y(n3769) );
AOI22X1TS U3694 ( .A0(n459), .A1(Add_result[22]), .B0(
Sgf_normalized_result[21]), .B1(n3817), .Y(n3624) );
OAI2BB1X1TS U3695 ( .A0N(n3769), .A1N(n492), .B0(n3624), .Y(n3625) );
AOI21X1TS U3696 ( .A0(n465), .A1(Add_result[21]), .B0(n3625), .Y(n3626) );
OAI2BB1X1TS U3697 ( .A0N(n3770), .A1N(n470), .B0(n3626), .Y(n223) );
NAND2X1TS U3698 ( .A(n2954), .B(n3629), .Y(n3631) );
INVX2TS U3699 ( .A(n3627), .Y(n3628) );
AOI21X1TS U3700 ( .A0(n475), .A1(n3629), .B0(n3628), .Y(n3630) );
OAI21X1TS U3701 ( .A0(n3693), .A1(n3631), .B0(n3630), .Y(n3636) );
NAND2X1TS U3702 ( .A(n3634), .B(n3633), .Y(n3635) );
XNOR2X1TS U3703 ( .A(n3636), .B(n3635), .Y(n3637) );
AOI22X1TS U3704 ( .A0(n3569), .A1(Add_result[14]), .B0(
Sgf_normalized_result[13]), .B1(n3788), .Y(n3638) );
AOI21X1TS U3705 ( .A0(n464), .A1(Add_result[13]), .B0(n3639), .Y(n3640) );
NOR2X1TS U3706 ( .A(n3641), .B(n4044), .Y(n3644) );
NAND2X1TS U3707 ( .A(n3644), .B(n474), .Y(n3646) );
AOI21X1TS U3708 ( .A0(n475), .A1(n3644), .B0(n3643), .Y(n3645) );
OAI21X1TS U3709 ( .A0(n3781), .A1(n3646), .B0(n3645), .Y(n3647) );
XOR2X1TS U3710 ( .A(n3647), .B(n4003), .Y(n3648) );
OAI2BB1X2TS U3711 ( .A0N(n411), .A1N(n3648), .B0(n4197), .Y(n3813) );
AOI22X1TS U3712 ( .A0(n460), .A1(Add_result[23]), .B0(
Sgf_normalized_result[22]), .B1(n3817), .Y(n3649) );
OAI2BB1X1TS U3713 ( .A0N(n3813), .A1N(n491), .B0(n3649), .Y(n3650) );
AOI21X1TS U3714 ( .A0(n466), .A1(Add_result[22]), .B0(n3650), .Y(n3651) );
OAI2BB1X1TS U3715 ( .A0N(n3769), .A1N(n471), .B0(n3651), .Y(n224) );
NAND2X1TS U3716 ( .A(n3653), .B(n4060), .Y(n3654) );
XNOR2X1TS U3717 ( .A(n3655), .B(n3654), .Y(n3656) );
INVX2TS U3718 ( .A(n3657), .Y(n3720) );
NOR2X1TS U3719 ( .A(n4039), .B(n3658), .Y(n3660) );
NAND2X1TS U3720 ( .A(n3660), .B(n4034), .Y(n3662) );
AOI21X1TS U3721 ( .A0(n4063), .A1(n3660), .B0(n3659), .Y(n3661) );
NAND2X1TS U3722 ( .A(n3665), .B(n3664), .Y(n3666) );
XNOR2X1TS U3723 ( .A(n3667), .B(n3666), .Y(n3668) );
AOI22X1TS U3724 ( .A0(n3569), .A1(Add_result[4]), .B0(
Sgf_normalized_result[3]), .B1(n3736), .Y(n3669) );
OAI2BB1X1TS U3725 ( .A0N(n491), .A1N(n265), .B0(n3669), .Y(n3670) );
AOI21X1TS U3726 ( .A0(n466), .A1(Add_result[3]), .B0(n3670), .Y(n3671) );
OAI2BB1X1TS U3727 ( .A0N(n471), .A1N(n264), .B0(n3671), .Y(n205) );
XNOR2X1TS U3728 ( .A(n3672), .B(n4010), .Y(n3673) );
XNOR2X1TS U3729 ( .A(n3674), .B(n4008), .Y(n3675) );
AOI22X1TS U3730 ( .A0(n460), .A1(Add_result[2]), .B0(
Sgf_normalized_result[1]), .B1(n3817), .Y(n3676) );
OAI2BB1X1TS U3731 ( .A0N(n492), .A1N(n263), .B0(n3676), .Y(n3677) );
AOI21X1TS U3732 ( .A0(n465), .A1(Add_result[1]), .B0(n3677), .Y(n3678) );
OAI2BB1X1TS U3733 ( .A0N(n470), .A1N(n262), .B0(n3678), .Y(n203) );
XNOR2X1TS U3734 ( .A(n3679), .B(n4009), .Y(n3680) );
AOI22X1TS U3735 ( .A0(n459), .A1(Add_result[1]), .B0(
Sgf_normalized_result[0]), .B1(n3788), .Y(n3681) );
OAI2BB1X1TS U3736 ( .A0N(n491), .A1N(n262), .B0(n3681), .Y(n3682) );
AOI21X1TS U3737 ( .A0(n464), .A1(Add_result[0]), .B0(n3682), .Y(n3683) );
OAI2BB1X1TS U3738 ( .A0N(n261), .A1N(n471), .B0(n3683), .Y(n202) );
AOI22X1TS U3739 ( .A0(n459), .A1(Add_result[3]), .B0(
Sgf_normalized_result[2]), .B1(n3817), .Y(n3684) );
OAI2BB1X1TS U3740 ( .A0N(n490), .A1N(n264), .B0(n3684), .Y(n3685) );
AOI21X1TS U3741 ( .A0(n464), .A1(Add_result[2]), .B0(n3685), .Y(n3686) );
OAI2BB1X1TS U3742 ( .A0N(n3562), .A1N(n263), .B0(n3686), .Y(n204) );
XNOR2X1TS U3743 ( .A(n3687), .B(n4011), .Y(n3688) );
INVX2TS U3744 ( .A(n3689), .Y(n3691) );
NAND2X1TS U3745 ( .A(n3691), .B(n3690), .Y(n3692) );
OAI2BB1X1TS U3746 ( .A0N(n411), .A1N(n3694), .B0(n4191), .Y(n3740) );
AOI22X1TS U3747 ( .A0(n460), .A1(Add_result[5]), .B0(
Sgf_normalized_result[4]), .B1(n3736), .Y(n3695) );
OAI2BB1X1TS U3748 ( .A0N(n492), .A1N(n3740), .B0(n3695), .Y(n3696) );
AOI21X1TS U3749 ( .A0(n466), .A1(Add_result[4]), .B0(n3696), .Y(n3697) );
OAI2BB1X1TS U3750 ( .A0N(n471), .A1N(n265), .B0(n3697), .Y(n206) );
BUFX3TS U3751 ( .A(n3698), .Y(n4225) );
BUFX3TS U3752 ( .A(n3698), .Y(n4221) );
BUFX3TS U3753 ( .A(n4219), .Y(n4222) );
BUFX3TS U3754 ( .A(n3698), .Y(n4220) );
CLKBUFX2TS U3755 ( .A(n445), .Y(n4230) );
CLKBUFX2TS U3756 ( .A(n462), .Y(n4147) );
BUFX3TS U3757 ( .A(n463), .Y(n4148) );
BUFX3TS U3758 ( .A(n4224), .Y(n4217) );
BUFX3TS U3759 ( .A(n4223), .Y(n4218) );
INVX2TS U3760 ( .A(n3699), .Y(n4186) );
AND4X1TS U3761 ( .A(n3702), .B(n3701), .C(n4186), .D(n3700), .Y(n4156) );
BUFX3TS U3762 ( .A(n489), .Y(n4224) );
BUFX3TS U3763 ( .A(n489), .Y(n4223) );
BUFX3TS U3764 ( .A(n489), .Y(n4219) );
NAND2X1TS U3765 ( .A(n3838), .B(Add_result[0]), .Y(n3705) );
XOR2X1TS U3766 ( .A(Op_MX[31]), .B(Op_MY[31]), .Y(n3732) );
NOR2XLTS U3767 ( .A(n3732), .B(underflow_flag), .Y(n3707) );
OAI32X1TS U3768 ( .A0(n3937), .A1(n3707), .A2(overflow_flag), .B0(n3939),
.B1(n4146), .Y(n168) );
NAND2X2TS U3769 ( .A(n3712), .B(n3711), .Y(n3931) );
OAI211X1TS U3770 ( .A0(n3713), .A1(n4127), .B0(n3838), .C0(n3931), .Y(n236)
);
INVX2TS U3771 ( .A(n3838), .Y(n3870) );
INVX2TS U3772 ( .A(n3713), .Y(n3714) );
OAI31X1TS U3773 ( .A0(n3861), .A1(n3715), .A2(n4130), .B0(n3714), .Y(n235)
);
AOI32X1TS U3774 ( .A0(FS_Module_state_reg[1]), .A1(n4131), .A2(
FS_Module_state_reg[0]), .B0(FS_Module_state_reg[2]), .B1(n3716), .Y(
n3717) );
XOR2X1TS U3775 ( .A(n3720), .B(n4006), .Y(n3719) );
XNOR2X1TS U3776 ( .A(n3721), .B(n4007), .Y(n3722) );
XOR2X1TS U3777 ( .A(n4031), .B(n4032), .Y(n3723) );
XNOR2X1TS U3778 ( .A(n4040), .B(n4041), .Y(n3724) );
NOR4X1TS U3779 ( .A(n255), .B(n468), .C(P_Sgf[15]), .D(P_Sgf[14]), .Y(n3731)
);
NOR4X1TS U3780 ( .A(n258), .B(n259), .C(n256), .D(n257), .Y(n3730) );
NOR4X1TS U3781 ( .A(P_Sgf[2]), .B(P_Sgf[3]), .C(P_Sgf[4]), .D(P_Sgf[5]), .Y(
n3728) );
AND4X1TS U3782 ( .A(n3728), .B(n3727), .C(n3726), .D(n3725), .Y(n3729) );
MXI2X1TS U3783 ( .A(round_mode[0]), .B(round_mode[1]), .S0(n3732), .Y(n3733)
);
OAI211X1TS U3784 ( .A0(round_mode[0]), .A1(round_mode[1]), .B0(n3734), .C0(
n3733), .Y(n3797) );
NAND2X1TS U3785 ( .A(n3892), .B(n3740), .Y(n4241) );
AOI22X1TS U3786 ( .A0(n3569), .A1(Add_result[6]), .B0(
Sgf_normalized_result[5]), .B1(n3736), .Y(n3737) );
OAI2BB1X1TS U3787 ( .A0N(n490), .A1N(n267), .B0(n3737), .Y(n3738) );
AOI21X1TS U3788 ( .A0(n465), .A1(Add_result[5]), .B0(n3738), .Y(n3739) );
OAI2BB1X1TS U3789 ( .A0N(n470), .A1N(n3740), .B0(n3739), .Y(n207) );
NAND2X1TS U3790 ( .A(n4213), .B(n3773), .Y(n4235) );
INVX2TS U3791 ( .A(n3741), .Y(n3777) );
NOR2X1TS U3792 ( .A(n3777), .B(n4049), .Y(n3744) );
NAND2X1TS U3793 ( .A(n2954), .B(n3744), .Y(n3746) );
INVX2TS U3794 ( .A(n3742), .Y(n3778) );
AOI21X1TS U3795 ( .A0(n476), .A1(n3744), .B0(n3743), .Y(n3745) );
OAI21X1TS U3796 ( .A0(n3781), .A1(n3746), .B0(n3745), .Y(n3747) );
XNOR2X1TS U3797 ( .A(n3747), .B(n3999), .Y(n3748) );
OAI2BB1X2TS U3798 ( .A0N(n407), .A1N(n3748), .B0(n4202), .Y(n3765) );
NAND2X1TS U3799 ( .A(n3892), .B(n3765), .Y(n4237) );
NOR2X1TS U3800 ( .A(n4048), .B(n3777), .Y(n3750) );
NAND2X1TS U3801 ( .A(n474), .B(n3750), .Y(n3752) );
XOR2X1TS U3802 ( .A(n3753), .B(n4002), .Y(n3754) );
AOI22X1TS U3803 ( .A0(n3569), .A1(Add_result[18]), .B0(
Sgf_normalized_result[17]), .B1(n3788), .Y(n3755) );
OAI2BB1X1TS U3804 ( .A0N(n3776), .A1N(n491), .B0(n3755), .Y(n3756) );
AOI21X1TS U3805 ( .A0(n465), .A1(Add_result[17]), .B0(n3756), .Y(n3757) );
OAI2BB1X1TS U3806 ( .A0N(n3765), .A1N(n470), .B0(n3757), .Y(n219) );
NOR2X1TS U3807 ( .A(n3777), .B(n4050), .Y(n3759) );
NAND2X1TS U3808 ( .A(n474), .B(n3759), .Y(n3761) );
AOI21X1TS U3809 ( .A0(n476), .A1(n3759), .B0(n3758), .Y(n3760) );
OAI21X1TS U3810 ( .A0(n3781), .A1(n3761), .B0(n3760), .Y(n3762) );
XNOR2X1TS U3811 ( .A(n3762), .B(n4000), .Y(n3763) );
NAND2X1TS U3812 ( .A(n3892), .B(n3785), .Y(n4238) );
AOI22X1TS U3813 ( .A0(n460), .A1(Add_result[17]), .B0(
Sgf_normalized_result[16]), .B1(n3788), .Y(n3764) );
OAI2BB1X1TS U3814 ( .A0N(n3765), .A1N(n492), .B0(n3764), .Y(n3766) );
AOI21X1TS U3815 ( .A0(n466), .A1(Add_result[16]), .B0(n3766), .Y(n3767) );
OAI2BB1X1TS U3816 ( .A0N(n3785), .A1N(n471), .B0(n3767), .Y(n218) );
NAND2X1TS U3817 ( .A(n4213), .B(n3768), .Y(n4234) );
NAND2X1TS U3818 ( .A(n3892), .B(n3769), .Y(n4232) );
NAND2X1TS U3819 ( .A(n4213), .B(n3770), .Y(n4233) );
NAND2X1TS U3820 ( .A(n3892), .B(n3771), .Y(n4242) );
NAND2X1TS U3821 ( .A(n3892), .B(n3813), .Y(n4231) );
AOI22X1TS U3822 ( .A0(n459), .A1(Add_result[19]), .B0(
Sgf_normalized_result[18]), .B1(n3788), .Y(n3772) );
OAI2BB1X1TS U3823 ( .A0N(n3773), .A1N(n490), .B0(n3772), .Y(n3774) );
AOI21X1TS U3824 ( .A0(n464), .A1(Add_result[18]), .B0(n3774), .Y(n3775) );
OAI2BB1X1TS U3825 ( .A0N(n3776), .A1N(n470), .B0(n3775), .Y(n220) );
NAND2X1TS U3826 ( .A(n3892), .B(n3776), .Y(n4236) );
NAND2X1TS U3827 ( .A(n2954), .B(n3741), .Y(n3780) );
AOI21X1TS U3828 ( .A0(n476), .A1(n3741), .B0(n3742), .Y(n3779) );
OAI21X1TS U3829 ( .A0(n3781), .A1(n3780), .B0(n3779), .Y(n3782) );
XOR2X1TS U3830 ( .A(n3782), .B(n4001), .Y(n3783) );
OAI2BB1X2TS U3831 ( .A0N(n411), .A1N(n3783), .B0(n4199), .Y(n3791) );
AOI22X1TS U3832 ( .A0(n459), .A1(Add_result[16]), .B0(
Sgf_normalized_result[15]), .B1(n3788), .Y(n3784) );
OAI2BB1X1TS U3833 ( .A0N(n3785), .A1N(n492), .B0(n3784), .Y(n3786) );
AOI21X1TS U3834 ( .A0(n465), .A1(Add_result[15]), .B0(n3786), .Y(n3787) );
OAI2BB1X1TS U3835 ( .A0N(n3791), .A1N(n470), .B0(n3787), .Y(n217) );
NAND2X1TS U3836 ( .A(n3892), .B(n3791), .Y(n4239) );
AOI22X1TS U3837 ( .A0(n459), .A1(Add_result[15]), .B0(
Sgf_normalized_result[14]), .B1(n3788), .Y(n3789) );
OAI2BB1X1TS U3838 ( .A0N(n3791), .A1N(n491), .B0(n3789), .Y(n3792) );
AOI21X1TS U3839 ( .A0(n464), .A1(Add_result[14]), .B0(n3792), .Y(n3793) );
OAI2BB1X1TS U3840 ( .A0N(n3794), .A1N(n471), .B0(n3793), .Y(n216) );
NAND2X1TS U3841 ( .A(n3892), .B(n3794), .Y(n4240) );
AOI22X1TS U3842 ( .A0(n3798), .A1(n3797), .B0(n3796), .B1(n3795), .Y(n3799)
);
OAI2BB1X1TS U3843 ( .A0N(n3800), .A1N(n4129), .B0(n3799), .Y(n378) );
NAND2X1TS U3844 ( .A(Sgf_normalized_result[6]), .B(Sgf_normalized_result[7]),
.Y(n3808) );
NAND2X1TS U3845 ( .A(Sgf_normalized_result[5]), .B(Sgf_normalized_result[4]),
.Y(n3853) );
NOR2X1TS U3846 ( .A(n4128), .B(n4133), .Y(n3845) );
NAND2X1TS U3847 ( .A(n3845), .B(Sgf_normalized_result[10]), .Y(n3811) );
MXI2X1TS U3848 ( .A(n3813), .B(Add_result[23]), .S0(FSM_selector_C), .Y(
n3814) );
AHHCINX2TS U3849 ( .A(Sgf_normalized_result[22]), .CIN(n3818), .S(n3819),
.CO(n3869) );
AHHCONX2TS U3850 ( .A(Sgf_normalized_result[21]), .CI(n3820), .CON(n3818),
.S(n3821) );
AHHCINX2TS U3851 ( .A(Sgf_normalized_result[20]), .CIN(n3822), .S(n3823),
.CO(n3820) );
AHHCONX2TS U3852 ( .A(Sgf_normalized_result[19]), .CI(n3824), .CON(n3822),
.S(n3825) );
AHHCINX2TS U3853 ( .A(Sgf_normalized_result[18]), .CIN(n3826), .S(n3827),
.CO(n3824) );
AHHCONX2TS U3854 ( .A(Sgf_normalized_result[17]), .CI(n3828), .CON(n3826),
.S(n3829) );
AHHCINX2TS U3855 ( .A(Sgf_normalized_result[16]), .CIN(n3830), .S(n3831),
.CO(n3828) );
AHHCONX2TS U3856 ( .A(Sgf_normalized_result[15]), .CI(n3832), .CON(n3830),
.S(n3833) );
AHHCINX2TS U3857 ( .A(Sgf_normalized_result[14]), .CIN(n3834), .S(n3836),
.CO(n3832) );
AHHCONX2TS U3858 ( .A(Sgf_normalized_result[13]), .CI(n3837), .CON(n3834),
.S(n3839) );
AHHCINX2TS U3859 ( .A(Sgf_normalized_result[12]), .CIN(n3840), .S(n3841),
.CO(n3837) );
AHHCONX2TS U3860 ( .A(Sgf_normalized_result[11]), .CI(n3842), .CON(n3840),
.S(n3843) );
NAND2X1TS U3861 ( .A(n3850), .B(n3845), .Y(n3846) );
XOR2X1TS U3862 ( .A(n3846), .B(n4142), .Y(n3847) );
NAND2X1TS U3863 ( .A(n3850), .B(Sgf_normalized_result[8]), .Y(n3848) );
XOR2X1TS U3864 ( .A(n3848), .B(n4133), .Y(n3849) );
XNOR2X1TS U3865 ( .A(n3850), .B(n4128), .Y(n3851) );
OAI21X1TS U3866 ( .A0(n3860), .A1(n4134), .B0(n3853), .Y(n3856) );
NAND2X1TS U3867 ( .A(n3856), .B(Sgf_normalized_result[6]), .Y(n3854) );
XOR2X1TS U3868 ( .A(n3854), .B(n4143), .Y(n3855) );
XNOR2X1TS U3869 ( .A(n3856), .B(n4140), .Y(n3857) );
NAND2X1TS U3870 ( .A(n3860), .B(n4139), .Y(n3858) );
XNOR2X1TS U3871 ( .A(n3858), .B(n4134), .Y(n3859) );
XOR2X1TS U3872 ( .A(n3860), .B(Sgf_normalized_result[4]), .Y(n3862) );
XOR2X1TS U3873 ( .A(n3864), .B(n4132), .Y(n3865) );
XOR2X1TS U3874 ( .A(n3866), .B(Sgf_normalized_result[2]), .Y(n3867) );
XNOR2X1TS U3875 ( .A(Sgf_normalized_result[0]), .B(Sgf_normalized_result[1]),
.Y(n3868) );
ADDHXLTS U3876 ( .A(Sgf_normalized_result[23]), .B(n3869), .CO(n3871), .S(
n3812) );
NAND2X1TS U3877 ( .A(n3931), .B(n4141), .Y(n376) );
NOR2BX1TS U3878 ( .AN(exp_oper_result[8]), .B(n4141), .Y(S_Oper_A_exp[8]) );
INVX2TS U3879 ( .A(n4070), .Y(n3894) );
AND4X1TS U3880 ( .A(Exp_module_Data_S[3]), .B(Exp_module_Data_S[2]), .C(
Exp_module_Data_S[1]), .D(Exp_module_Data_S[0]), .Y(n3896) );
AND4X1TS U3881 ( .A(Exp_module_Data_S[6]), .B(Exp_module_Data_S[5]), .C(
Exp_module_Data_S[4]), .D(n3896), .Y(n3897) );
AO21X1TS U3882 ( .A0(underflow_flag), .A1(n3931), .B0(n3898), .Y(n201) );
AO22X1TS U3883 ( .A0(n3933), .A1(Sgf_normalized_result[0]), .B0(
final_result_ieee[0]), .B1(n3937), .Y(n200) );
AO22X1TS U3884 ( .A0(n3933), .A1(Sgf_normalized_result[1]), .B0(
final_result_ieee[1]), .B1(n3937), .Y(n199) );
AO22X1TS U3885 ( .A0(n3933), .A1(Sgf_normalized_result[2]), .B0(
final_result_ieee[2]), .B1(n3937), .Y(n198) );
NOR4X1TS U3886 ( .A(Op_MY[27]), .B(Op_MY[26]), .C(Op_MY[25]), .D(Op_MY[24]),
.Y(n3907) );
NOR4BBX1TS U3887 ( .AN(n4182), .BN(n4183), .C(n3901), .D(n4211), .Y(n3906)
);
NAND4BXLTS U3888 ( .AN(DP_OP_154J7_123_2038_n357), .B(n4163), .C(n4178), .D(
n4179), .Y(n3902) );
INVX2TS U3889 ( .A(n3902), .Y(n3905) );
NOR4X1TS U3890 ( .A(n3903), .B(Op_MY[30]), .C(Op_MY[29]), .D(Op_MY[28]), .Y(
n3904) );
NAND4XLTS U3891 ( .A(n3907), .B(n3906), .C(n3905), .D(n3904), .Y(n3929) );
NAND4BBX1TS U3892 ( .AN(Op_MY[11]), .BN(DP_OP_155J7_124_2038_n793), .C(n4212), .D(n4162), .Y(n3908) );
INVX2TS U3893 ( .A(n3908), .Y(n3913) );
NOR4X1TS U3894 ( .A(Op_MY[6]), .B(Op_MY[4]), .C(DP_OP_155J7_124_2038_n791),
.D(Op_MY[2]), .Y(n3912) );
INVX2TS U3895 ( .A(n3910), .Y(n3911) );
NAND4XLTS U3896 ( .A(n3913), .B(n3912), .C(n3909), .D(n3911), .Y(n3928) );
NOR4X1TS U3897 ( .A(Op_MX[27]), .B(Op_MX[26]), .C(Op_MX[25]), .D(n472), .Y(
n3919) );
NOR4X1TS U3898 ( .A(Op_MX[22]), .B(Op_MX[21]), .C(Op_MX[19]), .D(Op_MX[20]),
.Y(n3918) );
NOR4BBX1TS U3899 ( .AN(n4172), .BN(n4173), .C(DP_OP_153J7_122_5442_n1495),
.D(Op_MX[18]), .Y(n3917) );
NAND4BXLTS U3900 ( .AN(n3914), .B(n4175), .C(n4176), .D(n4177), .Y(n3915) );
INVX2TS U3901 ( .A(n3915), .Y(n3916) );
NAND4XLTS U3902 ( .A(n3919), .B(n3918), .C(n3917), .D(n3916), .Y(n3927) );
NOR4BBX1TS U3903 ( .AN(n2090), .BN(n4180), .C(DP_OP_154J7_123_2038_n792),
.D(n3920), .Y(n3925) );
NOR4X1TS U3904 ( .A(Op_MX[10]), .B(n3921), .C(Op_MX[8]), .D(Op_MX[11]), .Y(
n3924) );
NAND4XLTS U3905 ( .A(n4174), .B(n3925), .C(n3924), .D(n3923), .Y(n3926) );
OA22X1TS U3906 ( .A0(n3929), .A1(n3928), .B0(n3927), .B1(n3926), .Y(n3930)
);
OAI2BB2XLTS U3907 ( .B0(n3931), .B1(n3930), .A0N(n3931), .A1N(zero_flag),
.Y(n311) );
AO22X1TS U3908 ( .A0(Sgf_normalized_result[3]), .A1(n3933), .B0(
final_result_ieee[3]), .B1(n3937), .Y(n197) );
INVX2TS U3909 ( .A(n3941), .Y(n3932) );
AO22X1TS U3910 ( .A0(Sgf_normalized_result[10]), .A1(n3935), .B0(
final_result_ieee[10]), .B1(n3934), .Y(n190) );
AO22X1TS U3911 ( .A0(Sgf_normalized_result[11]), .A1(n3935), .B0(
final_result_ieee[11]), .B1(n3934), .Y(n189) );
AO22X1TS U3912 ( .A0(Sgf_normalized_result[12]), .A1(n3935), .B0(
final_result_ieee[12]), .B1(n3934), .Y(n188) );
AO22X1TS U3913 ( .A0(Sgf_normalized_result[13]), .A1(n3935), .B0(
final_result_ieee[13]), .B1(n3934), .Y(n187) );
AO22X1TS U3914 ( .A0(Sgf_normalized_result[14]), .A1(n3935), .B0(
final_result_ieee[14]), .B1(n3934), .Y(n186) );
AO22X1TS U3915 ( .A0(Sgf_normalized_result[15]), .A1(n3935), .B0(
final_result_ieee[15]), .B1(n3934), .Y(n185) );
AO22X1TS U3916 ( .A0(Sgf_normalized_result[16]), .A1(n3935), .B0(
final_result_ieee[16]), .B1(n3934), .Y(n184) );
AO22X1TS U3917 ( .A0(Sgf_normalized_result[17]), .A1(n3935), .B0(
final_result_ieee[17]), .B1(n3934), .Y(n183) );
AO22X1TS U3918 ( .A0(Sgf_normalized_result[18]), .A1(n3935), .B0(
final_result_ieee[18]), .B1(n3934), .Y(n182) );
AO22X1TS U3919 ( .A0(Sgf_normalized_result[19]), .A1(n3935), .B0(
final_result_ieee[19]), .B1(n3937), .Y(n181) );
INVX2TS U3920 ( .A(n3940), .Y(n3938) );
AO22X1TS U3921 ( .A0(Sgf_normalized_result[20]), .A1(n3938), .B0(
final_result_ieee[20]), .B1(n3937), .Y(n180) );
AO22X1TS U3922 ( .A0(Sgf_normalized_result[21]), .A1(n3938), .B0(
final_result_ieee[21]), .B1(n3937), .Y(n179) );
AO22X1TS U3923 ( .A0(Sgf_normalized_result[22]), .A1(n3938), .B0(
final_result_ieee[22]), .B1(n3937), .Y(n178) );
OA22X1TS U3924 ( .A0(n3941), .A1(final_result_ieee[23]), .B0(
exp_oper_result[0]), .B1(n3940), .Y(n177) );
OA22X1TS U3925 ( .A0(n3941), .A1(final_result_ieee[24]), .B0(
exp_oper_result[1]), .B1(n3940), .Y(n176) );
OA22X1TS U3926 ( .A0(n3939), .A1(final_result_ieee[25]), .B0(
exp_oper_result[2]), .B1(n3940), .Y(n175) );
OA22X1TS U3927 ( .A0(n3939), .A1(final_result_ieee[26]), .B0(
exp_oper_result[3]), .B1(n3940), .Y(n174) );
OA22X1TS U3928 ( .A0(n3939), .A1(final_result_ieee[27]), .B0(
exp_oper_result[4]), .B1(n3940), .Y(n173) );
OA22X1TS U3929 ( .A0(n3939), .A1(final_result_ieee[28]), .B0(
exp_oper_result[5]), .B1(n3940), .Y(n172) );
OA22X1TS U3930 ( .A0(n3939), .A1(final_result_ieee[29]), .B0(
exp_oper_result[6]), .B1(n3940), .Y(n171) );
OA22X1TS U3931 ( .A0(n3941), .A1(final_result_ieee[30]), .B0(
exp_oper_result[7]), .B1(n3940), .Y(n170) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_clk10.tcl_RKOA_1STAGE_syn.sdf");
endmodule
|
`timescale 1ns / 1ps
//-----------------------------------------------
// Company: agh
// Engineer: komorkiewicz
// Create Date: 23:14:48 04/19/2011
// Description: vga generator
//-----------------------------------------------
module hdmi_in
(
//hdmi outputs
output reg hdmi_clk,
output hdmi_de,
output hdmi_hs,
output hdmi_vs,
//image data
output [7:0]hdmi_r,
output [7:0]hdmi_g,
output [7:0]hdmi_b
);
//-----------------------------------------------
//for now supports VGA 640x480 60Hz only
//horizontal
parameter hr=64; //resolution
parameter hbp=8; //back porch
parameter hfp=8; //front porch
parameter hs=2; //sync len
//vertical
parameter vr=64; //resolution
parameter vbp=8; //back porch
parameter vfp=8; //front porch
parameter vs=4; //sync len
//-----------------------------------------------
reg line=1'b0;
reg vsync=1'b1;
reg hsync=1'b1;
reg enab=1'b0;
reg eenab=1'b0;
reg h_enable=1'b0;
reg v_enable=1'b0;
reg [10:0]hcounter=0;
reg [10:0]vcounter=64+1;//480+7
//-----------------------------------------------
reg [7:0]red;
reg [7:0]green;
reg [7:0]blue;
//reg hdmi_clk=1'b0;
//-----------------------------------------------
initial
begin
while(1)
begin
#1 hdmi_clk=1'b0;
#1 hdmi_clk=1'b1;
end
end
//-----------------------------------------------
integer rgbfile,i,v,clo,cle,wl,x;
//-----------------------------------------------
always @(posedge hdmi_clk)
begin
hcounter<=hcounter+1;
eenab<=enab;
if(hcounter==(hr+hbp)) begin
hsync<=1'b0;
end
if(hcounter==(hr+hbp+hs)) begin
hsync<=1'b1;
line<=1'b0;
end
if(hcounter<hr)
h_enable<=1'b1;
else
h_enable<=1'b0;
if(vcounter<vr)
v_enable<=1'b1;
else
v_enable<=1'b0;
if((v_enable==1'b1)&&(h_enable==1'b1))
enab<=1'b1;
else
enab<=1'b0;
if(hcounter==(hr+hbp+hs+hfp))
begin
hcounter<=0;
line<=1'b1;
end
end
//-----------------------------------------------
//TB only
always @(posedge hdmi_clk)
begin
if(enab)
begin
red=$fgetc(rgbfile);
green=$fgetc(rgbfile);
blue=$fgetc(rgbfile);
end
end
//TB end
//-----------------------------------------------
reg [7:0]vsc=0;
always @(posedge line)
begin
vcounter<=vcounter+1;
if(vcounter==(vr+vbp))
begin
vsync<=1'b0;
//TB only
vsc=vsc+1;
rgbfile = $fopen("geirangerfjord_64.ppm","rb");
// read header file
for(i=0;i<13;i=i+1)
begin
v=$fgetc(rgbfile);
end
//TB end
end
if(vcounter==(vr+vbp+vs)) vsync<=1'b1;
if(vcounter==(vr+vbp+vs+vfp)) vcounter<=0;
end
//-----------------------------------------------
assign hdmi_r=red;
assign hdmi_g=green;
assign hdmi_b=blue;
assign hdmi_de=eenab;
assign hdmi_hs=hsync;
assign hdmi_vs=vsync;
//-----------------------------------------------
endmodule
//-----------------------------------------------
|
(***********************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA-Rocquencourt & LRI-CNRS-Orsay *)
(* \VV/ *************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(***********************************************************************)
(** * MSetRBT : Implementation of MSetInterface via Red-Black trees *)
(** Initial author: Andrew W. Appel, 2011.
Extra modifications by: Pierre Letouzey
The design decisions behind this implementation are described here:
- Efficient Verified Red-Black Trees, by Andrew W. Appel, September 2011.
http://www.cs.princeton.edu/~appel/papers/redblack.pdf
Additional suggested reading:
- Red-Black Trees in a Functional Setting by Chris Okasaki.
Journal of Functional Programming, 9(4):471-477, July 1999.
http://www.eecs.usma.edu/webs/people/okasaki/jfp99redblack.pdf
- Red-black trees with types, by Stefan Kahrs.
Journal of Functional Programming, 11(4), 425-432, 2001.
- Functors for Proofs and Programs, by J.-C. Filliatre and P. Letouzey.
ESOP'04: European Symposium on Programming, pp. 370-384, 2004.
http://www.lri.fr/~filliatr/ftp/publis/fpp.ps.gz
*)
Require MSetGenTree.
Require Import Bool List BinPos Pnat Setoid SetoidList PeanoNat.
Local Open Scope list_scope.
(* For nicer extraction, we create induction principles
only when needed *)
Local Unset Elimination Schemes.
(** An extra function not (yet?) in MSetInterface.S *)
Module Type MSetRemoveMin (Import M:MSetInterface.S).
Parameter remove_min : t -> option (elt * t).
Axiom remove_min_spec1 : forall s k s',
remove_min s = Some (k,s') ->
min_elt s = Some k /\ remove k s [=] s'.
Axiom remove_min_spec2 : forall s, remove_min s = None -> Empty s.
End MSetRemoveMin.
(** The type of color annotation. *)
Inductive color := Red | Black.
Module Color.
Definition t := color.
End Color.
(** * Ops : the pure functions *)
Module Ops (X:Orders.OrderedType) <: MSetInterface.Ops X.
(** ** Generic trees instantiated with color *)
(** We reuse a generic definition of trees where the information
parameter is a color. Functions like mem or fold are also
provided by this generic functor. *)
Include MSetGenTree.Ops X Color.
Definition t := tree.
Local Notation Rd := (Node Red).
Local Notation Bk := (Node Black).
(** ** Basic tree *)
Definition singleton (k: elt) : tree := Bk Leaf k Leaf.
(** ** Changing root color *)
Definition makeBlack t :=
match t with
| Leaf => Leaf
| Node _ a x b => Bk a x b
end.
Definition makeRed t :=
match t with
| Leaf => Leaf
| Node _ a x b => Rd a x b
end.
(** ** Balancing *)
(** We adapt when one side is not a true red-black tree.
Both sides have the same black depth. *)
Definition lbal l k r :=
match l with
| Rd (Rd a x b) y c => Rd (Bk a x b) y (Bk c k r)
| Rd a x (Rd b y c) => Rd (Bk a x b) y (Bk c k r)
| _ => Bk l k r
end.
Definition rbal l k r :=
match r with
| Rd (Rd b y c) z d => Rd (Bk l k b) y (Bk c z d)
| Rd b y (Rd c z d) => Rd (Bk l k b) y (Bk c z d)
| _ => Bk l k r
end.
(** A variant of [rbal], with reverse pattern order.
Is it really useful ? Should we always use it ? *)
Definition rbal' l k r :=
match r with
| Rd b y (Rd c z d) => Rd (Bk l k b) y (Bk c z d)
| Rd (Rd b y c) z d => Rd (Bk l k b) y (Bk c z d)
| _ => Bk l k r
end.
(** Balancing with different black depth.
One side is almost a red-black tree, while the other is
a true red-black tree, but with black depth + 1.
Used in deletion. *)
Definition lbalS l k r :=
match l with
| Rd a x b => Rd (Bk a x b) k r
| _ =>
match r with
| Bk a y b => rbal' l k (Rd a y b)
| Rd (Bk a y b) z c => Rd (Bk l k a) y (rbal' b z (makeRed c))
| _ => Rd l k r (* impossible *)
end
end.
Definition rbalS l k r :=
match r with
| Rd b y c => Rd l k (Bk b y c)
| _ =>
match l with
| Bk a x b => lbal (Rd a x b) k r
| Rd a x (Bk b y c) => Rd (lbal (makeRed a) x b) y (Bk c k r)
| _ => Rd l k r (* impossible *)
end
end.
(** ** Insertion *)
Fixpoint ins x s :=
match s with
| Leaf => Rd Leaf x Leaf
| Node c l y r =>
match X.compare x y with
| Eq => s
| Lt =>
match c with
| Red => Rd (ins x l) y r
| Black => lbal (ins x l) y r
end
| Gt =>
match c with
| Red => Rd l y (ins x r)
| Black => rbal l y (ins x r)
end
end
end.
Definition add x s := makeBlack (ins x s).
(** ** Deletion *)
Fixpoint append (l:tree) : tree -> tree :=
match l with
| Leaf => fun r => r
| Node lc ll lx lr =>
fix append_l (r:tree) : tree :=
match r with
| Leaf => l
| Node rc rl rx rr =>
match lc, rc with
| Red, Red =>
let lrl := append lr rl in
match lrl with
| Rd lr' x rl' => Rd (Rd ll lx lr') x (Rd rl' rx rr)
| _ => Rd ll lx (Rd lrl rx rr)
end
| Black, Black =>
let lrl := append lr rl in
match lrl with
| Rd lr' x rl' => Rd (Bk ll lx lr') x (Bk rl' rx rr)
| _ => lbalS ll lx (Bk lrl rx rr)
end
| Black, Red => Rd (append_l rl) rx rr
| Red, Black => Rd ll lx (append lr r)
end
end
end.
Fixpoint del x t :=
match t with
| Leaf => Leaf
| Node _ a y b =>
match X.compare x y with
| Eq => append a b
| Lt =>
match a with
| Bk _ _ _ => lbalS (del x a) y b
| _ => Rd (del x a) y b
end
| Gt =>
match b with
| Bk _ _ _ => rbalS a y (del x b)
| _ => Rd a y (del x b)
end
end
end.
Definition remove x t := makeBlack (del x t).
(** ** Removing minimal element *)
Fixpoint delmin l x r : (elt * tree) :=
match l with
| Leaf => (x,r)
| Node lc ll lx lr =>
let (k,l') := delmin ll lx lr in
match lc with
| Black => (k, lbalS l' x r)
| Red => (k, Rd l' x r)
end
end.
Definition remove_min t : option (elt * tree) :=
match t with
| Leaf => None
| Node _ l x r =>
let (k,t) := delmin l x r in
Some (k, makeBlack t)
end.
(** ** Tree-ification
We rebuild a tree of size [if pred then n-1 else n] as soon
as the list [l] has enough elements *)
Definition bogus : tree * list elt := (Leaf, nil).
Notation treeify_t := (list elt -> tree * list elt).
Definition treeify_zero : treeify_t :=
fun acc => (Leaf,acc).
Definition treeify_one : treeify_t :=
fun acc => match acc with
| x::acc => (Rd Leaf x Leaf, acc)
| _ => bogus
end.
Definition treeify_cont (f g : treeify_t) : treeify_t :=
fun acc =>
match f acc with
| (l, x::acc) =>
match g acc with
| (r, acc) => (Bk l x r, acc)
end
| _ => bogus
end.
Fixpoint treeify_aux (pred:bool)(n: positive) : treeify_t :=
match n with
| xH => if pred then treeify_zero else treeify_one
| xO n => treeify_cont (treeify_aux pred n) (treeify_aux true n)
| xI n => treeify_cont (treeify_aux false n) (treeify_aux pred n)
end.
Fixpoint plength_aux (l:list elt)(p:positive) := match l with
| nil => p
| _::l => plength_aux l (Pos.succ p)
end.
Definition plength l := plength_aux l 1.
Definition treeify (l:list elt) :=
fst (treeify_aux true (plength l) l).
(** ** Filtering *)
Fixpoint filter_aux (f: elt -> bool) s acc :=
match s with
| Leaf => acc
| Node _ l k r =>
let acc := filter_aux f r acc in
if f k then filter_aux f l (k::acc)
else filter_aux f l acc
end.
Definition filter (f: elt -> bool) (s: t) : t :=
treeify (filter_aux f s nil).
Fixpoint partition_aux (f: elt -> bool) s acc1 acc2 :=
match s with
| Leaf => (acc1,acc2)
| Node _ sl k sr =>
let (acc1, acc2) := partition_aux f sr acc1 acc2 in
if f k then partition_aux f sl (k::acc1) acc2
else partition_aux f sl acc1 (k::acc2)
end.
Definition partition (f: elt -> bool) (s:t) : t*t :=
let (ok,ko) := partition_aux f s nil nil in
(treeify ok, treeify ko).
(** ** Union, intersection, difference *)
(** union of the elements of [l1] and [l2] into a third [acc] list. *)
Fixpoint union_list l1 : list elt -> list elt -> list elt :=
match l1 with
| nil => @rev_append _
| x::l1' =>
fix union_l1 l2 acc :=
match l2 with
| nil => rev_append l1 acc
| y::l2' =>
match X.compare x y with
| Eq => union_list l1' l2' (x::acc)
| Lt => union_l1 l2' (y::acc)
| Gt => union_list l1' l2 (x::acc)
end
end
end.
Definition linear_union s1 s2 :=
treeify (union_list (rev_elements s1) (rev_elements s2) nil).
Fixpoint inter_list l1 : list elt -> list elt -> list elt :=
match l1 with
| nil => fun _ acc => acc
| x::l1' =>
fix inter_l1 l2 acc :=
match l2 with
| nil => acc
| y::l2' =>
match X.compare x y with
| Eq => inter_list l1' l2' (x::acc)
| Lt => inter_l1 l2' acc
| Gt => inter_list l1' l2 acc
end
end
end.
Definition linear_inter s1 s2 :=
treeify (inter_list (rev_elements s1) (rev_elements s2) nil).
Fixpoint diff_list l1 : list elt -> list elt -> list elt :=
match l1 with
| nil => fun _ acc => acc
| x::l1' =>
fix diff_l1 l2 acc :=
match l2 with
| nil => rev_append l1 acc
| y::l2' =>
match X.compare x y with
| Eq => diff_list l1' l2' acc
| Lt => diff_l1 l2' acc
| Gt => diff_list l1' l2 (x::acc)
end
end
end.
Definition linear_diff s1 s2 :=
treeify (diff_list (rev_elements s1) (rev_elements s2) nil).
(** [compare_height] returns:
- [Lt] if [height s2] is at least twice [height s1];
- [Gt] if [height s1] is at least twice [height s2];
- [Eq] if heights are approximately equal.
Warning: this is not an equivalence relation! but who cares.... *)
Definition skip_red t :=
match t with
| Rd t' _ _ => t'
| _ => t
end.
Definition skip_black t :=
match skip_red t with
| Bk t' _ _ => t'
| t' => t'
end.
Fixpoint compare_height (s1x s1 s2 s2x: tree) : comparison :=
match skip_red s1x, skip_red s1, skip_red s2, skip_red s2x with
| Node _ s1x' _ _, Node _ s1' _ _, Node _ s2' _ _, Node _ s2x' _ _ =>
compare_height (skip_black s1x') s1' s2' (skip_black s2x')
| _, Leaf, _, Node _ _ _ _ => Lt
| Node _ _ _ _, _, Leaf, _ => Gt
| Node _ s1x' _ _, Node _ s1' _ _, Node _ s2' _ _, Leaf =>
compare_height (skip_black s1x') s1' s2' Leaf
| Leaf, Node _ s1' _ _, Node _ s2' _ _, Node _ s2x' _ _ =>
compare_height Leaf s1' s2' (skip_black s2x')
| _, _, _, _ => Eq
end.
(** When one tree is quite smaller than the other, we simply
adds repeatively all its elements in the big one.
For trees of comparable height, we rather use [linear_union]. *)
Definition union (t1 t2: t) : t :=
match compare_height t1 t1 t2 t2 with
| Lt => fold add t1 t2
| Gt => fold add t2 t1
| Eq => linear_union t1 t2
end.
Definition diff (t1 t2: t) : t :=
match compare_height t1 t1 t2 t2 with
| Lt => filter (fun k => negb (mem k t2)) t1
| Gt => fold remove t2 t1
| Eq => linear_diff t1 t2
end.
Definition inter (t1 t2: t) : t :=
match compare_height t1 t1 t2 t2 with
| Lt => filter (fun k => mem k t2) t1
| Gt => filter (fun k => mem k t1) t2
| Eq => linear_inter t1 t2
end.
End Ops.
(** * MakeRaw : the pure functions and their specifications *)
Module Type MakeRaw (X:Orders.OrderedType) <: MSetInterface.RawSets X.
Include Ops X.
(** Generic definition of binary-search-trees and proofs of
specifications for generic functions such as mem or fold. *)
Include MSetGenTree.Props X Color.
Local Notation Rd := (Node Red).
Local Notation Bk := (Node Black).
Local Hint Immediate MX.eq_sym.
Local Hint Unfold In lt_tree gt_tree Ok.
Local Hint Constructors InT bst.
Local Hint Resolve MX.eq_refl MX.eq_trans MX.lt_trans ok.
Local Hint Resolve lt_leaf gt_leaf lt_tree_node gt_tree_node.
Local Hint Resolve lt_tree_not_in lt_tree_trans gt_tree_not_in gt_tree_trans.
Local Hint Resolve elements_spec2.
(** ** Singleton set *)
Lemma singleton_spec x y : InT y (singleton x) <-> X.eq y x.
Proof.
unfold singleton; intuition_in.
Qed.
Instance singleton_ok x : Ok (singleton x).
Proof.
unfold singleton; auto.
Qed.
(** ** makeBlack, MakeRed *)
Lemma makeBlack_spec s x : InT x (makeBlack s) <-> InT x s.
Proof.
destruct s; simpl; intuition_in.
Qed.
Lemma makeRed_spec s x : InT x (makeRed s) <-> InT x s.
Proof.
destruct s; simpl; intuition_in.
Qed.
Instance makeBlack_ok s `{Ok s} : Ok (makeBlack s).
Proof.
destruct s; simpl; ok.
Qed.
Instance makeRed_ok s `{Ok s} : Ok (makeRed s).
Proof.
destruct s; simpl; ok.
Qed.
(** ** Generic handling for red-matching and red-red-matching *)
Definition isblack t :=
match t with Bk _ _ _ => True | _ => False end.
Definition notblack t :=
match t with Bk _ _ _ => False | _ => True end.
Definition notred t :=
match t with Rd _ _ _ => False | _ => True end.
Definition rcase {A} f g t : A :=
match t with
| Rd a x b => f a x b
| _ => g t
end.
Inductive rspec {A} f g : tree -> A -> Prop :=
| rred a x b : rspec f g (Rd a x b) (f a x b)
| relse t : notred t -> rspec f g t (g t).
Fact rmatch {A} f g t : rspec (A:=A) f g t (rcase f g t).
Proof.
destruct t as [|[|] l x r]; simpl; now constructor.
Qed.
Definition rrcase {A} f g t : A :=
match t with
| Rd (Rd a x b) y c => f a x b y c
| Rd a x (Rd b y c) => f a x b y c
| _ => g t
end.
Notation notredred := (rrcase (fun _ _ _ _ _ => False) (fun _ => True)).
Inductive rrspec {A} f g : tree -> A -> Prop :=
| rrleft a x b y c : rrspec f g (Rd (Rd a x b) y c) (f a x b y c)
| rrright a x b y c : rrspec f g (Rd a x (Rd b y c)) (f a x b y c)
| rrelse t : notredred t -> rrspec f g t (g t).
Fact rrmatch {A} f g t : rrspec (A:=A) f g t (rrcase f g t).
Proof.
destruct t as [|[|] l x r]; simpl; try now constructor.
destruct l as [|[|] ll lx lr], r as [|[|] rl rx rr]; now constructor.
Qed.
Definition rrcase' {A} f g t : A :=
match t with
| Rd a x (Rd b y c) => f a x b y c
| Rd (Rd a x b) y c => f a x b y c
| _ => g t
end.
Fact rrmatch' {A} f g t : rrspec (A:=A) f g t (rrcase' f g t).
Proof.
destruct t as [|[|] l x r]; simpl; try now constructor.
destruct l as [|[|] ll lx lr], r as [|[|] rl rx rr]; now constructor.
Qed.
(** Balancing operations are instances of generic match *)
Fact lbal_match l k r :
rrspec
(fun a x b y c => Rd (Bk a x b) y (Bk c k r))
(fun l => Bk l k r)
l
(lbal l k r).
Proof.
exact (rrmatch _ _ _).
Qed.
Fact rbal_match l k r :
rrspec
(fun a x b y c => Rd (Bk l k a) x (Bk b y c))
(fun r => Bk l k r)
r
(rbal l k r).
Proof.
exact (rrmatch _ _ _).
Qed.
Fact rbal'_match l k r :
rrspec
(fun a x b y c => Rd (Bk l k a) x (Bk b y c))
(fun r => Bk l k r)
r
(rbal' l k r).
Proof.
exact (rrmatch' _ _ _).
Qed.
Fact lbalS_match l x r :
rspec
(fun a y b => Rd (Bk a y b) x r)
(fun l =>
match r with
| Bk a y b => rbal' l x (Rd a y b)
| Rd (Bk a y b) z c => Rd (Bk l x a) y (rbal' b z (makeRed c))
| _ => Rd l x r
end)
l
(lbalS l x r).
Proof.
exact (rmatch _ _ _).
Qed.
Fact rbalS_match l x r :
rspec
(fun a y b => Rd l x (Bk a y b))
(fun r =>
match l with
| Bk a y b => lbal (Rd a y b) x r
| Rd a y (Bk b z c) => Rd (lbal (makeRed a) y b) z (Bk c x r)
| _ => Rd l x r
end)
r
(rbalS l x r).
Proof.
exact (rmatch _ _ _).
Qed.
(** ** Balancing for insertion *)
Lemma lbal_spec l x r y :
InT y (lbal l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case lbal_match; intuition_in.
Qed.
Instance lbal_ok l x r `(Ok l, Ok r, lt_tree x l, gt_tree x r) :
Ok (lbal l x r).
Proof.
destruct (lbal_match l x r); ok.
Qed.
Lemma rbal_spec l x r y :
InT y (rbal l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case rbal_match; intuition_in.
Qed.
Instance rbal_ok l x r `(Ok l, Ok r, lt_tree x l, gt_tree x r) :
Ok (rbal l x r).
Proof.
destruct (rbal_match l x r); ok.
Qed.
Lemma rbal'_spec l x r y :
InT y (rbal' l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case rbal'_match; intuition_in.
Qed.
Instance rbal'_ok l x r `(Ok l, Ok r, lt_tree x l, gt_tree x r) :
Ok (rbal' l x r).
Proof.
destruct (rbal'_match l x r); ok.
Qed.
Hint Rewrite In_node_iff In_leaf_iff
makeRed_spec makeBlack_spec lbal_spec rbal_spec rbal'_spec : rb.
Ltac descolor := destruct_all Color.t.
Ltac destree t := destruct t as [|[|] ? ? ?].
Ltac autorew := autorewrite with rb.
Tactic Notation "autorew" "in" ident(H) := autorewrite with rb in H.
(** ** Insertion *)
Lemma ins_spec : forall s x y,
InT y (ins x s) <-> X.eq y x \/ InT y s.
Proof.
induct s x.
- intuition_in.
- intuition_in. setoid_replace y with x; eauto.
- descolor; autorew; rewrite IHl; intuition_in.
- descolor; autorew; rewrite IHr; intuition_in.
Qed.
Hint Rewrite ins_spec : rb.
Instance ins_ok s x `{Ok s} : Ok (ins x s).
Proof.
induct s x; auto; descolor;
(apply lbal_ok || apply rbal_ok || ok); auto;
intros y; autorew; intuition; order.
Qed.
Lemma add_spec' s x y :
InT y (add x s) <-> X.eq y x \/ InT y s.
Proof.
unfold add. now autorew.
Qed.
Hint Rewrite add_spec' : rb.
Lemma add_spec s x y `{Ok s} :
InT y (add x s) <-> X.eq y x \/ InT y s.
Proof.
apply add_spec'.
Qed.
Instance add_ok s x `{Ok s} : Ok (add x s).
Proof.
unfold add; auto_tc.
Qed.
(** ** Balancing for deletion *)
Lemma lbalS_spec l x r y :
InT y (lbalS l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case lbalS_match.
- intros; autorew; intuition_in.
- clear l. intros l _.
destruct r as [|[|] rl rx rr].
* autorew. intuition_in.
* destree rl; autorew; intuition_in.
* autorew. intuition_in.
Qed.
Instance lbalS_ok l x r :
forall `(Ok l, Ok r, lt_tree x l, gt_tree x r), Ok (lbalS l x r).
Proof.
case lbalS_match; intros.
- ok.
- destruct r as [|[|] rl rx rr].
* ok.
* destruct rl as [|[|] rll rlx rlr]; intros; ok.
+ apply rbal'_ok; ok.
intros w; autorew; auto.
+ intros w; autorew.
destruct 1 as [Hw|[Hw|Hw]]; try rewrite Hw; eauto.
* ok. autorew. apply rbal'_ok; ok.
Qed.
Lemma rbalS_spec l x r y :
InT y (rbalS l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case rbalS_match.
- intros; autorew; intuition_in.
- intros t _.
destruct l as [|[|] ll lx lr].
* autorew. intuition_in.
* destruct lr as [|[|] lrl lrx lrr]; autorew; intuition_in.
* autorew. intuition_in.
Qed.
Instance rbalS_ok l x r :
forall `(Ok l, Ok r, lt_tree x l, gt_tree x r), Ok (rbalS l x r).
Proof.
case rbalS_match; intros.
- ok.
- destruct l as [|[|] ll lx lr].
* ok.
* destruct lr as [|[|] lrl lrx lrr]; intros; ok.
+ apply lbal_ok; ok.
intros w; autorew; auto.
+ intros w; autorew.
destruct 1 as [Hw|[Hw|Hw]]; try rewrite Hw; eauto.
* ok. apply lbal_ok; ok.
Qed.
Hint Rewrite lbalS_spec rbalS_spec : rb.
(** ** Append for deletion *)
Ltac append_tac l r :=
induction l as [| lc ll _ lx lr IHlr];
[intro r; simpl
|induction r as [| rc rl IHrl rx rr _];
[simpl
|destruct lc, rc;
[specialize (IHlr rl); clear IHrl
|simpl;
assert (Hr:notred (Bk rl rx rr)) by (simpl; trivial);
set (r:=Bk rl rx rr) in *; clearbody r; clear IHrl rl rx rr;
specialize (IHlr r)
|change (append _ _) with (Rd (append (Bk ll lx lr) rl) rx rr);
assert (Hl:notred (Bk ll lx lr)) by (simpl; trivial);
set (l:=Bk ll lx lr) in *; clearbody l; clear IHlr ll lx lr
|specialize (IHlr rl); clear IHrl]]].
Fact append_rr_match ll lx lr rl rx rr :
rspec
(fun a x b => Rd (Rd ll lx a) x (Rd b rx rr))
(fun t => Rd ll lx (Rd t rx rr))
(append lr rl)
(append (Rd ll lx lr) (Rd rl rx rr)).
Proof.
exact (rmatch _ _ _).
Qed.
Fact append_bb_match ll lx lr rl rx rr :
rspec
(fun a x b => Rd (Bk ll lx a) x (Bk b rx rr))
(fun t => lbalS ll lx (Bk t rx rr))
(append lr rl)
(append (Bk ll lx lr) (Bk rl rx rr)).
Proof.
exact (rmatch _ _ _).
Qed.
Lemma append_spec l r x :
InT x (append l r) <-> InT x l \/ InT x r.
Proof.
revert r.
append_tac l r; autorew; try tauto.
- (* Red / Red *)
revert IHlr; case append_rr_match;
[intros a y b | intros t Ht]; autorew; tauto.
- (* Black / Black *)
revert IHlr; case append_bb_match;
[intros a y b | intros t Ht]; autorew; tauto.
Qed.
Hint Rewrite append_spec : rb.
Lemma append_ok : forall x l r `{Ok l, Ok r},
lt_tree x l -> gt_tree x r -> Ok (append l r).
Proof.
append_tac l r.
- (* Leaf / _ *)
trivial.
- (* _ / Leaf *)
trivial.
- (* Red / Red *)
intros; inv.
assert (IH : Ok (append lr rl)) by (apply IHlr; eauto). clear IHlr.
assert (X.lt lx rx) by (transitivity x; eauto).
assert (G : gt_tree lx (append lr rl)).
{ intros w. autorew. destruct 1; [|transitivity x]; eauto. }
assert (L : lt_tree rx (append lr rl)).
{ intros w. autorew. destruct 1; [transitivity x|]; eauto. }
revert IH G L; case append_rr_match; intros; ok.
- (* Red / Black *)
intros; ok.
intros w; autorew; destruct 1; eauto.
- (* Black / Red *)
intros; ok.
intros w; autorew; destruct 1; eauto.
- (* Black / Black *)
intros; inv.
assert (IH : Ok (append lr rl)) by (apply IHlr; eauto). clear IHlr.
assert (X.lt lx rx) by (transitivity x; eauto).
assert (G : gt_tree lx (append lr rl)).
{ intros w. autorew. destruct 1; [|transitivity x]; eauto. }
assert (L : lt_tree rx (append lr rl)).
{ intros w. autorew. destruct 1; [transitivity x|]; eauto. }
revert IH G L; case append_bb_match; intros; ok.
apply lbalS_ok; ok.
Qed.
(** ** Deletion *)
Lemma del_spec : forall s x y `{Ok s},
InT y (del x s) <-> InT y s /\ ~X.eq y x.
Proof.
induct s x.
- intuition_in.
- autorew; intuition_in.
assert (X.lt y x') by eauto. order.
assert (X.lt x' y) by eauto. order.
order.
- destruct l as [|[|] ll lx lr]; autorew;
rewrite ?IHl by trivial; intuition_in; order.
- destruct r as [|[|] rl rx rr]; autorew;
rewrite ?IHr by trivial; intuition_in; order.
Qed.
Hint Rewrite del_spec : rb.
Instance del_ok s x `{Ok s} : Ok (del x s).
Proof.
induct s x.
- trivial.
- eapply append_ok; eauto.
- assert (lt_tree x' (del x l)).
{ intro w. autorew; trivial. destruct 1. eauto. }
destruct l as [|[|] ll lx lr]; auto_tc.
- assert (gt_tree x' (del x r)).
{ intro w. autorew; trivial. destruct 1. eauto. }
destruct r as [|[|] rl rx rr]; auto_tc.
Qed.
Lemma remove_spec s x y `{Ok s} :
InT y (remove x s) <-> InT y s /\ ~X.eq y x.
Proof.
unfold remove. now autorew.
Qed.
Hint Rewrite remove_spec : rb.
Instance remove_ok s x `{Ok s} : Ok (remove x s).
Proof.
unfold remove; auto_tc.
Qed.
(** ** Removing the minimal element *)
Lemma delmin_spec l y r c x s' `{O : Ok (Node c l y r)} :
delmin l y r = (x,s') ->
min_elt (Node c l y r) = Some x /\ del x (Node c l y r) = s'.
Proof.
revert y r c x s' O.
induction l as [|lc ll IH ly lr _].
- simpl. intros y r _ x s' _. injection 1; intros; subst.
now rewrite MX.compare_refl.
- intros y r c x s' O.
simpl delmin.
specialize (IH ly lr). destruct delmin as (x0,s0).
destruct (IH lc x0 s0); clear IH; [ok|trivial|].
remember (Node lc ll ly lr) as l.
simpl min_elt in *.
intros E.
replace x0 with x in * by (destruct lc; now injection E).
split.
* subst l; intuition.
* assert (X.lt x y).
{ inversion_clear O.
assert (InT x l) by now apply min_elt_spec1. auto. }
simpl. case X.compare_spec; try order.
destruct lc; injection E; subst l s0; auto.
Qed.
Lemma remove_min_spec1 s x s' `{Ok s}:
remove_min s = Some (x,s') ->
min_elt s = Some x /\ remove x s = s'.
Proof.
unfold remove_min.
destruct s as [|c l y r]; try easy.
generalize (delmin_spec l y r c).
destruct delmin as (x0,s0). intros D.
destruct (D x0 s0) as (->,<-); auto.
fold (remove x0 (Node c l y r)).
inversion_clear 1; auto.
Qed.
Lemma remove_min_spec2 s : remove_min s = None -> Empty s.
Proof.
unfold remove_min.
destruct s as [|c l y r].
- easy.
- now destruct delmin.
Qed.
Lemma remove_min_ok (s:t) `{Ok s}:
match remove_min s with
| Some (_,s') => Ok s'
| None => True
end.
Proof.
generalize (remove_min_spec1 s).
destruct remove_min as [(x0,s0)|]; auto.
intros R. destruct (R x0 s0); auto. subst s0. auto_tc.
Qed.
(** ** Treeify *)
Notation ifpred p n := (if p then pred n else n%nat).
Definition treeify_invariant size (f:treeify_t) :=
forall acc,
size <= length acc ->
let (t,acc') := f acc in
cardinal t = size /\ acc = elements t ++ acc'.
Lemma treeify_zero_spec : treeify_invariant 0 treeify_zero.
Proof.
intro. simpl. auto.
Qed.
Lemma treeify_one_spec : treeify_invariant 1 treeify_one.
Proof.
intros [|x acc]; simpl; auto; inversion 1.
Qed.
Lemma treeify_cont_spec f g size1 size2 size :
treeify_invariant size1 f ->
treeify_invariant size2 g ->
size = S (size1 + size2) ->
treeify_invariant size (treeify_cont f g).
Proof.
intros Hf Hg EQ acc LE. unfold treeify_cont.
specialize (Hf acc).
destruct (f acc) as (t1,acc1).
destruct Hf as (Hf1,Hf2).
{ transitivity size; trivial. subst. auto with arith. }
destruct acc1 as [|x acc1].
{ exfalso. revert LE. apply Nat.lt_nge. subst.
rewrite app_nil_r, <- elements_cardinal; auto with arith. }
specialize (Hg acc1).
destruct (g acc1) as (t2,acc2).
destruct Hg as (Hg1,Hg2).
{ revert LE. subst.
rewrite app_length, <- elements_cardinal. simpl.
rewrite Nat.add_succ_r, <- Nat.succ_le_mono.
apply Nat.add_le_mono_l. }
rewrite elements_node, app_ass. now subst.
Qed.
Lemma treeify_aux_spec n (p:bool) :
treeify_invariant (ifpred p (Pos.to_nat n)) (treeify_aux p n).
Proof.
revert p.
induction n as [n|n|]; intros p; simpl treeify_aux.
- eapply treeify_cont_spec; [ apply (IHn false) | apply (IHn p) | ].
rewrite Pos2Nat.inj_xI.
assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H.
destruct p; simpl; intros; rewrite Nat.add_0_r; trivial.
now rewrite <- Nat.add_succ_r, Nat.succ_pred; trivial.
- eapply treeify_cont_spec; [ apply (IHn p) | apply (IHn true) | ].
rewrite Pos2Nat.inj_xO.
assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H.
rewrite <- Nat.add_succ_r, Nat.succ_pred by trivial.
destruct p; simpl; intros; rewrite Nat.add_0_r; trivial.
symmetry. now apply Nat.add_pred_l.
- destruct p; [ apply treeify_zero_spec | apply treeify_one_spec ].
Qed.
Lemma plength_aux_spec l p :
Pos.to_nat (plength_aux l p) = length l + Pos.to_nat p.
Proof.
revert p. induction l; trivial. simpl plength_aux.
intros. now rewrite IHl, Pos2Nat.inj_succ, Nat.add_succ_r.
Qed.
Lemma plength_spec l : Pos.to_nat (plength l) = S (length l).
Proof.
unfold plength. rewrite plength_aux_spec. apply Nat.add_1_r.
Qed.
Lemma treeify_elements l : elements (treeify l) = l.
Proof.
assert (H := treeify_aux_spec (plength l) true l).
unfold treeify. destruct treeify_aux as (t,acc); simpl in *.
destruct H as (H,H'). { now rewrite plength_spec. }
subst l. rewrite plength_spec, app_length, <- elements_cardinal in *.
destruct acc.
* now rewrite app_nil_r.
* exfalso. revert H. simpl.
rewrite Nat.add_succ_r, Nat.add_comm.
apply Nat.succ_add_discr.
Qed.
Lemma treeify_spec x l : InT x (treeify l) <-> InA X.eq x l.
Proof.
intros. now rewrite <- elements_spec1, treeify_elements.
Qed.
Lemma treeify_ok l : sort X.lt l -> Ok (treeify l).
Proof.
intros. apply elements_sort_ok. rewrite treeify_elements; auto.
Qed.
(** ** Filter *)
Lemma filter_app A f (l l':list A) :
List.filter f (l ++ l') = List.filter f l ++ List.filter f l'.
Proof.
induction l as [|x l IH]; simpl; trivial.
destruct (f x); simpl; now rewrite IH.
Qed.
Lemma filter_aux_elements s f acc :
filter_aux f s acc = List.filter f (elements s) ++ acc.
Proof.
revert acc.
induction s as [|c l IHl x r IHr]; trivial.
intros acc.
rewrite elements_node, filter_app. simpl.
destruct (f x); now rewrite IHl, IHr, app_ass.
Qed.
Lemma filter_elements s f :
elements (filter f s) = List.filter f (elements s).
Proof.
unfold filter.
now rewrite treeify_elements, filter_aux_elements, app_nil_r.
Qed.
Lemma filter_spec s x f :
Proper (X.eq==>Logic.eq) f ->
(InT x (filter f s) <-> InT x s /\ f x = true).
Proof.
intros Hf.
rewrite <- elements_spec1, filter_elements, filter_InA, elements_spec1;
now auto_tc.
Qed.
Instance filter_ok s f `(Ok s) : Ok (filter f s).
Proof.
apply elements_sort_ok.
rewrite filter_elements.
apply filter_sort with X.eq; auto_tc.
Qed.
(** ** Partition *)
Lemma partition_aux_spec s f acc1 acc2 :
partition_aux f s acc1 acc2 =
(filter_aux f s acc1, filter_aux (fun x => negb (f x)) s acc2).
Proof.
revert acc1 acc2.
induction s as [ | c l Hl x r Hr ]; simpl.
- trivial.
- intros acc1 acc2.
destruct (f x); simpl; now rewrite Hr, Hl.
Qed.
Lemma partition_spec s f :
partition f s = (filter f s, filter (fun x => negb (f x)) s).
Proof.
unfold partition, filter. now rewrite partition_aux_spec.
Qed.
Lemma partition_spec1 s f :
Proper (X.eq==>Logic.eq) f ->
Equal (fst (partition f s)) (filter f s).
Proof. now rewrite partition_spec. Qed.
Lemma partition_spec2 s f :
Proper (X.eq==>Logic.eq) f ->
Equal (snd (partition f s)) (filter (fun x => negb (f x)) s).
Proof. now rewrite partition_spec. Qed.
Instance partition_ok1 s f `(Ok s) : Ok (fst (partition f s)).
Proof. rewrite partition_spec; now apply filter_ok. Qed.
Instance partition_ok2 s f `(Ok s) : Ok (snd (partition f s)).
Proof. rewrite partition_spec; now apply filter_ok. Qed.
(** ** An invariant for binary list functions with accumulator. *)
Ltac inA :=
rewrite ?InA_app_iff, ?InA_cons, ?InA_nil, ?InA_rev in *; auto_tc.
Record INV l1 l2 acc : Prop := {
l1_sorted : sort X.lt (rev l1);
l2_sorted : sort X.lt (rev l2);
acc_sorted : sort X.lt acc;
l1_lt_acc x y : InA X.eq x l1 -> InA X.eq y acc -> X.lt x y;
l2_lt_acc x y : InA X.eq x l2 -> InA X.eq y acc -> X.lt x y}.
Local Hint Resolve l1_sorted l2_sorted acc_sorted.
Lemma INV_init s1 s2 `(Ok s1, Ok s2) :
INV (rev_elements s1) (rev_elements s2) nil.
Proof.
rewrite !rev_elements_rev.
split; rewrite ?rev_involutive; auto; intros; now inA.
Qed.
Lemma INV_sym l1 l2 acc : INV l1 l2 acc -> INV l2 l1 acc.
Proof.
destruct 1; now split.
Qed.
Lemma INV_drop x1 l1 l2 acc :
INV (x1 :: l1) l2 acc -> INV l1 l2 acc.
Proof.
intros (l1s,l2s,accs,l1a,l2a). simpl in *.
destruct (sorted_app_inv _ _ l1s) as (U & V & W); auto.
split; auto.
Qed.
Lemma INV_eq x1 x2 l1 l2 acc :
INV (x1 :: l1) (x2 :: l2) acc -> X.eq x1 x2 ->
INV l1 l2 (x1 :: acc).
Proof.
intros (U,V,W,X,Y) EQ. simpl in *.
destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto.
destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto.
split; auto.
- constructor; auto. apply InA_InfA with X.eq; auto_tc.
- intros x y; inA; intros Hx [Hy|Hy].
+ apply U3; inA.
+ apply X; inA.
- intros x y; inA; intros Hx [Hy|Hy].
+ rewrite Hy, EQ; apply V3; inA.
+ apply Y; inA.
Qed.
Lemma INV_lt x1 x2 l1 l2 acc :
INV (x1 :: l1) (x2 :: l2) acc -> X.lt x1 x2 ->
INV (x1 :: l1) l2 (x2 :: acc).
Proof.
intros (U,V,W,X,Y) EQ. simpl in *.
destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto.
destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto.
split; auto.
- constructor; auto. apply InA_InfA with X.eq; auto_tc.
- intros x y; inA; intros Hx [Hy|Hy].
+ rewrite Hy; clear Hy. destruct Hx; [order|].
transitivity x1; auto. apply U3; inA.
+ apply X; inA.
- intros x y; inA; intros Hx [Hy|Hy].
+ rewrite Hy. apply V3; inA.
+ apply Y; inA.
Qed.
Lemma INV_rev l1 l2 acc :
INV l1 l2 acc -> Sorted X.lt (rev_append l1 acc).
Proof.
intros. rewrite rev_append_rev.
apply SortA_app with X.eq; eauto with *.
intros x y. inA. eapply @l1_lt_acc; eauto.
Qed.
(** ** union *)
Lemma union_list_ok l1 l2 acc :
INV l1 l2 acc -> sort X.lt (union_list l1 l2 acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1];
[intro l2|induction l2 as [|x2 l2 IH2]];
intros acc inv.
- eapply INV_rev, INV_sym; eauto.
- eapply INV_rev; eauto.
- simpl. case X.compare_spec; intro C.
* apply IH1. eapply INV_eq; eauto.
* apply (IH2 (x2::acc)). eapply INV_lt; eauto.
* apply IH1. eapply INV_sym, INV_lt; eauto. now apply INV_sym.
Qed.
Instance linear_union_ok s1 s2 `(Ok s1, Ok s2) :
Ok (linear_union s1 s2).
Proof.
unfold linear_union. now apply treeify_ok, union_list_ok, INV_init.
Qed.
Instance fold_add_ok s1 s2 `(Ok s1, Ok s2) :
Ok (fold add s1 s2).
Proof.
rewrite fold_spec, <- fold_left_rev_right.
unfold elt in *.
induction (rev (elements s1)); simpl; unfold flip in *; auto_tc.
Qed.
Instance union_ok s1 s2 `(Ok s1, Ok s2) : Ok (union s1 s2).
Proof.
unfold union. destruct compare_height; auto_tc.
Qed.
Lemma union_list_spec x l1 l2 acc :
InA X.eq x (union_list l1 l2 acc) <->
InA X.eq x l1 \/ InA X.eq x l2 \/ InA X.eq x acc.
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1].
- intros l2 acc; simpl. rewrite rev_append_rev. inA. tauto.
- induction l2 as [|x2 l2 IH2]; intros acc; simpl.
* rewrite rev_append_rev. inA. tauto.
* case X.compare_spec; intro C.
+ rewrite IH1, !InA_cons, C; tauto.
+ rewrite (IH2 (x2::acc)), !InA_cons. tauto.
+ rewrite IH1, !InA_cons; tauto.
Qed.
Lemma linear_union_spec s1 s2 x :
InT x (linear_union s1 s2) <-> InT x s1 \/ InT x s2.
Proof.
unfold linear_union.
rewrite treeify_spec, union_list_spec, !rev_elements_rev.
rewrite !InA_rev, InA_nil, !elements_spec1 by auto_tc.
tauto.
Qed.
Lemma fold_add_spec s1 s2 x :
InT x (fold add s1 s2) <-> InT x s1 \/ InT x s2.
Proof.
rewrite fold_spec, <- fold_left_rev_right.
rewrite <- (elements_spec1 s1), <- InA_rev by auto_tc.
unfold elt in *.
induction (rev (elements s1)); simpl.
- rewrite InA_nil. tauto.
- unfold flip. rewrite add_spec', IHl, InA_cons. tauto.
Qed.
Lemma union_spec' s1 s2 x :
InT x (union s1 s2) <-> InT x s1 \/ InT x s2.
Proof.
unfold union. destruct compare_height.
- apply linear_union_spec.
- apply fold_add_spec.
- rewrite fold_add_spec. tauto.
Qed.
Lemma union_spec : forall s1 s2 y `{Ok s1, Ok s2},
(InT y (union s1 s2) <-> InT y s1 \/ InT y s2).
Proof.
intros; apply union_spec'.
Qed.
(** ** inter *)
Lemma inter_list_ok l1 l2 acc :
INV l1 l2 acc -> sort X.lt (inter_list l1 l2 acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1]; [|induction l2 as [|x2 l2 IH2]]; simpl.
- eauto.
- eauto.
- intros acc inv.
case X.compare_spec; intro C.
* apply IH1. eapply INV_eq; eauto.
* apply (IH2 acc). eapply INV_sym, INV_drop, INV_sym; eauto.
* apply IH1. eapply INV_drop; eauto.
Qed.
Instance linear_inter_ok s1 s2 `(Ok s1, Ok s2) :
Ok (linear_inter s1 s2).
Proof.
unfold linear_inter. now apply treeify_ok, inter_list_ok, INV_init.
Qed.
Instance inter_ok s1 s2 `(Ok s1, Ok s2) : Ok (inter s1 s2).
Proof.
unfold inter. destruct compare_height; auto_tc.
Qed.
Lemma inter_list_spec x l1 l2 acc :
sort X.lt (rev l1) ->
sort X.lt (rev l2) ->
(InA X.eq x (inter_list l1 l2 acc) <->
(InA X.eq x l1 /\ InA X.eq x l2) \/ InA X.eq x acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1].
- intros l2 acc; simpl. inA. tauto.
- induction l2 as [|x2 l2 IH2]; intros acc.
* simpl. inA. tauto.
* simpl. intros U V.
destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto.
destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto.
case X.compare_spec; intro C.
+ rewrite IH1, !InA_cons, C; tauto.
+ rewrite (IH2 acc); auto. inA. intuition; try order.
assert (X.lt x x1) by (apply U3; inA). order.
+ rewrite IH1; auto. inA. intuition; try order.
assert (X.lt x x2) by (apply V3; inA). order.
Qed.
Lemma linear_inter_spec s1 s2 x `(Ok s1, Ok s2) :
InT x (linear_inter s1 s2) <-> InT x s1 /\ InT x s2.
Proof.
unfold linear_inter.
rewrite !rev_elements_rev, treeify_spec, inter_list_spec
by (rewrite rev_involutive; auto_tc).
rewrite !InA_rev, InA_nil, !elements_spec1 by auto_tc. tauto.
Qed.
Local Instance mem_proper s `(Ok s) :
Proper (X.eq ==> Logic.eq) (fun k => mem k s).
Proof.
intros x y EQ. apply Bool.eq_iff_eq_true; rewrite !mem_spec; auto.
now rewrite EQ.
Qed.
Lemma inter_spec s1 s2 y `{Ok s1, Ok s2} :
InT y (inter s1 s2) <-> InT y s1 /\ InT y s2.
Proof.
unfold inter. destruct compare_height.
- now apply linear_inter_spec.
- rewrite filter_spec, mem_spec by auto_tc; tauto.
- rewrite filter_spec, mem_spec by auto_tc; tauto.
Qed.
(** ** difference *)
Lemma diff_list_ok l1 l2 acc :
INV l1 l2 acc -> sort X.lt (diff_list l1 l2 acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1];
[intro l2|induction l2 as [|x2 l2 IH2]];
intros acc inv.
- eauto.
- unfold diff_list. eapply INV_rev; eauto.
- simpl. case X.compare_spec; intro C.
* apply IH1. eapply INV_drop, INV_sym, INV_drop, INV_sym; eauto.
* apply (IH2 acc). eapply INV_sym, INV_drop, INV_sym; eauto.
* apply IH1. eapply INV_sym, INV_lt; eauto. now apply INV_sym.
Qed.
Instance diff_inter_ok s1 s2 `(Ok s1, Ok s2) :
Ok (linear_diff s1 s2).
Proof.
unfold linear_inter. now apply treeify_ok, diff_list_ok, INV_init.
Qed.
Instance fold_remove_ok s1 s2 `(Ok s2) :
Ok (fold remove s1 s2).
Proof.
rewrite fold_spec, <- fold_left_rev_right.
unfold elt in *.
induction (rev (elements s1)); simpl; unfold flip in *; auto_tc.
Qed.
Instance diff_ok s1 s2 `(Ok s1, Ok s2) : Ok (diff s1 s2).
Proof.
unfold diff. destruct compare_height; auto_tc.
Qed.
Lemma diff_list_spec x l1 l2 acc :
sort X.lt (rev l1) ->
sort X.lt (rev l2) ->
(InA X.eq x (diff_list l1 l2 acc) <->
(InA X.eq x l1 /\ ~InA X.eq x l2) \/ InA X.eq x acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1].
- intros l2 acc; simpl. inA. tauto.
- induction l2 as [|x2 l2 IH2]; intros acc.
* intros; simpl. rewrite rev_append_rev. inA. tauto.
* simpl. intros U V.
destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto.
destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto.
case X.compare_spec; intro C.
+ rewrite IH1; auto. f_equiv. inA. intuition; try order.
assert (X.lt x x1) by (apply U3; inA). order.
+ rewrite (IH2 acc); auto. f_equiv. inA. intuition; try order.
assert (X.lt x x1) by (apply U3; inA). order.
+ rewrite IH1; auto. inA. intuition; try order.
left; split; auto. destruct 1. order.
assert (X.lt x x2) by (apply V3; inA). order.
Qed.
Lemma linear_diff_spec s1 s2 x `(Ok s1, Ok s2) :
InT x (linear_diff s1 s2) <-> InT x s1 /\ ~InT x s2.
Proof.
unfold linear_diff.
rewrite !rev_elements_rev, treeify_spec, diff_list_spec
by (rewrite rev_involutive; auto_tc).
rewrite !InA_rev, InA_nil, !elements_spec1 by auto_tc. tauto.
Qed.
Lemma fold_remove_spec s1 s2 x `(Ok s2) :
InT x (fold remove s1 s2) <-> InT x s2 /\ ~InT x s1.
Proof.
rewrite fold_spec, <- fold_left_rev_right.
rewrite <- (elements_spec1 s1), <- InA_rev by auto_tc.
unfold elt in *.
induction (rev (elements s1)); simpl; intros.
- rewrite InA_nil. intuition.
- unfold flip in *. rewrite remove_spec, IHl, InA_cons. tauto.
clear IHl. induction l; simpl; auto_tc.
Qed.
Lemma diff_spec s1 s2 y `{Ok s1, Ok s2} :
InT y (diff s1 s2) <-> InT y s1 /\ ~InT y s2.
Proof.
unfold diff. destruct compare_height.
- now apply linear_diff_spec.
- rewrite filter_spec, Bool.negb_true_iff,
<- Bool.not_true_iff_false, mem_spec;
intuition.
intros x1 x2 EQ. f_equal. now apply mem_proper.
- now apply fold_remove_spec.
Qed.
End MakeRaw.
(** * Balancing properties
We now prove that all operations preserve a red-black invariant,
and that trees have hence a logarithmic depth.
*)
Module BalanceProps(X:Orders.OrderedType)(Import M : MakeRaw X).
Local Notation Rd := (Node Red).
Local Notation Bk := (Node Black).
Import M.MX.
(** ** Red-Black invariants *)
(** In a red-black tree :
- a red node has no red children
- the black depth at each node is the same along all paths.
The black depth is here an argument of the predicate. *)
Inductive rbt : nat -> tree -> Prop :=
| RB_Leaf : rbt 0 Leaf
| RB_Rd n l k r :
notred l -> notred r -> rbt n l -> rbt n r -> rbt n (Rd l k r)
| RB_Bk n l k r : rbt n l -> rbt n r -> rbt (S n) (Bk l k r).
(** A red-red tree is almost a red-black tree, except that it has
a _red_ root node which _may_ have red children. Note that a
red-red tree is hence non-empty, and all its strict subtrees
are red-black. *)
Inductive rrt (n:nat) : tree -> Prop :=
| RR_Rd l k r : rbt n l -> rbt n r -> rrt n (Rd l k r).
(** An almost-red-black tree is almost a red-black tree, except that
it's permitted to have two red nodes in a row at the very root (only).
We implement this notion by saying that a quasi-red-black tree
is either a red-black tree or a red-red tree. *)
Inductive arbt (n:nat)(t:tree) : Prop :=
| ARB_RB : rbt n t -> arbt n t
| ARB_RR : rrt n t -> arbt n t.
(** The main exported invariant : being a red-black tree for some
black depth. *)
Class Rbt (t:tree) := RBT : exists d, rbt d t.
(** ** Basic tactics and results about red-black *)
Scheme rbt_ind := Induction for rbt Sort Prop.
Local Hint Constructors rbt rrt arbt.
Local Hint Extern 0 (notred _) => (exact I).
Ltac invrb := intros; invtree rrt; invtree rbt; try contradiction.
Ltac desarb := match goal with H:arbt _ _ |- _ => destruct H end.
Ltac nonzero n := destruct n as [|n]; [try split; invrb|].
Lemma rr_nrr_rb n t :
rrt n t -> notredred t -> rbt n t.
Proof.
destruct 1 as [l x r Hl Hr].
destruct l, r; descolor; invrb; auto.
Qed.
Local Hint Resolve rr_nrr_rb.
Lemma arb_nrr_rb n t :
arbt n t -> notredred t -> rbt n t.
Proof.
destruct 1; auto.
Qed.
Lemma arb_nr_rb n t :
arbt n t -> notred t -> rbt n t.
Proof.
destruct 1; destruct t; descolor; invrb; auto.
Qed.
Local Hint Resolve arb_nrr_rb arb_nr_rb.
(** ** A Red-Black tree has indeed a logarithmic depth *)
Definition redcarac s := rcase (fun _ _ _ => 1) (fun _ => 0) s.
Lemma rb_maxdepth s n : rbt n s -> maxdepth s <= 2*n + redcarac s.
Proof.
induction 1.
- simpl; auto.
- replace (redcarac l) with 0 in * by now destree l.
replace (redcarac r) with 0 in * by now destree r.
simpl maxdepth. simpl redcarac.
rewrite Nat.add_succ_r, <- Nat.succ_le_mono.
now apply Nat.max_lub.
- simpl. rewrite <- Nat.succ_le_mono.
apply Nat.max_lub; eapply Nat.le_trans; eauto;
[destree l | destree r]; simpl;
rewrite !Nat.add_0_r, ?Nat.add_1_r; auto with arith.
Qed.
Lemma rb_mindepth s n : rbt n s -> n + redcarac s <= mindepth s.
Proof.
induction 1; simpl.
- trivial.
- rewrite Nat.add_succ_r.
apply -> Nat.succ_le_mono.
replace (redcarac l) with 0 in * by now destree l.
replace (redcarac r) with 0 in * by now destree r.
now apply Nat.min_glb.
- apply -> Nat.succ_le_mono. rewrite Nat.add_0_r.
apply Nat.min_glb; eauto with arith.
Qed.
Lemma maxdepth_upperbound s : Rbt s ->
maxdepth s <= 2 * Nat.log2 (S (cardinal s)).
Proof.
intros (n,H).
eapply Nat.le_trans; [eapply rb_maxdepth; eauto|].
transitivity (2*(n+redcarac s)).
- rewrite Nat.mul_add_distr_l. apply Nat.add_le_mono_l.
rewrite <- Nat.mul_1_l at 1. apply Nat.mul_le_mono_r.
auto with arith.
- apply Nat.mul_le_mono_l.
transitivity (mindepth s).
+ now apply rb_mindepth.
+ apply mindepth_log_cardinal.
Qed.
Lemma maxdepth_lowerbound s : s<>Leaf ->
Nat.log2 (cardinal s) < maxdepth s.
Proof.
apply maxdepth_log_cardinal.
Qed.
(** ** Singleton *)
Lemma singleton_rb x : Rbt (singleton x).
Proof.
unfold singleton. exists 1; auto.
Qed.
(** ** [makeBlack] and [makeRed] *)
Lemma makeBlack_rb n t : arbt n t -> Rbt (makeBlack t).
Proof.
destruct t as [|[|] l x r].
- exists 0; auto.
- destruct 1; invrb; exists (S n); simpl; auto.
- exists n; auto.
Qed.
Lemma makeRed_rr t n :
rbt (S n) t -> notred t -> rrt n (makeRed t).
Proof.
destruct t as [|[|] l x r]; invrb; simpl; auto.
Qed.
(** ** Balancing *)
Lemma lbal_rb n l k r :
arbt n l -> rbt n r -> rbt (S n) (lbal l k r).
Proof.
case lbal_match; intros; desarb; invrb; auto.
Qed.
Lemma rbal_rb n l k r :
rbt n l -> arbt n r -> rbt (S n) (rbal l k r).
Proof.
case rbal_match; intros; desarb; invrb; auto.
Qed.
Lemma rbal'_rb n l k r :
rbt n l -> arbt n r -> rbt (S n) (rbal' l k r).
Proof.
case rbal'_match; intros; desarb; invrb; auto.
Qed.
Lemma lbalS_rb n l x r :
arbt n l -> rbt (S n) r -> notred r -> rbt (S n) (lbalS l x r).
Proof.
intros Hl Hr Hr'.
destruct r as [|[|] rl rx rr]; invrb. clear Hr'.
revert Hl.
case lbalS_match.
- destruct 1; invrb; auto.
- intros. apply rbal'_rb; auto.
Qed.
Lemma lbalS_arb n l x r :
arbt n l -> rbt (S n) r -> arbt (S n) (lbalS l x r).
Proof.
case lbalS_match.
- destruct 1; invrb; auto.
- clear l. intros l Hl Hl' Hr.
destruct r as [|[|] rl rx rr]; invrb.
* destruct rl as [|[|] rll rlx rlr]; invrb.
right; auto using rbal'_rb, makeRed_rr.
* left; apply rbal'_rb; auto.
Qed.
Lemma rbalS_rb n l x r :
rbt (S n) l -> notred l -> arbt n r -> rbt (S n) (rbalS l x r).
Proof.
intros Hl Hl' Hr.
destruct l as [|[|] ll lx lr]; invrb. clear Hl'.
revert Hr.
case rbalS_match.
- destruct 1; invrb; auto.
- intros. apply lbal_rb; auto.
Qed.
Lemma rbalS_arb n l x r :
rbt (S n) l -> arbt n r -> arbt (S n) (rbalS l x r).
Proof.
case rbalS_match.
- destruct 2; invrb; auto.
- clear r. intros r Hr Hr' Hl.
destruct l as [|[|] ll lx lr]; invrb.
* destruct lr as [|[|] lrl lrx lrr]; invrb.
right; auto using lbal_rb, makeRed_rr.
* left; apply lbal_rb; auto.
Qed.
(** ** Insertion *)
(** The next lemmas combine simultaneous results about rbt and arbt.
A first solution here: statement with [if ... then ... else] *)
Definition ifred s (A B:Prop) := rcase (fun _ _ _ => A) (fun _ => B) s.
Lemma ifred_notred s A B : notred s -> (ifred s A B <-> B).
Proof.
destruct s; descolor; simpl; intuition.
Qed.
Lemma ifred_or s A B : ifred s A B -> A\/B.
Proof.
destruct s; descolor; simpl; intuition.
Qed.
Lemma ins_rr_rb x s n : rbt n s ->
ifred s (rrt n (ins x s)) (rbt n (ins x s)).
Proof.
induction 1 as [ | n l k r | n l k r Hl IHl Hr IHr ].
- simpl; auto.
- simpl. rewrite ifred_notred in * by trivial.
elim_compare x k; auto.
- rewrite ifred_notred by trivial.
unfold ins; fold ins. (* simpl is too much here ... *)
elim_compare x k.
* auto.
* apply lbal_rb; trivial. apply ifred_or in IHl; intuition.
* apply rbal_rb; trivial. apply ifred_or in IHr; intuition.
Qed.
Lemma ins_arb x s n : rbt n s -> arbt n (ins x s).
Proof.
intros H. apply (ins_rr_rb x), ifred_or in H. intuition.
Qed.
Instance add_rb x s : Rbt s -> Rbt (add x s).
Proof.
intros (n,H). unfold add. now apply (makeBlack_rb n), ins_arb.
Qed.
(** ** Deletion *)
(** A second approach here: statement with ... /\ ... *)
Lemma append_arb_rb n l r : rbt n l -> rbt n r ->
(arbt n (append l r)) /\
(notred l -> notred r -> rbt n (append l r)).
Proof.
revert r n.
append_tac l r.
- split; auto.
- split; auto.
- (* Red / Red *)
intros n. invrb.
case (IHlr n); auto; clear IHlr.
case append_rr_match.
+ intros a x b _ H; split; invrb.
assert (rbt n (Rd a x b)) by auto. invrb. auto.
+ split; invrb; auto.
- (* Red / Black *)
split; invrb. destruct (IHlr n) as (_,IH); auto.
- (* Black / Red *)
split; invrb. destruct (IHrl n) as (_,IH); auto.
- (* Black / Black *)
nonzero n.
invrb.
destruct (IHlr n) as (IH,_); auto; clear IHlr.
revert IH.
case append_bb_match.
+ intros a x b IH; split; destruct IH; invrb; auto.
+ split; [left | invrb]; auto using lbalS_rb.
Qed.
(** A third approach : Lemma ... with ... *)
Lemma del_arb s x n : rbt (S n) s -> isblack s -> arbt n (del x s)
with del_rb s x n : rbt n s -> notblack s -> rbt n (del x s).
Proof.
{ revert n.
induct s x; try destruct c; try contradiction; invrb.
- apply append_arb_rb; assumption.
- assert (IHl' := del_rb l x). clear IHr del_arb del_rb.
destruct l as [|[|] ll lx lr]; auto.
nonzero n. apply lbalS_arb; auto.
- assert (IHr' := del_rb r x). clear IHl del_arb del_rb.
destruct r as [|[|] rl rx rr]; auto.
nonzero n. apply rbalS_arb; auto. }
{ revert n.
induct s x; try assumption; try destruct c; try contradiction; invrb.
- apply append_arb_rb; assumption.
- assert (IHl' := del_arb l x). clear IHr del_arb del_rb.
destruct l as [|[|] ll lx lr]; auto.
nonzero n. destruct n as [|n]; [invrb|]; apply lbalS_rb; auto.
- assert (IHr' := del_arb r x). clear IHl del_arb del_rb.
destruct r as [|[|] rl rx rr]; auto.
nonzero n. apply rbalS_rb; auto. }
Qed.
Instance remove_rb s x : Rbt s -> Rbt (remove x s).
Proof.
intros (n,H). unfold remove.
destruct s as [|[|] l y r].
- apply (makeBlack_rb n). auto.
- apply (makeBlack_rb n). left. apply del_rb; simpl; auto.
- nonzero n. apply (makeBlack_rb n). apply del_arb; simpl; auto.
Qed.
(** ** Treeify *)
Definition treeify_rb_invariant size depth (f:treeify_t) :=
forall acc,
size <= length acc ->
rbt depth (fst (f acc)) /\
size + length (snd (f acc)) = length acc.
Lemma treeify_zero_rb : treeify_rb_invariant 0 0 treeify_zero.
Proof.
intros acc _; simpl; auto.
Qed.
Lemma treeify_one_rb : treeify_rb_invariant 1 0 treeify_one.
Proof.
intros [|x acc]; simpl; auto; inversion 1.
Qed.
Lemma treeify_cont_rb f g size1 size2 size d :
treeify_rb_invariant size1 d f ->
treeify_rb_invariant size2 d g ->
size = S (size1 + size2) ->
treeify_rb_invariant size (S d) (treeify_cont f g).
Proof.
intros Hf Hg H acc Hacc.
unfold treeify_cont.
specialize (Hf acc).
destruct (f acc) as (l, acc1). simpl in *.
destruct Hf as (Hf1, Hf2). { subst. eauto with arith. }
destruct acc1 as [|x acc2]; simpl in *.
- exfalso. revert Hacc. apply Nat.lt_nge. rewrite H, <- Hf2.
auto with arith.
- specialize (Hg acc2).
destruct (g acc2) as (r, acc3). simpl in *.
destruct Hg as (Hg1, Hg2).
{ revert Hacc.
rewrite H, <- Hf2, Nat.add_succ_r, <- Nat.succ_le_mono.
apply Nat.add_le_mono_l. }
split; auto.
now rewrite H, <- Hf2, <- Hg2, Nat.add_succ_r, Nat.add_assoc.
Qed.
Lemma treeify_aux_rb n :
exists d, forall (b:bool),
treeify_rb_invariant (ifpred b (Pos.to_nat n)) d (treeify_aux b n).
Proof.
induction n as [n (d,IHn)|n (d,IHn)| ].
- exists (S d). intros b.
eapply treeify_cont_rb; [ apply (IHn false) | apply (IHn b) | ].
rewrite Pos2Nat.inj_xI.
assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H.
destruct b; simpl; intros; rewrite Nat.add_0_r; trivial.
now rewrite <- Nat.add_succ_r, Nat.succ_pred; trivial.
- exists (S d). intros b.
eapply treeify_cont_rb; [ apply (IHn b) | apply (IHn true) | ].
rewrite Pos2Nat.inj_xO.
assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H.
rewrite <- Nat.add_succ_r, Nat.succ_pred by trivial.
destruct b; simpl; intros; rewrite Nat.add_0_r; trivial.
symmetry. now apply Nat.add_pred_l.
- exists 0; destruct b;
[ apply treeify_zero_rb | apply treeify_one_rb ].
Qed.
(** The black depth of [treeify l] is actually a log2, but
we don't need to mention that. *)
Instance treeify_rb l : Rbt (treeify l).
Proof.
unfold treeify.
destruct (treeify_aux_rb (plength l)) as (d,H).
exists d.
apply H.
now rewrite plength_spec.
Qed.
(** ** Filtering *)
Instance filter_rb f s : Rbt (filter f s).
Proof.
unfold filter; auto_tc.
Qed.
Instance partition_rb1 f s : Rbt (fst (partition f s)).
Proof.
unfold partition. destruct partition_aux. simpl. auto_tc.
Qed.
Instance partition_rb2 f s : Rbt (snd (partition f s)).
Proof.
unfold partition. destruct partition_aux. simpl. auto_tc.
Qed.
(** ** Union, intersection, difference *)
Instance fold_add_rb s1 s2 : Rbt s2 -> Rbt (fold add s1 s2).
Proof.
intros. rewrite fold_spec, <- fold_left_rev_right. unfold elt in *.
induction (rev (elements s1)); simpl; unfold flip in *; auto_tc.
Qed.
Instance fold_remove_rb s1 s2 : Rbt s2 -> Rbt (fold remove s1 s2).
Proof.
intros. rewrite fold_spec, <- fold_left_rev_right. unfold elt in *.
induction (rev (elements s1)); simpl; unfold flip in *; auto_tc.
Qed.
Lemma union_rb s1 s2 : Rbt s1 -> Rbt s2 -> Rbt (union s1 s2).
Proof.
intros. unfold union, linear_union. destruct compare_height; auto_tc.
Qed.
Lemma inter_rb s1 s2 : Rbt s1 -> Rbt s2 -> Rbt (inter s1 s2).
Proof.
intros. unfold inter, linear_inter. destruct compare_height; auto_tc.
Qed.
Lemma diff_rb s1 s2 : Rbt s1 -> Rbt s2 -> Rbt (diff s1 s2).
Proof.
intros. unfold diff, linear_diff. destruct compare_height; auto_tc.
Qed.
End BalanceProps.
(** * Final Encapsulation
Now, in order to really provide a functor implementing [S], we
need to encapsulate everything into a type of binary search trees.
They also happen to be well-balanced, but this has no influence
on the correctness of operations, so we won't state this here,
see [BalanceProps] if you need more than just the MSet interface.
*)
Module Type MSetInterface_S_Ext := MSetInterface.S <+ MSetRemoveMin.
Module Make (X: Orders.OrderedType) <:
MSetInterface_S_Ext with Module E := X.
Module Raw. Include MakeRaw X. End Raw.
Include MSetInterface.Raw2Sets X Raw.
Definition opt_ok (x:option (elt * Raw.t)) :=
match x with Some (_,s) => Raw.Ok s | None => True end.
Definition mk_opt_t (x: option (elt * Raw.t))(P: opt_ok x) :
option (elt * t) :=
match x as o return opt_ok o -> option (elt * t) with
| Some (k,s') => fun P : Raw.Ok s' => Some (k, Mkt s')
| None => fun _ => None
end P.
Definition remove_min s : option (elt * t) :=
mk_opt_t (Raw.remove_min (this s)) (Raw.remove_min_ok s).
Lemma remove_min_spec1 s x s' :
remove_min s = Some (x,s') ->
min_elt s = Some x /\ Equal (remove x s) s'.
Proof.
destruct s as (s,Hs).
unfold remove_min, mk_opt_t, min_elt, remove, Equal, In; simpl.
generalize (fun x s' => @Raw.remove_min_spec1 s x s' Hs).
set (P := Raw.remove_min_ok s). clearbody P.
destruct (Raw.remove_min s) as [(x0,s0)|]; try easy.
intros H U. injection U as -> <-. simpl.
destruct (H x s0); auto. subst; intuition.
Qed.
Lemma remove_min_spec2 s : remove_min s = None -> Empty s.
Proof.
destruct s as (s,Hs).
unfold remove_min, mk_opt_t, Empty, In; simpl.
generalize (Raw.remove_min_spec2 s).
set (P := Raw.remove_min_ok s). clearbody P.
destruct (Raw.remove_min s) as [(x0,s0)|]; now intuition.
Qed.
End Make.
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_dbg.v
//
// *Module Description:
// Debug interface
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_dbg (
// OUTPUTs
dbg_cpu_reset, // Reset CPU from debug interface
dbg_freeze, // Freeze peripherals
dbg_halt_cmd, // Halt CPU command
dbg_i2c_sda_out, // Debug interface: I2C SDA OUT
dbg_mem_addr, // Debug address for rd/wr access
dbg_mem_dout, // Debug unit data output
dbg_mem_en, // Debug unit memory enable
dbg_mem_wr, // Debug unit memory write
dbg_reg_wr, // Debug unit CPU register write
dbg_uart_txd, // Debug interface: UART TXD
// INPUTs
cpu_en_s, // Enable CPU code execution (synchronous)
cpu_id, // CPU ID
cpu_nr_inst, // Current oMSP instance number
cpu_nr_total, // Total number of oMSP instances-1
dbg_clk, // Debug unit clock
dbg_en_s, // Debug interface enable (synchronous)
dbg_halt_st, // Halt/Run status from CPU
dbg_i2c_addr, // Debug interface: I2C Address
dbg_i2c_broadcast, // Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl, // Debug interface: I2C SCL
dbg_i2c_sda_in, // Debug interface: I2C SDA IN
dbg_mem_din, // Debug unit Memory data input
dbg_reg_din, // Debug unit CPU register data input
dbg_rst, // Debug unit reset
dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
decode_noirq, // Frontend decode instruction
eu_mab, // Execution-Unit Memory address bus
eu_mb_en, // Execution-Unit Memory bus enable
eu_mb_wr, // Execution-Unit Memory bus write transfer
fe_mdb_in, // Frontend Memory data bus input
pc, // Program counter
puc_pnd_set // PUC pending set for the serial debug interface
);
// OUTPUTs
//=========
output dbg_cpu_reset; // Reset CPU from debug interface
output dbg_freeze; // Freeze peripherals
output dbg_halt_cmd; // Halt CPU command
output dbg_i2c_sda_out; // Debug interface: I2C SDA OUT
output [15:0] dbg_mem_addr; // Debug address for rd/wr access
output [15:0] dbg_mem_dout; // Debug unit data output
output dbg_mem_en; // Debug unit memory enable
output [1:0] dbg_mem_wr; // Debug unit memory write
output dbg_reg_wr; // Debug unit CPU register write
output dbg_uart_txd; // Debug interface: UART TXD
// INPUTs
//=========
input cpu_en_s; // Enable CPU code execution (synchronous)
input [31:0] cpu_id; // CPU ID
input [7:0] cpu_nr_inst; // Current oMSP instance number
input [7:0] cpu_nr_total; // Total number of oMSP instances-1
input dbg_clk; // Debug unit clock
input dbg_en_s; // Debug interface enable (synchronous)
input dbg_halt_st; // Halt/Run status from CPU
input [6:0] dbg_i2c_addr; // Debug interface: I2C Address
input [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
input dbg_i2c_scl; // Debug interface: I2C SCL
input dbg_i2c_sda_in; // Debug interface: I2C SDA IN
input [15:0] dbg_mem_din; // Debug unit Memory data input
input [15:0] dbg_reg_din; // Debug unit CPU register data input
input dbg_rst; // Debug unit reset
input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
input decode_noirq; // Frontend decode instruction
input [15:0] eu_mab; // Execution-Unit Memory address bus
input eu_mb_en; // Execution-Unit Memory bus enable
input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
input [15:0] fe_mdb_in; // Frontend Memory data bus input
input [15:0] pc; // Program counter
input puc_pnd_set; // PUC pending set for the serial debug interface
//=============================================================================
// 1) WIRE & PARAMETER DECLARATION
//=============================================================================
// Diverse wires and registers
wire [5:0] dbg_addr;
wire [15:0] dbg_din;
wire dbg_wr;
reg mem_burst;
wire dbg_reg_rd;
wire dbg_mem_rd;
reg dbg_mem_rd_dly;
wire dbg_swbrk;
wire dbg_rd;
reg dbg_rd_rdy;
wire mem_burst_rd;
wire mem_burst_wr;
wire brk0_halt;
wire brk0_pnd;
wire [15:0] brk0_dout;
wire brk1_halt;
wire brk1_pnd;
wire [15:0] brk1_dout;
wire brk2_halt;
wire brk2_pnd;
wire [15:0] brk2_dout;
wire brk3_halt;
wire brk3_pnd;
wire [15:0] brk3_dout;
// Number of registers
parameter NR_REG = 25;
// Register addresses
parameter CPU_ID_LO = 6'h00;
parameter CPU_ID_HI = 6'h01;
parameter CPU_CTL = 6'h02;
parameter CPU_STAT = 6'h03;
parameter MEM_CTL = 6'h04;
parameter MEM_ADDR = 6'h05;
parameter MEM_DATA = 6'h06;
parameter MEM_CNT = 6'h07;
`ifdef DBG_HWBRK_0
parameter BRK0_CTL = 6'h08;
parameter BRK0_STAT = 6'h09;
parameter BRK0_ADDR0 = 6'h0A;
parameter BRK0_ADDR1 = 6'h0B;
`endif
`ifdef DBG_HWBRK_1
parameter BRK1_CTL = 6'h0C;
parameter BRK1_STAT = 6'h0D;
parameter BRK1_ADDR0 = 6'h0E;
parameter BRK1_ADDR1 = 6'h0F;
`endif
`ifdef DBG_HWBRK_2
parameter BRK2_CTL = 6'h10;
parameter BRK2_STAT = 6'h11;
parameter BRK2_ADDR0 = 6'h12;
parameter BRK2_ADDR1 = 6'h13;
`endif
`ifdef DBG_HWBRK_3
parameter BRK3_CTL = 6'h14;
parameter BRK3_STAT = 6'h15;
parameter BRK3_ADDR0 = 6'h16;
parameter BRK3_ADDR1 = 6'h17;
`endif
parameter CPU_NR = 6'h18;
// Register one-hot decoder
parameter BASE_D = {{NR_REG-1{1'b0}}, 1'b1};
parameter CPU_ID_LO_D = (BASE_D << CPU_ID_LO);
parameter CPU_ID_HI_D = (BASE_D << CPU_ID_HI);
parameter CPU_CTL_D = (BASE_D << CPU_CTL);
parameter CPU_STAT_D = (BASE_D << CPU_STAT);
parameter MEM_CTL_D = (BASE_D << MEM_CTL);
parameter MEM_ADDR_D = (BASE_D << MEM_ADDR);
parameter MEM_DATA_D = (BASE_D << MEM_DATA);
parameter MEM_CNT_D = (BASE_D << MEM_CNT);
`ifdef DBG_HWBRK_0
parameter BRK0_CTL_D = (BASE_D << BRK0_CTL);
parameter BRK0_STAT_D = (BASE_D << BRK0_STAT);
parameter BRK0_ADDR0_D = (BASE_D << BRK0_ADDR0);
parameter BRK0_ADDR1_D = (BASE_D << BRK0_ADDR1);
`endif
`ifdef DBG_HWBRK_1
parameter BRK1_CTL_D = (BASE_D << BRK1_CTL);
parameter BRK1_STAT_D = (BASE_D << BRK1_STAT);
parameter BRK1_ADDR0_D = (BASE_D << BRK1_ADDR0);
parameter BRK1_ADDR1_D = (BASE_D << BRK1_ADDR1);
`endif
`ifdef DBG_HWBRK_2
parameter BRK2_CTL_D = (BASE_D << BRK2_CTL);
parameter BRK2_STAT_D = (BASE_D << BRK2_STAT);
parameter BRK2_ADDR0_D = (BASE_D << BRK2_ADDR0);
parameter BRK2_ADDR1_D = (BASE_D << BRK2_ADDR1);
`endif
`ifdef DBG_HWBRK_3
parameter BRK3_CTL_D = (BASE_D << BRK3_CTL);
parameter BRK3_STAT_D = (BASE_D << BRK3_STAT);
parameter BRK3_ADDR0_D = (BASE_D << BRK3_ADDR0);
parameter BRK3_ADDR1_D = (BASE_D << BRK3_ADDR1);
`endif
parameter CPU_NR_D = (BASE_D << CPU_NR);
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Select Data register during a burst
wire [5:0] dbg_addr_in = mem_burst ? MEM_DATA : dbg_addr;
// Register address decode
reg [NR_REG-1:0] reg_dec;
always @(dbg_addr_in)
case (dbg_addr_in)
CPU_ID_LO : reg_dec = CPU_ID_LO_D;
CPU_ID_HI : reg_dec = CPU_ID_HI_D;
CPU_CTL : reg_dec = CPU_CTL_D;
CPU_STAT : reg_dec = CPU_STAT_D;
MEM_CTL : reg_dec = MEM_CTL_D;
MEM_ADDR : reg_dec = MEM_ADDR_D;
MEM_DATA : reg_dec = MEM_DATA_D;
MEM_CNT : reg_dec = MEM_CNT_D;
`ifdef DBG_HWBRK_0
BRK0_CTL : reg_dec = BRK0_CTL_D;
BRK0_STAT : reg_dec = BRK0_STAT_D;
BRK0_ADDR0: reg_dec = BRK0_ADDR0_D;
BRK0_ADDR1: reg_dec = BRK0_ADDR1_D;
`endif
`ifdef DBG_HWBRK_1
BRK1_CTL : reg_dec = BRK1_CTL_D;
BRK1_STAT : reg_dec = BRK1_STAT_D;
BRK1_ADDR0: reg_dec = BRK1_ADDR0_D;
BRK1_ADDR1: reg_dec = BRK1_ADDR1_D;
`endif
`ifdef DBG_HWBRK_2
BRK2_CTL : reg_dec = BRK2_CTL_D;
BRK2_STAT : reg_dec = BRK2_STAT_D;
BRK2_ADDR0: reg_dec = BRK2_ADDR0_D;
BRK2_ADDR1: reg_dec = BRK2_ADDR1_D;
`endif
`ifdef DBG_HWBRK_3
BRK3_CTL : reg_dec = BRK3_CTL_D;
BRK3_STAT : reg_dec = BRK3_STAT_D;
BRK3_ADDR0: reg_dec = BRK3_ADDR0_D;
BRK3_ADDR1: reg_dec = BRK3_ADDR1_D;
`endif
CPU_NR : reg_dec = CPU_NR_D;
// pragma coverage off
default: reg_dec = {NR_REG{1'b0}};
// pragma coverage on
endcase
// Read/Write probes
wire reg_write = dbg_wr;
wire reg_read = 1'b1;
// Read/Write vectors
wire [NR_REG-1:0] reg_wr = reg_dec & {NR_REG{reg_write}};
wire [NR_REG-1:0] reg_rd = reg_dec & {NR_REG{reg_read}};
//=============================================================================
// 3) REGISTER: CORE INTERFACE
//=============================================================================
// CPU_ID Register
//-----------------
// -------------------------------------------------------------------
// CPU_ID_LO: | 15 14 13 12 11 10 9 | 8 7 6 5 4 | 3 | 2 1 0 |
// |----------------------------+-----------------+------+-------------|
// | PER_SPACE | USER_VERSION | ASIC | CPU_VERSION |
// --------------------------------------------------------------------
// CPU_ID_HI: | 15 14 13 12 11 10 | 9 8 7 6 5 4 3 2 1 | 0 |
// |----------------------------+-------------------------------+------|
// | PMEM_SIZE | DMEM_SIZE | MPY |
// -------------------------------------------------------------------
// This register is assigned in the SFR module
// CPU_NR Register
//-----------------
// -------------------------------------------------------------------
// | 15 14 13 12 11 10 9 8 | 7 6 5 4 3 2 1 0 |
// |---------------------------------+---------------------------------|
// | CPU_TOTAL_NR | CPU_INST_NR |
// -------------------------------------------------------------------
wire [15:0] cpu_nr = {cpu_nr_total, cpu_nr_inst};
// CPU_CTL Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved CPU_RST RST_BRK_EN FRZ_BRK_EN SW_BRK_EN ISTEP RUN HALT
//-----------------------------------------------------------------------------
reg [6:3] cpu_ctl;
wire cpu_ctl_wr = reg_wr[CPU_CTL];
always @ (posedge dbg_clk or posedge dbg_rst)
`ifdef DBG_RST_BRK_EN
if (dbg_rst) cpu_ctl <= 4'h6;
`else
if (dbg_rst) cpu_ctl <= 4'h2;
`endif
else if (cpu_ctl_wr) cpu_ctl <= dbg_din[6:3];
wire [7:0] cpu_ctl_full = {1'b0, cpu_ctl, 3'b000};
wire halt_cpu = cpu_ctl_wr & dbg_din[`HALT] & ~dbg_halt_st;
wire run_cpu = cpu_ctl_wr & dbg_din[`RUN] & dbg_halt_st;
wire istep = cpu_ctl_wr & dbg_din[`ISTEP] & dbg_halt_st;
// CPU_STAT Register
//------------------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// HWBRK3_PND HWBRK2_PND HWBRK1_PND HWBRK0_PND SWBRK_PND PUC_PND Res. HALT_RUN
//------------------------------------------------------------------------------------
reg [3:2] cpu_stat;
wire cpu_stat_wr = reg_wr[CPU_STAT];
wire [3:2] cpu_stat_set = {dbg_swbrk, puc_pnd_set};
wire [3:2] cpu_stat_clr = ~dbg_din[3:2];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) cpu_stat <= 2'b00;
else if (cpu_stat_wr) cpu_stat <= ((cpu_stat & cpu_stat_clr) | cpu_stat_set);
else cpu_stat <= (cpu_stat | cpu_stat_set);
wire [7:0] cpu_stat_full = {brk3_pnd, brk2_pnd, brk1_pnd, brk0_pnd,
cpu_stat, 1'b0, dbg_halt_st};
//=============================================================================
// 4) REGISTER: MEMORY INTERFACE
//=============================================================================
// MEM_CTL Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved B/W MEM/REG RD/WR START
//
// START : - 0 : Do nothing.
// - 1 : Initiate memory transfer.
//
// RD/WR : - 0 : Read access.
// - 1 : Write access.
//
// MEM/REG: - 0 : Memory access.
// - 1 : CPU Register access.
//
// B/W : - 0 : 16 bit access.
// - 1 : 8 bit access (not valid for CPU Registers).
//
//-----------------------------------------------------------------------------
reg [3:1] mem_ctl;
wire mem_ctl_wr = reg_wr[MEM_CTL];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_ctl <= 3'h0;
else if (mem_ctl_wr) mem_ctl <= dbg_din[3:1];
wire [7:0] mem_ctl_full = {4'b0000, mem_ctl, 1'b0};
reg mem_start;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_start <= 1'b0;
else mem_start <= mem_ctl_wr & dbg_din[0];
wire mem_bw = mem_ctl[3];
// MEM_DATA Register
//------------------
reg [15:0] mem_data;
reg [15:0] mem_addr;
wire mem_access;
wire mem_data_wr = reg_wr[MEM_DATA];
wire [15:0] dbg_mem_din_bw = ~mem_bw ? dbg_mem_din :
mem_addr[0] ? {8'h00, dbg_mem_din[15:8]} :
{8'h00, dbg_mem_din[7:0]};
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_data <= 16'h0000;
else if (mem_data_wr) mem_data <= dbg_din;
else if (dbg_reg_rd) mem_data <= dbg_reg_din;
else if (dbg_mem_rd_dly) mem_data <= dbg_mem_din_bw;
// MEM_ADDR Register
//------------------
reg [15:0] mem_cnt;
wire mem_addr_wr = reg_wr[MEM_ADDR];
wire dbg_mem_acc = (|dbg_mem_wr | (dbg_rd_rdy & ~mem_ctl[2]));
wire dbg_reg_acc = ( dbg_reg_wr | (dbg_rd_rdy & mem_ctl[2]));
wire [15:0] mem_addr_inc = (mem_cnt==16'h0000) ? 16'h0000 :
(mem_burst & dbg_mem_acc & ~mem_bw) ? 16'h0002 :
(mem_burst & (dbg_mem_acc | dbg_reg_acc)) ? 16'h0001 : 16'h0000;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_addr <= 16'h0000;
else if (mem_addr_wr) mem_addr <= dbg_din;
else mem_addr <= mem_addr + mem_addr_inc;
// MEM_CNT Register
//------------------
wire mem_cnt_wr = reg_wr[MEM_CNT];
wire [15:0] mem_cnt_dec = (mem_cnt==16'h0000) ? 16'h0000 :
(mem_burst & (dbg_mem_acc | dbg_reg_acc)) ? 16'hffff : 16'h0000;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_cnt <= 16'h0000;
else if (mem_cnt_wr) mem_cnt <= dbg_din;
else mem_cnt <= mem_cnt + mem_cnt_dec;
//=============================================================================
// 5) BREAKPOINTS / WATCHPOINTS
//=============================================================================
`ifdef DBG_HWBRK_0
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk0_reg_rd = {reg_rd[BRK0_ADDR1],
reg_rd[BRK0_ADDR0],
reg_rd[BRK0_STAT],
reg_rd[BRK0_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk0_reg_wr = {reg_wr[BRK0_ADDR1],
reg_wr[BRK0_ADDR0],
reg_wr[BRK0_STAT],
reg_wr[BRK0_CTL]};
omsp_dbg_hwbrk dbg_hwbr_0 (
// OUTPUTs
.brk_halt (brk0_halt), // Hardware breakpoint command
.brk_pnd (brk0_pnd), // Hardware break/watch-point pending
.brk_dout (brk0_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk0_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk0_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.decode_noirq (decode_noirq), // Frontend decode instruction
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.pc (pc) // Program counter
);
`else
assign brk0_halt = 1'b0;
assign brk0_pnd = 1'b0;
assign brk0_dout = 16'h0000;
wire [15:0] UNUSED_eu_mab = eu_mab;
wire UNUSED_eu_mb_en = eu_mb_en;
wire [1:0] UNUSED_eu_mb_wr = eu_mb_wr;
wire [15:0] UNUSED_pc = pc;
`endif
`ifdef DBG_HWBRK_1
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk1_reg_rd = {reg_rd[BRK1_ADDR1],
reg_rd[BRK1_ADDR0],
reg_rd[BRK1_STAT],
reg_rd[BRK1_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk1_reg_wr = {reg_wr[BRK1_ADDR1],
reg_wr[BRK1_ADDR0],
reg_wr[BRK1_STAT],
reg_wr[BRK1_CTL]};
omsp_dbg_hwbrk dbg_hwbr_1 (
// OUTPUTs
.brk_halt (brk1_halt), // Hardware breakpoint command
.brk_pnd (brk1_pnd), // Hardware break/watch-point pending
.brk_dout (brk1_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk1_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk1_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.decode_noirq (decode_noirq), // Frontend decode instruction
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.pc (pc) // Program counter
);
`else
assign brk1_halt = 1'b0;
assign brk1_pnd = 1'b0;
assign brk1_dout = 16'h0000;
`endif
`ifdef DBG_HWBRK_2
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk2_reg_rd = {reg_rd[BRK2_ADDR1],
reg_rd[BRK2_ADDR0],
reg_rd[BRK2_STAT],
reg_rd[BRK2_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk2_reg_wr = {reg_wr[BRK2_ADDR1],
reg_wr[BRK2_ADDR0],
reg_wr[BRK2_STAT],
reg_wr[BRK2_CTL]};
omsp_dbg_hwbrk dbg_hwbr_2 (
// OUTPUTs
.brk_halt (brk2_halt), // Hardware breakpoint command
.brk_pnd (brk2_pnd), // Hardware break/watch-point pending
.brk_dout (brk2_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk2_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk2_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.decode_noirq (decode_noirq), // Frontend decode instruction
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.pc (pc) // Program counter
);
`else
assign brk2_halt = 1'b0;
assign brk2_pnd = 1'b0;
assign brk2_dout = 16'h0000;
`endif
`ifdef DBG_HWBRK_3
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk3_reg_rd = {reg_rd[BRK3_ADDR1],
reg_rd[BRK3_ADDR0],
reg_rd[BRK3_STAT],
reg_rd[BRK3_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk3_reg_wr = {reg_wr[BRK3_ADDR1],
reg_wr[BRK3_ADDR0],
reg_wr[BRK3_STAT],
reg_wr[BRK3_CTL]};
omsp_dbg_hwbrk dbg_hwbr_3 (
// OUTPUTs
.brk_halt (brk3_halt), // Hardware breakpoint command
.brk_pnd (brk3_pnd), // Hardware break/watch-point pending
.brk_dout (brk3_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk3_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk3_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.decode_noirq (decode_noirq), // Frontend decode instruction
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.pc (pc) // Program counter
);
`else
assign brk3_halt = 1'b0;
assign brk3_pnd = 1'b0;
assign brk3_dout = 16'h0000;
`endif
//============================================================================
// 6) DATA OUTPUT GENERATION
//============================================================================
wire [15:0] cpu_id_lo_rd = cpu_id[15:0] & {16{reg_rd[CPU_ID_LO]}};
wire [15:0] cpu_id_hi_rd = cpu_id[31:16] & {16{reg_rd[CPU_ID_HI]}};
wire [15:0] cpu_ctl_rd = {8'h00, cpu_ctl_full} & {16{reg_rd[CPU_CTL]}};
wire [15:0] cpu_stat_rd = {8'h00, cpu_stat_full} & {16{reg_rd[CPU_STAT]}};
wire [15:0] mem_ctl_rd = {8'h00, mem_ctl_full} & {16{reg_rd[MEM_CTL]}};
wire [15:0] mem_data_rd = mem_data & {16{reg_rd[MEM_DATA]}};
wire [15:0] mem_addr_rd = mem_addr & {16{reg_rd[MEM_ADDR]}};
wire [15:0] mem_cnt_rd = mem_cnt & {16{reg_rd[MEM_CNT]}};
wire [15:0] cpu_nr_rd = cpu_nr & {16{reg_rd[CPU_NR]}};
wire [15:0] dbg_dout = cpu_id_lo_rd |
cpu_id_hi_rd |
cpu_ctl_rd |
cpu_stat_rd |
mem_ctl_rd |
mem_data_rd |
mem_addr_rd |
mem_cnt_rd |
brk0_dout |
brk1_dout |
brk2_dout |
brk3_dout |
cpu_nr_rd;
// Tell UART/I2C interface that the data is ready to be read
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_rd_rdy <= 1'b0;
else if (mem_burst | mem_burst_rd) dbg_rd_rdy <= (dbg_reg_rd | dbg_mem_rd_dly);
else dbg_rd_rdy <= dbg_rd;
//============================================================================
// 7) CPU CONTROL
//============================================================================
// Reset CPU
//--------------------------
wire dbg_cpu_reset = cpu_ctl[`CPU_RST];
// Break after reset
//--------------------------
wire halt_rst = cpu_ctl[`RST_BRK_EN] & dbg_en_s & puc_pnd_set;
// Freeze peripherals
//--------------------------
wire dbg_freeze = dbg_halt_st & (cpu_ctl[`FRZ_BRK_EN] | ~cpu_en_s);
// Software break
//--------------------------
assign dbg_swbrk = (fe_mdb_in==`DBG_SWBRK_OP) & decode_noirq & cpu_ctl[`SW_BRK_EN];
// Single step
//--------------------------
reg [1:0] inc_step;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) inc_step <= 2'b00;
else if (istep) inc_step <= 2'b11;
else inc_step <= {inc_step[0], 1'b0};
// Run / Halt
//--------------------------
reg halt_flag;
wire mem_halt_cpu;
wire mem_run_cpu;
wire halt_flag_clr = run_cpu | mem_run_cpu;
wire halt_flag_set = halt_cpu | halt_rst | dbg_swbrk | mem_halt_cpu |
brk0_halt | brk1_halt | brk2_halt | brk3_halt;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) halt_flag <= 1'b0;
else if (halt_flag_clr) halt_flag <= 1'b0;
else if (halt_flag_set) halt_flag <= 1'b1;
wire dbg_halt_cmd = (halt_flag | halt_flag_set) & ~inc_step[1];
//============================================================================
// 8) MEMORY CONTROL
//============================================================================
// Control Memory bursts
//------------------------------
wire mem_burst_start = (mem_start & |mem_cnt);
wire mem_burst_end = ((dbg_wr | dbg_rd_rdy) & ~|mem_cnt);
// Detect when burst is on going
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_burst <= 1'b0;
else if (mem_burst_start) mem_burst <= 1'b1;
else if (mem_burst_end) mem_burst <= 1'b0;
// Control signals for UART/I2C interface
assign mem_burst_rd = (mem_burst_start & ~mem_ctl[1]);
assign mem_burst_wr = (mem_burst_start & mem_ctl[1]);
// Trigger CPU Register or memory access during a burst
reg mem_startb;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_startb <= 1'b0;
else mem_startb <= (mem_burst & (dbg_wr | dbg_rd)) | mem_burst_rd;
// Combine single and burst memory start of sequence
wire mem_seq_start = ((mem_start & ~|mem_cnt) | mem_startb);
// Memory access state machine
//------------------------------
reg [1:0] mem_state;
reg [1:0] mem_state_nxt;
// State machine definition
parameter M_IDLE = 2'h0;
parameter M_SET_BRK = 2'h1;
parameter M_ACCESS_BRK = 2'h2;
parameter M_ACCESS = 2'h3;
// State transition
always @(mem_state or mem_seq_start or dbg_halt_st)
case (mem_state)
M_IDLE : mem_state_nxt = ~mem_seq_start ? M_IDLE :
dbg_halt_st ? M_ACCESS : M_SET_BRK;
M_SET_BRK : mem_state_nxt = dbg_halt_st ? M_ACCESS_BRK : M_SET_BRK;
M_ACCESS_BRK : mem_state_nxt = M_IDLE;
M_ACCESS : mem_state_nxt = M_IDLE;
// pragma coverage off
default : mem_state_nxt = M_IDLE;
// pragma coverage on
endcase
// State machine
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_state <= M_IDLE;
else mem_state <= mem_state_nxt;
// Utility signals
assign mem_halt_cpu = (mem_state==M_IDLE) & (mem_state_nxt==M_SET_BRK);
assign mem_run_cpu = (mem_state==M_ACCESS_BRK) & (mem_state_nxt==M_IDLE);
assign mem_access = (mem_state==M_ACCESS) | (mem_state==M_ACCESS_BRK);
// Interface to CPU Registers and Memory bacbkone
//------------------------------------------------
assign dbg_mem_addr = mem_addr;
assign dbg_mem_dout = ~mem_bw ? mem_data :
mem_addr[0] ? {mem_data[7:0], 8'h00} :
{8'h00, mem_data[7:0]};
assign dbg_reg_wr = mem_access & mem_ctl[1] & mem_ctl[2];
assign dbg_reg_rd = mem_access & ~mem_ctl[1] & mem_ctl[2];
assign dbg_mem_en = mem_access & ~mem_ctl[2];
assign dbg_mem_rd = dbg_mem_en & ~mem_ctl[1];
wire [1:0] dbg_mem_wr_msk = ~mem_bw ? 2'b11 :
mem_addr[0] ? 2'b10 : 2'b01;
assign dbg_mem_wr = {2{dbg_mem_en & mem_ctl[1]}} & dbg_mem_wr_msk;
// It takes one additional cycle to read from Memory as from registers
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_mem_rd_dly <= 1'b0;
else dbg_mem_rd_dly <= dbg_mem_rd;
//=============================================================================
// 9) UART COMMUNICATION
//=============================================================================
`ifdef DBG_UART
omsp_dbg_uart dbg_uart_0 (
// OUTPUTs
.dbg_addr (dbg_addr), // Debug register address
.dbg_din (dbg_din), // Debug register data input
.dbg_rd (dbg_rd), // Debug register data read
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
.dbg_wr (dbg_wr), // Debug register data write
// INPUTs
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_dout (dbg_dout), // Debug register data output
.dbg_rd_rdy (dbg_rd_rdy), // Debug register data is ready for read
.dbg_rst (dbg_rst), // Debug unit reset
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
.mem_burst (mem_burst), // Burst on going
.mem_burst_end (mem_burst_end), // End TX/RX burst
.mem_burst_rd (mem_burst_rd), // Start TX burst
.mem_burst_wr (mem_burst_wr), // Start RX burst
.mem_bw (mem_bw) // Burst byte width
);
`else
assign dbg_uart_txd = 1'b1;
wire UNUSED_dbg_uart_rxd = dbg_uart_rxd;
`ifdef DBG_I2C
`else
assign dbg_addr = 6'h00;
assign dbg_din = 16'h0000;
assign dbg_rd = 1'b0;
assign dbg_wr = 1'b0;
`endif
`endif
//=============================================================================
// 10) I2C COMMUNICATION
//=============================================================================
`ifdef DBG_I2C
omsp_dbg_i2c dbg_i2c_0 (
// OUTPUTs
.dbg_addr (dbg_addr), // Debug register address
.dbg_din (dbg_din), // Debug register data input
.dbg_i2c_sda_out (dbg_i2c_sda_out), // Debug interface: I2C SDA OUT
.dbg_rd (dbg_rd), // Debug register data read
.dbg_wr (dbg_wr), // Debug register data write
// INPUTs
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_dout (dbg_dout), // Debug register data output
.dbg_i2c_addr (dbg_i2c_addr), // Debug interface: I2C Address
.dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
.dbg_i2c_scl (dbg_i2c_scl), // Debug interface: I2C SCL
.dbg_i2c_sda_in (dbg_i2c_sda_in), // Debug interface: I2C SDA IN
.dbg_rst (dbg_rst), // Debug unit reset
.mem_burst (mem_burst), // Burst on going
.mem_burst_end (mem_burst_end), // End TX/RX burst
.mem_burst_rd (mem_burst_rd), // Start TX burst
.mem_burst_wr (mem_burst_wr), // Start RX burst
.mem_bw (mem_bw) // Burst byte width
);
`else
assign dbg_i2c_sda_out = 1'b1;
wire [6:0] UNUSED_dbg_i2c_addr = dbg_i2c_addr;
wire [6:0] UNUSED_dbg_i2c_broadcast = dbg_i2c_broadcast;
wire UNUSED_dbg_i2c_scl = dbg_i2c_scl;
wire UNUSED_dbg_i2c_sda_in = dbg_i2c_sda_in;
wire UNUSED_dbg_rd_rdy = dbg_rd_rdy;
`endif
endmodule // omsp_dbg
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:04:14 06/30/2012
// Design Name:
// Module Name: MIO_BUS
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MIO_BUS(input clk,
input rst,
input[3:0]BTN,
input[15:0]SW,
input mem_w,
input[31:0]Cpu_data2bus, //data from CPU
input[31:0]addr_bus,
input[31:0]ram_data_out,
input[15:0]led_out,
input[31:0]counter_out,
input counter0_out,
input counter1_out,
input counter2_out,
output reg[31:0]Cpu_data4bus, //write to CPU
output reg[31:0]ram_data_in, //from CPU write to Memory
output reg[9:0]ram_addr, //Memory Address signals
output reg data_ram_we,
output reg GPIOf0000000_we,
output reg GPIOe0000000_we,
output reg counter_we,
output reg[31:0]Peripheral_in
);
endmodule
|
/****************************************************************************
* Copyright (c) 2009 by Focus Robotics. All rights reserved.
*
* This program is an unpublished work fully protected by the United States
* copyright laws and is considered a trade secret belonging to the copyright
* holder. No part of this design may be reproduced stored in a retrieval
* system, or transmitted, in any form or by any means, electronic,
* mechanical, photocopying, recording, or otherwise, without prior written
* permission of Focus Robotics, Inc.
*
* Proprietary and Confidential
*
* Created By : Andrew Worcester
* Creation_Date: Mon Apr 6 2009
*
* Brief Description:
*
* Functionality:
*
* Issues:
*
* Limitations:
*
* Testing:
*
* Synthesis:
*
******************************************************************************/
module fric_xactor
(
clk,
rst,
fric_in,
fric_out
);
input clk;
input rst;
input [7:0] fric_in;
output [7:0] fric_out;
reg [7:0] fric_out_o;
wire [7:0] fric_in_i;
assign #1 fric_out = fric_out_o;
assign #1 fric_in_i = fric_in;
endmodule // fric_xactor
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam NO = 10; // number of access events
// packed structures
struct packed {
logic e0;
logic [1:0] e1;
logic [3:0] e2;
logic [7:0] e3;
} struct_bg; // big endian structure
/* verilator lint_off LITENDIAN */
struct packed {
logic e0;
logic [0:1] e1;
logic [0:3] e2;
logic [0:7] e3;
} struct_lt; // little endian structure
/* verilator lint_on LITENDIAN */
localparam WS = 15; // $bits(struct_bg)
integer cnt = 0;
// event counter
always @ (posedge clk)
begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin
$write("*-* All Finished *-*\n");
$finish;
end
// big endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaaults (all bits to 0)
if (cnt[30:2]==0) struct_bg <= '0;
else if (cnt[30:2]==1) struct_bg <= '0;
else if (cnt[30:2]==2) struct_bg <= '0;
else if (cnt[30:2]==3) struct_bg <= '0;
else if (cnt[30:2]==4) struct_bg <= '0;
else if (cnt[30:2]==5) struct_bg <= '0;
end else if (cnt[1:0]==2'd1) begin
// write value to structure
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) struct_bg <= '1;
else if (cnt[30:2]==2) struct_bg.e0 <= '1;
else if (cnt[30:2]==3) struct_bg.e1 <= '1;
else if (cnt[30:2]==4) struct_bg.e2 <= '1;
else if (cnt[30:2]==5) struct_bg.e3 <= '1;
end else if (cnt[1:0]==2'd2) begin
// check structure value
if (cnt[30:2]==0) begin if (struct_bg !== 15'b000000000000000) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==1) begin if (struct_bg !== 15'b111111111111111) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==2) begin if (struct_bg !== 15'b100000000000000) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==3) begin if (struct_bg !== 15'b011000000000000) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==4) begin if (struct_bg !== 15'b000111100000000) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==5) begin if (struct_bg !== 15'b000000011111111) begin $display("%b", struct_bg); $stop(); end end
end else if (cnt[1:0]==2'd3) begin
// read value from structure (not a very good test for now)
if (cnt[30:2]==0) begin if (struct_bg !== {WS{1'b0}}) $stop(); end
else if (cnt[30:2]==1) begin if (struct_bg !== {WS{1'b1}}) $stop(); end
else if (cnt[30:2]==2) begin if (struct_bg.e0 !== { 1{1'b1}}) $stop(); end
else if (cnt[30:2]==3) begin if (struct_bg.e1 !== { 2{1'b1}}) $stop(); end
else if (cnt[30:2]==4) begin if (struct_bg.e2 !== { 4{1'b1}}) $stop(); end
else if (cnt[30:2]==5) begin if (struct_bg.e3 !== { 8{1'b1}}) $stop(); end
end
// little endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaaults (all bits to 0)
if (cnt[30:2]==0) struct_lt <= '0;
else if (cnt[30:2]==1) struct_lt <= '0;
else if (cnt[30:2]==2) struct_lt <= '0;
else if (cnt[30:2]==3) struct_lt <= '0;
else if (cnt[30:2]==4) struct_lt <= '0;
else if (cnt[30:2]==5) struct_lt <= '0;
end else if (cnt[1:0]==2'd1) begin
// write value to structure
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) struct_lt <= '1;
else if (cnt[30:2]==2) struct_lt.e0 <= '1;
else if (cnt[30:2]==3) struct_lt.e1 <= '1;
else if (cnt[30:2]==4) struct_lt.e2 <= '1;
else if (cnt[30:2]==5) struct_lt.e3 <= '1;
end else if (cnt[1:0]==2'd2) begin
// check structure value
if (cnt[30:2]==0) begin if (struct_lt !== 15'b000000000000000) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==1) begin if (struct_lt !== 15'b111111111111111) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==2) begin if (struct_lt !== 15'b100000000000000) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==3) begin if (struct_lt !== 15'b011000000000000) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==4) begin if (struct_lt !== 15'b000111100000000) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==5) begin if (struct_lt !== 15'b000000011111111) begin $display("%b", struct_lt); $stop(); end end
end else if (cnt[1:0]==2'd3) begin
// read value from structure (not a very good test for now)
if (cnt[30:2]==0) begin if (struct_lt !== {WS{1'b0}}) $stop(); end
else if (cnt[30:2]==1) begin if (struct_lt !== {WS{1'b1}}) $stop(); end
else if (cnt[30:2]==2) begin if (struct_lt.e0 !== { 1{1'b1}}) $stop(); end
else if (cnt[30:2]==3) begin if (struct_lt.e1 !== { 2{1'b1}}) $stop(); end
else if (cnt[30:2]==4) begin if (struct_lt.e2 !== { 4{1'b1}}) $stop(); end
else if (cnt[30:2]==5) begin if (struct_lt.e3 !== { 8{1'b1}}) $stop(); end
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module convolve_kernel_control_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 4,
C_S_AXI_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
output wire interrupt,
// user signals
output wire ap_start,
input wire ap_done,
input wire ap_ready,
input wire ap_idle
);
//------------------------Address Info-------------------
// 0x0 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x4 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x8 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0xc : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
localparam
ADDR_AP_CTRL = 4'h0,
ADDR_GIE = 4'h4,
ADDR_IER = 4'h8,
ADDR_ISR = 4'hc,
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
WRRESET = 2'd3,
RDIDLE = 2'd0,
RDDATA = 2'd1,
RDRESET = 2'd2,
ADDR_BITS = 4;
//------------------------Local signal-------------------
reg [1:0] wstate = WRRESET;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
reg [1:0] rstate = RDRESET;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
wire int_ap_idle;
wire int_ap_ready;
reg int_ap_done = 1'b0;
reg int_ap_start = 1'b0;
reg int_auto_restart = 1'b0;
reg int_gie = 1'b0;
reg [1:0] int_ier = 2'b0;
reg [1:0] int_isr = 2'b0;
//------------------------Instantiation------------------
//------------------------AXI write fsm------------------
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRRESET;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//------------------------AXI read fsm-------------------
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDRESET;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_AP_CTRL: begin
rdata[0] <= int_ap_start;
rdata[1] <= int_ap_done;
rdata[2] <= int_ap_idle;
rdata[3] <= int_ap_ready;
rdata[7] <= int_auto_restart;
end
ADDR_GIE: begin
rdata <= int_gie;
end
ADDR_IER: begin
rdata <= int_ier;
end
ADDR_ISR: begin
rdata <= int_isr;
end
endcase
end
end
end
//------------------------Register logic-----------------
assign interrupt = int_gie & (|int_isr);
assign ap_start = int_ap_start;
assign int_ap_idle = ap_idle;
assign int_ap_ready = ap_ready;
// int_ap_start
always @(posedge ACLK) begin
if (ARESET)
int_ap_start <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
int_ap_start <= 1'b1;
else if (int_ap_ready)
int_ap_start <= int_auto_restart; // clear on handshake/auto restart
end
end
// int_ap_done
always @(posedge ACLK) begin
if (ARESET)
int_ap_done <= 1'b0;
else if (ACLK_EN) begin
if (ap_done)
int_ap_done <= 1'b1;
else if (ar_hs && raddr == ADDR_AP_CTRL)
int_ap_done <= 1'b0; // clear on read
end
end
// int_auto_restart
always @(posedge ACLK) begin
if (ARESET)
int_auto_restart <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
int_auto_restart <= WDATA[7];
end
end
// int_gie
always @(posedge ACLK) begin
if (ARESET)
int_gie <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_GIE && WSTRB[0])
int_gie <= WDATA[0];
end
end
// int_ier
always @(posedge ACLK) begin
if (ARESET)
int_ier <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IER && WSTRB[0])
int_ier <= WDATA[1:0];
end
end
// int_isr[0]
always @(posedge ACLK) begin
if (ARESET)
int_isr[0] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[0] & ap_done)
int_isr[0] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
end
end
// int_isr[1]
always @(posedge ACLK) begin
if (ARESET)
int_isr[1] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[1] & ap_ready)
int_isr[1] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
end
end
//------------------------Memory logic-------------------
endmodule
|
(** * PE: Partial Evaluation *)
(* Chapter written and maintained by Chung-chieh Shan *)
(** The [Equiv] chapter introduced constant folding as an example of a
program transformation and proved that it preserves the meaning of
programs. Constant folding operates on manifest constants such as
[ANum] expressions. For example, it simplifies the command [Y ::=
APlus (ANum 3) (ANum 1)] to the command [Y ::= ANum 4]. However,
it does not propagate known constants along data flow. For
example, it does not simplify the sequence
X ::= ANum 3;; Y ::= APlus (AId X) (ANum 1)
to
X ::= ANum 3;; Y ::= ANum 4
because it forgets that [X] is [3] by the time it gets to [Y].
We might naturally want to enhance constant folding so that it
propagates known constants and uses them to simplify programs.
Doing so constitutes a rudimentary form of _partial evaluation_.
As we will see, partial evaluation is so called because it is like
running a program, except only part of the program can be
evaluated because only part of the input to the program is known.
For example, we can only simplify the program
X ::= ANum 3;; Y ::= AMinus (APlus (AId X) (ANum 1)) (AId Y)
to
X ::= ANum 3;; Y ::= AMinus (ANum 4) (AId Y)
without knowing the initial value of [Y]. *)
Require Import Coq.Bool.Bool.
Require Import Coq.Arith.Arith.
Require Import Coq.Arith.EqNat.
Require Import Coq.omega.Omega.
Require Import Coq.Logic.FunctionalExtensionality.
Require Import Coq.Lists.List.
Import ListNotations.
Require Import SfLib.
Require Import Maps.
Require Import Imp.
(* ################################################################# *)
(** * Generalizing Constant Folding *)
(** The starting point of partial evaluation is to represent our
partial knowledge about the state. For example, between the two
assignments above, the partial evaluator may know only that [X] is
[3] and nothing about any other variable. *)
(* ================================================================= *)
(** ** Partial States *)
(** Conceptually speaking, we can think of such partial states as the
type [id -> option nat] (as opposed to the type [id -> nat] of
concrete, full states). However, in addition to looking up and
updating the values of individual variables in a partial state, we
may also want to compare two partial states to see if and where
they differ, to handle conditional control flow. It is not possible
to compare two arbitrary functions in this way, so we represent
partial states in a more concrete format: as a list of [id * nat]
pairs. *)
Definition pe_state := list (id * nat).
(** The idea is that a variable [id] appears in the list if and only
if we know its current [nat] value. The [pe_lookup] function thus
interprets this concrete representation. (If the same variable
[id] appears multiple times in the list, the first occurrence
wins, but we will define our partial evaluator to never construct
such a [pe_state].) *)
Fixpoint pe_lookup (pe_st : pe_state) (V:id) : option nat :=
match pe_st with
| [] => None
| (V',n')::pe_st => if beq_id V V' then Some n'
else pe_lookup pe_st V
end.
(** For example, [empty_pe_state] represents complete ignorance about
every variable -- the function that maps every [id] to [None]. *)
Definition empty_pe_state : pe_state := [].
(** More generally, if the [list] representing a [pe_state] does not
contain some [id], then that [pe_state] must map that [id] to
[None]. Before we prove this fact, we first define a useful
tactic for reasoning with [id] equality. The tactic
compare V V'
means to reason by cases over [beq_id V V'].
In the case where [V = V'], the tactic
substitutes [V] for [V'] throughout. *)
Tactic Notation "compare" ident(i) ident(j) :=
let H := fresh "Heq" i j in
destruct (beq_idP i j);
[ subst j | ].
Theorem pe_domain: forall pe_st V n,
pe_lookup pe_st V = Some n ->
In V (map (@fst _ _) pe_st).
Proof. intros pe_st V n H. induction pe_st as [| [V' n'] pe_st].
- (* [] *) inversion H.
- (* :: *) simpl in H. simpl. compare V V'; auto. Qed.
(** In what follows, we will make heavy use of the [In] property from
the standard library, also defined in [Logic.v]: *)
Print In.
(* ===> Fixpoint In {A:Type} (a: A) (l:list A) : Prop :=
match l with
| [] => False
| b :: m => b = a \/ In a m
end
: forall A : Type, A -> list A -> Prop *)
(** Besides the various lemmas about [In] that we've already come
across, the following one (taken from the standard library) will
also be useful: *)
Check filter_In.
(* ===> filter_In : forall (A : Type) (f : A -> bool) (x : A) (l : list A),
In x (filter f l) <-> In x l /\ f x = true *)
(** If a type [A] has an operator [beq] for testing equality of its
elements, we can compute a boolean [inb beq a l] for testing
whether [In a l] holds or not. *)
Fixpoint inb {A : Type} (beq : A -> A -> bool) (a : A) (l : list A) :=
match l with
| [] => false
| a'::l' => beq a a' || inb beq a l'
end.
(** It is easy to relate [inb] to [In] with the [reflect] property: *)
Lemma inbP : forall A : Type, forall beq : A->A->bool,
(forall a1 a2, reflect (a1 = a2) (beq a1 a2)) ->
forall a l, reflect (In a l) (inb beq a l).
Proof.
intros A beq beqP a l.
induction l as [|a' l' IH].
- constructor. intros [].
- simpl. destruct (beqP a a').
+ subst. constructor. left. reflexivity.
+ simpl. destruct IH; constructor.
* right. trivial.
* intros [H1 | H2]; congruence.
Qed.
(* ================================================================= *)
(** ** Arithmetic Expressions *)
(** Partial evaluation of [aexp] is straightforward -- it is basically
the same as constant folding, [fold_constants_aexp], except that
sometimes the partial state tells us the current value of a
variable and we can replace it by a constant expression. *)
Fixpoint pe_aexp (pe_st : pe_state) (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => match pe_lookup pe_st i with (* <----- NEW *)
| Some n => ANum n
| None => AId i
end
| APlus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
(** This partial evaluator folds constants but does not apply the
associativity of addition. *)
Example test_pe_aexp1:
pe_aexp [(X,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (ANum 4) (AId Y).
Proof. reflexivity. Qed.
Example text_pe_aexp2:
pe_aexp [(Y,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (APlus (AId X) (ANum 1)) (ANum 3).
Proof. reflexivity. Qed.
(** Now, in what sense is [pe_aexp] correct? It is reasonable to
define the correctness of [pe_aexp] as follows: whenever a full
state [st:state] is _consistent_ with a partial state
[pe_st:pe_state] (in other words, every variable to which [pe_st]
assigns a value is assigned the same value by [st]), evaluating
[a] and evaluating [pe_aexp pe_st a] in [st] yields the same
result. This statement is indeed true. *)
Definition pe_consistent (st:state) (pe_st:pe_state) :=
forall V n, Some n = pe_lookup pe_st V -> st V = n.
Theorem pe_aexp_correct_weak: forall st pe_st, pe_consistent st pe_st ->
forall a, aeval st a = aeval st (pe_aexp pe_st a).
Proof. unfold pe_consistent. intros st pe_st H a.
induction a; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound,
the only interesting case is AId *)
- (* AId *)
remember (pe_lookup pe_st i) as l. destruct l.
+ (* Some *) rewrite H with (n:=n) by apply Heql. reflexivity.
+ (* None *) reflexivity.
Qed.
(** However, we will soon want our partial evaluator to remove
assignments. For example, it will simplify
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to just
Y ::= AMinus (ANum 3) (AId Y);; X ::= ANum 4
by delaying the assignment to [X] until the end. To accomplish
this simplification, we need the result of partial evaluating
pe_aexp [(X,3)] (AMinus (AId X) (AId Y))
to be equal to [AMinus (ANum 3) (AId Y)] and _not_ the original
expression [AMinus (AId X) (AId Y)]. After all, it would be
incorrect, not just inefficient, to transform
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to
Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
even though the output expressions [AMinus (ANum 3) (AId Y)] and
[AMinus (AId X) (AId Y)] both satisfy the correctness criterion
that we just proved. Indeed, if we were to just define [pe_aexp
pe_st a = a] then the theorem [pe_aexp_correct'] would already
trivially hold.
Instead, we want to prove that the [pe_aexp] is correct in a
stronger sense: evaluating the expression produced by partial
evaluation ([aeval st (pe_aexp pe_st a)]) must not depend on those
parts of the full state [st] that are already specified in the
partial state [pe_st]. To be more precise, let us define a
function [pe_override], which updates [st] with the contents of
[pe_st]. In other words, [pe_override] carries out the
assignments listed in [pe_st] on top of [st]. *)
Fixpoint pe_update (st:state) (pe_st:pe_state) : state :=
match pe_st with
| [] => st
| (V,n)::pe_st => t_update (pe_update st pe_st) V n
end.
Example test_pe_update:
pe_update (t_update empty_state Y 1) [(X,3);(Z,2)]
= t_update (t_update (t_update empty_state Y 1) Z 2) X 3.
Proof. reflexivity. Qed.
(** Although [pe_update] operates on a concrete [list] representing
a [pe_state], its behavior is defined entirely by the [pe_lookup]
interpretation of the [pe_state]. *)
Theorem pe_update_correct: forall st pe_st V0,
pe_update st pe_st V0 =
match pe_lookup pe_st V0 with
| Some n => n
| None => st V0
end.
Proof. intros. induction pe_st as [| [V n] pe_st]. reflexivity.
simpl in *. unfold t_update.
compare V0 V; auto. rewrite <- beq_id_refl; auto. rewrite false_beq_id; auto. Qed.
(** We can relate [pe_consistent] to [pe_update] in two ways.
First, overriding a state with a partial state always gives a
state that is consistent with the partial state. Second, if a
state is already consistent with a partial state, then overriding
the state with the partial state gives the same state. *)
Theorem pe_update_consistent: forall st pe_st,
pe_consistent (pe_update st pe_st) pe_st.
Proof. intros st pe_st V n H. rewrite pe_update_correct.
destruct (pe_lookup pe_st V); inversion H. reflexivity. Qed.
Theorem pe_consistent_update: forall st pe_st,
pe_consistent st pe_st -> forall V, st V = pe_update st pe_st V.
Proof. intros st pe_st H V. rewrite pe_update_correct.
remember (pe_lookup pe_st V) as l. destruct l; auto. Qed.
(** Now we can state and prove that [pe_aexp] is correct in the
stronger sense that will help us define the rest of the partial
evaluator.
Intuitively, running a program using partial evaluation is a
two-stage process. In the first, _static_ stage, we partially
evaluate the given program with respect to some partial state to
get a _residual_ program. In the second, _dynamic_ stage, we
evaluate the residual program with respect to the rest of the
state. This dynamic state provides values for those variables
that are unknown in the static (partial) state. Thus, the
residual program should be equivalent to _prepending_ the
assignments listed in the partial state to the original program. *)
Theorem pe_aexp_correct: forall (pe_st:pe_state) (a:aexp) (st:state),
aeval (pe_update st pe_st) a = aeval st (pe_aexp pe_st a).
Proof.
intros pe_st a st.
induction a; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound, the only
interesting case is AId. *)
rewrite pe_update_correct. destruct (pe_lookup pe_st i); reflexivity.
Qed.
(* ================================================================= *)
(** ** Boolean Expressions *)
(** The partial evaluation of boolean expressions is similar. In
fact, it is entirely analogous to the constant folding of boolean
expressions, because our language has no boolean variables. *)
Fixpoint pe_bexp (pe_st : pe_state) (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BEq a1' a2'
end
| BLe a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if leb n1 n2 then BTrue else BFalse
| (a1', a2') => BLe a1' a2'
end
| BNot b1 =>
match (pe_bexp pe_st b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (pe_bexp pe_st b1, pe_bexp pe_st b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example test_pe_bexp1:
pe_bexp [(X,3)] (BNot (BLe (AId X) (ANum 3)))
= BFalse.
Proof. reflexivity. Qed.
Example test_pe_bexp2: forall b,
b = BNot (BLe (AId X) (APlus (AId X) (ANum 1))) ->
pe_bexp [] b = b.
Proof. intros b H. rewrite -> H. reflexivity. Qed.
(** The correctness of [pe_bexp] is analogous to the correctness of
[pe_aexp] above. *)
Theorem pe_bexp_correct: forall (pe_st:pe_state) (b:bexp) (st:state),
beval (pe_update st pe_st) b = beval st (pe_bexp pe_st b).
Proof.
intros pe_st b st.
induction b; simpl;
try reflexivity;
try (remember (pe_aexp pe_st a) as a';
remember (pe_aexp pe_st a0) as a0';
assert (Ha: aeval (pe_update st pe_st) a = aeval st a');
assert (Ha0: aeval (pe_update st pe_st) a0 = aeval st a0');
try (subst; apply pe_aexp_correct);
destruct a'; destruct a0'; rewrite Ha; rewrite Ha0;
simpl; try destruct (beq_nat n n0);
try destruct (leb n n0); reflexivity);
try (destruct (pe_bexp pe_st b); rewrite IHb; reflexivity);
try (destruct (pe_bexp pe_st b1);
destruct (pe_bexp pe_st b2);
rewrite IHb1; rewrite IHb2; reflexivity).
Qed.
(* ################################################################# *)
(** * Partial Evaluation of Commands, Without Loops *)
(** What about the partial evaluation of commands? The analogy
between partial evaluation and full evaluation continues: Just as
full evaluation of a command turns an initial state into a final
state, partial evaluation of a command turns an initial partial
state into a final partial state. The difference is that, because
the state is partial, some parts of the command may not be
executable at the static stage. Therefore, just as [pe_aexp]
returns a residual [aexp] and [pe_bexp] returns a residual [bexp]
above, partially evaluating a command yields a residual command.
Another way in which our partial evaluator is similar to a full
evaluator is that it does not terminate on all commands. It is
not hard to build a partial evaluator that terminates on all
commands; what is hard is building a partial evaluator that
terminates on all commands yet automatically performs desired
optimizations such as unrolling loops. Often a partial evaluator
can be coaxed into terminating more often and performing more
optimizations by writing the source program differently so that
the separation between static and dynamic information becomes more
apparent. Such coaxing is the art of _binding-time improvement_.
The binding time of a variable tells when its value is known --
either "static", or "dynamic."
Anyway, for now we will just live with the fact that our partial
evaluator is not a total function from the source command and the
initial partial state to the residual command and the final
partial state. To model this non-termination, just as with the
full evaluation of commands, we use an inductively defined
relation. We write
c1 / st \\ c1' / st'
to mean that partially evaluating the source command [c1] in the
initial partial state [st] yields the residual command [c1'] and
the final partial state [st']. For example, we want something like
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] \\ (Y ::= AMult (AId Z) (ANum 6)) / [(X,3)]
to hold. The assignment to [X] appears in the final partial state,
not the residual command. *)
(* ================================================================= *)
(** ** Assignment *)
(** Let's start by considering how to partially evaluate an
assignment. The two assignments in the source program above needs
to be treated differently. The first assignment [X ::= ANum 3],
is _static_: its right-hand-side is a constant (more generally,
simplifies to a constant), so we should update our partial state
at [X] to [3] and produce no residual code. (Actually, we produce
a residual [SKIP].) The second assignment [Y ::= AMult (AId Z)
(APlus (AId X) (AId X))] is _dynamic_: its right-hand-side does
not simplify to a constant, so we should leave it in the residual
code and remove [Y], if present, from our partial state. To
implement these two cases, we define the functions [pe_add] and
[pe_remove]. Like [pe_update] above, these functions operate on
a concrete [list] representing a [pe_state], but the theorems
[pe_add_correct] and [pe_remove_correct] specify their behavior by
the [pe_lookup] interpretation of the [pe_state]. *)
Fixpoint pe_remove (pe_st:pe_state) (V:id) : pe_state :=
match pe_st with
| [] => []
| (V',n')::pe_st => if beq_id V V' then pe_remove pe_st V
else (V',n') :: pe_remove pe_st V
end.
Theorem pe_remove_correct: forall pe_st V V0,
pe_lookup (pe_remove pe_st V) V0
= if beq_id V V0 then None else pe_lookup pe_st V0.
Proof. intros pe_st V V0. induction pe_st as [| [V' n'] pe_st].
- (* [] *) destruct (beq_id V V0); reflexivity.
- (* :: *) simpl. compare V V'.
+ (* equal *) rewrite IHpe_st.
destruct (beq_idP V V0). reflexivity.
rewrite false_beq_id; auto.
+ (* not equal *) simpl. compare V0 V'.
* (* equal *) rewrite false_beq_id; auto.
* (* not equal *) rewrite IHpe_st. reflexivity.
Qed.
Definition pe_add (pe_st:pe_state) (V:id) (n:nat) : pe_state :=
(V,n) :: pe_remove pe_st V.
Theorem pe_add_correct: forall pe_st V n V0,
pe_lookup (pe_add pe_st V n) V0
= if beq_id V V0 then Some n else pe_lookup pe_st V0.
Proof. intros pe_st V n V0. unfold pe_add. simpl.
compare V V0.
- (* equal *) rewrite <- beq_id_refl; auto.
- (* not equal *) rewrite pe_remove_correct.
repeat rewrite false_beq_id; auto.
Qed.
(** We will use the two theorems below to show that our partial
evaluator correctly deals with dynamic assignments and static
assignments, respectively. *)
Theorem pe_update_update_remove: forall st pe_st V n,
t_update (pe_update st pe_st) V n =
pe_update (t_update st V n) (pe_remove pe_st V).
Proof. intros st pe_st V n. apply functional_extensionality.
intros V0. unfold t_update. rewrite !pe_update_correct.
rewrite pe_remove_correct. destruct (beq_id V V0); reflexivity.
Qed.
Theorem pe_update_update_add: forall st pe_st V n,
t_update (pe_update st pe_st) V n =
pe_update st (pe_add pe_st V n).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold t_update. rewrite !pe_update_correct. rewrite pe_add_correct.
destruct (beq_id V V0); reflexivity. Qed.
(* ================================================================= *)
(** ** Conditional *)
(** Trickier than assignments to partially evaluate is the
conditional, [IFB b1 THEN c1 ELSE c2 FI]. If [b1] simplifies to
[BTrue] or [BFalse] then it's easy: we know which branch will be
taken, so just take that branch. If [b1] does not simplify to a
constant, then we need to take both branches, and the final
partial state may differ between the two branches!
The following program illustrates the difficulty:
X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI
Suppose the initial partial state is empty. We don't know
statically how [Y] compares to [4], so we must partially evaluate
both branches of the (outer) conditional. On the [THEN] branch,
we know that [Y] is set to [4] and can even use that knowledge to
simplify the code somewhat. On the [ELSE] branch, we still don't
know the exact value of [Y] at the end. What should the final
partial state and residual program be?
One way to handle such a dynamic conditional is to take the
intersection of the final partial states of the two branches. In
this example, we take the intersection of [(Y,4),(X,3)] and
[(X,3)], so the overall final partial state is [(X,3)]. To
compensate for forgetting that [Y] is [4], we need to add an
assignment [Y ::= ANum 4] to the end of the [THEN] branch. So,
the residual program will be something like
SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
SKIP;;
SKIP;;
Y ::= ANum 4
ELSE SKIP FI
Programming this case in Coq calls for several auxiliary
functions: we need to compute the intersection of two [pe_state]s
and turn their difference into sequences of assignments.
First, we show how to compute whether two [pe_state]s to disagree
at a given variable. In the theorem [pe_disagree_domain], we
prove that two [pe_state]s can only disagree at variables that
appear in at least one of them. *)
Definition pe_disagree_at (pe_st1 pe_st2 : pe_state) (V:id) : bool :=
match pe_lookup pe_st1 V, pe_lookup pe_st2 V with
| Some x, Some y => negb (beq_nat x y)
| None, None => false
| _, _ => true
end.
Theorem pe_disagree_domain: forall (pe_st1 pe_st2 : pe_state) (V:id),
true = pe_disagree_at pe_st1 pe_st2 V ->
In V (map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2).
Proof. unfold pe_disagree_at. intros pe_st1 pe_st2 V H.
apply in_app_iff.
remember (pe_lookup pe_st1 V) as lookup1.
destruct lookup1 as [n1|]. left. apply pe_domain with n1. auto.
remember (pe_lookup pe_st2 V) as lookup2.
destruct lookup2 as [n2|]. right. apply pe_domain with n2. auto.
inversion H. Qed.
(** We define the [pe_compare] function to list the variables where
two given [pe_state]s disagree. This list is exact, according to
the theorem [pe_compare_correct]: a variable appears on the list
if and only if the two given [pe_state]s disagree at that
variable. Furthermore, we use the [pe_unique] function to
eliminate duplicates from the list. *)
Fixpoint pe_unique (l : list id) : list id :=
match l with
| [] => []
| x::l =>
x :: filter (fun y => if beq_id x y then false else true) (pe_unique l)
end.
Theorem pe_unique_correct: forall l x,
In x l <-> In x (pe_unique l).
Proof. intros l x. induction l as [| h t]. reflexivity.
simpl in *. split.
- (* -> *)
intros. inversion H; clear H.
left. assumption.
destruct (beq_idP h x).
left. assumption.
right. apply filter_In. split.
apply IHt. assumption.
rewrite false_beq_id; auto.
- (* <- *)
intros. inversion H; clear H.
left. assumption.
apply filter_In in H0. inversion H0. right. apply IHt. assumption.
Qed.
Definition pe_compare (pe_st1 pe_st2 : pe_state) : list id :=
pe_unique (filter (pe_disagree_at pe_st1 pe_st2)
(map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2)).
Theorem pe_compare_correct: forall pe_st1 pe_st2 V,
pe_lookup pe_st1 V = pe_lookup pe_st2 V <->
~ In V (pe_compare pe_st1 pe_st2).
Proof. intros pe_st1 pe_st2 V.
unfold pe_compare. rewrite <- pe_unique_correct. rewrite filter_In.
split; intros Heq.
- (* -> *)
intro. destruct H. unfold pe_disagree_at in H0. rewrite Heq in H0.
destruct (pe_lookup pe_st2 V).
rewrite <- beq_nat_refl in H0. inversion H0.
inversion H0.
- (* <- *)
assert (Hagree: pe_disagree_at pe_st1 pe_st2 V = false).
{ (* Proof of assertion *)
remember (pe_disagree_at pe_st1 pe_st2 V) as disagree.
destruct disagree; [| reflexivity].
apply pe_disagree_domain in Heqdisagree.
exfalso. apply Heq. split. assumption. reflexivity. }
unfold pe_disagree_at in Hagree.
destruct (pe_lookup pe_st1 V) as [n1|];
destruct (pe_lookup pe_st2 V) as [n2|];
try reflexivity; try solve by inversion.
rewrite negb_false_iff in Hagree.
apply beq_nat_true in Hagree. subst. reflexivity. Qed.
(** The intersection of two partial states is the result of removing
from one of them all the variables where the two disagree. We
define the function [pe_removes], in terms of [pe_remove] above,
to perform such a removal of a whole list of variables at once.
The theorem [pe_compare_removes] testifies that the [pe_lookup]
interpretation of the result of this intersection operation is the
same no matter which of the two partial states we remove the
variables from. Because [pe_update] only depends on the
[pe_lookup] interpretation of partial states, [pe_update] also
does not care which of the two partial states we remove the
variables from; that theorem [pe_compare_update] is used in the
correctness proof shortly. *)
Fixpoint pe_removes (pe_st:pe_state) (ids : list id) : pe_state :=
match ids with
| [] => pe_st
| V::ids => pe_remove (pe_removes pe_st ids) V
end.
Theorem pe_removes_correct: forall pe_st ids V,
pe_lookup (pe_removes pe_st ids) V =
if inb beq_id V ids then None else pe_lookup pe_st V.
Proof. intros pe_st ids V. induction ids as [| V' ids]. reflexivity.
simpl. rewrite pe_remove_correct. rewrite IHids.
compare V' V.
- rewrite <- beq_id_refl. reflexivity.
- rewrite false_beq_id; try congruence. reflexivity.
Qed.
Theorem pe_compare_removes: forall pe_st1 pe_st2 V,
pe_lookup (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) V =
pe_lookup (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)) V.
Proof.
intros pe_st1 pe_st2 V. rewrite !pe_removes_correct.
destruct (inbP _ _ beq_idP V (pe_compare pe_st1 pe_st2)).
- reflexivity.
- apply pe_compare_correct. auto. Qed.
Theorem pe_compare_update: forall pe_st1 pe_st2 st,
pe_update st (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) =
pe_update st (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)).
Proof. intros. apply functional_extensionality. intros V.
rewrite !pe_update_correct. rewrite pe_compare_removes. reflexivity.
Qed.
(** Finally, we define an [assign] function to turn the difference
between two partial states into a sequence of assignment commands.
More precisely, [assign pe_st ids] generates an assignment command
for each variable listed in [ids]. *)
Fixpoint assign (pe_st : pe_state) (ids : list id) : com :=
match ids with
| [] => SKIP
| V::ids => match pe_lookup pe_st V with
| Some n => (assign pe_st ids;; V ::= ANum n)
| None => assign pe_st ids
end
end.
(** The command generated by [assign] always terminates, because it is
just a sequence of assignments. The (total) function [assigned]
below computes the effect of the command on the (dynamic state).
The theorem [assign_removes] then confirms that the generated
assignments perfectly compensate for removing the variables from
the partial state. *)
Definition assigned (pe_st:pe_state) (ids : list id) (st:state) : state :=
fun V => if inb beq_id V ids then
match pe_lookup pe_st V with
| Some n => n
| None => st V
end
else st V.
Theorem assign_removes: forall pe_st ids st,
pe_update st pe_st =
pe_update (assigned pe_st ids st) (pe_removes pe_st ids).
Proof. intros pe_st ids st. apply functional_extensionality. intros V.
rewrite !pe_update_correct. rewrite pe_removes_correct. unfold assigned.
destruct (inbP _ _ beq_idP V ids); destruct (pe_lookup pe_st V); reflexivity.
Qed.
Lemma ceval_extensionality: forall c st st1 st2,
c / st \\ st1 -> (forall V, st1 V = st2 V) -> c / st \\ st2.
Proof. intros c st st1 st2 H Heq.
apply functional_extensionality in Heq. rewrite <- Heq. apply H. Qed.
Theorem eval_assign: forall pe_st ids st,
assign pe_st ids / st \\ assigned pe_st ids st.
Proof. intros pe_st ids st. induction ids as [| V ids]; simpl.
- (* [] *) eapply ceval_extensionality. apply E_Skip. reflexivity.
- (* V::ids *)
remember (pe_lookup pe_st V) as lookup. destruct lookup.
+ (* Some *) eapply E_Seq. apply IHids. unfold assigned. simpl.
eapply ceval_extensionality. apply E_Ass. simpl. reflexivity.
intros V0. unfold t_update. compare V V0.
* (* equal *) rewrite <- Heqlookup. rewrite <- beq_id_refl. reflexivity.
* (* not equal *) rewrite false_beq_id; simpl; congruence.
+ (* None *) eapply ceval_extensionality. apply IHids.
unfold assigned. intros V0. simpl. compare V V0.
* (* equal *) rewrite <- Heqlookup.
rewrite <- beq_id_refl.
destruct (inbP _ _ beq_idP V ids); reflexivity.
* (* not equal *) rewrite false_beq_id; simpl; congruence.
Qed.
(* ================================================================= *)
(** ** The Partial Evaluation Relation *)
(** At long last, we can define a partial evaluator for commands
without loops, as an inductive relation! The inequality
conditions in [PE_AssDynamic] and [PE_If] are just to keep the
partial evaluator deterministic; they are not required for
correctness. *)
Reserved Notation "c1 '/' st '\\' c1' '/' st'"
(at level 40, st at level 39, c1' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st \\ SKIP / pe_st
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st \\ SKIP / pe_add pe_st l n1
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st \\ (l ::= a1') / pe_remove pe_st l
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2',
c1 / pe_st \\ c1' / pe_st' ->
c2 / pe_st' \\ c2' / pe_st'' ->
(c1 ;; c2) / pe_st \\ (c1' ;; c2') / pe_st''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st \\ c1' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st \\ c1' / pe_st'
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st \\ c2' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st \\ c2' / pe_st'
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st \\ c1' / pe_st1 ->
c2 / pe_st \\ c2' / pe_st2 ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
\\ (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
where "c1 '/' st '\\' c1' '/' st'" := (pe_com c1 st c1' st').
Hint Constructors pe_com.
Hint Constructors ceval.
(* ================================================================= *)
(** ** Examples *)
(** Below are some examples of using the partial evaluator. To make
the [pe_com] relation actually usable for automatic partial
evaluation, we would need to define more automation tactics in
Coq. That is not hard to do, but it is not needed here. *)
Example pe_example1:
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] \\ (SKIP;; Y ::= AMult (AId Z) (ANum 6)) / [(X,3)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_AssDynamic. reflexivity. intros n H. inversion H. Qed.
Example pe_example2:
(X ::= ANum 3 ;; IFB BLe (AId X) (ANum 4) THEN X ::= ANum 4 ELSE SKIP FI)
/ [] \\ (SKIP;; SKIP) / [(X,4)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_IfTrue. reflexivity.
eapply PE_AssStatic. reflexivity. Qed.
Example pe_example3:
(X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI) / []
\\ (SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
(SKIP;; SKIP);; (SKIP;; Y ::= ANum 4)
ELSE SKIP;; SKIP FI)
/ [(X,3)].
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_If; intuition eauto; try solve by inversion.
econstructor. eapply PE_AssStatic. reflexivity.
eapply PE_IfFalse. reflexivity. econstructor.
reflexivity. reflexivity. Qed.
(* ================================================================= *)
(** ** Correctness of Partial Evaluation *)
(** Finally let's prove that this partial evaluator is correct! *)
Reserved Notation "c' '/' pe_st' '/' st '\\' st''"
(at level 40, pe_st' at level 39, st at level 39).
Inductive pe_ceval
(c':com) (pe_st':pe_state) (st:state) (st'':state) : Prop :=
| pe_ceval_intro : forall st',
c' / st \\ st' ->
pe_update st' pe_st' = st'' ->
c' / pe_st' / st \\ st''
where "c' '/' pe_st' '/' st '\\' st''" := (pe_ceval c' pe_st' st st'').
Hint Constructors pe_ceval.
Theorem pe_com_complete:
forall c pe_st pe_st' c', c / pe_st \\ c' / pe_st' ->
forall st st'',
(c / pe_update st pe_st \\ st'') ->
(c' / pe_st' / st \\ st'').
Proof. intros c pe_st pe_st' c' Hpe.
induction Hpe; intros st st'' Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
- (* PE_AssStatic *) econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_add.
rewrite -> H. reflexivity.
- (* PE_AssDynamic *) econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_remove.
reflexivity.
- (* PE_Seq *)
edestruct IHHpe1. eassumption. subst.
edestruct IHHpe2. eassumption.
eauto.
- (* PE_If *) inversion Heval; subst.
+ (* E'IfTrue *) edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption.
+ (* E_IfFalse *) edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_update.
rewrite <- assign_removes. eassumption.
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c', c / pe_st \\ c' / pe_st' ->
forall st st'',
(c' / pe_st' / st \\ st'') ->
(c / pe_update st pe_st \\ st'').
Proof. intros c pe_st pe_st' c' Hpe.
induction Hpe;
intros st st'' [st' Heval Heq];
try (inversion Heval; []; subst); auto.
- (* PE_AssStatic *) rewrite <- pe_update_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
- (* PE_AssDynamic *) rewrite <- pe_update_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
- (* PE_Seq *) eapply E_Seq; eauto.
- (* PE_IfTrue *) apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
- (* PE_IfFalse *) apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
- (* PE_If *)
inversion Heval; subst; inversion H7;
(eapply ceval_deterministic in H8; [| apply eval_assign]); subst.
+ (* E_IfTrue *)
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
+ (* E_IfFalse *)
rewrite -> pe_compare_update.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
Qed.
(** The main theorem. Thanks to David Menendez for this formulation! *)
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st \\ c' / pe_st' ->
forall st st'',
(c / pe_update st pe_st \\ st'') <->
(c' / pe_st' / st \\ st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
- (* -> *) apply pe_com_complete. apply H.
- (* <- *) apply pe_com_sound. apply H.
Qed.
(* ################################################################# *)
(** * Partial Evaluation of Loops *)
(** It may seem straightforward at first glance to extend the partial
evaluation relation [pe_com] above to loops. Indeed, many loops
are easy to deal with. Considered this repeated-squaring loop,
for example:
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END
If we know neither [X] nor [Y] statically, then the entire loop is
dynamic and the residual command should be the same. If we know
[X] but not [Y], then the loop can be unrolled all the way and the
residual command should be, for example,
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y)
if [X] is initially [3] (and finally [0]). In general, a loop is
easy to partially evaluate if the final partial state of the loop
body is equal to the initial state, or if its guard condition is
static.
But there are other loops for which it is hard to express the
residual program we want in Imp. For example, take this program
for checking whether [Y] is even or odd:
X ::= ANum 0;;
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
X ::= AMinus (ANum 1) (AId X)
END
The value of [X] alternates between [0] and [1] during the loop.
Ideally, we would like to unroll this loop, not all the way but
_two-fold_, into something like
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
IF BLe (ANum 1) (AId Y) THEN
Y ::= AMinus (AId Y) (ANum 1)
ELSE
X ::= ANum 1;; EXIT
FI
END;;
X ::= ANum 0
Unfortunately, there is no [EXIT] command in Imp. Without
extending the range of control structures available in our
language, the best we can do is to repeat loop-guard tests or add
flag variables. Neither option is terribly attractive.
Still, as a digression, below is an attempt at performing partial
evaluation on Imp commands. We add one more command argument
[c''] to the [pe_com] relation, which keeps track of a loop to
roll up. *)
Module Loop.
Reserved Notation "c1 '/' st '\\' c1' '/' st' '/' c''"
(at level 40, st at level 39, c1' at level 39, st' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> com -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st \\ SKIP / pe_st / SKIP
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st \\ SKIP / pe_add pe_st l n1 / SKIP
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st \\ (l ::= a1') / pe_remove pe_st l / SKIP
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2' c'',
c1 / pe_st \\ c1' / pe_st' / SKIP ->
c2 / pe_st' \\ c2' / pe_st'' / c'' ->
(c1 ;; c2) / pe_st \\ (c1' ;; c2') / pe_st'' / c''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1' c'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st \\ c1' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st \\ c1' / pe_st' / c''
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2' c'',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st \\ c2' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st \\ c2' / pe_st' / c''
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2' c'',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st \\ c1' / pe_st1 / c'' ->
c2 / pe_st \\ c2' / pe_st2 / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
\\ (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
/ c''
| PE_WhileEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 = BFalse ->
(WHILE b1 DO c1 END) / pe_st \\ SKIP / pe_st / SKIP
| PE_WhileLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st \\ c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' \\ c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(WHILE b1 DO c1 END) / pe_st \\ (c1';;c2') / pe_st'' / c2''
| PE_While : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st \\ c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' \\ c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(c2'' = SKIP \/ c2'' = WHILE b1 DO c1 END) ->
(WHILE b1 DO c1 END) / pe_st
\\ (IFB pe_bexp pe_st b1
THEN c1';; c2';; assign pe_st'' (pe_compare pe_st pe_st'')
ELSE assign pe_st (pe_compare pe_st pe_st'') FI)
/ pe_removes pe_st (pe_compare pe_st pe_st'')
/ c2''
| PE_WhileFixedEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 <> BFalse ->
(WHILE b1 DO c1 END) / pe_st \\ SKIP / pe_st / (WHILE b1 DO c1 END)
| PE_WhileFixedLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st \\ c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
\\ c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
\\ (WHILE BTrue DO SKIP END) / pe_st / SKIP
(* Because we have an infinite loop, we should actually
start to throw away the rest of the program:
(WHILE b1 DO c1 END) / pe_st
\\ SKIP / pe_st / (WHILE BTrue DO SKIP END) *)
| PE_WhileFixed : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st \\ c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
\\ c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
\\ (WHILE pe_bexp pe_st b1 DO c1';; c2' END) / pe_st / SKIP
where "c1 '/' st '\\' c1' '/' st' '/' c''" := (pe_com c1 st c1' st' c'').
Hint Constructors pe_com.
(* ================================================================= *)
(** ** Examples *)
Ltac step i :=
(eapply i; intuition eauto; try solve by inversion);
repeat (try eapply PE_Seq;
try (eapply PE_AssStatic; simpl; reflexivity);
try (eapply PE_AssDynamic;
[ simpl; reflexivity
| intuition eauto; solve by inversion ])).
Definition square_loop: com :=
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END.
Example pe_loop_example1:
square_loop / []
\\ (WHILE BLe (ANum 1) (AId X) DO
(Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1));; SKIP
END) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st / SKIP).
step PE_WhileFixed. step PE_WhileFixedEnd. reflexivity.
reflexivity. reflexivity. Qed.
Example pe_loop_example2:
(X ::= ANum 3;; square_loop) / []
\\ (SKIP;;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
SKIP) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileEnd.
inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example3:
(Z ::= ANum 3;; subtract_slowly) / []
\\ (SKIP;;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
WHILE BNot (BEq (AId X) (ANum 0)) DO
(SKIP;; X ::= AMinus (AId X) (ANum 1));; SKIP
END;;
SKIP;; Z ::= ANum 0
ELSE SKIP;; Z ::= ANum 1 FI;; SKIP
ELSE SKIP;; Z ::= ANum 2 FI;; SKIP
ELSE SKIP;; Z ::= ANum 3 FI) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_While.
step PE_While.
step PE_While.
step PE_WhileFixed.
step PE_WhileFixedEnd.
reflexivity. inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example4:
(X ::= ANum 0;;
WHILE BLe (AId X) (ANum 2) DO
X ::= AMinus (ANum 1) (AId X)
END) / [] \\ (SKIP;; WHILE BTrue DO SKIP END) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileFixedLoop.
step PE_WhileLoop.
step PE_WhileFixedEnd.
inversion H. reflexivity. reflexivity. reflexivity. Qed.
(* ================================================================= *)
(** ** Correctness *)
(** Because this partial evaluator can unroll a loop n-fold where n is
a (finite) integer greater than one, in order to show it correct
we need to perform induction not structurally on dynamic
evaluation but on the number of times dynamic evaluation enters a
loop body. *)
Reserved Notation "c1 '/' st '\\' st' '#' n"
(at level 40, st at level 39, st' at level 39).
Inductive ceval_count : com -> state -> state -> nat -> Prop :=
| E'Skip : forall st,
SKIP / st \\ st # 0
| E'Ass : forall st a1 n l,
aeval st a1 = n ->
(l ::= a1) / st \\ (t_update st l n) # 0
| E'Seq : forall c1 c2 st st' st'' n1 n2,
c1 / st \\ st' # n1 ->
c2 / st' \\ st'' # n2 ->
(c1 ;; c2) / st \\ st'' # (n1 + n2)
| E'IfTrue : forall st st' b1 c1 c2 n,
beval st b1 = true ->
c1 / st \\ st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st \\ st' # n
| E'IfFalse : forall st st' b1 c1 c2 n,
beval st b1 = false ->
c2 / st \\ st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st \\ st' # n
| E'WhileEnd : forall b1 st c1,
beval st b1 = false ->
(WHILE b1 DO c1 END) / st \\ st # 0
| E'WhileLoop : forall st st' st'' b1 c1 n1 n2,
beval st b1 = true ->
c1 / st \\ st' # n1 ->
(WHILE b1 DO c1 END) / st' \\ st'' # n2 ->
(WHILE b1 DO c1 END) / st \\ st'' # S (n1 + n2)
where "c1 '/' st '\\' st' # n" := (ceval_count c1 st st' n).
Hint Constructors ceval_count.
Theorem ceval_count_complete: forall c st st',
c / st \\ st' -> exists n, c / st \\ st' # n.
Proof. intros c st st' Heval.
induction Heval;
try inversion IHHeval1;
try inversion IHHeval2;
try inversion IHHeval;
eauto. Qed.
Theorem ceval_count_sound: forall c st st' n,
c / st \\ st' # n -> c / st \\ st'.
Proof. intros c st st' n Heval. induction Heval; eauto. Qed.
Theorem pe_compare_nil_lookup: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall V, pe_lookup pe_st1 V = pe_lookup pe_st2 V.
Proof. intros pe_st1 pe_st2 H V.
apply (pe_compare_correct pe_st1 pe_st2 V).
rewrite H. intro. inversion H0. Qed.
Theorem pe_compare_nil_update: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall st, pe_update st pe_st1 = pe_update st pe_st2.
Proof. intros pe_st1 pe_st2 H st.
apply functional_extensionality. intros V.
rewrite !pe_update_correct.
apply pe_compare_nil_lookup with (V:=V) in H.
rewrite H. reflexivity. Qed.
Reserved Notation "c' '/' pe_st' '/' c'' '/' st '\\' st'' '#' n"
(at level 40, pe_st' at level 39, c'' at level 39,
st at level 39, st'' at level 39).
Inductive pe_ceval_count (c':com) (pe_st':pe_state) (c'':com)
(st:state) (st'':state) (n:nat) : Prop :=
| pe_ceval_count_intro : forall st' n',
c' / st \\ st' ->
c'' / pe_update st' pe_st' \\ st'' # n' ->
n' <= n ->
c' / pe_st' / c'' / st \\ st'' # n
where "c' '/' pe_st' '/' c'' '/' st '\\' st'' '#' n" :=
(pe_ceval_count c' pe_st' c'' st st'' n).
Hint Constructors pe_ceval_count.
Lemma pe_ceval_count_le: forall c' pe_st' c'' st st'' n n',
n' <= n ->
c' / pe_st' / c'' / st \\ st'' # n' ->
c' / pe_st' / c'' / st \\ st'' # n.
Proof. intros c' pe_st' c'' st st'' n n' Hle H. inversion H.
econstructor; try eassumption. omega. Qed.
Theorem pe_com_complete:
forall c pe_st pe_st' c' c'', c / pe_st \\ c' / pe_st' / c'' ->
forall st st'' n,
(c / pe_update st pe_st \\ st'' # n) ->
(c' / pe_st' / c'' / st \\ st'' # n).
Proof. intros c pe_st pe_st' c' c'' Hpe.
induction Hpe; intros st st'' n Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
- (* PE_AssStatic *) econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_add.
rewrite -> H. apply E'Skip. auto.
- (* PE_AssDynamic *) econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_remove.
apply E'Skip. auto.
- (* PE_Seq *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
- (* PE_If *) inversion Heval; subst.
+ (* E'IfTrue *) edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption. eassumption.
+ (* E_IfFalse *) edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_update.
rewrite <- assign_removes. eassumption. eassumption.
- (* PE_WhileLoop *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
- (* PE_While *) inversion Heval; subst.
+ (* E_WhileEnd *) econstructor. apply E_IfFalse.
rewrite <- pe_bexp_correct. assumption.
apply eval_assign.
rewrite <- assign_removes. inversion H2; subst; auto.
auto.
+ (* E_WhileLoop *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor. apply E_IfTrue.
rewrite <- pe_bexp_correct. assumption.
repeat eapply E_Seq; eauto. apply eval_assign.
rewrite -> pe_compare_update, <- assign_removes. eassumption.
omega.
- (* PE_WhileFixedLoop *) exfalso.
generalize dependent (S (n1 + n2)). intros n.
clear - H H0 IHHpe1 IHHpe2. generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
+ (* E'WhileEnd *) rewrite pe_bexp_correct, H in H7. inversion H7.
+ (* E'WhileLoop *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_update _ _ H0) in H7.
apply H1 in H7; [| omega]. inversion H7.
- (* PE_WhileFixed *) generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
+ (* E'WhileEnd *) rewrite pe_bexp_correct in H8. eauto.
+ (* E'WhileLoop *) rewrite pe_bexp_correct in H5.
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_update _ _ H1) in H8.
apply H2 in H8; [| omega]. inversion H8.
econstructor; [ eapply E_WhileLoop; eauto | eassumption | omega].
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c' c'', c / pe_st \\ c' / pe_st' / c'' ->
forall st st'' n,
(c' / pe_st' / c'' / st \\ st'' # n) ->
(c / pe_update st pe_st \\ st'').
Proof. intros c pe_st pe_st' c' c'' Hpe.
induction Hpe;
intros st st'' n [st' n' Heval Heval' Hle];
try (inversion Heval; []; subst);
try (inversion Heval'; []; subst); eauto.
- (* PE_AssStatic *) rewrite <- pe_update_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
- (* PE_AssDynamic *) rewrite <- pe_update_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
- (* PE_Seq *) eapply E_Seq; eauto.
- (* PE_IfTrue *) apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
- (* PE_IfFalse *) apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
- (* PE_If *) inversion Heval; subst; inversion H7; subst; clear H7.
+ (* E_IfTrue *)
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
+ (* E_IfFalse *)
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite -> pe_compare_update in Heval'.
rewrite <- assign_removes in Heval'.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe2. eauto.
- (* PE_WhileEnd *) apply E_WhileEnd.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
- (* PE_WhileLoop *) eapply E_WhileLoop.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe1. eauto. eapply IHHpe2. eauto.
- (* PE_While *) inversion Heval; subst.
+ (* E_IfTrue *)
inversion H9. subst. clear H9.
inversion H10. subst. clear H10.
eapply ceval_deterministic in H11; [| apply eval_assign]. subst.
rewrite -> pe_compare_update in Heval'.
rewrite <- assign_removes in Heval'.
eapply E_WhileLoop. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
eapply IHHpe2. eauto.
+ (* E_IfFalse *) apply ceval_count_sound in Heval'.
eapply ceval_deterministic in H9; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
inversion H2; subst.
* (* c2'' = SKIP *) inversion Heval'. subst. apply E_WhileEnd.
rewrite -> pe_bexp_correct. assumption.
* (* c2'' = WHILE b1 DO c1 END *) assumption.
- (* PE_WhileFixedEnd *) eapply ceval_count_sound. apply Heval'.
- (* PE_WhileFixedLoop *)
apply loop_never_stops in Heval. inversion Heval.
- (* PE_WhileFixed *)
clear - H1 IHHpe1 IHHpe2 Heval.
remember (WHILE pe_bexp pe_st b1 DO c1';; c2' END) as c'.
induction Heval;
inversion Heqc'; subst; clear Heqc'.
+ (* E_WhileEnd *) apply E_WhileEnd.
rewrite pe_bexp_correct. assumption.
+ (* E_WhileLoop *)
assert (IHHeval2' := IHHeval2 (refl_equal _)).
apply ceval_count_complete in IHHeval2'. inversion IHHeval2'.
clear IHHeval1 IHHeval2 IHHeval2'.
inversion Heval1. subst.
eapply E_WhileLoop. rewrite pe_bexp_correct. assumption. eauto.
eapply IHHpe2. econstructor. eassumption.
rewrite <- (pe_compare_nil_update _ _ H1). eassumption. apply le_n.
Qed.
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st \\ c' / pe_st' / SKIP ->
forall st st'',
(c / pe_update st pe_st \\ st'') <->
(exists st', c' / st \\ st' /\ pe_update st' pe_st' = st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
- (* -> *) intros Heval.
apply ceval_count_complete in Heval. inversion Heval as [n Heval'].
apply pe_com_complete with (st:=st) (st'':=st'') (n:=n) in H.
inversion H as [? ? ? Hskip ?]. inversion Hskip. subst. eauto.
assumption.
- (* <- *) intros [st' [Heval Heq]]. subst st''.
eapply pe_com_sound in H. apply H.
econstructor. apply Heval. apply E'Skip. apply le_n.
Qed.
End Loop.
(* ################################################################# *)
(** * Partial Evaluation of Flowchart Programs *)
(** Instead of partially evaluating [WHILE] loops directly, the
standard approach to partially evaluating imperative programs is
to convert them into _flowcharts_. In other words, it turns out
that adding labels and jumps to our language makes it much easier
to partially evaluate. The result of partially evaluating a
flowchart is a residual flowchart. If we are lucky, the jumps in
the residual flowchart can be converted back to [WHILE] loops, but
that is not possible in general; we do not pursue it here. *)
(* ================================================================= *)
(** ** Basic blocks *)
(** A flowchart is made of _basic blocks_, which we represent with the
inductive type [block]. A basic block is a sequence of
assignments (the constructor [Assign]), concluding with a
conditional jump (the constructor [If]) or an unconditional jump
(the constructor [Goto]). The destinations of the jumps are
specified by _labels_, which can be of any type. Therefore, we
parameterize the [block] type by the type of labels. *)
Inductive block (Label:Type) : Type :=
| Goto : Label -> block Label
| If : bexp -> Label -> Label -> block Label
| Assign : id -> aexp -> block Label -> block Label.
Arguments Goto {Label} _.
Arguments If {Label} _ _ _.
Arguments Assign {Label} _ _ _.
(** We use the "even or odd" program, expressed above in Imp, as our
running example. Converting this program into a flowchart turns
out to require 4 labels, so we define the following type. *)
Inductive parity_label : Type :=
| entry : parity_label
| loop : parity_label
| body : parity_label
| done : parity_label.
(** The following [block] is the basic block found at the [body] label
of the example program. *)
Definition parity_body : block parity_label :=
Assign Y (AMinus (AId Y) (ANum 1))
(Assign X (AMinus (ANum 1) (AId X))
(Goto loop)).
(** To evaluate a basic block, given an initial state, is to compute
the final state and the label to jump to next. Because basic
blocks do not _contain_ loops or other control structures,
evaluation of basic blocks is a total function -- we don't need to
worry about non-termination. *)
Fixpoint keval {L:Type} (st:state) (k : block L) : state * L :=
match k with
| Goto l => (st, l)
| If b l1 l2 => (st, if beval st b then l1 else l2)
| Assign i a k => keval (t_update st i (aeval st a)) k
end.
Example keval_example:
keval empty_state parity_body
= (t_update (t_update empty_state Y 0) X 1, loop).
Proof. reflexivity. Qed.
(* ================================================================= *)
(** ** Flowchart programs *)
(** A flowchart program is simply a lookup function that maps labels
to basic blocks. Actually, some labels are _halting states_ and
do not map to any basic block. So, more precisely, a flowchart
[program] whose labels are of type [L] is a function from [L] to
[option (block L)]. *)
Definition program (L:Type) : Type := L -> option (block L).
Definition parity : program parity_label := fun l =>
match l with
| entry => Some (Assign X (ANum 0) (Goto loop))
| loop => Some (If (BLe (ANum 1) (AId Y)) body done)
| body => Some parity_body
| done => None (* halt *)
end.
(** Unlike a basic block, a program may not terminate, so we model the
evaluation of programs by an inductive relation [peval] rather
than a recursive function. *)
Inductive peval {L:Type} (p : program L)
: state -> L -> state -> L -> Prop :=
| E_None: forall st l,
p l = None ->
peval p st l st l
| E_Some: forall st l k st' l' st'' l'',
p l = Some k ->
keval st k = (st', l') ->
peval p st' l' st'' l'' ->
peval p st l st'' l''.
Example parity_eval: peval parity empty_state entry empty_state done.
Proof. erewrite f_equal with (f := fun st => peval _ _ _ st _).
eapply E_Some. reflexivity. reflexivity.
eapply E_Some. reflexivity. reflexivity.
apply E_None. reflexivity.
apply functional_extensionality. intros i. rewrite t_update_same; auto.
Qed.
(* ================================================================= *)
(** ** Partial Evaluation of Basic Blocks and Flowchart Programs *)
(** Partial evaluation changes the label type in a systematic way: if
the label type used to be [L], it becomes [pe_state * L]. So the
same label in the original program may be unfolded, or blown up,
into multiple labels by being paired with different partial
states. For example, the label [loop] in the [parity] program
will become two labels: [([(X,0)], loop)] and [([(X,1)], loop)].
This change of label type is reflected in the types of [pe_block]
and [pe_program] defined presently. *)
Fixpoint pe_block {L:Type} (pe_st:pe_state) (k : block L)
: block (pe_state * L) :=
match k with
| Goto l => Goto (pe_st, l)
| If b l1 l2 =>
match pe_bexp pe_st b with
| BTrue => Goto (pe_st, l1)
| BFalse => Goto (pe_st, l2)
| b' => If b' (pe_st, l1) (pe_st, l2)
end
| Assign i a k =>
match pe_aexp pe_st a with
| ANum n => pe_block (pe_add pe_st i n) k
| a' => Assign i a' (pe_block (pe_remove pe_st i) k)
end
end.
Example pe_block_example:
pe_block [(X,0)] parity_body
= Assign Y (AMinus (AId Y) (ANum 1)) (Goto ([(X,1)], loop)).
Proof. reflexivity. Qed.
Theorem pe_block_correct: forall (L:Type) st pe_st k st' pe_st' (l':L),
keval st (pe_block pe_st k) = (st', (pe_st', l')) ->
keval (pe_update st pe_st) k = (pe_update st' pe_st', l').
Proof. intros. generalize dependent pe_st. generalize dependent st.
induction k as [l | b l1 l2 | i a k];
intros st pe_st H.
- (* Goto *) inversion H; reflexivity.
- (* If *)
replace (keval st (pe_block pe_st (If b l1 l2)))
with (keval st (If (pe_bexp pe_st b) (pe_st, l1) (pe_st, l2)))
in H by (simpl; destruct (pe_bexp pe_st b); reflexivity).
simpl in *. rewrite pe_bexp_correct.
destruct (beval st (pe_bexp pe_st b)); inversion H; reflexivity.
- (* Assign *)
simpl in *. rewrite pe_aexp_correct.
destruct (pe_aexp pe_st a); simpl;
try solve [rewrite pe_update_update_add; apply IHk; apply H];
solve [rewrite pe_update_update_remove; apply IHk; apply H].
Qed.
Definition pe_program {L:Type} (p : program L)
: program (pe_state * L) :=
fun pe_l => match pe_l with (pe_st, l) =>
option_map (pe_block pe_st) (p l)
end.
Inductive pe_peval {L:Type} (p : program L)
(st:state) (pe_st:pe_state) (l:L) (st'o:state) (l':L) : Prop :=
| pe_peval_intro : forall st' pe_st',
peval (pe_program p) st (pe_st, l) st' (pe_st', l') ->
pe_update st' pe_st' = st'o ->
pe_peval p st pe_st l st'o l'.
Theorem pe_program_correct:
forall (L:Type) (p : program L) st pe_st l st'o l',
peval p (pe_update st pe_st) l st'o l' <->
pe_peval p st pe_st l st'o l'.
Proof. intros.
split.
- (* -> *) intros Heval.
remember (pe_update st pe_st) as sto.
generalize dependent pe_st. generalize dependent st.
induction Heval as
[ sto l Hlookup | sto l k st'o l' st''o l'' Hlookup Hkeval Heval ];
intros st pe_st Heqsto; subst sto.
+ (* E_None *) eapply pe_peval_intro. apply E_None.
simpl. rewrite Hlookup. reflexivity. reflexivity.
+ (* E_Some *)
remember (keval st (pe_block pe_st k)) as x.
destruct x as [st' [pe_st' l'_]].
symmetry in Heqx. erewrite pe_block_correct in Hkeval by apply Heqx.
inversion Hkeval. subst st'o l'_. clear Hkeval.
edestruct IHHeval. reflexivity. subst st''o. clear IHHeval.
eapply pe_peval_intro; [| reflexivity]. eapply E_Some; eauto.
simpl. rewrite Hlookup. reflexivity.
- (* <- *) intros [st' pe_st' Heval Heqst'o].
remember (pe_st, l) as pe_st_l.
remember (pe_st', l') as pe_st'_l'.
generalize dependent pe_st. generalize dependent l.
induction Heval as
[ st [pe_st_ l_] Hlookup
| st [pe_st_ l_] pe_k st' [pe_st'_ l'_] st'' [pe_st'' l'']
Hlookup Hkeval Heval ];
intros l pe_st Heqpe_st_l;
inversion Heqpe_st_l; inversion Heqpe_st'_l'; repeat subst.
+ (* E_None *) apply E_None. simpl in Hlookup.
destruct (p l'); [ solve [ inversion Hlookup ] | reflexivity ].
+ (* E_Some *)
simpl in Hlookup. remember (p l) as k.
destruct k as [k|]; inversion Hlookup; subst.
eapply E_Some; eauto. apply pe_block_correct. apply Hkeval.
Qed.
(** $Date: 2016-05-26 16:17:19 -0400 (Thu, 26 May 2016) $ *)
|
/*
* Wrapper for Xilinx MIG'd DDR2 controller
* The DDR2 controller have 5 wishbone slave interfaces,
* if more masters than that is needed, arbiters have to be added
*/
module xilinx_ddr2
(
// Inputs
input [31:0] wbm0_adr_i,
input [1:0] wbm0_bte_i,
input [2:0] wbm0_cti_i,
input wbm0_cyc_i,
input [31:0] wbm0_dat_i,
input [3:0] wbm0_sel_i,
input wbm0_stb_i,
input wbm0_we_i,
// Outputs
output wbm0_ack_o,
output wbm0_err_o,
output wbm0_rty_o,
output [31:0] wbm0_dat_o,
// Inputs
input [31:0] wbm1_adr_i,
input [1:0] wbm1_bte_i,
input [2:0] wbm1_cti_i,
input wbm1_cyc_i,
input [31:0] wbm1_dat_i,
input [3:0] wbm1_sel_i,
input wbm1_stb_i,
input wbm1_we_i,
// Outputs
output wbm1_ack_o,
output wbm1_err_o,
output wbm1_rty_o,
output [31:0] wbm1_dat_o,
// Inputs
input [31:0] wbm2_adr_i,
input [1:0] wbm2_bte_i,
input [2:0] wbm2_cti_i,
input wbm2_cyc_i,
input [31:0] wbm2_dat_i,
input [3:0] wbm2_sel_i,
input wbm2_stb_i,
input wbm2_we_i,
// Outputs
output wbm2_ack_o,
output wbm2_err_o,
output wbm2_rty_o,
output [31:0] wbm2_dat_o,
// Inputs
input [31:0] wbm3_adr_i,
input [1:0] wbm3_bte_i,
input [2:0] wbm3_cti_i,
input wbm3_cyc_i,
input [31:0] wbm3_dat_i,
input [3:0] wbm3_sel_i,
input wbm3_stb_i,
input wbm3_we_i,
// Outputs
output wbm3_ack_o,
output wbm3_err_o,
output wbm3_rty_o,
output [31:0] wbm3_dat_o,
// Inputs
input [31:0] wbm4_adr_i,
input [1:0] wbm4_bte_i,
input [2:0] wbm4_cti_i,
input wbm4_cyc_i,
input [31:0] wbm4_dat_i,
input [3:0] wbm4_sel_i,
input wbm4_stb_i,
input wbm4_we_i,
// Outputs
output wbm4_ack_o,
output wbm4_err_o,
output wbm4_rty_o,
output [31:0] wbm4_dat_o,
input wb_clk,
input wb_rst,
output [12:0] ddr2_a,
output [2:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output ddr2_rzq,
output ddr2_zio,
output ddr2_odt,
output ddr2_cke,
output ddr2_dm,
output ddr2_udm,
inout [15:0] ddr2_dq,
inout ddr2_dqs,
inout ddr2_dqs_n,
inout ddr2_udqs,
inout ddr2_udqs_n,
output ddr2_ck,
output ddr2_ck_n,
input ddr2_if_clk,
input ddr2_if_rst
,
output [31:0] ddr2_trace_data0_o,
output [31:0] ddr2_trace_data1_o,
output [31:0] ddr2_trace_data2_o,
output [31:0] ddr2_trace_data3_o,
output [31:0] ddr2_trace_data4_o,
output [31:0] ddr2_trace_data5_o
);
// Wires to the four slaves of the DDR2 interface
wire [31:0] wbs0_ram_adr_i;
wire [1:0] wbs0_ram_bte_i;
wire [2:0] wbs0_ram_cti_i;
wire wbs0_ram_cyc_i;
wire [31:0] wbs0_ram_dat_i;
wire [3:0] wbs0_ram_sel_i;
wire wbs0_ram_stb_i;
wire wbs0_ram_we_i;
wire wbs0_ram_ack_o;
wire [31:0] wbs0_ram_dat_o;
wire [31:0] wbs1_ram_adr_i;
wire [1:0] wbs1_ram_bte_i;
wire [2:0] wbs1_ram_cti_i;
wire wbs1_ram_cyc_i;
wire [31:0] wbs1_ram_dat_i;
wire [3:0] wbs1_ram_sel_i;
wire wbs1_ram_stb_i;
wire wbs1_ram_we_i;
wire wbs1_ram_ack_o;
wire [31:0] wbs1_ram_dat_o;
wire [31:0] wbs2_ram_adr_i;
wire [1:0] wbs2_ram_bte_i;
wire [2:0] wbs2_ram_cti_i;
wire wbs2_ram_cyc_i;
wire [31:0] wbs2_ram_dat_i;
wire [3:0] wbs2_ram_sel_i;
wire wbs2_ram_stb_i;
wire wbs2_ram_we_i;
wire wbs2_ram_ack_o;
wire [31:0] wbs2_ram_dat_o;
wire [31:0] wbs3_ram_adr_i;
wire [1:0] wbs3_ram_bte_i;
wire [2:0] wbs3_ram_cti_i;
wire wbs3_ram_cyc_i;
wire [31:0] wbs3_ram_dat_i;
wire [3:0] wbs3_ram_sel_i;
wire wbs3_ram_stb_i;
wire wbs3_ram_we_i;
wire wbs3_ram_ack_o;
wire [31:0] wbs3_ram_dat_o;
wire [31:0] wbs4_ram_adr_i;
wire [1:0] wbs4_ram_bte_i;
wire [2:0] wbs4_ram_cti_i;
wire wbs4_ram_cyc_i;
wire [31:0] wbs4_ram_dat_i;
wire [3:0] wbs4_ram_sel_i;
wire wbs4_ram_stb_i;
wire wbs4_ram_we_i;
wire wbs4_ram_ack_o;
wire [31:0] wbs4_ram_dat_o;
// assign masters to slaves
assign wbs0_ram_adr_i = wbm0_adr_i;
assign wbs0_ram_bte_i = wbm0_bte_i;
assign wbs0_ram_cti_i = wbm0_cti_i;
assign wbs0_ram_cyc_i = wbm0_cyc_i;
assign wbs0_ram_dat_i = wbm0_dat_i;
assign wbs0_ram_sel_i = wbm0_sel_i;
assign wbs0_ram_stb_i = wbm0_stb_i;
assign wbs0_ram_we_i = wbm0_we_i;
assign wbm0_ack_o = wbs0_ram_ack_o;
assign wbm0_dat_o = wbs0_ram_dat_o;
assign wbm0_err_o = 0;
assign wbm0_rty_o = 0;
assign wbs1_ram_adr_i = wbm1_adr_i;
assign wbs1_ram_bte_i = wbm1_bte_i;
assign wbs1_ram_cti_i = wbm1_cti_i;
assign wbs1_ram_cyc_i = wbm1_cyc_i;
assign wbs1_ram_dat_i = wbm1_dat_i;
assign wbs1_ram_sel_i = wbm1_sel_i;
assign wbs1_ram_stb_i = wbm1_stb_i;
assign wbs1_ram_we_i = wbm1_we_i;
assign wbm1_ack_o = wbs1_ram_ack_o;
assign wbm1_dat_o = wbs1_ram_dat_o;
assign wbm1_err_o = 0;
assign wbm1_rty_o = 0;
assign wbs2_ram_adr_i = wbm2_adr_i;
assign wbs2_ram_bte_i = wbm2_bte_i;
assign wbs2_ram_cti_i = wbm2_cti_i;
assign wbs2_ram_cyc_i = wbm2_cyc_i;
assign wbs2_ram_dat_i = wbm2_dat_i;
assign wbs2_ram_sel_i = wbm2_sel_i;
assign wbs2_ram_stb_i = wbm2_stb_i;
assign wbs2_ram_we_i = wbm2_we_i;
assign wbm2_ack_o = wbs2_ram_ack_o;
assign wbm2_dat_o = wbs2_ram_dat_o;
assign wbm2_err_o = 0;
assign wbm2_rty_o = 0;
assign wbs3_ram_adr_i = wbm3_adr_i;
assign wbs3_ram_bte_i = wbm3_bte_i;
assign wbs3_ram_cti_i = wbm3_cti_i;
assign wbs3_ram_cyc_i = wbm3_cyc_i;
assign wbs3_ram_dat_i = wbm3_dat_i;
assign wbs3_ram_sel_i = wbm3_sel_i;
assign wbs3_ram_stb_i = wbm3_stb_i;
assign wbs3_ram_we_i = wbm3_we_i;
assign wbm3_ack_o = wbs3_ram_ack_o;
assign wbm3_dat_o = wbs3_ram_dat_o;
assign wbm3_err_o = 0;
assign wbm3_rty_o = 0;
assign wbs4_ram_adr_i = wbm4_adr_i;
assign wbs4_ram_bte_i = wbm4_bte_i;
assign wbs4_ram_cti_i = wbm4_cti_i;
assign wbs4_ram_cyc_i = wbm4_cyc_i;
assign wbs4_ram_dat_i = wbm4_dat_i;
assign wbs4_ram_sel_i = wbm4_sel_i;
assign wbs4_ram_stb_i = wbm4_stb_i;
assign wbs4_ram_we_i = wbm4_we_i;
assign wbm4_ack_o = wbs4_ram_ack_o;
assign wbm4_dat_o = wbs4_ram_dat_o;
assign wbm4_err_o = 0;
assign wbm4_rty_o = 0;
xilinx_ddr2_if xilinx_ddr2_if0
(
.wb0_dat_o (wbs0_ram_dat_o),
.wb0_ack_o (wbs0_ram_ack_o),
.wb0_adr_i (wbs0_ram_adr_i[31:0]),
.wb0_stb_i (wbs0_ram_stb_i),
.wb0_cti_i (wbs0_ram_cti_i),
.wb0_bte_i (wbs0_ram_bte_i),
.wb0_cyc_i (wbs0_ram_cyc_i),
.wb0_we_i (wbs0_ram_we_i),
.wb0_sel_i (wbs0_ram_sel_i[3:0]),
.wb0_dat_i (wbs0_ram_dat_i[31:0]),
.wb1_dat_o (wbs1_ram_dat_o),
.wb1_ack_o (wbs1_ram_ack_o),
.wb1_adr_i (wbs1_ram_adr_i[31:0]),
.wb1_stb_i (wbs1_ram_stb_i),
.wb1_cti_i (wbs1_ram_cti_i),
.wb1_bte_i (wbs1_ram_bte_i),
.wb1_cyc_i (wbs1_ram_cyc_i),
.wb1_we_i (wbs1_ram_we_i),
.wb1_sel_i (wbs1_ram_sel_i[3:0]),
.wb1_dat_i (wbs1_ram_dat_i[31:0]),
.wb2_dat_o (wbs2_ram_dat_o),
.wb2_ack_o (wbs2_ram_ack_o),
.wb2_adr_i (wbs2_ram_adr_i[31:0]),
.wb2_stb_i (wbs2_ram_stb_i),
.wb2_cti_i (wbs2_ram_cti_i),
.wb2_bte_i (wbs2_ram_bte_i),
.wb2_cyc_i (wbs2_ram_cyc_i),
.wb2_we_i (wbs2_ram_we_i),
.wb2_sel_i (wbs2_ram_sel_i[3:0]),
.wb2_dat_i (wbs2_ram_dat_i[31:0]),
.wb3_dat_o (wbs3_ram_dat_o),
.wb3_ack_o (wbs3_ram_ack_o),
.wb3_adr_i (wbs3_ram_adr_i[31:0]),
.wb3_stb_i (wbs3_ram_stb_i),
.wb3_cti_i (wbs3_ram_cti_i),
.wb3_bte_i (wbs3_ram_bte_i),
.wb3_cyc_i (wbs3_ram_cyc_i),
.wb3_we_i (wbs3_ram_we_i),
.wb3_sel_i (wbs3_ram_sel_i[3:0]),
.wb3_dat_i (wbs3_ram_dat_i[31:0]),
.wb4_dat_o (wbs4_ram_dat_o),
.wb4_ack_o (wbs4_ram_ack_o),
.wb4_adr_i (wbs4_ram_adr_i[31:0]),
.wb4_stb_i (wbs4_ram_stb_i),
.wb4_cti_i (wbs4_ram_cti_i),
.wb4_bte_i (wbs4_ram_bte_i),
.wb4_cyc_i (wbs4_ram_cyc_i),
.wb4_we_i (wbs4_ram_we_i),
.wb4_sel_i (wbs4_ram_sel_i[3:0]),
.wb4_dat_i (wbs4_ram_dat_i[31:0]),
.ddr2_a (ddr2_a[12:0]),
.ddr2_ba (ddr2_ba),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_we_n (ddr2_we_n),
.ddr2_rzq (ddr2_rzq),
.ddr2_zio (ddr2_zio),
.ddr2_odt (ddr2_odt),
.ddr2_cke (ddr2_cke),
.ddr2_dm (ddr2_dm),
.ddr2_udm (ddr2_udm),
.ddr2_ck (ddr2_ck),
.ddr2_ck_n (ddr2_ck_n),
.ddr2_dq (ddr2_dq),
.ddr2_dqs (ddr2_dqs),
.ddr2_dqs_n (ddr2_dqs_n),
.ddr2_udqs (ddr2_udqs),
.ddr2_udqs_n (ddr2_udqs_n),
.ddr2_if_clk (ddr2_if_clk),
.ddr2_if_rst (ddr2_if_rst),
.wb_clk (wb_clk),
.wb_rst (wb_rst)
,
.ddr2_trace_data0_o (ddr2_trace_data0_o[31:0]),
.ddr2_trace_data1_o (ddr2_trace_data1_o[31:0]),
.ddr2_trace_data2_o (ddr2_trace_data2_o[31:0]),
.ddr2_trace_data3_o (ddr2_trace_data3_o[31:0]),
.ddr2_trace_data4_o (ddr2_trace_data4_o[31:0]),
.ddr2_trace_data5_o (ddr2_trace_data5_o[31:0])
);
endmodule //xilinx_ddr2 |
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
// > Achronix eFPGA technology sim models. User must first simulate the generated \
// > netlist before going to test it on board/custom chip.
// > Changelog: 1) Removed unused VCC/GND modules
// > 2) Altera comments here (?). Removed.
// > 3) Reusing LUT sim model, removed wrong wires and parameters.
module PADIN (output padout, input padin);
assign padout = padin;
endmodule
module PADOUT (output padout, input padin, input oe);
assign padout = padin;
assign oe = oe;
endmodule
module LUT4 (output dout,
input din0, din1, din2, din3);
parameter [15:0] lut_function = 16'hFFFF;
reg combout_rt;
wire dataa_w;
wire datab_w;
wire datac_w;
wire datad_w;
assign dataa_w = din0;
assign datab_w = din1;
assign datac_w = din2;
assign datad_w = din3;
function lut_data;
input [15:0] mask;
input dataa, datab, datac, datad;
reg [7:0] s3;
reg [3:0] s2;
reg [1:0] s1;
begin
s3 = datad ? mask[15:8] : mask[7:0];
s2 = datac ? s3[7:4] : s3[3:0];
s1 = datab ? s2[3:2] : s2[1:0];
lut_data = dataa ? s1[1] : s1[0];
end
endfunction
always @(dataa_w or datab_w or datac_w or datad_w) begin
combout_rt = lut_data(lut_function, dataa_w, datab_w,
datac_w, datad_w);
end
assign dout = combout_rt & 1'b1;
endmodule
module DFF (output q,
input d, ck);
reg q;
always @(posedge ck)
q <= d;
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:14:12 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59,
n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73,
n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87,
n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100,
n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111,
n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122,
n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144,
n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155,
n156, n157, n158, n159, n160, n161, n162, n163, n164, n165;
NAND2XLTS U62 ( .A(n49), .B(n133), .Y(n135) );
NAND2XLTS U63 ( .A(n48), .B(n136), .Y(n138) );
NOR2X4TS U64 ( .A(n70), .B(n75), .Y(n134) );
NAND2X4TS U65 ( .A(n132), .B(n99), .Y(n71) );
OR2X2TS U66 ( .A(n102), .B(in1[15]), .Y(n99) );
BUFX3TS U67 ( .A(n77), .Y(n75) );
OA21XLTS U68 ( .A0(n163), .A1(in1[3]), .B0(in1[2]), .Y(n152) );
NOR2X4TS U69 ( .A(n77), .B(n133), .Y(n76) );
OR2X2TS U70 ( .A(n105), .B(in1[14]), .Y(n49) );
AND2X2TS U71 ( .A(in1[0]), .B(in2[0]), .Y(n160) );
INVX3TS U72 ( .A(n46), .Y(n74) );
CLKXOR2X2TS U73 ( .A(n107), .B(in2[13]), .Y(n108) );
NOR2XLTS U74 ( .A(n106), .B(n145), .Y(n107) );
NOR2XLTS U75 ( .A(n111), .B(n145), .Y(n112) );
NAND2XLTS U76 ( .A(n122), .B(add_sub), .Y(n123) );
INVX2TS U77 ( .A(n130), .Y(n62) );
INVX2TS U78 ( .A(in1[7]), .Y(n61) );
NOR2X2TS U79 ( .A(n115), .B(n145), .Y(n116) );
NAND2X6TS U80 ( .A(n88), .B(in1[5]), .Y(n87) );
INVX6TS U81 ( .A(n92), .Y(n88) );
NAND2X6TS U82 ( .A(n69), .B(in1[4]), .Y(n92) );
NOR2X2TS U83 ( .A(n119), .B(n145), .Y(n90) );
INVX4TS U84 ( .A(add_sub), .Y(n145) );
INVX8TS U85 ( .A(in2[4]), .Y(n93) );
CLKINVX3TS U86 ( .A(in2[6]), .Y(n78) );
NOR2X1TS U87 ( .A(n122), .B(in2[10]), .Y(n111) );
OAI21XLTS U88 ( .A0(in2[0]), .A1(in2[1]), .B0(add_sub), .Y(n149) );
XNOR2X2TS U89 ( .A(n110), .B(in2[12]), .Y(n127) );
AND2X8TS U90 ( .A(n137), .B(n48), .Y(n46) );
OR2X4TS U91 ( .A(n108), .B(in1[13]), .Y(n48) );
NAND2BX2TS U92 ( .AN(n55), .B(n127), .Y(n52) );
NAND2X4TS U93 ( .A(n62), .B(n61), .Y(n60) );
NAND2X4TS U94 ( .A(n113), .B(n84), .Y(n122) );
NOR2X4TS U95 ( .A(n120), .B(in2[8]), .Y(n113) );
NAND2X6TS U96 ( .A(n76), .B(n74), .Y(n73) );
AND2X2TS U97 ( .A(n99), .B(n131), .Y(n47) );
NAND2X2TS U98 ( .A(n102), .B(in1[15]), .Y(n131) );
NAND2X2TS U99 ( .A(n105), .B(in1[14]), .Y(n133) );
XNOR2X2TS U100 ( .A(n101), .B(in2[15]), .Y(n102) );
NAND2X2TS U101 ( .A(n108), .B(in1[13]), .Y(n136) );
XNOR2X2TS U102 ( .A(n104), .B(in2[14]), .Y(n105) );
NAND2X6TS U103 ( .A(n64), .B(n60), .Y(n59) );
NAND2X2TS U104 ( .A(n103), .B(add_sub), .Y(n104) );
OAI21X2TS U105 ( .A0(n103), .A1(in2[14]), .B0(add_sub), .Y(n101) );
NAND2BX2TS U106 ( .AN(in2[13]), .B(n106), .Y(n103) );
NAND2X2TS U107 ( .A(n111), .B(n83), .Y(n109) );
XOR2X1TS U108 ( .A(n157), .B(n156), .Y(res[5]) );
XOR2X1TS U109 ( .A(n165), .B(n164), .Y(res[3]) );
XOR2XLTS U110 ( .A(n154), .B(n153), .Y(res[4]) );
XOR2XLTS U111 ( .A(n160), .B(n148), .Y(res[1]) );
NAND2X6TS U112 ( .A(n50), .B(add_sub), .Y(n117) );
XOR2X1TS U113 ( .A(n163), .B(in1[3]), .Y(n164) );
OAI21X1TS U114 ( .A0(n160), .A1(in1[1]), .B0(n158), .Y(n159) );
NAND2X6TS U115 ( .A(n80), .B(n51), .Y(n50) );
XOR2X1TS U116 ( .A(n158), .B(in1[1]), .Y(n148) );
AOI2BB1XLTS U117 ( .A0N(in2[0]), .A1N(in1[0]), .B0(n160), .Y(res[0]) );
INVX3TS U118 ( .A(in2[5]), .Y(n98) );
INVX16TS U119 ( .A(in2[2]), .Y(n95) );
NAND2X4TS U120 ( .A(n118), .B(add_sub), .Y(n94) );
NAND2X4TS U121 ( .A(n59), .B(n58), .Y(n144) );
NAND4X8TS U122 ( .A(n96), .B(n100), .C(n146), .D(n95), .Y(n118) );
NOR2X8TS U123 ( .A(n137), .B(n136), .Y(n77) );
NAND2X8TS U124 ( .A(n53), .B(n52), .Y(n137) );
NAND3X8TS U125 ( .A(n93), .B(n146), .C(n95), .Y(n82) );
XOR2X2TS U126 ( .A(n132), .B(n47), .Y(res[15]) );
NAND2BX4TS U127 ( .AN(in2[7]), .B(n115), .Y(n120) );
NOR2X4TS U128 ( .A(n109), .B(in2[12]), .Y(n106) );
OR3X1TS U129 ( .A(in2[2]), .B(in2[0]), .C(in2[1]), .Y(n150) );
NOR2X4TS U130 ( .A(n82), .B(n81), .Y(n119) );
NAND2X4TS U131 ( .A(n96), .B(n100), .Y(n81) );
CLKINVX3TS U132 ( .A(n82), .Y(n51) );
INVX2TS U133 ( .A(in2[11]), .Y(n83) );
NAND2X1TS U134 ( .A(n130), .B(in1[7]), .Y(n58) );
INVX2TS U135 ( .A(in2[9]), .Y(n84) );
INVX2TS U136 ( .A(in1[12]), .Y(n55) );
BUFX3TS U137 ( .A(n46), .Y(n70) );
XNOR2X1TS U138 ( .A(n155), .B(in1[5]), .Y(n156) );
NOR2BX1TS U139 ( .AN(n86), .B(n154), .Y(n85) );
INVX2TS U140 ( .A(in1[6]), .Y(n68) );
XOR2XLTS U141 ( .A(n64), .B(n63), .Y(res[7]) );
XOR2X1TS U142 ( .A(n130), .B(in1[7]), .Y(n63) );
XOR2X1TS U143 ( .A(n126), .B(n56), .Y(res[12]) );
XNOR2X1TS U144 ( .A(n138), .B(n137), .Y(res[13]) );
AFHCINX4TS U145 ( .CIN(n141), .B(n142), .A(in1[9]), .S(res[9]), .CO(n140) );
XNOR2X2TS U146 ( .A(n151), .B(in2[3]), .Y(n163) );
XOR2X1TS U147 ( .A(n127), .B(in1[12]), .Y(n56) );
INVX2TS U148 ( .A(n127), .Y(n54) );
NAND2X2TS U149 ( .A(n109), .B(add_sub), .Y(n110) );
OR2X8TS U150 ( .A(n125), .B(in1[6]), .Y(n67) );
NAND2X8TS U151 ( .A(n72), .B(n73), .Y(n132) );
OAI2BB1X4TS U152 ( .A0N(n55), .A1N(n54), .B0(n126), .Y(n53) );
XNOR2X1TS U153 ( .A(n124), .B(n57), .Y(res[6]) );
XOR2X1TS U154 ( .A(n125), .B(n68), .Y(n57) );
NAND2X8TS U155 ( .A(n66), .B(n65), .Y(n64) );
NAND2X2TS U156 ( .A(n125), .B(in1[6]), .Y(n65) );
NAND2X8TS U157 ( .A(n124), .B(n67), .Y(n66) );
OR2X1TS U158 ( .A(n69), .B(in1[4]), .Y(n86) );
XNOR2X1TS U159 ( .A(n69), .B(in1[4]), .Y(n153) );
XOR2X4TS U160 ( .A(n94), .B(n93), .Y(n69) );
OAI21X2TS U161 ( .A0(n132), .A1(n131), .B0(n71), .Y(res[16]) );
OAI21X4TS U162 ( .A0(n46), .A1(n77), .B0(n49), .Y(n72) );
INVX16TS U163 ( .A(in2[1]), .Y(n146) );
NAND4X8TS U164 ( .A(n98), .B(n96), .C(n78), .D(n100), .Y(n79) );
NOR2X8TS U165 ( .A(n82), .B(n79), .Y(n115) );
NOR2X8TS U166 ( .A(n81), .B(in2[5]), .Y(n80) );
NOR2BX1TS U167 ( .AN(n92), .B(n85), .Y(n157) );
NAND2X8TS U168 ( .A(n89), .B(n87), .Y(n124) );
NAND2X8TS U169 ( .A(n91), .B(n155), .Y(n89) );
XOR2X4TS U170 ( .A(n90), .B(in2[5]), .Y(n155) );
NAND2X8TS U171 ( .A(n92), .B(n97), .Y(n91) );
INVX12TS U172 ( .A(in2[3]), .Y(n96) );
INVX16TS U173 ( .A(in2[0]), .Y(n100) );
INVX2TS U174 ( .A(in1[5]), .Y(n97) );
XOR2X2TS U175 ( .A(n135), .B(n134), .Y(res[14]) );
ADDFHX4TS U176 ( .A(n140), .B(in1[10]), .CI(n139), .CO(n128), .S(res[10]) );
XOR2X4TS U177 ( .A(n116), .B(in2[7]), .Y(n130) );
NOR2XLTS U178 ( .A(n145), .B(n100), .Y(n147) );
XOR2X1TS U179 ( .A(n114), .B(in2[9]), .Y(n142) );
CLKXOR2X2TS U180 ( .A(n112), .B(in2[11]), .Y(n129) );
NOR2X1TS U181 ( .A(n113), .B(n145), .Y(n114) );
XNOR2X4TS U182 ( .A(n117), .B(in2[6]), .Y(n125) );
NAND2X1TS U183 ( .A(n120), .B(add_sub), .Y(n121) );
XNOR2X1TS U184 ( .A(n121), .B(in2[8]), .Y(n143) );
XNOR2X1TS U185 ( .A(n123), .B(in2[10]), .Y(n139) );
ADDFHX4TS U186 ( .A(n129), .B(in1[11]), .CI(n128), .CO(n126), .S(res[11]) );
AFHCONX2TS U187 ( .A(in1[8]), .B(n144), .CI(n143), .CON(n141), .S(res[8]) );
XNOR2X1TS U188 ( .A(n147), .B(n146), .Y(n158) );
XNOR2X1TS U189 ( .A(n149), .B(in2[2]), .Y(n161) );
NAND2X1TS U190 ( .A(add_sub), .B(n150), .Y(n151) );
AOI22X1TS U191 ( .A0(n161), .A1(n152), .B0(in1[3]), .B1(n163), .Y(n154) );
OAI2BB1X1TS U192 ( .A0N(n160), .A1N(in1[1]), .B0(n159), .Y(n162) );
CMPR32X2TS U193 ( .A(in1[2]), .B(n162), .C(n161), .CO(n165), .S(res[2]) );
initial $sdf_annotate("Approx_adder_GeArN8R2P2_syn.sdf");
endmodule
|
/*
-- ============================================================================
-- FILE NAME : if_reg.v
-- DESCRIPTION : IF¥¹¥Æ©`¥¸¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ÐÂÒ×÷³É
-- ============================================================================
*/
/********** ¹²Í¨¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** e¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "isa.h"
`include "cpu.h"
/********** ¥â¥¸¥å©`¥ë **********/
module if_reg (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
input wire clk, // ¥¯¥í¥Ã¥¯
input wire reset, // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Õ¥§¥Ã¥Á¥Ç©`¥¿ **********/
input wire [`WordDataBus] insn, // ¥Õ¥§¥Ã¥Á¤·¤¿ÃüÁî
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
input wire stall, // ¥¹¥È©`¥ë
input wire flush, // ¥Õ¥é¥Ã¥·¥å
input wire [`WordAddrBus] new_pc, // Ф·¤¤¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
input wire br_taken, // ·Ö᪤γÉÁ¢
input wire [`WordAddrBus] br_addr, // ·ÖáªÏÈ¥¢¥É¥ì¥¹
/********** IF/ID¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
output reg [`WordAddrBus] if_pc, // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
output reg [`WordDataBus] if_insn, // ÃüÁî
output reg if_en // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
);
/********** ¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
/* ·ÇͬÆڥꥻ¥Ã¥È */
if_pc <= #1 `RESET_VECTOR;
if_insn <= #1 `ISA_NOP;
if_en <= #1 `DISABLE;
end else begin
/* ¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿¤Î¸üР*/
if (stall == `DISABLE) begin
if (flush == `ENABLE) begin // ¥Õ¥é¥Ã¥·¥å
if_pc <= #1 new_pc;
if_insn <= #1 `ISA_NOP;
if_en <= #1 `DISABLE;
end else if (br_taken == `ENABLE) begin // ·Ö᪤γÉÁ¢
if_pc <= #1 br_addr;
if_insn <= #1 insn;
if_en <= #1 `ENABLE;
end else begin // ´Î¤Î¥¢¥É¥ì¥¹
if_pc <= #1 if_pc + 1'd1;
if_insn <= #1 insn;
if_en <= #1 `ENABLE;
end
end
end
end
endmodule
|
// mmio_if.v
// Generated using ACDS version 14.0 200 at 2017.05.28.12:09:58
`timescale 1 ps / 1 ps
module mmio_if (
input wire clk_i_clk, // clk_i.clk
output wire [14:0] hps_ddr3_mem_a, // hps_ddr3.mem_a
output wire [2:0] hps_ddr3_mem_ba, // .mem_ba
output wire hps_ddr3_mem_ck, // .mem_ck
output wire hps_ddr3_mem_ck_n, // .mem_ck_n
output wire hps_ddr3_mem_cke, // .mem_cke
output wire hps_ddr3_mem_cs_n, // .mem_cs_n
output wire hps_ddr3_mem_ras_n, // .mem_ras_n
output wire hps_ddr3_mem_cas_n, // .mem_cas_n
output wire hps_ddr3_mem_we_n, // .mem_we_n
output wire hps_ddr3_mem_reset_n, // .mem_reset_n
inout wire [31:0] hps_ddr3_mem_dq, // .mem_dq
inout wire [3:0] hps_ddr3_mem_dqs, // .mem_dqs
inout wire [3:0] hps_ddr3_mem_dqs_n, // .mem_dqs_n
output wire hps_ddr3_mem_odt, // .mem_odt
output wire [3:0] hps_ddr3_mem_dm, // .mem_dm
input wire hps_ddr3_oct_rzqin, // .oct_rzqin
output wire [79:0] cpc_keys_keys, // cpc_keys.keys
output wire uart_tx_o, // uart.tx_o
input wire uart_rx_i, // .rx_i
output wire uart_reset_o, // .reset_o
input wire uart_clk_i_clk // uart_clk_i.clk
);
wire hps_0_h2f_reset_reset; // hps_0:h2f_rst_n -> [Fake_UART_0:reset_i, rst_controller:reset_in0, rst_controller_001:reset_in0]
wire hps_0_h2f_lw_axi_master_awvalid; // hps_0:h2f_lw_AWVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awvalid
wire [2:0] hps_0_h2f_lw_axi_master_arsize; // hps_0:h2f_lw_ARSIZE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arsize
wire [1:0] hps_0_h2f_lw_axi_master_arlock; // hps_0:h2f_lw_ARLOCK -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arlock
wire [3:0] hps_0_h2f_lw_axi_master_awcache; // hps_0:h2f_lw_AWCACHE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awcache
wire hps_0_h2f_lw_axi_master_arready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_arready -> hps_0:h2f_lw_ARREADY
wire [11:0] hps_0_h2f_lw_axi_master_arid; // hps_0:h2f_lw_ARID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arid
wire hps_0_h2f_lw_axi_master_rready; // hps_0:h2f_lw_RREADY -> mm_interconnect_0:hps_0_h2f_lw_axi_master_rready
wire hps_0_h2f_lw_axi_master_bready; // hps_0:h2f_lw_BREADY -> mm_interconnect_0:hps_0_h2f_lw_axi_master_bready
wire [2:0] hps_0_h2f_lw_axi_master_awsize; // hps_0:h2f_lw_AWSIZE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awsize
wire [2:0] hps_0_h2f_lw_axi_master_awprot; // hps_0:h2f_lw_AWPROT -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awprot
wire hps_0_h2f_lw_axi_master_arvalid; // hps_0:h2f_lw_ARVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arvalid
wire [2:0] hps_0_h2f_lw_axi_master_arprot; // hps_0:h2f_lw_ARPROT -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arprot
wire [11:0] hps_0_h2f_lw_axi_master_bid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bid -> hps_0:h2f_lw_BID
wire [3:0] hps_0_h2f_lw_axi_master_arlen; // hps_0:h2f_lw_ARLEN -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arlen
wire hps_0_h2f_lw_axi_master_awready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_awready -> hps_0:h2f_lw_AWREADY
wire [11:0] hps_0_h2f_lw_axi_master_awid; // hps_0:h2f_lw_AWID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awid
wire hps_0_h2f_lw_axi_master_bvalid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bvalid -> hps_0:h2f_lw_BVALID
wire [11:0] hps_0_h2f_lw_axi_master_wid; // hps_0:h2f_lw_WID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wid
wire [1:0] hps_0_h2f_lw_axi_master_awlock; // hps_0:h2f_lw_AWLOCK -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awlock
wire [1:0] hps_0_h2f_lw_axi_master_awburst; // hps_0:h2f_lw_AWBURST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awburst
wire [1:0] hps_0_h2f_lw_axi_master_bresp; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bresp -> hps_0:h2f_lw_BRESP
wire [3:0] hps_0_h2f_lw_axi_master_wstrb; // hps_0:h2f_lw_WSTRB -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wstrb
wire hps_0_h2f_lw_axi_master_rvalid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rvalid -> hps_0:h2f_lw_RVALID
wire [31:0] hps_0_h2f_lw_axi_master_wdata; // hps_0:h2f_lw_WDATA -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wdata
wire hps_0_h2f_lw_axi_master_wready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_wready -> hps_0:h2f_lw_WREADY
wire [1:0] hps_0_h2f_lw_axi_master_arburst; // hps_0:h2f_lw_ARBURST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arburst
wire [31:0] hps_0_h2f_lw_axi_master_rdata; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rdata -> hps_0:h2f_lw_RDATA
wire [20:0] hps_0_h2f_lw_axi_master_araddr; // hps_0:h2f_lw_ARADDR -> mm_interconnect_0:hps_0_h2f_lw_axi_master_araddr
wire [3:0] hps_0_h2f_lw_axi_master_arcache; // hps_0:h2f_lw_ARCACHE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arcache
wire [3:0] hps_0_h2f_lw_axi_master_awlen; // hps_0:h2f_lw_AWLEN -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awlen
wire [20:0] hps_0_h2f_lw_axi_master_awaddr; // hps_0:h2f_lw_AWADDR -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awaddr
wire [11:0] hps_0_h2f_lw_axi_master_rid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rid -> hps_0:h2f_lw_RID
wire hps_0_h2f_lw_axi_master_wvalid; // hps_0:h2f_lw_WVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wvalid
wire [1:0] hps_0_h2f_lw_axi_master_rresp; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rresp -> hps_0:h2f_lw_RRESP
wire hps_0_h2f_lw_axi_master_wlast; // hps_0:h2f_lw_WLAST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wlast
wire hps_0_h2f_lw_axi_master_rlast; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rlast -> hps_0:h2f_lw_RLAST
wire [31:0] mm_interconnect_0_mmio_0_avalon_slave_0_writedata; // mm_interconnect_0:mmio_0_avalon_slave_0_writedata -> mmio_0:data_i
wire [5:0] mm_interconnect_0_mmio_0_avalon_slave_0_address; // mm_interconnect_0:mmio_0_avalon_slave_0_address -> mmio_0:addr_i
wire mm_interconnect_0_mmio_0_avalon_slave_0_write; // mm_interconnect_0:mmio_0_avalon_slave_0_write -> mmio_0:write_i
wire mm_interconnect_0_mmio_0_avalon_slave_0_read; // mm_interconnect_0:mmio_0_avalon_slave_0_read -> mmio_0:read_i
wire [31:0] mm_interconnect_0_mmio_0_avalon_slave_0_readdata; // mmio_0:data_o -> mm_interconnect_0:mmio_0_avalon_slave_0_readdata
wire [31:0] mm_interconnect_0_fake_uart_0_fake_uart_writedata; // mm_interconnect_0:Fake_UART_0_fake_uart_writedata -> Fake_UART_0:data_i
wire [5:0] mm_interconnect_0_fake_uart_0_fake_uart_address; // mm_interconnect_0:Fake_UART_0_fake_uart_address -> Fake_UART_0:addr_i
wire mm_interconnect_0_fake_uart_0_fake_uart_write; // mm_interconnect_0:Fake_UART_0_fake_uart_write -> Fake_UART_0:write_i
wire mm_interconnect_0_fake_uart_0_fake_uart_read; // mm_interconnect_0:Fake_UART_0_fake_uart_read -> Fake_UART_0:read_i
wire [31:0] mm_interconnect_0_fake_uart_0_fake_uart_readdata; // Fake_UART_0:data_o -> mm_interconnect_0:Fake_UART_0_fake_uart_readdata
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [mm_interconnect_0:Fake_UART_0_reset_sink_reset_bridge_in_reset_reset, mm_interconnect_0:mmio_0_reset_sink_reset_bridge_in_reset_reset, mmio_0:reset_i]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> mm_interconnect_0:hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset
mmio mmio_0 (
.addr_i (mm_interconnect_0_mmio_0_avalon_slave_0_address), // avalon_slave_0.address
.data_i (mm_interconnect_0_mmio_0_avalon_slave_0_writedata), // .writedata
.data_o (mm_interconnect_0_mmio_0_avalon_slave_0_readdata), // .readdata
.write_i (mm_interconnect_0_mmio_0_avalon_slave_0_write), // .write
.read_i (mm_interconnect_0_mmio_0_avalon_slave_0_read), // .read
.clk_i (clk_i_clk), // clock_sink.clk
.reset_i (rst_controller_reset_out_reset), // reset_sink.reset
.keys (cpc_keys_keys) // keys.keys
);
mmio_if_hps_0 #(
.F2S_Width (0),
.S2F_Width (0)
) hps_0 (
.mem_a (hps_ddr3_mem_a), // memory.mem_a
.mem_ba (hps_ddr3_mem_ba), // .mem_ba
.mem_ck (hps_ddr3_mem_ck), // .mem_ck
.mem_ck_n (hps_ddr3_mem_ck_n), // .mem_ck_n
.mem_cke (hps_ddr3_mem_cke), // .mem_cke
.mem_cs_n (hps_ddr3_mem_cs_n), // .mem_cs_n
.mem_ras_n (hps_ddr3_mem_ras_n), // .mem_ras_n
.mem_cas_n (hps_ddr3_mem_cas_n), // .mem_cas_n
.mem_we_n (hps_ddr3_mem_we_n), // .mem_we_n
.mem_reset_n (hps_ddr3_mem_reset_n), // .mem_reset_n
.mem_dq (hps_ddr3_mem_dq), // .mem_dq
.mem_dqs (hps_ddr3_mem_dqs), // .mem_dqs
.mem_dqs_n (hps_ddr3_mem_dqs_n), // .mem_dqs_n
.mem_odt (hps_ddr3_mem_odt), // .mem_odt
.mem_dm (hps_ddr3_mem_dm), // .mem_dm
.oct_rzqin (hps_ddr3_oct_rzqin), // .oct_rzqin
.h2f_rst_n (hps_0_h2f_reset_reset), // h2f_reset.reset_n
.h2f_lw_axi_clk (clk_i_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (hps_0_h2f_lw_axi_master_awid), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.h2f_lw_AWLEN (hps_0_h2f_lw_axi_master_awlen), // .awlen
.h2f_lw_AWSIZE (hps_0_h2f_lw_axi_master_awsize), // .awsize
.h2f_lw_AWBURST (hps_0_h2f_lw_axi_master_awburst), // .awburst
.h2f_lw_AWLOCK (hps_0_h2f_lw_axi_master_awlock), // .awlock
.h2f_lw_AWCACHE (hps_0_h2f_lw_axi_master_awcache), // .awcache
.h2f_lw_AWPROT (hps_0_h2f_lw_axi_master_awprot), // .awprot
.h2f_lw_AWVALID (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.h2f_lw_AWREADY (hps_0_h2f_lw_axi_master_awready), // .awready
.h2f_lw_WID (hps_0_h2f_lw_axi_master_wid), // .wid
.h2f_lw_WDATA (hps_0_h2f_lw_axi_master_wdata), // .wdata
.h2f_lw_WSTRB (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.h2f_lw_WLAST (hps_0_h2f_lw_axi_master_wlast), // .wlast
.h2f_lw_WVALID (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.h2f_lw_WREADY (hps_0_h2f_lw_axi_master_wready), // .wready
.h2f_lw_BID (hps_0_h2f_lw_axi_master_bid), // .bid
.h2f_lw_BRESP (hps_0_h2f_lw_axi_master_bresp), // .bresp
.h2f_lw_BVALID (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.h2f_lw_BREADY (hps_0_h2f_lw_axi_master_bready), // .bready
.h2f_lw_ARID (hps_0_h2f_lw_axi_master_arid), // .arid
.h2f_lw_ARADDR (hps_0_h2f_lw_axi_master_araddr), // .araddr
.h2f_lw_ARLEN (hps_0_h2f_lw_axi_master_arlen), // .arlen
.h2f_lw_ARSIZE (hps_0_h2f_lw_axi_master_arsize), // .arsize
.h2f_lw_ARBURST (hps_0_h2f_lw_axi_master_arburst), // .arburst
.h2f_lw_ARLOCK (hps_0_h2f_lw_axi_master_arlock), // .arlock
.h2f_lw_ARCACHE (hps_0_h2f_lw_axi_master_arcache), // .arcache
.h2f_lw_ARPROT (hps_0_h2f_lw_axi_master_arprot), // .arprot
.h2f_lw_ARVALID (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.h2f_lw_ARREADY (hps_0_h2f_lw_axi_master_arready), // .arready
.h2f_lw_RID (hps_0_h2f_lw_axi_master_rid), // .rid
.h2f_lw_RDATA (hps_0_h2f_lw_axi_master_rdata), // .rdata
.h2f_lw_RRESP (hps_0_h2f_lw_axi_master_rresp), // .rresp
.h2f_lw_RLAST (hps_0_h2f_lw_axi_master_rlast), // .rlast
.h2f_lw_RVALID (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.h2f_lw_RREADY (hps_0_h2f_lw_axi_master_rready) // .rready
);
fake_uart fake_uart_0 (
.clk_i (clk_i_clk), // clock_sink.clk
.reset_i (~hps_0_h2f_reset_reset), // reset_sink.reset
.uart_tx_o (uart_tx_o), // conduit_end.tx_o
.uart_rx_i (uart_rx_i), // .rx_i
.reset_o (uart_reset_o), // .reset_o
.data_i (mm_interconnect_0_fake_uart_0_fake_uart_writedata), // fake_uart.writedata
.data_o (mm_interconnect_0_fake_uart_0_fake_uart_readdata), // .readdata
.write_i (mm_interconnect_0_fake_uart_0_fake_uart_write), // .write
.addr_i (mm_interconnect_0_fake_uart_0_fake_uart_address), // .address
.read_i (mm_interconnect_0_fake_uart_0_fake_uart_read), // .read
.uart_clk_i (uart_clk_i_clk) // clock_sink_1.clk
);
mmio_if_mm_interconnect_0 mm_interconnect_0 (
.hps_0_h2f_lw_axi_master_awid (hps_0_h2f_lw_axi_master_awid), // hps_0_h2f_lw_axi_master.awid
.hps_0_h2f_lw_axi_master_awaddr (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.hps_0_h2f_lw_axi_master_awlen (hps_0_h2f_lw_axi_master_awlen), // .awlen
.hps_0_h2f_lw_axi_master_awsize (hps_0_h2f_lw_axi_master_awsize), // .awsize
.hps_0_h2f_lw_axi_master_awburst (hps_0_h2f_lw_axi_master_awburst), // .awburst
.hps_0_h2f_lw_axi_master_awlock (hps_0_h2f_lw_axi_master_awlock), // .awlock
.hps_0_h2f_lw_axi_master_awcache (hps_0_h2f_lw_axi_master_awcache), // .awcache
.hps_0_h2f_lw_axi_master_awprot (hps_0_h2f_lw_axi_master_awprot), // .awprot
.hps_0_h2f_lw_axi_master_awvalid (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.hps_0_h2f_lw_axi_master_awready (hps_0_h2f_lw_axi_master_awready), // .awready
.hps_0_h2f_lw_axi_master_wid (hps_0_h2f_lw_axi_master_wid), // .wid
.hps_0_h2f_lw_axi_master_wdata (hps_0_h2f_lw_axi_master_wdata), // .wdata
.hps_0_h2f_lw_axi_master_wstrb (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.hps_0_h2f_lw_axi_master_wlast (hps_0_h2f_lw_axi_master_wlast), // .wlast
.hps_0_h2f_lw_axi_master_wvalid (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.hps_0_h2f_lw_axi_master_wready (hps_0_h2f_lw_axi_master_wready), // .wready
.hps_0_h2f_lw_axi_master_bid (hps_0_h2f_lw_axi_master_bid), // .bid
.hps_0_h2f_lw_axi_master_bresp (hps_0_h2f_lw_axi_master_bresp), // .bresp
.hps_0_h2f_lw_axi_master_bvalid (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.hps_0_h2f_lw_axi_master_bready (hps_0_h2f_lw_axi_master_bready), // .bready
.hps_0_h2f_lw_axi_master_arid (hps_0_h2f_lw_axi_master_arid), // .arid
.hps_0_h2f_lw_axi_master_araddr (hps_0_h2f_lw_axi_master_araddr), // .araddr
.hps_0_h2f_lw_axi_master_arlen (hps_0_h2f_lw_axi_master_arlen), // .arlen
.hps_0_h2f_lw_axi_master_arsize (hps_0_h2f_lw_axi_master_arsize), // .arsize
.hps_0_h2f_lw_axi_master_arburst (hps_0_h2f_lw_axi_master_arburst), // .arburst
.hps_0_h2f_lw_axi_master_arlock (hps_0_h2f_lw_axi_master_arlock), // .arlock
.hps_0_h2f_lw_axi_master_arcache (hps_0_h2f_lw_axi_master_arcache), // .arcache
.hps_0_h2f_lw_axi_master_arprot (hps_0_h2f_lw_axi_master_arprot), // .arprot
.hps_0_h2f_lw_axi_master_arvalid (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.hps_0_h2f_lw_axi_master_arready (hps_0_h2f_lw_axi_master_arready), // .arready
.hps_0_h2f_lw_axi_master_rid (hps_0_h2f_lw_axi_master_rid), // .rid
.hps_0_h2f_lw_axi_master_rdata (hps_0_h2f_lw_axi_master_rdata), // .rdata
.hps_0_h2f_lw_axi_master_rresp (hps_0_h2f_lw_axi_master_rresp), // .rresp
.hps_0_h2f_lw_axi_master_rlast (hps_0_h2f_lw_axi_master_rlast), // .rlast
.hps_0_h2f_lw_axi_master_rvalid (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.hps_0_h2f_lw_axi_master_rready (hps_0_h2f_lw_axi_master_rready), // .rready
.clk_0_clk_clk (clk_i_clk), // clk_0_clk.clk
.Fake_UART_0_reset_sink_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // Fake_UART_0_reset_sink_reset_bridge_in_reset.reset
.hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.mmio_0_reset_sink_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // mmio_0_reset_sink_reset_bridge_in_reset.reset
.Fake_UART_0_fake_uart_address (mm_interconnect_0_fake_uart_0_fake_uart_address), // Fake_UART_0_fake_uart.address
.Fake_UART_0_fake_uart_write (mm_interconnect_0_fake_uart_0_fake_uart_write), // .write
.Fake_UART_0_fake_uart_read (mm_interconnect_0_fake_uart_0_fake_uart_read), // .read
.Fake_UART_0_fake_uart_readdata (mm_interconnect_0_fake_uart_0_fake_uart_readdata), // .readdata
.Fake_UART_0_fake_uart_writedata (mm_interconnect_0_fake_uart_0_fake_uart_writedata), // .writedata
.mmio_0_avalon_slave_0_address (mm_interconnect_0_mmio_0_avalon_slave_0_address), // mmio_0_avalon_slave_0.address
.mmio_0_avalon_slave_0_write (mm_interconnect_0_mmio_0_avalon_slave_0_write), // .write
.mmio_0_avalon_slave_0_read (mm_interconnect_0_mmio_0_avalon_slave_0_read), // .read
.mmio_0_avalon_slave_0_readdata (mm_interconnect_0_mmio_0_avalon_slave_0_readdata), // .readdata
.mmio_0_avalon_slave_0_writedata (mm_interconnect_0_mmio_0_avalon_slave_0_writedata) // .writedata
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~hps_0_h2f_reset_reset), // reset_in0.reset
.clk (clk_i_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~hps_0_h2f_reset_reset), // reset_in0.reset
.clk (clk_i_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Reset: Push button, active low
*/
input wire reset,
/*
* GPIO
*/
input wire [3:0] sw,
output wire [2:0] led,
/*
* I2C for board management
*/
inout wire i2c_scl,
inout wire i2c_sda,
/*
* Ethernet: QSFP28
*/
output wire qsfp0_tx1_p,
output wire qsfp0_tx1_n,
input wire qsfp0_rx1_p,
input wire qsfp0_rx1_n,
output wire qsfp0_tx2_p,
output wire qsfp0_tx2_n,
input wire qsfp0_rx2_p,
input wire qsfp0_rx2_n,
output wire qsfp0_tx3_p,
output wire qsfp0_tx3_n,
input wire qsfp0_rx3_p,
input wire qsfp0_rx3_n,
output wire qsfp0_tx4_p,
output wire qsfp0_tx4_n,
input wire qsfp0_rx4_p,
input wire qsfp0_rx4_n,
// input wire qsfp0_mgt_refclk_0_p,
// input wire qsfp0_mgt_refclk_0_n,
input wire qsfp0_mgt_refclk_1_p,
input wire qsfp0_mgt_refclk_1_n,
output wire qsfp0_modsell,
output wire qsfp0_resetl,
input wire qsfp0_modprsl,
input wire qsfp0_intl,
output wire qsfp0_lpmode,
output wire qsfp0_refclk_reset,
output wire [1:0] qsfp0_fs,
output wire qsfp1_tx1_p,
output wire qsfp1_tx1_n,
input wire qsfp1_rx1_p,
input wire qsfp1_rx1_n,
output wire qsfp1_tx2_p,
output wire qsfp1_tx2_n,
input wire qsfp1_rx2_p,
input wire qsfp1_rx2_n,
output wire qsfp1_tx3_p,
output wire qsfp1_tx3_n,
input wire qsfp1_rx3_p,
input wire qsfp1_rx3_n,
output wire qsfp1_tx4_p,
output wire qsfp1_tx4_n,
input wire qsfp1_rx4_p,
input wire qsfp1_rx4_n,
// input wire qsfp1_mgt_refclk_0_p,
// input wire qsfp1_mgt_refclk_0_n,
// input wire qsfp1_mgt_refclk_1_p,
// input wire qsfp1_mgt_refclk_1_n,
output wire qsfp1_modsell,
output wire qsfp1_resetl,
input wire qsfp1_modprsl,
input wire qsfp1_intl,
output wire qsfp1_lpmode,
output wire qsfp1_refclk_reset,
output wire [1:0] qsfp1_fs,
/*
* UART: 500000 bps, 8N1
*/
output wire uart_rxd,
input wire uart_txd
);
// Clock and reset
wire cfgmclk_int;
wire clk_161mhz_ref_int;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
// Internal 156.25 MHz clock
wire clk_156mhz_int;
wire rst_156mhz_int;
wire mmcm_rst;
wire mmcm_locked;
wire mmcm_clkfb;
// MMCM instance
// 161.13 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 800 MHz to 1600 MHz
// M = 64, D = 11 sets Fvco = 937.5 MHz (in range)
// Divide by 7.5 to get output frequency of 125 MHz
MMCME4_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(7.5),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(64),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(11),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(6.206),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_161mhz_ref_int),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(4),
.N(4),
.RATE(156000)
)
debounce_switch_inst (
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
.in({sw}),
.out({sw_int})
);
wire uart_txd_int;
sync_signal #(
.WIDTH(1),
.N(2)
)
sync_signal_inst (
.clk(clk_156mhz_int),
.in({uart_txd}),
.out({uart_txd_int})
);
// SI570 I2C
wire i2c_scl_i;
wire i2c_scl_o = 1'b1;
wire i2c_scl_t = 1'b1;
wire i2c_sda_i;
wire i2c_sda_o = 1'b1;
wire i2c_sda_t = 1'b1;
assign i2c_scl_i = i2c_scl;
assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
assign i2c_sda_i = i2c_sda;
assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
// startupe3 instance
wire cfgmclk;
STARTUPE3
startupe3_inst (
.CFGCLK(),
.CFGMCLK(cfgmclk),
.DI(4'd0),
.DO(),
.DTS(1'b1),
.EOS(),
.FCSBO(1'b0),
.FCSBTS(1'b1),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(1'b0),
.USRCCLKTS(1'b1),
.USRDONEO(1'b0),
.USRDONETS(1'b1)
);
BUFG
cfgmclk_bufg_inst (
.I(cfgmclk),
.O(cfgmclk_int)
);
// configure SI5335 clock generators
reg qsfp_refclk_reset_reg = 1'b1;
reg sys_reset_reg = 1'b1;
reg [9:0] reset_timer_reg = 0;
assign mmcm_rst = sys_reset_reg;
always @(posedge cfgmclk_int) begin
if (&reset_timer_reg) begin
if (qsfp_refclk_reset_reg) begin
qsfp_refclk_reset_reg <= 1'b0;
reset_timer_reg <= 0;
end else begin
qsfp_refclk_reset_reg <= 1'b0;
sys_reset_reg <= 1'b0;
end
end else begin
reset_timer_reg <= reset_timer_reg + 1;
end
if (!reset) begin
qsfp_refclk_reset_reg <= 1'b1;
sys_reset_reg <= 1'b1;
reset_timer_reg <= 0;
end
end
// XGMII 10G PHY
assign qsfp0_modsell = 1'b0;
assign qsfp0_resetl = 1'b1;
assign qsfp0_lpmode = 1'b0;
assign qsfp0_refclk_reset = qsfp_refclk_reset_reg;
assign qsfp0_fs = 2'b10;
wire qsfp0_tx_clk_1_int;
wire qsfp0_tx_rst_1_int;
wire [63:0] qsfp0_txd_1_int;
wire [7:0] qsfp0_txc_1_int;
wire qsfp0_rx_clk_1_int;
wire qsfp0_rx_rst_1_int;
wire [63:0] qsfp0_rxd_1_int;
wire [7:0] qsfp0_rxc_1_int;
wire qsfp0_tx_clk_2_int;
wire qsfp0_tx_rst_2_int;
wire [63:0] qsfp0_txd_2_int;
wire [7:0] qsfp0_txc_2_int;
wire qsfp0_rx_clk_2_int;
wire qsfp0_rx_rst_2_int;
wire [63:0] qsfp0_rxd_2_int;
wire [7:0] qsfp0_rxc_2_int;
wire qsfp0_tx_clk_3_int;
wire qsfp0_tx_rst_3_int;
wire [63:0] qsfp0_txd_3_int;
wire [7:0] qsfp0_txc_3_int;
wire qsfp0_rx_clk_3_int;
wire qsfp0_rx_rst_3_int;
wire [63:0] qsfp0_rxd_3_int;
wire [7:0] qsfp0_rxc_3_int;
wire qsfp0_tx_clk_4_int;
wire qsfp0_tx_rst_4_int;
wire [63:0] qsfp0_txd_4_int;
wire [7:0] qsfp0_txc_4_int;
wire qsfp0_rx_clk_4_int;
wire qsfp0_rx_rst_4_int;
wire [63:0] qsfp0_rxd_4_int;
wire [7:0] qsfp0_rxc_4_int;
assign qsfp1_modsell = 1'b0;
assign qsfp1_resetl = 1'b1;
assign qsfp1_lpmode = 1'b0;
assign qsfp1_refclk_reset = qsfp_refclk_reset_reg;
assign qsfp1_fs = 2'b10;
wire qsfp1_tx_clk_1_int;
wire qsfp1_tx_rst_1_int;
wire [63:0] qsfp1_txd_1_int;
wire [7:0] qsfp1_txc_1_int;
wire qsfp1_rx_clk_1_int;
wire qsfp1_rx_rst_1_int;
wire [63:0] qsfp1_rxd_1_int;
wire [7:0] qsfp1_rxc_1_int;
wire qsfp1_tx_clk_2_int;
wire qsfp1_tx_rst_2_int;
wire [63:0] qsfp1_txd_2_int;
wire [7:0] qsfp1_txc_2_int;
wire qsfp1_rx_clk_2_int;
wire qsfp1_rx_rst_2_int;
wire [63:0] qsfp1_rxd_2_int;
wire [7:0] qsfp1_rxc_2_int;
wire qsfp1_tx_clk_3_int;
wire qsfp1_tx_rst_3_int;
wire [63:0] qsfp1_txd_3_int;
wire [7:0] qsfp1_txc_3_int;
wire qsfp1_rx_clk_3_int;
wire qsfp1_rx_rst_3_int;
wire [63:0] qsfp1_rxd_3_int;
wire [7:0] qsfp1_rxc_3_int;
wire qsfp1_tx_clk_4_int;
wire qsfp1_tx_rst_4_int;
wire [63:0] qsfp1_txd_4_int;
wire [7:0] qsfp1_txc_4_int;
wire qsfp1_rx_clk_4_int;
wire qsfp1_rx_rst_4_int;
wire [63:0] qsfp1_rxd_4_int;
wire [7:0] qsfp1_rxc_4_int;
wire qsfp0_rx_block_lock_1;
wire qsfp0_rx_block_lock_2;
wire qsfp0_rx_block_lock_3;
wire qsfp0_rx_block_lock_4;
wire qsfp1_rx_block_lock_1;
wire qsfp1_rx_block_lock_2;
wire qsfp1_rx_block_lock_3;
wire qsfp1_rx_block_lock_4;
wire [7:0] qsfp_gtpowergood;
wire qsfp0_mgt_refclk_1;
wire qsfp0_mgt_refclk_1_int;
wire qsfp0_mgt_refclk_1_bufg;
assign clk_161mhz_ref_int = qsfp0_mgt_refclk_1_bufg;
wire [7:0] gt_txclkout;
wire gt_txusrclk;
wire [7:0] gt_rxclkout;
wire [7:0] gt_rxusrclk;
wire gt_reset_tx_done;
wire gt_reset_rx_done;
wire [7:0] gt_txprgdivresetdone;
wire [7:0] gt_txpmaresetdone;
wire [7:0] gt_rxprgdivresetdone;
wire [7:0] gt_rxpmaresetdone;
wire gt_tx_reset = ~((>_txprgdivresetdone) & (>_txpmaresetdone));
wire gt_rx_reset = ~>_rxpmaresetdone;
reg gt_userclk_tx_active = 1'b0;
reg [7:0] gt_userclk_rx_active = 1'b0;
IBUFDS_GTE4 ibufds_gte4_qsfp0_mgt_refclk_1_inst (
.I (qsfp0_mgt_refclk_1_p),
.IB (qsfp0_mgt_refclk_1_n),
.CEB (1'b0),
.O (qsfp0_mgt_refclk_1),
.ODIV2 (qsfp0_mgt_refclk_1_int)
);
BUFG_GT bufg_gt_refclk_inst (
.CE (&qsfp_gtpowergood),
.CEMASK (1'b1),
.CLR (1'b0),
.CLRMASK (1'b1),
.DIV (3'd0),
.I (qsfp0_mgt_refclk_1_int),
.O (qsfp0_mgt_refclk_1_bufg)
);
BUFG_GT bufg_gt_tx_usrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gt_tx_reset),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (gt_txclkout[0]),
.O (gt_txusrclk)
);
assign clk_156mhz_int = gt_txusrclk;
always @(posedge gt_txusrclk, posedge gt_tx_reset) begin
if (gt_tx_reset) begin
gt_userclk_tx_active <= 1'b0;
end else begin
gt_userclk_tx_active <= 1'b1;
end
end
genvar n;
generate
for (n = 0; n < 8; n = n + 1) begin
BUFG_GT bufg_gt_rx_usrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gt_rx_reset),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (gt_rxclkout[n]),
.O (gt_rxusrclk[n])
);
always @(posedge gt_rxusrclk[n], posedge gt_rx_reset) begin
if (gt_rx_reset) begin
gt_userclk_rx_active[n] <= 1'b0;
end else begin
gt_userclk_rx_active[n] <= 1'b1;
end
end
end
endgenerate
sync_reset #(
.N(4)
)
sync_reset_156mhz_inst (
.clk(clk_156mhz_int),
.rst(~gt_reset_tx_done),
.out(rst_156mhz_int)
);
wire [5:0] qsfp0_gt_txheader_1;
wire [63:0] qsfp0_gt_txdata_1;
wire qsfp0_gt_rxgearboxslip_1;
wire [5:0] qsfp0_gt_rxheader_1;
wire [1:0] qsfp0_gt_rxheadervalid_1;
wire [63:0] qsfp0_gt_rxdata_1;
wire [1:0] qsfp0_gt_rxdatavalid_1;
wire [5:0] qsfp0_gt_txheader_2;
wire [63:0] qsfp0_gt_txdata_2;
wire qsfp0_gt_rxgearboxslip_2;
wire [5:0] qsfp0_gt_rxheader_2;
wire [1:0] qsfp0_gt_rxheadervalid_2;
wire [63:0] qsfp0_gt_rxdata_2;
wire [1:0] qsfp0_gt_rxdatavalid_2;
wire [5:0] qsfp0_gt_txheader_3;
wire [63:0] qsfp0_gt_txdata_3;
wire qsfp0_gt_rxgearboxslip_3;
wire [5:0] qsfp0_gt_rxheader_3;
wire [1:0] qsfp0_gt_rxheadervalid_3;
wire [63:0] qsfp0_gt_rxdata_3;
wire [1:0] qsfp0_gt_rxdatavalid_3;
wire [5:0] qsfp0_gt_txheader_4;
wire [63:0] qsfp0_gt_txdata_4;
wire qsfp0_gt_rxgearboxslip_4;
wire [5:0] qsfp0_gt_rxheader_4;
wire [1:0] qsfp0_gt_rxheadervalid_4;
wire [63:0] qsfp0_gt_rxdata_4;
wire [1:0] qsfp0_gt_rxdatavalid_4;
wire [5:0] qsfp1_gt_txheader_1;
wire [63:0] qsfp1_gt_txdata_1;
wire qsfp1_gt_rxgearboxslip_1;
wire [5:0] qsfp1_gt_rxheader_1;
wire [1:0] qsfp1_gt_rxheadervalid_1;
wire [63:0] qsfp1_gt_rxdata_1;
wire [1:0] qsfp1_gt_rxdatavalid_1;
wire [5:0] qsfp1_gt_txheader_2;
wire [63:0] qsfp1_gt_txdata_2;
wire qsfp1_gt_rxgearboxslip_2;
wire [5:0] qsfp1_gt_rxheader_2;
wire [1:0] qsfp1_gt_rxheadervalid_2;
wire [63:0] qsfp1_gt_rxdata_2;
wire [1:0] qsfp1_gt_rxdatavalid_2;
wire [5:0] qsfp1_gt_txheader_3;
wire [63:0] qsfp1_gt_txdata_3;
wire qsfp1_gt_rxgearboxslip_3;
wire [5:0] qsfp1_gt_rxheader_3;
wire [1:0] qsfp1_gt_rxheadervalid_3;
wire [63:0] qsfp1_gt_rxdata_3;
wire [1:0] qsfp1_gt_rxdatavalid_3;
wire [5:0] qsfp1_gt_txheader_4;
wire [63:0] qsfp1_gt_txdata_4;
wire qsfp1_gt_rxgearboxslip_4;
wire [5:0] qsfp1_gt_rxheader_4;
wire [1:0] qsfp1_gt_rxheadervalid_4;
wire [63:0] qsfp1_gt_rxdata_4;
wire [1:0] qsfp1_gt_rxdatavalid_4;
gtwizard_ultrascale_0
qsfp_gty_inst (
.gtwiz_userclk_tx_active_in(>_userclk_tx_active),
.gtwiz_userclk_rx_active_in(>_userclk_rx_active),
.gtwiz_reset_clk_freerun_in(clk_125mhz_int),
.gtwiz_reset_all_in(rst_125mhz_int),
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
.gtwiz_reset_tx_datapath_in(1'b0),
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
.gtwiz_reset_rx_datapath_in(1'b0),
.gtwiz_reset_rx_cdr_stable_out(),
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
.gtrefclk00_in({2{qsfp0_mgt_refclk_1}}),
.qpll0outclk_out(),
.qpll0outrefclk_out(),
.gtyrxn_in({qsfp0_rx4_n, qsfp0_rx3_n, qsfp0_rx2_n, qsfp0_rx1_n, qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}),
.gtyrxp_in({qsfp0_rx4_p, qsfp0_rx3_p, qsfp0_rx2_p, qsfp0_rx1_p, qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}),
.rxusrclk_in(gt_rxusrclk),
.rxusrclk2_in(gt_rxusrclk),
.gtwiz_userdata_tx_in({qsfp0_gt_txdata_4, qsfp0_gt_txdata_3, qsfp0_gt_txdata_2, qsfp0_gt_txdata_1, qsfp1_gt_txdata_4, qsfp1_gt_txdata_3, qsfp1_gt_txdata_2, qsfp1_gt_txdata_1}),
.txheader_in({qsfp0_gt_txheader_4, qsfp0_gt_txheader_3, qsfp0_gt_txheader_2, qsfp0_gt_txheader_1, qsfp1_gt_txheader_4, qsfp1_gt_txheader_3, qsfp1_gt_txheader_2, qsfp1_gt_txheader_1}),
.txsequence_in({8{1'b0}}),
.txusrclk_in({8{gt_txusrclk}}),
.txusrclk2_in({8{gt_txusrclk}}),
.gtpowergood_out(qsfp_gtpowergood),
.gtytxn_out({qsfp0_tx4_n, qsfp0_tx3_n, qsfp0_tx2_n, qsfp0_tx1_n, qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}),
.gtytxp_out({qsfp0_tx4_p, qsfp0_tx3_p, qsfp0_tx2_p, qsfp0_tx1_p, qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}),
.rxgearboxslip_in({qsfp0_gt_rxgearboxslip_4, qsfp0_gt_rxgearboxslip_3, qsfp0_gt_rxgearboxslip_2, qsfp0_gt_rxgearboxslip_1, qsfp1_gt_rxgearboxslip_4, qsfp1_gt_rxgearboxslip_3, qsfp1_gt_rxgearboxslip_2, qsfp1_gt_rxgearboxslip_1}),
.gtwiz_userdata_rx_out({qsfp0_gt_rxdata_4, qsfp0_gt_rxdata_3, qsfp0_gt_rxdata_2, qsfp0_gt_rxdata_1, qsfp1_gt_rxdata_4, qsfp1_gt_rxdata_3, qsfp1_gt_rxdata_2, qsfp1_gt_rxdata_1}),
.rxdatavalid_out({qsfp0_gt_rxdatavalid_4, qsfp0_gt_rxdatavalid_3, qsfp0_gt_rxdatavalid_2, qsfp0_gt_rxdatavalid_1, qsfp1_gt_rxdatavalid_4, qsfp1_gt_rxdatavalid_3, qsfp1_gt_rxdatavalid_2, qsfp1_gt_rxdatavalid_1}),
.rxheader_out({qsfp0_gt_rxheader_4, qsfp0_gt_rxheader_3, qsfp0_gt_rxheader_2, qsfp0_gt_rxheader_1, qsfp1_gt_rxheader_4, qsfp1_gt_rxheader_3, qsfp1_gt_rxheader_2, qsfp1_gt_rxheader_1}),
.rxheadervalid_out({qsfp0_gt_rxheadervalid_4, qsfp0_gt_rxheadervalid_3, qsfp0_gt_rxheadervalid_2, qsfp0_gt_rxheadervalid_1, qsfp1_gt_rxheadervalid_4, qsfp1_gt_rxheadervalid_3, qsfp1_gt_rxheadervalid_2, qsfp1_gt_rxheadervalid_1}),
.rxoutclk_out(gt_rxclkout),
.rxpmaresetdone_out(gt_rxpmaresetdone),
.rxprgdivresetdone_out(gt_rxprgdivresetdone),
.rxstartofseq_out(),
.txoutclk_out(gt_txclkout),
.txpmaresetdone_out(gt_txpmaresetdone),
.txprgdivresetdone_out(gt_txprgdivresetdone)
);
assign qsfp0_tx_clk_1_int = clk_156mhz_int;
assign qsfp0_tx_rst_1_int = rst_156mhz_int;
assign qsfp0_rx_clk_1_int = gt_rxusrclk[4];
sync_reset #(
.N(4)
)
qsfp0_rx_rst_1_reset_sync_inst (
.clk(qsfp0_rx_clk_1_int),
.rst(~gt_reset_rx_done),
.out(qsfp0_rx_rst_1_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp0_phy_1_inst (
.tx_clk(qsfp0_tx_clk_1_int),
.tx_rst(qsfp0_tx_rst_1_int),
.rx_clk(qsfp0_rx_clk_1_int),
.rx_rst(qsfp0_rx_rst_1_int),
.xgmii_txd(qsfp0_txd_1_int),
.xgmii_txc(qsfp0_txc_1_int),
.xgmii_rxd(qsfp0_rxd_1_int),
.xgmii_rxc(qsfp0_rxc_1_int),
.serdes_tx_data(qsfp0_gt_txdata_1),
.serdes_tx_hdr(qsfp0_gt_txheader_1),
.serdes_rx_data(qsfp0_gt_rxdata_1),
.serdes_rx_hdr(qsfp0_gt_rxheader_1),
.serdes_rx_bitslip(qsfp0_gt_rxgearboxslip_1),
.rx_block_lock(qsfp0_rx_block_lock_1),
.rx_high_ber()
);
assign qsfp0_tx_clk_2_int = clk_156mhz_int;
assign qsfp0_tx_rst_2_int = rst_156mhz_int;
assign qsfp0_rx_clk_2_int = gt_rxusrclk[5];
sync_reset #(
.N(4)
)
qsfp0_rx_rst_2_reset_sync_inst (
.clk(qsfp0_rx_clk_2_int),
.rst(~gt_reset_rx_done),
.out(qsfp0_rx_rst_2_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp0_phy_2_inst (
.tx_clk(qsfp0_tx_clk_2_int),
.tx_rst(qsfp0_tx_rst_2_int),
.rx_clk(qsfp0_rx_clk_2_int),
.rx_rst(qsfp0_rx_rst_2_int),
.xgmii_txd(qsfp0_txd_2_int),
.xgmii_txc(qsfp0_txc_2_int),
.xgmii_rxd(qsfp0_rxd_2_int),
.xgmii_rxc(qsfp0_rxc_2_int),
.serdes_tx_data(qsfp0_gt_txdata_2),
.serdes_tx_hdr(qsfp0_gt_txheader_2),
.serdes_rx_data(qsfp0_gt_rxdata_2),
.serdes_rx_hdr(qsfp0_gt_rxheader_2),
.serdes_rx_bitslip(qsfp0_gt_rxgearboxslip_2),
.rx_block_lock(qsfp0_rx_block_lock_2),
.rx_high_ber()
);
assign qsfp0_tx_clk_3_int = clk_156mhz_int;
assign qsfp0_tx_rst_3_int = rst_156mhz_int;
assign qsfp0_rx_clk_3_int = gt_rxusrclk[6];
sync_reset #(
.N(4)
)
qsfp0_rx_rst_3_reset_sync_inst (
.clk(qsfp0_rx_clk_3_int),
.rst(~gt_reset_rx_done),
.out(qsfp0_rx_rst_3_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp0_phy_3_inst (
.tx_clk(qsfp0_tx_clk_3_int),
.tx_rst(qsfp0_tx_rst_3_int),
.rx_clk(qsfp0_rx_clk_3_int),
.rx_rst(qsfp0_rx_rst_3_int),
.xgmii_txd(qsfp0_txd_3_int),
.xgmii_txc(qsfp0_txc_3_int),
.xgmii_rxd(qsfp0_rxd_3_int),
.xgmii_rxc(qsfp0_rxc_3_int),
.serdes_tx_data(qsfp0_gt_txdata_3),
.serdes_tx_hdr(qsfp0_gt_txheader_3),
.serdes_rx_data(qsfp0_gt_rxdata_3),
.serdes_rx_hdr(qsfp0_gt_rxheader_3),
.serdes_rx_bitslip(qsfp0_gt_rxgearboxslip_3),
.rx_block_lock(qsfp0_rx_block_lock_3),
.rx_high_ber()
);
assign qsfp0_tx_clk_4_int = clk_156mhz_int;
assign qsfp0_tx_rst_4_int = rst_156mhz_int;
assign qsfp0_rx_clk_4_int = gt_rxusrclk[7];
sync_reset #(
.N(4)
)
qsfp0_rx_rst_4_reset_sync_inst (
.clk(qsfp0_rx_clk_4_int),
.rst(~gt_reset_rx_done),
.out(qsfp0_rx_rst_4_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp0_phy_4_inst (
.tx_clk(qsfp0_tx_clk_4_int),
.tx_rst(qsfp0_tx_rst_4_int),
.rx_clk(qsfp0_rx_clk_4_int),
.rx_rst(qsfp0_rx_rst_4_int),
.xgmii_txd(qsfp0_txd_4_int),
.xgmii_txc(qsfp0_txc_4_int),
.xgmii_rxd(qsfp0_rxd_4_int),
.xgmii_rxc(qsfp0_rxc_4_int),
.serdes_tx_data(qsfp0_gt_txdata_4),
.serdes_tx_hdr(qsfp0_gt_txheader_4),
.serdes_rx_data(qsfp0_gt_rxdata_4),
.serdes_rx_hdr(qsfp0_gt_rxheader_4),
.serdes_rx_bitslip(qsfp0_gt_rxgearboxslip_4),
.rx_block_lock(qsfp0_rx_block_lock_4),
.rx_high_ber()
);
assign qsfp1_tx_clk_1_int = clk_156mhz_int;
assign qsfp1_tx_rst_1_int = rst_156mhz_int;
assign qsfp1_rx_clk_1_int = gt_rxusrclk[0];
sync_reset #(
.N(4)
)
qsfp1_rx_rst_1_reset_sync_inst (
.clk(qsfp1_rx_clk_1_int),
.rst(~gt_reset_rx_done),
.out(qsfp1_rx_rst_1_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp1_phy_1_inst (
.tx_clk(qsfp1_tx_clk_1_int),
.tx_rst(qsfp1_tx_rst_1_int),
.rx_clk(qsfp1_rx_clk_1_int),
.rx_rst(qsfp1_rx_rst_1_int),
.xgmii_txd(qsfp1_txd_1_int),
.xgmii_txc(qsfp1_txc_1_int),
.xgmii_rxd(qsfp1_rxd_1_int),
.xgmii_rxc(qsfp1_rxc_1_int),
.serdes_tx_data(qsfp1_gt_txdata_1),
.serdes_tx_hdr(qsfp1_gt_txheader_1),
.serdes_rx_data(qsfp1_gt_rxdata_1),
.serdes_rx_hdr(qsfp1_gt_rxheader_1),
.serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_1),
.rx_block_lock(qsfp1_rx_block_lock_1),
.rx_high_ber()
);
assign qsfp1_tx_clk_2_int = clk_156mhz_int;
assign qsfp1_tx_rst_2_int = rst_156mhz_int;
assign qsfp1_rx_clk_2_int = gt_rxusrclk[1];
sync_reset #(
.N(4)
)
qsfp1_rx_rst_2_reset_sync_inst (
.clk(qsfp1_rx_clk_2_int),
.rst(~gt_reset_rx_done),
.out(qsfp1_rx_rst_2_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp1_phy_2_inst (
.tx_clk(qsfp1_tx_clk_2_int),
.tx_rst(qsfp1_tx_rst_2_int),
.rx_clk(qsfp1_rx_clk_2_int),
.rx_rst(qsfp1_rx_rst_2_int),
.xgmii_txd(qsfp1_txd_2_int),
.xgmii_txc(qsfp1_txc_2_int),
.xgmii_rxd(qsfp1_rxd_2_int),
.xgmii_rxc(qsfp1_rxc_2_int),
.serdes_tx_data(qsfp1_gt_txdata_2),
.serdes_tx_hdr(qsfp1_gt_txheader_2),
.serdes_rx_data(qsfp1_gt_rxdata_2),
.serdes_rx_hdr(qsfp1_gt_rxheader_2),
.serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_2),
.rx_block_lock(qsfp1_rx_block_lock_2),
.rx_high_ber()
);
assign qsfp1_tx_clk_3_int = clk_156mhz_int;
assign qsfp1_tx_rst_3_int = rst_156mhz_int;
assign qsfp1_rx_clk_3_int = gt_rxusrclk[2];
sync_reset #(
.N(4)
)
qsfp1_rx_rst_3_reset_sync_inst (
.clk(qsfp1_rx_clk_3_int),
.rst(~gt_reset_rx_done),
.out(qsfp1_rx_rst_3_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp1_phy_3_inst (
.tx_clk(qsfp1_tx_clk_3_int),
.tx_rst(qsfp1_tx_rst_3_int),
.rx_clk(qsfp1_rx_clk_3_int),
.rx_rst(qsfp1_rx_rst_3_int),
.xgmii_txd(qsfp1_txd_3_int),
.xgmii_txc(qsfp1_txc_3_int),
.xgmii_rxd(qsfp1_rxd_3_int),
.xgmii_rxc(qsfp1_rxc_3_int),
.serdes_tx_data(qsfp1_gt_txdata_3),
.serdes_tx_hdr(qsfp1_gt_txheader_3),
.serdes_rx_data(qsfp1_gt_rxdata_3),
.serdes_rx_hdr(qsfp1_gt_rxheader_3),
.serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_3),
.rx_block_lock(qsfp1_rx_block_lock_3),
.rx_high_ber()
);
assign qsfp1_tx_clk_4_int = clk_156mhz_int;
assign qsfp1_tx_rst_4_int = rst_156mhz_int;
assign qsfp1_rx_clk_4_int = gt_rxusrclk[3];
sync_reset #(
.N(4)
)
qsfp1_rx_rst_4_reset_sync_inst (
.clk(qsfp1_rx_clk_4_int),
.rst(~gt_reset_rx_done),
.out(qsfp1_rx_rst_4_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp1_phy_4_inst (
.tx_clk(qsfp1_tx_clk_4_int),
.tx_rst(qsfp1_tx_rst_4_int),
.rx_clk(qsfp1_rx_clk_4_int),
.rx_rst(qsfp1_rx_rst_4_int),
.xgmii_txd(qsfp1_txd_4_int),
.xgmii_txc(qsfp1_txc_4_int),
.xgmii_rxd(qsfp1_rxd_4_int),
.xgmii_rxc(qsfp1_rxc_4_int),
.serdes_tx_data(qsfp1_gt_txdata_4),
.serdes_tx_hdr(qsfp1_gt_txheader_4),
.serdes_rx_data(qsfp1_gt_rxdata_4),
.serdes_rx_hdr(qsfp1_gt_rxheader_4),
.serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_4),
.rx_block_lock(qsfp1_rx_block_lock_4),
.rx_high_ber()
);
fpga_core
core_inst (
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
/*
* GPIO
*/
.sw(sw_int),
.led(led),
/*
* Ethernet: QSFP28
*/
.qsfp0_tx_clk_1(qsfp0_tx_clk_1_int),
.qsfp0_tx_rst_1(qsfp0_tx_rst_1_int),
.qsfp0_txd_1(qsfp0_txd_1_int),
.qsfp0_txc_1(qsfp0_txc_1_int),
.qsfp0_rx_clk_1(qsfp0_rx_clk_1_int),
.qsfp0_rx_rst_1(qsfp0_rx_rst_1_int),
.qsfp0_rxd_1(qsfp0_rxd_1_int),
.qsfp0_rxc_1(qsfp0_rxc_1_int),
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
.qsfp0_txd_2(qsfp0_txd_2_int),
.qsfp0_txc_2(qsfp0_txc_2_int),
.qsfp0_rx_clk_2(qsfp0_rx_clk_2_int),
.qsfp0_rx_rst_2(qsfp0_rx_rst_2_int),
.qsfp0_rxd_2(qsfp0_rxd_2_int),
.qsfp0_rxc_2(qsfp0_rxc_2_int),
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
.qsfp0_txd_3(qsfp0_txd_3_int),
.qsfp0_txc_3(qsfp0_txc_3_int),
.qsfp0_rx_clk_3(qsfp0_rx_clk_3_int),
.qsfp0_rx_rst_3(qsfp0_rx_rst_3_int),
.qsfp0_rxd_3(qsfp0_rxd_3_int),
.qsfp0_rxc_3(qsfp0_rxc_3_int),
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
.qsfp0_txd_4(qsfp0_txd_4_int),
.qsfp0_txc_4(qsfp0_txc_4_int),
.qsfp0_rx_clk_4(qsfp0_rx_clk_4_int),
.qsfp0_rx_rst_4(qsfp0_rx_rst_4_int),
.qsfp0_rxd_4(qsfp0_rxd_4_int),
.qsfp0_rxc_4(qsfp0_rxc_4_int),
.qsfp1_tx_clk_1(qsfp1_tx_clk_1_int),
.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
.qsfp1_txd_1(qsfp1_txd_1_int),
.qsfp1_txc_1(qsfp1_txc_1_int),
.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
.qsfp1_rxd_1(qsfp1_rxd_1_int),
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
.qsfp1_txc_2(qsfp1_txc_2_int),
.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
.qsfp1_rxd_2(qsfp1_rxd_2_int),
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
.qsfp1_txc_3(qsfp1_txc_3_int),
.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
.qsfp1_rxd_3(qsfp1_rxd_3_int),
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
.qsfp1_txc_4(qsfp1_txc_4_int),
.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
.qsfp1_rxd_4(qsfp1_rxd_4_int),
.qsfp1_rxc_4(qsfp1_rxc_4_int),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd),
.uart_txd(uart_txd_int)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2008 by Wilson Snyder.
module t (clk);
input clk;
integer cyc; initial cyc=1;
integer sum;
integer cpre;
always @ (posedge clk) begin
if (cyc!=0) begin
cpre = cyc;
cyc <= cyc + 1;
if (cyc==1) begin
if (mlog2(32'd0) != 32'd0) $stop;
if (mlog2(32'd1) != 32'd0) $stop;
if (mlog2(32'd3) != 32'd2) $stop;
sum <= 32'd0;
end
else if (cyc<90) begin
// (cyc) so if we trash the variable things will get upset.
sum <= mlog2(cyc) + sum * 32'd42;
if (cpre != cyc) $stop;
end
else if (cyc==90) begin
if (sum !== 32'h0f12bb51) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
function integer mlog2;
input [31:0] value;
integer i;
begin
if(value < 32'd1) begin
mlog2 = 0;
end
else begin
value = value - 32'd1;
mlog2 = 0;
for(i=0;i<32;i=i+1) begin
if(value > 32'd0) begin
mlog2 = mlog2 + 1;
end
value = value >> 1;
end
end
end
endfunction
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:27:32 06/14/2012
// Design Name:
// Module Name: reorder_queue_output
// Project Name:
// Target Devices:
// Tool versions:
// Description:
// Outputs stored TLPs in increasing tag order.
//
// Dependencies:
// reorder_queue.v
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "trellis.vh"
module reorder_queue_output #(
parameter C_PCI_DATA_WIDTH = 9'd128,
parameter C_NUM_CHNL = 4'd12,
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_TAG_DW_COUNT_WIDTH = 8, // Width of max count DWs per packet
parameter C_DATA_ADDR_STRIDE_WIDTH = 5, // Width of max num stored data addr positions per tag
parameter C_DATA_ADDR_WIDTH = 10, // Width of stored data address
// Local parameters
parameter C_PCI_DATA_WORD = C_PCI_DATA_WIDTH/32,
parameter C_PCI_DATA_WORD_WIDTH = clog2s(C_PCI_DATA_WORD),
parameter C_PCI_DATA_COUNT_WIDTH = clog2s(C_PCI_DATA_WORD+1),
parameter C_NUM_TAGS = 2**C_TAG_WIDTH
)
(
input CLK, // Clock
input RST, // Synchronous reset
output [C_DATA_ADDR_WIDTH-1:0] DATA_ADDR, // Address of stored packet data
input [C_PCI_DATA_WIDTH-1:0] DATA, // Stored packet data
input [C_NUM_TAGS-1:0] TAG_FINISHED, // Bitmap of finished tags
output [C_NUM_TAGS-1:0] TAG_CLEAR, // Bitmap of tags to clear
output [C_TAG_WIDTH-1:0] TAG, // Tag for which to retrieve packet data
input [5:0] TAG_MAPPED, // Mapped tag (i.e. internal tag)
input [C_TAG_DW_COUNT_WIDTH-1:0] PKT_WORDS, // Total count of packet payload in DWs
input PKT_WORDS_LTE1, // True if total count of packet payload is <= 4 DWs
input PKT_WORDS_LTE2, // True if total count of packet payload is <= 8 DWs
input PKT_DONE, // Packet done flag
input PKT_ERR, // Packet error flag
output [C_PCI_DATA_WIDTH-1:0] ENG_DATA, // Engine data
output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] MAIN_DATA_EN, // Main data enable
output [C_NUM_CHNL-1:0] MAIN_DONE, // Main data complete
output [C_NUM_CHNL-1:0] MAIN_ERR, // Main data completed with error
output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_RX_DATA_EN, // Scatter gather for RX data enable
output [C_NUM_CHNL-1:0] SG_RX_DONE, // Scatter gather for RX data complete
output [C_NUM_CHNL-1:0] SG_RX_ERR, // Scatter gather for RX data completed with error
output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_TX_DATA_EN, // Scatter gather for TX data enable
output [C_NUM_CHNL-1:0] SG_TX_DONE, // Scatter gather for TX data complete
output [C_NUM_CHNL-1:0] SG_TX_ERR // Scatter gather for TX data completed with error
);
reg [1:0] rState=0;
reg [C_DATA_ADDR_WIDTH-1:0] rDataAddr=0;
reg [C_PCI_DATA_WIDTH-1:0] rData=0;
reg rTagFinished=0;
reg [C_NUM_TAGS-1:0] rClear=0;
reg [C_TAG_WIDTH-1:0] rTag=0;
reg [C_TAG_WIDTH-1:0] rTagCurr=0;
wire [C_TAG_WIDTH-1:0] wTagNext = rTag + 1'd1;
reg [5:0] rShift;
reg rDone=0;
reg rDoneLast=0;
reg rErr=0;
reg rErrLast=0;
reg [C_PCI_DATA_COUNT_WIDTH-1:0] rDE=0;
reg [C_TAG_DW_COUNT_WIDTH-1:0] rWords=0;
reg rLTE2Pkts=0;
reg [C_PCI_DATA_WIDTH-1:0] rDataOut={C_PCI_DATA_WIDTH{1'b0}};
reg [(3*16*C_PCI_DATA_COUNT_WIDTH)-1:0] rDEOut={3*16*C_PCI_DATA_COUNT_WIDTH{1'd0}};
reg [(3*16)-1:0] rDoneOut={3*16{1'd0}};
reg [(3*16)-1:0] rErrOut={3*16{1'd0}};
assign DATA_ADDR = rDataAddr;
assign TAG = rTag;
assign TAG_CLEAR = rClear;
assign ENG_DATA = rDataOut;
assign MAIN_DATA_EN = rDEOut[(0*16*C_PCI_DATA_COUNT_WIDTH) +:(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)];
assign MAIN_DONE = rDoneOut[(0*16) +:C_NUM_CHNL];
assign MAIN_ERR = rErrOut[(0*16) +:C_NUM_CHNL];
assign SG_RX_DATA_EN = rDEOut[(1*16*C_PCI_DATA_COUNT_WIDTH) +:(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)];
assign SG_RX_DONE = rDoneOut[(1*16) +:C_NUM_CHNL];
assign SG_RX_ERR = rErrOut[(1*16) +:C_NUM_CHNL];
assign SG_TX_DATA_EN = rDEOut[(2*16*C_PCI_DATA_COUNT_WIDTH) +:(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)];
assign SG_TX_DONE = rDoneOut[(2*16) +:C_NUM_CHNL];
assign SG_TX_ERR = rErrOut[(2*16) +:C_NUM_CHNL];
// Output completed data in increasing tag order, avoid stalls if possible
always @ (posedge CLK) begin
if (RST) begin
rState <= #1 0;
rTag <= #1 0;
rDataAddr <= #1 0;
rDone <= #1 0;
rErr <= #1 0;
rDE <= #1 0;
rClear <= #1 0;
rTagFinished <= #1 0;
rShift <= 0; // Added
end
else begin
rTagFinished <= #1 TAG_FINISHED[rTag];
case (rState)
2'd0: begin // Request initial data and final info, output nothing
rDone <= #1 0;
rErr <= #1 0;
rDE <= #1 0;
rClear <= #1 0;
if (rTagFinished) begin
rTag <= #1 wTagNext;
rTagCurr <= #1 rTag;
rDataAddr <= #1 rDataAddr + 1'd1;
rState <= #1 2'd2;
end
else begin
rState <= #1 2'd0;
end
end
2'd1: begin // Request initial data and final info, output last data
rDone <= #1 rDoneLast;
rErr <= #1 rErrLast;
rDE <= #1 rWords[C_PCI_DATA_COUNT_WIDTH-1:0];
rClear <= #1 1<<rTagCurr; // Clear the tag
if (rTagFinished) begin
rTag <= #1 wTagNext;
rTagCurr <= #1 rTag;
rDataAddr <= #1 rDataAddr + 1'd1;
rState <= #1 2'd2;
end
else begin
rState <= #1 2'd0;
end
end
2'd2: begin // Initial data now available, output data
rShift <= #1 TAG_MAPPED;
rDoneLast <= #1 PKT_DONE;
rErrLast <= #1 PKT_ERR;
rWords <= #1 PKT_WORDS - C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
rLTE2Pkts <= #1 (PKT_WORDS <= (C_PCI_DATA_WORD*3));
if (PKT_WORDS_LTE1) begin // Guessed wrong, no addl data, need to reset
rDone <= #1 PKT_DONE;
rErr <= #1 PKT_ERR;
rDE <= #1 PKT_WORDS[C_PCI_DATA_COUNT_WIDTH-1:0];
rClear <= #1 1<<rTagCurr; // Clear the tag
rDataAddr <= #1 rTag<<C_DATA_ADDR_STRIDE_WIDTH; // rTag is already on the next
rState <= #1 2'd0;
end
else if (PKT_WORDS_LTE2) begin // Guessed right, end of data, output last and continue
rDone <= #1 0;
rErr <= #1 0;
rDE <= #1 C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
rClear <= #1 0;
rDataAddr <= #1 rTag<<C_DATA_ADDR_STRIDE_WIDTH; // rTag is already on the next
rState <= #1 2'd1;
end
else begin // Guessed right, more data, output it and continue
rDone <= #1 0;
rErr <= #1 0;
rDE <= #1 C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
rClear <= #1 0;
rDataAddr <= #1 rDataAddr + 1'd1;
rState <= #1 2'd3;
end
end
2'd3: begin // Next data now available, output data
rDone <= #1 0;
rErr <= #1 0;
rDE <= #1 C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
rWords <= #1 rWords - C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
rLTE2Pkts <= #1 (rWords <= (C_PCI_DATA_WORD*3));
if (rLTE2Pkts) begin // End of data, output last and continue
rDataAddr <= #1 rTag<<C_DATA_ADDR_STRIDE_WIDTH; // rTag is already on the next
rState <= #1 2'd1;
end
else begin // More data, output it and continue
rDataAddr <= #1 rDataAddr + 1'd1;
rState <= #1 2'd3;
end
end
endcase
end
end
// Output the data
always @ (posedge CLK) begin
rData <= #1 DATA;
rDataOut <= #1 rData;
if (RST) begin
rDEOut <= #1 0;
rDoneOut <= #1 0;
rErrOut <= #1 0;
end
else begin
rDEOut <= #1 rDE<<(C_PCI_DATA_COUNT_WIDTH*rShift);
rDoneOut <= #1 (rDone | rErr)<<rShift;
rErrOut <= #1 rErr<<rShift;
end
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(DVI_CLK),
.CONTROL(wControl0),
.TRIG0({wFifoFull, wFifoEmpty, rState, rPrevDVI_VS, DVI_DE, DVI_HS, DVI_VS}),
.DATA({457'd0,
rCount, // 21
rFrameCount, // 21
wCapture, // 1
RD_EN, // 1
RD_EMPTY, // 1
EOF, // 1
wPackerFull, // 1
wFifoFull, // 1
wFifoEmpty, // 1
rState, // 2
rPrevDVI_VS, // 1
DVI_DE, // 1
DVI_HS, // 1
DVI_VS}) // 1
);
*/
endmodule
|
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_reset O 1 const
// av_read O 32
// RDY_av_read O 1
// RDY_write O 1
// master_awvalid O 1 reg
// master_awid O 16 reg
// master_awaddr O 64 reg
// master_awlen O 8 reg
// master_awsize O 3 reg
// master_awburst O 2 reg
// master_awlock O 1 reg
// master_awcache O 4 reg
// master_awprot O 3 reg
// master_awqos O 4 reg
// master_awregion O 4 reg
// master_wvalid O 1 reg
// master_wdata O 64 reg
// master_wstrb O 8 reg
// master_wlast O 1 reg
// master_bready O 1 reg
// master_arvalid O 1 reg
// master_arid O 16 reg
// master_araddr O 64 reg
// master_arlen O 8 reg
// master_arsize O 3 reg
// master_arburst O 2 reg
// master_arlock O 1 reg
// master_arcache O 4 reg
// master_arprot O 3 reg
// master_arqos O 4 reg
// master_arregion O 4 reg
// master_rready O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// av_read_dm_addr I 7
// write_dm_addr I 7
// write_dm_word I 32
// master_awready I 1
// master_wready I 1
// master_bvalid I 1
// master_bid I 16 reg
// master_bresp I 2 reg
// master_arready I 1
// master_rvalid I 1
// master_rid I 16 reg
// master_rdata I 64 reg
// master_rresp I 2 reg
// master_rlast I 1 reg
// EN_reset I 1
// EN_write I 1
// EN_av_read I 1
//
// Combinational paths from inputs to outputs:
// av_read_dm_addr -> av_read
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkDM_System_Bus(CLK,
RST_N,
EN_reset,
RDY_reset,
av_read_dm_addr,
EN_av_read,
av_read,
RDY_av_read,
write_dm_addr,
write_dm_word,
EN_write,
RDY_write,
master_awvalid,
master_awid,
master_awaddr,
master_awlen,
master_awsize,
master_awburst,
master_awlock,
master_awcache,
master_awprot,
master_awqos,
master_awregion,
master_awready,
master_wvalid,
master_wdata,
master_wstrb,
master_wlast,
master_wready,
master_bvalid,
master_bid,
master_bresp,
master_bready,
master_arvalid,
master_arid,
master_araddr,
master_arlen,
master_arsize,
master_arburst,
master_arlock,
master_arcache,
master_arprot,
master_arqos,
master_arregion,
master_arready,
master_rvalid,
master_rid,
master_rdata,
master_rresp,
master_rlast,
master_rready);
input CLK;
input RST_N;
// action method reset
input EN_reset;
output RDY_reset;
// actionvalue method av_read
input [6 : 0] av_read_dm_addr;
input EN_av_read;
output [31 : 0] av_read;
output RDY_av_read;
// action method write
input [6 : 0] write_dm_addr;
input [31 : 0] write_dm_word;
input EN_write;
output RDY_write;
// value method master_m_awvalid
output master_awvalid;
// value method master_m_awid
output [15 : 0] master_awid;
// value method master_m_awaddr
output [63 : 0] master_awaddr;
// value method master_m_awlen
output [7 : 0] master_awlen;
// value method master_m_awsize
output [2 : 0] master_awsize;
// value method master_m_awburst
output [1 : 0] master_awburst;
// value method master_m_awlock
output master_awlock;
// value method master_m_awcache
output [3 : 0] master_awcache;
// value method master_m_awprot
output [2 : 0] master_awprot;
// value method master_m_awqos
output [3 : 0] master_awqos;
// value method master_m_awregion
output [3 : 0] master_awregion;
// value method master_m_awuser
// action method master_m_awready
input master_awready;
// value method master_m_wvalid
output master_wvalid;
// value method master_m_wdata
output [63 : 0] master_wdata;
// value method master_m_wstrb
output [7 : 0] master_wstrb;
// value method master_m_wlast
output master_wlast;
// value method master_m_wuser
// action method master_m_wready
input master_wready;
// action method master_m_bvalid
input master_bvalid;
input [15 : 0] master_bid;
input [1 : 0] master_bresp;
// value method master_m_bready
output master_bready;
// value method master_m_arvalid
output master_arvalid;
// value method master_m_arid
output [15 : 0] master_arid;
// value method master_m_araddr
output [63 : 0] master_araddr;
// value method master_m_arlen
output [7 : 0] master_arlen;
// value method master_m_arsize
output [2 : 0] master_arsize;
// value method master_m_arburst
output [1 : 0] master_arburst;
// value method master_m_arlock
output master_arlock;
// value method master_m_arcache
output [3 : 0] master_arcache;
// value method master_m_arprot
output [2 : 0] master_arprot;
// value method master_m_arqos
output [3 : 0] master_arqos;
// value method master_m_arregion
output [3 : 0] master_arregion;
// value method master_m_aruser
// action method master_m_arready
input master_arready;
// action method master_m_rvalid
input master_rvalid;
input [15 : 0] master_rid;
input [63 : 0] master_rdata;
input [1 : 0] master_rresp;
input master_rlast;
// value method master_m_rready
output master_rready;
// signals for module outputs
reg [31 : 0] av_read;
wire [63 : 0] master_araddr, master_awaddr, master_wdata;
wire [15 : 0] master_arid, master_awid;
wire [7 : 0] master_arlen, master_awlen, master_wstrb;
wire [3 : 0] master_arcache,
master_arqos,
master_arregion,
master_awcache,
master_awqos,
master_awregion;
wire [2 : 0] master_arprot, master_arsize, master_awprot, master_awsize;
wire [1 : 0] master_arburst, master_awburst;
wire RDY_av_read,
RDY_reset,
RDY_write,
master_arlock,
master_arvalid,
master_awlock,
master_awvalid,
master_bready,
master_rready,
master_wlast,
master_wvalid;
// register rg_sb_state
reg [1 : 0] rg_sb_state;
wire [1 : 0] rg_sb_state$D_IN;
wire rg_sb_state$EN;
// register rg_sbaddress0
reg [31 : 0] rg_sbaddress0;
reg [31 : 0] rg_sbaddress0$D_IN;
wire rg_sbaddress0$EN;
// register rg_sbaddress1
reg [31 : 0] rg_sbaddress1;
reg [31 : 0] rg_sbaddress1$D_IN;
wire rg_sbaddress1$EN;
// register rg_sbaddress_reading
reg [63 : 0] rg_sbaddress_reading;
wire [63 : 0] rg_sbaddress_reading$D_IN;
wire rg_sbaddress_reading$EN;
// register rg_sbcs_sbaccess
reg [2 : 0] rg_sbcs_sbaccess;
wire [2 : 0] rg_sbcs_sbaccess$D_IN;
wire rg_sbcs_sbaccess$EN;
// register rg_sbcs_sbautoincrement
reg rg_sbcs_sbautoincrement;
wire rg_sbcs_sbautoincrement$D_IN, rg_sbcs_sbautoincrement$EN;
// register rg_sbcs_sbbusyerror
reg rg_sbcs_sbbusyerror;
reg rg_sbcs_sbbusyerror$D_IN;
wire rg_sbcs_sbbusyerror$EN;
// register rg_sbcs_sberror
reg [2 : 0] rg_sbcs_sberror;
reg [2 : 0] rg_sbcs_sberror$D_IN;
wire rg_sbcs_sberror$EN;
// register rg_sbcs_sbreadonaddr
reg rg_sbcs_sbreadonaddr;
wire rg_sbcs_sbreadonaddr$D_IN, rg_sbcs_sbreadonaddr$EN;
// register rg_sbcs_sbreadondata
reg rg_sbcs_sbreadondata;
wire rg_sbcs_sbreadondata$D_IN, rg_sbcs_sbreadondata$EN;
// register rg_sbdata0
reg [31 : 0] rg_sbdata0;
reg [31 : 0] rg_sbdata0$D_IN;
wire rg_sbdata0$EN;
// ports of submodule master_xactor_f_rd_addr
wire [108 : 0] master_xactor_f_rd_addr$D_IN, master_xactor_f_rd_addr$D_OUT;
wire master_xactor_f_rd_addr$CLR,
master_xactor_f_rd_addr$DEQ,
master_xactor_f_rd_addr$EMPTY_N,
master_xactor_f_rd_addr$ENQ,
master_xactor_f_rd_addr$FULL_N;
// ports of submodule master_xactor_f_rd_data
wire [82 : 0] master_xactor_f_rd_data$D_IN, master_xactor_f_rd_data$D_OUT;
wire master_xactor_f_rd_data$CLR,
master_xactor_f_rd_data$DEQ,
master_xactor_f_rd_data$EMPTY_N,
master_xactor_f_rd_data$ENQ,
master_xactor_f_rd_data$FULL_N;
// ports of submodule master_xactor_f_wr_addr
wire [108 : 0] master_xactor_f_wr_addr$D_IN, master_xactor_f_wr_addr$D_OUT;
wire master_xactor_f_wr_addr$CLR,
master_xactor_f_wr_addr$DEQ,
master_xactor_f_wr_addr$EMPTY_N,
master_xactor_f_wr_addr$ENQ,
master_xactor_f_wr_addr$FULL_N;
// ports of submodule master_xactor_f_wr_data
wire [72 : 0] master_xactor_f_wr_data$D_IN, master_xactor_f_wr_data$D_OUT;
wire master_xactor_f_wr_data$CLR,
master_xactor_f_wr_data$DEQ,
master_xactor_f_wr_data$EMPTY_N,
master_xactor_f_wr_data$ENQ,
master_xactor_f_wr_data$FULL_N;
// ports of submodule master_xactor_f_wr_resp
wire [17 : 0] master_xactor_f_wr_resp$D_IN, master_xactor_f_wr_resp$D_OUT;
wire master_xactor_f_wr_resp$CLR,
master_xactor_f_wr_resp$DEQ,
master_xactor_f_wr_resp$EMPTY_N,
master_xactor_f_wr_resp$ENQ,
master_xactor_f_wr_resp$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_rl_sb_read_finish,
CAN_FIRE_RL_rl_sb_write_response,
CAN_FIRE_av_read,
CAN_FIRE_master_m_arready,
CAN_FIRE_master_m_awready,
CAN_FIRE_master_m_bvalid,
CAN_FIRE_master_m_rvalid,
CAN_FIRE_master_m_wready,
CAN_FIRE_reset,
CAN_FIRE_write,
WILL_FIRE_RL_rl_sb_read_finish,
WILL_FIRE_RL_rl_sb_write_response,
WILL_FIRE_av_read,
WILL_FIRE_master_m_arready,
WILL_FIRE_master_m_awready,
WILL_FIRE_master_m_bvalid,
WILL_FIRE_master_m_rvalid,
WILL_FIRE_master_m_wready,
WILL_FIRE_reset,
WILL_FIRE_write;
// inputs to muxes for submodule ports
reg [31 : 0] MUX_rg_sbaddress0$write_1__VAL_2,
MUX_rg_sbaddress1$write_1__VAL_2;
reg [2 : 0] MUX_rg_sbcs_sberror$write_1__VAL_4;
wire [108 : 0] MUX_master_xactor_f_rd_addr$enq_1__VAL_1,
MUX_master_xactor_f_rd_addr$enq_1__VAL_2;
wire MUX_master_xactor_f_rd_addr$enq_1__SEL_1,
MUX_rg_sbaddress0$write_1__SEL_2,
MUX_rg_sbaddress0$write_1__SEL_3,
MUX_rg_sbaddress1$write_1__SEL_2,
MUX_rg_sbcs_sbbusyerror$write_1__SEL_2,
MUX_rg_sbcs_sbbusyerror$write_1__SEL_3,
MUX_rg_sbcs_sberror$write_1__SEL_1,
MUX_rg_sbcs_sberror$write_1__SEL_3,
MUX_rg_sbcs_sberror$write_1__SEL_4,
MUX_rg_sbdata0$write_1__SEL_3;
// remaining internal signals
reg [63 : 0] CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1,
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53,
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66,
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103,
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79,
wrd_wdata__h4397;
reg [7 : 0] wrd_wstrb__h4398;
reg [2 : 0] x__h2654, x__h4302;
wire [63 : 0] _theResult___fst__h4340,
addr64__h3701,
result__h1250,
result__h1280,
result__h1307,
result__h1334,
result__h1361,
result__h1388,
result__h1415,
result__h1442,
result__h1487,
result__h1514,
result__h1541,
result__h1568,
result__h1609,
result__h1636,
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104,
rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299,
sbaddress__h638,
word64__h4284;
wire [31 : 0] IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310,
IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301,
v__h2132,
v__h2266;
wire [7 : 0] strobe64__h4339, strobe64__h4342, strobe64__h4345;
wire [5 : 0] shift_bits__h4287;
wire rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110,
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316,
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95,
rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291,
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256,
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265,
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271,
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273,
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278,
write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326;
// action method reset
assign RDY_reset = 1'd1 ;
assign CAN_FIRE_reset = 1'd1 ;
assign WILL_FIRE_reset = EN_reset ;
// actionvalue method av_read
always@(av_read_dm_addr or
v__h2132 or rg_sbaddress0 or rg_sbaddress1 or v__h2266)
begin
case (av_read_dm_addr)
7'h38: av_read = v__h2132;
7'h39: av_read = rg_sbaddress0;
7'h3A: av_read = rg_sbaddress1;
7'h3C: av_read = v__h2266;
default: av_read = 32'd0;
endcase
end
assign RDY_av_read =
rg_sb_state == 2'd0 &&
(rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0 ||
!rg_sbcs_sbreadondata ||
master_xactor_f_rd_addr$FULL_N) ;
assign CAN_FIRE_av_read = RDY_av_read ;
assign WILL_FIRE_av_read = EN_av_read ;
// action method write
assign RDY_write = CAN_FIRE_write && !WILL_FIRE_RL_rl_sb_read_finish ;
assign CAN_FIRE_write =
(rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror ||
rg_sbcs_sberror != 3'd0 ||
!rg_sbcs_sbreadonaddr ||
master_xactor_f_rd_addr$FULL_N) &&
(rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror ||
rg_sbcs_sberror != 3'd0 ||
master_xactor_f_wr_addr$FULL_N &&
master_xactor_f_wr_data$FULL_N) ;
assign WILL_FIRE_write = EN_write ;
// value method master_m_awvalid
assign master_awvalid = master_xactor_f_wr_addr$EMPTY_N ;
// value method master_m_awid
assign master_awid = master_xactor_f_wr_addr$D_OUT[108:93] ;
// value method master_m_awaddr
assign master_awaddr = master_xactor_f_wr_addr$D_OUT[92:29] ;
// value method master_m_awlen
assign master_awlen = master_xactor_f_wr_addr$D_OUT[28:21] ;
// value method master_m_awsize
assign master_awsize = master_xactor_f_wr_addr$D_OUT[20:18] ;
// value method master_m_awburst
assign master_awburst = master_xactor_f_wr_addr$D_OUT[17:16] ;
// value method master_m_awlock
assign master_awlock = master_xactor_f_wr_addr$D_OUT[15] ;
// value method master_m_awcache
assign master_awcache = master_xactor_f_wr_addr$D_OUT[14:11] ;
// value method master_m_awprot
assign master_awprot = master_xactor_f_wr_addr$D_OUT[10:8] ;
// value method master_m_awqos
assign master_awqos = master_xactor_f_wr_addr$D_OUT[7:4] ;
// value method master_m_awregion
assign master_awregion = master_xactor_f_wr_addr$D_OUT[3:0] ;
// action method master_m_awready
assign CAN_FIRE_master_m_awready = 1'd1 ;
assign WILL_FIRE_master_m_awready = 1'd1 ;
// value method master_m_wvalid
assign master_wvalid = master_xactor_f_wr_data$EMPTY_N ;
// value method master_m_wdata
assign master_wdata = master_xactor_f_wr_data$D_OUT[72:9] ;
// value method master_m_wstrb
assign master_wstrb = master_xactor_f_wr_data$D_OUT[8:1] ;
// value method master_m_wlast
assign master_wlast = master_xactor_f_wr_data$D_OUT[0] ;
// action method master_m_wready
assign CAN_FIRE_master_m_wready = 1'd1 ;
assign WILL_FIRE_master_m_wready = 1'd1 ;
// action method master_m_bvalid
assign CAN_FIRE_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_master_m_bvalid = 1'd1 ;
// value method master_m_bready
assign master_bready = master_xactor_f_wr_resp$FULL_N ;
// value method master_m_arvalid
assign master_arvalid = master_xactor_f_rd_addr$EMPTY_N ;
// value method master_m_arid
assign master_arid = master_xactor_f_rd_addr$D_OUT[108:93] ;
// value method master_m_araddr
assign master_araddr = master_xactor_f_rd_addr$D_OUT[92:29] ;
// value method master_m_arlen
assign master_arlen = master_xactor_f_rd_addr$D_OUT[28:21] ;
// value method master_m_arsize
assign master_arsize = master_xactor_f_rd_addr$D_OUT[20:18] ;
// value method master_m_arburst
assign master_arburst = master_xactor_f_rd_addr$D_OUT[17:16] ;
// value method master_m_arlock
assign master_arlock = master_xactor_f_rd_addr$D_OUT[15] ;
// value method master_m_arcache
assign master_arcache = master_xactor_f_rd_addr$D_OUT[14:11] ;
// value method master_m_arprot
assign master_arprot = master_xactor_f_rd_addr$D_OUT[10:8] ;
// value method master_m_arqos
assign master_arqos = master_xactor_f_rd_addr$D_OUT[7:4] ;
// value method master_m_arregion
assign master_arregion = master_xactor_f_rd_addr$D_OUT[3:0] ;
// action method master_m_arready
assign CAN_FIRE_master_m_arready = 1'd1 ;
assign WILL_FIRE_master_m_arready = 1'd1 ;
// action method master_m_rvalid
assign CAN_FIRE_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_master_m_rvalid = 1'd1 ;
// value method master_m_rready
assign master_rready = master_xactor_f_rd_data$FULL_N ;
// submodule master_xactor_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(32'd1)) master_xactor_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_rd_addr$D_IN),
.ENQ(master_xactor_f_rd_addr$ENQ),
.DEQ(master_xactor_f_rd_addr$DEQ),
.CLR(master_xactor_f_rd_addr$CLR),
.D_OUT(master_xactor_f_rd_addr$D_OUT),
.FULL_N(master_xactor_f_rd_addr$FULL_N),
.EMPTY_N(master_xactor_f_rd_addr$EMPTY_N));
// submodule master_xactor_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(32'd1)) master_xactor_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_rd_data$D_IN),
.ENQ(master_xactor_f_rd_data$ENQ),
.DEQ(master_xactor_f_rd_data$DEQ),
.CLR(master_xactor_f_rd_data$CLR),
.D_OUT(master_xactor_f_rd_data$D_OUT),
.FULL_N(master_xactor_f_rd_data$FULL_N),
.EMPTY_N(master_xactor_f_rd_data$EMPTY_N));
// submodule master_xactor_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(32'd1)) master_xactor_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_addr$D_IN),
.ENQ(master_xactor_f_wr_addr$ENQ),
.DEQ(master_xactor_f_wr_addr$DEQ),
.CLR(master_xactor_f_wr_addr$CLR),
.D_OUT(master_xactor_f_wr_addr$D_OUT),
.FULL_N(master_xactor_f_wr_addr$FULL_N),
.EMPTY_N(master_xactor_f_wr_addr$EMPTY_N));
// submodule master_xactor_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) master_xactor_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_data$D_IN),
.ENQ(master_xactor_f_wr_data$ENQ),
.DEQ(master_xactor_f_wr_data$DEQ),
.CLR(master_xactor_f_wr_data$CLR),
.D_OUT(master_xactor_f_wr_data$D_OUT),
.FULL_N(master_xactor_f_wr_data$FULL_N),
.EMPTY_N(master_xactor_f_wr_data$EMPTY_N));
// submodule master_xactor_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(32'd1)) master_xactor_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_resp$D_IN),
.ENQ(master_xactor_f_wr_resp$ENQ),
.DEQ(master_xactor_f_wr_resp$DEQ),
.CLR(master_xactor_f_wr_resp$CLR),
.D_OUT(master_xactor_f_wr_resp$D_OUT),
.FULL_N(master_xactor_f_wr_resp$FULL_N),
.EMPTY_N(master_xactor_f_wr_resp$EMPTY_N));
// rule RL_rl_sb_read_finish
assign CAN_FIRE_RL_rl_sb_read_finish =
master_xactor_f_rd_data$EMPTY_N && rg_sb_state == 2'd1 &&
rg_sbcs_sberror == 3'd0 ;
assign WILL_FIRE_RL_rl_sb_read_finish = CAN_FIRE_RL_rl_sb_read_finish ;
// rule RL_rl_sb_write_response
assign CAN_FIRE_RL_rl_sb_write_response = master_xactor_f_wr_resp$EMPTY_N ;
assign WILL_FIRE_RL_rl_sb_write_response = master_xactor_f_wr_resp$EMPTY_N ;
// inputs to muxes for submodule ports
assign MUX_master_xactor_f_rd_addr$enq_1__SEL_1 =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 ;
assign MUX_rg_sbaddress0$write_1__SEL_2 =
EN_write && write_dm_addr != 7'h38 &&
(rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror &&
rg_sbcs_sberror == 3'd0 &&
write_dm_addr == 7'h39 ||
write_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95) ;
assign MUX_rg_sbaddress0$write_1__SEL_3 =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 ;
assign MUX_rg_sbaddress1$write_1__SEL_2 =
EN_write && write_dm_addr != 7'h38 &&
((write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) &&
rg_sb_state == 2'd0 &&
!rg_sbcs_sbbusyerror &&
rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291 ||
write_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95) ;
assign MUX_rg_sbcs_sbbusyerror$write_1__SEL_2 =
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 ;
assign MUX_rg_sbcs_sbbusyerror$write_1__SEL_3 =
EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0 ;
assign MUX_rg_sbcs_sberror$write_1__SEL_1 =
master_xactor_f_wr_resp$EMPTY_N &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 ;
assign MUX_rg_sbcs_sberror$write_1__SEL_3 =
WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
assign MUX_rg_sbcs_sberror$write_1__SEL_4 =
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 ;
assign MUX_rg_sbdata0$write_1__SEL_3 =
EN_write &&
write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 ;
assign MUX_master_xactor_f_rd_addr$enq_1__VAL_1 =
{ 16'd0, sbaddress__h638, 8'd0, x__h2654, 18'd65536 } ;
assign MUX_master_xactor_f_rd_addr$enq_1__VAL_2 =
{ 16'd0, addr64__h3701, 8'd0, x__h2654, 18'd65536 } ;
always@(write_dm_addr or
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104 or
IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310)
begin
case (write_dm_addr)
7'h39, 7'h3A:
MUX_rg_sbaddress0$write_1__VAL_2 =
IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310;
default: MUX_rg_sbaddress0$write_1__VAL_2 =
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104[31:0];
endcase
end
always@(write_dm_addr or
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104 or
IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301)
begin
case (write_dm_addr)
7'h39, 7'h3A:
MUX_rg_sbaddress1$write_1__VAL_2 =
IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301;
default: MUX_rg_sbaddress1$write_1__VAL_2 =
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104[63:32];
endcase
end
always@(write_dm_word)
begin
case (write_dm_word[19:17])
3'd3, 3'd4: MUX_rg_sbcs_sberror$write_1__VAL_4 = 3'd3;
default: MUX_rg_sbcs_sberror$write_1__VAL_4 = 3'd0;
endcase
end
// register rg_sb_state
assign rg_sb_state$D_IN =
(EN_reset || WILL_FIRE_RL_rl_sb_read_finish) ? 2'd0 : 2'd1 ;
assign rg_sb_state$EN =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 ||
EN_write && write_dm_addr == 7'h39 &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 ||
WILL_FIRE_RL_rl_sb_read_finish ||
EN_reset ;
// register rg_sbaddress0
always@(EN_reset or
MUX_rg_sbaddress0$write_1__SEL_2 or
MUX_rg_sbaddress0$write_1__VAL_2 or
MUX_rg_sbaddress0$write_1__SEL_3 or
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104)
case (1'b1)
EN_reset: rg_sbaddress0$D_IN = 32'd0;
MUX_rg_sbaddress0$write_1__SEL_2:
rg_sbaddress0$D_IN = MUX_rg_sbaddress0$write_1__VAL_2;
MUX_rg_sbaddress0$write_1__SEL_3:
rg_sbaddress0$D_IN =
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104[31:0];
default: rg_sbaddress0$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
assign rg_sbaddress0$EN =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 ||
MUX_rg_sbaddress0$write_1__SEL_2 ||
EN_reset ;
// register rg_sbaddress1
always@(EN_reset or
MUX_rg_sbaddress1$write_1__SEL_2 or
MUX_rg_sbaddress1$write_1__VAL_2 or
MUX_rg_sbaddress0$write_1__SEL_3 or
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104)
case (1'b1)
EN_reset: rg_sbaddress1$D_IN = 32'd0;
MUX_rg_sbaddress1$write_1__SEL_2:
rg_sbaddress1$D_IN = MUX_rg_sbaddress1$write_1__VAL_2;
MUX_rg_sbaddress0$write_1__SEL_3:
rg_sbaddress1$D_IN =
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104[63:32];
default: rg_sbaddress1$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
assign rg_sbaddress1$EN =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 ||
MUX_rg_sbaddress1$write_1__SEL_2 ||
EN_reset ;
// register rg_sbaddress_reading
assign rg_sbaddress_reading$D_IN =
MUX_master_xactor_f_rd_addr$enq_1__SEL_1 ?
sbaddress__h638 :
addr64__h3701 ;
assign rg_sbaddress_reading$EN =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 ||
EN_write && write_dm_addr == 7'h39 &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 ;
// register rg_sbcs_sbaccess
assign rg_sbcs_sbaccess$D_IN = EN_reset ? 3'd2 : write_dm_word[19:17] ;
assign rg_sbcs_sbaccess$EN =
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 ||
EN_reset ;
// register rg_sbcs_sbautoincrement
assign rg_sbcs_sbautoincrement$D_IN = !EN_reset && write_dm_word[16] ;
assign rg_sbcs_sbautoincrement$EN =
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 ||
EN_reset ;
// register rg_sbcs_sbbusyerror
always@(EN_reset or
MUX_rg_sbcs_sbbusyerror$write_1__SEL_2 or
write_dm_addr or MUX_rg_sbcs_sbbusyerror$write_1__SEL_3)
case (1'b1)
EN_reset: rg_sbcs_sbbusyerror$D_IN = 1'd0;
MUX_rg_sbcs_sbbusyerror$write_1__SEL_2:
rg_sbcs_sbbusyerror$D_IN = write_dm_addr != 7'h38;
MUX_rg_sbcs_sbbusyerror$write_1__SEL_3: rg_sbcs_sbbusyerror$D_IN = 1'd1;
default: rg_sbcs_sbbusyerror$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign rg_sbcs_sbbusyerror$EN =
EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0 ||
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 ||
EN_reset ;
// register rg_sbcs_sberror
always@(MUX_rg_sbcs_sberror$write_1__SEL_1 or
EN_reset or
MUX_rg_sbcs_sberror$write_1__SEL_3 or
MUX_rg_sbcs_sberror$write_1__SEL_4 or
MUX_rg_sbcs_sberror$write_1__VAL_4)
case (1'b1)
MUX_rg_sbcs_sberror$write_1__SEL_1: rg_sbcs_sberror$D_IN = 3'd3;
EN_reset: rg_sbcs_sberror$D_IN = 3'd0;
MUX_rg_sbcs_sberror$write_1__SEL_3: rg_sbcs_sberror$D_IN = 3'd3;
MUX_rg_sbcs_sberror$write_1__SEL_4:
rg_sbcs_sberror$D_IN = MUX_rg_sbcs_sberror$write_1__VAL_4;
default: rg_sbcs_sberror$D_IN = 3'b010 /* unspecified value */ ;
endcase
assign rg_sbcs_sberror$EN =
WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
master_xactor_f_wr_resp$EMPTY_N &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 ||
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 ||
EN_reset ;
// register rg_sbcs_sbreadonaddr
assign rg_sbcs_sbreadonaddr$D_IN = !EN_reset && write_dm_word[20] ;
assign rg_sbcs_sbreadonaddr$EN =
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 ||
EN_reset ;
// register rg_sbcs_sbreadondata
assign rg_sbcs_sbreadondata$D_IN = !EN_reset && write_dm_word[15] ;
assign rg_sbcs_sbreadondata$EN =
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 ||
EN_reset ;
// register rg_sbdata0
always@(EN_reset or
WILL_FIRE_RL_rl_sb_read_finish or
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 or
MUX_rg_sbdata0$write_1__SEL_3 or write_dm_word)
case (1'b1)
EN_reset: rg_sbdata0$D_IN = 32'd0;
WILL_FIRE_RL_rl_sb_read_finish:
rg_sbdata0$D_IN =
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79[31:0];
MUX_rg_sbdata0$write_1__SEL_3: rg_sbdata0$D_IN = write_dm_word;
default: rg_sbdata0$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
assign rg_sbdata0$EN =
EN_write &&
write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 ||
WILL_FIRE_RL_rl_sb_read_finish ||
EN_reset ;
// submodule master_xactor_f_rd_addr
assign master_xactor_f_rd_addr$D_IN =
MUX_master_xactor_f_rd_addr$enq_1__SEL_1 ?
MUX_master_xactor_f_rd_addr$enq_1__VAL_1 :
MUX_master_xactor_f_rd_addr$enq_1__VAL_2 ;
assign master_xactor_f_rd_addr$ENQ =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 ||
EN_write && write_dm_addr == 7'h39 &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 ;
assign master_xactor_f_rd_addr$DEQ =
master_xactor_f_rd_addr$EMPTY_N && master_arready ;
assign master_xactor_f_rd_addr$CLR = 1'b0 ;
// submodule master_xactor_f_rd_data
assign master_xactor_f_rd_data$D_IN =
{ master_rid, master_rdata, master_rresp, master_rlast } ;
assign master_xactor_f_rd_data$ENQ =
master_rvalid && master_xactor_f_rd_data$FULL_N ;
assign master_xactor_f_rd_data$DEQ =
master_xactor_f_rd_data$EMPTY_N && rg_sb_state == 2'd1 &&
rg_sbcs_sberror == 3'd0 ;
assign master_xactor_f_rd_data$CLR = 1'b0 ;
// submodule master_xactor_f_wr_addr
assign master_xactor_f_wr_addr$D_IN =
{ 16'd0, sbaddress__h638, 8'd0, x__h4302, 18'd65536 } ;
assign master_xactor_f_wr_addr$ENQ =
EN_write &&
write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 ;
assign master_xactor_f_wr_addr$DEQ =
master_xactor_f_wr_addr$EMPTY_N && master_awready ;
assign master_xactor_f_wr_addr$CLR = 1'b0 ;
// submodule master_xactor_f_wr_data
assign master_xactor_f_wr_data$D_IN =
{ wrd_wdata__h4397, wrd_wstrb__h4398, 1'd1 } ;
assign master_xactor_f_wr_data$ENQ =
EN_write &&
write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 ;
assign master_xactor_f_wr_data$DEQ =
master_xactor_f_wr_data$EMPTY_N && master_wready ;
assign master_xactor_f_wr_data$CLR = 1'b0 ;
// submodule master_xactor_f_wr_resp
assign master_xactor_f_wr_resp$D_IN = { master_bid, master_bresp } ;
assign master_xactor_f_wr_resp$ENQ =
master_bvalid && master_xactor_f_wr_resp$FULL_N ;
assign master_xactor_f_wr_resp$DEQ = master_xactor_f_wr_resp$EMPTY_N ;
assign master_xactor_f_wr_resp$CLR = 1'b0 ;
// remaining internal signals
assign IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310 =
rg_sbcs_sbreadonaddr ?
(rg_sbcs_sbautoincrement ?
rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299[31:0] :
write_dm_word) :
write_dm_word ;
assign IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301 =
(write_dm_addr == 7'h39) ?
rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299[63:32] :
write_dm_word ;
assign _theResult___fst__h4340 = word64__h4284 << shift_bits__h4287 ;
assign addr64__h3701 = { rg_sbaddress1, write_dm_word } ;
assign result__h1250 = { 56'd0, master_xactor_f_rd_data$D_OUT[10:3] } ;
assign result__h1280 = { 56'd0, master_xactor_f_rd_data$D_OUT[18:11] } ;
assign result__h1307 = { 56'd0, master_xactor_f_rd_data$D_OUT[26:19] } ;
assign result__h1334 = { 56'd0, master_xactor_f_rd_data$D_OUT[34:27] } ;
assign result__h1361 = { 56'd0, master_xactor_f_rd_data$D_OUT[42:35] } ;
assign result__h1388 = { 56'd0, master_xactor_f_rd_data$D_OUT[50:43] } ;
assign result__h1415 = { 56'd0, master_xactor_f_rd_data$D_OUT[58:51] } ;
assign result__h1442 = { 56'd0, master_xactor_f_rd_data$D_OUT[66:59] } ;
assign result__h1487 = { 48'd0, master_xactor_f_rd_data$D_OUT[18:3] } ;
assign result__h1514 = { 48'd0, master_xactor_f_rd_data$D_OUT[34:19] } ;
assign result__h1541 = { 48'd0, master_xactor_f_rd_data$D_OUT[50:35] } ;
assign result__h1568 = { 48'd0, master_xactor_f_rd_data$D_OUT[66:51] } ;
assign result__h1609 = { 32'd0, master_xactor_f_rd_data$D_OUT[34:3] } ;
assign result__h1636 = { 32'd0, master_xactor_f_rd_data$D_OUT[66:35] } ;
assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 =
rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror &&
rg_sbcs_sberror == 3'd0 &&
rg_sbcs_sbreadondata ;
assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 =
rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror &&
rg_sbcs_sberror == 3'd0 &&
rg_sbcs_sbreadonaddr ;
assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 =
rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror &&
rg_sbcs_sberror == 3'd0 &&
rg_sbcs_sbautoincrement ;
assign rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104 =
sbaddress__h638 +
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 ;
assign rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299 =
addr64__h3701 +
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 ;
assign rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291 =
rg_sbcs_sberror == 3'd0 &&
(rg_sbcs_sbreadonaddr && rg_sbcs_sbautoincrement ||
write_dm_addr != 7'h39) ;
assign sbaddress__h638 = { rg_sbaddress1, rg_sbaddress0 } ;
assign shift_bits__h4287 = { rg_sbaddress0[2:0], 3'b0 } ;
assign strobe64__h4339 = 8'b00000001 << rg_sbaddress0[2:0] ;
assign strobe64__h4342 = 8'b00000011 << rg_sbaddress0[2:0] ;
assign strobe64__h4345 = 8'b00001111 << rg_sbaddress0[2:0] ;
assign v__h2132 =
{ 9'd64,
rg_sbcs_sbbusyerror,
rg_sb_state != 2'd0,
rg_sbcs_sbreadonaddr,
rg_sbcs_sbaccess,
rg_sbcs_sbautoincrement,
rg_sbcs_sbreadondata,
rg_sbcs_sberror,
12'd2055 } ;
assign v__h2266 =
(rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror ||
rg_sbcs_sberror != 3'd0) ?
32'd0 :
rg_sbdata0 ;
assign word64__h4284 = { 32'd0, write_dm_word } ;
assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 =
write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
(!rg_sbcs_sbbusyerror || write_dm_word[22]) &&
write_dm_word[19:17] != 3'd4 &&
write_dm_word[19:17] != 3'd3 ;
assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 =
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 ||
(write_dm_addr == 7'h39 || write_dm_addr == 7'h3A ||
write_dm_addr == 7'h3C) &&
rg_sb_state != 2'd0 ;
assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271 =
write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
rg_sbcs_sbbusyerror &&
!write_dm_word[22] ;
assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 =
write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
(!rg_sbcs_sbbusyerror || write_dm_word[22]) ;
assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278 =
write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
(!rg_sbcs_sbbusyerror || write_dm_word[22]) &&
(write_dm_word[19:17] == 3'd4 || write_dm_word[19:17] == 3'd3) ;
assign write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 =
write_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
!rg_sbcs_sbbusyerror &&
rg_sbcs_sberror == 3'd0 ;
always@(rg_sbcs_sbaccess)
begin
case (rg_sbcs_sbaccess)
3'd0, 3'd1, 3'd2: x__h2654 = rg_sbcs_sbaccess;
default: x__h2654 = 3'b011;
endcase
end
always@(rg_sbcs_sbaccess)
begin
case (rg_sbcs_sbaccess)
3'd0, 3'd1, 3'd2, 3'd3: x__h4302 = rg_sbcs_sbaccess;
default: x__h4302 = 3'b111;
endcase
end
always@(rg_sbcs_sbaccess or
strobe64__h4339 or strobe64__h4342 or strobe64__h4345)
begin
case (rg_sbcs_sbaccess)
3'd0: wrd_wstrb__h4398 = strobe64__h4339;
3'd1: wrd_wstrb__h4398 = strobe64__h4342;
3'd2: wrd_wstrb__h4398 = strobe64__h4345;
3'd3: wrd_wstrb__h4398 = 8'b11111111;
default: wrd_wstrb__h4398 = 8'd0;
endcase
end
always@(rg_sbcs_sbaccess or word64__h4284 or _theResult___fst__h4340)
begin
case (rg_sbcs_sbaccess)
3'd0, 3'd1, 3'd2: wrd_wdata__h4397 = _theResult___fst__h4340;
default: wrd_wdata__h4397 = word64__h4284;
endcase
end
always@(rg_sbcs_sbaccess)
begin
case (rg_sbcs_sbaccess)
3'd0: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd1;
3'd1: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd2;
3'd2: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd4;
3'd3: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd8;
default: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 =
64'd16;
endcase
end
always@(rg_sbaddress_reading or
result__h1250 or
result__h1280 or
result__h1307 or
result__h1334 or
result__h1361 or result__h1388 or result__h1415 or result__h1442)
begin
case (rg_sbaddress_reading[2:0])
3'h0:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1250;
3'h1:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1280;
3'h2:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1307;
3'h3:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1334;
3'h4:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1361;
3'h5:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1388;
3'h6:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1415;
3'h7:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1442;
endcase
end
always@(rg_sbaddress_reading or
result__h1487 or result__h1514 or result__h1541 or result__h1568)
begin
case (rg_sbaddress_reading[2:0])
3'h0:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 =
result__h1487;
3'h2:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 =
result__h1514;
3'h4:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 =
result__h1541;
3'h6:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 =
result__h1568;
default: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 =
64'd0;
endcase
end
always@(rg_sbaddress_reading or result__h1609 or result__h1636)
begin
case (rg_sbaddress_reading[2:0])
3'h0:
CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 =
result__h1609;
3'h4:
CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 =
result__h1636;
default: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 = 64'd0;
endcase
end
always@(rg_sbcs_sbaccess or
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 or
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 or
CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 or
rg_sbaddress_reading or master_xactor_f_rd_data$D_OUT)
begin
case (rg_sbcs_sbaccess)
3'd0:
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 =
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53;
3'd1:
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 =
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66;
3'd2:
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 =
CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1;
3'd3:
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 =
(rg_sbaddress_reading[2:0] == 3'h0) ?
master_xactor_f_rd_data$D_OUT[66:3] :
64'd0;
default: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 =
64'd0;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY 32'd0;
rg_sbaddress1 <= `BSV_ASSIGNMENT_DELAY 32'd0;
end
else
begin
if (rg_sbaddress0$EN)
rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY rg_sbaddress0$D_IN;
if (rg_sbaddress1$EN)
rg_sbaddress1 <= `BSV_ASSIGNMENT_DELAY rg_sbaddress1$D_IN;
end
if (rg_sb_state$EN) rg_sb_state <= `BSV_ASSIGNMENT_DELAY rg_sb_state$D_IN;
if (rg_sbaddress_reading$EN)
rg_sbaddress_reading <= `BSV_ASSIGNMENT_DELAY rg_sbaddress_reading$D_IN;
if (rg_sbcs_sbaccess$EN)
rg_sbcs_sbaccess <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sbaccess$D_IN;
if (rg_sbcs_sbautoincrement$EN)
rg_sbcs_sbautoincrement <= `BSV_ASSIGNMENT_DELAY
rg_sbcs_sbautoincrement$D_IN;
if (rg_sbcs_sbbusyerror$EN)
rg_sbcs_sbbusyerror <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sbbusyerror$D_IN;
if (rg_sbcs_sberror$EN)
rg_sbcs_sberror <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sberror$D_IN;
if (rg_sbcs_sbreadonaddr$EN)
rg_sbcs_sbreadonaddr <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sbreadonaddr$D_IN;
if (rg_sbcs_sbreadondata$EN)
rg_sbcs_sbreadondata <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sbreadondata$D_IN;
if (rg_sbdata0$EN) rg_sbdata0 <= `BSV_ASSIGNMENT_DELAY rg_sbdata0$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_sb_state = 2'h2;
rg_sbaddress0 = 32'hAAAAAAAA;
rg_sbaddress1 = 32'hAAAAAAAA;
rg_sbaddress_reading = 64'hAAAAAAAAAAAAAAAA;
rg_sbcs_sbaccess = 3'h2;
rg_sbcs_sbautoincrement = 1'h0;
rg_sbcs_sbbusyerror = 1'h0;
rg_sbcs_sberror = 3'h2;
rg_sbcs_sbreadonaddr = 1'h0;
rg_sbcs_sbreadondata = 1'h0;
rg_sbdata0 = 32'hAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
rg_sbcs_sbbusyerror)
$display("DM_System_Bus.sbdata.read: ignoring due to sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
!rg_sbcs_sbbusyerror &&
rg_sbcs_sberror != 3'd0)
$display("DM_System_Bus.sbdata.read: ignoring due to sberror = 0x%0h",
rg_sbcs_sberror);
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0)
$display("DM_System_Bus.sbdata.read: busy, setting sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr != 7'h38 &&
av_read_dm_addr != 7'h39 &&
av_read_dm_addr != 7'h3A &&
av_read_dm_addr != 7'h3C)
$write("DM_System_Bus.read: [");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h10) $write("dm_addr_dmcontrol");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h11) $write("dm_addr_dmstatus");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h12) $write("dm_addr_hartinfo");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h13) $write("dm_addr_haltsum");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h14)
$write("dm_addr_hawindowsel");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h15) $write("dm_addr_hawindow");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h19)
$write("dm_addr_devtreeaddr0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h30) $write("dm_addr_authdata");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h40)
$write("dm_addr_haltregion0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h5F)
$write("dm_addr_haltregion31");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h60) $write("dm_addr_verbosity");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h16)
$write("dm_addr_abstractcs");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h17) $write("dm_addr_command");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h04) $write("dm_addr_data0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h05) $write("dm_addr_data1");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h06) $write("dm_addr_data2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h07) $write("dm_addr_data3");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h08) $write("dm_addr_data4");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h09) $write("dm_addr_data5");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h0A) $write("dm_addr_data6");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h0B) $write("dm_addr_data7");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h0C) $write("dm_addr_data8");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h0D) $write("dm_addr_data9");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h0F) $write("dm_addr_data11");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h18)
$write("dm_addr_abstractauto");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h20) $write("dm_addr_progbuf0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3B)
$write("dm_addr_sbaddress2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3D) $write("dm_addr_sbdata1");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3E) $write("dm_addr_sbdata2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3F) $write("dm_addr_sbdata3");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr != 7'h38 &&
av_read_dm_addr != 7'h39 &&
av_read_dm_addr != 7'h3A &&
av_read_dm_addr != 7'h3C &&
av_read_dm_addr != 7'h10 &&
av_read_dm_addr != 7'h11 &&
av_read_dm_addr != 7'h12 &&
av_read_dm_addr != 7'h13 &&
av_read_dm_addr != 7'h14 &&
av_read_dm_addr != 7'h15 &&
av_read_dm_addr != 7'h19 &&
av_read_dm_addr != 7'h30 &&
av_read_dm_addr != 7'h40 &&
av_read_dm_addr != 7'h5F &&
av_read_dm_addr != 7'h60 &&
av_read_dm_addr != 7'h16 &&
av_read_dm_addr != 7'h17 &&
av_read_dm_addr != 7'h04 &&
av_read_dm_addr != 7'h05 &&
av_read_dm_addr != 7'h06 &&
av_read_dm_addr != 7'h07 &&
av_read_dm_addr != 7'h08 &&
av_read_dm_addr != 7'h09 &&
av_read_dm_addr != 7'h0A &&
av_read_dm_addr != 7'h0B &&
av_read_dm_addr != 7'h0C &&
av_read_dm_addr != 7'h0D &&
av_read_dm_addr != 7'h0F &&
av_read_dm_addr != 7'h18 &&
av_read_dm_addr != 7'h20 &&
av_read_dm_addr != 7'h3B &&
av_read_dm_addr != 7'h3D &&
av_read_dm_addr != 7'h3E &&
av_read_dm_addr != 7'h3F)
$write("<Unknown dm_abstract_command dm_addr 0x%0h>",
av_read_dm_addr);
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr != 7'h38 &&
av_read_dm_addr != 7'h39 &&
av_read_dm_addr != 7'h3A &&
av_read_dm_addr != 7'h3C)
$write("] not supported", "\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h38 && rg_sbcs_sberror != 3'd0 &&
write_dm_word[14:12] == 3'd0)
$display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h38 && rg_sbcs_sberror != 3'd0 &&
write_dm_word[14:12] == 3'd0)
$display(" ERROR: existing sberror (0x%0h) is not being cleared.",
rg_sbcs_sberror);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h38 && rg_sbcs_sberror != 3'd0 &&
write_dm_word[14:12] == 3'd0)
$display(" Must be cleared to re-enable system bus access.");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271)
$display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271)
$display(" ERROR: existing sbbusyerror (%0d) is not being cleared.",
rg_sbcs_sbbusyerror);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271)
$display(" Must be cleared to re-enable system bus access.");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278)
$display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278)
$write(" ERROR: sbaccess ");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
(!rg_sbcs_sbbusyerror || write_dm_word[22]) &&
write_dm_word[19:17] == 3'd3)
$write("DM_SBACCESS_64_BIT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
(!rg_sbcs_sbbusyerror || write_dm_word[22]) &&
write_dm_word[19:17] == 3'd4)
$write("DM_SBACCESS_128_BIT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278)
$write(" not supported", "\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 &&
(write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) &&
rg_sb_state == 2'd0 &&
rg_sbcs_sbbusyerror)
$display("DM_System_Bus.sbaddress.write: ignoring due to sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 &&
(write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) &&
rg_sb_state == 2'd0 &&
!rg_sbcs_sbbusyerror &&
rg_sbcs_sberror != 3'd0)
$display("DM_System_Bus.sbaddress.write: ignoring due to sberror = 0x%0h",
rg_sbcs_sberror);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 &&
(write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) &&
rg_sb_state != 2'd0)
$display("DM_System_Bus.sbaddress.write: busy, setting sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
rg_sbcs_sbbusyerror)
$display("DM_System_Bus.sbdata.write: ignoring due to sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
!rg_sbcs_sbbusyerror &&
rg_sbcs_sberror != 3'd0)
$display("DM_System_Bus.sbdata.write: ignoring due to sberror = 0x%0h",
rg_sbcs_sberror);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3C && rg_sb_state != 2'd0)
$display("DM_System_Bus.sbdata.write: busy, setting sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 && write_dm_addr != 7'h39 &&
write_dm_addr != 7'h3A &&
write_dm_addr != 7'h3C)
$write("DM_System_Bus.write: [");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h10) $write("dm_addr_dmcontrol");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h11) $write("dm_addr_dmstatus");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h12) $write("dm_addr_hartinfo");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h13) $write("dm_addr_haltsum");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h14) $write("dm_addr_hawindowsel");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h15) $write("dm_addr_hawindow");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h19) $write("dm_addr_devtreeaddr0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h30) $write("dm_addr_authdata");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h40) $write("dm_addr_haltregion0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h5F) $write("dm_addr_haltregion31");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h60) $write("dm_addr_verbosity");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h16) $write("dm_addr_abstractcs");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h17) $write("dm_addr_command");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h04) $write("dm_addr_data0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h05) $write("dm_addr_data1");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h06) $write("dm_addr_data2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h07) $write("dm_addr_data3");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h08) $write("dm_addr_data4");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h09) $write("dm_addr_data5");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h0A) $write("dm_addr_data6");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h0B) $write("dm_addr_data7");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h0C) $write("dm_addr_data8");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h0D) $write("dm_addr_data9");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h0F) $write("dm_addr_data11");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h18) $write("dm_addr_abstractauto");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h20) $write("dm_addr_progbuf0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3B) $write("dm_addr_sbaddress2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3D) $write("dm_addr_sbdata1");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3E) $write("dm_addr_sbdata2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3F) $write("dm_addr_sbdata3");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 && write_dm_addr != 7'h39 &&
write_dm_addr != 7'h3A &&
write_dm_addr != 7'h3C &&
write_dm_addr != 7'h10 &&
write_dm_addr != 7'h11 &&
write_dm_addr != 7'h12 &&
write_dm_addr != 7'h13 &&
write_dm_addr != 7'h14 &&
write_dm_addr != 7'h15 &&
write_dm_addr != 7'h19 &&
write_dm_addr != 7'h30 &&
write_dm_addr != 7'h40 &&
write_dm_addr != 7'h5F &&
write_dm_addr != 7'h60 &&
write_dm_addr != 7'h16 &&
write_dm_addr != 7'h17 &&
write_dm_addr != 7'h04 &&
write_dm_addr != 7'h05 &&
write_dm_addr != 7'h06 &&
write_dm_addr != 7'h07 &&
write_dm_addr != 7'h08 &&
write_dm_addr != 7'h09 &&
write_dm_addr != 7'h0A &&
write_dm_addr != 7'h0B &&
write_dm_addr != 7'h0C &&
write_dm_addr != 7'h0D &&
write_dm_addr != 7'h0F &&
write_dm_addr != 7'h18 &&
write_dm_addr != 7'h20 &&
write_dm_addr != 7'h3B &&
write_dm_addr != 7'h3D &&
write_dm_addr != 7'h3E &&
write_dm_addr != 7'h3F)
$write("<Unknown dm_abstract_command dm_addr 0x%0h>", write_dm_addr);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 && write_dm_addr != 7'h39 &&
write_dm_addr != 7'h3A &&
write_dm_addr != 7'h3C)
$write("] <= 0x%08h; addr not supported", write_dm_word, "\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$display("DM_System_Bus.rule_sb_read_finish: setting rg_sbcs_sberror to DM_SBERROR_OTHER\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write(" rdr = ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write("'h%h", master_xactor_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
master_xactor_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
!master_xactor_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write("\n");
end
// synopsys translate_on
endmodule // mkDM_System_Bus
|
module RAMB16_S1_S1(
input WEA,
input ENA,
input SSRA,
input CLKA,
input [13:0] ADDRA,
input [0:0] DIA,
// input DIPA,
// output [3:0] DOPA,
output [0:0] DOA,
input WEB,
input ENB,
input SSRB,
input CLKB,
input [13:0] ADDRB,
input [0:0] DIB,
// input DIPB,
// output [3:0] DOPB,
output [0:0] DOB);
parameter WRITE_MODE_A = "write_first";
parameter WRITE_MODE_B = "write_first";
parameter INIT_00=256'd0;
parameter INIT_01=256'd0;
parameter INIT_02=256'd0;
parameter INIT_03=256'd0;
parameter INIT_04=256'd0;
parameter INIT_05=256'd0;
parameter INIT_06=256'd0;
parameter INIT_07=256'd0;
parameter INIT_08=256'd0;
parameter INIT_09=256'd0;
parameter INIT_0A=256'd0;
parameter INIT_0B=256'd0;
parameter INIT_0C=256'd0;
parameter INIT_0D=256'd0;
parameter INIT_0E=256'd0;
parameter INIT_0F=256'd0;
parameter INIT_10=256'd0;
parameter INIT_11=256'd0;
parameter INIT_12=256'd0;
parameter INIT_13=256'd0;
parameter INIT_14=256'd0;
parameter INIT_15=256'd0;
parameter INIT_16=256'd0;
parameter INIT_17=256'd0;
parameter INIT_18=256'd0;
parameter INIT_19=256'd0;
parameter INIT_1A=256'd0;
parameter INIT_1B=256'd0;
parameter INIT_1C=256'd0;
parameter INIT_1D=256'd0;
parameter INIT_1E=256'd0;
parameter INIT_1F=256'd0;
parameter INIT_20=256'd0;
parameter INIT_21=256'd0;
parameter INIT_22=256'd0;
parameter INIT_23=256'd0;
parameter INIT_24=256'd0;
parameter INIT_25=256'd0;
parameter INIT_26=256'd0;
parameter INIT_27=256'd0;
parameter INIT_28=256'd0;
parameter INIT_29=256'd0;
parameter INIT_2A=256'd0;
parameter INIT_2B=256'd0;
parameter INIT_2C=256'd0;
parameter INIT_2D=256'd0;
parameter INIT_2E=256'd0;
parameter INIT_2F=256'd0;
parameter INIT_30=256'd0;
parameter INIT_31=256'd0;
parameter INIT_32=256'd0;
parameter INIT_33=256'd0;
parameter INIT_34=256'd0;
parameter INIT_35=256'd0;
parameter INIT_36=256'd0;
parameter INIT_37=256'd0;
parameter INIT_38=256'd0;
parameter INIT_39=256'd0;
parameter INIT_3A=256'd0;
parameter INIT_3B=256'd0;
parameter INIT_3C=256'd0;
parameter INIT_3D=256'd0;
parameter INIT_3E=256'd0;
parameter INIT_3F=256'd0;
RAMB16_RIGEL #(.WRITE_MODE_A(WRITE_MODE_A),.WRITE_MODE_B(WRITE_MODE_B),.BITS(1),.INIT_00(INIT_00),.INIT_01(INIT_01),.INIT_02(INIT_02),.INIT_03(INIT_03),.INIT_04(INIT_04),.INIT_05(INIT_05),.INIT_06(INIT_06),.INIT_07(INIT_07),.INIT_08(INIT_08),.INIT_09(INIT_09),.INIT_0A(INIT_0A),.INIT_0B(INIT_0B),.INIT_0C(INIT_0C),.INIT_0D(INIT_0D),.INIT_0E(INIT_0E),.INIT_0F(INIT_0F),.INIT_10(INIT_10),.INIT_11(INIT_11),.INIT_12(INIT_12),.INIT_13(INIT_13),.INIT_14(INIT_14),.INIT_15(INIT_15),.INIT_16(INIT_16),.INIT_17(INIT_17),.INIT_18(INIT_18),.INIT_19(INIT_19),.INIT_1A(INIT_1A),.INIT_1B(INIT_1B),.INIT_1C(INIT_1C),.INIT_1D(INIT_1D),.INIT_1E(INIT_1E),.INIT_1F(INIT_1F),.INIT_20(INIT_20),.INIT_21(INIT_21),.INIT_22(INIT_22),.INIT_23(INIT_23),.INIT_24(INIT_24),.INIT_25(INIT_25),.INIT_26(INIT_26),.INIT_27(INIT_27),.INIT_28(INIT_28),.INIT_29(INIT_29),.INIT_2A(INIT_2A),.INIT_2B(INIT_2B),.INIT_2C(INIT_2C),.INIT_2D(INIT_2D),.INIT_2E(INIT_2E),.INIT_2F(INIT_2F),.INIT_30(INIT_30),.INIT_31(INIT_31),.INIT_32(INIT_32),.INIT_33(INIT_33),.INIT_34(INIT_34),.INIT_35(INIT_35),.INIT_36(INIT_36),.INIT_37(INIT_37),.INIT_38(INIT_38),.INIT_39(INIT_39),.INIT_3A(INIT_3A),.INIT_3B(INIT_3B),.INIT_3C(INIT_3C),.INIT_3D(INIT_3D),.INIT_3E(INIT_3E),.INIT_3F(INIT_3F)) inner_ram(.WEA(WEA),.ENA(ENA),.SSRA(SSRA),.CLKA(CLKA),.ADDRA(ADDRA),.DIA(DIA),.DIPA(1'b0),.DOA(DOA),.WEB(WEB),.ENB(ENB),.SSRB(SSRB),.CLKB(CLKB),.ADDRB(ADDRB),.DIB(DIB),.DIPB(1'b0),.DOB(DOB));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
input clk;
`ifdef verilator
// Else it becomes a localparam, per IEEE 4.10.1, but we don't check it
defparam m3.FROMDEFP = 19;
`endif
m3 #(.P3(PAR),
.P2(2))
m3(.clk(clk));
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module m3
#(
parameter UNCH = 99,
parameter P1 = 10,
parameter P2 = 20,
P3 = 30
)
(/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam LOC = 13;
parameter FROMDEFP = 11;
initial begin
$display("%x %x %x",P1,P2,P3);
end
always @ (posedge clk) begin
if (UNCH !== 99) $stop;
if (P1 !== 10) $stop;
if (P2 !== 2) $stop;
if (P3 !== 3) $stop;
`ifdef verilator
if (FROMDEFP !== 19) $stop;
`endif
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t;
// verilator lint_off LITENDIAN
reg [5:0] binary_nostart [2:15];
reg [5:0] binary_start [0:15];
reg [175:0] hex [0:15];
// verilator lint_on LITENDIAN
integer i;
initial begin
begin
$readmemb("t/t_sys_readmem_b.mem", binary_nostart);
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_nostart[i]);
`endif
if (binary_nostart['h2] != 6'h02) $stop;
if (binary_nostart['h3] != 6'h03) $stop;
if (binary_nostart['h4] != 6'h04) $stop;
if (binary_nostart['h5] != 6'h05) $stop;
if (binary_nostart['h6] != 6'h06) $stop;
if (binary_nostart['h7] != 6'h07) $stop;
if (binary_nostart['h8] != 6'h10) $stop;
if (binary_nostart['hc] != 6'h14) $stop;
if (binary_nostart['hd] != 6'h15) $stop;
end
begin
$readmemb("t/t_sys_readmem_b_8.mem", binary_start, 4, 4+7);
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_start[i]);
`endif
if (binary_start['h04] != 6'h10) $stop;
if (binary_start['h05] != 6'h11) $stop;
if (binary_start['h06] != 6'h12) $stop;
if (binary_start['h07] != 6'h13) $stop;
if (binary_start['h08] != 6'h14) $stop;
if (binary_start['h09] != 6'h15) $stop;
if (binary_start['h0a] != 6'h16) $stop;
if (binary_start['h0b] != 6'h17) $stop;
end
begin
$readmemh("t/t_sys_readmem_h.mem", hex, 0);
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, hex[i]);
`endif
if (hex['h04] != 176'h400437654321276543211765432107654321abcdef10) $stop;
if (hex['h0a] != 176'h400a37654321276543211765432107654321abcdef11) $stop;
if (hex['h0b] != 176'h400b37654321276543211765432107654321abcdef12) $stop;
if (hex['h0c] != 176'h400c37654321276543211765432107654321abcdef13) $stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon May 22 19:34:37 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_clk_wiz_0_0 -prefix
// system_clk_wiz_0_0_ system_clk_wiz_0_0_sim_netlist.v
// Design : system_clk_wiz_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module system_clk_wiz_0_0
(clk_out1,
locked,
clk_in1);
output clk_out1;
output locked;
input clk_in1;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
wire locked;
system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.locked(locked));
endmodule
module system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz
(clk_out1,
locked,
clk_in1);
output clk_out1;
output locked;
input clk_in1;
wire clk_in1;
wire clk_in1_system_clk_wiz_0_0;
wire clk_out1;
wire clk_out1_system_clk_wiz_0_0;
wire clkfbout_buf_system_clk_wiz_0_0;
wire clkfbout_system_clk_wiz_0_0;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_system_clk_wiz_0_0),
.O(clkfbout_buf_system_clk_wiz_0_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_system_clk_wiz_0_0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_system_clk_wiz_0_0),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(44.625000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(75.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(5),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_system_clk_wiz_0_0),
.CLKFBOUT(clkfbout_system_clk_wiz_0_0),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_system_clk_wiz_0_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_system_clk_wiz_0_0),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O31AI_PP_BLACKBOX_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o31ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31AI_PP_BLACKBOX_V
|
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altfp_mult CBX_AUTO_BLACKBOX="ALL" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Stratix V" EXCEPTION_HANDLING="NO" PIPELINE=6 REDUCED_FUNCTIONALITY="NO" ROUNDING="TO_NEAREST" WIDTH_EXP=11 WIDTH_MAN=52 clk_en clock dataa datab result
//VERSION_BEGIN 12.0 cbx_alt_ded_mult_y 2012:05:31:20:08:01:SJ cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altera_mult_add 2012:05:31:20:08:02:SJ cbx_altfp_mult 2012:05:31:20:08:02:SJ cbx_altmult_add 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_parallel_add 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = lpm_add_sub 4 lpm_mult 1 reg 252
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_mul_ll_s5_double_altfp_mult_abo
(
clk_en,
clock,
dataa,
datab,
result) ;
input clk_en;
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg dataa_exp_all_one_ff_p1;
reg dataa_exp_not_zero_ff_p1;
reg dataa_man_not_zero_ff_p1;
reg dataa_man_not_zero_ff_p2;
reg datab_exp_all_one_ff_p1;
reg datab_exp_not_zero_ff_p1;
reg datab_man_not_zero_ff_p1;
reg datab_man_not_zero_ff_p2;
reg [12:0] delay_exp2_bias;
reg [12:0] delay_exp3_bias;
reg [12:0] delay_exp_bias;
reg delay_man_product_msb;
reg delay_man_product_msb_p0;
reg [11:0] exp_add_p1;
reg [10:0] exp_result_ff;
reg input_is_infinity_dffe_0;
reg input_is_infinity_dffe_1;
reg input_is_infinity_ff1;
reg input_is_infinity_ff2;
reg input_is_nan_dffe_0;
reg input_is_nan_dffe_1;
reg input_is_nan_ff1;
reg input_is_nan_ff2;
reg input_not_zero_dffe_0;
reg input_not_zero_dffe_1;
reg input_not_zero_ff1;
reg input_not_zero_ff2;
reg lsb_dffe;
reg [51:0] man_result_ff;
reg [52:0] man_round_p;
reg [53:0] man_round_p2;
reg round_dffe;
reg [0:0] sign_node_ff0;
reg [0:0] sign_node_ff1;
reg [0:0] sign_node_ff2;
reg [0:0] sign_node_ff3;
reg [0:0] sign_node_ff4;
reg [0:0] sign_node_ff5;
reg sticky_dffe;
wire [11:0] wire_exp_add_adder_result;
wire [12:0] wire_exp_adj_adder_result;
wire [12:0] wire_exp_bias_subtr_result;
wire [53:0] wire_man_round_adder_result;
wire [105:0] wire_man_product2_mult_result;
wire aclr;
wire [12:0] bias;
wire [10:0] dataa_exp_all_one;
wire [10:0] dataa_exp_not_zero;
wire [51:0] dataa_man_not_zero;
wire [10:0] datab_exp_all_one;
wire [10:0] datab_exp_not_zero;
wire [51:0] datab_man_not_zero;
wire [52:0] delay_round_wire;
wire exp_is_inf;
wire exp_is_zero;
wire [12:0] expmod;
wire [10:0] inf_num;
wire lsb_bit;
wire [53:0] man_shift_full;
wire [10:0] result_exp_all_one;
wire [11:0] result_exp_not_zero;
wire round_bit;
wire round_carry;
wire [51:0] sticky_bit;
// synopsys translate_off
initial
dataa_exp_all_one_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_exp_all_one_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) dataa_exp_all_one_ff_p1 <= dataa_exp_all_one[10];
// synopsys translate_off
initial
dataa_exp_not_zero_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_exp_not_zero_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) dataa_exp_not_zero_ff_p1 <= dataa_exp_not_zero[10];
// synopsys translate_off
initial
dataa_man_not_zero_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_man_not_zero_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) dataa_man_not_zero_ff_p1 <= dataa_man_not_zero[25];
// synopsys translate_off
initial
dataa_man_not_zero_ff_p2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_man_not_zero_ff_p2 <= 1'b0;
else if (clk_en == 1'b1) dataa_man_not_zero_ff_p2 <= dataa_man_not_zero[51];
// synopsys translate_off
initial
datab_exp_all_one_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_exp_all_one_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) datab_exp_all_one_ff_p1 <= datab_exp_all_one[10];
// synopsys translate_off
initial
datab_exp_not_zero_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_exp_not_zero_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) datab_exp_not_zero_ff_p1 <= datab_exp_not_zero[10];
// synopsys translate_off
initial
datab_man_not_zero_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_man_not_zero_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) datab_man_not_zero_ff_p1 <= datab_man_not_zero[25];
// synopsys translate_off
initial
datab_man_not_zero_ff_p2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_man_not_zero_ff_p2 <= 1'b0;
else if (clk_en == 1'b1) datab_man_not_zero_ff_p2 <= datab_man_not_zero[51];
// synopsys translate_off
initial
delay_exp2_bias = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_exp2_bias <= 13'b0;
else if (clk_en == 1'b1) delay_exp2_bias <= delay_exp_bias;
// synopsys translate_off
initial
delay_exp3_bias = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_exp3_bias <= 13'b0;
else if (clk_en == 1'b1) delay_exp3_bias <= delay_exp2_bias;
// synopsys translate_off
initial
delay_exp_bias = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_exp_bias <= 13'b0;
else if (clk_en == 1'b1) delay_exp_bias <= wire_exp_bias_subtr_result;
// synopsys translate_off
initial
delay_man_product_msb = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_man_product_msb <= 1'b0;
else if (clk_en == 1'b1) delay_man_product_msb <= delay_man_product_msb_p0;
// synopsys translate_off
initial
delay_man_product_msb_p0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_man_product_msb_p0 <= 1'b0;
else if (clk_en == 1'b1) delay_man_product_msb_p0 <= wire_man_product2_mult_result[105];
// synopsys translate_off
initial
exp_add_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_add_p1 <= 12'b0;
else if (clk_en == 1'b1) exp_add_p1 <= wire_exp_add_adder_result;
// synopsys translate_off
initial
exp_result_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_ff <= 11'b0;
else if (clk_en == 1'b1) exp_result_ff <= ((inf_num & {11{((exp_is_inf | input_is_infinity_ff2) | input_is_nan_ff2)}}) | ((wire_exp_adj_adder_result[10:0] & {11{(~ exp_is_zero)}}) & {11{input_not_zero_ff2}}));
// synopsys translate_off
initial
input_is_infinity_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_dffe_0 <= ((dataa_exp_all_one_ff_p1 & (~ (dataa_man_not_zero_ff_p1 | dataa_man_not_zero_ff_p2))) | (datab_exp_all_one_ff_p1 & (~ (datab_man_not_zero_ff_p1 | datab_man_not_zero_ff_p2))));
// synopsys translate_off
initial
input_is_infinity_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_dffe_1 <= input_is_infinity_dffe_0;
// synopsys translate_off
initial
input_is_infinity_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_ff1 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_ff1 <= input_is_infinity_dffe_1;
// synopsys translate_off
initial
input_is_infinity_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_ff2 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_ff2 <= input_is_infinity_ff1;
// synopsys translate_off
initial
input_is_nan_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe_0 <= ((dataa_exp_all_one_ff_p1 & (dataa_man_not_zero_ff_p1 | dataa_man_not_zero_ff_p2)) | (datab_exp_all_one_ff_p1 & (datab_man_not_zero_ff_p1 | datab_man_not_zero_ff_p2)));
// synopsys translate_off
initial
input_is_nan_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe_1 <= input_is_nan_dffe_0;
// synopsys translate_off
initial
input_is_nan_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_ff1 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_ff1 <= input_is_nan_dffe_1;
// synopsys translate_off
initial
input_is_nan_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_ff2 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_ff2 <= input_is_nan_ff1;
// synopsys translate_off
initial
input_not_zero_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_dffe_0 <= (dataa_exp_not_zero_ff_p1 & datab_exp_not_zero_ff_p1);
// synopsys translate_off
initial
input_not_zero_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_dffe_1 <= input_not_zero_dffe_0;
// synopsys translate_off
initial
input_not_zero_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_ff1 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_ff1 <= input_not_zero_dffe_1;
// synopsys translate_off
initial
input_not_zero_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_ff2 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_ff2 <= input_not_zero_ff1;
// synopsys translate_off
initial
lsb_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lsb_dffe <= 1'b0;
else if (clk_en == 1'b1) lsb_dffe <= lsb_bit;
// synopsys translate_off
initial
man_result_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_result_ff <= 52'b0;
else if (clk_en == 1'b1) man_result_ff <= {((((((delay_round_wire[51] & input_not_zero_ff2) & (~ input_is_infinity_ff2)) & (~ exp_is_inf)) & (~ exp_is_zero)) | (input_is_infinity_ff2 & (~ input_not_zero_ff2))) | input_is_nan_ff2), (((((delay_round_wire[50:0] & {51{input_not_zero_ff2}}) & {51{(~ input_is_infinity_ff2)}}) & {51{(~ exp_is_inf)}}) & {51{(~ exp_is_zero)}}) & {51{(~ input_is_nan_ff2)}})};
// synopsys translate_off
initial
man_round_p = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_round_p <= 53'b0;
else if (clk_en == 1'b1) man_round_p <= man_shift_full[53:1];
// synopsys translate_off
initial
man_round_p2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_round_p2 <= 54'b0;
else if (clk_en == 1'b1) man_round_p2 <= wire_man_round_adder_result;
// synopsys translate_off
initial
round_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) round_dffe <= 1'b0;
else if (clk_en == 1'b1) round_dffe <= round_bit;
// synopsys translate_off
initial
sign_node_ff0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff0 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff0 <= (dataa[63] ^ datab[63]);
// synopsys translate_off
initial
sign_node_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff1 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff1 <= sign_node_ff0[0:0];
// synopsys translate_off
initial
sign_node_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff2 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff2 <= sign_node_ff1[0:0];
// synopsys translate_off
initial
sign_node_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff3 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff3 <= sign_node_ff2[0:0];
// synopsys translate_off
initial
sign_node_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff4 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff4 <= sign_node_ff3[0:0];
// synopsys translate_off
initial
sign_node_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff5 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff5 <= sign_node_ff4[0:0];
// synopsys translate_off
initial
sticky_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sticky_dffe <= 1'b0;
else if (clk_en == 1'b1) sticky_dffe <= sticky_bit[51];
lpm_add_sub exp_add_adder
(
.aclr(aclr),
.cin(1'b0),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({1'b0, dataa[62:52]}),
.datab({1'b0, datab[62:52]}),
.overflow(),
.result(wire_exp_add_adder_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_add_adder.lpm_pipeline = 1,
exp_add_adder.lpm_width = 12,
exp_add_adder.lpm_type = "lpm_add_sub";
lpm_add_sub exp_adj_adder
(
.cin(1'b0),
.cout(),
.dataa(delay_exp3_bias),
.datab(expmod),
.overflow(),
.result(wire_exp_adj_adder_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_adj_adder.lpm_pipeline = 0,
exp_adj_adder.lpm_width = 13,
exp_adj_adder.lpm_type = "lpm_add_sub";
lpm_add_sub exp_bias_subtr
(
.cout(),
.dataa({1'b0, exp_add_p1[11:0]}),
.datab({bias[12:0]}),
.overflow(),
.result(wire_exp_bias_subtr_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_bias_subtr.lpm_direction = "SUB",
exp_bias_subtr.lpm_pipeline = 0,
exp_bias_subtr.lpm_representation = "UNSIGNED",
exp_bias_subtr.lpm_width = 13,
exp_bias_subtr.lpm_type = "lpm_add_sub";
lpm_add_sub man_round_adder
(
.cout(),
.dataa({1'b0, man_round_p}),
.datab({{53{1'b0}}, round_carry}),
.overflow(),
.result(wire_man_round_adder_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
man_round_adder.lpm_pipeline = 0,
man_round_adder.lpm_width = 54,
man_round_adder.lpm_type = "lpm_add_sub";
lpm_mult man_product2_mult
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa({1'b1, dataa[51:0]}),
.datab({1'b1, datab[51:0]}),
.result(wire_man_product2_mult_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
man_product2_mult.lpm_pipeline = 3,
man_product2_mult.lpm_representation = "UNSIGNED",
man_product2_mult.lpm_widtha = 53,
man_product2_mult.lpm_widthb = 53,
man_product2_mult.lpm_widthp = 106,
man_product2_mult.lpm_widths = 1,
man_product2_mult.lpm_type = "lpm_mult",
man_product2_mult.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
assign
aclr = 1'b0,
bias = {{3{1'b0}}, {10{1'b1}}},
dataa_exp_all_one = {(dataa[62] & dataa_exp_all_one[9]), (dataa[61] & dataa_exp_all_one[8]), (dataa[60] & dataa_exp_all_one[7]), (dataa[59] & dataa_exp_all_one[6]), (dataa[58] & dataa_exp_all_one[5]), (dataa[57] & dataa_exp_all_one[4]), (dataa[56] & dataa_exp_all_one[3]), (dataa[55] & dataa_exp_all_one[2]), (dataa[54] & dataa_exp_all_one[1]), (dataa[53] & dataa_exp_all_one[0]), dataa[52]},
dataa_exp_not_zero = {(dataa[62] | dataa_exp_not_zero[9]), (dataa[61] | dataa_exp_not_zero[8]), (dataa[60] | dataa_exp_not_zero[7]), (dataa[59] | dataa_exp_not_zero[6]), (dataa[58] | dataa_exp_not_zero[5]), (dataa[57] | dataa_exp_not_zero[4]), (dataa[56] | dataa_exp_not_zero[3]), (dataa[55] | dataa_exp_not_zero[2]), (dataa[54] | dataa_exp_not_zero[1]), (dataa[53] | dataa_exp_not_zero[0]), dataa[52]},
dataa_man_not_zero = {(dataa[51] | dataa_man_not_zero[50]), (dataa[50] | dataa_man_not_zero[49]), (dataa[49] | dataa_man_not_zero[48]), (dataa[48] | dataa_man_not_zero[47]), (dataa[47] | dataa_man_not_zero[46]), (dataa[46] | dataa_man_not_zero[45]), (dataa[45] | dataa_man_not_zero[44]), (dataa[44] | dataa_man_not_zero[43]), (dataa[43] | dataa_man_not_zero[42]), (dataa[42] | dataa_man_not_zero[41]), (dataa[41] | dataa_man_not_zero[40]), (dataa[40] | dataa_man_not_zero[39]), (dataa[39] | dataa_man_not_zero[38]), (dataa[38] | dataa_man_not_zero[37]), (dataa[37] | dataa_man_not_zero[36]), (dataa[36] | dataa_man_not_zero[35]), (dataa[35] | dataa_man_not_zero[34]), (dataa[34] | dataa_man_not_zero[33]), (dataa[33] | dataa_man_not_zero[32]), (dataa[32] | dataa_man_not_zero[31]), (dataa[31] | dataa_man_not_zero[30]), (dataa[30] | dataa_man_not_zero[29]), (dataa[29] | dataa_man_not_zero[28]), (dataa[28] | dataa_man_not_zero[27]), (dataa[27] | dataa_man_not_zero[26]), dataa[26], (dataa[25] | dataa_man_not_zero[24]), (dataa[24] | dataa_man_not_zero[23]), (dataa[23] | dataa_man_not_zero[22]), (dataa[22] | dataa_man_not_zero[21]), (dataa[21] | dataa_man_not_zero[20]), (dataa[20] | dataa_man_not_zero[19]), (dataa[19] | dataa_man_not_zero[18]), (dataa[18] | dataa_man_not_zero[17]), (dataa[17] | dataa_man_not_zero[16]), (dataa[16] | dataa_man_not_zero[15]), (dataa[15] | dataa_man_not_zero[14]), (dataa[14] | dataa_man_not_zero[13]), (dataa[13] | dataa_man_not_zero[12]), (dataa[12] | dataa_man_not_zero[11]), (dataa[11] | dataa_man_not_zero[10]), (dataa[10] | dataa_man_not_zero[9]), (dataa[9] | dataa_man_not_zero[8]), (dataa[8] | dataa_man_not_zero[7]), (dataa[7] | dataa_man_not_zero[6]), (dataa[6] | dataa_man_not_zero[5]), (dataa[5] | dataa_man_not_zero[4]), (dataa[4] | dataa_man_not_zero[3]), (dataa[3] | dataa_man_not_zero[2]), (dataa[2] | dataa_man_not_zero[1]), (dataa[1] | dataa_man_not_zero[0]), dataa[0]},
datab_exp_all_one = {(datab[62] & datab_exp_all_one[9]), (datab[61] & datab_exp_all_one[8]), (datab[60] & datab_exp_all_one[7]), (datab[59] & datab_exp_all_one[6]), (datab[58] & datab_exp_all_one[5]), (datab[57] & datab_exp_all_one[4]), (datab[56] & datab_exp_all_one[3]), (datab[55] & datab_exp_all_one[2]), (datab[54] & datab_exp_all_one[1]), (datab[53] & datab_exp_all_one[0]), datab[52]},
datab_exp_not_zero = {(datab[62] | datab_exp_not_zero[9]), (datab[61] | datab_exp_not_zero[8]), (datab[60] | datab_exp_not_zero[7]), (datab[59] | datab_exp_not_zero[6]), (datab[58] | datab_exp_not_zero[5]), (datab[57] | datab_exp_not_zero[4]), (datab[56] | datab_exp_not_zero[3]), (datab[55] | datab_exp_not_zero[2]), (datab[54] | datab_exp_not_zero[1]), (datab[53] | datab_exp_not_zero[0]), datab[52]},
datab_man_not_zero = {(datab[51] | datab_man_not_zero[50]), (datab[50] | datab_man_not_zero[49]), (datab[49] | datab_man_not_zero[48]), (datab[48] | datab_man_not_zero[47]), (datab[47] | datab_man_not_zero[46]), (datab[46] | datab_man_not_zero[45]), (datab[45] | datab_man_not_zero[44]), (datab[44] | datab_man_not_zero[43]), (datab[43] | datab_man_not_zero[42]), (datab[42] | datab_man_not_zero[41]), (datab[41] | datab_man_not_zero[40]), (datab[40] | datab_man_not_zero[39]), (datab[39] | datab_man_not_zero[38]), (datab[38] | datab_man_not_zero[37]), (datab[37] | datab_man_not_zero[36]), (datab[36] | datab_man_not_zero[35]), (datab[35] | datab_man_not_zero[34]), (datab[34] | datab_man_not_zero[33]), (datab[33] | datab_man_not_zero[32]), (datab[32] | datab_man_not_zero[31]), (datab[31] | datab_man_not_zero[30]), (datab[30] | datab_man_not_zero[29]), (datab[29] | datab_man_not_zero[28]), (datab[28] | datab_man_not_zero[27]), (datab[27] | datab_man_not_zero[26]), datab[26], (datab[25] | datab_man_not_zero[24]), (datab[24] | datab_man_not_zero[23]), (datab[23] | datab_man_not_zero[22]), (datab[22] | datab_man_not_zero[21]), (datab[21] | datab_man_not_zero[20]), (datab[20] | datab_man_not_zero[19]), (datab[19] | datab_man_not_zero[18]), (datab[18] | datab_man_not_zero[17]), (datab[17] | datab_man_not_zero[16]), (datab[16] | datab_man_not_zero[15]), (datab[15] | datab_man_not_zero[14]), (datab[14] | datab_man_not_zero[13]), (datab[13] | datab_man_not_zero[12]), (datab[12] | datab_man_not_zero[11]), (datab[11] | datab_man_not_zero[10]), (datab[10] | datab_man_not_zero[9]), (datab[9] | datab_man_not_zero[8]), (datab[8] | datab_man_not_zero[7]), (datab[7] | datab_man_not_zero[6]), (datab[6] | datab_man_not_zero[5]), (datab[5] | datab_man_not_zero[4]), (datab[4] | datab_man_not_zero[3]), (datab[3] | datab_man_not_zero[2]), (datab[2] | datab_man_not_zero[1]), (datab[1] | datab_man_not_zero[0]), datab[0]},
delay_round_wire = ((man_round_p2[52:0] & {53{(~ man_round_p2[53])}}) | (man_round_p2[53:1] & {53{man_round_p2[53]}})),
exp_is_inf = (((~ wire_exp_adj_adder_result[12]) & wire_exp_adj_adder_result[11]) | ((~ wire_exp_adj_adder_result[11]) & result_exp_all_one[10])),
exp_is_zero = (wire_exp_adj_adder_result[12] | (~ result_exp_not_zero[11])),
expmod = {{11{1'b0}}, (delay_man_product_msb & man_round_p2[53]), (delay_man_product_msb ^ man_round_p2[53])},
inf_num = {11{1'b1}},
lsb_bit = man_shift_full[1],
man_shift_full = ((wire_man_product2_mult_result[104:51] & {54{(~ wire_man_product2_mult_result[105])}}) | (wire_man_product2_mult_result[105:52] & {54{wire_man_product2_mult_result[105]}})),
result = {sign_node_ff5[0:0], exp_result_ff[10:0], man_result_ff[51:0]},
result_exp_all_one = {(result_exp_all_one[9] & wire_exp_adj_adder_result[10]), (result_exp_all_one[8] & wire_exp_adj_adder_result[9]), (result_exp_all_one[7] & wire_exp_adj_adder_result[8]), (result_exp_all_one[6] & wire_exp_adj_adder_result[7]), (result_exp_all_one[5] & wire_exp_adj_adder_result[6]), (result_exp_all_one[4] & wire_exp_adj_adder_result[5]), (result_exp_all_one[3] & wire_exp_adj_adder_result[4]), (result_exp_all_one[2] & wire_exp_adj_adder_result[3]), (result_exp_all_one[1] & wire_exp_adj_adder_result[2]), (result_exp_all_one[0] & wire_exp_adj_adder_result[1]), wire_exp_adj_adder_result[0]},
result_exp_not_zero = {(result_exp_not_zero[10] | wire_exp_adj_adder_result[11]), (result_exp_not_zero[9] | wire_exp_adj_adder_result[10]), (result_exp_not_zero[8] | wire_exp_adj_adder_result[9]), (result_exp_not_zero[7] | wire_exp_adj_adder_result[8]), (result_exp_not_zero[6] | wire_exp_adj_adder_result[7]), (result_exp_not_zero[5] | wire_exp_adj_adder_result[6]), (result_exp_not_zero[4] | wire_exp_adj_adder_result[5]), (result_exp_not_zero[3] | wire_exp_adj_adder_result[4]), (result_exp_not_zero[2] | wire_exp_adj_adder_result[3]), (result_exp_not_zero[1] | wire_exp_adj_adder_result[2]), (result_exp_not_zero[0] | wire_exp_adj_adder_result[1]), wire_exp_adj_adder_result[0]},
round_bit = man_shift_full[0],
round_carry = (round_dffe & (lsb_dffe | sticky_dffe)),
sticky_bit = {(sticky_bit[50] | (wire_man_product2_mult_result[105] & wire_man_product2_mult_result[51])), (sticky_bit[49] | wire_man_product2_mult_result[50]), (sticky_bit[48] | wire_man_product2_mult_result[49]), (sticky_bit[47] | wire_man_product2_mult_result[48]), (sticky_bit[46] | wire_man_product2_mult_result[47]), (sticky_bit[45] | wire_man_product2_mult_result[46]), (sticky_bit[44] | wire_man_product2_mult_result[45]), (sticky_bit[43] | wire_man_product2_mult_result[44]), (sticky_bit[42] | wire_man_product2_mult_result[43]), (sticky_bit[41] | wire_man_product2_mult_result[42]), (sticky_bit[40] | wire_man_product2_mult_result[41]), (sticky_bit[39] | wire_man_product2_mult_result[40]), (sticky_bit[38] | wire_man_product2_mult_result[39]), (sticky_bit[37] | wire_man_product2_mult_result[38]), (sticky_bit[36] | wire_man_product2_mult_result[37]), (sticky_bit[35] | wire_man_product2_mult_result[36]), (sticky_bit[34] | wire_man_product2_mult_result[35]), (sticky_bit[33] | wire_man_product2_mult_result[34]), (sticky_bit[32] | wire_man_product2_mult_result[33]), (sticky_bit[31] | wire_man_product2_mult_result[32]), (sticky_bit[30] | wire_man_product2_mult_result[31]), (sticky_bit[29] | wire_man_product2_mult_result[30]), (sticky_bit[28] | wire_man_product2_mult_result[29]), (sticky_bit[27] | wire_man_product2_mult_result[28]), (sticky_bit[26] | wire_man_product2_mult_result[27]), (sticky_bit[25] | wire_man_product2_mult_result[26]), (sticky_bit[24] | wire_man_product2_mult_result[25]), (sticky_bit[23] | wire_man_product2_mult_result[24]), (sticky_bit[22] | wire_man_product2_mult_result[23]), (sticky_bit[21] | wire_man_product2_mult_result[22]), (sticky_bit[20] | wire_man_product2_mult_result[21]), (sticky_bit[19] | wire_man_product2_mult_result[20]), (sticky_bit[18] | wire_man_product2_mult_result[19]), (sticky_bit[17] | wire_man_product2_mult_result[18]), (sticky_bit[16] | wire_man_product2_mult_result[17]), (sticky_bit[15] | wire_man_product2_mult_result[16]), (sticky_bit[14] | wire_man_product2_mult_result[15]
), (sticky_bit[13] | wire_man_product2_mult_result[14]), (sticky_bit[12] | wire_man_product2_mult_result[13]), (sticky_bit[11] | wire_man_product2_mult_result[12]), (sticky_bit[10] | wire_man_product2_mult_result[11]), (sticky_bit[9] | wire_man_product2_mult_result[10]), (sticky_bit[8] | wire_man_product2_mult_result[9]), (sticky_bit[7] | wire_man_product2_mult_result[8]), (sticky_bit[6] | wire_man_product2_mult_result[7]), (sticky_bit[5] | wire_man_product2_mult_result[6]), (sticky_bit[4] | wire_man_product2_mult_result[5]), (sticky_bit[3] | wire_man_product2_mult_result[4]), (sticky_bit[2] | wire_man_product2_mult_result[3]), (sticky_bit[1] | wire_man_product2_mult_result[2]), (sticky_bit[0] | wire_man_product2_mult_result[1]), wire_man_product2_mult_result[0]};
endmodule //acl_fp_mul_ll_s5_double_altfp_mult_abo
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_mul_ll_s5_double (
enable,
clock,
dataa,
datab,
result);
input enable;
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
acl_fp_mul_ll_s5_double_altfp_mult_abo acl_fp_mul_ll_s5_double_altfp_mult_abo_component (
.clk_en (enable),
.clock (clock),
.datab (datab),
.dataa (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: FPM_FORMAT STRING "Double"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
// Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
// Retrieval info: CONSTANT: EXCEPTION_HANDLING STRING "NO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_mult"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "6"
// Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
// Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "52"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: dataa 0 0 64 0 INPUT NODEFVAL "dataa[63..0]"
// Retrieval info: CONNECT: @dataa 0 0 64 0 dataa 0 0 64 0
// Retrieval info: USED_PORT: datab 0 0 64 0 INPUT NODEFVAL "datab[63..0]"
// Retrieval info: CONNECT: @datab 0 0 64 0 datab 0 0 64 0
// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL "result[63..0]"
// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_mul_ll_s5_double.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_mul_ll_s5_double.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_mul_ll_s5_double.bsf TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_mul_ll_s5_double_inst.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_mul_ll_s5_double_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_mul_ll_s5_double.inc TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_mul_ll_s5_double.cmp TRUE TRUE
// Retrieval info: LIB_FILE: lpm
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
`include "qlf_k6n10f/cells_sim.v"
module tb();
// Clock
reg clk;
initial clk <= 1'b0;
always #0.5 clk <= ~clk;
// Reset
reg rst;
initial begin
rst <= 1'b0;
#2 rst <= 1'b1;
#2 rst <= 1'b0;
end
// Filter control
reg [2:0] fcnt;
reg [3:0] dcnt;
initial begin
fcnt <= 0;
dcnt <= 0;
end
// MAC cycle counter
always @(posedge clk)
if (rst) fcnt <= 0;
else begin
if (fcnt == 4)
fcnt <= 0;
else
fcnt <= fcnt + 1;
end
wire stb = (fcnt == 4);
// Data address counter
always @(posedge clk)
if (rst) dcnt <= 0;
else if (stb) dcnt <= dcnt + 1;
// Filter coeffs (S0.19)
reg signed [19:0] coeff;
always @(*) case (fcnt)
2'd0: coeff <= 20'h0000B;
2'd1: coeff <= 20'h0000E;
2'd2: coeff <= 20'h0000E;
2'd3: coeff <= 20'h0000F;
default: coeff <= 20'h00000;
endcase
// Input data (S0.17)
reg signed [17:0] data;
always @(*) case (dcnt)
'd0: data <= 18'h00400;
'd1: data <= 18'h00000;
'd2: data <= 18'h00000;
'd3: data <= 18'h00000;
'd4: data <= 18'h00000;
'd5: data <= 18'h00000;
'd6: data <= 18'h00000;
'd7: data <= 18'h00000;
'd8: data <= 18'h00800;
default data <= 18'h00000;
endcase
// UUT
wire signed [3:0] acc_fir_i = 4'h0;
wire signed [19:0] A = coeff;
wire signed [17:0] B = data;
wire signed [37:0] Z;
dsp_t1_sim # (
) uut (
.clock_i (clk),
.reset_n_i (~rst),
.a_i ((!stb) ? A : 20'h0),
.b_i ((!stb) ? B : 18'h0),
.acc_fir_i ((!stb) ? acc_fir_i : 4'h0),
.unsigned_a_i (1'b0),
.unsigned_b_i (1'b0),
.feedback_i (stb),
.load_acc_i (1'b1),
.shift_right_i (6'd10),
.register_inputs_i (1'b0),
.output_select_i (3'h1),
.round_i (1'b1),
.saturate_enable_i (1'b1),
.subtract_i (1'b0),
.z_o (Z)
);
// Output counter
integer ocnt;
initial ocnt <= 0;
always @(posedge clk)
if (stb) ocnt <= ocnt + 1;
// Expected output data
reg signed [31:0] odata;
always @(*) case (ocnt)
'd0: odata <= 32'h000036;
'd1: odata <= 32'h000000;
'd2: odata <= 32'h000000;
'd3: odata <= 32'h000000;
'd4: odata <= 32'h000000;
'd5: odata <= 32'h000000;
'd6: odata <= 32'h000000;
'd7: odata <= 32'h000000;
'd8: odata <= 32'h00006C;
default: odata <= 32'h000000;
endcase
// Error detection
wire error = stb && (odata !== Z[31:0]);
// Error counting
integer error_count;
initial error_count <= 0;
always @(posedge clk) begin
if (error) error_count <= error_count + 1;
end
// Simulation control / data dump
initial begin
$dumpfile(`VCD_FILE);
$dumpvars(0, tb);
#150 $finish_and_return( (error_count == 0) ? 0 : -1 );
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Muhammad Ijaz
//
// Create Date: 05/05/2017 09:31:01 AM
// Design Name:
// Module Name: REGISTER_FILE
// Project Name: RISC-V
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module REGISTER_FILE #(
parameter REGISTER_WIDTH = 32 ,
parameter REGISTER_DEPTH = 32 ,
parameter STACK_POINTER_ADD = 2 ,
parameter STACK_POINTER_VAL = 32'd1024 ,
parameter HIGH = 1'b1
) (
input CLK ,
input [$clog2(REGISTER_DEPTH) - 1 : 0] RS1_ADDRESS ,
input [$clog2(REGISTER_DEPTH) - 1 : 0] RS2_ADDRESS ,
input [$clog2(REGISTER_DEPTH) - 1 : 0] RD_ADDRESS ,
input [REGISTER_WIDTH - 1 : 0] RD_DATA ,
input RD_WRITE_EN ,
output [REGISTER_WIDTH - 1 : 0] RS1_DATA ,
output [REGISTER_WIDTH - 1 : 0] RS2_DATA
);
reg [REGISTER_WIDTH - 1 : 0] register [REGISTER_DEPTH - 1 : 0] ;
reg [REGISTER_WIDTH - 1 : 0] rs1_data_reg ;
reg [REGISTER_WIDTH - 1 : 0] rs2_data_reg ;
integer i;
initial
begin
for(i = 0 ; i < REGISTER_DEPTH ; i = i + 1)
begin
if(i == STACK_POINTER_ADD)
register[ i ] = STACK_POINTER_VAL ;
else
register[ i ] = {REGISTER_WIDTH{1'b0}} ;
end
end
always@(*)
begin
rs1_data_reg = register [ RS1_ADDRESS ];
rs2_data_reg = register [ RS2_ADDRESS ];
end
always@(negedge CLK)
begin
if((RD_WRITE_EN == HIGH) & (RD_ADDRESS != 5'b0))
begin
register [RD_ADDRESS] <= RD_DATA;
end
end
assign RS1_DATA = rs1_data_reg;
assign RS2_DATA = rs2_data_reg;
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 23512 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w1024,
w1023,
w2048,
w3071,
w32,
w33,
w132,
w2939,
w23512;
assign w1 = i_data0;
assign w1023 = w1024 - w1;
assign w1024 = w1 << 10;
assign w132 = w33 << 2;
assign w2048 = w1 << 11;
assign w23512 = w2939 << 3;
assign w2939 = w3071 - w132;
assign w3071 = w1023 + w2048;
assign w32 = w1 << 5;
assign w33 = w1 + w32;
assign o_data0 = w23512;
//multiplier_block area estimate = 6153.83997047941;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DFF_PS_TB_V
`define SKY130_FD_SC_MS__UDP_DFF_PS_TB_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__udp_dff_ps.v"
module top();
// Inputs are registered
reg D;
reg SET;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SET = 1'bX;
#20 D = 1'b0;
#40 SET = 1'b0;
#60 D = 1'b1;
#80 SET = 1'b1;
#100 D = 1'b0;
#120 SET = 1'b0;
#140 SET = 1'b1;
#160 D = 1'b1;
#180 SET = 1'bx;
#200 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ms__udp_dff$PS dut (.D(D), .SET(SET), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DFF_PS_TB_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_register_slice:2.1
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module OpenSSD2_s01_regslice_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_register_slice_v2_1_axi_register_slice #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_REG_CONFIG_AW(7),
.C_REG_CONFIG_W(1),
.C_REG_CONFIG_B(7),
.C_REG_CONFIG_AR(7),
.C_REG_CONFIG_R(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22AI_SYMBOL_V
`define SKY130_FD_SC_LS__O22AI_SYMBOL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o22ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22AI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21AI_1_V
`define SKY130_FD_SC_HS__O21AI_1_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o21ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o21ai_1 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21AI_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BA_1_V
`define SKY130_FD_SC_HD__O21BA_1_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21ba with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21ba.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21ba_1 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21ba_1 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BA_1_V
|
`timescale 1ns / 1ps
/////////////////////////////////////////////////////////////////
// Module Name: lab1_tb
/////////////////////////////////////////////////////////////////
module lab1_tb(
);
reg [7:0] switches;
wire [7:0] leds;
reg [7:0] e_led;
integer i;
lab1 dut(.led(leds),.swt(switches));
function [7:0] expected_led;
input [7:0] swt;
begin
expected_led[0] = ~swt[0];
expected_led[1] = swt[1] & ~swt[2];
expected_led[3] = swt[2] & swt[3];
expected_led[2] = expected_led[1] | expected_led[3];
expected_led[7:4] = swt[7:4];
end
endfunction
initial
begin
for (i=0; i < 255; i=i+2)
begin
#50 switches=i;
#10 e_led = expected_led(switches);
if(leds == e_led)
$display("LED output matched at", $time);
else
$display("LED output mis-matched at ",$time,": expected: %b, actual: %b", e_led, leds);
end
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cordic_nco(clk_i,rst_i,ena_i,strobe_i,ampl_i,freq_i,phs_i,data_i_o,data_q_o);
input clk_i;
input rst_i;
input ena_i;
input strobe_i;
input [15:0] ampl_i;
input [31:0] freq_i;
input [31:0] phs_i;
output [15:0] data_i_o;
output [15:0] data_q_o;
reg [31:0] phase_reg;
wire [31:0] phase = phase_reg + phs_i;
wire [15:0] ampl;
always @(posedge clk_i)
begin
if (rst_i | ~ena_i)
phase_reg <= 32'b0;
else if (strobe_i)
phase_reg <= phase_reg + freq_i;
end
assign ampl = ena_i ? ampl_i : 16'b0;
cordic tx_cordic
(.clock(clk_i),.reset(rst_i),.enable(strobe_i),
.xi(ampl),.yi(16'b0),.zi(phase[31:16]),
.xo(data_i_o),.yo(data_q_o),.zo());
endmodule // cordic_nco
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_nlb # (
parameter P_DATA_WIDTH = 19,
parameter P_ADDR_WIDTH = 7
)
(
input clk,
input rst_n,
input wr0_en,
input [P_ADDR_WIDTH-1:0] wr0_addr,
input [P_DATA_WIDTH-1:0] wr0_data,
output wr0_rdy_n,
input wr1_en,
input [P_ADDR_WIDTH-1:0] wr1_addr,
input [P_DATA_WIDTH-1:0] wr1_data,
output wr1_rdy_n,
input [P_ADDR_WIDTH-1:0] rd_addr,
output [P_DATA_WIDTH-1:0] rd_data
);
localparam S_IDLE = 2'b01;
localparam S_WRITE = 2'b10;
reg [1:0] cur_state;
reg [1:0] next_state;
reg r_wr0_req;
reg r_wr1_req;
reg r_wr0_req_ack;
reg r_wr1_req_ack;
reg [1:0] r_wr_gnt;
reg r_wr_en;
reg [P_ADDR_WIDTH-1:0] r_wr_addr;
reg [P_DATA_WIDTH-1:0] r_wr_data;
reg [P_ADDR_WIDTH-1:0] r_wr0_addr;
reg [P_DATA_WIDTH-1:0] r_wr0_data;
reg [P_ADDR_WIDTH-1:0] r_wr1_addr;
reg [P_DATA_WIDTH-1:0] r_wr1_data;
assign wr0_rdy_n = r_wr0_req;
assign wr1_rdy_n = r_wr1_req | r_wr0_req;
always @(posedge clk)
begin
if(wr0_en == 1) begin
r_wr0_addr <= wr0_addr;
r_wr0_data <= wr0_data;
end
if(wr1_en == 1) begin
r_wr1_addr <= wr1_addr;
r_wr1_data <= wr1_data;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_wr0_req <= 0;
r_wr1_req <= 0;
end
else begin
if(r_wr0_req_ack == 1)
r_wr0_req <= 0;
else if(wr0_en == 1)
r_wr0_req <= 1;
if(r_wr1_req_ack == 1)
r_wr1_req <= 0;
else if(wr1_en == 1)
r_wr1_req <= 1;
end
end
always @ (posedge clk or negedge rst_n)
begin
if(rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(r_wr0_req == 1 || r_wr1_req == 1)
next_state <= S_WRITE;
else
next_state <= S_IDLE;
end
S_WRITE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge clk)
begin
case(cur_state)
S_IDLE: begin
if(r_wr1_req == 1)
r_wr_gnt <= 2'b10;
else if(r_wr0_req == 1)
r_wr_gnt <= 2'b01;
end
S_WRITE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
S_WRITE: begin
r_wr_en <= 1;
r_wr0_req_ack <= r_wr_gnt[0];
r_wr1_req_ack <= r_wr_gnt[1];
end
default: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
endcase
end
always @ (*)
begin
case(r_wr_gnt) // synthesis parallel_case full_case
2'b01: begin
r_wr_addr <= r_wr0_addr;
r_wr_data <= r_wr0_data;
end
2'b10: begin
r_wr_addr <= r_wr1_addr;
r_wr_data <= r_wr1_data;
end
endcase
end
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_ADDR_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = rd_addr[P_ADDR_WIDTH-1:0];
assign wraddr = r_wr_addr[P_ADDR_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], rd_addr[P_ADDR_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_wr_addr[P_ADDR_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (r_wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (r_wr_en)
);
endmodule |
(* abc9_lut=1 *)
module LUT1(output F, input I0);
parameter [1:0] INIT = 0;
specify
(I0 => F) = (555, 902);
endspecify
assign F = I0 ? INIT[1] : INIT[0];
endmodule
(* abc9_lut=1 *)
module LUT2(output F, input I0, I1);
parameter [3:0] INIT = 0;
specify
(I0 => F) = (867, 1184);
(I1 => F) = (555, 902);
endspecify
wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
endmodule
(* abc9_lut=1 *)
module LUT3(output F, input I0, I1, I2);
parameter [7:0] INIT = 0;
specify
(I0 => F) = (1054, 1486);
(I1 => F) = (867, 1184);
(I2 => F) = (555, 902);
endspecify
wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
endmodule
(* abc9_lut=1 *)
module LUT4(output F, input I0, I1, I2, I3);
parameter [15:0] INIT = 0;
specify
(I0 => F) = (1054, 1486);
(I1 => F) = (1053, 1583);
(I2 => F) = (867, 1184);
(I3 => F) = (555, 902);
endspecify
wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
endmodule
(* abc9_lut=2 *)
module __APICULA_LUT5(output F, input I0, I1, I2, I3, M0);
specify
(I0 => F) = (1187, 1638);
(I1 => F) = (1184, 1638);
(I2 => F) = (995, 1371);
(I3 => F) = (808, 1116);
(M0 => F) = (486, 680);
endspecify
endmodule
(* abc9_lut=4 *)
module __APICULA_LUT6(output F, input I0, I1, I2, I3, M0, M1);
specify
(I0 => F) = (1187 + 136, 1638 + 255);
(I1 => F) = (1184 + 136, 1638 + 255);
(I2 => F) = (995 + 136, 1371 + 255);
(I3 => F) = (808 + 136, 1116 + 255);
(M0 => F) = (486 + 136, 680 + 255);
(M1 => F) = (478, 723);
endspecify
endmodule
(* abc9_lut=8 *)
module __APICULA_LUT7(output F, input I0, I1, I2, I3, M0, M1, M2);
specify
(I0 => F) = (1187 + 136 + 136, 1638 + 255 + 255);
(I1 => F) = (1184 + 136 + 136, 1638 + 255 + 255);
(I2 => F) = (995 + 136 + 136, 1371 + 255 + 255);
(I3 => F) = (808 + 136 + 136, 1116 + 255 + 255);
(M0 => F) = (486 + 136 + 136, 680 + 255 + 255);
(M1 => F) = (478 + 136, 723 + 255);
(M2 => F) = (478, 723);
endspecify
endmodule
(* abc9_lut=16 *)
module __APICULA_LUT8(output F, input I0, I1, I2, I3, M0, M1, M2, M3);
specify
(I0 => F) = (1187 + 136 + 136 + 136, 1638 + 255 + 255 + 255);
(I1 => F) = (1184 + 136 + 136 + 136, 1638 + 255 + 255 + 255);
(I2 => F) = (995 + 136 + 136 + 136, 1371 + 255 + 255 + 255);
(I3 => F) = (808 + 136 + 136 + 136, 1116 + 255 + 255 + 255);
(M0 => F) = (486 + 136 + 136 + 136, 680 + 255 + 255 + 255);
(M1 => F) = (478 + 136 + 136, 723 + 255 + 255);
(M2 => F) = (478 + 136, 723 + 255);
(M3 => F) = (478, 723);
endspecify
endmodule
module MUX2 (O, I0, I1, S0);
input I0,I1;
input S0;
output O;
specify
(I0 => O) = (141, 160);
(I1 => O) = (141, 160);
(S0 => O) = (486, 680);
endspecify
assign O = S0 ? I1 : I0;
endmodule
module MUX2_LUT5 (O, I0, I1, S0);
input I0,I1;
input S0;
output O;
specify
(I0 => O) = (141, 160);
(I1 => O) = (141, 160);
(S0 => O) = (486, 680);
endspecify
MUX2 mux2_lut5 (O, I0, I1, S0);
endmodule
module MUX2_LUT6 (O, I0, I1, S0);
input I0,I1;
input S0;
output O;
specify
(I0 => O) = (136, 255);
(I1 => O) = (136, 255);
(S0 => O) = (478, 723);
endspecify
MUX2 mux2_lut6 (O, I0, I1, S0);
endmodule
module MUX2_LUT7 (O, I0, I1, S0);
input I0,I1;
input S0;
output O;
specify
(I0 => O) = (136, 255);
(I1 => O) = (136, 255);
(S0 => O) = (478, 723);
endspecify
MUX2 mux2_lut7 (O, I0, I1, S0);
endmodule
module MUX2_LUT8 (O, I0, I1, S0);
input I0,I1;
input S0;
output O;
specify
(I0 => O) = (136, 255);
(I1 => O) = (136, 255);
(S0 => O) = (478, 723);
endspecify
MUX2 mux2_lut8 (O, I0, I1, S0);
endmodule
(* abc9_flop, lib_whitebox *)
module DFF (output reg Q, input CLK, D);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
(posedge CLK => (Q : D)) = (480, 660);
$setup(D, posedge CLK, 576);
endspecify
always @(posedge CLK)
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module DFFE (output reg Q, input D, CLK, CE);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
if (CE) (posedge CLK => (Q : D)) = (480, 660);
$setup(D, posedge CLK &&& CE, 576);
$setup(CE, posedge CLK, 63);
endspecify
always @(posedge CLK) begin
if (CE)
Q <= D;
end
endmodule // DFFE (positive clock edge; clock enable)
(* abc9_box, lib_whitebox *)
module DFFS (output reg Q, input D, CLK, SET);
parameter [0:0] INIT = 1'b1;
initial Q = INIT;
specify
(posedge CLK => (Q : D)) = (480, 660);
$setup(D, posedge CLK, 576);
$setup(SET, posedge CLK, 63);
endspecify
always @(posedge CLK) begin
if (SET)
Q <= 1'b1;
else
Q <= D;
end
endmodule // DFFS (positive clock edge; synchronous set)
(* abc9_box, lib_whitebox *)
module DFFSE (output reg Q, input D, CLK, CE, SET);
parameter [0:0] INIT = 1'b1;
initial Q = INIT;
specify
if (CE) (posedge CLK => (Q : D)) = (480, 660);
$setup(D, posedge CLK &&& CE, 576);
$setup(CE, posedge CLK, 63);
$setup(SET, posedge CLK, 63);
endspecify
always @(posedge CLK) begin
if (SET)
Q <= 1'b1;
else if (CE)
Q <= D;
end
endmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable)
(* abc9_flop, lib_whitebox *)
module DFFR (output reg Q, input D, CLK, RESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
(posedge CLK => (Q : D)) = (480, 660);
$setup(D, posedge CLK, 576);
$setup(RESET, posedge CLK, 63);
endspecify
always @(posedge CLK) begin
if (RESET)
Q <= 1'b0;
else
Q <= D;
end
endmodule // DFFR (positive clock edge; synchronous reset)
(* abc9_flop, lib_whitebox *)
module DFFRE (output reg Q, input D, CLK, CE, RESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
if (CE) (posedge CLK => (Q : D)) = (480, 660);
$setup(D, posedge CLK &&& CE, 576);
$setup(CE, posedge CLK, 63);
$setup(RESET, posedge CLK, 63);
endspecify
always @(posedge CLK) begin
if (RESET)
Q <= 1'b0;
else if (CE)
Q <= D;
end
endmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable)
(* abc9_box, lib_whitebox *)
module DFFP (output reg Q, input D, CLK, PRESET);
parameter [0:0] INIT = 1'b1;
initial Q = INIT;
specify
(posedge CLK => (Q : D)) = (480, 660);
(posedge PRESET => (Q : 1'b1)) = (1800, 2679);
$setup(D, posedge CLK, 576);
endspecify
always @(posedge CLK or posedge PRESET) begin
if(PRESET)
Q <= 1'b1;
else
Q <= D;
end
endmodule // DFFP (positive clock edge; asynchronous preset)
(* abc9_box, lib_whitebox *)
module DFFPE (output reg Q, input D, CLK, CE, PRESET);
parameter [0:0] INIT = 1'b1;
initial Q = INIT;
specify
if (CE) (posedge CLK => (Q : D)) = (480, 660);
(posedge PRESET => (Q : 1'b1)) = (1800, 2679);
$setup(D, posedge CLK &&& CE, 576);
$setup(CE, posedge CLK, 63);
endspecify
always @(posedge CLK or posedge PRESET) begin
if(PRESET)
Q <= 1'b1;
else if (CE)
Q <= D;
end
endmodule // DFFPE (positive clock edge; asynchronous preset; clock enable)
(* abc9_box, lib_whitebox *)
module DFFC (output reg Q, input D, CLK, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
(posedge CLK => (Q : D)) = (480, 660);
(posedge CLEAR => (Q : 1'b0)) = (1800, 2679);
$setup(D, posedge CLK, 576);
endspecify
always @(posedge CLK or posedge CLEAR) begin
if(CLEAR)
Q <= 1'b0;
else
Q <= D;
end
endmodule // DFFC (positive clock edge; asynchronous clear)
(* abc9_box, lib_whitebox *)
module DFFCE (output reg Q, input D, CLK, CE, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
if (CE) (posedge CLK => (Q : D)) = (480, 660);
(posedge CLEAR => (Q : 1'b0)) = (1800, 2679);
$setup(D, posedge CLK &&& CE, 576);
$setup(CE, posedge CLK, 63);
endspecify
always @(posedge CLK or posedge CLEAR) begin
if(CLEAR)
Q <= 1'b0;
else if (CE)
Q <= D;
end
endmodule // DFFCE (positive clock edge; asynchronous clear; clock enable)
(* abc9_flop, lib_whitebox *)
module DFFN (output reg Q, input CLK, D);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
(negedge CLK => (Q : D)) = (480, 660);
$setup(D, negedge CLK, 576);
endspecify
always @(negedge CLK)
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module DFFNE (output reg Q, input D, CLK, CE);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
if (CE) (negedge CLK => (Q : D)) = (480, 660);
$setup(D, negedge CLK &&& CE, 576);
$setup(CE, negedge CLK, 63);
endspecify
always @(negedge CLK) begin
if (CE)
Q <= D;
end
endmodule // DFFNE (negative clock edge; clock enable)
(* abc9_box, lib_whitebox *)
module DFFNS (output reg Q, input D, CLK, SET);
parameter [0:0] INIT = 1'b1;
initial Q = INIT;
specify
(negedge CLK => (Q : D)) = (480, 660);
$setup(D, negedge CLK, 576);
$setup(SET, negedge CLK, 63);
endspecify
always @(negedge CLK) begin
if (SET)
Q <= 1'b1;
else
Q <= D;
end
endmodule // DFFNS (negative clock edge; synchronous set)
(* abc9_box, lib_whitebox *)
module DFFNSE (output reg Q, input D, CLK, CE, SET);
parameter [0:0] INIT = 1'b1;
initial Q = INIT;
specify
if (CE) (negedge CLK => (Q : D)) = (480, 660);
$setup(D, negedge CLK &&& CE, 576);
$setup(CE, negedge CLK, 63);
$setup(SET, negedge CLK, 63);
endspecify
always @(negedge CLK) begin
if (SET)
Q <= 1'b1;
else if (CE)
Q <= D;
end
endmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable)
(* abc9_flop, lib_whitebox *)
module DFFNR (output reg Q, input D, CLK, RESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
(negedge CLK => (Q : D)) = (480, 660);
$setup(D, negedge CLK, 576);
$setup(RESET, negedge CLK, 63);
endspecify
always @(negedge CLK) begin
if (RESET)
Q <= 1'b0;
else
Q <= D;
end
endmodule // DFFNR (negative clock edge; synchronous reset)
(* abc9_flop, lib_whitebox *)
module DFFNRE (output reg Q, input D, CLK, CE, RESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
if (CE) (negedge CLK => (Q : D)) = (480, 660);
$setup(D, negedge CLK &&& CE, 576);
$setup(CE, negedge CLK, 63);
$setup(RESET, negedge CLK, 63);
endspecify
always @(negedge CLK) begin
if (RESET)
Q <= 1'b0;
else if (CE)
Q <= D;
end
endmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable)
(* abc9_box, lib_whitebox *)
module DFFNP (output reg Q, input D, CLK, PRESET);
parameter [0:0] INIT = 1'b1;
initial Q = INIT;
specify
(negedge CLK => (Q : D)) = (480, 660);
(posedge PRESET => (Q : 1'b1)) = (1800, 2679);
$setup(D, negedge CLK, 576);
endspecify
always @(negedge CLK or posedge PRESET) begin
if(PRESET)
Q <= 1'b1;
else
Q <= D;
end
endmodule // DFFNP (negative clock edge; asynchronous preset)
(* abc9_box, lib_whitebox *)
module DFFNPE (output reg Q, input D, CLK, CE, PRESET);
parameter [0:0] INIT = 1'b1;
initial Q = INIT;
specify
if (CE) (negedge CLK => (Q : D)) = (480, 660);
(posedge PRESET => (Q : 1'b1)) = (1800, 2679);
$setup(D, negedge CLK &&& CE, 576);
$setup(CE, negedge CLK, 63);
endspecify
always @(negedge CLK or posedge PRESET) begin
if(PRESET)
Q <= 1'b1;
else if (CE)
Q <= D;
end
endmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable)
(* abc9_box, lib_whitebox *)
module DFFNC (output reg Q, input D, CLK, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
(negedge CLK => (Q : D)) = (480, 660);
(posedge CLEAR => (Q : 1'b0)) = (1800, 2679);
$setup(D, negedge CLK, 576);
endspecify
always @(negedge CLK or posedge CLEAR) begin
if(CLEAR)
Q <= 1'b0;
else
Q <= D;
end
endmodule // DFFNC (negative clock edge; asynchronous clear)
(* abc9_box, lib_whitebox *)
module DFFNCE (output reg Q, input D, CLK, CE, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
if (CE) (negedge CLK => (Q : D)) = (480, 660);
(posedge CLEAR => (Q : 1'b0)) = (1800, 2679);
$setup(D, negedge CLK &&& CE, 576);
$setup(CE, negedge CLK, 63);
endspecify
always @(negedge CLK or posedge CLEAR) begin
if(CLEAR)
Q <= 1'b0;
else if (CE)
Q <= D;
end
endmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable)
// TODO add more DFF sim cells
module VCC(output V);
assign V = 1;
endmodule
module GND(output G);
assign G = 0;
endmodule
(* abc9_box *)
module IBUF(output O, input I);
specify
(I => O) = 0;
endspecify
assign O = I;
endmodule
(* abc9_box *)
module OBUF(output O, input I);
specify
(I => O) = 0;
endspecify
assign O = I;
endmodule
module TBUF (O, I, OEN);
input I, OEN;
output O;
assign O = OEN ? I : 1'bz;
endmodule
module IOBUF (O, IO, I, OEN);
input I,OEN;
output O;
inout IO;
assign IO = OEN ? I : 1'bz;
assign I = IO;
endmodule
module GSR (input GSRI);
wire GSRO = GSRI;
endmodule
(* abc9_box, lib_whitebox *)
module ALU (SUM, COUT, I0, I1, I3, CIN);
input I0;
input I1;
input I3;
(* abc9_carry *) input CIN;
output SUM;
(* abc9_carry *) output COUT;
localparam ADD = 0;
localparam SUB = 1;
localparam ADDSUB = 2;
localparam NE = 3;
localparam GE = 4;
localparam LE = 5;
localparam CUP = 6;
localparam CDN = 7;
localparam CUPCDN = 8;
localparam MULT = 9;
parameter ALU_MODE = 0;
reg S, C;
specify
(I0 => SUM) = (1043, 1432);
(I1 => SUM) = (775, 1049);
(I3 => SUM) = (751, 1010);
(CIN => SUM) = (694, 811);
(I0 => COUT) = (1010, 1380);
(I1 => COUT) = (1021, 1505);
(I3 => COUT) = (483, 792);
(CIN => COUT) = (49, 82);
endspecify
assign SUM = S ^ CIN;
assign COUT = S? CIN : C;
always @* begin
case (ALU_MODE)
ADD: begin
S = I0 ^ I1;
C = I0;
end
SUB: begin
S = I0 ^ ~I1;
C = I0;
end
ADDSUB: begin
S = I3? I0 ^ I1 : I0 ^ ~I1;
C = I0;
end
NE: begin
S = I0 ^ ~I1;
C = 1'b1;
end
GE: begin
S = I0 ^ ~I1;
C = I0;
end
LE: begin
S = ~I0 ^ I1;
C = I1;
end
CUP: begin
S = I0;
C = 1'b0;
end
CDN: begin
S = ~I0;
C = 1'b1;
end
CUPCDN: begin
S = I3? I0 : ~I0;
C = I0;
end
MULT: begin
S = I0 & I1;
C = I0 & I1;
end
endcase
end
endmodule
module RAM16S4 (DO, DI, AD, WRE, CLK);
parameter WIDTH = 4;
parameter INIT_0 = 16'h0000;
parameter INIT_1 = 16'h0000;
parameter INIT_2 = 16'h0000;
parameter INIT_3 = 16'h0000;
input [WIDTH-1:0] AD;
input [WIDTH-1:0] DI;
output [WIDTH-1:0] DO;
input CLK;
input WRE;
specify
(AD => DO) = (270, 405);
$setup(DI, posedge CLK, 62);
$setup(WRE, posedge CLK, 62);
$setup(AD, posedge CLK, 62);
(posedge CLK => (DO : {WIDTH{1'bx}})) = (474, 565);
endspecify
reg [15:0] mem0, mem1, mem2, mem3;
initial begin
mem0 = INIT_0;
mem1 = INIT_1;
mem2 = INIT_2;
mem3 = INIT_3;
end
assign DO[0] = mem0[AD];
assign DO[1] = mem1[AD];
assign DO[2] = mem2[AD];
assign DO[3] = mem3[AD];
always @(posedge CLK) begin
if (WRE) begin
mem0[AD] <= DI[0];
mem1[AD] <= DI[1];
mem2[AD] <= DI[2];
mem3[AD] <= DI[3];
end
end
endmodule // RAM16S4
(* blackbox *)
module SDP (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);
//1'b0: Bypass mode; 1'b1 Pipeline mode
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 32; // 1, 2, 4, 8, 16, 32
parameter BIT_WIDTH_1 = 32; // 1, 2, 4, 8, 16, 32
parameter BLK_SEL = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCE; // clock enable of memory output register
input RESETA, RESETB; // resets output registers, not memory contents
input WREA, WREB; // 1'b0: read enabled; 1'b1: write enabled
input [13:0] ADA, ADB;
input [31:0] DI;
input [2:0] BLKSEL;
output [31:0] DO;
specify
(posedge CLKB => (DO : DI)) = (419, 493);
$setup(RESETA, posedge CLKA, 62);
$setup(RESETB, posedge CLKB, 62);
$setup(OCE, posedge CLKB, 62);
$setup(CEA, posedge CLKA, 62);
$setup(CEB, posedge CLKB, 62);
$setup(OCE, posedge CLKB, 62);
$setup(WREA, posedge CLKA, 62);
$setup(WREB, posedge CLKB, 62);
$setup(DI, posedge CLKA, 62);
$setup(ADA, posedge CLKA, 62);
$setup(ADB, posedge CLKB, 62);
$setup(BLKSEL, posedge CLKA, 62);
endspecify
endmodule
(* blackbox *)
module rPLL (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P);
input CLKIN;
input CLKFB;
input RESET;
input RESET_P;
input [5:0] FBDSEL;
input [5:0] IDSEL;
input [5:0] ODSEL;
input [3:0] PSDA,FDLY;
input [3:0] DUTYDA;
output CLKOUT;
output LOCK;
output CLKOUTP;
output CLKOUTD;
output CLKOUTD3;
parameter FCLKIN = "100.0"; // frequency of CLKIN
parameter DYN_IDIV_SEL= "false"; // true:IDSEL, false:IDIV_SEL
parameter IDIV_SEL = 0; // 0:1, 1:2 ... 63:64
parameter DYN_FBDIV_SEL= "false"; // true:FBDSEL, false:FBDIV_SEL
parameter FBDIV_SEL = 0; // 0:1, 1:2 ... 63:64
parameter DYN_ODIV_SEL= "false"; // true:ODSEL, false:ODIV_SEL
parameter ODIV_SEL = 8; // 2/4/8/16/32/48/64/80/96/112/128
parameter PSDA_SEL= "0000";
parameter DYN_DA_EN = "false"; // true:PSDA or DUTYDA or FDA, false: DA_SEL
parameter DUTYDA_SEL= "1000";
parameter CLKOUT_FT_DIR = 1'b1; // CLKOUT fine tuning direction. 1'b1 only
parameter CLKOUTP_FT_DIR = 1'b1; // 1'b1 only
parameter CLKOUT_DLY_STEP = 0; // 0, 1, 2, 4
parameter CLKOUTP_DLY_STEP = 0; // 0, 1, 2
parameter CLKFB_SEL = "internal"; // "internal", "external"
parameter CLKOUT_BYPASS = "false"; // "true", "false"
parameter CLKOUTP_BYPASS = "false"; // "true", "false"
parameter CLKOUTD_BYPASS = "false"; // "true", "false"
parameter DYN_SDIV_SEL = 2; // 2~128, only even numbers
parameter CLKOUTD_SRC = "CLKOUT"; // CLKOUT, CLKOUTP
parameter CLKOUTD3_SRC = "CLKOUT"; // CLKOUT, CLKOUTP
parameter DEVICE = "GW1N-1"; // "GW1N-1", "GW1N-4", "GW1N-9", "GW1NR-4", "GW1NR-9", "GW1N-4B", "GW1NR-4B", "GW1NS-2", "GW1NS-2C", "GW1NZ-1", "GW1NSR-2", "GW1NSR-2C", "GW1N-1S", "GW1NSE-2C", "GW1NRF-4B", "GW1N-9C", "GW1NR-9C", "GW1N-4C", "GW1NR-4C"
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE SD Card Controller IP Core ////
//// ////
//// sd_clock_divider.v ////
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// Control of sd card clock rate ////
//// ////
//// Author(s): ////
//// - Marek Czerski, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson ([email protected]) ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module sd_clock_divider (
input CLK,
input [7:0] DIVIDER,
input RST,
output SD_CLK
);
reg [7:0] ClockDiv;
reg SD_CLK_O;
//assign SD_CLK = DIVIDER[7] ? CLK : SD_CLK_O;
assign SD_CLK = SD_CLK_O;
always @(posedge CLK or posedge RST)
begin
if (RST) begin
ClockDiv <= 8'b0000_0000;
SD_CLK_O <= 0;
end
else if (ClockDiv == DIVIDER) begin
ClockDiv <= 0;
SD_CLK_O <= ~SD_CLK_O;
end else begin
ClockDiv <= ClockDiv + 8'h1;
SD_CLK_O <= SD_CLK_O;
end
end
endmodule
|